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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 10:48:49 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[1:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[1:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [1:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
input [0:0]probe20;
input [1:0]probe21;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:35:40 05/31/2016
// Design Name:
// Module Name: Contador_AD_Dia
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Dia(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 7;
parameter X = 99;
always @(posedge clk)
if (rst)
Cuenta <= 1;
else if (en == 2'd2 && estado == 8'h7D)
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 1;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 1)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PG (
Q ,
D ,
GATE ,
RESET,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxtp (
CLK ,
D ,
Q ,
VPWR,
VGND
);
input CLK ;
input D ;
output Q ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXTP_PP_BLACKBOX_V
|
module object_store(
input wire mclk,
input wire stall,
input wire reset,
output reg[31:0] mem_address = 0,
output reg[31:0] mem_din,
input wire[31:0] mem_dout,
output reg mem_re = 0,
output reg mem_we = 0,
input wire [4:0] slot_index,
output wire[31:0] slot_value,
output reg initialized = 0
);
parameter state_reset = 2'b00;
parameter state_load_ptr = 2'b01;
parameter state_load_regs = 2'b10;
parameter state_complete = 2'b11;
reg[1:0] state = state_reset;
parameter last_slot = 5'd26;
reg[4:0] store_index = 0;
reg[31:0] slots[0:26];
wire has_control = !stall && !mem_re && !mem_we;
// Should slots be wired or accessed via bus?
assign slot_value = slots[slot_index];
always @ (posedge mclk) begin
if(reset) begin
state <= state_reset;
end else begin
if(has_control) begin
case(state)
state_reset: begin
// Read memory at address 0
mem_address <= 31'b0;
mem_re <= 1;
state <= state_load_ptr;
store_index <= 0;
initialized <= 0;
end
state_load_ptr: begin
// Read memory at location of first slot;
mem_address <= mem_dout + 2;
mem_re <= 1;
state <= state_load_regs;
end
state_load_regs: begin
// Store slot value & increment memory address;
slots[store_index] <= mem_dout;
if(store_index == last_slot) begin
state <= state_complete;
initialized <= 1;
end else begin
mem_address <= mem_address + 1;
store_index <= store_index + 1;
mem_re <= 1;
end
end
default: begin
// Trap
end
endcase
end else begin
// No pipeline
// Force machine to wait at least a cycle after asserting read/write
// and ensure read/write is asserted for just one cycle.
mem_we <= 0;
mem_re <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_2_V
`define SKY130_FD_SC_LP__OR2_2_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:47:09 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_hessian_1_0/system_vga_hessian_1_0_stub.v
// Design : system_vga_hessian_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_hessian,Vivado 2016.4" *)
module system_vga_hessian_1_0(clk_x16, active, rst, x_addr, y_addr, g_in,
hessian_out)
/* synthesis syn_black_box black_box_pad_pin="clk_x16,active,rst,x_addr[9:0],y_addr[9:0],g_in[7:0],hessian_out[31:0]" */;
input clk_x16;
input active;
input rst;
input [9:0]x_addr;
input [9:0]y_addr;
input [7:0]g_in;
output [31:0]hessian_out;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/05/2016 08:56:02 PM
// Design Name:
// Module Name: hapara_axis_64timer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hapara_axis_64timer # (
parameter DATA_WIDTH = 32
)(
bram_clk,
bram_rst,
bram_en,
bram_we,
bram_addr,
bram_din,
bram_dout,
valid,
ready,
data,
rstn,
clk
);
output bram_clk;
output bram_rst;
output bram_en;
output [3 : 0] bram_we;
output [DATA_WIDTH - 1 : 0] bram_addr;
output [DATA_WIDTH - 1 : 0] bram_din;
input [DATA_WIDTH - 1 : 0] bram_dout;
output valid;
input ready;
output [DATA_WIDTH - 1 : 0] data;
input rstn;
input clk;
assign bram_clk = clk;
assign bram_rst = ~rstn;
reg [DATA_WIDTH - 1 : 0] bram_din;
reg [2 * DATA_WIDTH - 1 : 0] counter;
reg [2 * DATA_WIDTH - 1 : 0] temp;
reg [DATA_WIDTH - 1 : 0] raddr;
reg [1 : 0] curr_state;
reg [1 : 0] next_state;
localparam idle = 2'b00;
localparam s0 = 2'b01;
localparam s1 = 2'b10;
localparam wait0 = 2'b11;
// Logic for raadr;
always @(posedge clk) begin
if (~rstn) begin
raddr <= {DATA_WIDTH{1'b0}};
end else if (curr_state == s0 || curr_state == s1) begin
raddr <= raddr + 4;
end else begin
raddr <= raddr;
end
end
assign bram_addr = raddr;
// Logic for curr_state
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
curr_state <= idle;
end else begin
curr_state <= next_state;
end
end
// Logic for next_state
always @(*) begin
case (curr_state)
idle:
if (ready) next_state = s0;
else next_state = idle;
s0:
next_state = s1;
s1:
next_state = wait0;
wait0:
if (~ready) next_state = idle;
else next_state = wait0;
default:
next_state = 2'bxx;
endcase
end
// Logic for counter
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
counter <= {2 * DATA_WIDTH{1'b0}};
end else begin
counter <= counter + 1;
end
end
// Logic for temp
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
temp <= {2 * DATA_WIDTH{1'b0}};
end else if ((curr_state == idle) && ready) begin
temp <= counter;
end else begin
temp <= temp;
end
end
// Logic for bram_din
always @(*) begin
case (curr_state)
idle:
bram_din = {DATA_WIDTH{1'b0}};
s0:
bram_din = temp[DATA_WIDTH - 1 : 0];
s1:
bram_din = temp[2 * DATA_WIDTH - 1 : DATA_WIDTH];
wait0:
bram_din = {DATA_WIDTH{1'b0}};
default:
bram_din = {DATA_WIDTH{1'bx}};
endcase
end
// Logic for bram_en and bram_we
assign bram_en = (curr_state == s0 || curr_state == s1)?1'b1:1'b0;
assign bram_we = (curr_state == s0 || curr_state == s1)?4'b1111:4'b0000;
// Logic for valid
assign valid = (curr_state == wait0 && ready)?1'b1:1'b0;
assign data = (curr_state == wait0 && ready)?1:0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISO0P_FUNCTIONAL_V
/**
* iso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_1_V
`define SKY130_FD_SC_MS__DFSBP_1_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSTP_2_V
`define SKY130_FD_SC_HS__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfstp_2 (
CLK ,
D ,
Q ,
SET_B,
VPWR ,
VGND
);
input CLK ;
input D ;
output Q ;
input SET_B;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfstp_2 (
CLK ,
D ,
Q ,
SET_B
);
input CLK ;
input D ;
output Q ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfstp base (
.CLK(CLK),
.D(D),
.Q(Q),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSTP_2_V
|
`timescale 1ns / 1ps
/*
* File : Control.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 7-Jun-2011 GEA Initial design.
* 2.0 26-May-2012 GEA Release version with CP0.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Datapath Controller. This module sets the datapath control
* bits for an incoming instruction. These control bits follow the
* instruction through each pipeline stage as needed, and constitute
* the effective operation of the processor through each pipeline stage.
*/
module Control(
input ID_Stall,
input [5:0] OpCode,
input [5:0] Funct,
input [4:0] Rs, // used to differentiate mfc0 and mtc0
input [4:0] Rt, // used to differentiate bgez,bgezal,bltz,bltzal,teqi,tgei,tgeiu,tlti,tltiu,tnei
input Cmp_EQ,
input Cmp_GZ,
input Cmp_GEZ,
input Cmp_LZ,
input Cmp_LEZ,
//------------
output IF_Flush,
output reg [7:0] DP_Hazards,
output [1:0] PCSrc,
output SignExtend,
output Link,
output Movn,
output Movz,
output Mfc0,
output Mtc0,
output CP1,
output CP2,
output CP3,
output Eret,
output Trap,
output TrapCond,
output EXC_Sys,
output EXC_Bp,
output EXC_RI,
output ID_CanErr,
output EX_CanErr,
output M_CanErr,
output NextIsDelay,
output RegDst,
output ALUSrcImm,
output reg [4:0] ALUOp,
output LLSC,
output MemWrite,
output MemRead,
output MemByte,
output MemHalf,
output MemSignExtend,
output Left,
output Right,
output RegWrite,
output MemtoReg
);
`include "MIPS_Parameters.v"
wire Movc;
wire Branch, Branch_EQ, Branch_GTZ, Branch_LEZ, Branch_NEQ, Branch_GEZ, Branch_LTZ;
wire Unaligned_Mem;
reg [15:0] Datapath;
assign PCSrc[0] = Datapath[14];
assign Link = Datapath[13];
assign ALUSrcImm = Datapath[12];
assign Movc = Datapath[11];
assign Trap = Datapath[10];
assign TrapCond = Datapath[9];
assign RegDst = Datapath[8];
assign LLSC = Datapath[7];
assign MemRead = Datapath[6];
assign MemWrite = Datapath[5];
assign MemHalf = Datapath[4];
assign MemByte = Datapath[3];
assign MemSignExtend = Datapath[2];
assign RegWrite = Datapath[1];
assign MemtoReg = Datapath[0];
reg [2:0] DP_Exceptions;
assign ID_CanErr = DP_Exceptions[2];
assign EX_CanErr = DP_Exceptions[1];
assign M_CanErr = DP_Exceptions[0];
// Set the main datapath control signals based on the Op Code
always @(*) begin
if (ID_Stall)
Datapath <= `DP_None;
else begin
case (OpCode)
// R-Type
`Op_Type_R :
begin
case (Funct)
`Funct_Add : Datapath <= `DP_Add;
`Funct_Addu : Datapath <= `DP_Addu;
`Funct_And : Datapath <= `DP_And;
`Funct_Break : Datapath <= `DP_Break;
`Funct_Div : Datapath <= `DP_Div;
`Funct_Divu : Datapath <= `DP_Divu;
`Funct_Jalr : Datapath <= `DP_Jalr;
`Funct_Jr : Datapath <= `DP_Jr;
`Funct_Mfhi : Datapath <= `DP_Mfhi;
`Funct_Mflo : Datapath <= `DP_Mflo;
`Funct_Movn : Datapath <= `DP_Movn;
`Funct_Movz : Datapath <= `DP_Movz;
`Funct_Mthi : Datapath <= `DP_Mthi;
`Funct_Mtlo : Datapath <= `DP_Mtlo;
`Funct_Mult : Datapath <= `DP_Mult;
`Funct_Multu : Datapath <= `DP_Multu;
`Funct_Nor : Datapath <= `DP_Nor;
`Funct_Or : Datapath <= `DP_Or;
`Funct_Sll : Datapath <= `DP_Sll;
`Funct_Sllv : Datapath <= `DP_Sllv;
`Funct_Slt : Datapath <= `DP_Slt;
`Funct_Sltu : Datapath <= `DP_Sltu;
`Funct_Sra : Datapath <= `DP_Sra;
`Funct_Srav : Datapath <= `DP_Srav;
`Funct_Srl : Datapath <= `DP_Srl;
`Funct_Srlv : Datapath <= `DP_Srlv;
`Funct_Sub : Datapath <= `DP_Sub;
`Funct_Subu : Datapath <= `DP_Subu;
`Funct_Syscall : Datapath <= `DP_Syscall;
`Funct_Teq : Datapath <= `DP_Teq;
`Funct_Tge : Datapath <= `DP_Tge;
`Funct_Tgeu : Datapath <= `DP_Tgeu;
`Funct_Tlt : Datapath <= `DP_Tlt;
`Funct_Tltu : Datapath <= `DP_Tltu;
`Funct_Tne : Datapath <= `DP_Tne;
`Funct_Xor : Datapath <= `DP_Xor;
default : Datapath <= `DP_None;
endcase
end
// R2-Type
`Op_Type_R2 :
begin
case (Funct)
`Funct_Clo : Datapath <= `DP_Clo;
`Funct_Clz : Datapath <= `DP_Clz;
`Funct_Madd : Datapath <= `DP_Madd;
`Funct_Maddu : Datapath <= `DP_Maddu;
`Funct_Msub : Datapath <= `DP_Msub;
`Funct_Msubu : Datapath <= `DP_Msubu;
`Funct_Mul : Datapath <= `DP_Mul;
default : Datapath <= `DP_None;
endcase
end
// I-Type
`Op_Addi : Datapath <= `DP_Addi;
`Op_Addiu : Datapath <= `DP_Addiu;
`Op_Andi : Datapath <= `DP_Andi;
`Op_Ori : Datapath <= `DP_Ori;
`Op_Pref : Datapath <= `DP_Pref;
`Op_Slti : Datapath <= `DP_Slti;
`Op_Sltiu : Datapath <= `DP_Sltiu;
`Op_Xori : Datapath <= `DP_Xori;
// Jumps (using immediates)
`Op_J : Datapath <= `DP_J;
`Op_Jal : Datapath <= `DP_Jal;
// Branches and Traps
`Op_Type_BI :
begin
case (Rt)
`OpRt_Bgez : Datapath <= `DP_Bgez;
`OpRt_Bgezal : Datapath <= `DP_Bgezal;
`OpRt_Bltz : Datapath <= `DP_Bltz;
`OpRt_Bltzal : Datapath <= `DP_Bltzal;
`OpRt_Teqi : Datapath <= `DP_Teqi;
`OpRt_Tgei : Datapath <= `DP_Tgei;
`OpRt_Tgeiu : Datapath <= `DP_Tgeiu;
`OpRt_Tlti : Datapath <= `DP_Tlti;
`OpRt_Tltiu : Datapath <= `DP_Tltiu;
`OpRt_Tnei : Datapath <= `DP_Tnei;
default : Datapath <= `DP_None;
endcase
end
`Op_Beq : Datapath <= `DP_Beq;
`Op_Bgtz : Datapath <= `DP_Bgtz;
`Op_Blez : Datapath <= `DP_Blez;
`Op_Bne : Datapath <= `DP_Bne;
// Coprocessor 0
`Op_Type_CP0 :
begin
case (Rs)
`OpRs_MF : Datapath <= `DP_Mfc0;
`OpRs_MT : Datapath <= `DP_Mtc0;
`OpRs_ERET : Datapath <= (Funct == `Funct_ERET) ? `DP_Eret : `DP_None;
default : Datapath <= `DP_None;
endcase
end
// Memory
`Op_Lb : Datapath <= `DP_Lb;
`Op_Lbu : Datapath <= `DP_Lbu;
`Op_Lh : Datapath <= `DP_Lh;
`Op_Lhu : Datapath <= `DP_Lhu;
`Op_Ll : Datapath <= `DP_Ll;
`Op_Lui : Datapath <= `DP_Lui;
`Op_Lw : Datapath <= `DP_Lw;
`Op_Lwl : Datapath <= `DP_Lwl;
`Op_Lwr : Datapath <= `DP_Lwr;
`Op_Sb : Datapath <= `DP_Sb;
`Op_Sc : Datapath <= `DP_Sc;
`Op_Sh : Datapath <= `DP_Sh;
`Op_Sw : Datapath <= `DP_Sw;
`Op_Swl : Datapath <= `DP_Swl;
`Op_Swr : Datapath <= `DP_Swr;
default : Datapath <= `DP_None;
endcase
end
end
// Set the Hazard Control Signals and Exception Indicators based on the Op Code
always @(*) begin
case (OpCode)
// R-Type
`Op_Type_R :
begin
case (Funct)
`Funct_Add : begin DP_Hazards <= `HAZ_Add; DP_Exceptions <= `EXC_Add; end
`Funct_Addu : begin DP_Hazards <= `HAZ_Addu; DP_Exceptions <= `EXC_Addu; end
`Funct_And : begin DP_Hazards <= `HAZ_And; DP_Exceptions <= `EXC_And; end
`Funct_Break : begin DP_Hazards <= `HAZ_Break; DP_Exceptions <= `EXC_Break; end
`Funct_Div : begin DP_Hazards <= `HAZ_Div; DP_Exceptions <= `EXC_Div; end
`Funct_Divu : begin DP_Hazards <= `HAZ_Divu; DP_Exceptions <= `EXC_Divu; end
`Funct_Jalr : begin DP_Hazards <= `HAZ_Jalr; DP_Exceptions <= `EXC_Jalr; end
`Funct_Jr : begin DP_Hazards <= `HAZ_Jr; DP_Exceptions <= `EXC_Jr; end
`Funct_Mfhi : begin DP_Hazards <= `HAZ_Mfhi; DP_Exceptions <= `EXC_Mfhi; end
`Funct_Mflo : begin DP_Hazards <= `HAZ_Mflo; DP_Exceptions <= `EXC_Mflo; end
`Funct_Movn : begin DP_Hazards <= `HAZ_Movn; DP_Exceptions <= `EXC_Movn; end
`Funct_Movz : begin DP_Hazards <= `HAZ_Movz; DP_Exceptions <= `EXC_Movz; end
`Funct_Mthi : begin DP_Hazards <= `HAZ_Mthi; DP_Exceptions <= `EXC_Mthi; end
`Funct_Mtlo : begin DP_Hazards <= `HAZ_Mtlo; DP_Exceptions <= `EXC_Mtlo; end
`Funct_Mult : begin DP_Hazards <= `HAZ_Mult; DP_Exceptions <= `EXC_Mult; end
`Funct_Multu : begin DP_Hazards <= `HAZ_Multu; DP_Exceptions <= `EXC_Multu; end
`Funct_Nor : begin DP_Hazards <= `HAZ_Nor; DP_Exceptions <= `EXC_Nor; end
`Funct_Or : begin DP_Hazards <= `HAZ_Or; DP_Exceptions <= `EXC_Or; end
`Funct_Sll : begin DP_Hazards <= `HAZ_Sll; DP_Exceptions <= `EXC_Sll; end
`Funct_Sllv : begin DP_Hazards <= `HAZ_Sllv; DP_Exceptions <= `EXC_Sllv; end
`Funct_Slt : begin DP_Hazards <= `HAZ_Slt; DP_Exceptions <= `EXC_Slt; end
`Funct_Sltu : begin DP_Hazards <= `HAZ_Sltu; DP_Exceptions <= `EXC_Sltu; end
`Funct_Sra : begin DP_Hazards <= `HAZ_Sra; DP_Exceptions <= `EXC_Sra; end
`Funct_Srav : begin DP_Hazards <= `HAZ_Srav; DP_Exceptions <= `EXC_Srav; end
`Funct_Srl : begin DP_Hazards <= `HAZ_Srl; DP_Exceptions <= `EXC_Srl; end
`Funct_Srlv : begin DP_Hazards <= `HAZ_Srlv; DP_Exceptions <= `EXC_Srlv; end
`Funct_Sub : begin DP_Hazards <= `HAZ_Sub; DP_Exceptions <= `EXC_Sub; end
`Funct_Subu : begin DP_Hazards <= `HAZ_Subu; DP_Exceptions <= `EXC_Subu; end
`Funct_Syscall : begin DP_Hazards <= `HAZ_Syscall; DP_Exceptions <= `EXC_Syscall; end
`Funct_Teq : begin DP_Hazards <= `HAZ_Teq; DP_Exceptions <= `EXC_Teq; end
`Funct_Tge : begin DP_Hazards <= `HAZ_Tge; DP_Exceptions <= `EXC_Tge; end
`Funct_Tgeu : begin DP_Hazards <= `HAZ_Tgeu; DP_Exceptions <= `EXC_Tgeu; end
`Funct_Tlt : begin DP_Hazards <= `HAZ_Tlt; DP_Exceptions <= `EXC_Tlt; end
`Funct_Tltu : begin DP_Hazards <= `HAZ_Tltu; DP_Exceptions <= `EXC_Tltu; end
`Funct_Tne : begin DP_Hazards <= `HAZ_Tne; DP_Exceptions <= `EXC_Tne; end
`Funct_Xor : begin DP_Hazards <= `HAZ_Xor; DP_Exceptions <= `EXC_Xor; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// R2-Type
`Op_Type_R2 :
begin
case (Funct)
`Funct_Clo : begin DP_Hazards <= `HAZ_Clo; DP_Exceptions <= `EXC_Clo; end
`Funct_Clz : begin DP_Hazards <= `HAZ_Clz; DP_Exceptions <= `EXC_Clz; end
`Funct_Madd : begin DP_Hazards <= `HAZ_Madd; DP_Exceptions <= `EXC_Madd; end
`Funct_Maddu : begin DP_Hazards <= `HAZ_Maddu; DP_Exceptions <= `EXC_Maddu; end
`Funct_Msub : begin DP_Hazards <= `HAZ_Msub; DP_Exceptions <= `EXC_Msub; end
`Funct_Msubu : begin DP_Hazards <= `HAZ_Msubu; DP_Exceptions <= `EXC_Msubu; end
`Funct_Mul : begin DP_Hazards <= `HAZ_Mul; DP_Exceptions <= `EXC_Mul; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// I-Type
`Op_Addi : begin DP_Hazards <= `HAZ_Addi; DP_Exceptions <= `EXC_Addi; end
`Op_Addiu : begin DP_Hazards <= `HAZ_Addiu; DP_Exceptions <= `EXC_Addiu; end
`Op_Andi : begin DP_Hazards <= `HAZ_Andi; DP_Exceptions <= `EXC_Andi; end
`Op_Ori : begin DP_Hazards <= `HAZ_Ori; DP_Exceptions <= `EXC_Ori; end
`Op_Pref : begin DP_Hazards <= `HAZ_Pref; DP_Exceptions <= `EXC_Pref; end
`Op_Slti : begin DP_Hazards <= `HAZ_Slti; DP_Exceptions <= `EXC_Slti; end
`Op_Sltiu : begin DP_Hazards <= `HAZ_Sltiu; DP_Exceptions <= `EXC_Sltiu; end
`Op_Xori : begin DP_Hazards <= `HAZ_Xori; DP_Exceptions <= `EXC_Xori; end
// Jumps
`Op_J : begin DP_Hazards <= `HAZ_J; DP_Exceptions <= `EXC_J; end
`Op_Jal : begin DP_Hazards <= `HAZ_Jal; DP_Exceptions <= `EXC_Jal; end
// Branches and Traps
`Op_Type_BI :
begin
case (Rt)
`OpRt_Bgez : begin DP_Hazards <= `HAZ_Bgez; DP_Exceptions <= `EXC_Bgez; end
`OpRt_Bgezal : begin DP_Hazards <= `HAZ_Bgezal; DP_Exceptions <= `EXC_Bgezal; end
`OpRt_Bltz : begin DP_Hazards <= `HAZ_Bltz; DP_Exceptions <= `EXC_Bltz; end
`OpRt_Bltzal : begin DP_Hazards <= `HAZ_Bltzal; DP_Exceptions <= `EXC_Bltzal; end
`OpRt_Teqi : begin DP_Hazards <= `HAZ_Teqi; DP_Exceptions <= `EXC_Teqi; end
`OpRt_Tgei : begin DP_Hazards <= `HAZ_Tgei; DP_Exceptions <= `EXC_Tgei; end
`OpRt_Tgeiu : begin DP_Hazards <= `HAZ_Tgeiu; DP_Exceptions <= `EXC_Tgeiu; end
`OpRt_Tlti : begin DP_Hazards <= `HAZ_Tlti; DP_Exceptions <= `EXC_Tlti; end
`OpRt_Tltiu : begin DP_Hazards <= `HAZ_Tltiu; DP_Exceptions <= `EXC_Tltiu; end
`OpRt_Tnei : begin DP_Hazards <= `HAZ_Tnei; DP_Exceptions <= `EXC_Tnei; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
`Op_Beq : begin DP_Hazards <= `HAZ_Beq; DP_Exceptions <= `EXC_Beq; end
`Op_Bgtz : begin DP_Hazards <= `HAZ_Bgtz; DP_Exceptions <= `EXC_Bgtz; end
`Op_Blez : begin DP_Hazards <= `HAZ_Blez; DP_Exceptions <= `EXC_Blez; end
`Op_Bne : begin DP_Hazards <= `HAZ_Bne; DP_Exceptions <= `EXC_Bne; end
// Coprocessor 0
`Op_Type_CP0 :
begin
case (Rs)
`OpRs_MF : begin DP_Hazards <= `HAZ_Mfc0; DP_Exceptions <= `EXC_Mfc0; end
`OpRs_MT : begin DP_Hazards <= `HAZ_Mtc0; DP_Exceptions <= `EXC_Mtc0; end
`OpRs_ERET : begin DP_Hazards <= (Funct == `Funct_ERET) ? `HAZ_Eret : 8'hxx; DP_Exceptions <= `EXC_Eret; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// Memory
`Op_Lb : begin DP_Hazards <= `HAZ_Lb; DP_Exceptions <= `EXC_Lb; end
`Op_Lbu : begin DP_Hazards <= `HAZ_Lbu; DP_Exceptions <= `EXC_Lbu; end
`Op_Lh : begin DP_Hazards <= `HAZ_Lh; DP_Exceptions <= `EXC_Lh; end
`Op_Lhu : begin DP_Hazards <= `HAZ_Lhu; DP_Exceptions <= `EXC_Lhu; end
`Op_Ll : begin DP_Hazards <= `HAZ_Ll; DP_Exceptions <= `EXC_Ll; end
`Op_Lui : begin DP_Hazards <= `HAZ_Lui; DP_Exceptions <= `EXC_Lui; end
`Op_Lw : begin DP_Hazards <= `HAZ_Lw; DP_Exceptions <= `EXC_Lw; end
`Op_Lwl : begin DP_Hazards <= `HAZ_Lwl; DP_Exceptions <= `EXC_Lwl; end
`Op_Lwr : begin DP_Hazards <= `HAZ_Lwr; DP_Exceptions <= `EXC_Lwr; end
`Op_Sb : begin DP_Hazards <= `HAZ_Sb; DP_Exceptions <= `EXC_Sb; end
`Op_Sc : begin DP_Hazards <= `HAZ_Sc; DP_Exceptions <= `EXC_Sc; end
`Op_Sh : begin DP_Hazards <= `HAZ_Sh; DP_Exceptions <= `EXC_Sh; end
`Op_Sw : begin DP_Hazards <= `HAZ_Sw; DP_Exceptions <= `EXC_Sw; end
`Op_Swl : begin DP_Hazards <= `HAZ_Swl; DP_Exceptions <= `EXC_Swl; end
`Op_Swr : begin DP_Hazards <= `HAZ_Swr; DP_Exceptions <= `EXC_Swr; end
default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end
endcase
end
// ALU Assignment
always @(*) begin
if (ID_Stall)
ALUOp <= `AluOp_Addu; // Any Op that doesn't write HILO or cause exceptions
else begin
case (OpCode)
`Op_Type_R :
begin
case (Funct)
`Funct_Add : ALUOp <= `AluOp_Add;
`Funct_Addu : ALUOp <= `AluOp_Addu;
`Funct_And : ALUOp <= `AluOp_And;
`Funct_Div : ALUOp <= `AluOp_Div;
`Funct_Divu : ALUOp <= `AluOp_Divu;
`Funct_Jalr : ALUOp <= `AluOp_Addu;
`Funct_Mfhi : ALUOp <= `AluOp_Mfhi;
`Funct_Mflo : ALUOp <= `AluOp_Mflo;
`Funct_Movn : ALUOp <= `AluOp_Addu;
`Funct_Movz : ALUOp <= `AluOp_Addu;
`Funct_Mthi : ALUOp <= `AluOp_Mthi;
`Funct_Mtlo : ALUOp <= `AluOp_Mtlo;
`Funct_Mult : ALUOp <= `AluOp_Mult;
`Funct_Multu : ALUOp <= `AluOp_Multu;
`Funct_Nor : ALUOp <= `AluOp_Nor;
`Funct_Or : ALUOp <= `AluOp_Or;
`Funct_Sll : ALUOp <= `AluOp_Sll;
`Funct_Sllv : ALUOp <= `AluOp_Sllv;
`Funct_Slt : ALUOp <= `AluOp_Slt;
`Funct_Sltu : ALUOp <= `AluOp_Sltu;
`Funct_Sra : ALUOp <= `AluOp_Sra;
`Funct_Srav : ALUOp <= `AluOp_Srav;
`Funct_Srl : ALUOp <= `AluOp_Srl;
`Funct_Srlv : ALUOp <= `AluOp_Srlv;
`Funct_Sub : ALUOp <= `AluOp_Sub;
`Funct_Subu : ALUOp <= `AluOp_Subu;
`Funct_Syscall : ALUOp <= `AluOp_Addu;
`Funct_Teq : ALUOp <= `AluOp_Subu;
`Funct_Tge : ALUOp <= `AluOp_Slt;
`Funct_Tgeu : ALUOp <= `AluOp_Sltu;
`Funct_Tlt : ALUOp <= `AluOp_Slt;
`Funct_Tltu : ALUOp <= `AluOp_Sltu;
`Funct_Tne : ALUOp <= `AluOp_Subu;
`Funct_Xor : ALUOp <= `AluOp_Xor;
default : ALUOp <= `AluOp_Addu;
endcase
end
`Op_Type_R2 :
begin
case (Funct)
`Funct_Clo : ALUOp <= `AluOp_Clo;
`Funct_Clz : ALUOp <= `AluOp_Clz;
`Funct_Madd : ALUOp <= `AluOp_Madd;
`Funct_Maddu : ALUOp <= `AluOp_Maddu;
`Funct_Msub : ALUOp <= `AluOp_Msub;
`Funct_Msubu : ALUOp <= `AluOp_Msubu;
`Funct_Mul : ALUOp <= `AluOp_Mul;
default : ALUOp <= `AluOp_Addu;
endcase
end
`Op_Type_BI :
begin
case (Rt)
`OpRt_Teqi : ALUOp <= `AluOp_Subu;
`OpRt_Tgei : ALUOp <= `AluOp_Slt;
`OpRt_Tgeiu : ALUOp <= `AluOp_Sltu;
`OpRt_Tlti : ALUOp <= `AluOp_Slt;
`OpRt_Tltiu : ALUOp <= `AluOp_Sltu;
`OpRt_Tnei : ALUOp <= `AluOp_Subu;
default : ALUOp <= `AluOp_Addu; // Branches don't matter.
endcase
end
`Op_Type_CP0 : ALUOp <= `AluOp_Addu;
`Op_Addi : ALUOp <= `AluOp_Add;
`Op_Addiu : ALUOp <= `AluOp_Addu;
`Op_Andi : ALUOp <= `AluOp_And;
`Op_Jal : ALUOp <= `AluOp_Addu;
`Op_Lb : ALUOp <= `AluOp_Addu;
`Op_Lbu : ALUOp <= `AluOp_Addu;
`Op_Lh : ALUOp <= `AluOp_Addu;
`Op_Lhu : ALUOp <= `AluOp_Addu;
`Op_Ll : ALUOp <= `AluOp_Addu;
`Op_Lui : ALUOp <= `AluOp_Sllc;
`Op_Lw : ALUOp <= `AluOp_Addu;
`Op_Lwl : ALUOp <= `AluOp_Addu;
`Op_Lwr : ALUOp <= `AluOp_Addu;
`Op_Ori : ALUOp <= `AluOp_Or;
`Op_Sb : ALUOp <= `AluOp_Addu;
`Op_Sc : ALUOp <= `AluOp_Addu; // XXX Needs HW implement
`Op_Sh : ALUOp <= `AluOp_Addu;
`Op_Slti : ALUOp <= `AluOp_Slt;
`Op_Sltiu : ALUOp <= `AluOp_Sltu;
`Op_Sw : ALUOp <= `AluOp_Addu;
`Op_Swl : ALUOp <= `AluOp_Addu;
`Op_Swr : ALUOp <= `AluOp_Addu;
`Op_Xori : ALUOp <= `AluOp_Xor;
default : ALUOp <= `AluOp_Addu;
endcase
end
end
/***
These remaining options cover portions of the datapath that are not
controlled directly by the datapath bits. Note that some refer to bits of
the opcode or other fields, which breaks the otherwise fully-abstracted view
of instruction encodings. Make sure when adding custom instructions that
no false positives/negatives are generated here.
***/
// Branch Detection: Options are mutually exclusive.
assign Branch_EQ = OpCode[2] & ~OpCode[1] & ~OpCode[0] & Cmp_EQ;
assign Branch_GTZ = OpCode[2] & OpCode[1] & OpCode[0] & Cmp_GZ;
assign Branch_LEZ = OpCode[2] & OpCode[1] & ~OpCode[0] & Cmp_LEZ;
assign Branch_NEQ = OpCode[2] & ~OpCode[1] & OpCode[0] & ~Cmp_EQ;
assign Branch_GEZ = ~OpCode[2] & Rt[0] & Cmp_GEZ;
assign Branch_LTZ = ~OpCode[2] & ~Rt[0] & Cmp_LZ;
assign Branch = Branch_EQ | Branch_GTZ | Branch_LEZ | Branch_NEQ | Branch_GEZ | Branch_LTZ;
assign PCSrc[1] = (Datapath[15] & ~Datapath[14]) ? Branch : Datapath[15];
/* In MIPS32, all Branch and Jump operations execute the Branch Delay Slot,
* or next instruction, regardless if the branch is taken or not. The exception
* is the "Branch Likely" instruction group. These are deprecated, however, and not
* implemented here. "IF_Flush" is defined to allow for the cancelation of a
* Branch Delay Slot should these be implemented later.
*/
assign IF_Flush = 0;
// Indicator that next instruction is a Branch Delay Slot.
assign NextIsDelay = Datapath[15] | Datapath[14];
// Sign- or Zero-Extension Control. The only ops that require zero-extension are
// Andi, Ori, and Xori. The following also zero-extends 'lui', however it does not alter the effect of lui.
assign SignExtend = (OpCode[5:2] != 4'b0011);
// Move Conditional
assign Movn = Movc & Funct[0];
assign Movz = Movc & ~Funct[0];
// Coprocessor 0 (Mfc0, Mtc0) control signals.
assign Mfc0 = ((OpCode == `Op_Type_CP0) && (Rs == `OpRs_MF));
assign Mtc0 = ((OpCode == `Op_Type_CP0) && (Rs == `OpRs_MT));
assign Eret = ((OpCode == `Op_Type_CP0) && (Rs == `OpRs_ERET) && (Funct == `Funct_ERET));
// Coprocessor 1,2,3 accesses (not implemented)
assign CP1 = (OpCode == `Op_Type_CP1);
assign CP2 = (OpCode == `Op_Type_CP2);
assign CP3 = (OpCode == `Op_Type_CP3);
// Exceptions found in ID
assign EXC_Sys = ((OpCode == `Op_Type_R) && (Funct == `Funct_Syscall));
assign EXC_Bp = ((OpCode == `Op_Type_R) && (Funct == `Funct_Break));
// Unaligned Memory Accesses (lwl, lwr, swl, swr)
assign Unaligned_Mem = OpCode[5] & ~OpCode[4] & OpCode[1] & ~OpCode[0];
assign Left = Unaligned_Mem & ~OpCode[2];
assign Right = Unaligned_Mem & OpCode[2];
// TODO: Reserved Instruction Exception must still be implemented
assign EXC_RI = 0;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_out (
// data interface
tx_clk,
tx_data_p,
tx_data_n,
tx_data_out_p,
tx_data_out_n);
// parameters
parameter BUFTYPE = 0;
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input tx_clk;
input tx_data_p;
input tx_data_n;
output tx_data_out_p;
output tx_data_out_n;
// defaults
assign tx_data_out_n = 1'd0;
// instantiations
altddio_out #(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1))
i_tx_data_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.oe_out (),
.outclocken (1'b1),
.outclock (tx_clk),
.datain_h (tx_data_p),
.datain_l (tx_data_n),
.dataout (tx_data_out_p));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_SYMBOL_V
`define SKY130_FD_SC_HD__DLRTP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:43:12 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_debounce_0_0 -prefix
// system_debounce_0_0_ system_debounce_0_0_stub.v
// Design : system_debounce_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "debounce,Vivado 2016.4" *)
module system_debounce_0_0(clk, signal_in, signal_out)
/* synthesis syn_black_box black_box_pad_pin="clk,signal_in,signal_out" */;
input clk;
input signal_in;
output signal_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_SYMBOL_V
`define SKY130_FD_SC_LP__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_SYMBOL_V
|
module testbench_16 ();
parameter START_ADDR = 32'h8002_0000; // h80020000
reg clk;
reg [31:0] addr;
reg [31:0] din;
reg enable;
reg rw;
reg [1:0] access_size;
reg test_mode;
reg [31:0] int_addr;
wire [31:0] dout;
wire busy;
mips_memory2 test_memory(.clk(clk),
.addr(addr),
.din(din),
.dout(dout),
.access_size(access_size),
.rw(rw),
.busy(busy),
.enable(enable));
reg [7:0] mem[0:256];
initial
begin
clk = 1'b0;
enable = 1'b0;
addr = 32'h8002_0000;
din = 32'b0000_0000;
rw = 1'b1;
access_size = 2'b11;
test_mode = 0;
int_addr = 0;
$readmemh("SumArray.x", mem);
end
always @(negedge clk)
begin
if ((addr + int_addr) > 32'h8002_00b4 & test_mode == 0)
begin
enable = 0;
if (busy == 0)
begin
enable = 1;
test_mode = 1;
addr = 32'h8002_0000;
rw = 1'b0;
int_addr = 4;
end
end
else
begin
if (test_mode == 0)
begin
enable = 1'b1;
din[31:24] = mem[addr + int_addr - START_ADDR];
din[23:16] = mem[addr + int_addr + 1 - START_ADDR];
din[15:8] = mem[addr + int_addr + 2 - START_ADDR];
din[7:0] = mem[addr + int_addr + 3 - START_ADDR];
int_addr = int_addr + 32'h0000_0004;
if (int_addr == 68)
begin
addr = addr + 32'h0000_0040;
int_addr = 4;
end
end
else
begin
enable = 1'b1;
int_addr = int_addr + 32'h0000_0004;
if (int_addr == 68)
begin
addr = addr + 32'h0000_0040;
int_addr = 4;
end
end
end
end
always
#5 clk = !clk;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_4_V
`define SKY130_FD_SC_LP__OR3B_4_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_rxeq_scan.v
// Version : 1.3
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE Equalization Eye Scan Test Module for 7 Series Transceiver
// Version : 10.5
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- RXEQ Eye Scan Module ----------------------------------------------
module pcie_7x_v1_3_rxeq_scan
(
//---------- Input -------------------------------------
input RXEQSCAN_CLK,
input RXEQSCAN_RST_N,
input [ 2:0] RXEQSCAN_PRESET,
input RXEQSCAN_PRESET_VALID,
input [ 3:0] RXEQSCAN_TXPRESET,
input [17:0] RXEQSCAN_TXCOEFF,
input RXEQSCAN_NEW_TXCOEFF_REQ,
input [ 5:0] RXEQSCAN_FS,
input [ 5:0] RXEQSCAN_LF,
//---------- Output ------------------------------------
output RXEQSCAN_PRESET_DONE,
output [17:0] RXEQSCAN_NEW_TXCOEFF,
output RXEQSCAN_NEW_TXCOEFF_DONE,
output RXEQSCAN_LFFS_SEL,
output RXEQSCAN_ADAPT_DONE
);
//---------- Input Register ----------------------------
reg [ 2:0] preset_reg1;
reg preset_valid_reg1;
reg [ 3:0] txpreset_reg1;
reg [17:0] txcoeff_reg1;
reg new_txcoeff_req_reg1;
reg [ 5:0] fs_reg1;
reg [ 5:0] lf_reg1;
reg [ 2:0] preset_reg2;
reg preset_valid_reg2;
reg [ 3:0] txpreset_reg2;
reg [17:0] txcoeff_reg2;
reg new_txcoeff_req_reg2;
reg [ 5:0] fs_reg2;
reg [ 5:0] lf_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] lffs_sel_cnt = 2'd0;
reg [ 2:0] adapt_done_cnt = 3'd0;
//---------- Output Register ---------------------------
reg preset_done = 1'd0;
reg [17:0] new_txcoeff = 18'd0;
reg new_txcoeff_done = 1'd0;
reg lffs_sel = 1'd0;
reg adapt_done = 1'd0;
reg [ 2:0] fsm = 3'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 3'b001;
localparam FSM_PRESET = 3'b010;
localparam FSM_NEW_TXCOEFF_REQ = 3'b100;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= 3'd0;
preset_valid_reg1 <= 1'd0;
txpreset_reg1 <= 4'd0;
txcoeff_reg1 <= 18'd0;
new_txcoeff_req_reg1 <= 1'd0;
fs_reg1 <= 6'd0;
lf_reg1 <= 6'd0;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= 3'd0;
preset_valid_reg2 <= 1'd0;
txpreset_reg2 <= 4'd0;
txcoeff_reg2 <= 18'd0;
new_txcoeff_req_reg2 <= 1'd0;
fs_reg2 <= 6'd0;
lf_reg2 <= 6'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= RXEQSCAN_PRESET;
preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
txpreset_reg1 <= RXEQSCAN_TXPRESET;
txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
fs_reg1 <= RXEQSCAN_FS;
lf_reg1 <= RXEQSCAN_LF;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= preset_reg1;
preset_valid_reg2 <= preset_valid_reg1;
txpreset_reg2 <= txpreset_reg1;
txcoeff_reg2 <= txcoeff_reg1;
new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
fs_reg2 <= fs_reg1;
lf_reg2 <= lf_reg1;
end
end
//---------- Eye Scan ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= 2'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 3'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Process RXEQ Preset ---------------
if (preset_valid_reg2)
begin
fsm <= FSM_PRESET;
preset_done <= 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient --------
else if (new_txcoeff_req_reg2)
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
new_txcoeff <= txcoeff_reg2;
new_txcoeff_done <= 1'd1;
lffs_sel <= (lffs_sel_cnt == 2'd1);
lffs_sel_cnt <= (lffs_sel_cnt + 2'd1);
adapt_done <= (adapt_done_cnt == 3'd1);
adapt_done_cnt <= (adapt_done_cnt + 3'd1);
end
//---------- Default ---------------------------
else
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Process RXEQ Preset -------------------
FSM_PRESET :
begin
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
preset_done <= 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient ------------
FSM_NEW_TXCOEFF_REQ :
begin
fsm <= (!new_txcoeff_req_reg2) ? FSM_IDLE : FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd1;
lffs_sel <= lffs_sel;
lffs_sel_cnt <= lffs_sel_cnt;
adapt_done <= adapt_done;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
lffs_sel_cnt <= 2'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 3'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Output ----------------------------------------------
assign RXEQSCAN_PRESET_DONE = preset_done;
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
assign RXEQSCAN_LFFS_SEL = lffs_sel;
assign RXEQSCAN_ADAPT_DONE = adapt_done;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: cpu_dma_queue.v
// Project: NF2.1
// Description:
// a slim CPU rx_fifo and tx_fifo connecting to the DMA interface
//
// Note that both rx_fifo and tx_fifo are first-word-fall-through FIFOs.
//
///////////////////////////////////////////////////////////////////////////////
module cpu_dma_queue
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter DMA_DATA_WIDTH = `CPCI_NF2_DATA_WIDTH,
parameter DMA_CTRL_WIDTH = DMA_DATA_WIDTH/8,
parameter TX_WATCHDOG_TIMEOUT = 125000
)
(output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- DMA rd rxfifo interface
output cpu_q_dma_pkt_avail,
input cpu_q_dma_rd,
output [DMA_DATA_WIDTH-1:0] cpu_q_dma_rd_data,
output [DMA_CTRL_WIDTH-1:0] cpu_q_dma_rd_ctrl,
// DMA wr txfifo interface
output cpu_q_dma_nearly_full,
input cpu_q_dma_wr,
input [DMA_DATA_WIDTH-1:0] cpu_q_dma_wr_data,
input [DMA_CTRL_WIDTH-1:0] cpu_q_dma_wr_ctrl,
// Register interface
input reg_req,
input reg_rd_wr_L,
input [`MAC_GRP_REG_ADDR_WIDTH-1:0] reg_addr,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_wr_data,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_rd_data,
output reg_ack,
// --- Misc
input reset,
input clk
);
// -------- Internal parameters --------------
// ------------- Wires/reg ------------------
wire tx_timeout;
// ------------- Modules -------------------
cpu_dma_queue_main
#(
.DATA_WIDTH (DATA_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DMA_CTRL_WIDTH (DMA_CTRL_WIDTH),
.TX_WATCHDOG_TIMEOUT (TX_WATCHDOG_TIMEOUT)
) cpu_dma_queue_main (
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_rdy (in_rdy),
// --- DMA rd rxfifo interface
.cpu_q_dma_pkt_avail (cpu_q_dma_pkt_avail),
.cpu_q_dma_rd (cpu_q_dma_rd),
.cpu_q_dma_rd_data (cpu_q_dma_rd_data),
.cpu_q_dma_rd_ctrl (cpu_q_dma_rd_ctrl),
// DMA wr txfifo interface
.cpu_q_dma_nearly_full (cpu_q_dma_nearly_full),
.cpu_q_dma_wr (cpu_q_dma_wr),
.cpu_q_dma_wr_data (cpu_q_dma_wr_data),
.cpu_q_dma_wr_ctrl (cpu_q_dma_wr_ctrl),
// Register interface
.tx_timeout (tx_timeout),
// --- Misc
.reset (reset),
.clk (clk)
);
cpu_dma_queue_regs
#(
.TX_WATCHDOG_TIMEOUT (TX_WATCHDOG_TIMEOUT)
) cpu_dma_queue_regs (
// Interface to "main" module
.tx_timeout (tx_timeout),
// Register interface
.reg_req (reg_req),
.reg_rd_wr_L (reg_rd_wr_L),
.reg_addr (reg_addr),
.reg_wr_data (reg_wr_data),
.reg_rd_data (reg_rd_data),
.reg_ack (reg_ack),
// --- Misc
.reset (reset),
.clk (clk)
);
// -------------- Logic --------------------
endmodule // cpu_dma_queue
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file TEST_TX_DP_RAM.v when simulating
// the core, TEST_TX_DP_RAM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module TEST_TX_DP_RAM(
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [10 : 0] addra;
input [31 : 0] dina;
input clkb;
input enb;
input [10 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("virtex5"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("virtex5")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ENB(enb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_LP__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_lp__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_lp__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_HS__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3B_BEHAVIORAL_V
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* avalon to rcn bus master interface.
*
* rcn bus vector definition =
* {valid, pending, wr, id[5:0], mask[3:0], addr[23:2], seq[1:0], data[31:0]}
*
* data = [31:0]
* seq = [33:32]
* addr = [55:34]
* mask = [59:56]
* id = [65:60]
* wr = [66]
* pending = [67]
* valid = [68]
*
*/
module avalon2rcn
(
input av_clk,
input av_rst,
output av_waitrequest,
input [21:0] av_address,
input av_write,
input av_read,
input [3:0] av_byteenable,
input [31:0] av_writedata,
output [31:0] av_readdata,
output av_readdatavalid,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter MASTER_ID = 6'h3F;
reg [68:0] rin;
reg [68:0] rout;
reg [2:0] next_rd_id;
reg [2:0] wait_rd_id;
reg [2:0] next_wr_id;
reg [2:0] wait_wr_id;
assign rcn_out = rout;
wire [5:0] my_id = MASTER_ID;
wire my_resp = rin[68] && !rin[67] && (rin[65:60] == my_id) &&
((rin[66]) ? (rin[33:32] == wait_wr_id[1:0]) : (rin[33:32] == wait_rd_id[1:0]));
wire bus_stall = (rin[68] && !my_resp) || ((av_read) ? (next_rd_id == wait_rd_id) : (next_wr_id == wait_wr_id));
assign av_waitrequest = bus_stall;
wire req_valid;
wire [68:0] req;
always @ (posedge av_clk or posedge av_rst)
if (av_rst)
begin
rin <= 69'd0;
rout <= 69'd0;
next_rd_id <= 3'b000;
wait_rd_id <= 3'b100;
next_wr_id <= 3'b000;
wait_wr_id <= 3'b100;
end
else
begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
next_rd_id <= (req_valid && av_read) ? next_rd_id + 3'd1 : next_rd_id;
wait_rd_id <= (my_resp && !rin[66]) ? wait_rd_id + 3'd1 : wait_rd_id;
next_wr_id <= (req_valid && av_write) ? next_wr_id + 3'd1 : next_wr_id;
wait_wr_id <= (my_resp && rin[66]) ? wait_wr_id + 3'd1 : wait_wr_id;
end
assign req_valid = (av_write || av_read) && !bus_stall;
wire [1:0] seq = (av_read) ? next_rd_id[1:0] : next_wr_id[1:0];
assign req = {1'b1, 1'b1, av_write, my_id, av_byteenable, av_address[21:0], seq, av_writedata};
assign av_readdatavalid = my_resp && !rin[66];
assign av_readdata = rin[31:0];
endmodule
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand1_and
#(parameter DATA_WIDTH=16, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps/ram_init1_and.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
// Test bench for our 6 bit shift register.
module main;
reg clk, rst_n, in;
wire [5:0] q;
shift sh (clk, rst_n, in, q);
always #10 clk = ~clk;
task assert(input condition);
if(!condition)
$finish(2);
endtask // assert
initial begin
clk = 0;
rst_n = 0;
in = 1;
#5 rst_n = 1;
#5
$display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd0);
#5 in = 0;
#5
$display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd1);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd2);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd4);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd8);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd16);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd32);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd0);
#20 $display("q = %d rst_n = %d", q, rst_n);
assert(q == 6'd0);
$finish;
end // initial begin
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_0_V
`define SKY130_FD_SC_LP__NAND3_0_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_0 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_0 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_0_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_1_V
`define SKY130_FD_SC_MS__NOR4B_1_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_1_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 18K-Bit FIFO
// /___/ /\ Filename : FIFO18E1.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/18/08 - Initial version.
// 07/10/08 - IR476500 Add INIT parameter support, sync with FIFO36 internal
// 08/22/08 - Updated SRVAL and INIT port mapping for FIFO_MODE = FIFO18_36. (IR 479958)
// 08/26/08 - Updated unused bit on wrcount and rdcount to match the hardware.
// 04/02/09 - Implemented DRC for FIFO_MODE (CR 517127).
// 04/29/09 - Fixed timing violation for asynchronous reset (CR 519016).
// 10/07/09 - Fixed reset behavior (CR 532794).
// 10/23/09 - Fixed RST and RSTREG (CR 537067).
// 06/30/10 - Updated RESET behavior and added SIM_DEVICE (CR 567515).
// 07/16/10 - Fixed RESET behavior during startup (CR 568626).
// 08/19/10 - Fixed RESET DRC during startup (CR 570708).
// 09/16/10 - Updated from bit to bus timing (CR 575523).
// 12/02/10 - Added warning message for 7SERIES Aysnc mode (CR 584052).
// 12/07/10 - Error out if no reset before first use of the fifo (CR 583638).
// 01/12/11 - updated warning message for 7SERIES Aysnc mode (CR 589721).
// 05/11/11 - Fixed DO not suppose to be reseted when RST asserted (CR 586526).
// 05/26/11 - Update Aysnc fifo behavior (CR 599680).
// 06/06/11 - Fixed RST in standard mode (CR 613216).
// 06/07/11 - Update DRC equation for ALMOST_FULL_OFFSET (CR 611057).
// 06/09/11 - Fixed GSR behavior (CR 611989).
// 06/13/11 - Added setup/hold timing check for RST (CR 606107).
// 07/07/11 - Fixed Full flag (CR 615773).
// 08/26/11 - Fixed FULL and ALMOSTFULL during initial time (CR 622163).
// 10/28/11 - Removed all mention of internal block ram from messaging (CR 569190).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/08/12 - Added DRC to check WREN/RDEN after RST deassertion (CR 644571).
// 05/16/12 - Added support of negative setup/hold/recovery/removal timing (CR 639991).
// 11/05/12 - Fixed full flag in async mode with sync clocks (CR 677254).
// 01/15/13 - Fixed index out of bound warnings for parity (CR 694713).
// 07/18/13 - Added invertible pins support (CR 715417).
// 08/01/13 - Fixed async mode with sync clocks (CR 728728).
// 10/31/13 - Fixed flags in async mode with sync clocks (CR 718734, 724006).
// 03/25/14 - Balanced all iniputs with xor (CR778933).
// 05/16/14 - Fixed empty flag (CR 799323).
// 06/12/14 - Fixed almost_*_offset DRC (CR 799864).
// 07/24/14 - Fixed DRC message error (CR 798755).
// 10/01/14 - Updated conditional timing check for IS_INVERTED parameter.
// 10/13/14 - Fixed almost_full_offset DRC (CR 824363).
// 10/22/14 - Added #1 to $finish (CR 808642).
// 01/21/15 - SIM_DEVICE defaulted to 7SERIES (PR 841966).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module FIFO18E1 (ALMOSTEMPTY, ALMOSTFULL, DO, DOP, EMPTY, FULL, RDCOUNT, RDERR, WRCOUNT, WRERR,
DI, DIP, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO18";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter INIT = 36'h0;
parameter IS_RDCLK_INVERTED = 1'b0;
parameter IS_RDEN_INVERTED = 1'b0;
parameter IS_RSTREG_INVERTED = 1'b0;
parameter IS_RST_INVERTED = 1'b0;
parameter IS_WRCLK_INVERTED = 1'b0;
parameter IS_WREN_INVERTED = 1'b0;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter SIM_DEVICE = "7SERIES";
parameter SRVAL = 36'h0;
output ALMOSTEMPTY;
output ALMOSTFULL;
output [31:0] DO;
output [3:0] DOP;
output EMPTY;
output FULL;
output [11:0] RDCOUNT;
output RDERR;
output [11:0] WRCOUNT;
output WRERR;
input [31:0] DI;
input [3:0] DIP;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
tri0 GSR = glbl.GSR;
wire dangle_out, dangle_out1, dangle_out1_1, dangle_out1_2;
wire [3:0] dangle_out4;
wire [7:0] dangle_out8;
wire [31:0] dangle_out32;
wire almostempty_wire, empty_wire, rderr_wire;
wire almostfull_wire, full_wire, wrerr_wire;
wire [11:0] wrcount_wire, rdcount_wire;
reg notifier, notifier_wrclk, notifier_rdclk;
wire [31:0] do_wire;
wire [3:0] dop_wire;
reg finish_error = 0;
`ifdef XIL_TIMING
wire [31:0] DI_dly;
wire [3:0] DIP_dly;
wire RDCLK_dly;
wire RDEN_dly;
wire REGCE_dly;
wire RST_dly;
wire RSTREG_dly;
wire WRCLK_dly;
wire WREN_dly;
`endif
wire [31:0] di_in;
wire [3:0] dip_in;
wire rdclk_in;
wire rden_in;
wire regce_in;
wire rst_in;
wire rstreg_in;
wire wrclk_in;
wire wren_in;
reg IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED;
reg IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED;
reg IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED;
reg IS_RST_INVERTED_REG = IS_RST_INVERTED;
reg IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED;
reg IS_WREN_INVERTED_REG = IS_WREN_INVERTED;
`ifdef XIL_TIMING
assign di_in = DI_dly;
assign dip_in = DIP_dly;
assign regce_in = REGCE_dly;
assign rdclk_in = RDCLK_dly ^ IS_RDCLK_INVERTED_REG;
assign rden_in = RDEN_dly ^ IS_RDEN_INVERTED_REG;
assign rst_in = RST_dly ^ IS_RST_INVERTED_REG;
assign rstreg_in = RSTREG_dly ^ IS_RSTREG_INVERTED_REG;
assign wrclk_in = WRCLK_dly ^ IS_WRCLK_INVERTED_REG;
assign wren_in = WREN_dly ^ IS_WREN_INVERTED_REG;
`else
assign di_in = DI;
assign dip_in = DIP;
assign regce_in = REGCE;
assign rdclk_in = RDCLK ^ IS_RDCLK_INVERTED_REG;
assign rden_in = RDEN ^ IS_RDEN_INVERTED_REG;
assign rst_in = RST ^ IS_RST_INVERTED_REG;
assign rstreg_in = RSTREG ^ IS_RSTREG_INVERTED_REG;
assign wrclk_in = WRCLK ^ IS_WRCLK_INVERTED_REG;
assign wren_in = WREN ^ IS_WREN_INVERTED_REG;
`endif // `ifndef XIL_TIMING
initial begin
case (FIFO_MODE)
"FIFO18" : ;
"FIFO18_36" : if (DATA_WIDTH != 36) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 36 when attribute FIFO_MODE = FIFO18_36.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute FIFO_MODE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are FIFO18 or FIFO18_36.", FIFO_MODE);
finish_error = 1;
end
endcase // case(FIFO_MODE)
case (DATA_WIDTH)
4, 9, 18 : ;
36 : if (FIFO_MODE != "FIFO18_36") begin
$display("DRC Error : The attribute FIFO_MODE must be set to FIFO18_36 when attribute DATA_WIDTH = 36.");
finish_error = 1;
end
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18 or 36.", DATA_WIDTH);
finish_error = 1;
end
endcase
if (!((IS_RDCLK_INVERTED >= 1'b0) && (IS_RDCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RDEN_INVERTED >= 1'b0) && (IS_RDEN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RDEN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RDEN_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RSTREG_INVERTED >= 1'b0) && (IS_RSTREG_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RSTREG_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RSTREG_INVERTED);
finish_error = 1'b1;
end
if (!((IS_RST_INVERTED >= 1'b0) && (IS_RST_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_RST_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_RST_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WRCLK_INVERTED >= 1'b0) && (IS_WRCLK_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WRCLK_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WRCLK_INVERTED);
finish_error = 1'b1;
end
if (!((IS_WREN_INVERTED >= 1'b0) && (IS_WREN_INVERTED <= 1'b1))) begin
$display("Attribute Syntax Error : The attribute IS_WREN_INVERTED on FIFO18E1 instance %m is set to %b. Legal values for this attribute are 1'b0 to 1'b1.", IS_WREN_INVERTED);
finish_error = 1'b1;
end
if (finish_error == 1)
#1 $finish;
end // initial begin
// Matching HW
localparam init_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,INIT[35:34],INIT[17:16],INIT[33:18],INIT[15:0]} : {36'h0, INIT};
localparam srval_sdp = (FIFO_MODE == "FIFO18_36") ? {36'h0,SRVAL[35:34],SRVAL[17:16],SRVAL[33:18],SRVAL[15:0]} : {36'h0, SRVAL};
FF18_INTERNAL_VLOG #(.ALMOST_EMPTY_OFFSET(ALMOST_EMPTY_OFFSET),
.ALMOST_FULL_OFFSET(ALMOST_FULL_OFFSET),
.DATA_WIDTH(DATA_WIDTH),
.DO_REG(DO_REG),
.EN_SYN(EN_SYN),
.FIFO_MODE(FIFO_MODE),
.FIFO_SIZE(18),
.FIRST_WORD_FALL_THROUGH(FIRST_WORD_FALL_THROUGH),
.INIT({36'h0,init_sdp}),
.SIM_DEVICE(SIM_DEVICE),
.SRVAL({36'h0,srval_sdp}))
INT_FIFO (.ALMOSTEMPTY(almostempty_wire),
.ALMOSTFULL(almostfull_wire),
.DBITERR(dangle_out),
.DI({32'b0,di_in}),
.DIP({4'b0,dip_in}),
.DO({dangle_out32,do_wire}),
.DOP({dangle_out4,dop_wire}),
.ECCPARITY(dangle_out8),
.EMPTY(empty_wire),
.FULL(full_wire),
.GSR(GSR),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDCLK(rdclk_in),
.RDCOUNT({dangle_out1,rdcount_wire}),
.RDEN(rden_in),
.RDERR(rderr_wire),
.REGCE(regce_in),
.RST(rst_in),
.RSTREG(rstreg_in),
.SBITERR(dangle_out1_2),
.WRCLK(wrclk_in),
.WRCOUNT({dangle_out1_1,wrcount_wire}),
.WREN(wren_in),
.WRERR(wrerr_wire));
reg ALMOSTEMPTY_out;
reg ALMOSTFULL_out;
reg [31:0] DO_out;
reg [3:0] DOP_out;
reg EMPTY_out;
reg FULL_out;
reg [11:0] RDCOUNT_out;
reg RDERR_out;
reg [11:0] WRCOUNT_out;
reg WRERR_out;
assign ALMOSTEMPTY = ALMOSTEMPTY_out;
assign ALMOSTFULL = ALMOSTFULL_out;
assign DO = DO_out;
assign DOP = DOP_out;
assign EMPTY = EMPTY_out;
assign FULL = FULL_out;
assign RDCOUNT = RDCOUNT_out;
assign RDERR = RDERR_out;
assign WRCOUNT = WRCOUNT_out;
assign WRERR = WRERR_out;
//*** Timing Checks Start here
//wrclk_in
always @(almostfull_wire or rst_in or GSR) ALMOSTFULL_out = almostfull_wire;
always @(full_wire or rst_in or GSR) FULL_out = full_wire;
always @(wrerr_wire or rst_in or GSR) WRERR_out = wrerr_wire;
always @(wrcount_wire or rst_in or GSR) WRCOUNT_out = wrcount_wire;
//rdclk_in
always @(almostempty_wire or rst_in or GSR) ALMOSTEMPTY_out = almostempty_wire;
always @(empty_wire or rst_in or GSR) EMPTY_out = empty_wire;
always @(rderr_wire or rst_in or GSR) RDERR_out = rderr_wire;
always @(rdcount_wire or rst_in or GSR) RDCOUNT_out = rdcount_wire;
always @(do_wire or rst_in or GSR) DO_out = do_wire;
always @(dop_wire or rst_in or GSR) DOP_out = dop_wire;
`ifdef XIL_TIMING
always @(notifier) begin
DO_out <= 32'bx;
DOP_out <= 4'bx;
end
always @(notifier_wrclk) begin
ALMOSTFULL_out <= 1'bx;
FULL_out <= 1'bx;
WRCOUNT_out <= 12'bx;
WRERR_out <= 1'bx;
end
always @(notifier_rdclk) begin
ALMOSTEMPTY_out <= 1'bx;
EMPTY_out <= 1'bx;
RDCOUNT_out <= 12'bx;
RDERR_out <= 1'bx;
end
wire rdclk_en_n;
wire rdclk_en_p;
wire wrclk_en_n;
wire wrclk_en_p;
assign rdclk_en_n = IS_RDCLK_INVERTED_REG;
assign rdclk_en_p = ~IS_RDCLK_INVERTED_REG;
assign wrclk_en_n = IS_WRCLK_INVERTED_REG;
assign wrclk_en_p = ~IS_WRCLK_INVERTED_REG;
wire nrst;
wire wren_enable;
not (nrst, RST);
and (wren_enable, WREN, nrst);
wire rst_rdclk_n = nrst && rdclk_en_n;
wire rst_rdclk_p = nrst && rdclk_en_p;
wire rst_wrclk_n = nrst && wrclk_en_n;
wire rst_wrclk_p = nrst && wrclk_en_p;
wire wren_enable_p = wren_enable && wrclk_en_p;
wire wren_enable_n = wren_enable && wrclk_en_n;
`endif // `ifdef XIL_TIMING
specify
(RDCLK *> DO) = (100:100:100, 100:100:100);
(RDCLK *> DOP) = (100:100:100, 100:100:100);
(RDCLK => ALMOSTEMPTY) = (100:100:100, 100:100:100);
(RDCLK => EMPTY) = (100:100:100, 100:100:100);
(RDCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(RDCLK => RDERR) = (100:100:100, 100:100:100);
(WRCLK => ALMOSTFULL) = (100:100:100, 100:100:100);
(WRCLK => FULL) = (100:100:100, 100:100:100);
(WRCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(WRCLK => WRERR) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(RST => ALMOSTEMPTY) = (0:0:0, 0:0:0);
(RST => ALMOSTFULL) = (0:0:0, 0:0:0);
(RST => EMPTY) = (0:0:0, 0:0:0);
(RST => FULL) = (0:0:0, 0:0:0);
(RST *> RDCOUNT) = (0:0:0, 0:0:0);
(RST => RDERR) = (0:0:0, 0:0:0);
(RST *> WRCOUNT) = (0:0:0, 0:0:0);
(RST => WRERR) = (0:0:0, 0:0:0);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_p, rst_rdclk_p, RDCLK_dly, RDEN_dly);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, REGCE_dly);
$setuphold (posedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RST_dly);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_p, rdclk_en_p, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0,,rst_rdclk_n, rst_rdclk_n, RDCLK_dly, RDEN_dly);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, negedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, REGCE_dly);
$setuphold (negedge RDCLK, posedge RST, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RST_dly);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0,,rdclk_en_n, rdclk_en_n, RDCLK_dly, RSTREG_dly);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_p, wrclk_en_p, WRCLK_dly, RST_dly);
$setuphold (posedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DIP_dly);
$setuphold (posedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_p, wren_enable_p, WRCLK_dly, DI_dly);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_p, rst_wrclk_p, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0,, wrclk_en_n, wrclk_en_n, WRCLK_dly, RST_dly);
$setuphold (negedge WRCLK, negedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, negedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, posedge DIP, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DIP_dly);
$setuphold (negedge WRCLK, posedge DI, 0:0:0, 0:0:0,, wren_enable_n, wren_enable_n, WRCLK_dly, DI_dly);
$setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly);
$setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0,, rst_wrclk_n, rst_wrclk_n, WRCLK_dly, WREN_dly);
$recrem (negedge RST, posedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_p, rdclk_en_p, RST_dly, RDCLK_dly);
$recrem (negedge RST, posedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_p, wrclk_en_p, RST_dly, WRCLK_dly);
$recrem (negedge RST, negedge RDCLK, 0:0:0, 0:0:0, notifier_rdclk, rdclk_en_n, rdclk_en_n, RST_dly, RDCLK_dly);
$recrem (negedge RST, negedge WRCLK, 0:0:0, 0:0:0, notifier_wrclk, wrclk_en_n, wrclk_en_n, RST_dly, WRCLK_dly);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
`endif // `ifdef XIL_TIMING
specparam PATHPULSE$ = 0;
endspecify
endmodule // FIFO18E1
// WARNING !!!: The following model is not an user primitive.
// Please do not modify any part of it. FIFO18E1 may not work properly if do so.
//
`timescale 1 ps/1 ps
module FF18_INTERNAL_VLOG (ALMOSTEMPTY, ALMOSTFULL, DBITERR, DO, DOP, ECCPARITY, EMPTY, FULL, RDCOUNT, RDERR, SBITERR, WRCOUNT, WRERR,
DI, DIP, GSR, INJECTDBITERR, INJECTSBITERR, RDCLK, RDEN, REGCE, RST, RSTREG, WRCLK, WREN);
output reg ALMOSTEMPTY;
output reg ALMOSTFULL;
output DBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
output reg EMPTY;
output reg FULL;
output reg [12:0] RDCOUNT;
output reg RDERR;
output SBITERR;
output reg [12:0] WRCOUNT;
output reg WRERR;
input [63:0] DI;
input [7:0] DIP;
input RDCLK;
input RDEN;
input REGCE;
input RST;
input RSTREG;
input WRCLK;
input WREN;
input GSR;
input INJECTDBITERR;
input INJECTSBITERR;
parameter integer DATA_WIDTH = 4;
parameter integer DO_REG = 1;
parameter EN_SYN = "FALSE";
parameter FIFO_MODE = "FIFO36";
parameter FIRST_WORD_FALL_THROUGH = "FALSE";
parameter ALMOST_EMPTY_OFFSET = 13'h0080;
parameter ALMOST_FULL_OFFSET = 13'h0080;
parameter EN_ECC_WRITE = "FALSE";
parameter EN_ECC_READ = "FALSE";
parameter INIT = 72'h0;
parameter SIM_DEVICE = "7SERIES";
parameter SRVAL = 72'h0;
reg [63:0] do_in = 64'b0;
reg [63:0] do_out = 64'b0;
reg [63:0] do_outreg = 64'b0;
reg [63:0] do_out_mux = 64'b0;
reg [7:0] dop_in = 8'b0, dop_out = 8'b0;
reg [7:0] dop_outreg = 8'b0, dop_out_mux = 8'b0;
reg dbiterr_out = 0, sbiterr_out = 0;
reg dbiterr_out_out = 0, sbiterr_out_out = 0;
reg [71:0] ecc_bit_position;
reg [7:0] eccparity_out = 8'b0;
reg [7:0] dopr_ecc, dop_buf = 8'b0, dip_ecc, dip_int;
reg [63:0] do_buf = 64'b0, di_in_ecc_corrected;
reg [7:0] syndrome, dip_in_ecc_corrected;
wire full_v3;
reg rden_reg, wren_reg;
reg fwft;
integer addr_limit, rd_prefetch = 0;
integer wr1_addr = 0;
integer viol_rst_rden = 0, viol_rst_wren = 0;
reg [3:0] rden_rdckreg = 4'b0, wren_wrckreg = 4'b0;
reg [12:0] rd_addr = 0;
reg [12:0] rdcount_out_out = 13'b0, wr_addr_out = 13'b0;
reg rd_flag = 0, rdcount_flag = 0, rdprefetch_flag = 0, wr_flag = 0;
reg wr1_flag = 0, awr_flag = 0;
reg [3:0] almostfull_int = 4'b0000, almostempty_int = 4'b1111;
reg [3:0] full_int = 4'b0000;
reg [3:0] empty_ram = 4'b1111;
reg [8:0] i, j;
reg rst_tmp1 = 0, rst_tmp2 = 0;
reg [4:0] rst_rdckreg = 5'b0, rst_wrckreg = 5'b0;
reg rst_rdclk_flag = 0, rst_wrclk_flag = 0;
reg en_ecc_write_int, en_ecc_read_int, finish_error = 0;
reg [63:0] di_ecc_col;
reg first_rst_flag = 0;
reg rm1wp1_eq = 1'b0, rm1w_eq = 1'b0;
reg awr_flag_sync_1 = 0, awr_flag_sync_2 = 0;
integer after_rst_rdclk = 0, after_rst_wrclk = 0;
integer count_freq_rdclk = 0, count_freq_wrclk = 0;
integer roundup_int_period_rdclk_wrclk=0, roundup_int_period_wrclk_rdclk=0;
integer s7_roundup_int_period_rdclk_wrclk=0;
time rise_rdclk=0, period_rdclk=0, rise_wrclk=0, period_wrclk=0;
integer fwft_prefetch_flag = 1;
real real_period_rdclk=0.0, real_period_wrclk=0.0;
reg rst_trans_rden_1 = 1'b0, rst_trans_rden_2 = 1'b0;
reg rst_trans_wren_1 = 1'b0, rst_trans_wren_2 = 1'b0;
reg after_rst_rden_flag = 1'b0, after_rst_wren_flag = 1'b0, after_rst_x_flag = 1'b0;
time time_wrclk = 0, time_rdclk = 0;
time prev_time_wrclk = 0, prev_time_rdclk = 0;
reg sync_clk_async_mode = 1'b0;
reg sync_clk_async_mode_done = 1'b0;
reg count_freq_wrclk_reset = 0;
// xilinx_internal_parameter on
// WARNING !!!: This model may not work properly if the following parameter is changed.
parameter integer FIFO_SIZE = 36;
// xilinx_internal_parameter off
localparam counter_width = (FIFO_SIZE == 36) ? ((DATA_WIDTH == 4) ? 12 :
(DATA_WIDTH == 9) ? 11 : (DATA_WIDTH == 18) ? 10 :
(DATA_WIDTH == 36) ? 9 : (DATA_WIDTH == 72) ? 8 : 12)
: ((DATA_WIDTH == 4) ? 11 : (DATA_WIDTH == 9) ? 10 :
(DATA_WIDTH == 18) ? 9 : (DATA_WIDTH == 36) ? 8 : 11);
reg [counter_width:0] rdcount_out = 13'b0, wr_addr = 13'b0;
reg [counter_width:0] ae_empty, ae_full;
reg [counter_width:0] rdcount_out_sync_3 = 13'h1fff, rdcount_out_sync_2 = 13'h1fff;
reg [counter_width:0] rdcount_out_sync_1 = 13'h1fff, rdcount_out_m1 = 13'h1fff;
reg [counter_width:0] wr_addr_sync_3 = 13'b0, wr_addr_sync_2 = 13'b0, wr_addr_sync_1 = 13'b0;
// Determinte memory size
localparam mem_size4 = (FIFO_SIZE == 18) ? 4095 : (FIFO_SIZE == 36) ? 8191 : 0;
localparam mem_size9 = (FIFO_SIZE == 18) ? 2047 : (FIFO_SIZE == 36) ? 4095 : 0;
localparam mem_size18 = (FIFO_SIZE == 18) ? 1023 : (FIFO_SIZE == 36) ? 2047 : 0;
localparam mem_size36 = (FIFO_SIZE == 18) ? 511 : (FIFO_SIZE == 36) ? 1023 : 0;
localparam mem_size72 = (FIFO_SIZE == 18) ? 0 : (FIFO_SIZE == 36) ? 511 : 0;
localparam mem_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam mem_width = (DATA_WIDTH == 4) ? 3 : (DATA_WIDTH == 9) ? 7 :
(DATA_WIDTH == 18) ? 15 : (DATA_WIDTH == 36) ? 31 : (DATA_WIDTH == 72) ? 63 : 0;
localparam memp_depth = (DATA_WIDTH == 4) ? mem_size4 : (DATA_WIDTH == 9) ? mem_size9 :
(DATA_WIDTH == 18) ? mem_size18 : (DATA_WIDTH == 36) ? mem_size36 :
(DATA_WIDTH == 72) ? mem_size72 : 0;
localparam memp_width = (DATA_WIDTH == 4 || DATA_WIDTH == 9) ? 1 :
(DATA_WIDTH == 18) ? 1 : (DATA_WIDTH == 36) ? 3 : (DATA_WIDTH == 72) ? 7 : 0;
reg [mem_width : 0] mem [mem_depth : 0];
reg [memp_width : 0] memp [memp_depth : 0];
reg sync;
// Input and output ports
assign SBITERR = sbiterr_out_out;
assign DBITERR = dbiterr_out_out;
assign ECCPARITY = eccparity_out;
initial begin
ALMOSTEMPTY = 1'b1;
ALMOSTFULL = 1'b0;
EMPTY = 1'b1;
FULL = 1'b0;
RDCOUNT = 13'h0;
RDERR = 1'b0;
WRCOUNT = 13'h0;
WRERR = 1'b0;
end
assign full_v3 = (rm1w_eq || (rm1wp1_eq && (WREN && !FULL))) ? 1 : 0;
initial begin
// Determine address limit
case (DATA_WIDTH)
4 : begin
if (FIFO_SIZE == 36)
addr_limit = 8192;
else
addr_limit = 4096;
end
9 : begin
if (FIFO_SIZE == 36)
addr_limit = 4096;
else
addr_limit = 2048;
end
18 : begin
if (FIFO_SIZE == 36)
addr_limit = 2048;
else
addr_limit = 1024;
end
36 : begin
if (FIFO_SIZE == 36)
addr_limit = 1024;
else
addr_limit = 512;
end
72 : begin
addr_limit = 512;
end
default :
begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on FIFO18E1 instance %m is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72.", DATA_WIDTH);
finish_error = 1;
end
endcase
case (EN_SYN)
"FALSE" : sync = 0;
"TRUE" : sync = 1;
default : begin
$display("Attribute Syntax Error : The attribute EN_SYN on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_SYN);
finish_error = 1;
end
endcase // case(EN_SYN)
case (FIRST_WORD_FALL_THROUGH)
"FALSE" : begin
fwft = 0;
if (EN_SYN == "FALSE") begin
ae_empty = ALMOST_EMPTY_OFFSET - 1;
ae_full = ALMOST_FULL_OFFSET;
end
else begin
ae_empty = ALMOST_EMPTY_OFFSET;
ae_full = ALMOST_FULL_OFFSET;
end
end
"TRUE" : begin
fwft = 1;
ae_empty = ALMOST_EMPTY_OFFSET - 2;
ae_full = ALMOST_FULL_OFFSET;
end
default : begin
$display("Attribute Syntax Error : The attribute FIRST_WORD_FALL_THROUGH on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", FIRST_WORD_FALL_THROUGH);
finish_error = 1;
end
endcase
// DRC for fwft in sync mode
if (fwft == 1'b1 && EN_SYN == "TRUE") begin
$display("DRC Error : First word fall through is not supported in synchronous mode on FIFO18E1 instance %m.");
finish_error = 1;
end
if (EN_SYN == "FALSE" && DO_REG == 0) begin
$display("DRC Error : DO_REG = 0 is invalid when EN_SYN is set to FALSE on FIFO18E1 instance %m.");
finish_error = 1;
end
case (EN_ECC_WRITE)
"TRUE" : en_ecc_write_int <= 1;
"FALSE" : en_ecc_write_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_WRITE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_WRITE);
finish_error = 1;
end
endcase
case (EN_ECC_READ)
"TRUE" : en_ecc_read_int <= 1;
"FALSE" : en_ecc_read_int <= 0;
default : begin
$display("Attribute Syntax Error : The attribute EN_ECC_READ on FIFO18E1 instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", EN_ECC_READ);
finish_error = 1;
end
endcase
if ((EN_ECC_READ == "TRUE" || EN_ECC_WRITE == "TRUE") && DATA_WIDTH != 72) begin
$display("DRC Error : The attribute DATA_WIDTH must be set to 72 when FIFO18E1 is configured in the ECC mode.");
finish_error = 1;
end
if (!(SIM_DEVICE == "VIRTEX6" || SIM_DEVICE == "7SERIES")) begin
$display("Attribute Syntax Error : The Attribute SIM_DEVICE on FIFO18E1 instance %m is set to %s. Legal values for this attribute are VIRTEX6, or 7SERIES.", SIM_DEVICE);
finish_error = 1;
end
if (finish_error == 1)
#1 $finish;
end // initial begin
// GSR and RST
always @(GSR)
if (GSR === 1'b1) begin
if (DO_REG == 1'b1 && sync == 1'b1) begin
assign do_out = INIT[0 +: mem_width+1];
assign dop_out = INIT[mem_width+1 +: memp_width+1];
assign do_outreg = INIT[0 +: mem_width+1];
assign dop_outreg = INIT[mem_width+1 +: memp_width+1];
assign do_in = INIT[0 +: mem_width+1];
assign dop_in = INIT[mem_width+1 +: memp_width+1];
assign do_buf = INIT[0 +: mem_width+1];
assign dop_buf = INIT[mem_width+1 +: memp_width+1];
end
else begin
assign do_out = 64'b0;
assign dop_out = 8'b0;
assign do_outreg = 64'b0;
assign dop_outreg = 8'b0;
assign do_in = 64'b0;
assign dop_in = 8'b0;
assign do_buf = 64'b0;
assign dop_buf = 8'b0;
end
end
else if (GSR === 1'b0) begin
deassign do_out;
deassign dop_out;
deassign do_outreg;
deassign dop_outreg;
deassign do_in;
deassign dop_in;
deassign do_buf;
deassign dop_buf;
end
always @(RST)
if (RST === 1'b1) begin
assign almostempty_int = 4'b1111;
ALMOSTEMPTY = 1'b1;
assign almostfull_int = 4'b0000;
ALMOSTFULL = 1'b0;
assign empty_ram = 4'b1111;
EMPTY = 1'b1;
assign full_int = 4'b0000;
FULL = 1'b0;
assign rdcount_out = 13'b0;
RDCOUNT = 13'b0;
WRCOUNT = 13'b0;
RDERR = 0;
WRERR = 0;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign wr_addr = 0;
assign wr1_addr = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'b1111111111111;
assign rdcount_out_m1 = 13'b1111111111111;
assign wr_addr_sync_3 = 13'b0;
end
else if (RST === 1'b0) begin
deassign almostempty_int;
// deassign ALMOSTEMPTY;
deassign almostfull_int;
// deassign ALMOSTFULL;
deassign empty_ram;
// deassign EMPTY;
deassign full_int;
// deassign FULL;
deassign rdcount_out;
// deassign RDCOUNT;
// deassign WRCOUNT;
// deassign RDERR;
// deassign WRERR;
deassign rd_addr;
deassign rd_prefetch;
deassign wr_addr;
deassign wr1_addr;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end
// DRC
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
always @(posedge RDCLK) begin
if (RST === 1'b1 && RDEN === 1'b1)
viol_rst_rden = 1;
if (RST === 1'b0)
rden_rdckreg[3:0] <= {rden_rdckreg[2:0], RDEN};
if (rden_rdckreg == 4'h0) begin
rst_rdckreg[0] <= RST;
rst_rdckreg[1] <= rst_rdckreg[0] & RST;
rst_rdckreg[2] <= rst_rdckreg[1] & RST;
end
end // always @ (posedge RDCLK)
always @(posedge WRCLK) begin
if (RST === 1'b1 && WREN === 1'b1)
viol_rst_wren = 1;
if (RST === 1'b0)
wren_wrckreg[3:0] <= {wren_wrckreg[2:0], WREN};
if (wren_wrckreg == 4'h0) begin
rst_wrckreg[0] <= RST;
rst_wrckreg[1] <= rst_wrckreg[0] & RST;
rst_wrckreg[2] <= rst_wrckreg[1] & RST;
end
end // always @ (posedge WRCLK)
always @(RST) begin
rst_tmp1 = RST;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three RDCLK clock cycles, and RDEN must be low for four clock cycles before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
#1 $finish;
end
if (((rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least three WRCLK clock cycles, and WREN must be low for four clock cycles before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
#1 $finish;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
FULL = 1'bX;
EMPTY = 1'bX;
RDERR = 1'bX;
WRERR = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
RDCOUNT = 13'bx;
WRCOUNT = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
ALMOSTEMPTY = 1'bx;
assign almostfull_int = 4'b0000;
ALMOSTFULL = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
end
else if (RST == 1'b0) begin
// deassign FULL;
// deassign EMPTY;
// deassign RDERR;
// deassign WRERR;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
// deassign RDCOUNT;
// deassign WRCOUNT;
deassign wr1_addr;
deassign almostempty_int;
// deassign ALMOSTEMPTY;
deassign almostfull_int;
// deassign ALMOSTFULL;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
end // if (RST == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rden_rdckreg = 4'h0;
wren_wrckreg = 4'h0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (RST)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge RST)
rst_trans_rden_1 = RST;
always @(negedge RST)
if (rst_trans_rden_1 == 1'b1)
rst_trans_rden_2 = ~RST;
always @(posedge RDCLK) begin
if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1) begin
after_rst_rdclk = after_rst_rdclk + 1;
if (RDEN === 1'b1 && after_rst_rdclk <= 2) begin
after_rst_rden_flag = 1'b1;
end
else if (after_rst_rdclk >= 3) begin
after_rst_rdclk = 0;
rst_trans_rden_1 = 1'b0;
rst_trans_rden_2 = 1'b0;
if (after_rst_rden_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RDEN must be low for at least two RDCLK clock cycles after RST deasserted.", $stime);
after_rst_rden_flag = 1'b0;
after_rst_x_flag = 1'b1;
#1 $finish;
end
end
end // if (rst_trans_rden_1 == 1'b1 && rst_trans_rden_2 == 1'b1)
end // always @ (posedge RDCLK)
always @(posedge RST)
rst_trans_wren_1 = RST;
always @(negedge RST)
if (rst_trans_wren_1 == 1'b1)
rst_trans_wren_2 = ~RST;
always @(posedge WRCLK) begin
if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1) begin
after_rst_wrclk = after_rst_wrclk + 1;
if (WREN === 1'b1 && after_rst_wrclk <= 2) begin
after_rst_wren_flag = 1'b1;
end
else if (after_rst_wrclk >= 3) begin
after_rst_wrclk = 0;
rst_trans_wren_1 = 1'b0;
rst_trans_wren_2 = 1'b0;
if (after_rst_wren_flag == 1'b1) begin
$display("DRC Error : Reset is unsuccessful at time %t. WREN must be low for at least two WRCLK clock cycles after RST deasserted.", $stime);
after_rst_wren_flag = 1'b0;
after_rst_x_flag = 1'b1;
#1 $finish;
end
end
end // if (rst_trans_wren_1 == 1'b1 && rst_trans_wren_2 == 1'b1)
end // always @ (posedge WRCLK)
always @(posedge after_rst_x_flag or negedge RST) begin
if (after_rst_x_flag == 1'b1) begin
FULL = 1'bX;
EMPTY = 1'bX;
RDERR = 1'bX;
WRERR = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
RDCOUNT = 13'bx;
WRCOUNT = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
ALMOSTEMPTY = 1'bx;
assign almostfull_int = 4'b0000;
ALMOSTFULL = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
after_rst_x_flag = 1'b0;
end
else if (RST == 1'b0) begin
// deassign FULL;
// deassign EMPTY;
// deassign RDERR;
// deassign WRERR;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
// deassign RDCOUNT;
// deassign WRCOUNT;
deassign wr1_addr;
deassign almostempty_int;
// deassign ALMOSTEMPTY;
deassign almostfull_int;
deassign ALMOSTFULL;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (RST == 1'b0)
end // always @ (posedge after_rst_x_flag or negedge RST)
always @(posedge RDCLK) begin
if (RST === 1'b1 && RDEN === 1'b1)
viol_rst_rden = 1;
if (RDEN === 1'b0 && RST === 1'b1) begin
rst_rdckreg[0] <= RST;
rst_rdckreg[1] <= rst_rdckreg[0] & RST;
rst_rdckreg[2] <= rst_rdckreg[1] & RST;
rst_rdckreg[3] <= rst_rdckreg[2] & RST;
rst_rdckreg[4] <= rst_rdckreg[3] & RST;
end
else if (RDEN === 1'b1 && RST === 1'b1) begin
rst_rdckreg <= 5'b0;
end
end // always @ (posedge RDCLK)
always @(posedge WRCLK) begin
if (RST === 1'b1 && WREN === 1'b1)
viol_rst_wren = 1;
if (WREN === 1'b0 && RST === 1'b1) begin
rst_wrckreg[0] <= RST;
rst_wrckreg[1] <= rst_wrckreg[0] & RST;
rst_wrckreg[2] <= rst_wrckreg[1] & RST;
rst_wrckreg[3] <= rst_wrckreg[2] & RST;
rst_wrckreg[4] <= rst_wrckreg[3] & RST;
end
else if (WREN === 1'b1 && RST === 1'b1) begin
rst_wrckreg <= 5'b0;
end
end // always @ (posedge WRCLK)
always @(RST) begin
rst_tmp1 = RST;
rst_rdclk_flag = 0;
rst_wrclk_flag = 0;
if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
if (((rst_rdckreg[4] & rst_rdckreg[3] & rst_rdckreg[2] & rst_rdckreg[1] & rst_rdckreg[0]) == 0) || viol_rst_rden == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five RDCLK clock cycles, and RDEN must be low before RST becomes active high, and RDEN remains low during this reset cycle.", $stime);
rst_rdclk_flag = 1;
#1 $finish;
end
if (((rst_wrckreg[4] & rst_wrckreg[3] & rst_wrckreg[2] & rst_wrckreg[1] & rst_wrckreg[0]) == 0) || viol_rst_wren == 1) begin
$display("DRC Error : Reset is unsuccessful at time %t. RST must be held high for at least five WRCLK clock cycles, and WREN must be low before RST becomes active high, and WREN remains low during this reset cycle.", $stime);
rst_wrclk_flag = 1;
#1 $finish;
end
if ((rst_rdclk_flag | rst_wrclk_flag) == 1) begin
FULL = 1'bX;
EMPTY = 1'bX;
RDERR = 1'bX;
WRERR = 1'bX;
assign eccparity_out = 8'bx;
assign rdcount_out = 13'bx;
RDCOUNT = 13'bx;
WRCOUNT = 13'bx;
assign wr_addr = 13'bx;
assign wr1_addr = 0;
assign almostempty_int = 4'b1111;
ALMOSTEMPTY = 1'bx;
assign almostfull_int = 4'b0000;
ALMOSTFULL = 1'bx;
assign empty_ram = 4'b1111;
assign full_int = 4'b0000;
assign rd_addr = 0;
assign rd_prefetch = 0;
assign rdcount_flag = 0;
assign rd_flag = 0;
assign rdprefetch_flag = 0;
assign wr_flag = 0;
assign wr1_flag = 0;
assign awr_flag = 0;
assign rdcount_out_sync_3 = 13'bx;
assign rdcount_out_m1 = 13'bx;
assign wr_addr_sync_3 = 13'bx;
end
else if (RST == 1'b0) begin
// deassign FULL;
// deassign EMPTY;
// deassign RDERR;
// deassign WRERR;
deassign eccparity_out;
deassign rdcount_out;
rdcount_out = 13'b0;
deassign wr_addr;
wr_addr = 13'b0;
// deassign RDCOUNT;
// deassign WRCOUNT;
deassign wr1_addr;
deassign almostempty_int;
// deassign ALMOSTEMPTY;
deassign almostfull_int;
// deassign ALMOSTFULL;
deassign empty_ram;
deassign full_int;
deassign rd_addr;
deassign rd_prefetch;
deassign rdcount_flag;
deassign rd_flag;
deassign rdprefetch_flag;
deassign wr_flag;
deassign wr1_flag;
deassign awr_flag;
deassign rdcount_out_sync_3;
deassign rdcount_out_m1;
deassign wr_addr_sync_3;
end // if (RST == 1'b0)
viol_rst_rden = 0;
viol_rst_wren = 0;
rst_rdckreg = 5'b0;
rst_wrckreg = 5'b0;
if (rst_rdclk_flag == 0 && rst_wrclk_flag == 0 && first_rst_flag == 0)
first_rst_flag = 1;
end // if (rst_tmp1 == 0 && rst_tmp2 == 1)
rst_tmp2 = rst_tmp1;
end // always @ (RST)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// DRC
always @(posedge RDEN or negedge GSR)
@(posedge RDCLK)
if (first_rst_flag == 0 && RDEN == 1'b1 && GSR == 1'b0) begin
$display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time);
#1 $finish;
end
always @(posedge WREN or negedge GSR)
@(posedge WRCLK)
if (first_rst_flag == 0 && WREN == 1'b1 && GSR == 1'b0) begin
$display("DRC Error : A RESET cycle must be observed before the first use of the FIFO instance %m which occurs at time %t.", $time);
#1 $finish;
end
always @(posedge RDCLK) begin
if (((period_rdclk == 0) && (count_freq_rdclk < 152)) ||
((count_freq_rdclk == 0) && (GSR == 1 || RST == 1)) ||
((count_freq_rdclk > 0) && (count_freq_rdclk < 152))) begin
count_freq_rdclk = count_freq_rdclk + 1;
end else if (count_freq_wrclk == 152) begin
count_freq_rdclk = 0;
count_freq_wrclk_reset = 1;
end
if (count_freq_rdclk == 150)
rise_rdclk = $time;
else if (count_freq_rdclk == 151)
period_rdclk = $time - rise_rdclk;
if (count_freq_rdclk >= 151 && count_freq_wrclk >= 151 && RST === 1'b0 && GSR === 1'b0) begin
// Setup ranges for almostempty
if (period_rdclk == period_wrclk) begin
if (EN_SYN == "FALSE") begin
if (SIM_DEVICE == "7SERIES") begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 6)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 6);
finish_error = 1;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
finish_error = 1;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 5);
finish_error = 1;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 7)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 7);
finish_error = 1;
end
end // else: !if(fwft == 1'b0)
end // if (SIM_DEVICE == "7SERIES")
else begin
if (fwft == 1'b0) begin
if ((ALMOST_EMPTY_OFFSET < 5) || (ALMOST_EMPTY_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 5, addr_limit - 5);
finish_error = 1;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
finish_error = 1;
end
end // if (fwft == 1'b0)
else begin
if ((ALMOST_EMPTY_OFFSET < 6) || (ALMOST_EMPTY_OFFSET > addr_limit - 4)) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 6, addr_limit - 4);
finish_error = 1;
end
if ((ALMOST_FULL_OFFSET < 4) || (ALMOST_FULL_OFFSET > addr_limit - 5)) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 4, addr_limit - 5);
finish_error = 1;
end
end // else: !if(fwft == 1'b0)
end // else: !if(SIM_DEVICE == "7SERIES")
end // if (EN_SYN == "FALSE")
else begin
if ((fwft == 1'b0) && ((ALMOST_EMPTY_OFFSET < 1) || (ALMOST_EMPTY_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_EMPTY_OFFSET, 1, addr_limit - 2);
finish_error = 1;
end
if ((fwft == 1'b0) && ((ALMOST_FULL_OFFSET < 1) || (ALMOST_FULL_OFFSET > addr_limit - 2))) begin
$display("Attribute Syntax Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. Legal values for this attribute are %d to %d", ALMOST_FULL_OFFSET, 1, addr_limit - 2);
finish_error = 1;
end
end // else: !if(EN_SYN == "FALSE")
end // if (period_rdclk == period_wrclk)
else begin
real_period_rdclk = period_rdclk * 1.0;
real_period_wrclk = period_wrclk * 1.0;
roundup_int_period_rdclk_wrclk = (real_period_rdclk / real_period_wrclk) + 0.499;
roundup_int_period_wrclk_rdclk = (real_period_wrclk / real_period_rdclk) + 0.499;
s7_roundup_int_period_rdclk_wrclk = (4.0 * (real_period_rdclk / real_period_wrclk)) + 0.499;
if (SIM_DEVICE == "7SERIES") begin
// $display ("addr_limit (%h) period_rdclk (%d) period_wrclk (%d) real_period_rdclk (%f) real_period_wrclk (%f) roundup_int_period_rdclk_wrclk (%d) roundup_int_period_wrclk_rdclk (%d) s7_roundup_int_period_rdclk_wrclk (%d) instance %m\n",addr_limit,period_rdclk,period_wrclk,real_period_rdclk,real_period_wrclk,roundup_int_period_rdclk_wrclk,roundup_int_period_wrclk_rdclk,s7_roundup_int_period_rdclk_wrclk);
if (ALMOST_FULL_OFFSET > (addr_limit - (s7_roundup_int_period_rdclk_wrclk + 6))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((roundup(4 * (WRCLK frequency / RDCLK frequency))) + 6)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
finish_error = 1;
end
end
else begin
if (ALMOST_FULL_OFFSET > (addr_limit - ((3 * roundup_int_period_wrclk_rdclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_FULL_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (RDCLK frequency / WRCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_FULL_OFFSET);
finish_error = 1;
end
if (ALMOST_EMPTY_OFFSET > (addr_limit - ((3 * roundup_int_period_rdclk_wrclk) + 3))) begin
$display("DRC Error : The attribute ALMOST_EMPTY_OFFSET on FIFO18E1 instance %m is set to %d. It must be set to a value smaller than (FIFO_DEPTH - ((3 * roundup (WRCLK frequency / RDCLK frequency)) + 3)) when FIFO18E1 has different frequencies for RDCLK and WRCLK.", ALMOST_EMPTY_OFFSET);
finish_error = 1;
end
end // else: !if(SIM_DEVICE == "7SERIES")
end // else: !if(period_rdclk == period_wrclk)
count_freq_rdclk = 0;
count_freq_wrclk_reset = 1;
if (finish_error == 1)
#100 $finish;
end // if (count_freq_wrclk >= 151 && count_freq_rdclk >= 151 && RST === 1'b0 && GSR === 1'b0)
end // always @ (posedge RDCLK)
always @(posedge WRCLK or posedge count_freq_wrclk_reset) begin
if (count_freq_wrclk_reset == 1) begin
count_freq_wrclk = 0;
count_freq_wrclk_reset = 0;
end else if (((period_wrclk == 0) && (count_freq_wrclk < 152)) ||
((count_freq_wrclk == 0) && (GSR == 1 || RST == 1)) ||
((count_freq_wrclk > 0) && (count_freq_wrclk < 152)))
count_freq_wrclk = count_freq_wrclk + 1;
if (count_freq_wrclk == 150)
rise_wrclk = $time;
else if (count_freq_wrclk == 151) begin
period_wrclk = $time - rise_wrclk;
end
end // always @ (posedge WRCLK)
generate
case (SIM_DEVICE)
"VIRTEX6" : begin
// read clock
always @(posedge RDCLK) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (RDEN == 1'b1) begin
if (EMPTY == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (EMPTY == 1'b0)
end // if (RDEN == 1'b1)
RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1);
if (WREN == 1'b1) begin
EMPTY = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
EMPTY = 1'b1;
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
ALMOSTEMPTY = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
ALMOSTFULL = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rden_reg = RDEN;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1);
ALMOSTEMPTY = almostempty_int[3];
if ((((rdcount_out + ae_empty) >= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) >= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[2] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync == 1'b0)
end // always @ (posedge RDCLK)
// Write clock
always @(posedge WRCLK) begin
// DRC
if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (WREN == 1'b1) begin
if (FULL == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8]
^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19]
^DI[21]^DI[23]^DI[25]^DI[26]^DI[28]
^DI[30]^DI[32]^DI[34]^DI[36]^DI[38]
^DI[40]^DI[42]^DI[44]^DI[46]^DI[48]
^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59]
^DI[61]^DI[63];
dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9]
^DI[10]^DI[12]^DI[13]^DI[16]^DI[17]
^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28]
^DI[31]^DI[32]^DI[35]^DI[36]^DI[39]
^DI[40]^DI[43]^DI[44]^DI[47]^DI[48]
^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59]
^DI[62]^DI[63];
dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[14]^DI[15]^DI[16]^DI[17]
^DI[22]^DI[23]^DI[24]^DI[25]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[45]^DI[46]^DI[47]^DI[48]
^DI[53]^DI[54]^DI[55]^DI[56]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[6] = DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = DIP; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (RST === 1'b0) begin
// injecting error
di_ecc_col = DI;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (INJECTDBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (INJECTSBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (FULL == 1'b0)
end // if (WREN == 1'b1)
if (RST === 1'b0) begin
WRERR = (WREN == 1'b1) && (FULL == 1'b1);
if (RDEN == 1'b1) begin
FULL = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
FULL = 1'b1;
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
ALMOSTEMPTY = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
ALMOSTFULL = 1'b1;
end
end // if (RST === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wren_reg = WREN;
if (wren_reg == 1'b1 && FULL == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8]
^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19]
^DI[21]^DI[23]^DI[25]^DI[26]^DI[28]
^DI[30]^DI[32]^DI[34]^DI[36]^DI[38]
^DI[40]^DI[42]^DI[44]^DI[46]^DI[48]
^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59]
^DI[61]^DI[63];
dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9]
^DI[10]^DI[12]^DI[13]^DI[16]^DI[17]
^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28]
^DI[31]^DI[32]^DI[35]^DI[36]^DI[39]
^DI[40]^DI[43]^DI[44]^DI[47]^DI[48]
^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59]
^DI[62]^DI[63];
dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[14]^DI[15]^DI[16]^DI[17]
^DI[22]^DI[23]^DI[24]^DI[25]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[45]^DI[46]^DI[47]^DI[48]
^DI[53]^DI[54]^DI[55]^DI[56]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[6] = DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = DIP; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (RST === 1'b0) begin
// injecting error
di_ecc_col = DI;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (INJECTDBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (INJECTSBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (RST === 1'b0)
end // if (wren_reg == 1'b1 && FULL == 1'b0)
if (RST === 1'b0) begin
WRERR = (wren_reg == 1'b1) && (FULL == 1'b1);
ALMOSTFULL = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) < wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) < (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || FULL == 1'b1)
FULL = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
end // if (RST === 1'b0)
end // if (sync == 1'b0)
end // always @ (posedge WRCLK)
end // case: "VIRTEX6"
"7SERIES" : begin
always @(posedge RDCLK) begin
if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin
prev_time_rdclk = time_rdclk;
time_rdclk = $time;
end
end
always @(posedge WRCLK) begin
if ((sync == 1'b0) && (sync_clk_async_mode_done == 1'b0)) begin
prev_time_wrclk = time_wrclk;
time_wrclk = $time;
end
end
always @(time_rdclk or time_wrclk) begin
if (((time_rdclk - time_wrclk == 0 && prev_time_rdclk - prev_time_wrclk == 0) || (time_wrclk - time_rdclk == 0 && prev_time_wrclk - prev_time_rdclk == 0)) && $time != 0)
sync_clk_async_mode = 1'b1;
if ((((period_wrclk > 0) && (period_rdclk > 0)) || (sync_clk_async_mode == 1'b1)) && (RST == 1'b0) && (GSR == 1'b0))
sync_clk_async_mode_done = 1'b1;
end
// read clock
always @(posedge RDCLK) begin
// SRVAL in output register mode
if (DO_REG == 1 && sync == 1'b1 && RSTREG === 1'b1) begin
do_outreg = SRVAL[0 +: mem_width+1];
if (mem_width+1 >= 8)
dop_outreg = SRVAL[mem_width+1 +: memp_width+1];
end
// sync mode
if (sync == 1'b1) begin
// output register
if (DO_REG == 1 && REGCE === 1'b1 && RSTREG === 1'b0) begin
do_outreg = do_out;
dop_outreg = dop_out;
dbiterr_out_out = dbiterr_out; // reg out in sync mode
sbiterr_out_out = sbiterr_out;
end
if (RDEN == 1'b1) begin
if (EMPTY == 1'b0) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
// checking error
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0; // latch out in sync mode
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
if (DO_REG == 0) begin
dbiterr_out_out = dbiterr_out;
sbiterr_out_out = sbiterr_out;
end
do_out = do_buf;
dop_out = dop_buf;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end // if (EMPTY == 1'b0)
end // if (RDEN == 1'b1)
RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1);
if (WREN == 1'b1) begin
EMPTY = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag == wr_flag)
EMPTY = 1'b1;
if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
ALMOSTEMPTY = 1'b1;
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == wr_flag)
ALMOSTFULL = 1'b0;
end
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
wr_addr_sync_3 = wr_addr_sync_2;
wr_addr_sync_2 = wr_addr_sync_1;
wr_addr_sync_1 = wr_addr;
awr_flag_sync_2 = awr_flag_sync_1;
awr_flag_sync_1 = awr_flag;
if (sync_clk_async_mode == 1'b1) begin
rden_reg = RDEN;
if (fwft == 1'b0) begin
if ((rden_reg == 1'b1) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((rden_reg == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr) && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (((rd_addr == rdcount_out) && (empty_ram[3] == 1'b0)) ||
((rden_reg == 1'b1) && (empty_ram[1] == 1'b0)) ||
((rden_reg == 1'b0) && (empty_ram[1] == 1'b0) && (rd_addr == rdcount_out))) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#1;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
RDERR = (rden_reg == 1'b1) && (EMPTY == 1'b1);
ALMOSTEMPTY = almostempty_int[3];
if ((((rdcount_out + ae_empty) > wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) > (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
almostempty_int[3] = 1'b1;
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
almostempty_int[0] = 1'b1;
end
else if (almostempty_int[1] == 1'b0) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != awr_flag) begin
almostempty_int[3] = almostempty_int[0];
almostempty_int[0] = 1'b0;
end
end
if ((((rdcount_out + addr_limit) > (wr_addr + ae_full)) && (rdcount_flag == awr_flag)) || ((rdcount_out > (wr_addr + ae_full)) && (rdcount_flag != awr_flag))) begin
if (((rden_reg == 1'b1) && (EMPTY == 1'b0)) || ((((rd_addr + 1) % addr_limit) == rdcount_out) && (almostfull_int[1] == 1'b1))) begin
almostfull_int[2] = almostfull_int[1];
almostfull_int[1] = 1'b0;
end
end
else begin
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
end
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end
if ((rdcount_out == wr_addr) && (rdcount_flag == awr_flag)) begin
empty_ram[2] = 1'b1;
empty_ram[1] = 1'b1;
empty_ram[0] = 1'b1;
end
else begin
empty_ram[2] = empty_ram[1];
empty_ram[1] = empty_ram[0];
empty_ram[0] = 1'b0;
end
if ((rdcount_out == wr1_addr) && (rdcount_flag == wr1_flag)) begin
empty_ram[3] = 1'b1;
end
else begin
empty_ram[3] = 1'b0;
end
wr1_addr = wr_addr;
wr1_flag = awr_flag;
end // if (sync_clk_async_mode == 1'b1)
else begin
if (fwft == 1'b0) begin
if (RDEN == 1'b1 && (rd_addr != rdcount_out)) begin
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0) begin
rdcount_flag = ~rdcount_flag;
end
end
end
// First word fall through = true
if (fwft == 1'b1) begin
if ((RDEN == 1'b1) && (rd_addr != rd_prefetch)) begin
rd_prefetch = (rd_prefetch + 1) % addr_limit;
if (rd_prefetch == 0)
rdprefetch_flag = ~rdprefetch_flag;
end
if ((rd_prefetch == rd_addr && rd_addr != rdcount_out) || (RST === 1'b1 && fwft_prefetch_flag == 1)) begin
fwft_prefetch_flag = 0;
do_out = do_in;
if (DATA_WIDTH != 4)
dop_out = dop_in;
rd_addr = (rd_addr + 1) % addr_limit;
if (rd_addr == 0)
rd_flag = ~rd_flag;
dbiterr_out_out = dbiterr_out; // reg out in async mode
sbiterr_out_out = sbiterr_out;
end
if (empty_ram[0] == 1'b0 && (RDEN == 1'b1 || rd_addr == rdcount_out)) begin
do_buf = mem[rdcount_out];
dop_buf = memp[rdcount_out];
// ECC decode
if (EN_ECC_READ == "TRUE") begin
// regenerate parity
dopr_ecc[0] = do_buf[0]^do_buf[1]^do_buf[3]^do_buf[4]^do_buf[6]^do_buf[8]
^do_buf[10]^do_buf[11]^do_buf[13]^do_buf[15]^do_buf[17]^do_buf[19]
^do_buf[21]^do_buf[23]^do_buf[25]^do_buf[26]^do_buf[28]
^do_buf[30]^do_buf[32]^do_buf[34]^do_buf[36]^do_buf[38]
^do_buf[40]^do_buf[42]^do_buf[44]^do_buf[46]^do_buf[48]
^do_buf[50]^do_buf[52]^do_buf[54]^do_buf[56]^do_buf[57]^do_buf[59]
^do_buf[61]^do_buf[63];
dopr_ecc[1] = do_buf[0]^do_buf[2]^do_buf[3]^do_buf[5]^do_buf[6]^do_buf[9]
^do_buf[10]^do_buf[12]^do_buf[13]^do_buf[16]^do_buf[17]
^do_buf[20]^do_buf[21]^do_buf[24]^do_buf[25]^do_buf[27]^do_buf[28]
^do_buf[31]^do_buf[32]^do_buf[35]^do_buf[36]^do_buf[39]
^do_buf[40]^do_buf[43]^do_buf[44]^do_buf[47]^do_buf[48]
^do_buf[51]^do_buf[52]^do_buf[55]^do_buf[56]^do_buf[58]^do_buf[59]
^do_buf[62]^do_buf[63];
dopr_ecc[2] = do_buf[1]^do_buf[2]^do_buf[3]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[14]^do_buf[15]^do_buf[16]^do_buf[17]
^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[37]^do_buf[38]^do_buf[39]
^do_buf[40]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[3] = do_buf[4]^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]
^do_buf[10]^do_buf[18]^do_buf[19]
^do_buf[20]^do_buf[21]^do_buf[22]^do_buf[23]^do_buf[24]^do_buf[25]
^do_buf[33]^do_buf[34]^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]
^do_buf[39]^do_buf[40]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[4] = do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[41]^do_buf[42]^do_buf[43]
^do_buf[44]^do_buf[45]^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]
^do_buf[50]^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[5] = do_buf[26]^do_buf[27]^do_buf[28]^do_buf[29]
^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]^do_buf[35]
^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]
^do_buf[46]^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]
^do_buf[51]^do_buf[52]^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56];
dopr_ecc[6] = do_buf[57]^do_buf[58]^do_buf[59]
^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
dopr_ecc[7] = dop_buf[0]^dop_buf[1]^dop_buf[2]^dop_buf[3]^dop_buf[4]^dop_buf[5]
^dop_buf[6]^do_buf[0]^do_buf[1]^do_buf[2]^do_buf[3]^do_buf[4]
^do_buf[5]^do_buf[6]^do_buf[7]^do_buf[8]^do_buf[9]^do_buf[10]
^do_buf[11]^do_buf[12]^do_buf[13]^do_buf[14]^do_buf[15]^do_buf[16]
^do_buf[17]^do_buf[18]^do_buf[19]^do_buf[20]^do_buf[21]^do_buf[22]
^do_buf[23]^do_buf[24]^do_buf[25]^do_buf[26]^do_buf[27]^do_buf[28]
^do_buf[29]^do_buf[30]^do_buf[31]^do_buf[32]^do_buf[33]^do_buf[34]
^do_buf[35]^do_buf[36]^do_buf[37]^do_buf[38]^do_buf[39]^do_buf[40]
^do_buf[41]^do_buf[42]^do_buf[43]^do_buf[44]^do_buf[45]^do_buf[46]
^do_buf[47]^do_buf[48]^do_buf[49]^do_buf[50]^do_buf[51]^do_buf[52]
^do_buf[53]^do_buf[54]^do_buf[55]^do_buf[56]^do_buf[57]^do_buf[58]
^do_buf[59]^do_buf[60]^do_buf[61]^do_buf[62]^do_buf[63];
syndrome = dopr_ecc ^ dop_buf;
if (syndrome !== 0) begin
if (syndrome[7]) begin // dectect single bit error
ecc_bit_position = {do_buf[63:57], dop_buf[6], do_buf[56:26], dop_buf[5], do_buf[25:11], dop_buf[4], do_buf[10:4], dop_buf[3], do_buf[3:1], dop_buf[2], do_buf[0], dop_buf[1:0], dop_buf[7]};
if (syndrome[6:0] > 71) begin
$display ("DRC Error : Simulation halted due Corrupted DIP. To correct this problem, make sure that reliable data is fed to the DIP. The correct Parity must be generated by a Hamming code encoder or encoder in the Block RAM. The output from the model is unreliable if there are more than 2 bit errors. The model doesn't warn if there is sporadic input of more than 2 bit errors due to the limitation in Hamming code.");
#1 $finish;
end
ecc_bit_position[syndrome[6:0]] = ~ecc_bit_position[syndrome[6:0]]; // correct single bit error in the output
di_in_ecc_corrected = {ecc_bit_position[71:65], ecc_bit_position[63:33], ecc_bit_position[31:17], ecc_bit_position[15:9], ecc_bit_position[7:5], ecc_bit_position[3]}; // correct single bit error in the memory
do_buf = di_in_ecc_corrected;
dip_in_ecc_corrected = {ecc_bit_position[0], ecc_bit_position[64], ecc_bit_position[32], ecc_bit_position[16], ecc_bit_position[8], ecc_bit_position[4], ecc_bit_position[2:1]}; // correct single bit error in the parity memory
dop_buf = dip_in_ecc_corrected;
dbiterr_out = 0;
sbiterr_out = 1;
end
else if (!syndrome[7]) begin // double bit error
sbiterr_out = 0;
dbiterr_out = 1;
end
end // if (syndrome !== 0)
else begin
dbiterr_out = 0;
sbiterr_out = 0;
end // else: !if(syndrome !== 0)
end // if (EN_ECC_READ == "TRUE")
// end ecc decode
do_in = do_buf;
dop_in = dop_buf;
#0;
rdcount_out_m1 = rdcount_out;
rdcount_out = (rdcount_out + 1) % addr_limit;
if (rdcount_out == 0)
rdcount_flag = ~rdcount_flag;
end
end // if (fwft == 1'b1)
RDERR = (RDEN == 1'b1) && (EMPTY == 1'b1);
ALMOSTEMPTY = almostempty_int[0];
if (wr_addr_sync_3 - rdcount_out <= ae_empty)
almostempty_int[0] = 1'b1;
else
almostempty_int[0] = 1'b0;
if (fwft == 1'b0) begin
if ((rdcount_out == rd_addr) && (rdcount_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end // if (fwft == 1'b0)
else if (fwft == 1'b1) begin
if ((rd_prefetch == rd_addr) && (rdprefetch_flag == rd_flag)) begin
EMPTY = 1'b1;
end
else begin
EMPTY = 1'b0;
end
end
if ((rdcount_out == wr_addr_sync_2) && (rdcount_flag == awr_flag_sync_2)) begin
empty_ram[0] = 1'b1;
end
else begin
empty_ram[0] = 1'b0;
end
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge RDCLK)
// Write clock
always @(posedge WRCLK) begin
// DRC
if ((INJECTSBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTSBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
if ((INJECTDBITERR === 1) && !(en_ecc_write_int == 1 || en_ecc_read_int == 1))
$display("DRC Warning : INJECTDBITERR is not supported when neither EN_ECC_WRITE nor EN_ECCREAD = TRUE on FIFO18E1 instance %m.");
// sync mode
if (sync == 1'b1) begin
if (WREN == 1'b1) begin
if (FULL == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8]
^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19]
^DI[21]^DI[23]^DI[25]^DI[26]^DI[28]
^DI[30]^DI[32]^DI[34]^DI[36]^DI[38]
^DI[40]^DI[42]^DI[44]^DI[46]^DI[48]
^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59]
^DI[61]^DI[63];
dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9]
^DI[10]^DI[12]^DI[13]^DI[16]^DI[17]
^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28]
^DI[31]^DI[32]^DI[35]^DI[36]^DI[39]
^DI[40]^DI[43]^DI[44]^DI[47]^DI[48]
^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59]
^DI[62]^DI[63];
dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[14]^DI[15]^DI[16]^DI[17]
^DI[22]^DI[23]^DI[24]^DI[25]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[45]^DI[46]^DI[47]^DI[48]
^DI[53]^DI[54]^DI[55]^DI[56]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[6] = DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = DIP; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (RST === 1'b0) begin
// injecting error
di_ecc_col = DI;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (INJECTDBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (INJECTSBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
wr_flag = ~wr_flag;
end
end // if (FULL == 1'b0)
end // if (WREN == 1'b1)
if (RST === 1'b0) begin
WRERR = (WREN == 1'b1) && (FULL == 1'b1);
if (RDEN == 1'b1) begin
FULL = 1'b0;
end
else if (rdcount_out == wr_addr && rdcount_flag != wr_flag)
FULL = 1'b1;
if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == wr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit) && (rdcount_flag != wr_flag)))) begin
if (rdcount_out <= rdcount_out + ae_empty || rdcount_flag != wr_flag)
ALMOSTEMPTY = 1'b0;
end
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full)) && (rdcount_flag == wr_flag)) || ((rdcount_out <= (wr_addr + ae_full)) && (rdcount_flag != wr_flag))) begin
ALMOSTFULL = 1'b1;
end
end // if (RST === 1'b0)
end // if (sync == 1'b1)
// async mode
else if (sync == 1'b0) begin
rdcount_out_sync_3 = rdcount_out_sync_2;
rdcount_out_sync_2 = rdcount_out_sync_1;
rdcount_out_sync_1 = rdcount_out_m1;
if (sync_clk_async_mode == 1'b1) begin
wren_reg = WREN;
if (wren_reg == 1'b1 && FULL == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8]
^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19]
^DI[21]^DI[23]^DI[25]^DI[26]^DI[28]
^DI[30]^DI[32]^DI[34]^DI[36]^DI[38]
^DI[40]^DI[42]^DI[44]^DI[46]^DI[48]
^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59]
^DI[61]^DI[63];
dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9]
^DI[10]^DI[12]^DI[13]^DI[16]^DI[17]
^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28]
^DI[31]^DI[32]^DI[35]^DI[36]^DI[39]
^DI[40]^DI[43]^DI[44]^DI[47]^DI[48]
^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59]
^DI[62]^DI[63];
dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[14]^DI[15]^DI[16]^DI[17]
^DI[22]^DI[23]^DI[24]^DI[25]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[45]^DI[46]^DI[47]^DI[48]
^DI[53]^DI[54]^DI[55]^DI[56]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[6] = DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = DIP; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (RST === 1'b0) begin
// injecting error
di_ecc_col = DI;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (INJECTDBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (INJECTSBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#1;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (RST === 1'b0)
end // if (wren_reg == 1'b1 && FULL == 1'b0)
if (RST === 1'b0) begin
WRERR = (wren_reg == 1'b1) && (FULL == 1'b1);
ALMOSTFULL = almostfull_int[3];
if ((((rdcount_out + addr_limit) <= (wr_addr + ae_full + 1)) && (rdcount_flag == awr_flag)) || ((rdcount_out <= (wr_addr + ae_full + 1)) && (rdcount_flag != awr_flag))) begin
almostfull_int[3] = 1'b1;
almostfull_int[2] = 1'b1;
almostfull_int[1] = 1'b1;
almostfull_int[0] = 1'b1;
end
else if (almostfull_int[2] == 1'b0) begin
if (wr_addr <= wr_addr + ae_full || rdcount_flag == awr_flag) begin
almostfull_int[3] = almostfull_int[0];
almostfull_int[0] = 1'b0;
end
end
if ((((rdcount_out + ae_empty) <= wr_addr) && (rdcount_flag == awr_flag)) || (((rdcount_out + ae_empty) <= (wr_addr + addr_limit)) && (rdcount_flag != awr_flag))) begin
if (wren_reg == 1'b1) begin
almostempty_int[2] = almostempty_int[1];
almostempty_int[1] = 1'b0;
end
end
else begin
almostempty_int[2] = 1'b1;
almostempty_int[1] = 1'b1;
end
if (wren_reg == 1'b1 || FULL == 1'b1)
FULL = full_int[1];
if (((rdcount_out == wr_addr) || (rdcount_out - 1 == wr_addr || (rdcount_out + addr_limit - 1 == wr_addr))) && ALMOSTFULL) begin
full_int[1] = 1'b1;
full_int[0] = 1'b1;
end
else begin
full_int[1] = full_int[0];
full_int[0] = 0;
end
// fix for 724006
if (rdcount_out - 1 == wr_addr && (wren_reg == 1'b1 || FULL == 1'b1))
FULL = full_int[1];
end // if (RST === 1'b0)
end // if (sync_clk_async_mode == 1'b1)
else begin
if (WREN == 1'b1 && FULL == 1'b0) begin
// ECC encode
if (EN_ECC_WRITE == "TRUE") begin
dip_ecc[0] = DI[0]^DI[1]^DI[3]^DI[4]^DI[6]^DI[8]
^DI[10]^DI[11]^DI[13]^DI[15]^DI[17]^DI[19]
^DI[21]^DI[23]^DI[25]^DI[26]^DI[28]
^DI[30]^DI[32]^DI[34]^DI[36]^DI[38]
^DI[40]^DI[42]^DI[44]^DI[46]^DI[48]
^DI[50]^DI[52]^DI[54]^DI[56]^DI[57]^DI[59]
^DI[61]^DI[63];
dip_ecc[1] = DI[0]^DI[2]^DI[3]^DI[5]^DI[6]^DI[9]
^DI[10]^DI[12]^DI[13]^DI[16]^DI[17]
^DI[20]^DI[21]^DI[24]^DI[25]^DI[27]^DI[28]
^DI[31]^DI[32]^DI[35]^DI[36]^DI[39]
^DI[40]^DI[43]^DI[44]^DI[47]^DI[48]
^DI[51]^DI[52]^DI[55]^DI[56]^DI[58]^DI[59]
^DI[62]^DI[63];
dip_ecc[2] = DI[1]^DI[2]^DI[3]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[14]^DI[15]^DI[16]^DI[17]
^DI[22]^DI[23]^DI[24]^DI[25]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[45]^DI[46]^DI[47]^DI[48]
^DI[53]^DI[54]^DI[55]^DI[56]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[3] = DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[4] = DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]
^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[5] = DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56];
dip_ecc[6] = DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
dip_ecc[7] = dip_ecc[0]^dip_ecc[1]^dip_ecc[2]^dip_ecc[3]^dip_ecc[4]^dip_ecc[5]^dip_ecc[6]
^DI[0]^DI[1]^DI[2]^DI[3]^DI[4]^DI[5]^DI[6]^DI[7]^DI[8]^DI[9]
^DI[10]^DI[11]^DI[12]^DI[13]^DI[14]^DI[15]^DI[16]^DI[17]^DI[18]^DI[19]
^DI[20]^DI[21]^DI[22]^DI[23]^DI[24]^DI[25]^DI[26]^DI[27]^DI[28]^DI[29]
^DI[30]^DI[31]^DI[32]^DI[33]^DI[34]^DI[35]^DI[36]^DI[37]^DI[38]^DI[39]
^DI[40]^DI[41]^DI[42]^DI[43]^DI[44]^DI[45]^DI[46]^DI[47]^DI[48]^DI[49]
^DI[50]^DI[51]^DI[52]^DI[53]^DI[54]^DI[55]^DI[56]^DI[57]^DI[58]^DI[59]
^DI[60]^DI[61]^DI[62]^DI[63];
eccparity_out = dip_ecc;
dip_int = dip_ecc; // only 64 bits width
end // if (EN_ECC_WRITE == "TRUE")
else begin
dip_int = DIP; // only 64 bits width
end // else: !if(EN_ECC_WRITE == "TRUE")
// end ecc encode
if (RST === 1'b0) begin
// injecting error
di_ecc_col = DI;
if (en_ecc_write_int == 1 || en_ecc_read_int == 1) begin
if (INJECTDBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
di_ecc_col[62] = ~di_ecc_col[62];
end
else if (INJECTSBITERR === 1) begin
di_ecc_col[30] = ~di_ecc_col[30];
end
end // if (en_ecc_write_int == 1 || en_ecc_read_int == 1)
mem[wr_addr] = di_ecc_col;
memp[wr_addr] = dip_int;
#0;
wr_addr = (wr_addr + 1) % addr_limit;
if (wr_addr == 0)
awr_flag = ~awr_flag;
if (wr_addr == addr_limit - 1)
wr_flag = ~wr_flag;
end // if (RST === 1'b0)
end // if (WREN == 1'b1 && FULL == 1'b0)
rm1w_eq = (rdcount_out_sync_2 == wr_addr) ? 1 : 0;
if (wr_addr + 1 == addr_limit) // wr_addr(FF) + 1 != 0
rm1wp1_eq = (rdcount_out_sync_2 == 0) ? 1 : 0;
else
rm1wp1_eq = (rdcount_out_sync_2 == wr_addr + 1) ? 1 : 0;
if (RST === 1'b0) begin
WRERR = (WREN == 1'b1) && (FULL == 1'b1);
ALMOSTFULL = almostfull_int[0];
if (rdcount_out_sync_3 - wr_addr <= ae_full)
almostfull_int[0] = 1'b1;
else
almostfull_int[0] = 1'b0;
FULL = full_v3;
//fwft prefetch
if (EMPTY == 1'b1 && WREN === 1'b1 && fwft_prefetch_flag == 0)
fwft_prefetch_flag = 1;
end // if (RST === 1'b0)
end // else: !if(sync_clk_async_mode == 1'b1)
end // if (sync == 1'b0)
end // always @ (posedge WRCLK)
end // case: "7SERIES"
endcase // case(SIM_DEVICE)
endgenerate
// output register
always @(do_out or dop_out or do_outreg or dop_outreg) begin
if (sync == 1)
case (DO_REG)
0 : begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end
1 : begin
do_out_mux = do_outreg;
dop_out_mux = dop_outreg;
end
default : begin
$display("Attribute Syntax Error : The attribute DO_REG on FIFO18E1 instance %m is set to %2d. Legal values for this attribute are 0 or 1.", DO_REG);
#1 $finish;
end
endcase
else begin
do_out_mux = do_out;
dop_out_mux = dop_out;
end // else: !if(sync == 1)
end // always @ (do_out or dop_out or do_outreg or dop_outreg)
// matching HW behavior to X the unused output bits
assign DO = (DATA_WIDTH == 4) ? {60'bx, do_out_mux[3:0]}
: (DATA_WIDTH == 9) ? {56'bx, do_out_mux[7:0]}
: (DATA_WIDTH == 18) ? {48'bx, do_out_mux[15:0]}
: (DATA_WIDTH == 36) ? {32'bx, do_out_mux[31:0]}
: (DATA_WIDTH == 72) ? do_out_mux
: do_out_mux;
// matching HW behavior to X the unused output bits
assign DOP = (DATA_WIDTH == 9) ? {7'bx, dop_out_mux[0:0]}
: (DATA_WIDTH == 18) ? {6'bx, dop_out_mux[1:0]}
: (DATA_WIDTH == 36) ? {4'bx, dop_out_mux[3:0]}
: (DATA_WIDTH == 72) ? dop_out_mux
: 8'bx;
// matching HW behavior to pull up the unused output bits
always @(wr_addr) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : WRCOUNT = {1'b1, wr_addr[counter_width:0]};
9 : WRCOUNT = {2'b11, wr_addr[counter_width:0]};
18 : WRCOUNT = {3'b111, wr_addr[counter_width:0]};
36 : WRCOUNT = {4'hf, wr_addr[counter_width:0]};
default : WRCOUNT = wr_addr;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : WRCOUNT = wr_addr;
9 : WRCOUNT = {1'b1, wr_addr[counter_width:0]};
18 : WRCOUNT = {2'b11, wr_addr[counter_width:0]};
36 : WRCOUNT = {3'b111, wr_addr[counter_width:0]};
72 : WRCOUNT = {4'hf, wr_addr[counter_width:0]};
default : WRCOUNT = wr_addr;
endcase // case(DATA_WIDTH)
end // always @ (wr_addr)
// matching HW behavior to pull up the unused output bits
always @(rdcount_out) begin
if (FIFO_SIZE == 18)
case (DATA_WIDTH)
4 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]};
9 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]};
18 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]};
36 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]};
default : RDCOUNT = rdcount_out;
endcase // case(DATA_WIDTH)
else
case (DATA_WIDTH)
4 : RDCOUNT = rdcount_out;
9 : RDCOUNT = {1'b1, rdcount_out[counter_width:0]};
18 : RDCOUNT = {2'b11, rdcount_out[counter_width:0]};
36 : RDCOUNT = {3'b111, rdcount_out[counter_width:0]};
72 : RDCOUNT = {4'hf, rdcount_out[counter_width:0]};
default : RDCOUNT = rdcount_out;
endcase // case(DATA_WIDTH)
end // always @ (rdcount_out)
endmodule
`endcelldefine
// end of FF18_INTERNAL_VLOG - Note: Not an user primitive
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_4_V
`define SKY130_FD_SC_HDLL__NAND4BB_4_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_4 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_4 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PG$N (
Q ,
D ,
GATE ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altpcie_hip_pipen1b_qsys
#(
parameter pcie_qsys = 1,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW = 32'h00000000,
parameter CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B0 = 32'h80000000,
parameter CB_P2A_AVALON_ADDR_B5 = 32'h00000000,
parameter CB_P2A_AVALON_ADDR_B6 = 32'h00000000,
parameter CG_NO_CPL_REORDERING = 0,
parameter enable_gen2_core = "true",
parameter use_crc_forwarding = "false",
parameter enable_function_msi_support = "true",
parameter flow_control_timeout_count = 200,
parameter CG_IMPL_CRA_AV_SLAVE_PORT = 1,
parameter CG_ENABLE_A2P_INTERRUPT = 0,
parameter vc0_clk_enable = "true",
parameter RH_NUM = 7,
parameter CB_P2A_AVALON_ADDR_B3 = 32'h00000000,
parameter INTENDED_DEVICE_FAMILY = "Stratix IV GX",
parameter RX_BUF = 10,
parameter l0_exit_latency_sameclock = 0,
parameter enable_hip_x1_loopback = "false",
parameter enable_ecrc_gen = "false",
parameter vc1_rx_flow_ctrl_posted_data = 360,
parameter l01_entry_latency = 31,
parameter msix_pba_bir = 0,
parameter vc1_rx_flow_ctrl_posted_header = 50,
parameter ei_delay_powerdown_count = 10,
parameter TL_SELECTION = 1,
parameter bar0_prefetchable = "true",
parameter bar4_size_mask = 0,
parameter enable_coreclk_out_half_rate = "false",
parameter maximum_current = 0,
parameter p_pcie_use_pcie_reconfig = "0",
parameter class_code = 16711680,
parameter bridge_port_vga_enable = "false",
parameter ssvid = 0,
parameter enable_adapter_half_rate_mode = "false",
parameter bar1_64bit_mem_space = "false",
parameter subsystem_vendor_id = 4466,
parameter sameclock_nfts_count = 0,
parameter msix_table_offset = 0,
parameter l0_exit_latency_diffclock = 0,
parameter eie_before_nfts_count = 4,
parameter CB_P2A_AVALON_ADDR_B4 = 32'h00000000,
parameter retry_buffer_memory_settings = 0,
parameter bar0_size_mask = 0,
parameter surprise_down_error_support = "false",
parameter vc0_rx_buffer_memory_settings = 0,
parameter credit_buffer_allocation_aux = "BALANCED",
parameter enable_rx0buf_ecc = "true",
parameter bar3_size_mask = 0,
parameter enable_rx_reordering = "true",
parameter bar4_io_space = "false",
parameter CG_COMMON_CLOCK_MODE = 0,
parameter extend_tag_field = "false",
parameter core_clk_divider = 0,
parameter G_TAG_NUM0 = 32,
parameter enable_retrybuf_x8_clk_stealing = 0,
parameter flow_control_update_count = 30,
parameter rx_ptr1_posted_dpram_max = 0,
parameter rx_ptr0_posted_dpram_min = 0,
parameter pme_state_enable = 5'b00000,
parameter port_link_number = 1,
parameter vc0_rx_flow_ctrl_posted_header = 50,
parameter ssid = 0,
parameter endpoint_l1_latency = 0,
parameter rx_ptr0_nonposted_dpram_min = 0,
parameter l1_exit_latency_diffclock = 0,
parameter retry_buffer_last_active_address = 2047,
parameter CB_P2A_AVALON_ADDR_B1 = 32'h00000000,
parameter bar_io_window_size = "32BIT",
parameter CB_A2P_ADDR_MAP_PASS_THRU_BITS = 20,
parameter rx_ptr1_posted_dpram_min = 0,
parameter CB_A2P_ADDR_MAP_IS_FIXED = 0,
parameter rx_ptr1_nonposted_dpram_max = 0,
parameter bar5_io_space = "false",
parameter gen2_sameclock_nfts_count = 255,
parameter max_payload_size = 512,
parameter gen2_diffclock_nfts_count = 255,
parameter vc_arbitration = 1,
parameter disable_snoop_packet = 8'b00000000,
parameter vc0_rx_flow_ctrl_posted_data = 360,
parameter AST_LITE = 0,
parameter CB_PCIE_RX_LITE = 0,
parameter CB_A2P_ADDR_MAP_NUM_ENTRIES = 2,
parameter vc1_rx_flow_ctrl_compl_data = 448,
parameter expansion_base_address_register = 0,
parameter msi_function_count = 4,
parameter vc0_rx_flow_ctrl_compl_data = 448,
parameter single_rx_detect = 0,
parameter CB_P2A_AVALON_ADDR_B2 = 32'h80000000,
parameter slot_number = 0,
parameter enable_rx_buffer_checking = "true",
parameter deemphasis_enable = "false",
parameter bar5_prefetchable = "false",
parameter device_number = 0,
parameter msix_pba_offset = 0,
parameter gen2_lane_rate_mode = "true",
parameter subsystem_device_id = 1,
parameter bypass_cdc = "false",
parameter tx_cdc_full_value = 12,
parameter bar_prefetchable = 32,
parameter enable_retrybuf_ecc = "true",
parameter fc_init_timer = 1024,
parameter base_address = 0,
parameter register_pipe_signals = "false",
parameter core_clk_source = "PLL_FIXED_CLK",
parameter no_command_completed = "true",
parameter msix_table_size = 0,
parameter bar3_prefetchable = "false",
parameter enable_msi_64bit_addressing = "true",
parameter port_address = 0,
parameter enable_rx1buf_x8_clk_stealing = 0,
parameter bar0_io_space = "false",
parameter vc1_rx_flow_ctrl_nonposted_header = 54,
parameter bar2_size_mask = 0,
parameter slot_power_limit = 0,
parameter enable_function_msix_support = "true",
parameter bar3_io_space = "false",
parameter bar0_64bit_mem_space = "true",
parameter millisecond_cycle_count = 0,
parameter enable_msi_masking = "false",
parameter endpoint_l0_latency = 0,
parameter bar4_prefetchable = "false",
parameter lpm_type = "stratixiv_hssi_pcie_hip",
parameter diffclock_nfts_count = 0,
parameter indicator = 0,
parameter bar1_io_space = "false",
parameter enable_l1_aspm = "false",
parameter vc1_rx_flow_ctrl_nonposted_data = 0,
parameter vc1_rx_flow_ctrl_compl_header = 112,
parameter low_priority_vc = 0,
parameter l1_exit_latency_sameclock = 0,
parameter bar1_size_mask = 0,
parameter vc0_rx_flow_ctrl_nonposted_header = 54,
parameter lane_mask = 8'hF0,
parameter bar2_io_space = "false",
parameter enable_ch0_pclk_out = "true",
parameter CB_A2P_ADDR_MAP_FIXED_TABLE = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000,
parameter enable_ecrc_check = "false",
parameter rx_ptr0_posted_dpram_max = 0,
parameter bar1_prefetchable = "false",
parameter p_pcie_hip_type = "0",
parameter bar2_64bit_mem_space = "false",
parameter vc0_rx_flow_ctrl_nonposted_data = 0,
parameter bar5_size_mask = 0,
parameter disable_link_x2_support = "false",
parameter bridge_port_ssid_support = "false",
parameter enable_rx0buf_x8_clk_stealing = 0,
parameter dll_active_report_support = "false",
parameter CB_PCIE_MODE = 0,
parameter vendor_id = 4466,
parameter msix_table_bir = 0,
parameter slot_power_scale = 0,
parameter device_address = 0,
parameter bar3_64bit_mem_space = "false",
parameter CG_AVALON_S_ADDR_WIDTH = 21,
parameter advanced_errors = "false",
parameter enable_rx1buf_ecc = "true",
parameter vc1_rx_buffer_memory_settings = 0,
parameter bypass_tl = "false",
parameter vc_enable = 7'b0000000,
parameter completion_timeout = "NONE",
parameter hot_plug_support = 7'b0000000,
parameter disable_cdc_clk_ppm = "false",
parameter no_soft_reset = "false",
parameter enable_slot_register = "false",
parameter rx_ptr0_nonposted_dpram_max = 0,
parameter bar5_64bit_mem_space = "false",
parameter vc0_rx_flow_ctrl_compl_header = 112,
parameter revision_id = 1,
parameter pcie_mode = "EP_NATIVE",
parameter max_link_width = 4,
parameter rx_ptr1_nonposted_dpram_min = 0,
parameter device_id = 1,
parameter bar4_64bit_mem_space = "false",
parameter enable_completion_timeout_disable = "false",
parameter skp_os_schedule_count = 0,
parameter vc1_clk_enable = "false",
parameter bar2_prefetchable = "false",
parameter RXM_DATA_WIDTH = 64,
parameter RXM_BEN_WIDTH = 8,
parameter RXM_BCNT_WIDTH = (pcie_qsys == 0) ? 10 : 7,
parameter TXS_BCNT_WIDTH = (pcie_qsys == 0) ? 10 : 7,
parameter CG_RXM_IRQ_NUM = 1,
parameter CG_IRQ_BIT_ENA = 65535
)
(
output CraIrq_o,
output [ 31: 0] CraReadData_o,
output CraWaitRequest_o,
// Avalon- RX Master
input [15:0] RxmIrq_i,
// Avalon Rx Master interface 0
output RxmWrite_0_o,
output [31:0] RxmAddress_0_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_0_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_0_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_0_o,
input RxmWaitRequest_0_i,
output RxmRead_0_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_0_i,
input RxmReadDataValid_0_i,
// Avalon Rx Master interface 1
output RxmWrite_1_o,
output [31:0] RxmAddress_1_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_1_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_1_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_1_o,
input RxmWaitRequest_1_i,
output RxmRead_1_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_1_i,
input RxmReadDataValid_1_i,
// Avalon Rx Master interface 2
output RxmWrite_2_o,
output [31:0] RxmAddress_2_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_2_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_2_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_2_o,
input RxmWaitRequest_2_i,
output RxmRead_2_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_2_i,
input RxmReadDataValid_2_i,
// Avalon Rx Master interface 3
output RxmWrite_3_o,
output [31:0] RxmAddress_3_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_3_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_3_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_3_o,
input RxmWaitRequest_3_i,
output RxmRead_3_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_3_i,
input RxmReadDataValid_3_i,
// Avalon Rx Master interface 4
output RxmWrite_4_o,
output [31:0] RxmAddress_4_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_4_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_4_o,
output [6:0] RxmBurstCount_4_o,
input RxmWaitRequest_4_i,
output RxmRead_4_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_4_i,
input RxmReadDataValid_4_i,
// Avalon Rx Master interface 5
output RxmWrite_5_o,
output [31:0] RxmAddress_5_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_5_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_5_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_5_o,
input RxmWaitRequest_5_i,
output RxmRead_5_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_5_i,
input RxmReadDataValid_5_i,
// Avalon Rx Master interface 6
output RxmWrite_6_o,
output [31:0] RxmAddress_6_o,
output [RXM_DATA_WIDTH-1:0] RxmWriteData_6_o,
output [(RXM_DATA_WIDTH/8)-1:0] RxmByteEnable_6_o,
output [RXM_BCNT_WIDTH-1:0] RxmBurstCount_6_o,
input RxmWaitRequest_6_i,
output RxmRead_6_o,
input [RXM_DATA_WIDTH-1:0] RxmReadData_6_i,
input RxmReadDataValid_6_i,
output TxsReadDataValid_o,
output [ 63: 0] TxsReadData_o,
output TxsWaitRequest_o,
output app_int_ack,
output app_msi_ack,
output [ 15: 0] avs_pcie_reconfig_readdata,
output avs_pcie_reconfig_readdatavalid,
output avs_pcie_reconfig_waitrequest,
output core_clk_out,
output derr_cor_ext_rcv0,
output derr_cor_ext_rcv1,
output derr_cor_ext_rpl,
output derr_rpl,
output [ 4: 0] dl_ltssm,
output dlup_exit,
output [ 23: 0] eidle_infer_sel,
output ev_128ns,
output ev_1us,
output [ 1: 0] hip_extraclkout,
output hotrst_exit,
output [ 3: 0] int_status,
output l2_exit,
output [ 3: 0] lane_act,
output lmi_ack,
output [ 31: 0] lmi_dout,
output npd_alloc_1cred_vc0,
output npd_alloc_1cred_vc1,
output npd_cred_vio_vc0,
output npd_cred_vio_vc1,
output nph_alloc_1cred_vc0,
output nph_alloc_1cred_vc1,
output nph_cred_vio_vc0,
output nph_cred_vio_vc1,
output pme_to_sr,
output [ 1: 0] powerdown0_ext,
output [ 1: 0] powerdown1_ext,
output [ 1: 0] powerdown2_ext,
output [ 1: 0] powerdown3_ext,
output [ 1: 0] powerdown4_ext,
output [ 1: 0] powerdown5_ext,
output [ 1: 0] powerdown6_ext,
output [ 1: 0] powerdown7_ext,
output r2c_err0,
output r2c_err1,
output rate_ext,
output rc_gxb_powerdown,
output rc_rx_analogreset,
output rc_rx_digitalreset,
output rc_tx_digitalreset,
output reset_status,
output rx_fifo_empty0,
output rx_fifo_empty1,
output rx_fifo_full0,
output rx_fifo_full1,
output [ 7: 0] rx_st_bardec0,
output [ 7: 0] rx_st_bardec1,
output [ 7: 0] rx_st_be0,
output [ 7: 0] rx_st_be0_p1,
output [ 7: 0] rx_st_be1,
output [ 7: 0] rx_st_be1_p1,
output [ 63: 0] rx_st_data0,
output [ 63: 0] rx_st_data0_p1,
output [ 63: 0] rx_st_data1,
output [ 63: 0] rx_st_data1_p1,
output rx_st_eop0,
output rx_st_eop0_p1,
output rx_st_eop1,
output rx_st_eop1_p1,
output rx_st_err0,
output rx_st_err1,
output rx_st_sop0,
output rx_st_sop0_p1,
output rx_st_sop1,
output rx_st_sop1_p1,
output rx_st_valid0,
output rx_st_valid1,
output rxpolarity0_ext,
output rxpolarity1_ext,
output rxpolarity2_ext,
output rxpolarity3_ext,
output rxpolarity4_ext,
output rxpolarity5_ext,
output rxpolarity6_ext,
output rxpolarity7_ext,
output serr_out,
output suc_spd_neg,
output swdn_wake,
output swup_hotrst,
output [ 63: 0] test_out,
output [ 3: 0] tl_cfg_add,
output [ 31: 0] tl_cfg_ctl,
output tl_cfg_ctl_wr,
output [ 52: 0] tl_cfg_sts,
output tl_cfg_sts_wr,
output [ 1: 0] tlbp_dl_ack_phypm,
output tlbp_dl_ack_requpfc,
output tlbp_dl_ack_sndupfc,
output tlbp_dl_current_deemp,
output [ 1: 0] tlbp_dl_currentspeed,
output tlbp_dl_dll_req,
output [ 4: 0] tlbp_dl_err_dll,
output tlbp_dl_errphy,
output tlbp_dl_link_autobdw_status,
output tlbp_dl_link_bdwmng_status,
output tlbp_dl_rpbuf_emp,
output tlbp_dl_rst_enter_comp_bit,
output tlbp_dl_rst_tx_margin_field,
output [ 2: 0] tlbp_dl_rx_typ_pm,
output tlbp_dl_rx_valpm,
output tlbp_dl_tx_ackpm,
output tlbp_dl_up,
output [ 7: 0] tlbp_dl_vc_status,
output tlbp_link_up,
output [ 35: 0] tx_cred0,
output [ 35: 0] tx_cred1,
output tx_deemph_0,
output tx_deemph_1,
output tx_deemph_2,
output tx_deemph_3,
output tx_deemph_4,
output tx_deemph_5,
output tx_deemph_6,
output tx_deemph_7,
output tx_fifo_empty0,
output tx_fifo_empty1,
output tx_fifo_full0,
output tx_fifo_full1,
output [ 3: 0] tx_fifo_rdptr0,
output [ 3: 0] tx_fifo_rdptr1,
output [ 3: 0] tx_fifo_wrptr0,
output [ 3: 0] tx_fifo_wrptr1,
output [ 2: 0] tx_margin_0,
output [ 2:0] tx_margin_1,
output [ 2:0] tx_margin_2,
output [ 2:0] tx_margin_3,
output [ 2:0] tx_margin_4,
output [ 2:0] tx_margin_5,
output [ 2:0] tx_margin_6,
output [ 2:0] tx_margin_7,
output tx_st_ready0,
output tx_st_ready1,
output txcompl0_ext,
output txcompl1_ext,
output txcompl2_ext,
output txcompl3_ext,
output txcompl4_ext,
output txcompl5_ext,
output txcompl6_ext,
output txcompl7_ext,
output [ 7: 0] txdata0_ext,
output [ 7: 0] txdata1_ext,
output [ 7: 0] txdata2_ext,
output [ 7: 0] txdata3_ext,
output [ 7: 0] txdata4_ext,
output [ 7: 0] txdata5_ext,
output [ 7: 0] txdata6_ext,
output [ 7: 0] txdata7_ext,
output txdatak0_ext,
output txdatak1_ext,
output txdatak2_ext,
output txdatak3_ext,
output txdatak4_ext,
output txdatak5_ext,
output txdatak6_ext,
output txdatak7_ext,
output txdetectrx0_ext,
output txdetectrx1_ext,
output txdetectrx2_ext,
output txdetectrx3_ext,
output txdetectrx4_ext,
output txdetectrx5_ext,
output txdetectrx6_ext,
output txdetectrx7_ext,
output txelecidle0_ext,
output txelecidle1_ext,
output txelecidle2_ext,
output txelecidle3_ext,
output txelecidle4_ext,
output txelecidle5_ext,
output txelecidle6_ext,
output txelecidle7_ext,
output use_pcie_reconfig,
output wake_oen,
input AvlClk_i,
input [ 11: 0] CraAddress_i,
input [ 3: 0] CraByteEnable_i,
input CraChipSelect_i,
input CraRead,
input CraWrite,
input [ 31: 0] CraWriteData_i,
input Rstn_i,
input [CG_AVALON_S_ADDR_WIDTH - 1: 0] TxsAddress_i,
input [ TXS_BCNT_WIDTH-1: 0] TxsBurstCount_i,
input [ 7: 0] TxsByteEnable_i,
input TxsChipSelect_i,
input TxsRead_i,
input [ 63: 0] TxsWriteData_i,
input TxsWrite_i,
input [ 4: 0] aer_msi_num,
input app_int_sts,
input [ 4: 0] app_msi_num,
input app_msi_req,
input [ 2: 0] app_msi_tc,
input [ 7: 0] avs_pcie_reconfig_address,
input avs_pcie_reconfig_chipselect,
input avs_pcie_reconfig_clk,
input avs_pcie_reconfig_read,
input avs_pcie_reconfig_rstn,
input avs_pcie_reconfig_write,
input [ 15: 0] avs_pcie_reconfig_writedata,
input core_clk_in,
input [ 6: 0] cpl_err,
input cpl_pending,
input crst,
input [ 14: 0] dbg_pipex1_rx,
input [ 4: 0] hpg_ctrler,
input [ 11: 0] lmi_addr,
input [ 31: 0] lmi_din,
input lmi_rden,
input lmi_wren,
input [ 1: 0] mode,
input npor,
input pclk_central,
input pclk_ch0,
input [ 4: 0] pex_msi_num,
input phystatus0_ext,
input phystatus1_ext,
input phystatus2_ext,
input phystatus3_ext,
input phystatus4_ext,
input phystatus5_ext,
input phystatus6_ext,
input phystatus7_ext,
input pld_clk,
input pll_fixed_clk,
input pm_auxpwr,
input [ 9: 0] pm_data,
input pm_event,
input pme_to_cr,
input rc_areset,
input rc_inclk_eq_125mhz,
input rc_pll_locked,
input rc_rx_pll_locked_one,
input rx_st_mask0,
input rx_st_mask1,
input rx_st_ready0,
input rx_st_ready1,
input [ 7: 0] rxdata0_ext,
input [ 7: 0] rxdata1_ext,
input [ 7: 0] rxdata2_ext,
input [ 7: 0] rxdata3_ext,
input [ 7: 0] rxdata4_ext,
input [ 7: 0] rxdata5_ext,
input [ 7: 0] rxdata6_ext,
input [ 7: 0] rxdata7_ext,
input rxdatak0_ext,
input rxdatak1_ext,
input rxdatak2_ext,
input rxdatak3_ext,
input rxdatak4_ext,
input rxdatak5_ext,
input rxdatak6_ext,
input rxdatak7_ext,
input rxelecidle0_ext,
input rxelecidle1_ext,
input rxelecidle2_ext,
input rxelecidle3_ext,
input rxelecidle4_ext,
input rxelecidle5_ext,
input rxelecidle6_ext,
input rxelecidle7_ext,
input [ 2: 0] rxstatus0_ext,
input [ 2: 0] rxstatus1_ext,
input [ 2: 0] rxstatus2_ext,
input [ 2: 0] rxstatus3_ext,
input [ 2: 0] rxstatus4_ext,
input [ 2: 0] rxstatus5_ext,
input [ 2: 0] rxstatus6_ext,
input [ 2: 0] rxstatus7_ext,
input rxvalid0_ext,
input rxvalid1_ext,
input rxvalid2_ext,
input rxvalid3_ext,
input rxvalid4_ext,
input rxvalid5_ext,
input rxvalid6_ext,
input rxvalid7_ext,
input srst,
input [ 2: 0] swdn_in,
input [ 6: 0] swup_in,
input [ 39: 0] test_in,
input tl_slotclk_cfg,
input tlbp_dl_aspm_cr0,
input tlbp_dl_comclk_reg,
input [ 12: 0] tlbp_dl_ctrl_link2,
input [ 11: 0] tlbp_dl_data_upfc,
input [ 7: 0] tlbp_dl_hdr_upfc,
input tlbp_dl_inh_dllp,
input [ 2: 0] tlbp_dl_maxpload_dcr,
input [ 3: 0] tlbp_dl_req_phycfg,
input [ 3: 0] tlbp_dl_req_phypm,
input tlbp_dl_req_upfc,
input tlbp_dl_req_wake,
input tlbp_dl_rx_ecrcchk,
input tlbp_dl_snd_upfc,
input tlbp_dl_tx_reqpm,
input [ 2: 0] tlbp_dl_tx_typpm,
input tlbp_dl_txcfg_extsy,
input [ 1: 0] tlbp_dl_typ_upfc,
input [ 7: 0] tlbp_dl_vc_ctrl,
input [ 23: 0] tlbp_dl_vcid_map,
input [ 2: 0] tlbp_dl_vcid_upfc,
input [ 63: 0] tx_st_data0,
input [ 63: 0] tx_st_data0_p1,
input [ 63: 0] tx_st_data1,
input [ 63: 0] tx_st_data1_p1,
input tx_st_eop0,
input tx_st_eop0_p1,
input tx_st_eop1,
input tx_st_eop1_p1,
input tx_st_err0,
input tx_st_err1,
input tx_st_sop0,
input tx_st_sop0_p1,
input tx_st_sop1,
input tx_st_sop1_p1,
input tx_st_valid0,
input tx_st_valid1
)
;
localparam CB_A2P_ADDR_MAP_FIXED_TABLE_INT = (pcie_qsys == 0) ? CB_A2P_ADDR_MAP_FIXED_TABLE :
{ CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW,
CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH,
CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW
};
localparam SOPC_BUILDER_MODE=((TL_SELECTION == 1)||(TL_SELECTION == 2)||(TL_SELECTION == 3)||(TL_SELECTION == 4)||(TL_SELECTION==5))?1:0;
wire [ 35: 0] tx_cred0_int;
wire [ 35: 0] tx_cred1_int;
wire [ 4: 0] aer_msi_num_int;
wire [ 4: 0] aer_msi_num_sopc;
wire app_int_sts_int;
wire app_int_sts_sopc;
wire app_msi_req_int;
wire app_msi_req_sopc;
wire [ 2: 0] app_msi_tc_int;
wire [ 2: 0] app_msi_tc_sopc;
wire avs_pcie_reconfig_rstn_int;
wire clrrxpath;
wire core_crst;
wire core_por;
wire core_rst;
wire core_srst;
wire cpl_pending_int;
wire cpl_pending_sopc;
wire [ 14: 0] dbgpipex1rx;
wire [ 1: 0] dlackphypm;
wire dlackrequpfc;
wire dlacksndupfc;
wire [ 12: 0] dlctrllink2;
wire dlcurrentdeemp;
wire [ 1: 0] dlcurrentspeed;
wire [ 11: 0] dldataupfc;
wire dldllreq;
wire [ 4: 0] dlerrdll;
wire dlerrphy;
wire [ 7: 0] dlhdrupfc;
wire dlinhdllp;
wire [ 3: 0] dlreqphycfg;
wire [ 3: 0] dlreqphypm;
wire dlrequpfc;
wire dlreqwake;
wire dlrpbufemp;
wire dlrxecrcchk;
wire [ 2: 0] dlrxtyppm;
wire dlrxvalpm;
wire dlsndupfc;
wire dltxackpm;
wire dltxcfgextsy;
wire dltxreqpm;
wire [ 2: 0] dltxtyppm;
wire [ 1: 0] dltypupfc;
wire dlup;
// wire dlup_exit;
wire [ 7: 0] dlvcctrl;
wire [ 23: 0] dlvcidmap;
wire [ 2: 0] dlvcidupfc;
wire [ 7: 0] dlvcstatus;
wire dpclk;
wire dpriodisable;
wire dprioin;
wire dprioload;
wire dprioout;
wire gen2rate;
wire gnd_bistenrcv0;
wire gnd_bistenrcv1;
wire gnd_bistenrpl;
wire gnd_bistscanen;
wire gnd_bistscanin;
wire gnd_bisttesten;
wire gnd_mram_hip_test_enable;
wire gnd_mramregscanen;
wire gnd_mramregscanin;
wire gnd_scanen;
wire [ 6: 0] hip_extraout;
wire in_l0s_req;
wire in_l1_rec;
wire linkup;
wire ltssml0state;
wire nowhere;
wire open_bistdonearcv0;
wire open_bistdonearcv1;
wire open_bistdonearpl;
wire open_bistdonebrcv0;
wire open_bistdonebrcv1;
wire open_bistdonebrpl;
wire open_bistpassrcv0;
wire open_bistpassrcv1;
wire open_bistpassrpl;
wire open_bistscanoutrcv0;
wire open_bistscanoutrcv1;
wire open_bistscanoutrpl;
wire open_dataenablen;
wire [ 2: 0] open_dpriostate;
wire open_gen2rategnd;
wire open_mramregscanout;
wire [ 3: 0] open_rxfifordpvc0;
wire [ 3: 0] open_rxfifordpvc1;
wire [ 3: 0] open_rxfifowrpvc0;
wire [ 3: 0] open_rxfifowrpvc1;
wire phy_rst;
wire phy_srst;
wire [ 7: 0] phystatus;
wire pld_rst;
wire pld_srst;
wire pm_event_int;
wire pm_event_sopc;
wire pme_to_cr_int;
wire pme_to_cr_sopc;
wire [ 15: 0] powerdown;
wire r2cerr0ext_cycloneiv;
wire rx_st_mask0_int;
wire rx_st_mask0_sopc;
wire rx_st_ready0_int;
wire rx_st_ready0_sopc;
wire [ 63: 0] rxdata;
wire [ 7: 0] rxdatak;
wire [ 7: 0] rxelecidle;
wire [ 7: 0] rxpolarity;
wire [ 23: 0] rxstatus;
wire [ 7: 0] rxvalid;
wire scanmoden;
wire [ 12: 0] sopc_dlctrllink2;
wire [ 11: 0] sopc_dldataupfc;
wire [ 7: 0] sopc_dlhdrupfc;
wire sopc_dlinhdllp;
wire [ 3: 0] sopc_dlreqphycfg;
wire [ 3: 0] sopc_dlreqphypm;
wire sopc_dlrequpfc;
wire sopc_dlreqwake;
wire sopc_dlrxecrcchk;
wire sopc_dlsndupfc;
wire sopc_dltxcfgextsy;
wire sopc_dltxreqpm;
wire [ 2: 0] sopc_dltxtyppm;
wire [ 1: 0] sopc_dltypupfc;
wire [ 23: 0] sopc_dlvcidmap;
wire [ 2: 0] sopc_dlvcidupfc;
wire sopc_mode;
wire srstn;
wire successspeednegoint;
wire swdn_hotrst;
wire [ 2: 0] swdn_in_int;
wire [ 2: 0] swdn_in_sopc;
wire [ 6: 0] swup_in_int;
wire [ 6: 0] swup_in_sopc;
wire [ 3: 0] tl_sel;
wire tlbp_clrrx_path;
wire [ 63: 0] tx_st_data0_int;
wire [ 63: 0] tx_st_data0_sopc;
wire [ 63: 0] tx_st_data1_int;
wire tx_st_eop0_int;
wire tx_st_eop0_sopc;
wire tx_st_err0_int;
wire tx_st_err0_sopc;
wire tx_st_sop0_int;
wire tx_st_sop0_sopc;
wire tx_st_sop1_int;
wire tx_st_valid0_int;
wire tx_st_valid0_sopc;
wire tx_st_valid1_int;
wire [ 7: 0] txcompl;
wire [ 63: 0] txdata;
wire [ 7: 0] txdatak;
wire [ 7: 0] txdetectrx;
wire [ 7: 0] txelecidle;
wire [39:0] test_in_sopc;
wire [7:0] tx_deemph;
wire [23:0] tx_margin;
wire [ 3: 0] tl_cfg_add_hip;
wire [ 31: 0] tl_cfg_ctl_hip;
wire tl_cfg_ctl_wr_hip;
wire [ 52: 0] tl_cfg_sts_hip;
wire tl_cfg_sts_wr_hip;
assign gnd_bistenrcv0 = 0;
assign gnd_bistenrcv1 = 0;
assign gnd_bistenrpl = 0;
assign gnd_bistscanen = 0;
assign gnd_bistscanin = 0;
assign gnd_bisttesten = 0;
assign test_in_sopc = {test_in[39:8], 1'b1, test_in[6:0]}; // turn on bit 7 for SOPC TLBP
assign dlctrllink2 = sopc_mode ? sopc_dlctrllink2 : tlbp_dl_ctrl_link2;
assign dldataupfc = sopc_mode ? sopc_dldataupfc : tlbp_dl_data_upfc;
assign dlhdrupfc = sopc_mode ? sopc_dlhdrupfc : tlbp_dl_hdr_upfc;
assign dlinhdllp = sopc_mode ? sopc_dlinhdllp : tlbp_dl_inh_dllp;
assign dlreqphycfg = sopc_mode ? sopc_dlreqphycfg : tlbp_dl_req_phycfg;
assign dlreqphypm = sopc_mode ? sopc_dlreqphypm : tlbp_dl_req_phypm;
assign dlrequpfc = sopc_mode ? sopc_dlrequpfc : tlbp_dl_req_upfc;
assign dlreqwake = sopc_mode ? sopc_dlreqwake : tlbp_dl_req_wake;
assign dlrxecrcchk = sopc_mode ? sopc_dlrxecrcchk : tlbp_dl_rx_ecrcchk;
assign dlsndupfc = sopc_mode ? sopc_dlsndupfc : tlbp_dl_snd_upfc;
assign dltxcfgextsy = sopc_mode ? sopc_dltxcfgextsy : tlbp_dl_txcfg_extsy;
assign dltypupfc = sopc_mode ? sopc_dltypupfc : tlbp_dl_typ_upfc;
assign dlvcctrl = sopc_mode ? 8'h1 : tlbp_dl_vc_ctrl;
assign dlvcidmap = sopc_mode ? sopc_dlvcidmap : tlbp_dl_vcid_map;
assign dltxreqpm = sopc_mode ? sopc_dltxreqpm : tlbp_dl_tx_reqpm;
assign dltxtyppm = sopc_mode ? sopc_dltxtyppm : tlbp_dl_tx_typpm;
assign gnd_mram_hip_test_enable = 0;
assign dlvcidupfc = sopc_mode ? sopc_dlvcidupfc : tlbp_dl_vcid_upfc;
assign gnd_mramregscanen = 0;
assign gnd_mramregscanin = 0;
assign gnd_scanen = 0;
assign pme_to_cr_int = sopc_mode ? pme_to_cr_sopc : pme_to_cr;
assign pm_event_int = sopc_mode ? pm_event_sopc : pm_event;
assign rx_st_mask0_int = sopc_mode ? rx_st_mask0_sopc : rx_st_mask0;
assign rx_st_ready0_int = sopc_mode ? rx_st_ready0_sopc : rx_st_ready0;
assign tx_st_valid0_int = sopc_mode ? tx_st_valid0_sopc : tx_st_valid0;
assign tx_st_valid1_int = tx_st_valid1;
assign tx_st_err0_int = sopc_mode ? tx_st_err0_sopc : tx_st_err0;
assign tx_st_sop0_int = sopc_mode ? tx_st_sop0_sopc : tx_st_sop0;
assign cpl_pending_int = sopc_mode ? cpl_pending_sopc : cpl_pending;
assign tx_st_sop1_int = tx_st_sop1;
assign tx_st_eop0_int = sopc_mode ? tx_st_eop0_sopc : tx_st_eop0;
assign tx_st_data0_int = sopc_mode ? tx_st_data0_sopc : tx_st_data0;
assign tx_st_data1_int = tx_st_data1;
assign swdn_in_int = sopc_mode ? swdn_in_sopc : swdn_in;
assign swup_in_int = sopc_mode ? swup_in_sopc : swup_in;
assign in_l0s_req = swup_in_sopc[6];
assign in_l1_rec = swup_in_sopc[5];
assign swdn_hotrst = swdn_in_sopc[0];
assign app_msi_tc_int = sopc_mode ? app_msi_tc_sopc : app_msi_tc;
assign aer_msi_num_int = sopc_mode ? aer_msi_num_sopc : aer_msi_num;
assign app_int_sts_int = sopc_mode ? app_int_sts_sopc : app_int_sts;
assign app_msi_req_int = sopc_mode ? app_msi_req_sopc : app_msi_req;
assign tlbp_clrrx_path = clrrxpath;
assign tlbp_dl_ack_phypm = dlackphypm;
assign tlbp_dl_ack_requpfc = dlackrequpfc;
assign tlbp_dl_ack_sndupfc = dlacksndupfc;
assign tlbp_dl_current_deemp = dlcurrentdeemp;
assign tlbp_dl_currentspeed = dlcurrentspeed;
assign tlbp_dl_dll_req = dldllreq;
assign tlbp_dl_err_dll = dlerrdll;
assign tlbp_dl_errphy = dlerrphy;
assign tlbp_dl_rpbuf_emp = dlrpbufemp;
assign tlbp_dl_rx_typ_pm = dlrxtyppm;
assign tlbp_dl_rx_valpm = dlrxvalpm;
assign tlbp_dl_tx_ackpm = dltxackpm;
assign tlbp_dl_up = dlup;
assign tlbp_dl_vc_status = dlvcstatus;
assign tlbp_link_up = linkup;
//Transcation layer mode
assign tl_sel = TL_SELECTION;
assign sopc_mode = (tl_sel == 4'h1) ? 1'b1: 1'b0;
assign srstn = ~srst;
assign rxdata[7 : 0] = rxdata0_ext;
assign rxdatak[0] = rxdatak0_ext;
assign phystatus[0] = phystatus0_ext;
assign rxelecidle[0] = rxelecidle0_ext;
assign rxvalid[0] = rxvalid0_ext;
assign txdata0_ext = txdata[7 : 0];
assign rxstatus[2 : 0] = rxstatus0_ext;
assign powerdown0_ext = powerdown[1 : 0];
assign rxpolarity0_ext = rxpolarity[0];
assign txcompl0_ext = txcompl[0];
assign txdatak0_ext = txdatak[0];
assign txdetectrx0_ext = txdetectrx[0];
assign txelecidle0_ext = txelecidle[0];
assign rxdata[15 : 8] = rxdata1_ext;
assign rxdatak[1] = rxdatak1_ext;
assign phystatus[1] = phystatus1_ext;
assign rxelecidle[1] = rxelecidle1_ext;
assign rxvalid[1] = rxvalid1_ext;
assign txdata1_ext = txdata[15 : 8];
assign rxstatus[5 : 3] = rxstatus1_ext;
assign powerdown1_ext = powerdown[3 : 2];
assign rxpolarity1_ext = rxpolarity[1];
assign txcompl1_ext = txcompl[1];
assign txdatak1_ext = txdatak[1];
assign txdetectrx1_ext = txdetectrx[1];
assign txelecidle1_ext = txelecidle[1];
assign rxdata[23 : 16] = rxdata2_ext;
assign rxdatak[2] = rxdatak2_ext;
assign phystatus[2] = phystatus2_ext;
assign rxelecidle[2] = rxelecidle2_ext;
assign rxvalid[2] = rxvalid2_ext;
assign txdata2_ext = txdata[23 : 16];
assign rxstatus[8 : 6] = rxstatus2_ext;
assign powerdown2_ext = powerdown[5 : 4];
assign rxpolarity2_ext = rxpolarity[2];
assign txcompl2_ext = txcompl[2];
assign txdatak2_ext = txdatak[2];
assign txdetectrx2_ext = txdetectrx[2];
assign txelecidle2_ext = txelecidle[2];
assign rxdata[31 : 24] = rxdata3_ext;
assign rxdatak[3] = rxdatak3_ext;
assign phystatus[3] = phystatus3_ext;
assign rxelecidle[3] = rxelecidle3_ext;
assign rxvalid[3] = rxvalid3_ext;
assign txdata3_ext = txdata[31 : 24];
assign rxstatus[11 : 9] = rxstatus3_ext;
assign powerdown3_ext = powerdown[7 : 6];
assign rxpolarity3_ext = rxpolarity[3];
assign txcompl3_ext = txcompl[3];
assign txdatak3_ext = txdatak[3];
assign txdetectrx3_ext = txdetectrx[3];
assign txelecidle3_ext = txelecidle[3];
assign rxdata[39 : 32] = rxdata4_ext;
assign rxdatak[4] = rxdatak4_ext;
assign phystatus[4] = phystatus4_ext;
assign rxelecidle[4] = rxelecidle4_ext;
assign rxvalid[4] = rxvalid4_ext;
assign txdata4_ext = txdata[39 : 32];
assign rxstatus[14 : 12] = rxstatus4_ext;
assign powerdown4_ext = powerdown[9 : 8];
assign rxpolarity4_ext = rxpolarity[4];
assign txcompl4_ext = txcompl[4];
assign txdatak4_ext = txdatak[4];
assign txdetectrx4_ext = txdetectrx[4];
assign txelecidle4_ext = txelecidle[4];
assign rxdata[47 : 40] = rxdata5_ext;
assign rxdatak[5] = rxdatak5_ext;
assign phystatus[5] = phystatus5_ext;
assign rxelecidle[5] = rxelecidle5_ext;
assign rxvalid[5] = rxvalid5_ext;
assign txdata5_ext = txdata[47 : 40];
assign rxstatus[17 : 15] = rxstatus5_ext;
assign powerdown5_ext = powerdown[11 : 10];
assign rxpolarity5_ext = rxpolarity[5];
assign txcompl5_ext = txcompl[5];
assign txdatak5_ext = txdatak[5];
assign txdetectrx5_ext = txdetectrx[5];
assign txelecidle5_ext = txelecidle[5];
assign rxdata[55 : 48] = rxdata6_ext;
assign rxdatak[6] = rxdatak6_ext;
assign phystatus[6] = phystatus6_ext;
assign rxelecidle[6] = rxelecidle6_ext;
assign rxvalid[6] = rxvalid6_ext;
assign txdata6_ext = txdata[55 : 48];
assign rxstatus[20 : 18] = rxstatus6_ext;
assign powerdown6_ext = powerdown[13 : 12];
assign rxpolarity6_ext = rxpolarity[6];
assign txcompl6_ext = txcompl[6];
assign txdatak6_ext = txdatak[6];
assign txdetectrx6_ext = txdetectrx[6];
assign txelecidle6_ext = txelecidle[6];
assign rxdata[63 : 56] = rxdata7_ext;
assign rxdatak[7] = rxdatak7_ext;
assign phystatus[7] = phystatus7_ext;
assign rxelecidle[7] = rxelecidle7_ext;
assign rxvalid[7] = rxvalid7_ext;
assign txdata7_ext = txdata[63 : 56];
assign rxstatus[23 : 21] = rxstatus7_ext;
assign powerdown7_ext = powerdown[15 : 14];
assign rxpolarity7_ext = rxpolarity[7];
assign txcompl7_ext = txcompl[7];
assign txdatak7_ext = txdatak[7];
assign txdetectrx7_ext = txdetectrx[7];
assign txelecidle7_ext = txelecidle[7];
//Instantiate PCIE Reconfig block
assign use_pcie_reconfig = p_pcie_use_pcie_reconfig;
assign avs_pcie_reconfig_rstn_int = (use_pcie_reconfig == 1) ? avs_pcie_reconfig_rstn : 1'b0;
//GND debug bus
assign dbgpipex1rx = (enable_hip_x1_loopback == "false") ? 15'h0 : dbg_pipex1_rx;
// for cycloneiv, remap r2c_err: spr 324831 & 388597
assign r2c_err0 = (p_pcie_hip_type == "2") ? r2cerr0ext_cycloneiv : hip_extraout[1];
assign r2c_err1 = hip_extraout[2];
// for cycloneiv, remap r2c_err: spr 324831 & 388597
assign suc_spd_neg = (p_pcie_hip_type == "2") ? successspeednegoint : hip_extraout[0];
assign core_srst = srst;
assign core_crst = crst;
assign core_por = ~npor;
assign core_rst = ~npor;
assign phy_rst = ~npor;
assign phy_srst = srst;
assign pld_rst = ~npor;
assign pld_srst = srst;
assign scanmoden = 1;
assign rate_ext = gen2rate;
assign tx_deemph_0 = tx_deemph[0];
assign tx_deemph_1 = tx_deemph[1];
assign tx_deemph_2 = tx_deemph[2];
assign tx_deemph_3 = tx_deemph[3];
assign tx_deemph_4 = tx_deemph[4];
assign tx_deemph_5 = tx_deemph[5];
assign tx_deemph_6 = tx_deemph[6];
assign tx_deemph_7 = tx_deemph[7];
assign tx_margin_0 = tx_margin[ 2: 0];
assign tx_margin_1 = tx_margin[ 5:3];
assign tx_margin_2 = tx_margin[ 8: 6];
assign tx_margin_3 = tx_margin[ 11: 9];
assign tx_margin_4 = tx_margin[ 14:12];
assign tx_margin_5 = tx_margin[ 17:15];
assign tx_margin_6 = tx_margin[ 20:18];
assign tx_margin_7 = tx_margin[ 23:21];
generate
if (p_pcie_hip_type == "0")
begin : stratix_iv
stratixiv_hssi_pcie_hip stratixiv_hssi_pcie_hip
(
.bistdonearcv0 (open_bistdonearcv0),
.bistdonearcv1 (open_bistdonearcv1),
.bistdonearpl (open_bistdonearpl),
.bistdonebrcv0 (open_bistdonebrcv0),
.bistdonebrcv1 (open_bistdonebrcv1),
.bistdonebrpl (open_bistdonebrpl),
.bistenrcv0 (gnd_bistenrcv0),
.bistenrcv1 (gnd_bistenrcv1),
.bistenrpl (gnd_bistenrpl),
.bistpassrcv0 (open_bistpassrcv0),
.bistpassrcv1 (open_bistpassrcv1),
.bistpassrpl (open_bistpassrpl),
.bistscanen (gnd_bistscanen),
.bistscanin (gnd_bistscanin),
.bistscanoutrcv0 (open_bistscanoutrcv0),
.bistscanoutrcv1 (open_bistscanoutrcv1),
.bistscanoutrpl (open_bistscanoutrpl),
.bisttesten (gnd_bisttesten),
.clrrxpath (clrrxpath),
.coreclkin (core_clk_in),
.coreclkout (core_clk_out),
.corecrst (core_crst),
.corepor (core_por),
.corerst (core_rst),
.coresrst (core_srst),
.cplerr (cpl_err),
.cplpending (cpl_pending_int),
.dataenablen (open_dataenablen),
.dbgpipex1rx (dbgpipex1rx),
.derrcorextrcv0 (derr_cor_ext_rcv0),
.derrcorextrcv1 (derr_cor_ext_rcv1),
.derrcorextrpl (derr_cor_ext_rpl),
.derrrpl (derr_rpl),
.dlackphypm (dlackphypm),
.dlackrequpfc (dlackrequpfc),
.dlacksndupfc (dlacksndupfc),
.dlaspmcr0 (tlbp_dl_aspm_cr0),
.dlcomclkreg (tlbp_dl_comclk_reg),
.dlctrllink2 (dlctrllink2),
.dlcurrentdeemp (dlcurrentdeemp),
.dlcurrentspeed (dlcurrentspeed),
.dldataupfc (dldataupfc),
.dldllreq (dldllreq),
.dlerrdll (dlerrdll),
.dlerrphy (dlerrphy),
.dlhdrupfc (dlhdrupfc),
.dlinhdllp (dlinhdllp),
.dllinkautobdwstatus (tlbp_dl_link_autobdw_status),
.dllinkbdwmngstatus (tlbp_dl_link_bdwmng_status),
.dlltssm (dl_ltssm),
.dlmaxploaddcr (tlbp_dl_maxpload_dcr),
.dlreqphycfg (dlreqphycfg),
.dlreqphypm (dlreqphypm),
.dlrequpfc (dlrequpfc),
.dlreqwake (dlreqwake),
.dlrpbufemp (dlrpbufemp),
.dlrstentercompbit (tlbp_dl_rst_enter_comp_bit),
.dlrsttxmarginfield (tlbp_dl_rst_tx_margin_field),
.dlrxecrcchk (dlrxecrcchk),
.dlrxtyppm (dlrxtyppm),
.dlrxvalpm (dlrxvalpm),
.dlsndupfc (dlsndupfc),
.dltxackpm (dltxackpm),
.dltxcfgextsy (dltxcfgextsy),
.dltxreqpm (dltxreqpm),
.dltxtyppm (dltxtyppm),
.dltypupfc (dltypupfc),
.dlup (dlup),
.dlupexit (dlup_exit),
.dlvcctrl (dlvcctrl),
.dlvcidmap (dlvcidmap),
.dlvcidupfc (dlvcidupfc),
.dlvcstatus (dlvcstatus),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout),
.dpriostate (open_dpriostate),
.eidleinfersel (eidle_infer_sel),
.ev128ns (ev_128ns),
.ev1us (ev_1us),
.extraclkout (hip_extraclkout),
.extraout (hip_extraout),
.gen2rate (gen2rate),
.gen2rategnd (open_gen2rategnd),
.hotrstexit (hotrst_exit),
.intstatus (int_status),
.l2exit (l2_exit),
.laneact (lane_act),
.linkup (linkup),
.lmiack (lmi_ack),
.lmiaddr (lmi_addr),
.lmidin (lmi_din),
.lmidout (lmi_dout),
.lmirden (lmi_rden),
.lmiwren (lmi_wren),
.ltssml0state (ltssml0state),
.mode (mode),
.mramhiptestenable (gnd_mram_hip_test_enable),
.mramregscanen (gnd_mramregscanen),
.mramregscanin (gnd_mramregscanin),
.mramregscanout (open_mramregscanout),
.pclkcentral (pclk_central),
.pclkch0 (pclk_ch0),
.phyrst (phy_rst),
.physrst (phy_srst),
.phystatus (phystatus),
.pldclk (pld_clk),
.pldrst (pld_rst),
.pldsrst (pld_srst),
.pllfixedclk (pll_fixed_clk),
.powerdown (powerdown),
.resetstatus (reset_status),
.rxbardecvc0 (rx_st_bardec0),
.rxbardecvc1 (rx_st_bardec1),
.rxbevc00 (rx_st_be0),
.rxbevc01 (rx_st_be0_p1),
.rxbevc10 (rx_st_be1),
.rxbevc11 (rx_st_be1_p1),
.rxdata (rxdata),
.rxdatak (rxdatak),
.rxdatavc00 (rx_st_data0),
.rxdatavc01 (rx_st_data0_p1),
.rxdatavc10 (rx_st_data1),
.rxdatavc11 (rx_st_data1_p1),
.rxelecidle (rxelecidle),
.rxeopvc00 (rx_st_eop0),
.rxeopvc01 (rx_st_eop0_p1),
.rxeopvc10 (rx_st_eop1),
.rxeopvc11 (rx_st_eop1_p1),
.rxerrvc0 (rx_st_err0),
.rxerrvc1 (rx_st_err1),
.rxfifoemptyvc0 (rx_fifo_empty0),
.rxfifoemptyvc1 (rx_fifo_empty1),
.rxfifofullvc0 (rx_fifo_full0),
.rxfifofullvc1 (rx_fifo_full1),
.rxfifordpvc0 (open_rxfifordpvc0),
.rxfifordpvc1 (open_rxfifordpvc1),
.rxfifowrpvc0 (open_rxfifowrpvc0),
.rxfifowrpvc1 (open_rxfifowrpvc1),
.rxmaskvc0 (rx_st_mask0_int),
.rxmaskvc1 (rx_st_mask1),
.rxpolarity (rxpolarity),
.rxreadyvc0 (rx_st_ready0_int),
.rxreadyvc1 (rx_st_ready1),
.rxsopvc00 (rx_st_sop0),
.rxsopvc01 (rx_st_sop0_p1),
.rxsopvc10 (rx_st_sop1),
.rxsopvc11 (rx_st_sop1_p1),
.rxstatus (rxstatus),
.rxvalid (rxvalid),
.rxvalidvc0 (rx_st_valid0),
.rxvalidvc1 (rx_st_valid1),
.scanen (gnd_scanen),
.scanmoden (scanmoden),
.serrout (serr_out),
.swdnin (swdn_in_int),
.swdnwake (swdn_wake),
.swuphotrst (swup_hotrst),
.swupin (swup_in_int),
.testin (test_in),
.testout (test_out),
.tlaermsinum (aer_msi_num_int),
.tlappintaack (app_int_ack),
.tlappintasts (app_int_sts_int),
.tlappmsiack (app_msi_ack),
.tlappmsinum (app_msi_num),
.tlappmsireq (app_msi_req_int),
.tlappmsitc (app_msi_tc_int),
.tlcfgadd (tl_cfg_add_hip),
.tlcfgctl (tl_cfg_ctl_hip),
.tlcfgctlwr (tl_cfg_ctl_wr_hip),
.tlcfgsts (tl_cfg_sts_hip),
.tlcfgstswr (tl_cfg_sts_wr_hip),
.tlhpgctrler (hpg_ctrler),
.tlpexmsinum (pex_msi_num),
.tlpmauxpwr (pm_auxpwr),
.tlpmdata (pm_data),
.tlpmetocr (pme_to_cr_int),
.tlpmetosr (pme_to_sr),
.tlpmevent (pm_event_int),
.tlslotclkcfg (tl_slotclk_cfg),
.txcompl (txcompl),
.txcredvc0 (tx_cred0_int),
.txcredvc1 (tx_cred1_int),
.txdata (txdata),
.txdatak (txdatak),
.txdatavc00 (tx_st_data0_int),
.txdatavc01 (tx_st_data0_p1),
.txdatavc10 (tx_st_data1),
.txdatavc11 (tx_st_data1_p1),
.txdeemph (tx_deemph),
.txdetectrx (txdetectrx),
.txelecidle (txelecidle),
.txeopvc00 (tx_st_eop0_int),
.txeopvc01 (tx_st_eop0_p1),
.txeopvc10 (tx_st_eop1),
.txeopvc11 (tx_st_eop1_p1),
.txerrvc0 (tx_st_err0_int),
.txerrvc1 (tx_st_err1),
.txfifoemptyvc0 (tx_fifo_empty0),
.txfifoemptyvc1 (tx_fifo_empty1),
.txfifofullvc0 (tx_fifo_full0),
.txfifofullvc1 (tx_fifo_full1),
.txfifordpvc0 (tx_fifo_rdptr0),
.txfifordpvc1 (tx_fifo_rdptr1),
.txfifowrpvc0 (tx_fifo_wrptr0),
.txfifowrpvc1 (tx_fifo_wrptr1),
.txmargin (tx_margin),
.txreadyvc0 (tx_st_ready0),
.txreadyvc1 (tx_st_ready1),
.txsopvc00 (tx_st_sop0_int),
.txsopvc01 (tx_st_sop0_p1),
.txsopvc10 (tx_st_sop1),
.txsopvc11 (tx_st_sop1_p1),
.txvalidvc0 (tx_st_valid0_int),
.txvalidvc1 (tx_st_valid1),
.wakeoen (wake_oen)
);
defparam stratixiv_hssi_pcie_hip.advanced_errors = advanced_errors,
stratixiv_hssi_pcie_hip.bar0_64bit_mem_space = bar0_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar0_io_space = bar0_io_space,
stratixiv_hssi_pcie_hip.bar0_prefetchable = bar0_prefetchable,
stratixiv_hssi_pcie_hip.bar0_size_mask = bar0_size_mask,
stratixiv_hssi_pcie_hip.bar1_64bit_mem_space = bar1_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar1_io_space = bar1_io_space,
stratixiv_hssi_pcie_hip.bar1_prefetchable = bar1_prefetchable,
stratixiv_hssi_pcie_hip.bar1_size_mask = bar1_size_mask,
stratixiv_hssi_pcie_hip.bar2_64bit_mem_space = bar2_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar2_io_space = bar2_io_space,
stratixiv_hssi_pcie_hip.bar2_prefetchable = bar2_prefetchable,
stratixiv_hssi_pcie_hip.bar2_size_mask = bar2_size_mask,
stratixiv_hssi_pcie_hip.bar3_64bit_mem_space = bar3_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar3_io_space = bar3_io_space,
stratixiv_hssi_pcie_hip.bar3_prefetchable = bar3_prefetchable,
stratixiv_hssi_pcie_hip.bar3_size_mask = bar3_size_mask,
stratixiv_hssi_pcie_hip.bar4_64bit_mem_space = bar4_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar4_io_space = bar4_io_space,
stratixiv_hssi_pcie_hip.bar4_prefetchable = bar4_prefetchable,
stratixiv_hssi_pcie_hip.bar4_size_mask = bar4_size_mask,
stratixiv_hssi_pcie_hip.bar5_64bit_mem_space = bar5_64bit_mem_space,
stratixiv_hssi_pcie_hip.bar5_io_space = bar5_io_space,
stratixiv_hssi_pcie_hip.bar5_prefetchable = bar5_prefetchable,
stratixiv_hssi_pcie_hip.bar5_size_mask = bar5_size_mask,
stratixiv_hssi_pcie_hip.bar_io_window_size = bar_io_window_size,
stratixiv_hssi_pcie_hip.bar_prefetchable = bar_prefetchable,
stratixiv_hssi_pcie_hip.bridge_port_ssid_support = bridge_port_ssid_support,
stratixiv_hssi_pcie_hip.bridge_port_vga_enable = bridge_port_vga_enable,
stratixiv_hssi_pcie_hip.bypass_cdc = bypass_cdc,
stratixiv_hssi_pcie_hip.tx_cdc_full_value = tx_cdc_full_value ,
stratixiv_hssi_pcie_hip.bypass_tl = bypass_tl,
stratixiv_hssi_pcie_hip.class_code = class_code,
stratixiv_hssi_pcie_hip.completion_timeout = completion_timeout,
stratixiv_hssi_pcie_hip.core_clk_divider = core_clk_divider,
stratixiv_hssi_pcie_hip.core_clk_source = core_clk_source,
stratixiv_hssi_pcie_hip.credit_buffer_allocation_aux = credit_buffer_allocation_aux,
stratixiv_hssi_pcie_hip.deemphasis_enable = deemphasis_enable,
stratixiv_hssi_pcie_hip.device_id = device_id,
stratixiv_hssi_pcie_hip.device_number = device_number,
stratixiv_hssi_pcie_hip.diffclock_nfts_count = diffclock_nfts_count,
stratixiv_hssi_pcie_hip.disable_cdc_clk_ppm = disable_cdc_clk_ppm,
stratixiv_hssi_pcie_hip.disable_link_x2_support = disable_link_x2_support,
stratixiv_hssi_pcie_hip.disable_snoop_packet = disable_snoop_packet,
stratixiv_hssi_pcie_hip.dll_active_report_support = dll_active_report_support,
stratixiv_hssi_pcie_hip.ei_delay_powerdown_count = ei_delay_powerdown_count,
stratixiv_hssi_pcie_hip.eie_before_nfts_count = eie_before_nfts_count,
stratixiv_hssi_pcie_hip.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode,
stratixiv_hssi_pcie_hip.enable_ch0_pclk_out = enable_ch0_pclk_out,
stratixiv_hssi_pcie_hip.enable_completion_timeout_disable = enable_completion_timeout_disable,
stratixiv_hssi_pcie_hip.enable_coreclk_out_half_rate = enable_coreclk_out_half_rate,
stratixiv_hssi_pcie_hip.enable_ecrc_check = enable_ecrc_check,
stratixiv_hssi_pcie_hip.enable_ecrc_gen = enable_ecrc_gen,
stratixiv_hssi_pcie_hip.enable_function_msi_support = enable_function_msi_support,
stratixiv_hssi_pcie_hip.enable_function_msix_support = enable_function_msix_support,
stratixiv_hssi_pcie_hip.enable_gen2_core = enable_gen2_core,
stratixiv_hssi_pcie_hip.enable_hip_x1_loopback = enable_hip_x1_loopback,
stratixiv_hssi_pcie_hip.enable_l1_aspm = enable_l1_aspm,
stratixiv_hssi_pcie_hip.enable_msi_64bit_addressing = enable_msi_64bit_addressing,
stratixiv_hssi_pcie_hip.enable_msi_masking = enable_msi_masking,
stratixiv_hssi_pcie_hip.enable_retrybuf_ecc = enable_retrybuf_ecc,
stratixiv_hssi_pcie_hip.enable_retrybuf_x8_clk_stealing = enable_retrybuf_x8_clk_stealing,
stratixiv_hssi_pcie_hip.enable_rx0buf_ecc = enable_rx0buf_ecc,
stratixiv_hssi_pcie_hip.enable_rx0buf_x8_clk_stealing = enable_rx0buf_x8_clk_stealing,
stratixiv_hssi_pcie_hip.enable_rx1buf_ecc = enable_rx1buf_ecc,
stratixiv_hssi_pcie_hip.enable_rx1buf_x8_clk_stealing = enable_rx1buf_x8_clk_stealing,
stratixiv_hssi_pcie_hip.enable_rx_buffer_checking = enable_rx_buffer_checking,
stratixiv_hssi_pcie_hip.enable_rx_reordering = enable_rx_reordering,
stratixiv_hssi_pcie_hip.enable_slot_register = enable_slot_register,
stratixiv_hssi_pcie_hip.endpoint_l0_latency = endpoint_l0_latency,
stratixiv_hssi_pcie_hip.endpoint_l1_latency = endpoint_l1_latency,
stratixiv_hssi_pcie_hip.expansion_base_address_register = expansion_base_address_register,
stratixiv_hssi_pcie_hip.extend_tag_field = extend_tag_field,
stratixiv_hssi_pcie_hip.fc_init_timer = fc_init_timer,
stratixiv_hssi_pcie_hip.flow_control_timeout_count = flow_control_timeout_count,
stratixiv_hssi_pcie_hip.flow_control_update_count = flow_control_update_count,
stratixiv_hssi_pcie_hip.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count,
stratixiv_hssi_pcie_hip.gen2_lane_rate_mode = gen2_lane_rate_mode,
stratixiv_hssi_pcie_hip.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count,
stratixiv_hssi_pcie_hip.hot_plug_support = hot_plug_support,
stratixiv_hssi_pcie_hip.indicator = indicator,
stratixiv_hssi_pcie_hip.l01_entry_latency = l01_entry_latency,
stratixiv_hssi_pcie_hip.l0_exit_latency_diffclock = l0_exit_latency_diffclock,
stratixiv_hssi_pcie_hip.l0_exit_latency_sameclock = l0_exit_latency_sameclock,
stratixiv_hssi_pcie_hip.l1_exit_latency_diffclock = l1_exit_latency_diffclock,
stratixiv_hssi_pcie_hip.l1_exit_latency_sameclock = l1_exit_latency_sameclock,
stratixiv_hssi_pcie_hip.lane_mask = lane_mask,
stratixiv_hssi_pcie_hip.low_priority_vc = low_priority_vc,
stratixiv_hssi_pcie_hip.lpm_type = lpm_type,
stratixiv_hssi_pcie_hip.max_link_width = max_link_width,
stratixiv_hssi_pcie_hip.max_payload_size = max_payload_size,
stratixiv_hssi_pcie_hip.maximum_current = maximum_current,
stratixiv_hssi_pcie_hip.millisecond_cycle_count = millisecond_cycle_count,
stratixiv_hssi_pcie_hip.msi_function_count = msi_function_count,
stratixiv_hssi_pcie_hip.msix_pba_bir = msix_pba_bir,
stratixiv_hssi_pcie_hip.msix_pba_offset = msix_pba_offset,
stratixiv_hssi_pcie_hip.msix_table_bir = msix_table_bir,
stratixiv_hssi_pcie_hip.msix_table_offset = msix_table_offset,
stratixiv_hssi_pcie_hip.msix_table_size = msix_table_size,
stratixiv_hssi_pcie_hip.no_command_completed = no_command_completed,
stratixiv_hssi_pcie_hip.no_soft_reset = no_soft_reset,
stratixiv_hssi_pcie_hip.pcie_mode = pcie_mode,
stratixiv_hssi_pcie_hip.pme_state_enable = pme_state_enable,
stratixiv_hssi_pcie_hip.port_link_number = port_link_number,
stratixiv_hssi_pcie_hip.register_pipe_signals = register_pipe_signals,
stratixiv_hssi_pcie_hip.retry_buffer_last_active_address = retry_buffer_last_active_address,
stratixiv_hssi_pcie_hip.retry_buffer_memory_settings = retry_buffer_memory_settings,
stratixiv_hssi_pcie_hip.revision_id = revision_id,
stratixiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max,
stratixiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min,
stratixiv_hssi_pcie_hip.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max,
stratixiv_hssi_pcie_hip.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min,
stratixiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_max = rx_ptr1_nonposted_dpram_max,
stratixiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_min = rx_ptr1_nonposted_dpram_min,
stratixiv_hssi_pcie_hip.rx_ptr1_posted_dpram_max = rx_ptr1_posted_dpram_max,
stratixiv_hssi_pcie_hip.rx_ptr1_posted_dpram_min = rx_ptr1_posted_dpram_min,
stratixiv_hssi_pcie_hip.sameclock_nfts_count = sameclock_nfts_count,
stratixiv_hssi_pcie_hip.single_rx_detect = single_rx_detect,
stratixiv_hssi_pcie_hip.skp_os_schedule_count = skp_os_schedule_count,
stratixiv_hssi_pcie_hip.slot_number = slot_number,
stratixiv_hssi_pcie_hip.slot_power_limit = slot_power_limit,
stratixiv_hssi_pcie_hip.slot_power_scale = slot_power_scale,
stratixiv_hssi_pcie_hip.ssid = ssid,
stratixiv_hssi_pcie_hip.ssvid = ssvid,
stratixiv_hssi_pcie_hip.subsystem_device_id = subsystem_device_id,
stratixiv_hssi_pcie_hip.subsystem_vendor_id = subsystem_vendor_id,
stratixiv_hssi_pcie_hip.surprise_down_error_support = surprise_down_error_support,
stratixiv_hssi_pcie_hip.use_crc_forwarding = use_crc_forwarding,
stratixiv_hssi_pcie_hip.vc0_clk_enable = vc0_clk_enable,
stratixiv_hssi_pcie_hip.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data,
stratixiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header,
stratixiv_hssi_pcie_hip.vc1_clk_enable = vc1_clk_enable,
stratixiv_hssi_pcie_hip.vc1_rx_buffer_memory_settings = vc1_rx_buffer_memory_settings,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_data = vc1_rx_flow_ctrl_compl_data,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_header = vc1_rx_flow_ctrl_compl_header,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_data = vc1_rx_flow_ctrl_nonposted_data,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_header = vc1_rx_flow_ctrl_nonposted_header,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_data = vc1_rx_flow_ctrl_posted_data,
stratixiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_header = vc1_rx_flow_ctrl_posted_header,
stratixiv_hssi_pcie_hip.vc_arbitration = vc_arbitration,
stratixiv_hssi_pcie_hip.vc_enable = vc_enable,
stratixiv_hssi_pcie_hip.vendor_id = vendor_id;
end
endgenerate
generate
if (p_pcie_hip_type == "4")
begin : arriaiigz
arriaiigz_hssi_pcie_hip arriaiigz_hssi_pcie_hip
(
.bistdonearcv0 (open_bistdonearcv0),
.bistdonearcv1 (open_bistdonearcv1),
.bistdonearpl (open_bistdonearpl),
.bistdonebrcv0 (open_bistdonebrcv0),
.bistdonebrcv1 (open_bistdonebrcv1),
.bistdonebrpl (open_bistdonebrpl),
.bistenrcv0 (gnd_bistenrcv0),
.bistenrcv1 (gnd_bistenrcv1),
.bistenrpl (gnd_bistenrpl),
.bistpassrcv0 (open_bistpassrcv0),
.bistpassrcv1 (open_bistpassrcv1),
.bistpassrpl (open_bistpassrpl),
.bistscanen (gnd_bistscanen),
.bistscanin (gnd_bistscanin),
.bistscanoutrcv0 (open_bistscanoutrcv0),
.bistscanoutrcv1 (open_bistscanoutrcv1),
.bistscanoutrpl (open_bistscanoutrpl),
.bisttesten (gnd_bisttesten),
.clrrxpath (clrrxpath),
.coreclkin (core_clk_in),
.coreclkout (core_clk_out),
.corecrst (core_crst),
.corepor (core_por),
.corerst (core_rst),
.coresrst (core_srst),
.cplerr (cpl_err),
.cplpending (cpl_pending_int),
.dataenablen (open_dataenablen),
.dbgpipex1rx (dbgpipex1rx),
.derrcorextrcv0 (derr_cor_ext_rcv0),
.derrcorextrcv1 (derr_cor_ext_rcv1),
.derrcorextrpl (derr_cor_ext_rpl),
.derrrpl (derr_rpl),
.dlackphypm (dlackphypm),
.dlackrequpfc (dlackrequpfc),
.dlacksndupfc (dlacksndupfc),
.dlaspmcr0 (tlbp_dl_aspm_cr0),
.dlcomclkreg (tlbp_dl_comclk_reg),
.dlctrllink2 (dlctrllink2),
.dlcurrentdeemp (dlcurrentdeemp),
.dlcurrentspeed (dlcurrentspeed),
.dldataupfc (dldataupfc),
.dldllreq (dldllreq),
.dlerrdll (dlerrdll),
.dlerrphy (dlerrphy),
.dlhdrupfc (dlhdrupfc),
.dlinhdllp (dlinhdllp),
.dllinkautobdwstatus (tlbp_dl_link_autobdw_status),
.dllinkbdwmngstatus (tlbp_dl_link_bdwmng_status),
.dlltssm (dl_ltssm),
.dlmaxploaddcr (tlbp_dl_maxpload_dcr),
.dlreqphycfg (dlreqphycfg),
.dlreqphypm (dlreqphypm),
.dlrequpfc (dlrequpfc),
.dlreqwake (dlreqwake),
.dlrpbufemp (dlrpbufemp),
.dlrstentercompbit (tlbp_dl_rst_enter_comp_bit),
.dlrsttxmarginfield (tlbp_dl_rst_tx_margin_field),
.dlrxecrcchk (dlrxecrcchk),
.dlrxtyppm (dlrxtyppm),
.dlrxvalpm (dlrxvalpm),
.dlsndupfc (dlsndupfc),
.dltxackpm (dltxackpm),
.dltxcfgextsy (dltxcfgextsy),
.dltxreqpm (dltxreqpm),
.dltxtyppm (dltxtyppm),
.dltypupfc (dltypupfc),
.dlup (dlup),
.dlupexit (dlup_exit),
.dlvcctrl (dlvcctrl),
.dlvcidmap (dlvcidmap),
.dlvcidupfc (dlvcidupfc),
.dlvcstatus (dlvcstatus),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout),
.dpriostate (open_dpriostate),
.eidleinfersel (eidle_infer_sel),
.ev128ns (ev_128ns),
.ev1us (ev_1us),
.extraclkout (hip_extraclkout),
.extraout (hip_extraout),
.gen2rate (gen2rate),
.gen2rategnd (open_gen2rategnd),
.hotrstexit (hotrst_exit),
.intstatus (int_status),
.l2exit (l2_exit),
.laneact (lane_act),
.linkup (linkup),
.lmiack (lmi_ack),
.lmiaddr (lmi_addr),
.lmidin (lmi_din),
.lmidout (lmi_dout),
.lmirden (lmi_rden),
.lmiwren (lmi_wren),
.ltssml0state (ltssml0state),
.mode (mode),
.mramhiptestenable (gnd_mram_hip_test_enable),
.mramregscanen (gnd_mramregscanen),
.mramregscanin (gnd_mramregscanin),
.mramregscanout (open_mramregscanout),
.pclkcentral (pclk_central),
.pclkch0 (pclk_ch0),
.phyrst (phy_rst),
.physrst (phy_srst),
.phystatus (phystatus),
.pldclk (pld_clk),
.pldrst (pld_rst),
.pldsrst (pld_srst),
.pllfixedclk (pll_fixed_clk),
.powerdown (powerdown),
.resetstatus (reset_status),
.rxbardecvc0 (rx_st_bardec0),
.rxbardecvc1 (rx_st_bardec1),
.rxbevc00 (rx_st_be0),
.rxbevc01 (rx_st_be0_p1),
.rxbevc10 (rx_st_be1),
.rxbevc11 (rx_st_be1_p1),
.rxdata (rxdata),
.rxdatak (rxdatak),
.rxdatavc00 (rx_st_data0),
.rxdatavc01 (rx_st_data0_p1),
.rxdatavc10 (rx_st_data1),
.rxdatavc11 (rx_st_data1_p1),
.rxelecidle (rxelecidle),
.rxeopvc00 (rx_st_eop0),
.rxeopvc01 (rx_st_eop0_p1),
.rxeopvc10 (rx_st_eop1),
.rxeopvc11 (rx_st_eop1_p1),
.rxerrvc0 (rx_st_err0),
.rxerrvc1 (rx_st_err1),
.rxfifoemptyvc0 (rx_fifo_empty0),
.rxfifoemptyvc1 (rx_fifo_empty1),
.rxfifofullvc0 (rx_fifo_full0),
.rxfifofullvc1 (rx_fifo_full1),
.rxfifordpvc0 (open_rxfifordpvc0),
.rxfifordpvc1 (open_rxfifordpvc1),
.rxfifowrpvc0 (open_rxfifowrpvc0),
.rxfifowrpvc1 (open_rxfifowrpvc1),
.rxmaskvc0 (rx_st_mask0_int),
.rxmaskvc1 (rx_st_mask1),
.rxpolarity (rxpolarity),
.rxreadyvc0 (rx_st_ready0_int),
.rxreadyvc1 (rx_st_ready1),
.rxsopvc00 (rx_st_sop0),
.rxsopvc01 (rx_st_sop0_p1),
.rxsopvc10 (rx_st_sop1),
.rxsopvc11 (rx_st_sop1_p1),
.rxstatus (rxstatus),
.rxvalid (rxvalid),
.rxvalidvc0 (rx_st_valid0),
.rxvalidvc1 (rx_st_valid1),
.scanen (gnd_scanen),
.scanmoden (scanmoden),
.serrout (serr_out),
.swdnin (swdn_in_int),
.swdnwake (swdn_wake),
.swuphotrst (swup_hotrst),
.swupin (swup_in_int),
.testin (test_in),
.testout (test_out),
.tlaermsinum (aer_msi_num_int),
.tlappintaack (app_int_ack),
.tlappintasts (app_int_sts_int),
.tlappmsiack (app_msi_ack),
.tlappmsinum (app_msi_num),
.tlappmsireq (app_msi_req_int),
.tlappmsitc (app_msi_tc_int),
.tlcfgadd (tl_cfg_add_hip),
.tlcfgctl (tl_cfg_ctl_hip),
.tlcfgctlwr (tl_cfg_ctl_wr_hip),
.tlcfgsts (tl_cfg_sts_hip),
.tlcfgstswr (tl_cfg_sts_wr_hip),
.tlhpgctrler (hpg_ctrler),
.tlpexmsinum (pex_msi_num),
.tlpmauxpwr (pm_auxpwr),
.tlpmdata (pm_data),
.tlpmetocr (pme_to_cr_int),
.tlpmetosr (pme_to_sr),
.tlpmevent (pm_event_int),
.tlslotclkcfg (tl_slotclk_cfg),
.txcompl (txcompl),
.txcredvc0 (tx_cred0_int),
.txcredvc1 (tx_cred1_int),
.txdata (txdata),
.txdatak (txdatak),
.txdatavc00 (tx_st_data0_int),
.txdatavc01 (tx_st_data0_p1),
.txdatavc10 (tx_st_data1),
.txdatavc11 (tx_st_data1_p1),
.txdeemph (tx_deemph),
.txdetectrx (txdetectrx),
.txelecidle (txelecidle),
.txeopvc00 (tx_st_eop0_int),
.txeopvc01 (tx_st_eop0_p1),
.txeopvc10 (tx_st_eop1),
.txeopvc11 (tx_st_eop1_p1),
.txerrvc0 (tx_st_err0_int),
.txerrvc1 (tx_st_err1),
.txfifoemptyvc0 (tx_fifo_empty0),
.txfifoemptyvc1 (tx_fifo_empty1),
.txfifofullvc0 (tx_fifo_full0),
.txfifofullvc1 (tx_fifo_full1),
.txfifordpvc0 (tx_fifo_rdptr0),
.txfifordpvc1 (tx_fifo_rdptr1),
.txfifowrpvc0 (tx_fifo_wrptr0),
.txfifowrpvc1 (tx_fifo_wrptr1),
.txmargin (tx_margin),
.txreadyvc0 (tx_st_ready0),
.txreadyvc1 (tx_st_ready1),
.txsopvc00 (tx_st_sop0_int),
.txsopvc01 (tx_st_sop0_p1),
.txsopvc10 (tx_st_sop1),
.txsopvc11 (tx_st_sop1_p1),
.txvalidvc0 (tx_st_valid0_int),
.txvalidvc1 (tx_st_valid1),
.wakeoen (wake_oen)
);
defparam arriaiigz_hssi_pcie_hip.advanced_errors = advanced_errors,
arriaiigz_hssi_pcie_hip.bar0_64bit_mem_space = bar0_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar0_io_space = bar0_io_space,
arriaiigz_hssi_pcie_hip.bar0_prefetchable = bar0_prefetchable,
arriaiigz_hssi_pcie_hip.bar0_size_mask = bar0_size_mask,
arriaiigz_hssi_pcie_hip.bar1_64bit_mem_space = bar1_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar1_io_space = bar1_io_space,
arriaiigz_hssi_pcie_hip.bar1_prefetchable = bar1_prefetchable,
arriaiigz_hssi_pcie_hip.bar1_size_mask = bar1_size_mask,
arriaiigz_hssi_pcie_hip.bar2_64bit_mem_space = bar2_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar2_io_space = bar2_io_space,
arriaiigz_hssi_pcie_hip.bar2_prefetchable = bar2_prefetchable,
arriaiigz_hssi_pcie_hip.bar2_size_mask = bar2_size_mask,
arriaiigz_hssi_pcie_hip.bar3_64bit_mem_space = bar3_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar3_io_space = bar3_io_space,
arriaiigz_hssi_pcie_hip.bar3_prefetchable = bar3_prefetchable,
arriaiigz_hssi_pcie_hip.bar3_size_mask = bar3_size_mask,
arriaiigz_hssi_pcie_hip.bar4_64bit_mem_space = bar4_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar4_io_space = bar4_io_space,
arriaiigz_hssi_pcie_hip.bar4_prefetchable = bar4_prefetchable,
arriaiigz_hssi_pcie_hip.bar4_size_mask = bar4_size_mask,
arriaiigz_hssi_pcie_hip.bar5_64bit_mem_space = bar5_64bit_mem_space,
arriaiigz_hssi_pcie_hip.bar5_io_space = bar5_io_space,
arriaiigz_hssi_pcie_hip.bar5_prefetchable = bar5_prefetchable,
arriaiigz_hssi_pcie_hip.bar5_size_mask = bar5_size_mask,
arriaiigz_hssi_pcie_hip.bar_io_window_size = bar_io_window_size,
arriaiigz_hssi_pcie_hip.bar_prefetchable = bar_prefetchable,
arriaiigz_hssi_pcie_hip.bridge_port_ssid_support = bridge_port_ssid_support,
arriaiigz_hssi_pcie_hip.bridge_port_vga_enable = bridge_port_vga_enable,
arriaiigz_hssi_pcie_hip.bypass_cdc = bypass_cdc,
arriaiigz_hssi_pcie_hip.tx_cdc_full_value = tx_cdc_full_value ,
arriaiigz_hssi_pcie_hip.bypass_tl = bypass_tl,
arriaiigz_hssi_pcie_hip.class_code = class_code,
arriaiigz_hssi_pcie_hip.completion_timeout = completion_timeout,
arriaiigz_hssi_pcie_hip.core_clk_divider = core_clk_divider,
arriaiigz_hssi_pcie_hip.core_clk_source = core_clk_source,
arriaiigz_hssi_pcie_hip.credit_buffer_allocation_aux = credit_buffer_allocation_aux,
arriaiigz_hssi_pcie_hip.deemphasis_enable = deemphasis_enable,
arriaiigz_hssi_pcie_hip.device_id = device_id,
arriaiigz_hssi_pcie_hip.device_number = device_number,
arriaiigz_hssi_pcie_hip.diffclock_nfts_count = diffclock_nfts_count,
arriaiigz_hssi_pcie_hip.disable_cdc_clk_ppm = disable_cdc_clk_ppm,
arriaiigz_hssi_pcie_hip.disable_link_x2_support = disable_link_x2_support,
arriaiigz_hssi_pcie_hip.disable_snoop_packet = disable_snoop_packet,
arriaiigz_hssi_pcie_hip.dll_active_report_support = dll_active_report_support,
arriaiigz_hssi_pcie_hip.ei_delay_powerdown_count = ei_delay_powerdown_count,
arriaiigz_hssi_pcie_hip.eie_before_nfts_count = eie_before_nfts_count,
arriaiigz_hssi_pcie_hip.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode,
arriaiigz_hssi_pcie_hip.enable_ch0_pclk_out = enable_ch0_pclk_out,
arriaiigz_hssi_pcie_hip.enable_completion_timeout_disable = enable_completion_timeout_disable,
arriaiigz_hssi_pcie_hip.enable_coreclk_out_half_rate = enable_coreclk_out_half_rate,
arriaiigz_hssi_pcie_hip.enable_ecrc_check = enable_ecrc_check,
arriaiigz_hssi_pcie_hip.enable_ecrc_gen = enable_ecrc_gen,
arriaiigz_hssi_pcie_hip.enable_function_msi_support = enable_function_msi_support,
arriaiigz_hssi_pcie_hip.enable_function_msix_support = enable_function_msix_support,
arriaiigz_hssi_pcie_hip.enable_gen2_core = enable_gen2_core,
arriaiigz_hssi_pcie_hip.enable_hip_x1_loopback = enable_hip_x1_loopback,
arriaiigz_hssi_pcie_hip.enable_l1_aspm = enable_l1_aspm,
arriaiigz_hssi_pcie_hip.enable_msi_64bit_addressing = enable_msi_64bit_addressing,
arriaiigz_hssi_pcie_hip.enable_msi_masking = enable_msi_masking,
arriaiigz_hssi_pcie_hip.enable_retrybuf_ecc = enable_retrybuf_ecc,
arriaiigz_hssi_pcie_hip.enable_retrybuf_x8_clk_stealing = enable_retrybuf_x8_clk_stealing,
arriaiigz_hssi_pcie_hip.enable_rx0buf_ecc = enable_rx0buf_ecc,
arriaiigz_hssi_pcie_hip.enable_rx0buf_x8_clk_stealing = enable_rx0buf_x8_clk_stealing,
arriaiigz_hssi_pcie_hip.enable_rx1buf_ecc = enable_rx1buf_ecc,
arriaiigz_hssi_pcie_hip.enable_rx1buf_x8_clk_stealing = enable_rx1buf_x8_clk_stealing,
arriaiigz_hssi_pcie_hip.enable_rx_buffer_checking = enable_rx_buffer_checking,
arriaiigz_hssi_pcie_hip.enable_rx_reordering = enable_rx_reordering,
arriaiigz_hssi_pcie_hip.enable_slot_register = enable_slot_register,
arriaiigz_hssi_pcie_hip.endpoint_l0_latency = endpoint_l0_latency,
arriaiigz_hssi_pcie_hip.endpoint_l1_latency = endpoint_l1_latency,
arriaiigz_hssi_pcie_hip.expansion_base_address_register = expansion_base_address_register,
arriaiigz_hssi_pcie_hip.extend_tag_field = extend_tag_field,
arriaiigz_hssi_pcie_hip.fc_init_timer = fc_init_timer,
arriaiigz_hssi_pcie_hip.flow_control_timeout_count = flow_control_timeout_count,
arriaiigz_hssi_pcie_hip.flow_control_update_count = flow_control_update_count,
arriaiigz_hssi_pcie_hip.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count,
arriaiigz_hssi_pcie_hip.gen2_lane_rate_mode = gen2_lane_rate_mode,
arriaiigz_hssi_pcie_hip.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count,
arriaiigz_hssi_pcie_hip.hot_plug_support = hot_plug_support,
arriaiigz_hssi_pcie_hip.indicator = indicator,
arriaiigz_hssi_pcie_hip.l01_entry_latency = l01_entry_latency,
arriaiigz_hssi_pcie_hip.l0_exit_latency_diffclock = l0_exit_latency_diffclock,
arriaiigz_hssi_pcie_hip.l0_exit_latency_sameclock = l0_exit_latency_sameclock,
arriaiigz_hssi_pcie_hip.l1_exit_latency_diffclock = l1_exit_latency_diffclock,
arriaiigz_hssi_pcie_hip.l1_exit_latency_sameclock = l1_exit_latency_sameclock,
arriaiigz_hssi_pcie_hip.lane_mask = lane_mask,
arriaiigz_hssi_pcie_hip.low_priority_vc = low_priority_vc,
arriaiigz_hssi_pcie_hip.lpm_type = lpm_type,
arriaiigz_hssi_pcie_hip.max_link_width = max_link_width,
arriaiigz_hssi_pcie_hip.max_payload_size = max_payload_size,
arriaiigz_hssi_pcie_hip.maximum_current = maximum_current,
arriaiigz_hssi_pcie_hip.millisecond_cycle_count = millisecond_cycle_count,
arriaiigz_hssi_pcie_hip.msi_function_count = msi_function_count,
arriaiigz_hssi_pcie_hip.msix_pba_bir = msix_pba_bir,
arriaiigz_hssi_pcie_hip.msix_pba_offset = msix_pba_offset,
arriaiigz_hssi_pcie_hip.msix_table_bir = msix_table_bir,
arriaiigz_hssi_pcie_hip.msix_table_offset = msix_table_offset,
arriaiigz_hssi_pcie_hip.msix_table_size = msix_table_size,
arriaiigz_hssi_pcie_hip.no_command_completed = no_command_completed,
arriaiigz_hssi_pcie_hip.no_soft_reset = no_soft_reset,
arriaiigz_hssi_pcie_hip.pcie_mode = pcie_mode,
arriaiigz_hssi_pcie_hip.pme_state_enable = pme_state_enable,
arriaiigz_hssi_pcie_hip.port_link_number = port_link_number,
arriaiigz_hssi_pcie_hip.register_pipe_signals = register_pipe_signals,
arriaiigz_hssi_pcie_hip.retry_buffer_last_active_address = retry_buffer_last_active_address,
arriaiigz_hssi_pcie_hip.retry_buffer_memory_settings = retry_buffer_memory_settings,
arriaiigz_hssi_pcie_hip.revision_id = revision_id,
arriaiigz_hssi_pcie_hip.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max,
arriaiigz_hssi_pcie_hip.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min,
arriaiigz_hssi_pcie_hip.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max,
arriaiigz_hssi_pcie_hip.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min,
arriaiigz_hssi_pcie_hip.rx_ptr1_nonposted_dpram_max = rx_ptr1_nonposted_dpram_max,
arriaiigz_hssi_pcie_hip.rx_ptr1_nonposted_dpram_min = rx_ptr1_nonposted_dpram_min,
arriaiigz_hssi_pcie_hip.rx_ptr1_posted_dpram_max = rx_ptr1_posted_dpram_max,
arriaiigz_hssi_pcie_hip.rx_ptr1_posted_dpram_min = rx_ptr1_posted_dpram_min,
arriaiigz_hssi_pcie_hip.sameclock_nfts_count = sameclock_nfts_count,
arriaiigz_hssi_pcie_hip.single_rx_detect = single_rx_detect,
arriaiigz_hssi_pcie_hip.skp_os_schedule_count = skp_os_schedule_count,
arriaiigz_hssi_pcie_hip.slot_number = slot_number,
arriaiigz_hssi_pcie_hip.slot_power_limit = slot_power_limit,
arriaiigz_hssi_pcie_hip.slot_power_scale = slot_power_scale,
arriaiigz_hssi_pcie_hip.ssid = ssid,
arriaiigz_hssi_pcie_hip.ssvid = ssvid,
arriaiigz_hssi_pcie_hip.subsystem_device_id = subsystem_device_id,
arriaiigz_hssi_pcie_hip.subsystem_vendor_id = subsystem_vendor_id,
arriaiigz_hssi_pcie_hip.surprise_down_error_support = surprise_down_error_support,
arriaiigz_hssi_pcie_hip.use_crc_forwarding = use_crc_forwarding,
arriaiigz_hssi_pcie_hip.vc0_clk_enable = vc0_clk_enable,
arriaiigz_hssi_pcie_hip.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data,
arriaiigz_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header,
arriaiigz_hssi_pcie_hip.vc1_clk_enable = vc1_clk_enable,
arriaiigz_hssi_pcie_hip.vc1_rx_buffer_memory_settings = vc1_rx_buffer_memory_settings,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_data = vc1_rx_flow_ctrl_compl_data,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_header = vc1_rx_flow_ctrl_compl_header,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_data = vc1_rx_flow_ctrl_nonposted_data,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_header = vc1_rx_flow_ctrl_nonposted_header,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_data = vc1_rx_flow_ctrl_posted_data,
arriaiigz_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_header = vc1_rx_flow_ctrl_posted_header,
arriaiigz_hssi_pcie_hip.vc_arbitration = vc_arbitration,
arriaiigz_hssi_pcie_hip.vc_enable = vc_enable,
arriaiigz_hssi_pcie_hip.vendor_id = vendor_id;
end
endgenerate
generate
if (p_pcie_hip_type == "1")
begin : arria_ii
arriaii_hssi_pcie_hip arriaii_hssi_pcie_hip
(
.bistdonearcv0 (open_bistdonearcv0),
.bistdonearcv1 (open_bistdonearcv1),
.bistdonearpl (open_bistdonearpl),
.bistdonebrcv0 (open_bistdonebrcv0),
.bistdonebrcv1 (open_bistdonebrcv1),
.bistdonebrpl (open_bistdonebrpl),
.bistenrcv0 (gnd_bistenrcv0),
.bistenrcv1 (gnd_bistenrcv1),
.bistenrpl (gnd_bistenrpl),
.bistpassrcv0 (open_bistpassrcv0),
.bistpassrcv1 (open_bistpassrcv1),
.bistpassrpl (open_bistpassrpl),
.bistscanen (gnd_bistscanen),
.bistscanin (gnd_bistscanin),
.bistscanoutrcv0 (open_bistscanoutrcv0),
.bistscanoutrcv1 (open_bistscanoutrcv1),
.bistscanoutrpl (open_bistscanoutrpl),
.bisttesten (gnd_bisttesten),
.clrrxpath (clrrxpath),
.coreclkin (core_clk_in),
.coreclkout (core_clk_out),
.corecrst (core_crst),
.corepor (core_por),
.corerst (core_rst),
.coresrst (core_srst),
.cplerr (cpl_err),
.cplpending (cpl_pending_int),
.dataenablen (open_dataenablen),
.dbgpipex1rx (dbgpipex1rx),
.derrcorextrcv0 (derr_cor_ext_rcv0),
.derrcorextrcv1 (derr_cor_ext_rcv1),
.derrcorextrpl (derr_cor_ext_rpl),
.derrrpl (derr_rpl),
.dlackphypm (dlackphypm),
.dlackrequpfc (dlackrequpfc),
.dlacksndupfc (dlacksndupfc),
.dlaspmcr0 (tlbp_dl_aspm_cr0),
.dlcomclkreg (tlbp_dl_comclk_reg),
.dlctrllink2 (dlctrllink2),
.dlcurrentdeemp (dlcurrentdeemp),
.dlcurrentspeed (dlcurrentspeed),
.dldataupfc (dldataupfc),
.dldllreq (dldllreq),
.dlerrdll (dlerrdll),
.dlerrphy (dlerrphy),
.dlhdrupfc (dlhdrupfc),
.dlinhdllp (dlinhdllp),
.dllinkautobdwstatus (tlbp_dl_link_autobdw_status),
.dllinkbdwmngstatus (tlbp_dl_link_bdwmng_status),
.dlltssm (dl_ltssm),
.dlmaxploaddcr (tlbp_dl_maxpload_dcr),
.dlreqphycfg (dlreqphycfg),
.dlreqphypm (dlreqphypm),
.dlrequpfc (dlrequpfc),
.dlreqwake (dlreqwake),
.dlrpbufemp (dlrpbufemp),
.dlrstentercompbit (tlbp_dl_rst_enter_comp_bit),
.dlrsttxmarginfield (tlbp_dl_rst_tx_margin_field),
.dlrxecrcchk (dlrxecrcchk),
.dlrxtyppm (dlrxtyppm),
.dlrxvalpm (dlrxvalpm),
.dlsndupfc (dlsndupfc),
.dltxackpm (dltxackpm),
.dltxcfgextsy (dltxcfgextsy),
.dltxreqpm (dltxreqpm),
.dltxtyppm (dltxtyppm),
.dltypupfc (dltypupfc),
.dlup (dlup),
.dlupexit (dlup_exit),
.dlvcctrl (dlvcctrl),
.dlvcidmap (dlvcidmap),
.dlvcidupfc (dlvcidupfc),
.dlvcstatus (dlvcstatus),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout),
.dpriostate (open_dpriostate),
.eidleinfersel (eidle_infer_sel),
.ev128ns (ev_128ns),
.ev1us (ev_1us),
.extraclkout (hip_extraclkout),
.extraout (hip_extraout),
.gen2rate (gen2rate),
.gen2rategnd (open_gen2rategnd),
.hotrstexit (hotrst_exit),
.intstatus (int_status),
.l2exit (l2_exit),
.laneact (lane_act),
.linkup (linkup),
.lmiack (lmi_ack),
.lmiaddr (lmi_addr),
.lmidin (lmi_din),
.lmidout (lmi_dout),
.lmirden (lmi_rden),
.lmiwren (lmi_wren),
.ltssml0state (ltssml0state),
.mode (mode),
.mramhiptestenable (gnd_mram_hip_test_enable),
.mramregscanen (gnd_mramregscanen),
.mramregscanin (gnd_mramregscanin),
.mramregscanout (open_mramregscanout),
.pclkcentral (pclk_central),
.pclkch0 (pclk_ch0),
.phyrst (phy_rst),
.physrst (phy_srst),
.phystatus (phystatus),
.pldclk (pld_clk),
.pldrst (pld_rst),
.pldsrst (pld_srst),
.pllfixedclk (pll_fixed_clk),
.powerdown (powerdown),
.resetstatus (reset_status),
.rxbardecvc0 (rx_st_bardec0),
.rxbardecvc1 (rx_st_bardec1),
.rxbevc00 (rx_st_be0),
.rxbevc01 (rx_st_be0_p1),
.rxbevc10 (rx_st_be1),
.rxbevc11 (rx_st_be1_p1),
.rxdata (rxdata),
.rxdatak (rxdatak),
.rxdatavc00 (rx_st_data0),
.rxdatavc01 (rx_st_data0_p1),
.rxdatavc10 (rx_st_data1),
.rxdatavc11 (rx_st_data1_p1),
.rxelecidle (rxelecidle),
.rxeopvc00 (rx_st_eop0),
.rxeopvc01 (rx_st_eop0_p1),
.rxeopvc10 (rx_st_eop1),
.rxeopvc11 (rx_st_eop1_p1),
.rxerrvc0 (rx_st_err0),
.rxerrvc1 (rx_st_err1),
.rxfifoemptyvc0 (rx_fifo_empty0),
.rxfifoemptyvc1 (rx_fifo_empty1),
.rxfifofullvc0 (rx_fifo_full0),
.rxfifofullvc1 (rx_fifo_full1),
.rxfifordpvc0 (open_rxfifordpvc0),
.rxfifordpvc1 (open_rxfifordpvc1),
.rxfifowrpvc0 (open_rxfifowrpvc0),
.rxfifowrpvc1 (open_rxfifowrpvc1),
.rxmaskvc0 (rx_st_mask0_int),
.rxmaskvc1 (rx_st_mask1),
.rxpolarity (rxpolarity),
.rxreadyvc0 (rx_st_ready0_int),
.rxreadyvc1 (rx_st_ready1),
.rxsopvc00 (rx_st_sop0),
.rxsopvc01 (rx_st_sop0_p1),
.rxsopvc10 (rx_st_sop1),
.rxsopvc11 (rx_st_sop1_p1),
.rxstatus (rxstatus),
.rxvalid (rxvalid),
.rxvalidvc0 (rx_st_valid0),
.rxvalidvc1 (rx_st_valid1),
.scanen (gnd_scanen),
.scanmoden (scanmoden),
.serrout (serr_out),
.swdnin (swdn_in_int),
.swdnwake (swdn_wake),
.swuphotrst (swup_hotrst),
.swupin (swup_in_int),
.testin (test_in),
.testout (test_out),
.tlaermsinum (aer_msi_num_int),
.tlappintaack (app_int_ack),
.tlappintasts (app_int_sts_int),
.tlappmsiack (app_msi_ack),
.tlappmsinum (app_msi_num),
.tlappmsireq (app_msi_req_int),
.tlappmsitc (app_msi_tc_int),
.tlcfgadd (tl_cfg_add_hip),
.tlcfgctl (tl_cfg_ctl_hip),
.tlcfgctlwr (tl_cfg_ctl_wr_hip),
.tlcfgsts (tl_cfg_sts_hip),
.tlcfgstswr (tl_cfg_sts_wr_hip),
.tlhpgctrler (hpg_ctrler),
.tlpexmsinum (pex_msi_num),
.tlpmauxpwr (pm_auxpwr),
.tlpmdata (pm_data),
.tlpmetocr (pme_to_cr_int),
.tlpmetosr (pme_to_sr),
.tlpmevent (pm_event_int),
.tlslotclkcfg (tl_slotclk_cfg),
.txcompl (txcompl),
.txcredvc0 (tx_cred0_int),
.txcredvc1 (tx_cred1_int),
.txdata (txdata),
.txdatak (txdatak),
.txdatavc00 (tx_st_data0_int),
.txdatavc01 (tx_st_data0_p1),
.txdatavc10 (tx_st_data1),
.txdatavc11 (tx_st_data1_p1),
.txdeemph (tx_deemph),
.txdetectrx (txdetectrx),
.txelecidle (txelecidle),
.txeopvc00 (tx_st_eop0_int),
.txeopvc01 (tx_st_eop0_p1),
.txeopvc10 (tx_st_eop1),
.txeopvc11 (tx_st_eop1_p1),
.txerrvc0 (tx_st_err0_int),
.txerrvc1 (tx_st_err1),
.txfifoemptyvc0 (tx_fifo_empty0),
.txfifoemptyvc1 (tx_fifo_empty1),
.txfifofullvc0 (tx_fifo_full0),
.txfifofullvc1 (tx_fifo_full1),
.txfifordpvc0 (tx_fifo_rdptr0),
.txfifordpvc1 (tx_fifo_rdptr1),
.txfifowrpvc0 (tx_fifo_wrptr0),
.txfifowrpvc1 (tx_fifo_wrptr1),
.txmargin (tx_margin),
.txreadyvc0 (tx_st_ready0),
.txreadyvc1 (tx_st_ready1),
.txsopvc00 (tx_st_sop0_int),
.txsopvc01 (tx_st_sop0_p1),
.txsopvc10 (tx_st_sop1),
.txsopvc11 (tx_st_sop1_p1),
.txvalidvc0 (tx_st_valid0_int),
.txvalidvc1 (tx_st_valid1),
.wakeoen (wake_oen)
);
defparam arriaii_hssi_pcie_hip.advanced_errors = advanced_errors,
arriaii_hssi_pcie_hip.bar0_64bit_mem_space = bar0_64bit_mem_space,
arriaii_hssi_pcie_hip.bar0_io_space = bar0_io_space,
arriaii_hssi_pcie_hip.bar0_prefetchable = bar0_prefetchable,
arriaii_hssi_pcie_hip.bar0_size_mask = bar0_size_mask,
arriaii_hssi_pcie_hip.bar1_64bit_mem_space = bar1_64bit_mem_space,
arriaii_hssi_pcie_hip.bar1_io_space = bar1_io_space,
arriaii_hssi_pcie_hip.bar1_prefetchable = bar1_prefetchable,
arriaii_hssi_pcie_hip.bar1_size_mask = bar1_size_mask,
arriaii_hssi_pcie_hip.bar2_64bit_mem_space = bar2_64bit_mem_space,
arriaii_hssi_pcie_hip.bar2_io_space = bar2_io_space,
arriaii_hssi_pcie_hip.bar2_prefetchable = bar2_prefetchable,
arriaii_hssi_pcie_hip.bar2_size_mask = bar2_size_mask,
arriaii_hssi_pcie_hip.bar3_64bit_mem_space = bar3_64bit_mem_space,
arriaii_hssi_pcie_hip.bar3_io_space = bar3_io_space,
arriaii_hssi_pcie_hip.bar3_prefetchable = bar3_prefetchable,
arriaii_hssi_pcie_hip.bar3_size_mask = bar3_size_mask,
arriaii_hssi_pcie_hip.bar4_64bit_mem_space = bar4_64bit_mem_space,
arriaii_hssi_pcie_hip.bar4_io_space = bar4_io_space,
arriaii_hssi_pcie_hip.bar4_prefetchable = bar4_prefetchable,
arriaii_hssi_pcie_hip.bar4_size_mask = bar4_size_mask,
arriaii_hssi_pcie_hip.bar5_64bit_mem_space = bar5_64bit_mem_space,
arriaii_hssi_pcie_hip.bar5_io_space = bar5_io_space,
arriaii_hssi_pcie_hip.bar5_prefetchable = bar5_prefetchable,
arriaii_hssi_pcie_hip.bar5_size_mask = bar5_size_mask,
arriaii_hssi_pcie_hip.bar_io_window_size = bar_io_window_size,
arriaii_hssi_pcie_hip.bar_prefetchable = bar_prefetchable,
arriaii_hssi_pcie_hip.bridge_port_ssid_support = bridge_port_ssid_support,
arriaii_hssi_pcie_hip.bridge_port_vga_enable = bridge_port_vga_enable,
arriaii_hssi_pcie_hip.bypass_cdc = bypass_cdc,
arriaii_hssi_pcie_hip.tx_cdc_full_value = tx_cdc_full_value ,
arriaii_hssi_pcie_hip.bypass_tl = bypass_tl,
arriaii_hssi_pcie_hip.class_code = class_code,
arriaii_hssi_pcie_hip.completion_timeout = completion_timeout,
arriaii_hssi_pcie_hip.core_clk_divider = core_clk_divider,
arriaii_hssi_pcie_hip.core_clk_source = core_clk_source,
arriaii_hssi_pcie_hip.credit_buffer_allocation_aux = credit_buffer_allocation_aux,
arriaii_hssi_pcie_hip.deemphasis_enable = deemphasis_enable,
arriaii_hssi_pcie_hip.device_id = device_id,
arriaii_hssi_pcie_hip.device_number = device_number,
arriaii_hssi_pcie_hip.diffclock_nfts_count = diffclock_nfts_count,
arriaii_hssi_pcie_hip.disable_cdc_clk_ppm = disable_cdc_clk_ppm,
arriaii_hssi_pcie_hip.disable_link_x2_support = disable_link_x2_support,
arriaii_hssi_pcie_hip.disable_snoop_packet = disable_snoop_packet,
arriaii_hssi_pcie_hip.dll_active_report_support = dll_active_report_support,
arriaii_hssi_pcie_hip.ei_delay_powerdown_count = ei_delay_powerdown_count,
arriaii_hssi_pcie_hip.eie_before_nfts_count = eie_before_nfts_count,
arriaii_hssi_pcie_hip.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode,
arriaii_hssi_pcie_hip.enable_ch0_pclk_out = enable_ch0_pclk_out,
arriaii_hssi_pcie_hip.enable_completion_timeout_disable = enable_completion_timeout_disable,
arriaii_hssi_pcie_hip.enable_coreclk_out_half_rate = enable_coreclk_out_half_rate,
arriaii_hssi_pcie_hip.enable_ecrc_check = enable_ecrc_check,
arriaii_hssi_pcie_hip.enable_ecrc_gen = enable_ecrc_gen,
arriaii_hssi_pcie_hip.enable_function_msi_support = enable_function_msi_support,
arriaii_hssi_pcie_hip.enable_function_msix_support = enable_function_msix_support,
arriaii_hssi_pcie_hip.enable_gen2_core = enable_gen2_core,
arriaii_hssi_pcie_hip.enable_hip_x1_loopback = enable_hip_x1_loopback,
arriaii_hssi_pcie_hip.enable_l1_aspm = enable_l1_aspm,
arriaii_hssi_pcie_hip.enable_msi_64bit_addressing = enable_msi_64bit_addressing,
arriaii_hssi_pcie_hip.enable_msi_masking = enable_msi_masking,
arriaii_hssi_pcie_hip.enable_retrybuf_ecc = enable_retrybuf_ecc,
arriaii_hssi_pcie_hip.enable_retrybuf_x8_clk_stealing = enable_retrybuf_x8_clk_stealing,
arriaii_hssi_pcie_hip.enable_rx0buf_ecc = enable_rx0buf_ecc,
arriaii_hssi_pcie_hip.enable_rx0buf_x8_clk_stealing = enable_rx0buf_x8_clk_stealing,
arriaii_hssi_pcie_hip.enable_rx1buf_ecc = enable_rx1buf_ecc,
arriaii_hssi_pcie_hip.enable_rx1buf_x8_clk_stealing = enable_rx1buf_x8_clk_stealing,
arriaii_hssi_pcie_hip.enable_rx_buffer_checking = enable_rx_buffer_checking,
arriaii_hssi_pcie_hip.enable_rx_reordering = enable_rx_reordering,
arriaii_hssi_pcie_hip.enable_slot_register = enable_slot_register,
arriaii_hssi_pcie_hip.endpoint_l0_latency = endpoint_l0_latency,
arriaii_hssi_pcie_hip.endpoint_l1_latency = endpoint_l1_latency,
arriaii_hssi_pcie_hip.expansion_base_address_register = expansion_base_address_register,
arriaii_hssi_pcie_hip.extend_tag_field = extend_tag_field,
arriaii_hssi_pcie_hip.fc_init_timer = fc_init_timer,
arriaii_hssi_pcie_hip.flow_control_timeout_count = flow_control_timeout_count,
arriaii_hssi_pcie_hip.flow_control_update_count = flow_control_update_count,
arriaii_hssi_pcie_hip.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count,
arriaii_hssi_pcie_hip.gen2_lane_rate_mode = gen2_lane_rate_mode,
arriaii_hssi_pcie_hip.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count,
arriaii_hssi_pcie_hip.hot_plug_support = hot_plug_support,
arriaii_hssi_pcie_hip.indicator = indicator,
arriaii_hssi_pcie_hip.l01_entry_latency = l01_entry_latency,
arriaii_hssi_pcie_hip.l0_exit_latency_diffclock = l0_exit_latency_diffclock,
arriaii_hssi_pcie_hip.l0_exit_latency_sameclock = l0_exit_latency_sameclock,
arriaii_hssi_pcie_hip.l1_exit_latency_diffclock = l1_exit_latency_diffclock,
arriaii_hssi_pcie_hip.l1_exit_latency_sameclock = l1_exit_latency_sameclock,
arriaii_hssi_pcie_hip.lane_mask = lane_mask,
arriaii_hssi_pcie_hip.low_priority_vc = low_priority_vc,
arriaii_hssi_pcie_hip.lpm_type = lpm_type,
arriaii_hssi_pcie_hip.max_link_width = max_link_width,
arriaii_hssi_pcie_hip.max_payload_size = max_payload_size,
arriaii_hssi_pcie_hip.maximum_current = maximum_current,
arriaii_hssi_pcie_hip.millisecond_cycle_count = millisecond_cycle_count,
arriaii_hssi_pcie_hip.msi_function_count = msi_function_count,
arriaii_hssi_pcie_hip.msix_pba_bir = msix_pba_bir,
arriaii_hssi_pcie_hip.msix_pba_offset = msix_pba_offset,
arriaii_hssi_pcie_hip.msix_table_bir = msix_table_bir,
arriaii_hssi_pcie_hip.msix_table_offset = msix_table_offset,
arriaii_hssi_pcie_hip.msix_table_size = msix_table_size,
arriaii_hssi_pcie_hip.no_command_completed = no_command_completed,
arriaii_hssi_pcie_hip.no_soft_reset = no_soft_reset,
arriaii_hssi_pcie_hip.pcie_mode = pcie_mode,
arriaii_hssi_pcie_hip.pme_state_enable = pme_state_enable,
arriaii_hssi_pcie_hip.port_link_number = port_link_number,
arriaii_hssi_pcie_hip.register_pipe_signals = register_pipe_signals,
arriaii_hssi_pcie_hip.retry_buffer_last_active_address = retry_buffer_last_active_address,
arriaii_hssi_pcie_hip.retry_buffer_memory_settings = retry_buffer_memory_settings,
arriaii_hssi_pcie_hip.revision_id = revision_id,
arriaii_hssi_pcie_hip.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max,
arriaii_hssi_pcie_hip.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min,
arriaii_hssi_pcie_hip.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max,
arriaii_hssi_pcie_hip.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min,
arriaii_hssi_pcie_hip.rx_ptr1_nonposted_dpram_max = rx_ptr1_nonposted_dpram_max,
arriaii_hssi_pcie_hip.rx_ptr1_nonposted_dpram_min = rx_ptr1_nonposted_dpram_min,
arriaii_hssi_pcie_hip.rx_ptr1_posted_dpram_max = rx_ptr1_posted_dpram_max,
arriaii_hssi_pcie_hip.rx_ptr1_posted_dpram_min = rx_ptr1_posted_dpram_min,
arriaii_hssi_pcie_hip.sameclock_nfts_count = sameclock_nfts_count,
arriaii_hssi_pcie_hip.single_rx_detect = single_rx_detect,
arriaii_hssi_pcie_hip.skp_os_schedule_count = skp_os_schedule_count,
arriaii_hssi_pcie_hip.slot_number = slot_number,
arriaii_hssi_pcie_hip.slot_power_limit = slot_power_limit,
arriaii_hssi_pcie_hip.slot_power_scale = slot_power_scale,
arriaii_hssi_pcie_hip.ssid = ssid,
arriaii_hssi_pcie_hip.ssvid = ssvid,
arriaii_hssi_pcie_hip.subsystem_device_id = subsystem_device_id,
arriaii_hssi_pcie_hip.subsystem_vendor_id = subsystem_vendor_id,
arriaii_hssi_pcie_hip.surprise_down_error_support = surprise_down_error_support,
arriaii_hssi_pcie_hip.use_crc_forwarding = use_crc_forwarding,
arriaii_hssi_pcie_hip.vc0_clk_enable = vc0_clk_enable,
arriaii_hssi_pcie_hip.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data,
arriaii_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header,
arriaii_hssi_pcie_hip.vc1_clk_enable = vc1_clk_enable,
arriaii_hssi_pcie_hip.vc1_rx_buffer_memory_settings = vc1_rx_buffer_memory_settings,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_data = vc1_rx_flow_ctrl_compl_data,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_header = vc1_rx_flow_ctrl_compl_header,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_data = vc1_rx_flow_ctrl_nonposted_data,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_header = vc1_rx_flow_ctrl_nonposted_header,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_data = vc1_rx_flow_ctrl_posted_data,
arriaii_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_header = vc1_rx_flow_ctrl_posted_header,
arriaii_hssi_pcie_hip.vc_arbitration = vc_arbitration,
arriaii_hssi_pcie_hip.vc_enable = vc_enable,
arriaii_hssi_pcie_hip.vendor_id = vendor_id;
end
endgenerate
generate
if (p_pcie_hip_type == "2")
begin : cyclone_iii
cycloneiv_hssi_pcie_hip cycloneiv_hssi_pcie_hip
(
.bistdonearcv0 (open_bistdonearcv0),
.bistdonearcv1 (open_bistdonearcv1),
.bistdonearpl (open_bistdonearpl),
.bistdonebrcv0 (open_bistdonebrcv0),
.bistdonebrcv1 (open_bistdonebrcv1),
.bistdonebrpl (open_bistdonebrpl),
.bistenrcv0 (gnd_bistenrcv0),
.bistenrcv1 (gnd_bistenrcv1),
.bistenrpl (gnd_bistenrpl),
.bistpassrcv0 (open_bistpassrcv0),
.bistpassrcv1 (open_bistpassrcv1),
.bistpassrpl (open_bistpassrpl),
.bistscanen (gnd_bistscanen),
.bistscanin (gnd_bistscanin),
.bistscanoutrcv0 (open_bistscanoutrcv0),
.bistscanoutrcv1 (open_bistscanoutrcv1),
.bistscanoutrpl (open_bistscanoutrpl),
.bisttesten (gnd_bisttesten),
.clrrxpath (clrrxpath),
.coreclkin (core_clk_in),
.coreclkout (core_clk_out),
.corecrst (core_crst),
.corepor (core_por),
.corerst (core_rst),
.coresrst (core_srst),
.cplerr (cpl_err),
.cplpending (cpl_pending_int),
.dataenablen (open_dataenablen),
.dbgpipex1rx (dbgpipex1rx),
.derrcorextrcv0 (derr_cor_ext_rcv0),
.derrcorextrcv1 (derr_cor_ext_rcv1),
.derrcorextrpl (derr_cor_ext_rpl),
.derrrpl (derr_rpl),
.dlackphypm (dlackphypm),
.dlackrequpfc (dlackrequpfc),
.dlacksndupfc (dlacksndupfc),
.dlaspmcr0 (tlbp_dl_aspm_cr0),
.dlcomclkreg (tlbp_dl_comclk_reg),
.dlctrllink2 (dlctrllink2),
.dlcurrentdeemp (dlcurrentdeemp),
.dlcurrentspeed (dlcurrentspeed),
.dldataupfc (dldataupfc),
.dldllreq (dldllreq),
.dlerrdll (dlerrdll),
.dlerrphy (dlerrphy),
.dlhdrupfc (dlhdrupfc),
.dlinhdllp (dlinhdllp),
.dllinkautobdwstatus (tlbp_dl_link_autobdw_status),
.dllinkbdwmngstatus (tlbp_dl_link_bdwmng_status),
.dlltssm (dl_ltssm),
.dlmaxploaddcr (tlbp_dl_maxpload_dcr),
.dlreqphycfg (dlreqphycfg),
.dlreqphypm (dlreqphypm),
.dlrequpfc (dlrequpfc),
.dlreqwake (dlreqwake),
.dlrpbufemp (dlrpbufemp),
.dlrstentercompbit (tlbp_dl_rst_enter_comp_bit),
.dlrsttxmarginfield (tlbp_dl_rst_tx_margin_field),
.dlrxecrcchk (dlrxecrcchk),
.dlrxtyppm (dlrxtyppm),
.dlrxvalpm (dlrxvalpm),
.dlsndupfc (dlsndupfc),
.dltxackpm (dltxackpm),
.dltxcfgextsy (dltxcfgextsy),
.dltxreqpm (dltxreqpm),
.dltxtyppm (dltxtyppm),
.dltypupfc (dltypupfc),
.dlup (dlup),
.dlupexit (dlup_exit),
.dlvcctrl (dlvcctrl),
.dlvcidmap (dlvcidmap),
.dlvcidupfc (dlvcidupfc),
.dlvcstatus (dlvcstatus),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout),
.dpriostate (open_dpriostate),
.eidleinfersel (eidle_infer_sel),
.ev128ns (ev_128ns),
.ev1us (ev_1us),
.extraclkout (hip_extraclkout),
.extraout (hip_extraout),
.gen2rate (gen2rate),
.gen2rategnd (open_gen2rategnd),
.hotrstexit (hotrst_exit),
.intstatus (int_status),
.l2exit (l2_exit),
.laneact (lane_act),
.linkup (linkup),
.lmiack (lmi_ack),
.lmiaddr (lmi_addr),
.lmidin (lmi_din),
.lmidout (lmi_dout),
.lmirden (lmi_rden),
.lmiwren (lmi_wren),
.ltssml0state (ltssml0state),
.mode (mode),
.mramhiptestenable (gnd_mram_hip_test_enable),
.mramregscanen (gnd_mramregscanen),
.mramregscanin (gnd_mramregscanin),
.mramregscanout (open_mramregscanout),
.pclkcentral (pclk_central),
.pclkch0 (pclk_ch0),
.phyrst (phy_rst),
.physrst (phy_srst),
.phystatus (phystatus),
.pldclk (pld_clk),
.pldrst (pld_rst),
.pldsrst (pld_srst),
.pllfixedclk (pll_fixed_clk),
.powerdown (powerdown),
.r2cerr0ext (r2cerr0ext_cycloneiv),
.resetstatus (reset_status),
.rxbardecvc0 (rx_st_bardec0),
.rxbardecvc1 (rx_st_bardec1),
.rxbevc00 (rx_st_be0),
.rxbevc01 (rx_st_be0_p1),
.rxbevc10 (rx_st_be1),
.rxbevc11 (rx_st_be1_p1),
.rxdata (rxdata),
.rxdatak (rxdatak),
.rxdatavc00 (rx_st_data0),
.rxdatavc01 (rx_st_data0_p1),
.rxdatavc10 (rx_st_data1),
.rxdatavc11 (rx_st_data1_p1),
.rxelecidle (rxelecidle),
.rxeopvc00 (rx_st_eop0),
.rxeopvc01 (rx_st_eop0_p1),
.rxeopvc10 (rx_st_eop1),
.rxeopvc11 (rx_st_eop1_p1),
.rxerrvc0 (rx_st_err0),
.rxerrvc1 (rx_st_err1),
.rxfifoemptyvc0 (rx_fifo_empty0),
.rxfifoemptyvc1 (rx_fifo_empty1),
.rxfifofullvc0 (rx_fifo_full0),
.rxfifofullvc1 (rx_fifo_full1),
.rxfifordpvc0 (open_rxfifordpvc0),
.rxfifordpvc1 (open_rxfifordpvc1),
.rxfifowrpvc0 (open_rxfifowrpvc0),
.rxfifowrpvc1 (open_rxfifowrpvc1),
.rxmaskvc0 (rx_st_mask0_int),
.rxmaskvc1 (rx_st_mask1),
.rxpolarity (rxpolarity),
.rxreadyvc0 (rx_st_ready0_int),
.rxreadyvc1 (rx_st_ready1),
.rxsopvc00 (rx_st_sop0),
.rxsopvc01 (rx_st_sop0_p1),
.rxsopvc10 (rx_st_sop1),
.rxsopvc11 (rx_st_sop1_p1),
.rxstatus (rxstatus),
.rxvalid (rxvalid),
.rxvalidvc0 (rx_st_valid0),
.rxvalidvc1 (rx_st_valid1),
.scanen (gnd_scanen),
.scanmoden (scanmoden),
.serrout (serr_out),
.successspeednegoint(successspeednegoint),
.swdnin (swdn_in_int),
.swdnwake (swdn_wake),
.swuphotrst (swup_hotrst),
.swupin (swup_in_int),
.testin (test_in),
.testout (test_out),
.tlaermsinum (aer_msi_num_int),
.tlappintaack (app_int_ack),
.tlappintasts (app_int_sts_int),
.tlappmsiack (app_msi_ack),
.tlappmsinum (app_msi_num),
.tlappmsireq (app_msi_req_int),
.tlappmsitc (app_msi_tc_int),
.tlcfgadd (tl_cfg_add_hip),
.tlcfgctl (tl_cfg_ctl_hip),
.tlcfgctlwr (tl_cfg_ctl_wr_hip),
.tlcfgsts (tl_cfg_sts_hip),
.tlcfgstswr (tl_cfg_sts_wr_hip),
.tlhpgctrler (hpg_ctrler),
.tlpexmsinum (pex_msi_num),
.tlpmauxpwr (pm_auxpwr),
.tlpmdata (pm_data),
.tlpmetocr (pme_to_cr_int),
.tlpmetosr (pme_to_sr),
.tlpmevent (pm_event_int),
.tlslotclkcfg (tl_slotclk_cfg),
.txcompl (txcompl),
.txcredvc0 (tx_cred0_int),
.txcredvc1 (tx_cred1_int),
.txdata (txdata),
.txdatak (txdatak),
.txdatavc00 (tx_st_data0_int),
.txdatavc01 (tx_st_data0_p1),
.txdatavc10 (tx_st_data1),
.txdatavc11 (tx_st_data1_p1),
.txdeemph (tx_deemph),
.txdetectrx (txdetectrx),
.txelecidle (txelecidle),
.txeopvc00 (tx_st_eop0_int),
.txeopvc01 (tx_st_eop0_p1),
.txeopvc10 (tx_st_eop1),
.txeopvc11 (tx_st_eop1_p1),
.txerrvc0 (tx_st_err0_int),
.txerrvc1 (tx_st_err1),
.txfifoemptyvc0 (tx_fifo_empty0),
.txfifoemptyvc1 (tx_fifo_empty1),
.txfifofullvc0 (tx_fifo_full0),
.txfifofullvc1 (tx_fifo_full1),
.txfifordpvc0 (tx_fifo_rdptr0),
.txfifordpvc1 (tx_fifo_rdptr1),
.txfifowrpvc0 (tx_fifo_wrptr0),
.txfifowrpvc1 (tx_fifo_wrptr1),
.txmargin (tx_margin),
.txreadyvc0 (tx_st_ready0),
.txreadyvc1 (tx_st_ready1),
.txsopvc00 (tx_st_sop0_int),
.txsopvc01 (tx_st_sop0_p1),
.txsopvc10 (tx_st_sop1),
.txsopvc11 (tx_st_sop1_p1),
.txvalidvc0 (tx_st_valid0_int),
.txvalidvc1 (tx_st_valid1),
.wakeoen (wake_oen)
);
defparam cycloneiv_hssi_pcie_hip.advanced_errors = advanced_errors,
cycloneiv_hssi_pcie_hip.bar0_64bit_mem_space = bar0_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar0_io_space = bar0_io_space,
cycloneiv_hssi_pcie_hip.bar0_prefetchable = bar0_prefetchable,
cycloneiv_hssi_pcie_hip.bar0_size_mask = bar0_size_mask,
cycloneiv_hssi_pcie_hip.bar1_64bit_mem_space = bar1_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar1_io_space = bar1_io_space,
cycloneiv_hssi_pcie_hip.bar1_prefetchable = bar1_prefetchable,
cycloneiv_hssi_pcie_hip.bar1_size_mask = bar1_size_mask,
cycloneiv_hssi_pcie_hip.bar2_64bit_mem_space = bar2_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar2_io_space = bar2_io_space,
cycloneiv_hssi_pcie_hip.bar2_prefetchable = bar2_prefetchable,
cycloneiv_hssi_pcie_hip.bar2_size_mask = bar2_size_mask,
cycloneiv_hssi_pcie_hip.bar3_64bit_mem_space = bar3_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar3_io_space = bar3_io_space,
cycloneiv_hssi_pcie_hip.bar3_prefetchable = bar3_prefetchable,
cycloneiv_hssi_pcie_hip.bar3_size_mask = bar3_size_mask,
cycloneiv_hssi_pcie_hip.bar4_64bit_mem_space = bar4_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar4_io_space = bar4_io_space,
cycloneiv_hssi_pcie_hip.bar4_prefetchable = bar4_prefetchable,
cycloneiv_hssi_pcie_hip.bar4_size_mask = bar4_size_mask,
cycloneiv_hssi_pcie_hip.bar5_64bit_mem_space = bar5_64bit_mem_space,
cycloneiv_hssi_pcie_hip.bar5_io_space = bar5_io_space,
cycloneiv_hssi_pcie_hip.bar5_prefetchable = bar5_prefetchable,
cycloneiv_hssi_pcie_hip.bar5_size_mask = bar5_size_mask,
cycloneiv_hssi_pcie_hip.bar_io_window_size = bar_io_window_size,
cycloneiv_hssi_pcie_hip.bar_prefetchable = bar_prefetchable,
cycloneiv_hssi_pcie_hip.bridge_port_ssid_support = bridge_port_ssid_support,
cycloneiv_hssi_pcie_hip.bridge_port_vga_enable = bridge_port_vga_enable,
cycloneiv_hssi_pcie_hip.bypass_cdc = bypass_cdc,
cycloneiv_hssi_pcie_hip.tx_cdc_full_value = tx_cdc_full_value ,
cycloneiv_hssi_pcie_hip.bypass_tl = bypass_tl,
cycloneiv_hssi_pcie_hip.class_code = class_code,
cycloneiv_hssi_pcie_hip.completion_timeout = completion_timeout,
cycloneiv_hssi_pcie_hip.core_clk_divider = core_clk_divider,
cycloneiv_hssi_pcie_hip.core_clk_source = core_clk_source,
cycloneiv_hssi_pcie_hip.credit_buffer_allocation_aux = credit_buffer_allocation_aux,
cycloneiv_hssi_pcie_hip.deemphasis_enable = deemphasis_enable,
cycloneiv_hssi_pcie_hip.device_id = device_id,
cycloneiv_hssi_pcie_hip.device_number = device_number,
cycloneiv_hssi_pcie_hip.diffclock_nfts_count = diffclock_nfts_count,
cycloneiv_hssi_pcie_hip.disable_cdc_clk_ppm = disable_cdc_clk_ppm,
cycloneiv_hssi_pcie_hip.disable_link_x2_support = disable_link_x2_support,
cycloneiv_hssi_pcie_hip.disable_snoop_packet = disable_snoop_packet,
cycloneiv_hssi_pcie_hip.dll_active_report_support = dll_active_report_support,
cycloneiv_hssi_pcie_hip.ei_delay_powerdown_count = ei_delay_powerdown_count,
cycloneiv_hssi_pcie_hip.eie_before_nfts_count = eie_before_nfts_count,
cycloneiv_hssi_pcie_hip.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode,
cycloneiv_hssi_pcie_hip.enable_ch0_pclk_out = enable_ch0_pclk_out,
cycloneiv_hssi_pcie_hip.enable_completion_timeout_disable = enable_completion_timeout_disable,
cycloneiv_hssi_pcie_hip.enable_coreclk_out_half_rate = enable_coreclk_out_half_rate,
cycloneiv_hssi_pcie_hip.enable_ecrc_check = enable_ecrc_check,
cycloneiv_hssi_pcie_hip.enable_ecrc_gen = enable_ecrc_gen,
cycloneiv_hssi_pcie_hip.enable_function_msi_support = enable_function_msi_support,
cycloneiv_hssi_pcie_hip.enable_function_msix_support = enable_function_msix_support,
cycloneiv_hssi_pcie_hip.enable_gen2_core = enable_gen2_core,
cycloneiv_hssi_pcie_hip.enable_hip_x1_loopback = enable_hip_x1_loopback,
cycloneiv_hssi_pcie_hip.enable_l1_aspm = enable_l1_aspm,
cycloneiv_hssi_pcie_hip.enable_msi_64bit_addressing = enable_msi_64bit_addressing,
cycloneiv_hssi_pcie_hip.enable_msi_masking = enable_msi_masking,
cycloneiv_hssi_pcie_hip.enable_retrybuf_ecc = enable_retrybuf_ecc,
cycloneiv_hssi_pcie_hip.enable_retrybuf_x8_clk_stealing = enable_retrybuf_x8_clk_stealing,
cycloneiv_hssi_pcie_hip.enable_rx0buf_ecc = enable_rx0buf_ecc,
cycloneiv_hssi_pcie_hip.enable_rx0buf_x8_clk_stealing = enable_rx0buf_x8_clk_stealing,
cycloneiv_hssi_pcie_hip.enable_rx1buf_ecc = enable_rx1buf_ecc,
cycloneiv_hssi_pcie_hip.enable_rx1buf_x8_clk_stealing = enable_rx1buf_x8_clk_stealing,
cycloneiv_hssi_pcie_hip.enable_rx_buffer_checking = enable_rx_buffer_checking,
cycloneiv_hssi_pcie_hip.enable_rx_reordering = enable_rx_reordering,
cycloneiv_hssi_pcie_hip.enable_slot_register = enable_slot_register,
cycloneiv_hssi_pcie_hip.endpoint_l0_latency = endpoint_l0_latency,
cycloneiv_hssi_pcie_hip.endpoint_l1_latency = endpoint_l1_latency,
cycloneiv_hssi_pcie_hip.expansion_base_address_register = expansion_base_address_register,
cycloneiv_hssi_pcie_hip.extend_tag_field = extend_tag_field,
cycloneiv_hssi_pcie_hip.fc_init_timer = fc_init_timer,
cycloneiv_hssi_pcie_hip.flow_control_timeout_count = flow_control_timeout_count,
cycloneiv_hssi_pcie_hip.flow_control_update_count = flow_control_update_count,
cycloneiv_hssi_pcie_hip.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count,
cycloneiv_hssi_pcie_hip.gen2_lane_rate_mode = gen2_lane_rate_mode,
cycloneiv_hssi_pcie_hip.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count,
cycloneiv_hssi_pcie_hip.hot_plug_support = hot_plug_support,
cycloneiv_hssi_pcie_hip.indicator = indicator,
cycloneiv_hssi_pcie_hip.l01_entry_latency = l01_entry_latency,
cycloneiv_hssi_pcie_hip.l0_exit_latency_diffclock = l0_exit_latency_diffclock,
cycloneiv_hssi_pcie_hip.l0_exit_latency_sameclock = l0_exit_latency_sameclock,
cycloneiv_hssi_pcie_hip.l1_exit_latency_diffclock = l1_exit_latency_diffclock,
cycloneiv_hssi_pcie_hip.l1_exit_latency_sameclock = l1_exit_latency_sameclock,
cycloneiv_hssi_pcie_hip.lane_mask = lane_mask,
cycloneiv_hssi_pcie_hip.low_priority_vc = low_priority_vc,
cycloneiv_hssi_pcie_hip.lpm_type = lpm_type,
cycloneiv_hssi_pcie_hip.max_link_width = max_link_width,
cycloneiv_hssi_pcie_hip.max_payload_size = max_payload_size,
cycloneiv_hssi_pcie_hip.maximum_current = maximum_current,
cycloneiv_hssi_pcie_hip.millisecond_cycle_count = millisecond_cycle_count,
cycloneiv_hssi_pcie_hip.msi_function_count = msi_function_count,
cycloneiv_hssi_pcie_hip.msix_pba_bir = msix_pba_bir,
cycloneiv_hssi_pcie_hip.msix_pba_offset = msix_pba_offset,
cycloneiv_hssi_pcie_hip.msix_table_bir = msix_table_bir,
cycloneiv_hssi_pcie_hip.msix_table_offset = msix_table_offset,
cycloneiv_hssi_pcie_hip.msix_table_size = msix_table_size,
cycloneiv_hssi_pcie_hip.no_command_completed = no_command_completed,
cycloneiv_hssi_pcie_hip.no_soft_reset = no_soft_reset,
cycloneiv_hssi_pcie_hip.pcie_mode = pcie_mode,
cycloneiv_hssi_pcie_hip.pme_state_enable = pme_state_enable,
cycloneiv_hssi_pcie_hip.port_link_number = port_link_number,
cycloneiv_hssi_pcie_hip.register_pipe_signals = register_pipe_signals,
cycloneiv_hssi_pcie_hip.retry_buffer_last_active_address = retry_buffer_last_active_address,
cycloneiv_hssi_pcie_hip.retry_buffer_memory_settings = retry_buffer_memory_settings,
cycloneiv_hssi_pcie_hip.revision_id = revision_id,
cycloneiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max,
cycloneiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min,
cycloneiv_hssi_pcie_hip.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max,
cycloneiv_hssi_pcie_hip.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min,
cycloneiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_max = rx_ptr1_nonposted_dpram_max,
cycloneiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_min = rx_ptr1_nonposted_dpram_min,
cycloneiv_hssi_pcie_hip.rx_ptr1_posted_dpram_max = rx_ptr1_posted_dpram_max,
cycloneiv_hssi_pcie_hip.rx_ptr1_posted_dpram_min = rx_ptr1_posted_dpram_min,
cycloneiv_hssi_pcie_hip.sameclock_nfts_count = sameclock_nfts_count,
cycloneiv_hssi_pcie_hip.single_rx_detect = single_rx_detect,
cycloneiv_hssi_pcie_hip.skp_os_schedule_count = skp_os_schedule_count,
cycloneiv_hssi_pcie_hip.slot_number = slot_number,
cycloneiv_hssi_pcie_hip.slot_power_limit = slot_power_limit,
cycloneiv_hssi_pcie_hip.slot_power_scale = slot_power_scale,
cycloneiv_hssi_pcie_hip.ssid = ssid,
cycloneiv_hssi_pcie_hip.ssvid = ssvid,
cycloneiv_hssi_pcie_hip.subsystem_device_id = subsystem_device_id,
cycloneiv_hssi_pcie_hip.subsystem_vendor_id = subsystem_vendor_id,
cycloneiv_hssi_pcie_hip.surprise_down_error_support = surprise_down_error_support,
cycloneiv_hssi_pcie_hip.use_crc_forwarding = use_crc_forwarding,
cycloneiv_hssi_pcie_hip.vc0_clk_enable = vc0_clk_enable,
cycloneiv_hssi_pcie_hip.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data,
cycloneiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header,
cycloneiv_hssi_pcie_hip.vc1_clk_enable = vc1_clk_enable,
cycloneiv_hssi_pcie_hip.vc1_rx_buffer_memory_settings = vc1_rx_buffer_memory_settings,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_data = vc1_rx_flow_ctrl_compl_data,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_header = vc1_rx_flow_ctrl_compl_header,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_data = vc1_rx_flow_ctrl_nonposted_data,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_header = vc1_rx_flow_ctrl_nonposted_header,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_data = vc1_rx_flow_ctrl_posted_data,
cycloneiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_header = vc1_rx_flow_ctrl_posted_header,
cycloneiv_hssi_pcie_hip.vc_arbitration = vc_arbitration,
cycloneiv_hssi_pcie_hip.vc_enable = vc_enable,
cycloneiv_hssi_pcie_hip.vendor_id = vendor_id;
end
endgenerate
generate
if (p_pcie_hip_type == "3")
begin : hc_iv
hardcopyiv_hssi_pcie_hip hardcopyiv_hssi_pcie_hip
(
.bistdonearcv0 (open_bistdonearcv0),
.bistdonearcv1 (open_bistdonearcv1),
.bistdonearpl (open_bistdonearpl),
.bistdonebrcv0 (open_bistdonebrcv0),
.bistdonebrcv1 (open_bistdonebrcv1),
.bistdonebrpl (open_bistdonebrpl),
.bistenrcv0 (gnd_bistenrcv0),
.bistenrcv1 (gnd_bistenrcv1),
.bistenrpl (gnd_bistenrpl),
.bistpassrcv0 (open_bistpassrcv0),
.bistpassrcv1 (open_bistpassrcv1),
.bistpassrpl (open_bistpassrpl),
.bistscanen (gnd_bistscanen),
.bistscanin (gnd_bistscanin),
.bistscanoutrcv0 (open_bistscanoutrcv0),
.bistscanoutrcv1 (open_bistscanoutrcv1),
.bistscanoutrpl (open_bistscanoutrpl),
.bisttesten (gnd_bisttesten),
.clrrxpath (clrrxpath),
.coreclkin (core_clk_in),
.coreclkout (core_clk_out),
.corecrst (core_crst),
.corepor (core_por),
.corerst (core_rst),
.coresrst (core_srst),
.cplerr (cpl_err),
.cplpending (cpl_pending_int),
.dataenablen (open_dataenablen),
.dbgpipex1rx (dbgpipex1rx),
.derrcorextrcv0 (derr_cor_ext_rcv0),
.derrcorextrcv1 (derr_cor_ext_rcv1),
.derrcorextrpl (derr_cor_ext_rpl),
.derrrpl (derr_rpl),
.dlackphypm (dlackphypm),
.dlackrequpfc (dlackrequpfc),
.dlacksndupfc (dlacksndupfc),
.dlaspmcr0 (tlbp_dl_aspm_cr0),
.dlcomclkreg (tlbp_dl_comclk_reg),
.dlctrllink2 (dlctrllink2),
.dlcurrentdeemp (dlcurrentdeemp),
.dlcurrentspeed (dlcurrentspeed),
.dldataupfc (dldataupfc),
.dldllreq (dldllreq),
.dlerrdll (dlerrdll),
.dlerrphy (dlerrphy),
.dlhdrupfc (dlhdrupfc),
.dlinhdllp (dlinhdllp),
.dllinkautobdwstatus (tlbp_dl_link_autobdw_status),
.dllinkbdwmngstatus (tlbp_dl_link_bdwmng_status),
.dlltssm (dl_ltssm),
.dlmaxploaddcr (tlbp_dl_maxpload_dcr),
.dlreqphycfg (dlreqphycfg),
.dlreqphypm (dlreqphypm),
.dlrequpfc (dlrequpfc),
.dlreqwake (dlreqwake),
.dlrpbufemp (dlrpbufemp),
.dlrstentercompbit (tlbp_dl_rst_enter_comp_bit),
.dlrsttxmarginfield (tlbp_dl_rst_tx_margin_field),
.dlrxecrcchk (dlrxecrcchk),
.dlrxtyppm (dlrxtyppm),
.dlrxvalpm (dlrxvalpm),
.dlsndupfc (dlsndupfc),
.dltxackpm (dltxackpm),
.dltxcfgextsy (dltxcfgextsy),
.dltxreqpm (dltxreqpm),
.dltxtyppm (dltxtyppm),
.dltypupfc (dltypupfc),
.dlup (dlup),
.dlupexit (dlup_exit),
.dlvcctrl (dlvcctrl),
.dlvcidmap (dlvcidmap),
.dlvcidupfc (dlvcidupfc),
.dlvcstatus (dlvcstatus),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout),
.dpriostate (open_dpriostate),
.eidleinfersel (eidle_infer_sel),
.ev128ns (ev_128ns),
.ev1us (ev_1us),
.extraclkout (hip_extraclkout),
.extraout (hip_extraout),
.gen2rate (gen2rate),
.gen2rategnd (open_gen2rategnd),
.hotrstexit (hotrst_exit),
.intstatus (int_status),
.l2exit (l2_exit),
.laneact (lane_act),
.linkup (linkup),
.lmiack (lmi_ack),
.lmiaddr (lmi_addr),
.lmidin (lmi_din),
.lmidout (lmi_dout),
.lmirden (lmi_rden),
.lmiwren (lmi_wren),
.ltssml0state (ltssml0state),
.mode (mode),
.mramhiptestenable (gnd_mram_hip_test_enable),
.mramregscanen (gnd_mramregscanen),
.mramregscanin (gnd_mramregscanin),
.mramregscanout (open_mramregscanout),
.pclkcentral (pclk_central),
.pclkch0 (pclk_ch0),
.phyrst (phy_rst),
.physrst (phy_srst),
.phystatus (phystatus),
.pldclk (pld_clk),
.pldrst (pld_rst),
.pldsrst (pld_srst),
.pllfixedclk (pll_fixed_clk),
.powerdown (powerdown),
.resetstatus (reset_status),
.rxbardecvc0 (rx_st_bardec0),
.rxbardecvc1 (rx_st_bardec1),
.rxbevc00 (rx_st_be0),
.rxbevc01 (rx_st_be0_p1),
.rxbevc10 (rx_st_be1),
.rxbevc11 (rx_st_be1_p1),
.rxdata (rxdata),
.rxdatak (rxdatak),
.rxdatavc00 (rx_st_data0),
.rxdatavc01 (rx_st_data0_p1),
.rxdatavc10 (rx_st_data1),
.rxdatavc11 (rx_st_data1_p1),
.rxelecidle (rxelecidle),
.rxeopvc00 (rx_st_eop0),
.rxeopvc01 (rx_st_eop0_p1),
.rxeopvc10 (rx_st_eop1),
.rxeopvc11 (rx_st_eop1_p1),
.rxerrvc0 (rx_st_err0),
.rxerrvc1 (rx_st_err1),
.rxfifoemptyvc0 (rx_fifo_empty0),
.rxfifoemptyvc1 (rx_fifo_empty1),
.rxfifofullvc0 (rx_fifo_full0),
.rxfifofullvc1 (rx_fifo_full1),
.rxfifordpvc0 (open_rxfifordpvc0),
.rxfifordpvc1 (open_rxfifordpvc1),
.rxfifowrpvc0 (open_rxfifowrpvc0),
.rxfifowrpvc1 (open_rxfifowrpvc1),
.rxmaskvc0 (rx_st_mask0_int),
.rxmaskvc1 (rx_st_mask1),
.rxpolarity (rxpolarity),
.rxreadyvc0 (rx_st_ready0_int),
.rxreadyvc1 (rx_st_ready1),
.rxsopvc00 (rx_st_sop0),
.rxsopvc01 (rx_st_sop0_p1),
.rxsopvc10 (rx_st_sop1),
.rxsopvc11 (rx_st_sop1_p1),
.rxstatus (rxstatus),
.rxvalid (rxvalid),
.rxvalidvc0 (rx_st_valid0),
.rxvalidvc1 (rx_st_valid1),
.scanen (gnd_scanen),
.scanmoden (scanmoden),
.serrout (serr_out),
.swdnin (swdn_in_int),
.swdnwake (swdn_wake),
.swuphotrst (swup_hotrst),
.swupin (swup_in_int),
.testin (test_in),
.testout (test_out),
.tlaermsinum (aer_msi_num_int),
.tlappintaack (app_int_ack),
.tlappintasts (app_int_sts_int),
.tlappmsiack (app_msi_ack),
.tlappmsinum (app_msi_num),
.tlappmsireq (app_msi_req_int),
.tlappmsitc (app_msi_tc_int),
.tlcfgadd (tl_cfg_add_hip),
.tlcfgctl (tl_cfg_ctl_hip),
.tlcfgctlwr (tl_cfg_ctl_wr_hip),
.tlcfgsts (tl_cfg_sts_hip),
.tlcfgstswr (tl_cfg_sts_wr_hip),
.tlhpgctrler (hpg_ctrler),
.tlpexmsinum (pex_msi_num),
.tlpmauxpwr (pm_auxpwr),
.tlpmdata (pm_data),
.tlpmetocr (pme_to_cr_int),
.tlpmetosr (pme_to_sr),
.tlpmevent (pm_event_int),
.tlslotclkcfg (tl_slotclk_cfg),
.txcompl (txcompl),
.txcredvc0 (tx_cred0_int),
.txcredvc1 (tx_cred1_int),
.txdata (txdata),
.txdatak (txdatak),
.txdatavc00 (tx_st_data0_int),
.txdatavc01 (tx_st_data0_p1),
.txdatavc10 (tx_st_data1),
.txdatavc11 (tx_st_data1_p1),
.txdeemph (tx_deemph),
.txdetectrx (txdetectrx),
.txelecidle (txelecidle),
.txeopvc00 (tx_st_eop0_int),
.txeopvc01 (tx_st_eop0_p1),
.txeopvc10 (tx_st_eop1),
.txeopvc11 (tx_st_eop1_p1),
.txerrvc0 (tx_st_err0_int),
.txerrvc1 (tx_st_err1),
.txfifoemptyvc0 (tx_fifo_empty0),
.txfifoemptyvc1 (tx_fifo_empty1),
.txfifofullvc0 (tx_fifo_full0),
.txfifofullvc1 (tx_fifo_full1),
.txfifordpvc0 (tx_fifo_rdptr0),
.txfifordpvc1 (tx_fifo_rdptr1),
.txfifowrpvc0 (tx_fifo_wrptr0),
.txfifowrpvc1 (tx_fifo_wrptr1),
.txmargin (tx_margin),
.txreadyvc0 (tx_st_ready0),
.txreadyvc1 (tx_st_ready1),
.txsopvc00 (tx_st_sop0_int),
.txsopvc01 (tx_st_sop0_p1),
.txsopvc10 (tx_st_sop1),
.txsopvc11 (tx_st_sop1_p1),
.txvalidvc0 (tx_st_valid0_int),
.txvalidvc1 (tx_st_valid1),
.wakeoen (wake_oen)
);
defparam hardcopyiv_hssi_pcie_hip.advanced_errors = advanced_errors,
hardcopyiv_hssi_pcie_hip.bar0_64bit_mem_space = bar0_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar0_io_space = bar0_io_space,
hardcopyiv_hssi_pcie_hip.bar0_prefetchable = bar0_prefetchable,
hardcopyiv_hssi_pcie_hip.bar0_size_mask = bar0_size_mask,
hardcopyiv_hssi_pcie_hip.bar1_64bit_mem_space = bar1_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar1_io_space = bar1_io_space,
hardcopyiv_hssi_pcie_hip.bar1_prefetchable = bar1_prefetchable,
hardcopyiv_hssi_pcie_hip.bar1_size_mask = bar1_size_mask,
hardcopyiv_hssi_pcie_hip.bar2_64bit_mem_space = bar2_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar2_io_space = bar2_io_space,
hardcopyiv_hssi_pcie_hip.bar2_prefetchable = bar2_prefetchable,
hardcopyiv_hssi_pcie_hip.bar2_size_mask = bar2_size_mask,
hardcopyiv_hssi_pcie_hip.bar3_64bit_mem_space = bar3_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar3_io_space = bar3_io_space,
hardcopyiv_hssi_pcie_hip.bar3_prefetchable = bar3_prefetchable,
hardcopyiv_hssi_pcie_hip.bar3_size_mask = bar3_size_mask,
hardcopyiv_hssi_pcie_hip.bar4_64bit_mem_space = bar4_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar4_io_space = bar4_io_space,
hardcopyiv_hssi_pcie_hip.bar4_prefetchable = bar4_prefetchable,
hardcopyiv_hssi_pcie_hip.bar4_size_mask = bar4_size_mask,
hardcopyiv_hssi_pcie_hip.bar5_64bit_mem_space = bar5_64bit_mem_space,
hardcopyiv_hssi_pcie_hip.bar5_io_space = bar5_io_space,
hardcopyiv_hssi_pcie_hip.bar5_prefetchable = bar5_prefetchable,
hardcopyiv_hssi_pcie_hip.bar5_size_mask = bar5_size_mask,
hardcopyiv_hssi_pcie_hip.bar_io_window_size = bar_io_window_size,
hardcopyiv_hssi_pcie_hip.bar_prefetchable = bar_prefetchable,
hardcopyiv_hssi_pcie_hip.bridge_port_ssid_support = bridge_port_ssid_support,
hardcopyiv_hssi_pcie_hip.bridge_port_vga_enable = bridge_port_vga_enable,
hardcopyiv_hssi_pcie_hip.bypass_cdc = bypass_cdc,
hardcopyiv_hssi_pcie_hip.tx_cdc_full_value = tx_cdc_full_value ,
hardcopyiv_hssi_pcie_hip.bypass_tl = bypass_tl,
hardcopyiv_hssi_pcie_hip.class_code = class_code,
hardcopyiv_hssi_pcie_hip.completion_timeout = completion_timeout,
hardcopyiv_hssi_pcie_hip.core_clk_divider = core_clk_divider,
hardcopyiv_hssi_pcie_hip.core_clk_source = core_clk_source,
hardcopyiv_hssi_pcie_hip.credit_buffer_allocation_aux = credit_buffer_allocation_aux,
hardcopyiv_hssi_pcie_hip.deemphasis_enable = deemphasis_enable,
hardcopyiv_hssi_pcie_hip.device_id = device_id,
hardcopyiv_hssi_pcie_hip.device_number = device_number,
hardcopyiv_hssi_pcie_hip.diffclock_nfts_count = diffclock_nfts_count,
hardcopyiv_hssi_pcie_hip.disable_cdc_clk_ppm = disable_cdc_clk_ppm,
hardcopyiv_hssi_pcie_hip.disable_link_x2_support = disable_link_x2_support,
hardcopyiv_hssi_pcie_hip.disable_snoop_packet = disable_snoop_packet,
hardcopyiv_hssi_pcie_hip.dll_active_report_support = dll_active_report_support,
hardcopyiv_hssi_pcie_hip.ei_delay_powerdown_count = ei_delay_powerdown_count,
hardcopyiv_hssi_pcie_hip.eie_before_nfts_count = eie_before_nfts_count,
hardcopyiv_hssi_pcie_hip.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode,
hardcopyiv_hssi_pcie_hip.enable_ch0_pclk_out = enable_ch0_pclk_out,
hardcopyiv_hssi_pcie_hip.enable_completion_timeout_disable = enable_completion_timeout_disable,
hardcopyiv_hssi_pcie_hip.enable_coreclk_out_half_rate = enable_coreclk_out_half_rate,
hardcopyiv_hssi_pcie_hip.enable_ecrc_check = enable_ecrc_check,
hardcopyiv_hssi_pcie_hip.enable_ecrc_gen = enable_ecrc_gen,
hardcopyiv_hssi_pcie_hip.enable_function_msi_support = enable_function_msi_support,
hardcopyiv_hssi_pcie_hip.enable_function_msix_support = enable_function_msix_support,
hardcopyiv_hssi_pcie_hip.enable_gen2_core = enable_gen2_core,
hardcopyiv_hssi_pcie_hip.enable_hip_x1_loopback = enable_hip_x1_loopback,
hardcopyiv_hssi_pcie_hip.enable_l1_aspm = enable_l1_aspm,
hardcopyiv_hssi_pcie_hip.enable_msi_64bit_addressing = enable_msi_64bit_addressing,
hardcopyiv_hssi_pcie_hip.enable_msi_masking = enable_msi_masking,
hardcopyiv_hssi_pcie_hip.enable_retrybuf_ecc = enable_retrybuf_ecc,
hardcopyiv_hssi_pcie_hip.enable_retrybuf_x8_clk_stealing = enable_retrybuf_x8_clk_stealing,
hardcopyiv_hssi_pcie_hip.enable_rx0buf_ecc = enable_rx0buf_ecc,
hardcopyiv_hssi_pcie_hip.enable_rx0buf_x8_clk_stealing = enable_rx0buf_x8_clk_stealing,
hardcopyiv_hssi_pcie_hip.enable_rx1buf_ecc = enable_rx1buf_ecc,
hardcopyiv_hssi_pcie_hip.enable_rx1buf_x8_clk_stealing = enable_rx1buf_x8_clk_stealing,
hardcopyiv_hssi_pcie_hip.enable_rx_buffer_checking = enable_rx_buffer_checking,
hardcopyiv_hssi_pcie_hip.enable_rx_reordering = enable_rx_reordering,
hardcopyiv_hssi_pcie_hip.enable_slot_register = enable_slot_register,
hardcopyiv_hssi_pcie_hip.endpoint_l0_latency = endpoint_l0_latency,
hardcopyiv_hssi_pcie_hip.endpoint_l1_latency = endpoint_l1_latency,
hardcopyiv_hssi_pcie_hip.expansion_base_address_register = expansion_base_address_register,
hardcopyiv_hssi_pcie_hip.extend_tag_field = extend_tag_field,
hardcopyiv_hssi_pcie_hip.fc_init_timer = fc_init_timer,
hardcopyiv_hssi_pcie_hip.flow_control_timeout_count = flow_control_timeout_count,
hardcopyiv_hssi_pcie_hip.flow_control_update_count = flow_control_update_count,
hardcopyiv_hssi_pcie_hip.gen2_diffclock_nfts_count = gen2_diffclock_nfts_count,
hardcopyiv_hssi_pcie_hip.gen2_lane_rate_mode = gen2_lane_rate_mode,
hardcopyiv_hssi_pcie_hip.gen2_sameclock_nfts_count = gen2_sameclock_nfts_count,
hardcopyiv_hssi_pcie_hip.hot_plug_support = hot_plug_support,
hardcopyiv_hssi_pcie_hip.indicator = indicator,
hardcopyiv_hssi_pcie_hip.l01_entry_latency = l01_entry_latency,
hardcopyiv_hssi_pcie_hip.l0_exit_latency_diffclock = l0_exit_latency_diffclock,
hardcopyiv_hssi_pcie_hip.l0_exit_latency_sameclock = l0_exit_latency_sameclock,
hardcopyiv_hssi_pcie_hip.l1_exit_latency_diffclock = l1_exit_latency_diffclock,
hardcopyiv_hssi_pcie_hip.l1_exit_latency_sameclock = l1_exit_latency_sameclock,
hardcopyiv_hssi_pcie_hip.lane_mask = lane_mask,
hardcopyiv_hssi_pcie_hip.low_priority_vc = low_priority_vc,
hardcopyiv_hssi_pcie_hip.lpm_type = lpm_type,
hardcopyiv_hssi_pcie_hip.max_link_width = max_link_width,
hardcopyiv_hssi_pcie_hip.max_payload_size = max_payload_size,
hardcopyiv_hssi_pcie_hip.maximum_current = maximum_current,
hardcopyiv_hssi_pcie_hip.millisecond_cycle_count = millisecond_cycle_count,
hardcopyiv_hssi_pcie_hip.msi_function_count = msi_function_count,
hardcopyiv_hssi_pcie_hip.msix_pba_bir = msix_pba_bir,
hardcopyiv_hssi_pcie_hip.msix_pba_offset = msix_pba_offset,
hardcopyiv_hssi_pcie_hip.msix_table_bir = msix_table_bir,
hardcopyiv_hssi_pcie_hip.msix_table_offset = msix_table_offset,
hardcopyiv_hssi_pcie_hip.msix_table_size = msix_table_size,
hardcopyiv_hssi_pcie_hip.no_command_completed = no_command_completed,
hardcopyiv_hssi_pcie_hip.no_soft_reset = no_soft_reset,
hardcopyiv_hssi_pcie_hip.pcie_mode = pcie_mode,
hardcopyiv_hssi_pcie_hip.pme_state_enable = pme_state_enable,
hardcopyiv_hssi_pcie_hip.port_link_number = port_link_number,
hardcopyiv_hssi_pcie_hip.register_pipe_signals = register_pipe_signals,
hardcopyiv_hssi_pcie_hip.retry_buffer_last_active_address = retry_buffer_last_active_address,
hardcopyiv_hssi_pcie_hip.retry_buffer_memory_settings = retry_buffer_memory_settings,
hardcopyiv_hssi_pcie_hip.revision_id = revision_id,
hardcopyiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_max = rx_ptr0_nonposted_dpram_max,
hardcopyiv_hssi_pcie_hip.rx_ptr0_nonposted_dpram_min = rx_ptr0_nonposted_dpram_min,
hardcopyiv_hssi_pcie_hip.rx_ptr0_posted_dpram_max = rx_ptr0_posted_dpram_max,
hardcopyiv_hssi_pcie_hip.rx_ptr0_posted_dpram_min = rx_ptr0_posted_dpram_min,
hardcopyiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_max = rx_ptr1_nonposted_dpram_max,
hardcopyiv_hssi_pcie_hip.rx_ptr1_nonposted_dpram_min = rx_ptr1_nonposted_dpram_min,
hardcopyiv_hssi_pcie_hip.rx_ptr1_posted_dpram_max = rx_ptr1_posted_dpram_max,
hardcopyiv_hssi_pcie_hip.rx_ptr1_posted_dpram_min = rx_ptr1_posted_dpram_min,
hardcopyiv_hssi_pcie_hip.sameclock_nfts_count = sameclock_nfts_count,
hardcopyiv_hssi_pcie_hip.single_rx_detect = single_rx_detect,
hardcopyiv_hssi_pcie_hip.skp_os_schedule_count = skp_os_schedule_count,
hardcopyiv_hssi_pcie_hip.slot_number = slot_number,
hardcopyiv_hssi_pcie_hip.slot_power_limit = slot_power_limit,
hardcopyiv_hssi_pcie_hip.slot_power_scale = slot_power_scale,
hardcopyiv_hssi_pcie_hip.ssid = ssid,
hardcopyiv_hssi_pcie_hip.ssvid = ssvid,
hardcopyiv_hssi_pcie_hip.subsystem_device_id = subsystem_device_id,
hardcopyiv_hssi_pcie_hip.subsystem_vendor_id = subsystem_vendor_id,
hardcopyiv_hssi_pcie_hip.surprise_down_error_support = surprise_down_error_support,
hardcopyiv_hssi_pcie_hip.use_crc_forwarding = use_crc_forwarding,
hardcopyiv_hssi_pcie_hip.vc0_clk_enable = vc0_clk_enable,
hardcopyiv_hssi_pcie_hip.vc0_rx_buffer_memory_settings = vc0_rx_buffer_memory_settings,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_data = vc0_rx_flow_ctrl_compl_data,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_compl_header = vc0_rx_flow_ctrl_compl_header,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_data = vc0_rx_flow_ctrl_nonposted_data,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_nonposted_header = vc0_rx_flow_ctrl_nonposted_header,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_data = vc0_rx_flow_ctrl_posted_data,
hardcopyiv_hssi_pcie_hip.vc0_rx_flow_ctrl_posted_header = vc0_rx_flow_ctrl_posted_header,
hardcopyiv_hssi_pcie_hip.vc1_clk_enable = vc1_clk_enable,
hardcopyiv_hssi_pcie_hip.vc1_rx_buffer_memory_settings = vc1_rx_buffer_memory_settings,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_data = vc1_rx_flow_ctrl_compl_data,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_compl_header = vc1_rx_flow_ctrl_compl_header,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_data = vc1_rx_flow_ctrl_nonposted_data,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_nonposted_header = vc1_rx_flow_ctrl_nonposted_header,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_data = vc1_rx_flow_ctrl_posted_data,
hardcopyiv_hssi_pcie_hip.vc1_rx_flow_ctrl_posted_header = vc1_rx_flow_ctrl_posted_header,
hardcopyiv_hssi_pcie_hip.vc_arbitration = vc_arbitration,
hardcopyiv_hssi_pcie_hip.vc_enable = vc_enable,
hardcopyiv_hssi_pcie_hip.vendor_id = vendor_id;
end
endgenerate
generate
if (SOPC_BUILDER_MODE==1) begin : g_reset_controller
reg rc_areset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg rc_areset_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg rc_areset_rrr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire rc_areset_n;
//rc_areset Synchronizer
assign rc_areset_n = ~rc_areset;
always @(posedge pld_clk or negedge rc_areset_n) begin
if (rc_areset_n == 1'b0) begin
rc_areset_r <= 1'b1;
rc_areset_rr <=1'b1;
rc_areset_rrr <=1'b1;
end
else begin
rc_areset_r <= 1'b0;
rc_areset_rr <= rc_areset_r;
rc_areset_rrr <= rc_areset_rr;
end
end
alt4gxb_reset_controller alt4gxb_reset_controller0
(
.async_reset (rc_areset_rrr),
.fifo_err (1'b0),
.gxb_powerdown (rc_gxb_powerdown),
.inclk (pld_clk),
.inclk_eq_125mhz (rc_inclk_eq_125mhz),
.pll_locked (rc_pll_locked),
.rx_pll_locked (rc_rx_pll_locked_one),
.rxanalogreset (rc_rx_analogreset),
.rxdigitalreset (rc_rx_digitalreset),
.test_sim (test_in[0]),
.txdigitalreset (rc_tx_digitalreset)
);
end
endgenerate
altpcie_pcie_reconfig_bridge altpcie_pcie_reconfig_bridge0
(
.avs_pcie_reconfig_address (avs_pcie_reconfig_address),
.avs_pcie_reconfig_chipselect (avs_pcie_reconfig_chipselect),
.avs_pcie_reconfig_clk (avs_pcie_reconfig_clk),
.avs_pcie_reconfig_read (avs_pcie_reconfig_read),
.avs_pcie_reconfig_readdata (avs_pcie_reconfig_readdata),
.avs_pcie_reconfig_readdatavalid (avs_pcie_reconfig_readdatavalid),
.avs_pcie_reconfig_rstn (avs_pcie_reconfig_rstn_int),
.avs_pcie_reconfig_waitrequest (avs_pcie_reconfig_waitrequest),
.avs_pcie_reconfig_write (avs_pcie_reconfig_write),
.avs_pcie_reconfig_writedata (avs_pcie_reconfig_writedata),
.dpclk (dpclk),
.dpriodisable (dpriodisable),
.dprioin (dprioin),
.dprioload (dprioload),
.dprioout (dprioout)
);
defparam altpcie_pcie_reconfig_bridge0.base_address = base_address,
altpcie_pcie_reconfig_bridge0.device_address = device_address,
altpcie_pcie_reconfig_bridge0.port_address = port_address;
generate if (!(CB_PCIE_MODE == 1 && CB_PCIE_RX_LITE == 1))
begin : avalon_stream_hip_qsys
altpciexpav_stif_app
# (
.INTENDED_DEVICE_FAMILY (INTENDED_DEVICE_FAMILY),
.CG_AVALON_S_ADDR_WIDTH (CG_AVALON_S_ADDR_WIDTH),
.CG_COMMON_CLOCK_MODE (1),
.CG_IMPL_CRA_AV_SLAVE_PORT (CG_IMPL_CRA_AV_SLAVE_PORT),
.CB_PCIE_MODE (CB_PCIE_MODE),
.CB_A2P_ADDR_MAP_IS_FIXED (CB_A2P_ADDR_MAP_IS_FIXED),
.CB_A2P_ADDR_MAP_FIXED_TABLE (CB_A2P_ADDR_MAP_FIXED_TABLE_INT),
.CB_A2P_ADDR_MAP_NUM_ENTRIES (CB_A2P_ADDR_MAP_NUM_ENTRIES),
.CB_A2P_ADDR_MAP_PASS_THRU_BITS (CB_A2P_ADDR_MAP_PASS_THRU_BITS),
.CB_P2A_AVALON_ADDR_B0 (CB_P2A_AVALON_ADDR_B0),
.CB_P2A_AVALON_ADDR_B1 (CB_P2A_AVALON_ADDR_B1),
.CB_P2A_AVALON_ADDR_B2 (CB_P2A_AVALON_ADDR_B2),
.CB_P2A_AVALON_ADDR_B3 (CB_P2A_AVALON_ADDR_B3),
.CB_P2A_AVALON_ADDR_B4 (CB_P2A_AVALON_ADDR_B4),
.CB_P2A_AVALON_ADDR_B5 (CB_P2A_AVALON_ADDR_B5),
.CB_P2A_AVALON_ADDR_B6 (CB_P2A_AVALON_ADDR_B6),
.bar0_64bit_mem_space (bar0_64bit_mem_space),
.bar0_io_space (bar0_io_space),
.bar0_prefetchable (bar0_prefetchable),
.bar0_size_mask (bar0_size_mask),
.bar1_64bit_mem_space (bar1_64bit_mem_space),
.bar1_io_space (bar1_io_space),
.bar1_prefetchable (bar1_prefetchable),
.bar1_size_mask (bar1_size_mask),
.bar2_64bit_mem_space ( bar2_64bit_mem_space),
.bar2_io_space (bar2_io_space),
.bar2_prefetchable (bar2_prefetchable),
.bar2_size_mask (bar2_size_mask),
.bar3_64bit_mem_space (bar3_64bit_mem_space),
.bar3_io_space (bar3_io_space),
.bar3_prefetchable (bar3_prefetchable),
.bar3_size_mask (bar3_size_mask),
.bar4_64bit_mem_space (bar4_64bit_mem_space),
.bar4_io_space (bar4_io_space),
.bar4_prefetchable (bar4_prefetchable),
.bar4_size_mask (bar4_size_mask),
.bar5_64bit_mem_space (bar5_64bit_mem_space),
.bar5_io_space (bar5_io_space),
.bar5_prefetchable (bar5_prefetchable),
.bar5_size_mask (bar5_size_mask),
.bar_io_window_size (bar_io_window_size),
.bar_prefetchable (bar_prefetchable),
.expansion_base_address_register (expansion_base_address_register),
.EXTERNAL_A2P_TRANS (0),
.CG_ENABLE_A2P_INTERRUPT (CG_ENABLE_A2P_INTERRUPT),
.CG_RXM_IRQ_NUM (CG_RXM_IRQ_NUM),
.CB_RXM_DATA_WIDTH (RXM_DATA_WIDTH),
.CB_PCIE_RX_LITE (CB_PCIE_RX_LITE)
)
avalon_bridge (
// system inputs
.AvlClk_i(AvlClk_i),
.Rstn_i(Rstn_i),
.RxStReady_o(rx_st_ready0_sopc),
.RxStMask_o(rx_st_mask0_sopc),
.RxStData_i(rx_st_data0),
.RxStParity_i(32'h00000000),
.RxStBe_i(rx_st_be0),
.RxStEmpty_i(2'b00),
.RxStErr_i(8'h00),
.RxStSop_i(rx_st_sop0),
.RxStEop_i(rx_st_eop0),
.RxStValid_i(rx_st_valid0),
.RxStBarDec1_i(rx_st_bardec0),
.RxStBarDec2_i(8'h0),
.TxStReady_i(tx_st_ready0) ,
.TxStData_o (tx_st_data0_sopc) ,
.TxStParity_o (),
.TxStErr_o (tx_st_err0_sopc) ,
.TxStSop_o (tx_st_sop0_sopc) ,
.TxStEop_o (tx_st_eop0_sopc) ,
.TxStEmpty_o () ,
.TxStValid_o(tx_st_valid0_sopc) ,
.TxAdapterFifoEmpty_i(tx_fifo_empty0),
.CplPending_o(cpl_pending_sopc),
.TxCredPDataLimit_i(),
.TxCredNpDataLimit_i(0),
.TxCredCplDataLimit_i(0),
.TxCredHipCons_i(0),
.TxCredInfinit_i(0),
.TxCredPHdrLimit_i(0),
.TxCredNpHdrLimit_i(0),
.TxCredCplHdrLimit_i(),
.ko_cpl_spc_header (0), // .ko_cpl_spc_header
.ko_cpl_spc_data (0), // .ko_cpl_spc_data
.TxCredit_i(tx_cred0),
.TxNpCredOne_i(nph_alloc_1cred_vc0),
.CfgCtlWr_i(tl_cfg_ctl_wr),
.CfgAddr_i(tl_cfg_add),
.CfgCtl_i(tl_cfg_ctl),
// MSI and Interrupt interface
.MsiReq_o(app_msi_req_sopc),
.MsiAck_i(app_msi_ack),
.MsiTc_o(app_msi_tc_sopc),
.MsiNum_o(aer_msi_num_sopc),
.IntxReq_o(app_int_sts_sopc),
.IntxAck_i(app_int_ack),
// Avalon Tx Slave interface
.TxsClk_i(AvlClk_i),
.TxsRstn_i(Rstn_i),
.TxsChipSelect_i(TxsChipSelect_i),
.TxsRead_i(TxsRead_i),
.TxsWrite_i(TxsWrite_i),
.TxsWriteData_i(TxsWriteData_i),
.TxsBurstCount_i(TxsBurstCount_i),
.TxsAddress_i(TxsAddress_i),
.TxsByteEnable_i(TxsByteEnable_i),
.TxsReadDataValid_o(TxsReadDataValid_o),
.TxsReadData_o(TxsReadData_o),
.TxsWaitRequest_o(TxsWaitRequest_o),
// Avalon Rx Master interface
.RxmWrite_0_o(RxmWrite_0_o),
.RxmAddress_0_o(RxmAddress_0_o),
.RxmWriteData_0_o(RxmWriteData_0_o),
.RxmByteEnable_0_o(RxmByteEnable_0_o),
.RxmBurstCount_0_o(RxmBurstCount_0_o),
.RxmWaitRequest_0_i(RxmWaitRequest_0_i),
.RxmRead_0_o(RxmRead_0_o),
.RxmReadData_0_i(RxmReadData_0_i),
.RxmReadDataValid_0_i(RxmReadDataValid_0_i),
.RxmWrite_1_o(RxmWrite_1_o),
.RxmAddress_1_o(RxmAddress_1_o),
.RxmWriteData_1_o(RxmWriteData_1_o),
.RxmByteEnable_1_o(RxmByteEnable_1_o),
.RxmBurstCount_1_o(RxmBurstCount_1_o),
.RxmWaitRequest_1_i(RxmWaitRequest_1_i),
.RxmRead_1_o(RxmRead_1_o),
.RxmReadData_1_i(RxmReadData_1_i),
.RxmReadDataValid_1_i(RxmReadDataValid_1_i),
.RxmWrite_2_o(RxmWrite_2_o),
.RxmAddress_2_o(RxmAddress_2_o),
.RxmWriteData_2_o(RxmWriteData_2_o),
.RxmByteEnable_2_o(RxmByteEnable_2_o),
.RxmBurstCount_2_o(RxmBurstCount_2_o),
.RxmWaitRequest_2_i(RxmWaitRequest_2_i),
.RxmRead_2_o(RxmRead_2_o),
.RxmReadData_2_i(RxmReadData_2_i),
.RxmReadDataValid_2_i(RxmReadDataValid_2_i),
.RxmWrite_3_o(RxmWrite_3_o),
.RxmAddress_3_o(RxmAddress_3_o),
.RxmWriteData_3_o(RxmWriteData_3_o),
.RxmByteEnable_3_o(RxmByteEnable_3_o),
.RxmBurstCount_3_o(RxmBurstCount_3_o),
.RxmWaitRequest_3_i(RxmWaitRequest_3_i),
.RxmRead_3_o(RxmRead_3_o),
.RxmReadData_3_i(RxmReadData_3_i),
.RxmReadDataValid_3_i(RxmReadDataValid_3_i),
.RxmWrite_4_o(RxmWrite_4_o),
.RxmAddress_4_o(RxmAddress_4_o),
.RxmWriteData_4_o(RxmWriteData_4_o),
.RxmByteEnable_4_o(RxmByteEnable_4_o),
.RxmBurstCount_4_o(RxmBurstCount_4_o),
.RxmWaitRequest_4_i(RxmWaitRequest_4_i),
.RxmRead_4_o(RxmRead_4_o),
.RxmReadData_4_i(RxmReadData_4_i),
.RxmReadDataValid_4_i(RxmReadDataValid_4_i),
.RxmWrite_5_o(RxmWrite_5_o),
.RxmAddress_5_o(RxmAddress_5_o),
.RxmWriteData_5_o(RxmWriteData_5_o),
.RxmByteEnable_5_o(RxmByteEnable_5_o),
.RxmBurstCount_5_o(RxmBurstCount_5_o),
.RxmWaitRequest_5_i(RxmWaitRequest_5_i),
.RxmRead_5_o(RxmRead_5_o),
.RxmReadData_5_i(RxmReadData_5_i),
.RxmReadDataValid_5_i(RxmReadDataValid_5_i),
.RxmIrq_i(RxmIrq_i),
.CraClk_i(AvlClk_i),
.CraRstn_i(Rstn_i),
.CraChipSelect_i(CraChipSelect_i),
.CraRead(CraRead),
.CraWrite(CraWrite),
.CraWriteData_i(CraWriteData_i),
.CraAddress_i(CraAddress_i),
.CraByteEnable_i(CraByteEnable_i),
.CraReadData_o(CraReadData_o), // This comes from Rx Completion to be returned to Avalon master
.CraWaitRequest_o(CraWaitRequest_o),
.CraIrq_o (CraIrq_o )
);
end
endgenerate
generate if ( CB_PCIE_MODE == 1 && CB_PCIE_RX_LITE == 1)
begin
altpciexpav_lite_app
# (
.CB_P2A_AVALON_ADDR_B0( CB_P2A_AVALON_ADDR_B0),
.CB_P2A_AVALON_ADDR_B1(CB_P2A_AVALON_ADDR_B1 ),
.CB_P2A_AVALON_ADDR_B2(CB_P2A_AVALON_ADDR_B2 ),
.CB_P2A_AVALON_ADDR_B3(CB_P2A_AVALON_ADDR_B3 ),
.CB_P2A_AVALON_ADDR_B4(CB_P2A_AVALON_ADDR_B4 ),
.CB_P2A_AVALON_ADDR_B5(CB_P2A_AVALON_ADDR_B5 ),
.CB_P2A_AVALON_ADDR_B6(CB_P2A_AVALON_ADDR_B6 ),
.bar0_64bit_mem_space(bar0_64bit_mem_space ),
.bar0_io_space(bar0_io_space ),
.bar0_prefetchable(bar0_prefetchable ),
.bar0_size_mask(bar0_size_mask ),
.bar1_64bit_mem_space(bar1_64bit_mem_space ),
.bar1_io_space( bar1_io_space),
.bar1_prefetchable( bar1_prefetchable),
.bar1_size_mask (bar1_size_mask ),
.bar2_64bit_mem_space(bar2_64bit_mem_space ),
.bar2_io_space( bar2_io_space),
.bar2_prefetchable(bar2_prefetchable ),
.bar2_size_mask( bar2_size_mask),
.bar3_64bit_mem_space( bar3_64bit_mem_space),
.bar3_io_space(bar3_io_space ),
.bar3_prefetchable(bar3_prefetchable ),
.bar3_size_mask(bar3_size_mask ),
.bar4_64bit_mem_space(bar4_64bit_mem_space ),
.bar4_io_space(bar4_io_space ),
.bar4_prefetchable( bar4_prefetchable),
.bar4_size_mask(bar4_size_mask ),
.bar5_64bit_mem_space(bar5_64bit_mem_space ),
.bar5_io_space(bar5_io_space ),
.bar5_prefetchable( bar5_prefetchable),
.bar5_size_mask (bar5_size_mask ),
.bar_io_window_size(bar_io_window_size ),
.bar_prefetchable ( bar_prefetchable),
.expansion_base_address_register(expansion_base_address_register ),
.CB_RXM_DATA_WIDTH(RXM_DATA_WIDTH),
.CG_RXM_IRQ_NUM(CG_RXM_IRQ_NUM),
.deviceFamily(INTENDED_DEVICE_FAMILY)
)
avalon_bridge_lite
(
.Clk_i( AvlClk_i),
.Rstn_i(Rstn_i ),
.RxStEmpty_i(2'b00 ),
.RxStMask_o(rx_st_mask0_sopc),
.RxStSop_i(rx_st_sop0 ),
.RxStEop_i(rx_st_eop0 ),
.RxStData_i(rx_st_data0 ),
.RxStValid_i(rx_st_valid0 ),
.RxStReady_o(rx_st_ready0_sopc ),
.RxStBarDec_i(rx_st_bardec0 ),
.TxStReady_i(tx_st_ready0 ),
.TxStSop_o(tx_st_sop0_sopc ),
.TxStEop_o(tx_st_eop0_sopc ),
.TxStData_o(tx_st_data0_sopc ),
.TxStValid_o(tx_st_valid0_sopc ),
.RxmWrite_0_o(RxmWrite_0_o ),
.RxmAddress_0_o(RxmAddress_0_o ),
.RxmWriteData_0_o(RxmWriteData_0_o ),
.RxmByteEnable_0_o(RxmByteEnable_0_o ),
.RxmWaitRequest_0_i(RxmWaitRequest_0_i ),
.RxmRead_0_o(RxmRead_0_o ),
.RxmReadData_0_i( RxmReadData_0_i),
.RxmReadDataValid_0_i(RxmReadDataValid_0_i ),
.RxmWrite_1_o(RxmWrite_1_o ),
.RxmAddress_1_o(RxmAddress_1_o ),
.RxmWriteData_1_o(RxmWriteData_1_o ),
.RxmByteEnable_1_o( RxmByteEnable_1_o),
.RxmWaitRequest_1_i(RxmWaitRequest_1_i ),
.RxmRead_1_o(RxmRead_1_o ),
.RxmReadData_1_i( RxmReadData_1_i),
.RxmReadDataValid_1_i(RxmReadDataValid_1_i ),
.RxmWrite_2_o( RxmWrite_2_o),
.RxmAddress_2_o(RxmAddress_2_o ),
.RxmWriteData_2_o(RxmWriteData_2_o ),
.RxmByteEnable_2_o(RxmByteEnable_2_o ),
.RxmWaitRequest_2_i(RxmWaitRequest_2_i ),
.RxmRead_2_o(RxmRead_2_o ),
.RxmReadData_2_i( RxmReadData_2_i),
.RxmReadDataValid_2_i( RxmReadDataValid_2_i),
.RxmWrite_3_o(RxmWrite_3_o ),
.RxmAddress_3_o( RxmAddress_3_o),
.RxmWriteData_3_o(RxmWriteData_3_o ),
.RxmByteEnable_3_o(RxmByteEnable_3_o ),
.RxmWaitRequest_3_i( RxmWaitRequest_3_i),
.RxmRead_3_o(RxmRead_3_o ),
.RxmReadData_3_i(RxmReadData_3_i ),
.RxmReadDataValid_3_i(RxmReadDataValid_3_i ),
.RxmWrite_4_o(RxmWrite_4_o ),
.RxmAddress_4_o( RxmAddress_4_o),
.RxmWriteData_4_o(RxmWriteData_4_o ),
.RxmByteEnable_4_o( RxmByteEnable_4_o),
.RxmWaitRequest_4_i(RxmWaitRequest_4_i ),
.RxmRead_4_o( RxmRead_4_o),
.RxmReadData_4_i( RxmReadData_4_i),
.RxmReadDataValid_4_i(RxmReadDataValid_4_i ),
.RxmWrite_5_o( RxmWrite_5_o),
.RxmAddress_5_o(RxmAddress_5_o ),
.RxmWriteData_5_o( RxmWriteData_5_o),
.RxmByteEnable_5_o( RxmByteEnable_5_o),
.RxmWaitRequest_5_i(RxmWaitRequest_5_i ),
.RxmRead_5_o( RxmRead_5_o),
.RxmReadData_5_i(RxmReadData_5_i ),
.RxmReadDataValid_5_i(RxmReadDataValid_5_i ),
.RxmIrq_i( RxmIrq_i),
.CfgCtlWr_i( tl_cfg_ctl_wr),
.CfgAddr_i(tl_cfg_add ),
.CfgCtl_i( tl_cfg_ctl),
.AppIntSts_o(app_int_sts_sopc),
.MsiReq_o(app_msi_req_sopc ),
.MsiAck_i(app_msi_ack ),
.MsiTc_o(app_msi_tc_sopc ),
.MsiNum_o (aer_msi_num_sopc)
);
assign tx_st_err0_sopc = 1'b0;
assign cpl_pending_sopc = 1'b0;
end
endgenerate
altpcie_txcred_patch txcred_patch0
(
.clk (pld_clk),
.npd_alloc_1cred (npd_alloc_1cred_vc0),
.npd_cred_viol (npd_cred_vio_vc0),
.nph_alloc_1cred (nph_alloc_1cred_vc0),
.nph_cred_viol (nph_cred_vio_vc0),
.rstn (npor),
.srst (srst),
.tx_cred (tx_cred0),
.tx_cred_int (tx_cred0_int),
.tx_st_data (tx_st_data0_int[31 : 0]),
.tx_st_eop ({tx_st_eop0_p1, tx_st_eop0_int}),
.tx_st_err (tx_st_err0_int),
.tx_st_sop (tx_st_sop0_int),
.tx_stream_valid (tx_st_valid0_int)
);
defparam txcred_patch0.BYP_PATCH = (p_pcie_hip_type == "2") ? 1 : 0,
txcred_patch0.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode;
altpcie_txcred_patch txcred_patch1
(
.clk (pld_clk),
.npd_alloc_1cred (npd_alloc_1cred_vc1),
.npd_cred_viol (npd_cred_vio_vc1),
.nph_alloc_1cred (nph_alloc_1cred_vc1),
.nph_cred_viol (nph_cred_vio_vc1),
.rstn (npor),
.srst (srst),
.tx_cred (tx_cred1),
.tx_cred_int (tx_cred1_int),
.tx_st_data (tx_st_data1_int[31 : 0]),
.tx_st_eop ({tx_st_eop1_p1, tx_st_eop1}),
.tx_st_err (tx_st_err1),
.tx_st_sop (tx_st_sop1_int),
.tx_stream_valid (tx_st_valid1_int)
);
defparam txcred_patch1.BYP_PATCH = (p_pcie_hip_type == "2") ? 1 : 0,
txcred_patch1.enable_adapter_half_rate_mode = enable_adapter_half_rate_mode;
altpcie_tl_cfg_pipe altpcie_tl_cfg_pipe_inst
(
.clk (pld_clk),
.srst (srst),
.o_tl_cfg_add(tl_cfg_add),
.o_tl_cfg_ctl(tl_cfg_ctl),
.o_tl_cfg_ctl_wr(tl_cfg_ctl_wr),
.o_tl_cfg_sts(tl_cfg_sts),
.o_tl_cfg_sts_wr(tl_cfg_sts_wr),
.i_tl_cfg_add(tl_cfg_add_hip),
.i_tl_cfg_ctl(tl_cfg_ctl_hip),
.i_tl_cfg_ctl_wr(tl_cfg_ctl_wr_hip),
.i_tl_cfg_sts(tl_cfg_sts_hip),
.i_tl_cfg_sts_wr(tl_cfg_sts_wr_hip)
);
endmodule
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.54 Aug. 8, 2005
// Fri Nov 4 10:07:57 2005
//
// Input file : D:/cvs_build/projects/pci_express_r1/altera/src/vhdl/top/alt4gxb_reset_controller.vhd
// Design name : alt4gxb_reset_controller
// Author :
// Company :
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Logic Core: PCI Express Megacore Function
// Company: Altera Corporation.
// www.altera.com
// Author: IPBU SIO Group
//
// Description: Altera PCI Express MegaCore Reset controller for Alt2gxb
//
// Copyright (c) 2005 Altera Corporation. All rights reserved. This source code
// is highly confidential and proprietary information of Altera and is being
// provided in accordance with and subject to the protections of a
// Non-Disclosure Agreement which governs its use and disclosure. Altera
// products and services are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws. Altera
// assumes no responsibility or liability arising out of the application or use
// of this source code.
//
// For Best Viewing Set tab stops to 4 spaces.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Reset Controller for the ALT2GXB
//
//
module alt4gxb_reset_controller
(input inclk,
input async_reset,
input test_sim,
input pll_locked,
input rx_pll_locked,
input fifo_err,
input inclk_eq_125mhz,
output gxb_powerdown,
output txdigitalreset,
output rxanalogreset,
output rxdigitalreset
) ;
localparam [19:0] WS_SIM = 20'h00020;
localparam [19:0] WS_1MS_10000 = 20'h186a0;
localparam [19:0] WS_1MS_12500 = 20'h1e848;
localparam [19:0] WS_1MS_15625 = 20'h2625a;
localparam [19:0] WS_1MS_25000 = 20'h3d090;
localparam [1:0] idle = 0;
localparam [1:0] strobe_txpll_locked = 1;
localparam [1:0] stable_tx_pll = 2;
localparam [1:0] wait_state = 3;
// Suppressing R102 here because gxb_powredown takes out the whole alt2gxb and no clock
// will be running
(* syn_encoding = "user" *) reg [1:0] rst_ctrl_sm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg [19:0] waitstate_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg txdigitalreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg rxanalogreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg rxdigitalreset_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg ws_tmr_eq_0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg ld_ws_tmr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg ld_ws_tmr_short /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg [2:0] rx_pll_locked_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
reg rx_pll_locked_sync_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL =R102" */ ;
wire pll_locked_sync;
reg [2:0] pll_locked_r;
wire rx_pll_locked_sync;
reg [2:0] rx_pll_locked_r;
assign gxb_powerdown = async_reset ;
assign txdigitalreset = txdigitalreset_r ;
assign rxanalogreset = rxanalogreset_r ;
assign rxdigitalreset = rxdigitalreset_r ;
// Synchronize rx_pll_locked and pll_locked to inclk
always @(posedge inclk or posedge async_reset) begin
if (async_reset == 1'b1) begin
rx_pll_locked_r[2:0] <= 3'b000;
pll_locked_r[2:0] <= 3'b000;
end
else begin
rx_pll_locked_r[2:0] <= {rx_pll_locked_r[1],rx_pll_locked_r[0],rx_pll_locked};
pll_locked_r[2:0] <= {pll_locked_r[1] ,pll_locked_r[0] ,pll_locked};
end
end
assign rx_pll_locked_sync = rx_pll_locked_r[2];
assign pll_locked_sync = pll_locked_r[2];
always @(posedge inclk or posedge async_reset)
begin
if (async_reset == 1'b1)
begin
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
waitstate_timer <= 20'hFFFFF ;
rst_ctrl_sm <= strobe_txpll_locked ;
ws_tmr_eq_0 <= 1'b0 ;
ld_ws_tmr <= 1'b1 ;
ld_ws_tmr_short <= 1'b0 ;
rx_pll_locked_cnt <= 3'h0;
rx_pll_locked_sync_r <= 1'b0;
end
else
begin
// add hysterisis for losing lock
if (rx_pll_locked_sync == 1'b1)
rx_pll_locked_cnt <= 3'h7;
else if (rx_pll_locked_cnt == 3'h0)
rx_pll_locked_cnt <= 3'h0;
else if (rx_pll_locked_sync == 1'b0)
rx_pll_locked_cnt <= rx_pll_locked_cnt - 1;
rx_pll_locked_sync_r <= (rx_pll_locked_cnt != 3'h0);
if (ld_ws_tmr == 1'b1)
begin
if (test_sim == 1'b1)
begin
waitstate_timer <= WS_SIM ;
end
else if (inclk_eq_125mhz == 1'b1)
begin
waitstate_timer <= WS_1MS_12500 ;
end
else
begin
waitstate_timer <= WS_1MS_25000 ;
end
end
else if (ld_ws_tmr_short == 1'b1)
waitstate_timer <= WS_SIM ;
else if (waitstate_timer != 20'h00000)
begin
waitstate_timer <= waitstate_timer - 1 ;
end
if (ld_ws_tmr == 1'b1 | ld_ws_tmr_short)
begin
ws_tmr_eq_0 <= 1'b0 ;
end
else if (waitstate_timer == 20'h00000)
begin
ws_tmr_eq_0 <= 1'b1 ;
end
else
begin
ws_tmr_eq_0 <= 1'b0 ;
end
case (rst_ctrl_sm)
idle :
begin
if (rx_pll_locked_sync_r == 1'b1)
begin
if (fifo_err == 1'b1)
rst_ctrl_sm <= stable_tx_pll ;
else
rst_ctrl_sm <= idle ;
end
else
begin
rst_ctrl_sm <= strobe_txpll_locked ;
ld_ws_tmr <= 1'b1 ;
end
end
strobe_txpll_locked :
begin
ld_ws_tmr <= 1'b0 ;
if (pll_locked_sync == 1'b1 & ws_tmr_eq_0 == 1'b1)
begin
rst_ctrl_sm <= stable_tx_pll ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
else
begin
rst_ctrl_sm <= strobe_txpll_locked ;
txdigitalreset_r <= 1'b1 ;
rxanalogreset_r <= 1'b1 ;
rxdigitalreset_r <= 1'b1 ;
end
end
stable_tx_pll :
begin
if (rx_pll_locked_sync_r == 1'b1)
begin
rst_ctrl_sm <= wait_state ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
ld_ws_tmr_short <= 1'b1 ;
end
else
begin
rst_ctrl_sm <= stable_tx_pll ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
wait_state :
begin
if (rx_pll_locked_sync_r == 1'b1)
begin
ld_ws_tmr_short <= 1'b0 ;
if (ld_ws_tmr_short == 1'b0 & ws_tmr_eq_0 == 1'b1)
begin
rst_ctrl_sm <= idle ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b0 ;
end
else
begin
rst_ctrl_sm <= wait_state ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
else
begin
rst_ctrl_sm <= stable_tx_pll ;
txdigitalreset_r <= 1'b0 ;
rxanalogreset_r <= 1'b0 ;
rxdigitalreset_r <= 1'b1 ;
end
end
default :
begin
rst_ctrl_sm <= idle ;
waitstate_timer <= 20'hFFFFF ;
end
endcase
end
end
endmodule
//Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : altpcie_txcred_patch
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcie_txcred_patch.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
//
// Description: This module is a patch for the hip tx_cred
//-----------------------------------------------------------------------------
module altpcie_txcred_patch # (
parameter enable_adapter_half_rate_mode = "false", // 64 bit vs 128 bit AV-ST mode
parameter BYP_PATCH = 0 // Bypasses this patch - routes tx_cred back out as-is.
) (
input clk,
input rstn,
input srst,
input [35:0] tx_cred_int, // tx_cred from HIP
input tx_stream_valid, // means tx_st_data is valid
input tx_st_sop, // Start of TLP
input[1:0] tx_st_eop, // End of TLP
input tx_st_err,
input[31:0] tx_st_data, // AV-ST Transmit data H0 (first Header DW on wire.
output reg nph_alloc_1cred, // means NPH negotiated to 1 credit. credit info is unreliable.
output reg npd_alloc_1cred,
output reg nph_cred_viol, // Means application violated tx_cred -- patch is no longer reliable.
output reg npd_cred_viol,
output[35:0] tx_cred // corrected tx_cred
);
localparam CONSUMED_LAT = 1; // # clks to delay nph_sent to sync consumed pointers in patch and adaptor.
localparam AVST_128_BITMODE = (enable_adapter_half_rate_mode=="false") ? 0 : 1; // AV-ST 128 bit mode
reg[CONSUMED_LAT-1:0] nph_sent_pipe; // synchronization pipe for nph_sent (from AV-ST to reflection on adaptor's consumed pointer)
reg[CONSUMED_LAT-1:0] npd_sent_pipe; // synchronization pipe for npd_sent (from AV-ST to reflection on adaptor's consumed pointer)
wire[CONSUMED_LAT-1:0] nph_sent_pipe_n; // synchronization pipe for nph_sent (from AV-ST to reflection on adaptor's consumed pointer)
wire[CONSUMED_LAT-1:0] npd_sent_pipe_n; // synchronization pipe for npd_sent (from AV-ST to reflection on adaptor's consumed pointer)
reg [2:0] nph_cred_app; // NPH credits given to application (modified nph_cred_hip)
reg [2:0] npd_cred_app; // NPD credits given to application (modified nph_cred_hip)
reg[7:0] nph_cred_cons; // credits consumed counter
reg[7:0] nph_cred_avail,
nph_cred_avail_n; // actual # of known available credits (which is later encoded to 3 bits).
reg[11:0] npd_cred_cons; // credits consumed counter
reg[11:0] npd_cred_avail,
npd_cred_avail_n; // actual # of known available credits (which is later encoded to 3 bits).
reg nph_unitialized; // Means NPH credits is not yet initialized
reg npd_unitialized; // Means NPD credits is not yet initialized
wire nph_sent; // means a nonposted TLP was sent on AV-ST TX
wire npd_sent; // means a nonposted TLP with data was sent on AV-ST TX
wire has_payld; // means TLP has payload
wire [2:0] nph_cred_hip; // NonPosted Header credits from HIP
wire [2:0] npd_cred_hip; // NonPosted Data credits from HIP
wire cfg0; // TLP decoding
wire non_posted; // TLP decoding
reg [35:0] tx_cred_reg; // Registered version of tx_cred from HIP -- boundary reg
reg non_posted_hold; // memorize if TLP is NP - hold for EOP
reg has_payld_hold; // memorize if TLP has payload - hold for EOP
wire debug_128bitmode;
reg debug_bogus0_nph;
reg debug_bogus0_npd;
wire[1:0] tx_eop_int;
wire bogus_0_detect_nph_n; // When 1, and tx_cred from HIP is 0, tx_cred is bogus
wire bogus_0_detect_npd_n; // When 1, and tx_cred from HIP is 0, tx_cred is bogus
reg rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign debug_128bitmode = (enable_adapter_half_rate_mode=="false") ? 1'b0 : 1'b1;
assign tx_eop_int = {tx_st_eop[0], (tx_st_eop[1] ^ tx_st_eop[0])} ;
//--------------------------------------
// tx_cred output:
// - pass Posted/CPL credits thru as-is
// - replace NP credits with patch
assign tx_cred[35:21] = tx_cred_int[35:21];
assign tx_cred[20:18] = (BYP_PATCH==1) ? tx_cred_int[20:18] : npd_cred_app;
assign tx_cred[17:15] = (BYP_PATCH==1) ? tx_cred_int[17:15] : nph_cred_app;
assign tx_cred[14:0] = tx_cred_int[14:0];
//------------------------
// patch for NP creds
assign nph_cred_hip = tx_cred_int[17:15];
assign npd_cred_hip = tx_cred_int[20:18];
//---------------------------------------------------
// decoding for non_posted TLPs is
// identical to HIP Adaptor --
// do not count CFG0's for NP creds.
assign cfg0 = (tx_st_data[29:24] == 6'b000100) ? 1'b1 : 1'b0 ;
assign non_posted = (cfg0 == 1'b0 &
((tx_st_data[30] == 1'b0 & tx_st_data[28:27] == 2'b00) |
(tx_st_data[30:29] == 2'b10 & tx_st_data[26:24] != 3'b000 & tx_st_data[28:27] == 2'b00))) ? 1'b1 : 1'b0 ;
assign has_payld = tx_stream_valid & tx_st_sop & tx_st_data[30];
// Count NPH creds on EOP
// Mirror adaptor for tx_st_err behavior.
assign nph_sent = (tx_stream_valid & tx_st_sop & |tx_eop_int & AVST_128_BITMODE) ? non_posted :
(tx_stream_valid & |tx_eop_int & ~tx_st_err) ? non_posted_hold : 1'b0;
assign npd_sent = (tx_stream_valid & tx_st_sop & |tx_eop_int & AVST_128_BITMODE) ? (non_posted & has_payld) :
(tx_stream_valid & |tx_eop_int & ~tx_st_err) ? has_payld_hold : 1'b0;
//------------------------------------------------
// Synchronization Pipes for nph_sent
// - This synchronizes the patch's internal cred_consumed
// pointer to the adaptor's cred_consumed pointer.
// They are cycle-to-cycle identical.
// - length of pipeline depends on CONSUMED_LAT
generate
if (CONSUMED_LAT>1) begin: gen_nph_sent_pipe
assign nph_sent_pipe_n = {nph_sent, nph_sent_pipe[CONSUMED_LAT-1:1]};
end
endgenerate
generate
if (CONSUMED_LAT==1) begin: gen_nph_sent_del
assign nph_sent_pipe_n = nph_sent;
end
endgenerate
//--------------------------------------------------
// Synchronization Pipes for npd_sent
generate
if (CONSUMED_LAT>1) begin: gen_npd_sent_pipe
assign npd_sent_pipe_n = {npd_sent, npd_sent_pipe[CONSUMED_LAT-1:1]};
end
endgenerate
generate
if (CONSUMED_LAT==1) begin: gen_npd_sent_del
assign npd_sent_pipe_n = npd_sent;
end
endgenerate
always @ (posedge clk or negedge rstn)
begin
if (rstn == 1'b0)
begin
rstn_r <= 1'b0;
rstn_rr <= 1'b0;
end
else
begin
rstn_r <= 1'b1;
rstn_rr <= rstn_r;
end
end
always @ (posedge clk or negedge rstn_rr) begin
if (~rstn_rr) begin
nph_sent_pipe <= {CONSUMED_LAT{1'b0}};
nph_cred_app <= 3'h0;
nph_cred_avail <= 8'h0;
nph_cred_cons <= 8'h0;
npd_sent_pipe <= {CONSUMED_LAT{1'b0}};
npd_cred_app <= 3'h0;
npd_cred_avail <= 12'h0;
npd_cred_cons <= 12'h0;
nph_unitialized <= 1'b1;
npd_unitialized <= 1'b1;
nph_alloc_1cred <= 1'b0;
npd_alloc_1cred <= 1'b0;
nph_cred_viol <= 1'b0;
npd_cred_viol <= 1'b0;
tx_cred_reg <= 36'h0;
non_posted_hold <= 1'b0;
has_payld_hold <= 1'b0;
end
else begin
if (srst) begin
nph_sent_pipe <= {CONSUMED_LAT{1'b0}};
nph_cred_app <= 3'h0;
nph_cred_avail <= 8'h0;
nph_cred_cons <= 8'h0;
npd_sent_pipe <= {CONSUMED_LAT{1'b0}};
npd_cred_app <= 3'h0;
npd_cred_avail <= 12'h0;
npd_cred_cons <= 12'h0;
nph_unitialized <= 1'b1;
npd_unitialized <= 1'b1;
nph_alloc_1cred <= 1'b0;
npd_alloc_1cred <= 1'b0;
nph_cred_viol <= 1'b0;
npd_cred_viol <= 1'b0;
tx_cred_reg <= 36'h0;
non_posted_hold <= 1'b0;
has_payld_hold <= 1'b0;
end
else begin
tx_cred_reg <= tx_cred_int; // input boundary reg for Fmax
//--------------------------------------
// Memorize NP decoding from SOP cycle.
// Hold for EOP.
if (tx_stream_valid & tx_st_err) begin
non_posted_hold <= 1'b0;
has_payld_hold <= 1'b0;
end
else if (tx_stream_valid & tx_st_sop) begin
non_posted_hold <= non_posted;
has_payld_hold <= non_posted & has_payld;
end
//-----------------------------------
// Detect initialized credits
// - Flag if only 1 credit is allocated.
// - Patch cannot be used for single credit systems
// because the patch withholds 1 cred from the user.
if (nph_unitialized) begin
nph_unitialized <= (nph_cred_hip > 8'h0) ? 1'b0 : 1'b1;
nph_alloc_1cred <= (nph_cred_hip == 8'h1) ? 1'b1 : 1'b0;
end
if (npd_unitialized) begin
npd_unitialized <= (npd_cred_hip > 8'h0) ? 1'b0 : 1'b1;
npd_alloc_1cred <= (npd_cred_hip == 8'h1) ? 1'b1 : 1'b0;
end
//----------------------------------------------------
// Track nph and npd credits consumed.
// Should exactly shadow the cred_cons counter in HIP.
nph_sent_pipe <= nph_sent_pipe_n;
npd_sent_pipe <= npd_sent_pipe_n;
nph_cred_cons <= nph_sent_pipe[0] ? nph_cred_cons + 8'h1 : nph_cred_cons;
npd_cred_cons <= npd_sent_pipe[0] ? npd_cred_cons + 12'h1 : npd_cred_cons;
//---------------------------------------------------
// Credits available
nph_cred_avail <= nph_cred_avail_n;
npd_cred_avail <= npd_cred_avail_n;
//----------------------------------------------------
// Credits violated: Means last credit in HIP has
// been consumed, and the patch is no longer reliable.
nph_cred_viol <= ((nph_cred_avail_n ==8'h0) & nph_sent) | nph_cred_viol;
npd_cred_viol <= ((npd_cred_avail_n ==8'h0) & npd_sent) | npd_cred_viol;
//----------------------------------------
// tx_cred output stage.
// Encode output to 3 bits, top out at 7.
//--------
// Header
if (nph_cred_avail_n > 8'h7) begin
nph_cred_app <= 3'h7;
end
else begin
nph_cred_app <= nph_cred_avail_n[2:0];
end
//--------
// Data
if (npd_cred_avail_n > 12'h7) begin
npd_cred_app <= 3'h7;
end
else begin
npd_cred_app <= npd_cred_avail_n[2:0];
end
end
end
end
//--------------------------------------
// Calculate available credits
// Turn ON detection for bogus 0 when NPH consumed
// pointer is somewhere between 0 and 127.
// Chose 64 because it is the middle.
// Actually, any 0 that occurs when consumed!=0
// is bogus. But bogus 0 will not happen until
// consumed pointer is somewhere in upper half of
// it's value range.
assign bogus_0_detect_nph_n = nph_cred_cons>8'h40;
assign bogus_0_detect_npd_n = npd_cred_cons>12'h400;
always @ (*) begin
//----------------------------------------
// Detect 'bogus 0' on nph_cred_hip:
// - when cred_lim pointer in adaptor
// rolls over to 0
// Algorithm:
// - in normal op, withhold 1 cred
// from nph_cred_hip so that nph_cred_hip
// should never be 0 (except when cred_cons
// pointer rolls over and both pointers are at 0).
// - detect bogus 0 when cred_cons is in
// upper half of counter, and nph_cred_hip
// is 0 (i.e. counters are on different pages).
// - when bogus 0 detected, assume credit_limit pointer is
// at 0. Give app (0-consumed) creds until
// cred_cons to rolls over to 0.
// - when cred_cons==0, then 2 clks later, tx_cred
// will be true again. during the 2 clk cycle latency, HIP will
// still show bogus 0. so patch will just hold at 0 creds.
// functionally, this is okay .. effectively the patch
// just 'releases' credits 2 cycles late.
// Note: It is possible at this point for the HIP to
// really have 0 creds -- it happens when consumed==0,
// and limit==0. This is okay. Whether you treat this
// as a bogus 0 or not, the credits sent to app is still 0.
// Patch considers this a real 0 and not bogus.
// * NOTE1: tx_cred from HIP is always delayed wrt to
// changes in the CONSUMED pointer. This is true
// with or without the patch, and is due
// normal ckt latencies. The user must
// always account for these delays when evaluating
// the tx_cred or else they can end up working
// with OVER-stated credits.
// To do this, the user should sample tx_cred when there
// are no NP's in flight (i.e. consumed pointer is
// quiet). The procedure is:
// - latch the tx_cred before sending any NPs.
// - consume those creds,
// - then stop sending NP's and wait xx cycles
// for the HIP to process the last pkt sent
// - then latch new tx_cred, repeat.
// NOTE2: Latencies between changes in the LIMIT pointer
// and tx_cred are not an issue because this only
// translates into a delay in the release of credits
// (i.e. tx_cred can only be UNDERstated).
// cred_lim rollover occured.
// grant credits up to cred_lim = 8'h0 (allows creds
// consumed to roll over to next page).
//-------
// Header
if (bogus_0_detect_nph_n & (nph_cred_hip==3'h0)) begin
// receiving bogus 0 (assume limit=0).
nph_cred_avail_n = (8'hFF - nph_cred_cons) + 8'h1;
debug_bogus0_nph = 1'b1;
end
else begin
// cred_lim & cred_consumed are on same page.
// nph_cred_hip is true (after 2 cycles*, but in the
// the meantime is showing bogus 0).
// Patch waits for more than 1 credit from adaptor.
// Then withholds 1 cred.
nph_cred_avail_n = (nph_cred_hip > 8'h1) ? (nph_cred_hip - 8'h1) : 8'h0;
debug_bogus0_nph = 1'b0;
end
//--------
// Data
// cred_lim rollover occured
// grant credits up to cred_lim = 8'h0 (to allow creds
// consumed to roll over to next page).
if (bogus_0_detect_npd_n & (npd_cred_hip==3'h0)) begin
npd_cred_avail_n = (12'hFFF - npd_cred_cons) + 12'h1;
debug_bogus0_npd = 1'b1;
end
else begin
// cred_lim & cred_consumed are on same page.
// npd_cred_hip is true. withhold 1 cred
npd_cred_avail_n = (npd_cred_hip > 12'h1) ? (npd_cred_hip - 12'h1) : 12'h0;
debug_bogus0_npd = 1'b0;
end
end
endmodule
//Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// synthesis verilog_input_version verilog_2001
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//-----------------------------------------------------------------------------
// Title : altpcie_tl_cfg_pipe
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcie_tl_cfg_pipe.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
//
// Description: This module is to assist timing closure on TL_CFG bus
//-----------------------------------------------------------------------------
module altpcie_tl_cfg_pipe
(
input clk,
input srst,
output reg [ 3:0] o_tl_cfg_add,
output reg [31:0] o_tl_cfg_ctl,
output reg o_tl_cfg_ctl_wr,
output reg [52:0] o_tl_cfg_sts,
output reg o_tl_cfg_sts_wr,
input [ 3:0] i_tl_cfg_add,
input [31:0] i_tl_cfg_ctl,
input i_tl_cfg_ctl_wr,
input [52:0] i_tl_cfg_sts,
input i_tl_cfg_sts_wr
);
reg sts_wr_r,sts_wr_rr;
reg ctl_wr_r,ctl_wr_rr;
always @ (posedge clk)
begin
if (srst)
begin
o_tl_cfg_add <= 4'h0;
o_tl_cfg_ctl <= {32{1'b0}};
o_tl_cfg_ctl_wr <= {1{1'b0}};
o_tl_cfg_sts <= {53{1'b0}};
o_tl_cfg_sts_wr <= {1{1'b0}};
end
else
begin
// sts pipeline
sts_wr_r <= i_tl_cfg_sts_wr;
sts_wr_rr <= sts_wr_r;
o_tl_cfg_sts_wr <= sts_wr_rr;
if (o_tl_cfg_sts_wr != sts_wr_rr)
o_tl_cfg_sts <= i_tl_cfg_sts;
// ctl pipeline
ctl_wr_r <= i_tl_cfg_ctl_wr;
ctl_wr_rr <= ctl_wr_r;
o_tl_cfg_ctl_wr <= ctl_wr_rr;
if (o_tl_cfg_ctl_wr != ctl_wr_rr)
begin
o_tl_cfg_add <= i_tl_cfg_add;
o_tl_cfg_ctl <= i_tl_cfg_ctl;
end
end
end
endmodule
|
/*******************************************************************
*****串口接收模块
*****1：确认开始位（检测低电平）
*****2：采集8bit有效数据位
*******************************************************************/
module Uart_rx(
input clk, //系统50MHz时钟
input rst_n, //复位，低电平有效
input rs232_rx, //输入串行数据
input [3:0] num, //控制一帧数据有多少bit
input sel_data, //波特率计数的中心点（采集数据的使能信号）
output rx_en, //接收信号使能：启动接收波特率计数
output reg tx_en, //发送信号使能：接收数据完成后，开始启动发送数据
output reg [7:0] rx_data //将接收到的8bit的串行数据转换为并行数据
);
//检测低电平信号（开始位）
reg in_1,in_2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
in_1 <= 1'b1;
in_2 <= 1'b1;
end
else
begin
in_1 <= rs232_rx;
in_2 <= in_1;
end
assign rx_en = in_2 & (~in_1); //当检测到信号由高变低时，将使能信号拉高
//确保一帧数据的中间8bit进行数据的读取，读取完成后，使能信号tx_en控制串口发送模块
reg [7:0] rx_data_r; //锁存数据寄存器
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
rx_data_r <= 8'd0;
rx_data <= 8'd0;
end
else
if(sel_data)
case(num)
0: ; //忽略开始位
1: rx_data_r[0] <= rs232_rx; //采集中间八位有效数据
2: rx_data_r[1] <= rs232_rx;
3: rx_data_r[2] <= rs232_rx;
4: rx_data_r[3] <= rs232_rx;
5: rx_data_r[4] <= rs232_rx;
6: rx_data_r[5] <= rs232_rx;
7: rx_data_r[6] <= rs232_rx;
8: rx_data_r[7] <= rs232_rx;
9: rx_data <= rx_data_r; //锁存采集的8位有效数据（忽略停止位）
default: ; //默认状态下不采集
endcase
//发送使能模块，检测数据接收是否完成？完成后就将tx_en拉高（开始启动数据发送模块）
always @(posedge clk or negedge rst_n)
if(!rst_n)
tx_en <= 0;
else
if(num == 4'd9 && sel_data) //接收停止之后拉高一个时钟
tx_en <= 1;
else
tx_en <= 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_SYMBOL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module receiver_logic
#(
parameter DSIZE = 10
)
(
input wire RESET,
input wire WCLK,
input wire FCLK,
input wire FCLK2X,
input wire BUS_CLK,
input wire RX_DATA,
input wire read,
output wire [23:0] data,
output wire empty,
output wire full,
output wire rec_sync_ready,
output reg [7:0] lost_err_cnt,
output reg [7:0] decoder_err_cnt,
output reg [15:0] fifo_size,
input wire invert_rx_data,
input wire enable_rx,
input wire FIFO_CLK
);
wire RESET_WCLK;
flag_domain_crossing reset_domain_crossing_wclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(WCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_WCLK)
);
wire RESET_FCLK;
flag_domain_crossing reset_domain_crossing_fclk_inst (
.CLK_A(BUS_CLK),
.CLK_B(FCLK),
.FLAG_IN_CLK_A(RESET),
.FLAG_OUT_CLK_B(RESET_FCLK)
);
reg enable_rx_buf, enable_rx_buf2, enable_rx_wclk;
always @ (posedge WCLK)
begin
enable_rx_buf <= enable_rx;
enable_rx_buf2 <= enable_rx_buf;
enable_rx_wclk <= enable_rx_buf2;
end
// data to clock phase alignment
wire RX_DATA_SYNC; //, USEAOUT, USEBOUT, USECOUT, USEDOUT;
sync_master sync_master_inst(
.clk(FCLK), // clock input
.clk_2x(FCLK2X), // clock 90 input
.datain(RX_DATA), // data inputs
.rst(RESET_FCLK), // reset input
.useaout(), // useA output for cascade
.usebout(), // useB output for cascade
.usecout(), // useC output for cascade
.usedout(), // useD output for cascade
.ctrlout(), // ctrl outputs for cascade
.sdataout(RX_DATA_SYNC)
);
// 8b/10b record sync
wire [9:0] data_8b10b;
reg decoder_err;
rec_sync #(
.DSIZE(DSIZE)
) rec_sync_inst (
.reset(RESET_WCLK),
.datain(invert_rx_data ? ~RX_DATA_SYNC : RX_DATA_SYNC),
.data(data_8b10b),
.WCLK(WCLK),
.FCLK(FCLK),
.rec_sync_ready(rec_sync_ready),
.decoder_err(decoder_err)
);
wire write_8b10b;
assign write_8b10b = rec_sync_ready & enable_rx_wclk;
reg [9:0] data_to_dec;
integer i;
always @ (*) begin
for (i=0; i<10; i=i+1)
data_to_dec[(10-1)-i] = data_8b10b[i];
end
reg dispin;
wire dispout;
always@(posedge WCLK) begin
if(RESET_WCLK)
dispin <= 1'b0;
else// if(write_8b10b)
dispin <= dispout;
// if(RESET_WCLK)
// dispin <= 1'b0;
// else
// if(write_8b10b)
// dispin <= ~dispout;
// else
// dispin <= dispin;
end
wire dec_k;
wire [7:0] dec_data;
wire code_err, disp_err;
decode_8b10b decode_8b10b_inst (
.datain(data_to_dec),
.dispin(dispin),
.dataout({dec_k,dec_data}), // control character, data out
.dispout(dispout),
.code_err(code_err),
.disp_err(disp_err)
);
always@(negedge WCLK) begin // avoid glitches from code_err or disp_err
if(RESET_WCLK)
decoder_err <= 1'b0;
else
decoder_err <= code_err | disp_err;
end
// Invalid symbols may or may not cause
// disparity errors depending on the symbol
// itself and the disparities of the previous and
// subsequent symbols. For this reason,
// DISP_ERR should always be combined
// with CODE_ERR to detect all errors.
always@(posedge WCLK) begin
if(RESET_WCLK)
decoder_err_cnt <= 0;
else
if(decoder_err && write_8b10b && decoder_err_cnt != 8'hff)
decoder_err_cnt <= decoder_err_cnt + 1;
else
decoder_err_cnt <= decoder_err_cnt;
end
reg [2:0] byte_sel;
always@(posedge WCLK) begin
if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
byte_sel <= 0;
else if(write_8b10b)
byte_sel <= byte_sel + 1;
// if(RESET_WCLK || (write_8b10b && dec_k) || (write_8b10b && dec_k==0 && byte_sel==2))
// byte_sel <= 0;
// else
// if(write_8b10b)
// byte_sel <= byte_sel + 1;
// else
// byte_sel <= byte_sel;
end
reg [7:0] data_dec_in [2:0];
always@(posedge WCLK) begin
for (i=0; i<3; i=i+1)
data_dec_in[i] <= data_dec_in[i];
if(RESET_WCLK)
for (i=0; i<3; i=i+1)
data_dec_in[i] <= 8'b0;
else
if(write_8b10b && dec_k==0)
data_dec_in[byte_sel] <= dec_data;
end
reg write_dec_in;
always@(posedge WCLK) begin
if(RESET_WCLK)
write_dec_in <= 0;
else
if(write_8b10b && dec_k==0 && byte_sel==2)
write_dec_in <= 1;
else
write_dec_in <= 0;
end
wire cdc_fifo_full, cdc_fifo_empty;
always@(posedge WCLK) begin
if(RESET_WCLK)
lost_err_cnt <= 0;
else
if(cdc_fifo_full && write_dec_in && lost_err_cnt != 8'hff)
lost_err_cnt <= lost_err_cnt + 1;
else
lost_err_cnt <= lost_err_cnt;
end
wire [23:0] cdc_data_out;
wire [23:0] wdata;
assign wdata = {data_dec_in[0],data_dec_in[1],data_dec_in[2]};
// generate delayed and long reset
reg [5:0] rst_cnt;
always@(posedge BUS_CLK) begin
if(RESET)
rst_cnt <= 5'd8;
else if(rst_cnt != 5'd7)
rst_cnt <= rst_cnt +1;
end
wire rst_long = rst_cnt[5];
reg cdc_sync_ff;
always @(posedge WCLK) begin
cdc_sync_ff <= rst_long;
end
//assign FIFO_CLK = BUS_CLK;
cdc_syncfifo #(
.DSIZE(24),
.ASIZE(2)
) cdc_syncfifo_i (
.rdata(cdc_data_out),
.wfull(cdc_fifo_full),
.rempty(cdc_fifo_empty),
.wdata(wdata),
.winc(write_dec_in),
.wclk(WCLK),
.wrst(cdc_sync_ff),
.rinc(!full),
.rclk(FIFO_CLK),
.rrst(rst_long)
);
wire [10:0] fifo_size_int;
gerneric_fifo #(
.DATA_SIZE(24),
.DEPTH(2048)
) fifo_i (
.clk(FIFO_CLK),
.reset(rst_long),
.write(!cdc_fifo_empty),
.read(read),
.data_in(cdc_data_out),
.full(full),
.empty(empty),
.data_out(data),
.size(fifo_size_int)
);
always @(posedge FIFO_CLK) begin
fifo_size <= {5'b0, fifo_size_int};
end
`ifdef SYNTHESIS_NOT
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(FCLK),
.TRIG0({dec_k, dec_data, data_to_dec, rec_sync_ready, 1'b0, USEAOUT, USEBOUT, USECOUT, USEDOUT, RX_DATA_SYNC, RX_DATA})
);
`endif
endmodule
|
// $File: //acds/rel/14.1/ip/sopc/components/altera_avalon_dc_fifo/altera_dcfifo_synchronizer_bundle.v $
// $Revision: #1 $
// $Date: 2014/10/06 $
// $Author: swbranch $
//-------------------------------------------------------------------------------
`timescale 1 ns / 1 ns
module altera_dcfifo_synchronizer_bundle(
clk,
reset_n,
din,
dout
);
parameter WIDTH = 1;
parameter DEPTH = 3;
input clk;
input reset_n;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
genvar i;
generate
for (i=0; i<WIDTH; i=i+1)
begin : sync
altera_std_synchronizer_nocut #(.depth(DEPTH))
u (
.clk(clk),
.reset_n(reset_n),
.din(din[i]),
.dout(dout[i])
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_1_V
`define SKY130_FD_SC_LP__DIODE_1_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_1 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__diode_1 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_1_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file vram.v when simulating
// the core, vram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module vram(
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [12 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [12 : 0] addrb;
input [7 : 0] dinb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(13),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(8192),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(8192),
.C_WRITE_MODE_A("READ_FIRST"),
.C_WRITE_MODE_B("READ_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
module cpu_ctl(op,func,equal_result,JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,BJ,Aluc
);
input wire [5:0] op, func;
input wire equal_result;
output wire JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,BJ;
output wire [4:0] Aluc;
wire r_type, i_jr, i_sll, i_srl, i_sra; //i_mfhi,i_mflo,i_mthi,i_mtlo;
wire i_type, i_addi, i_addiu, i_andi, i_ori, i_xori, i_lui, i_lw, i_sw, i_slti, i_sltiu;//i_lh,i_sh,i_mul,i_div,
wire b_type, i_beq, i_bne;
wire i_j, i_jal;
/* R_type */
and(r_type,~op[5],~op[4],~op[3],~op[2],~op[1],~op[0]);
and(i_jr, r_type, ~func[5], ~func[4], func[3], ~func[2], ~func[1], ~func[0]); //func:001000
and(i_sll, r_type, ~func[5], ~func[4], ~func[3], ~func[2], ~func[1], ~func[0]); //func:000000
and(i_srl, r_type, ~func[5], ~func[4], ~func[3], ~func[2], func[1], ~func[0]); //func:000010
and(i_sra, r_type, ~func[5], ~func[4], ~func[3], ~func[2], func[1], func[0]); //func:000011
// and(i_sllv, r_type, ~func[5], ~func[4], ~func[3], func[2], ~func[1], ~func[0]); //func:000100
// and(i_srlv, r_type, ~func[5], ~func[4], ~func[3], func[2], func[1], ~func[0]); //func:000110
// and(i_srav, r_type, ~func[5], ~func[4], ~func[3], func[2], func[1], func[0]); //func:000111
/* I_type */
or(i_type, i_addi, i_andi, i_ori, i_xori, i_slti, b_type, i_lw, i_sw );
and(i_addi, ~op[5],~op[4], op[3],~op[2],~op[1],~op[0]); //001000
and(i_addiu, ~op[5],~op[4], op[3],~op[2],~op[1], op[0]); //001001
and(i_andi, ~op[5],~op[4], op[3], op[2],~op[1],~op[0]); //001100
and(i_ori, ~op[5],~op[4], op[3], op[2],~op[1], op[0]); //001101
and(i_xori, ~op[5],~op[4], op[3], op[2], op[1],~op[0]); //001110
and(i_lui, ~op[5],~op[4], op[3], op[2], op[1], op[0]); //001111
and(i_lw, op[5],~op[4],~op[3],~op[2], op[1], op[0]); //100011
and(i_sw, op[5],~op[4], op[3],~op[2], op[1], op[0]); //101011
and(i_slti, ~op[5],~op[4], op[3],~op[2], op[1],~op[0]); //001010
and(i_sltiu, ~op[5],~op[4], op[3],~op[2], op[1], op[0]); //001011
/* I_type(B) */
or(b_type, i_beq, i_bgez, i_bgtz, i_blez, i_bltz, i_bne);
and(i_beq, ~op[5],~op[4],~op[3], op[2],~op[1],~op[0]); //000100
and(i_bne, ~op[5],~op[4],~op[3], op[2],~op[1], op[0]); //000101
/* J_type */
and(i_j, ~op[5],~op[4],~op[3],~op[2], op[1],~op[0]);
and(i_jal, ~op[5],~op[4],~op[3],~op[2], op[1], op[0]);
/* JR,J,JAL,LW,WREG,WMEM,RDorRT,SE,SA,IorR,AluCtl£¬BJ */
assign JR = i_jr;
assign J = i_j;
assign JAL = i_jal;
assign LW = i_lw;
assign WREG = i_jal | (IorR & ~i_sw) | (r_type & ~i_jr);
assign WMEM = i_sw;
assign RDorRT = r_type & ~i_jr;
assign SE = i_addi | i_addiu | i_lw |i_sw | i_slti;//i_andi i_ori zero_extend
assign SA = i_sll | i_srl | i_sra;
// assign IR =( r_type | i_type ) & ~i_jr & ~b_type & ~i_lw & ~i_sw;
assign IorR = i_type & ~b_type;
alt_ctl AC(.op(op),.func(func),.aluc(Aluc));
assign BJ = ( i_beq & equal_result ) | ( i_bne & ~equal_result );
endmodule
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave_b2b
* this module will get 64 bytes and then return the count 64 at next clks
*******************************************************************************/
module spi_slave_b2b_reduced(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg sselr;
reg [7:0] byte_data_sent;
reg [7:0] next_byte_data_sent;
reg [7:0] bit_cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
reg curr, last;
always@(posedge clk)
begin
if(!rst_n) begin
curr <= 1'b0;
last <= 1'b0;
end
else begin
curr <= sck;
last <= curr;
end
end
//Raising edge
assign sck_risingedge = curr & (~last);
//failing edge
assign sck_fallingedge = ~curr & (last);
/*******************************************************************************
*detect ssel status
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 1'h1;
else
sselr <= ssel;
end
assign ssel_active = (~sselr) ? 1'b1 : 1'b0; // SSEL is active low
/*******************************************************************************
*read from mosi
*******************************************************************************/
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
/*******************************************************************************
*SPI slave send data
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
byte_data_sent <= 8'h1;
next_byte_data_sent <= 8'h2;
bit_cnt <= 8'h0;
end
else begin
if(ssel_active && sck_fallingedge)
begin
if(next_byte_data_sent == 8'h41)
next_byte_data_sent <= 8'h1;
if (bit_cnt == 8'h7f)
begin
byte_data_sent <= next_byte_data_sent;
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
bit_cnt <= {bit_cnt[6:0], 1'b1};
end
else begin
if(ssel_active && sck_risingedge) begin
/*
update the next byte
*/
if(bit_cnt == 8'hff)
begin
bit_cnt <= 8'h0;
next_byte_data_sent <= next_byte_data_sent + 1;
end
end
end
end
end
assign miso = byte_data_sent[7]; // send MSB first
endmodule
|
module generator(clk, validdata, Readtoa, Readtob, iWriteEnable, iAddress, iReadAddress);
output clk, Readtoa, Readtob, iWriteEnable;
output [7:0] validdata;
output [9:0] iAddress;
output [9:0] iReadAddress;
reloj r1(clk);
inputs d1(validdata, Readtoa, Readtob, iWriteEnable, iAddress, iReadAddress);
endmodule
//Generacion del reloj
module reloj(clk);
output reg clk;
initial
begin
clk = 0;
end
always
begin
#250 clk = 1;
#250 clk = 0;
end
endmodule
//Generación de entradas a la memoria
module inputs (validdata, Readtoa, Readtob, iWriteEnable, iAddress, iReadAddress);
output reg Readtoa, Readtob, iWriteEnable ;
output reg [7:0] validdata;
output reg [9:0] iAddress;
output reg [9:0] iReadAddress;
initial
begin
#10 validdata = 8'd8; Readtoa = 0; Readtob = 0; iWriteEnable = 1; iAddress =10'd0; iReadAddress =10'd0;
#500 validdata = 8'd8; Readtoa = 1; Readtob = 0; iWriteEnable = 0; iAddress =10'd0;iReadAddress =10'd0;
#1000 validdata = 8'd16; Readtoa = 0; Readtob = 0; iWriteEnable = 1; iAddress =10'd10; iReadAddress =10'd10;
#1500 validdata = 8'd16; Readtoa = 0; Readtob = 1; iWriteEnable = 0; iAddress =10'd10; iReadAddress =10'd10;
#2000 validdata = 8'd32; Readtoa = 0; Readtob = 0; iWriteEnable = 1; iAddress =10'b0000011111;iReadAddress =10'b0000011111;
#2500 validdata = 8'd32; Readtoa = 1; Readtob = 0; iWriteEnable = 0;iAddress =10'b0000011111;iReadAddress =10'b0000011111;
#3000 validdata = 8'd64; Readtoa = 0; Readtob = 0; iWriteEnable = 1; iAddress =10'b1111111111; iReadAddress =10'b1111111111;
#3500 validdata = 8'd64; Readtoa = 0; Readtob = 1; iWriteEnable = 0; iAddress =10'b1111111111; iReadAddress =10'b1111111111;
end
endmodule
|
// megafunction wizard: %ALTFP_ADD_SUB%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_add_sub
// ============================================================
// File Name: float_add_sub.v
// Megafunction Name(s):
// altfp_add_sub
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module float_add_sub (
clk_en,
clock,
dataa,
datab,
overflow,
result)/* synthesis synthesis_clearbox = 1 */;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output overflow;
output [31:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
// Retrieval info: CONSTANT: DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
// Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL "overflow"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_add_sub_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
/**
* udp_dff$PR_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PR_pp$PKG$sN (
Q ,
D ,
CLK ,
RESET ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input RESET ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PR_PP_PKG_SN_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_1_V
`define SKY130_FD_SC_HS__AND2B_1_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Anton Potocnik
//
// Create Date: 07.01.2017 22:45:53
// Design Name:
// Module Name: signal_decoder
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module signal_decoder #
(
parameter ADC_WIDTH = 14,
parameter AXIS_TDATA_WIDTH = 32,
parameter BIT_OFFSET = 4 // 4 for +/-20 V or 0 for +/-1 V ADC voltage range setting
)
(
(* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_tdata,
input S_AXIS_tvalid,
input clk,
input rst,
output reg [7:0] led_out
);
wire [2:0] value;
assign value = S_AXIS_tdata[ADC_WIDTH-BIT_OFFSET-1:ADC_WIDTH-BIT_OFFSET-3];
always @(posedge clk)
if (~rst)
led_out <= 8'hFF;
else
case (value)
3'b011 : led_out <= 8'b00000001;
3'b010 : led_out <= 8'b00000010;
3'b001 : led_out <= 8'b00000100;
3'b000 : led_out <= 8'b00001000;
3'b111 : led_out <= 8'b00010000;
3'b110 : led_out <= 8'b00100000;
3'b101 : led_out <= 8'b01000000;
3'b100 : led_out <= 8'b10000000;
default : led_out <= 8'b00000000;
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BEHAVIORAL_PP_V
|
// -*- Mode: Verilog -*-
// Filename : display_top.v
// Description : Display numbers from UART to 7 Segments
// Author : Philip Tracton
// Created On : Wed May 27 17:15:49 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed May 27 17:15:49 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module display_top (/*AUTOARG*/
// Outputs
TX, ANODE, CATHODE,
// Inputs
CLK_IN, RESET_IN, RX
) ;
input CLK_IN;
input RESET_IN;
input RX;
output TX;
output [3:0] ANODE;
output [7:0] CATHODE;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CLK_OUT; // From syscon of system_controller.v
wire RESET_OUT; // From syscon of system_controller.v
// End of automatics
/*AUTOREG*/
wire TX;
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire [7:0] uart_data_out;
wire [7:0] display_data_out;
wire [3:0] ANODE;
wire [7:0] CATHODE;
//
// System Controller
//
system_controller syscon(/*AUTOINST*/
// Outputs
.CLK_OUT (CLK_OUT),
.RESET_OUT (RESET_OUT),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN));
//
// Picoblaze CPU
//
cpu Picoblaze(
// Outputs
.port_id (port_id[7:0]),
.out_port (out_port[7:0]),
.write_strobe (write_strobe),
.read_strobe (read_strobe),
.interrupt_ack (interrupt_ack),
// Inputs
.clk (CLK_OUT),
.in_port (in_port[7:0]),
.interrupt (interrupt),
.kcpsm6_sleep (kcpsm6_sleep),
.cpu_reset (RESET_OUT));
assign in_port = uart_data_out | display_data_out;
assign interrupt = uart_irq;
assign kcpsm6_sleep = 0;
//
// UART
//
pb_uart uart(
// Outputs
.TX(TX),
.data_out(uart_data_out),
.interrupt(uart_irq),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.RX(RX),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe)
) ;
//
// Display
//
pb_display #(.BASE_ADDRESS(8'h10))
seven_segments(
// Outputs
.data_out(display_data_out),
.anode(ANODE),
.cathode(CATHODE),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe)
) ;
endmodule // uart_echo_pb
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_2_V
`define SKY130_FD_SC_HDLL__NOR4_2_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
/**
* iso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso0p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepn;
// Name Output Other arguments
not not0 (sleepn, SLEEP );
and and0 (X , A, sleepn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0P_BEHAVIORAL_V
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.05.04.18:11:56
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_0 (
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cra_reset_reset_bridge_in_reset_reset, // kernel_cra_reset_reset_bridge_in_reset.reset
input wire [29:0] address_span_extender_0_expanded_master_address, // address_span_extender_0_expanded_master.address
output wire address_span_extender_0_expanded_master_waitrequest, // .waitrequest
input wire [0:0] address_span_extender_0_expanded_master_burstcount, // .burstcount
input wire [3:0] address_span_extender_0_expanded_master_byteenable, // .byteenable
input wire address_span_extender_0_expanded_master_read, // .read
output wire [31:0] address_span_extender_0_expanded_master_readdata, // .readdata
output wire address_span_extender_0_expanded_master_readdatavalid, // .readdatavalid
input wire address_span_extender_0_expanded_master_write, // .write
input wire [31:0] address_span_extender_0_expanded_master_writedata, // .writedata
output wire [29:0] kernel_cra_s0_address, // kernel_cra_s0.address
output wire kernel_cra_s0_write, // .write
output wire kernel_cra_s0_read, // .read
input wire [63:0] kernel_cra_s0_readdata, // .readdata
output wire [63:0] kernel_cra_s0_writedata, // .writedata
output wire [0:0] kernel_cra_s0_burstcount, // .burstcount
output wire [7:0] kernel_cra_s0_byteenable, // .byteenable
input wire kernel_cra_s0_readdatavalid, // .readdatavalid
input wire kernel_cra_s0_waitrequest, // .waitrequest
output wire kernel_cra_s0_debugaccess // .debugaccess
);
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest; // address_span_extender_0_expanded_master_agent:av_waitrequest -> address_span_extender_0_expanded_master_translator:uav_waitrequest
wire [2:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount; // address_span_extender_0_expanded_master_translator:uav_burstcount -> address_span_extender_0_expanded_master_agent:av_burstcount
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata; // address_span_extender_0_expanded_master_translator:uav_writedata -> address_span_extender_0_expanded_master_agent:av_writedata
wire [29:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address; // address_span_extender_0_expanded_master_translator:uav_address -> address_span_extender_0_expanded_master_agent:av_address
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock; // address_span_extender_0_expanded_master_translator:uav_lock -> address_span_extender_0_expanded_master_agent:av_lock
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write; // address_span_extender_0_expanded_master_translator:uav_write -> address_span_extender_0_expanded_master_agent:av_write
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read; // address_span_extender_0_expanded_master_translator:uav_read -> address_span_extender_0_expanded_master_agent:av_read
wire [31:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata; // address_span_extender_0_expanded_master_agent:av_readdata -> address_span_extender_0_expanded_master_translator:uav_readdata
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess; // address_span_extender_0_expanded_master_translator:uav_debugaccess -> address_span_extender_0_expanded_master_agent:av_debugaccess
wire [3:0] address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable; // address_span_extender_0_expanded_master_translator:uav_byteenable -> address_span_extender_0_expanded_master_agent:av_byteenable
wire address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_0_expanded_master_agent:av_readdatavalid -> address_span_extender_0_expanded_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> address_span_extender_0_expanded_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> address_span_extender_0_expanded_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> address_span_extender_0_expanded_master_agent:rp_startofpacket
wire [100:0] rsp_mux_src_data; // rsp_mux:src_data -> address_span_extender_0_expanded_master_agent:rp_data
wire [0:0] rsp_mux_src_channel; // rsp_mux:src_channel -> address_span_extender_0_expanded_master_agent:rp_channel
wire rsp_mux_src_ready; // address_span_extender_0_expanded_master_agent:rp_ready -> rsp_mux:src_ready
wire kernel_cra_s0_agent_m0_waitrequest; // kernel_cra_s0_translator:uav_waitrequest -> kernel_cra_s0_agent:m0_waitrequest
wire [3:0] kernel_cra_s0_agent_m0_burstcount; // kernel_cra_s0_agent:m0_burstcount -> kernel_cra_s0_translator:uav_burstcount
wire [63:0] kernel_cra_s0_agent_m0_writedata; // kernel_cra_s0_agent:m0_writedata -> kernel_cra_s0_translator:uav_writedata
wire [29:0] kernel_cra_s0_agent_m0_address; // kernel_cra_s0_agent:m0_address -> kernel_cra_s0_translator:uav_address
wire kernel_cra_s0_agent_m0_write; // kernel_cra_s0_agent:m0_write -> kernel_cra_s0_translator:uav_write
wire kernel_cra_s0_agent_m0_lock; // kernel_cra_s0_agent:m0_lock -> kernel_cra_s0_translator:uav_lock
wire kernel_cra_s0_agent_m0_read; // kernel_cra_s0_agent:m0_read -> kernel_cra_s0_translator:uav_read
wire [63:0] kernel_cra_s0_agent_m0_readdata; // kernel_cra_s0_translator:uav_readdata -> kernel_cra_s0_agent:m0_readdata
wire kernel_cra_s0_agent_m0_readdatavalid; // kernel_cra_s0_translator:uav_readdatavalid -> kernel_cra_s0_agent:m0_readdatavalid
wire kernel_cra_s0_agent_m0_debugaccess; // kernel_cra_s0_agent:m0_debugaccess -> kernel_cra_s0_translator:uav_debugaccess
wire [7:0] kernel_cra_s0_agent_m0_byteenable; // kernel_cra_s0_agent:m0_byteenable -> kernel_cra_s0_translator:uav_byteenable
wire kernel_cra_s0_agent_rf_source_endofpacket; // kernel_cra_s0_agent:rf_source_endofpacket -> kernel_cra_s0_agent_rsp_fifo:in_endofpacket
wire kernel_cra_s0_agent_rf_source_valid; // kernel_cra_s0_agent:rf_source_valid -> kernel_cra_s0_agent_rsp_fifo:in_valid
wire kernel_cra_s0_agent_rf_source_startofpacket; // kernel_cra_s0_agent:rf_source_startofpacket -> kernel_cra_s0_agent_rsp_fifo:in_startofpacket
wire [137:0] kernel_cra_s0_agent_rf_source_data; // kernel_cra_s0_agent:rf_source_data -> kernel_cra_s0_agent_rsp_fifo:in_data
wire kernel_cra_s0_agent_rf_source_ready; // kernel_cra_s0_agent_rsp_fifo:in_ready -> kernel_cra_s0_agent:rf_source_ready
wire kernel_cra_s0_agent_rsp_fifo_out_endofpacket; // kernel_cra_s0_agent_rsp_fifo:out_endofpacket -> kernel_cra_s0_agent:rf_sink_endofpacket
wire kernel_cra_s0_agent_rsp_fifo_out_valid; // kernel_cra_s0_agent_rsp_fifo:out_valid -> kernel_cra_s0_agent:rf_sink_valid
wire kernel_cra_s0_agent_rsp_fifo_out_startofpacket; // kernel_cra_s0_agent_rsp_fifo:out_startofpacket -> kernel_cra_s0_agent:rf_sink_startofpacket
wire [137:0] kernel_cra_s0_agent_rsp_fifo_out_data; // kernel_cra_s0_agent_rsp_fifo:out_data -> kernel_cra_s0_agent:rf_sink_data
wire kernel_cra_s0_agent_rsp_fifo_out_ready; // kernel_cra_s0_agent:rf_sink_ready -> kernel_cra_s0_agent_rsp_fifo:out_ready
wire kernel_cra_s0_agent_rdata_fifo_src_valid; // kernel_cra_s0_agent:rdata_fifo_src_valid -> kernel_cra_s0_agent:rdata_fifo_sink_valid
wire [65:0] kernel_cra_s0_agent_rdata_fifo_src_data; // kernel_cra_s0_agent:rdata_fifo_src_data -> kernel_cra_s0_agent:rdata_fifo_sink_data
wire kernel_cra_s0_agent_rdata_fifo_src_ready; // kernel_cra_s0_agent:rdata_fifo_sink_ready -> kernel_cra_s0_agent:rdata_fifo_src_ready
wire address_span_extender_0_expanded_master_agent_cp_endofpacket; // address_span_extender_0_expanded_master_agent:cp_endofpacket -> router:sink_endofpacket
wire address_span_extender_0_expanded_master_agent_cp_valid; // address_span_extender_0_expanded_master_agent:cp_valid -> router:sink_valid
wire address_span_extender_0_expanded_master_agent_cp_startofpacket; // address_span_extender_0_expanded_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [100:0] address_span_extender_0_expanded_master_agent_cp_data; // address_span_extender_0_expanded_master_agent:cp_data -> router:sink_data
wire address_span_extender_0_expanded_master_agent_cp_ready; // router:sink_ready -> address_span_extender_0_expanded_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [100:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [0:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire kernel_cra_s0_agent_rp_endofpacket; // kernel_cra_s0_agent:rp_endofpacket -> router_001:sink_endofpacket
wire kernel_cra_s0_agent_rp_valid; // kernel_cra_s0_agent:rp_valid -> router_001:sink_valid
wire kernel_cra_s0_agent_rp_startofpacket; // kernel_cra_s0_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [136:0] kernel_cra_s0_agent_rp_data; // kernel_cra_s0_agent:rp_data -> router_001:sink_data
wire kernel_cra_s0_agent_rp_ready; // router_001:sink_ready -> kernel_cra_s0_agent:rp_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [100:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [0:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [100:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [0:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> kernel_cra_s0_cmd_width_adapter:in_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> kernel_cra_s0_cmd_width_adapter:in_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> kernel_cra_s0_cmd_width_adapter:in_startofpacket
wire [100:0] cmd_mux_src_data; // cmd_mux:src_data -> kernel_cra_s0_cmd_width_adapter:in_data
wire [0:0] cmd_mux_src_channel; // cmd_mux:src_channel -> kernel_cra_s0_cmd_width_adapter:in_channel
wire cmd_mux_src_ready; // kernel_cra_s0_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire kernel_cra_s0_cmd_width_adapter_src_endofpacket; // kernel_cra_s0_cmd_width_adapter:out_endofpacket -> kernel_cra_s0_agent:cp_endofpacket
wire kernel_cra_s0_cmd_width_adapter_src_valid; // kernel_cra_s0_cmd_width_adapter:out_valid -> kernel_cra_s0_agent:cp_valid
wire kernel_cra_s0_cmd_width_adapter_src_startofpacket; // kernel_cra_s0_cmd_width_adapter:out_startofpacket -> kernel_cra_s0_agent:cp_startofpacket
wire [136:0] kernel_cra_s0_cmd_width_adapter_src_data; // kernel_cra_s0_cmd_width_adapter:out_data -> kernel_cra_s0_agent:cp_data
wire kernel_cra_s0_cmd_width_adapter_src_ready; // kernel_cra_s0_agent:cp_ready -> kernel_cra_s0_cmd_width_adapter:out_ready
wire [0:0] kernel_cra_s0_cmd_width_adapter_src_channel; // kernel_cra_s0_cmd_width_adapter:out_channel -> kernel_cra_s0_agent:cp_channel
wire router_001_src_endofpacket; // router_001:src_endofpacket -> kernel_cra_s0_rsp_width_adapter:in_endofpacket
wire router_001_src_valid; // router_001:src_valid -> kernel_cra_s0_rsp_width_adapter:in_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> kernel_cra_s0_rsp_width_adapter:in_startofpacket
wire [136:0] router_001_src_data; // router_001:src_data -> kernel_cra_s0_rsp_width_adapter:in_data
wire [0:0] router_001_src_channel; // router_001:src_channel -> kernel_cra_s0_rsp_width_adapter:in_channel
wire router_001_src_ready; // kernel_cra_s0_rsp_width_adapter:in_ready -> router_001:src_ready
wire kernel_cra_s0_rsp_width_adapter_src_endofpacket; // kernel_cra_s0_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire kernel_cra_s0_rsp_width_adapter_src_valid; // kernel_cra_s0_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire kernel_cra_s0_rsp_width_adapter_src_startofpacket; // kernel_cra_s0_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire [100:0] kernel_cra_s0_rsp_width_adapter_src_data; // kernel_cra_s0_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire kernel_cra_s0_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> kernel_cra_s0_rsp_width_adapter:out_ready
wire [0:0] kernel_cra_s0_rsp_width_adapter_src_channel; // kernel_cra_s0_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) address_span_extender_0_expanded_master_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.uav_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_expanded_master_address), // avalon_anti_master_0.address
.av_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.av_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.av_read (address_span_extender_0_expanded_master_read), // .read
.av_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.av_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.av_write (address_span_extender_0_expanded_master_write), // .write
.av_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) kernel_cra_s0_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cra_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.uav_read (kernel_cra_s0_agent_m0_read), // .read
.uav_write (kernel_cra_s0_agent_m0_write), // .write
.uav_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.uav_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.uav_lock (kernel_cra_s0_agent_m0_lock), // .lock
.uav_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.av_address (kernel_cra_s0_address), // avalon_anti_slave_0.address
.av_write (kernel_cra_s0_write), // .write
.av_read (kernel_cra_s0_read), // .read
.av_readdata (kernel_cra_s0_readdata), // .readdata
.av_writedata (kernel_cra_s0_writedata), // .writedata
.av_burstcount (kernel_cra_s0_burstcount), // .burstcount
.av_byteenable (kernel_cra_s0_byteenable), // .byteenable
.av_readdatavalid (kernel_cra_s0_readdatavalid), // .readdatavalid
.av_waitrequest (kernel_cra_s0_waitrequest), // .waitrequest
.av_debugaccess (kernel_cra_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (91),
.PKT_PROTECTION_L (89),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (76),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (72),
.PKT_ADDR_H (65),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (66),
.PKT_TRANS_POSTED (67),
.PKT_TRANS_WRITE (68),
.PKT_TRANS_READ (69),
.PKT_TRANS_LOCK (70),
.PKT_TRANS_EXCLUSIVE (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (88),
.PKT_THREAD_ID_L (88),
.PKT_CACHE_H (95),
.PKT_CACHE_L (92),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (97),
.PKT_RESPONSE_STATUS_L (96),
.PKT_ORI_BURST_SIZE_L (98),
.PKT_ORI_BURST_SIZE_H (100),
.ST_DATA_W (101),
.ST_CHANNEL_W (1),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_expanded_master_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_address), // av.address
.av_write (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_write), // .write
.av_read (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (address_span_extender_0_expanded_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (address_span_extender_0_expanded_master_agent_cp_valid), // cp.valid
.cp_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.cp_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (address_span_extender_0_expanded_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (120),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (101),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (102),
.PKT_TRANS_POSTED (103),
.PKT_TRANS_WRITE (104),
.PKT_TRANS_READ (105),
.PKT_TRANS_LOCK (106),
.PKT_SRC_ID_H (122),
.PKT_SRC_ID_L (122),
.PKT_DEST_ID_H (123),
.PKT_DEST_ID_L (123),
.PKT_BURSTWRAP_H (112),
.PKT_BURSTWRAP_L (112),
.PKT_BYTE_CNT_H (111),
.PKT_BYTE_CNT_L (108),
.PKT_PROTECTION_H (127),
.PKT_PROTECTION_L (125),
.PKT_RESPONSE_STATUS_H (133),
.PKT_RESPONSE_STATUS_L (132),
.PKT_BURST_SIZE_H (115),
.PKT_BURST_SIZE_L (113),
.PKT_ORI_BURST_SIZE_L (134),
.PKT_ORI_BURST_SIZE_H (136),
.ST_CHANNEL_W (1),
.ST_DATA_W (137),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cra_s0_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (kernel_cra_s0_agent_m0_address), // m0.address
.m0_burstcount (kernel_cra_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (kernel_cra_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (kernel_cra_s0_agent_m0_lock), // .lock
.m0_readdata (kernel_cra_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cra_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (kernel_cra_s0_agent_m0_read), // .read
.m0_waitrequest (kernel_cra_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (kernel_cra_s0_agent_m0_writedata), // .writedata
.m0_write (kernel_cra_s0_agent_m0_write), // .write
.rp_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (kernel_cra_s0_agent_rp_ready), // .ready
.rp_valid (kernel_cra_s0_agent_rp_valid), // .valid
.rp_data (kernel_cra_s0_agent_rp_data), // .data
.rp_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.cp_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.cp_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (kernel_cra_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (kernel_cra_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (kernel_cra_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (kernel_cra_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (kernel_cra_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (kernel_cra_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (138),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) kernel_cra_s0_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (kernel_cra_s0_agent_rf_source_data), // in.data
.in_valid (kernel_cra_s0_agent_rf_source_valid), // .valid
.in_ready (kernel_cra_s0_agent_rf_source_ready), // .ready
.in_startofpacket (kernel_cra_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (kernel_cra_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (kernel_cra_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (kernel_cra_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (kernel_cra_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (kernel_cra_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (kernel_cra_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router router (
.sink_ready (address_span_extender_0_expanded_master_agent_cp_ready), // sink.ready
.sink_valid (address_span_extender_0_expanded_master_agent_cp_valid), // .valid
.sink_data (address_span_extender_0_expanded_master_agent_cp_data), // .data
.sink_startofpacket (address_span_extender_0_expanded_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_expanded_master_agent_cp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_router_001 router_001 (
.sink_ready (kernel_cra_s0_agent_rp_ready), // sink.ready
.sink_valid (kernel_cra_s0_agent_rp_valid), // .valid
.sink_data (kernel_cra_s0_agent_rp_data), // .data
.sink_startofpacket (kernel_cra_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_cmd_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.sink_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (65),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (72),
.IN_PKT_TRANS_COMPRESSED_READ (66),
.IN_PKT_BURSTWRAP_H (76),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (79),
.IN_PKT_BURST_SIZE_L (77),
.IN_PKT_RESPONSE_STATUS_H (97),
.IN_PKT_RESPONSE_STATUS_L (96),
.IN_PKT_TRANS_EXCLUSIVE (71),
.IN_PKT_BURST_TYPE_H (81),
.IN_PKT_BURST_TYPE_L (80),
.IN_PKT_ORI_BURST_SIZE_L (98),
.IN_PKT_ORI_BURST_SIZE_H (100),
.IN_ST_DATA_W (101),
.OUT_PKT_ADDR_H (101),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (111),
.OUT_PKT_BYTE_CNT_L (108),
.OUT_PKT_TRANS_COMPRESSED_READ (102),
.OUT_PKT_BURST_SIZE_H (115),
.OUT_PKT_BURST_SIZE_L (113),
.OUT_PKT_RESPONSE_STATUS_H (133),
.OUT_PKT_RESPONSE_STATUS_L (132),
.OUT_PKT_TRANS_EXCLUSIVE (107),
.OUT_PKT_BURST_TYPE_H (117),
.OUT_PKT_BURST_TYPE_L (116),
.OUT_PKT_ORI_BURST_SIZE_L (134),
.OUT_PKT_ORI_BURST_SIZE_H (136),
.OUT_ST_DATA_W (137),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (kernel_cra_s0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_cmd_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_cmd_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_cmd_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (101),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (111),
.IN_PKT_BYTE_CNT_L (108),
.IN_PKT_TRANS_COMPRESSED_READ (102),
.IN_PKT_BURSTWRAP_H (112),
.IN_PKT_BURSTWRAP_L (112),
.IN_PKT_BURST_SIZE_H (115),
.IN_PKT_BURST_SIZE_L (113),
.IN_PKT_RESPONSE_STATUS_H (133),
.IN_PKT_RESPONSE_STATUS_L (132),
.IN_PKT_TRANS_EXCLUSIVE (107),
.IN_PKT_BURST_TYPE_H (117),
.IN_PKT_BURST_TYPE_L (116),
.IN_PKT_ORI_BURST_SIZE_L (134),
.IN_PKT_ORI_BURST_SIZE_H (136),
.IN_ST_DATA_W (137),
.OUT_PKT_ADDR_H (65),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (72),
.OUT_PKT_TRANS_COMPRESSED_READ (66),
.OUT_PKT_BURST_SIZE_H (79),
.OUT_PKT_BURST_SIZE_L (77),
.OUT_PKT_RESPONSE_STATUS_H (97),
.OUT_PKT_RESPONSE_STATUS_L (96),
.OUT_PKT_TRANS_EXCLUSIVE (71),
.OUT_PKT_BURST_TYPE_H (81),
.OUT_PKT_BURST_TYPE_L (80),
.OUT_PKT_ORI_BURST_SIZE_L (98),
.OUT_PKT_ORI_BURST_SIZE_H (100),
.OUT_ST_DATA_W (101),
.ST_CHANNEL_W (1),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) kernel_cra_s0_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (kernel_cra_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_001_src_valid), // sink.valid
.in_channel (router_001_src_channel), // .channel
.in_startofpacket (router_001_src_startofpacket), // .startofpacket
.in_endofpacket (router_001_src_endofpacket), // .endofpacket
.in_ready (router_001_src_ready), // .ready
.in_data (router_001_src_data), // .data
.out_endofpacket (kernel_cra_s0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (kernel_cra_s0_rsp_width_adapter_src_data), // .data
.out_channel (kernel_cra_s0_rsp_width_adapter_src_channel), // .channel
.out_valid (kernel_cra_s0_rsp_width_adapter_src_valid), // .valid
.out_ready (kernel_cra_s0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (kernel_cra_s0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
endmodule
|
module signalinput(
input [1:0] testmode, // 00, 01, 10, 11 分别代表4种频率,
// 分别为 3125, 250, 50, 12500Hz, 使用 SW1~SW0 来控制
input sysclk, // 系统时钟100M
output sigin1 // 输出待测信号
);
reg [20:0] state;
reg [20:0] divide;
reg sigin;
assign sigin1 = sigin;
initial
begin
sigin = 0;
state = 21'b000000000000000000000;
divide = 21'b0_0000_0111_1101_0000_0000;
end
always @(testmode)
begin
case(testmode[1:0])
2'b00: divide = 21'b0_0000_0111_1101_0000_0000; // 3125Hz, 分频比为32000
2'b01: divide = 21'b0_0000_0011_1110_1000_0000; // 6250Hz, 分频比为16000
2'b10: divide = 21'b1_1110_1000_0100_1000_0000; // 50Hz, 分频比为2000000
2'b11: divide = 21'b0_0000_0001_1111_0100_0000; // 12500Hz, 分频比为8000
endcase
end
always @(posedge sysclk) // 按divide分频
begin
if(state == 0)
sigin = ~sigin;
state = state + 21'd2;
if(state == divide)
state = 0;
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* Testbench for the non-synthesizable behavioral model for the
* instruction memory
*/
// Import the modules that will be tested for in this testbench
`include "instrmem.v"
// IMPORTANT: To run this, try: ncverilog -f instrmem.f +gui
module tb_instrmem ();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the instruction memory
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// instr output signals
wire [0:31] instruction;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// enb;
reg enable;
// instr_addr
reg [0:127] instruction_address;
reg [0:31] counter;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
parameter size_of_input2 = 4'd8;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
// always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 10ns <==> 100 MHz clock
*/
// #5 clock = 0;
// #5 clock = 1;
// end
// ============================================================
/**
* Instantiate an instance of instr_mem() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "im"
*/
instr_mem im (
// instance_name(signal name),
// Signal name can be the same as the instance name
instruction_address,instruction,enable);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
instruction_address=32'd10;
enable=1'd0;
counter=32'd0;
#30
instruction_address=32'd0;
enable=1'd1;
//counter=32'd0;
#30
instruction_address=32'd1;
enable=1'd1;
#30
instruction_address=32'd2;
enable=1'd1;
#30
instruction_address=32'd3;
enable=1'd1;
/*
instruction_address=8'd200;
reset=1'b0;
*/
// Try reading the instruction memory without being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
// Randomly set the instruction address to a value
instruction_address=counter;
// Reset the instruction memory
enable=1'b1;
counter=counter+3'd1;
end
// Reset the instruction memory
#10
instruction_address=8'd180;
enable=1'b0;
// Read the instruction memory after being reset
for(count=0;count<=size_of_input;count=count+1)
begin
#10
// Randomly set the instruction address to a value
instruction_address=counter;
// Reset the instruction memory
enable=1'b1;
counter=counter+3'd1;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/**************************************************************************
Sync FIFO
-parameter N
Queue data vector width
Example : DATA[3:0] is N=4
-parameter DEPTH
Queue entry depth
Example DEPTH 16 is DEPTH=16
-parameter D_N
Queue entry depth n size
Example PARAMETER_DEPTH16 is 4
-Make : 2013/2/13
-Update :
Takahiro Ito
**************************************************************************/
`default_nettype none
module mist1032sa_sync_fifo
#(
parameter N = 16,
parameter DEPTH = 4,
parameter D_N = 2
)(
//System
input wire iCLOCK,
input wire inRESET,
input wire iREMOVE,
//Counter
output wire [D_N-1:0] oCOUNT,
//WR
input wire iWR_EN,
input wire [N-1:0] iWR_DATA,
output wire oWR_FULL,
//RD
input wire iRD_EN,
output wire [N-1:0] oRD_DATA,
output wire oRD_EMPTY
);
//Count - Wire
wire [D_N:0] count;
//Reg
reg [D_N:0] b_write_pointer;
reg [D_N:0] b_read_pointer;
reg [N-1:0] b_memory [0 : DEPTH-1];
assign count = b_write_pointer - b_read_pointer;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_write_pointer <= {D_N+1{1'b0}};
b_read_pointer <= {D_N+1{1'b0}};
end
else if(iREMOVE)begin
b_write_pointer <= {D_N+1{1'b0}};
b_read_pointer <= {D_N+1{1'b0}};
end
else begin
if(iWR_EN)begin
b_write_pointer <= b_write_pointer + {{D_N-1{1'b0}}, 1'b1};
b_memory [b_write_pointer[D_N-1:0]] <= iWR_DATA;
end
if(iRD_EN)begin
b_read_pointer <= b_read_pointer + {{D_N-1{1'b0}}, 1'b1};
end
end
end //always
//Assign
assign oRD_DATA = b_memory [b_read_pointer[D_N-1:0]];
assign oRD_EMPTY = ((b_write_pointer - b_read_pointer) == {D_N+1{1'b0}})? 1'b1 : 1'b0;
assign oWR_FULL = count[D_N];//|| (count [D_N-1:0] == {D_N{1'b1}})? 1'b1 : 1'b0;
assign oCOUNT = count [D_N-1:0];
endmodule
`default_nettype wire
|
// TODO: Make far ptr relative to root
`include "raycast_defines.v"
module raycast_master
(
// WB Master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
m_wb_cti_o, m_wb_bte_o,
// Controller i/o
ctrl_wb_adr_i, ctrl_wb_sel_i, ctrl_wb_we_i,
ctrl_wb_dat_o, ctrl_wb_dat_i, ctrl_wb_cyc_i,
ctrl_wb_stb_i, ctrl_wb_ack_o,
ctrl_wb_cti_i, ctrl_wb_bte_i,
// Core i/o
`ifdef CORE0
c0_wb_adr_i, c0_wb_dat_o, c0_wb_cyc_i, c0_wb_stb_i,
c0_wb_ack_o,
`endif
`ifdef CORE1
c1_wb_adr_i, c1_wb_dat_o, c1_wb_cyc_i, c1_wb_stb_i,
c1_wb_ack_o,
`endif
`ifdef CORE2
c2_wb_adr_i, c2_wb_dat_o, c2_wb_cyc_i, c2_wb_stb_i,
c2_wb_ack_o,
`endif
`ifdef CORE3
c3_wb_adr_i, c3_wb_dat_o, c3_wb_cyc_i, c3_wb_stb_i,
c3_wb_ack_o,
`endif
wb_clk, wb_rst,
);
// = Parameters =
parameter CS = 64, CS_L2 = 6;
parameter WRAP_BITS = 5;
parameter WRAP_CNT = 8;
parameter WRAP_BTE = 2'b00; // 01 for 4-beat, 10 for 8-beat, 11 for 16-beat
// --
// = Ports =
input wb_clk;
input wb_rst;
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
input [31:0] ctrl_wb_adr_i;
input [3:0] ctrl_wb_sel_i;
input ctrl_wb_we_i;
output [31:0] ctrl_wb_dat_o;
input [31:0] ctrl_wb_dat_i;
input ctrl_wb_cyc_i;
input ctrl_wb_stb_i;
output ctrl_wb_ack_o;
input [2:0] ctrl_wb_cti_i;
input [1:0] ctrl_wb_bte_i;
`ifdef CORE0
input c0_wb_cyc_i;
input c0_wb_stb_i;
input [31:0] c0_wb_adr_i;
output c0_wb_ack_o;
output reg [31:0] c0_wb_dat_o;
wire c0_wb_req = c0_wb_cyc_i & c0_wb_stb_i;
assign c0_wb_ack_o = c0_ack & c0_wb_cyc_i;
`else
wire [31:0] c0_wb_adr_i = 0;
reg [31:0] c0_wb_dat_o;
wire c0_wb_req = 0;
`endif
`ifdef CORE1
input c1_wb_cyc_i;
input c1_wb_stb_i;
input [31:0] c1_wb_adr_i;
output c1_wb_ack_o;
output reg [31:0] c1_wb_dat_o;
wire c1_wb_req = c1_wb_cyc_i & c1_wb_stb_i;
assign c1_wb_ack_o = c1_ack & c1_wb_cyc_i;
`else
wire [31:0] c1_wb_adr_i = 0;
reg [31:0] c1_wb_dat_o;
wire c1_wb_req = 0;
`endif
`ifdef CORE2
input c2_wb_cyc_i;
input c2_wb_stb_i;
input [31:0] c2_wb_adr_i;
output c2_wb_ack_o;
output reg [31:0] c2_wb_dat_o;
wire c2_wb_req = c2_wb_cyc_i & c2_wb_stb_i;
assign c2_wb_ack_o = c2_ack & c2_wb_cyc_i;
`else
wire [31:0] c2_wb_adr_i = 0;
reg [31:0] c2_wb_dat_o;
wire c2_wb_req = 0;
`endif
`ifdef CORE3
input c3_wb_cyc_i;
input c3_wb_stb_i;
input [31:0] c3_wb_adr_i;
output c3_wb_ack_o;
output reg [31:0] c3_wb_dat_o;
wire c3_wb_req = c3_wb_cyc_i & c3_wb_stb_i;
assign c3_wb_ack_o = c3_ack & c3_wb_cyc_i;
`else
wire [31:0] c3_wb_adr_i = 0;
reg [31:0] c3_wb_dat_o;
wire c3_wb_req = 0;
`endif
// --
// == Registers/memories =
reg cache_updating;
reg [3:0] servicing_core;
reg c0_ack, c1_ack, c2_ack, c3_ack;
reg reading_cache;
reg cache_did_write;
reg cache_wb_cyc;
reg [2:0] cache_wb_cti;
reg [2:0] cache_burst_cnt;
reg m_wb_blank;
reg [31:0] cache_adr;
reg [31:0] cache [0:CS-1];
reg [31:0] tags [0:CS-1];
reg valid [0:CS-1];
reg [31:0] cache_hits = 0;
reg [31:0] cache_miss = 0;
// --
// ==
wire [CS_L2-1:0] cache_ptr = cache_adr[CS_L2-1:0];
wire [31:0] cache_out = cache[cache_ptr];
wire [31:0] tags_out = tags[cache_ptr];
wire valid_out = valid[cache_ptr];
wire cache_hit = (valid_out==1) && (tags[cache_ptr]==cache_adr);
wire [WRAP_BITS-1:0] cache_wrap_inc = cache_adr[WRAP_BITS:0]+4'd4;
wire cache_write = cache_updating && m_wb_ack_i;
// --
assign m_wb_cyc_o = !m_wb_blank & (!cache_updating ? ctrl_wb_cyc_i : cache_wb_cyc) ;
assign m_wb_stb_o = !m_wb_blank & (!cache_updating ? ctrl_wb_stb_i : cache_wb_cyc) ;
assign m_wb_adr_o = !cache_updating ? ctrl_wb_adr_i : cache_adr ;
assign m_wb_sel_o = (!cache_updating & !m_wb_blank) ? ctrl_wb_sel_i : 4'b1111 ;
assign m_wb_we_o = (!cache_updating & !m_wb_blank) ? ctrl_wb_we_i : 0 ;
assign m_wb_dat_o = (!cache_updating & !m_wb_blank) ? ctrl_wb_dat_i : 0 ;
assign m_wb_cti_o = (!cache_updating & !m_wb_blank) ? ctrl_wb_cti_i : 0;//cache_wb_cti ;
assign m_wb_bte_o = (!cache_updating & !m_wb_blank) ? ctrl_wb_bte_i : WRAP_BTE ;
assign ctrl_wb_dat_o = (!cache_updating & !m_wb_blank) ? m_wb_dat_i: 32'b0;
assign ctrl_wb_ack_o = !m_wb_blank & !cache_updating & m_wb_ack_i;
always @(posedge wb_clk) begin
if (wb_rst) begin
cache_updating <= 0;
m_wb_blank <= 0;
end
else begin
if (m_wb_blank) begin
m_wb_blank <= 0;
end
else begin
if (cache_updating) begin
if (m_wb_ack_i) begin
// cache_burst_cnt <= cache_burst_cnt-1;
// if (cache_burst_cnt==1) begin
// cache_wb_cti <= 3'b111;
// end
// if (cache_burst_cnt==0) begin
cache_updating <= 0;
m_wb_blank <= 1;
// end
end
end
else if (!ctrl_wb_cyc_i && cache_wb_cyc) begin
cache_updating <= 1;
m_wb_blank <= 1;
// cache_wb_cti <= 3'b010;
// cache_burst_cnt <= WRAP_CNT-1;
end
end
end
end
always @(posedge wb_clk) begin
if (wb_rst) begin
servicing_core <= 4'b0;
reading_cache <= 0;
cache_adr <= 0;
end
else if (!reading_cache && !cache_wb_cyc) begin
if (c0_wb_req && !c0_ack) begin
cache_adr <= c0_wb_adr_i;
servicing_core[0] <= 1;
reading_cache <= 1;
end else
if (c1_wb_req && !c1_ack) begin
cache_adr <= c1_wb_adr_i;
servicing_core[1] <= 1;
reading_cache <= 1;
end else
if (c2_wb_req && !c2_ack) begin
cache_adr <= c2_wb_adr_i;
servicing_core[2] <= 1;
reading_cache <= 1;
end else
if (c3_wb_req && !c3_ack) begin
cache_adr <= c3_wb_adr_i;
servicing_core[3] <= 1;
reading_cache <= 1;
end
end
else begin
reading_cache <= 0;
if (cache_write)
cache_adr <= {cache_adr[31:WRAP_BITS], cache_wrap_inc};
if (cache_hit || cache_write)
servicing_core <= 0;
end
end
always @(posedge wb_clk) begin
if (wb_rst) begin
// c0_wb_dat_o <= 0;
// c1_wb_dat_o <= 0;
// c2_wb_dat_o <= 0;
// c3_wb_dat_o <= 0;
cache_wb_cyc <= 0;
end
else if (cache_wb_cyc) begin
if (cache_write) begin
cache_miss = cache_miss + 1;
if (servicing_core[0]) begin
c0_wb_dat_o <= m_wb_dat_i;
end
if (servicing_core[1]) begin
c1_wb_dat_o <= m_wb_dat_i;
end
if (servicing_core[2]) begin
c2_wb_dat_o <= m_wb_dat_i;
end
if (servicing_core[3]) begin
c3_wb_dat_o <= m_wb_dat_i;
end
// if (cache_burst_cnt==0)
cache_wb_cyc <= 0;
end
end
else if (reading_cache) begin
if (cache_hit) begin
cache_hits = cache_hits + 1;
if (servicing_core[0]) begin
c0_wb_dat_o <= cache_out;
end
if (servicing_core[1]) begin
c1_wb_dat_o <= cache_out;
end
if (servicing_core[2]) begin
c2_wb_dat_o <= cache_out;
end
if (servicing_core[3]) begin
c3_wb_dat_o <= cache_out;
end
end
else begin
cache_wb_cyc <= 1;
end
end
end
always @(posedge wb_clk)
begin
if (cache_write) begin
cache_did_write <= 1;
cache[cache_ptr] <= m_wb_dat_i;
tags[cache_ptr] <= cache_adr;
valid[cache_ptr] <= 1;
end
else begin
cache_did_write <= 0;
end
end
always @(posedge wb_clk)
if (wb_rst)
c0_ack <= 0;
else if (c0_ack)
c0_ack <= 0;
else if (servicing_core[0]) begin
if (cache_did_write)
c0_ack <= 1;
else if (reading_cache && cache_hit)
c0_ack <= 1;
end
always @(posedge wb_clk)
if (wb_rst)
c1_ack <= 0;
else if (c1_ack)
c1_ack <= 0;
else if (servicing_core[1]) begin
if (cache_did_write)
c1_ack <= 1;
else if (reading_cache && cache_hit)
c1_ack <= 1;
end
always @(posedge wb_clk)
if (wb_rst)
c2_ack <= 0;
else if (c2_ack)
c2_ack <= 0;
else if (servicing_core[2]) begin
if (cache_did_write)
c2_ack <= 1;
else if (reading_cache && cache_hit)
c2_ack <= 1;
end
always @(posedge wb_clk)
if (wb_rst)
c3_ack <= 0;
else if (c3_ack)
c3_ack <= 0;
else if (servicing_core[3]) begin
if (cache_did_write)
c3_ack <= 1;
else if (reading_cache && cache_hit)
c3_ack <= 1;
end
integer k;
initial
for (k = 0; k < CS - 1; k = k + 1)
begin
cache[k] = 0;
tags[k] = 0;
valid[k] = 0;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// to_raw_mem_request_get O 353
// RDY_to_raw_mem_request_get O 1
// RDY_to_raw_mem_response_put O 1
// get_to_console_get O 8 reg
// RDY_get_to_console_get O 1 reg
// RDY_put_from_console_put O 1 reg
// status O 8 const
// RDY_set_verbosity O 1 const
// RDY_set_watch_tohost O 1 const
// mv_tohost_value O 64 reg
// RDY_mv_tohost_value O 1 const
// RDY_ma_ddr4_ready O 1 const
// mv_status O 8
// CLK I 1 clock
// RST_N I 1 reset
// to_raw_mem_response_put I 256
// put_from_console_put I 8 reg
// set_verbosity_verbosity I 4 reg
// set_verbosity_logdelay I 64 reg
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_to_raw_mem_response_put I 1
// EN_put_from_console_put I 1
// EN_set_verbosity I 1
// EN_set_watch_tohost I 1
// EN_ma_ddr4_ready I 1
// EN_to_raw_mem_request_get I 1
// EN_get_to_console_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSoC_Top(CLK,
RST_N,
EN_to_raw_mem_request_get,
to_raw_mem_request_get,
RDY_to_raw_mem_request_get,
to_raw_mem_response_put,
EN_to_raw_mem_response_put,
RDY_to_raw_mem_response_put,
EN_get_to_console_get,
get_to_console_get,
RDY_get_to_console_get,
put_from_console_put,
EN_put_from_console_put,
RDY_put_from_console_put,
status,
set_verbosity_verbosity,
set_verbosity_logdelay,
EN_set_verbosity,
RDY_set_verbosity,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost,
mv_tohost_value,
RDY_mv_tohost_value,
EN_ma_ddr4_ready,
RDY_ma_ddr4_ready,
mv_status);
input CLK;
input RST_N;
// actionvalue method to_raw_mem_request_get
input EN_to_raw_mem_request_get;
output [352 : 0] to_raw_mem_request_get;
output RDY_to_raw_mem_request_get;
// action method to_raw_mem_response_put
input [255 : 0] to_raw_mem_response_put;
input EN_to_raw_mem_response_put;
output RDY_to_raw_mem_response_put;
// actionvalue method get_to_console_get
input EN_get_to_console_get;
output [7 : 0] get_to_console_get;
output RDY_get_to_console_get;
// action method put_from_console_put
input [7 : 0] put_from_console_put;
input EN_put_from_console_put;
output RDY_put_from_console_put;
// value method status
output [7 : 0] status;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input [63 : 0] set_verbosity_logdelay;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// value method mv_tohost_value
output [63 : 0] mv_tohost_value;
output RDY_mv_tohost_value;
// action method ma_ddr4_ready
input EN_ma_ddr4_ready;
output RDY_ma_ddr4_ready;
// value method mv_status
output [7 : 0] mv_status;
// signals for module outputs
wire [352 : 0] to_raw_mem_request_get;
wire [63 : 0] mv_tohost_value;
wire [7 : 0] get_to_console_get, mv_status, status;
wire RDY_get_to_console_get,
RDY_ma_ddr4_ready,
RDY_mv_tohost_value,
RDY_put_from_console_put,
RDY_set_verbosity,
RDY_set_watch_tohost,
RDY_to_raw_mem_request_get,
RDY_to_raw_mem_response_put;
// register rg_state
reg [1 : 0] rg_state;
wire [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule boot_rom
wire [63 : 0] boot_rom$set_addr_map_addr_base,
boot_rom$set_addr_map_addr_lim,
boot_rom$slave_araddr,
boot_rom$slave_awaddr,
boot_rom$slave_rdata,
boot_rom$slave_wdata;
wire [15 : 0] boot_rom$slave_arid,
boot_rom$slave_awid,
boot_rom$slave_bid,
boot_rom$slave_rid;
wire [7 : 0] boot_rom$slave_arlen,
boot_rom$slave_awlen,
boot_rom$slave_wstrb;
wire [3 : 0] boot_rom$slave_arcache,
boot_rom$slave_arqos,
boot_rom$slave_arregion,
boot_rom$slave_awcache,
boot_rom$slave_awqos,
boot_rom$slave_awregion;
wire [2 : 0] boot_rom$slave_arprot,
boot_rom$slave_arsize,
boot_rom$slave_awprot,
boot_rom$slave_awsize;
wire [1 : 0] boot_rom$slave_arburst,
boot_rom$slave_awburst,
boot_rom$slave_bresp,
boot_rom$slave_rresp;
wire boot_rom$EN_set_addr_map,
boot_rom$slave_arlock,
boot_rom$slave_arready,
boot_rom$slave_arvalid,
boot_rom$slave_awlock,
boot_rom$slave_awready,
boot_rom$slave_awvalid,
boot_rom$slave_bready,
boot_rom$slave_bvalid,
boot_rom$slave_rlast,
boot_rom$slave_rready,
boot_rom$slave_rvalid,
boot_rom$slave_wlast,
boot_rom$slave_wready,
boot_rom$slave_wvalid;
// ports of submodule boot_rom_axi4_deburster
wire [63 : 0] boot_rom_axi4_deburster$from_master_araddr,
boot_rom_axi4_deburster$from_master_awaddr,
boot_rom_axi4_deburster$from_master_rdata,
boot_rom_axi4_deburster$from_master_wdata,
boot_rom_axi4_deburster$to_slave_araddr,
boot_rom_axi4_deburster$to_slave_awaddr,
boot_rom_axi4_deburster$to_slave_rdata,
boot_rom_axi4_deburster$to_slave_wdata;
wire [15 : 0] boot_rom_axi4_deburster$from_master_arid,
boot_rom_axi4_deburster$from_master_awid,
boot_rom_axi4_deburster$from_master_bid,
boot_rom_axi4_deburster$from_master_rid,
boot_rom_axi4_deburster$to_slave_arid,
boot_rom_axi4_deburster$to_slave_awid,
boot_rom_axi4_deburster$to_slave_bid,
boot_rom_axi4_deburster$to_slave_rid;
wire [7 : 0] boot_rom_axi4_deburster$from_master_arlen,
boot_rom_axi4_deburster$from_master_awlen,
boot_rom_axi4_deburster$from_master_wstrb,
boot_rom_axi4_deburster$to_slave_arlen,
boot_rom_axi4_deburster$to_slave_awlen,
boot_rom_axi4_deburster$to_slave_wstrb;
wire [3 : 0] boot_rom_axi4_deburster$from_master_arcache,
boot_rom_axi4_deburster$from_master_arqos,
boot_rom_axi4_deburster$from_master_arregion,
boot_rom_axi4_deburster$from_master_awcache,
boot_rom_axi4_deburster$from_master_awqos,
boot_rom_axi4_deburster$from_master_awregion,
boot_rom_axi4_deburster$to_slave_arcache,
boot_rom_axi4_deburster$to_slave_arqos,
boot_rom_axi4_deburster$to_slave_arregion,
boot_rom_axi4_deburster$to_slave_awcache,
boot_rom_axi4_deburster$to_slave_awqos,
boot_rom_axi4_deburster$to_slave_awregion;
wire [2 : 0] boot_rom_axi4_deburster$from_master_arprot,
boot_rom_axi4_deburster$from_master_arsize,
boot_rom_axi4_deburster$from_master_awprot,
boot_rom_axi4_deburster$from_master_awsize,
boot_rom_axi4_deburster$to_slave_arprot,
boot_rom_axi4_deburster$to_slave_arsize,
boot_rom_axi4_deburster$to_slave_awprot,
boot_rom_axi4_deburster$to_slave_awsize;
wire [1 : 0] boot_rom_axi4_deburster$from_master_arburst,
boot_rom_axi4_deburster$from_master_awburst,
boot_rom_axi4_deburster$from_master_bresp,
boot_rom_axi4_deburster$from_master_rresp,
boot_rom_axi4_deburster$to_slave_arburst,
boot_rom_axi4_deburster$to_slave_awburst,
boot_rom_axi4_deburster$to_slave_bresp,
boot_rom_axi4_deburster$to_slave_rresp;
wire boot_rom_axi4_deburster$EN_reset,
boot_rom_axi4_deburster$from_master_arlock,
boot_rom_axi4_deburster$from_master_arready,
boot_rom_axi4_deburster$from_master_arvalid,
boot_rom_axi4_deburster$from_master_awlock,
boot_rom_axi4_deburster$from_master_awready,
boot_rom_axi4_deburster$from_master_awvalid,
boot_rom_axi4_deburster$from_master_bready,
boot_rom_axi4_deburster$from_master_bvalid,
boot_rom_axi4_deburster$from_master_rlast,
boot_rom_axi4_deburster$from_master_rready,
boot_rom_axi4_deburster$from_master_rvalid,
boot_rom_axi4_deburster$from_master_wlast,
boot_rom_axi4_deburster$from_master_wready,
boot_rom_axi4_deburster$from_master_wvalid,
boot_rom_axi4_deburster$to_slave_arlock,
boot_rom_axi4_deburster$to_slave_arready,
boot_rom_axi4_deburster$to_slave_arvalid,
boot_rom_axi4_deburster$to_slave_awlock,
boot_rom_axi4_deburster$to_slave_awready,
boot_rom_axi4_deburster$to_slave_awvalid,
boot_rom_axi4_deburster$to_slave_bready,
boot_rom_axi4_deburster$to_slave_bvalid,
boot_rom_axi4_deburster$to_slave_rlast,
boot_rom_axi4_deburster$to_slave_rready,
boot_rom_axi4_deburster$to_slave_rvalid,
boot_rom_axi4_deburster$to_slave_wlast,
boot_rom_axi4_deburster$to_slave_wready,
boot_rom_axi4_deburster$to_slave_wvalid;
// ports of submodule core
wire [511 : 0] core$dma_server_wdata;
wire [63 : 0] core$core_mem_master_araddr,
core$core_mem_master_awaddr,
core$core_mem_master_rdata,
core$core_mem_master_wdata,
core$cpu_imem_master_araddr,
core$cpu_imem_master_awaddr,
core$cpu_imem_master_rdata,
core$cpu_imem_master_wdata,
core$dma_server_araddr,
core$dma_server_awaddr,
core$dma_server_wstrb,
core$mv_tohost_value,
core$set_verbosity_logdelay,
core$set_watch_tohost_tohost_addr;
wire [15 : 0] core$core_mem_master_arid,
core$core_mem_master_awid,
core$core_mem_master_bid,
core$core_mem_master_rid,
core$cpu_imem_master_arid,
core$cpu_imem_master_awid,
core$cpu_imem_master_bid,
core$cpu_imem_master_rid,
core$dma_server_arid,
core$dma_server_awid;
wire [7 : 0] core$core_mem_master_arlen,
core$core_mem_master_awlen,
core$core_mem_master_wstrb,
core$cpu_imem_master_arlen,
core$cpu_imem_master_awlen,
core$cpu_imem_master_wstrb,
core$dma_server_arlen,
core$dma_server_awlen,
core$mv_status;
wire [3 : 0] core$core_mem_master_arcache,
core$core_mem_master_arqos,
core$core_mem_master_arregion,
core$core_mem_master_awcache,
core$core_mem_master_awqos,
core$core_mem_master_awregion,
core$cpu_imem_master_arcache,
core$cpu_imem_master_arqos,
core$cpu_imem_master_arregion,
core$cpu_imem_master_awcache,
core$cpu_imem_master_awqos,
core$cpu_imem_master_awregion,
core$dma_server_arcache,
core$dma_server_arqos,
core$dma_server_arregion,
core$dma_server_awcache,
core$dma_server_awqos,
core$dma_server_awregion,
core$set_verbosity_verbosity;
wire [2 : 0] core$core_mem_master_arprot,
core$core_mem_master_arsize,
core$core_mem_master_awprot,
core$core_mem_master_awsize,
core$cpu_imem_master_arprot,
core$cpu_imem_master_arsize,
core$cpu_imem_master_awprot,
core$cpu_imem_master_awsize,
core$dma_server_arprot,
core$dma_server_arsize,
core$dma_server_awprot,
core$dma_server_awsize;
wire [1 : 0] core$core_mem_master_arburst,
core$core_mem_master_awburst,
core$core_mem_master_bresp,
core$core_mem_master_rresp,
core$cpu_imem_master_arburst,
core$cpu_imem_master_awburst,
core$cpu_imem_master_bresp,
core$cpu_imem_master_rresp,
core$dma_server_arburst,
core$dma_server_awburst;
wire core$EN_cpu_reset_server_request_put,
core$EN_cpu_reset_server_response_get,
core$EN_ma_ddr4_ready,
core$EN_set_verbosity,
core$EN_set_watch_tohost,
core$RDY_cpu_reset_server_request_put,
core$RDY_cpu_reset_server_response_get,
core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear,
core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear,
core$core_mem_master_arlock,
core$core_mem_master_arready,
core$core_mem_master_arvalid,
core$core_mem_master_awlock,
core$core_mem_master_awready,
core$core_mem_master_awvalid,
core$core_mem_master_bready,
core$core_mem_master_bvalid,
core$core_mem_master_rlast,
core$core_mem_master_rready,
core$core_mem_master_rvalid,
core$core_mem_master_wlast,
core$core_mem_master_wready,
core$core_mem_master_wvalid,
core$cpu_imem_master_arlock,
core$cpu_imem_master_arready,
core$cpu_imem_master_arvalid,
core$cpu_imem_master_awlock,
core$cpu_imem_master_awready,
core$cpu_imem_master_awvalid,
core$cpu_imem_master_bready,
core$cpu_imem_master_bvalid,
core$cpu_imem_master_rlast,
core$cpu_imem_master_rready,
core$cpu_imem_master_rvalid,
core$cpu_imem_master_wlast,
core$cpu_imem_master_wready,
core$cpu_imem_master_wvalid,
core$cpu_reset_server_request_put,
core$dma_server_arlock,
core$dma_server_arvalid,
core$dma_server_awlock,
core$dma_server_awvalid,
core$dma_server_bready,
core$dma_server_rready,
core$dma_server_wlast,
core$dma_server_wvalid,
core$nmi_req_set_not_clear,
core$set_watch_tohost_watch_tohost;
// ports of submodule fabric
wire [63 : 0] fabric$v_from_masters_0_araddr,
fabric$v_from_masters_0_awaddr,
fabric$v_from_masters_0_rdata,
fabric$v_from_masters_0_wdata,
fabric$v_from_masters_1_araddr,
fabric$v_from_masters_1_awaddr,
fabric$v_from_masters_1_rdata,
fabric$v_from_masters_1_wdata,
fabric$v_to_slaves_0_araddr,
fabric$v_to_slaves_0_awaddr,
fabric$v_to_slaves_0_rdata,
fabric$v_to_slaves_0_wdata,
fabric$v_to_slaves_1_araddr,
fabric$v_to_slaves_1_awaddr,
fabric$v_to_slaves_1_rdata,
fabric$v_to_slaves_1_wdata,
fabric$v_to_slaves_2_araddr,
fabric$v_to_slaves_2_awaddr,
fabric$v_to_slaves_2_rdata,
fabric$v_to_slaves_2_wdata;
wire [15 : 0] fabric$v_from_masters_0_arid,
fabric$v_from_masters_0_awid,
fabric$v_from_masters_0_bid,
fabric$v_from_masters_0_rid,
fabric$v_from_masters_1_arid,
fabric$v_from_masters_1_awid,
fabric$v_from_masters_1_bid,
fabric$v_from_masters_1_rid,
fabric$v_to_slaves_0_arid,
fabric$v_to_slaves_0_awid,
fabric$v_to_slaves_0_bid,
fabric$v_to_slaves_0_rid,
fabric$v_to_slaves_1_arid,
fabric$v_to_slaves_1_awid,
fabric$v_to_slaves_1_bid,
fabric$v_to_slaves_1_rid,
fabric$v_to_slaves_2_arid,
fabric$v_to_slaves_2_awid,
fabric$v_to_slaves_2_bid,
fabric$v_to_slaves_2_rid;
wire [7 : 0] fabric$v_from_masters_0_arlen,
fabric$v_from_masters_0_awlen,
fabric$v_from_masters_0_wstrb,
fabric$v_from_masters_1_arlen,
fabric$v_from_masters_1_awlen,
fabric$v_from_masters_1_wstrb,
fabric$v_to_slaves_0_arlen,
fabric$v_to_slaves_0_awlen,
fabric$v_to_slaves_0_wstrb,
fabric$v_to_slaves_1_arlen,
fabric$v_to_slaves_1_awlen,
fabric$v_to_slaves_1_wstrb,
fabric$v_to_slaves_2_arlen,
fabric$v_to_slaves_2_awlen,
fabric$v_to_slaves_2_wstrb;
wire [3 : 0] fabric$set_verbosity_verbosity,
fabric$v_from_masters_0_arcache,
fabric$v_from_masters_0_arqos,
fabric$v_from_masters_0_arregion,
fabric$v_from_masters_0_awcache,
fabric$v_from_masters_0_awqos,
fabric$v_from_masters_0_awregion,
fabric$v_from_masters_1_arcache,
fabric$v_from_masters_1_arqos,
fabric$v_from_masters_1_arregion,
fabric$v_from_masters_1_awcache,
fabric$v_from_masters_1_awqos,
fabric$v_from_masters_1_awregion,
fabric$v_to_slaves_0_arcache,
fabric$v_to_slaves_0_arqos,
fabric$v_to_slaves_0_arregion,
fabric$v_to_slaves_0_awcache,
fabric$v_to_slaves_0_awqos,
fabric$v_to_slaves_0_awregion,
fabric$v_to_slaves_1_arcache,
fabric$v_to_slaves_1_arqos,
fabric$v_to_slaves_1_arregion,
fabric$v_to_slaves_1_awcache,
fabric$v_to_slaves_1_awqos,
fabric$v_to_slaves_1_awregion,
fabric$v_to_slaves_2_arcache,
fabric$v_to_slaves_2_arqos,
fabric$v_to_slaves_2_arregion,
fabric$v_to_slaves_2_awcache,
fabric$v_to_slaves_2_awqos,
fabric$v_to_slaves_2_awregion;
wire [2 : 0] fabric$v_from_masters_0_arprot,
fabric$v_from_masters_0_arsize,
fabric$v_from_masters_0_awprot,
fabric$v_from_masters_0_awsize,
fabric$v_from_masters_1_arprot,
fabric$v_from_masters_1_arsize,
fabric$v_from_masters_1_awprot,
fabric$v_from_masters_1_awsize,
fabric$v_to_slaves_0_arprot,
fabric$v_to_slaves_0_arsize,
fabric$v_to_slaves_0_awprot,
fabric$v_to_slaves_0_awsize,
fabric$v_to_slaves_1_arprot,
fabric$v_to_slaves_1_arsize,
fabric$v_to_slaves_1_awprot,
fabric$v_to_slaves_1_awsize,
fabric$v_to_slaves_2_arprot,
fabric$v_to_slaves_2_arsize,
fabric$v_to_slaves_2_awprot,
fabric$v_to_slaves_2_awsize;
wire [1 : 0] fabric$v_from_masters_0_arburst,
fabric$v_from_masters_0_awburst,
fabric$v_from_masters_0_bresp,
fabric$v_from_masters_0_rresp,
fabric$v_from_masters_1_arburst,
fabric$v_from_masters_1_awburst,
fabric$v_from_masters_1_bresp,
fabric$v_from_masters_1_rresp,
fabric$v_to_slaves_0_arburst,
fabric$v_to_slaves_0_awburst,
fabric$v_to_slaves_0_bresp,
fabric$v_to_slaves_0_rresp,
fabric$v_to_slaves_1_arburst,
fabric$v_to_slaves_1_awburst,
fabric$v_to_slaves_1_bresp,
fabric$v_to_slaves_1_rresp,
fabric$v_to_slaves_2_arburst,
fabric$v_to_slaves_2_awburst,
fabric$v_to_slaves_2_bresp,
fabric$v_to_slaves_2_rresp;
wire fabric$EN_reset,
fabric$EN_set_verbosity,
fabric$RDY_reset,
fabric$v_from_masters_0_arlock,
fabric$v_from_masters_0_arready,
fabric$v_from_masters_0_arvalid,
fabric$v_from_masters_0_awlock,
fabric$v_from_masters_0_awready,
fabric$v_from_masters_0_awvalid,
fabric$v_from_masters_0_bready,
fabric$v_from_masters_0_bvalid,
fabric$v_from_masters_0_rlast,
fabric$v_from_masters_0_rready,
fabric$v_from_masters_0_rvalid,
fabric$v_from_masters_0_wlast,
fabric$v_from_masters_0_wready,
fabric$v_from_masters_0_wvalid,
fabric$v_from_masters_1_arlock,
fabric$v_from_masters_1_arready,
fabric$v_from_masters_1_arvalid,
fabric$v_from_masters_1_awlock,
fabric$v_from_masters_1_awready,
fabric$v_from_masters_1_awvalid,
fabric$v_from_masters_1_bready,
fabric$v_from_masters_1_bvalid,
fabric$v_from_masters_1_rlast,
fabric$v_from_masters_1_rready,
fabric$v_from_masters_1_rvalid,
fabric$v_from_masters_1_wlast,
fabric$v_from_masters_1_wready,
fabric$v_from_masters_1_wvalid,
fabric$v_to_slaves_0_arlock,
fabric$v_to_slaves_0_arready,
fabric$v_to_slaves_0_arvalid,
fabric$v_to_slaves_0_awlock,
fabric$v_to_slaves_0_awready,
fabric$v_to_slaves_0_awvalid,
fabric$v_to_slaves_0_bready,
fabric$v_to_slaves_0_bvalid,
fabric$v_to_slaves_0_rlast,
fabric$v_to_slaves_0_rready,
fabric$v_to_slaves_0_rvalid,
fabric$v_to_slaves_0_wlast,
fabric$v_to_slaves_0_wready,
fabric$v_to_slaves_0_wvalid,
fabric$v_to_slaves_1_arlock,
fabric$v_to_slaves_1_arready,
fabric$v_to_slaves_1_arvalid,
fabric$v_to_slaves_1_awlock,
fabric$v_to_slaves_1_awready,
fabric$v_to_slaves_1_awvalid,
fabric$v_to_slaves_1_bready,
fabric$v_to_slaves_1_bvalid,
fabric$v_to_slaves_1_rlast,
fabric$v_to_slaves_1_rready,
fabric$v_to_slaves_1_rvalid,
fabric$v_to_slaves_1_wlast,
fabric$v_to_slaves_1_wready,
fabric$v_to_slaves_1_wvalid,
fabric$v_to_slaves_2_arlock,
fabric$v_to_slaves_2_arready,
fabric$v_to_slaves_2_arvalid,
fabric$v_to_slaves_2_awlock,
fabric$v_to_slaves_2_awready,
fabric$v_to_slaves_2_awvalid,
fabric$v_to_slaves_2_bready,
fabric$v_to_slaves_2_bvalid,
fabric$v_to_slaves_2_rlast,
fabric$v_to_slaves_2_rready,
fabric$v_to_slaves_2_rvalid,
fabric$v_to_slaves_2_wlast,
fabric$v_to_slaves_2_wready,
fabric$v_to_slaves_2_wvalid;
// ports of submodule mem0_controller
wire [352 : 0] mem0_controller$to_raw_mem_request_get;
wire [255 : 0] mem0_controller$to_raw_mem_response_put;
wire [63 : 0] mem0_controller$set_addr_map_addr_base,
mem0_controller$set_addr_map_addr_lim,
mem0_controller$set_watch_tohost_tohost_addr,
mem0_controller$slave_araddr,
mem0_controller$slave_awaddr,
mem0_controller$slave_rdata,
mem0_controller$slave_wdata;
wire [15 : 0] mem0_controller$slave_arid,
mem0_controller$slave_awid,
mem0_controller$slave_bid,
mem0_controller$slave_rid;
wire [7 : 0] mem0_controller$slave_arlen,
mem0_controller$slave_awlen,
mem0_controller$slave_wstrb;
wire [3 : 0] mem0_controller$slave_arcache,
mem0_controller$slave_arqos,
mem0_controller$slave_arregion,
mem0_controller$slave_awcache,
mem0_controller$slave_awqos,
mem0_controller$slave_awregion;
wire [2 : 0] mem0_controller$slave_arprot,
mem0_controller$slave_arsize,
mem0_controller$slave_awprot,
mem0_controller$slave_awsize;
wire [1 : 0] mem0_controller$slave_arburst,
mem0_controller$slave_awburst,
mem0_controller$slave_bresp,
mem0_controller$slave_rresp;
wire mem0_controller$EN_server_reset_request_put,
mem0_controller$EN_server_reset_response_get,
mem0_controller$EN_set_addr_map,
mem0_controller$EN_set_watch_tohost,
mem0_controller$EN_to_raw_mem_request_get,
mem0_controller$EN_to_raw_mem_response_put,
mem0_controller$RDY_server_reset_request_put,
mem0_controller$RDY_server_reset_response_get,
mem0_controller$RDY_set_addr_map,
mem0_controller$RDY_to_raw_mem_request_get,
mem0_controller$RDY_to_raw_mem_response_put,
mem0_controller$set_watch_tohost_watch_tohost,
mem0_controller$slave_arlock,
mem0_controller$slave_arready,
mem0_controller$slave_arvalid,
mem0_controller$slave_awlock,
mem0_controller$slave_awready,
mem0_controller$slave_awvalid,
mem0_controller$slave_bready,
mem0_controller$slave_bvalid,
mem0_controller$slave_rlast,
mem0_controller$slave_rready,
mem0_controller$slave_rvalid,
mem0_controller$slave_wlast,
mem0_controller$slave_wready,
mem0_controller$slave_wvalid;
// ports of submodule mem0_controller_axi4_deburster
wire [63 : 0] mem0_controller_axi4_deburster$from_master_araddr,
mem0_controller_axi4_deburster$from_master_awaddr,
mem0_controller_axi4_deburster$from_master_rdata,
mem0_controller_axi4_deburster$from_master_wdata,
mem0_controller_axi4_deburster$to_slave_araddr,
mem0_controller_axi4_deburster$to_slave_awaddr,
mem0_controller_axi4_deburster$to_slave_rdata,
mem0_controller_axi4_deburster$to_slave_wdata;
wire [15 : 0] mem0_controller_axi4_deburster$from_master_arid,
mem0_controller_axi4_deburster$from_master_awid,
mem0_controller_axi4_deburster$from_master_bid,
mem0_controller_axi4_deburster$from_master_rid,
mem0_controller_axi4_deburster$to_slave_arid,
mem0_controller_axi4_deburster$to_slave_awid,
mem0_controller_axi4_deburster$to_slave_bid,
mem0_controller_axi4_deburster$to_slave_rid;
wire [7 : 0] mem0_controller_axi4_deburster$from_master_arlen,
mem0_controller_axi4_deburster$from_master_awlen,
mem0_controller_axi4_deburster$from_master_wstrb,
mem0_controller_axi4_deburster$to_slave_arlen,
mem0_controller_axi4_deburster$to_slave_awlen,
mem0_controller_axi4_deburster$to_slave_wstrb;
wire [3 : 0] mem0_controller_axi4_deburster$from_master_arcache,
mem0_controller_axi4_deburster$from_master_arqos,
mem0_controller_axi4_deburster$from_master_arregion,
mem0_controller_axi4_deburster$from_master_awcache,
mem0_controller_axi4_deburster$from_master_awqos,
mem0_controller_axi4_deburster$from_master_awregion,
mem0_controller_axi4_deburster$to_slave_arcache,
mem0_controller_axi4_deburster$to_slave_arqos,
mem0_controller_axi4_deburster$to_slave_arregion,
mem0_controller_axi4_deburster$to_slave_awcache,
mem0_controller_axi4_deburster$to_slave_awqos,
mem0_controller_axi4_deburster$to_slave_awregion;
wire [2 : 0] mem0_controller_axi4_deburster$from_master_arprot,
mem0_controller_axi4_deburster$from_master_arsize,
mem0_controller_axi4_deburster$from_master_awprot,
mem0_controller_axi4_deburster$from_master_awsize,
mem0_controller_axi4_deburster$to_slave_arprot,
mem0_controller_axi4_deburster$to_slave_arsize,
mem0_controller_axi4_deburster$to_slave_awprot,
mem0_controller_axi4_deburster$to_slave_awsize;
wire [1 : 0] mem0_controller_axi4_deburster$from_master_arburst,
mem0_controller_axi4_deburster$from_master_awburst,
mem0_controller_axi4_deburster$from_master_bresp,
mem0_controller_axi4_deburster$from_master_rresp,
mem0_controller_axi4_deburster$to_slave_arburst,
mem0_controller_axi4_deburster$to_slave_awburst,
mem0_controller_axi4_deburster$to_slave_bresp,
mem0_controller_axi4_deburster$to_slave_rresp;
wire mem0_controller_axi4_deburster$EN_reset,
mem0_controller_axi4_deburster$from_master_arlock,
mem0_controller_axi4_deburster$from_master_arready,
mem0_controller_axi4_deburster$from_master_arvalid,
mem0_controller_axi4_deburster$from_master_awlock,
mem0_controller_axi4_deburster$from_master_awready,
mem0_controller_axi4_deburster$from_master_awvalid,
mem0_controller_axi4_deburster$from_master_bready,
mem0_controller_axi4_deburster$from_master_bvalid,
mem0_controller_axi4_deburster$from_master_rlast,
mem0_controller_axi4_deburster$from_master_rready,
mem0_controller_axi4_deburster$from_master_rvalid,
mem0_controller_axi4_deburster$from_master_wlast,
mem0_controller_axi4_deburster$from_master_wready,
mem0_controller_axi4_deburster$from_master_wvalid,
mem0_controller_axi4_deburster$to_slave_arlock,
mem0_controller_axi4_deburster$to_slave_arready,
mem0_controller_axi4_deburster$to_slave_arvalid,
mem0_controller_axi4_deburster$to_slave_awlock,
mem0_controller_axi4_deburster$to_slave_awready,
mem0_controller_axi4_deburster$to_slave_awvalid,
mem0_controller_axi4_deburster$to_slave_bready,
mem0_controller_axi4_deburster$to_slave_bvalid,
mem0_controller_axi4_deburster$to_slave_rlast,
mem0_controller_axi4_deburster$to_slave_rready,
mem0_controller_axi4_deburster$to_slave_rvalid,
mem0_controller_axi4_deburster$to_slave_wlast,
mem0_controller_axi4_deburster$to_slave_wready,
mem0_controller_axi4_deburster$to_slave_wvalid;
// ports of submodule uart0
wire [63 : 0] uart0$set_addr_map_addr_base,
uart0$set_addr_map_addr_lim,
uart0$slave_araddr,
uart0$slave_awaddr,
uart0$slave_rdata,
uart0$slave_wdata;
wire [15 : 0] uart0$slave_arid,
uart0$slave_awid,
uart0$slave_bid,
uart0$slave_rid;
wire [7 : 0] uart0$get_to_console_get,
uart0$put_from_console_put,
uart0$slave_arlen,
uart0$slave_awlen,
uart0$slave_wstrb;
wire [3 : 0] uart0$slave_arcache,
uart0$slave_arqos,
uart0$slave_arregion,
uart0$slave_awcache,
uart0$slave_awqos,
uart0$slave_awregion;
wire [2 : 0] uart0$slave_arprot,
uart0$slave_arsize,
uart0$slave_awprot,
uart0$slave_awsize;
wire [1 : 0] uart0$slave_arburst,
uart0$slave_awburst,
uart0$slave_bresp,
uart0$slave_rresp;
wire uart0$EN_get_to_console_get,
uart0$EN_put_from_console_put,
uart0$EN_server_reset_request_put,
uart0$EN_server_reset_response_get,
uart0$EN_set_addr_map,
uart0$RDY_get_to_console_get,
uart0$RDY_put_from_console_put,
uart0$RDY_server_reset_request_put,
uart0$RDY_server_reset_response_get,
uart0$intr,
uart0$slave_arlock,
uart0$slave_arready,
uart0$slave_arvalid,
uart0$slave_awlock,
uart0$slave_awready,
uart0$slave_awvalid,
uart0$slave_bready,
uart0$slave_bvalid,
uart0$slave_rlast,
uart0$slave_rready,
uart0$slave_rvalid,
uart0$slave_wlast,
uart0$slave_wready,
uart0$slave_wvalid;
// rule scheduling signals
wire CAN_FIRE_RL_rl_connect_external_interrupt_requests,
CAN_FIRE_RL_rl_rd_addr_channel,
CAN_FIRE_RL_rl_rd_addr_channel_1,
CAN_FIRE_RL_rl_rd_addr_channel_2,
CAN_FIRE_RL_rl_rd_addr_channel_3,
CAN_FIRE_RL_rl_rd_addr_channel_4,
CAN_FIRE_RL_rl_rd_addr_channel_5,
CAN_FIRE_RL_rl_rd_addr_channel_6,
CAN_FIRE_RL_rl_rd_addr_channel_7,
CAN_FIRE_RL_rl_rd_data_channel,
CAN_FIRE_RL_rl_rd_data_channel_1,
CAN_FIRE_RL_rl_rd_data_channel_2,
CAN_FIRE_RL_rl_rd_data_channel_3,
CAN_FIRE_RL_rl_rd_data_channel_4,
CAN_FIRE_RL_rl_rd_data_channel_5,
CAN_FIRE_RL_rl_rd_data_channel_6,
CAN_FIRE_RL_rl_rd_data_channel_7,
CAN_FIRE_RL_rl_reset_complete_initial,
CAN_FIRE_RL_rl_reset_start_initial,
CAN_FIRE_RL_rl_wr_addr_channel,
CAN_FIRE_RL_rl_wr_addr_channel_1,
CAN_FIRE_RL_rl_wr_addr_channel_2,
CAN_FIRE_RL_rl_wr_addr_channel_3,
CAN_FIRE_RL_rl_wr_addr_channel_4,
CAN_FIRE_RL_rl_wr_addr_channel_5,
CAN_FIRE_RL_rl_wr_addr_channel_6,
CAN_FIRE_RL_rl_wr_addr_channel_7,
CAN_FIRE_RL_rl_wr_data_channel,
CAN_FIRE_RL_rl_wr_data_channel_1,
CAN_FIRE_RL_rl_wr_data_channel_2,
CAN_FIRE_RL_rl_wr_data_channel_3,
CAN_FIRE_RL_rl_wr_data_channel_4,
CAN_FIRE_RL_rl_wr_data_channel_5,
CAN_FIRE_RL_rl_wr_data_channel_6,
CAN_FIRE_RL_rl_wr_data_channel_7,
CAN_FIRE_RL_rl_wr_response_channel,
CAN_FIRE_RL_rl_wr_response_channel_1,
CAN_FIRE_RL_rl_wr_response_channel_2,
CAN_FIRE_RL_rl_wr_response_channel_3,
CAN_FIRE_RL_rl_wr_response_channel_4,
CAN_FIRE_RL_rl_wr_response_channel_5,
CAN_FIRE_RL_rl_wr_response_channel_6,
CAN_FIRE_RL_rl_wr_response_channel_7,
CAN_FIRE_get_to_console_get,
CAN_FIRE_ma_ddr4_ready,
CAN_FIRE_put_from_console_put,
CAN_FIRE_set_verbosity,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_to_raw_mem_request_get,
CAN_FIRE_to_raw_mem_response_put,
WILL_FIRE_RL_rl_connect_external_interrupt_requests,
WILL_FIRE_RL_rl_rd_addr_channel,
WILL_FIRE_RL_rl_rd_addr_channel_1,
WILL_FIRE_RL_rl_rd_addr_channel_2,
WILL_FIRE_RL_rl_rd_addr_channel_3,
WILL_FIRE_RL_rl_rd_addr_channel_4,
WILL_FIRE_RL_rl_rd_addr_channel_5,
WILL_FIRE_RL_rl_rd_addr_channel_6,
WILL_FIRE_RL_rl_rd_addr_channel_7,
WILL_FIRE_RL_rl_rd_data_channel,
WILL_FIRE_RL_rl_rd_data_channel_1,
WILL_FIRE_RL_rl_rd_data_channel_2,
WILL_FIRE_RL_rl_rd_data_channel_3,
WILL_FIRE_RL_rl_rd_data_channel_4,
WILL_FIRE_RL_rl_rd_data_channel_5,
WILL_FIRE_RL_rl_rd_data_channel_6,
WILL_FIRE_RL_rl_rd_data_channel_7,
WILL_FIRE_RL_rl_reset_complete_initial,
WILL_FIRE_RL_rl_reset_start_initial,
WILL_FIRE_RL_rl_wr_addr_channel,
WILL_FIRE_RL_rl_wr_addr_channel_1,
WILL_FIRE_RL_rl_wr_addr_channel_2,
WILL_FIRE_RL_rl_wr_addr_channel_3,
WILL_FIRE_RL_rl_wr_addr_channel_4,
WILL_FIRE_RL_rl_wr_addr_channel_5,
WILL_FIRE_RL_rl_wr_addr_channel_6,
WILL_FIRE_RL_rl_wr_addr_channel_7,
WILL_FIRE_RL_rl_wr_data_channel,
WILL_FIRE_RL_rl_wr_data_channel_1,
WILL_FIRE_RL_rl_wr_data_channel_2,
WILL_FIRE_RL_rl_wr_data_channel_3,
WILL_FIRE_RL_rl_wr_data_channel_4,
WILL_FIRE_RL_rl_wr_data_channel_5,
WILL_FIRE_RL_rl_wr_data_channel_6,
WILL_FIRE_RL_rl_wr_data_channel_7,
WILL_FIRE_RL_rl_wr_response_channel,
WILL_FIRE_RL_rl_wr_response_channel_1,
WILL_FIRE_RL_rl_wr_response_channel_2,
WILL_FIRE_RL_rl_wr_response_channel_3,
WILL_FIRE_RL_rl_wr_response_channel_4,
WILL_FIRE_RL_rl_wr_response_channel_5,
WILL_FIRE_RL_rl_wr_response_channel_6,
WILL_FIRE_RL_rl_wr_response_channel_7,
WILL_FIRE_get_to_console_get,
WILL_FIRE_ma_ddr4_ready,
WILL_FIRE_put_from_console_put,
WILL_FIRE_set_verbosity,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_to_raw_mem_request_get,
WILL_FIRE_to_raw_mem_response_put;
// inputs to muxes for submodule ports
wire MUX_rg_state$write_1__SEL_1, MUX_rg_state$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h11352;
reg [31 : 0] v__h11582;
reg [31 : 0] v__h11346;
reg [31 : 0] v__h11576;
// synopsys translate_on
// actionvalue method to_raw_mem_request_get
assign to_raw_mem_request_get = mem0_controller$to_raw_mem_request_get ;
assign RDY_to_raw_mem_request_get =
mem0_controller$RDY_to_raw_mem_request_get ;
assign CAN_FIRE_to_raw_mem_request_get =
mem0_controller$RDY_to_raw_mem_request_get ;
assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ;
// action method to_raw_mem_response_put
assign RDY_to_raw_mem_response_put =
mem0_controller$RDY_to_raw_mem_response_put ;
assign CAN_FIRE_to_raw_mem_response_put =
mem0_controller$RDY_to_raw_mem_response_put ;
assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ;
// actionvalue method get_to_console_get
assign get_to_console_get = uart0$get_to_console_get ;
assign RDY_get_to_console_get = uart0$RDY_get_to_console_get ;
assign CAN_FIRE_get_to_console_get = uart0$RDY_get_to_console_get ;
assign WILL_FIRE_get_to_console_get = EN_get_to_console_get ;
// action method put_from_console_put
assign RDY_put_from_console_put = uart0$RDY_put_from_console_put ;
assign CAN_FIRE_put_from_console_put = uart0$RDY_put_from_console_put ;
assign WILL_FIRE_put_from_console_put = EN_put_from_console_put ;
// value method status
assign status = 8'd0 ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// value method mv_tohost_value
assign mv_tohost_value = core$mv_tohost_value ;
assign RDY_mv_tohost_value = 1'd1 ;
// action method ma_ddr4_ready
assign RDY_ma_ddr4_ready = 1'd1 ;
assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;
// value method mv_status
assign mv_status = core$mv_status ;
// submodule boot_rom
mkBoot_ROM boot_rom(.CLK(CLK),
.RST_N(RST_N),
.set_addr_map_addr_base(boot_rom$set_addr_map_addr_base),
.set_addr_map_addr_lim(boot_rom$set_addr_map_addr_lim),
.slave_araddr(boot_rom$slave_araddr),
.slave_arburst(boot_rom$slave_arburst),
.slave_arcache(boot_rom$slave_arcache),
.slave_arid(boot_rom$slave_arid),
.slave_arlen(boot_rom$slave_arlen),
.slave_arlock(boot_rom$slave_arlock),
.slave_arprot(boot_rom$slave_arprot),
.slave_arqos(boot_rom$slave_arqos),
.slave_arregion(boot_rom$slave_arregion),
.slave_arsize(boot_rom$slave_arsize),
.slave_arvalid(boot_rom$slave_arvalid),
.slave_awaddr(boot_rom$slave_awaddr),
.slave_awburst(boot_rom$slave_awburst),
.slave_awcache(boot_rom$slave_awcache),
.slave_awid(boot_rom$slave_awid),
.slave_awlen(boot_rom$slave_awlen),
.slave_awlock(boot_rom$slave_awlock),
.slave_awprot(boot_rom$slave_awprot),
.slave_awqos(boot_rom$slave_awqos),
.slave_awregion(boot_rom$slave_awregion),
.slave_awsize(boot_rom$slave_awsize),
.slave_awvalid(boot_rom$slave_awvalid),
.slave_bready(boot_rom$slave_bready),
.slave_rready(boot_rom$slave_rready),
.slave_wdata(boot_rom$slave_wdata),
.slave_wlast(boot_rom$slave_wlast),
.slave_wstrb(boot_rom$slave_wstrb),
.slave_wvalid(boot_rom$slave_wvalid),
.EN_set_addr_map(boot_rom$EN_set_addr_map),
.RDY_set_addr_map(),
.slave_awready(boot_rom$slave_awready),
.slave_wready(boot_rom$slave_wready),
.slave_bvalid(boot_rom$slave_bvalid),
.slave_bid(boot_rom$slave_bid),
.slave_bresp(boot_rom$slave_bresp),
.slave_arready(boot_rom$slave_arready),
.slave_rvalid(boot_rom$slave_rvalid),
.slave_rid(boot_rom$slave_rid),
.slave_rdata(boot_rom$slave_rdata),
.slave_rresp(boot_rom$slave_rresp),
.slave_rlast(boot_rom$slave_rlast));
// submodule boot_rom_axi4_deburster
mkAXI4_Deburster_A boot_rom_axi4_deburster(.CLK(CLK),
.RST_N(RST_N),
.from_master_araddr(boot_rom_axi4_deburster$from_master_araddr),
.from_master_arburst(boot_rom_axi4_deburster$from_master_arburst),
.from_master_arcache(boot_rom_axi4_deburster$from_master_arcache),
.from_master_arid(boot_rom_axi4_deburster$from_master_arid),
.from_master_arlen(boot_rom_axi4_deburster$from_master_arlen),
.from_master_arlock(boot_rom_axi4_deburster$from_master_arlock),
.from_master_arprot(boot_rom_axi4_deburster$from_master_arprot),
.from_master_arqos(boot_rom_axi4_deburster$from_master_arqos),
.from_master_arregion(boot_rom_axi4_deburster$from_master_arregion),
.from_master_arsize(boot_rom_axi4_deburster$from_master_arsize),
.from_master_arvalid(boot_rom_axi4_deburster$from_master_arvalid),
.from_master_awaddr(boot_rom_axi4_deburster$from_master_awaddr),
.from_master_awburst(boot_rom_axi4_deburster$from_master_awburst),
.from_master_awcache(boot_rom_axi4_deburster$from_master_awcache),
.from_master_awid(boot_rom_axi4_deburster$from_master_awid),
.from_master_awlen(boot_rom_axi4_deburster$from_master_awlen),
.from_master_awlock(boot_rom_axi4_deburster$from_master_awlock),
.from_master_awprot(boot_rom_axi4_deburster$from_master_awprot),
.from_master_awqos(boot_rom_axi4_deburster$from_master_awqos),
.from_master_awregion(boot_rom_axi4_deburster$from_master_awregion),
.from_master_awsize(boot_rom_axi4_deburster$from_master_awsize),
.from_master_awvalid(boot_rom_axi4_deburster$from_master_awvalid),
.from_master_bready(boot_rom_axi4_deburster$from_master_bready),
.from_master_rready(boot_rom_axi4_deburster$from_master_rready),
.from_master_wdata(boot_rom_axi4_deburster$from_master_wdata),
.from_master_wlast(boot_rom_axi4_deburster$from_master_wlast),
.from_master_wstrb(boot_rom_axi4_deburster$from_master_wstrb),
.from_master_wvalid(boot_rom_axi4_deburster$from_master_wvalid),
.to_slave_arready(boot_rom_axi4_deburster$to_slave_arready),
.to_slave_awready(boot_rom_axi4_deburster$to_slave_awready),
.to_slave_bid(boot_rom_axi4_deburster$to_slave_bid),
.to_slave_bresp(boot_rom_axi4_deburster$to_slave_bresp),
.to_slave_bvalid(boot_rom_axi4_deburster$to_slave_bvalid),
.to_slave_rdata(boot_rom_axi4_deburster$to_slave_rdata),
.to_slave_rid(boot_rom_axi4_deburster$to_slave_rid),
.to_slave_rlast(boot_rom_axi4_deburster$to_slave_rlast),
.to_slave_rresp(boot_rom_axi4_deburster$to_slave_rresp),
.to_slave_rvalid(boot_rom_axi4_deburster$to_slave_rvalid),
.to_slave_wready(boot_rom_axi4_deburster$to_slave_wready),
.EN_reset(boot_rom_axi4_deburster$EN_reset),
.RDY_reset(),
.from_master_awready(boot_rom_axi4_deburster$from_master_awready),
.from_master_wready(boot_rom_axi4_deburster$from_master_wready),
.from_master_bvalid(boot_rom_axi4_deburster$from_master_bvalid),
.from_master_bid(boot_rom_axi4_deburster$from_master_bid),
.from_master_bresp(boot_rom_axi4_deburster$from_master_bresp),
.from_master_arready(boot_rom_axi4_deburster$from_master_arready),
.from_master_rvalid(boot_rom_axi4_deburster$from_master_rvalid),
.from_master_rid(boot_rom_axi4_deburster$from_master_rid),
.from_master_rdata(boot_rom_axi4_deburster$from_master_rdata),
.from_master_rresp(boot_rom_axi4_deburster$from_master_rresp),
.from_master_rlast(boot_rom_axi4_deburster$from_master_rlast),
.to_slave_awvalid(boot_rom_axi4_deburster$to_slave_awvalid),
.to_slave_awid(boot_rom_axi4_deburster$to_slave_awid),
.to_slave_awaddr(boot_rom_axi4_deburster$to_slave_awaddr),
.to_slave_awlen(boot_rom_axi4_deburster$to_slave_awlen),
.to_slave_awsize(boot_rom_axi4_deburster$to_slave_awsize),
.to_slave_awburst(boot_rom_axi4_deburster$to_slave_awburst),
.to_slave_awlock(boot_rom_axi4_deburster$to_slave_awlock),
.to_slave_awcache(boot_rom_axi4_deburster$to_slave_awcache),
.to_slave_awprot(boot_rom_axi4_deburster$to_slave_awprot),
.to_slave_awqos(boot_rom_axi4_deburster$to_slave_awqos),
.to_slave_awregion(boot_rom_axi4_deburster$to_slave_awregion),
.to_slave_wvalid(boot_rom_axi4_deburster$to_slave_wvalid),
.to_slave_wdata(boot_rom_axi4_deburster$to_slave_wdata),
.to_slave_wstrb(boot_rom_axi4_deburster$to_slave_wstrb),
.to_slave_wlast(boot_rom_axi4_deburster$to_slave_wlast),
.to_slave_bready(boot_rom_axi4_deburster$to_slave_bready),
.to_slave_arvalid(boot_rom_axi4_deburster$to_slave_arvalid),
.to_slave_arid(boot_rom_axi4_deburster$to_slave_arid),
.to_slave_araddr(boot_rom_axi4_deburster$to_slave_araddr),
.to_slave_arlen(boot_rom_axi4_deburster$to_slave_arlen),
.to_slave_arsize(boot_rom_axi4_deburster$to_slave_arsize),
.to_slave_arburst(boot_rom_axi4_deburster$to_slave_arburst),
.to_slave_arlock(boot_rom_axi4_deburster$to_slave_arlock),
.to_slave_arcache(boot_rom_axi4_deburster$to_slave_arcache),
.to_slave_arprot(boot_rom_axi4_deburster$to_slave_arprot),
.to_slave_arqos(boot_rom_axi4_deburster$to_slave_arqos),
.to_slave_arregion(boot_rom_axi4_deburster$to_slave_arregion),
.to_slave_rready(boot_rom_axi4_deburster$to_slave_rready));
// submodule core
mkCore core(.RST_N_dm_power_on_reset(RST_N),
.CLK(CLK),
.RST_N(RST_N),
.core_external_interrupt_sources_0_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_10_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_11_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_12_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_13_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_14_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_15_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_1_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_2_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_3_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_4_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_5_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_6_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_7_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_8_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear),
.core_external_interrupt_sources_9_m_interrupt_req_set_not_clear(core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear),
.core_mem_master_arready(core$core_mem_master_arready),
.core_mem_master_awready(core$core_mem_master_awready),
.core_mem_master_bid(core$core_mem_master_bid),
.core_mem_master_bresp(core$core_mem_master_bresp),
.core_mem_master_bvalid(core$core_mem_master_bvalid),
.core_mem_master_rdata(core$core_mem_master_rdata),
.core_mem_master_rid(core$core_mem_master_rid),
.core_mem_master_rlast(core$core_mem_master_rlast),
.core_mem_master_rresp(core$core_mem_master_rresp),
.core_mem_master_rvalid(core$core_mem_master_rvalid),
.core_mem_master_wready(core$core_mem_master_wready),
.cpu_imem_master_arready(core$cpu_imem_master_arready),
.cpu_imem_master_awready(core$cpu_imem_master_awready),
.cpu_imem_master_bid(core$cpu_imem_master_bid),
.cpu_imem_master_bresp(core$cpu_imem_master_bresp),
.cpu_imem_master_bvalid(core$cpu_imem_master_bvalid),
.cpu_imem_master_rdata(core$cpu_imem_master_rdata),
.cpu_imem_master_rid(core$cpu_imem_master_rid),
.cpu_imem_master_rlast(core$cpu_imem_master_rlast),
.cpu_imem_master_rresp(core$cpu_imem_master_rresp),
.cpu_imem_master_rvalid(core$cpu_imem_master_rvalid),
.cpu_imem_master_wready(core$cpu_imem_master_wready),
.cpu_reset_server_request_put(core$cpu_reset_server_request_put),
.dma_server_araddr(core$dma_server_araddr),
.dma_server_arburst(core$dma_server_arburst),
.dma_server_arcache(core$dma_server_arcache),
.dma_server_arid(core$dma_server_arid),
.dma_server_arlen(core$dma_server_arlen),
.dma_server_arlock(core$dma_server_arlock),
.dma_server_arprot(core$dma_server_arprot),
.dma_server_arqos(core$dma_server_arqos),
.dma_server_arregion(core$dma_server_arregion),
.dma_server_arsize(core$dma_server_arsize),
.dma_server_arvalid(core$dma_server_arvalid),
.dma_server_awaddr(core$dma_server_awaddr),
.dma_server_awburst(core$dma_server_awburst),
.dma_server_awcache(core$dma_server_awcache),
.dma_server_awid(core$dma_server_awid),
.dma_server_awlen(core$dma_server_awlen),
.dma_server_awlock(core$dma_server_awlock),
.dma_server_awprot(core$dma_server_awprot),
.dma_server_awqos(core$dma_server_awqos),
.dma_server_awregion(core$dma_server_awregion),
.dma_server_awsize(core$dma_server_awsize),
.dma_server_awvalid(core$dma_server_awvalid),
.dma_server_bready(core$dma_server_bready),
.dma_server_rready(core$dma_server_rready),
.dma_server_wdata(core$dma_server_wdata),
.dma_server_wlast(core$dma_server_wlast),
.dma_server_wstrb(core$dma_server_wstrb),
.dma_server_wvalid(core$dma_server_wvalid),
.nmi_req_set_not_clear(core$nmi_req_set_not_clear),
.set_verbosity_logdelay(core$set_verbosity_logdelay),
.set_verbosity_verbosity(core$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(core$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(core$set_watch_tohost_watch_tohost),
.EN_cpu_reset_server_request_put(core$EN_cpu_reset_server_request_put),
.EN_cpu_reset_server_response_get(core$EN_cpu_reset_server_response_get),
.EN_set_verbosity(core$EN_set_verbosity),
.EN_set_watch_tohost(core$EN_set_watch_tohost),
.EN_ma_ddr4_ready(core$EN_ma_ddr4_ready),
.RDY_cpu_reset_server_request_put(core$RDY_cpu_reset_server_request_put),
.cpu_reset_server_response_get(),
.RDY_cpu_reset_server_response_get(core$RDY_cpu_reset_server_response_get),
.cpu_imem_master_awvalid(core$cpu_imem_master_awvalid),
.cpu_imem_master_awid(core$cpu_imem_master_awid),
.cpu_imem_master_awaddr(core$cpu_imem_master_awaddr),
.cpu_imem_master_awlen(core$cpu_imem_master_awlen),
.cpu_imem_master_awsize(core$cpu_imem_master_awsize),
.cpu_imem_master_awburst(core$cpu_imem_master_awburst),
.cpu_imem_master_awlock(core$cpu_imem_master_awlock),
.cpu_imem_master_awcache(core$cpu_imem_master_awcache),
.cpu_imem_master_awprot(core$cpu_imem_master_awprot),
.cpu_imem_master_awqos(core$cpu_imem_master_awqos),
.cpu_imem_master_awregion(core$cpu_imem_master_awregion),
.cpu_imem_master_wvalid(core$cpu_imem_master_wvalid),
.cpu_imem_master_wdata(core$cpu_imem_master_wdata),
.cpu_imem_master_wstrb(core$cpu_imem_master_wstrb),
.cpu_imem_master_wlast(core$cpu_imem_master_wlast),
.cpu_imem_master_bready(core$cpu_imem_master_bready),
.cpu_imem_master_arvalid(core$cpu_imem_master_arvalid),
.cpu_imem_master_arid(core$cpu_imem_master_arid),
.cpu_imem_master_araddr(core$cpu_imem_master_araddr),
.cpu_imem_master_arlen(core$cpu_imem_master_arlen),
.cpu_imem_master_arsize(core$cpu_imem_master_arsize),
.cpu_imem_master_arburst(core$cpu_imem_master_arburst),
.cpu_imem_master_arlock(core$cpu_imem_master_arlock),
.cpu_imem_master_arcache(core$cpu_imem_master_arcache),
.cpu_imem_master_arprot(core$cpu_imem_master_arprot),
.cpu_imem_master_arqos(core$cpu_imem_master_arqos),
.cpu_imem_master_arregion(core$cpu_imem_master_arregion),
.cpu_imem_master_rready(core$cpu_imem_master_rready),
.core_mem_master_awvalid(core$core_mem_master_awvalid),
.core_mem_master_awid(core$core_mem_master_awid),
.core_mem_master_awaddr(core$core_mem_master_awaddr),
.core_mem_master_awlen(core$core_mem_master_awlen),
.core_mem_master_awsize(core$core_mem_master_awsize),
.core_mem_master_awburst(core$core_mem_master_awburst),
.core_mem_master_awlock(core$core_mem_master_awlock),
.core_mem_master_awcache(core$core_mem_master_awcache),
.core_mem_master_awprot(core$core_mem_master_awprot),
.core_mem_master_awqos(core$core_mem_master_awqos),
.core_mem_master_awregion(core$core_mem_master_awregion),
.core_mem_master_wvalid(core$core_mem_master_wvalid),
.core_mem_master_wdata(core$core_mem_master_wdata),
.core_mem_master_wstrb(core$core_mem_master_wstrb),
.core_mem_master_wlast(core$core_mem_master_wlast),
.core_mem_master_bready(core$core_mem_master_bready),
.core_mem_master_arvalid(core$core_mem_master_arvalid),
.core_mem_master_arid(core$core_mem_master_arid),
.core_mem_master_araddr(core$core_mem_master_araddr),
.core_mem_master_arlen(core$core_mem_master_arlen),
.core_mem_master_arsize(core$core_mem_master_arsize),
.core_mem_master_arburst(core$core_mem_master_arburst),
.core_mem_master_arlock(core$core_mem_master_arlock),
.core_mem_master_arcache(core$core_mem_master_arcache),
.core_mem_master_arprot(core$core_mem_master_arprot),
.core_mem_master_arqos(core$core_mem_master_arqos),
.core_mem_master_arregion(core$core_mem_master_arregion),
.core_mem_master_rready(core$core_mem_master_rready),
.dma_server_awready(),
.dma_server_wready(),
.dma_server_bvalid(),
.dma_server_bid(),
.dma_server_bresp(),
.dma_server_arready(),
.dma_server_rvalid(),
.dma_server_rid(),
.dma_server_rdata(),
.dma_server_rresp(),
.dma_server_rlast(),
.RDY_set_verbosity(),
.RDY_set_watch_tohost(),
.mv_tohost_value(core$mv_tohost_value),
.RDY_mv_tohost_value(),
.RDY_ma_ddr4_ready(),
.mv_status(core$mv_status));
// submodule fabric
mkFabric_AXI4 fabric(.CLK(CLK),
.RST_N(RST_N),
.set_verbosity_verbosity(fabric$set_verbosity_verbosity),
.v_from_masters_0_araddr(fabric$v_from_masters_0_araddr),
.v_from_masters_0_arburst(fabric$v_from_masters_0_arburst),
.v_from_masters_0_arcache(fabric$v_from_masters_0_arcache),
.v_from_masters_0_arid(fabric$v_from_masters_0_arid),
.v_from_masters_0_arlen(fabric$v_from_masters_0_arlen),
.v_from_masters_0_arlock(fabric$v_from_masters_0_arlock),
.v_from_masters_0_arprot(fabric$v_from_masters_0_arprot),
.v_from_masters_0_arqos(fabric$v_from_masters_0_arqos),
.v_from_masters_0_arregion(fabric$v_from_masters_0_arregion),
.v_from_masters_0_arsize(fabric$v_from_masters_0_arsize),
.v_from_masters_0_arvalid(fabric$v_from_masters_0_arvalid),
.v_from_masters_0_awaddr(fabric$v_from_masters_0_awaddr),
.v_from_masters_0_awburst(fabric$v_from_masters_0_awburst),
.v_from_masters_0_awcache(fabric$v_from_masters_0_awcache),
.v_from_masters_0_awid(fabric$v_from_masters_0_awid),
.v_from_masters_0_awlen(fabric$v_from_masters_0_awlen),
.v_from_masters_0_awlock(fabric$v_from_masters_0_awlock),
.v_from_masters_0_awprot(fabric$v_from_masters_0_awprot),
.v_from_masters_0_awqos(fabric$v_from_masters_0_awqos),
.v_from_masters_0_awregion(fabric$v_from_masters_0_awregion),
.v_from_masters_0_awsize(fabric$v_from_masters_0_awsize),
.v_from_masters_0_awvalid(fabric$v_from_masters_0_awvalid),
.v_from_masters_0_bready(fabric$v_from_masters_0_bready),
.v_from_masters_0_rready(fabric$v_from_masters_0_rready),
.v_from_masters_0_wdata(fabric$v_from_masters_0_wdata),
.v_from_masters_0_wlast(fabric$v_from_masters_0_wlast),
.v_from_masters_0_wstrb(fabric$v_from_masters_0_wstrb),
.v_from_masters_0_wvalid(fabric$v_from_masters_0_wvalid),
.v_from_masters_1_araddr(fabric$v_from_masters_1_araddr),
.v_from_masters_1_arburst(fabric$v_from_masters_1_arburst),
.v_from_masters_1_arcache(fabric$v_from_masters_1_arcache),
.v_from_masters_1_arid(fabric$v_from_masters_1_arid),
.v_from_masters_1_arlen(fabric$v_from_masters_1_arlen),
.v_from_masters_1_arlock(fabric$v_from_masters_1_arlock),
.v_from_masters_1_arprot(fabric$v_from_masters_1_arprot),
.v_from_masters_1_arqos(fabric$v_from_masters_1_arqos),
.v_from_masters_1_arregion(fabric$v_from_masters_1_arregion),
.v_from_masters_1_arsize(fabric$v_from_masters_1_arsize),
.v_from_masters_1_arvalid(fabric$v_from_masters_1_arvalid),
.v_from_masters_1_awaddr(fabric$v_from_masters_1_awaddr),
.v_from_masters_1_awburst(fabric$v_from_masters_1_awburst),
.v_from_masters_1_awcache(fabric$v_from_masters_1_awcache),
.v_from_masters_1_awid(fabric$v_from_masters_1_awid),
.v_from_masters_1_awlen(fabric$v_from_masters_1_awlen),
.v_from_masters_1_awlock(fabric$v_from_masters_1_awlock),
.v_from_masters_1_awprot(fabric$v_from_masters_1_awprot),
.v_from_masters_1_awqos(fabric$v_from_masters_1_awqos),
.v_from_masters_1_awregion(fabric$v_from_masters_1_awregion),
.v_from_masters_1_awsize(fabric$v_from_masters_1_awsize),
.v_from_masters_1_awvalid(fabric$v_from_masters_1_awvalid),
.v_from_masters_1_bready(fabric$v_from_masters_1_bready),
.v_from_masters_1_rready(fabric$v_from_masters_1_rready),
.v_from_masters_1_wdata(fabric$v_from_masters_1_wdata),
.v_from_masters_1_wlast(fabric$v_from_masters_1_wlast),
.v_from_masters_1_wstrb(fabric$v_from_masters_1_wstrb),
.v_from_masters_1_wvalid(fabric$v_from_masters_1_wvalid),
.v_to_slaves_0_arready(fabric$v_to_slaves_0_arready),
.v_to_slaves_0_awready(fabric$v_to_slaves_0_awready),
.v_to_slaves_0_bid(fabric$v_to_slaves_0_bid),
.v_to_slaves_0_bresp(fabric$v_to_slaves_0_bresp),
.v_to_slaves_0_bvalid(fabric$v_to_slaves_0_bvalid),
.v_to_slaves_0_rdata(fabric$v_to_slaves_0_rdata),
.v_to_slaves_0_rid(fabric$v_to_slaves_0_rid),
.v_to_slaves_0_rlast(fabric$v_to_slaves_0_rlast),
.v_to_slaves_0_rresp(fabric$v_to_slaves_0_rresp),
.v_to_slaves_0_rvalid(fabric$v_to_slaves_0_rvalid),
.v_to_slaves_0_wready(fabric$v_to_slaves_0_wready),
.v_to_slaves_1_arready(fabric$v_to_slaves_1_arready),
.v_to_slaves_1_awready(fabric$v_to_slaves_1_awready),
.v_to_slaves_1_bid(fabric$v_to_slaves_1_bid),
.v_to_slaves_1_bresp(fabric$v_to_slaves_1_bresp),
.v_to_slaves_1_bvalid(fabric$v_to_slaves_1_bvalid),
.v_to_slaves_1_rdata(fabric$v_to_slaves_1_rdata),
.v_to_slaves_1_rid(fabric$v_to_slaves_1_rid),
.v_to_slaves_1_rlast(fabric$v_to_slaves_1_rlast),
.v_to_slaves_1_rresp(fabric$v_to_slaves_1_rresp),
.v_to_slaves_1_rvalid(fabric$v_to_slaves_1_rvalid),
.v_to_slaves_1_wready(fabric$v_to_slaves_1_wready),
.v_to_slaves_2_arready(fabric$v_to_slaves_2_arready),
.v_to_slaves_2_awready(fabric$v_to_slaves_2_awready),
.v_to_slaves_2_bid(fabric$v_to_slaves_2_bid),
.v_to_slaves_2_bresp(fabric$v_to_slaves_2_bresp),
.v_to_slaves_2_bvalid(fabric$v_to_slaves_2_bvalid),
.v_to_slaves_2_rdata(fabric$v_to_slaves_2_rdata),
.v_to_slaves_2_rid(fabric$v_to_slaves_2_rid),
.v_to_slaves_2_rlast(fabric$v_to_slaves_2_rlast),
.v_to_slaves_2_rresp(fabric$v_to_slaves_2_rresp),
.v_to_slaves_2_rvalid(fabric$v_to_slaves_2_rvalid),
.v_to_slaves_2_wready(fabric$v_to_slaves_2_wready),
.EN_reset(fabric$EN_reset),
.EN_set_verbosity(fabric$EN_set_verbosity),
.RDY_reset(fabric$RDY_reset),
.RDY_set_verbosity(),
.v_from_masters_0_awready(fabric$v_from_masters_0_awready),
.v_from_masters_0_wready(fabric$v_from_masters_0_wready),
.v_from_masters_0_bvalid(fabric$v_from_masters_0_bvalid),
.v_from_masters_0_bid(fabric$v_from_masters_0_bid),
.v_from_masters_0_bresp(fabric$v_from_masters_0_bresp),
.v_from_masters_0_arready(fabric$v_from_masters_0_arready),
.v_from_masters_0_rvalid(fabric$v_from_masters_0_rvalid),
.v_from_masters_0_rid(fabric$v_from_masters_0_rid),
.v_from_masters_0_rdata(fabric$v_from_masters_0_rdata),
.v_from_masters_0_rresp(fabric$v_from_masters_0_rresp),
.v_from_masters_0_rlast(fabric$v_from_masters_0_rlast),
.v_from_masters_1_awready(fabric$v_from_masters_1_awready),
.v_from_masters_1_wready(fabric$v_from_masters_1_wready),
.v_from_masters_1_bvalid(fabric$v_from_masters_1_bvalid),
.v_from_masters_1_bid(fabric$v_from_masters_1_bid),
.v_from_masters_1_bresp(fabric$v_from_masters_1_bresp),
.v_from_masters_1_arready(fabric$v_from_masters_1_arready),
.v_from_masters_1_rvalid(fabric$v_from_masters_1_rvalid),
.v_from_masters_1_rid(fabric$v_from_masters_1_rid),
.v_from_masters_1_rdata(fabric$v_from_masters_1_rdata),
.v_from_masters_1_rresp(fabric$v_from_masters_1_rresp),
.v_from_masters_1_rlast(fabric$v_from_masters_1_rlast),
.v_to_slaves_0_awvalid(fabric$v_to_slaves_0_awvalid),
.v_to_slaves_0_awid(fabric$v_to_slaves_0_awid),
.v_to_slaves_0_awaddr(fabric$v_to_slaves_0_awaddr),
.v_to_slaves_0_awlen(fabric$v_to_slaves_0_awlen),
.v_to_slaves_0_awsize(fabric$v_to_slaves_0_awsize),
.v_to_slaves_0_awburst(fabric$v_to_slaves_0_awburst),
.v_to_slaves_0_awlock(fabric$v_to_slaves_0_awlock),
.v_to_slaves_0_awcache(fabric$v_to_slaves_0_awcache),
.v_to_slaves_0_awprot(fabric$v_to_slaves_0_awprot),
.v_to_slaves_0_awqos(fabric$v_to_slaves_0_awqos),
.v_to_slaves_0_awregion(fabric$v_to_slaves_0_awregion),
.v_to_slaves_0_wvalid(fabric$v_to_slaves_0_wvalid),
.v_to_slaves_0_wdata(fabric$v_to_slaves_0_wdata),
.v_to_slaves_0_wstrb(fabric$v_to_slaves_0_wstrb),
.v_to_slaves_0_wlast(fabric$v_to_slaves_0_wlast),
.v_to_slaves_0_bready(fabric$v_to_slaves_0_bready),
.v_to_slaves_0_arvalid(fabric$v_to_slaves_0_arvalid),
.v_to_slaves_0_arid(fabric$v_to_slaves_0_arid),
.v_to_slaves_0_araddr(fabric$v_to_slaves_0_araddr),
.v_to_slaves_0_arlen(fabric$v_to_slaves_0_arlen),
.v_to_slaves_0_arsize(fabric$v_to_slaves_0_arsize),
.v_to_slaves_0_arburst(fabric$v_to_slaves_0_arburst),
.v_to_slaves_0_arlock(fabric$v_to_slaves_0_arlock),
.v_to_slaves_0_arcache(fabric$v_to_slaves_0_arcache),
.v_to_slaves_0_arprot(fabric$v_to_slaves_0_arprot),
.v_to_slaves_0_arqos(fabric$v_to_slaves_0_arqos),
.v_to_slaves_0_arregion(fabric$v_to_slaves_0_arregion),
.v_to_slaves_0_rready(fabric$v_to_slaves_0_rready),
.v_to_slaves_1_awvalid(fabric$v_to_slaves_1_awvalid),
.v_to_slaves_1_awid(fabric$v_to_slaves_1_awid),
.v_to_slaves_1_awaddr(fabric$v_to_slaves_1_awaddr),
.v_to_slaves_1_awlen(fabric$v_to_slaves_1_awlen),
.v_to_slaves_1_awsize(fabric$v_to_slaves_1_awsize),
.v_to_slaves_1_awburst(fabric$v_to_slaves_1_awburst),
.v_to_slaves_1_awlock(fabric$v_to_slaves_1_awlock),
.v_to_slaves_1_awcache(fabric$v_to_slaves_1_awcache),
.v_to_slaves_1_awprot(fabric$v_to_slaves_1_awprot),
.v_to_slaves_1_awqos(fabric$v_to_slaves_1_awqos),
.v_to_slaves_1_awregion(fabric$v_to_slaves_1_awregion),
.v_to_slaves_1_wvalid(fabric$v_to_slaves_1_wvalid),
.v_to_slaves_1_wdata(fabric$v_to_slaves_1_wdata),
.v_to_slaves_1_wstrb(fabric$v_to_slaves_1_wstrb),
.v_to_slaves_1_wlast(fabric$v_to_slaves_1_wlast),
.v_to_slaves_1_bready(fabric$v_to_slaves_1_bready),
.v_to_slaves_1_arvalid(fabric$v_to_slaves_1_arvalid),
.v_to_slaves_1_arid(fabric$v_to_slaves_1_arid),
.v_to_slaves_1_araddr(fabric$v_to_slaves_1_araddr),
.v_to_slaves_1_arlen(fabric$v_to_slaves_1_arlen),
.v_to_slaves_1_arsize(fabric$v_to_slaves_1_arsize),
.v_to_slaves_1_arburst(fabric$v_to_slaves_1_arburst),
.v_to_slaves_1_arlock(fabric$v_to_slaves_1_arlock),
.v_to_slaves_1_arcache(fabric$v_to_slaves_1_arcache),
.v_to_slaves_1_arprot(fabric$v_to_slaves_1_arprot),
.v_to_slaves_1_arqos(fabric$v_to_slaves_1_arqos),
.v_to_slaves_1_arregion(fabric$v_to_slaves_1_arregion),
.v_to_slaves_1_rready(fabric$v_to_slaves_1_rready),
.v_to_slaves_2_awvalid(fabric$v_to_slaves_2_awvalid),
.v_to_slaves_2_awid(fabric$v_to_slaves_2_awid),
.v_to_slaves_2_awaddr(fabric$v_to_slaves_2_awaddr),
.v_to_slaves_2_awlen(fabric$v_to_slaves_2_awlen),
.v_to_slaves_2_awsize(fabric$v_to_slaves_2_awsize),
.v_to_slaves_2_awburst(fabric$v_to_slaves_2_awburst),
.v_to_slaves_2_awlock(fabric$v_to_slaves_2_awlock),
.v_to_slaves_2_awcache(fabric$v_to_slaves_2_awcache),
.v_to_slaves_2_awprot(fabric$v_to_slaves_2_awprot),
.v_to_slaves_2_awqos(fabric$v_to_slaves_2_awqos),
.v_to_slaves_2_awregion(fabric$v_to_slaves_2_awregion),
.v_to_slaves_2_wvalid(fabric$v_to_slaves_2_wvalid),
.v_to_slaves_2_wdata(fabric$v_to_slaves_2_wdata),
.v_to_slaves_2_wstrb(fabric$v_to_slaves_2_wstrb),
.v_to_slaves_2_wlast(fabric$v_to_slaves_2_wlast),
.v_to_slaves_2_bready(fabric$v_to_slaves_2_bready),
.v_to_slaves_2_arvalid(fabric$v_to_slaves_2_arvalid),
.v_to_slaves_2_arid(fabric$v_to_slaves_2_arid),
.v_to_slaves_2_araddr(fabric$v_to_slaves_2_araddr),
.v_to_slaves_2_arlen(fabric$v_to_slaves_2_arlen),
.v_to_slaves_2_arsize(fabric$v_to_slaves_2_arsize),
.v_to_slaves_2_arburst(fabric$v_to_slaves_2_arburst),
.v_to_slaves_2_arlock(fabric$v_to_slaves_2_arlock),
.v_to_slaves_2_arcache(fabric$v_to_slaves_2_arcache),
.v_to_slaves_2_arprot(fabric$v_to_slaves_2_arprot),
.v_to_slaves_2_arqos(fabric$v_to_slaves_2_arqos),
.v_to_slaves_2_arregion(fabric$v_to_slaves_2_arregion),
.v_to_slaves_2_rready(fabric$v_to_slaves_2_rready));
// submodule mem0_controller
mkMem_Controller mem0_controller(.CLK(CLK),
.RST_N(RST_N),
.set_addr_map_addr_base(mem0_controller$set_addr_map_addr_base),
.set_addr_map_addr_lim(mem0_controller$set_addr_map_addr_lim),
.set_watch_tohost_tohost_addr(mem0_controller$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(mem0_controller$set_watch_tohost_watch_tohost),
.slave_araddr(mem0_controller$slave_araddr),
.slave_arburst(mem0_controller$slave_arburst),
.slave_arcache(mem0_controller$slave_arcache),
.slave_arid(mem0_controller$slave_arid),
.slave_arlen(mem0_controller$slave_arlen),
.slave_arlock(mem0_controller$slave_arlock),
.slave_arprot(mem0_controller$slave_arprot),
.slave_arqos(mem0_controller$slave_arqos),
.slave_arregion(mem0_controller$slave_arregion),
.slave_arsize(mem0_controller$slave_arsize),
.slave_arvalid(mem0_controller$slave_arvalid),
.slave_awaddr(mem0_controller$slave_awaddr),
.slave_awburst(mem0_controller$slave_awburst),
.slave_awcache(mem0_controller$slave_awcache),
.slave_awid(mem0_controller$slave_awid),
.slave_awlen(mem0_controller$slave_awlen),
.slave_awlock(mem0_controller$slave_awlock),
.slave_awprot(mem0_controller$slave_awprot),
.slave_awqos(mem0_controller$slave_awqos),
.slave_awregion(mem0_controller$slave_awregion),
.slave_awsize(mem0_controller$slave_awsize),
.slave_awvalid(mem0_controller$slave_awvalid),
.slave_bready(mem0_controller$slave_bready),
.slave_rready(mem0_controller$slave_rready),
.slave_wdata(mem0_controller$slave_wdata),
.slave_wlast(mem0_controller$slave_wlast),
.slave_wstrb(mem0_controller$slave_wstrb),
.slave_wvalid(mem0_controller$slave_wvalid),
.to_raw_mem_response_put(mem0_controller$to_raw_mem_response_put),
.EN_server_reset_request_put(mem0_controller$EN_server_reset_request_put),
.EN_server_reset_response_get(mem0_controller$EN_server_reset_response_get),
.EN_set_addr_map(mem0_controller$EN_set_addr_map),
.EN_to_raw_mem_request_get(mem0_controller$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(mem0_controller$EN_to_raw_mem_response_put),
.EN_set_watch_tohost(mem0_controller$EN_set_watch_tohost),
.RDY_server_reset_request_put(mem0_controller$RDY_server_reset_request_put),
.RDY_server_reset_response_get(mem0_controller$RDY_server_reset_response_get),
.RDY_set_addr_map(mem0_controller$RDY_set_addr_map),
.slave_awready(mem0_controller$slave_awready),
.slave_wready(mem0_controller$slave_wready),
.slave_bvalid(mem0_controller$slave_bvalid),
.slave_bid(mem0_controller$slave_bid),
.slave_bresp(mem0_controller$slave_bresp),
.slave_arready(mem0_controller$slave_arready),
.slave_rvalid(mem0_controller$slave_rvalid),
.slave_rid(mem0_controller$slave_rid),
.slave_rdata(mem0_controller$slave_rdata),
.slave_rresp(mem0_controller$slave_rresp),
.slave_rlast(mem0_controller$slave_rlast),
.to_raw_mem_request_get(mem0_controller$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(mem0_controller$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(mem0_controller$RDY_to_raw_mem_response_put),
.status(),
.RDY_set_watch_tohost());
// submodule mem0_controller_axi4_deburster
mkAXI4_Deburster_A mem0_controller_axi4_deburster(.CLK(CLK),
.RST_N(RST_N),
.from_master_araddr(mem0_controller_axi4_deburster$from_master_araddr),
.from_master_arburst(mem0_controller_axi4_deburster$from_master_arburst),
.from_master_arcache(mem0_controller_axi4_deburster$from_master_arcache),
.from_master_arid(mem0_controller_axi4_deburster$from_master_arid),
.from_master_arlen(mem0_controller_axi4_deburster$from_master_arlen),
.from_master_arlock(mem0_controller_axi4_deburster$from_master_arlock),
.from_master_arprot(mem0_controller_axi4_deburster$from_master_arprot),
.from_master_arqos(mem0_controller_axi4_deburster$from_master_arqos),
.from_master_arregion(mem0_controller_axi4_deburster$from_master_arregion),
.from_master_arsize(mem0_controller_axi4_deburster$from_master_arsize),
.from_master_arvalid(mem0_controller_axi4_deburster$from_master_arvalid),
.from_master_awaddr(mem0_controller_axi4_deburster$from_master_awaddr),
.from_master_awburst(mem0_controller_axi4_deburster$from_master_awburst),
.from_master_awcache(mem0_controller_axi4_deburster$from_master_awcache),
.from_master_awid(mem0_controller_axi4_deburster$from_master_awid),
.from_master_awlen(mem0_controller_axi4_deburster$from_master_awlen),
.from_master_awlock(mem0_controller_axi4_deburster$from_master_awlock),
.from_master_awprot(mem0_controller_axi4_deburster$from_master_awprot),
.from_master_awqos(mem0_controller_axi4_deburster$from_master_awqos),
.from_master_awregion(mem0_controller_axi4_deburster$from_master_awregion),
.from_master_awsize(mem0_controller_axi4_deburster$from_master_awsize),
.from_master_awvalid(mem0_controller_axi4_deburster$from_master_awvalid),
.from_master_bready(mem0_controller_axi4_deburster$from_master_bready),
.from_master_rready(mem0_controller_axi4_deburster$from_master_rready),
.from_master_wdata(mem0_controller_axi4_deburster$from_master_wdata),
.from_master_wlast(mem0_controller_axi4_deburster$from_master_wlast),
.from_master_wstrb(mem0_controller_axi4_deburster$from_master_wstrb),
.from_master_wvalid(mem0_controller_axi4_deburster$from_master_wvalid),
.to_slave_arready(mem0_controller_axi4_deburster$to_slave_arready),
.to_slave_awready(mem0_controller_axi4_deburster$to_slave_awready),
.to_slave_bid(mem0_controller_axi4_deburster$to_slave_bid),
.to_slave_bresp(mem0_controller_axi4_deburster$to_slave_bresp),
.to_slave_bvalid(mem0_controller_axi4_deburster$to_slave_bvalid),
.to_slave_rdata(mem0_controller_axi4_deburster$to_slave_rdata),
.to_slave_rid(mem0_controller_axi4_deburster$to_slave_rid),
.to_slave_rlast(mem0_controller_axi4_deburster$to_slave_rlast),
.to_slave_rresp(mem0_controller_axi4_deburster$to_slave_rresp),
.to_slave_rvalid(mem0_controller_axi4_deburster$to_slave_rvalid),
.to_slave_wready(mem0_controller_axi4_deburster$to_slave_wready),
.EN_reset(mem0_controller_axi4_deburster$EN_reset),
.RDY_reset(),
.from_master_awready(mem0_controller_axi4_deburster$from_master_awready),
.from_master_wready(mem0_controller_axi4_deburster$from_master_wready),
.from_master_bvalid(mem0_controller_axi4_deburster$from_master_bvalid),
.from_master_bid(mem0_controller_axi4_deburster$from_master_bid),
.from_master_bresp(mem0_controller_axi4_deburster$from_master_bresp),
.from_master_arready(mem0_controller_axi4_deburster$from_master_arready),
.from_master_rvalid(mem0_controller_axi4_deburster$from_master_rvalid),
.from_master_rid(mem0_controller_axi4_deburster$from_master_rid),
.from_master_rdata(mem0_controller_axi4_deburster$from_master_rdata),
.from_master_rresp(mem0_controller_axi4_deburster$from_master_rresp),
.from_master_rlast(mem0_controller_axi4_deburster$from_master_rlast),
.to_slave_awvalid(mem0_controller_axi4_deburster$to_slave_awvalid),
.to_slave_awid(mem0_controller_axi4_deburster$to_slave_awid),
.to_slave_awaddr(mem0_controller_axi4_deburster$to_slave_awaddr),
.to_slave_awlen(mem0_controller_axi4_deburster$to_slave_awlen),
.to_slave_awsize(mem0_controller_axi4_deburster$to_slave_awsize),
.to_slave_awburst(mem0_controller_axi4_deburster$to_slave_awburst),
.to_slave_awlock(mem0_controller_axi4_deburster$to_slave_awlock),
.to_slave_awcache(mem0_controller_axi4_deburster$to_slave_awcache),
.to_slave_awprot(mem0_controller_axi4_deburster$to_slave_awprot),
.to_slave_awqos(mem0_controller_axi4_deburster$to_slave_awqos),
.to_slave_awregion(mem0_controller_axi4_deburster$to_slave_awregion),
.to_slave_wvalid(mem0_controller_axi4_deburster$to_slave_wvalid),
.to_slave_wdata(mem0_controller_axi4_deburster$to_slave_wdata),
.to_slave_wstrb(mem0_controller_axi4_deburster$to_slave_wstrb),
.to_slave_wlast(mem0_controller_axi4_deburster$to_slave_wlast),
.to_slave_bready(mem0_controller_axi4_deburster$to_slave_bready),
.to_slave_arvalid(mem0_controller_axi4_deburster$to_slave_arvalid),
.to_slave_arid(mem0_controller_axi4_deburster$to_slave_arid),
.to_slave_araddr(mem0_controller_axi4_deburster$to_slave_araddr),
.to_slave_arlen(mem0_controller_axi4_deburster$to_slave_arlen),
.to_slave_arsize(mem0_controller_axi4_deburster$to_slave_arsize),
.to_slave_arburst(mem0_controller_axi4_deburster$to_slave_arburst),
.to_slave_arlock(mem0_controller_axi4_deburster$to_slave_arlock),
.to_slave_arcache(mem0_controller_axi4_deburster$to_slave_arcache),
.to_slave_arprot(mem0_controller_axi4_deburster$to_slave_arprot),
.to_slave_arqos(mem0_controller_axi4_deburster$to_slave_arqos),
.to_slave_arregion(mem0_controller_axi4_deburster$to_slave_arregion),
.to_slave_rready(mem0_controller_axi4_deburster$to_slave_rready));
// submodule uart0
mkUART uart0(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(uart0$put_from_console_put),
.set_addr_map_addr_base(uart0$set_addr_map_addr_base),
.set_addr_map_addr_lim(uart0$set_addr_map_addr_lim),
.slave_araddr(uart0$slave_araddr),
.slave_arburst(uart0$slave_arburst),
.slave_arcache(uart0$slave_arcache),
.slave_arid(uart0$slave_arid),
.slave_arlen(uart0$slave_arlen),
.slave_arlock(uart0$slave_arlock),
.slave_arprot(uart0$slave_arprot),
.slave_arqos(uart0$slave_arqos),
.slave_arregion(uart0$slave_arregion),
.slave_arsize(uart0$slave_arsize),
.slave_arvalid(uart0$slave_arvalid),
.slave_awaddr(uart0$slave_awaddr),
.slave_awburst(uart0$slave_awburst),
.slave_awcache(uart0$slave_awcache),
.slave_awid(uart0$slave_awid),
.slave_awlen(uart0$slave_awlen),
.slave_awlock(uart0$slave_awlock),
.slave_awprot(uart0$slave_awprot),
.slave_awqos(uart0$slave_awqos),
.slave_awregion(uart0$slave_awregion),
.slave_awsize(uart0$slave_awsize),
.slave_awvalid(uart0$slave_awvalid),
.slave_bready(uart0$slave_bready),
.slave_rready(uart0$slave_rready),
.slave_wdata(uart0$slave_wdata),
.slave_wlast(uart0$slave_wlast),
.slave_wstrb(uart0$slave_wstrb),
.slave_wvalid(uart0$slave_wvalid),
.EN_server_reset_request_put(uart0$EN_server_reset_request_put),
.EN_server_reset_response_get(uart0$EN_server_reset_response_get),
.EN_set_addr_map(uart0$EN_set_addr_map),
.EN_get_to_console_get(uart0$EN_get_to_console_get),
.EN_put_from_console_put(uart0$EN_put_from_console_put),
.RDY_server_reset_request_put(uart0$RDY_server_reset_request_put),
.RDY_server_reset_response_get(uart0$RDY_server_reset_response_get),
.RDY_set_addr_map(),
.slave_awready(uart0$slave_awready),
.slave_wready(uart0$slave_wready),
.slave_bvalid(uart0$slave_bvalid),
.slave_bid(uart0$slave_bid),
.slave_bresp(uart0$slave_bresp),
.slave_arready(uart0$slave_arready),
.slave_rvalid(uart0$slave_rvalid),
.slave_rid(uart0$slave_rid),
.slave_rdata(uart0$slave_rdata),
.slave_rresp(uart0$slave_rresp),
.slave_rlast(uart0$slave_rlast),
.get_to_console_get(uart0$get_to_console_get),
.RDY_get_to_console_get(uart0$RDY_get_to_console_get),
.RDY_put_from_console_put(uart0$RDY_put_from_console_put),
.intr(uart0$intr));
// rule RL_rl_wr_addr_channel
assign CAN_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel = 1'd1 ;
// rule RL_rl_wr_data_channel
assign CAN_FIRE_RL_rl_wr_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel = 1'd1 ;
// rule RL_rl_wr_response_channel
assign CAN_FIRE_RL_rl_wr_response_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel = 1'd1 ;
// rule RL_rl_rd_addr_channel
assign CAN_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel = 1'd1 ;
// rule RL_rl_rd_data_channel
assign CAN_FIRE_RL_rl_rd_data_channel = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel = 1'd1 ;
// rule RL_rl_wr_addr_channel_1
assign CAN_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_1 = 1'd1 ;
// rule RL_rl_wr_data_channel_1
assign CAN_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_response_channel_1
assign CAN_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_1 = 1'd1 ;
// rule RL_rl_rd_addr_channel_1
assign CAN_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_1 = 1'd1 ;
// rule RL_rl_rd_data_channel_1
assign CAN_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_1 = 1'd1 ;
// rule RL_rl_wr_addr_channel_2
assign CAN_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_2 = 1'd1 ;
// rule RL_rl_wr_data_channel_2
assign CAN_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_response_channel_2
assign CAN_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_2 = 1'd1 ;
// rule RL_rl_rd_addr_channel_2
assign CAN_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_2 = 1'd1 ;
// rule RL_rl_rd_data_channel_2
assign CAN_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_2 = 1'd1 ;
// rule RL_rl_wr_addr_channel_3
assign CAN_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_3 = 1'd1 ;
// rule RL_rl_wr_data_channel_3
assign CAN_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_response_channel_3
assign CAN_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_3 = 1'd1 ;
// rule RL_rl_rd_addr_channel_3
assign CAN_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_3 = 1'd1 ;
// rule RL_rl_rd_data_channel_3
assign CAN_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_3 = 1'd1 ;
// rule RL_rl_wr_addr_channel_4
assign CAN_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_4 = 1'd1 ;
// rule RL_rl_wr_data_channel_4
assign CAN_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_4 = 1'd1 ;
// rule RL_rl_wr_response_channel_4
assign CAN_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_4 = 1'd1 ;
// rule RL_rl_rd_addr_channel_4
assign CAN_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_4 = 1'd1 ;
// rule RL_rl_rd_data_channel_4
assign CAN_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_4 = 1'd1 ;
// rule RL_rl_wr_addr_channel_5
assign CAN_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_5 = 1'd1 ;
// rule RL_rl_wr_data_channel_5
assign CAN_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_5 = 1'd1 ;
// rule RL_rl_wr_response_channel_5
assign CAN_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_5 = 1'd1 ;
// rule RL_rl_rd_addr_channel_5
assign CAN_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_5 = 1'd1 ;
// rule RL_rl_rd_data_channel_5
assign CAN_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_5 = 1'd1 ;
// rule RL_rl_wr_addr_channel_6
assign CAN_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_6 = 1'd1 ;
// rule RL_rl_wr_data_channel_6
assign CAN_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_6 = 1'd1 ;
// rule RL_rl_wr_response_channel_6
assign CAN_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_6 = 1'd1 ;
// rule RL_rl_rd_addr_channel_6
assign CAN_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_6 = 1'd1 ;
// rule RL_rl_rd_data_channel_6
assign CAN_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_6 = 1'd1 ;
// rule RL_rl_wr_addr_channel_7
assign CAN_FIRE_RL_rl_wr_addr_channel_7 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_addr_channel_7 = 1'd1 ;
// rule RL_rl_wr_data_channel_7
assign CAN_FIRE_RL_rl_wr_data_channel_7 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_data_channel_7 = 1'd1 ;
// rule RL_rl_wr_response_channel_7
assign CAN_FIRE_RL_rl_wr_response_channel_7 = 1'd1 ;
assign WILL_FIRE_RL_rl_wr_response_channel_7 = 1'd1 ;
// rule RL_rl_rd_addr_channel_7
assign CAN_FIRE_RL_rl_rd_addr_channel_7 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_addr_channel_7 = 1'd1 ;
// rule RL_rl_rd_data_channel_7
assign CAN_FIRE_RL_rl_rd_data_channel_7 = 1'd1 ;
assign WILL_FIRE_RL_rl_rd_data_channel_7 = 1'd1 ;
// rule RL_rl_connect_external_interrupt_requests
assign CAN_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ;
assign WILL_FIRE_RL_rl_connect_external_interrupt_requests = 1'd1 ;
// rule RL_rl_reset_start_initial
assign CAN_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ;
assign WILL_FIRE_RL_rl_reset_start_initial = MUX_rg_state$write_1__SEL_1 ;
// rule RL_rl_reset_complete_initial
assign CAN_FIRE_RL_rl_reset_complete_initial = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_reset_complete_initial =
MUX_rg_state$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_rg_state$write_1__SEL_1 =
mem0_controller$RDY_server_reset_request_put &&
uart0$RDY_server_reset_request_put &&
fabric$RDY_reset &&
core$RDY_cpu_reset_server_request_put &&
rg_state == 2'd0 ;
assign MUX_rg_state$write_1__SEL_2 =
mem0_controller$RDY_set_addr_map &&
mem0_controller$RDY_server_reset_response_get &&
uart0$RDY_server_reset_response_get &&
core$RDY_cpu_reset_server_response_get &&
rg_state == 2'd1 ;
// register rg_state
assign rg_state$D_IN = WILL_FIRE_RL_rl_reset_start_initial ? 2'd1 : 2'd2 ;
assign rg_state$EN =
WILL_FIRE_RL_rl_reset_start_initial ||
WILL_FIRE_RL_rl_reset_complete_initial ;
// submodule boot_rom
assign boot_rom$set_addr_map_addr_base = 64'h0000000000001000 ;
assign boot_rom$set_addr_map_addr_lim = 64'd8192 ;
assign boot_rom$slave_araddr = boot_rom_axi4_deburster$to_slave_araddr ;
assign boot_rom$slave_arburst = boot_rom_axi4_deburster$to_slave_arburst ;
assign boot_rom$slave_arcache = boot_rom_axi4_deburster$to_slave_arcache ;
assign boot_rom$slave_arid = boot_rom_axi4_deburster$to_slave_arid ;
assign boot_rom$slave_arlen = boot_rom_axi4_deburster$to_slave_arlen ;
assign boot_rom$slave_arlock = boot_rom_axi4_deburster$to_slave_arlock ;
assign boot_rom$slave_arprot = boot_rom_axi4_deburster$to_slave_arprot ;
assign boot_rom$slave_arqos = boot_rom_axi4_deburster$to_slave_arqos ;
assign boot_rom$slave_arregion = boot_rom_axi4_deburster$to_slave_arregion ;
assign boot_rom$slave_arsize = boot_rom_axi4_deburster$to_slave_arsize ;
assign boot_rom$slave_arvalid = boot_rom_axi4_deburster$to_slave_arvalid ;
assign boot_rom$slave_awaddr = boot_rom_axi4_deburster$to_slave_awaddr ;
assign boot_rom$slave_awburst = boot_rom_axi4_deburster$to_slave_awburst ;
assign boot_rom$slave_awcache = boot_rom_axi4_deburster$to_slave_awcache ;
assign boot_rom$slave_awid = boot_rom_axi4_deburster$to_slave_awid ;
assign boot_rom$slave_awlen = boot_rom_axi4_deburster$to_slave_awlen ;
assign boot_rom$slave_awlock = boot_rom_axi4_deburster$to_slave_awlock ;
assign boot_rom$slave_awprot = boot_rom_axi4_deburster$to_slave_awprot ;
assign boot_rom$slave_awqos = boot_rom_axi4_deburster$to_slave_awqos ;
assign boot_rom$slave_awregion = boot_rom_axi4_deburster$to_slave_awregion ;
assign boot_rom$slave_awsize = boot_rom_axi4_deburster$to_slave_awsize ;
assign boot_rom$slave_awvalid = boot_rom_axi4_deburster$to_slave_awvalid ;
assign boot_rom$slave_bready = boot_rom_axi4_deburster$to_slave_bready ;
assign boot_rom$slave_rready = boot_rom_axi4_deburster$to_slave_rready ;
assign boot_rom$slave_wdata = boot_rom_axi4_deburster$to_slave_wdata ;
assign boot_rom$slave_wlast = boot_rom_axi4_deburster$to_slave_wlast ;
assign boot_rom$slave_wstrb = boot_rom_axi4_deburster$to_slave_wstrb ;
assign boot_rom$slave_wvalid = boot_rom_axi4_deburster$to_slave_wvalid ;
assign boot_rom$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ;
// submodule boot_rom_axi4_deburster
assign boot_rom_axi4_deburster$from_master_araddr =
fabric$v_to_slaves_0_araddr ;
assign boot_rom_axi4_deburster$from_master_arburst =
fabric$v_to_slaves_0_arburst ;
assign boot_rom_axi4_deburster$from_master_arcache =
fabric$v_to_slaves_0_arcache ;
assign boot_rom_axi4_deburster$from_master_arid =
fabric$v_to_slaves_0_arid ;
assign boot_rom_axi4_deburster$from_master_arlen =
fabric$v_to_slaves_0_arlen ;
assign boot_rom_axi4_deburster$from_master_arlock =
fabric$v_to_slaves_0_arlock ;
assign boot_rom_axi4_deburster$from_master_arprot =
fabric$v_to_slaves_0_arprot ;
assign boot_rom_axi4_deburster$from_master_arqos =
fabric$v_to_slaves_0_arqos ;
assign boot_rom_axi4_deburster$from_master_arregion =
fabric$v_to_slaves_0_arregion ;
assign boot_rom_axi4_deburster$from_master_arsize =
fabric$v_to_slaves_0_arsize ;
assign boot_rom_axi4_deburster$from_master_arvalid =
fabric$v_to_slaves_0_arvalid ;
assign boot_rom_axi4_deburster$from_master_awaddr =
fabric$v_to_slaves_0_awaddr ;
assign boot_rom_axi4_deburster$from_master_awburst =
fabric$v_to_slaves_0_awburst ;
assign boot_rom_axi4_deburster$from_master_awcache =
fabric$v_to_slaves_0_awcache ;
assign boot_rom_axi4_deburster$from_master_awid =
fabric$v_to_slaves_0_awid ;
assign boot_rom_axi4_deburster$from_master_awlen =
fabric$v_to_slaves_0_awlen ;
assign boot_rom_axi4_deburster$from_master_awlock =
fabric$v_to_slaves_0_awlock ;
assign boot_rom_axi4_deburster$from_master_awprot =
fabric$v_to_slaves_0_awprot ;
assign boot_rom_axi4_deburster$from_master_awqos =
fabric$v_to_slaves_0_awqos ;
assign boot_rom_axi4_deburster$from_master_awregion =
fabric$v_to_slaves_0_awregion ;
assign boot_rom_axi4_deburster$from_master_awsize =
fabric$v_to_slaves_0_awsize ;
assign boot_rom_axi4_deburster$from_master_awvalid =
fabric$v_to_slaves_0_awvalid ;
assign boot_rom_axi4_deburster$from_master_bready =
fabric$v_to_slaves_0_bready ;
assign boot_rom_axi4_deburster$from_master_rready =
fabric$v_to_slaves_0_rready ;
assign boot_rom_axi4_deburster$from_master_wdata =
fabric$v_to_slaves_0_wdata ;
assign boot_rom_axi4_deburster$from_master_wlast =
fabric$v_to_slaves_0_wlast ;
assign boot_rom_axi4_deburster$from_master_wstrb =
fabric$v_to_slaves_0_wstrb ;
assign boot_rom_axi4_deburster$from_master_wvalid =
fabric$v_to_slaves_0_wvalid ;
assign boot_rom_axi4_deburster$to_slave_arready = boot_rom$slave_arready ;
assign boot_rom_axi4_deburster$to_slave_awready = boot_rom$slave_awready ;
assign boot_rom_axi4_deburster$to_slave_bid = boot_rom$slave_bid ;
assign boot_rom_axi4_deburster$to_slave_bresp = boot_rom$slave_bresp ;
assign boot_rom_axi4_deburster$to_slave_bvalid = boot_rom$slave_bvalid ;
assign boot_rom_axi4_deburster$to_slave_rdata = boot_rom$slave_rdata ;
assign boot_rom_axi4_deburster$to_slave_rid = boot_rom$slave_rid ;
assign boot_rom_axi4_deburster$to_slave_rlast = boot_rom$slave_rlast ;
assign boot_rom_axi4_deburster$to_slave_rresp = boot_rom$slave_rresp ;
assign boot_rom_axi4_deburster$to_slave_rvalid = boot_rom$slave_rvalid ;
assign boot_rom_axi4_deburster$to_slave_wready = boot_rom$slave_wready ;
assign boot_rom_axi4_deburster$EN_reset = 1'b0 ;
// submodule core
assign core$core_external_interrupt_sources_0_m_interrupt_req_set_not_clear =
uart0$intr ;
assign core$core_external_interrupt_sources_10_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_11_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_12_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_13_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_14_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_15_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_1_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_2_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_3_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_4_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_5_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_6_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_7_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_8_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_external_interrupt_sources_9_m_interrupt_req_set_not_clear =
1'd0 ;
assign core$core_mem_master_arready = fabric$v_from_masters_1_arready ;
assign core$core_mem_master_awready = fabric$v_from_masters_1_awready ;
assign core$core_mem_master_bid = fabric$v_from_masters_1_bid ;
assign core$core_mem_master_bresp = fabric$v_from_masters_1_bresp ;
assign core$core_mem_master_bvalid = fabric$v_from_masters_1_bvalid ;
assign core$core_mem_master_rdata = fabric$v_from_masters_1_rdata ;
assign core$core_mem_master_rid = fabric$v_from_masters_1_rid ;
assign core$core_mem_master_rlast = fabric$v_from_masters_1_rlast ;
assign core$core_mem_master_rresp = fabric$v_from_masters_1_rresp ;
assign core$core_mem_master_rvalid = fabric$v_from_masters_1_rvalid ;
assign core$core_mem_master_wready = fabric$v_from_masters_1_wready ;
assign core$cpu_imem_master_arready = fabric$v_from_masters_0_arready ;
assign core$cpu_imem_master_awready = fabric$v_from_masters_0_awready ;
assign core$cpu_imem_master_bid = fabric$v_from_masters_0_bid ;
assign core$cpu_imem_master_bresp = fabric$v_from_masters_0_bresp ;
assign core$cpu_imem_master_bvalid = fabric$v_from_masters_0_bvalid ;
assign core$cpu_imem_master_rdata = fabric$v_from_masters_0_rdata ;
assign core$cpu_imem_master_rid = fabric$v_from_masters_0_rid ;
assign core$cpu_imem_master_rlast = fabric$v_from_masters_0_rlast ;
assign core$cpu_imem_master_rresp = fabric$v_from_masters_0_rresp ;
assign core$cpu_imem_master_rvalid = fabric$v_from_masters_0_rvalid ;
assign core$cpu_imem_master_wready = fabric$v_from_masters_0_wready ;
assign core$cpu_reset_server_request_put = 1'd1 ;
assign core$dma_server_araddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign core$dma_server_arburst = 2'b10 /* unspecified value */ ;
assign core$dma_server_arcache = 4'b1010 /* unspecified value */ ;
assign core$dma_server_arid =
16'b1010101010101010 /* unspecified value */ ;
assign core$dma_server_arlen = 8'b10101010 /* unspecified value */ ;
assign core$dma_server_arlock = 1'b0 /* unspecified value */ ;
assign core$dma_server_arprot = 3'b010 /* unspecified value */ ;
assign core$dma_server_arqos = 4'b1010 /* unspecified value */ ;
assign core$dma_server_arregion = 4'b1010 /* unspecified value */ ;
assign core$dma_server_arsize = 3'b010 /* unspecified value */ ;
assign core$dma_server_arvalid = 1'd0 ;
assign core$dma_server_awaddr =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign core$dma_server_awburst = 2'b10 /* unspecified value */ ;
assign core$dma_server_awcache = 4'b1010 /* unspecified value */ ;
assign core$dma_server_awid =
16'b1010101010101010 /* unspecified value */ ;
assign core$dma_server_awlen = 8'b10101010 /* unspecified value */ ;
assign core$dma_server_awlock = 1'b0 /* unspecified value */ ;
assign core$dma_server_awprot = 3'b010 /* unspecified value */ ;
assign core$dma_server_awqos = 4'b1010 /* unspecified value */ ;
assign core$dma_server_awregion = 4'b1010 /* unspecified value */ ;
assign core$dma_server_awsize = 3'b010 /* unspecified value */ ;
assign core$dma_server_awvalid = 1'd0 ;
assign core$dma_server_bready = 1'd0 ;
assign core$dma_server_rready = 1'd0 ;
assign core$dma_server_wdata =
512'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign core$dma_server_wlast = 1'b0 /* unspecified value */ ;
assign core$dma_server_wstrb =
64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign core$dma_server_wvalid = 1'd0 ;
assign core$nmi_req_set_not_clear = 1'd0 ;
assign core$set_verbosity_logdelay = set_verbosity_logdelay ;
assign core$set_verbosity_verbosity = set_verbosity_verbosity ;
assign core$set_watch_tohost_tohost_addr = set_watch_tohost_tohost_addr ;
assign core$set_watch_tohost_watch_tohost = set_watch_tohost_watch_tohost ;
assign core$EN_cpu_reset_server_request_put = MUX_rg_state$write_1__SEL_1 ;
assign core$EN_cpu_reset_server_response_get = MUX_rg_state$write_1__SEL_2 ;
assign core$EN_set_verbosity = EN_set_verbosity ;
assign core$EN_set_watch_tohost = EN_set_watch_tohost ;
assign core$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;
// submodule fabric
assign fabric$set_verbosity_verbosity = 4'h0 ;
assign fabric$v_from_masters_0_araddr = core$cpu_imem_master_araddr ;
assign fabric$v_from_masters_0_arburst = core$cpu_imem_master_arburst ;
assign fabric$v_from_masters_0_arcache = core$cpu_imem_master_arcache ;
assign fabric$v_from_masters_0_arid = core$cpu_imem_master_arid ;
assign fabric$v_from_masters_0_arlen = core$cpu_imem_master_arlen ;
assign fabric$v_from_masters_0_arlock = core$cpu_imem_master_arlock ;
assign fabric$v_from_masters_0_arprot = core$cpu_imem_master_arprot ;
assign fabric$v_from_masters_0_arqos = core$cpu_imem_master_arqos ;
assign fabric$v_from_masters_0_arregion = core$cpu_imem_master_arregion ;
assign fabric$v_from_masters_0_arsize = core$cpu_imem_master_arsize ;
assign fabric$v_from_masters_0_arvalid = core$cpu_imem_master_arvalid ;
assign fabric$v_from_masters_0_awaddr = core$cpu_imem_master_awaddr ;
assign fabric$v_from_masters_0_awburst = core$cpu_imem_master_awburst ;
assign fabric$v_from_masters_0_awcache = core$cpu_imem_master_awcache ;
assign fabric$v_from_masters_0_awid = core$cpu_imem_master_awid ;
assign fabric$v_from_masters_0_awlen = core$cpu_imem_master_awlen ;
assign fabric$v_from_masters_0_awlock = core$cpu_imem_master_awlock ;
assign fabric$v_from_masters_0_awprot = core$cpu_imem_master_awprot ;
assign fabric$v_from_masters_0_awqos = core$cpu_imem_master_awqos ;
assign fabric$v_from_masters_0_awregion = core$cpu_imem_master_awregion ;
assign fabric$v_from_masters_0_awsize = core$cpu_imem_master_awsize ;
assign fabric$v_from_masters_0_awvalid = core$cpu_imem_master_awvalid ;
assign fabric$v_from_masters_0_bready = core$cpu_imem_master_bready ;
assign fabric$v_from_masters_0_rready = core$cpu_imem_master_rready ;
assign fabric$v_from_masters_0_wdata = core$cpu_imem_master_wdata ;
assign fabric$v_from_masters_0_wlast = core$cpu_imem_master_wlast ;
assign fabric$v_from_masters_0_wstrb = core$cpu_imem_master_wstrb ;
assign fabric$v_from_masters_0_wvalid = core$cpu_imem_master_wvalid ;
assign fabric$v_from_masters_1_araddr = core$core_mem_master_araddr ;
assign fabric$v_from_masters_1_arburst = core$core_mem_master_arburst ;
assign fabric$v_from_masters_1_arcache = core$core_mem_master_arcache ;
assign fabric$v_from_masters_1_arid = core$core_mem_master_arid ;
assign fabric$v_from_masters_1_arlen = core$core_mem_master_arlen ;
assign fabric$v_from_masters_1_arlock = core$core_mem_master_arlock ;
assign fabric$v_from_masters_1_arprot = core$core_mem_master_arprot ;
assign fabric$v_from_masters_1_arqos = core$core_mem_master_arqos ;
assign fabric$v_from_masters_1_arregion = core$core_mem_master_arregion ;
assign fabric$v_from_masters_1_arsize = core$core_mem_master_arsize ;
assign fabric$v_from_masters_1_arvalid = core$core_mem_master_arvalid ;
assign fabric$v_from_masters_1_awaddr = core$core_mem_master_awaddr ;
assign fabric$v_from_masters_1_awburst = core$core_mem_master_awburst ;
assign fabric$v_from_masters_1_awcache = core$core_mem_master_awcache ;
assign fabric$v_from_masters_1_awid = core$core_mem_master_awid ;
assign fabric$v_from_masters_1_awlen = core$core_mem_master_awlen ;
assign fabric$v_from_masters_1_awlock = core$core_mem_master_awlock ;
assign fabric$v_from_masters_1_awprot = core$core_mem_master_awprot ;
assign fabric$v_from_masters_1_awqos = core$core_mem_master_awqos ;
assign fabric$v_from_masters_1_awregion = core$core_mem_master_awregion ;
assign fabric$v_from_masters_1_awsize = core$core_mem_master_awsize ;
assign fabric$v_from_masters_1_awvalid = core$core_mem_master_awvalid ;
assign fabric$v_from_masters_1_bready = core$core_mem_master_bready ;
assign fabric$v_from_masters_1_rready = core$core_mem_master_rready ;
assign fabric$v_from_masters_1_wdata = core$core_mem_master_wdata ;
assign fabric$v_from_masters_1_wlast = core$core_mem_master_wlast ;
assign fabric$v_from_masters_1_wstrb = core$core_mem_master_wstrb ;
assign fabric$v_from_masters_1_wvalid = core$core_mem_master_wvalid ;
assign fabric$v_to_slaves_0_arready =
boot_rom_axi4_deburster$from_master_arready ;
assign fabric$v_to_slaves_0_awready =
boot_rom_axi4_deburster$from_master_awready ;
assign fabric$v_to_slaves_0_bid = boot_rom_axi4_deburster$from_master_bid ;
assign fabric$v_to_slaves_0_bresp =
boot_rom_axi4_deburster$from_master_bresp ;
assign fabric$v_to_slaves_0_bvalid =
boot_rom_axi4_deburster$from_master_bvalid ;
assign fabric$v_to_slaves_0_rdata =
boot_rom_axi4_deburster$from_master_rdata ;
assign fabric$v_to_slaves_0_rid = boot_rom_axi4_deburster$from_master_rid ;
assign fabric$v_to_slaves_0_rlast =
boot_rom_axi4_deburster$from_master_rlast ;
assign fabric$v_to_slaves_0_rresp =
boot_rom_axi4_deburster$from_master_rresp ;
assign fabric$v_to_slaves_0_rvalid =
boot_rom_axi4_deburster$from_master_rvalid ;
assign fabric$v_to_slaves_0_wready =
boot_rom_axi4_deburster$from_master_wready ;
assign fabric$v_to_slaves_1_arready =
mem0_controller_axi4_deburster$from_master_arready ;
assign fabric$v_to_slaves_1_awready =
mem0_controller_axi4_deburster$from_master_awready ;
assign fabric$v_to_slaves_1_bid =
mem0_controller_axi4_deburster$from_master_bid ;
assign fabric$v_to_slaves_1_bresp =
mem0_controller_axi4_deburster$from_master_bresp ;
assign fabric$v_to_slaves_1_bvalid =
mem0_controller_axi4_deburster$from_master_bvalid ;
assign fabric$v_to_slaves_1_rdata =
mem0_controller_axi4_deburster$from_master_rdata ;
assign fabric$v_to_slaves_1_rid =
mem0_controller_axi4_deburster$from_master_rid ;
assign fabric$v_to_slaves_1_rlast =
mem0_controller_axi4_deburster$from_master_rlast ;
assign fabric$v_to_slaves_1_rresp =
mem0_controller_axi4_deburster$from_master_rresp ;
assign fabric$v_to_slaves_1_rvalid =
mem0_controller_axi4_deburster$from_master_rvalid ;
assign fabric$v_to_slaves_1_wready =
mem0_controller_axi4_deburster$from_master_wready ;
assign fabric$v_to_slaves_2_arready = uart0$slave_arready ;
assign fabric$v_to_slaves_2_awready = uart0$slave_awready ;
assign fabric$v_to_slaves_2_bid = uart0$slave_bid ;
assign fabric$v_to_slaves_2_bresp = uart0$slave_bresp ;
assign fabric$v_to_slaves_2_bvalid = uart0$slave_bvalid ;
assign fabric$v_to_slaves_2_rdata = uart0$slave_rdata ;
assign fabric$v_to_slaves_2_rid = uart0$slave_rid ;
assign fabric$v_to_slaves_2_rlast = uart0$slave_rlast ;
assign fabric$v_to_slaves_2_rresp = uart0$slave_rresp ;
assign fabric$v_to_slaves_2_rvalid = uart0$slave_rvalid ;
assign fabric$v_to_slaves_2_wready = uart0$slave_wready ;
assign fabric$EN_reset = MUX_rg_state$write_1__SEL_1 ;
assign fabric$EN_set_verbosity = 1'b0 ;
// submodule mem0_controller
assign mem0_controller$set_addr_map_addr_base = 64'h0000000080000000 ;
assign mem0_controller$set_addr_map_addr_lim = 64'h0000000090000000 ;
assign mem0_controller$set_watch_tohost_tohost_addr = 64'h0 ;
assign mem0_controller$set_watch_tohost_watch_tohost = 1'b0 ;
assign mem0_controller$slave_araddr =
mem0_controller_axi4_deburster$to_slave_araddr ;
assign mem0_controller$slave_arburst =
mem0_controller_axi4_deburster$to_slave_arburst ;
assign mem0_controller$slave_arcache =
mem0_controller_axi4_deburster$to_slave_arcache ;
assign mem0_controller$slave_arid =
mem0_controller_axi4_deburster$to_slave_arid ;
assign mem0_controller$slave_arlen =
mem0_controller_axi4_deburster$to_slave_arlen ;
assign mem0_controller$slave_arlock =
mem0_controller_axi4_deburster$to_slave_arlock ;
assign mem0_controller$slave_arprot =
mem0_controller_axi4_deburster$to_slave_arprot ;
assign mem0_controller$slave_arqos =
mem0_controller_axi4_deburster$to_slave_arqos ;
assign mem0_controller$slave_arregion =
mem0_controller_axi4_deburster$to_slave_arregion ;
assign mem0_controller$slave_arsize =
mem0_controller_axi4_deburster$to_slave_arsize ;
assign mem0_controller$slave_arvalid =
mem0_controller_axi4_deburster$to_slave_arvalid ;
assign mem0_controller$slave_awaddr =
mem0_controller_axi4_deburster$to_slave_awaddr ;
assign mem0_controller$slave_awburst =
mem0_controller_axi4_deburster$to_slave_awburst ;
assign mem0_controller$slave_awcache =
mem0_controller_axi4_deburster$to_slave_awcache ;
assign mem0_controller$slave_awid =
mem0_controller_axi4_deburster$to_slave_awid ;
assign mem0_controller$slave_awlen =
mem0_controller_axi4_deburster$to_slave_awlen ;
assign mem0_controller$slave_awlock =
mem0_controller_axi4_deburster$to_slave_awlock ;
assign mem0_controller$slave_awprot =
mem0_controller_axi4_deburster$to_slave_awprot ;
assign mem0_controller$slave_awqos =
mem0_controller_axi4_deburster$to_slave_awqos ;
assign mem0_controller$slave_awregion =
mem0_controller_axi4_deburster$to_slave_awregion ;
assign mem0_controller$slave_awsize =
mem0_controller_axi4_deburster$to_slave_awsize ;
assign mem0_controller$slave_awvalid =
mem0_controller_axi4_deburster$to_slave_awvalid ;
assign mem0_controller$slave_bready =
mem0_controller_axi4_deburster$to_slave_bready ;
assign mem0_controller$slave_rready =
mem0_controller_axi4_deburster$to_slave_rready ;
assign mem0_controller$slave_wdata =
mem0_controller_axi4_deburster$to_slave_wdata ;
assign mem0_controller$slave_wlast =
mem0_controller_axi4_deburster$to_slave_wlast ;
assign mem0_controller$slave_wstrb =
mem0_controller_axi4_deburster$to_slave_wstrb ;
assign mem0_controller$slave_wvalid =
mem0_controller_axi4_deburster$to_slave_wvalid ;
assign mem0_controller$to_raw_mem_response_put = to_raw_mem_response_put ;
assign mem0_controller$EN_server_reset_request_put =
MUX_rg_state$write_1__SEL_1 ;
assign mem0_controller$EN_server_reset_response_get =
MUX_rg_state$write_1__SEL_2 ;
assign mem0_controller$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ;
assign mem0_controller$EN_to_raw_mem_request_get =
EN_to_raw_mem_request_get ;
assign mem0_controller$EN_to_raw_mem_response_put =
EN_to_raw_mem_response_put ;
assign mem0_controller$EN_set_watch_tohost = 1'b0 ;
// submodule mem0_controller_axi4_deburster
assign mem0_controller_axi4_deburster$from_master_araddr =
fabric$v_to_slaves_1_araddr ;
assign mem0_controller_axi4_deburster$from_master_arburst =
fabric$v_to_slaves_1_arburst ;
assign mem0_controller_axi4_deburster$from_master_arcache =
fabric$v_to_slaves_1_arcache ;
assign mem0_controller_axi4_deburster$from_master_arid =
fabric$v_to_slaves_1_arid ;
assign mem0_controller_axi4_deburster$from_master_arlen =
fabric$v_to_slaves_1_arlen ;
assign mem0_controller_axi4_deburster$from_master_arlock =
fabric$v_to_slaves_1_arlock ;
assign mem0_controller_axi4_deburster$from_master_arprot =
fabric$v_to_slaves_1_arprot ;
assign mem0_controller_axi4_deburster$from_master_arqos =
fabric$v_to_slaves_1_arqos ;
assign mem0_controller_axi4_deburster$from_master_arregion =
fabric$v_to_slaves_1_arregion ;
assign mem0_controller_axi4_deburster$from_master_arsize =
fabric$v_to_slaves_1_arsize ;
assign mem0_controller_axi4_deburster$from_master_arvalid =
fabric$v_to_slaves_1_arvalid ;
assign mem0_controller_axi4_deburster$from_master_awaddr =
fabric$v_to_slaves_1_awaddr ;
assign mem0_controller_axi4_deburster$from_master_awburst =
fabric$v_to_slaves_1_awburst ;
assign mem0_controller_axi4_deburster$from_master_awcache =
fabric$v_to_slaves_1_awcache ;
assign mem0_controller_axi4_deburster$from_master_awid =
fabric$v_to_slaves_1_awid ;
assign mem0_controller_axi4_deburster$from_master_awlen =
fabric$v_to_slaves_1_awlen ;
assign mem0_controller_axi4_deburster$from_master_awlock =
fabric$v_to_slaves_1_awlock ;
assign mem0_controller_axi4_deburster$from_master_awprot =
fabric$v_to_slaves_1_awprot ;
assign mem0_controller_axi4_deburster$from_master_awqos =
fabric$v_to_slaves_1_awqos ;
assign mem0_controller_axi4_deburster$from_master_awregion =
fabric$v_to_slaves_1_awregion ;
assign mem0_controller_axi4_deburster$from_master_awsize =
fabric$v_to_slaves_1_awsize ;
assign mem0_controller_axi4_deburster$from_master_awvalid =
fabric$v_to_slaves_1_awvalid ;
assign mem0_controller_axi4_deburster$from_master_bready =
fabric$v_to_slaves_1_bready ;
assign mem0_controller_axi4_deburster$from_master_rready =
fabric$v_to_slaves_1_rready ;
assign mem0_controller_axi4_deburster$from_master_wdata =
fabric$v_to_slaves_1_wdata ;
assign mem0_controller_axi4_deburster$from_master_wlast =
fabric$v_to_slaves_1_wlast ;
assign mem0_controller_axi4_deburster$from_master_wstrb =
fabric$v_to_slaves_1_wstrb ;
assign mem0_controller_axi4_deburster$from_master_wvalid =
fabric$v_to_slaves_1_wvalid ;
assign mem0_controller_axi4_deburster$to_slave_arready =
mem0_controller$slave_arready ;
assign mem0_controller_axi4_deburster$to_slave_awready =
mem0_controller$slave_awready ;
assign mem0_controller_axi4_deburster$to_slave_bid =
mem0_controller$slave_bid ;
assign mem0_controller_axi4_deburster$to_slave_bresp =
mem0_controller$slave_bresp ;
assign mem0_controller_axi4_deburster$to_slave_bvalid =
mem0_controller$slave_bvalid ;
assign mem0_controller_axi4_deburster$to_slave_rdata =
mem0_controller$slave_rdata ;
assign mem0_controller_axi4_deburster$to_slave_rid =
mem0_controller$slave_rid ;
assign mem0_controller_axi4_deburster$to_slave_rlast =
mem0_controller$slave_rlast ;
assign mem0_controller_axi4_deburster$to_slave_rresp =
mem0_controller$slave_rresp ;
assign mem0_controller_axi4_deburster$to_slave_rvalid =
mem0_controller$slave_rvalid ;
assign mem0_controller_axi4_deburster$to_slave_wready =
mem0_controller$slave_wready ;
assign mem0_controller_axi4_deburster$EN_reset = 1'b0 ;
// submodule uart0
assign uart0$put_from_console_put = put_from_console_put ;
assign uart0$set_addr_map_addr_base = 64'h00000000C0000000 ;
assign uart0$set_addr_map_addr_lim = 64'h00000000C0000080 ;
assign uart0$slave_araddr = fabric$v_to_slaves_2_araddr ;
assign uart0$slave_arburst = fabric$v_to_slaves_2_arburst ;
assign uart0$slave_arcache = fabric$v_to_slaves_2_arcache ;
assign uart0$slave_arid = fabric$v_to_slaves_2_arid ;
assign uart0$slave_arlen = fabric$v_to_slaves_2_arlen ;
assign uart0$slave_arlock = fabric$v_to_slaves_2_arlock ;
assign uart0$slave_arprot = fabric$v_to_slaves_2_arprot ;
assign uart0$slave_arqos = fabric$v_to_slaves_2_arqos ;
assign uart0$slave_arregion = fabric$v_to_slaves_2_arregion ;
assign uart0$slave_arsize = fabric$v_to_slaves_2_arsize ;
assign uart0$slave_arvalid = fabric$v_to_slaves_2_arvalid ;
assign uart0$slave_awaddr = fabric$v_to_slaves_2_awaddr ;
assign uart0$slave_awburst = fabric$v_to_slaves_2_awburst ;
assign uart0$slave_awcache = fabric$v_to_slaves_2_awcache ;
assign uart0$slave_awid = fabric$v_to_slaves_2_awid ;
assign uart0$slave_awlen = fabric$v_to_slaves_2_awlen ;
assign uart0$slave_awlock = fabric$v_to_slaves_2_awlock ;
assign uart0$slave_awprot = fabric$v_to_slaves_2_awprot ;
assign uart0$slave_awqos = fabric$v_to_slaves_2_awqos ;
assign uart0$slave_awregion = fabric$v_to_slaves_2_awregion ;
assign uart0$slave_awsize = fabric$v_to_slaves_2_awsize ;
assign uart0$slave_awvalid = fabric$v_to_slaves_2_awvalid ;
assign uart0$slave_bready = fabric$v_to_slaves_2_bready ;
assign uart0$slave_rready = fabric$v_to_slaves_2_rready ;
assign uart0$slave_wdata = fabric$v_to_slaves_2_wdata ;
assign uart0$slave_wlast = fabric$v_to_slaves_2_wlast ;
assign uart0$slave_wstrb = fabric$v_to_slaves_2_wstrb ;
assign uart0$slave_wvalid = fabric$v_to_slaves_2_wvalid ;
assign uart0$EN_server_reset_request_put = MUX_rg_state$write_1__SEL_1 ;
assign uart0$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
assign uart0$EN_set_addr_map = MUX_rg_state$write_1__SEL_2 ;
assign uart0$EN_get_to_console_get = EN_get_to_console_get ;
assign uart0$EN_put_from_console_put = EN_put_from_console_put ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start_initial)
begin
v__h11352 = $stime;
#0;
end
v__h11346 = v__h11352 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_start_initial)
$display("%0d:%m.rl_reset_start_initial ...", v__h11346);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete_initial)
begin
v__h11582 = $stime;
#0;
end
v__h11576 = v__h11582 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_complete_initial)
$display("%0d:%m.rl_reset_complete_initial", v__h11576);
end
// synopsys translate_on
endmodule // mkSoC_Top
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk the_DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_instance_index = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_ir_width = 2,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_mfg_id = 70,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_action = "",
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_n_scan = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_sim_total_length = 0,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_type_id = 34,
// DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/***********************************************
Module Name: CORDIC_atan_test
Feature: Testbench for CORDIC (mode 2)
An example for the GEM Projects
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Variables:
clk: clock for processing
reset: reset flag
------------------------------------------------------
History:
06-21-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
`define MODE 2
`define LENGTH 256
`define WIDTH 16
`define ORDER 12
//Insert the modules
module CORDIC_atan_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
//loop for test vectors
reg signed[(`WIDTH-1):0] test_vector_tan[(`LENGTH-1):0];
reg signed[(`WIDTH-1):0] test_vector_atan[(`LENGTH-1):0];
//Test Vector Value
wire signed[(`WIDTH-1):0] atan_value;
//middle signals
wire signed[(`WIDTH-1):0] atan_adj;
wire signed[(`WIDTH-1):0] comp_atan;
//Results right? Comparision results
wire[(`WIDTH*2-1):0] op;
wire[(`WIDTH*2-1):0] res;
wire signed[(`WIDTH-1):0] res_atan;
wire [7:0] index;
assign res_atan = res[`WIDTH -1 : 0];
assign op = {{(`WIDTH){1'b0}}, test_vector_tan[cntr]};
assign index = (cntr - 1 - `ORDER) % `LENGTH;
assign atan_value = test_vector_atan[index];
assign atan_adj = res_atan;
assign comp_atan = atan_value - atan_adj;
//Connection to the modules
CORDIC #(.MODE(`MODE))
//CORDIC Mode
C (
.CLK(clk), .RESET_n(reset),
.operand(op), .results(res)
);
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Load the test vectors
initial
begin
$readmemh("tan_test_vector.txt", test_vector_tan);
$readmemh("atan_test_vector.txt", test_vector_atan);
end
//Load the input of 0 order element
//Comparision
always @(posedge clk or negedge reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
begin
cntr <= cntr + 8'h01;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_PP_SYMBOL_V
|
(** * Basics: Functional Programming in Coq *)
(* This library definition is included here temporarily
for backward compatibility with Coq 8.3.
Please ignore. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_andb1: (andb true false) = false.
Proof. reflexivity. Qed.
Example test_andb2: (andb false false) = false.
Proof. reflexivity. Qed.
Example test_andb3: (andb false true) = false.
Proof. reflexivity. Qed.
Example test_andb4: (andb true true) = true.
Proof. reflexivity. Qed.
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof.
simpl.
reflexivity.
Qed.
Example test_nandb2: (nandb false false) = true.
Proof.
simpl.
reflexivity.
Qed.
Example test_nandb3: (nandb false true) = true.
Proof.
simpl.
reflexivity.
Qed.
Example test_nandb4: (nandb true true) = false.
Proof.
simpl.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof.
simpl. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof.
simpl. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof.
simpl. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof.
simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof.
simpl.
reflexivity.
Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof.
simpl.
reflexivity.
Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
(andb (negb (beq_nat n m)) (ble_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof.
reflexivity.
Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof.
reflexivity.
Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more than [simpl] -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword keyword [Theorem] instead of
[Example]. Indeed, the latter difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H. rewrite -> H.
intros H'. rewrite <- H'.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
rewrite <- plus_1_l.
intros H.
rewrite <- H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros A.
intros b.
rewrite A. rewrite A.
reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice:
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros A.
intros b.
rewrite A.
rewrite A.
rewrite negb_involutive.
reflexivity. Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two.) *)
Theorem andb_orb_eq_impl_b_c_eq:
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
destruct c.
auto. (* FIXME Is it unfair to auto? *)
auto. (* How would the cases be proven by hand? *)
destruct c.
auto.
auto. Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| Z : bin
| T : bin -> bin
| ST : bin -> bin.
Fixpoint succ_bin (num: bin) :=
match num with
| Z => ST Z
| T num' => ST num'
| ST num' => match num' with
| Z => T num
| T num'' => T (ST num'')
| ST num'' => T (T (succ_bin num'')) end end.
Fixpoint bin_to_nat (b: bin) :=
match b with
| Z => O
| T b' => 2 * bin_to_nat(b')
| ST b' => 2 * bin_to_nat(b') + 1 end.
Example succ_zero_bin_nat:
(bin_to_nat (succ_bin Z)) = (S O).
Proof.
reflexivity. Qed.
Example succ_one_bin_nat:
(bin_to_nat (succ_bin (T (ST Z)))) = (S (S (S O))).
Proof.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
Fixpoint add_at_most_two_nat (n: nat) (two: bool) :=
match two with
| true => add_at_most_two_nat (S n) false
| false => S n
end.
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// system1_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module system1_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
system1_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:01:56 04/23/2017
// Design Name: decrypt
// Module Name: C:/Users/vkoro/Final_Project/project/des/DES/decrypt_tb.v
// Project Name: DES
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: decrypt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module decrypt_tb;
// Inputs
reg [63:0] message;
reg [63:0] DESkey;
reg clk;
reg reset;
reg enable;
reg ack;
integer clk_cnt;
parameter CLK_PERIOD = 10;
// Outputs
wire [63:0] decrypted;
wire done;
// Instantiate the Unit Under Test (UUT)
decrypt_dumb uut (
.message(message),
.DESkey(DESkey),
.decrypted(decrypted),
.done(done),
.clk(clk),
.reset(reset),
.enable(enable),
.ack(ack)
);
initial
begin : CLK_GENERATOR
clk = 0;
forever
begin
#(CLK_PERIOD/2) clk = ~clk;
end
end
initial
begin : RESET_GENERATOR
reset = 1;
#(10 * CLK_PERIOD) reset = 0;
end
initial
begin : CLK_COUNTER
clk_cnt = 0;
forever
begin
#(CLK_PERIOD) clk_cnt = clk_cnt + 1;
end
end
initial begin
// Initialize Inputs
message = 0;
DESkey = 0;
enable = 0;
ack = 0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
message = 64'b1110000010100110111110111111100010010010011001011010011101100101;
DESkey = 64'h133457799BBCDFF1;
enable = 1;
wait(done);
ack = 1;
# 100;
DESkey = 64'h133457799BBCDFF0;
wait(done);
ack = 1;
# 100;
DESkey = 64'hab01986231bc8d01;
//ack = 1;
# 10;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Response Down-Sizer
// Collect MI-side responses and set the SI-side response to the most critical
// level (in descending order):
// DECERR, SLVERROR and OKAY.
// EXOKAY cannot occur for split transactions.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// wr_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_b_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire [8-1:0] cmd_repeat,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Repeat handling related.
reg [8-1:0] repeat_cnt_pre;
reg [8-1:0] repeat_cnt;
wire [8-1:0] next_repeat_cnt;
reg first_mi_word;
wire last_word;
// Ongoing split transaction.
wire load_bresp;
wire need_to_update_bresp;
reg [2-1:0] S_AXI_BRESP_ACC;
// Internal signals for MI-side.
wire M_AXI_BREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID_I;
reg [2-1:0] S_AXI_BRESP_I;
wire S_AXI_BVALID_I;
wire S_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// The MI-side BRESP is popped when at once for split transactions, except
// for the last cycle that behaves like a "normal" transaction.
// A "normal" BRESP is popped once the SI-side is able to use it,
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from MI-side.
assign M_AXI_BREADY_I = M_AXI_BVALID & ~mi_stalling;
assign M_AXI_BREADY = M_AXI_BREADY_I;
// Indicate when there is a BRESP available @ SI-side.
assign S_AXI_BVALID_I = M_AXI_BVALID & last_word;
// Get MI-side data.
assign pop_mi_data = M_AXI_BVALID & M_AXI_BREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = (~S_AXI_BREADY_I & last_word);
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of BRESP.
//
// Forward the accumulated or MI-side BRESP value depending on state:
// * MI-side BRESP is forwarded untouched when it is a non split cycle.
// (MI-side BRESP value is also used when updating the accumulated for
// the last access during a split access).
// * The accumulated BRESP is for a split transaction.
//
// The accumulated BRESP register is updated for each MI-side response that
// is used.
//
/////////////////////////////////////////////////////////////////////////////
// Force load accumulated BRESPs to first value
assign load_bresp = (cmd_split & first_mi_word);
// Update if more critical.
assign need_to_update_bresp = ( M_AXI_BRESP > S_AXI_BRESP_ACC );
// Select accumultated or direct depending on setting.
always @ *
begin
if ( cmd_split ) begin
if ( load_bresp || need_to_update_bresp ) begin
S_AXI_BRESP_I = M_AXI_BRESP;
end else begin
S_AXI_BRESP_I = S_AXI_BRESP_ACC;
end
end else begin
S_AXI_BRESP_I = M_AXI_BRESP;
end
end
// Accumulate MI-side BRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_BRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_BRESP_ACC <= S_AXI_BRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Keep track of BRESP repeat counter.
//
// Last BRESP word is either:
// * The first and only word when not merging.
// * The last value when merging.
//
// The internal counter is taken from the external command interface during
// the first response when merging. The counter is updated each time a
// BRESP is popped from the MI-side interface.
//
/////////////////////////////////////////////////////////////////////////////
// Determine last BRESP cycle.
assign last_word = ( ( repeat_cnt == 8'b0 ) & ~first_mi_word ) |
~cmd_split;
// Select command reapeat or counted repeat value.
always @ *
begin
if ( first_mi_word ) begin
repeat_cnt_pre = cmd_repeat;
end else begin
repeat_cnt_pre = repeat_cnt;
end
end
// Calculate next repeat counter value.
assign next_repeat_cnt = repeat_cnt_pre - 2'b01;
// Keep track of the repeat count.
always @ (posedge ACLK) begin
if (ARESET) begin
repeat_cnt <= 8'b0;
first_mi_word <= 1'b1;
end else begin
if ( pop_mi_data ) begin
repeat_cnt <= next_repeat_cnt;
first_mi_word <= last_word;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// BID Handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_BID_I = cmd_id;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_BID = S_AXI_BID_I;
assign S_AXI_BRESP = S_AXI_BRESP_I;
assign S_AXI_BVALID = S_AXI_BVALID_I;
assign S_AXI_BREADY_I = S_AXI_BREADY;
endmodule
|
`include "core.h"
`default_nettype none
module execute_forwarding(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Writeback - General Register
input wire iWB_GR_VALID,
input wire [31:0] iWB_GR_DATA,
input wire [4:0] iWB_GR_DEST,
input wire iWB_GR_DEST_SYSREG,
//Writeback - Stack Point Register
input wire iWB_SPR_VALID,
input wire [31:0] iWB_SPR_DATA,
//Writeback - FRCR
input wire iWR_FRCR_VALID,
input wire [63:0] iWR_FRCR_DATA,
//Previous Writeback - General Register
input wire iPREV_WB_GR_VALID,
input wire [31:0] iPREV_WB_GR_DATA,
input wire [4:0] iPREV_WB_GR_DEST,
input wire iPREV_WB_GR_DEST_SYSREG,
//Previous Writeback - Stack Point Register
input wire iPREV_WB_SPR_VALID,
input wire [31:0] iPREV_WB_SPR_DATA,
//Previous Writeback - FRCR
input wire iPREV_WB_FRCR_VALID,
input wire [63:0] iPREV_WB_FRCR_DATA,
//Source
input wire iPREVIOUS_SOURCE_SYSREG,
input wire [4:0] iPREVIOUS_SOURCE_POINTER,
input wire iPREVIOUS_SOURCE_IMM,
input wire [31:0] iPREVIOUS_SOURCE_DATA,
input wire [31:0] iPREVIOUS_SOURCE_PDTR,
input wire [31:0] iPREVIOUS_SOURCE_KPDTR,
input wire [31:0] iPREVIOUS_SOURCE_TIDR,
input wire [31:0] iPREVIOUS_SOURCE_PSR,
//Output
output wire [31:0] oNEXT_SOURCE_DATA,
output wire [31:0] oNEXT_SOURCE_SPR,
output wire [31:0] oNEXT_SOURCE_PDTR,
output wire [31:0] oNEXT_SOURCE_KPDTR,
output wire [31:0] oNEXT_SOURCE_TIDR,
output wire [31:0] oNEXT_SOURCE_PSR
);
/************************************************************************
Fowarding Function
************************************************************************/
function [31:0] func_forwarding_rewrite;
input func_src_settle; //No forwarding
input [4:0] func_src_pointer;
input func_src_sysreg;
input [31:0] func_src_data;
//Previous
input func_prev_valid;
input func_prev_sysreg;
input func_prev_spr_writeback;
input func_prev_frcr_writeback;
input [4:0] func_prev_dest_pointer;
//input [31:0] func_prev_pcr;
input [31:0] func_prev_spr;
input [63:0] func_prev_frcr;
input [31:0] func_prev_gr_data;
begin
//Forwarding Valid
if(func_prev_valid && !func_src_settle)begin
//SPR Forwarding
//Source Sysreg -> Valid, Source Pointer -> SPR, Previous Data -> Valid, Previous SPR Writeback -> Valid
if(func_src_sysreg && func_src_pointer == `SYSREG_SPR && (func_prev_spr_writeback || func_prev_dest_pointer == `SYSREG_SPR))begin
func_forwarding_rewrite = func_prev_spr;
end
//FRCLR Forwarding
else if(func_src_sysreg && func_src_pointer == `SYSREG_FRCLR && func_prev_dest_pointer == `SYSREG_FRCR2FRCXR)begin
func_forwarding_rewrite = func_prev_frcr[31:0];
end
//FRCHR Forwarding
else if(func_src_sysreg && func_src_pointer == `SYSREG_FRCHR && func_prev_dest_pointer == `SYSREG_FRCR2FRCXR)begin
func_forwarding_rewrite = func_prev_frcr[63:32];
end
//General Register Fowerding
else if(!func_src_sysreg && !func_prev_sysreg && func_src_pointer == func_prev_dest_pointer)begin
func_forwarding_rewrite = func_prev_gr_data;
end
//No Forwarding
else begin
func_forwarding_rewrite = func_src_data;
end
end
//No Forwarding
else begin
func_forwarding_rewrite = func_src_data;
end
end
endfunction
function [31:0] func_forwarding_reqrite_spr;
input [31:0] func_prev_data;
input func_cuur_valid;
input [31:0] func_cuur_data;
begin
if(func_cuur_valid)begin
func_forwarding_reqrite_spr = func_cuur_data;
end
else begin
func_forwarding_reqrite_spr = func_prev_data;
end
end
endfunction
function [31:0] func_forwarding_rewrite_sysreg;
input [4:0] func_target_sysreg;
//Current
input [31:0] func_src_data;
//Previous
input func_prev_valid;
input func_prev_sysreg;
input [4:0] func_prev_dest_pointer;
input [31:0] func_prev_data;
begin
//Forwarding Valid
if(func_prev_valid && func_prev_sysreg && func_prev_dest_pointer == func_target_sysreg)begin
//Forwarding
func_forwarding_rewrite_sysreg = func_prev_data;
end
//No Forwarding
else begin
func_forwarding_rewrite_sysreg = func_src_data;
end
end
endfunction
/************************************************************************
Assign
************************************************************************/
//GR
wire [31:0] prev_forwarding_data = func_forwarding_rewrite(
iPREVIOUS_SOURCE_IMM,
iPREVIOUS_SOURCE_POINTER,
iPREVIOUS_SOURCE_SYSREG,
iPREVIOUS_SOURCE_DATA,
iPREV_WB_GR_VALID,
iPREV_WB_GR_DEST_SYSREG,
iPREV_WB_SPR_VALID,
iPREV_WB_FRCR_VALID,
iPREV_WB_GR_DEST,
iPREV_WB_SPR_DATA,
iPREV_WB_FRCR_DATA,
iPREV_WB_GR_DATA
);
wire [31:0] cuur_forwarding_data = func_forwarding_rewrite(
iPREVIOUS_SOURCE_IMM,
iPREVIOUS_SOURCE_POINTER,
iPREVIOUS_SOURCE_SYSREG,
prev_forwarding_data,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_SPR_VALID,
iWR_FRCR_VALID,
iWB_GR_DEST,
iWB_SPR_DATA,
iWR_FRCR_DATA,
iWB_GR_DATA
);
//SPR
wire [31:0] cuur_forwarding_spr = func_forwarding_reqrite_spr(
iPREV_WB_SPR_DATA,
iWB_SPR_VALID,
iWB_SPR_DATA
);
//PDTR
wire [31:0] prev_forwarding_pdtr = func_forwarding_rewrite_sysreg(
`SYSREG_PDTR,
iPREVIOUS_SOURCE_PDTR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_pdtr = func_forwarding_rewrite_sysreg(
`SYSREG_PDTR,
prev_forwarding_pdtr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//KPDTR
wire [31:0] prev_forwarding_kpdtr = func_forwarding_rewrite_sysreg(
`SYSREG_KPDTR,
iPREVIOUS_SOURCE_KPDTR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_kpdtr = func_forwarding_rewrite_sysreg(
`SYSREG_KPDTR,
prev_forwarding_kpdtr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//TIDR
wire [31:0] prev_forwarding_tidr = func_forwarding_rewrite_sysreg(
`SYSREG_TIDR,
iPREVIOUS_SOURCE_TIDR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_tidr = func_forwarding_rewrite_sysreg(
`SYSREG_TIDR,
prev_forwarding_tidr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//PSR
wire [31:0] prev_forwarding_psr = func_forwarding_rewrite_sysreg(
`SYSREG_PSR,
iPREVIOUS_SOURCE_PSR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_psr = func_forwarding_rewrite_sysreg(
`SYSREG_PSR,
prev_forwarding_psr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
assign oNEXT_SOURCE_DATA = cuur_forwarding_data;
assign oNEXT_SOURCE_SPR = cuur_forwarding_spr;
assign oNEXT_SOURCE_PDTR = cuur_forwarding_pdtr;
assign oNEXT_SOURCE_KPDTR = cuur_forwarding_kpdtr;
assign oNEXT_SOURCE_TIDR = cuur_forwarding_tidr;
assign oNEXT_SOURCE_PSR = cuur_forwarding_psr;
endmodule
`default_nettype wire
|
(** * PE: Partial Evaluation *)
(* $Date: 2011-02-21 11:20:32 -0500 (Mon, 21 Feb 2011) $ *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
[[
X ::= ANum 3; Y ::= APlus (AId X) (ANum 1)
]]
to
[[
X ::= ANum 3; Y ::= ANum 4
]]
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
[[
X ::= ANum 3; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
]]
to
[[
X ::= ANum 3; Y ::= AMinus (ANum 4) (AId Y)
]]
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
[[
compare V V' SCase
]]
means to reason by cases whether [beq_id V V'] is [true] or
[false]. In the case where [beq_id V V' = true], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (beq_id i j) as [|]_eqn:H;
[ Case_aux c "equal"; symmetry in H; apply beq_id_eq in H; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
true = existsb (beq_id V) (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
[[
X ::= ANum 3; Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
to just
[[
Y ::= AMinus (ANum 3) (AId Y); X ::= ANum 4
]]
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
[[
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
]]
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
[[
X ::= ANum 3; Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
to
[[
Y ::= AMinus (AId X) (AId Y); X ::= ANum 4
]]
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3),(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update. rewrite beq_id_sym.
compare V0 V Case; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
[[
c1 / st || c1' / st'
]]
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
[[
(X ::= ANum 3 ; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
]]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (beq_id V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
replace (beq_id V0 V) with (beq_id V V0) by apply beq_id_sym.
destruct (beq_id V V0); reflexivity.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite HeqVV'. reflexivity.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl. rewrite beq_id_sym.
compare V V0 Case.
Case "equal". reflexivity.
Case "not equal". rewrite pe_remove_correct. rewrite HeqVV0. reflexivity.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (beq_id V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
[[
X ::= ANum 3;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
]]
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
[[
SKIP;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;
SKIP;
Y ::= ANum 4
ELSE SKIP FI
]]
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Lemma existsb_app: forall X (f:X->bool) l1 l2,
existsb f (l1 ++ l2) = orb (existsb f l1) (existsb f l2).
Proof. intros X f l1 l2. induction l1. reflexivity.
simpl. rewrite IHl1. rewrite orb_assoc. reflexivity. Qed.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
true = existsb (beq_id V) (map (@fst _ _) pe_st1 ++
map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
rewrite existsb_app. symmetry. apply orb_true_intro.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. symmetry. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. symmetry. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => negb (beq_id x y)) (pe_unique l)
end.
Lemma existsb_beq_id_filter: forall V f l,
existsb (beq_id V) (filter f l) = andb (existsb (beq_id V) l) (f V).
Proof. intros V f l. induction l as [| h l].
Case "[]". reflexivity.
Case "h::l". simpl. remember (f h) as fh. destruct fh.
SCase "true = f h". simpl. rewrite IHl. compare V h SSCase.
rewrite <- Heqfh. reflexivity. reflexivity.
SCase "false = f h". rewrite IHl. compare V h SSCase.
rewrite <- Heqfh. rewrite !andb_false_r. reflexivity. reflexivity.
Qed.
Theorem pe_unique_correct: forall l x,
existsb (beq_id x) l = existsb (beq_id x) (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. compare x h Case.
Case "equal". reflexivity.
Case "not equal".
rewrite -> existsb_beq_id_filter, <- IHt, -> beq_id_sym, -> Heqxh,
-> andb_true_r. reflexivity. Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
false = existsb (beq_id V) (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct, -> existsb_beq_id_filter.
split; intros Heq.
Case "->".
symmetry. apply andb_false_intro2. unfold pe_disagree_at. rewrite Heq.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl. reflexivity.
reflexivity.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
rewrite -> andb_true_r, <- pe_disagree_domain in Heq.
inversion Heq.
apply Heqdisagree.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite beq_nat_eq with n1 n2. reflexivity.
rewrite <- negb_involutive. rewrite Hagree. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if existsb (beq_id V) ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
replace (beq_id V' V) with (beq_id V V') by apply beq_id_sym.
destruct (beq_id V V'); destruct (existsb (beq_id V) ids); reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
remember (existsb (beq_id V) (pe_compare pe_st1 pe_st2)) as b.
destruct b. reflexivity.
apply pe_compare_correct in Heqb. apply Heqb. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => match existsb (beq_id V) ids, pe_lookup pe_st V with
| true, Some n => n
| _, _ => st V
end.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (existsb (beq_id V)); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. rewrite beq_id_sym. compare V0 V SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". reflexivity.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V0 V SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (existsb (beq_id V0) ids); reflexivity.
SSCase "not equal". reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ; c2) / pe_st || (c1' ; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP; SKIP); (SKIP; Y ::= ANum 4)
ELSE SKIP; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
[[
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END
]]
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
[[
Y ::= AMult (AId Y) (AId Y);
Y ::= AMult (AId Y) (AId Y);
Y ::= AMult (AId Y) (AId Y)
]]
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
[[
X ::= ANum 0;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);
X ::= AMinus (ANum 1) (AId X)
END
]]
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
[[
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1; EXIT
FI
END;
X ::= ANum 0
]]
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ; c2) / pe_st || (c1' ; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1'; c2'; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1'; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Tactic Notation "step" ident(i) :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);
X ::= AMinus (AId X) (ANum 1)); SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3; square_loop) / []
|| (SKIP;
(Y ::= AMult (AId Y) (AId Y); SKIP);
(Y ::= AMult (AId Y) (AId Y); SKIP);
(Y ::= AMult (AId Y) (AId Y); SKIP);
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3; subtract_slowly) / []
|| (SKIP;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP; X ::= AMinus (AId X) (ANum 1));
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP; X ::= AMinus (AId X) (ANum 1)); SKIP
END;
SKIP; Z ::= ANum 0
ELSE SKIP; Z ::= ANum 1 FI; SKIP
ELSE SKIP; Z ::= ANum 2 FI; SKIP
ELSE SKIP; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. reflexivity. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1'; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Implicit Arguments Goto [[Label]].
Implicit Arguments If [[Label]].
Implicit Arguments Assign [[Label]].
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_LP_V
`define SKY130_FD_SC_LP__NOR2B_LP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_lp (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_lp (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_LP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tapvpwrvgnd.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__tapvpwrvgnd dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_TB_V
|
`timescale 1ns / 1ps
module Coprocessor(
clk,
rst,
c0_rd_addr,
c0_wr_addr,
c0_w_data,
pc_i,
InTcause,
c0_reg_we,
WriteEPC,
WriteCause,
c0_r_data,
epc_o,
WriteInt,
Int_en_i,
Int_en_o
);
// ================ IO interface
input clk, rst;
input wire [31: 0] c0_w_data, pc_i;
input wire [ 4: 0] c0_rd_addr, c0_wr_addr;
input wire [ 4: 0] InTcause;
input wire c0_reg_we, WriteEPC, WriteCause,
WriteInt, Int_en_i;
output wire [31: 0] c0_r_data, epc_o, Int_en_o;
integer i = 0;
reg [31: 0] c0reg[11:14];
// 11 Enable, 12 Base, 13 Cause, 14 Epc
assign c0_r_data = c0reg[c0_rd_addr];
assign epc_o = c0reg[14];
assign Int_en_o = c0reg[11];
initial begin
for(i = 11; i <= 14; i = i + 1)
c0reg[i] <= 32'b0;
end
always @(posedge clk ) begin
if (rst) begin
// reset
for(i = 11; i <= 14; i = i + 1)
c0reg[i] <= 32'b0;
end
else begin
if (c0_reg_we == 1)
c0reg[c0_wr_addr] <= c0_w_data;
if (WriteInt == 1)
c0reg[11][0] <= Int_en_i;
if (WriteCause == 1)
c0reg[13] <= InTcause;
if (WriteEPC == 1)
c0reg[14] <= pc_i;
end
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module dsp_t1_20x18x64 (
input [19:0] a_i,
input [17:0] b_i,
input [ 3:0] acc_fir_i,
output [37:0] z_o,
output [17:0] dly_b_o,
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i
);
parameter [19:0] COEFF_0 = 20'd0;
parameter [19:0] COEFF_1 = 20'd0;
parameter [19:0] COEFF_2 = 20'd0;
parameter [19:0] COEFF_3 = 20'd0;
QL_DSP2 # (
.COEFF_0 (COEFF_0),
.COEFF_1 (COEFF_1),
.COEFF_2 (COEFF_2),
.COEFF_3 (COEFF_3)
) _TECHMAP_REPLACE_ (
.a (a_i),
.b (b_i),
.acc_fir (acc_fir_i),
.z (z_o),
.dly_b (dly_b_o),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b0), // No fracturation
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
endmodule
module dsp_t1_10x9x32 (
input [ 9:0] a_i,
input [ 8:0] b_i,
input [ 1:0] acc_fir_i,
output [18:0] z_o,
output [ 8:0] dly_b_o,
(* clkbuf_sink *)
input clock_i,
input reset_i,
input [2:0] feedback_i,
input load_acc_i,
input unsigned_a_i,
input unsigned_b_i,
input [2:0] output_select_i,
input saturate_enable_i,
input [5:0] shift_right_i,
input round_i,
input subtract_i,
input register_inputs_i,
input [ 9:0] coeff_0_i,
input [ 9:0] coeff_1_i,
input [ 9:0] coeff_2_i,
input [ 9:0] coeff_3_i
);
parameter [9:0] COEFF_0 = 10'd0;
parameter [9:0] COEFF_1 = 10'd0;
parameter [9:0] COEFF_2 = 10'd0;
parameter [9:0] COEFF_3 = 10'd0;
wire [37:0] z;
wire [17:0] dly_b;
QL_DSP2 # (
.COEFF_0 ({10'd0, COEFF_0}),
.COEFF_1 ({10'd0, COEFF_1}),
.COEFF_2 ({10'd0, COEFF_2}),
.COEFF_3 ({10'd0, COEFF_3})
) _TECHMAP_REPLACE_ (
.a ({10'd0, a_i}),
.b ({ 9'd0, b_i}),
.acc_fir ({ 2'd0, acc_fir_i}),
.z (z),
.dly_b (dly_b),
.clk (clock_i),
.reset (reset_i),
.feedback (feedback_i),
.load_acc (load_acc_i),
.unsigned_a (unsigned_a_i),
.unsigned_b (unsigned_b_i),
.f_mode (1'b1), // Enable fractuation, Use the lower half
.output_select (output_select_i),
.saturate_enable (saturate_enable_i),
.shift_right (shift_right_i),
.round (round_i),
.subtract (subtract_i),
.register_inputs (register_inputs_i)
);
assign z_o = z[18:0];
assign dly_b_o = dly_b_o[8:0];
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_alu_result,
E_mem_byte_en,
E_st_data,
E_valid,
F_pcb,
F_valid,
R_ctrl_exception,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_bstatus_reg,
W_cmp_result,
W_estatus_reg,
W_ienable_reg,
W_ipending_reg,
W_mem_baddr,
W_rf_wr_data,
W_status_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input [ 31: 0] E_alu_result;
input [ 3: 0] E_mem_byte_en;
input [ 31: 0] E_st_data;
input E_valid;
input [ 16: 0] F_pcb;
input F_valid;
input R_ctrl_exception;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_bstatus_reg;
input W_cmp_result;
input W_estatus_reg;
input [ 31: 0] W_ienable_reg;
input [ 31: 0] W_ipending_reg;
input [ 18: 0] W_mem_baddr;
input [ 31: 0] W_rf_wr_data;
input W_status_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 18: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 16: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_test_bench/W_wr_data is 'x'\n", $time);
end
end
reg [31:0] trace_handle; // for $fopen
initial
begin
trace_handle = $fopen("ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst.tr");
$fwrite(trace_handle, "version 3\nnumThreads 1\n");
end
always @(posedge clk)
begin
if ((~reset_n || (W_valid)) && ~test_has_ended)
$fwrite(trace_handle, "%0d ns: %0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h,%0h\n", $time, ~reset_n, F_pcb, 0, D_op_intr, D_op_hbreak, D_iw, ~(D_op_intr | D_op_hbreak), R_wr_dst_reg, R_dst_regnum, 0, W_rf_wr_data, W_mem_baddr, E_st_data, E_mem_byte_en, W_cmp_result, E_alu_result, W_status_reg, W_estatus_reg, W_bstatus_reg, W_ienable_reg, W_ipending_reg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, R_ctrl_exception, 0, 0, 0, 0);
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "encoder_pl.v"
`include "decoder_pl.v"
`include "pipelinedec.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipeline();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUTs
// Output of stage 1
wire [11:0] c;
// Output of stage 2
wire [11:0] cx;
// Output of stage 3
wire [7:0] q;
//wire [10:0] rb;
// Declare "reg" signals: inputs to the DUTs
// 1st stage
reg [7:0] b;
reg [7:0] r_b;
reg [11:0] e;
reg [11:0] r_e;
// 2nd stage
reg [11:0] r_c;
reg [11:0] rr_e;
reg [7:0] rr_b;
//reg [15:1] err;
// 3rd stage
//reg [11:0] cx;
//reg [10:0] qx;
reg [11:0] r_qx;
reg [7:0] rb;
reg clk,reset;
reg [11:0] e2;
encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_b,c);
decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_qx,q);
large_xor xr (
// instance_name(signal name),
// Signal name can be the same as the instance name
r_c,rr_e,cx);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#10 clk = 0;
#10 clk = 1;
end
// Create the register (flip-flop) for the initial/1st stage
always@(posedge clk)
begin
if(reset)
begin
r_b<=0;
r_e<=0;
end
else
begin
r_e<=e;
r_b<=b;
end
end
// Create the register (flip-flop) for the 2nd stage
always@(posedge clk)
begin
if(reset)
begin
r_c<=0;
rr_e<=0;
rr_b<=0;
end
else
begin
r_c<=c;
rr_e<=r_e;
rr_b<=r_b;
end
end
// Create the register (flip-flop) for the 3rd stage
always@(posedge clk)
begin
if(reset)
begin
rb<=0;
end
else
begin
r_qx<=cx;
rb<=rr_b;
e2<=rr_e;
end
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
reset=1;
#20;
reset=0;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000100000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000100000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00010000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#20;
b = $random;
e = 11'b00000000000;
$display(q, "<< Displaying q >>");
$display(rb, "<< Displaying rb >>");
#300;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLL (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Bidirectional I/O Buffer with Offset Calibration and VREF Tuning
// /___/ /\ Filename : IOBUFE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUFE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer DRIVE = 12,
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SIM_DEVICE = "ULTRASCALE",
parameter integer SIM_INPUT_BUFFER_OFFSET = 0,
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
inout IO,
input DCITERMDISABLE,
input I,
input IBUFDISABLE,
input [3:0] OSC,
input OSC_EN,
input T,
input VREF
);
// define constants
localparam MODULE_NAME = "IOBUFE3";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam SIM_DEVICE_ULTRASCALE = 0;
localparam SIM_DEVICE_ULTRASCALE_PLUS = 1;
localparam SIM_DEVICE_VERSAL_AI_CORE = 2;
localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 3;
localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 4;
localparam SIM_DEVICE_VERSAL_AI_EDGE = 5;
localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 6;
localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 7;
localparam SIM_DEVICE_VERSAL_AI_RF = 8;
localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 9;
localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 10;
localparam SIM_DEVICE_VERSAL_HBM = 11;
localparam SIM_DEVICE_VERSAL_HBM_ES1 = 12;
localparam SIM_DEVICE_VERSAL_HBM_ES2 = 13;
localparam SIM_DEVICE_VERSAL_PREMIUM = 14;
localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 15;
localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 16;
localparam SIM_DEVICE_VERSAL_PRIME = 17;
localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 18;
localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 19;
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [4:0] DRIVE_REG = DRIVE;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam integer SIM_INPUT_BUFFER_OFFSET_REG = SIM_INPUT_BUFFER_OFFSET;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
localparam [144:1] SIM_DEVICE_REG = SIM_DEVICE;
wire [4:0] DRIVE_BIN;
wire IBUF_LOW_PWR_BIN;
wire [4:0] SIM_DEVICE_BIN;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire O_out;
reg O_OSC_in;
wire O_delay;
wire DCITERMDISABLE_in;
wire IBUFDISABLE_in;
wire I_in;
wire IO_in;
wire IO_out;
wire OSC_EN_in;
wire T_in;
wire VREF_in;
wire [3:0] OSC_in;
wire DCITERMDISABLE_delay;
wire IBUFDISABLE_delay;
wire I_delay;
wire OSC_EN_delay;
wire T_delay;
wire IO_delay_O;
wire IO_delay_I;
wire VREF_delay;
wire [3:0] OSC_delay;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) DCITERMDISABLE_delay = DCITERMDISABLE;
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) I_delay = I;
assign #(in_delay) IO_delay_I = IO;
assign #(in_delay) IO = IO_delay_O;
assign #(in_delay) OSC_EN_delay = OSC_EN;
assign #(in_delay) OSC_delay = OSC;
assign #(in_delay) T_delay = T;
assign #(in_delay) VREF_delay = VREF;
assign O_delay = O_out;
assign IO_delay_O = IO_out;
assign DCITERMDISABLE_in = DCITERMDISABLE_delay;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign I_in = I_delay;
assign IO_in = IO_delay_I;
assign OSC_EN_in = OSC_EN_delay;
assign OSC_in = OSC_delay;
assign T_in = T_delay;
assign VREF_in = VREF_delay;
wire ts;
integer OSC_int = 0;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T_in);
bufif0 T1 (IO_out, I_in, ts);
assign DRIVE_BIN = DRIVE_REG;
assign IBUF_LOW_PWR_BIN =
(IBUF_LOW_PWR_REG == "TRUE") ? IBUF_LOW_PWR_TRUE :
(IBUF_LOW_PWR_REG == "FALSE") ? IBUF_LOW_PWR_FALSE :
IBUF_LOW_PWR_TRUE;
assign SIM_DEVICE_BIN =
(SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
(SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 :
(SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM :
(SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 :
(SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 :
SIM_DEVICE_ULTRASCALE;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DRIVE_REG < 2) || (DRIVE_REG > 24))) begin
$display("Error: [Unisim %s-101] DRIVE attribute is set to %d. Legal values for this attribute are 2 to 24. Instance: %m", MODULE_NAME, DRIVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_INPUT_BUFFER_OFFSET_REG < -50) || (SIM_INPUT_BUFFER_OFFSET_REG > 50))) begin
$display("Error: [Unisim %s-104] SIM_INPUT_BUFFER_OFFSET attribute is set to %d. Legal values for this attribute are -50 to 50. Instance: %m", MODULE_NAME, SIM_INPUT_BUFFER_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-102] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
( (SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE_REG != "VERSAL_HBM") &&
(SIM_DEVICE_REG != "VERSAL_HBM_ES1") &&
(SIM_DEVICE_REG != "VERSAL_HBM_ES2") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE_REG != "VERSAL_PRIME") &&
(SIM_DEVICE_REG != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin
$display("Error: [Unisim %s-106] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
// begin behavioral model
wire not_t_or_ibufdisable;
wire versal_or_later;
wire OSC_EN_in_muxed;
wire [3:0] OSC_in_muxed;
assign versal_or_later = ( SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE ||
SIM_DEVICE_BIN == SIM_DEVICE_ULTRASCALE_PLUS ) ? 1'b0 : 1'b1;
assign OSC_in_muxed = versal_or_later ? 4'd0 : OSC_in;
assign OSC_EN_in_muxed = versal_or_later ? 1'b0 : OSC_EN_in;
initial begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int)< 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= 1'bx;
end
assign not_t_or_ibufdisable = ~T_in || IBUFDISABLE_in;
generate
case (USE_IBUFDISABLE_REG)
"TRUE" : begin
assign O_out = (not_t_or_ibufdisable == 0)? (OSC_EN_in_muxed) ? O_OSC_in : IO_in : (not_t_or_ibufdisable == 1 && OSC_EN_in_muxed != 1)? 1'b0 : 1'bx;
end
"FALSE" : begin
assign O_out = (OSC_EN_in_muxed) ? O_OSC_in : IO_in;
end
endcase
endgenerate
always @ (OSC_in_muxed or OSC_EN_in_muxed) begin
OSC_int = OSC_in_muxed[2:0] * 5;
if (OSC_in_muxed[3] == 1'b0 )
OSC_int = -1*OSC_int;
if(OSC_EN_in_muxed == 1'b1) begin
if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) < 0)
O_OSC_in <= 1'b0;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) > 0)
O_OSC_in <= 1'b1;
else if ((SIM_INPUT_BUFFER_OFFSET_REG - OSC_int) == 0)
O_OSC_in <= ~O_OSC_in;
end
end
// end behavioral model
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_TB_V
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(** In this chapter we continue our development of basic
concepts of functional programming. The critical new ideas are
_polymorphism_ (abstracting functions over the types of the data
they manipulate) and _higher-order functions_ (treating functions
as data).
*)
Require Export Lists.
Set Asymmetric Patterns.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** For the last couple of chapters, we've been working just
with lists of numbers. Obviously, interesting programs also need
to be able to manipulate lists with elements from other types --
lists of strings, lists of booleans, lists of lists, etc. We
_could_ just define a new inductive datatype for each of these,
for example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** *** *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a _polymorphic
list_ datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** The "[forall X]" in these types can be read as an additional
argument to the constructors that determines the expected types of
the arguments that follow. When [nil] and [cons] are used, these
arguments are supplied in the same way as the others. For
example, the list containing [2] and [1] is written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
(** *** *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: Coq already knows that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More precisely, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** *** *)
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
Module MumbleBaz.
(** **** Exercise: 2 stars (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)]
- [d mumble (b a 5)]
- [d bool (b a 5)]
- [e bool true]
- [e mumble (b c 0)]
- [e bool (b c 0)]
- [c]
+ [d mumble (b a 5)]
+ [d bool (b a 5)]
+ [e bool true]
+ [e mumble (b c 0)]
*)
(** [] *)
(** **** Exercise: 2 stars (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
Zero. No base case :(
*)
(** [] *)
End MumbleBaz.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
(* ===> forall X : Type, list X -> list X -> list X *)
Check app.
(* ===> forall X : Type, list X -> list X -> list X *)
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** In fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. The [Arguments] directive
specifies the name of the function or constructor, and then lists
its argument names, with curly braces around any arguments to be
treated as implicit.
*)
Arguments nil {X}.
Arguments cons {X} _ _. (* use underscore for argument position that has no name *)
Arguments length {X} l.
Arguments app {X} l1 l2.
Arguments rev {X} l.
Arguments snoc {X} l v.
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** *** *)
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length'']; indeed, it is invalid to provide
one.) We will use this style whenever possible, although we will
continue to use use explicit [Argument] declarations for
[Inductive] constructors. *)
(** *** *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, suppose we
write this: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** *** *)
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x ; .. ; y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1; 2; 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat {X : Type} (n : X) (count : nat) : list X :=
match count with
| O => nil
| S count' => n :: repeat n count'
end.
Example test_repeat1:
repeat true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros X v s. induction s as [| h s'].
Case "s = []".
reflexivity.
Case "s = h :: s'".
simpl. rewrite IHs'. reflexivity. Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros X l. induction l as [| h l'].
Case "l = []".
reflexivity.
Case "l = h :: l'".
simpl. rewrite rev_snoc. rewrite IHl'. reflexivity. Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros X l1 l2 v. induction l1 as [| h1 l1'].
Case "l1 = []".
reflexivity.
Case "l1 = h1 :: l1'".
simpl. rewrite IHl1'. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Arguments pair {X} {Y} _ _.
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** *** *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval compute in (combine [1;2] [false;false;true;true]).
print? []
*)
(** **** Exercise: 2 stars (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split
{X Y : Type} (l : list (X*Y))
: (list X) * (list Y) :=
match l with
| [] => ([], [])
| (x,y) :: l' => match split l' with
| (l1', l2') => (x :: l1', y :: l2')
end
end.
Example test_split:
split [(1,false);(2,false)] = ([1;2],[false;false]).
Proof.
reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Arguments Some {X} _.
Arguments None {X}.
(** *** *)
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4;5;6;7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1];[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| h :: _ => Some h
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1;2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1];[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, advanced (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z := f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros X Y Z f p.
destruct p. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1;2;3;4] = [2;4].
Proof. reflexivity. Qed.
(** *** *)
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** *** *)
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1;0;3;1;4;5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0;2;4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1; 2]; [3]; [4]; [5;6;7]; []; [8] ]
= [ [3]; [4]; [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] that takes a list of natural numbers as input
and returns a list of just those that are even and greater than
7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (blt_nat 7 n) (evenb n)) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1;2;6;9;10;3;12;8] = [10;12;8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5;2;6;19;129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1;2;3;4;5] = ([1;3;5], [2;4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5;9;0] = ([], [5;9;0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** *** *)
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2;0;2] = [5;3;5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2;1;2;5] = [false;true;false;true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n;oddb n]) [2;1;2;5]
= [[true;false];[false;true];[true;false];[false;true]].
Proof. reflexivity. Qed.
(** ** Map for options *)
(** **** Exercise: 3 stars (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Lemma map_snoc : forall (X Y : Type) (f : X -> Y) (l : list X) (n : X),
map f (snoc l n) = snoc (map f l) (f n).
Proof.
intros X Y f l n. induction l as [| h l'].
Case "l = []".
reflexivity.
Case "l = h :: l'".
simpl. rewrite IHl'. reflexivity. Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros X Y f l. induction l as [| h l'].
Case "l = []".
reflexivity.
Case "l = h :: l'".
simpl. rewrite <- IHl'. rewrite map_snoc. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n;n+1;n+2]) [1;5;10]
= [1; 2; 3; 5; 6; 7; 10; 11; 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: l' => f h ++ flat_map f l'
end.
Example test_flat_map1:
flat_map (fun n => [n;n;n]) [1;5;4]
= [1; 1; 1; 5; 5; 5; 4; 4; 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. (This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards.) [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** *** *)
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1;2;3;4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1;2;3;4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold andb).
(* ===> fold andb : list bool -> bool -> bool *)
Example fold_example1 : fold mult [1;2;3;4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true;true;false;true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1];[];[2;3];[4]] [] = [1;2;3;4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, advanced (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
(** *** *)
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** *** *)
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
reflexivity. Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the next chapter. For now, though, let's introduce just
one very useful tactic that will also help us with proving
properties of some of the other functions we have introduced in
this chapter. *)
(* ###################################################### *)
(* ###################################################### *)
(** * The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Abort.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros X x1 x2 k1 k2 f Hf Hbeq.
unfold override. rewrite Hbeq. rewrite Hf. reflexivity. Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternative definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4;7;0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
unfold fold_length.
intros X l. induction l as [| h l'].
Case "l = []".
reflexivity.
Case "l = h :: l'".
simpl. rewrite IHl'. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x k => f x :: k) l [].
(** Write down a theorem [fold_map_correct] in Coq stating that
[fold_map] is correct, and prove it. *)
Theorem fold_map_correct : forall (X Y : Type) (f : X -> Y) (l : list X),
fold_map f l = map f l.
Proof.
unfold fold_map.
intros X Y f l. induction l as [| h l'].
Case "l = []".
reflexivity.
Case "l = h :: l'".
simpl. rewrite IHl'. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X n l = None.
- Induction over l, generalizing n
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (church_numerals) *)
Module Church.
(** In this exercise, we will explore an alternative way of defining
natural numbers, using the so-called _Church numerals_, named
after mathematician Alonzo Church. We can represent a natural
number [n] as a function that takes a function [f] as a parameter
and returns [f] iterated [n] times. More formally, *)
Definition nat := forall X : Type, (X -> X) -> X -> X.
(** Let's see how to write some numbers with this notation. Any
function [f] iterated once shouldn't change. Thus, *)
Definition one : nat :=
fun (X : Type) (f : X -> X) (x : X) => f x.
(** [two] should apply [f] twice to its argument: *)
Definition two : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (f x).
(** [zero] is somewhat trickier: how can we apply a function zero
times? The answer is simple: just leave the argument untouched. *)
Definition zero : nat :=
fun (X : Type) (f : X -> X) (x : X) => x.
(** More generally, a number [n] will be written as [fun X f x => f (f
... (f x) ...)], with [n] occurrences of [f]. Notice in particular
how the [doit3times] function we've defined previously is actually
just the representation of [3]. *)
Definition three : nat := @doit3times.
(** Complete the definitions of the following functions. Make sure
that the corresponding unit tests pass by proving them with
[reflexivity]. *)
(** Successor of a natural number *)
Definition succ (n : nat) : nat :=
fun (X : Type) (f : X -> X) (x : X) => f (n X f x).
Example succ_1 : succ zero = one.
Proof. reflexivity. Qed.
Example succ_2 : succ one = two.
Proof. reflexivity. Qed.
Example succ_3 : succ two = three.
Proof. reflexivity. Qed.
(** Addition of two natural numbers *)
Definition plus (n m : nat) : nat :=
fun (X : Type) (f : X -> X) (x : X) => n X f (m X f x).
Example plus_1 : plus zero one = one.
Proof. reflexivity. Qed.
Example plus_2 : plus two three = plus three two.
Proof. reflexivity. Qed.
Example plus_3 :
plus (plus two two) three = plus one (plus three three).
Proof. reflexivity. Qed.
(** Multiplication *)
Definition mult (n m : nat) : nat :=
fun (X : Type) (f : X -> X) => n X (m X f).
Example mult_1 : mult one one = one.
Proof. reflexivity. Qed.
Example mult_2 : mult zero (plus three three) = zero.
Proof. reflexivity. Qed.
Example mult_3 : mult two three = plus three three.
Proof. reflexivity. Qed.
(** Exponentiation *)
(** Hint: Polymorphism plays a crucial role here. However, choosing
the right type to iterate over can be tricky. If you hit a
"Universe inconsistency" error, try iterating over a different
type: [nat] itself is usually problematic. *)
Definition exp (n m : nat) : nat :=
fun (X : Type) => m (X -> X) (n X).
Example exp_1 : exp two two = plus two two.
Proof. reflexivity. Qed.
Example exp_2 : exp three two = plus (mult two (mult two two)) one.
Proof. reflexivity. Qed.
Example exp_3 : exp three zero = one.
Proof. reflexivity. Qed.
End Church.
(** [] *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
(** $Done: 2016-03-11 14:59:12 -0500 (Fri, 11 Mar 2016) $ *)
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: three_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module three_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/three_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/three_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/three_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_BEHAVIORAL_PP_V
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: STEUER_MISC.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 21 January 2016
//
// Copyright (C) 2016 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. OPDEC_REG Central Instruction Register
// 2. PROG_COUNTER Program Counters
// 3. REG_LIST Register List Evaluation
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. OPDEC_REG Central Instruction Register
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,
OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);
input BCLK,BRESET;
input NEW; // a program jump took place
input [3:0] ACC_STAT; // ICACHE signals data is available or Abort
input PROT_ERROR; // comes direct from ICACHE
input [1:0] ALSB; // lower addressbits of access address to ICACHE
input [2:0] USED; // Message from DECODER how many bytes were used
input [31:0] IC_DIN; // ICACHE Data
input IC_INIT,DC_INIT,Y_INIT; // Initialising or new setting is running
input RESTART; // "Break" of Instruction Pipeline - set up new i.e. after load of PSR
input STOP_IC; // For LMR and CINV
output [55:0] OPREG; // this is the Central Opcode Decode Register, length = 7 bytes
output [2:0] ANZ_VAL;
output IC_READ;
output NEW_PC;
output NEXT_ADR;
output DATA_HOLD;
output ABORT;
output [2:0] IC_TEX;
output INIT_DONE;
reg [55:0] OPREG;
reg [2:0] ANZ_VAL;
reg IC_READ;
reg ABORT;
reg abort_flag;
reg [2:0] IC_TEX;
reg [55:0] data_to_ri;
reg old_init;
reg pre_new;
reg new_reg;
reg nseq_flag;
reg stop_init;
wire [2:0] new_anz;
wire new_restart;
wire acc_err,acc_ok,acc_ende;
// ++++++++++++++++++++ Evaluation of ACC_STAT from Instructioncache ++++++++++++++++++++++++++++
// ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
assign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;
assign acc_ok = ACC_STAT[0];
always @(posedge BCLK or negedge BRESET) // is kept until DECODER really needs the data !
if (!BRESET) ABORT <= 1'b0;
else ABORT <= (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);
always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};
always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok); // for MMU Status Register
always @(posedge BCLK) abort_flag <= acc_err;
assign acc_ende = ~IC_READ | acc_ok | abort_flag; // abort_flag one cycle later is ok ! If no ICache access always end
assign new_restart = NEW | RESTART; // They are pulses
// Branch work out : NEW/RESTART notice if access still not ended
always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);
assign NEW_PC = (new_restart | pre_new) & acc_ende; // At the end of access geenerate new address !
// There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register
always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);
always @(USED or OPREG) // Data first shift to the right
case (USED)
3'b000 : data_to_ri = OPREG;
3'b001 : data_to_ri = { 8'hxx, OPREG[55:8]};
3'b010 : data_to_ri = {16'hxxxx,OPREG[55:16]};
3'b011 : data_to_ri = {24'hxx_xxxx,OPREG[55:24]};
3'b100 : data_to_ri = {32'hxxxx_xxxx,OPREG[55:32]};
3'b101 : data_to_ri = {40'hxx_xxxx_xxxx,OPREG[55:40]};
3'b110 : data_to_ri = {48'hxxxx_xxxx_xxxx,OPREG[55:48]};
3'b111 : data_to_ri = 56'hxx_xxxx_xxxx_xxxx;
endcase
assign new_anz = ANZ_VAL - USED;
always @(posedge BCLK)
casex ({new_reg,acc_ok,ALSB,new_anz})
7'b1_100_xxx : OPREG <= {24'hxx_xxxx,IC_DIN};
7'b1_101_xxx : OPREG <= {32'hxxxx_xxxx,IC_DIN[31:8]};
7'b1_110_xxx : OPREG <= {40'hxx_xxxx_xxxx,IC_DIN[31:16]};
7'b1_111_xxx : OPREG <= {48'hxxxx_xxxx_xxxx,IC_DIN[31:24]};
7'b0_0xx_xxx : OPREG <= data_to_ri;
7'b0_1xx_000 : OPREG <= {24'hxx_xxxx,IC_DIN};
7'b0_1xx_001 : OPREG <= { 16'hxxxx,IC_DIN, data_to_ri[7:0]};
7'b0_1xx_010 : OPREG <= { 8'hxx,IC_DIN,data_to_ri[15:0]};
7'b0_1xx_011 : OPREG <= { IC_DIN,data_to_ri[23:0]};
7'b0_1xx_1xx : OPREG <= data_to_ri;
endcase
always @(posedge BCLK or negedge BRESET)
if (!BRESET) ANZ_VAL <= 3'b000;
else
casex ({new_restart,new_reg,acc_ok,new_anz[2]})
4'b1x_x_x : ANZ_VAL <= 3'b000; // hard setting to 0
4'b01_0_x : ANZ_VAL <= 3'b000;
4'b01_1_x : ANZ_VAL <= pre_new ? 3'b000 : 3'b100 - {1'b0,ALSB};
4'b00_0_x : ANZ_VAL <= new_anz;
4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;
4'b00_1_1 : ANZ_VAL <= new_anz;
endcase
assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]); // switches MUX at PC resp. ICACHE
// Instruction CACHE Control : READ is coming after all INITs are done
always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;
assign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) stop_init <= 1'b0;
else stop_init <= stop_init | IC_READ;
// The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !
always @(posedge BCLK or negedge BRESET)
if (!BRESET) IC_READ <= 1'b0;
else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);
// The Opcode-Register can not store the data : keep them in ICACHE at IO-access
assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. PROG_COUNTER Program Counters
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,
ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);
input BCLK,BRESET;
input NEW;
input LOAD_PC;
input NEW_PC;
input NEXT_ADR;
input NEXT_PCA;
input [31:0] DISP;
input [31:0] PC_NEW;
input [2:0] USED;
input USER;
input SAVE_PC;
input FPU_TRAP;
input ADIVAR;
output [31:0] PC_ARCHI; // goes to Datapath
output [31:0] PC_ICACHE;
output [31:0] PC_SAVE; // is the return address
output [1:0] ALSB;
output IC_USER;
reg [31:0] PC_ARCHI;
reg [31:0] pc_adduse;
reg [31:0] pc_ic_reg;
reg [31:0] fpu_trap_pc;
reg IC_USER;
wire [31:0] branch,pc_jump,next_pc,pc_icache_i;
assign PC_SAVE = pc_adduse + {29'h0,USED};
assign branch = PC_ARCHI + DISP;
assign pc_jump = LOAD_PC ? PC_NEW : branch;
assign next_pc = NEW ? pc_jump : PC_SAVE; // Only at NEW is the DISP correct !
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pc_adduse <= 32'h0;
else
pc_adduse <= next_pc;
// The Architectur - PC : Address mode "Programm Memory"-relativ
// no BRESET because NEXT_PCA is immediately valid
always @(posedge BCLK)
if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc; // go back !
else
if (NEXT_PCA) PC_ARCHI <= pc_adduse;
always @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI; // Special storage for PC for FPU Trap
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pc_ic_reg <= 32'h0;
else
pc_ic_reg <= pc_icache_i;
// NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC
// is used to initiate a new access in ICACHE
assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);
// This MUX is extra for LMR IVAR,... and CINV build in
assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};
assign ALSB = pc_ic_reg[1:0]; // for OPDEC_REG
// The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE
always @(posedge BCLK or negedge BRESET)
if (!BRESET) IC_USER <= 1'b0;
else
if (NEW_PC) IC_USER <= USER;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. REG_LIST Register List Evaluation
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);
// Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT
input [7:0] DIN;
input [2:0] IPOS;
input INIT;
output [2:0] OPOS;
output VALID;
reg [7:1] filter;
wire [7:0] mdat_0;
wire [3:0] mdat_1;
wire [1:0] mdat_2;
always @(IPOS or DIN)
case (IPOS)
3'd0 : filter = DIN[7:1];
3'd1 : filter = {DIN[7:2],1'b0};
3'd2 : filter = {DIN[7:3],2'b0};
3'd3 : filter = {DIN[7:4],3'b0};
3'd4 : filter = {DIN[7:5],4'b0};
3'd5 : filter = {DIN[7:6],5'b0};
3'd6 : filter = {DIN[7] ,6'b0};
3'd7 : filter = 7'b0;
endcase
assign mdat_0 = INIT ? DIN : {filter,1'b0};
assign OPOS[2] = (mdat_0[3:0] == 4'h0);
assign mdat_1 = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];
assign OPOS[1] = (mdat_1[1:0] == 2'b00);
assign mdat_2 = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];
assign OPOS[0] = ~mdat_2[0];
assign VALID = (mdat_2 != 2'b00);
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 4. ILL_UNDEF Illegal and Undefined Opcodes Detection
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );
input [23:0] OPREG;
input [2:0] ANZ_VAL;
input [3:1] CFG; // 3=CUSTOM,2=MMU,1=FPU
input USER;
output reg ILL;
output UNDEF;
reg undef_opc;
reg undef_am;
reg undef_im;
wire [2:0] valid;
wire gen12,gen22,gen13,gen23;
wire igen12,igen22,igen13,igen23;
wire lsbes;
parameter udef_amode = 5'b10011; // Undefined Addressing Mode
parameter imode = 5'b10100; // Immediate Addressing Mode
// [2]= minimum 3, [1]= minimum 2, [0]=minimum 1
assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};
assign lsbes = (OPREG[1:0] == 2'b10); // Tag of all 3 Byte opcodes
// +++++++++++++++++++++++++ Detect illegale opcodes +++++++++++++++++++
always @(OPREG or lsbes or valid or USER)
casex ({valid[2:1],OPREG[13:2],lsbes})
15'bx1_xx_x000_1x10_11_0 : ILL = USER; // SPRi/LPRi DCR
15'bx1_xx_x001_xx10_11_0 : ILL = USER; // SPRi/LPRi BPC/DSR
15'bx1_xx_xx10_xx10_11_0 : ILL = USER; // SPRi/LPRi CAR/CFG/PSR
15'bx1_xx_x101_1x10_11_0 : ILL = USER; // SPRi/LPRi USP
15'bx1_xx_x111_0x10_11_0 : ILL = USER; // SPRi/LPRi INTBASE
15'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0]; // BICPSRW,BISPSRW
15'bx1_00_10xx_0000_11_1 : ILL = USER; // SETCFG - Achtung : is coded as 2 Byte Opcode
15'b1x_00_xxxx_0001_11_1 : ILL = USER; // LMR/SMR/RDVAL/WRVAL
15'b1x_10_01xx_0001_11_1 : ILL = USER; // CINV
default : ILL = 1'b0;
endcase
// ++++++++++++++++++++++++ Detect Undefined opcodes +++++++++++++++
always @(OPREG or lsbes or valid or CFG)
casex ({valid,OPREG[13:2],lsbes})
16'bx1x_xx_xxxx_1111_110 : undef_opc = 1'b1; // Format 3 : xxx1
16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1; // Format 3 : 1000
16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 1xxx
16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1; // Format 5 : 01xx
16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1; // Format 6 : 0100
16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1; // Format 6/7 : 1010
16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1]; // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.
16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1]; // Format 12 : FPU Befehle wie POLYf etc.
16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1; // Format 14 : x1xx
16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1; // Format 14 : 1000
16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1; // Format 14 : 101x
16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18]; // Format 14 : LMR/SMR
16'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3]; // Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.
16'b1xx_xx_xxxx_0001_011 : undef_opc = 1'b1; // Format 15.0 - not yet in, requires HW change
16'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1'b1; // Format 15 : rest
16'b1xx_xx_xxxx_1001_011 : undef_opc = 1'b1; // Format 15.4
// completely undefined :
16'bxx1_xx_xxxx_0111_111 : undef_opc = 1'b1; // Format 10
16'bxx1_xx_xxxx_100x_111 : undef_opc = 1'b1; // Format 13/18
16'bxx1_xx_xxxx_x101_111 : undef_opc = 1'b1; // Format 16/17
16'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1'b1; // Format 19
default : undef_opc = 1'b0;
endcase
// 2. Undefined Addressing mode 5'b10011
assign gen12 = (OPREG[15:11] == udef_amode);
assign gen22 = (OPREG[10:6] == udef_amode);
assign gen13 = (OPREG[23:19] == udef_amode);
assign gen23 = (OPREG[18:14] == udef_amode);
always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)
if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23; // nearly all 3 Byte opcodes
else
undef_am = valid[1] & gen12 & (OPREG[1:0] != 2'b10) & ((OPREG[3:2] != 2'b11) & gen22); // all 2 Byte opcodes
// 3. When is Immediate not allowed ?
assign igen12 = (OPREG[15:11] == imode);
assign igen22 = (OPREG[10:6] == imode);
assign igen13 = (OPREG[23:19] == imode);
assign igen23 = (OPREG[18:14] == imode);
always @(*)
casex ({valid[2:1],OPREG[13:2],lsbes})
15'bx1_xxxxxx_x0xx11_0 : undef_im = igen12 & (OPREG[5:4] != 2'b01); // Format 2 : ADDQD,SPR,Scond
15'bx1_xxxxxx_x10111_0 : undef_im = igen12; // Format 2 : ACB,MOVQ
15'bx1_xxxxx0_011111_0 : undef_im = igen12; // Format 3 : CXPD,JUMP,JSR
15'bx1_xxxxxx_xxxxx0_0 : undef_im = igen22; // Format 4
15'bx1_xxxxxx_xxxx01_0 : undef_im = (igen12 & (OPREG[5:4] == 2'b10)) // Format 4 : SRC1 - not ADDR
|(igen22 & (OPREG[5:4] != 2'b00)); // Format 4 : SRC2 - CMP
15'b1x_xxxxxx_x10011_1 : undef_im = igen23; // Format 6+7
15'b1x_xxx0xx_0x1011_1 : undef_im = igen13 | igen23; // Format 8 EXT,CVTP
15'b1x_xxx0xx_101011_1 : undef_im = igen23; // Format 8 : INS
15'b1x_xxx0xx_111011_1 : undef_im = igen13; // Format 8 : CHECK
15'b1x_xxx1xx_101011_1 : undef_im = igen13 | igen23; // Format 8 MOVUS,MOVSU
15'b1x_xxx1xx_011011_1 : undef_im = igen23; // Format 8 : FFS
15'b1x_xxxxxx_001111_1 : undef_im = igen23; // Format 9
15'b1x_xxxxxx_101111_1 : undef_im = igen23 & (OPREG[13:10] != 4'h2); // Format 10 without CMPf
15'b1x_010xxx_111111_1 : undef_im = igen23; // Format 12 SCALB+LOGB
15'b1x_000xxx_000111_1 : undef_im = igen13; // Format 14 RDVAL+WRVAL
15'b1x_0011xx_000111_1 : undef_im = igen13; // Format 14 SMR
default : undef_im = 1'b0;
endcase
// Final Message :
assign UNDEF = undef_opc | undef_am | undef_im;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 5. GRUPPE_2 Decoder and State Machine for GRUPPE_2 Opcodes
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module GRUPPE_2 ( BCLK, PHASE_0, OPREG, PHASE, SRC_1, SRC_2, REGA1, REGA2, IRRW1, IRRW2, ADRD1, ADRD2, EXR12, EXR22,
PHRD1, PHRD2, NXRD1, NXRW2, ACCA, OPERA,
STATE_0, STATE_GROUP_50, STATE_GROUP_60 );
input BCLK,PHASE_0;
input [18:0] OPREG;
input [3:0] PHASE; // nur die 4 LSBs
// Source 1 & 2 Inputs
input [6:0] SRC_1,SRC_2,REGA1,REGA2,IRRW1,IRRW2;
input [18:0] ADRD1,ADRD2,EXR12,EXR22;
input [3:0] PHRD1,PHRD2;
input [3:0] NXRD1,NXRW2;
input [3:0] ACCA; // ACCA = Access type : 0x Register
// [3:2] or [1:0] 10 Memory
// 11 Memory + Index
input [10:0] OPERA;
output [66:0] STATE_0;
output [66:0] STATE_GROUP_50,STATE_GROUP_60;
reg [66:0] STATE_GROUP_50,STATE_GROUP_60;
reg [66:0] STATE_0,state_50,state_53,state_54,state_55,state_58,state_59,state_5A;
reg [4:0] op_code,op_reg_reg;
reg [7:0] phsrc1,phsrc2;
reg [5:0] chkreg;
reg [1:0] bwdreg;
reg tbit_flag,size_dw;
reg inss_flag;
reg ext_tos;
wire [18:0] exoffset,re_wr,rexwr;
wire [10:0] op_kust,op_bwd;
wire [7:0] phchk;
wire [4:0] op_reg;
wire [6:0] src_1l,src_2l;
wire [5:0] dest_2;
wire [3:0] get8b_s,get8b_d;
wire [6:0] rd_reg;
wire [10:0] op_zext;
wire [3:0] imdi;
parameter dont_care = 67'hx_xxxx_xxxx_xxxx_xxxx;
// Address-Field : Size:2 RD WR LDEA FULLACC INDEX:4 SPUPD disp_val:4 POST CLRMSW SRC2SEL:2
parameter addr_nop = 19'h0; // alle Parameter auf 0
parameter disp2ea = 19'bxx_0010_0000_0_0000_0010; // pass DISP
parameter case_op = 19'bxx_0010_1000_0_0000_0001; // SRC1 add to PC_ARCHI
parameter read_byb = 19'b00_1011_11xx_0_0000_0011; // read of SRC2 for Bit opcodes
parameter exr11 = {2'b10 ,4'b1011,4'h0 ,9'h080}; // 2. access External with Mem.-Pointer + 4* Disp
parameter adrcvtp = 19'bxx_0010_0111_0_0000_0000; // for CVTP
parameter addone = 19'bxx_0010_0100_0_0000_0000; // for INDEX : SRC1 + SRC2 , simple Add without Flags
parameter addind = 19'bxx_0010_0100_0_0000_0011; // for INDEX : SRC1 + EA
parameter src_x = 7'hxx;
parameter dest_x = 6'hxx;
parameter imme = {1'b1,6'hxx};
parameter F0 = 7'h20;
parameter F0_h = 7'h21;
parameter w_F0 = 6'h20;
parameter w_F0_h = 6'h21;
parameter temp_l = 6'h3C;
parameter temp_h = 6'h3D; // Second last place for 8B TEMP Register
parameter temp_1 = 6'h3E;
parameter rtmpl = 7'h3C;
parameter rtmph = 7'h3D;
parameter rtmp1 = 7'h3E;
parameter op_mov = {3'bx1x,8'h45};
parameter op_adr = {3'bx1x,8'h49};
parameter op_addl = {3'b01x,8'hB0};
parameter op_addf = {3'b11x,8'hB0};
parameter op_mull = {3'b01x,8'hBC};
parameter op_mulf = {3'b11x,8'hBC};
parameter op_truf = {3'b101,8'h9A}; // TRUNCFW for SCALBF
parameter op_trul = {3'b001,8'h9A}; // TRUNCLW for SCALBL
parameter op_stpr = {3'b11x,8'h54}; // Special-Op for String opcodes
parameter op_lsh = {3'b011,8'h65}; // EXT : shift to right : DOUBLE !
parameter op_msk = {3'b011,8'h80}; // reuse of EXT Opcode at INS !
parameter op_mul = {3'b011,8'h78}; // INDEX
parameter op_rwv = {3'bx1x,8'hE0}; // RDVAL+WRVAL
always @(OPREG) // whether the Opcode is valid is decided in DECODER !
casex (OPREG[13:0])
// 14'bxx_xxxx_1111_1110 : op_code = {2'b01,OPREG[11:10],OPREG[8]}; // DOT/POLY/SCALB
14'b00_0xxx_0000_1110 : op_code = 5'b1_0000; // MOVS/CMPS
14'b00_11xx_0000_1110 : op_code = 5'b1_0000; // SKPS
14'b00_0xxx_1100_1110 : op_code = 5'b1_0001; // MOVM/CMPM
14'bxx_xx10_0111_11xx : op_code = 5'b1_0010; // JUMP/JSR
14'bxx_x111_0111_11xx : op_code = 5'b1_0011; // CASE
14'bxx_xxxx_xx11_010x : op_code = 5'b1_0100; // TBIT
14'bxx_xxxx_xx11_0111 : op_code = 5'b1_0100; // TBIT
14'b0x_1xxx_0100_1110 : op_code = 5'b1_0100; // CBIT/SBIT
14'b11_10xx_0100_1110 : op_code = 5'b1_0100; // IBIT
14'b00_11xx_1100_1110 : op_code = 5'b1_0101; // EXTS
14'b10_x1xx_1100_1110 : op_code = 5'b1_0111; // DEI/MEI
14'bxx_x0xx_1110_1110 : op_code = 5'b1_1000; // CHECK
14'bxx_x0xx_0010_1110 : op_code = 5'b1_1010; // EXT
14'bxx_x0xx_1010_1110 : op_code = 5'b1_1011; // INS
14'b00_10xx_1100_1110 : op_code = 5'b1_1011; // INSS, the same like INS !
14'bxx_x0xx_0110_1110 : op_code = 5'b1_1100; // CVTP
14'bxx_x1xx_0010_1110 : op_code = 5'b1_1101; // INDEX
14'bxx_x000_0111_11xx : op_code = 5'b1_1110; // CXPD
14'b00_0xxx_0001_1110 : op_code = 5'b1_1111; // RDVAL+WRVAL
default : op_code = 5'b00_xxx;
endcase
always @(posedge BCLK) if (PHASE_0) op_reg_reg <= op_code;
assign op_reg = PHASE_0 ? op_code : op_reg_reg;
always @(PHRD1) // recode of States
casex (PHRD1)
4'h5 : phsrc1 = 8'h51;
4'h6 : phsrc1 = 8'h52;
4'hB : phsrc1 = 8'h53; // ok, is in default ...
default : phsrc1 = 8'h53;
endcase
assign get8b_s = (PHRD1 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 53
always @(PHRD2) // recode of States
casex (PHRD2)
4'h5 : phsrc2 = 8'h56;
4'h6 : phsrc2 = 8'h57;
4'hB : phsrc2 = 8'h58; // ok, is in default ...
default : phsrc2 = 8'h58;
endcase
assign get8b_d = (PHRD2 == 4'hB) ? 4'hC : 4'h0; // Special case 8B Immeadiate, is used in State 58
assign src_1l = {SRC_1[6:1],1'b0};
assign src_2l = {SRC_2[6:1],~SRC_2[0]}; // needed only for DEI/MEI
assign dest_2 = SRC_2[5:0];
assign phchk = {7'b0101_010,size_dw}; // Phase 54 or 55
assign op_kust = {1'bx,OPERA[9:8],8'h7A}; // Special-Opcode for MOVM/CMPM
assign op_bwd = {1'bx,OPERA[9:8],8'h45}; // for CASE and Bit opcodes
assign re_wr = {EXR22[18:17],4'b0101,4'h0, 9'h003}; // REUSE Address : Write of rmw , top 2 Bits contain size
always @(posedge BCLK) if (PHASE_0) ext_tos <= (OPREG[18:14] == 5'h17); // if TOS
assign rexwr = {EXR22[18:17],4'b0101,4'h0, ext_tos, 8'h03}; // REUSE Addresse : Write von rmw , only for EXT and EXTS !
always @(posedge BCLK) tbit_flag <= ~OPERA[1]; // due to Timing ...
always @(posedge BCLK) size_dw <= OPERA[9];
always @(posedge BCLK) if (PHASE_0) chkreg <= {3'b000,OPREG[13:11]}; // for CHECK
assign rd_reg = (PHASE_0) ? {4'b0,OPREG[13:11]} : {1'b0,chkreg}; // for read operation at EXT/INS
always @(posedge BCLK) if (PHASE_0) bwdreg <= OPREG[9:8]; // only for INS/INSS !
assign op_zext = {1'bx,(PHASE_0 ? OPREG[9:8] : bwdreg),8'h76};
always @(posedge BCLK) if (PHASE_0) inss_flag <= OPREG[6]; // Difference INSS to INS
assign imdi = inss_flag ? 4'h8 : 4'hE; // read Immediate or Displacement
assign exoffset = inss_flag ? 19'b10_1011_0000_0_0000_0011 // Read of SRC2 at INSS
: 19'b10_1011_1100_0_0000_0011; // Read of SRC1+Offset at EXT, SRC2+Offset at INS
always @(*)
casex (op_reg)
5'b1_0000 : // MOVS Phase 0 : Entry 1. Pointer "in Page"-test prepare, 2. test for R0=0 , then jump to x'C0
begin
STATE_0 = { addr_nop,8'h67, 7'h01, 7'h02, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String-Pointer prepare
state_50 = dont_care;
state_53 = dont_care;
state_54 = dont_care;
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
5'b1_0001 : // MOVM Phase 0 : Entry with test for R0=0 , then jump to x'C0
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b1,temp_h,op_adr, 2'b00,2'b00,NXRW2 };
state_54 = dont_care;
state_55 = dont_care;
state_58 = { disp2ea, 8'h65, src_x, src_x, 1'b1,temp_1,op_adr, 2'b00,2'b00,4'b1110 }; // Read of DISP for count
state_59 = { addr_nop,8'h67, rtmph, rtmp1, 1'b0,dest_x,op_stpr, 2'b00,2'b00,4'h0 }; // String-Pointer prepare
state_5A = dont_care;
end
5'b1_0010 : // JUMP/JSR
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
state_54 = dont_care;
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
5'b1_1110 : // CXPD
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { addr_nop,8'h6B, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_54 = dont_care;
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
5'b1_1111 : // RDVAL+WRVAL
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { addr_nop,8'h00, src_x, src_x, 1'b0,dest_x,op_rwv, 2'b00,2'b10,4'h0 }; // LD_OUT set because of "F"
state_54 = dont_care;
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
5'b1_0011 : // CASE
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { case_op, 8'h54, SRC_1, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // only one operand in mem.
state_53 = { case_op, 8'h54, imme, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h0 };
state_54 = { addr_nop,8'h66, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
5'b1_0100 : // all Bit opcodes with Bit in memory. RMW Test in Phase x'59 = Special case, otherwise x'58
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_54 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // here SRC1 => TEMP_H
state_55 = dont_care;
state_58 = { read_byb,8'h59, rtmph, src_x, 1'b0,dest_x,op_bwd, 2'b00,2'b00,4'h1 }; // next read of Byte
state_59 = tbit_flag ?
{ addr_nop,8'h00, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // TBIT end
: { re_wr, 8'h27, src_x, imme, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 }; // CBIT/SBIT/IBIT end
state_5A = dont_care;
end
5'b1_0101 : // EXTS : BASE Operand => TEMP, calculate address of Destination
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_54 = ACCA[1] ?
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
: { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
state_55 = dont_care;
state_58 = { addr_nop,8'h59, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h8 }; // 1 Byte Immediate read
state_59 = ACCA[1] ? // _..M.
{ rexwr, 8'h27, imme, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
: { addr_nop,8'h00, imme, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
state_5A = dont_care;
end
5'b1_1010 : // EXT : BASE Operand => TEMP, calculate address of Destination
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Addr => EA Reg
state_54 = ACCA[1] ?
( ACCA[3] ?
{addr_nop,8'h5A, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
:{ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } ) // here Adr(DEST) => EA
: { addr_nop,8'h59, rd_reg,(ACCA[3] ? imme : rtmph),
1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
state_55 = { exoffset,8'h54, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
state_58 = { addr_nop,8'h59, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'hE }; // Displacement read
state_59 = ACCA[1] ? // _..M.
{ rexwr, 8'h27, src_x, rtmph, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
: { addr_nop,8'h00, src_x, rtmph, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
state_5A = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }; // special case Mem-Mem
end
5'b1_1011 : // INS/INSS : BASE Operand => TEMP, SRC2 read as Double ! RMW not tested (Phase x'6A) but uncritical
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(SRC1) => TEMP
state_54 = ACCA[1] ?
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here Adr(DEST) => EA
: { addr_nop,8'h5A, SRC_2, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi }; // Imme./Disp. read
state_55 = { exoffset,8'h6A, rd_reg,src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h1 }; // Read Source, EA reuse
state_58 = { addr_nop,8'h55, src_x, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; //
state_59 = ACCA[1] ? // _..M.
{ re_wr, 8'h27, rtmph, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h1 } // result in memory
: { addr_nop,8'h00, rtmph, rtmpl, 1'b1,dest_2,OPERA, 2'b00,2'b00,4'h0 }; // result in Register
state_5A = { addr_nop,8'h68, imme, src_x, 1'b1,temp_1,op_msk, 2'b00,2'b00,4'h0 }; // Mask generate
end
5'b1_1101 : // INDEX :
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_zext, 2'b00,2'b00,4'h0 }; // zext(SRC1) => TEMP_H
state_54 = ACCA[1] ?
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // zext(SRC2) => TEMP_L
: { addr_nop,8'h55, SRC_2, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 };
state_55 = { addr_nop,8'h5A, rd_reg,rtmph, 1'b1,temp_h,op_mul, 2'b00,2'b00,4'h0 }; // Multiplication
state_58 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_zext, 2'b00,2'b00,4'h0 }; //
state_59 = { addind, 8'h60, rtmpl, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of Index in EA
state_5A = { addone, 8'h59, rd_reg,rtmph, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // Add of EA (=+1)
end
5'b1_0111 : // DEI + MEI , both read 8B from DEST ! RMW critical !
begin
STATE_0 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_50 = ACCA[3] ? // _M...
{ ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
: { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 };
state_54 = ACCA[1] ?
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } // here SRC1 => TEMP_H
: { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 }; // 1. part of Register
state_55 = dont_care;
state_58 = size_dw ?
{ addr_nop,8'h59, rtmph, imme, 1'b0,dest_x,OPERA, 2'b01,2'b00,4'h0 } // D needs 2 accesses
: { addr_nop,8'h1F, rtmph, imme, 1'b0,dest_x,OPERA, 2'b11,2'b00,4'h0 }; // B+W start at once
state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l), // SRC2 = memory or Reg
~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
state_5A = dont_care;
end
5'b1_1000 : // CHECK
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // No Register !
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { addr_nop,phchk, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }; // No Immediate !
state_54 = ACCA[1] ?
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
: ( size_dw ?
{addr_nop,8'h5A, SRC_2, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 } // Upper Bound - pointer
: {addr_nop,8'h00, rtmph, SRC_2, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 } );
state_55 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
state_58 = size_dw ?
{ addr_nop,8'h59, imme, src_x, 1'b1,temp_1,op_mov, 2'b00,2'b00,4'h0 } // here SRC2 => TEMP_1
: { addr_nop,8'h00, rtmph, imme, 1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 };
state_59 = { addr_nop,8'h5A, rtmp1, rtmpl, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // Upper Bound - pointer
state_5A = { addr_nop,8'h00, rtmph, (ACCA[1] ? rtmp1 : SRC_2),
1'b1,chkreg,OPERA, 2'b00,2'b10,4'h0 }; // pointer - Lower Bound
end
5'b1_1100 : // CVTP
begin
STATE_0 = { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }; // Address
state_50 = { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 };
state_53 = { addr_nop,8'h54, src_x, src_x, 1'b1,temp_h,op_adr, 2'b00,2'b00,4'h0 };
state_54 = { adrcvtp, 8'h73, rtmph, rd_reg,1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // 8*TEMP+Offset
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
// 5'b01_000 : // SCALBL : RMW critical !
// begin
// STATE_0 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, src_1l,1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 };
// state_53 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,get8b_s };
// state_54 = ACCA[1] ?
// { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_trul, 2'b00,2'b00,NXRW2 }
// : { addr_nop,8'h5A, src_x, src_x, 1'b0,temp_h,op_trul, 2'b00,2'b00,4'h0 };
// state_55 = { addr_nop,8'h54, rtmph, imme, 1'b1,temp_h,op_trul, 2'b11,2'b00,4'h0 }; // 2. half of external SRC1
// state_58 = { addr_nop,8'h59, rtmph, imme, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 };
// state_59 = { addr_nop,8'h1F, src_x, (ACCA[1] ? imme : src_2l),
// ~ACCA[1],dest_2,OPERA, 2'b10,2'b00,4'h0 };
// state_5A = { addr_nop,8'h59, rtmph, SRC_2, 1'b0,dest_2,OPERA, 2'b01,2'b00,4'h0 }; // empty cycle for TRUNC => TEMP !
// end
// 5'b01_001 : // SCALBF : RMW critical !
// begin
// STATE_0 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
// state_53 = { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_truf, 2'b00,2'b00,4'h0 };
// state_54 = ACCA[1] ?
// { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
// : { addr_nop,8'h1F, rtmph, SRC_2, 1'b1,dest_2,OPERA, 2'b11,2'b00,4'h0 };
// state_55 = dont_care;
// state_58 = { addr_nop,8'h1F, rtmph, imme, 1'b0,dest_x,OPERA, 2'b11,2'b00,4'h0 };
// state_59 = dont_care;
// state_5A = dont_care;
// end
// 5'b01_100 : // POLYL
// begin
// STATE_0 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
// state_53 = { addr_nop,8'h54, imme, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,get8b_s };
// state_54 = { addr_nop,8'h64, (ACCA[3] ? imme : src_1l),
// F0, 1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0 };
// state_55 = dont_care;
// state_58 = { addr_nop,8'h59, imme, rtmph, 1'b0,dest_x,op_addl, 2'b01,2'b00,get8b_d };
// state_59 = { addr_nop,8'h62, (ACCA[1] ? imme : src_2l),
// rtmpl, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 };
// state_5A = dont_care;
// end
// 5'b01_101 : // POLYF
// begin
// STATE_0 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { addr_nop,8'h54, SRC_1, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
// state_53 = { addr_nop,8'h54, imme, F0, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
// state_54 = ACCA[1] ?
// { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 }
// : { addr_nop,8'h00, rtmph, SRC_2, 1'b1,w_F0 ,op_addf, 2'b00,2'b00,4'h0 };
// state_55 = dont_care;
// state_58 = { addr_nop,8'h00, rtmph, imme, 1'b1,w_F0 ,op_addf, 2'b00,2'b00,4'h0 };
// state_59 = dont_care;
// state_5A = dont_care;
// end
// 5'b01_110 : // DOTL
// begin
// STATE_0 = (~ACCA[3] & ~ACCA[1]) ? // _R.R.
// { addr_nop,8'h59, SRC_1, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,4'h0 }
// : ( ACCA[3] ? // _M...
// {ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : {ADRD2, phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } );
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
// state_53 = ACCA[1] ? // _..M.
// { addr_nop,8'h54, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,get8b_s }
// : { addr_nop,8'h59, imme, SRC_2, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_s };
// state_54 = { addr_nop,8'h55, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 };
// state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
// state_58 = { addr_nop,8'h59, (ACCA[3] ? rtmph : SRC_1), //_M...
// imme, 1'b0,dest_x,op_mull, 2'b01,2'b00,get8b_d };
// state_59 = { addr_nop,8'h5A, (ACCA[3] ? (ACCA[1] ? rtmpl : imme) : src_1l), (ACCA[1] ? imme : src_2l),
// 1'b1,temp_h,op_mull, 2'b10,2'b00,4'h0 };
// state_5A = { addr_nop,8'h61, rtmph, F0_h, 1'b0,temp_h,op_mull, 2'b01,2'b00,4'h0 };
// end
// 5'b01_111 : // DOTF
// begin
// STATE_0 = (~ACCA[3] & ~ACCA[1]) ? // _R.R.
// { addr_nop,8'h63, SRC_1 ,SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 } // opera = MULF
// : ( ACCA[3] ? // _M...
// {ADRD1, phsrc1,src_x, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : {ADRD2, phsrc2,src_x, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 } );
// state_50 = ACCA[3] ? // _M...
// { ADRD1, phsrc1,IRRW1, REGA1, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRD1 }
// : { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
// state_53 = ACCA[1] ? // _..M.
// { addr_nop,8'h55, imme, src_x, 1'b1,temp_h,op_mov, 2'b00,2'b00,4'h0 }
// : { addr_nop,8'h63, imme, SRC_2 ,1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
// state_54 = dont_care;
// state_55 = { ADRD2, phsrc2,IRRW2, REGA2, 1'b0,dest_x,op_mov, 2'b00,2'b00,NXRW2 };
// state_58 = { addr_nop,8'h63, (ACCA[3] ? rtmph : SRC_1), //_M...
// imme, 1'b1,temp_h,op_mulf, 2'b00,2'b00,4'h0 };
// state_59 = dont_care;
// state_5A = dont_care;
// end
default
begin
STATE_0 = dont_care;
state_50 = dont_care;
state_53 = dont_care;
state_54 = dont_care;
state_55 = dont_care;
state_58 = dont_care;
state_59 = dont_care;
state_5A = dont_care;
end
endcase
always @(*)
casex (PHASE)
4'h0 : STATE_GROUP_50 = state_50;
// Phase 51 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
4'h1 : STATE_GROUP_50 = {exr11, 8'h52, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111};
// Phase 52 : Memory-Pointer for Memory Relative and last access External
4'h2 : STATE_GROUP_50 = {EXR12, 8'h53, IRRW1,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}; // atys[0] !
4'h3 : STATE_GROUP_50 = state_53;
4'h4 : STATE_GROUP_50 = state_54;
4'h5 : STATE_GROUP_50 = state_55;
// Phase 56 : wait for data and Disp2 for External Address mode : part 2 EA = (MOD+4)+4*DISP1
4'h6 : STATE_GROUP_50 = {exr11, 8'h57, src_x,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111};
// Phase 57 : Memory-Pointer for Memory Relative and last access External
4'h7 : STATE_GROUP_50 = {EXR22, 8'h58, IRRW2,imme , 1'b0,dest_x, op_mov, 2'b00,2'b00, 4'b1111}; // atyd[0] !
4'h8 : STATE_GROUP_50 = state_58;
4'h9 : STATE_GROUP_50 = state_59;
4'hA : STATE_GROUP_50 = state_5A;
default : STATE_GROUP_50 = dont_care;
endcase
always @(*)
casex (PHASE)
4'h0 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b1,chkreg,op_adr, 2'b00,2'b00,4'h0 }; // for INDEX
4'h1 : STATE_GROUP_60 = { addr_nop,8'h62, rtmpl, F0, 1'b1,w_F0_h,op_addl, 2'b10,2'b00,4'h0 }; // for DOTL
4'h2 : STATE_GROUP_60 = { addr_nop,8'h00, src_x, src_x, 1'b0,w_F0_h,op_addl, 2'b00,2'b00,4'h0 }; // for DOTL & POLYL !
4'h3 : STATE_GROUP_60 = { addr_nop,8'h00, rtmph, F0, 1'b1,w_F0, op_addf, 2'b00,2'b00,4'h0 }; // for DOTF
4'h4 : STATE_GROUP_60 = ACCA[1] ? // ..M.
{ ADRD2, phsrc2,IRRW2, REGA2, 1'b0,temp_h,op_mull, 2'b00,2'b00,NXRW2 }
: { addr_nop,8'h59, SRC_2, rtmph, 1'b0,temp_h,op_addl, 2'b01,2'b00,4'h0 }; // for POLYL
4'h5 : STATE_GROUP_60 = { addr_nop,8'h59, src_x, src_x, 1'b1,temp_l,op_kust, 2'b00,2'b00,4'h0 }; // for MOVM/CMPM
4'h6 : STATE_GROUP_60 = { addr_nop,8'h01, rtmph, src_x, 1'b0,dest_x,op_mov, 2'b00,2'b00,4'h0 }; // for JUMP/JSR/CASE
4'h7 : STATE_GROUP_60 = { addr_nop,8'hC0, (op_reg_reg[0] ? rtmpl : 7'h00), // Jump to String execution
src_x, 1'b0,dest_x,OPERA, 2'b00,2'b10,4'h0 }; // LD_OUT set, CMPS F-Flag
// for INS
4'h8 : STATE_GROUP_60 = { addr_nop,8'h69, rd_reg,rtmph, 1'b1,temp_h,op_lsh, 2'b00,2'b00,4'h0 }; // SRC1 shift
4'h9 : STATE_GROUP_60 = { addr_nop,8'h59, rd_reg,rtmp1, 1'b0,dest_x,op_lsh, 2'b00,2'b00,4'h0 }; // Mask shift
4'hA : STATE_GROUP_60 = { addr_nop,8'h5A, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,imdi }; // Imme./Disp. read
// for CXPD, this State is decoded explicitly in DECODER
4'hB : STATE_GROUP_60 = { addr_nop,8'h39, imme, src_x, 1'b1,temp_l,op_mov, 2'b00,2'b00,4'h0 }; // pass PC
default : STATE_GROUP_60 = dont_care;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLRTN_BLACKBOX_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// too bad- we have to do this!
`timescale 1ns/100ps
module util_bsplit (
data,
split_data_0,
split_data_1,
split_data_2,
split_data_3,
split_data_4,
split_data_5,
split_data_6,
split_data_7);
// parameters
parameter CH_DW = 1;
parameter CH_CNT = 8;
localparam CH_MCNT = 9;
// interface
input [((CH_CNT*CH_DW)-1):0] data;
output [(CH_DW-1):0] split_data_0;
output [(CH_DW-1):0] split_data_1;
output [(CH_DW-1):0] split_data_2;
output [(CH_DW-1):0] split_data_3;
output [(CH_DW-1):0] split_data_4;
output [(CH_DW-1):0] split_data_5;
output [(CH_DW-1):0] split_data_6;
output [(CH_DW-1):0] split_data_7;
// internal signals
wire [((CH_MCNT*CH_DW)-1):0] data_s;
// extend and split
assign data_s[((CH_MCNT*CH_DW)-1):(CH_CNT*CH_DW)] = 'd0;
assign data_s[((CH_CNT*CH_DW)-1):0] = data;
assign split_data_0 = data_s[((CH_DW*1)-1):(CH_DW*0)];
assign split_data_1 = data_s[((CH_DW*2)-1):(CH_DW*1)];
assign split_data_2 = data_s[((CH_DW*3)-1):(CH_DW*2)];
assign split_data_3 = data_s[((CH_DW*4)-1):(CH_DW*3)];
assign split_data_4 = data_s[((CH_DW*5)-1):(CH_DW*4)];
assign split_data_5 = data_s[((CH_DW*6)-1):(CH_DW*5)];
assign split_data_6 = data_s[((CH_DW*7)-1):(CH_DW*6)];
assign split_data_7 = data_s[((CH_DW*8)-1):(CH_DW*7)];
endmodule
// ***************************************************************************
// ***************************************************************************
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: sound_module.v
// /___/ /\ Timestamp: Tue Nov 19 15:10:47 2013
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/ipcore_dir/tmp/_cg/sound_module.ngc" "C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/ipcore_dir/tmp/_cg/sound_module.v"
// Device : 6slx16csg324-3
// Input file : C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/ipcore_dir/tmp/_cg/sound_module.ngc
// Output file : C:/Users/Fabian/Desktop/Respaldo taller/taller-diseno-digital-master/Proyecto Final/tec-drums/ipcore_dir/tmp/_cg/sound_module.v
// # of Modules : 1
// Design Name : sound_module
// Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module sound_module (
aclk, m_axis_data_tvalid, m_axis_data_tdata
)/* synthesis syn_black_box syn_noprune=1 */;
input aclk;
output m_axis_data_tvalid;
output [15 : 0] m_axis_data_tdata;
// synthesis translate_off
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/sig00000044 ;
wire \blk00000001/sig00000043 ;
wire \blk00000001/sig00000042 ;
wire \blk00000001/sig00000041 ;
wire \blk00000001/sig00000040 ;
wire \blk00000001/sig0000003f ;
wire \blk00000001/sig0000003e ;
wire \blk00000001/sig0000003d ;
wire \blk00000001/sig0000003c ;
wire \blk00000001/sig0000003b ;
wire \blk00000001/sig0000003a ;
wire \blk00000001/sig00000039 ;
wire \blk00000001/sig00000038 ;
wire \blk00000001/sig00000037 ;
wire \blk00000001/sig00000036 ;
wire \blk00000001/sig00000035 ;
wire \blk00000001/sig00000034 ;
wire \blk00000001/sig00000033 ;
wire \blk00000001/sig00000032 ;
wire \blk00000001/sig00000031 ;
wire \blk00000001/sig00000030 ;
wire \blk00000001/sig0000002f ;
wire \blk00000001/sig0000002e ;
wire \blk00000001/sig0000002d ;
wire \blk00000001/sig0000002c ;
wire \blk00000001/sig0000002b ;
wire \blk00000001/sig0000002a ;
wire \blk00000001/sig00000029 ;
wire \blk00000001/sig00000028 ;
wire \blk00000001/sig00000027 ;
wire \blk00000001/sig00000026 ;
wire \blk00000001/sig00000025 ;
wire \blk00000001/sig00000024 ;
wire \blk00000001/sig00000023 ;
wire \blk00000001/sig00000022 ;
wire \blk00000001/sig00000021 ;
wire \blk00000001/sig00000020 ;
wire \blk00000001/sig0000001f ;
wire \blk00000001/sig0000001e ;
wire \blk00000001/sig0000001d ;
wire \blk00000001/sig0000001c ;
wire \blk00000001/sig0000001b ;
wire \blk00000001/sig0000001a ;
wire \blk00000001/sig00000019 ;
wire \blk00000001/sig00000018 ;
wire \blk00000001/sig00000017 ;
wire \blk00000001/sig00000016 ;
wire \blk00000001/sig00000015 ;
wire \blk00000001/sig00000014 ;
wire \blk00000001/sig00000013 ;
wire \blk00000001/blk0000003a/sig000001bf ;
wire \blk00000001/blk0000003a/sig000001be ;
wire \blk00000001/blk0000003a/sig000001bd ;
wire \blk00000001/blk0000003a/sig000001bc ;
wire \blk00000001/blk0000003a/sig000001bb ;
wire \blk00000001/blk0000003a/sig000001ba ;
wire \blk00000001/blk0000003a/sig000001b9 ;
wire \blk00000001/blk0000003a/sig000001b8 ;
wire \blk00000001/blk0000003a/sig000001b7 ;
wire \blk00000001/blk0000003a/sig000001b6 ;
wire \blk00000001/blk0000003a/sig000001b5 ;
wire \blk00000001/blk0000003a/sig000001b4 ;
wire \blk00000001/blk0000003a/sig000001b3 ;
wire \blk00000001/blk0000003a/sig000001b2 ;
wire \blk00000001/blk0000003a/sig000001b1 ;
wire \blk00000001/blk0000003a/sig000001b0 ;
wire \blk00000001/blk0000003a/sig000001af ;
wire \blk00000001/blk0000003a/sig000001ae ;
wire \blk00000001/blk0000003a/sig000001ad ;
wire \blk00000001/blk0000003a/sig000001ac ;
wire \blk00000001/blk0000003a/sig000001ab ;
wire \blk00000001/blk0000003a/sig000001aa ;
wire \blk00000001/blk0000003a/sig000001a9 ;
wire \blk00000001/blk0000003a/sig000001a8 ;
wire \blk00000001/blk0000003a/sig000001a7 ;
wire \blk00000001/blk0000003a/sig000001a6 ;
wire \blk00000001/blk0000003a/sig000001a5 ;
wire \blk00000001/blk0000003a/sig000001a4 ;
wire \blk00000001/blk0000003a/sig000001a3 ;
wire \blk00000001/blk0000003a/sig000001a2 ;
wire \blk00000001/blk0000003a/sig000001a1 ;
wire \blk00000001/blk0000003a/sig000001a0 ;
wire \NLW_blk00000001/blk0000017c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000178_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000176_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000174_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000172_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000170_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000168_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000166_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000164_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000162_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000160_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000158_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000156_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000154_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000152_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000150_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000148_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000146_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000144_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000142_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000140_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000013a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000139_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000138_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000137_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000136_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000135_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000134_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000133_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000132_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000131_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000130_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012f_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012e_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012d_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012c_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPA<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOPB<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DOB<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000012b_DIA<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000007_DOD<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000007_DOD<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000006_SPO_UNCONNECTED ;
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017c (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000013 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000068 ),
.Q(\blk00000001/sig0000001b ),
.Q15(\NLW_blk00000001/blk0000017c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016f ),
.Q(\blk00000001/sig00000137 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017a (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f5 ),
.Q(\blk00000001/sig0000016f ),
.Q15(\NLW_blk00000001/blk0000017a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000179 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016e ),
.Q(\blk00000001/sig00000138 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000178 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig0000016e ),
.Q15(\NLW_blk00000001/blk00000178_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000177 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016d ),
.Q(\blk00000001/sig00000139 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000176 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f7 ),
.Q(\blk00000001/sig0000016d ),
.Q15(\NLW_blk00000001/blk00000176_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000175 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016c ),
.Q(\blk00000001/sig0000013a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000174 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f8 ),
.Q(\blk00000001/sig0000016c ),
.Q15(\NLW_blk00000001/blk00000174_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000173 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016b ),
.Q(\blk00000001/sig0000013b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000172 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f9 ),
.Q(\blk00000001/sig0000016b ),
.Q15(\NLW_blk00000001/blk00000172_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000171 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000016a ),
.Q(\blk00000001/sig0000013c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000170 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig0000016a ),
.Q15(\NLW_blk00000001/blk00000170_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000169 ),
.Q(\blk00000001/sig0000013d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016e (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000169 ),
.Q15(\NLW_blk00000001/blk0000016e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000168 ),
.Q(\blk00000001/sig0000013e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016c (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000168 ),
.Q15(\NLW_blk00000001/blk0000016c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000167 ),
.Q(\blk00000001/sig0000013f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016a (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000fd ),
.Q(\blk00000001/sig00000167 ),
.Q15(\NLW_blk00000001/blk0000016a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000169 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000166 ),
.Q(\blk00000001/sig00000140 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000168 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000fe ),
.Q(\blk00000001/sig00000166 ),
.Q15(\NLW_blk00000001/blk00000168_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000167 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000165 ),
.Q(\blk00000001/sig00000141 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000166 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ff ),
.Q(\blk00000001/sig00000165 ),
.Q15(\NLW_blk00000001/blk00000166_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000165 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000164 ),
.Q(\blk00000001/sig00000142 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000164 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000100 ),
.Q(\blk00000001/sig00000164 ),
.Q15(\NLW_blk00000001/blk00000164_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000163 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000163 ),
.Q(\blk00000001/sig00000143 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000162 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000101 ),
.Q(\blk00000001/sig00000163 ),
.Q15(\NLW_blk00000001/blk00000162_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000161 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000162 ),
.Q(\blk00000001/sig00000144 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000160 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000102 ),
.Q(\blk00000001/sig00000162 ),
.Q15(\NLW_blk00000001/blk00000160_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000161 ),
.Q(\blk00000001/sig00000128 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015e (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig00000161 ),
.Q15(\NLW_blk00000001/blk0000015e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000160 ),
.Q(\blk00000001/sig00000129 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015c (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig00000160 ),
.Q15(\NLW_blk00000001/blk0000015c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015f ),
.Q(\blk00000001/sig00000145 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000015a (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000103 ),
.Q(\blk00000001/sig0000015f ),
.Q15(\NLW_blk00000001/blk0000015a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000159 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015e ),
.Q(\blk00000001/sig0000012a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000158 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig0000015e ),
.Q15(\NLW_blk00000001/blk00000158_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000157 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015d ),
.Q(\blk00000001/sig0000012b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000156 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000e9 ),
.Q(\blk00000001/sig0000015d ),
.Q15(\NLW_blk00000001/blk00000156_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000155 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015c ),
.Q(\blk00000001/sig0000012c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000154 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ea ),
.Q(\blk00000001/sig0000015c ),
.Q15(\NLW_blk00000001/blk00000154_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000153 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015b ),
.Q(\blk00000001/sig0000012d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000152 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000eb ),
.Q(\blk00000001/sig0000015b ),
.Q15(\NLW_blk00000001/blk00000152_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000151 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000015a ),
.Q(\blk00000001/sig0000012e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000150 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ec ),
.Q(\blk00000001/sig0000015a ),
.Q15(\NLW_blk00000001/blk00000150_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000159 ),
.Q(\blk00000001/sig0000012f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014e (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ed ),
.Q(\blk00000001/sig00000159 ),
.Q15(\NLW_blk00000001/blk0000014e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000158 ),
.Q(\blk00000001/sig00000130 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014c (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ee ),
.Q(\blk00000001/sig00000158 ),
.Q15(\NLW_blk00000001/blk0000014c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000157 ),
.Q(\blk00000001/sig00000131 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000014a (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000ef ),
.Q(\blk00000001/sig00000157 ),
.Q15(\NLW_blk00000001/blk0000014a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000149 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000156 ),
.Q(\blk00000001/sig00000132 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000148 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f0 ),
.Q(\blk00000001/sig00000156 ),
.Q15(\NLW_blk00000001/blk00000148_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000147 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000155 ),
.Q(\blk00000001/sig00000133 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000146 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f1 ),
.Q(\blk00000001/sig00000155 ),
.Q15(\NLW_blk00000001/blk00000146_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000145 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000154 ),
.Q(\blk00000001/sig00000134 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000144 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f2 ),
.Q(\blk00000001/sig00000154 ),
.Q15(\NLW_blk00000001/blk00000144_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000143 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000153 ),
.Q(\blk00000001/sig00000135 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000142 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f3 ),
.Q(\blk00000001/sig00000153 ),
.Q15(\NLW_blk00000001/blk00000142_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000141 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000152 ),
.Q(\blk00000001/sig00000136 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000140 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig000000f4 ),
.Q(\blk00000001/sig00000152 ),
.Q15(\NLW_blk00000001/blk00000140_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000151 ),
.Q(\blk00000001/sig00000147 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013e (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000149 ),
.Q(\blk00000001/sig00000151 ),
.Q15(\NLW_blk00000001/blk0000013e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000150 ),
.Q(\blk00000001/sig00000068 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013c (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig0000001c ),
.Q(\blk00000001/sig00000150 ),
.Q15(\NLW_blk00000001/blk0000013c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000013b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000014f ),
.Q(\blk00000001/sig00000146 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000013a (
.A0(\blk00000001/sig00000013 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.CE(\blk00000001/sig00000013 ),
.CLK(aclk),
.D(\blk00000001/sig00000148 ),
.Q(\blk00000001/sig0000014f ),
.Q15(\NLW_blk00000001/blk0000013a_Q15_UNCONNECTED )
);
RAMB16BWER #(
.INIT_00 ( 256'hD5AB56AD5AA54A952A54A952A54A956AD5AB56AD5AB56AD5AB56A952A54A952A ),
.INIT_01 ( 256'h52AD5AB56A952A54AB56AD5AB54A952A54AB56AD5AB56AD52A54A952A54AB56A ),
.INIT_02 ( 256'hB54A956AD52A55AB56A952AD5AA54A956AD5AA54AB56AD52A54A956AD5AA54A9 ),
.INIT_03 ( 256'h52AD52AD52A55AA55AA54AB54AB56A956A952AD52A55AB54AB56A952AD52A55A ),
.INIT_04 ( 256'hAA55AAD52AD56A956AB54AB55AA55AA55AAD52AD52AD52AD52AD52AD52AD52AD ),
.INIT_05 ( 256'h54AA556AB55AAD56AB55AAD56AB55AAD56AB55AA552A954AB55AA552A956AB54 ),
.INIT_06 ( 256'h55AA9552AB552AB556AA556AA556AA552AB552AB55AA955AAD54AA556AB552A9 ),
.INIT_07 ( 256'hA555AAA555AAA555AAA555AAB554AA9552AAD55AAB556AAD55AAB552AA554AAD ),
.INIT_08 ( 256'h2AAA5554AAA95552AAB5552AAB5552AAB555AAA9554AAA5552AA9554AAB555AA ),
.INIT_09 ( 256'h556AAAAB55554AAAA955552AAAB55552AAAB5555AAAAD5556AAA95556AAA9555 ),
.INIT_0A ( 256'h5AAAAAAAA955555552AAAAAAB5555556AAAAAA5555552AAAAA555554AAAAAD55 ),
.INIT_0B ( 256'h55555555555554AAAAAAAAAAAAAAAAAB5555555555554AAAAAAAAAA955555555 ),
.INIT_0C ( 256'hAAAAAAAAAAAAAAAA555555555555555555555555555555555555555555555555 ),
.INIT_0D ( 256'hAAB555555AAAAAAB5555555AAAAAAAA555555555AAAAAAAAAAD555555555556A ),
.INIT_0E ( 256'hAA95552AAA5555AAAA5555AAAAD5554AAAAD5555AAAAB55555AAAAAD55555AAA ),
.INIT_0F ( 256'h556AAD54AA9552AA554AA9556AAD552AAD552AA9556AAB555AAA9554AAAD554A ),
.INIT_10 ( 256'hAB54AB54AB54AB54AA55AAD52A956AB55AAD56AB55AA954AAD56AA556AA556AA ),
.INIT_11 ( 256'h52B52A56A54AD5A952B56AD5A952A54A952A54A952A55AB56A952AD5AA54AB54 ),
.INIT_12 ( 256'hAD4A5294AD6B5294AD6A52B5A94AD6A56B52B5295A95A95AD4AD4AD5A95A95A9 ),
.INIT_13 ( 256'h2D696B4A5AD296B4A5AD294B5A5294B5AD294A52D6B5AD6B5AD6B5AD6B5AD6B5 ),
.INIT_14 ( 256'hB69692D2D2DA5A5A5A4B4B4B4B4B4B4B4B4B4B5A5A5A5A52D2D29696B4B5A5AD ),
.INIT_15 ( 256'h496DB492DB492DA496DA4B6925B496D25B496D25A4B692D25A4B696D2D25A4B4 ),
.INIT_16 ( 256'h24DB6DB6DB6DB24924924924925B6DB6DB6DB4924925B6DB692496DB6924B6DA ),
.INIT_17 ( 256'hB64DB26D936C936C9B649B6C936C926D924DB64936DB249B6DB24926DB6C9249 ),
.INIT_18 ( 256'h6CD9B366C993264D9B364C9B364D9B26CD9364D9326C9B26C9B24D9364DB26C9 ),
.INIT_19 ( 256'hCCCCD999933336664CCC999B336664CC99933666CC99B3266CC993366CC99326 ),
.INIT_1A ( 256'hC666667333333339999999999999999999999999999999999333333336666664 ),
.INIT_1B ( 256'hC67319CC663399CC6633198CC66733998CCE66333999CCCC666333319998CCCC ),
.INIT_1C ( 256'h8C639C631CE738C6318E739CE739CE739CE7318C6339CC6319CC6339CC67319C ),
.INIT_1D ( 256'hC78E38E38E38C71C71C71C638E38C71C638E31C638E71CE39C638C738C738C73 ),
.INIT_1E ( 256'h0E1C3C78F1E3C78F1E3C70E1C78F1C38F1C78E1C70E38F1C71E38E3871C71C71 ),
.INIT_1F ( 256'h1E0F0F87C3C1E1F0F0F878787C3C3C3C3C3C3C3C3C38787870F0F1E1E3C3878F ),
.INIT_20 ( 256'h7E07E07E0FC0F81F83F07C0F81F07C0F83E0F83E0F83E0F87C1F0F83C1F0F87C ),
.INIT_21 ( 256'hF803FC01FF00FF00FF00FF00FE01FC07F80FE03F80FC07F03F81FC0FC07E07E0 ),
.INIT_22 ( 256'h0FFFFC0001FFFE0003FFF8003FFF000FFF800FFF001FFC007FE007FE007FC01F ),
.INIT_23 ( 256'hFC000000000001FFFFFFFFFFFFFFFFFE000000000FFFFFFFC000003FFFFF0000 ),
.INIT_24 ( 256'h00FFFF00007FFFE00003FFFFF000000FFFFFFF8000000001FFFFFFFFFFFFFFFF ),
.INIT_25 ( 256'hF807F807F807FC01FF007FC01FF801FF801FFC007FF000FFF0007FFC001FFF80 ),
.INIT_26 ( 256'h1F07E0F81F03E07E0FC0FC0FC0FC0FC0FE07E03F01FC07E03F80FF01FC03F807 ),
.INIT_27 ( 256'hC3C3C3C3C3C3E1E1E1F0F078783C1E0F0783C1E0F87C1F0F83E0F83E0F83E0F8 ),
.INIT_28 ( 256'h1C38E3871C78E1C70E3C70E3C78E1C3870E1C3878F1E1C3C7878F0F1E1E1E3C3 ),
.INIT_29 ( 256'h1CE718E718E718E71CE39C738E71C638E39C71C718E38E38E38E38E38E3871C7 ),
.INIT_2A ( 256'h6673399CCE673198CE63398CE63398C67398C6739CE6318C6318C631CE739C63 ),
.INIT_2B ( 256'h666CCCCCCCCCCCCCCCCCCCCCCCCCCCCCC6666667333319998CCCE667333998CC ),
.INIT_2C ( 256'hC9B364C99366CD9B366CD993266CC99B32664CD99B332666CCCD999933332666 ),
.INIT_2D ( 256'hB6DB6C9249B6DB249B6C926D924DB24DB26D926C9B64D926C9B26C9B26CD9364 ),
.INIT_2E ( 256'h5B4B692DA4B492DA4B6925B6925B6924B6DB4924B6DB6DB4924924924924926D ),
.INIT_2F ( 256'hA5294A5AD694A5AD294B4A5AD2D69694B4B4B5A5A5A5A5A5A4B4B4B69696D2DA ),
.INIT_30 ( 256'h4AB56A952A54A952B56AD4A95A95A952B5295A95AD4AD6A52B5AD6A5294A5294 ),
.INIT_31 ( 256'h554AAA95552AAB555AAAD552AA555AA9552AB552AB55AAD56AB54AA55AA55AA5 ),
.INIT_32 ( 256'h555555555555555555555555555552AAAAAAAAAD5555556AAAAA955554AAAA95 ),
.INIT_33 ( 256'hAA9556AAB555AAA9555AAAA55552AAAB55555AAAAAA55555552AAAAAAAAA9555 ),
.INIT_34 ( 256'hA95A952B56A54A952A54A956AD52A55AA55AAD52A954AA552AB55AAB552AA554 ),
.INIT_35 ( 256'h5A52D29694B5A52D694A5AD6B5A5294A5294AD6B5A94A56B52B5A95AD4AD4AD4 ),
.INIT_36 ( 256'h5B6D2496DA496D24B692DB49692DA4B49692D2DA5A5B4B4B4B4B4B4B4B4B4B5A ),
.INIT_37 ( 256'h64DB26D926D926D924DB64936DB24926DB6DB64924924924924925B6DB6D2492 ),
.INIT_38 ( 256'hCC999B33666CC99B3266CD993264C993264D9B364D9B26CD9364D9364D926C9B ),
.INIT_39 ( 256'hCCE6663333399999CCCCCCCCE66666666666666664CCCCCCCD9999933336666C ),
.INIT_3A ( 256'hE718C639CE739CE739CC6319CE7319CE63398CE63399CC6633198CC66733199C ),
.INIT_3B ( 256'h3C71C38E3871C71C71C71C71C71C71C738E38C71C638C718E31C639C639C631C ),
.INIT_3C ( 256'hE1F0F0F8787878787878787870F0F1E1E3C3870F1E3C78F1E3C78E1C78E1C78E ),
.INIT_3D ( 256'h01F81FC0FC0FC0F81F81F03E07C1F83E0F81F07C1E0F83E1F07C3E1F0F87C3C1 ),
.INIT_3E ( 256'h00FFF000FFE003FF801FF801FF007FC01FE01FF00FE01FE03F807F01FC0FE03F ),
.INIT_3F ( 256'h000000000000003FFFFFFFFFF00000007FFFFF000007FFFE0000FFFE0003FFE0 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000139 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000139_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000139_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOA<1>_UNCONNECTED , \blk00000001/sig000000f5 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000139_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000139_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000139_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000139_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000139_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000139_DOB<1>_UNCONNECTED , \blk00000001/sig000000e6 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000139_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000139_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000139_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000139_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'hCC67319CC663398CE63398CE63398CE63398CE63398CE63398CE67319CC67319 ),
.INIT_01 ( 256'hCE63398CE67319CC67319CC673398CE63398CE63398CE63319CC67319CC67319 ),
.INIT_02 ( 256'h73398CE63319CC673198CE63399CC67319CC663398CE63319CC67319CC663398 ),
.INIT_03 ( 256'hCE63319CCE63399CC663398CC673198CE67319CCE63398CC673198CE63319CC6 ),
.INIT_04 ( 256'h663399CCE633198CE673398CC663399CC663319CCE63319CCE63319CCE63319C ),
.INIT_05 ( 256'hCC6633198CC6633198CC6633198CC6633198CC6633198CC673399CCE673198CC ),
.INIT_06 ( 256'h33998CCE6733198CCE6633199CCE6633198CCE6733998CC6633399CCE6733198 ),
.INIT_07 ( 256'h9CCC666333999CCC666333998CCC66733199CCC66733199CCC66733199CCC663 ),
.INIT_08 ( 256'hE66633339998CCCE6673331998CCCE6673339998CCC6663331998CCC66733399 ),
.INIT_09 ( 256'h33199998CCCCC66667333319998CCCCE666733339999CCCCE666733319998CCC ),
.INIT_0A ( 256'hC666666667333333319999998CCCCCCE666666333333199999CCCCCC66666333 ),
.INIT_0B ( 256'hCCCCCCCCCCCCCC666666666666666667333333333333399999999998CCCCCCCC ),
.INIT_0C ( 256'h6666666666666666CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_0D ( 256'h666CCCCCC9999999333333366666666CCCCCCCCC9999999999B3333333333326 ),
.INIT_0E ( 256'h99B3336666CCCC9999333366664CCCD9999B333366666CCCCC99999B33333666 ),
.INIT_0F ( 256'hCCD99B32664CC999332664CCD99B336664CC999B332666CCC999B3326664CCD9 ),
.INIT_10 ( 256'h66CD993266CD993266CC99B3664CD9933664CD9933664CD99B3266CCD9933266 ),
.INIT_11 ( 256'h366C99326CD9B364C993264C9B366CD9B366CD9B366CC993264C99B366CD9932 ),
.INIT_12 ( 256'h9B26C9B264D9364D9B26C99364D9B26CD9366C9B364C9B364D9B264C9B364C9B ),
.INIT_13 ( 256'h64DB26D93649B26D93649B26C9364D93649B26C9B26C9B26C9B26C9B26C9B26C ),
.INIT_14 ( 256'h6DB249B649B6C936C926D926D926D926D926D936C936C93649B64DB26D936C9B ),
.INIT_15 ( 256'h24DB6DB649249B6DB24926DB6C924DB6C924DB6C926DB64936D924DB64936D92 ),
.INIT_16 ( 256'h6DB6DB6DB6DB6924924924924936DB6DB6DB6DB6DB6C924924924DB6DB6D9249 ),
.INIT_17 ( 256'h92DB6924B6DA4925B6D24925B6DA4924B6DB6D2492496DB6DB6924924925B6DB ),
.INIT_18 ( 256'hDA4B692DA4B692DB496D25B692DB496DA4B6D24B6925B6925B6924B6D2496DA4 ),
.INIT_19 ( 256'h5A5A4B4B49696D2D25A5B4B696D2D25A4B496D2DA5B49692DA5B496D25A4B692 ),
.INIT_1A ( 256'h52D2D2D696969694B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B4B696969692D2D2D2 ),
.INIT_1B ( 256'h52D6B4A52D694B5AD296B4A5AD2D694B5A5AD29694B4A5A52D29696B4B4A5A5A ),
.INIT_1C ( 256'h5AD6B5294A5295AD6B5AD6B5AD6B5AD6B5AD6B5AD694A5294B5AD694A52D6B4A ),
.INIT_1D ( 256'hAD5A95A95A95AD4AD4AD4AD6A56A52B5295A94AD6A52B5A94AD6A5295AD6A529 ),
.INIT_1E ( 256'h5AB56AD5AB56AD5AB56AD5AB52A54A95AB52A54AD5A95AB52B56A56AD4AD4AD4 ),
.INIT_1F ( 256'h4AA55AAD56AB54AA55AAD52AD56A956A956A956A956AD52AD5AA54AB56A952A5 ),
.INIT_20 ( 256'hD552AAD55AAA554AA9552AA554AAD55AA955AA955AA955AAD54AA556AB55AAD5 ),
.INIT_21 ( 256'h5556AAAB5555AAAA5555AAAA5554AAAD555AAA9555AAAD556AAB555AAAD552AA ),
.INIT_22 ( 256'hA555555554AAAAAAA95555556AAAAAA555555AAAAAB555552AAAAD55552AAAB5 ),
.INIT_23 ( 256'hA9555555555554AAAAAAAAAAAAAAAAAAAAAAAAAAA55555555555556AAAAAAAAA ),
.INIT_24 ( 256'hAAAAAA555555554AAAAAAAAAA55555555555552AAAAAAAAAAAAAAAAAAAAAAAAA ),
.INIT_25 ( 256'h52AAAD5552AAA95555AAAA955552AAAAD55556AAAAA555555AAAAAA95555552A ),
.INIT_26 ( 256'h55AAB552AA554AAB556AA9556AA9556AAB554AAA5556AAB5552AAA5556AAAD55 ),
.INIT_27 ( 256'h956A956A956AB54AB55AA552AD56AB55AAD56AB552A955AAD54AAD54AAD54AAD ),
.INIT_28 ( 256'hA952B52A56AD4A95AB56A54A952B56AD5AB56AD52A54A956AD52A55AB54AB56A ),
.INIT_29 ( 256'h56B5AD4A52B5AD4A56B5295AD4A56B52B5295A95AD4AD4AD4AD4AD4AD4AD5A95 ),
.INIT_2A ( 256'h4B5A52D694B5A52D6B4A52D6B4A52D6B5AD294A5294B5AD6B5AD6B5A94A5294A ),
.INIT_2B ( 256'h4B4969696969696969696969696969696B4B4B4A5A5A52D2D696B4B5A5AD2D69 ),
.INIT_2C ( 256'h92DA496D25B496D25B496D25B4B692D25B4B696D2DA5B4B49696D2D25A5A4B4B ),
.INIT_2D ( 256'hDB6DB6DB6D2492492DB6DB492496DB6924B6DB492DB6924B6D24B6D24B6925B6 ),
.INIT_2E ( 256'h926DB24936D924936DB24924DB6DB24924926DB6DB6DB6D924924924924924B6 ),
.INIT_2F ( 256'hC9B26C9364D936C9B26D936C9B64DB26D926D936C936C936C926D924DB249B6C ),
.INIT_30 ( 256'h93264CD9B366CD9B264C99326CD93264D9B26CD9366C9B364D9364C9B26C9B26 ),
.INIT_31 ( 256'h99933326664CCD9993336664CC999332664CD99B3266CC99B3266CC993366CC9 ),
.INIT_32 ( 256'h666666666666666666666666666664CCCCCCCCC9999999B33333266666CCCCD9 ),
.INIT_33 ( 256'hCCE667333999CCCE66633339999CCCCC666663333339999999CCCCCCCCCCE666 ),
.INIT_34 ( 256'hCE6319CC67398CE63398CE67319CC663399CCE633198CC6633399CCC66333998 ),
.INIT_35 ( 256'h639CE318E739C6318E739CE739C6318C6318CE739CE7398C6339CE6318CE7318 ),
.INIT_36 ( 256'h9C71C718E38E71C738E31C718E31C738E71CE31C639C738C738C738C738C739C ),
.INIT_37 ( 256'h78E3C71E38E1C71E38E3871C71C38E38E38E3871C71C71C71C71C638E38E38E3 ),
.INIT_38 ( 256'hF0E1E3C3878F0E1C3C78F1E1C3870E1C3871E3C78E1C38F1E3871E3871E38F1C ),
.INIT_39 ( 256'hF0F8783C3C3E1E1E0F0F0F0F0787878787878787870F0F0F0E1E1E1C3C387870 ),
.INIT_3A ( 256'hF81F07C1F07C1F07C1F07C1E0F83E1F07C3E0F07C3E1F0783C1E0F0787C3E1E0 ),
.INIT_3B ( 256'h3F81FC0FC07E07E07E07E07E07E07E07C0FC0F81F83F07E0FC1F83E07C1F83E0 ),
.INIT_3C ( 256'h01FF00FF807F807F807F807F80FF01FE03FC07F01FC07F01FC07F01F80FE07F0 ),
.INIT_3D ( 256'hFE001FFF000FFF001FFE003FF801FFC00FFE007FE00FFC01FF803FE00FF803FE ),
.INIT_3E ( 256'h00FFFFFF000003FFFFE00001FFFF80001FFFE0000FFFE0003FFF8001FFF0003F ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFC000000000000000007FFFFFFFFFF800000000FFFFFFFC0000 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000138 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000138_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000138_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOA<1>_UNCONNECTED , \blk00000001/sig000000f6 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000138_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000138_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000138_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000138_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000138_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000138_DOB<1>_UNCONNECTED , \blk00000001/sig000000e7 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000138_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000138_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000138_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000138_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h694A5AD694B5AD294B5AD294B5AD294B5AD294B5AD294B5AD294B5A5296B5A52 ),
.INIT_01 ( 256'h94B5AD294B5A5296B5A5296B5A52D6B4A52D6B4A52D6B4A5AD694A5AD694A5AD ),
.INIT_02 ( 256'h5A52D6B4A5AD694A5AD294B5AD296B5A5296B4A52D6B4A5AD694A5AD694B5AD2 ),
.INIT_03 ( 256'h6B4A5AD694B5AD296B4A52D694A5AD294B5A5296B4A52D694A5AD294B5A5296B ),
.INIT_04 ( 256'h4B5AD296B4A5AD294B5A52D694B5AD296B4A5AD694B5A5296B4A5AD694B5A529 ),
.INIT_05 ( 256'h96B4A5AD296B4A5AD296B4A5AD296B4A5AD296B4A5AD296B5A52D694B5A52D69 ),
.INIT_06 ( 256'h5AD2D694B5A5AD296B4B5A52D694B4A5AD296B4A5AD2D694B5A52D694B5A5AD2 ),
.INIT_07 ( 256'hD696B4B5A52D29694B4A5AD2D696B4A5A52D696B4A5A52D696B4A5A52D696B4A ),
.INIT_08 ( 256'h4B4B5A5AD2D29694B4A5A5AD2D696B4B5A5AD2D29694B4A5A52D29694B5A5AD2 ),
.INIT_09 ( 256'h5A52D2D2969694B4B5A5A5AD2D29696B4B4A5A5AD2D29696B4B4A5A5AD2D2969 ),
.INIT_0A ( 256'h6B4B4B4B4A5A5A5A5AD2D2D2D6969694B4B4B4A5A5A5AD2D2D6969694B4B4A5A ),
.INIT_0B ( 256'h96969696969696B4B4B4B4B4B4B4B4B5A5A5A5A5A5A5AD2D2D2D2D2D69696969 ),
.INIT_0C ( 256'hB4B4B4B4B4B4B4B4969696969696969696969696969696969696969696969696 ),
.INIT_0D ( 256'hB4B6969692D2D2D25A5A5A5B4B4B4B49696969692D2D2D2D2D25A5A5A5A5A5B4 ),
.INIT_0E ( 256'hD2DA5A4B4B69692D2DA5A5B4B4969692D2D25A5A4B4B4969692D2D2DA5A5A4B4 ),
.INIT_0F ( 256'h696D2DA4B49692D25A4B49696D2DA5B4B696D2D25A4B4B696D2D25A4B4B69692 ),
.INIT_10 ( 256'hB496D25B4B692DA4B496D2DA4B696D25A4B696D25A4B696D2DA4B49692DA5B4B ),
.INIT_11 ( 256'h5B492DA4B692DA496D25B496D25B496D25B496D25B496D25B496D2DA4B692DA4 ),
.INIT_12 ( 256'h2DB492DB496DA496D24B6D25B692DB496DA4B6D25B692DA496D24B692DA496D2 ),
.INIT_13 ( 256'hB6924B6DA492DB4925B6D24B6DA496DA492DB492DB492DB492DB492DB492DB49 ),
.INIT_14 ( 256'hB6DB6D2492DB6DA4924B6DB4924B6DB4924B6DA4925B6DA492DB6924B6DA492D ),
.INIT_15 ( 256'hB692492492492DB6DB6DB492492496DB6DB6924924B6DB6DA492496DB6DA4924 ),
.INIT_16 ( 256'h4924924924924DB6DB6DB6DB6DA492492492492492492492492496DB6DB6DB6D ),
.INIT_17 ( 256'h24924DB6DB6C9249249B6DB6DB6C9249249249B6DB6DB6DB6DB2492492492492 ),
.INIT_18 ( 256'h6C924DB6C924DB6D9249B6DB24926DB6C9249B6DB24924DB6DB249249B6DB6C9 ),
.INIT_19 ( 256'h936C926D924DB649B6C926DB249B64936D9249B6C926DB24936D9249B6C924DB ),
.INIT_1A ( 256'h9B649B64DB24DB26D926D926D926D926D926D926D926D926DB24DB24DB649B64 ),
.INIT_1B ( 256'h649B26C9B64D926C9B24D936C9B64D926C9364DB26D936C9B64DB24D926C936C ),
.INIT_1C ( 256'h6C9B264D9364D9364D9364D9364D9364D9364D9364D9364D926C9B26C9B64D93 ),
.INIT_1D ( 256'h366CD9326CD9366C99366C9B364C9B264D9326C9B364D9326C9B364D9364C9B2 ),
.INIT_1E ( 256'h6CD9B366CD9B366CD9B366CD9B366CD93264C99366CD93264D9B364C99366C99 ),
.INIT_1F ( 256'h6CC9933664CD993366CC99B3664CD9B3264CD9B3264C99B366CC993264CD9B36 ),
.INIT_20 ( 256'h6664CC999333666CCD99B33666CC99933266CCD9933266CC99933664CD993366 ),
.INIT_21 ( 256'h999B33326666CCCC999933336666CCC99993332666CCC999B332666CCC999B33 ),
.INIT_22 ( 256'h3666666666CCCCCCCD999999B333333666666CCCCCD99999B3333666664CCCD9 ),
.INIT_23 ( 256'hCE666666666666CCCCCCCCCCCCCCCCCCCCCCCCCCC9999999999999B333333333 ),
.INIT_24 ( 256'hCCCCCC66666666733333333339999999999999CCCCCCCCCCCCCCCCCCCCCCCCCC ),
.INIT_25 ( 256'h9CCCCE666333319999CCCCE666633333199998CCCCC6666663333331999999CC ),
.INIT_26 ( 256'h99CCC66333998CCC667331998CCE667333998CCC6667333999CCCC6667333199 ),
.INIT_27 ( 256'h198CE673198CC673399CC6633198CC6633198CC6633199CCE6733198CCE67331 ),
.INIT_28 ( 256'h319CC63398CE7319CC67398CE63398CE63398CE63398CE67319CC663398CC673 ),
.INIT_29 ( 256'h6739CE739CC6318C6739CE6318C6739CC6319CE6318CE7318CE7318CE7319CE6 ),
.INIT_2A ( 256'h8C639CE718C639CE738C6318C739CE739CE318C6318C6318C6318C6318C6318C ),
.INIT_2B ( 256'h738E718E718E718E718E718E718E718E738C738C639C631CE718C739C631CE71 ),
.INIT_2C ( 256'h1CE38E71C638E71C638E71C638C71CE39C738E71CE39C738E718E31C639C738C ),
.INIT_2D ( 256'h1C71C71C71C71C71CE38E38E38E71C71C738E38E31C71C738E38C71C738E39C7 ),
.INIT_2E ( 256'h1C71C38E38E1C71C71C38E38E38E3C71C71C71C71C71C71E38E38E38E38E38C7 ),
.INIT_2F ( 256'hF1C38F1C78E1C70E3C71E38F1C78E3C71E38E1C70E38F1C70E38E1C71C38E38F ),
.INIT_30 ( 256'h1C3870E1C3870E1C3870E1C38F1E3C78E1C38F1E3870E3C78E1C78F1C38F1C38 ),
.INIT_31 ( 256'h1E1C3C387870F1E1E3C387870F1E1C3C7870E1E3C3870F1E3C3870F1E3C78F0E ),
.INIT_32 ( 256'h787878787878787878787878787878F0F0F0F0F1E1E1E1C3C3C3C787870F0F1E ),
.INIT_33 ( 256'h0F0787C3C1E1F0F0787C3C3E1E1F0F0F878783C3C3C1E1E1E1F0F0F0F0F0F878 ),
.INIT_34 ( 256'h0F83E1F0783E0F07C3E0F0783E1F0783C1E0F07C3E1F0F87C3C1E0F0783C3E1F ),
.INIT_35 ( 256'h7C1F03E0F83E07C1F07C1F07C1F83E0F83E0F07C1F07C1F07C3E0F83E0F07C1F ),
.INIT_36 ( 256'h1F81F81F03F07E07C0FC1F81F03E07C0F81F03E07C1F83F07C0F83F07C0F83E0 ),
.INIT_37 ( 256'h7F03F81FC0FE07E03F03F81F81FC0FC0FC0FC07E07E07E07E07E07C0FC0FC0FC ),
.INIT_38 ( 256'h00FE03FC07F00FE03F80FE01FC07F01FC07E03F80FE03F01FC07E03F81FC0FE0 ),
.INIT_39 ( 256'h00FF803FC03FE01FF00FF00FF807F807F807F807F80FF00FF01FE01FC03F807F ),
.INIT_3A ( 256'hFFE007FE007FE007FE007FE00FFC01FF803FF007FC01FF803FE00FF807FC01FF ),
.INIT_3B ( 256'h3FFE000FFF8007FF8007FF8007FF8007FF000FFE003FF800FFE003FF801FFC00 ),
.INIT_3C ( 256'hFE0000FFFF80007FFF80007FFF0001FFFC0007FFE0007FFE0007FFE000FFF800 ),
.INIT_3D ( 256'hFFFFE000000FFFFFE000003FFFFE00000FFFFF80000FFFFE00003FFFF00003FF ),
.INIT_3E ( 256'hFF000000000003FFFFFFFFFE000000001FFFFFFFF00000003FFFFFFE0000003F ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000FFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000137 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000137_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000137_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOA<1>_UNCONNECTED , \blk00000001/sig000000f7 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000137_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000137_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000137_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000137_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000137_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000137_DOB<1>_UNCONNECTED , \blk00000001/sig000000e8 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000137_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000137_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000137_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000137_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h718C6318E739CE318C631CE739CE318C631CE739CE318C631CE739C6318C639C ),
.INIT_01 ( 256'h18C631CE739C6318C639CE739C6318C739CE738C6318C739CE718C6318E739CE ),
.INIT_02 ( 256'h9C6318C739CE718C631CE739CE318C639CE738C6318C739CE718C6318E739CE3 ),
.INIT_03 ( 256'h8C739CE718C631CE738C6318E739CE318C639CE738C6318E739CE318C639CE73 ),
.INIT_04 ( 256'h8C631CE738C631CE739C6318E739CE318C739CE718C639CE738C6318E739C631 ),
.INIT_05 ( 256'h18C739CE318C739CE318C739CE318C739CE318C739CE318C639CE718C639CE71 ),
.INIT_06 ( 256'h631CE718C639CE318C739C6318E738C631CE738C631CE718C639CE718C639CE3 ),
.INIT_07 ( 256'h18E738C639CE318E738C631CE718C739C6318E738C639CE718C739C6318E738C ),
.INIT_08 ( 256'h8C739C631CE318E738C639CE318E738C639CE31CE718C739C631CE718C639CE3 ),
.INIT_09 ( 256'h9C631CE318E718C739C639CE31CE718C738C639CE31CE718C738C639CE31CE71 ),
.INIT_0A ( 256'h738C738C739C639C631CE31CE718E718C738C739C639CE31CE718E718C738C63 ),
.INIT_0B ( 256'h18E718E718E718C738C738C738C738C639C639C639C631CE31CE31CE718E718E ),
.INIT_0C ( 256'h38C738C738C738C718E718E718E718E718E718E718E718E718E718E718E718E7 ),
.INIT_0D ( 256'hC738E718E31CE31C639C639C738C738E718E718E31CE31CE31C639C639C639C7 ),
.INIT_0E ( 256'hE31C638C738E71CE31C639C738E718E31CE39C638C738E718E31CE31C639C738 ),
.INIT_0F ( 256'h8E71CE38C718E31C638C718E71CE39C738E71CE39C738C718E31C638C738E71C ),
.INIT_10 ( 256'hC718E39C738E31C738E71CE38C718E39C738E71C638C718E31C738E71CE39C73 ),
.INIT_11 ( 256'h9C71CE38C71CE38E71C638E71C638E71C638E71C638E71C638E71CE38C71CE38 ),
.INIT_12 ( 256'hCE38E31C718E38E71C738E39C71CE38E71C738E39C71CE38E71C738E31C718E3 ),
.INIT_13 ( 256'h38E38C71C71CE38E39C71C738E38E71C71CE38E31C71CE38E31C71CE38E31C71 ),
.INIT_14 ( 256'h38E38E38E31C71C71C738E38E38C71C71C738E38E39C71C71CE38E38C71C71CE ),
.INIT_15 ( 256'hC71C71C71C71CE38E38E38E38E38E71C71C71C71C738E38E38E38E71C71C71C7 ),
.INIT_16 ( 256'h8E38E38E38E38E38E38E38E38E38E38E38E38E38E38E38E38E38E71C71C71C71 ),
.INIT_17 ( 256'hC71C71C71C70E38E38E38E38E38F1C71C71C71C71C71C71C71C38E38E38E38E3 ),
.INIT_18 ( 256'h70E38E38F1C71C71E38E38E3C71C71C70E38E38E3C71C71C71C38E38E38E38F1 ),
.INIT_19 ( 256'hE38F1C71E38E3871C70E38E3C71C78E38E1C71C70E38E3C71C71E38E38F1C71C ),
.INIT_1A ( 256'hE3871C78E3C71C38E1C71E38E1C71E38E1C71E38E1C71E38E3C71C38E3871C78 ),
.INIT_1B ( 256'h78E3C70E3871E38F1C38E1C70E3871E38F1C78E3C71E38F1C78E3C71E38F1C70 ),
.INIT_1C ( 256'h8F1C3871E3871E3871E3871E3871E3871E3871E3871E3871E38F1C38F1C78E1C ),
.INIT_1D ( 256'h3870E1C38F1E3870E1C78F1C3870E3C78E1C38F1C3871E3C70E3C78E1C78F1C3 ),
.INIT_1E ( 256'h70E1C3870E1C3870E1C3870E1C3870E1C3870E1C78F1E3C78E1C3870E1C78F1E ),
.INIT_1F ( 256'h70F1E3C7870E1E3C78F0E1C3878F1E3C3870E1C3C78F1E3C78F0E1C3870E1C38 ),
.INIT_20 ( 256'h7878F0E1E3C3878F0E1E3C3878F0E1E3C3870F1E1C3C78F0E1E3C7870E1E3C78 ),
.INIT_21 ( 256'h1E1C3C3C7878F0F0E1E1C3C387870F0E1E1C3C3878F0F1E1C3C3878F0F1E1C3C ),
.INIT_22 ( 256'hC7878787870F0F0F0E1E1E1E3C3C3C38787870F0F0E1E1E1C3C3C787878F0F1E ),
.INIT_23 ( 256'hF0787878787878F0F0F0F0F0F0F0F0F0F0F0F0F0F1E1E1E1E1E1E1C3C3C3C3C3 ),
.INIT_24 ( 256'h0F0F0F8787878783C3C3C3C3C1E1E1E1E1E1E1F0F0F0F0F0F0F0F0F0F0F0F0F0 ),
.INIT_25 ( 256'hE0F0F0787C3C3E1E1E0F0F078783C3C3E1E1E0F0F0F878787C3C3C3E1E1E1E0F ),
.INIT_26 ( 256'h1E0F0783C3E1F0F0787C3E1E0F0F8783C3E1F0F078783C3E1E0F0F8787C3C1E1 ),
.INIT_27 ( 256'hE1F0F87C1E0F0783C1E0F87C3E1F0F87C3E1F0F87C3E1E0F0783C1E0F0F87C3E ),
.INIT_28 ( 256'h3E1F07C3E0F07C1E0F87C1F0F83C1F0F83C1F0F83C1F0F87C1E0F87C3E0F0783 ),
.INIT_29 ( 256'h87C1F07C1F07C1F0783E0F83E0F87C1F07C1E0F83E0F07C1F0F83E0F07C1E0F8 ),
.INIT_2A ( 256'hF07C1F07E0F83E0F83F07C1F07C1F07C1F03E0F83E0F83E0F83E0F83E0F83E0F ),
.INIT_2B ( 256'h7C0F81F07E0F81F07E0F81F07E0F81F07C0F83F07C1F83E0F81F07C1F83E0F81 ),
.INIT_2C ( 256'h1F03F07E07C0F81F83F07E07C0F81F03E07C0F81F03E07C0F81F03E07C1F83F0 ),
.INIT_2D ( 256'h1F81F81F81F81F81F03F03F03F07E07E07C0FC0FC1F81F83F03F07E07C0FC1F8 ),
.INIT_2E ( 256'h1F81FC0FC0FE07E07E03F03F03F03F81F81F81F81F81F81FC0FC0FC0FC0FC0F8 ),
.INIT_2F ( 256'hFE03F01F80FE07F03F81FC0FE07F03F81FC0FE07F03F01F80FC0FE07E03F03F0 ),
.INIT_30 ( 256'hE03F80FE03F80FE03F80FE03F01FC07F01FC0FE03F80FC07F01F80FE03F01FC0 ),
.INIT_31 ( 256'h1FE03FC07F80FE01FC03F807F01FE03F807F01FC03F80FE03FC07F01FC07F00F ),
.INIT_32 ( 256'h807F807F807F807F807F807F807F80FF00FF00FE01FE01FC03FC07F807F00FE0 ),
.INIT_33 ( 256'hF007F803FE01FF007F803FC01FE00FF007F803FC03FE01FE01FF00FF00FF007F ),
.INIT_34 ( 256'hF003FE007FC00FF803FF007FC01FF803FE00FF803FE00FF803FE00FF803FC01F ),
.INIT_35 ( 256'h801FFC00FFC007FE007FE007FE003FF003FF007FE007FE007FC00FFC00FF801F ),
.INIT_36 ( 256'h1FFE001FFC007FF800FFE001FFC007FF001FFC007FE003FF800FFC007FF003FF ),
.INIT_37 ( 256'h8003FFE000FFF8003FFC001FFE000FFF000FFF8007FF8007FF8007FF000FFF00 ),
.INIT_38 ( 256'hFF0003FFF8000FFFC000FFFE0007FFE0007FFC000FFFC001FFF8003FFE000FFF ),
.INIT_39 ( 256'hFF00003FFFC0001FFFF0000FFFF80007FFF80007FFF0000FFFE0001FFFC0007F ),
.INIT_3A ( 256'h000007FFFF800007FFFF80000FFFFE00003FFFF80001FFFFC0000FFFF80001FF ),
.INIT_3B ( 256'h3FFFFFF0000007FFFFF8000007FFFFF800000FFFFFC00000FFFFFC00001FFFFF ),
.INIT_3C ( 256'h000000FFFFFFFF800000007FFFFFFE00000007FFFFFF80000007FFFFFF000000 ),
.INIT_3D ( 256'h00000000000FFFFFFFFFFFC0000000000FFFFFFFFFF0000000003FFFFFFFFC00 ),
.INIT_3E ( 256'h00000000000003FFFFFFFFFFFFFFFFFFE0000000000000003FFFFFFFFFFFFFC0 ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000 ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000136 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000136_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000136_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOA<1>_UNCONNECTED , \blk00000001/sig000000f8 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000136_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000136_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000136_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000136_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000136_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000136_DOB<1>_UNCONNECTED , \blk00000001/sig000000e9 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000136_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000136_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000136_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000136_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h7E0F83E0F83E0FC1F07C1F07C1F03E0F83E0F83E0FC1F07C1F07C1F83E0F83E0 ),
.INIT_01 ( 256'h1F07C1F07C1F83E0F83E0F83E07C1F07C1F07C0F83E0F83E0F81F07C1F07C1F0 ),
.INIT_02 ( 256'h1F83E0F83E0F81F07C1F07C1F03E0F83E0F83F07C1F07C1F07E0F83E0F83E0FC ),
.INIT_03 ( 256'h0F83E0F81F07C1F07C0F83E0F83E0FC1F07C1F07C0F83E0F83E0FC1F07C1F07C ),
.INIT_04 ( 256'h0F83E0F83F07C1F07C1F83E0F83E0FC1F07C1F07E0F83E0F83F07C1F07C1F83E ),
.INIT_05 ( 256'h1F07C1F03E0F83E0FC1F07C1F03E0F83E0FC1F07C1F03E0F83E0F81F07C1F07E ),
.INIT_06 ( 256'h7C1F07E0F83E0FC1F07C1F83E0F83F07C1F07C0F83E0F81F07C1F07E0F83E0FC ),
.INIT_07 ( 256'hE0F83F07C1F03E0F83F07C1F07E0F83E07C1F07C0F83E0F81F07C1F83E0F83F0 ),
.INIT_08 ( 256'h0F83E07C1F03E0F83F07C1F03E0F83F07C1F03E0F81F07C1F83E0F81F07C1F03 ),
.INIT_09 ( 256'hE07C1F03E0F81F07C1F83E0FC1F07E0F83F07C1F03E0F81F07C0F83E0FC1F07E ),
.INIT_0A ( 256'h7C0F83F07C1F83E07C1F03E0F81F07E0F83F07C1F83E0FC1F07E0F81F07C0F83 ),
.INIT_0B ( 256'h1F07E0F81F07E0F83F07C0F83F07C0F83E07C1F83E07C1F03E0FC1F07E0F81F0 ),
.INIT_0C ( 256'h3F07C0F83F07C0F81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F8 ),
.INIT_0D ( 256'hF83F07E0FC1F03E07C1F83E07C0F83F07E0F81F03E0FC1F03E07C1F83E07C1F8 ),
.INIT_0E ( 256'h03E07C0F83F07E0FC1F83E07C0F81F03E0FC1F83F07C0F81F03E0FC1F83E07C0 ),
.INIT_0F ( 256'hF07E0FC0F81F03E07C0F81F07E0FC1F83F07E0FC1F83F07E0FC1F83F07C0F81F ),
.INIT_10 ( 256'hF81F03E07C0FC1F83F07E0FC0F81F03E07C0F81F83F07E0FC1F83F07E0FC1F83 ),
.INIT_11 ( 256'hE07E0FC0F81F03F07E07C0F81F83F07E07C0F81F83F07E07C0F81F03F07E0FC0 ),
.INIT_12 ( 256'h0FC0FC1F81F03F07E07C0FC1F81F03F07E07C0FC1F81F03F07E07C0FC1F81F03 ),
.INIT_13 ( 256'hC0FC0F81F81F03F03E07E07C0FC0F81F81F03F03E07E0FC0FC1F81F03F03E07E ),
.INIT_14 ( 256'hC0FC0FC0FC1F81F81F83F03F03F07E07E07C0FC0FC1F81F81F03F03F07E07E0F ),
.INIT_15 ( 256'h07E07E07E07E0FC0FC0FC0FC0FC0F81F81F81F81F83F03F03F03F07E07E07E07 ),
.INIT_16 ( 256'hF03F03F03F03F03F03F03F03F03F03F03F03F03F03F03F03F03F07E07E07E07E ),
.INIT_17 ( 256'hF81F81F81F80FC0FC0FC0FC0FC0FE07E07E07E07E07E07E07E03F03F03F03F03 ),
.INIT_18 ( 256'h80FC0FC0FE07E07E03F03F03F81F81F80FC0FC0FC07E07E07E03F03F03F03F01 ),
.INIT_19 ( 256'hFC0FE07E03F03F81F80FC0FC07E07F03F01F81F80FC0FC07E07E03F03F01F81F ),
.INIT_1A ( 256'hFC07E07F03F81FC0FE07E03F01F81FC0FE07E03F01F81FC0FC07E03F03F81F80 ),
.INIT_1B ( 256'h80FC07F03F81FC0FE03F01F80FC07E03F01F80FC07E03F01F80FC07E03F01F80 ),
.INIT_1C ( 256'hF01FC07E03F81FC07E03F81FC07E03F81FC07E03F81FC07E03F01FC0FE07F01F ),
.INIT_1D ( 256'hC07F01FC0FE03F80FE07F01FC07F03F80FE03F01FC07E03F80FC07F01F80FE03 ),
.INIT_1E ( 256'h7F01FC07F01FC07F01FC07F01FC07F01FC07F01F80FE03F80FE03F80FE07F01F ),
.INIT_1F ( 256'h7F01FC07F80FE03F80FF01FC07F01FC03F80FE03F80FE03F80FF01FC07F01FC0 ),
.INIT_20 ( 256'h807F00FE03FC07F00FE03FC07F00FE03FC07F01FE03F80FF01FC07F80FE03F80 ),
.INIT_21 ( 256'hE01FC03F807F00FF01FE03FC07F80FF01FE03FC07F00FE01FC03F80FF01FE03F ),
.INIT_22 ( 256'h07F807F807F00FF00FE01FE03FC03FC07F807F00FF01FE01FC03F807F80FF01F ),
.INIT_23 ( 256'h007F807F807F80FF00FF00FF00FF00FF00FF00FF01FE01FE01FE01FC03FC03FC ),
.INIT_24 ( 256'h0FF00FF807F807FC03FC03FC01FE01FE01FE01FF00FF00FF00FF00FF00FF00FF ),
.INIT_25 ( 256'h00FF007F803FC01FE00FF007F803FC03FE01FF00FF007F807FC03FC01FE01FF0 ),
.INIT_26 ( 256'h1FF007FC03FE00FF807FC01FF00FF803FC01FF007F803FC01FF00FF807FC01FE ),
.INIT_27 ( 256'h01FF007FE00FF803FE00FF803FE00FF803FE00FF803FE00FF803FE00FF007FC0 ),
.INIT_28 ( 256'h3FE007FC00FF801FF007FE00FFC01FF003FE00FFC01FF007FE00FF803FF007FC ),
.INIT_29 ( 256'h07FE007FE007FE007FC00FFC00FF801FF801FF003FF007FE00FFC00FF801FF00 ),
.INIT_2A ( 256'hFF801FF800FFC00FFC007FE007FE007FE003FF003FF003FF003FF003FF003FF0 ),
.INIT_2B ( 256'h7FF001FF800FFE007FF001FF800FFE007FF003FF801FFC00FFE007FE003FF001 ),
.INIT_2C ( 256'hE003FF8007FF001FFC007FF800FFE003FF800FFE003FF800FFE003FF801FFC00 ),
.INIT_2D ( 256'hE001FFE001FFE001FFC003FFC007FF8007FF000FFE001FFC003FF8007FF001FF ),
.INIT_2E ( 256'h1FFE000FFF0007FF8003FFC003FFC001FFE001FFE001FFE000FFF000FFF000FF ),
.INIT_2F ( 256'hFFFC001FFF0007FFC001FFF0007FFC001FFF0007FFC001FFF000FFF8003FFC00 ),
.INIT_30 ( 256'h003FFF0003FFF0003FFF0003FFE0007FFE000FFFC000FFF8001FFF0003FFE000 ),
.INIT_31 ( 256'h1FFFC0007FFF0001FFFC0007FFE0003FFF8001FFFC000FFFC0007FFE0007FFF0 ),
.INIT_32 ( 256'h007FFF80007FFF80007FFF80007FFF0000FFFF0001FFFE0003FFF80007FFF000 ),
.INIT_33 ( 256'hFFF80003FFFE00007FFFC0001FFFF00007FFFC0003FFFE0001FFFF0000FFFF80 ),
.INIT_34 ( 256'hFFFC00007FFFF00003FFFF80001FFFFC0000FFFFC0000FFFFC0000FFFFC0001F ),
.INIT_35 ( 256'h001FFFFF000007FFFF800007FFFFC00003FFFF800007FFFF80000FFFFF00001F ),
.INIT_36 ( 256'h1FFFFFE000007FFFFF000001FFFFF800001FFFFF800003FFFFF000007FFFFC00 ),
.INIT_37 ( 256'h0003FFFFFF0000003FFFFFE000000FFFFFF0000007FFFFF8000007FFFFF00000 ),
.INIT_38 ( 256'hFFFFFC0000000FFFFFFF00000007FFFFFF8000000FFFFFFE0000003FFFFFF000 ),
.INIT_39 ( 256'hFFFFFFC00000001FFFFFFFF000000007FFFFFFF80000000FFFFFFFE00000007F ),
.INIT_3A ( 256'h000007FFFFFFFFF8000000000FFFFFFFFFC000000001FFFFFFFFF000000001FF ),
.INIT_3B ( 256'h3FFFFFFFFFFFF8000000000007FFFFFFFFFFF00000000000FFFFFFFFFFE00000 ),
.INIT_3C ( 256'h000000FFFFFFFFFFFFFFFF8000000000000007FFFFFFFFFFFFF8000000000000 ),
.INIT_3D ( 256'hFFFFFFFFFFF0000000000000000000000FFFFFFFFFFFFFFFFFFFC00000000000 ),
.INIT_3E ( 256'hFFFFFFFFFFFFFC00000000000000000000000000000000003FFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000135 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000135_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000135_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOA<1>_UNCONNECTED , \blk00000001/sig000000f9 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000135_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000135_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000135_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000135_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000135_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000135_DOB<1>_UNCONNECTED , \blk00000001/sig000000ea }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000135_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000135_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000135_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000135_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h800FFC00FFC00FFE007FE007FE003FF003FF003FF001FF801FF801FFC00FFC00 ),
.INIT_01 ( 256'h1FF801FF801FFC00FFC00FFC007FE007FE007FF003FF003FF001FF801FF801FF ),
.INIT_02 ( 256'hE003FF003FF001FF801FF801FFC00FFC00FFC007FE007FE007FF003FF003FF00 ),
.INIT_03 ( 256'h0FFC00FFE007FE007FF003FF003FF001FF801FF800FFC00FFC00FFE007FE007F ),
.INIT_04 ( 256'hF003FF003FF801FF801FFC00FFC00FFE007FE007FF003FF003FF801FF801FFC0 ),
.INIT_05 ( 256'h1FF801FFC00FFC00FFE007FE003FF003FF001FF801FFC00FFC00FFE007FE007F ),
.INIT_06 ( 256'h801FF800FFC00FFE007FE003FF003FF801FF800FFC00FFE007FE007FF003FF00 ),
.INIT_07 ( 256'hFF003FF801FFC00FFC007FE007FF003FF801FF800FFC00FFE007FE003FF003FF ),
.INIT_08 ( 256'h0FFC007FE003FF003FF801FFC00FFC007FE003FF001FF801FFC00FFE007FE003 ),
.INIT_09 ( 256'h007FE003FF001FF801FFC00FFE007FF003FF801FFC00FFE007FF003FF001FF80 ),
.INIT_0A ( 256'h800FFC007FE003FF801FFC00FFE007FF003FF801FFC00FFE007FF001FF800FFC ),
.INIT_0B ( 256'hE007FF001FF800FFC007FF003FF800FFC007FE003FF801FFC00FFE007FF001FF ),
.INIT_0C ( 256'hC007FF003FF800FFE007FF001FF800FFE007FF001FF800FFE007FF001FF800FF ),
.INIT_0D ( 256'h003FF800FFE003FF801FFC007FF003FF800FFE003FF001FFC007FE003FF801FF ),
.INIT_0E ( 256'h03FF800FFC007FF001FFC007FF001FFC00FFE003FF800FFE003FF001FFC007FF ),
.INIT_0F ( 256'hFF800FFF001FFC007FF001FF800FFE003FF800FFE003FF800FFE003FF800FFE0 ),
.INIT_10 ( 256'h001FFC007FF001FFC007FF000FFE003FF800FFE003FF800FFE003FF800FFE003 ),
.INIT_11 ( 256'hFF800FFF001FFC007FF800FFE003FF8007FF001FFC007FF800FFE003FF800FFF ),
.INIT_12 ( 256'h0FFF001FFE003FF8007FF001FFE003FF8007FF001FFE003FF8007FF001FFE003 ),
.INIT_13 ( 256'h00FFF001FFE003FFC007FF800FFF001FFE003FFC007FF000FFE001FFC003FF80 ),
.INIT_14 ( 256'h00FFF000FFE001FFE003FFC003FF8007FF800FFF001FFE001FFC003FF8007FF0 ),
.INIT_15 ( 256'h07FF8007FF800FFF000FFF000FFF001FFE001FFE003FFC003FFC007FF8007FF8 ),
.INIT_16 ( 256'hFFC003FFC003FFC003FFC003FFC003FFC003FFC003FFC003FFC007FF8007FF80 ),
.INIT_17 ( 256'h001FFE001FFF000FFF000FFF000FFF8007FF8007FF8007FF8003FFC003FFC003 ),
.INIT_18 ( 256'hFF000FFF0007FF8003FFC003FFE001FFF000FFF0007FF8007FFC003FFC003FFE ),
.INIT_19 ( 256'hFFF0007FFC003FFE000FFF0007FF8003FFE001FFF000FFF8007FFC003FFE001F ),
.INIT_1A ( 256'hFFF8007FFC001FFF0007FFC001FFE000FFF8003FFE001FFF0007FFC003FFE000 ),
.INIT_1B ( 256'hFF0007FFC001FFF0003FFE000FFF8003FFE000FFF8003FFE000FFF8003FFE000 ),
.INIT_1C ( 256'h001FFF8003FFE0007FFC001FFF8003FFE0007FFC001FFF8003FFE000FFF8001F ),
.INIT_1D ( 256'hFF8001FFF0003FFF0007FFE0007FFC000FFFC001FFF8003FFF0007FFE000FFFC ),
.INIT_1E ( 256'h7FFE0007FFE0007FFE0007FFE0007FFE0007FFE000FFFC000FFFC000FFF8001F ),
.INIT_1F ( 256'h7FFE0007FFF0003FFF0001FFF8001FFFC000FFFC000FFFC000FFFE0007FFE000 ),
.INIT_20 ( 256'hFF8000FFFC0007FFF0003FFF8000FFFC0007FFE0003FFF0001FFF8000FFFC000 ),
.INIT_21 ( 256'h001FFFC0007FFF0001FFFC0007FFF0001FFFC0007FFF0001FFFC000FFFE0003F ),
.INIT_22 ( 256'hF80007FFF8000FFFF0001FFFC0003FFF80007FFF0001FFFE0003FFF8000FFFE0 ),
.INIT_23 ( 256'hFF80007FFF8000FFFF0000FFFF0000FFFF0000FFFE0001FFFE0001FFFC0003FF ),
.INIT_24 ( 256'hF0000FFFF80007FFFC0003FFFE0001FFFE0001FFFF0000FFFF0000FFFF0000FF ),
.INIT_25 ( 256'h00FFFF80003FFFE0000FFFF80003FFFC0001FFFF00007FFF80003FFFE0001FFF ),
.INIT_26 ( 256'hE00007FFFC0000FFFF80001FFFF00003FFFE00007FFFC0001FFFF00007FFFE00 ),
.INIT_27 ( 256'hFE00007FFFF00003FFFF00003FFFF00003FFFF00003FFFF00003FFFF00007FFF ),
.INIT_28 ( 256'hC00007FFFF00001FFFF80000FFFFE00003FFFF00001FFFF80000FFFFC00007FF ),
.INIT_29 ( 256'h07FFFF800007FFFF80000FFFFF00001FFFFE00003FFFF80000FFFFF00001FFFF ),
.INIT_2A ( 256'h00001FFFFF00000FFFFF800007FFFF800003FFFFC00003FFFFC00003FFFFC000 ),
.INIT_2B ( 256'h800001FFFFF000007FFFFE00000FFFFF800003FFFFE00000FFFFF800003FFFFE ),
.INIT_2C ( 256'h0003FFFFF800001FFFFF800000FFFFFC00000FFFFFC00000FFFFFC00001FFFFF ),
.INIT_2D ( 256'hFFFE000001FFFFFE000003FFFFF8000007FFFFF000001FFFFFC000007FFFFE00 ),
.INIT_2E ( 256'h1FFFFFF0000007FFFFFC000003FFFFFE000001FFFFFE000000FFFFFF000000FF ),
.INIT_2F ( 256'hFFFFFFE0000007FFFFFE0000007FFFFFE0000007FFFFFE000000FFFFFFC00000 ),
.INIT_30 ( 256'hFFC0000003FFFFFFC0000003FFFFFF8000000FFFFFFF0000001FFFFFFC000000 ),
.INIT_31 ( 256'h1FFFFFFF80000001FFFFFFF80000003FFFFFFE0000000FFFFFFF80000007FFFF ),
.INIT_32 ( 256'h007FFFFFFF800000007FFFFFFF80000000FFFFFFFE00000003FFFFFFF8000000 ),
.INIT_33 ( 256'hFFFFFFFC000000007FFFFFFFE000000007FFFFFFFC00000001FFFFFFFF000000 ),
.INIT_34 ( 256'h000000007FFFFFFFFC000000001FFFFFFFFF000000000FFFFFFFFF000000001F ),
.INIT_35 ( 256'hFFE00000000007FFFFFFFFF80000000003FFFFFFFFF8000000000FFFFFFFFFE0 ),
.INIT_36 ( 256'hE000000000007FFFFFFFFFFE00000000001FFFFFFFFFFC00000000007FFFFFFF ),
.INIT_37 ( 256'h0003FFFFFFFFFFFFC000000000000FFFFFFFFFFFF8000000000007FFFFFFFFFF ),
.INIT_38 ( 256'h0000000000000FFFFFFFFFFFFFF80000000000000FFFFFFFFFFFFFC000000000 ),
.INIT_39 ( 256'h000000000000001FFFFFFFFFFFFFFFF8000000000000000FFFFFFFFFFFFFFF80 ),
.INIT_3A ( 256'h000007FFFFFFFFFFFFFFFFFFF0000000000000000001FFFFFFFFFFFFFFFFFE00 ),
.INIT_3B ( 256'hC0000000000000000000000007FFFFFFFFFFFFFFFFFFFFFF0000000000000000 ),
.INIT_3C ( 256'hFFFFFF00000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'h000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000 ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000134 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000134_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000134_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOA<1>_UNCONNECTED , \blk00000001/sig000000fa }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000134_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000134_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000134_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000134_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000134_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000134_DOB<1>_UNCONNECTED , \blk00000001/sig000000eb }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000134_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000134_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000134_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000134_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h000FFFFF00000FFFFF800007FFFFC00003FFFFC00001FFFFE00001FFFFF00000 ),
.INIT_01 ( 256'hE00001FFFFE00000FFFFF000007FFFF800007FFFFC00003FFFFE00001FFFFE00 ),
.INIT_02 ( 256'hFFFC00003FFFFE00001FFFFE00000FFFFF000007FFFF800007FFFFC00003FFFF ),
.INIT_03 ( 256'h0FFFFF000007FFFF800003FFFFC00001FFFFE00000FFFFF00000FFFFF800007F ),
.INIT_04 ( 256'h0003FFFFC00001FFFFE00000FFFFF000007FFFF800003FFFFC00001FFFFE0000 ),
.INIT_05 ( 256'hE00001FFFFF00000FFFFF800003FFFFC00001FFFFE00000FFFFF000007FFFF80 ),
.INIT_06 ( 256'hFFE00000FFFFF000007FFFFC00003FFFFE00000FFFFF000007FFFF800003FFFF ),
.INIT_07 ( 256'hFFFFC00001FFFFF000007FFFF800003FFFFE00000FFFFF000007FFFFC00003FF ),
.INIT_08 ( 256'h0FFFFF800003FFFFC00001FFFFF000007FFFFC00001FFFFE00000FFFFF800003 ),
.INIT_09 ( 256'h007FFFFC00001FFFFE00000FFFFF800003FFFFE00000FFFFF800003FFFFE0000 ),
.INIT_0A ( 256'h000FFFFF800003FFFFE00000FFFFF800003FFFFE00000FFFFF800001FFFFF000 ),
.INIT_0B ( 256'h0007FFFFE00000FFFFF800003FFFFF000007FFFFC00001FFFFF000007FFFFE00 ),
.INIT_0C ( 256'h0007FFFFC00000FFFFF800001FFFFF000007FFFFE00000FFFFF800001FFFFF00 ),
.INIT_0D ( 256'h003FFFFF000003FFFFE000007FFFFC00000FFFFFC00001FFFFF800003FFFFE00 ),
.INIT_0E ( 256'h03FFFFF000007FFFFE000007FFFFE00000FFFFFC00000FFFFFC00001FFFFF800 ),
.INIT_0F ( 256'hFFFFF000001FFFFF800001FFFFF000003FFFFF000003FFFFF000003FFFFF0000 ),
.INIT_10 ( 256'hFFE000007FFFFE000007FFFFF000003FFFFF000003FFFFF000003FFFFF000003 ),
.INIT_11 ( 256'h00000FFFFFE000007FFFFF000003FFFFF800001FFFFF800000FFFFFC00000FFF ),
.INIT_12 ( 256'h0FFFFFE000003FFFFF800001FFFFFC000007FFFFE000003FFFFF800001FFFFFC ),
.INIT_13 ( 256'hFF000001FFFFFC000007FFFFF000001FFFFFC000007FFFFF000001FFFFFC0000 ),
.INIT_14 ( 256'h00FFFFFF000001FFFFFC000003FFFFF800000FFFFFE000001FFFFFC000007FFF ),
.INIT_15 ( 256'hF8000007FFFFF000000FFFFFF000001FFFFFE000003FFFFFC000007FFFFF8000 ),
.INIT_16 ( 256'hFFFFFC000003FFFFFC000003FFFFFC000003FFFFFC000003FFFFF8000007FFFF ),
.INIT_17 ( 256'h001FFFFFE000000FFFFFF000000FFFFFF8000007FFFFF8000003FFFFFC000003 ),
.INIT_18 ( 256'h00000FFFFFF8000003FFFFFC000001FFFFFF0000007FFFFF8000003FFFFFC000 ),
.INIT_19 ( 256'h0000007FFFFFC000000FFFFFF8000003FFFFFE000000FFFFFF8000003FFFFFE0 ),
.INIT_1A ( 256'h0000007FFFFFE0000007FFFFFE000000FFFFFFC000001FFFFFF8000003FFFFFF ),
.INIT_1B ( 256'h000007FFFFFE0000003FFFFFF0000003FFFFFF0000003FFFFFF0000003FFFFFF ),
.INIT_1C ( 256'h001FFFFFFC0000007FFFFFE0000003FFFFFF8000001FFFFFFC000000FFFFFFE0 ),
.INIT_1D ( 256'hFFFFFE0000003FFFFFF80000007FFFFFF0000001FFFFFFC0000007FFFFFF0000 ),
.INIT_1E ( 256'h80000007FFFFFF80000007FFFFFF80000007FFFFFF0000000FFFFFFF0000001F ),
.INIT_1F ( 256'h7FFFFFF80000003FFFFFFE0000001FFFFFFF0000000FFFFFFF00000007FFFFFF ),
.INIT_20 ( 256'h000000FFFFFFF80000003FFFFFFF00000007FFFFFFC0000001FFFFFFF0000000 ),
.INIT_21 ( 256'hFFE00000007FFFFFFE00000007FFFFFFE00000007FFFFFFE0000000FFFFFFFC0 ),
.INIT_22 ( 256'hFFFFF80000000FFFFFFFE00000003FFFFFFF80000001FFFFFFFC0000000FFFFF ),
.INIT_23 ( 256'hFFFFFF80000000FFFFFFFF00000000FFFFFFFF00000001FFFFFFFE00000003FF ),
.INIT_24 ( 256'hFFFFF000000007FFFFFFFC00000001FFFFFFFE00000000FFFFFFFF00000000FF ),
.INIT_25 ( 256'hFF000000003FFFFFFFF000000003FFFFFFFE000000007FFFFFFFC00000001FFF ),
.INIT_26 ( 256'h000007FFFFFFFF000000001FFFFFFFFC000000007FFFFFFFE000000007FFFFFF ),
.INIT_27 ( 256'hFFFFFF8000000003FFFFFFFFC000000003FFFFFFFFC000000003FFFFFFFF8000 ),
.INIT_28 ( 256'h000007FFFFFFFFE000000000FFFFFFFFFC000000001FFFFFFFFF0000000007FF ),
.INIT_29 ( 256'hF80000000007FFFFFFFFF0000000001FFFFFFFFFC000000000FFFFFFFFFE0000 ),
.INIT_2A ( 256'hFFFFE0000000000FFFFFFFFFF80000000003FFFFFFFFFC0000000003FFFFFFFF ),
.INIT_2B ( 256'hFFFFFE00000000007FFFFFFFFFF00000000003FFFFFFFFFF00000000003FFFFF ),
.INIT_2C ( 256'hFFFC00000000001FFFFFFFFFFF00000000000FFFFFFFFFFF00000000001FFFFF ),
.INIT_2D ( 256'h0000000001FFFFFFFFFFFC000000000007FFFFFFFFFFE000000000007FFFFFFF ),
.INIT_2E ( 256'h1FFFFFFFFFFFF8000000000003FFFFFFFFFFFE000000000000FFFFFFFFFFFF00 ),
.INIT_2F ( 256'h00000000000007FFFFFFFFFFFF80000000000007FFFFFFFFFFFF000000000000 ),
.INIT_30 ( 256'hFFFFFFFFFC00000000000003FFFFFFFFFFFFF00000000000001FFFFFFFFFFFFF ),
.INIT_31 ( 256'h1FFFFFFFFFFFFFFE000000000000003FFFFFFFFFFFFFF000000000000007FFFF ),
.INIT_32 ( 256'h007FFFFFFFFFFFFFFF8000000000000000FFFFFFFFFFFFFFFC00000000000000 ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFF800000000000000007FFFFFFFFFFFFFFFE00000000000000 ),
.INIT_34 ( 256'hFFFFFFFF8000000000000000001FFFFFFFFFFFFFFFFFF000000000000000001F ),
.INIT_35 ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFC0000000000000000000FFFFFFFFFFF ),
.INIT_36 ( 256'hFFFFFFFFFFFF80000000000000000000001FFFFFFFFFFFFFFFFFFFFF80000000 ),
.INIT_37 ( 256'h0003FFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000007FFFFFFFFFF ),
.INIT_38 ( 256'h0000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000 ),
.INIT_39 ( 256'h000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000 ),
.INIT_3A ( 256'h000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000 ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFF800000000000000000000000000000000000000 ),
.INIT_3C ( 256'h00000000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000 ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000133 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000133_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000133_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOA<1>_UNCONNECTED , \blk00000001/sig000000fb }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000133_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000133_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000133_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000133_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000133_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000133_DOB<1>_UNCONNECTED , \blk00000001/sig000000ec }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000133_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000133_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000133_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000133_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h000FFFFFFFFFF00000000007FFFFFFFFFC0000000001FFFFFFFFFE0000000000 ),
.INIT_01 ( 256'h000001FFFFFFFFFF00000000007FFFFFFFFF80000000003FFFFFFFFFE0000000 ),
.INIT_02 ( 256'h000000003FFFFFFFFFE0000000000FFFFFFFFFF80000000007FFFFFFFFFC0000 ),
.INIT_03 ( 256'hF00000000007FFFFFFFFFC0000000001FFFFFFFFFF0000000000FFFFFFFFFF80 ),
.INIT_04 ( 256'hFFFC0000000001FFFFFFFFFF00000000007FFFFFFFFFC0000000001FFFFFFFFF ),
.INIT_05 ( 256'hFFFFFE0000000000FFFFFFFFFFC0000000001FFFFFFFFFF00000000007FFFFFF ),
.INIT_06 ( 256'hFFFFFFFF00000000007FFFFFFFFFC0000000000FFFFFFFFFF80000000003FFFF ),
.INIT_07 ( 256'hFFFFFFFFFE00000000007FFFFFFFFFC0000000000FFFFFFFFFF80000000003FF ),
.INIT_08 ( 256'h0FFFFFFFFFFC0000000001FFFFFFFFFF80000000001FFFFFFFFFF00000000003 ),
.INIT_09 ( 256'h007FFFFFFFFFE0000000000FFFFFFFFFFC0000000000FFFFFFFFFFC000000000 ),
.INIT_0A ( 256'h000FFFFFFFFFFC0000000000FFFFFFFFFFC0000000000FFFFFFFFFFE00000000 ),
.INIT_0B ( 256'h0007FFFFFFFFFF00000000003FFFFFFFFFF80000000001FFFFFFFFFF80000000 ),
.INIT_0C ( 256'h0007FFFFFFFFFF00000000001FFFFFFFFFF80000000000FFFFFFFFFFE0000000 ),
.INIT_0D ( 256'h003FFFFFFFFFFC00000000007FFFFFFFFFF00000000001FFFFFFFFFFC0000000 ),
.INIT_0E ( 256'h03FFFFFFFFFF800000000007FFFFFFFFFF00000000000FFFFFFFFFFE00000000 ),
.INIT_0F ( 256'hFFFFFFFFFFE00000000001FFFFFFFFFFC00000000003FFFFFFFFFFC000000000 ),
.INIT_10 ( 256'hFFFFFFFF800000000007FFFFFFFFFFC00000000003FFFFFFFFFFC00000000003 ),
.INIT_11 ( 256'hFFFFF000000000007FFFFFFFFFFC00000000001FFFFFFFFFFF00000000000FFF ),
.INIT_12 ( 256'hF000000000003FFFFFFFFFFE000000000007FFFFFFFFFFC00000000001FFFFFF ),
.INIT_13 ( 256'h00000001FFFFFFFFFFF800000000001FFFFFFFFFFF800000000001FFFFFFFFFF ),
.INIT_14 ( 256'h00FFFFFFFFFFFE000000000003FFFFFFFFFFF000000000001FFFFFFFFFFF8000 ),
.INIT_15 ( 256'hFFFFFFF800000000000FFFFFFFFFFFE000000000003FFFFFFFFFFF8000000000 ),
.INIT_16 ( 256'h000000000003FFFFFFFFFFFC000000000003FFFFFFFFFFFC000000000007FFFF ),
.INIT_17 ( 256'h001FFFFFFFFFFFF000000000000FFFFFFFFFFFF8000000000003FFFFFFFFFFFC ),
.INIT_18 ( 256'hFFFFF0000000000003FFFFFFFFFFFE0000000000007FFFFFFFFFFFC000000000 ),
.INIT_19 ( 256'h0000007FFFFFFFFFFFF0000000000003FFFFFFFFFFFF0000000000003FFFFFFF ),
.INIT_1A ( 256'hFFFFFF80000000000007FFFFFFFFFFFF0000000000001FFFFFFFFFFFFC000000 ),
.INIT_1B ( 256'h000007FFFFFFFFFFFFC0000000000003FFFFFFFFFFFFC0000000000003FFFFFF ),
.INIT_1C ( 256'hFFE00000000000007FFFFFFFFFFFFC0000000000001FFFFFFFFFFFFF00000000 ),
.INIT_1D ( 256'hFFFFFFFFFFFFC00000000000007FFFFFFFFFFFFE00000000000007FFFFFFFFFF ),
.INIT_1E ( 256'h00000007FFFFFFFFFFFFF800000000000007FFFFFFFFFFFFF00000000000001F ),
.INIT_1F ( 256'h800000000000003FFFFFFFFFFFFFE00000000000000FFFFFFFFFFFFFF8000000 ),
.INIT_20 ( 256'hFFFFFF000000000000003FFFFFFFFFFFFFF800000000000001FFFFFFFFFFFFFF ),
.INIT_21 ( 256'hFFFFFFFFFF8000000000000007FFFFFFFFFFFFFF800000000000000FFFFFFFFF ),
.INIT_22 ( 256'hFFFFFFFFFFFFF0000000000000003FFFFFFFFFFFFFFE000000000000000FFFFF ),
.INIT_23 ( 256'hFFFFFFFFFFFFFF0000000000000000FFFFFFFFFFFFFFFE0000000000000003FF ),
.INIT_24 ( 256'hFFFFFFFFFFFFF80000000000000001FFFFFFFFFFFFFFFF0000000000000000FF ),
.INIT_25 ( 256'hFFFFFFFFFFC00000000000000003FFFFFFFFFFFFFFFF80000000000000001FFF ),
.INIT_26 ( 256'hFFFFF800000000000000001FFFFFFFFFFFFFFFFF800000000000000007FFFFFF ),
.INIT_27 ( 256'h0000000000000003FFFFFFFFFFFFFFFFFC000000000000000003FFFFFFFFFFFF ),
.INIT_28 ( 256'h000007FFFFFFFFFFFFFFFFFF0000000000000000001FFFFFFFFFFFFFFFFFF800 ),
.INIT_29 ( 256'hFFFFFFFFFFF80000000000000000001FFFFFFFFFFFFFFFFFFF00000000000000 ),
.INIT_2A ( 256'h000000000000000FFFFFFFFFFFFFFFFFFFFC00000000000000000003FFFFFFFF ),
.INIT_2B ( 256'hFFFFFFFFFFFFFFFF8000000000000000000003FFFFFFFFFFFFFFFFFFFFC00000 ),
.INIT_2C ( 256'h000000000000001FFFFFFFFFFFFFFFFFFFFFF0000000000000000000001FFFFF ),
.INIT_2D ( 256'hFFFFFFFFFE000000000000000000000007FFFFFFFFFFFFFFFFFFFFFF80000000 ),
.INIT_2E ( 256'h1FFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000000FFFFFFFFFFFFFF ),
.INIT_2F ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000 ),
.INIT_30 ( 256'h000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000 ),
.INIT_31 ( 256'hE000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFF80000 ),
.INIT_32 ( 256'hFF80000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_33 ( 256'h0000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'h000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0 ),
.INIT_35 ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000 ),
.INIT_36 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000 ),
.INIT_37 ( 256'hFFFC00000000000000000000000000000000000000000000000007FFFFFFFFFF ),
.INIT_38 ( 256'h0000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFE0000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000000000000000000000 ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000132 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000132_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000132_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOA<1>_UNCONNECTED , \blk00000001/sig000000fc }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000132_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000132_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000132_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000132_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000132_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000132_DOB<1>_UNCONNECTED , \blk00000001/sig000000ed }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000132_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000132_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000132_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000132_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'hFFF000000000000000000007FFFFFFFFFFFFFFFFFFFE00000000000000000000 ),
.INIT_01 ( 256'h000001FFFFFFFFFFFFFFFFFFFF800000000000000000003FFFFFFFFFFFFFFFFF ),
.INIT_02 ( 256'hFFFFFFFFC00000000000000000000FFFFFFFFFFFFFFFFFFFF800000000000000 ),
.INIT_03 ( 256'h000000000007FFFFFFFFFFFFFFFFFFFE00000000000000000000FFFFFFFFFFFF ),
.INIT_04 ( 256'hFFFFFFFFFFFFFE000000000000000000007FFFFFFFFFFFFFFFFFFFE000000000 ),
.INIT_05 ( 256'h0000000000000000FFFFFFFFFFFFFFFFFFFFE000000000000000000007FFFFFF ),
.INIT_06 ( 256'hFFFFFFFFFFFFFFFFFF800000000000000000000FFFFFFFFFFFFFFFFFFFFC0000 ),
.INIT_07 ( 256'h000000000000000000007FFFFFFFFFFFFFFFFFFFF000000000000000000003FF ),
.INIT_08 ( 256'h0FFFFFFFFFFFFFFFFFFFFE000000000000000000001FFFFFFFFFFFFFFFFFFFFC ),
.INIT_09 ( 256'hFF800000000000000000000FFFFFFFFFFFFFFFFFFFFF00000000000000000000 ),
.INIT_0A ( 256'h000FFFFFFFFFFFFFFFFFFFFF000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'hFFF8000000000000000000003FFFFFFFFFFFFFFFFFFFFE000000000000000000 ),
.INIT_0C ( 256'h0007FFFFFFFFFFFFFFFFFFFFE000000000000000000000FFFFFFFFFFFFFFFFFF ),
.INIT_0D ( 256'hFFC0000000000000000000007FFFFFFFFFFFFFFFFFFFFE000000000000000000 ),
.INIT_0E ( 256'h03FFFFFFFFFFFFFFFFFFFFF8000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0F ( 256'h0000000000000000000001FFFFFFFFFFFFFFFFFFFFFC00000000000000000000 ),
.INIT_10 ( 256'hFFFFFFFFFFFFFFFFFFF80000000000000000000003FFFFFFFFFFFFFFFFFFFFFC ),
.INIT_11 ( 256'h00000000000000007FFFFFFFFFFFFFFFFFFFFFE0000000000000000000000FFF ),
.INIT_12 ( 256'hFFFFFFFFFFFFC00000000000000000000007FFFFFFFFFFFFFFFFFFFFFE000000 ),
.INIT_13 ( 256'h00000001FFFFFFFFFFFFFFFFFFFFFFE00000000000000000000001FFFFFFFFFF ),
.INIT_14 ( 256'hFF000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFE000000000000000 ),
.INIT_15 ( 256'hFFFFFFFFFFFFFFFFFFF000000000000000000000003FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h000000000003FFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000007FFFF ),
.INIT_17 ( 256'hFFE000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFC000000000000 ),
.INIT_18 ( 256'hFFFFFFFFFFFFFFFFFC0000000000000000000000007FFFFFFFFFFFFFFFFFFFFF ),
.INIT_19 ( 256'h0000007FFFFFFFFFFFFFFFFFFFFFFFFC0000000000000000000000003FFFFFFF ),
.INIT_1A ( 256'h00000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000 ),
.INIT_1B ( 256'hFFFFF800000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFC000000 ),
.INIT_1C ( 256'hFFFFFFFFFFFFFFFF800000000000000000000000001FFFFFFFFFFFFFFFFFFFFF ),
.INIT_1D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000007FFFFFFFFFF ),
.INIT_1E ( 256'h00000007FFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000001F ),
.INIT_1F ( 256'h000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000 ),
.INIT_20 ( 256'h000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000000000000 ),
.INIT_21 ( 256'h00000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000 ),
.INIT_22 ( 256'h00000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000 ),
.INIT_23 ( 256'h000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00 ),
.INIT_24 ( 256'h000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00 ),
.INIT_25 ( 256'h0000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000 ),
.INIT_26 ( 256'h00000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000 ),
.INIT_27 ( 256'h0000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000 ),
.INIT_28 ( 256'h000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000 ),
.INIT_29 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000000000000000 ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFF00000000000000000000000000000000000000003FFFFFFFF ),
.INIT_2B ( 256'h00000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE00000 ),
.INIT_2D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000000000 ),
.INIT_2E ( 256'hE0000000000000000000000000000000000000000000000000FFFFFFFFFFFFFF ),
.INIT_2F ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_30 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFC0000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_32 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000000000000000000000 ),
.INIT_35 ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000 ),
.INIT_38 ( 256'h0000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'hFFFFF80000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000131 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000131_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000131_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOA<1>_UNCONNECTED , \blk00000001/sig000000fd }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000131_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000131_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000131_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000131_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000131_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000131_DOB<1>_UNCONNECTED , \blk00000001/sig000000ee }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000131_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000131_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000131_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000131_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
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.INIT_01 ( 256'hFFFFFE00000000000000000000000000000000000000003FFFFFFFFFFFFFFFFF ),
.INIT_02 ( 256'h00000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_03 ( 256'h000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000 ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF800000000000000000000000000000 ),
.INIT_05 ( 256'hFFFFFFFFFFFFFFFF000000000000000000000000000000000000000007FFFFFF ),
.INIT_06 ( 256'h000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_07 ( 256'h000000000000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00 ),
.INIT_08 ( 256'h0FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000 ),
.INIT_09 ( 256'hFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000000000000 ),
.INIT_0A ( 256'hFFF000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h0000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0C ( 256'h0007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000 ),
.INIT_0D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000000000000000000 ),
.INIT_0E ( 256'hFC0000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0F ( 256'h0000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_10 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000000000000000000 ),
.INIT_11 ( 256'hFFFFFFFFFFFFFFFF800000000000000000000000000000000000000000000FFF ),
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.INIT_13 ( 256'h00000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000 ),
.INIT_14 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000000000000000 ),
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.INIT_16 ( 256'h000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000 ),
.INIT_17 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFF ),
.INIT_19 ( 256'h0000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC0000000 ),
.INIT_1A ( 256'hFFFFFFFFFFFFFFFFFFF800000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h00000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE000000000000000000000 ),
.INIT_1D ( 256'h000000000000000000000000000000000000000000000000000007FFFFFFFFFF ),
.INIT_1E ( 256'h00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0 ),
.INIT_1F ( 256'hFFFFFFFFFFFFFFC0000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_21 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFF800000000000000000000000000000000000000 ),
.INIT_22 ( 256'h00000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_23 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000 ),
.INIT_24 ( 256'h000000000000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_25 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000000000000000000 ),
.INIT_26 ( 256'h00000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_27 ( 256'hFFFFFFFFFFFFFFFC000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000 ),
.INIT_2B ( 256'h00000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'hFFFFFFFFFFFFFFE0000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2E ( 256'h00000000000000000000000000000000000000000000000000FFFFFFFFFFFFFF ),
.INIT_2F ( 256'hFFFFFFFFFFFFF800000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_31 ( 256'h0000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000000000000 ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_35 ( 256'h00000000000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'hFFFFFFFFFFFFF000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk00000130 (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk00000130_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk00000130_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOA<1>_UNCONNECTED , \blk00000001/sig000000fe }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk00000130_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk00000130_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk00000130_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk00000130_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk00000130_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk00000130_DOB<1>_UNCONNECTED , \blk00000001/sig000000ef }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk00000130_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000130_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk00000130_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk00000130_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
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.INIT_04 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
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.INIT_0C ( 256'h0007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
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.INIT_17 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000007FFFFFFFFFFFFFFFFFFFFF ),
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.INIT_1B ( 256'h00000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000 ),
.INIT_1E ( 256'h00000007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'hFFFFFFFFFFFFFFFFFFFFC0000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
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.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE0000000000000000000000000000000000 ),
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.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'hFFFFF80000000000000000000000000000000000000000000000000000000000 ),
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.INIT_2B ( 256'h00000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000 ),
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.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_38 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
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.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
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.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
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.EN_RSTRAM_A ( "TRUE" ),
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.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.RST_PRIORITY_A ( "CE" ),
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.SRVAL_A ( 36'h000000000 ),
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.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000012f (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk0000012f_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk0000012f_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOA<1>_UNCONNECTED , \blk00000001/sig000000ff }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk0000012f_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk0000012f_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk0000012f_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk0000012f_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk0000012f_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DOB<1>_UNCONNECTED , \blk00000001/sig000000f0 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk0000012f_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012f_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012f_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012f_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000000 ),
.INIT_03 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_04 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000007FFFFFF ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'hFFFFFFFFFFFFFFFFFFFF80000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_09 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0A ( 256'h000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'hFFF8000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0F ( 256'h0000000000000000000001FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80000000000000000000000000000 ),
.INIT_13 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_14 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000000000000000000 ),
.INIT_19 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1B ( 256'h00000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'hFFFFFFF800000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_20 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_21 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_22 ( 256'h00000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'hFFFFFFFFFFFFFFFFFFFFFFE00000000000000000000000000000000000000000 ),
.INIT_27 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_28 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_29 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2B ( 256'h00000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000000000000000 ),
.INIT_32 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_35 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_38 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000012e (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk0000012e_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk0000012e_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOA<1>_UNCONNECTED , \blk00000001/sig00000100 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk0000012e_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk0000012e_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk0000012e_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk0000012e_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk0000012e_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DOB<1>_UNCONNECTED , \blk00000001/sig000000f1 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk0000012e_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012e_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012e_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012e_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8000000 ),
.INIT_06 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_07 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_08 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_09 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0A ( 256'h000000000000000000000000000000000000000000000FFFFFFFFFFFFFFFFFFF ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'hFFFFFFFFFFFFFFFFFFFFFE000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_11 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_12 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_13 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_14 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000000000 ),
.INIT_1C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_20 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_21 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_22 ( 256'h00000000000000000000000000003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000 ),
.INIT_2C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_30 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_31 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_32 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_35 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_38 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000012d (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk0000012d_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk0000012d_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOA<1>_UNCONNECTED , \blk00000001/sig00000101 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk0000012d_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk0000012d_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk0000012d_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk0000012d_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk0000012d_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DOB<1>_UNCONNECTED , \blk00000001/sig000000f2 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk0000012d_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012d_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012d_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012d_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000 ),
.INIT_0B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_0F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_10 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_11 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_12 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_13 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_14 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000003FFFFFFFFFFFFFFFFFFFFF ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFC00000000000000000000000000000000000 ),
.INIT_23 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_24 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_25 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_26 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_27 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_28 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_29 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_30 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_31 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_32 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_35 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_38 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000012c (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk0000012c_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk0000012c_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOA<1>_UNCONNECTED , \blk00000001/sig00000102 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk0000012c_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk0000012c_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk0000012c_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk0000012c_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk0000012c_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DOB<1>_UNCONNECTED , \blk00000001/sig000000f3 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk0000012c_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012c_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012c_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012c_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
RAMB16BWER #(
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC000000000000000000000 ),
.INIT_16 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_17 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_18 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_19 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_1F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_20 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_21 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_22 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_23 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_24 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_25 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_26 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_27 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_28 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_29 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_2F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_30 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_31 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_32 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_33 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_34 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_35 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_36 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_37 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_38 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_39 ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3A ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3B ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3C ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3D ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3E ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_3F ( 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.DATA_WIDTH_A ( 1 ),
.DATA_WIDTH_B ( 1 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "TRUE" ),
.EN_RSTRAM_B ( "TRUE" ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.RSTTYPE ( "SYNC" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_FILE ( "NONE" ))
\blk00000001/blk0000012b (
.REGCEA(\blk00000001/sig00000014 ),
.CLKA(aclk),
.ENB(\blk00000001/sig00000013 ),
.RSTB(\blk00000001/sig00000014 ),
.CLKB(aclk),
.REGCEB(\blk00000001/sig00000014 ),
.RSTA(\blk00000001/sig00000014 ),
.ENA(\blk00000001/sig00000013 ),
.DIPA({\NLW_blk00000001/blk0000012b_DIPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIPA<0>_UNCONNECTED }),
.WEA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\NLW_blk00000001/blk0000012b_DOA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOA<1>_UNCONNECTED , \blk00000001/sig00000103 }),
.ADDRA({\blk00000001/sig000000e5 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 , \blk00000001/sig000000e1 ,
\blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de , \blk00000001/sig000000dd , \blk00000001/sig000000dc ,
\blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 ,
\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\NLW_blk00000001/blk0000012b_DIB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIB<0>_UNCONNECTED
}),
.DOPA({\NLW_blk00000001/blk0000012b_DOPA<3>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOPA<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOPA<1>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOPA<0>_UNCONNECTED }),
.DIPB({\NLW_blk00000001/blk0000012b_DIPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIPB<0>_UNCONNECTED }),
.DOPB({\NLW_blk00000001/blk0000012b_DOPB<3>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOPB<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOPB<1>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOPB<0>_UNCONNECTED }),
.DOB({\NLW_blk00000001/blk0000012b_DOB<31>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<29>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<27>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<25>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<23>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<21>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<19>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<17>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<15>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<13>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DOB<11>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<10>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOB<8>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<7>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOB<5>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<4>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DOB<2>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DOB<1>_UNCONNECTED , \blk00000001/sig000000f4 }),
.WEB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIA({\NLW_blk00000001/blk0000012b_DIA<31>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<29>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<27>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<25>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<23>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<21>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<19>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<17>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<15>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<13>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000012b_DIA<11>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<10>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<9>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIA<8>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<7>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<6>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIA<5>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<4>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<3>_UNCONNECTED
, \NLW_blk00000001/blk0000012b_DIA<2>_UNCONNECTED , \NLW_blk00000001/blk0000012b_DIA<1>_UNCONNECTED , \blk00000001/sig00000014 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000012a (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig0000014e )
);
LUT1 #(
.INIT ( 2'h2 ))
\blk00000001/blk00000129 (
.I0(\blk00000001/sig00000137 ),
.O(\blk00000001/sig0000014d )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000128 (
.I0(\blk00000001/sig00000136 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000a3 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000127 (
.I0(\blk00000001/sig00000135 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000a2 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000126 (
.I0(\blk00000001/sig00000134 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000a1 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000125 (
.I0(\blk00000001/sig00000133 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000a0 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000124 (
.I0(\blk00000001/sig00000132 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009f )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000123 (
.I0(\blk00000001/sig00000131 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009e )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000122 (
.I0(\blk00000001/sig00000130 ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009d )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000121 (
.I0(\blk00000001/sig00000079 ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig00000126 ),
.O(\blk00000001/sig000000c3 )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000120 (
.I0(\blk00000001/sig00000071 ),
.I1(\blk00000001/sig0000011d ),
.I2(\blk00000001/sig0000011c ),
.O(\blk00000001/sig000000bc )
);
LUT4 #(
.INIT ( 16'h6AAA ))
\blk00000001/blk0000011f (
.I0(\blk00000001/sig00000070 ),
.I1(\blk00000001/sig0000011d ),
.I2(\blk00000001/sig0000011c ),
.I3(\blk00000001/sig00000071 ),
.O(\blk00000001/sig000000bd )
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
\blk00000001/blk0000011e (
.I0(\blk00000001/sig0000006e ),
.I1(\blk00000001/sig0000011d ),
.I2(\blk00000001/sig0000011c ),
.I3(\blk00000001/sig00000071 ),
.I4(\blk00000001/sig00000070 ),
.I5(\blk00000001/sig0000006f ),
.O(\blk00000001/sig000000bf )
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
\blk00000001/blk0000011d (
.I0(\blk00000001/sig0000006f ),
.I1(\blk00000001/sig0000011d ),
.I2(\blk00000001/sig0000011c ),
.I3(\blk00000001/sig00000071 ),
.I4(\blk00000001/sig00000070 ),
.O(\blk00000001/sig000000be )
);
LUT4 #(
.INIT ( 16'h6AAA ))
\blk00000001/blk0000011c (
.I0(\blk00000001/sig00000078 ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig00000126 ),
.I3(\blk00000001/sig00000079 ),
.O(\blk00000001/sig000000c4 )
);
LUT6 #(
.INIT ( 64'h6AAAAAAAAAAAAAAA ))
\blk00000001/blk0000011b (
.I0(\blk00000001/sig00000076 ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig00000126 ),
.I3(\blk00000001/sig00000079 ),
.I4(\blk00000001/sig00000078 ),
.I5(\blk00000001/sig00000077 ),
.O(\blk00000001/sig000000c6 )
);
LUT5 #(
.INIT ( 32'h6AAAAAAA ))
\blk00000001/blk0000011a (
.I0(\blk00000001/sig00000077 ),
.I1(\blk00000001/sig00000127 ),
.I2(\blk00000001/sig00000126 ),
.I3(\blk00000001/sig00000079 ),
.I4(\blk00000001/sig00000078 ),
.O(\blk00000001/sig000000c5 )
);
LUT3 #(
.INIT ( 8'h54 ))
\blk00000001/blk00000119 (
.I0(\blk00000001/sig00000015 ),
.I1(\blk00000001/sig00000019 ),
.I2(\blk00000001/sig00000018 ),
.O(\blk00000001/sig0000014c )
);
LUT3 #(
.INIT ( 8'h98 ))
\blk00000001/blk00000118 (
.I0(\blk00000001/sig00000018 ),
.I1(\blk00000001/sig00000015 ),
.I2(\blk00000001/sig00000019 ),
.O(\blk00000001/sig0000014b )
);
LUT3 #(
.INIT ( 8'hA8 ))
\blk00000001/blk00000117 (
.I0(\blk00000001/sig00000019 ),
.I1(\blk00000001/sig00000018 ),
.I2(\blk00000001/sig00000015 ),
.O(\blk00000001/sig0000014a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000001/blk00000116 (
.C(aclk),
.D(\blk00000001/sig0000014c ),
.Q(\blk00000001/sig00000015 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000001/blk00000115 (
.C(aclk),
.D(\blk00000001/sig0000014b ),
.Q(\blk00000001/sig00000018 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000001/blk00000114 (
.C(aclk),
.D(\blk00000001/sig0000014a ),
.Q(\blk00000001/sig00000019 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000113 (
.I0(\blk00000001/sig0000012f ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009c )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000112 (
.I0(\blk00000001/sig0000012e ),
.I1(\blk00000001/sig00000146 ),
.I2(\blk00000001/sig000000bb ),
.O(\blk00000001/sig0000009b )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000111 (
.I0(\blk00000001/sig0000012d ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig0000009a )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk00000110 (
.I0(\blk00000001/sig0000012c ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000099 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk0000010f (
.I0(\blk00000001/sig0000012b ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000098 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk0000010e (
.I0(\blk00000001/sig0000012a ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000097 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk0000010d (
.I0(\blk00000001/sig00000129 ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000096 )
);
LUT3 #(
.INIT ( 8'h96 ))
\blk00000001/blk0000010c (
.I0(\blk00000001/sig00000128 ),
.I1(\blk00000001/sig0000014e ),
.I2(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000095 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000010b (
.I0(\blk00000001/sig0000014e ),
.I1(\blk00000001/sig00000146 ),
.O(\blk00000001/sig00000084 )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\blk00000001/blk0000010a (
.I0(\blk00000001/sig0000006e ),
.I1(\blk00000001/sig0000006f ),
.I2(\blk00000001/sig00000070 ),
.I3(\blk00000001/sig00000071 ),
.I4(\blk00000001/sig0000011c ),
.I5(\blk00000001/sig0000011d ),
.O(\blk00000001/sig0000006a )
);
LUT6 #(
.INIT ( 64'h7FFFFFFFFFFFFFFF ))
\blk00000001/blk00000109 (
.I0(\blk00000001/sig00000076 ),
.I1(\blk00000001/sig00000077 ),
.I2(\blk00000001/sig00000078 ),
.I3(\blk00000001/sig00000079 ),
.I4(\blk00000001/sig00000126 ),
.I5(\blk00000001/sig00000127 ),
.O(\blk00000001/sig00000069 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000108 (
.I0(\blk00000001/sig00000127 ),
.I1(\blk00000001/sig00000126 ),
.O(\blk00000001/sig0000007a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000107 (
.I0(\blk00000001/sig0000011d ),
.I1(\blk00000001/sig0000011c ),
.O(\blk00000001/sig00000072 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000106 (
.I0(\blk00000001/sig00000146 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000105 (
.I0(\blk00000001/sig00000026 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000104 (
.I0(\blk00000001/sig00000025 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000103 (
.I0(\blk00000001/sig00000024 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000102 (
.I0(\blk00000001/sig00000023 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000101 (
.I0(\blk00000001/sig00000022 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000100 (
.I0(\blk00000001/sig00000021 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ff (
.I0(\blk00000001/sig00000020 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fe (
.I0(\blk00000001/sig0000001f ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fd (
.I0(\blk00000001/sig0000001e ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fc (
.I0(\blk00000001/sig0000002a ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fb (
.I0(\blk00000001/sig00000029 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000fa (
.I0(\blk00000001/sig00000028 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f9 (
.I0(\blk00000001/sig00000027 ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f8 (
.I0(\blk00000001/sig0000001d ),
.I1(\blk00000001/sig0000002b ),
.O(\blk00000001/sig000000ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f7 (
.I0(\blk00000001/sig00000145 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f6 (
.I0(\blk00000001/sig00000144 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f5 (
.I0(\blk00000001/sig00000143 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f4 (
.I0(\blk00000001/sig00000142 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f3 (
.I0(\blk00000001/sig00000141 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f2 (
.I0(\blk00000001/sig00000140 ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f1 (
.I0(\blk00000001/sig0000013f ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000f0 (
.I0(\blk00000001/sig0000013e ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ef (
.I0(\blk00000001/sig0000013d ),
.I1(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ee (
.I0(\blk00000001/sig0000013c ),
.I1(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000000b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ed (
.I0(\blk00000001/sig0000013b ),
.I1(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000000b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ec (
.I0(\blk00000001/sig0000013a ),
.I1(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000000af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000eb (
.I0(\blk00000001/sig00000139 ),
.I1(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000000ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000000ea (
.I0(\blk00000001/sig00000138 ),
.I1(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000000ad )
);
LUT4 #(
.INIT ( 16'hAA6A ))
\blk00000001/blk000000e9 (
.I0(\blk00000001/sig0000006b ),
.I1(\blk00000001/sig0000006c ),
.I2(\blk00000001/sig0000006d ),
.I3(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000000c2 )
);
LUT4 #(
.INIT ( 16'hAA6A ))
\blk00000001/blk000000e8 (
.I0(\blk00000001/sig00000073 ),
.I1(\blk00000001/sig00000074 ),
.I2(\blk00000001/sig00000075 ),
.I3(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000000c9 )
);
LUT3 #(
.INIT ( 8'hA6 ))
\blk00000001/blk000000e7 (
.I0(\blk00000001/sig0000006c ),
.I1(\blk00000001/sig0000006d ),
.I2(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000000c1 )
);
LUT3 #(
.INIT ( 8'hA6 ))
\blk00000001/blk000000e6 (
.I0(\blk00000001/sig00000074 ),
.I1(\blk00000001/sig00000075 ),
.I2(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000000c8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk000000e5 (
.I0(\blk00000001/sig0000006d ),
.I1(\blk00000001/sig0000006a ),
.O(\blk00000001/sig000000c0 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk000000e4 (
.I0(\blk00000001/sig00000075 ),
.I1(\blk00000001/sig00000069 ),
.O(\blk00000001/sig000000c7 )
);
LUT3 #(
.INIT ( 8'h01 ))
\blk00000001/blk000000e3 (
.I0(\blk00000001/sig00000019 ),
.I1(\blk00000001/sig00000018 ),
.I2(\blk00000001/sig00000015 ),
.O(\blk00000001/sig00000017 )
);
LUT1 #(
.INIT ( 2'h1 ))
\blk00000001/blk000000e2 (
.I0(\blk00000001/sig0000001c ),
.O(\blk00000001/sig00000016 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e1 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a5 ),
.Q(\blk00000001/sig0000011e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e0 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a6 ),
.Q(\blk00000001/sig0000011f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000df (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a7 ),
.Q(\blk00000001/sig00000120 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000de (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a8 ),
.Q(\blk00000001/sig00000121 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dd (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a9 ),
.Q(\blk00000001/sig00000122 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dc (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000aa ),
.Q(\blk00000001/sig00000123 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000db (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000ab ),
.Q(\blk00000001/sig00000124 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000da (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000ac ),
.Q(\blk00000001/sig00000125 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d9 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000085 ),
.Q(\blk00000001/sig00000126 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d8 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000008d ),
.Q(\blk00000001/sig00000114 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d7 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000008e ),
.Q(\blk00000001/sig00000115 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d6 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000008f ),
.Q(\blk00000001/sig00000116 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d5 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000090 ),
.Q(\blk00000001/sig00000117 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d4 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000091 ),
.Q(\blk00000001/sig00000118 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d3 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000092 ),
.Q(\blk00000001/sig00000119 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d2 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000093 ),
.Q(\blk00000001/sig0000011a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d1 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000094 ),
.Q(\blk00000001/sig0000011b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d0 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000007b ),
.Q(\blk00000001/sig0000011c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cf (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b4 ),
.Q(\blk00000001/sig00000127 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ce (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b5 ),
.Q(\blk00000001/sig00000079 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cd (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b6 ),
.Q(\blk00000001/sig00000078 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cc (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b7 ),
.Q(\blk00000001/sig00000077 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cb (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b8 ),
.Q(\blk00000001/sig00000076 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ca (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000b9 ),
.Q(\blk00000001/sig00000075 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c9 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000ba ),
.Q(\blk00000001/sig00000074 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c8 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000bb ),
.Q(\blk00000001/sig00000073 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c7 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000009d ),
.Q(\blk00000001/sig0000011d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c6 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000009e ),
.Q(\blk00000001/sig00000071 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c5 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000009f ),
.Q(\blk00000001/sig00000070 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c4 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a0 ),
.Q(\blk00000001/sig0000006f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c3 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a1 ),
.Q(\blk00000001/sig0000006e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c2 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a2 ),
.Q(\blk00000001/sig0000006d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c1 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a3 ),
.Q(\blk00000001/sig0000006c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c0 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000a4 ),
.Q(\blk00000001/sig0000006b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bf (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000007a ),
.Q(m_axis_data_tdata[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000be (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c3 ),
.Q(m_axis_data_tdata[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bd (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c4 ),
.Q(m_axis_data_tdata[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bc (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c5 ),
.Q(m_axis_data_tdata[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bb (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c6 ),
.Q(m_axis_data_tdata[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ba (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c7 ),
.Q(m_axis_data_tdata[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b9 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c8 ),
.Q(m_axis_data_tdata[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b8 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c9 ),
.Q(m_axis_data_tdata[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b7 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000011e ),
.Q(m_axis_data_tdata[0])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b6 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000011f ),
.Q(m_axis_data_tdata[1])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b5 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000120 ),
.Q(m_axis_data_tdata[2])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b4 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000121 ),
.Q(m_axis_data_tdata[3])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b3 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000122 ),
.Q(m_axis_data_tdata[4])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b2 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000123 ),
.Q(m_axis_data_tdata[5])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b1 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000124 ),
.Q(m_axis_data_tdata[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b0 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000125 ),
.Q(m_axis_data_tdata[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000af (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000072 ),
.Q(\blk00000001/sig0000010c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000bc ),
.Q(\blk00000001/sig0000010d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ad (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000bd ),
.Q(\blk00000001/sig0000010e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ac (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000be ),
.Q(\blk00000001/sig0000010f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ab (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000bf ),
.Q(\blk00000001/sig00000110 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000aa (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c0 ),
.Q(\blk00000001/sig00000111 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a9 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig00000112 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a8 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000c2 ),
.Q(\blk00000001/sig00000113 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a7 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig00000104 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a6 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig00000105 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a5 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig00000106 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a4 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig00000107 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig00000108 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a2 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig00000109 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a1 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig0000010a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a0 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000011b ),
.Q(\blk00000001/sig0000010b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002b ),
.Q(\blk00000001/sig00000148 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009e (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002c ),
.Q(\blk00000001/sig00000149 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000147 ),
.Q(\blk00000001/sig000000bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009c (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000ca ),
.Q(\blk00000001/sig000000d8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000cb ),
.Q(\blk00000001/sig000000d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009a (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000cc ),
.Q(\blk00000001/sig000000da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000099 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000cd ),
.Q(\blk00000001/sig000000db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000098 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000ce ),
.Q(\blk00000001/sig000000dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000097 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000cf ),
.Q(\blk00000001/sig000000dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000096 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d0 ),
.Q(\blk00000001/sig000000de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000095 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d1 ),
.Q(\blk00000001/sig000000df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000094 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d2 ),
.Q(\blk00000001/sig000000e0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000093 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d3 ),
.Q(\blk00000001/sig000000e1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000092 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d4 ),
.Q(\blk00000001/sig000000e2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000091 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d5 ),
.Q(\blk00000001/sig000000e3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000090 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d6 ),
.Q(\blk00000001/sig000000e4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000008f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig000000d7 ),
.Q(\blk00000001/sig000000e5 )
);
MUXCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig00000014 ),
.DI(\blk00000001/sig000000bb ),
.S(\blk00000001/sig0000014d ),
.O(\blk00000001/sig0000008c )
);
XORCY \blk00000001/blk0000008d (
.CI(\blk00000001/sig00000014 ),
.LI(\blk00000001/sig0000014d ),
.O(\blk00000001/sig000000a5 )
);
MUXCY \blk00000001/blk0000008c (
.CI(\blk00000001/sig0000008c ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000ad ),
.O(\blk00000001/sig0000008b )
);
XORCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig0000008c ),
.LI(\blk00000001/sig000000ad ),
.O(\blk00000001/sig000000a6 )
);
MUXCY \blk00000001/blk0000008a (
.CI(\blk00000001/sig0000008b ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000ae ),
.O(\blk00000001/sig0000008a )
);
XORCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig0000008b ),
.LI(\blk00000001/sig000000ae ),
.O(\blk00000001/sig000000a7 )
);
MUXCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig0000008a ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000af ),
.O(\blk00000001/sig00000089 )
);
XORCY \blk00000001/blk00000087 (
.CI(\blk00000001/sig0000008a ),
.LI(\blk00000001/sig000000af ),
.O(\blk00000001/sig000000a8 )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig00000089 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig00000088 )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig00000089 ),
.LI(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig000000a9 )
);
MUXCY \blk00000001/blk00000084 (
.CI(\blk00000001/sig00000088 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig00000088 ),
.LI(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig000000aa )
);
MUXCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig00000087 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig00000086 )
);
XORCY \blk00000001/blk00000081 (
.CI(\blk00000001/sig00000087 ),
.LI(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig000000ab )
);
MUXCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig00000086 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig00000086 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000000ac )
);
MUXCY \blk00000001/blk0000007e (
.CI(\blk00000001/sig00000014 ),
.DI(\blk00000001/sig00000013 ),
.S(\blk00000001/sig00000084 ),
.O(\blk00000001/sig00000083 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig00000083 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig00000083 ),
.LI(\blk00000001/sig00000095 ),
.O(\blk00000001/sig0000008d )
);
MUXCY \blk00000001/blk0000007b (
.CI(\blk00000001/sig00000082 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000081 )
);
XORCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000082 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000081 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig00000097 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk00000078 (
.CI(\blk00000001/sig00000081 ),
.LI(\blk00000001/sig00000097 ),
.O(\blk00000001/sig0000008f )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig00000098 ),
.O(\blk00000001/sig0000007f )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk00000075 (
.CI(\blk00000001/sig0000007f ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig00000099 ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig0000007f ),
.LI(\blk00000001/sig00000099 ),
.O(\blk00000001/sig00000091 )
);
MUXCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig0000009a ),
.O(\blk00000001/sig0000007d )
);
XORCY \blk00000001/blk00000072 (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000009a ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig0000007d ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig0000009b ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig0000007d ),
.LI(\blk00000001/sig0000009b ),
.O(\blk00000001/sig00000093 )
);
MUXCY \blk00000001/blk0000006f (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig00000014 ),
.S(\blk00000001/sig0000009c ),
.O(\blk00000001/sig0000007b )
);
XORCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000009c ),
.O(\blk00000001/sig00000094 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000006d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000001b ),
.R(\blk00000001/sig00000014 ),
.Q(\blk00000001/sig0000001a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000006c (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000017 ),
.Q(m_axis_data_tvalid)
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002e ),
.Q(\blk00000001/sig0000001d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000038 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002f ),
.Q(\blk00000001/sig0000001e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000037 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000030 ),
.Q(\blk00000001/sig0000001f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000036 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000031 ),
.Q(\blk00000001/sig00000020 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000035 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000032 ),
.Q(\blk00000001/sig00000021 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000034 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000033 ),
.Q(\blk00000001/sig00000022 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000033 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000034 ),
.Q(\blk00000001/sig00000023 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000032 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000035 ),
.Q(\blk00000001/sig00000024 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000031 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000036 ),
.Q(\blk00000001/sig00000025 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000030 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000037 ),
.Q(\blk00000001/sig00000026 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000038 ),
.Q(\blk00000001/sig00000027 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002e (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000039 ),
.Q(\blk00000001/sig00000028 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000003a ),
.Q(\blk00000001/sig00000029 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002c (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000003b ),
.Q(\blk00000001/sig0000002a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000003c ),
.Q(\blk00000001/sig0000002b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002a (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000003d ),
.Q(\blk00000001/sig0000002c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000029 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000003e ),
.Q(\blk00000001/sig0000002d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000028 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000001d ),
.Q(\blk00000001/sig00000040 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000027 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000001e ),
.Q(\blk00000001/sig00000041 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000026 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000001f ),
.Q(\blk00000001/sig00000042 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000025 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000020 ),
.Q(\blk00000001/sig00000043 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000024 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000021 ),
.Q(\blk00000001/sig00000044 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000023 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000022 ),
.Q(\blk00000001/sig00000045 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000022 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000023 ),
.Q(\blk00000001/sig00000046 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000021 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000024 ),
.Q(\blk00000001/sig00000047 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000020 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000025 ),
.Q(\blk00000001/sig00000048 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000026 ),
.Q(\blk00000001/sig00000049 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001e (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000027 ),
.Q(\blk00000001/sig0000004a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000028 ),
.Q(\blk00000001/sig0000004b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001c (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000029 ),
.Q(\blk00000001/sig0000004c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002a ),
.Q(\blk00000001/sig0000004d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000001a (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002b ),
.Q(\blk00000001/sig0000004e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000019 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002c ),
.Q(\blk00000001/sig0000004f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000018 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig0000002d ),
.Q(\blk00000001/sig00000067 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000017 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000060 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000050 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000016 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000061 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000051 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000015 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000062 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000052 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000014 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000063 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000053 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000064 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000054 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000065 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000055 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000060 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000056 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000061 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000057 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000062 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000058 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000063 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig00000059 )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000064 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005a )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000065 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005b )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000066 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005c )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000066 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005d )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000066 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005e )
);
FDRE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000066 ),
.R(\blk00000001/sig0000003f ),
.Q(\blk00000001/sig0000005f )
);
RAM32M #(
.INIT_A ( 64'h0000000000000000 ),
.INIT_B ( 64'h0000000000000000 ),
.INIT_C ( 64'h0000000000000000 ),
.INIT_D ( 64'h0000000000000000 ))
\blk00000001/blk00000007 (
.WCLK(aclk),
.WE(\blk00000001/sig00000014 ),
.DIA({\blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIB({\blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DIC({\blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DID({\blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.ADDRA({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig0000001c }),
.ADDRB({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig0000001c }),
.ADDRC({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig0000001c }),
.ADDRD({\blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 , \blk00000001/sig00000014 }),
.DOA({\blk00000001/sig00000061 , \blk00000001/sig00000060 }),
.DOB({\blk00000001/sig00000063 , \blk00000001/sig00000062 }),
.DOC({\blk00000001/sig00000065 , \blk00000001/sig00000064 }),
.DOD({\NLW_blk00000001/blk00000007_DOD<1>_UNCONNECTED , \NLW_blk00000001/blk00000007_DOD<0>_UNCONNECTED })
);
RAM16X1D #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000006 (
.A0(\blk00000001/sig00000014 ),
.A1(\blk00000001/sig00000014 ),
.A2(\blk00000001/sig00000014 ),
.A3(\blk00000001/sig00000014 ),
.D(\blk00000001/sig00000014 ),
.DPRA0(\blk00000001/sig0000001c ),
.DPRA1(\blk00000001/sig00000014 ),
.DPRA2(\blk00000001/sig00000014 ),
.DPRA3(\blk00000001/sig00000014 ),
.WCLK(aclk),
.WE(\blk00000001/sig00000014 ),
.SPO(\NLW_blk00000001/blk00000006_SPO_UNCONNECTED ),
.DPO(\blk00000001/sig00000066 )
);
FDE #(
.INIT ( 1'b1 ))
\blk00000001/blk00000005 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000014 ),
.Q(\blk00000001/sig0000003f )
);
FDSE #(
.INIT ( 1'b1 ))
\blk00000001/blk00000004 (
.C(aclk),
.CE(\blk00000001/sig00000013 ),
.D(\blk00000001/sig00000016 ),
.S(\blk00000001/sig00000014 ),
.Q(\blk00000001/sig0000001c )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig00000014 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000013 )
);
XORCY \blk00000001/blk0000003a/blk0000006b (
.CI(\blk00000001/blk0000003a/sig000001be ),
.LI(\blk00000001/blk0000003a/sig000001bf ),
.O(\blk00000001/sig0000003d )
);
MUXCY \blk00000001/blk0000003a/blk0000006a (
.CI(\blk00000001/blk0000003a/sig000001be ),
.DI(\blk00000001/sig0000004f ),
.S(\blk00000001/blk0000003a/sig000001bf ),
.O(\blk00000001/sig0000003e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000069 (
.I0(\blk00000001/sig0000004f ),
.I1(\blk00000001/sig0000005f ),
.O(\blk00000001/blk0000003a/sig000001bf )
);
XORCY \blk00000001/blk0000003a/blk00000068 (
.CI(\blk00000001/blk0000003a/sig000001bc ),
.LI(\blk00000001/blk0000003a/sig000001bd ),
.O(\blk00000001/sig0000003c )
);
MUXCY \blk00000001/blk0000003a/blk00000067 (
.CI(\blk00000001/blk0000003a/sig000001bc ),
.DI(\blk00000001/sig0000004e ),
.S(\blk00000001/blk0000003a/sig000001bd ),
.O(\blk00000001/blk0000003a/sig000001be )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000066 (
.I0(\blk00000001/sig0000004e ),
.I1(\blk00000001/sig0000005e ),
.O(\blk00000001/blk0000003a/sig000001bd )
);
XORCY \blk00000001/blk0000003a/blk00000065 (
.CI(\blk00000001/blk0000003a/sig000001ba ),
.LI(\blk00000001/blk0000003a/sig000001bb ),
.O(\blk00000001/sig0000003b )
);
MUXCY \blk00000001/blk0000003a/blk00000064 (
.CI(\blk00000001/blk0000003a/sig000001ba ),
.DI(\blk00000001/sig0000004d ),
.S(\blk00000001/blk0000003a/sig000001bb ),
.O(\blk00000001/blk0000003a/sig000001bc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000063 (
.I0(\blk00000001/sig0000004d ),
.I1(\blk00000001/sig0000005d ),
.O(\blk00000001/blk0000003a/sig000001bb )
);
XORCY \blk00000001/blk0000003a/blk00000062 (
.CI(\blk00000001/blk0000003a/sig000001b8 ),
.LI(\blk00000001/blk0000003a/sig000001b9 ),
.O(\blk00000001/sig0000003a )
);
MUXCY \blk00000001/blk0000003a/blk00000061 (
.CI(\blk00000001/blk0000003a/sig000001b8 ),
.DI(\blk00000001/sig0000004c ),
.S(\blk00000001/blk0000003a/sig000001b9 ),
.O(\blk00000001/blk0000003a/sig000001ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000060 (
.I0(\blk00000001/sig0000004c ),
.I1(\blk00000001/sig0000005c ),
.O(\blk00000001/blk0000003a/sig000001b9 )
);
XORCY \blk00000001/blk0000003a/blk0000005f (
.CI(\blk00000001/blk0000003a/sig000001b6 ),
.LI(\blk00000001/blk0000003a/sig000001b7 ),
.O(\blk00000001/sig00000039 )
);
MUXCY \blk00000001/blk0000003a/blk0000005e (
.CI(\blk00000001/blk0000003a/sig000001b6 ),
.DI(\blk00000001/sig0000004b ),
.S(\blk00000001/blk0000003a/sig000001b7 ),
.O(\blk00000001/blk0000003a/sig000001b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000005d (
.I0(\blk00000001/sig0000004b ),
.I1(\blk00000001/sig0000005b ),
.O(\blk00000001/blk0000003a/sig000001b7 )
);
XORCY \blk00000001/blk0000003a/blk0000005c (
.CI(\blk00000001/blk0000003a/sig000001b4 ),
.LI(\blk00000001/blk0000003a/sig000001b5 ),
.O(\blk00000001/sig00000038 )
);
MUXCY \blk00000001/blk0000003a/blk0000005b (
.CI(\blk00000001/blk0000003a/sig000001b4 ),
.DI(\blk00000001/sig0000004a ),
.S(\blk00000001/blk0000003a/sig000001b5 ),
.O(\blk00000001/blk0000003a/sig000001b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000005a (
.I0(\blk00000001/sig0000004a ),
.I1(\blk00000001/sig0000005a ),
.O(\blk00000001/blk0000003a/sig000001b5 )
);
XORCY \blk00000001/blk0000003a/blk00000059 (
.CI(\blk00000001/blk0000003a/sig000001b2 ),
.LI(\blk00000001/blk0000003a/sig000001b3 ),
.O(\blk00000001/sig00000037 )
);
MUXCY \blk00000001/blk0000003a/blk00000058 (
.CI(\blk00000001/blk0000003a/sig000001b2 ),
.DI(\blk00000001/sig00000049 ),
.S(\blk00000001/blk0000003a/sig000001b3 ),
.O(\blk00000001/blk0000003a/sig000001b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000057 (
.I0(\blk00000001/sig00000049 ),
.I1(\blk00000001/sig00000059 ),
.O(\blk00000001/blk0000003a/sig000001b3 )
);
XORCY \blk00000001/blk0000003a/blk00000056 (
.CI(\blk00000001/blk0000003a/sig000001b0 ),
.LI(\blk00000001/blk0000003a/sig000001b1 ),
.O(\blk00000001/sig00000036 )
);
MUXCY \blk00000001/blk0000003a/blk00000055 (
.CI(\blk00000001/blk0000003a/sig000001b0 ),
.DI(\blk00000001/sig00000048 ),
.S(\blk00000001/blk0000003a/sig000001b1 ),
.O(\blk00000001/blk0000003a/sig000001b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000054 (
.I0(\blk00000001/sig00000048 ),
.I1(\blk00000001/sig00000058 ),
.O(\blk00000001/blk0000003a/sig000001b1 )
);
XORCY \blk00000001/blk0000003a/blk00000053 (
.CI(\blk00000001/blk0000003a/sig000001ae ),
.LI(\blk00000001/blk0000003a/sig000001af ),
.O(\blk00000001/sig00000035 )
);
MUXCY \blk00000001/blk0000003a/blk00000052 (
.CI(\blk00000001/blk0000003a/sig000001ae ),
.DI(\blk00000001/sig00000047 ),
.S(\blk00000001/blk0000003a/sig000001af ),
.O(\blk00000001/blk0000003a/sig000001b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000051 (
.I0(\blk00000001/sig00000047 ),
.I1(\blk00000001/sig00000057 ),
.O(\blk00000001/blk0000003a/sig000001af )
);
XORCY \blk00000001/blk0000003a/blk00000050 (
.CI(\blk00000001/blk0000003a/sig000001ac ),
.LI(\blk00000001/blk0000003a/sig000001ad ),
.O(\blk00000001/sig00000034 )
);
MUXCY \blk00000001/blk0000003a/blk0000004f (
.CI(\blk00000001/blk0000003a/sig000001ac ),
.DI(\blk00000001/sig00000046 ),
.S(\blk00000001/blk0000003a/sig000001ad ),
.O(\blk00000001/blk0000003a/sig000001ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000004e (
.I0(\blk00000001/sig00000046 ),
.I1(\blk00000001/sig00000056 ),
.O(\blk00000001/blk0000003a/sig000001ad )
);
XORCY \blk00000001/blk0000003a/blk0000004d (
.CI(\blk00000001/blk0000003a/sig000001aa ),
.LI(\blk00000001/blk0000003a/sig000001ab ),
.O(\blk00000001/sig00000033 )
);
MUXCY \blk00000001/blk0000003a/blk0000004c (
.CI(\blk00000001/blk0000003a/sig000001aa ),
.DI(\blk00000001/sig00000045 ),
.S(\blk00000001/blk0000003a/sig000001ab ),
.O(\blk00000001/blk0000003a/sig000001ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000004b (
.I0(\blk00000001/sig00000045 ),
.I1(\blk00000001/sig00000055 ),
.O(\blk00000001/blk0000003a/sig000001ab )
);
XORCY \blk00000001/blk0000003a/blk0000004a (
.CI(\blk00000001/blk0000003a/sig000001a8 ),
.LI(\blk00000001/blk0000003a/sig000001a9 ),
.O(\blk00000001/sig00000032 )
);
MUXCY \blk00000001/blk0000003a/blk00000049 (
.CI(\blk00000001/blk0000003a/sig000001a8 ),
.DI(\blk00000001/sig00000044 ),
.S(\blk00000001/blk0000003a/sig000001a9 ),
.O(\blk00000001/blk0000003a/sig000001aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000048 (
.I0(\blk00000001/sig00000044 ),
.I1(\blk00000001/sig00000054 ),
.O(\blk00000001/blk0000003a/sig000001a9 )
);
XORCY \blk00000001/blk0000003a/blk00000047 (
.CI(\blk00000001/blk0000003a/sig000001a6 ),
.LI(\blk00000001/blk0000003a/sig000001a7 ),
.O(\blk00000001/sig00000031 )
);
MUXCY \blk00000001/blk0000003a/blk00000046 (
.CI(\blk00000001/blk0000003a/sig000001a6 ),
.DI(\blk00000001/sig00000043 ),
.S(\blk00000001/blk0000003a/sig000001a7 ),
.O(\blk00000001/blk0000003a/sig000001a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000045 (
.I0(\blk00000001/sig00000043 ),
.I1(\blk00000001/sig00000053 ),
.O(\blk00000001/blk0000003a/sig000001a7 )
);
XORCY \blk00000001/blk0000003a/blk00000044 (
.CI(\blk00000001/blk0000003a/sig000001a4 ),
.LI(\blk00000001/blk0000003a/sig000001a5 ),
.O(\blk00000001/sig00000030 )
);
MUXCY \blk00000001/blk0000003a/blk00000043 (
.CI(\blk00000001/blk0000003a/sig000001a4 ),
.DI(\blk00000001/sig00000042 ),
.S(\blk00000001/blk0000003a/sig000001a5 ),
.O(\blk00000001/blk0000003a/sig000001a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk00000042 (
.I0(\blk00000001/sig00000042 ),
.I1(\blk00000001/sig00000052 ),
.O(\blk00000001/blk0000003a/sig000001a5 )
);
XORCY \blk00000001/blk0000003a/blk00000041 (
.CI(\blk00000001/blk0000003a/sig000001a2 ),
.LI(\blk00000001/blk0000003a/sig000001a3 ),
.O(\blk00000001/sig0000002f )
);
MUXCY \blk00000001/blk0000003a/blk00000040 (
.CI(\blk00000001/blk0000003a/sig000001a2 ),
.DI(\blk00000001/sig00000041 ),
.S(\blk00000001/blk0000003a/sig000001a3 ),
.O(\blk00000001/blk0000003a/sig000001a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000003f (
.I0(\blk00000001/sig00000041 ),
.I1(\blk00000001/sig00000051 ),
.O(\blk00000001/blk0000003a/sig000001a3 )
);
XORCY \blk00000001/blk0000003a/blk0000003e (
.CI(\blk00000001/blk0000003a/sig000001a0 ),
.LI(\blk00000001/blk0000003a/sig000001a1 ),
.O(\blk00000001/sig0000002e )
);
MUXCY \blk00000001/blk0000003a/blk0000003d (
.CI(\blk00000001/blk0000003a/sig000001a0 ),
.DI(\blk00000001/sig00000040 ),
.S(\blk00000001/blk0000003a/sig000001a1 ),
.O(\blk00000001/blk0000003a/sig000001a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000003a/blk0000003c (
.I0(\blk00000001/sig00000040 ),
.I1(\blk00000001/sig00000050 ),
.O(\blk00000001/blk0000003a/sig000001a1 )
);
GND \blk00000001/blk0000003a/blk0000003b (
.G(\blk00000001/blk0000003a/sig000001a0 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
//-----------------------------------------------------
// Proyecto 1 : DISEÑO DE UN CONTROLADOR DE SD HOST
// Archivo : BloqueDATA.v
// Descripcion : CONTROLADOR de datos del SD Host.
// La función de este bloque es servir de interfaz entre la tajeta SD y el buffer FIFO.
//
//
// Grupo 02
// Estudiante : Mario Castresana Avendaño | A41267
//-----------------------------------------------------
/*
PINOUT DEL BLOQUE DE DATA
_____________________________________________________________________________________
Nombre de Señal : Entradas : Salidas : procedencia : destino
CLK x - HOST DATA
SD_CLK x - HOST DATA
RESET_L x - HOST DATA
timeout_Reg_DATA x - Reg DATA
writeRead_Reg_DATA x - Reg DATA
blockCount_Reg_DATA x - Reg DATA
multipleData_Reg_DATA x - Reg DATA
timeout_enable_Reg_DATA x - Reg DATA
FIFO_OK_FIFO_DATA x - FIFO DATA
New_DAT_DMA_DATA x - DMA DATA
DATA_PIN_IN x - SD_CARD DATA
writeFIFO_enable_DATA_FIFO - x DATA FIFO
readFIFO_enable_DATA_FIFO - x DATA FIFO
transfer_complete_DATA_DMA - x DATA DMA
IO_enable_DATA_SD_CARD - x DATA SD_CARD
DATA_PIN_OUT - x DATA SD_CARD
_____________________________________________________________________________________
*/
//Define
`define PALABRA 32
//Módulos utilizados
`include "DATA.v"
`include "DATA_PHYSICAL.v"
module BloqueDATA(
input wire CLK,
input wire SD_CLK,
input wire RESET_L,
input wire [15:0] timeout_Reg_Regs_DATA,
input wire writeRead_Regs_DATA,
input wire [3:0] blockCount_Regs_DATA,
input wire multipleData_Regs_DATA,
input wire timeout_enable_Regs_DATA,
input wire FIFO_OK_FIFO_DATA,
input wire [31:0] dataFromFIFO_FIFO_Phy,
input wire New_DAT_DMA_DATA,
input wire DATA_PIN_IN,
output wire writeFIFO_enable_Phy_FIFO,
output wire readFIFO_enable_Phy_FIFO,
output wire [31:0] dataReadToFIFO_Phy_FIFO,
output wire transfer_complete_DATA_DMA,
output wire IO_enable_Phy_SD_CARD,
output wire DATA_PIN_OUT,
output wire pad_state_Phy_PAD,
output wire pad_enable_Phy_PAD
);
//wires entre DATA y DATA_PHYSICAL
wire serial_Ready_Phy_DATA;
wire timeout_Phy_DATA;
wire complete_Phy_DATA;
wire ack_IN_Phy_DATA;
wire strobe_OUT;
wire strobe_OUT_DATA_Phy;
wire ack_OUT_DATA_Phy;
wire [3:0] blocks_DATA_Phy;
wire [15:0] timeout_value_DATA_Phy;
wire writeReadPhysical_DATA_Phy;
wire multiple_DATA_Phy;
wire idle_out_DATA_Phy;
//wires a SP o PS converter
//SP
wire reception_complete_SP_Phy;
wire [31:0] data_read_SP_Phy;
wire enable_stp_Wrapper_Phy_SP;
//PS
wire transmission_complete_PS_Phy;
wire reset_Wrapper_Phy_PS;
wire enable_pts_Wrapper_Phy_PS;
wire [31:0] dataParallel_Phy_PS;
//CONTROLADOR de DATOS
DATA ControlDatos(
.CLK(CLK),
.RESET_L(RESET_L),
.writeRead_Regs_DATA(writeRead_Regs_DATA),
.blockCount_Regs_DATA(blockCount_Regs_DATA),
.multipleData_Regs_DATA(multipleData_Regs_DATA),
.timeout_Enable_Regs_DATA(timeout_enable_Regs_DATA),
.timeout_Reg_Regs_DATA(timeout_Reg_Regs_DATA),
.new_DAT_DMA_DATA(New_DAT_DMA_DATA),
.serial_Ready_Phy_DATA(serial_Ready_Phy_DATA),
.timeout_Phy_DATA(timeout_Phy_DATA),
.complete_Phy_DATA(complete_Phy_DATA),
.ack_IN_Phy_DATA(ack_IN_Phy_DATA),
.fifo_OK_FIFO_DATA(FIFO_OK_FIFO_DATA),
.transfer_complete_DATA_DMA(transfer_complete_DATA_DMA),
.strobe_OUT_DATA_Phy(strobe_OUT_DATA_Phy),
.ack_OUT_DATA_Phy(ack_OUT_DATA_Phy),
.blocks_DATA_Phy(blocks_DATA_Phy),
.timeout_value_DATA_Phy(timeout_value_DATA_Phy),
.writeReadPhysical_DATA_Phy(writeReadPhysical_DATA_Phy),
.multiple_DATA_Phy(multiple_DATA_Phy),
.idle_out_DATA_Phy(idle_out_DATA_Phy)
);
//Capa física de control de datos
DATA_PHYSICAL CapaFisica(
.SD_CLK(SD_CLK),
.RESET_L(RESET_L),
.strobe_IN_DATA_Phy(strobe_OUT_DATA_Phy),
.ack_IN_DATA_Phy(ack_OUT_DATA_Phy),
.timeout_Reg_DATA_Phy(timeout_value_DATA_Phy),
.blocks_DATA_Phy(blocks_DATA_Phy),
.writeRead_DATA_Phy(writeReadPhysical_DATA_Phy),
.multiple_DATA_Phy(multiple_DATA_Phy),
.idle_in_DATA_Phy(idle_out_DATA_Phy),
.transmission_complete_PS_Phy(transmission_complete_PS_Phy),
.reception_complete_SP_Phy(reception_complete_SP_Phy),
.data_read_SP_Phy(data_read_SP_Phy),
.dataFromFIFO_FIFO_Phy(dataFromFIFO_FIFO_Phy),
.serial_Ready_Phy_DATA(serial_Ready_Phy_DATA),
.complete_Phy_DATA(complete_Phy_DATA),
.ack_OUT_Phy_DATA(ack_IN_Phy_DATA),
.data_timeout_Phy_DATA(timeout_Phy_DATA),
.reset_Wrapper_Phy_PS(reset_Wrapper_Phy_PS),
.enable_pts_Wrapper_Phy_PS(enable_pts_Wrapper_Phy_PS),
.enable_stp_Wrapper_Phy_SP(enable_stp_Wrapper_Phy_SP),
.dataParallel_Phy_PS(dataParallel_Phy_PS),
.pad_state_Phy_PAD(pad_state_Phy_PAD),
.pad_enable_Phy_PAD(pad_enable_Phy_PAD),
.writeFIFO_enable_Phy_FIFO(writeFIFO_enable_Phy_FIFO),
.readFIFO_enable_Phy_FIFO(readFIFO_enable_Phy_FIFO),
.dataReadToFIFO_Phy_FIFO(dataReadToFIFO_Phy_FIFO),
.IO_enable_Phy_SD_CARD(IO_enable_Phy_SD_CARD)
);
//convertidor Paralelo a Serial
PARALLEL_TO_SERIAL convert_paralelo_serial(
.enable_pts(enable_pts_Wrapper_Phy_PS),
.reset_pts(reset_Wrapper_Phy_PS),
.SD_CLK(SD_CLK),
.signal_in(dataParallel_Phy_PS),
.signal_out(DATA_PIN_OUT),
.parallel_complete(transmission_complete_PS_Phy)
);
//convertidor serial a paralelo
SERIAL_TO_PARALLEL #(32) convert_serial_paralelo(
.serial_in(DATA_PIN_IN),
.enable_stp(enable_stp_Wrapper_Phy_SP),
.SD_CLK(SD_CLK),
.RESET_L(RESET_L),
.reception_complete(reception_complete_SP_Phy),
.parallel_out(data_read_SP_Phy)
);
endmodule // BloqueDATA
/*
----------------------------------------
MODULOS adicionales para el BloqueDATA
----------------------------------------
*/
module PARALLEL_TO_SERIAL (
input wire enable_pts,
input wire reset_pts,
input wire SD_CLK,
input wire [31:0] signal_in,
output reg signal_out,
output reg parallel_complete
);
//registros y wires internos
reg [8:0]contador = 0;
always @ ( posedge SD_CLK ) begin
if (~reset_pts) begin
signal_out <= 0;
contador <= 0;
parallel_complete <= 0;
end else begin
if (enable_pts == 1) begin
if (contador == 32) begin
parallel_complete <= 1;
contador <= 0;
end else begin
parallel_complete <= 0;
signal_out = signal_in[31 - contador];
contador <= contador + 1;
end
end else begin
signal_out <= 0;
end
end
end
endmodule // PARALLEL_TO_SERIAL
module SERIAL_TO_PARALLEL # (parameter SIZE = `PALABRA)
(
input wire serial_in,
input wire enable_stp,
input wire SD_CLK,
input wire RESET_L,
output reg reception_complete,
output reg [SIZE - 1:0] parallel_out
);
reg [8:0] contador;
always @ (posedge SD_CLK or negedge RESET_L)
begin
if (~RESET_L)
begin
parallel_out <= 0;
reception_complete <= 0;
contador <= 0;
end
else
begin
if (enable_stp)
begin
if (contador == SIZE)
begin
reception_complete <= 1;
contador <= 0;
end
else
begin
reception_complete <= 0;
parallel_out <= {serial_in, parallel_out[SIZE-1:1]};
contador <= contador + 1;
end
end
else
begin
parallel_out <= 0;
end
end
end //always
endmodule // CONVERT_SERIAL_TO_PARALLEL
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/10/2017 09:26:11 AM
// Design Name:
// Module Name: MULTIPLEXER_16_TO_1
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MULTIPLEXER_16_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input [BUS_WIDTH - 1 : 0] IN3 ,
input [BUS_WIDTH - 1 : 0] IN4 ,
input [BUS_WIDTH - 1 : 0] IN5 ,
input [BUS_WIDTH - 1 : 0] IN6 ,
input [BUS_WIDTH - 1 : 0] IN7 ,
input [BUS_WIDTH - 1 : 0] IN8 ,
input [BUS_WIDTH - 1 : 0] IN9 ,
input [BUS_WIDTH - 1 : 0] IN10 ,
input [BUS_WIDTH - 1 : 0] IN11 ,
input [BUS_WIDTH - 1 : 0] IN12 ,
input [BUS_WIDTH - 1 : 0] IN13 ,
input [BUS_WIDTH - 1 : 0] IN14 ,
input [BUS_WIDTH - 1 : 0] IN15 ,
input [BUS_WIDTH - 1 : 0] IN16 ,
input [3 : 0] SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
4'b0000:
begin
out_reg = IN1 ;
end
4'b0001:
begin
out_reg = IN2 ;
end
4'b0010:
begin
out_reg = IN3 ;
end
4'b0011:
begin
out_reg = IN4 ;
end
4'b0100:
begin
out_reg = IN5 ;
end
4'b0101:
begin
out_reg = IN6 ;
end
4'b0110:
begin
out_reg = IN7 ;
end
4'b0111:
begin
out_reg = IN8 ;
end
4'b1000:
begin
out_reg = IN9 ;
end
4'b1001:
begin
out_reg = IN10 ;
end
4'b1010:
begin
out_reg = IN11 ;
end
4'b1011:
begin
out_reg = IN12 ;
end
4'b1100:
begin
out_reg = IN13 ;
end
4'b1101:
begin
out_reg = IN14 ;
end
4'b1110:
begin
out_reg = IN15 ;
end
4'b1111:
begin
out_reg = IN16 ;
end
endcase
end
assign OUT = out_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_BLACKBOX_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
module BypassWire(WGET, WVAL);
parameter width = 1;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
|
//-----------------------------------------------------------------
// USB CDC Device
// V0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module usbf_sie_rx
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input [ 7:0] utmi_data_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input [ 6:0] current_addr_i
// Outputs
,output [ 7:0] pid_o
,output frame_valid_o
,output [ 10:0] frame_number_o
,output token_valid_o
,output [ 6:0] token_addr_o
,output [ 3:0] token_ep_o
,output token_crc_err_o
,output handshake_valid_o
,output data_valid_o
,output data_strb_o
,output [ 7:0] data_o
,output data_last_o
,output data_crc_err_o
,output data_complete_o
);
//-----------------------------------------------------------------
// Defines:
//-----------------------------------------------------------------
`include "usbf_defs.v"
localparam STATE_W = 4;
localparam STATE_RX_IDLE = 4'd0;
localparam STATE_RX_TOKEN2 = 4'd1;
localparam STATE_RX_TOKEN3 = 4'd2;
localparam STATE_RX_TOKEN_COMPLETE = 4'd3;
localparam STATE_RX_SOF2 = 4'd4;
localparam STATE_RX_SOF3 = 4'd5;
localparam STATE_RX_DATA = 4'd6;
localparam STATE_RX_DATA_COMPLETE = 4'd7;
localparam STATE_RX_IGNORED = 4'd8;
reg [STATE_W-1:0] state_q;
//-----------------------------------------------------------------
// Wire / Regs
//-----------------------------------------------------------------
`define USB_FRAME_W 11
reg [`USB_FRAME_W-1:0] frame_num_q;
`define USB_DEV_W 7
reg [`USB_DEV_W-1:0] token_dev_q;
`define USB_EP_W 4
reg [`USB_EP_W-1:0] token_ep_q;
`define USB_PID_W 8
reg [`USB_PID_W-1:0] token_pid_q;
//-----------------------------------------------------------------
// Data delay (to strip the CRC16 trailing bytes)
//-----------------------------------------------------------------
reg [31:0] data_buffer_q;
reg [3:0] data_valid_q;
reg [3:0] rx_active_q;
wire shift_en_w = (utmi_rxvalid_i & utmi_rxactive_i) || !utmi_rxactive_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_buffer_q <= 32'b0;
else if (shift_en_w)
data_buffer_q <= {utmi_data_i, data_buffer_q[31:8]};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_valid_q <= 4'b0;
else if (shift_en_w)
data_valid_q <= {(utmi_rxvalid_i & utmi_rxactive_i), data_valid_q[3:1]};
else
data_valid_q <= {data_valid_q[3:1], 1'b0};
reg [1:0] data_crc_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_crc_q <= 2'b0;
else if (shift_en_w)
data_crc_q <= {!utmi_rxactive_i, data_crc_q[1]};
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rx_active_q <= 4'b0;
else
rx_active_q <= {utmi_rxactive_i, rx_active_q[3:1]};
wire [7:0] data_w = data_buffer_q[7:0];
wire data_ready_w = data_valid_q[0];
wire crc_byte_w = data_crc_q[0];
wire rx_active_w = rx_active_q[0];
wire address_match_w = (token_dev_q == current_addr_i);
//-----------------------------------------------------------------
// Next state
//-----------------------------------------------------------------
reg [STATE_W-1:0] next_state_r;
always @ *
begin
next_state_r = state_q;
case (state_q)
//-----------------------------------------
// IDLE
//-----------------------------------------
STATE_RX_IDLE :
begin
if (data_ready_w)
begin
// Decode PID
case (data_w)
`PID_OUT, `PID_IN, `PID_SETUP, `PID_PING:
next_state_r = STATE_RX_TOKEN2;
`PID_SOF:
next_state_r = STATE_RX_SOF2;
`PID_DATA0, `PID_DATA1, `PID_DATA2, `PID_MDATA:
begin
next_state_r = STATE_RX_DATA;
end
`PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
next_state_r = STATE_RX_IDLE;
default : // SPLIT / ERR
next_state_r = STATE_RX_IGNORED;
endcase
end
end
//-----------------------------------------
// RX_IGNORED: Unknown / unsupported
//-----------------------------------------
STATE_RX_IGNORED :
begin
// Wait until the end of the packet
if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// SOF (BYTE 2)
//-----------------------------------------
STATE_RX_SOF2 :
begin
if (data_ready_w)
next_state_r = STATE_RX_SOF3;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// SOF (BYTE 3)
//-----------------------------------------
STATE_RX_SOF3 :
begin
if (data_ready_w || !rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TOKEN (IN/OUT/SETUP) (Address/Endpoint)
//-----------------------------------------
STATE_RX_TOKEN2 :
begin
if (data_ready_w)
next_state_r = STATE_RX_TOKEN3;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// TOKEN (IN/OUT/SETUP) (Endpoint/CRC)
//-----------------------------------------
STATE_RX_TOKEN3 :
begin
if (data_ready_w)
next_state_r = STATE_RX_TOKEN_COMPLETE;
else if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// RX_TOKEN_COMPLETE
//-----------------------------------------
STATE_RX_TOKEN_COMPLETE :
begin
next_state_r = STATE_RX_IDLE;
end
//-----------------------------------------
// RX_DATA
//-----------------------------------------
STATE_RX_DATA :
begin
// Receive complete
if (crc_byte_w)
next_state_r = STATE_RX_DATA_COMPLETE;
end
//-----------------------------------------
// RX_DATA_COMPLETE
//-----------------------------------------
STATE_RX_DATA_COMPLETE :
begin
if (!rx_active_w)
next_state_r = STATE_RX_IDLE;
end
default :
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_RX_IDLE;
else if (!enable_i)
state_q <= STATE_RX_IDLE;
else
state_q <= next_state_r;
//-----------------------------------------------------------------
// Handshake:
//-----------------------------------------------------------------
reg handshake_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
handshake_valid_q <= 1'b0;
else if (state_q == STATE_RX_IDLE && data_ready_w)
begin
case (data_w)
`PID_ACK, `PID_NAK, `PID_STALL, `PID_NYET:
handshake_valid_q <= address_match_w;
default :
handshake_valid_q <= 1'b0;
endcase
end
else
handshake_valid_q <= 1'b0;
assign handshake_valid_o = handshake_valid_q;
//-----------------------------------------------------------------
// SOF: Frame number
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_num_q <= `USB_FRAME_W'b0;
else if (state_q == STATE_RX_SOF2 && data_ready_w)
frame_num_q <= {3'b0, data_w};
else if (state_q == STATE_RX_SOF3 && data_ready_w)
frame_num_q <= {data_w[2:0], frame_num_q[7:0]};
else if (!enable_i)
frame_num_q <= `USB_FRAME_W'b0;
assign frame_number_o = frame_num_q;
reg frame_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
frame_valid_q <= 1'b0;
else
frame_valid_q <= (state_q == STATE_RX_SOF3 && data_ready_w);
assign frame_valid_o = frame_valid_q;
//-----------------------------------------------------------------
// Token: PID
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_pid_q <= `USB_PID_W'b0;
else if (state_q == STATE_RX_IDLE && data_ready_w)
token_pid_q <= data_w;
else if (!enable_i)
token_pid_q <= `USB_PID_W'b0;
assign pid_o = token_pid_q;
reg token_valid_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_valid_q <= 1'b0;
else
token_valid_q <= (state_q == STATE_RX_TOKEN_COMPLETE) && address_match_w;
assign token_valid_o = token_valid_q;
//-----------------------------------------------------------------
// Token: Device Address
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_dev_q <= `USB_DEV_W'b0;
else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
token_dev_q <= data_w[6:0];
else if (!enable_i)
token_dev_q <= `USB_DEV_W'b0;
assign token_addr_o = token_dev_q;
//-----------------------------------------------------------------
// Token: Endpoint
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
token_ep_q <= `USB_EP_W'b0;
else if (state_q == STATE_RX_TOKEN2 && data_ready_w)
token_ep_q[0] <= data_w[7];
else if (state_q == STATE_RX_TOKEN3 && data_ready_w)
token_ep_q[3:1] <= data_w[2:0];
else if (!enable_i)
token_ep_q <= `USB_EP_W'b0;
assign token_ep_o = token_ep_q;
assign token_crc_err_o = 1'b0;
wire [7:0] input_data_w = data_w;
wire input_ready_w = state_q == STATE_RX_DATA && data_ready_w && !crc_byte_w;
//-----------------------------------------------------------------
// CRC16: Generate CRC16 on incoming data bytes
//-----------------------------------------------------------------
reg [15:0] crc_sum_q;
wire [15:0] crc_out_w;
reg crc_err_q;
usbf_crc16
u_crc16
(
.crc_in_i(crc_sum_q),
.din_i(data_w),
.crc_out_o(crc_out_w)
);
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_sum_q <= 16'hFFFF;
else if (state_q == STATE_RX_IDLE)
crc_sum_q <= 16'hFFFF;
else if (data_ready_w)
crc_sum_q <= crc_out_w;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
crc_err_q <= 1'b0;
else if (state_q == STATE_RX_IDLE)
crc_err_q <= 1'b0;
else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
crc_err_q <= (crc_sum_q != 16'hB001);
assign data_crc_err_o = crc_err_q;
reg data_complete_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_complete_q <= 1'b0;
else if (state_q == STATE_RX_DATA_COMPLETE && next_state_r == STATE_RX_IDLE)
data_complete_q <= 1'b1;
else
data_complete_q <= 1'b0;
assign data_complete_o = data_complete_q;
reg data_zlp_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
data_zlp_q <= 1'b0;
else if (state_q == STATE_RX_IDLE && next_state_r == STATE_RX_DATA)
data_zlp_q <= 1'b1;
else if (input_ready_w)
data_zlp_q <= 1'b0;
//-----------------------------------------------------------------
// Data Output
//-----------------------------------------------------------------
reg valid_q;
reg last_q;
reg [7:0] data_q;
reg mask_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
valid_q <= 1'b0;
data_q <= 8'b0;
mask_q <= 1'b0;
last_q <= 1'b0;
end
else
begin
valid_q <= input_ready_w || ((state_q == STATE_RX_DATA) && crc_byte_w && data_zlp_q);
data_q <= input_data_w;
mask_q <= input_ready_w;
last_q <= (state_q == STATE_RX_DATA) && crc_byte_w;
end
// Data
assign data_valid_o = valid_q;
assign data_strb_o = mask_q;
assign data_o = data_q;
assign data_last_o = last_q | crc_byte_w;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_4_V
`define SKY130_FD_SC_HD__NAND4_4_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_2_V
`define SKY130_FD_SC_HS__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_2 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, SLEEP_B, VPWR, KAGND );
and and0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_sleepb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_FUNCTIONAL_PP_V
|
//
// Conformal-LEC Version 15.20-d235 ( 27-Mar-2016) ( 64 bit executable)
//
module top ( n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 , n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 );
input n0 , n1 , n2 , n3 , n4 , n5 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 , n59 , n60 , n61 , n62 , n63 , n64 , n65 , n66 , n67 , n68 , n69 , n70 , n71 , n72 , n73 , n74 , n75 , n76 , n77 , n78 , n79 ;
output n80 , n81 , n82 , n83 , n84 , n85 , n86 , n87 , n88 , n89 , n90 , n91 , n92 , n93 , n94 , n95 ;
wire n192 , n193 , n194 , n195 , n196 , n197 , n198 , n199 , n200 ,
n201 , n202 , n203 , n204 , n205 , n206 , n207 , n208 , n209 , n210 ,
n211 , n212 , n213 , n214 , n215 , n216 , n217 , n218 , n219 , n220 ,
n221 , n222 , n223 , n224 , n225 , n226 , n227 , n228 , n229 , n230 ,
n231 , n232 , n233 , n234 , n235 , n236 , n237 , n238 , n239 , n240 ,
n241 , n242 , n243 , n244 , n245 , n246 , n247 , n248 , n249 , n250 ,
n251 , n252 , n253 , n254 , n255 , n256 , n257 , n258 , n259 , n260 ,
n261 , n262 , n263 , n264 , n265 , n266 , n267 , n268 , n269 , n270 ,
n271 , n272 , n273 , n274 , n275 , n276 , n277 , n278 , n279 , n280 ,
n281 , n282 , n283 , n284 , n285 , n286 , n287 , n288 , n289 , n290 ,
n291 , n292 , n293 , n294 , n295 , n296 , n297 , n298 , n299 , n300 ,
n301 , n302 , n303 , n304 , n305 , n306 , n307 , n308 , n309 , n310 ,
n311 , n312 , n313 , n314 , n315 , n316 , n317 , n318 , n319 , n320 ,
n321 , n322 , n323 , n324 , n325 , n326 , n327 , n328 , n329 , n330 ,
n331 , n332 , n333 , n334 , n335 , n336 , n337 , n338 , n339 , n340 ,
n341 , n342 , n343 , n344 , n345 , n346 , n347 , n348 , n349 , n350 ,
n351 , n352 , n353 , n354 , n355 , n356 , n357 , n358 , n359 , n360 ,
n361 , n362 , n363 , n364 , n365 , n366 , n367 , n368 , n369 , n370 ,
n371 , n372 , n373 , n374 , n375 , n376 , n377 , n378 , n379 , n380 ,
n381 , n382 , n383 , n384 , n385 , n386 , n387 , n388 , n389 , n390 ,
n391 , n392 , n393 , n394 , n395 , n396 , n397 , n398 , n399 , n400 ,
n401 , n402 , n403 , n404 , n405 , n406 , n407 , n408 , n409 , n410 ,
n411 , n412 , n413 , n414 , n415 , n416 , n417 , n418 , n419 , n420 ,
n421 , n422 , n423 , n424 , n425 , n426 , n427 , n428 , n429 , n430 ,
n431 , n432 , n433 , n434 , n435 , n436 , n437 , n438 , n439 , n440 ,
n441 , n442 , n443 , n444 , n445 , n446 , n447 , n448 , n449 , n450 ,
n451 , n452 , n453 , n454 , n455 , n456 , n457 , n458 , n459 , n460 ,
n461 , n462 , n463 , n464 , n465 , n466 , n467 , n468 , n469 , n470 ,
n471 , n472 , n473 , n474 , n475 , n476 , n477 , n478 , n479 , n480 ,
n481 , n482 , n483 , n484 , n485 , n486 , n487 , n488 , n489 , n490 ,
n491 , n492 , n493 , n494 , n495 , n496 , n497 , n498 , n499 , n500 ,
n501 , n502 , n503 , n504 , n505 , n506 , n507 , n508 , n509 , n510 ,
n511 , n512 , n513 , n514 , n515 , n516 , n517 , n518 , n519 , n520 ,
n521 , n522 , n523 , n524 , n525 , n526 , n527 , n528 , n529 , n530 ,
n531 , n532 , n533 , n534 , n535 , n536 , n537 , n538 , n539 , n540 ,
n541 , n542 , n543 , n544 , n545 , n546 , n547 , n548 , n549 , n550 ,
n551 , n552 , n553 , n554 , n555 , n556 , n557 , n558 , n559 , n560 ,
n561 , n562 , n563 , n564 , n565 , n566 , n567 , n568 , n569 , n570 ,
n571 , n572 , n573 , n574 , n575 , n576 , n577 , n578 , n579 , n580 ,
n581 , n582 , n583 , n584 , n585 , n586 , n587 , n588 , n589 , n590 ,
n591 , n592 , n593 , n594 , n595 , n596 , n597 , n598 , n599 , n600 ,
n601 , n602 , n603 , n604 , n605 , n606 , n607 , n608 , n609 , n610 ,
n611 , n612 , n613 , n614 , n615 , n616 , n617 , n618 , n619 , n620 ,
n621 , n622 , n623 , n624 , n625 , n626 , n627 , n628 , n629 , n630 ,
n631 , n632 , n633 , n634 , n635 , n636 , n637 , n638 , n639 , n640 ,
n641 , n642 , n643 , n644 , n645 , n646 , n647 , n648 , n649 , n650 ,
n651 , n652 , n653 , n654 , n655 , n656 , n657 , n658 , n659 , n660 ,
n661 , n662 , n663 , n664 , n665 , n666 , n667 , n668 , n669 , n670 ,
n671 , n672 , n673 , n674 , n675 , n676 , n677 , n678 , n679 , n680 ,
n681 , n682 , n683 , n684 , n685 , n686 , n687 , n688 , n689 , n690 ,
n691 , n692 , n693 , n694 , n695 , n696 , n697 , n698 , n699 , n700 ,
n701 , n702 , n703 , n704 , n705 , n706 , n707 , n708 , n709 , n710 ,
n711 , n712 , n713 , n714 , n715 , n716 , n717 , n718 , n719 , n720 ,
n721 , n722 , n723 , n724 , n725 , n726 , n727 , n728 , n729 , n730 ,
n731 , n732 , n733 , n734 , n735 , n736 , n737 , n738 , n739 , n740 ,
n741 , n742 , n743 , n744 , n745 , n746 , n747 , n748 , n749 , n750 ,
n751 , n752 , n753 , n754 , n755 , n756 , n757 , n758 , n759 , n760 ,
n761 , n762 , n763 , n764 , n765 , n766 , n767 , n768 , n769 , n770 ,
n771 , n772 , n773 , n774 , n775 , n776 , n777 , n778 , n779 , n780 ,
n781 , n782 , n783 , n784 , n785 , n786 , n787 , n788 , n789 , n790 ,
n791 , n792 , n793 , n794 , n795 , n796 , n797 , n798 , n799 , n800 ,
n801 , n802 , n803 , n804 , n805 , n806 , n807 , n808 , n809 , n810 ,
n811 , n812 , n813 , n814 , n815 , n816 , n817 , n818 , n819 , n820 ,
n821 , n822 , n823 , n824 , n825 , n826 , n827 , n828 , n829 , n830 ,
n831 , n832 , n833 , n834 , n835 , n836 , n837 , n838 , n839 , n840 ,
n841 , n842 , n843 , n844 , n845 , n846 , n847 , n848 , n849 , n850 ,
n851 , n852 , n853 , n854 , n855 , n856 , n857 , n858 , n859 , n860 ,
n861 , n862 , n863 , n864 , n865 , n866 , n867 , n868 , n869 , n870 ,
n871 , n872 , n873 , n874 , n875 , n876 , n877 , n878 , n879 , n880 ,
n881 , n882 , n883 , n884 , n885 , n886 , n887 , n888 , n889 , n890 ,
n891 , n892 , n893 , n894 , n895 , n896 , n897 , n898 , n899 , n900 ,
n901 , n902 , n903 , n904 , n905 , n906 , n907 , n908 , n909 , n910 ,
n911 , n912 , n913 , n914 , n915 , n916 , n917 , n918 , n919 , n920 ,
n921 , n922 , n923 , n924 , n925 , n926 , n927 , n928 , n929 , n930 ,
n931 , n932 , n933 , n934 , n935 , n936 , n937 , n938 , n939 , n940 ,
n941 , n942 , n943 , n944 , n945 , n946 , n947 , n948 , n949 , n950 ,
n951 , n952 , n953 , n954 , n955 , n956 , n957 , n958 , n959 , n960 ,
n961 , n962 , n963 , n964 , n965 , n966 , n967 , n968 , n969 , n970 ,
n971 , n972 , n973 , n974 , n975 , n976 , n977 , n978 , n979 , n980 ,
n981 , n982 , n983 , n984 , n985 , n986 , n987 , n988 , n989 , n990 ,
n991 , n992 , n993 , n994 , n995 , n996 , n997 , n998 , n999 , n1000 ,
n1001 , n1002 , n1003 , n1004 , n1005 , n1006 , n1007 , n1008 , n1009 , n1010 ,
n1011 , n1012 , n1013 , n1014 , n1015 , n1016 , n1017 , n1018 , n1019 , n1020 ,
n1021 , n1022 , n1023 , n1024 , n1025 , n1026 , n1027 , n1028 , n1029 , n1030 ,
n1031 , n1032 , n1033 , n1034 , n1035 , n1036 , n1037 , n1038 , n1039 , n1040 ,
n1041 , n1042 , n1043 , n1044 , n1045 , n1046 , n1047 , n1048 , n1049 , n1050 ,
n1051 , n1052 , n1053 , n1054 , n1055 , n1056 , n1057 , n1058 , n1059 , n1060 ,
n1061 , n1062 , n1063 , n1064 , n1065 , n1066 , n1067 , n1068 , n1069 , n1070 ,
n1071 , n1072 , n1073 , n1074 , n1075 , n1076 , n1077 , n1078 , n1079 , n1080 ,
n1081 , n1082 , n1083 , n1084 , n1085 , n1086 , n1087 , n1088 , n1089 , n1090 ,
n1091 , n1092 , n1093 , n1094 , n1095 , n1096 , n1097 , n1098 , n1099 , n1100 ,
n1101 , n1102 , n1103 , n1104 , n1105 , n1106 , n1107 , n1108 , n1109 , n1110 ,
n1111 , n1112 , n1113 , n1114 , n1115 , n1116 , n1117 , n1118 , n1119 , n1120 ,
n1121 , n1122 , n1123 , n1124 , n1125 , n1126 , n1127 , n1128 , n1129 , n1130 ,
n1131 , n1132 , n1133 , n1134 , n1135 , n1136 , n1137 , n1138 , n1139 , n1140 ,
n1141 , n1142 , n1143 , n1144 , n1145 , n1146 , n1147 , n1148 , n1149 , n1150 ,
n1151 , n1152 , n1153 , n1154 , n1155 , n1156 , n1157 , n1158 , n1159 , n1160 ,
n1161 , n1162 , n1163 , n1164 , n1165 , n1166 , n1167 , n1168 , n1169 , n1170 ,
n1171 , n1172 , n1173 , n1174 , n1175 , n1176 , n1177 , n1178 , n1179 , n1180 ,
n1181 , n1182 , n1183 , n1184 , n1185 , n1186 , n1187 , n1188 , n1189 , n1190 ,
n1191 , n1192 , n1193 , n1194 , n1195 , n1196 , n1197 , n1198 , n1199 , n1200 ,
n1201 , n1202 , n1203 , n1204 , n1205 , n1206 , n1207 , n1208 , n1209 , n1210 ,
n1211 , n1212 , n1213 , n1214 , n1215 , n1216 , n1217 , n1218 , n1219 , n1220 ,
n1221 , n1222 , n1223 , n1224 , n1225 , n1226 , n1227 , n1228 , n1229 , n1230 ,
n1231 , n1232 , n1233 , n1234 , n1235 , n1236 , n1237 , n1238 , n1239 , n1240 ,
n1241 , n1242 , n1243 , n1244 , n1245 , n1246 , n1247 , n1248 , n1249 , n1250 ,
n1251 , n1252 , n1253 , n1254 , n1255 , n1256 , n1257 , n1258 , n1259 , n1260 ,
n1261 , n1262 , n1263 , n1264 , n1265 , n1266 , n1267 , n1268 , n1269 , n1270 ,
n1271 , n1272 , n1273 , n1274 , n1275 , n1276 , n1277 , n1278 , n1279 , n1280 ,
n1281 , n1282 , n1283 , n1284 , n1285 , n1286 , n1287 , n1288 , n1289 , n1290 ,
n1291 , n1292 , n1293 , n1294 , n1295 , n1296 , n1297 , n1298 , n1299 , n1300 ,
n1301 , n1302 , n1303 , n1304 , n1305 , n1306 , n1307 , n1308 , n1309 , n1310 ,
n1311 , n1312 , n1313 , n1314 , n1315 , n1316 , n1317 , n1318 , n1319 , n1320 ,
n1321 , n1322 , n1323 , n1324 , n1325 , n1326 , n1327 , n1328 , n1329 , n1330 ,
n1331 , n1332 , n1333 , n1334 , n1335 , n1336 , n1337 , n1338 , n1339 , n1340 ,
n1341 , n1342 , n1343 , n1344 , n1345 , n1346 , n1347 , n1348 , n1349 , n1350 ,
n1351 , n1352 , n1353 , n1354 , n1355 , n1356 , n1357 , n1358 , n1359 , n1360 ,
n1361 , n1362 , n1363 , n1364 , n1365 , n1366 , n1367 , n1368 , n1369 , n1370 ,
n1371 , n1372 , n1373 , n1374 , n1375 , n1376 , n1377 , n1378 , n1379 , n1380 ,
n1381 , n1382 , n1383 , n1384 , n1385 , n1386 , n1387 , n1388 , n1389 , n1390 ,
n1391 , n1392 , n1393 , n1394 , n1395 , n1396 , n1397 , n1398 , n1399 , n1400 ,
n1401 , n1402 , n1403 , n1404 , n1405 , n1406 , n1407 , n1408 , n1409 , n1410 ,
n1411 , n1412 , n1413 , n1414 , n1415 , n1416 , n1417 , n1418 , n1419 , n1420 ,
n1421 , n1422 , n1423 , n1424 , n1425 , n1426 , n1427 , n1428 , n1429 , n1430 ,
n1431 , n1432 , n1433 , n1434 , n1435 , n1436 , n1437 , n1438 , n1439 , n1440 ,
n1441 , n1442 , n1443 , n1444 , n1445 , n1446 , n1447 , n1448 , n1449 , n1450 ,
n1451 , n1452 , n1453 , n1454 , n1455 , n1456 , n1457 , n1458 , n1459 , n1460 ,
n1461 , n1462 , n1463 , n1464 , n1465 , n1466 , n1467 , n1468 , n1469 , n1470 ,
n1471 , n1472 , n1473 , n1474 , n1475 , n1476 , n1477 , n1478 , n1479 , n1480 ,
n1481 , n1482 , n1483 , n1484 , n1485 , n1486 , n1487 , n1488 , n1489 , n1490 ,
n1491 , n1492 , n1493 , n1494 , n1495 , n1496 , n1497 , n1498 , n1499 , n1500 ,
n1501 , n1502 , n1503 , n1504 , n1505 , n1506 , n1507 , n1508 , n1509 , n1510 ,
n1511 , n1512 , n1513 , n1514 , n1515 , n1516 , n1517 , n1518 , n1519 , n1520 ,
n1521 , n1522 , n1523 , n1524 , n1525 , n1526 , n1527 , n1528 , n1529 , n1530 ,
n1531 , n1532 , n1533 , n1534 , n1535 , n1536 , n1537 , n1538 , n1539 , n1540 ,
n1541 , n1542 , n1543 , n1544 , n1545 , n1546 , n1547 , n1548 , n1549 , n1550 ,
n1551 , n1552 , n1553 , n1554 , n1555 , n1556 , n1557 , n1558 , n1559 , n1560 ,
n1561 , n1562 , n1563 , n1564 , n1565 , n1566 , n1567 , n1568 , n1569 , n1570 ,
n1571 , n1572 , n1573 , n1574 , n1575 , n1576 , n1577 , n1578 , n1579 , n1580 ,
n1581 , n1582 , n1583 , n1584 , n1585 , n1586 , n1587 , n1588 , n1589 , n1590 ,
n1591 , n1592 , n1593 , n1594 , n1595 , n1596 , n1597 , n1598 , n1599 , n1600 ,
n1601 , n1602 , n1603 , n1604 , n1605 , n1606 , n1607 , n1608 , n1609 , n1610 ,
n1611 , n1612 , n1613 , n1614 , n1615 , n1616 , n1617 , n1618 , n1619 , n1620 ,
n1621 , n1622 , n1623 , n1624 , n1625 , n1626 , n1627 , n1628 , n1629 , n1630 ,
n1631 , n1632 , n1633 , n1634 , n1635 , n1636 , n1637 , n1638 , n1639 , n1640 ,
n1641 , n1642 , n1643 , n1644 , n1645 , n1646 , n1647 , n1648 , n1649 , n1650 ,
n1651 , n1652 , n1653 , n1654 , n1655 , n1656 , n1657 , n1658 , n1659 , n1660 ,
n1661 , n1662 , n1663 , n1664 , n1665 , n1666 , n1667 , n1668 , n1669 , n1670 ,
n1671 , n1672 , n1673 , n1674 , n1675 , n1676 , n1677 , n1678 , n1679 , n1680 ,
n1681 , n1682 , n1683 , n1684 , n1685 , n1686 , n1687 , n1688 , n1689 , n1690 ,
n1691 , n1692 , n1693 , n1694 , n1695 , n1696 , n1697 , n1698 , n1699 , n1700 ,
n1701 , n1702 , n1703 , n1704 , n1705 , n1706 , n1707 , n1708 , n1709 , n1710 ,
n1711 , n1712 , n1713 , n1714 , n1715 , n1716 , n1717 , n1718 , n1719 , n1720 ,
n1721 , n1722 , n1723 , n1724 , n1725 , n1726 , n1727 , n1728 , n1729 , n1730 ,
n1731 , n1732 , n1733 , n1734 , n1735 , n1736 , n1737 , n1738 , n1739 , n1740 ,
n1741 , n1742 , n1743 , n1744 , n1745 , n1746 , n1747 , n1748 , n1749 , n1750 ,
n1751 , n1752 , n1753 , n1754 , n1755 , n1756 , n1757 , n1758 , n1759 , n1760 ,
n1761 , n1762 , n1763 , n1764 , n1765 , n1766 , n1767 , n1768 , n1769 , n1770 ,
n1771 , n1772 , n1773 , n1774 , n1775 , n1776 , n1777 , n1778 , n1779 , n1780 ,
n1781 , n1782 , n1783 , n1784 , n1785 , n1786 , n1787 , n1788 , n1789 , n1790 ,
n1791 , n1792 , n1793 , n1794 , n1795 , n1796 , n1797 , n1798 , n1799 , n1800 ,
n1801 , n1802 , n1803 , n1804 , n1805 , n1806 , n1807 , n1808 , n1809 , n1810 ,
n1811 , n1812 , n1813 , n1814 , n1815 , n1816 , n1817 , n1818 , n1819 , n1820 ,
n1821 , n1822 , n1823 , n1824 , n1825 , n1826 , n1827 , n1828 , n1829 , n1830 ,
n1831 , n1832 , n1833 , n1834 , n1835 , n1836 , n1837 , n1838 , n1839 , n1840 ,
n1841 , n1842 , n1843 , n1844 , n1845 , n1846 , n1847 , n1848 , n1849 , n1850 ,
n1851 , n1852 , n1853 , n1854 , n1855 , n1856 , n1857 , n1858 , n1859 , n1860 ,
n1861 , n1862 , n1863 , n1864 , n1865 , n1866 , n1867 , n1868 , n1869 , n1870 ,
n1871 , n1872 , n1873 , n1874 , n1875 , n1876 , n1877 , n1878 , n1879 , n1880 ,
n1881 , n1882 , n1883 , n1884 , n1885 , n1886 , n1887 , n1888 , n1889 , n1890 ,
n1891 , n1892 , n1893 , n1894 , n1895 , n1896 , n1897 , n1898 , n1899 , n1900 ,
n1901 , n1902 , n1903 , n1904 , n1905 , n1906 , n1907 , n1908 , n1909 , n1910 ,
n1911 , n1912 , n1913 , n1914 , n1915 , n1916 , n1917 , n1918 , n1919 , n1920 ,
n1921 , n1922 , n1923 , n1924 , n1925 , n1926 , n1927 , n1928 , n1929 , n1930 ,
n1931 , n1932 , n1933 , n1934 , n1935 , n1936 , n1937 , n1938 , n1939 , n1940 ,
n1941 , n1942 , n1943 , n1944 , n1945 , n1946 , n1947 , n1948 , n1949 , n1950 ,
n1951 , n1952 , n1953 , n1954 , n1955 , n1956 , n1957 , n1958 , n1959 , n1960 ,
n1961 , n1962 , n1963 , n1964 , n1965 , n1966 , n1967 , n1968 , n1969 , n1970 ,
n1971 , n1972 , n1973 , n1974 , n1975 , n1976 , n1977 , n1978 , n1979 , n1980 ,
n1981 , n1982 , n1983 , n1984 , n1985 , n1986 , n1987 , n1988 , n1989 , n1990 ,
n1991 , n1992 , n1993 , n1994 , n1995 , n1996 , n1997 , n1998 , n1999 , n2000 ,
n2001 , n2002 , n2003 , n2004 , n2005 , n2006 , n2007 , n2008 , n2009 , n2010 ,
n2011 , n2012 , n2013 , n2014 , n2015 , n2016 , n2017 , n2018 , n2019 , n2020 ,
n2021 , n2022 , n2023 , n2024 , n2025 , n2026 , n2027 , n2028 , n2029 , n2030 ,
n2031 , n2032 , n2033 , n2034 , n2035 , n2036 , n2037 , n2038 , n2039 , n2040 ,
n2041 , n2042 , n2043 , n2044 , n2045 , n2046 , n2047 , n2048 , n2049 , n2050 ,
n2051 , n2052 , n2053 , n2054 , n2055 , n2056 , n2057 , n2058 , n2059 , n2060 ,
n2061 , n2062 , n2063 , n2064 , n2065 , n2066 , n2067 , n2068 , n2069 , n2070 ,
n2071 , n2072 , n2073 , n2074 , n2075 , n2076 , n2077 , n2078 , n2079 , n2080 ,
n2081 , n2082 , n2083 , n2084 , n2085 , n2086 , n2087 , n2088 , n2089 , n2090 ,
n2091 , n2092 , n2093 , n2094 , n2095 , n2096 , n2097 , n2098 , n2099 , n2100 ,
n2101 , n2102 , n2103 , n2104 , n2105 , n2106 , n2107 , n2108 , n2109 , n2110 ,
n2111 , n2112 , n2113 , n2114 , n2115 , n2116 , n2117 , n2118 , n2119 , n2120 ,
n2121 , n2122 , n2123 , n2124 , n2125 , n2126 , n2127 , n2128 , n2129 , n2130 ,
n2131 , n2132 , n2133 , n2134 , n2135 , n2136 , n2137 , n2138 , n2139 , n2140 ,
n2141 , n2142 , n2143 , n2144 , n2145 , n2146 , n2147 , n2148 , n2149 , n2150 ,
n2151 , n2152 , n2153 , n2154 , n2155 , n2156 , n2157 , n2158 , n2159 , n2160 ,
n2161 , n2162 , n2163 , n2164 , n2165 , n2166 , n2167 , n2168 , n2169 , n2170 ,
n2171 , n2172 , n2173 , n2174 , n2175 , n2176 , n2177 , n2178 , n2179 , n2180 ,
n2181 , n2182 , n2183 , n2184 , n2185 , n2186 , n2187 , n2188 , n2189 , n2190 ,
n2191 , n2192 , n2193 , n2194 , n2195 , n2196 , n2197 , n2198 , n2199 , n2200 ,
n2201 , n2202 , n2203 , n2204 , n2205 , n2206 , n2207 , n2208 , n2209 , n2210 ,
n2211 , n2212 , n2213 , n2214 , n2215 , n2216 , n2217 , n2218 , n2219 , n2220 ,
n2221 , n2222 , n2223 , n2224 , n2225 , n2226 , n2227 , n2228 , n2229 , n2230 ,
n2231 , n2232 , n2233 , n2234 , n2235 , n2236 , n2237 , n2238 , n2239 , n2240 ,
n2241 , n2242 , n2243 , n2244 , n2245 , n2246 , n2247 , n2248 , n2249 , n2250 ,
n2251 , n2252 , n2253 , n2254 , n2255 , n2256 , n2257 , n2258 , n2259 , n2260 ,
n2261 , n2262 , n2263 , n2264 , n2265 , n2266 , n2267 , n2268 , n2269 , n2270 ,
n2271 , n2272 , n2273 , n2274 , n2275 , n2276 , n2277 , n2278 , n2279 , n2280 ,
n2281 , n2282 , n2283 , n2284 , n2285 , n2286 , n2287 , n2288 , n2289 , n2290 ,
n2291 , n2292 , n2293 , n2294 , n2295 , n2296 , n2297 , n2298 , n2299 , n2300 ,
n2301 , n2302 , n2303 , n2304 , n2305 , n2306 , n2307 , n2308 , n2309 , n2310 ,
n2311 , n2312 , n2313 , n2314 , n2315 , n2316 , n2317 , n2318 , n2319 , n2320 ,
n2321 , n2322 , n2323 , n2324 , n2325 , n2326 , n2327 , n2328 , n2329 , n2330 ,
n2331 , n2332 , n2333 , n2334 , n2335 , n2336 , n2337 , n2338 , n2339 , n2340 ,
n2341 , n2342 , n2343 , n2344 , n2345 , n2346 , n2347 , n2348 , n2349 , n2350 ,
n2351 , n2352 , n2353 , n2354 , n2355 , n2356 , n2357 , n2358 , n2359 , n2360 ,
n2361 , n2362 , n2363 , n2364 , n2365 , n2366 , n2367 , n2368 , n2369 , n2370 ,
n2371 , n2372 , n2373 , n2374 , n2375 , n2376 , n2377 , n2378 , n2379 , n2380 ,
n2381 , n2382 , n2383 , n2384 , n2385 , n2386 , n2387 , n2388 , n2389 , n2390 ,
n2391 , n2392 , n2393 , n2394 , n2395 , n2396 , n2397 , n2398 , n2399 , n2400 ,
n2401 , n2402 , n2403 , n2404 , n2405 , n2406 , n2407 , n2408 , n2409 , n2410 ,
n2411 , n2412 , n2413 , n2414 , n2415 , n2416 , n2417 , n2418 , n2419 , n2420 ,
n2421 , n2422 , n2423 , n2424 , n2425 , n2426 , n2427 , n2428 , n2429 , n2430 ,
n2431 , n2432 , n2433 , n2434 , n2435 , n2436 , n2437 , n2438 , n2439 , n2440 ,
n2441 , n2442 , n2443 , n2444 , n2445 , n2446 , n2447 , n2448 , n2449 , n2450 ,
n2451 , n2452 , n2453 , n2454 , n2455 , n2456 , n2457 , n2458 , n2459 , n2460 ,
n2461 , n2462 , n2463 , n2464 , n2465 , n2466 , n2467 , n2468 , n2469 , n2470 ,
n2471 , n2472 , n2473 , n2474 , n2475 , n2476 , n2477 , n2478 , n2479 , n2480 ,
n2481 , n2482 , n2483 , n2484 , n2485 , n2486 , n2487 , n2488 , n2489 , n2490 ,
n2491 , n2492 , n2493 , n2494 , n2495 , n2496 , n2497 , n2498 , n2499 , n2500 ,
n2501 , n2502 , n2503 , n2504 , n2505 , n2506 , n2507 , n2508 , n2509 , n2510 ,
n2511 , n2512 , n2513 , n2514 , n2515 , n2516 , n2517 , n2518 , n2519 , n2520 ,
n2521 , n2522 , n2523 , n2524 , n2525 , n2526 , n2527 , n2528 , n2529 , n2530 ,
n2531 , n2532 , n2533 , n2534 , n2535 , n2536 , n2537 , n2538 , n2539 , n2540 ,
n2541 , n2542 , n2543 , n2544 , n2545 , n2546 , n2547 , n2548 , n2549 , n2550 ,
n2551 , n2552 , n2553 , n2554 , n2555 , n2556 , n2557 , n2558 , n2559 , n2560 ,
n2561 , n2562 , n2563 , n2564 , n2565 , n2566 , n2567 , n2568 , n2569 , n2570 ,
n2571 , n2572 , n2573 , n2574 , n2575 , n2576 , n2577 , n2578 , n2579 , n2580 ,
n2581 , n2582 , n2583 , n2584 , n2585 , n2586 , n2587 , n2588 , n2589 , n2590 ,
n2591 , n2592 , n2593 , n2594 , n2595 , n2596 , n2597 , n2598 , n2599 , n2600 ,
n2601 , n2602 , n2603 , n2604 , n2605 , n2606 , n2607 , n2608 , n2609 , n2610 ,
n2611 , n2612 , n2613 , n2614 , n2615 , n2616 , n2617 , n2618 , n2619 , n2620 ,
n2621 , n2622 , n2623 , n2624 , n2625 , n2626 , n2627 , n2628 , n2629 , n2630 ,
n2631 , n2632 , n2633 , n2634 , n2635 , n2636 , n2637 , n2638 , n2639 , n2640 ,
n2641 , n2642 , n2643 , n2644 , n2645 , n2646 , n2647 , n2648 , n2649 , n2650 ,
n2651 , n2652 , n2653 , n2654 , n2655 , n2656 , n2657 , n2658 , n2659 , n2660 ,
n2661 , n2662 , n2663 , n2664 , n2665 , n2666 , n2667 , n2668 , n2669 , n2670 ,
n2671 , n2672 , n2673 , n2674 , n2675 , n2676 , n2677 , n2678 , n2679 , n2680 ,
n2681 , n2682 , n2683 , n2684 , n2685 , n2686 , n2687 , n2688 , n2689 , n2690 ,
n2691 , n2692 , n2693 , n2694 , n2695 , n2696 , n2697 , n2698 , n2699 , n2700 ,
n2701 , n2702 , n2703 , n2704 , n2705 , n2706 , n2707 , n2708 , n2709 , n2710 ,
n2711 , n2712 , n2713 , n2714 , n2715 , n2716 , n2717 , n2718 , n2719 , n2720 ,
n2721 , n2722 , n2723 , n2724 , n2725 , n2726 , n2727 , n2728 , n2729 , n2730 ,
n2731 , n2732 , n2733 , n2734 , n2735 , n2736 , n2737 , n2738 , n2739 , n2740 ,
n2741 , n2742 , n2743 , n2744 , n2745 , n2746 , n2747 , n2748 , n2749 , n2750 ,
n2751 , n2752 , n2753 , n2754 , n2755 , n2756 , n2757 , n2758 , n2759 , n2760 ,
n2761 , n2762 , n2763 , n2764 , n2765 , n2766 , n2767 , n2768 , n2769 , n2770 ,
n2771 , n2772 , n2773 , n2774 , n2775 , n2776 , n2777 , n2778 , n2779 , n2780 ,
n2781 , n2782 , n2783 , n2784 , n2785 , n2786 , n2787 , n2788 , n2789 , n2790 ,
n2791 , n2792 , n2793 , n2794 , n2795 , n2796 , n2797 , n2798 , n2799 , n2800 ,
n2801 , n2802 , n2803 , n2804 , n2805 , n2806 , n2807 , n2808 , n2809 , n2810 ,
n2811 , n2812 , n2813 , n2814 , n2815 , n2816 , n2817 , n2818 , n2819 , n2820 ,
n2821 , n2822 , n2823 , n2824 , n2825 , n2826 , n2827 , n2828 , n2829 , n2830 ,
n2831 , n2832 , n2833 , n2834 , n2835 , n2836 , n2837 , n2838 , n2839 , n2840 ,
n2841 , n2842 , n2843 , n2844 , n2845 , n2846 , n2847 , n2848 , n2849 , n2850 ,
n2851 , n2852 , n2853 , n2854 , n2855 , n2856 , n2857 , n2858 , n2859 , n2860 ,
n2861 , n2862 , n2863 , n2864 , n2865 , n2866 , n2867 , n2868 , n2869 , n2870 ,
n2871 , n2872 , n2873 , n2874 , n2875 , n2876 , n2877 , n2878 , n2879 , n2880 ,
n2881 , n2882 , n2883 , n2884 , n2885 , n2886 , n2887 , n2888 , n2889 , n2890 ,
n2891 , n2892 , n2893 , n2894 , n2895 , n2896 , n2897 , n2898 , n2899 , n2900 ,
n2901 , n2902 , n2903 , n2904 , n2905 , n2906 , n2907 , n2908 , n2909 , n2910 ,
n2911 , n2912 , n2913 , n2914 , n2915 , n2916 , n2917 , n2918 , n2919 , n2920 ,
n2921 , n2922 , n2923 , n2924 , n2925 , n2926 , n2927 , n2928 , n2929 , n2930 ,
n2931 , n2932 , n2933 , n2934 , n2935 , n2936 , n2937 , n2938 , n2939 , n2940 ,
n2941 , n2942 , n2943 , n2944 , n2945 , n2946 , n2947 , n2948 , n2949 , n2950 ,
n2951 , n2952 , n2953 , n2954 , n2955 , n2956 , n2957 , n2958 , n2959 , n2960 ,
n2961 , n2962 , n2963 , n2964 , n2965 , n2966 , n2967 , n2968 , n2969 , n2970 ,
n2971 , n2972 , n2973 , n2974 , n2975 , n2976 , n2977 , n2978 , n2979 , n2980 ,
n2981 , n2982 , n2983 , n2984 , n2985 , n2986 , n2987 , n2988 , n2989 , n2990 ,
n2991 , n2992 , n2993 , n2994 , n2995 , n2996 , n2997 , n2998 , n2999 , n3000 ,
n3001 , n3002 , n3003 , n3004 , n3005 , n3006 , n3007 , n3008 , n3009 , n3010 ,
n3011 , n3012 , n3013 , n3014 , n3015 , n3016 , n3017 , n3018 , n3019 , n3020 ,
n3021 , n3022 , n3023 , n3024 , n3025 , n3026 , n3027 , n3028 , n3029 , n3030 ,
n3031 , n3032 , n3033 , n3034 , n3035 , n3036 , n3037 , n3038 , n3039 , n3040 ,
n3041 , n3042 , n3043 , n3044 , n3045 , n3046 , n3047 , n3048 , n3049 , n3050 ,
n3051 , n3052 , n3053 , n3054 , n3055 , n3056 , n3057 , n3058 , n3059 , n3060 ,
n3061 , n3062 , n3063 , n3064 , n3065 , n3066 , n3067 , n3068 , n3069 , n3070 ,
n3071 , n3072 , n3073 , n3074 , n3075 , n3076 , n3077 , n3078 , n3079 , n3080 ,
n3081 , n3082 , n3083 , n3084 , n3085 , n3086 , n3087 , n3088 , n3089 , n3090 ,
n3091 , n3092 , n3093 , n3094 , n3095 , n3096 , n3097 , n3098 , n3099 , n3100 ,
n3101 , n3102 , n3103 , n3104 , n3105 , n3106 , n3107 , n3108 , n3109 , n3110 ,
n3111 , n3112 , n3113 , n3114 , n3115 , n3116 , n3117 , n3118 , n3119 , n3120 ,
n3121 , n3122 , n3123 , n3124 , n3125 , n3126 , n3127 , n3128 , n3129 , n3130 ,
n3131 , n3132 , n3133 , n3134 , n3135 , n3136 , n3137 , n3138 , n3139 , n3140 ,
n3141 , n3142 , n3143 , n3144 , n3145 , n3146 , n3147 , n3148 , n3149 , n3150 ,
n3151 , n3152 , n3153 , n3154 , n3155 , n3156 , n3157 , n3158 , n3159 , n3160 ,
n3161 , n3162 , n3163 , n3164 , n3165 , n3166 , n3167 , n3168 , n3169 , n3170 ,
n3171 , n3172 , n3173 , n3174 , n3175 , n3176 , n3177 , n3178 , n3179 , n3180 ,
n3181 , n3182 , n3183 , n3184 , n3185 , n3186 , n3187 , n3188 , n3189 , n3190 ,
n3191 , n3192 , n3193 , n3194 , n3195 , n3196 , n3197 , n3198 , n3199 , n3200 ,
n3201 , n3202 , n3203 , n3204 , n3205 , n3206 , n3207 , n3208 , n3209 , n3210 ,
n3211 , n3212 , n3213 , n3214 , n3215 , n3216 , n3217 , n3218 , n3219 , n3220 ,
n3221 , n3222 , n3223 , n3224 , n3225 , n3226 , n3227 , n3228 , n3229 , n3230 ,
n3231 , n3232 , n3233 , n3234 , n3235 , n3236 , n3237 , n3238 , n3239 , n3240 ,
n3241 , n3242 , n3243 , n3244 , n3245 , n3246 , n3247 , n3248 , n3249 , n3250 ,
n3251 , n3252 , n3253 , n3254 , n3255 , n3256 , n3257 , n3258 , n3259 , n3260 ,
n3261 , n3262 , n3263 , n3264 , n3265 , n3266 , n3267 , n3268 , n3269 , n3270 ,
n3271 , n3272 , n3273 , n3274 , n3275 , n3276 , n3277 , n3278 , n3279 , n3280 ,
n3281 , n3282 , n3283 , n3284 , n3285 , n3286 , n3287 , n3288 , n3289 , n3290 ,
n3291 , n3292 , n3293 , n3294 , n3295 , n3296 , n3297 , n3298 , n3299 , n3300 ,
n3301 , n3302 , n3303 , n3304 , n3305 , n3306 , n3307 , n3308 , n3309 , n3310 ,
n3311 , n3312 , n3313 , n3314 , n3315 , n3316 , n3317 , n3318 , n3319 , n3320 ,
n3321 , n3322 , n3323 , n3324 , n3325 , n3326 , n3327 , n3328 , n3329 , n3330 ,
n3331 , n3332 , n3333 , n3334 , n3335 , n3336 , n3337 , n3338 , n3339 , n3340 ,
n3341 , n3342 , n3343 , n3344 , n3345 , n3346 , n3347 , n3348 , n3349 , n3350 ,
n3351 , n3352 , n3353 , n3354 , n3355 , n3356 , n3357 , n3358 , n3359 , n3360 ,
n3361 , n3362 , n3363 , n3364 , n3365 , n3366 , n3367 , n3368 , n3369 , n3370 ,
n3371 , n3372 , n3373 , n3374 , n3375 , n3376 , n3377 , n3378 , n3379 , n3380 ,
n3381 , n3382 , n3383 , n3384 , n3385 , n3386 , n3387 , n3388 , n3389 , n3390 ,
n3391 , n3392 , n3393 , n3394 , n3395 , n3396 , n3397 , n3398 , n3399 , n3400 ,
n3401 , n3402 , n3403 , n3404 , n3405 , n3406 , n3407 , n3408 , n3409 , n3410 ,
n3411 , n3412 , n3413 , n3414 , n3415 , n3416 , n3417 , n3418 , n3419 , n3420 ,
n3421 , n3422 , n3423 , n3424 , n3425 , n3426 , n3427 , n3428 , n3429 , n3430 ,
n3431 , n3432 , n3433 , n3434 , n3435 , n3436 , n3437 , n3438 , n3439 , n3440 ,
n3441 , n3442 , n3443 , n3444 , n3445 , n3446 , n3447 , n3448 , n3449 , n3450 ,
n3451 , n3452 , n3453 , n3454 , n3455 , n3456 , n3457 , n3458 , n3459 , n3460 ,
n3461 , n3462 , n3463 , n3464 , n3465 , n3466 , n3467 , n3468 , n3469 , n3470 ,
n3471 , n3472 , n3473 , n3474 , n3475 , n3476 , n3477 , n3478 , n3479 , n3480 ,
n3481 , n3482 , n3483 , n3484 , n3485 , n3486 , n3487 , n3488 , n3489 , n3490 ,
n3491 , n3492 , n3493 , n3494 , n3495 , n3496 , n3497 , n3498 , n3499 , n3500 ,
n3501 , n3502 , n3503 , n3504 , n3505 , n3506 , n3507 , n3508 , n3509 , n3510 ,
n3511 , n3512 , n3513 , n3514 , n3515 , n3516 , n3517 , n3518 , n3519 , n3520 ,
n3521 , n3522 , n3523 , n3524 , n3525 , n3526 , n3527 , n3528 , n3529 , n3530 ,
n3531 , n3532 , n3533 , n3534 , n3535 , n3536 , n3537 , n3538 , n3539 , n3540 ,
n3541 , n3542 , n3543 , n3544 , n3545 , n3546 , n3547 , n3548 , n3549 , n3550 ,
n3551 , n3552 , n3553 , n3554 , n3555 , n3556 , n3557 , n3558 , n3559 , n3560 ,
n3561 , n3562 , n3563 , n3564 , n3565 , n3566 , n3567 , n3568 , n3569 , n3570 ,
n3571 , n3572 , n3573 , n3574 , n3575 , n3576 , n3577 , n3578 , n3579 , n3580 ,
n3581 , n3582 , n3583 , n3584 , n3585 , n3586 , n3587 , n3588 , n3589 , n3590 ,
n3591 , n3592 , n3593 , n3594 , n3595 , n3596 , n3597 , n3598 , n3599 , n3600 ,
n3601 , n3602 , n3603 , n3604 , n3605 , n3606 , n3607 , n3608 , n3609 , n3610 ,
n3611 , n3612 , n3613 , n3614 , n3615 , n3616 , n3617 , n3618 , n3619 , n3620 ,
n3621 , n3622 , n3623 , n3624 , n3625 , n3626 , n3627 , n3628 , n3629 , n3630 ,
n3631 , n3632 , n3633 , n3634 , n3635 , n3636 , n3637 , n3638 , n3639 , n3640 ,
n3641 , n3642 , n3643 , n3644 , n3645 , n3646 , n3647 , n3648 , n3649 , n3650 ,
n3651 , n3652 , n3653 , n3654 , n3655 , n3656 , n3657 , n3658 , n3659 , n3660 ,
n3661 , n3662 , n3663 , n3664 , n3665 , n3666 , n3667 , n3668 , n3669 , n3670 ,
n3671 , n3672 , n3673 , n3674 , n3675 , n3676 , n3677 , n3678 , n3679 , n3680 ,
n3681 , n3682 , n3683 , n3684 , n3685 , n3686 , n3687 , n3688 , n3689 , n3690 ,
n3691 , n3692 , n3693 , n3694 , n3695 , n3696 , n3697 , n3698 , n3699 , n3700 ,
n3701 , n3702 , n3703 , n3704 , n3705 , n3706 , n3707 , n3708 , n3709 , n3710 ,
n3711 , n3712 , n3713 , n3714 , n3715 , n3716 , n3717 , n3718 , n3719 , n3720 ,
n3721 , n3722 , n3723 , n3724 , n3725 , n3726 , n3727 , n3728 , n3729 , n3730 ,
n3731 , n3732 , n3733 , n3734 , n3735 , n3736 , n3737 , n3738 , n3739 , n3740 ,
n3741 , n3742 , n3743 , n3744 , n3745 , n3746 , n3747 , n3748 , n3749 , n3750 ,
n3751 , n3752 , n3753 , n3754 , n3755 , n3756 , n3757 , n3758 , n3759 , n3760 ,
n3761 , n3762 , n3763 , n3764 , n3765 , n3766 , n3767 , n3768 , n3769 , n3770 ,
n3771 , n3772 , n3773 , n3774 , n3775 , n3776 , n3777 , n3778 , n3779 , n3780 ,
n3781 , n3782 , n3783 , n3784 , n3785 , n3786 , n3787 , n3788 , n3789 , n3790 ,
n3791 , n3792 , n3793 , n3794 , n3795 , n3796 , n3797 , n3798 , n3799 , n3800 ,
n3801 , n3802 , n3803 , n3804 , n3805 , n3806 , n3807 , n3808 , n3809 , n3810 ,
n3811 , n3812 , n3813 , n3814 , n3815 , n3816 , n3817 , n3818 , n3819 , n3820 ,
n3821 , n3822 , n3823 , n3824 , n3825 , n3826 , n3827 , n3828 , n3829 , n3830 ,
n3831 , n3832 , n3833 , n3834 , n3835 , n3836 , n3837 , n3838 , n3839 , n3840 ,
n3841 , n3842 , n3843 , n3844 , n3845 , n3846 , n3847 , n3848 , n3849 , n3850 ,
n3851 , n3852 , n3853 , n3854 , n3855 , n3856 , n3857 , n3858 , n3859 , n3860 ,
n3861 , n3862 , n3863 , n3864 , n3865 , n3866 , n3867 , n3868 , n3869 , n3870 ,
n3871 , n3872 , n3873 , n3874 , n3875 , n3876 , n3877 , n3878 , n3879 , n3880 ,
n3881 , n3882 , n3883 , n3884 , n3885 , n3886 , n3887 , n3888 , n3889 , n3890 ,
n3891 , n3892 , n3893 , n3894 , n3895 , n3896 , n3897 , n3898 , n3899 , n3900 ,
n3901 , n3902 , n3903 , n3904 , n3905 , n3906 , n3907 , n3908 , n3909 , n3910 ,
n3911 , n3912 , n3913 , n3914 , n3915 , n3916 , n3917 , n3918 , n3919 , n3920 ,
n3921 , n3922 , n3923 , n3924 , n3925 , n3926 , n3927 , n3928 , n3929 , n3930 ,
n3931 , n3932 , n3933 , n3934 , n3935 , n3936 , n3937 , n3938 , n3939 , n3940 ,
n3941 , n3942 , n3943 , n3944 , n3945 , n3946 , n3947 , n3948 , n3949 , n3950 ,
n3951 , n3952 , n3953 , n3954 , n3955 , n3956 , n3957 , n3958 , n3959 , n3960 ,
n3961 , n3962 , n3963 , n3964 , n3965 , n3966 , n3967 , n3968 , n3969 , n3970 ,
n3971 , n3972 , n3973 , n3974 , n3975 , n3976 , n3977 , n3978 , n3979 , n3980 ,
n3981 , n3982 , n3983 , n3984 , n3985 , n3986 , n3987 , n3988 , n3989 , n3990 ,
n3991 , n3992 , n3993 , n3994 , n3995 , n3996 , n3997 , n3998 , n3999 , n4000 ,
n4001 , n4002 , n4003 , n4004 , n4005 , n4006 , n4007 , n4008 , n4009 , n4010 ,
n4011 , n4012 , n4013 , n4014 , n4015 , n4016 , n4017 , n4018 , n4019 , n4020 ,
n4021 , n4022 , n4023 , n4024 , n4025 , n4026 , n4027 , n4028 , n4029 , n4030 ,
n4031 , n4032 , n4033 , n4034 , n4035 , n4036 , n4037 , n4038 , n4039 , n4040 ,
n4041 , n4042 , n4043 , n4044 , n4045 , n4046 , n4047 , n4048 , n4049 , n4050 ,
n4051 , n4052 , n4053 , n4054 , n4055 , n4056 , n4057 , n4058 , n4059 , n4060 ,
n4061 , n4062 , n4063 , n4064 , n4065 , n4066 , n4067 , n4068 , n4069 , n4070 ,
n4071 , n4072 , n4073 , n4074 , n4075 , n4076 , n4077 , n4078 , n4079 , n4080 ,
n4081 , n4082 , n4083 , n4084 , n4085 , n4086 , n4087 , n4088 , n4089 , n4090 ,
n4091 , n4092 , n4093 , n4094 , n4095 , n4096 , n4097 , n4098 , n4099 , n4100 ,
n4101 , n4102 , n4103 , n4104 , n4105 , n4106 , n4107 , n4108 , n4109 , n4110 ,
n4111 , n4112 , n4113 , n4114 , n4115 , n4116 , n4117 , n4118 , n4119 , n4120 ,
n4121 , n4122 , n4123 , n4124 , n4125 , n4126 , n4127 , n4128 , n4129 , n4130 ,
n4131 , n4132 , n4133 , n4134 , n4135 , n4136 , n4137 , n4138 , n4139 , n4140 ,
n4141 , n4142 , n4143 , n4144 , n4145 , n4146 , n4147 , n4148 , n4149 , n4150 ,
n4151 , n4152 , n4153 , n4154 , n4155 , n4156 , n4157 , n4158 , n4159 , n4160 ,
n4161 , n4162 , n4163 , n4164 , n4165 , n4166 , n4167 , n4168 , n4169 , n4170 ,
n4171 , n4172 , n4173 , n4174 , n4175 , n4176 , n4177 , n4178 , n4179 , n4180 ,
n4181 , n4182 , n4183 , n4184 , n4185 , n4186 , n4187 , n4188 , n4189 , n4190 ,
n4191 , n4192 , n4193 , n4194 , n4195 , n4196 , n4197 , n4198 , n4199 , n4200 ,
n4201 , n4202 , n4203 , n4204 , n4205 , n4206 , n4207 , n4208 , n4209 , n4210 ,
n4211 , n4212 , n4213 , n4214 , n4215 , n4216 , n4217 , n4218 , n4219 , n4220 ,
n4221 , n4222 , n4223 , n4224 , n4225 , n4226 , n4227 , n4228 , n4229 , n4230 ,
n4231 , n4232 , n4233 , n4234 , n4235 , n4236 , n4237 , n4238 , n4239 , n4240 ,
n4241 , n4242 , n4243 , n4244 , n4245 , n4246 , n4247 , n4248 , n4249 , n4250 ,
n4251 , n4252 , n4253 , n4254 , n4255 , n4256 , n4257 , n4258 , n4259 , n4260 ,
n4261 , n4262 , n4263 , n4264 , n4265 , n4266 , n4267 , n4268 , n4269 , n4270 ,
n4271 , n4272 , n4273 , n4274 , n4275 , n4276 , n4277 , n4278 , n4279 , n4280 ,
n4281 , n4282 , n4283 , n4284 , n4285 , n4286 , n4287 , n4288 , n4289 , n4290 ,
n4291 , n4292 , n4293 , n4294 , n4295 , n4296 , n4297 , n4298 , n4299 , n4300 ,
n4301 , n4302 , n4303 , n4304 , n4305 , n4306 , n4307 , n4308 , n4309 , n4310 ,
n4311 , n4312 , n4313 , n4314 , n4315 , n4316 , n4317 , n4318 , n4319 , n4320 ,
n4321 , n4322 , n4323 , n4324 , n4325 , n4326 , n4327 , n4328 , n4329 , n4330 ,
n4331 , n4332 , n4333 , n4334 , n4335 , n4336 , n4337 , n4338 , n4339 , n4340 ,
n4341 , n4342 , n4343 , n4344 , n4345 , n4346 , n4347 , n4348 , n4349 , n4350 ,
n4351 , n4352 , n4353 , n4354 , n4355 , n4356 , n4357 , n4358 , n4359 , n4360 ,
n4361 , n4362 , n4363 , n4364 , n4365 , n4366 , n4367 , n4368 , n4369 , n4370 ,
n4371 , n4372 , n4373 , n4374 , n4375 , n4376 , n4377 , n4378 , n4379 , n4380 ,
n4381 , n4382 , n4383 , n4384 , n4385 , n4386 , n4387 , n4388 , n4389 , n4390 ,
n4391 , n4392 , n4393 , n4394 , n4395 , n4396 , n4397 , n4398 , n4399 , n4400 ,
n4401 , n4402 , n4403 , n4404 , n4405 , n4406 , n4407 , n4408 , n4409 , n4410 ,
n4411 , n4412 , n4413 , n4414 , n4415 , n4416 , n4417 , n4418 , n4419 , n4420 ,
n4421 , n4422 , n4423 , n4424 , n4425 , n4426 , n4427 , n4428 , n4429 , n4430 ,
n4431 , n4432 , n4433 , n4434 , n4435 , n4436 , n4437 , n4438 , n4439 , n4440 ,
n4441 , n4442 , n4443 , n4444 , n4445 , n4446 , n4447 , n4448 , n4449 , n4450 ,
n4451 , n4452 , n4453 , n4454 , n4455 , n4456 , n4457 , n4458 , n4459 , n4460 ,
n4461 , n4462 , n4463 , n4464 , n4465 , n4466 , n4467 , n4468 , n4469 , n4470 ,
n4471 , n4472 , n4473 , n4474 , n4475 , n4476 , n4477 , n4478 , n4479 , n4480 ,
n4481 , n4482 , n4483 , n4484 , n4485 , n4486 , n4487 , n4488 , n4489 , n4490 ,
n4491 , n4492 , n4493 , n4494 , n4495 , n4496 , n4497 , n4498 , n4499 , n4500 ,
n4501 , n4502 , n4503 , n4504 , n4505 , n4506 , n4507 , n4508 , n4509 , n4510 ,
n4511 , n4512 , n4513 , n4514 , n4515 , n4516 , n4517 , n4518 , n4519 , n4520 ,
n4521 , n4522 , n4523 , n4524 , n4525 , n4526 , n4527 , n4528 , n4529 , n4530 ,
n4531 , n4532 , n4533 , n4534 , n4535 , n4536 , n4537 , n4538 , n4539 , n4540 ,
n4541 , n4542 , n4543 , n4544 , n4545 , n4546 , n4547 , n4548 , n4549 , n4550 ,
n4551 , n4552 , n4553 , n4554 , n4555 , n4556 , n4557 , n4558 , n4559 , n4560 ,
n4561 , n4562 , n4563 , n4564 , n4565 , n4566 , n4567 , n4568 , n4569 , n4570 ,
n4571 , n4572 , n4573 , n4574 , n4575 , n4576 , n4577 , n4578 , n4579 , n4580 ,
n4581 , n4582 , n4583 , n4584 , n4585 , n4586 , n4587 , n4588 , n4589 , n4590 ,
n4591 , n4592 , n4593 , n4594 , n4595 , n4596 , n4597 , n4598 , n4599 , n4600 ,
n4601 , n4602 , n4603 , n4604 , n4605 , n4606 , n4607 , n4608 , n4609 , n4610 ,
n4611 , n4612 , n4613 , n4614 , n4615 , n4616 , n4617 , n4618 , n4619 , n4620 ,
n4621 , n4622 , n4623 , n4624 , n4625 , n4626 , n4627 , n4628 , n4629 , n4630 ,
n4631 , n4632 , n4633 , n4634 , n4635 , n4636 , n4637 , n4638 , n4639 , n4640 ,
n4641 , n4642 , n4643 , n4644 , n4645 , n4646 , n4647 , n4648 , n4649 , n4650 ,
n4651 , n4652 , n4653 , n4654 , n4655 , n4656 , n4657 , n4658 , n4659 , n4660 ,
n4661 , n4662 , n4663 , n4664 , n4665 , n4666 , n4667 , n4668 , n4669 , n4670 ,
n4671 , n4672 , n4673 , n4674 , n4675 , n4676 , n4677 , n4678 , n4679 , n4680 ,
n4681 , n4682 , n4683 , n4684 , n4685 , n4686 , n4687 , n4688 , n4689 , n4690 ,
n4691 , n4692 , n4693 , n4694 , n4695 , n4696 , n4697 , n4698 , n4699 , n4700 ,
n4701 , n4702 , n4703 , n4704 , n4705 , n4706 , n4707 , n4708 , n4709 , n4710 ,
n4711 , n4712 , n4713 , n4714 , n4715 , n4716 , n4717 , n4718 , n4719 , n4720 ,
n4721 , n4722 , n4723 , n4724 , n4725 , n4726 , n4727 , n4728 , n4729 , n4730 ,
n4731 , n4732 , n4733 , n4734 , n4735 , n4736 , n4737 , n4738 , n4739 , n4740 ,
n4741 , n4742 , n4743 , n4744 , n4745 , n4746 , n4747 , n4748 , n4749 , n4750 ,
n4751 , n4752 , n4753 , n4754 , n4755 , n4756 , n4757 , n4758 , n4759 , n4760 ,
n4761 , n4762 , n4763 , n4764 , n4765 , n4766 , n4767 , n4768 , n4769 , n4770 ,
n4771 , n4772 , n4773 , n4774 , n4775 , n4776 , n4777 , n4778 , n4779 , n4780 ,
n4781 , n4782 , n4783 , n4784 , n4785 , n4786 , n4787 , n4788 , n4789 , n4790 ,
n4791 , n4792 , n4793 , n4794 , n4795 , n4796 , n4797 , n4798 , n4799 , n4800 ,
n4801 , n4802 , n4803 , n4804 , n4805 , n4806 , n4807 , n4808 , n4809 , n4810 ,
n4811 , n4812 , n4813 , n4814 , n4815 , n4816 , n4817 , n4818 , n4819 , n4820 ,
n4821 , n4822 , n4823 , n4824 , n4825 , n4826 , n4827 , n4828 , n4829 , n4830 ,
n4831 , n4832 , n4833 , n4834 , n4835 , n4836 , n4837 , n4838 , n4839 , n4840 ,
n4841 , n4842 , n4843 , n4844 , n4845 , n4846 , n4847 , n4848 , n4849 , n4850 ,
n4851 , n4852 , n4853 , n4854 , n4855 , n4856 , n4857 , n4858 , n4859 , n4860 ,
n4861 , n4862 , n4863 , n4864 , n4865 , n4866 , n4867 , n4868 , n4869 , n4870 ,
n4871 , n4872 , n4873 , n4874 , n4875 , n4876 , n4877 , n4878 , n4879 , n4880 ,
n4881 , n4882 , n4883 , n4884 , n4885 , n4886 , n4887 , n4888 , n4889 , n4890 ,
n4891 , n4892 , n4893 , n4894 , n4895 , n4896 , n4897 , n4898 , n4899 , n4900 ,
n4901 , n4902 , n4903 , n4904 , n4905 , n4906 , n4907 , n4908 , n4909 , n4910 ,
n4911 , n4912 , n4913 , n4914 , n4915 , n4916 , n4917 , n4918 , n4919 , n4920 ,
n4921 , n4922 , n4923 , n4924 , n4925 , n4926 , n4927 , n4928 , n4929 , n4930 ,
n4931 , n4932 , n4933 , n4934 , n4935 , n4936 , n4937 , n4938 , n4939 , n4940 ,
n4941 , n4942 , n4943 , n4944 , n4945 , n4946 , n4947 , n4948 , n4949 , n4950 ,
n4951 , n4952 , n4953 , n4954 , n4955 , n4956 , n4957 , n4958 , n4959 , n4960 ,
n4961 , n4962 , n4963 , n4964 , n4965 , n4966 , n4967 , n4968 , n4969 , n4970 ,
n4971 , n4972 , n4973 , n4974 , n4975 , n4976 , n4977 , n4978 , n4979 , n4980 ,
n4981 , n4982 , n4983 , n4984 , n4985 , n4986 , n4987 , n4988 , n4989 , n4990 ,
n4991 , n4992 , n4993 , n4994 , n4995 , n4996 , n4997 , n4998 , n4999 , n5000 ,
n5001 , n5002 , n5003 , n5004 , n5005 , n5006 , n5007 , n5008 , n5009 , n5010 ,
n5011 , n5012 , n5013 , n5014 , n5015 , n5016 , n5017 , n5018 , n5019 , n5020 ,
n5021 , n5022 , n5023 , n5024 , n5025 , n5026 , n5027 , n5028 , n5029 , n5030 ,
n5031 , n5032 , n5033 , n5034 , n5035 , n5036 , n5037 , n5038 , n5039 , n5040 ,
n5041 , n5042 , n5043 , n5044 , n5045 , n5046 , n5047 , n5048 , n5049 , n5050 ,
n5051 , n5052 , n5053 , n5054 , n5055 , n5056 , n5057 , n5058 , n5059 , n5060 ,
n5061 , n5062 , n5063 , n5064 , n5065 , n5066 , n5067 , n5068 , n5069 , n5070 ,
n5071 , n5072 , n5073 , n5074 , n5075 , n5076 , n5077 , n5078 , n5079 , n5080 ,
n5081 , n5082 , n5083 , n5084 , n5085 , n5086 , n5087 , n5088 , n5089 , n5090 ,
n5091 , n5092 , n5093 , n5094 , n5095 , n5096 , n5097 , n5098 , n5099 , n5100 ,
n5101 , n5102 , n5103 , n5104 , n5105 , n5106 , n5107 , n5108 , n5109 , n5110 ,
n5111 , n5112 , n5113 , n5114 , n5115 , n5116 , n5117 , n5118 , n5119 , n5120 ,
n5121 , n5122 , n5123 , n5124 , n5125 , n5126 , n5127 , n5128 , n5129 , n5130 ,
n5131 , n5132 , n5133 , n5134 , n5135 , n5136 , n5137 , n5138 , n5139 , n5140 ,
n5141 , n5142 , n5143 , n5144 , n5145 , n5146 , n5147 , n5148 , n5149 , n5150 ,
n5151 , n5152 , n5153 , n5154 , n5155 , n5156 , n5157 , n5158 , n5159 , n5160 ,
n5161 , n5162 , n5163 , n5164 , n5165 , n5166 , n5167 , n5168 , n5169 , n5170 ,
n5171 , n5172 , n5173 , n5174 , n5175 , n5176 , n5177 , n5178 , n5179 , n5180 ,
n5181 , n5182 , n5183 , n5184 , n5185 , n5186 , n5187 , n5188 , n5189 , n5190 ,
n5191 , n5192 , n5193 , n5194 , n5195 , n5196 , n5197 , n5198 , n5199 , n5200 ,
n5201 , n5202 , n5203 , n5204 , n5205 , n5206 , n5207 , n5208 , n5209 , n5210 ,
n5211 , n5212 , n5213 , n5214 , n5215 , n5216 , n5217 , n5218 , n5219 , n5220 ,
n5221 , n5222 , n5223 , n5224 , n5225 , n5226 , n5227 , n5228 , n5229 , n5230 ,
n5231 , n5232 , n5233 , n5234 , n5235 , n5236 , n5237 , n5238 , n5239 , n5240 ,
n5241 , n5242 , n5243 , n5244 , n5245 , n5246 , n5247 , n5248 , n5249 , n5250 ,
n5251 , n5252 , n5253 , n5254 , n5255 , n5256 , n5257 , n5258 , n5259 , n5260 ,
n5261 , n5262 , n5263 , n5264 , n5265 , n5266 , n5267 , n5268 , n5269 , n5270 ,
n5271 , n5272 , n5273 , n5274 , n5275 , n5276 , n5277 , n5278 , n5279 , n5280 ,
n5281 , n5282 , n5283 , n5284 , n5285 , n5286 , n5287 , n5288 , n5289 , n5290 ,
n5291 , n5292 , n5293 , n5294 , n5295 , n5296 , n5297 , n5298 , n5299 , n5300 ,
n5301 , n5302 , n5303 , n5304 , n5305 , n5306 , n5307 , n5308 , n5309 , n5310 ,
n5311 , n5312 , n5313 , n5314 , n5315 , n5316 , n5317 , n5318 , n5319 , n5320 ,
n5321 , n5322 , n5323 , n5324 , n5325 , n5326 , n5327 , n5328 , n5329 , n5330 ,
n5331 , n5332 , n5333 , n5334 , n5335 , n5336 , n5337 , n5338 , n5339 , n5340 ,
n5341 , n5342 , n5343 , n5344 , n5345 , n5346 , n5347 , n5348 , n5349 , n5350 ,
n5351 , n5352 , n5353 , n5354 , n5355 , n5356 , n5357 , n5358 , n5359 , n5360 ,
n5361 , n5362 , n5363 , n5364 , n5365 , n5366 , n5367 , n5368 , n5369 , n5370 ,
n5371 , n5372 , n5373 , n5374 , n5375 , n5376 , n5377 , n5378 , n5379 , n5380 ,
n5381 , n5382 , n5383 , n5384 , n5385 , n5386 , n5387 , n5388 , n5389 , n5390 ,
n5391 , n5392 , n5393 , n5394 , n5395 , n5396 , n5397 , n5398 , n5399 , n5400 ,
n5401 , n5402 , n5403 , n5404 , n5405 , n5406 , n5407 , n5408 , n5409 , n5410 ,
n5411 , n5412 , n5413 , n5414 , n5415 , n5416 , n5417 , n5418 , n5419 , n5420 ,
n5421 , n5422 , n5423 , n5424 , n5425 , n5426 , n5427 , n5428 , n5429 , n5430 ,
n5431 , n5432 , n5433 , n5434 , n5435 , n5436 , n5437 , n5438 , n5439 , n5440 ,
n5441 , n5442 , n5443 , n5444 , n5445 , n5446 , n5447 , n5448 , n5449 , n5450 ,
n5451 , n5452 , n5453 , n5454 , n5455 , n5456 , n5457 , n5458 , n5459 , n5460 ,
n5461 , n5462 , n5463 , n5464 , n5465 , n5466 , n5467 , n5468 , n5469 , n5470 ,
n5471 , n5472 , n5473 , n5474 , n5475 , n5476 , n5477 , n5478 , n5479 , n5480 ,
n5481 , n5482 , n5483 , n5484 , n5485 , n5486 , n5487 , n5488 , n5489 , n5490 ,
n5491 , n5492 , n5493 , n5494 , n5495 , n5496 , n5497 , n5498 , n5499 , n5500 ,
n5501 , n5502 , n5503 , n5504 , n5505 , n5506 , n5507 , n5508 , n5509 , n5510 ,
n5511 , n5512 , n5513 , n5514 , n5515 , n5516 , n5517 , n5518 , n5519 , n5520 ,
n5521 , n5522 , n5523 , n5524 , n5525 , n5526 , n5527 , n5528 , n5529 , n5530 ,
n5531 , n5532 , n5533 , n5534 , n5535 , n5536 , n5537 , n5538 , n5539 , n5540 ,
n5541 , n5542 , n5543 , n5544 , n5545 , n5546 , n5547 , n5548 , n5549 , n5550 ,
n5551 , n5552 , n5553 , n5554 , n5555 , n5556 , n5557 , n5558 , n5559 , n5560 ,
n5561 , n5562 , n5563 , n5564 , n5565 , n5566 , n5567 , n5568 , n5569 , n5570 ,
n5571 , n5572 , n5573 , n5574 , n5575 , n5576 , n5577 , n5578 , n5579 , n5580 ,
n5581 , n5582 , n5583 , n5584 , n5585 , n5586 , n5587 , n5588 , n5589 , n5590 ,
n5591 , n5592 , n5593 , n5594 , n5595 , n5596 , n5597 , n5598 , n5599 , n5600 ,
n5601 , n5602 , n5603 , n5604 , n5605 , n5606 , n5607 , n5608 , n5609 , n5610 ,
n5611 , n5612 , n5613 , n5614 , n5615 , n5616 , n5617 , n5618 , n5619 , n5620 ,
n5621 , n5622 , n5623 , n5624 , n5625 , n5626 , n5627 , n5628 , n5629 , n5630 ,
n5631 , n5632 , n5633 , n5634 , n5635 , n5636 , n5637 , n5638 , n5639 , n5640 ,
n5641 , n5642 , n5643 , n5644 , n5645 , n5646 , n5647 , n5648 , n5649 , n5650 ,
n5651 , n5652 , n5653 , n5654 , n5655 , n5656 , n5657 , n5658 , n5659 , n5660 ,
n5661 , n5662 , n5663 , n5664 , n5665 , n5666 , n5667 , n5668 , n5669 , n5670 ,
n5671 , n5672 , n5673 , n5674 , n5675 , n5676 , n5677 , n5678 , n5679 , n5680 ,
n5681 , n5682 , n5683 , n5684 , n5685 , n5686 , n5687 , n5688 , n5689 , n5690 ,
n5691 , n5692 , n5693 , n5694 , n5695 , n5696 , n5697 , n5698 , n5699 , n5700 ,
n5701 , n5702 , n5703 , n5704 , n5705 , n5706 , n5707 , n5708 , n5709 , n5710 ,
n5711 , n5712 , n5713 , n5714 , n5715 , n5716 , n5717 , n5718 , n5719 , n5720 ,
n5721 , n5722 , n5723 , n5724 , n5725 , n5726 , n5727 , n5728 , n5729 , n5730 ,
n5731 , n5732 , n5733 , n5734 , n5735 , n5736 , n5737 , n5738 , n5739 , n5740 ,
n5741 , n5742 , n5743 , n5744 , n5745 , n5746 , n5747 , n5748 , n5749 , n5750 ,
n5751 , n5752 , n5753 , n5754 , n5755 , n5756 , n5757 , n5758 , n5759 , n5760 ,
n5761 , n5762 , n5763 , n5764 , n5765 , n5766 , n5767 , n5768 , n5769 , n5770 ,
n5771 , n5772 , n5773 , n5774 , n5775 , n5776 , n5777 , n5778 , n5779 , n5780 ,
n5781 , n5782 , n5783 , n5784 , n5785 , n5786 , n5787 , n5788 , n5789 , n5790 ,
n5791 , n5792 , n5793 , n5794 , n5795 , n5796 , n5797 , n5798 , n5799 , n5800 ,
n5801 , n5802 , n5803 , n5804 , n5805 , n5806 , n5807 , n5808 , n5809 , n5810 ,
n5811 , n5812 , n5813 , n5814 , n5815 , n5816 , n5817 , n5818 , n5819 , n5820 ,
n5821 , n5822 , n5823 , n5824 , n5825 , n5826 , n5827 , n5828 , n5829 , n5830 ,
n5831 , n5832 , n5833 , n5834 , n5835 , n5836 , n5837 , n5838 , n5839 , n5840 ,
n5841 , n5842 , n5843 , n5844 , n5845 , n5846 , n5847 , n5848 , n5849 , n5850 ,
n5851 , n5852 , n5853 , n5854 , n5855 , n5856 , n5857 , n5858 , n5859 , n5860 ,
n5861 , n5862 , n5863 , n5864 , n5865 , n5866 , n5867 , n5868 , n5869 , n5870 ,
n5871 , n5872 , n5873 , n5874 , n5875 , n5876 , n5877 , n5878 , n5879 , n5880 ,
n5881 , n5882 , n5883 , n5884 , n5885 , n5886 , n5887 , n5888 , n5889 , n5890 ,
n5891 , n5892 , n5893 , n5894 , n5895 , n5896 , n5897 , n5898 , n5899 , n5900 ,
n5901 , n5902 , n5903 , n5904 , n5905 , n5906 , n5907 , n5908 , n5909 , n5910 ,
n5911 , n5912 , n5913 , n5914 , n5915 , n5916 , n5917 , n5918 , n5919 , n5920 ,
n5921 , n5922 , n5923 , n5924 , n5925 , n5926 , n5927 , n5928 , n5929 , n5930 ,
n5931 , n5932 , n5933 , n5934 , n5935 , n5936 , n5937 , n5938 , n5939 , n5940 ,
n5941 , n5942 , n5943 , n5944 , n5945 , n5946 , n5947 , n5948 , n5949 , n5950 ,
n5951 , n5952 , n5953 , n5954 , n5955 , n5956 , n5957 , n5958 , n5959 , n5960 ,
n5961 , n5962 , n5963 , n5964 , n5965 , n5966 , n5967 , n5968 , n5969 , n5970 ,
n5971 , n5972 , n5973 , n5974 , n5975 , n5976 , n5977 , n5978 , n5979 , n5980 ,
n5981 , n5982 , n5983 , n5984 , n5985 , n5986 , n5987 , n5988 , n5989 , n5990 ,
n5991 , n5992 , n5993 , n5994 , n5995 , n5996 , n5997 , n5998 , n5999 , n6000 ,
n6001 , n6002 , n6003 , n6004 , n6005 , n6006 , n6007 , n6008 , n6009 , n6010 ,
n6011 , n6012 , n6013 , n6014 , n6015 , n6016 , n6017 , n6018 , n6019 , n6020 ,
n6021 , n6022 , n6023 , n6024 , n6025 , n6026 , n6027 , n6028 , n6029 , n6030 ,
n6031 , n6032 , n6033 , n6034 , n6035 , n6036 , n6037 , n6038 , n6039 , n6040 ,
n6041 , n6042 , n6043 , n6044 , n6045 , n6046 , n6047 , n6048 , n6049 , n6050 ,
n6051 , n6052 , n6053 , n6054 , n6055 , n6056 , n6057 , n6058 , n6059 , n6060 ,
n6061 , n6062 , n6063 , n6064 , n6065 , n6066 , n6067 , n6068 , n6069 , n6070 ,
n6071 , n6072 , n6073 , n6074 , n6075 , n6076 , n6077 , n6078 , n6079 , n6080 ,
n6081 , n6082 , n6083 , n6084 , n6085 , n6086 , n6087 , n6088 , n6089 , n6090 ,
n6091 , n6092 , n6093 , n6094 , n6095 , n6096 , n6097 , n6098 , n6099 , n6100 ,
n6101 , n6102 , n6103 , n6104 , n6105 , n6106 , n6107 , n6108 , n6109 , n6110 ,
n6111 , n6112 , n6113 , n6114 , n6115 , n6116 , n6117 , n6118 , n6119 , n6120 ,
n6121 , n6122 , n6123 , n6124 , n6125 , n6126 , n6127 , n6128 , n6129 , n6130 ,
n6131 , n6132 , n6133 , n6134 , n6135 , n6136 , n6137 , n6138 , n6139 , n6140 ,
n6141 , n6142 , n6143 , n6144 , n6145 , n6146 , n6147 , n6148 , n6149 , n6150 ,
n6151 , n6152 , n6153 , n6154 , n6155 , n6156 , n6157 , n6158 , n6159 , n6160 ,
n6161 , n6162 , n6163 , n6164 , n6165 , n6166 , n6167 , n6168 , n6169 , n6170 ,
n6171 , n6172 , n6173 , n6174 , n6175 , n6176 , n6177 , n6178 , n6179 , n6180 ,
n6181 , n6182 , n6183 , n6184 , n6185 , n6186 , n6187 , n6188 , n6189 , n6190 ,
n6191 , n6192 , n6193 , n6194 , n6195 , n6196 , n6197 , n6198 , n6199 , n6200 ,
n6201 , n6202 , n6203 , n6204 , n6205 , n6206 , n6207 , n6208 , n6209 , n6210 ,
n6211 , n6212 , n6213 , n6214 , n6215 , n6216 , n6217 , n6218 , n6219 , n6220 ,
n6221 , n6222 , n6223 , n6224 , n6225 , n6226 , n6227 , n6228 , n6229 , n6230 ,
n6231 , n6232 , n6233 , n6234 , n6235 , n6236 , n6237 , n6238 , n6239 , n6240 ,
n6241 , n6242 , n6243 , n6244 , n6245 , n6246 , n6247 , n6248 , n6249 , n6250 ,
n6251 , n6252 , n6253 , n6254 , n6255 , n6256 , n6257 , n6258 , n6259 , n6260 ,
n6261 , n6262 , n6263 , n6264 , n6265 , n6266 , n6267 , n6268 , n6269 , n6270 ,
n6271 , n6272 , n6273 , n6274 , n6275 , n6276 , n6277 , n6278 , n6279 , n6280 ,
n6281 , n6282 , n6283 , n6284 , n6285 , n6286 , n6287 , n6288 , n6289 , n6290 ,
n6291 , n6292 , n6293 , n6294 , n6295 , n6296 , n6297 , n6298 , n6299 , n6300 ,
n6301 , n6302 , n6303 , n6304 , n6305 , n6306 , n6307 , n6308 , n6309 , n6310 ,
n6311 , n6312 , n6313 , n6314 , n6315 , n6316 , n6317 , n6318 , n6319 , n6320 ,
n6321 , n6322 , n6323 , n6324 , n6325 , n6326 , n6327 , n6328 , n6329 , n6330 ,
n6331 , n6332 , n6333 , n6334 , n6335 , n6336 , n6337 , n6338 , n6339 , n6340 ,
n6341 , n6342 , n6343 , n6344 , n6345 , n6346 , n6347 , n6348 , n6349 , n6350 ,
n6351 , n6352 , n6353 , n6354 , n6355 , n6356 , n6357 , n6358 , n6359 , n6360 ,
n6361 , n6362 , n6363 , n6364 , n6365 , n6366 , n6367 , n6368 , n6369 , n6370 ,
n6371 , n6372 , n6373 , n6374 , n6375 , n6376 , n6377 , n6378 , n6379 , n6380 ,
n6381 , n6382 , n6383 , n6384 , n6385 , n6386 , n6387 , n6388 , n6389 , n6390 ,
n6391 , n6392 , n6393 , n6394 , n6395 , n6396 , n6397 , n6398 , n6399 , n6400 ,
n6401 , n6402 , n6403 , n6404 , n6405 , n6406 , n6407 , n6408 , n6409 , n6410 ,
n6411 , n6412 , n6413 , n6414 , n6415 , n6416 , n6417 , n6418 , n6419 , n6420 ,
n6421 , n6422 , n6423 , n6424 , n6425 , n6426 , n6427 , n6428 , n6429 , n6430 ,
n6431 , n6432 , n6433 , n6434 , n6435 , n6436 , n6437 , n6438 , n6439 , n6440 ,
n6441 , n6442 , n6443 , n6444 , n6445 , n6446 , n6447 , n6448 , n6449 , n6450 ,
n6451 , n6452 , n6453 , n6454 , n6455 , n6456 , n6457 , n6458 , n6459 , n6460 ,
n6461 , n6462 , n6463 , n6464 , n6465 , n6466 , n6467 , n6468 , n6469 , n6470 ,
n6471 , n6472 , n6473 , n6474 , n6475 , n6476 , n6477 , n6478 , n6479 , n6480 ,
n6481 , n6482 , n6483 , n6484 , n6485 , n6486 , n6487 , n6488 , n6489 , n6490 ,
n6491 , n6492 , n6493 , n6494 , n6495 , n6496 , n6497 , n6498 , n6499 , n6500 ,
n6501 , n6502 , n6503 , n6504 , n6505 , n6506 , n6507 , n6508 , n6509 , n6510 ,
n6511 , n6512 , n6513 , n6514 , n6515 , n6516 , n6517 , n6518 , n6519 , n6520 ,
n6521 , n6522 , n6523 , n6524 , n6525 , n6526 , n6527 , n6528 , n6529 , n6530 ,
n6531 , n6532 , n6533 , n6534 , n6535 , n6536 , n6537 , n6538 , n6539 , n6540 ,
n6541 , n6542 , n6543 , n6544 , n6545 , n6546 , n6547 , n6548 , n6549 , n6550 ,
n6551 , n6552 , n6553 , n6554 , n6555 , n6556 , n6557 , n6558 , n6559 , n6560 ,
n6561 , n6562 , n6563 , n6564 , n6565 , n6566 , n6567 , n6568 , n6569 , n6570 ,
n6571 , n6572 , n6573 , n6574 , n6575 , n6576 , n6577 , n6578 , n6579 , n6580 ,
n6581 , n6582 , n6583 , n6584 , n6585 , n6586 , n6587 , n6588 , n6589 , n6590 ,
n6591 , n6592 , n6593 , n6594 , n6595 , n6596 , n6597 , n6598 , n6599 , n6600 ,
n6601 , n6602 , n6603 , n6604 , n6605 , n6606 , n6607 , n6608 , n6609 , n6610 ,
n6611 , n6612 , n6613 , n6614 , n6615 , n6616 , n6617 , n6618 , n6619 , n6620 ,
n6621 , n6622 , n6623 , n6624 , n6625 , n6626 , n6627 , n6628 , n6629 , n6630 ,
n6631 , n6632 , n6633 , n6634 , n6635 , n6636 , n6637 , n6638 , n6639 , n6640 ,
n6641 , n6642 , n6643 , n6644 , n6645 , n6646 , n6647 , n6648 , n6649 , n6650 ,
n6651 , n6652 , n6653 , n6654 , n6655 , n6656 , n6657 , n6658 , n6659 , n6660 ,
n6661 , n6662 , n6663 , n6664 , n6665 , n6666 , n6667 , n6668 , n6669 , n6670 ,
n6671 , n6672 , n6673 , n6674 , n6675 , n6676 , n6677 , n6678 , n6679 , n6680 ,
n6681 , n6682 , n6683 , n6684 , n6685 , n6686 , n6687 , n6688 , n6689 , n6690 ,
n6691 , n6692 , n6693 , n6694 , n6695 , n6696 , n6697 , n6698 , n6699 , n6700 ,
n6701 , n6702 , n6703 , n6704 , n6705 , n6706 , n6707 , n6708 , n6709 , n6710 ,
n6711 , n6712 , n6713 , n6714 , n6715 , n6716 , n6717 , n6718 , n6719 , n6720 ,
n6721 , n6722 , n6723 , n6724 , n6725 , n6726 , n6727 , n6728 , n6729 , n6730 ,
n6731 , n6732 , n6733 , n6734 , n6735 , n6736 , n6737 , n6738 , n6739 , n6740 ,
n6741 , n6742 , n6743 , n6744 , n6745 , n6746 , n6747 , n6748 , n6749 , n6750 ,
n6751 , n6752 , n6753 , n6754 , n6755 , n6756 , n6757 , n6758 , n6759 , n6760 ,
n6761 , n6762 , n6763 , n6764 , n6765 , n6766 , n6767 , n6768 , n6769 , n6770 ,
n6771 , n6772 , n6773 , n6774 , n6775 , n6776 , n6777 , n6778 , n6779 , n6780 ,
n6781 , n6782 , n6783 , n6784 , n6785 , n6786 , n6787 , n6788 , n6789 , n6790 ,
n6791 , n6792 , n6793 , n6794 , n6795 , n6796 , n6797 , n6798 , n6799 , n6800 ,
n6801 , n6802 , n6803 , n6804 , n6805 , n6806 , n6807 , n6808 , n6809 , n6810 ,
n6811 , n6812 , n6813 , n6814 , n6815 , n6816 , n6817 , n6818 , n6819 , n6820 ,
n6821 , n6822 , n6823 , n6824 , n6825 , n6826 , n6827 , n6828 , n6829 , n6830 ,
n6831 , n6832 , n6833 , n6834 , n6835 , n6836 , n6837 , n6838 , n6839 , n6840 ,
n6841 , n6842 , n6843 , n6844 , n6845 , n6846 , n6847 , n6848 , n6849 , n6850 ,
n6851 , n6852 , n6853 , n6854 , n6855 , n6856 , n6857 , n6858 , n6859 , n6860 ,
n6861 , n6862 , n6863 , n6864 , n6865 , n6866 , n6867 , n6868 , n6869 , n6870 ,
n6871 , n6872 , n6873 , n6874 , n6875 , n6876 , n6877 , n6878 , n6879 , n6880 ,
n6881 , n6882 , n6883 , n6884 , n6885 , n6886 , n6887 , n6888 , n6889 , n6890 ,
n6891 , n6892 , n6893 , n6894 , n6895 , n6896 , n6897 , n6898 , n6899 , n6900 ,
n6901 , n6902 , n6903 , n6904 , n6905 , n6906 , n6907 , n6908 , n6909 , n6910 ,
n6911 , n6912 , n6913 , n6914 , n6915 , n6916 , n6917 , n6918 , n6919 , n6920 ,
n6921 , n6922 , n6923 , n6924 , n6925 , n6926 , n6927 , n6928 , n6929 , n6930 ,
n6931 , n6932 , n6933 , n6934 , n6935 , n6936 , n6937 , n6938 , n6939 , n6940 ,
n6941 , n6942 , n6943 , n6944 , n6945 , n6946 , n6947 , n6948 , n6949 , n6950 ,
n6951 , n6952 , n6953 , n6954 , n6955 , n6956 , n6957 , n6958 , n6959 , n6960 ,
n6961 , n6962 , n6963 , n6964 , n6965 , n6966 , n6967 , n6968 , n6969 , n6970 ,
n6971 , n6972 , n6973 , n6974 , n6975 , n6976 , n6977 , n6978 , n6979 , n6980 ,
n6981 , n6982 , n6983 , n6984 , n6985 , n6986 , n6987 , n6988 , n6989 , n6990 ,
n6991 , n6992 , n6993 , n6994 , n6995 , n6996 , n6997 , n6998 , n6999 , n7000 ,
n7001 , n7002 , n7003 , n7004 , n7005 , n7006 , n7007 , n7008 , n7009 , n7010 ,
n7011 , n7012 , n7013 , n7014 , n7015 , n7016 , n7017 , n7018 , n7019 , n7020 ,
n7021 , n7022 , n7023 , n7024 , n7025 , n7026 , n7027 , n7028 , n7029 , n7030 ,
n7031 , n7032 , n7033 , n7034 , n7035 , n7036 , n7037 , n7038 , n7039 , n7040 ,
n7041 , n7042 , n7043 , n7044 , n7045 , n7046 , n7047 , n7048 , n7049 , n7050 ,
n7051 , n7052 , n7053 , n7054 , n7055 , n7056 , n7057 , n7058 , n7059 , n7060 ,
n7061 , n7062 , n7063 , n7064 , n7065 , n7066 , n7067 , n7068 , n7069 , n7070 ,
n7071 , n7072 , n7073 , n7074 , n7075 , n7076 , n7077 , n7078 , n7079 , n7080 ,
n7081 , n7082 , n7083 , n7084 , n7085 , n7086 , n7087 , n7088 , n7089 , n7090 ,
n7091 , n7092 , n7093 , n7094 , n7095 , n7096 , n7097 , n7098 , n7099 , n7100 ,
n7101 , n7102 , n7103 , n7104 , n7105 , n7106 , n7107 , n7108 , n7109 , n7110 ,
n7111 , n7112 , n7113 , n7114 , n7115 , n7116 , n7117 , n7118 , n7119 , n7120 ,
n7121 , n7122 , n7123 , n7124 , n7125 , n7126 , n7127 , n7128 , n7129 , n7130 ,
n7131 , n7132 , n7133 , n7134 , n7135 , n7136 , n7137 , n7138 , n7139 , n7140 ,
n7141 , n7142 , n7143 , n7144 , n7145 , n7146 , n7147 , n7148 , n7149 , n7150 ,
n7151 , n7152 , n7153 , n7154 , n7155 , n7156 , n7157 , n7158 , n7159 , n7160 ,
n7161 , n7162 , n7163 , n7164 , n7165 , n7166 , n7167 , n7168 , n7169 , n7170 ,
n7171 , n7172 , n7173 , n7174 , n7175 , n7176 , n7177 , n7178 , n7179 , n7180 ,
n7181 , n7182 , n7183 , n7184 , n7185 , n7186 , n7187 , n7188 , n7189 , n7190 ,
n7191 , n7192 , n7193 , n7194 , n7195 , n7196 , n7197 , n7198 , n7199 , n7200 ,
n7201 , n7202 , n7203 , n7204 , n7205 , n7206 , n7207 , n7208 , n7209 , n7210 ,
n7211 , n7212 , n7213 , n7214 , n7215 , n7216 , n7217 , n7218 , n7219 , n7220 ,
n7221 , n7222 , n7223 , n7224 , n7225 , n7226 , n7227 , n7228 , n7229 , n7230 ,
n7231 , n7232 , n7233 , n7234 , n7235 , n7236 , n7237 , n7238 , n7239 , n7240 ,
n7241 , n7242 , n7243 , n7244 , n7245 , n7246 , n7247 , n7248 , n7249 , n7250 ,
n7251 , n7252 , n7253 , n7254 , n7255 , n7256 , n7257 , n7258 , n7259 , n7260 ,
n7261 , n7262 , n7263 , n7264 , n7265 , n7266 , n7267 , n7268 , n7269 , n7270 ,
n7271 , n7272 , n7273 , n7274 , n7275 , n7276 , n7277 , n7278 , n7279 , n7280 ,
n7281 , n7282 , n7283 , n7284 , n7285 , n7286 , n7287 , n7288 , n7289 , n7290 ,
n7291 , n7292 , n7293 , n7294 , n7295 , n7296 , n7297 , n7298 , n7299 , n7300 ,
n7301 , n7302 , n7303 , n7304 , n7305 , n7306 , n7307 , n7308 , n7309 , n7310 ,
n7311 , n7312 , n7313 , n7314 , n7315 , n7316 , n7317 , n7318 , n7319 , n7320 ,
n7321 , n7322 , n7323 , n7324 , n7325 , n7326 , n7327 , n7328 , n7329 , n7330 ,
n7331 , n7332 , n7333 , n7334 , n7335 , n7336 , n7337 , n7338 , n7339 , n7340 ,
n7341 , n7342 , n7343 , n7344 , n7345 , n7346 , n7347 , n7348 , n7349 , n7350 ,
n7351 , n7352 , n7353 , n7354 , n7355 , n7356 , n7357 , n7358 , n7359 , n7360 ,
n7361 , n7362 , n7363 , n7364 , n7365 , n7366 , n7367 , n7368 , n7369 , n7370 ,
n7371 , n7372 , n7373 , n7374 , n7375 , n7376 , n7377 , n7378 , n7379 , n7380 ,
n7381 , n7382 , n7383 , n7384 , n7385 , n7386 , n7387 , n7388 , n7389 , n7390 ,
n7391 , n7392 , n7393 , n7394 , n7395 , n7396 , n7397 , n7398 , n7399 , n7400 ,
n7401 , n7402 , n7403 , n7404 , n7405 , n7406 , n7407 , n7408 , n7409 , n7410 ,
n7411 , n7412 , n7413 , n7414 , n7415 , n7416 , n7417 , n7418 , n7419 , n7420 ,
n7421 , n7422 , n7423 , n7424 , n7425 , n7426 , n7427 , n7428 , n7429 , n7430 ,
n7431 , n7432 , n7433 , n7434 , n7435 , n7436 , n7437 , n7438 , n7439 , n7440 ,
n7441 , n7442 , n7443 , n7444 , n7445 , n7446 , n7447 , n7448 , n7449 , n7450 ,
n7451 , n7452 , n7453 , n7454 , n7455 , n7456 , n7457 , n7458 , n7459 , n7460 ,
n7461 , n7462 , n7463 , n7464 , n7465 , n7466 , n7467 , n7468 , n7469 , n7470 ,
n7471 , n7472 , n7473 , n7474 , n7475 , n7476 , n7477 , n7478 , n7479 , n7480 ,
n7481 , n7482 , n7483 , n7484 , n7485 , n7486 , n7487 , n7488 , n7489 , n7490 ,
n7491 , n7492 , n7493 , n7494 , n7495 , n7496 , n7497 , n7498 , n7499 , n7500 ,
n7501 , n7502 , n7503 , n7504 , n7505 , n7506 , n7507 , n7508 , n7509 , n7510 ,
n7511 , n7512 , n7513 , n7514 , n7515 , n7516 , n7517 , n7518 , n7519 , n7520 ,
n7521 , n7522 , n7523 , n7524 , n7525 , n7526 , n7527 , n7528 , n7529 , n7530 ,
n7531 , n7532 , n7533 , n7534 , n7535 , n7536 , n7537 , n7538 , n7539 , n7540 ,
n7541 , n7542 , n7543 , n7544 , n7545 , n7546 , n7547 , n7548 , n7549 , n7550 ,
n7551 , n7552 , n7553 , n7554 , n7555 , n7556 , n7557 , n7558 , n7559 , n7560 ,
n7561 , n7562 , n7563 , n7564 , n7565 , n7566 , n7567 , n7568 , n7569 , n7570 ,
n7571 , n7572 , n7573 , n7574 , n7575 , n7576 , n7577 , n7578 , n7579 , n7580 ,
n7581 , n7582 , n7583 , n7584 , n7585 , n7586 , n7587 , n7588 , n7589 , n7590 ,
n7591 , n7592 , n7593 , n7594 , n7595 , n7596 , n7597 , n7598 , n7599 , n7600 ,
n7601 , n7602 , n7603 , n7604 , n7605 , n7606 , n7607 , n7608 , n7609 , n7610 ,
n7611 , n7612 , n7613 , n7614 , n7615 , n7616 , n7617 , n7618 , n7619 , n7620 ,
n7621 , n7622 , n7623 , n7624 , n7625 , n7626 , n7627 , n7628 , n7629 , n7630 ,
n7631 , n7632 , n7633 , n7634 , n7635 , n7636 , n7637 , n7638 , n7639 , n7640 ,
n7641 , n7642 , n7643 , n7644 , n7645 , n7646 , n7647 , n7648 , n7649 , n7650 ,
n7651 , n7652 , n7653 , n7654 , n7655 , n7656 , n7657 , n7658 , n7659 , n7660 ,
n7661 , n7662 , n7663 , n7664 , n7665 , n7666 , n7667 , n7668 , n7669 , n7670 ,
n7671 , n7672 , n7673 , n7674 , n7675 , n7676 , n7677 , n7678 , n7679 , n7680 ,
n7681 , n7682 , n7683 , n7684 , n7685 , n7686 , n7687 , n7688 , n7689 , n7690 ,
n7691 , n7692 , n7693 , n7694 , n7695 , n7696 , n7697 , n7698 , n7699 , n7700 ,
n7701 , n7702 , n7703 , n7704 , n7705 , n7706 , n7707 , n7708 , n7709 , n7710 ,
n7711 , n7712 , n7713 , n7714 , n7715 , n7716 , n7717 , n7718 , n7719 , n7720 ,
n7721 , n7722 , n7723 , n7724 , n7725 , n7726 , n7727 , n7728 , n7729 , n7730 ,
n7731 , n7732 , n7733 , n7734 , n7735 , n7736 , n7737 , n7738 , n7739 , n7740 ,
n7741 , n7742 , n7743 , n7744 , n7745 , n7746 , n7747 , n7748 , n7749 , n7750 ,
n7751 , n7752 , n7753 , n7754 , n7755 , n7756 , n7757 , n7758 , n7759 , n7760 ,
n7761 , n7762 , n7763 , n7764 , n7765 , n7766 , n7767 , n7768 , n7769 , n7770 ,
n7771 , n7772 , n7773 , n7774 , n7775 , n7776 , n7777 , n7778 , n7779 , n7780 ,
n7781 , n7782 , n7783 , n7784 , n7785 , n7786 , n7787 , n7788 , n7789 , n7790 ,
n7791 , n7792 , n7793 , n7794 , n7795 , n7796 , n7797 , n7798 , n7799 , n7800 ,
n7801 , n7802 , n7803 , n7804 , n7805 , n7806 , n7807 , n7808 , n7809 , n7810 ,
n7811 , n7812 , n7813 , n7814 , n7815 , n7816 , n7817 , n7818 , n7819 , n7820 ,
n7821 , n7822 , n7823 , n7824 , n7825 , n7826 , n7827 , n7828 , n7829 , n7830 ,
n7831 , n7832 , n7833 , n7834 , n7835 , n7836 , n7837 , n7838 , n7839 , n7840 ,
n7841 , n7842 , n7843 , n7844 , n7845 , n7846 , n7847 , n7848 , n7849 , n7850 ,
n7851 , n7852 , n7853 , n7854 , n7855 , n7856 , n7857 , n7858 , n7859 , n7860 ,
n7861 , n7862 , n7863 , n7864 , n7865 , n7866 , n7867 , n7868 , n7869 , n7870 ,
n7871 , n7872 , n7873 , n7874 , n7875 , n7876 , n7877 , n7878 , n7879 , n7880 ,
n7881 , n7882 , n7883 , n7884 , n7885 , n7886 , n7887 , n7888 , n7889 , n7890 ,
n7891 , n7892 , n7893 , n7894 , n7895 , n7896 , n7897 , n7898 , n7899 , n7900 ,
n7901 , n7902 , n7903 , n7904 , n7905 , n7906 , n7907 , n7908 , n7909 , n7910 ,
n7911 , n7912 , n7913 , n7914 , n7915 , n7916 , n7917 , n7918 , n7919 , n7920 ,
n7921 , n7922 , n7923 , n7924 , n7925 , n7926 , n7927 , n7928 , n7929 , n7930 ,
n7931 , n7932 , n7933 , n7934 , n7935 , n7936 , n7937 , n7938 , n7939 , n7940 ,
n7941 , n7942 , n7943 , n7944 , n7945 , n7946 , n7947 , n7948 , n7949 , n7950 ,
n7951 , n7952 , n7953 , n7954 , n7955 , n7956 , n7957 , n7958 , n7959 , n7960 ,
n7961 , n7962 , n7963 , n7964 , n7965 , n7966 , n7967 , n7968 , n7969 , n7970 ,
n7971 , n7972 , n7973 , n7974 , n7975 , n7976 , n7977 , n7978 , n7979 , n7980 ,
n7981 , n7982 , n7983 , n7984 , n7985 , n7986 , n7987 , n7988 , n7989 , n7990 ,
n7991 , n7992 , n7993 , n7994 , n7995 , n7996 , n7997 , n7998 , n7999 , n8000 ,
n8001 , n8002 , n8003 , n8004 , n8005 , n8006 , n8007 , n8008 , n8009 , n8010 ,
n8011 , n8012 , n8013 , n8014 , n8015 , n8016 , n8017 , n8018 , n8019 , n8020 ,
n8021 , n8022 , n8023 , n8024 , n8025 , n8026 , n8027 , n8028 , n8029 , n8030 ,
n8031 , n8032 , n8033 , n8034 , n8035 , n8036 , n8037 , n8038 , n8039 , n8040 ,
n8041 , n8042 , n8043 , n8044 , n8045 , n8046 , n8047 , n8048 , n8049 , n8050 ,
n8051 , n8052 , n8053 , n8054 , n8055 , n8056 , n8057 , n8058 , n8059 , n8060 ,
n8061 , n8062 , n8063 , n8064 , n8065 , n8066 , n8067 , n8068 , n8069 , n8070 ,
n8071 , n8072 , n8073 , n8074 , n8075 , n8076 , n8077 , n8078 , n8079 , n8080 ,
n8081 , n8082 , n8083 , n8084 , n8085 , n8086 , n8087 , n8088 , n8089 , n8090 ,
n8091 , n8092 , n8093 , n8094 , n8095 , n8096 , n8097 , n8098 , n8099 , n8100 ,
n8101 , n8102 , n8103 , n8104 , n8105 , n8106 , n8107 , n8108 , n8109 , n8110 ,
n8111 , n8112 , n8113 , n8114 , n8115 , n8116 , n8117 , n8118 , n8119 , n8120 ,
n8121 , n8122 , n8123 , n8124 , n8125 , n8126 , n8127 , n8128 , n8129 , n8130 ,
n8131 , n8132 , n8133 , n8134 , n8135 , n8136 , n8137 , n8138 , n8139 , n8140 ,
n8141 , n8142 , n8143 , n8144 , n8145 , n8146 , n8147 , n8148 , n8149 , n8150 ,
n8151 , n8152 , n8153 , n8154 , n8155 , n8156 , n8157 , n8158 , n8159 , n8160 ,
n8161 , n8162 , n8163 , n8164 , n8165 , n8166 , n8167 , n8168 , n8169 , n8170 ,
n8171 , n8172 , n8173 , n8174 , n8175 , n8176 , n8177 , n8178 , n8179 , n8180 ,
n8181 , n8182 , n8183 , n8184 , n8185 , n8186 , n8187 , n8188 , n8189 , n8190 ,
n8191 , n8192 , n8193 , n8194 , n8195 , n8196 , n8197 , n8198 , n8199 , n8200 ,
n8201 , n8202 , n8203 , n8204 , n8205 , n8206 , n8207 , n8208 , n8209 , n8210 ,
n8211 , n8212 , n8213 , n8214 , n8215 , n8216 , n8217 , n8218 , n8219 , n8220 ,
n8221 , n8222 , n8223 , n8224 , n8225 , n8226 , n8227 , n8228 , n8229 , n8230 ,
n8231 , n8232 , n8233 , n8234 , n8235 , n8236 , n8237 , n8238 , n8239 , n8240 ,
n8241 , n8242 , n8243 , n8244 , n8245 , n8246 , n8247 , n8248 , n8249 , n8250 ,
n8251 , n8252 , n8253 , n8254 , n8255 , n8256 , n8257 , n8258 , n8259 , n8260 ,
n8261 , n8262 , n8263 , n8264 , n8265 , n8266 , n8267 , n8268 , n8269 , n8270 ,
n8271 , n8272 , n8273 , n8274 , n8275 , n8276 , n8277 , n8278 , n8279 , n8280 ,
n8281 , n8282 , n8283 , n8284 , n8285 , n8286 , n8287 , n8288 , n8289 , n8290 ,
n8291 , n8292 , n8293 , n8294 , n8295 , n8296 , n8297 , n8298 , n8299 , n8300 ,
n8301 , n8302 , n8303 , n8304 , n8305 , n8306 , n8307 , n8308 , n8309 , n8310 ,
n8311 , n8312 , n8313 , n8314 , n8315 , n8316 , n8317 , n8318 , n8319 , n8320 ,
n8321 , n8322 , n8323 , n8324 , n8325 , n8326 , n8327 , n8328 , n8329 , n8330 ,
n8331 , n8332 , n8333 , n8334 , n8335 , n8336 , n8337 , n8338 , n8339 , n8340 ,
n8341 , n8342 , n8343 , n8344 , n8345 , n8346 , n8347 , n8348 , n8349 , n8350 ,
n8351 , n8352 , n8353 , n8354 , n8355 , n8356 , n8357 , n8358 , n8359 , n8360 ,
n8361 , n8362 , n8363 , n8364 , n8365 , n8366 , n8367 , n8368 , n8369 , n8370 ,
n8371 , n8372 , n8373 , n8374 , n8375 , n8376 , n8377 , n8378 , n8379 , n8380 ,
n8381 , n8382 , n8383 , n8384 , n8385 , n8386 , n8387 , n8388 , n8389 , n8390 ,
n8391 , n8392 , n8393 , n8394 , n8395 , n8396 , n8397 , n8398 , n8399 , n8400 ,
n8401 , n8402 , n8403 , n8404 , n8405 , n8406 , n8407 , n8408 , n8409 , n8410 ,
n8411 , n8412 , n8413 , n8414 , n8415 , n8416 , n8417 , n8418 , n8419 , n8420 ,
n8421 , n8422 , n8423 , n8424 , n8425 , n8426 , n8427 , n8428 , n8429 , n8430 ,
n8431 , n8432 , n8433 , n8434 , n8435 , n8436 , n8437 , n8438 , n8439 , n8440 ,
n8441 , n8442 , n8443 , n8444 , n8445 , n8446 , n8447 , n8448 , n8449 , n8450 ,
n8451 , n8452 , n8453 , n8454 , n8455 , n8456 , n8457 , n8458 , n8459 , n8460 ,
n8461 , n8462 , n8463 , n8464 , n8465 , n8466 , n8467 , n8468 , n8469 , n8470 ,
n8471 , n8472 , n8473 , n8474 , n8475 , n8476 , n8477 , n8478 , n8479 , n8480 ,
n8481 , n8482 , n8483 , n8484 , n8485 , n8486 , n8487 , n8488 , n8489 , n8490 ,
n8491 , n8492 , n8493 , n8494 , n8495 , n8496 , n8497 , n8498 , n8499 , n8500 ,
n8501 , n8502 , n8503 , n8504 , n8505 , n8506 , n8507 , n8508 , n8509 , n8510 ,
n8511 , n8512 , n8513 , n8514 , n8515 , n8516 , n8517 , n8518 , n8519 , n8520 ,
n8521 , n8522 , n8523 , n8524 , n8525 , n8526 , n8527 , n8528 , n8529 , n8530 ,
n8531 , n8532 , n8533 , n8534 , n8535 , n8536 , n8537 , n8538 , n8539 , n8540 ,
n8541 , n8542 , n8543 , n8544 , n8545 , n8546 , n8547 , n8548 , n8549 , n8550 ,
n8551 , n8552 , n8553 , n8554 , n8555 , n8556 , n8557 , n8558 , n8559 , n8560 ,
n8561 , n8562 , n8563 , n8564 , n8565 , n8566 , n8567 , n8568 , n8569 , n8570 ,
n8571 , n8572 , n8573 , n8574 , n8575 , n8576 , n8577 , n8578 , n8579 , n8580 ,
n8581 , n8582 , n8583 , n8584 , n8585 , n8586 , n8587 , n8588 , n8589 , n8590 ,
n8591 , n8592 , n8593 , n8594 , n8595 , n8596 , n8597 , n8598 , n8599 , n8600 ,
n8601 , n8602 , n8603 , n8604 , n8605 , n8606 , n8607 , n8608 , n8609 , n8610 ,
n8611 , n8612 , n8613 , n8614 , n8615 , n8616 , n8617 , n8618 , n8619 , n8620 ,
n8621 , n8622 , n8623 , n8624 , n8625 , n8626 , n8627 , n8628 , n8629 , n8630 ,
n8631 , n8632 , n8633 , n8634 , n8635 , n8636 , n8637 , n8638 , n8639 , n8640 ,
n8641 , n8642 , n8643 , n8644 , n8645 , n8646 , n8647 , n8648 , n8649 , n8650 ,
n8651 , n8652 , n8653 , n8654 , n8655 , n8656 , n8657 , n8658 , n8659 , n8660 ,
n8661 , n8662 , n8663 , n8664 , n8665 , n8666 , n8667 , n8668 , n8669 , n8670 ,
n8671 , n8672 , n8673 , n8674 , n8675 , n8676 , n8677 , n8678 , n8679 , n8680 ,
n8681 , n8682 , n8683 , n8684 , n8685 , n8686 , n8687 , n8688 , n8689 , n8690 ,
n8691 , n8692 , n8693 , n8694 , n8695 , n8696 , n8697 , n8698 , n8699 , n8700 ,
n8701 , n8702 , n8703 , n8704 , n8705 , n8706 , n8707 , n8708 , n8709 , n8710 ,
n8711 , n8712 , n8713 , n8714 , n8715 , n8716 , n8717 , n8718 , n8719 , n8720 ,
n8721 , n8722 , n8723 , n8724 , n8725 , n8726 , n8727 , n8728 , n8729 , n8730 ,
n8731 , n8732 , n8733 , n8734 , n8735 , n8736 , n8737 , n8738 , n8739 , n8740 ,
n8741 , n8742 , n8743 , n8744 , n8745 , n8746 , n8747 , n8748 , n8749 , n8750 ,
n8751 , n8752 , n8753 , n8754 , n8755 , n8756 , n8757 , n8758 , n8759 , n8760 ,
n8761 , n8762 , n8763 , n8764 , n8765 , n8766 , n8767 , n8768 , n8769 , n8770 ,
n8771 , n8772 , n8773 , n8774 , n8775 , n8776 , n8777 , n8778 , n8779 , n8780 ,
n8781 , n8782 , n8783 , n8784 , n8785 , n8786 , n8787 , n8788 , n8789 , n8790 ,
n8791 , n8792 , n8793 , n8794 , n8795 , n8796 , n8797 , n8798 , n8799 , n8800 ,
n8801 , n8802 , n8803 , n8804 , n8805 , n8806 , n8807 , n8808 , n8809 , n8810 ,
n8811 , n8812 , n8813 , n8814 , n8815 , n8816 , n8817 , n8818 , n8819 , n8820 ,
n8821 , n8822 , n8823 , n8824 , n8825 , n8826 , n8827 , n8828 , n8829 , n8830 ,
n8831 , n8832 , n8833 , n8834 , n8835 , n8836 , n8837 ;
buf ( n88 , n8792 );
buf ( n91 , n8795 );
buf ( n94 , n8798 );
buf ( n95 , n8801 );
buf ( n80 , n8804 );
buf ( n85 , n8807 );
buf ( n86 , n8810 );
buf ( n89 , n8813 );
buf ( n81 , n8816 );
buf ( n83 , n8819 );
buf ( n93 , n8822 );
buf ( n87 , n8825 );
buf ( n90 , n8828 );
buf ( n82 , n8831 );
buf ( n84 , n8834 );
buf ( n92 , n8837 );
buf ( n195 , n21 );
buf ( n196 , n59 );
buf ( n197 , n25 );
buf ( n198 , n12 );
buf ( n199 , n47 );
buf ( n200 , n13 );
buf ( n201 , n36 );
buf ( n202 , n11 );
buf ( n203 , n2 );
buf ( n204 , n37 );
buf ( n205 , n1 );
buf ( n206 , n31 );
buf ( n207 , n8 );
buf ( n208 , n51 );
buf ( n209 , n15 );
buf ( n210 , n20 );
buf ( n211 , n42 );
buf ( n212 , n4 );
buf ( n213 , n50 );
buf ( n214 , n71 );
buf ( n215 , n5 );
buf ( n216 , n32 );
buf ( n217 , n38 );
buf ( n218 , n62 );
buf ( n219 , n57 );
buf ( n220 , n9 );
buf ( n221 , n23 );
buf ( n222 , n67 );
buf ( n223 , n3 );
buf ( n224 , n27 );
buf ( n225 , n41 );
buf ( n226 , n65 );
buf ( n227 , n54 );
buf ( n228 , n18 );
buf ( n229 , n7 );
buf ( n230 , n69 );
buf ( n231 , n6 );
buf ( n232 , n30 );
buf ( n233 , n61 );
buf ( n234 , n63 );
buf ( n235 , n60 );
buf ( n236 , n73 );
buf ( n237 , n49 );
buf ( n238 , n17 );
buf ( n239 , n66 );
buf ( n240 , n48 );
buf ( n241 , n72 );
buf ( n242 , n74 );
buf ( n243 , n46 );
buf ( n244 , n35 );
buf ( n245 , n43 );
buf ( n246 , n40 );
buf ( n247 , n53 );
buf ( n248 , n55 );
buf ( n249 , n79 );
buf ( n250 , n29 );
buf ( n251 , n70 );
buf ( n252 , n56 );
buf ( n253 , n33 );
buf ( n254 , n10 );
buf ( n255 , n19 );
buf ( n256 , n76 );
buf ( n257 , n68 );
buf ( n258 , n39 );
buf ( n259 , n75 );
buf ( n260 , n26 );
buf ( n261 , n0 );
buf ( n262 , n28 );
buf ( n263 , n78 );
buf ( n264 , n52 );
buf ( n265 , n34 );
buf ( n266 , n14 );
buf ( n267 , n44 );
buf ( n268 , n16 );
buf ( n269 , n22 );
buf ( n270 , n24 );
buf ( n271 , n58 );
buf ( n272 , n77 );
buf ( n273 , n225 );
buf ( n274 , n256 );
and ( n275 , n273 , n274 );
buf ( n276 , n275 );
buf ( n277 , n276 );
not ( n278 , n238 );
buf ( n279 , n278 );
and ( n280 , n277 , n279 );
buf ( n281 , n280 );
buf ( n282 , n281 );
not ( n283 , n282 );
buf ( n284 , n195 );
not ( n285 , n284 );
and ( n286 , n285 , n282 );
nor ( n287 , n283 , n286 );
buf ( n288 , n240 );
and ( n289 , n277 , n288 );
buf ( n290 , n289 );
buf ( n291 , n255 );
and ( n292 , n273 , n291 );
buf ( n293 , n292 );
buf ( n294 , n224 );
and ( n295 , n294 , n274 );
xor ( n296 , n293 , n295 );
buf ( n297 , n296 );
buf ( n298 , n297 );
and ( n299 , n298 , n279 );
xor ( n300 , n290 , n299 );
buf ( n301 , n300 );
buf ( n302 , n301 );
not ( n303 , n302 );
buf ( n304 , n196 );
not ( n305 , n304 );
nor ( n306 , n303 , n305 );
xor ( n307 , n287 , n306 );
buf ( n308 , n307 );
and ( n309 , n289 , n299 );
buf ( n310 , n309 );
buf ( n311 , n310 );
buf ( n312 , n239 );
and ( n313 , n277 , n312 );
and ( n314 , n298 , n288 );
xor ( n315 , n313 , n314 );
and ( n316 , n292 , n295 );
buf ( n317 , n316 );
buf ( n318 , n223 );
and ( n319 , n318 , n274 );
xor ( n320 , n317 , n319 );
buf ( n321 , n254 );
and ( n322 , n273 , n321 );
buf ( n323 , n322 );
and ( n324 , n294 , n291 );
xor ( n325 , n323 , n324 );
xor ( n326 , n320 , n325 );
buf ( n327 , n326 );
buf ( n328 , n327 );
and ( n329 , n328 , n279 );
xor ( n330 , n315 , n329 );
xor ( n331 , n311 , n330 );
buf ( n332 , n331 );
buf ( n333 , n332 );
not ( n334 , n333 );
buf ( n335 , n197 );
not ( n336 , n335 );
nor ( n337 , n334 , n336 );
xor ( n338 , n308 , n337 );
nor ( n339 , n283 , n305 );
buf ( n340 , n339 );
nor ( n341 , n303 , n336 );
and ( n342 , n340 , n341 );
buf ( n343 , n342 );
xor ( n344 , n338 , n343 );
and ( n345 , n313 , n314 );
and ( n346 , n314 , n329 );
and ( n347 , n313 , n329 );
or ( n348 , n345 , n346 , n347 );
and ( n349 , n298 , n312 );
and ( n350 , n328 , n288 );
xor ( n351 , n349 , n350 );
and ( n352 , n322 , n324 );
buf ( n353 , n352 );
buf ( n354 , n253 );
and ( n355 , n273 , n354 );
buf ( n356 , n355 );
and ( n357 , n294 , n321 );
xor ( n358 , n356 , n357 );
xor ( n359 , n353 , n358 );
and ( n360 , n318 , n291 );
buf ( n361 , n222 );
and ( n362 , n361 , n274 );
xor ( n363 , n360 , n362 );
xor ( n364 , n359 , n363 );
and ( n365 , n317 , n319 );
and ( n366 , n319 , n325 );
and ( n367 , n317 , n325 );
or ( n368 , n365 , n366 , n367 );
xor ( n369 , n364 , n368 );
buf ( n370 , n369 );
buf ( n371 , n370 );
and ( n372 , n371 , n279 );
xor ( n373 , n351 , n372 );
xor ( n374 , n348 , n373 );
buf ( n375 , n238 );
and ( n376 , n277 , n375 );
buf ( n377 , n376 );
xor ( n378 , n374 , n377 );
and ( n379 , n310 , n330 );
buf ( n380 , n379 );
xor ( n381 , n378 , n380 );
buf ( n382 , n381 );
buf ( n383 , n382 );
not ( n384 , n383 );
buf ( n385 , n198 );
not ( n386 , n385 );
nor ( n387 , n384 , n386 );
xor ( n388 , n344 , n387 );
xor ( n389 , n340 , n341 );
buf ( n390 , n389 );
nor ( n391 , n334 , n386 );
and ( n392 , n390 , n391 );
xor ( n393 , n390 , n391 );
nor ( n394 , n283 , n336 );
buf ( n395 , n394 );
nor ( n396 , n303 , n386 );
and ( n397 , n395 , n396 );
buf ( n398 , n397 );
and ( n399 , n393 , n398 );
or ( n400 , n392 , n399 );
xor ( n401 , n388 , n400 );
and ( n402 , n348 , n373 );
and ( n403 , n373 , n377 );
and ( n404 , n348 , n377 );
or ( n405 , n402 , n403 , n404 );
buf ( n406 , n405 );
and ( n407 , n349 , n350 );
and ( n408 , n350 , n372 );
and ( n409 , n349 , n372 );
or ( n410 , n407 , n408 , n409 );
buf ( n411 , n237 );
and ( n412 , n277 , n411 );
buf ( n413 , n412 );
and ( n414 , n298 , n375 );
xor ( n415 , n413 , n414 );
xor ( n416 , n410 , n415 );
and ( n417 , n328 , n312 );
and ( n418 , n371 , n288 );
xor ( n419 , n417 , n418 );
and ( n420 , n360 , n362 );
and ( n421 , n353 , n358 );
and ( n422 , n358 , n363 );
and ( n423 , n353 , n363 );
or ( n424 , n421 , n422 , n423 );
xor ( n425 , n420 , n424 );
and ( n426 , n355 , n357 );
buf ( n427 , n426 );
and ( n428 , n318 , n321 );
and ( n429 , n361 , n291 );
xor ( n430 , n428 , n429 );
buf ( n431 , n221 );
and ( n432 , n431 , n274 );
xor ( n433 , n430 , n432 );
xor ( n434 , n427 , n433 );
buf ( n435 , n252 );
and ( n436 , n273 , n435 );
buf ( n437 , n436 );
and ( n438 , n294 , n354 );
xor ( n439 , n437 , n438 );
xor ( n440 , n434 , n439 );
xor ( n441 , n425 , n440 );
and ( n442 , n364 , n368 );
buf ( n443 , n442 );
xor ( n444 , n441 , n443 );
buf ( n445 , n444 );
buf ( n446 , n445 );
and ( n447 , n446 , n279 );
xor ( n448 , n419 , n447 );
xor ( n449 , n416 , n448 );
xor ( n450 , n406 , n449 );
and ( n451 , n378 , n380 );
buf ( n452 , n451 );
xor ( n453 , n450 , n452 );
buf ( n454 , n453 );
buf ( n455 , n454 );
not ( n456 , n455 );
buf ( n457 , n199 );
not ( n458 , n457 );
nor ( n459 , n456 , n458 );
xor ( n460 , n401 , n459 );
xor ( n461 , n393 , n398 );
nor ( n462 , n384 , n458 );
and ( n463 , n461 , n462 );
xor ( n464 , n461 , n462 );
xor ( n465 , n395 , n396 );
buf ( n466 , n465 );
nor ( n467 , n334 , n458 );
and ( n468 , n466 , n467 );
xor ( n469 , n466 , n467 );
nor ( n470 , n283 , n386 );
buf ( n471 , n470 );
nor ( n472 , n303 , n458 );
and ( n473 , n471 , n472 );
buf ( n474 , n473 );
and ( n475 , n469 , n474 );
or ( n476 , n468 , n475 );
and ( n477 , n464 , n476 );
or ( n478 , n463 , n477 );
xor ( n479 , n460 , n478 );
and ( n480 , n410 , n415 );
and ( n481 , n415 , n448 );
and ( n482 , n410 , n448 );
or ( n483 , n480 , n481 , n482 );
and ( n484 , n417 , n418 );
and ( n485 , n418 , n447 );
and ( n486 , n417 , n447 );
or ( n487 , n484 , n485 , n486 );
buf ( n488 , n236 );
and ( n489 , n277 , n488 );
and ( n490 , n298 , n411 );
xor ( n491 , n489 , n490 );
and ( n492 , n328 , n375 );
xor ( n493 , n491 , n492 );
xor ( n494 , n487 , n493 );
and ( n495 , n371 , n312 );
and ( n496 , n446 , n288 );
xor ( n497 , n495 , n496 );
and ( n498 , n427 , n433 );
and ( n499 , n433 , n439 );
and ( n500 , n427 , n439 );
or ( n501 , n498 , n499 , n500 );
and ( n502 , n436 , n438 );
buf ( n503 , n502 );
and ( n504 , n318 , n354 );
and ( n505 , n361 , n321 );
xor ( n506 , n504 , n505 );
and ( n507 , n431 , n291 );
xor ( n508 , n506 , n507 );
xor ( n509 , n503 , n508 );
buf ( n510 , n251 );
and ( n511 , n273 , n510 );
buf ( n512 , n511 );
and ( n513 , n294 , n435 );
xor ( n514 , n512 , n513 );
xor ( n515 , n509 , n514 );
xor ( n516 , n501 , n515 );
and ( n517 , n428 , n429 );
and ( n518 , n429 , n432 );
and ( n519 , n428 , n432 );
or ( n520 , n517 , n518 , n519 );
buf ( n521 , n220 );
and ( n522 , n521 , n274 );
xor ( n523 , n520 , n522 );
xor ( n524 , n516 , n523 );
and ( n525 , n420 , n424 );
and ( n526 , n424 , n440 );
and ( n527 , n420 , n440 );
or ( n528 , n525 , n526 , n527 );
xor ( n529 , n524 , n528 );
and ( n530 , n441 , n443 );
xor ( n531 , n529 , n530 );
buf ( n532 , n531 );
buf ( n533 , n532 );
and ( n534 , n533 , n279 );
xor ( n535 , n497 , n534 );
xor ( n536 , n494 , n535 );
xor ( n537 , n483 , n536 );
and ( n538 , n412 , n414 );
buf ( n539 , n538 );
buf ( n540 , n539 );
xor ( n541 , n537 , n540 );
and ( n542 , n405 , n449 );
buf ( n543 , n542 );
xor ( n544 , n541 , n543 );
and ( n545 , n450 , n452 );
xor ( n546 , n544 , n545 );
buf ( n547 , n546 );
buf ( n548 , n547 );
not ( n549 , n548 );
buf ( n550 , n200 );
not ( n551 , n550 );
nor ( n552 , n549 , n551 );
xor ( n553 , n479 , n552 );
xor ( n554 , n464 , n476 );
nor ( n555 , n456 , n551 );
and ( n556 , n554 , n555 );
xor ( n557 , n554 , n555 );
xor ( n558 , n469 , n474 );
nor ( n559 , n384 , n551 );
and ( n560 , n558 , n559 );
xor ( n561 , n558 , n559 );
xor ( n562 , n471 , n472 );
buf ( n563 , n562 );
nor ( n564 , n334 , n551 );
and ( n565 , n563 , n564 );
xor ( n566 , n563 , n564 );
nor ( n567 , n283 , n458 );
buf ( n568 , n567 );
nor ( n569 , n303 , n551 );
and ( n570 , n568 , n569 );
buf ( n571 , n570 );
and ( n572 , n566 , n571 );
or ( n573 , n565 , n572 );
and ( n574 , n561 , n573 );
or ( n575 , n560 , n574 );
and ( n576 , n557 , n575 );
or ( n577 , n556 , n576 );
xor ( n578 , n553 , n577 );
and ( n579 , n483 , n536 );
and ( n580 , n536 , n540 );
and ( n581 , n483 , n540 );
or ( n582 , n579 , n580 , n581 );
buf ( n583 , n582 );
and ( n584 , n487 , n493 );
and ( n585 , n493 , n535 );
and ( n586 , n487 , n535 );
or ( n587 , n584 , n585 , n586 );
and ( n588 , n495 , n496 );
and ( n589 , n496 , n534 );
and ( n590 , n495 , n534 );
or ( n591 , n588 , n589 , n590 );
and ( n592 , n446 , n312 );
and ( n593 , n533 , n288 );
xor ( n594 , n592 , n593 );
and ( n595 , n520 , n522 );
and ( n596 , n501 , n515 );
and ( n597 , n515 , n523 );
and ( n598 , n501 , n523 );
or ( n599 , n596 , n597 , n598 );
xor ( n600 , n595 , n599 );
and ( n601 , n503 , n508 );
and ( n602 , n508 , n514 );
and ( n603 , n503 , n514 );
or ( n604 , n601 , n602 , n603 );
and ( n605 , n511 , n513 );
buf ( n606 , n605 );
buf ( n607 , n250 );
and ( n608 , n273 , n607 );
buf ( n609 , n608 );
and ( n610 , n294 , n510 );
xor ( n611 , n609 , n610 );
xor ( n612 , n606 , n611 );
and ( n613 , n318 , n435 );
and ( n614 , n361 , n354 );
xor ( n615 , n613 , n614 );
and ( n616 , n431 , n321 );
xor ( n617 , n615 , n616 );
xor ( n618 , n612 , n617 );
xor ( n619 , n604 , n618 );
and ( n620 , n504 , n505 );
and ( n621 , n505 , n507 );
and ( n622 , n504 , n507 );
or ( n623 , n620 , n621 , n622 );
and ( n624 , n521 , n291 );
buf ( n625 , n219 );
and ( n626 , n625 , n274 );
xor ( n627 , n624 , n626 );
xor ( n628 , n623 , n627 );
xor ( n629 , n619 , n628 );
xor ( n630 , n600 , n629 );
and ( n631 , n524 , n528 );
and ( n632 , n529 , n530 );
or ( n633 , n631 , n632 );
xor ( n634 , n630 , n633 );
buf ( n635 , n634 );
buf ( n636 , n635 );
and ( n637 , n636 , n279 );
xor ( n638 , n594 , n637 );
xor ( n639 , n591 , n638 );
and ( n640 , n298 , n488 );
and ( n641 , n328 , n411 );
xor ( n642 , n640 , n641 );
and ( n643 , n371 , n375 );
xor ( n644 , n642 , n643 );
xor ( n645 , n639 , n644 );
xor ( n646 , n587 , n645 );
and ( n647 , n489 , n490 );
and ( n648 , n490 , n492 );
and ( n649 , n489 , n492 );
or ( n650 , n647 , n648 , n649 );
buf ( n651 , n235 );
and ( n652 , n277 , n651 );
buf ( n653 , n652 );
xor ( n654 , n650 , n653 );
xor ( n655 , n646 , n654 );
xor ( n656 , n583 , n655 );
and ( n657 , n541 , n543 );
and ( n658 , n544 , n545 );
or ( n659 , n657 , n658 );
xor ( n660 , n656 , n659 );
buf ( n661 , n660 );
buf ( n662 , n661 );
not ( n663 , n662 );
buf ( n664 , n201 );
not ( n665 , n664 );
nor ( n666 , n663 , n665 );
xor ( n667 , n578 , n666 );
xor ( n668 , n557 , n575 );
nor ( n669 , n549 , n665 );
and ( n670 , n668 , n669 );
xor ( n671 , n668 , n669 );
xor ( n672 , n561 , n573 );
nor ( n673 , n456 , n665 );
and ( n674 , n672 , n673 );
xor ( n675 , n672 , n673 );
xor ( n676 , n566 , n571 );
nor ( n677 , n384 , n665 );
and ( n678 , n676 , n677 );
xor ( n679 , n676 , n677 );
xor ( n680 , n568 , n569 );
buf ( n681 , n680 );
nor ( n682 , n334 , n665 );
and ( n683 , n681 , n682 );
xor ( n684 , n681 , n682 );
nor ( n685 , n283 , n551 );
buf ( n686 , n685 );
nor ( n687 , n303 , n665 );
and ( n688 , n686 , n687 );
buf ( n689 , n688 );
and ( n690 , n684 , n689 );
or ( n691 , n683 , n690 );
and ( n692 , n679 , n691 );
or ( n693 , n678 , n692 );
and ( n694 , n675 , n693 );
or ( n695 , n674 , n694 );
and ( n696 , n671 , n695 );
or ( n697 , n670 , n696 );
xor ( n698 , n667 , n697 );
and ( n699 , n650 , n653 );
and ( n700 , n587 , n645 );
and ( n701 , n645 , n654 );
and ( n702 , n587 , n654 );
or ( n703 , n700 , n701 , n702 );
xor ( n704 , n699 , n703 );
and ( n705 , n591 , n638 );
and ( n706 , n638 , n644 );
and ( n707 , n591 , n644 );
or ( n708 , n705 , n706 , n707 );
and ( n709 , n640 , n641 );
and ( n710 , n641 , n643 );
and ( n711 , n640 , n643 );
or ( n712 , n709 , n710 , n711 );
buf ( n713 , n712 );
buf ( n714 , n234 );
and ( n715 , n277 , n714 );
buf ( n716 , n715 );
and ( n717 , n298 , n651 );
xor ( n718 , n716 , n717 );
xor ( n719 , n713 , n718 );
xor ( n720 , n708 , n719 );
and ( n721 , n592 , n593 );
and ( n722 , n593 , n637 );
and ( n723 , n592 , n637 );
or ( n724 , n721 , n722 , n723 );
and ( n725 , n328 , n488 );
and ( n726 , n371 , n411 );
xor ( n727 , n725 , n726 );
and ( n728 , n446 , n375 );
xor ( n729 , n727 , n728 );
xor ( n730 , n724 , n729 );
and ( n731 , n533 , n312 );
and ( n732 , n636 , n288 );
xor ( n733 , n731 , n732 );
and ( n734 , n623 , n627 );
and ( n735 , n604 , n618 );
and ( n736 , n618 , n628 );
and ( n737 , n604 , n628 );
or ( n738 , n735 , n736 , n737 );
xor ( n739 , n734 , n738 );
and ( n740 , n606 , n611 );
and ( n741 , n611 , n617 );
and ( n742 , n606 , n617 );
or ( n743 , n740 , n741 , n742 );
and ( n744 , n613 , n614 );
and ( n745 , n614 , n616 );
and ( n746 , n613 , n616 );
or ( n747 , n744 , n745 , n746 );
and ( n748 , n624 , n626 );
xor ( n749 , n747 , n748 );
and ( n750 , n521 , n321 );
and ( n751 , n625 , n291 );
xor ( n752 , n750 , n751 );
buf ( n753 , n218 );
and ( n754 , n753 , n274 );
xor ( n755 , n752 , n754 );
xor ( n756 , n749 , n755 );
xor ( n757 , n743 , n756 );
and ( n758 , n608 , n610 );
buf ( n759 , n758 );
and ( n760 , n318 , n510 );
and ( n761 , n361 , n435 );
xor ( n762 , n760 , n761 );
and ( n763 , n431 , n354 );
xor ( n764 , n762 , n763 );
xor ( n765 , n759 , n764 );
buf ( n766 , n249 );
and ( n767 , n273 , n766 );
buf ( n768 , n767 );
and ( n769 , n294 , n607 );
xor ( n770 , n768 , n769 );
xor ( n771 , n765 , n770 );
xor ( n772 , n757 , n771 );
xor ( n773 , n739 , n772 );
and ( n774 , n595 , n599 );
and ( n775 , n599 , n629 );
and ( n776 , n595 , n629 );
or ( n777 , n774 , n775 , n776 );
xor ( n778 , n773 , n777 );
and ( n779 , n630 , n633 );
xor ( n780 , n778 , n779 );
buf ( n781 , n780 );
buf ( n782 , n781 );
and ( n783 , n782 , n279 );
xor ( n784 , n733 , n783 );
xor ( n785 , n730 , n784 );
xor ( n786 , n720 , n785 );
xor ( n787 , n704 , n786 );
and ( n788 , n582 , n655 );
buf ( n789 , n788 );
xor ( n790 , n787 , n789 );
and ( n791 , n656 , n659 );
xor ( n792 , n790 , n791 );
buf ( n793 , n792 );
buf ( n794 , n793 );
not ( n795 , n794 );
buf ( n796 , n202 );
not ( n797 , n796 );
nor ( n798 , n795 , n797 );
xor ( n799 , n698 , n798 );
xor ( n800 , n671 , n695 );
nor ( n801 , n663 , n797 );
and ( n802 , n800 , n801 );
xor ( n803 , n800 , n801 );
xor ( n804 , n675 , n693 );
nor ( n805 , n549 , n797 );
and ( n806 , n804 , n805 );
xor ( n807 , n804 , n805 );
xor ( n808 , n679 , n691 );
nor ( n809 , n456 , n797 );
and ( n810 , n808 , n809 );
xor ( n811 , n808 , n809 );
xor ( n812 , n684 , n689 );
nor ( n813 , n384 , n797 );
and ( n814 , n812 , n813 );
xor ( n815 , n812 , n813 );
xor ( n816 , n686 , n687 );
buf ( n817 , n816 );
nor ( n818 , n334 , n797 );
and ( n819 , n817 , n818 );
xor ( n820 , n817 , n818 );
nor ( n821 , n283 , n665 );
buf ( n822 , n821 );
nor ( n823 , n303 , n797 );
and ( n824 , n822 , n823 );
buf ( n825 , n824 );
and ( n826 , n820 , n825 );
or ( n827 , n819 , n826 );
and ( n828 , n815 , n827 );
or ( n829 , n814 , n828 );
and ( n830 , n811 , n829 );
or ( n831 , n810 , n830 );
and ( n832 , n807 , n831 );
or ( n833 , n806 , n832 );
and ( n834 , n803 , n833 );
or ( n835 , n802 , n834 );
xor ( n836 , n799 , n835 );
and ( n837 , n708 , n719 );
and ( n838 , n719 , n785 );
and ( n839 , n708 , n785 );
or ( n840 , n837 , n838 , n839 );
and ( n841 , n724 , n729 );
and ( n842 , n729 , n784 );
and ( n843 , n724 , n784 );
or ( n844 , n841 , n842 , n843 );
and ( n845 , n715 , n717 );
buf ( n846 , n845 );
and ( n847 , n725 , n726 );
and ( n848 , n726 , n728 );
and ( n849 , n725 , n728 );
or ( n850 , n847 , n848 , n849 );
xor ( n851 , n846 , n850 );
buf ( n852 , n233 );
and ( n853 , n277 , n852 );
and ( n854 , n298 , n714 );
xor ( n855 , n853 , n854 );
and ( n856 , n328 , n651 );
xor ( n857 , n855 , n856 );
xor ( n858 , n851 , n857 );
xor ( n859 , n844 , n858 );
and ( n860 , n731 , n732 );
and ( n861 , n732 , n783 );
and ( n862 , n731 , n783 );
or ( n863 , n860 , n861 , n862 );
and ( n864 , n371 , n488 );
and ( n865 , n446 , n411 );
xor ( n866 , n864 , n865 );
and ( n867 , n533 , n375 );
xor ( n868 , n866 , n867 );
xor ( n869 , n863 , n868 );
and ( n870 , n636 , n312 );
and ( n871 , n782 , n288 );
xor ( n872 , n870 , n871 );
and ( n873 , n743 , n756 );
and ( n874 , n756 , n771 );
and ( n875 , n743 , n771 );
or ( n876 , n873 , n874 , n875 );
and ( n877 , n759 , n764 );
and ( n878 , n764 , n770 );
and ( n879 , n759 , n770 );
or ( n880 , n877 , n878 , n879 );
and ( n881 , n750 , n751 );
and ( n882 , n751 , n754 );
and ( n883 , n750 , n754 );
or ( n884 , n881 , n882 , n883 );
and ( n885 , n760 , n761 );
and ( n886 , n761 , n763 );
and ( n887 , n760 , n763 );
or ( n888 , n885 , n886 , n887 );
xor ( n889 , n884 , n888 );
and ( n890 , n521 , n354 );
and ( n891 , n625 , n321 );
xor ( n892 , n890 , n891 );
and ( n893 , n753 , n291 );
xor ( n894 , n892 , n893 );
xor ( n895 , n889 , n894 );
xor ( n896 , n880 , n895 );
and ( n897 , n767 , n769 );
buf ( n898 , n897 );
and ( n899 , n318 , n607 );
and ( n900 , n361 , n510 );
xor ( n901 , n899 , n900 );
and ( n902 , n431 , n435 );
xor ( n903 , n901 , n902 );
xor ( n904 , n898 , n903 );
buf ( n905 , n248 );
and ( n906 , n273 , n905 );
buf ( n907 , n906 );
and ( n908 , n294 , n766 );
xor ( n909 , n907 , n908 );
xor ( n910 , n904 , n909 );
xor ( n911 , n896 , n910 );
xor ( n912 , n876 , n911 );
and ( n913 , n747 , n748 );
and ( n914 , n748 , n755 );
and ( n915 , n747 , n755 );
or ( n916 , n913 , n914 , n915 );
buf ( n917 , n217 );
and ( n918 , n917 , n274 );
xor ( n919 , n916 , n918 );
xor ( n920 , n912 , n919 );
and ( n921 , n734 , n738 );
and ( n922 , n738 , n772 );
and ( n923 , n734 , n772 );
or ( n924 , n921 , n922 , n923 );
xor ( n925 , n920 , n924 );
and ( n926 , n773 , n777 );
and ( n927 , n778 , n779 );
or ( n928 , n926 , n927 );
xor ( n929 , n925 , n928 );
buf ( n930 , n929 );
buf ( n931 , n930 );
and ( n932 , n931 , n279 );
xor ( n933 , n872 , n932 );
xor ( n934 , n869 , n933 );
xor ( n935 , n859 , n934 );
xor ( n936 , n840 , n935 );
and ( n937 , n712 , n718 );
buf ( n938 , n937 );
buf ( n939 , n938 );
xor ( n940 , n936 , n939 );
and ( n941 , n699 , n703 );
and ( n942 , n703 , n786 );
and ( n943 , n699 , n786 );
or ( n944 , n941 , n942 , n943 );
xor ( n945 , n940 , n944 );
and ( n946 , n787 , n789 );
and ( n947 , n790 , n791 );
or ( n948 , n946 , n947 );
xor ( n949 , n945 , n948 );
buf ( n950 , n949 );
buf ( n951 , n950 );
not ( n952 , n951 );
buf ( n953 , n203 );
not ( n954 , n953 );
nor ( n955 , n952 , n954 );
xor ( n956 , n836 , n955 );
xor ( n957 , n803 , n833 );
nor ( n958 , n795 , n954 );
and ( n959 , n957 , n958 );
xor ( n960 , n957 , n958 );
xor ( n961 , n807 , n831 );
nor ( n962 , n663 , n954 );
and ( n963 , n961 , n962 );
xor ( n964 , n961 , n962 );
xor ( n965 , n811 , n829 );
nor ( n966 , n549 , n954 );
and ( n967 , n965 , n966 );
xor ( n968 , n965 , n966 );
xor ( n969 , n815 , n827 );
nor ( n970 , n456 , n954 );
and ( n971 , n969 , n970 );
xor ( n972 , n969 , n970 );
xor ( n973 , n820 , n825 );
nor ( n974 , n384 , n954 );
and ( n975 , n973 , n974 );
xor ( n976 , n973 , n974 );
xor ( n977 , n822 , n823 );
buf ( n978 , n977 );
nor ( n979 , n334 , n954 );
and ( n980 , n978 , n979 );
xor ( n981 , n978 , n979 );
nor ( n982 , n283 , n797 );
buf ( n983 , n982 );
nor ( n984 , n303 , n954 );
and ( n985 , n983 , n984 );
buf ( n986 , n985 );
and ( n987 , n981 , n986 );
or ( n988 , n980 , n987 );
and ( n989 , n976 , n988 );
or ( n990 , n975 , n989 );
and ( n991 , n972 , n990 );
or ( n992 , n971 , n991 );
and ( n993 , n968 , n992 );
or ( n994 , n967 , n993 );
and ( n995 , n964 , n994 );
or ( n996 , n963 , n995 );
and ( n997 , n960 , n996 );
or ( n998 , n959 , n997 );
xor ( n999 , n956 , n998 );
and ( n1000 , n840 , n935 );
and ( n1001 , n935 , n939 );
and ( n1002 , n840 , n939 );
or ( n1003 , n1000 , n1001 , n1002 );
buf ( n1004 , n1003 );
and ( n1005 , n844 , n858 );
and ( n1006 , n858 , n934 );
and ( n1007 , n844 , n934 );
or ( n1008 , n1005 , n1006 , n1007 );
and ( n1009 , n863 , n868 );
and ( n1010 , n868 , n933 );
and ( n1011 , n863 , n933 );
or ( n1012 , n1009 , n1010 , n1011 );
and ( n1013 , n870 , n871 );
and ( n1014 , n871 , n932 );
and ( n1015 , n870 , n932 );
or ( n1016 , n1013 , n1014 , n1015 );
and ( n1017 , n446 , n488 );
and ( n1018 , n533 , n411 );
xor ( n1019 , n1017 , n1018 );
and ( n1020 , n636 , n375 );
xor ( n1021 , n1019 , n1020 );
xor ( n1022 , n1016 , n1021 );
and ( n1023 , n782 , n312 );
and ( n1024 , n931 , n288 );
xor ( n1025 , n1023 , n1024 );
and ( n1026 , n916 , n918 );
and ( n1027 , n876 , n911 );
and ( n1028 , n911 , n919 );
and ( n1029 , n876 , n919 );
or ( n1030 , n1027 , n1028 , n1029 );
xor ( n1031 , n1026 , n1030 );
and ( n1032 , n880 , n895 );
and ( n1033 , n895 , n910 );
and ( n1034 , n880 , n910 );
or ( n1035 , n1032 , n1033 , n1034 );
and ( n1036 , n898 , n903 );
and ( n1037 , n903 , n909 );
and ( n1038 , n898 , n909 );
or ( n1039 , n1036 , n1037 , n1038 );
and ( n1040 , n906 , n908 );
buf ( n1041 , n1040 );
and ( n1042 , n318 , n766 );
and ( n1043 , n361 , n607 );
xor ( n1044 , n1042 , n1043 );
and ( n1045 , n431 , n510 );
xor ( n1046 , n1044 , n1045 );
xor ( n1047 , n1041 , n1046 );
buf ( n1048 , n247 );
and ( n1049 , n273 , n1048 );
buf ( n1050 , n1049 );
and ( n1051 , n294 , n905 );
xor ( n1052 , n1050 , n1051 );
xor ( n1053 , n1047 , n1052 );
xor ( n1054 , n1039 , n1053 );
and ( n1055 , n890 , n891 );
and ( n1056 , n891 , n893 );
and ( n1057 , n890 , n893 );
or ( n1058 , n1055 , n1056 , n1057 );
and ( n1059 , n899 , n900 );
and ( n1060 , n900 , n902 );
and ( n1061 , n899 , n902 );
or ( n1062 , n1059 , n1060 , n1061 );
xor ( n1063 , n1058 , n1062 );
and ( n1064 , n521 , n435 );
and ( n1065 , n625 , n354 );
xor ( n1066 , n1064 , n1065 );
and ( n1067 , n753 , n321 );
xor ( n1068 , n1066 , n1067 );
xor ( n1069 , n1063 , n1068 );
xor ( n1070 , n1054 , n1069 );
xor ( n1071 , n1035 , n1070 );
and ( n1072 , n884 , n888 );
and ( n1073 , n888 , n894 );
and ( n1074 , n884 , n894 );
or ( n1075 , n1072 , n1073 , n1074 );
and ( n1076 , n917 , n291 );
buf ( n1077 , n216 );
and ( n1078 , n1077 , n274 );
xor ( n1079 , n1076 , n1078 );
xor ( n1080 , n1075 , n1079 );
xor ( n1081 , n1071 , n1080 );
xor ( n1082 , n1031 , n1081 );
and ( n1083 , n920 , n924 );
and ( n1084 , n925 , n928 );
or ( n1085 , n1083 , n1084 );
xor ( n1086 , n1082 , n1085 );
buf ( n1087 , n1086 );
buf ( n1088 , n1087 );
and ( n1089 , n1088 , n279 );
xor ( n1090 , n1025 , n1089 );
xor ( n1091 , n1022 , n1090 );
xor ( n1092 , n1012 , n1091 );
and ( n1093 , n853 , n854 );
and ( n1094 , n854 , n856 );
and ( n1095 , n853 , n856 );
or ( n1096 , n1093 , n1094 , n1095 );
and ( n1097 , n864 , n865 );
and ( n1098 , n865 , n867 );
and ( n1099 , n864 , n867 );
or ( n1100 , n1097 , n1098 , n1099 );
xor ( n1101 , n1096 , n1100 );
and ( n1102 , n298 , n852 );
and ( n1103 , n328 , n714 );
xor ( n1104 , n1102 , n1103 );
and ( n1105 , n371 , n651 );
xor ( n1106 , n1104 , n1105 );
xor ( n1107 , n1101 , n1106 );
xor ( n1108 , n1092 , n1107 );
xor ( n1109 , n1008 , n1108 );
and ( n1110 , n846 , n850 );
and ( n1111 , n850 , n857 );
and ( n1112 , n846 , n857 );
or ( n1113 , n1110 , n1111 , n1112 );
buf ( n1114 , n232 );
and ( n1115 , n277 , n1114 );
buf ( n1116 , n1115 );
xor ( n1117 , n1113 , n1116 );
xor ( n1118 , n1109 , n1117 );
xor ( n1119 , n1004 , n1118 );
and ( n1120 , n940 , n944 );
and ( n1121 , n945 , n948 );
or ( n1122 , n1120 , n1121 );
xor ( n1123 , n1119 , n1122 );
buf ( n1124 , n1123 );
buf ( n1125 , n1124 );
not ( n1126 , n1125 );
buf ( n1127 , n204 );
not ( n1128 , n1127 );
nor ( n1129 , n1126 , n1128 );
xor ( n1130 , n999 , n1129 );
xor ( n1131 , n960 , n996 );
nor ( n1132 , n952 , n1128 );
and ( n1133 , n1131 , n1132 );
xor ( n1134 , n1131 , n1132 );
xor ( n1135 , n964 , n994 );
nor ( n1136 , n795 , n1128 );
and ( n1137 , n1135 , n1136 );
xor ( n1138 , n1135 , n1136 );
xor ( n1139 , n968 , n992 );
nor ( n1140 , n663 , n1128 );
and ( n1141 , n1139 , n1140 );
xor ( n1142 , n1139 , n1140 );
xor ( n1143 , n972 , n990 );
nor ( n1144 , n549 , n1128 );
and ( n1145 , n1143 , n1144 );
xor ( n1146 , n1143 , n1144 );
xor ( n1147 , n976 , n988 );
nor ( n1148 , n456 , n1128 );
and ( n1149 , n1147 , n1148 );
xor ( n1150 , n1147 , n1148 );
xor ( n1151 , n981 , n986 );
nor ( n1152 , n384 , n1128 );
and ( n1153 , n1151 , n1152 );
xor ( n1154 , n1151 , n1152 );
xor ( n1155 , n983 , n984 );
buf ( n1156 , n1155 );
nor ( n1157 , n334 , n1128 );
and ( n1158 , n1156 , n1157 );
xor ( n1159 , n1156 , n1157 );
nor ( n1160 , n283 , n954 );
buf ( n1161 , n1160 );
nor ( n1162 , n303 , n1128 );
and ( n1163 , n1161 , n1162 );
buf ( n1164 , n1163 );
and ( n1165 , n1159 , n1164 );
or ( n1166 , n1158 , n1165 );
and ( n1167 , n1154 , n1166 );
or ( n1168 , n1153 , n1167 );
and ( n1169 , n1150 , n1168 );
or ( n1170 , n1149 , n1169 );
and ( n1171 , n1146 , n1170 );
or ( n1172 , n1145 , n1171 );
and ( n1173 , n1142 , n1172 );
or ( n1174 , n1141 , n1173 );
and ( n1175 , n1138 , n1174 );
or ( n1176 , n1137 , n1175 );
and ( n1177 , n1134 , n1176 );
or ( n1178 , n1133 , n1177 );
xor ( n1179 , n1130 , n1178 );
and ( n1180 , n1113 , n1116 );
and ( n1181 , n1008 , n1108 );
and ( n1182 , n1108 , n1117 );
and ( n1183 , n1008 , n1117 );
or ( n1184 , n1181 , n1182 , n1183 );
xor ( n1185 , n1180 , n1184 );
and ( n1186 , n1012 , n1091 );
and ( n1187 , n1091 , n1107 );
and ( n1188 , n1012 , n1107 );
or ( n1189 , n1186 , n1187 , n1188 );
and ( n1190 , n1016 , n1021 );
and ( n1191 , n1021 , n1090 );
and ( n1192 , n1016 , n1090 );
or ( n1193 , n1190 , n1191 , n1192 );
and ( n1194 , n1017 , n1018 );
and ( n1195 , n1018 , n1020 );
and ( n1196 , n1017 , n1020 );
or ( n1197 , n1194 , n1195 , n1196 );
and ( n1198 , n1102 , n1103 );
and ( n1199 , n1103 , n1105 );
and ( n1200 , n1102 , n1105 );
or ( n1201 , n1198 , n1199 , n1200 );
xor ( n1202 , n1197 , n1201 );
and ( n1203 , n328 , n852 );
and ( n1204 , n371 , n714 );
xor ( n1205 , n1203 , n1204 );
and ( n1206 , n446 , n651 );
xor ( n1207 , n1205 , n1206 );
xor ( n1208 , n1202 , n1207 );
xor ( n1209 , n1193 , n1208 );
and ( n1210 , n1023 , n1024 );
and ( n1211 , n1024 , n1089 );
and ( n1212 , n1023 , n1089 );
or ( n1213 , n1210 , n1211 , n1212 );
and ( n1214 , n533 , n488 );
and ( n1215 , n636 , n411 );
xor ( n1216 , n1214 , n1215 );
and ( n1217 , n782 , n375 );
xor ( n1218 , n1216 , n1217 );
xor ( n1219 , n1213 , n1218 );
and ( n1220 , n931 , n312 );
and ( n1221 , n1088 , n288 );
xor ( n1222 , n1220 , n1221 );
and ( n1223 , n1075 , n1079 );
and ( n1224 , n1035 , n1070 );
and ( n1225 , n1070 , n1080 );
and ( n1226 , n1035 , n1080 );
or ( n1227 , n1224 , n1225 , n1226 );
xor ( n1228 , n1223 , n1227 );
and ( n1229 , n1039 , n1053 );
and ( n1230 , n1053 , n1069 );
and ( n1231 , n1039 , n1069 );
or ( n1232 , n1229 , n1230 , n1231 );
and ( n1233 , n1041 , n1046 );
and ( n1234 , n1046 , n1052 );
and ( n1235 , n1041 , n1052 );
or ( n1236 , n1233 , n1234 , n1235 );
and ( n1237 , n1042 , n1043 );
and ( n1238 , n1043 , n1045 );
and ( n1239 , n1042 , n1045 );
or ( n1240 , n1237 , n1238 , n1239 );
and ( n1241 , n1064 , n1065 );
and ( n1242 , n1065 , n1067 );
and ( n1243 , n1064 , n1067 );
or ( n1244 , n1241 , n1242 , n1243 );
xor ( n1245 , n1240 , n1244 );
and ( n1246 , n521 , n510 );
and ( n1247 , n625 , n435 );
xor ( n1248 , n1246 , n1247 );
and ( n1249 , n753 , n354 );
xor ( n1250 , n1248 , n1249 );
xor ( n1251 , n1245 , n1250 );
xor ( n1252 , n1236 , n1251 );
and ( n1253 , n1049 , n1051 );
buf ( n1254 , n1253 );
and ( n1255 , n318 , n905 );
and ( n1256 , n361 , n766 );
xor ( n1257 , n1255 , n1256 );
and ( n1258 , n431 , n607 );
xor ( n1259 , n1257 , n1258 );
xor ( n1260 , n1254 , n1259 );
buf ( n1261 , n246 );
and ( n1262 , n273 , n1261 );
buf ( n1263 , n1262 );
and ( n1264 , n294 , n1048 );
xor ( n1265 , n1263 , n1264 );
xor ( n1266 , n1260 , n1265 );
xor ( n1267 , n1252 , n1266 );
xor ( n1268 , n1232 , n1267 );
and ( n1269 , n1058 , n1062 );
and ( n1270 , n1062 , n1068 );
and ( n1271 , n1058 , n1068 );
or ( n1272 , n1269 , n1270 , n1271 );
and ( n1273 , n1076 , n1078 );
and ( n1274 , n917 , n321 );
and ( n1275 , n1077 , n291 );
xor ( n1276 , n1274 , n1275 );
buf ( n1277 , n215 );
and ( n1278 , n1277 , n274 );
xor ( n1279 , n1276 , n1278 );
xor ( n1280 , n1273 , n1279 );
xor ( n1281 , n1272 , n1280 );
xor ( n1282 , n1268 , n1281 );
xor ( n1283 , n1228 , n1282 );
and ( n1284 , n1026 , n1030 );
and ( n1285 , n1030 , n1081 );
and ( n1286 , n1026 , n1081 );
or ( n1287 , n1284 , n1285 , n1286 );
xor ( n1288 , n1283 , n1287 );
and ( n1289 , n1082 , n1085 );
xor ( n1290 , n1288 , n1289 );
buf ( n1291 , n1290 );
buf ( n1292 , n1291 );
and ( n1293 , n1292 , n279 );
xor ( n1294 , n1222 , n1293 );
xor ( n1295 , n1219 , n1294 );
xor ( n1296 , n1209 , n1295 );
xor ( n1297 , n1189 , n1296 );
and ( n1298 , n1096 , n1100 );
and ( n1299 , n1100 , n1106 );
and ( n1300 , n1096 , n1106 );
or ( n1301 , n1298 , n1299 , n1300 );
buf ( n1302 , n231 );
and ( n1303 , n277 , n1302 );
buf ( n1304 , n1303 );
and ( n1305 , n298 , n1114 );
xor ( n1306 , n1304 , n1305 );
buf ( n1307 , n1306 );
xor ( n1308 , n1301 , n1307 );
xor ( n1309 , n1297 , n1308 );
xor ( n1310 , n1185 , n1309 );
and ( n1311 , n1003 , n1118 );
buf ( n1312 , n1311 );
xor ( n1313 , n1310 , n1312 );
and ( n1314 , n1119 , n1122 );
xor ( n1315 , n1313 , n1314 );
buf ( n1316 , n1315 );
buf ( n1317 , n1316 );
not ( n1318 , n1317 );
buf ( n1319 , n205 );
not ( n1320 , n1319 );
nor ( n1321 , n1318 , n1320 );
xor ( n1322 , n1179 , n1321 );
xor ( n1323 , n1134 , n1176 );
nor ( n1324 , n1126 , n1320 );
and ( n1325 , n1323 , n1324 );
xor ( n1326 , n1323 , n1324 );
xor ( n1327 , n1138 , n1174 );
nor ( n1328 , n952 , n1320 );
and ( n1329 , n1327 , n1328 );
xor ( n1330 , n1327 , n1328 );
xor ( n1331 , n1142 , n1172 );
nor ( n1332 , n795 , n1320 );
and ( n1333 , n1331 , n1332 );
xor ( n1334 , n1331 , n1332 );
xor ( n1335 , n1146 , n1170 );
nor ( n1336 , n663 , n1320 );
and ( n1337 , n1335 , n1336 );
xor ( n1338 , n1335 , n1336 );
xor ( n1339 , n1150 , n1168 );
nor ( n1340 , n549 , n1320 );
and ( n1341 , n1339 , n1340 );
xor ( n1342 , n1339 , n1340 );
xor ( n1343 , n1154 , n1166 );
nor ( n1344 , n456 , n1320 );
and ( n1345 , n1343 , n1344 );
xor ( n1346 , n1343 , n1344 );
xor ( n1347 , n1159 , n1164 );
nor ( n1348 , n384 , n1320 );
and ( n1349 , n1347 , n1348 );
xor ( n1350 , n1347 , n1348 );
xor ( n1351 , n1161 , n1162 );
buf ( n1352 , n1351 );
nor ( n1353 , n334 , n1320 );
and ( n1354 , n1352 , n1353 );
xor ( n1355 , n1352 , n1353 );
nor ( n1356 , n283 , n1128 );
buf ( n1357 , n1356 );
nor ( n1358 , n303 , n1320 );
and ( n1359 , n1357 , n1358 );
buf ( n1360 , n1359 );
and ( n1361 , n1355 , n1360 );
or ( n1362 , n1354 , n1361 );
and ( n1363 , n1350 , n1362 );
or ( n1364 , n1349 , n1363 );
and ( n1365 , n1346 , n1364 );
or ( n1366 , n1345 , n1365 );
and ( n1367 , n1342 , n1366 );
or ( n1368 , n1341 , n1367 );
and ( n1369 , n1338 , n1368 );
or ( n1370 , n1337 , n1369 );
and ( n1371 , n1334 , n1370 );
or ( n1372 , n1333 , n1371 );
and ( n1373 , n1330 , n1372 );
or ( n1374 , n1329 , n1373 );
and ( n1375 , n1326 , n1374 );
or ( n1376 , n1325 , n1375 );
xor ( n1377 , n1322 , n1376 );
and ( n1378 , n1301 , n1307 );
and ( n1379 , n1189 , n1296 );
and ( n1380 , n1296 , n1308 );
and ( n1381 , n1189 , n1308 );
or ( n1382 , n1379 , n1380 , n1381 );
xor ( n1383 , n1378 , n1382 );
and ( n1384 , n1193 , n1208 );
and ( n1385 , n1208 , n1295 );
and ( n1386 , n1193 , n1295 );
or ( n1387 , n1384 , n1385 , n1386 );
and ( n1388 , n1197 , n1201 );
and ( n1389 , n1201 , n1207 );
and ( n1390 , n1197 , n1207 );
or ( n1391 , n1388 , n1389 , n1390 );
buf ( n1392 , n1391 );
and ( n1393 , n1303 , n1305 );
buf ( n1394 , n1393 );
buf ( n1395 , n1394 );
buf ( n1396 , n230 );
and ( n1397 , n277 , n1396 );
and ( n1398 , n298 , n1302 );
xor ( n1399 , n1397 , n1398 );
and ( n1400 , n328 , n1114 );
xor ( n1401 , n1399 , n1400 );
xor ( n1402 , n1395 , n1401 );
xor ( n1403 , n1392 , n1402 );
xor ( n1404 , n1387 , n1403 );
and ( n1405 , n1213 , n1218 );
and ( n1406 , n1218 , n1294 );
and ( n1407 , n1213 , n1294 );
or ( n1408 , n1405 , n1406 , n1407 );
and ( n1409 , n1203 , n1204 );
and ( n1410 , n1204 , n1206 );
and ( n1411 , n1203 , n1206 );
or ( n1412 , n1409 , n1410 , n1411 );
and ( n1413 , n1214 , n1215 );
and ( n1414 , n1215 , n1217 );
and ( n1415 , n1214 , n1217 );
or ( n1416 , n1413 , n1414 , n1415 );
xor ( n1417 , n1412 , n1416 );
and ( n1418 , n371 , n852 );
and ( n1419 , n446 , n714 );
xor ( n1420 , n1418 , n1419 );
and ( n1421 , n533 , n651 );
xor ( n1422 , n1420 , n1421 );
xor ( n1423 , n1417 , n1422 );
xor ( n1424 , n1408 , n1423 );
and ( n1425 , n1220 , n1221 );
and ( n1426 , n1221 , n1293 );
and ( n1427 , n1220 , n1293 );
or ( n1428 , n1425 , n1426 , n1427 );
and ( n1429 , n636 , n488 );
and ( n1430 , n782 , n411 );
xor ( n1431 , n1429 , n1430 );
and ( n1432 , n931 , n375 );
xor ( n1433 , n1431 , n1432 );
xor ( n1434 , n1428 , n1433 );
and ( n1435 , n1088 , n312 );
and ( n1436 , n1292 , n288 );
xor ( n1437 , n1435 , n1436 );
and ( n1438 , n1272 , n1280 );
and ( n1439 , n1232 , n1267 );
and ( n1440 , n1267 , n1281 );
and ( n1441 , n1232 , n1281 );
or ( n1442 , n1439 , n1440 , n1441 );
xor ( n1443 , n1438 , n1442 );
and ( n1444 , n1236 , n1251 );
and ( n1445 , n1251 , n1266 );
and ( n1446 , n1236 , n1266 );
or ( n1447 , n1444 , n1445 , n1446 );
and ( n1448 , n1240 , n1244 );
and ( n1449 , n1244 , n1250 );
and ( n1450 , n1240 , n1250 );
or ( n1451 , n1448 , n1449 , n1450 );
and ( n1452 , n1273 , n1279 );
xor ( n1453 , n1451 , n1452 );
and ( n1454 , n1274 , n1275 );
and ( n1455 , n1275 , n1278 );
and ( n1456 , n1274 , n1278 );
or ( n1457 , n1454 , n1455 , n1456 );
buf ( n1458 , n214 );
and ( n1459 , n1458 , n274 );
xor ( n1460 , n1457 , n1459 );
and ( n1461 , n917 , n354 );
and ( n1462 , n1077 , n321 );
xor ( n1463 , n1461 , n1462 );
and ( n1464 , n1277 , n291 );
xor ( n1465 , n1463 , n1464 );
xor ( n1466 , n1460 , n1465 );
xor ( n1467 , n1453 , n1466 );
xor ( n1468 , n1447 , n1467 );
and ( n1469 , n1254 , n1259 );
and ( n1470 , n1259 , n1265 );
and ( n1471 , n1254 , n1265 );
or ( n1472 , n1469 , n1470 , n1471 );
and ( n1473 , n1246 , n1247 );
and ( n1474 , n1247 , n1249 );
and ( n1475 , n1246 , n1249 );
or ( n1476 , n1473 , n1474 , n1475 );
and ( n1477 , n1255 , n1256 );
and ( n1478 , n1256 , n1258 );
and ( n1479 , n1255 , n1258 );
or ( n1480 , n1477 , n1478 , n1479 );
xor ( n1481 , n1476 , n1480 );
and ( n1482 , n521 , n607 );
and ( n1483 , n625 , n510 );
xor ( n1484 , n1482 , n1483 );
and ( n1485 , n753 , n435 );
xor ( n1486 , n1484 , n1485 );
xor ( n1487 , n1481 , n1486 );
xor ( n1488 , n1472 , n1487 );
and ( n1489 , n1262 , n1264 );
buf ( n1490 , n1489 );
and ( n1491 , n318 , n1048 );
and ( n1492 , n361 , n905 );
xor ( n1493 , n1491 , n1492 );
and ( n1494 , n431 , n766 );
xor ( n1495 , n1493 , n1494 );
xor ( n1496 , n1490 , n1495 );
buf ( n1497 , n245 );
and ( n1498 , n273 , n1497 );
buf ( n1499 , n1498 );
and ( n1500 , n294 , n1261 );
xor ( n1501 , n1499 , n1500 );
xor ( n1502 , n1496 , n1501 );
xor ( n1503 , n1488 , n1502 );
xor ( n1504 , n1468 , n1503 );
xor ( n1505 , n1443 , n1504 );
and ( n1506 , n1223 , n1227 );
and ( n1507 , n1227 , n1282 );
and ( n1508 , n1223 , n1282 );
or ( n1509 , n1506 , n1507 , n1508 );
xor ( n1510 , n1505 , n1509 );
and ( n1511 , n1283 , n1287 );
and ( n1512 , n1288 , n1289 );
or ( n1513 , n1511 , n1512 );
xor ( n1514 , n1510 , n1513 );
buf ( n1515 , n1514 );
buf ( n1516 , n1515 );
and ( n1517 , n1516 , n279 );
xor ( n1518 , n1437 , n1517 );
xor ( n1519 , n1434 , n1518 );
xor ( n1520 , n1424 , n1519 );
xor ( n1521 , n1404 , n1520 );
xor ( n1522 , n1383 , n1521 );
and ( n1523 , n1180 , n1184 );
and ( n1524 , n1184 , n1309 );
and ( n1525 , n1180 , n1309 );
or ( n1526 , n1523 , n1524 , n1525 );
xor ( n1527 , n1522 , n1526 );
and ( n1528 , n1310 , n1312 );
and ( n1529 , n1313 , n1314 );
or ( n1530 , n1528 , n1529 );
xor ( n1531 , n1527 , n1530 );
buf ( n1532 , n1531 );
buf ( n1533 , n1532 );
not ( n1534 , n1533 );
buf ( n1535 , n206 );
not ( n1536 , n1535 );
nor ( n1537 , n1534 , n1536 );
xor ( n1538 , n1377 , n1537 );
xor ( n1539 , n1326 , n1374 );
nor ( n1540 , n1318 , n1536 );
and ( n1541 , n1539 , n1540 );
xor ( n1542 , n1539 , n1540 );
xor ( n1543 , n1330 , n1372 );
nor ( n1544 , n1126 , n1536 );
and ( n1545 , n1543 , n1544 );
xor ( n1546 , n1543 , n1544 );
xor ( n1547 , n1334 , n1370 );
nor ( n1548 , n952 , n1536 );
and ( n1549 , n1547 , n1548 );
xor ( n1550 , n1547 , n1548 );
xor ( n1551 , n1338 , n1368 );
nor ( n1552 , n795 , n1536 );
and ( n1553 , n1551 , n1552 );
xor ( n1554 , n1551 , n1552 );
xor ( n1555 , n1342 , n1366 );
nor ( n1556 , n663 , n1536 );
and ( n1557 , n1555 , n1556 );
xor ( n1558 , n1555 , n1556 );
xor ( n1559 , n1346 , n1364 );
nor ( n1560 , n549 , n1536 );
and ( n1561 , n1559 , n1560 );
xor ( n1562 , n1559 , n1560 );
xor ( n1563 , n1350 , n1362 );
nor ( n1564 , n456 , n1536 );
and ( n1565 , n1563 , n1564 );
xor ( n1566 , n1563 , n1564 );
xor ( n1567 , n1355 , n1360 );
nor ( n1568 , n384 , n1536 );
and ( n1569 , n1567 , n1568 );
xor ( n1570 , n1567 , n1568 );
xor ( n1571 , n1357 , n1358 );
buf ( n1572 , n1571 );
nor ( n1573 , n334 , n1536 );
and ( n1574 , n1572 , n1573 );
xor ( n1575 , n1572 , n1573 );
nor ( n1576 , n283 , n1320 );
buf ( n1577 , n1576 );
nor ( n1578 , n303 , n1536 );
and ( n1579 , n1577 , n1578 );
buf ( n1580 , n1579 );
and ( n1581 , n1575 , n1580 );
or ( n1582 , n1574 , n1581 );
and ( n1583 , n1570 , n1582 );
or ( n1584 , n1569 , n1583 );
and ( n1585 , n1566 , n1584 );
or ( n1586 , n1565 , n1585 );
and ( n1587 , n1562 , n1586 );
or ( n1588 , n1561 , n1587 );
and ( n1589 , n1558 , n1588 );
or ( n1590 , n1557 , n1589 );
and ( n1591 , n1554 , n1590 );
or ( n1592 , n1553 , n1591 );
and ( n1593 , n1550 , n1592 );
or ( n1594 , n1549 , n1593 );
and ( n1595 , n1546 , n1594 );
or ( n1596 , n1545 , n1595 );
and ( n1597 , n1542 , n1596 );
or ( n1598 , n1541 , n1597 );
xor ( n1599 , n1538 , n1598 );
and ( n1600 , n1391 , n1402 );
buf ( n1601 , n1600 );
and ( n1602 , n1387 , n1403 );
and ( n1603 , n1403 , n1520 );
and ( n1604 , n1387 , n1520 );
or ( n1605 , n1602 , n1603 , n1604 );
xor ( n1606 , n1601 , n1605 );
and ( n1607 , n1408 , n1423 );
and ( n1608 , n1423 , n1519 );
and ( n1609 , n1408 , n1519 );
or ( n1610 , n1607 , n1608 , n1609 );
and ( n1611 , n1428 , n1433 );
and ( n1612 , n1433 , n1518 );
and ( n1613 , n1428 , n1518 );
or ( n1614 , n1611 , n1612 , n1613 );
and ( n1615 , n1418 , n1419 );
and ( n1616 , n1419 , n1421 );
and ( n1617 , n1418 , n1421 );
or ( n1618 , n1615 , n1616 , n1617 );
and ( n1619 , n1429 , n1430 );
and ( n1620 , n1430 , n1432 );
and ( n1621 , n1429 , n1432 );
or ( n1622 , n1619 , n1620 , n1621 );
xor ( n1623 , n1618 , n1622 );
and ( n1624 , n446 , n852 );
and ( n1625 , n533 , n714 );
xor ( n1626 , n1624 , n1625 );
and ( n1627 , n636 , n651 );
xor ( n1628 , n1626 , n1627 );
xor ( n1629 , n1623 , n1628 );
xor ( n1630 , n1614 , n1629 );
and ( n1631 , n1435 , n1436 );
and ( n1632 , n1436 , n1517 );
and ( n1633 , n1435 , n1517 );
or ( n1634 , n1631 , n1632 , n1633 );
and ( n1635 , n782 , n488 );
and ( n1636 , n931 , n411 );
xor ( n1637 , n1635 , n1636 );
and ( n1638 , n1088 , n375 );
xor ( n1639 , n1637 , n1638 );
xor ( n1640 , n1634 , n1639 );
and ( n1641 , n1292 , n312 );
and ( n1642 , n1516 , n288 );
xor ( n1643 , n1641 , n1642 );
and ( n1644 , n1451 , n1452 );
and ( n1645 , n1452 , n1466 );
and ( n1646 , n1451 , n1466 );
or ( n1647 , n1644 , n1645 , n1646 );
and ( n1648 , n1447 , n1467 );
and ( n1649 , n1467 , n1503 );
and ( n1650 , n1447 , n1503 );
or ( n1651 , n1648 , n1649 , n1650 );
xor ( n1652 , n1647 , n1651 );
and ( n1653 , n1472 , n1487 );
and ( n1654 , n1487 , n1502 );
and ( n1655 , n1472 , n1502 );
or ( n1656 , n1653 , n1654 , n1655 );
and ( n1657 , n1490 , n1495 );
and ( n1658 , n1495 , n1501 );
and ( n1659 , n1490 , n1501 );
or ( n1660 , n1657 , n1658 , n1659 );
and ( n1661 , n1482 , n1483 );
and ( n1662 , n1483 , n1485 );
and ( n1663 , n1482 , n1485 );
or ( n1664 , n1661 , n1662 , n1663 );
and ( n1665 , n1491 , n1492 );
and ( n1666 , n1492 , n1494 );
and ( n1667 , n1491 , n1494 );
or ( n1668 , n1665 , n1666 , n1667 );
xor ( n1669 , n1664 , n1668 );
and ( n1670 , n521 , n766 );
and ( n1671 , n625 , n607 );
xor ( n1672 , n1670 , n1671 );
and ( n1673 , n753 , n510 );
xor ( n1674 , n1672 , n1673 );
xor ( n1675 , n1669 , n1674 );
xor ( n1676 , n1660 , n1675 );
and ( n1677 , n1498 , n1500 );
buf ( n1678 , n1677 );
and ( n1679 , n318 , n1261 );
and ( n1680 , n361 , n1048 );
xor ( n1681 , n1679 , n1680 );
and ( n1682 , n431 , n905 );
xor ( n1683 , n1681 , n1682 );
xor ( n1684 , n1678 , n1683 );
buf ( n1685 , n244 );
and ( n1686 , n273 , n1685 );
buf ( n1687 , n1686 );
and ( n1688 , n294 , n1497 );
xor ( n1689 , n1687 , n1688 );
xor ( n1690 , n1684 , n1689 );
xor ( n1691 , n1676 , n1690 );
xor ( n1692 , n1656 , n1691 );
and ( n1693 , n1457 , n1459 );
and ( n1694 , n1459 , n1465 );
and ( n1695 , n1457 , n1465 );
or ( n1696 , n1693 , n1694 , n1695 );
and ( n1697 , n1476 , n1480 );
and ( n1698 , n1480 , n1486 );
and ( n1699 , n1476 , n1486 );
or ( n1700 , n1697 , n1698 , n1699 );
xor ( n1701 , n1696 , n1700 );
and ( n1702 , n1461 , n1462 );
and ( n1703 , n1462 , n1464 );
and ( n1704 , n1461 , n1464 );
or ( n1705 , n1702 , n1703 , n1704 );
and ( n1706 , n917 , n435 );
and ( n1707 , n1077 , n354 );
xor ( n1708 , n1706 , n1707 );
and ( n1709 , n1277 , n321 );
xor ( n1710 , n1708 , n1709 );
xor ( n1711 , n1705 , n1710 );
and ( n1712 , n1458 , n291 );
buf ( n1713 , n213 );
and ( n1714 , n1713 , n274 );
xor ( n1715 , n1712 , n1714 );
xor ( n1716 , n1711 , n1715 );
xor ( n1717 , n1701 , n1716 );
xor ( n1718 , n1692 , n1717 );
xor ( n1719 , n1652 , n1718 );
and ( n1720 , n1438 , n1442 );
and ( n1721 , n1442 , n1504 );
and ( n1722 , n1438 , n1504 );
or ( n1723 , n1720 , n1721 , n1722 );
xor ( n1724 , n1719 , n1723 );
and ( n1725 , n1505 , n1509 );
and ( n1726 , n1510 , n1513 );
or ( n1727 , n1725 , n1726 );
xor ( n1728 , n1724 , n1727 );
buf ( n1729 , n1728 );
buf ( n1730 , n1729 );
and ( n1731 , n1730 , n279 );
xor ( n1732 , n1643 , n1731 );
xor ( n1733 , n1640 , n1732 );
xor ( n1734 , n1630 , n1733 );
xor ( n1735 , n1610 , n1734 );
and ( n1736 , n1394 , n1401 );
buf ( n1737 , n1736 );
and ( n1738 , n1412 , n1416 );
and ( n1739 , n1416 , n1422 );
and ( n1740 , n1412 , n1422 );
or ( n1741 , n1738 , n1739 , n1740 );
xor ( n1742 , n1737 , n1741 );
and ( n1743 , n1397 , n1398 );
and ( n1744 , n1398 , n1400 );
and ( n1745 , n1397 , n1400 );
or ( n1746 , n1743 , n1744 , n1745 );
and ( n1747 , n298 , n1396 );
and ( n1748 , n328 , n1302 );
xor ( n1749 , n1747 , n1748 );
and ( n1750 , n371 , n1114 );
xor ( n1751 , n1749 , n1750 );
xor ( n1752 , n1746 , n1751 );
buf ( n1753 , n229 );
and ( n1754 , n277 , n1753 );
buf ( n1755 , n1754 );
xor ( n1756 , n1752 , n1755 );
xor ( n1757 , n1742 , n1756 );
xor ( n1758 , n1735 , n1757 );
xor ( n1759 , n1606 , n1758 );
and ( n1760 , n1378 , n1382 );
and ( n1761 , n1382 , n1521 );
and ( n1762 , n1378 , n1521 );
or ( n1763 , n1760 , n1761 , n1762 );
xor ( n1764 , n1759 , n1763 );
and ( n1765 , n1522 , n1526 );
and ( n1766 , n1527 , n1530 );
or ( n1767 , n1765 , n1766 );
xor ( n1768 , n1764 , n1767 );
buf ( n1769 , n1768 );
buf ( n1770 , n1769 );
not ( n1771 , n1770 );
buf ( n1772 , n207 );
not ( n1773 , n1772 );
nor ( n1774 , n1771 , n1773 );
xor ( n1775 , n1599 , n1774 );
xor ( n1776 , n1542 , n1596 );
nor ( n1777 , n1534 , n1773 );
and ( n1778 , n1776 , n1777 );
xor ( n1779 , n1776 , n1777 );
xor ( n1780 , n1546 , n1594 );
nor ( n1781 , n1318 , n1773 );
and ( n1782 , n1780 , n1781 );
xor ( n1783 , n1780 , n1781 );
xor ( n1784 , n1550 , n1592 );
nor ( n1785 , n1126 , n1773 );
and ( n1786 , n1784 , n1785 );
xor ( n1787 , n1784 , n1785 );
xor ( n1788 , n1554 , n1590 );
nor ( n1789 , n952 , n1773 );
and ( n1790 , n1788 , n1789 );
xor ( n1791 , n1788 , n1789 );
xor ( n1792 , n1558 , n1588 );
nor ( n1793 , n795 , n1773 );
and ( n1794 , n1792 , n1793 );
xor ( n1795 , n1792 , n1793 );
xor ( n1796 , n1562 , n1586 );
nor ( n1797 , n663 , n1773 );
and ( n1798 , n1796 , n1797 );
xor ( n1799 , n1796 , n1797 );
xor ( n1800 , n1566 , n1584 );
nor ( n1801 , n549 , n1773 );
and ( n1802 , n1800 , n1801 );
xor ( n1803 , n1800 , n1801 );
xor ( n1804 , n1570 , n1582 );
nor ( n1805 , n456 , n1773 );
and ( n1806 , n1804 , n1805 );
xor ( n1807 , n1804 , n1805 );
xor ( n1808 , n1575 , n1580 );
nor ( n1809 , n384 , n1773 );
and ( n1810 , n1808 , n1809 );
xor ( n1811 , n1808 , n1809 );
xor ( n1812 , n1577 , n1578 );
buf ( n1813 , n1812 );
nor ( n1814 , n334 , n1773 );
and ( n1815 , n1813 , n1814 );
xor ( n1816 , n1813 , n1814 );
nor ( n1817 , n283 , n1536 );
buf ( n1818 , n1817 );
nor ( n1819 , n303 , n1773 );
and ( n1820 , n1818 , n1819 );
buf ( n1821 , n1820 );
and ( n1822 , n1816 , n1821 );
or ( n1823 , n1815 , n1822 );
and ( n1824 , n1811 , n1823 );
or ( n1825 , n1810 , n1824 );
and ( n1826 , n1807 , n1825 );
or ( n1827 , n1806 , n1826 );
and ( n1828 , n1803 , n1827 );
or ( n1829 , n1802 , n1828 );
and ( n1830 , n1799 , n1829 );
or ( n1831 , n1798 , n1830 );
and ( n1832 , n1795 , n1831 );
or ( n1833 , n1794 , n1832 );
and ( n1834 , n1791 , n1833 );
or ( n1835 , n1790 , n1834 );
and ( n1836 , n1787 , n1835 );
or ( n1837 , n1786 , n1836 );
and ( n1838 , n1783 , n1837 );
or ( n1839 , n1782 , n1838 );
and ( n1840 , n1779 , n1839 );
or ( n1841 , n1778 , n1840 );
xor ( n1842 , n1775 , n1841 );
and ( n1843 , n1610 , n1734 );
and ( n1844 , n1734 , n1757 );
and ( n1845 , n1610 , n1757 );
or ( n1846 , n1843 , n1844 , n1845 );
and ( n1847 , n1614 , n1629 );
and ( n1848 , n1629 , n1733 );
and ( n1849 , n1614 , n1733 );
or ( n1850 , n1847 , n1848 , n1849 );
and ( n1851 , n1618 , n1622 );
and ( n1852 , n1622 , n1628 );
and ( n1853 , n1618 , n1628 );
or ( n1854 , n1851 , n1852 , n1853 );
and ( n1855 , n1746 , n1751 );
and ( n1856 , n1751 , n1755 );
and ( n1857 , n1746 , n1755 );
or ( n1858 , n1855 , n1856 , n1857 );
xor ( n1859 , n1854 , n1858 );
and ( n1860 , n1747 , n1748 );
and ( n1861 , n1748 , n1750 );
and ( n1862 , n1747 , n1750 );
or ( n1863 , n1860 , n1861 , n1862 );
buf ( n1864 , n228 );
and ( n1865 , n277 , n1864 );
buf ( n1866 , n1865 );
and ( n1867 , n298 , n1753 );
xor ( n1868 , n1866 , n1867 );
xor ( n1869 , n1863 , n1868 );
and ( n1870 , n328 , n1396 );
and ( n1871 , n371 , n1302 );
xor ( n1872 , n1870 , n1871 );
and ( n1873 , n446 , n1114 );
xor ( n1874 , n1872 , n1873 );
xor ( n1875 , n1869 , n1874 );
xor ( n1876 , n1859 , n1875 );
xor ( n1877 , n1850 , n1876 );
and ( n1878 , n1634 , n1639 );
and ( n1879 , n1639 , n1732 );
and ( n1880 , n1634 , n1732 );
or ( n1881 , n1878 , n1879 , n1880 );
and ( n1882 , n1624 , n1625 );
and ( n1883 , n1625 , n1627 );
and ( n1884 , n1624 , n1627 );
or ( n1885 , n1882 , n1883 , n1884 );
and ( n1886 , n1635 , n1636 );
and ( n1887 , n1636 , n1638 );
and ( n1888 , n1635 , n1638 );
or ( n1889 , n1886 , n1887 , n1888 );
xor ( n1890 , n1885 , n1889 );
and ( n1891 , n533 , n852 );
and ( n1892 , n636 , n714 );
xor ( n1893 , n1891 , n1892 );
and ( n1894 , n782 , n651 );
xor ( n1895 , n1893 , n1894 );
xor ( n1896 , n1890 , n1895 );
xor ( n1897 , n1881 , n1896 );
and ( n1898 , n1641 , n1642 );
and ( n1899 , n1642 , n1731 );
and ( n1900 , n1641 , n1731 );
or ( n1901 , n1898 , n1899 , n1900 );
and ( n1902 , n931 , n488 );
and ( n1903 , n1088 , n411 );
xor ( n1904 , n1902 , n1903 );
and ( n1905 , n1292 , n375 );
xor ( n1906 , n1904 , n1905 );
xor ( n1907 , n1901 , n1906 );
and ( n1908 , n1516 , n312 );
and ( n1909 , n1730 , n288 );
xor ( n1910 , n1908 , n1909 );
and ( n1911 , n1656 , n1691 );
and ( n1912 , n1691 , n1717 );
and ( n1913 , n1656 , n1717 );
or ( n1914 , n1911 , n1912 , n1913 );
and ( n1915 , n1660 , n1675 );
and ( n1916 , n1675 , n1690 );
and ( n1917 , n1660 , n1690 );
or ( n1918 , n1915 , n1916 , n1917 );
and ( n1919 , n1664 , n1668 );
and ( n1920 , n1668 , n1674 );
and ( n1921 , n1664 , n1674 );
or ( n1922 , n1919 , n1920 , n1921 );
and ( n1923 , n1705 , n1710 );
and ( n1924 , n1710 , n1715 );
and ( n1925 , n1705 , n1715 );
or ( n1926 , n1923 , n1924 , n1925 );
xor ( n1927 , n1922 , n1926 );
and ( n1928 , n1706 , n1707 );
and ( n1929 , n1707 , n1709 );
and ( n1930 , n1706 , n1709 );
or ( n1931 , n1928 , n1929 , n1930 );
and ( n1932 , n1458 , n321 );
and ( n1933 , n1713 , n291 );
xor ( n1934 , n1932 , n1933 );
buf ( n1935 , n212 );
and ( n1936 , n1935 , n274 );
xor ( n1937 , n1934 , n1936 );
xor ( n1938 , n1931 , n1937 );
and ( n1939 , n917 , n510 );
and ( n1940 , n1077 , n435 );
xor ( n1941 , n1939 , n1940 );
and ( n1942 , n1277 , n354 );
xor ( n1943 , n1941 , n1942 );
xor ( n1944 , n1938 , n1943 );
xor ( n1945 , n1927 , n1944 );
xor ( n1946 , n1918 , n1945 );
and ( n1947 , n1678 , n1683 );
and ( n1948 , n1683 , n1689 );
and ( n1949 , n1678 , n1689 );
or ( n1950 , n1947 , n1948 , n1949 );
and ( n1951 , n1670 , n1671 );
and ( n1952 , n1671 , n1673 );
and ( n1953 , n1670 , n1673 );
or ( n1954 , n1951 , n1952 , n1953 );
and ( n1955 , n1679 , n1680 );
and ( n1956 , n1680 , n1682 );
and ( n1957 , n1679 , n1682 );
or ( n1958 , n1955 , n1956 , n1957 );
xor ( n1959 , n1954 , n1958 );
and ( n1960 , n521 , n905 );
and ( n1961 , n625 , n766 );
xor ( n1962 , n1960 , n1961 );
and ( n1963 , n753 , n607 );
xor ( n1964 , n1962 , n1963 );
xor ( n1965 , n1959 , n1964 );
xor ( n1966 , n1950 , n1965 );
and ( n1967 , n1686 , n1688 );
buf ( n1968 , n1967 );
and ( n1969 , n318 , n1497 );
and ( n1970 , n361 , n1261 );
xor ( n1971 , n1969 , n1970 );
and ( n1972 , n431 , n1048 );
xor ( n1973 , n1971 , n1972 );
xor ( n1974 , n1968 , n1973 );
buf ( n1975 , n243 );
and ( n1976 , n273 , n1975 );
buf ( n1977 , n1976 );
and ( n1978 , n294 , n1685 );
xor ( n1979 , n1977 , n1978 );
xor ( n1980 , n1974 , n1979 );
xor ( n1981 , n1966 , n1980 );
xor ( n1982 , n1946 , n1981 );
xor ( n1983 , n1914 , n1982 );
and ( n1984 , n1712 , n1714 );
and ( n1985 , n1696 , n1700 );
and ( n1986 , n1700 , n1716 );
and ( n1987 , n1696 , n1716 );
or ( n1988 , n1985 , n1986 , n1987 );
xor ( n1989 , n1984 , n1988 );
xor ( n1990 , n1983 , n1989 );
and ( n1991 , n1647 , n1651 );
and ( n1992 , n1651 , n1718 );
and ( n1993 , n1647 , n1718 );
or ( n1994 , n1991 , n1992 , n1993 );
xor ( n1995 , n1990 , n1994 );
and ( n1996 , n1719 , n1723 );
and ( n1997 , n1724 , n1727 );
or ( n1998 , n1996 , n1997 );
xor ( n1999 , n1995 , n1998 );
buf ( n2000 , n1999 );
buf ( n2001 , n2000 );
and ( n2002 , n2001 , n279 );
xor ( n2003 , n1910 , n2002 );
xor ( n2004 , n1907 , n2003 );
xor ( n2005 , n1897 , n2004 );
xor ( n2006 , n1877 , n2005 );
xor ( n2007 , n1846 , n2006 );
and ( n2008 , n1737 , n1741 );
and ( n2009 , n1741 , n1756 );
and ( n2010 , n1737 , n1756 );
or ( n2011 , n2008 , n2009 , n2010 );
buf ( n2012 , n2011 );
xor ( n2013 , n2007 , n2012 );
and ( n2014 , n1601 , n1605 );
and ( n2015 , n1605 , n1758 );
and ( n2016 , n1601 , n1758 );
or ( n2017 , n2014 , n2015 , n2016 );
xor ( n2018 , n2013 , n2017 );
and ( n2019 , n1759 , n1763 );
and ( n2020 , n1764 , n1767 );
or ( n2021 , n2019 , n2020 );
xor ( n2022 , n2018 , n2021 );
buf ( n2023 , n2022 );
buf ( n2024 , n2023 );
not ( n2025 , n2024 );
buf ( n2026 , n208 );
not ( n2027 , n2026 );
nor ( n2028 , n2025 , n2027 );
xor ( n2029 , n1842 , n2028 );
xor ( n2030 , n1779 , n1839 );
nor ( n2031 , n1771 , n2027 );
and ( n2032 , n2030 , n2031 );
xor ( n2033 , n2030 , n2031 );
xor ( n2034 , n1783 , n1837 );
nor ( n2035 , n1534 , n2027 );
and ( n2036 , n2034 , n2035 );
xor ( n2037 , n2034 , n2035 );
xor ( n2038 , n1787 , n1835 );
nor ( n2039 , n1318 , n2027 );
and ( n2040 , n2038 , n2039 );
xor ( n2041 , n2038 , n2039 );
xor ( n2042 , n1791 , n1833 );
nor ( n2043 , n1126 , n2027 );
and ( n2044 , n2042 , n2043 );
xor ( n2045 , n2042 , n2043 );
xor ( n2046 , n1795 , n1831 );
nor ( n2047 , n952 , n2027 );
and ( n2048 , n2046 , n2047 );
xor ( n2049 , n2046 , n2047 );
xor ( n2050 , n1799 , n1829 );
nor ( n2051 , n795 , n2027 );
and ( n2052 , n2050 , n2051 );
xor ( n2053 , n2050 , n2051 );
xor ( n2054 , n1803 , n1827 );
nor ( n2055 , n663 , n2027 );
and ( n2056 , n2054 , n2055 );
xor ( n2057 , n2054 , n2055 );
xor ( n2058 , n1807 , n1825 );
nor ( n2059 , n549 , n2027 );
and ( n2060 , n2058 , n2059 );
xor ( n2061 , n2058 , n2059 );
xor ( n2062 , n1811 , n1823 );
nor ( n2063 , n456 , n2027 );
and ( n2064 , n2062 , n2063 );
xor ( n2065 , n2062 , n2063 );
xor ( n2066 , n1816 , n1821 );
nor ( n2067 , n384 , n2027 );
and ( n2068 , n2066 , n2067 );
xor ( n2069 , n2066 , n2067 );
xor ( n2070 , n1818 , n1819 );
buf ( n2071 , n2070 );
nor ( n2072 , n334 , n2027 );
and ( n2073 , n2071 , n2072 );
xor ( n2074 , n2071 , n2072 );
nor ( n2075 , n283 , n1773 );
buf ( n2076 , n2075 );
nor ( n2077 , n303 , n2027 );
and ( n2078 , n2076 , n2077 );
buf ( n2079 , n2078 );
and ( n2080 , n2074 , n2079 );
or ( n2081 , n2073 , n2080 );
and ( n2082 , n2069 , n2081 );
or ( n2083 , n2068 , n2082 );
and ( n2084 , n2065 , n2083 );
or ( n2085 , n2064 , n2084 );
and ( n2086 , n2061 , n2085 );
or ( n2087 , n2060 , n2086 );
and ( n2088 , n2057 , n2087 );
or ( n2089 , n2056 , n2088 );
and ( n2090 , n2053 , n2089 );
or ( n2091 , n2052 , n2090 );
and ( n2092 , n2049 , n2091 );
or ( n2093 , n2048 , n2092 );
and ( n2094 , n2045 , n2093 );
or ( n2095 , n2044 , n2094 );
and ( n2096 , n2041 , n2095 );
or ( n2097 , n2040 , n2096 );
and ( n2098 , n2037 , n2097 );
or ( n2099 , n2036 , n2098 );
and ( n2100 , n2033 , n2099 );
or ( n2101 , n2032 , n2100 );
xor ( n2102 , n2029 , n2101 );
and ( n2103 , n1846 , n2006 );
and ( n2104 , n2006 , n2012 );
and ( n2105 , n1846 , n2012 );
or ( n2106 , n2103 , n2104 , n2105 );
buf ( n2107 , n2106 );
and ( n2108 , n1850 , n1876 );
and ( n2109 , n1876 , n2005 );
and ( n2110 , n1850 , n2005 );
or ( n2111 , n2108 , n2109 , n2110 );
and ( n2112 , n1865 , n1867 );
buf ( n2113 , n2112 );
and ( n2114 , n1854 , n1858 );
and ( n2115 , n1858 , n1875 );
and ( n2116 , n1854 , n1875 );
or ( n2117 , n2114 , n2115 , n2116 );
xor ( n2118 , n2113 , n2117 );
buf ( n2119 , n2118 );
xor ( n2120 , n2111 , n2119 );
and ( n2121 , n1881 , n1896 );
and ( n2122 , n1896 , n2004 );
and ( n2123 , n1881 , n2004 );
or ( n2124 , n2121 , n2122 , n2123 );
and ( n2125 , n1863 , n1868 );
and ( n2126 , n1868 , n1874 );
and ( n2127 , n1863 , n1874 );
or ( n2128 , n2125 , n2126 , n2127 );
and ( n2129 , n1885 , n1889 );
and ( n2130 , n1889 , n1895 );
and ( n2131 , n1885 , n1895 );
or ( n2132 , n2129 , n2130 , n2131 );
xor ( n2133 , n2128 , n2132 );
and ( n2134 , n1870 , n1871 );
and ( n2135 , n1871 , n1873 );
and ( n2136 , n1870 , n1873 );
or ( n2137 , n2134 , n2135 , n2136 );
buf ( n2138 , n227 );
and ( n2139 , n277 , n2138 );
and ( n2140 , n298 , n1864 );
xor ( n2141 , n2139 , n2140 );
and ( n2142 , n328 , n1753 );
xor ( n2143 , n2141 , n2142 );
xor ( n2144 , n2137 , n2143 );
and ( n2145 , n371 , n1396 );
and ( n2146 , n446 , n1302 );
xor ( n2147 , n2145 , n2146 );
and ( n2148 , n533 , n1114 );
xor ( n2149 , n2147 , n2148 );
xor ( n2150 , n2144 , n2149 );
xor ( n2151 , n2133 , n2150 );
xor ( n2152 , n2124 , n2151 );
and ( n2153 , n1901 , n1906 );
and ( n2154 , n1906 , n2003 );
and ( n2155 , n1901 , n2003 );
or ( n2156 , n2153 , n2154 , n2155 );
and ( n2157 , n1891 , n1892 );
and ( n2158 , n1892 , n1894 );
and ( n2159 , n1891 , n1894 );
or ( n2160 , n2157 , n2158 , n2159 );
and ( n2161 , n1902 , n1903 );
and ( n2162 , n1903 , n1905 );
and ( n2163 , n1902 , n1905 );
or ( n2164 , n2161 , n2162 , n2163 );
xor ( n2165 , n2160 , n2164 );
and ( n2166 , n636 , n852 );
and ( n2167 , n782 , n714 );
xor ( n2168 , n2166 , n2167 );
and ( n2169 , n931 , n651 );
xor ( n2170 , n2168 , n2169 );
xor ( n2171 , n2165 , n2170 );
xor ( n2172 , n2156 , n2171 );
and ( n2173 , n1908 , n1909 );
and ( n2174 , n1909 , n2002 );
and ( n2175 , n1908 , n2002 );
or ( n2176 , n2173 , n2174 , n2175 );
and ( n2177 , n1088 , n488 );
and ( n2178 , n1292 , n411 );
xor ( n2179 , n2177 , n2178 );
and ( n2180 , n1516 , n375 );
xor ( n2181 , n2179 , n2180 );
xor ( n2182 , n2176 , n2181 );
and ( n2183 , n1730 , n312 );
and ( n2184 , n2001 , n288 );
xor ( n2185 , n2183 , n2184 );
and ( n2186 , n1984 , n1988 );
and ( n2187 , n1914 , n1982 );
and ( n2188 , n1982 , n1989 );
and ( n2189 , n1914 , n1989 );
or ( n2190 , n2187 , n2188 , n2189 );
xor ( n2191 , n2186 , n2190 );
and ( n2192 , n1918 , n1945 );
and ( n2193 , n1945 , n1981 );
and ( n2194 , n1918 , n1981 );
or ( n2195 , n2192 , n2193 , n2194 );
and ( n2196 , n1932 , n1933 );
and ( n2197 , n1933 , n1936 );
and ( n2198 , n1932 , n1936 );
or ( n2199 , n2196 , n2197 , n2198 );
and ( n2200 , n1922 , n1926 );
and ( n2201 , n1926 , n1944 );
and ( n2202 , n1922 , n1944 );
or ( n2203 , n2200 , n2201 , n2202 );
xor ( n2204 , n2199 , n2203 );
buf ( n2205 , n211 );
not ( n2206 , n2205 );
and ( n2207 , n2206 , n274 );
not ( n2208 , n274 );
nor ( n2209 , n2207 , n2208 );
xor ( n2210 , n2204 , n2209 );
xor ( n2211 , n2195 , n2210 );
and ( n2212 , n1950 , n1965 );
and ( n2213 , n1965 , n1980 );
and ( n2214 , n1950 , n1980 );
or ( n2215 , n2212 , n2213 , n2214 );
and ( n2216 , n1931 , n1937 );
and ( n2217 , n1937 , n1943 );
and ( n2218 , n1931 , n1943 );
or ( n2219 , n2216 , n2217 , n2218 );
and ( n2220 , n1954 , n1958 );
and ( n2221 , n1958 , n1964 );
and ( n2222 , n1954 , n1964 );
or ( n2223 , n2220 , n2221 , n2222 );
xor ( n2224 , n2219 , n2223 );
and ( n2225 , n1939 , n1940 );
and ( n2226 , n1940 , n1942 );
and ( n2227 , n1939 , n1942 );
or ( n2228 , n2225 , n2226 , n2227 );
and ( n2229 , n1458 , n354 );
and ( n2230 , n1713 , n321 );
xor ( n2231 , n2229 , n2230 );
and ( n2232 , n1935 , n291 );
xor ( n2233 , n2231 , n2232 );
xor ( n2234 , n2228 , n2233 );
and ( n2235 , n917 , n607 );
and ( n2236 , n1077 , n510 );
xor ( n2237 , n2235 , n2236 );
and ( n2238 , n1277 , n435 );
xor ( n2239 , n2237 , n2238 );
xor ( n2240 , n2234 , n2239 );
xor ( n2241 , n2224 , n2240 );
xor ( n2242 , n2215 , n2241 );
and ( n2243 , n1968 , n1973 );
and ( n2244 , n1973 , n1979 );
and ( n2245 , n1968 , n1979 );
or ( n2246 , n2243 , n2244 , n2245 );
and ( n2247 , n1960 , n1961 );
and ( n2248 , n1961 , n1963 );
and ( n2249 , n1960 , n1963 );
or ( n2250 , n2247 , n2248 , n2249 );
and ( n2251 , n1969 , n1970 );
and ( n2252 , n1970 , n1972 );
and ( n2253 , n1969 , n1972 );
or ( n2254 , n2251 , n2252 , n2253 );
xor ( n2255 , n2250 , n2254 );
and ( n2256 , n521 , n1048 );
and ( n2257 , n625 , n905 );
xor ( n2258 , n2256 , n2257 );
and ( n2259 , n753 , n766 );
xor ( n2260 , n2258 , n2259 );
xor ( n2261 , n2255 , n2260 );
xor ( n2262 , n2246 , n2261 );
and ( n2263 , n1976 , n1978 );
buf ( n2264 , n2263 );
and ( n2265 , n318 , n1685 );
and ( n2266 , n361 , n1497 );
xor ( n2267 , n2265 , n2266 );
and ( n2268 , n431 , n1261 );
xor ( n2269 , n2267 , n2268 );
xor ( n2270 , n2264 , n2269 );
buf ( n2271 , n242 );
and ( n2272 , n273 , n2271 );
buf ( n2273 , n2272 );
and ( n2274 , n294 , n1975 );
xor ( n2275 , n2273 , n2274 );
xor ( n2276 , n2270 , n2275 );
xor ( n2277 , n2262 , n2276 );
xor ( n2278 , n2242 , n2277 );
xor ( n2279 , n2211 , n2278 );
xor ( n2280 , n2191 , n2279 );
and ( n2281 , n1990 , n1994 );
and ( n2282 , n1995 , n1998 );
or ( n2283 , n2281 , n2282 );
xor ( n2284 , n2280 , n2283 );
buf ( n2285 , n2284 );
buf ( n2286 , n2285 );
and ( n2287 , n2286 , n279 );
xor ( n2288 , n2185 , n2287 );
xor ( n2289 , n2182 , n2288 );
xor ( n2290 , n2172 , n2289 );
xor ( n2291 , n2152 , n2290 );
xor ( n2292 , n2120 , n2291 );
xor ( n2293 , n2107 , n2292 );
and ( n2294 , n2013 , n2017 );
and ( n2295 , n2018 , n2021 );
or ( n2296 , n2294 , n2295 );
xor ( n2297 , n2293 , n2296 );
buf ( n2298 , n2297 );
buf ( n2299 , n2298 );
not ( n2300 , n2299 );
buf ( n2301 , n209 );
not ( n2302 , n2301 );
nor ( n2303 , n2300 , n2302 );
xor ( n2304 , n2102 , n2303 );
xor ( n2305 , n2033 , n2099 );
nor ( n2306 , n2025 , n2302 );
and ( n2307 , n2305 , n2306 );
xor ( n2308 , n2305 , n2306 );
xor ( n2309 , n2037 , n2097 );
nor ( n2310 , n1771 , n2302 );
and ( n2311 , n2309 , n2310 );
xor ( n2312 , n2309 , n2310 );
xor ( n2313 , n2041 , n2095 );
nor ( n2314 , n1534 , n2302 );
and ( n2315 , n2313 , n2314 );
xor ( n2316 , n2313 , n2314 );
xor ( n2317 , n2045 , n2093 );
nor ( n2318 , n1318 , n2302 );
and ( n2319 , n2317 , n2318 );
xor ( n2320 , n2317 , n2318 );
xor ( n2321 , n2049 , n2091 );
nor ( n2322 , n1126 , n2302 );
and ( n2323 , n2321 , n2322 );
xor ( n2324 , n2321 , n2322 );
xor ( n2325 , n2053 , n2089 );
nor ( n2326 , n952 , n2302 );
and ( n2327 , n2325 , n2326 );
xor ( n2328 , n2325 , n2326 );
xor ( n2329 , n2057 , n2087 );
nor ( n2330 , n795 , n2302 );
and ( n2331 , n2329 , n2330 );
xor ( n2332 , n2329 , n2330 );
xor ( n2333 , n2061 , n2085 );
nor ( n2334 , n663 , n2302 );
and ( n2335 , n2333 , n2334 );
xor ( n2336 , n2333 , n2334 );
xor ( n2337 , n2065 , n2083 );
nor ( n2338 , n549 , n2302 );
and ( n2339 , n2337 , n2338 );
xor ( n2340 , n2337 , n2338 );
xor ( n2341 , n2069 , n2081 );
nor ( n2342 , n456 , n2302 );
and ( n2343 , n2341 , n2342 );
xor ( n2344 , n2341 , n2342 );
xor ( n2345 , n2074 , n2079 );
nor ( n2346 , n384 , n2302 );
and ( n2347 , n2345 , n2346 );
xor ( n2348 , n2345 , n2346 );
xor ( n2349 , n2076 , n2077 );
buf ( n2350 , n2349 );
nor ( n2351 , n334 , n2302 );
and ( n2352 , n2350 , n2351 );
xor ( n2353 , n2350 , n2351 );
nor ( n2354 , n283 , n2027 );
buf ( n2355 , n2354 );
nor ( n2356 , n303 , n2302 );
and ( n2357 , n2355 , n2356 );
buf ( n2358 , n2357 );
and ( n2359 , n2353 , n2358 );
or ( n2360 , n2352 , n2359 );
and ( n2361 , n2348 , n2360 );
or ( n2362 , n2347 , n2361 );
and ( n2363 , n2344 , n2362 );
or ( n2364 , n2343 , n2363 );
and ( n2365 , n2340 , n2364 );
or ( n2366 , n2339 , n2365 );
and ( n2367 , n2336 , n2366 );
or ( n2368 , n2335 , n2367 );
and ( n2369 , n2332 , n2368 );
or ( n2370 , n2331 , n2369 );
and ( n2371 , n2328 , n2370 );
or ( n2372 , n2327 , n2371 );
and ( n2373 , n2324 , n2372 );
or ( n2374 , n2323 , n2373 );
and ( n2375 , n2320 , n2374 );
or ( n2376 , n2319 , n2375 );
and ( n2377 , n2316 , n2376 );
or ( n2378 , n2315 , n2377 );
and ( n2379 , n2312 , n2378 );
or ( n2380 , n2311 , n2379 );
and ( n2381 , n2308 , n2380 );
or ( n2382 , n2307 , n2381 );
xor ( n2383 , n2304 , n2382 );
and ( n2384 , n2113 , n2117 );
buf ( n2385 , n2384 );
and ( n2386 , n2111 , n2119 );
and ( n2387 , n2119 , n2291 );
and ( n2388 , n2111 , n2291 );
or ( n2389 , n2386 , n2387 , n2388 );
xor ( n2390 , n2385 , n2389 );
and ( n2391 , n2124 , n2151 );
and ( n2392 , n2151 , n2290 );
and ( n2393 , n2124 , n2290 );
or ( n2394 , n2391 , n2392 , n2393 );
and ( n2395 , n2139 , n2140 );
and ( n2396 , n2140 , n2142 );
and ( n2397 , n2139 , n2142 );
or ( n2398 , n2395 , n2396 , n2397 );
and ( n2399 , n2128 , n2132 );
and ( n2400 , n2132 , n2150 );
and ( n2401 , n2128 , n2150 );
or ( n2402 , n2399 , n2400 , n2401 );
xor ( n2403 , n2398 , n2402 );
not ( n2404 , n277 );
buf ( n2405 , n226 );
not ( n2406 , n2405 );
and ( n2407 , n2406 , n277 );
nor ( n2408 , n2404 , n2407 );
xor ( n2409 , n2403 , n2408 );
xor ( n2410 , n2394 , n2409 );
and ( n2411 , n2156 , n2171 );
and ( n2412 , n2171 , n2289 );
and ( n2413 , n2156 , n2289 );
or ( n2414 , n2411 , n2412 , n2413 );
and ( n2415 , n2137 , n2143 );
and ( n2416 , n2143 , n2149 );
and ( n2417 , n2137 , n2149 );
or ( n2418 , n2415 , n2416 , n2417 );
and ( n2419 , n2160 , n2164 );
and ( n2420 , n2164 , n2170 );
and ( n2421 , n2160 , n2170 );
or ( n2422 , n2419 , n2420 , n2421 );
xor ( n2423 , n2418 , n2422 );
and ( n2424 , n2145 , n2146 );
and ( n2425 , n2146 , n2148 );
and ( n2426 , n2145 , n2148 );
or ( n2427 , n2424 , n2425 , n2426 );
and ( n2428 , n298 , n2138 );
and ( n2429 , n328 , n1864 );
xor ( n2430 , n2428 , n2429 );
and ( n2431 , n371 , n1753 );
xor ( n2432 , n2430 , n2431 );
xor ( n2433 , n2427 , n2432 );
and ( n2434 , n446 , n1396 );
and ( n2435 , n533 , n1302 );
xor ( n2436 , n2434 , n2435 );
and ( n2437 , n636 , n1114 );
xor ( n2438 , n2436 , n2437 );
xor ( n2439 , n2433 , n2438 );
xor ( n2440 , n2423 , n2439 );
xor ( n2441 , n2414 , n2440 );
and ( n2442 , n2176 , n2181 );
and ( n2443 , n2181 , n2288 );
and ( n2444 , n2176 , n2288 );
or ( n2445 , n2442 , n2443 , n2444 );
and ( n2446 , n2166 , n2167 );
and ( n2447 , n2167 , n2169 );
and ( n2448 , n2166 , n2169 );
or ( n2449 , n2446 , n2447 , n2448 );
and ( n2450 , n2177 , n2178 );
and ( n2451 , n2178 , n2180 );
and ( n2452 , n2177 , n2180 );
or ( n2453 , n2450 , n2451 , n2452 );
xor ( n2454 , n2449 , n2453 );
and ( n2455 , n782 , n852 );
and ( n2456 , n931 , n714 );
xor ( n2457 , n2455 , n2456 );
and ( n2458 , n1088 , n651 );
xor ( n2459 , n2457 , n2458 );
xor ( n2460 , n2454 , n2459 );
xor ( n2461 , n2445 , n2460 );
and ( n2462 , n2183 , n2184 );
and ( n2463 , n2184 , n2287 );
and ( n2464 , n2183 , n2287 );
or ( n2465 , n2462 , n2463 , n2464 );
and ( n2466 , n1292 , n488 );
and ( n2467 , n1516 , n411 );
xor ( n2468 , n2466 , n2467 );
and ( n2469 , n1730 , n375 );
xor ( n2470 , n2468 , n2469 );
xor ( n2471 , n2465 , n2470 );
and ( n2472 , n2001 , n312 );
and ( n2473 , n2286 , n288 );
xor ( n2474 , n2472 , n2473 );
and ( n2475 , n2199 , n2203 );
and ( n2476 , n2203 , n2209 );
and ( n2477 , n2199 , n2209 );
or ( n2478 , n2475 , n2476 , n2477 );
and ( n2479 , n2195 , n2210 );
and ( n2480 , n2210 , n2278 );
and ( n2481 , n2195 , n2278 );
or ( n2482 , n2479 , n2480 , n2481 );
xor ( n2483 , n2478 , n2482 );
and ( n2484 , n2215 , n2241 );
and ( n2485 , n2241 , n2277 );
and ( n2486 , n2215 , n2277 );
or ( n2487 , n2484 , n2485 , n2486 );
and ( n2488 , n2229 , n2230 );
and ( n2489 , n2230 , n2232 );
and ( n2490 , n2229 , n2232 );
or ( n2491 , n2488 , n2489 , n2490 );
and ( n2492 , n2219 , n2223 );
and ( n2493 , n2223 , n2240 );
and ( n2494 , n2219 , n2240 );
or ( n2495 , n2492 , n2493 , n2494 );
xor ( n2496 , n2491 , n2495 );
and ( n2497 , n2206 , n291 );
not ( n2498 , n291 );
nor ( n2499 , n2497 , n2498 );
xor ( n2500 , n2496 , n2499 );
xor ( n2501 , n2487 , n2500 );
and ( n2502 , n2246 , n2261 );
and ( n2503 , n2261 , n2276 );
and ( n2504 , n2246 , n2276 );
or ( n2505 , n2502 , n2503 , n2504 );
and ( n2506 , n2228 , n2233 );
and ( n2507 , n2233 , n2239 );
and ( n2508 , n2228 , n2239 );
or ( n2509 , n2506 , n2507 , n2508 );
and ( n2510 , n2250 , n2254 );
and ( n2511 , n2254 , n2260 );
and ( n2512 , n2250 , n2260 );
or ( n2513 , n2510 , n2511 , n2512 );
xor ( n2514 , n2509 , n2513 );
and ( n2515 , n2235 , n2236 );
and ( n2516 , n2236 , n2238 );
and ( n2517 , n2235 , n2238 );
or ( n2518 , n2515 , n2516 , n2517 );
and ( n2519 , n1458 , n435 );
and ( n2520 , n1713 , n354 );
xor ( n2521 , n2519 , n2520 );
and ( n2522 , n1935 , n321 );
xor ( n2523 , n2521 , n2522 );
xor ( n2524 , n2518 , n2523 );
and ( n2525 , n917 , n766 );
and ( n2526 , n1077 , n607 );
xor ( n2527 , n2525 , n2526 );
and ( n2528 , n1277 , n510 );
xor ( n2529 , n2527 , n2528 );
xor ( n2530 , n2524 , n2529 );
xor ( n2531 , n2514 , n2530 );
xor ( n2532 , n2505 , n2531 );
and ( n2533 , n2264 , n2269 );
and ( n2534 , n2269 , n2275 );
and ( n2535 , n2264 , n2275 );
or ( n2536 , n2533 , n2534 , n2535 );
and ( n2537 , n2256 , n2257 );
and ( n2538 , n2257 , n2259 );
and ( n2539 , n2256 , n2259 );
or ( n2540 , n2537 , n2538 , n2539 );
and ( n2541 , n2265 , n2266 );
and ( n2542 , n2266 , n2268 );
and ( n2543 , n2265 , n2268 );
or ( n2544 , n2541 , n2542 , n2543 );
xor ( n2545 , n2540 , n2544 );
and ( n2546 , n521 , n1261 );
and ( n2547 , n625 , n1048 );
xor ( n2548 , n2546 , n2547 );
and ( n2549 , n753 , n905 );
xor ( n2550 , n2548 , n2549 );
xor ( n2551 , n2545 , n2550 );
xor ( n2552 , n2536 , n2551 );
and ( n2553 , n2272 , n2274 );
buf ( n2554 , n2553 );
and ( n2555 , n318 , n1975 );
and ( n2556 , n361 , n1685 );
xor ( n2557 , n2555 , n2556 );
and ( n2558 , n431 , n1497 );
xor ( n2559 , n2557 , n2558 );
xor ( n2560 , n2554 , n2559 );
not ( n2561 , n273 );
buf ( n2562 , n241 );
not ( n2563 , n2562 );
and ( n2564 , n2563 , n273 );
nor ( n2565 , n2561 , n2564 );
and ( n2566 , n294 , n2271 );
xor ( n2567 , n2565 , n2566 );
xor ( n2568 , n2560 , n2567 );
xor ( n2569 , n2552 , n2568 );
xor ( n2570 , n2532 , n2569 );
xor ( n2571 , n2501 , n2570 );
xor ( n2572 , n2483 , n2571 );
and ( n2573 , n2186 , n2190 );
and ( n2574 , n2190 , n2279 );
and ( n2575 , n2186 , n2279 );
or ( n2576 , n2573 , n2574 , n2575 );
xor ( n2577 , n2572 , n2576 );
and ( n2578 , n2280 , n2283 );
xor ( n2579 , n2577 , n2578 );
buf ( n2580 , n2579 );
buf ( n2581 , n2580 );
and ( n2582 , n2581 , n279 );
xor ( n2583 , n2474 , n2582 );
xor ( n2584 , n2471 , n2583 );
xor ( n2585 , n2461 , n2584 );
xor ( n2586 , n2441 , n2585 );
xor ( n2587 , n2410 , n2586 );
xor ( n2588 , n2390 , n2587 );
and ( n2589 , n2106 , n2292 );
buf ( n2590 , n2589 );
xor ( n2591 , n2588 , n2590 );
and ( n2592 , n2293 , n2296 );
xor ( n2593 , n2591 , n2592 );
buf ( n2594 , n2593 );
buf ( n2595 , n2594 );
not ( n2596 , n2595 );
buf ( n2597 , n210 );
not ( n2598 , n2597 );
nor ( n2599 , n2596 , n2598 );
xor ( n2600 , n2383 , n2599 );
xor ( n2601 , n2308 , n2380 );
nor ( n2602 , n2300 , n2598 );
and ( n2603 , n2601 , n2602 );
xor ( n2604 , n2601 , n2602 );
xor ( n2605 , n2312 , n2378 );
nor ( n2606 , n2025 , n2598 );
and ( n2607 , n2605 , n2606 );
xor ( n2608 , n2605 , n2606 );
xor ( n2609 , n2316 , n2376 );
nor ( n2610 , n1771 , n2598 );
and ( n2611 , n2609 , n2610 );
xor ( n2612 , n2609 , n2610 );
xor ( n2613 , n2320 , n2374 );
nor ( n2614 , n1534 , n2598 );
and ( n2615 , n2613 , n2614 );
xor ( n2616 , n2613 , n2614 );
xor ( n2617 , n2324 , n2372 );
nor ( n2618 , n1318 , n2598 );
and ( n2619 , n2617 , n2618 );
xor ( n2620 , n2617 , n2618 );
xor ( n2621 , n2328 , n2370 );
nor ( n2622 , n1126 , n2598 );
and ( n2623 , n2621 , n2622 );
xor ( n2624 , n2621 , n2622 );
xor ( n2625 , n2332 , n2368 );
nor ( n2626 , n952 , n2598 );
and ( n2627 , n2625 , n2626 );
xor ( n2628 , n2625 , n2626 );
xor ( n2629 , n2336 , n2366 );
nor ( n2630 , n795 , n2598 );
and ( n2631 , n2629 , n2630 );
xor ( n2632 , n2629 , n2630 );
xor ( n2633 , n2340 , n2364 );
nor ( n2634 , n663 , n2598 );
and ( n2635 , n2633 , n2634 );
xor ( n2636 , n2633 , n2634 );
xor ( n2637 , n2344 , n2362 );
nor ( n2638 , n549 , n2598 );
and ( n2639 , n2637 , n2638 );
xor ( n2640 , n2637 , n2638 );
xor ( n2641 , n2348 , n2360 );
nor ( n2642 , n456 , n2598 );
and ( n2643 , n2641 , n2642 );
xor ( n2644 , n2641 , n2642 );
xor ( n2645 , n2353 , n2358 );
nor ( n2646 , n384 , n2598 );
and ( n2647 , n2645 , n2646 );
xor ( n2648 , n2645 , n2646 );
xor ( n2649 , n2355 , n2356 );
buf ( n2650 , n2649 );
nor ( n2651 , n334 , n2598 );
and ( n2652 , n2650 , n2651 );
xor ( n2653 , n2650 , n2651 );
nor ( n2654 , n283 , n2302 );
buf ( n2655 , n2654 );
nor ( n2656 , n303 , n2598 );
and ( n2657 , n2655 , n2656 );
buf ( n2658 , n2657 );
and ( n2659 , n2653 , n2658 );
or ( n2660 , n2652 , n2659 );
and ( n2661 , n2648 , n2660 );
or ( n2662 , n2647 , n2661 );
and ( n2663 , n2644 , n2662 );
or ( n2664 , n2643 , n2663 );
and ( n2665 , n2640 , n2664 );
or ( n2666 , n2639 , n2665 );
and ( n2667 , n2636 , n2666 );
or ( n2668 , n2635 , n2667 );
and ( n2669 , n2632 , n2668 );
or ( n2670 , n2631 , n2669 );
and ( n2671 , n2628 , n2670 );
or ( n2672 , n2627 , n2671 );
and ( n2673 , n2624 , n2672 );
or ( n2674 , n2623 , n2673 );
and ( n2675 , n2620 , n2674 );
or ( n2676 , n2619 , n2675 );
and ( n2677 , n2616 , n2676 );
or ( n2678 , n2615 , n2677 );
and ( n2679 , n2612 , n2678 );
or ( n2680 , n2611 , n2679 );
and ( n2681 , n2608 , n2680 );
or ( n2682 , n2607 , n2681 );
and ( n2683 , n2604 , n2682 );
or ( n2684 , n2603 , n2683 );
xor ( n2685 , n2600 , n2684 );
buf ( n2686 , n2685 );
buf ( n2687 , n2686 );
not ( n2688 , n2687 );
buf ( n2689 , n257 );
not ( n2690 , n2689 );
and ( n2691 , n2690 , n2687 );
nor ( n2692 , n2688 , n2691 );
and ( n2693 , n285 , n302 );
nor ( n2694 , n303 , n2693 );
nor ( n2695 , n334 , n305 );
xor ( n2696 , n2694 , n2695 );
and ( n2697 , n287 , n306 );
buf ( n2698 , n2697 );
xor ( n2699 , n2696 , n2698 );
nor ( n2700 , n384 , n336 );
xor ( n2701 , n2699 , n2700 );
and ( n2702 , n308 , n337 );
and ( n2703 , n338 , n343 );
or ( n2704 , n2702 , n2703 );
xor ( n2705 , n2701 , n2704 );
nor ( n2706 , n456 , n386 );
xor ( n2707 , n2705 , n2706 );
and ( n2708 , n344 , n387 );
and ( n2709 , n388 , n400 );
or ( n2710 , n2708 , n2709 );
xor ( n2711 , n2707 , n2710 );
nor ( n2712 , n549 , n458 );
xor ( n2713 , n2711 , n2712 );
and ( n2714 , n401 , n459 );
and ( n2715 , n460 , n478 );
or ( n2716 , n2714 , n2715 );
xor ( n2717 , n2713 , n2716 );
nor ( n2718 , n663 , n551 );
xor ( n2719 , n2717 , n2718 );
and ( n2720 , n479 , n552 );
and ( n2721 , n553 , n577 );
or ( n2722 , n2720 , n2721 );
xor ( n2723 , n2719 , n2722 );
nor ( n2724 , n795 , n665 );
xor ( n2725 , n2723 , n2724 );
and ( n2726 , n578 , n666 );
and ( n2727 , n667 , n697 );
or ( n2728 , n2726 , n2727 );
xor ( n2729 , n2725 , n2728 );
nor ( n2730 , n952 , n797 );
xor ( n2731 , n2729 , n2730 );
and ( n2732 , n698 , n798 );
and ( n2733 , n799 , n835 );
or ( n2734 , n2732 , n2733 );
xor ( n2735 , n2731 , n2734 );
nor ( n2736 , n1126 , n954 );
xor ( n2737 , n2735 , n2736 );
and ( n2738 , n836 , n955 );
and ( n2739 , n956 , n998 );
or ( n2740 , n2738 , n2739 );
xor ( n2741 , n2737 , n2740 );
nor ( n2742 , n1318 , n1128 );
xor ( n2743 , n2741 , n2742 );
and ( n2744 , n999 , n1129 );
and ( n2745 , n1130 , n1178 );
or ( n2746 , n2744 , n2745 );
xor ( n2747 , n2743 , n2746 );
nor ( n2748 , n1534 , n1320 );
xor ( n2749 , n2747 , n2748 );
and ( n2750 , n1179 , n1321 );
and ( n2751 , n1322 , n1376 );
or ( n2752 , n2750 , n2751 );
xor ( n2753 , n2749 , n2752 );
nor ( n2754 , n1771 , n1536 );
xor ( n2755 , n2753 , n2754 );
and ( n2756 , n1377 , n1537 );
and ( n2757 , n1538 , n1598 );
or ( n2758 , n2756 , n2757 );
xor ( n2759 , n2755 , n2758 );
nor ( n2760 , n2025 , n1773 );
xor ( n2761 , n2759 , n2760 );
and ( n2762 , n1599 , n1774 );
and ( n2763 , n1775 , n1841 );
or ( n2764 , n2762 , n2763 );
xor ( n2765 , n2761 , n2764 );
nor ( n2766 , n2300 , n2027 );
xor ( n2767 , n2765 , n2766 );
and ( n2768 , n1842 , n2028 );
and ( n2769 , n2029 , n2101 );
or ( n2770 , n2768 , n2769 );
xor ( n2771 , n2767 , n2770 );
nor ( n2772 , n2596 , n2302 );
xor ( n2773 , n2771 , n2772 );
and ( n2774 , n2102 , n2303 );
and ( n2775 , n2304 , n2382 );
or ( n2776 , n2774 , n2775 );
xor ( n2777 , n2773 , n2776 );
and ( n2778 , n2398 , n2402 );
and ( n2779 , n2402 , n2408 );
and ( n2780 , n2398 , n2408 );
or ( n2781 , n2778 , n2779 , n2780 );
and ( n2782 , n2394 , n2409 );
and ( n2783 , n2409 , n2586 );
and ( n2784 , n2394 , n2586 );
or ( n2785 , n2782 , n2783 , n2784 );
xor ( n2786 , n2781 , n2785 );
and ( n2787 , n2414 , n2440 );
and ( n2788 , n2440 , n2585 );
and ( n2789 , n2414 , n2585 );
or ( n2790 , n2787 , n2788 , n2789 );
and ( n2791 , n2428 , n2429 );
and ( n2792 , n2429 , n2431 );
and ( n2793 , n2428 , n2431 );
or ( n2794 , n2791 , n2792 , n2793 );
and ( n2795 , n2418 , n2422 );
and ( n2796 , n2422 , n2439 );
and ( n2797 , n2418 , n2439 );
or ( n2798 , n2795 , n2796 , n2797 );
xor ( n2799 , n2794 , n2798 );
not ( n2800 , n298 );
and ( n2801 , n2406 , n298 );
nor ( n2802 , n2800 , n2801 );
xor ( n2803 , n2799 , n2802 );
xor ( n2804 , n2790 , n2803 );
and ( n2805 , n2445 , n2460 );
and ( n2806 , n2460 , n2584 );
and ( n2807 , n2445 , n2584 );
or ( n2808 , n2805 , n2806 , n2807 );
and ( n2809 , n2427 , n2432 );
and ( n2810 , n2432 , n2438 );
and ( n2811 , n2427 , n2438 );
or ( n2812 , n2809 , n2810 , n2811 );
and ( n2813 , n2449 , n2453 );
and ( n2814 , n2453 , n2459 );
and ( n2815 , n2449 , n2459 );
or ( n2816 , n2813 , n2814 , n2815 );
xor ( n2817 , n2812 , n2816 );
and ( n2818 , n2434 , n2435 );
and ( n2819 , n2435 , n2437 );
and ( n2820 , n2434 , n2437 );
or ( n2821 , n2818 , n2819 , n2820 );
and ( n2822 , n328 , n2138 );
and ( n2823 , n371 , n1864 );
xor ( n2824 , n2822 , n2823 );
and ( n2825 , n446 , n1753 );
xor ( n2826 , n2824 , n2825 );
xor ( n2827 , n2821 , n2826 );
and ( n2828 , n533 , n1396 );
and ( n2829 , n636 , n1302 );
xor ( n2830 , n2828 , n2829 );
and ( n2831 , n782 , n1114 );
xor ( n2832 , n2830 , n2831 );
xor ( n2833 , n2827 , n2832 );
xor ( n2834 , n2817 , n2833 );
xor ( n2835 , n2808 , n2834 );
and ( n2836 , n2465 , n2470 );
and ( n2837 , n2470 , n2583 );
and ( n2838 , n2465 , n2583 );
or ( n2839 , n2836 , n2837 , n2838 );
and ( n2840 , n2455 , n2456 );
and ( n2841 , n2456 , n2458 );
and ( n2842 , n2455 , n2458 );
or ( n2843 , n2840 , n2841 , n2842 );
and ( n2844 , n2466 , n2467 );
and ( n2845 , n2467 , n2469 );
and ( n2846 , n2466 , n2469 );
or ( n2847 , n2844 , n2845 , n2846 );
xor ( n2848 , n2843 , n2847 );
and ( n2849 , n931 , n852 );
and ( n2850 , n1088 , n714 );
xor ( n2851 , n2849 , n2850 );
and ( n2852 , n1292 , n651 );
xor ( n2853 , n2851 , n2852 );
xor ( n2854 , n2848 , n2853 );
xor ( n2855 , n2839 , n2854 );
and ( n2856 , n2472 , n2473 );
and ( n2857 , n2473 , n2582 );
and ( n2858 , n2472 , n2582 );
or ( n2859 , n2856 , n2857 , n2858 );
and ( n2860 , n1516 , n488 );
and ( n2861 , n1730 , n411 );
xor ( n2862 , n2860 , n2861 );
and ( n2863 , n2001 , n375 );
xor ( n2864 , n2862 , n2863 );
xor ( n2865 , n2859 , n2864 );
and ( n2866 , n2286 , n312 );
and ( n2867 , n2581 , n288 );
xor ( n2868 , n2866 , n2867 );
and ( n2869 , n2491 , n2495 );
and ( n2870 , n2495 , n2499 );
and ( n2871 , n2491 , n2499 );
or ( n2872 , n2869 , n2870 , n2871 );
and ( n2873 , n2487 , n2500 );
and ( n2874 , n2500 , n2570 );
and ( n2875 , n2487 , n2570 );
or ( n2876 , n2873 , n2874 , n2875 );
xor ( n2877 , n2872 , n2876 );
and ( n2878 , n2505 , n2531 );
and ( n2879 , n2531 , n2569 );
and ( n2880 , n2505 , n2569 );
or ( n2881 , n2878 , n2879 , n2880 );
and ( n2882 , n2519 , n2520 );
and ( n2883 , n2520 , n2522 );
and ( n2884 , n2519 , n2522 );
or ( n2885 , n2882 , n2883 , n2884 );
and ( n2886 , n2509 , n2513 );
and ( n2887 , n2513 , n2530 );
and ( n2888 , n2509 , n2530 );
or ( n2889 , n2886 , n2887 , n2888 );
xor ( n2890 , n2885 , n2889 );
and ( n2891 , n2206 , n321 );
not ( n2892 , n321 );
nor ( n2893 , n2891 , n2892 );
xor ( n2894 , n2890 , n2893 );
xor ( n2895 , n2881 , n2894 );
and ( n2896 , n2536 , n2551 );
and ( n2897 , n2551 , n2568 );
and ( n2898 , n2536 , n2568 );
or ( n2899 , n2896 , n2897 , n2898 );
and ( n2900 , n2518 , n2523 );
and ( n2901 , n2523 , n2529 );
and ( n2902 , n2518 , n2529 );
or ( n2903 , n2900 , n2901 , n2902 );
and ( n2904 , n2540 , n2544 );
and ( n2905 , n2544 , n2550 );
and ( n2906 , n2540 , n2550 );
or ( n2907 , n2904 , n2905 , n2906 );
xor ( n2908 , n2903 , n2907 );
and ( n2909 , n2525 , n2526 );
and ( n2910 , n2526 , n2528 );
and ( n2911 , n2525 , n2528 );
or ( n2912 , n2909 , n2910 , n2911 );
and ( n2913 , n1458 , n510 );
and ( n2914 , n1713 , n435 );
xor ( n2915 , n2913 , n2914 );
and ( n2916 , n1935 , n354 );
xor ( n2917 , n2915 , n2916 );
xor ( n2918 , n2912 , n2917 );
and ( n2919 , n917 , n905 );
and ( n2920 , n1077 , n766 );
xor ( n2921 , n2919 , n2920 );
and ( n2922 , n1277 , n607 );
xor ( n2923 , n2921 , n2922 );
xor ( n2924 , n2918 , n2923 );
xor ( n2925 , n2908 , n2924 );
xor ( n2926 , n2899 , n2925 );
and ( n2927 , n2554 , n2559 );
and ( n2928 , n2559 , n2567 );
and ( n2929 , n2554 , n2567 );
or ( n2930 , n2927 , n2928 , n2929 );
and ( n2931 , n2546 , n2547 );
and ( n2932 , n2547 , n2549 );
and ( n2933 , n2546 , n2549 );
or ( n2934 , n2931 , n2932 , n2933 );
and ( n2935 , n2555 , n2556 );
and ( n2936 , n2556 , n2558 );
and ( n2937 , n2555 , n2558 );
or ( n2938 , n2935 , n2936 , n2937 );
xor ( n2939 , n2934 , n2938 );
and ( n2940 , n521 , n1497 );
and ( n2941 , n625 , n1261 );
xor ( n2942 , n2940 , n2941 );
and ( n2943 , n753 , n1048 );
xor ( n2944 , n2942 , n2943 );
xor ( n2945 , n2939 , n2944 );
xor ( n2946 , n2930 , n2945 );
and ( n2947 , n2565 , n2566 );
not ( n2948 , n294 );
and ( n2949 , n2563 , n294 );
nor ( n2950 , n2948 , n2949 );
xor ( n2951 , n2947 , n2950 );
and ( n2952 , n318 , n2271 );
and ( n2953 , n361 , n1975 );
xor ( n2954 , n2952 , n2953 );
and ( n2955 , n431 , n1685 );
xor ( n2956 , n2954 , n2955 );
xor ( n2957 , n2951 , n2956 );
xor ( n2958 , n2946 , n2957 );
xor ( n2959 , n2926 , n2958 );
xor ( n2960 , n2895 , n2959 );
xor ( n2961 , n2877 , n2960 );
and ( n2962 , n2478 , n2482 );
and ( n2963 , n2482 , n2571 );
and ( n2964 , n2478 , n2571 );
or ( n2965 , n2962 , n2963 , n2964 );
xor ( n2966 , n2961 , n2965 );
and ( n2967 , n2572 , n2576 );
and ( n2968 , n2577 , n2578 );
or ( n2969 , n2967 , n2968 );
xor ( n2970 , n2966 , n2969 );
buf ( n2971 , n2970 );
buf ( n2972 , n2971 );
and ( n2973 , n2972 , n279 );
xor ( n2974 , n2868 , n2973 );
xor ( n2975 , n2865 , n2974 );
xor ( n2976 , n2855 , n2975 );
xor ( n2977 , n2835 , n2976 );
xor ( n2978 , n2804 , n2977 );
xor ( n2979 , n2786 , n2978 );
and ( n2980 , n2385 , n2389 );
and ( n2981 , n2389 , n2587 );
and ( n2982 , n2385 , n2587 );
or ( n2983 , n2980 , n2981 , n2982 );
xor ( n2984 , n2979 , n2983 );
and ( n2985 , n2588 , n2590 );
and ( n2986 , n2591 , n2592 );
or ( n2987 , n2985 , n2986 );
xor ( n2988 , n2984 , n2987 );
buf ( n2989 , n2988 );
buf ( n2990 , n2989 );
not ( n2991 , n2990 );
nor ( n2992 , n2991 , n2598 );
xor ( n2993 , n2777 , n2992 );
and ( n2994 , n2383 , n2599 );
and ( n2995 , n2600 , n2684 );
or ( n2996 , n2994 , n2995 );
xor ( n2997 , n2993 , n2996 );
buf ( n2998 , n2997 );
buf ( n2999 , n2998 );
not ( n3000 , n2999 );
buf ( n3001 , n258 );
not ( n3002 , n3001 );
nor ( n3003 , n3000 , n3002 );
xor ( n3004 , n2692 , n3003 );
xor ( n3005 , n2604 , n2682 );
buf ( n3006 , n3005 );
buf ( n3007 , n3006 );
not ( n3008 , n3007 );
and ( n3009 , n2690 , n3007 );
nor ( n3010 , n3008 , n3009 );
nor ( n3011 , n2688 , n3002 );
and ( n3012 , n3010 , n3011 );
xor ( n3013 , n3010 , n3011 );
xor ( n3014 , n2608 , n2680 );
buf ( n3015 , n3014 );
buf ( n3016 , n3015 );
not ( n3017 , n3016 );
and ( n3018 , n2690 , n3016 );
nor ( n3019 , n3017 , n3018 );
nor ( n3020 , n3008 , n3002 );
and ( n3021 , n3019 , n3020 );
xor ( n3022 , n3019 , n3020 );
xor ( n3023 , n2612 , n2678 );
buf ( n3024 , n3023 );
buf ( n3025 , n3024 );
not ( n3026 , n3025 );
and ( n3027 , n2690 , n3025 );
nor ( n3028 , n3026 , n3027 );
nor ( n3029 , n3017 , n3002 );
and ( n3030 , n3028 , n3029 );
xor ( n3031 , n3028 , n3029 );
xor ( n3032 , n2616 , n2676 );
buf ( n3033 , n3032 );
buf ( n3034 , n3033 );
not ( n3035 , n3034 );
and ( n3036 , n2690 , n3034 );
nor ( n3037 , n3035 , n3036 );
nor ( n3038 , n3026 , n3002 );
and ( n3039 , n3037 , n3038 );
xor ( n3040 , n3037 , n3038 );
xor ( n3041 , n2620 , n2674 );
buf ( n3042 , n3041 );
buf ( n3043 , n3042 );
not ( n3044 , n3043 );
and ( n3045 , n2690 , n3043 );
nor ( n3046 , n3044 , n3045 );
nor ( n3047 , n3035 , n3002 );
and ( n3048 , n3046 , n3047 );
xor ( n3049 , n3046 , n3047 );
xor ( n3050 , n2624 , n2672 );
buf ( n3051 , n3050 );
buf ( n3052 , n3051 );
not ( n3053 , n3052 );
and ( n3054 , n2690 , n3052 );
nor ( n3055 , n3053 , n3054 );
nor ( n3056 , n3044 , n3002 );
and ( n3057 , n3055 , n3056 );
xor ( n3058 , n3055 , n3056 );
xor ( n3059 , n2628 , n2670 );
buf ( n3060 , n3059 );
buf ( n3061 , n3060 );
not ( n3062 , n3061 );
and ( n3063 , n2690 , n3061 );
nor ( n3064 , n3062 , n3063 );
nor ( n3065 , n3053 , n3002 );
and ( n3066 , n3064 , n3065 );
xor ( n3067 , n3064 , n3065 );
xor ( n3068 , n2632 , n2668 );
buf ( n3069 , n3068 );
buf ( n3070 , n3069 );
not ( n3071 , n3070 );
and ( n3072 , n2690 , n3070 );
nor ( n3073 , n3071 , n3072 );
nor ( n3074 , n3062 , n3002 );
and ( n3075 , n3073 , n3074 );
xor ( n3076 , n3073 , n3074 );
xor ( n3077 , n2636 , n2666 );
buf ( n3078 , n3077 );
buf ( n3079 , n3078 );
not ( n3080 , n3079 );
and ( n3081 , n2690 , n3079 );
nor ( n3082 , n3080 , n3081 );
nor ( n3083 , n3071 , n3002 );
and ( n3084 , n3082 , n3083 );
xor ( n3085 , n3082 , n3083 );
xor ( n3086 , n2640 , n2664 );
buf ( n3087 , n3086 );
buf ( n3088 , n3087 );
not ( n3089 , n3088 );
and ( n3090 , n2690 , n3088 );
nor ( n3091 , n3089 , n3090 );
nor ( n3092 , n3080 , n3002 );
and ( n3093 , n3091 , n3092 );
xor ( n3094 , n3091 , n3092 );
xor ( n3095 , n2644 , n2662 );
buf ( n3096 , n3095 );
buf ( n3097 , n3096 );
not ( n3098 , n3097 );
and ( n3099 , n2690 , n3097 );
nor ( n3100 , n3098 , n3099 );
nor ( n3101 , n3089 , n3002 );
and ( n3102 , n3100 , n3101 );
xor ( n3103 , n3100 , n3101 );
xor ( n3104 , n2648 , n2660 );
buf ( n3105 , n3104 );
buf ( n3106 , n3105 );
not ( n3107 , n3106 );
and ( n3108 , n2690 , n3106 );
nor ( n3109 , n3107 , n3108 );
nor ( n3110 , n3098 , n3002 );
and ( n3111 , n3109 , n3110 );
xor ( n3112 , n3109 , n3110 );
xor ( n3113 , n2653 , n2658 );
buf ( n3114 , n3113 );
buf ( n3115 , n3114 );
not ( n3116 , n3115 );
and ( n3117 , n2690 , n3115 );
nor ( n3118 , n3116 , n3117 );
nor ( n3119 , n3107 , n3002 );
and ( n3120 , n3118 , n3119 );
xor ( n3121 , n3118 , n3119 );
xor ( n3122 , n2655 , n2656 );
buf ( n3123 , n3122 );
buf ( n3124 , n3123 );
not ( n3125 , n3124 );
and ( n3126 , n2690 , n3124 );
nor ( n3127 , n3125 , n3126 );
nor ( n3128 , n3116 , n3002 );
and ( n3129 , n3127 , n3128 );
xor ( n3130 , n3127 , n3128 );
nor ( n3131 , n283 , n2598 );
buf ( n3132 , n3131 );
buf ( n3133 , n3132 );
not ( n3134 , n3133 );
and ( n3135 , n2690 , n3133 );
nor ( n3136 , n3134 , n3135 );
nor ( n3137 , n3125 , n3002 );
and ( n3138 , n3136 , n3137 );
buf ( n3139 , n3138 );
and ( n3140 , n3130 , n3139 );
or ( n3141 , n3129 , n3140 );
and ( n3142 , n3121 , n3141 );
or ( n3143 , n3120 , n3142 );
and ( n3144 , n3112 , n3143 );
or ( n3145 , n3111 , n3144 );
and ( n3146 , n3103 , n3145 );
or ( n3147 , n3102 , n3146 );
and ( n3148 , n3094 , n3147 );
or ( n3149 , n3093 , n3148 );
and ( n3150 , n3085 , n3149 );
or ( n3151 , n3084 , n3150 );
and ( n3152 , n3076 , n3151 );
or ( n3153 , n3075 , n3152 );
and ( n3154 , n3067 , n3153 );
or ( n3155 , n3066 , n3154 );
and ( n3156 , n3058 , n3155 );
or ( n3157 , n3057 , n3156 );
and ( n3158 , n3049 , n3157 );
or ( n3159 , n3048 , n3158 );
and ( n3160 , n3040 , n3159 );
or ( n3161 , n3039 , n3160 );
and ( n3162 , n3031 , n3161 );
or ( n3163 , n3030 , n3162 );
and ( n3164 , n3022 , n3163 );
or ( n3165 , n3021 , n3164 );
and ( n3166 , n3013 , n3165 );
or ( n3167 , n3012 , n3166 );
xor ( n3168 , n3004 , n3167 );
and ( n3169 , n285 , n333 );
nor ( n3170 , n334 , n3169 );
nor ( n3171 , n384 , n305 );
xor ( n3172 , n3170 , n3171 );
and ( n3173 , n2694 , n2695 );
and ( n3174 , n2696 , n2698 );
or ( n3175 , n3173 , n3174 );
xor ( n3176 , n3172 , n3175 );
nor ( n3177 , n456 , n336 );
xor ( n3178 , n3176 , n3177 );
and ( n3179 , n2699 , n2700 );
and ( n3180 , n2701 , n2704 );
or ( n3181 , n3179 , n3180 );
xor ( n3182 , n3178 , n3181 );
nor ( n3183 , n549 , n386 );
xor ( n3184 , n3182 , n3183 );
and ( n3185 , n2705 , n2706 );
and ( n3186 , n2707 , n2710 );
or ( n3187 , n3185 , n3186 );
xor ( n3188 , n3184 , n3187 );
nor ( n3189 , n663 , n458 );
xor ( n3190 , n3188 , n3189 );
and ( n3191 , n2711 , n2712 );
and ( n3192 , n2713 , n2716 );
or ( n3193 , n3191 , n3192 );
xor ( n3194 , n3190 , n3193 );
nor ( n3195 , n795 , n551 );
xor ( n3196 , n3194 , n3195 );
and ( n3197 , n2717 , n2718 );
and ( n3198 , n2719 , n2722 );
or ( n3199 , n3197 , n3198 );
xor ( n3200 , n3196 , n3199 );
nor ( n3201 , n952 , n665 );
xor ( n3202 , n3200 , n3201 );
and ( n3203 , n2723 , n2724 );
and ( n3204 , n2725 , n2728 );
or ( n3205 , n3203 , n3204 );
xor ( n3206 , n3202 , n3205 );
nor ( n3207 , n1126 , n797 );
xor ( n3208 , n3206 , n3207 );
and ( n3209 , n2729 , n2730 );
and ( n3210 , n2731 , n2734 );
or ( n3211 , n3209 , n3210 );
xor ( n3212 , n3208 , n3211 );
nor ( n3213 , n1318 , n954 );
xor ( n3214 , n3212 , n3213 );
and ( n3215 , n2735 , n2736 );
and ( n3216 , n2737 , n2740 );
or ( n3217 , n3215 , n3216 );
xor ( n3218 , n3214 , n3217 );
nor ( n3219 , n1534 , n1128 );
xor ( n3220 , n3218 , n3219 );
and ( n3221 , n2741 , n2742 );
and ( n3222 , n2743 , n2746 );
or ( n3223 , n3221 , n3222 );
xor ( n3224 , n3220 , n3223 );
nor ( n3225 , n1771 , n1320 );
xor ( n3226 , n3224 , n3225 );
and ( n3227 , n2747 , n2748 );
and ( n3228 , n2749 , n2752 );
or ( n3229 , n3227 , n3228 );
xor ( n3230 , n3226 , n3229 );
nor ( n3231 , n2025 , n1536 );
xor ( n3232 , n3230 , n3231 );
and ( n3233 , n2753 , n2754 );
and ( n3234 , n2755 , n2758 );
or ( n3235 , n3233 , n3234 );
xor ( n3236 , n3232 , n3235 );
nor ( n3237 , n2300 , n1773 );
xor ( n3238 , n3236 , n3237 );
and ( n3239 , n2759 , n2760 );
and ( n3240 , n2761 , n2764 );
or ( n3241 , n3239 , n3240 );
xor ( n3242 , n3238 , n3241 );
nor ( n3243 , n2596 , n2027 );
xor ( n3244 , n3242 , n3243 );
and ( n3245 , n2765 , n2766 );
and ( n3246 , n2767 , n2770 );
or ( n3247 , n3245 , n3246 );
xor ( n3248 , n3244 , n3247 );
nor ( n3249 , n2991 , n2302 );
xor ( n3250 , n3248 , n3249 );
and ( n3251 , n2771 , n2772 );
and ( n3252 , n2773 , n2776 );
or ( n3253 , n3251 , n3252 );
xor ( n3254 , n3250 , n3253 );
and ( n3255 , n2794 , n2798 );
and ( n3256 , n2798 , n2802 );
and ( n3257 , n2794 , n2802 );
or ( n3258 , n3255 , n3256 , n3257 );
and ( n3259 , n2790 , n2803 );
and ( n3260 , n2803 , n2977 );
and ( n3261 , n2790 , n2977 );
or ( n3262 , n3259 , n3260 , n3261 );
xor ( n3263 , n3258 , n3262 );
and ( n3264 , n2808 , n2834 );
and ( n3265 , n2834 , n2976 );
and ( n3266 , n2808 , n2976 );
or ( n3267 , n3264 , n3265 , n3266 );
and ( n3268 , n2822 , n2823 );
and ( n3269 , n2823 , n2825 );
and ( n3270 , n2822 , n2825 );
or ( n3271 , n3268 , n3269 , n3270 );
and ( n3272 , n2812 , n2816 );
and ( n3273 , n2816 , n2833 );
and ( n3274 , n2812 , n2833 );
or ( n3275 , n3272 , n3273 , n3274 );
xor ( n3276 , n3271 , n3275 );
not ( n3277 , n328 );
and ( n3278 , n2406 , n328 );
nor ( n3279 , n3277 , n3278 );
xor ( n3280 , n3276 , n3279 );
xor ( n3281 , n3267 , n3280 );
and ( n3282 , n2839 , n2854 );
and ( n3283 , n2854 , n2975 );
and ( n3284 , n2839 , n2975 );
or ( n3285 , n3282 , n3283 , n3284 );
and ( n3286 , n2821 , n2826 );
and ( n3287 , n2826 , n2832 );
and ( n3288 , n2821 , n2832 );
or ( n3289 , n3286 , n3287 , n3288 );
and ( n3290 , n2843 , n2847 );
and ( n3291 , n2847 , n2853 );
and ( n3292 , n2843 , n2853 );
or ( n3293 , n3290 , n3291 , n3292 );
xor ( n3294 , n3289 , n3293 );
and ( n3295 , n2828 , n2829 );
and ( n3296 , n2829 , n2831 );
and ( n3297 , n2828 , n2831 );
or ( n3298 , n3295 , n3296 , n3297 );
and ( n3299 , n371 , n2138 );
and ( n3300 , n446 , n1864 );
xor ( n3301 , n3299 , n3300 );
and ( n3302 , n533 , n1753 );
xor ( n3303 , n3301 , n3302 );
xor ( n3304 , n3298 , n3303 );
and ( n3305 , n636 , n1396 );
and ( n3306 , n782 , n1302 );
xor ( n3307 , n3305 , n3306 );
and ( n3308 , n931 , n1114 );
xor ( n3309 , n3307 , n3308 );
xor ( n3310 , n3304 , n3309 );
xor ( n3311 , n3294 , n3310 );
xor ( n3312 , n3285 , n3311 );
and ( n3313 , n2859 , n2864 );
and ( n3314 , n2864 , n2974 );
and ( n3315 , n2859 , n2974 );
or ( n3316 , n3313 , n3314 , n3315 );
and ( n3317 , n2849 , n2850 );
and ( n3318 , n2850 , n2852 );
and ( n3319 , n2849 , n2852 );
or ( n3320 , n3317 , n3318 , n3319 );
and ( n3321 , n2860 , n2861 );
and ( n3322 , n2861 , n2863 );
and ( n3323 , n2860 , n2863 );
or ( n3324 , n3321 , n3322 , n3323 );
xor ( n3325 , n3320 , n3324 );
and ( n3326 , n1088 , n852 );
and ( n3327 , n1292 , n714 );
xor ( n3328 , n3326 , n3327 );
and ( n3329 , n1516 , n651 );
xor ( n3330 , n3328 , n3329 );
xor ( n3331 , n3325 , n3330 );
xor ( n3332 , n3316 , n3331 );
and ( n3333 , n2866 , n2867 );
and ( n3334 , n2867 , n2973 );
and ( n3335 , n2866 , n2973 );
or ( n3336 , n3333 , n3334 , n3335 );
and ( n3337 , n1730 , n488 );
and ( n3338 , n2001 , n411 );
xor ( n3339 , n3337 , n3338 );
and ( n3340 , n2286 , n375 );
xor ( n3341 , n3339 , n3340 );
xor ( n3342 , n3336 , n3341 );
and ( n3343 , n2581 , n312 );
and ( n3344 , n2972 , n288 );
xor ( n3345 , n3343 , n3344 );
and ( n3346 , n2885 , n2889 );
and ( n3347 , n2889 , n2893 );
and ( n3348 , n2885 , n2893 );
or ( n3349 , n3346 , n3347 , n3348 );
and ( n3350 , n2881 , n2894 );
and ( n3351 , n2894 , n2959 );
and ( n3352 , n2881 , n2959 );
or ( n3353 , n3350 , n3351 , n3352 );
xor ( n3354 , n3349 , n3353 );
and ( n3355 , n2899 , n2925 );
and ( n3356 , n2925 , n2958 );
and ( n3357 , n2899 , n2958 );
or ( n3358 , n3355 , n3356 , n3357 );
and ( n3359 , n2913 , n2914 );
and ( n3360 , n2914 , n2916 );
and ( n3361 , n2913 , n2916 );
or ( n3362 , n3359 , n3360 , n3361 );
and ( n3363 , n2903 , n2907 );
and ( n3364 , n2907 , n2924 );
and ( n3365 , n2903 , n2924 );
or ( n3366 , n3363 , n3364 , n3365 );
xor ( n3367 , n3362 , n3366 );
and ( n3368 , n2206 , n354 );
not ( n3369 , n354 );
nor ( n3370 , n3368 , n3369 );
xor ( n3371 , n3367 , n3370 );
xor ( n3372 , n3358 , n3371 );
and ( n3373 , n2930 , n2945 );
and ( n3374 , n2945 , n2957 );
and ( n3375 , n2930 , n2957 );
or ( n3376 , n3373 , n3374 , n3375 );
and ( n3377 , n2912 , n2917 );
and ( n3378 , n2917 , n2923 );
and ( n3379 , n2912 , n2923 );
or ( n3380 , n3377 , n3378 , n3379 );
and ( n3381 , n2934 , n2938 );
and ( n3382 , n2938 , n2944 );
and ( n3383 , n2934 , n2944 );
or ( n3384 , n3381 , n3382 , n3383 );
xor ( n3385 , n3380 , n3384 );
and ( n3386 , n2919 , n2920 );
and ( n3387 , n2920 , n2922 );
and ( n3388 , n2919 , n2922 );
or ( n3389 , n3386 , n3387 , n3388 );
and ( n3390 , n917 , n1048 );
and ( n3391 , n1077 , n905 );
xor ( n3392 , n3390 , n3391 );
and ( n3393 , n1277 , n766 );
xor ( n3394 , n3392 , n3393 );
xor ( n3395 , n3389 , n3394 );
and ( n3396 , n1458 , n607 );
and ( n3397 , n1713 , n510 );
xor ( n3398 , n3396 , n3397 );
and ( n3399 , n1935 , n435 );
xor ( n3400 , n3398 , n3399 );
xor ( n3401 , n3395 , n3400 );
xor ( n3402 , n3385 , n3401 );
xor ( n3403 , n3376 , n3402 );
and ( n3404 , n2947 , n2950 );
and ( n3405 , n2950 , n2956 );
and ( n3406 , n2947 , n2956 );
or ( n3407 , n3404 , n3405 , n3406 );
not ( n3408 , n318 );
and ( n3409 , n2563 , n318 );
nor ( n3410 , n3408 , n3409 );
and ( n3411 , n361 , n2271 );
xor ( n3412 , n3410 , n3411 );
and ( n3413 , n431 , n1975 );
xor ( n3414 , n3412 , n3413 );
xor ( n3415 , n3407 , n3414 );
and ( n3416 , n2940 , n2941 );
and ( n3417 , n2941 , n2943 );
and ( n3418 , n2940 , n2943 );
or ( n3419 , n3416 , n3417 , n3418 );
and ( n3420 , n2952 , n2953 );
and ( n3421 , n2953 , n2955 );
and ( n3422 , n2952 , n2955 );
or ( n3423 , n3420 , n3421 , n3422 );
xor ( n3424 , n3419 , n3423 );
and ( n3425 , n521 , n1685 );
and ( n3426 , n625 , n1497 );
xor ( n3427 , n3425 , n3426 );
and ( n3428 , n753 , n1261 );
xor ( n3429 , n3427 , n3428 );
xor ( n3430 , n3424 , n3429 );
xor ( n3431 , n3415 , n3430 );
xor ( n3432 , n3403 , n3431 );
xor ( n3433 , n3372 , n3432 );
xor ( n3434 , n3354 , n3433 );
and ( n3435 , n2872 , n2876 );
and ( n3436 , n2876 , n2960 );
and ( n3437 , n2872 , n2960 );
or ( n3438 , n3435 , n3436 , n3437 );
xor ( n3439 , n3434 , n3438 );
and ( n3440 , n2961 , n2965 );
and ( n3441 , n2966 , n2969 );
or ( n3442 , n3440 , n3441 );
xor ( n3443 , n3439 , n3442 );
buf ( n3444 , n3443 );
buf ( n3445 , n3444 );
and ( n3446 , n3445 , n279 );
xor ( n3447 , n3345 , n3446 );
xor ( n3448 , n3342 , n3447 );
xor ( n3449 , n3332 , n3448 );
xor ( n3450 , n3312 , n3449 );
xor ( n3451 , n3281 , n3450 );
xor ( n3452 , n3263 , n3451 );
and ( n3453 , n2781 , n2785 );
and ( n3454 , n2785 , n2978 );
and ( n3455 , n2781 , n2978 );
or ( n3456 , n3453 , n3454 , n3455 );
xor ( n3457 , n3452 , n3456 );
and ( n3458 , n2979 , n2983 );
and ( n3459 , n2984 , n2987 );
or ( n3460 , n3458 , n3459 );
xor ( n3461 , n3457 , n3460 );
buf ( n3462 , n3461 );
buf ( n3463 , n3462 );
not ( n3464 , n3463 );
nor ( n3465 , n3464 , n2598 );
xor ( n3466 , n3254 , n3465 );
and ( n3467 , n2777 , n2992 );
and ( n3468 , n2993 , n2996 );
or ( n3469 , n3467 , n3468 );
xor ( n3470 , n3466 , n3469 );
buf ( n3471 , n3470 );
buf ( n3472 , n3471 );
not ( n3473 , n3472 );
buf ( n3474 , n259 );
not ( n3475 , n3474 );
nor ( n3476 , n3473 , n3475 );
xor ( n3477 , n3168 , n3476 );
xor ( n3478 , n3013 , n3165 );
nor ( n3479 , n3000 , n3475 );
and ( n3480 , n3478 , n3479 );
xor ( n3481 , n3478 , n3479 );
xor ( n3482 , n3022 , n3163 );
nor ( n3483 , n2688 , n3475 );
and ( n3484 , n3482 , n3483 );
xor ( n3485 , n3482 , n3483 );
xor ( n3486 , n3031 , n3161 );
nor ( n3487 , n3008 , n3475 );
and ( n3488 , n3486 , n3487 );
xor ( n3489 , n3486 , n3487 );
xor ( n3490 , n3040 , n3159 );
nor ( n3491 , n3017 , n3475 );
and ( n3492 , n3490 , n3491 );
xor ( n3493 , n3490 , n3491 );
xor ( n3494 , n3049 , n3157 );
nor ( n3495 , n3026 , n3475 );
and ( n3496 , n3494 , n3495 );
xor ( n3497 , n3494 , n3495 );
xor ( n3498 , n3058 , n3155 );
nor ( n3499 , n3035 , n3475 );
and ( n3500 , n3498 , n3499 );
xor ( n3501 , n3498 , n3499 );
xor ( n3502 , n3067 , n3153 );
nor ( n3503 , n3044 , n3475 );
and ( n3504 , n3502 , n3503 );
xor ( n3505 , n3502 , n3503 );
xor ( n3506 , n3076 , n3151 );
nor ( n3507 , n3053 , n3475 );
and ( n3508 , n3506 , n3507 );
xor ( n3509 , n3506 , n3507 );
xor ( n3510 , n3085 , n3149 );
nor ( n3511 , n3062 , n3475 );
and ( n3512 , n3510 , n3511 );
xor ( n3513 , n3510 , n3511 );
xor ( n3514 , n3094 , n3147 );
nor ( n3515 , n3071 , n3475 );
and ( n3516 , n3514 , n3515 );
xor ( n3517 , n3514 , n3515 );
xor ( n3518 , n3103 , n3145 );
nor ( n3519 , n3080 , n3475 );
and ( n3520 , n3518 , n3519 );
xor ( n3521 , n3518 , n3519 );
xor ( n3522 , n3112 , n3143 );
nor ( n3523 , n3089 , n3475 );
and ( n3524 , n3522 , n3523 );
xor ( n3525 , n3522 , n3523 );
xor ( n3526 , n3121 , n3141 );
nor ( n3527 , n3098 , n3475 );
and ( n3528 , n3526 , n3527 );
xor ( n3529 , n3526 , n3527 );
xor ( n3530 , n3130 , n3139 );
nor ( n3531 , n3107 , n3475 );
and ( n3532 , n3530 , n3531 );
xor ( n3533 , n3530 , n3531 );
xor ( n3534 , n3136 , n3137 );
buf ( n3535 , n3534 );
nor ( n3536 , n3116 , n3475 );
and ( n3537 , n3535 , n3536 );
xor ( n3538 , n3535 , n3536 );
nor ( n3539 , n3134 , n3002 );
buf ( n3540 , n3539 );
nor ( n3541 , n3125 , n3475 );
and ( n3542 , n3540 , n3541 );
buf ( n3543 , n3542 );
and ( n3544 , n3538 , n3543 );
or ( n3545 , n3537 , n3544 );
and ( n3546 , n3533 , n3545 );
or ( n3547 , n3532 , n3546 );
and ( n3548 , n3529 , n3547 );
or ( n3549 , n3528 , n3548 );
and ( n3550 , n3525 , n3549 );
or ( n3551 , n3524 , n3550 );
and ( n3552 , n3521 , n3551 );
or ( n3553 , n3520 , n3552 );
and ( n3554 , n3517 , n3553 );
or ( n3555 , n3516 , n3554 );
and ( n3556 , n3513 , n3555 );
or ( n3557 , n3512 , n3556 );
and ( n3558 , n3509 , n3557 );
or ( n3559 , n3508 , n3558 );
and ( n3560 , n3505 , n3559 );
or ( n3561 , n3504 , n3560 );
and ( n3562 , n3501 , n3561 );
or ( n3563 , n3500 , n3562 );
and ( n3564 , n3497 , n3563 );
or ( n3565 , n3496 , n3564 );
and ( n3566 , n3493 , n3565 );
or ( n3567 , n3492 , n3566 );
and ( n3568 , n3489 , n3567 );
or ( n3569 , n3488 , n3568 );
and ( n3570 , n3485 , n3569 );
or ( n3571 , n3484 , n3570 );
and ( n3572 , n3481 , n3571 );
or ( n3573 , n3480 , n3572 );
xor ( n3574 , n3477 , n3573 );
and ( n3575 , n285 , n383 );
nor ( n3576 , n384 , n3575 );
nor ( n3577 , n456 , n305 );
xor ( n3578 , n3576 , n3577 );
and ( n3579 , n3170 , n3171 );
and ( n3580 , n3172 , n3175 );
or ( n3581 , n3579 , n3580 );
xor ( n3582 , n3578 , n3581 );
nor ( n3583 , n549 , n336 );
xor ( n3584 , n3582 , n3583 );
and ( n3585 , n3176 , n3177 );
and ( n3586 , n3178 , n3181 );
or ( n3587 , n3585 , n3586 );
xor ( n3588 , n3584 , n3587 );
nor ( n3589 , n663 , n386 );
xor ( n3590 , n3588 , n3589 );
and ( n3591 , n3182 , n3183 );
and ( n3592 , n3184 , n3187 );
or ( n3593 , n3591 , n3592 );
xor ( n3594 , n3590 , n3593 );
nor ( n3595 , n795 , n458 );
xor ( n3596 , n3594 , n3595 );
and ( n3597 , n3188 , n3189 );
and ( n3598 , n3190 , n3193 );
or ( n3599 , n3597 , n3598 );
xor ( n3600 , n3596 , n3599 );
nor ( n3601 , n952 , n551 );
xor ( n3602 , n3600 , n3601 );
and ( n3603 , n3194 , n3195 );
and ( n3604 , n3196 , n3199 );
or ( n3605 , n3603 , n3604 );
xor ( n3606 , n3602 , n3605 );
nor ( n3607 , n1126 , n665 );
xor ( n3608 , n3606 , n3607 );
and ( n3609 , n3200 , n3201 );
and ( n3610 , n3202 , n3205 );
or ( n3611 , n3609 , n3610 );
xor ( n3612 , n3608 , n3611 );
nor ( n3613 , n1318 , n797 );
xor ( n3614 , n3612 , n3613 );
and ( n3615 , n3206 , n3207 );
and ( n3616 , n3208 , n3211 );
or ( n3617 , n3615 , n3616 );
xor ( n3618 , n3614 , n3617 );
nor ( n3619 , n1534 , n954 );
xor ( n3620 , n3618 , n3619 );
and ( n3621 , n3212 , n3213 );
and ( n3622 , n3214 , n3217 );
or ( n3623 , n3621 , n3622 );
xor ( n3624 , n3620 , n3623 );
nor ( n3625 , n1771 , n1128 );
xor ( n3626 , n3624 , n3625 );
and ( n3627 , n3218 , n3219 );
and ( n3628 , n3220 , n3223 );
or ( n3629 , n3627 , n3628 );
xor ( n3630 , n3626 , n3629 );
nor ( n3631 , n2025 , n1320 );
xor ( n3632 , n3630 , n3631 );
and ( n3633 , n3224 , n3225 );
and ( n3634 , n3226 , n3229 );
or ( n3635 , n3633 , n3634 );
xor ( n3636 , n3632 , n3635 );
nor ( n3637 , n2300 , n1536 );
xor ( n3638 , n3636 , n3637 );
and ( n3639 , n3230 , n3231 );
and ( n3640 , n3232 , n3235 );
or ( n3641 , n3639 , n3640 );
xor ( n3642 , n3638 , n3641 );
nor ( n3643 , n2596 , n1773 );
xor ( n3644 , n3642 , n3643 );
and ( n3645 , n3236 , n3237 );
and ( n3646 , n3238 , n3241 );
or ( n3647 , n3645 , n3646 );
xor ( n3648 , n3644 , n3647 );
nor ( n3649 , n2991 , n2027 );
xor ( n3650 , n3648 , n3649 );
and ( n3651 , n3242 , n3243 );
and ( n3652 , n3244 , n3247 );
or ( n3653 , n3651 , n3652 );
xor ( n3654 , n3650 , n3653 );
nor ( n3655 , n3464 , n2302 );
xor ( n3656 , n3654 , n3655 );
and ( n3657 , n3248 , n3249 );
and ( n3658 , n3250 , n3253 );
or ( n3659 , n3657 , n3658 );
xor ( n3660 , n3656 , n3659 );
and ( n3661 , n3271 , n3275 );
and ( n3662 , n3275 , n3279 );
and ( n3663 , n3271 , n3279 );
or ( n3664 , n3661 , n3662 , n3663 );
and ( n3665 , n3267 , n3280 );
and ( n3666 , n3280 , n3450 );
and ( n3667 , n3267 , n3450 );
or ( n3668 , n3665 , n3666 , n3667 );
xor ( n3669 , n3664 , n3668 );
and ( n3670 , n3285 , n3311 );
and ( n3671 , n3311 , n3449 );
and ( n3672 , n3285 , n3449 );
or ( n3673 , n3670 , n3671 , n3672 );
and ( n3674 , n3299 , n3300 );
and ( n3675 , n3300 , n3302 );
and ( n3676 , n3299 , n3302 );
or ( n3677 , n3674 , n3675 , n3676 );
and ( n3678 , n3289 , n3293 );
and ( n3679 , n3293 , n3310 );
and ( n3680 , n3289 , n3310 );
or ( n3681 , n3678 , n3679 , n3680 );
xor ( n3682 , n3677 , n3681 );
not ( n3683 , n371 );
and ( n3684 , n2406 , n371 );
nor ( n3685 , n3683 , n3684 );
xor ( n3686 , n3682 , n3685 );
xor ( n3687 , n3673 , n3686 );
and ( n3688 , n3316 , n3331 );
and ( n3689 , n3331 , n3448 );
and ( n3690 , n3316 , n3448 );
or ( n3691 , n3688 , n3689 , n3690 );
and ( n3692 , n3298 , n3303 );
and ( n3693 , n3303 , n3309 );
and ( n3694 , n3298 , n3309 );
or ( n3695 , n3692 , n3693 , n3694 );
and ( n3696 , n3320 , n3324 );
and ( n3697 , n3324 , n3330 );
and ( n3698 , n3320 , n3330 );
or ( n3699 , n3696 , n3697 , n3698 );
xor ( n3700 , n3695 , n3699 );
and ( n3701 , n3305 , n3306 );
and ( n3702 , n3306 , n3308 );
and ( n3703 , n3305 , n3308 );
or ( n3704 , n3701 , n3702 , n3703 );
and ( n3705 , n446 , n2138 );
and ( n3706 , n533 , n1864 );
xor ( n3707 , n3705 , n3706 );
and ( n3708 , n636 , n1753 );
xor ( n3709 , n3707 , n3708 );
xor ( n3710 , n3704 , n3709 );
and ( n3711 , n782 , n1396 );
and ( n3712 , n931 , n1302 );
xor ( n3713 , n3711 , n3712 );
and ( n3714 , n1088 , n1114 );
xor ( n3715 , n3713 , n3714 );
xor ( n3716 , n3710 , n3715 );
xor ( n3717 , n3700 , n3716 );
xor ( n3718 , n3691 , n3717 );
and ( n3719 , n3336 , n3341 );
and ( n3720 , n3341 , n3447 );
and ( n3721 , n3336 , n3447 );
or ( n3722 , n3719 , n3720 , n3721 );
and ( n3723 , n3326 , n3327 );
and ( n3724 , n3327 , n3329 );
and ( n3725 , n3326 , n3329 );
or ( n3726 , n3723 , n3724 , n3725 );
and ( n3727 , n3337 , n3338 );
and ( n3728 , n3338 , n3340 );
and ( n3729 , n3337 , n3340 );
or ( n3730 , n3727 , n3728 , n3729 );
xor ( n3731 , n3726 , n3730 );
and ( n3732 , n1292 , n852 );
and ( n3733 , n1516 , n714 );
xor ( n3734 , n3732 , n3733 );
and ( n3735 , n1730 , n651 );
xor ( n3736 , n3734 , n3735 );
xor ( n3737 , n3731 , n3736 );
xor ( n3738 , n3722 , n3737 );
and ( n3739 , n3343 , n3344 );
and ( n3740 , n3344 , n3446 );
and ( n3741 , n3343 , n3446 );
or ( n3742 , n3739 , n3740 , n3741 );
and ( n3743 , n2001 , n488 );
and ( n3744 , n2286 , n411 );
xor ( n3745 , n3743 , n3744 );
and ( n3746 , n2581 , n375 );
xor ( n3747 , n3745 , n3746 );
xor ( n3748 , n3742 , n3747 );
and ( n3749 , n2972 , n312 );
and ( n3750 , n3445 , n288 );
xor ( n3751 , n3749 , n3750 );
and ( n3752 , n3362 , n3366 );
and ( n3753 , n3366 , n3370 );
and ( n3754 , n3362 , n3370 );
or ( n3755 , n3752 , n3753 , n3754 );
and ( n3756 , n3358 , n3371 );
and ( n3757 , n3371 , n3432 );
and ( n3758 , n3358 , n3432 );
or ( n3759 , n3756 , n3757 , n3758 );
xor ( n3760 , n3755 , n3759 );
and ( n3761 , n3376 , n3402 );
and ( n3762 , n3402 , n3431 );
and ( n3763 , n3376 , n3431 );
or ( n3764 , n3761 , n3762 , n3763 );
and ( n3765 , n3396 , n3397 );
and ( n3766 , n3397 , n3399 );
and ( n3767 , n3396 , n3399 );
or ( n3768 , n3765 , n3766 , n3767 );
and ( n3769 , n3380 , n3384 );
and ( n3770 , n3384 , n3401 );
and ( n3771 , n3380 , n3401 );
or ( n3772 , n3769 , n3770 , n3771 );
xor ( n3773 , n3768 , n3772 );
and ( n3774 , n2206 , n435 );
not ( n3775 , n435 );
nor ( n3776 , n3774 , n3775 );
xor ( n3777 , n3773 , n3776 );
xor ( n3778 , n3764 , n3777 );
and ( n3779 , n3407 , n3414 );
and ( n3780 , n3414 , n3430 );
and ( n3781 , n3407 , n3430 );
or ( n3782 , n3779 , n3780 , n3781 );
and ( n3783 , n3389 , n3394 );
and ( n3784 , n3394 , n3400 );
and ( n3785 , n3389 , n3400 );
or ( n3786 , n3783 , n3784 , n3785 );
and ( n3787 , n3419 , n3423 );
and ( n3788 , n3423 , n3429 );
and ( n3789 , n3419 , n3429 );
or ( n3790 , n3787 , n3788 , n3789 );
xor ( n3791 , n3786 , n3790 );
and ( n3792 , n3390 , n3391 );
and ( n3793 , n3391 , n3393 );
and ( n3794 , n3390 , n3393 );
or ( n3795 , n3792 , n3793 , n3794 );
and ( n3796 , n917 , n1261 );
and ( n3797 , n1077 , n1048 );
xor ( n3798 , n3796 , n3797 );
and ( n3799 , n1277 , n905 );
xor ( n3800 , n3798 , n3799 );
xor ( n3801 , n3795 , n3800 );
and ( n3802 , n1458 , n766 );
and ( n3803 , n1713 , n607 );
xor ( n3804 , n3802 , n3803 );
and ( n3805 , n1935 , n510 );
xor ( n3806 , n3804 , n3805 );
xor ( n3807 , n3801 , n3806 );
xor ( n3808 , n3791 , n3807 );
xor ( n3809 , n3782 , n3808 );
and ( n3810 , n3410 , n3411 );
and ( n3811 , n3411 , n3413 );
and ( n3812 , n3410 , n3413 );
or ( n3813 , n3810 , n3811 , n3812 );
and ( n3814 , n3425 , n3426 );
and ( n3815 , n3426 , n3428 );
and ( n3816 , n3425 , n3428 );
or ( n3817 , n3814 , n3815 , n3816 );
xor ( n3818 , n3813 , n3817 );
and ( n3819 , n521 , n1975 );
and ( n3820 , n625 , n1685 );
xor ( n3821 , n3819 , n3820 );
and ( n3822 , n753 , n1497 );
xor ( n3823 , n3821 , n3822 );
xor ( n3824 , n3818 , n3823 );
not ( n3825 , n361 );
and ( n3826 , n2563 , n361 );
nor ( n3827 , n3825 , n3826 );
and ( n3828 , n431 , n2271 );
xor ( n3829 , n3827 , n3828 );
xor ( n3830 , n3824 , n3829 );
xor ( n3831 , n3809 , n3830 );
xor ( n3832 , n3778 , n3831 );
xor ( n3833 , n3760 , n3832 );
and ( n3834 , n3349 , n3353 );
and ( n3835 , n3353 , n3433 );
and ( n3836 , n3349 , n3433 );
or ( n3837 , n3834 , n3835 , n3836 );
xor ( n3838 , n3833 , n3837 );
and ( n3839 , n3434 , n3438 );
and ( n3840 , n3439 , n3442 );
or ( n3841 , n3839 , n3840 );
xor ( n3842 , n3838 , n3841 );
buf ( n3843 , n3842 );
buf ( n3844 , n3843 );
and ( n3845 , n3844 , n279 );
xor ( n3846 , n3751 , n3845 );
xor ( n3847 , n3748 , n3846 );
xor ( n3848 , n3738 , n3847 );
xor ( n3849 , n3718 , n3848 );
xor ( n3850 , n3687 , n3849 );
xor ( n3851 , n3669 , n3850 );
and ( n3852 , n3258 , n3262 );
and ( n3853 , n3262 , n3451 );
and ( n3854 , n3258 , n3451 );
or ( n3855 , n3852 , n3853 , n3854 );
xor ( n3856 , n3851 , n3855 );
and ( n3857 , n3452 , n3456 );
and ( n3858 , n3457 , n3460 );
or ( n3859 , n3857 , n3858 );
xor ( n3860 , n3856 , n3859 );
buf ( n3861 , n3860 );
buf ( n3862 , n3861 );
not ( n3863 , n3862 );
nor ( n3864 , n3863 , n2598 );
xor ( n3865 , n3660 , n3864 );
and ( n3866 , n3254 , n3465 );
and ( n3867 , n3466 , n3469 );
or ( n3868 , n3866 , n3867 );
xor ( n3869 , n3865 , n3868 );
buf ( n3870 , n3869 );
buf ( n3871 , n3870 );
not ( n3872 , n3871 );
buf ( n3873 , n260 );
not ( n3874 , n3873 );
nor ( n3875 , n3872 , n3874 );
xor ( n3876 , n3574 , n3875 );
xor ( n3877 , n3481 , n3571 );
nor ( n3878 , n3473 , n3874 );
and ( n3879 , n3877 , n3878 );
xor ( n3880 , n3877 , n3878 );
xor ( n3881 , n3485 , n3569 );
nor ( n3882 , n3000 , n3874 );
and ( n3883 , n3881 , n3882 );
xor ( n3884 , n3881 , n3882 );
xor ( n3885 , n3489 , n3567 );
nor ( n3886 , n2688 , n3874 );
and ( n3887 , n3885 , n3886 );
xor ( n3888 , n3885 , n3886 );
xor ( n3889 , n3493 , n3565 );
nor ( n3890 , n3008 , n3874 );
and ( n3891 , n3889 , n3890 );
xor ( n3892 , n3889 , n3890 );
xor ( n3893 , n3497 , n3563 );
nor ( n3894 , n3017 , n3874 );
and ( n3895 , n3893 , n3894 );
xor ( n3896 , n3893 , n3894 );
xor ( n3897 , n3501 , n3561 );
nor ( n3898 , n3026 , n3874 );
and ( n3899 , n3897 , n3898 );
xor ( n3900 , n3897 , n3898 );
xor ( n3901 , n3505 , n3559 );
nor ( n3902 , n3035 , n3874 );
and ( n3903 , n3901 , n3902 );
xor ( n3904 , n3901 , n3902 );
xor ( n3905 , n3509 , n3557 );
nor ( n3906 , n3044 , n3874 );
and ( n3907 , n3905 , n3906 );
xor ( n3908 , n3905 , n3906 );
xor ( n3909 , n3513 , n3555 );
nor ( n3910 , n3053 , n3874 );
and ( n3911 , n3909 , n3910 );
xor ( n3912 , n3909 , n3910 );
xor ( n3913 , n3517 , n3553 );
nor ( n3914 , n3062 , n3874 );
and ( n3915 , n3913 , n3914 );
xor ( n3916 , n3913 , n3914 );
xor ( n3917 , n3521 , n3551 );
nor ( n3918 , n3071 , n3874 );
and ( n3919 , n3917 , n3918 );
xor ( n3920 , n3917 , n3918 );
xor ( n3921 , n3525 , n3549 );
nor ( n3922 , n3080 , n3874 );
and ( n3923 , n3921 , n3922 );
xor ( n3924 , n3921 , n3922 );
xor ( n3925 , n3529 , n3547 );
nor ( n3926 , n3089 , n3874 );
and ( n3927 , n3925 , n3926 );
xor ( n3928 , n3925 , n3926 );
xor ( n3929 , n3533 , n3545 );
nor ( n3930 , n3098 , n3874 );
and ( n3931 , n3929 , n3930 );
xor ( n3932 , n3929 , n3930 );
xor ( n3933 , n3538 , n3543 );
nor ( n3934 , n3107 , n3874 );
and ( n3935 , n3933 , n3934 );
xor ( n3936 , n3933 , n3934 );
xor ( n3937 , n3540 , n3541 );
buf ( n3938 , n3937 );
nor ( n3939 , n3116 , n3874 );
and ( n3940 , n3938 , n3939 );
xor ( n3941 , n3938 , n3939 );
nor ( n3942 , n3134 , n3475 );
buf ( n3943 , n3942 );
nor ( n3944 , n3125 , n3874 );
and ( n3945 , n3943 , n3944 );
buf ( n3946 , n3945 );
and ( n3947 , n3941 , n3946 );
or ( n3948 , n3940 , n3947 );
and ( n3949 , n3936 , n3948 );
or ( n3950 , n3935 , n3949 );
and ( n3951 , n3932 , n3950 );
or ( n3952 , n3931 , n3951 );
and ( n3953 , n3928 , n3952 );
or ( n3954 , n3927 , n3953 );
and ( n3955 , n3924 , n3954 );
or ( n3956 , n3923 , n3955 );
and ( n3957 , n3920 , n3956 );
or ( n3958 , n3919 , n3957 );
and ( n3959 , n3916 , n3958 );
or ( n3960 , n3915 , n3959 );
and ( n3961 , n3912 , n3960 );
or ( n3962 , n3911 , n3961 );
and ( n3963 , n3908 , n3962 );
or ( n3964 , n3907 , n3963 );
and ( n3965 , n3904 , n3964 );
or ( n3966 , n3903 , n3965 );
and ( n3967 , n3900 , n3966 );
or ( n3968 , n3899 , n3967 );
and ( n3969 , n3896 , n3968 );
or ( n3970 , n3895 , n3969 );
and ( n3971 , n3892 , n3970 );
or ( n3972 , n3891 , n3971 );
and ( n3973 , n3888 , n3972 );
or ( n3974 , n3887 , n3973 );
and ( n3975 , n3884 , n3974 );
or ( n3976 , n3883 , n3975 );
and ( n3977 , n3880 , n3976 );
or ( n3978 , n3879 , n3977 );
xor ( n3979 , n3876 , n3978 );
and ( n3980 , n285 , n455 );
nor ( n3981 , n456 , n3980 );
nor ( n3982 , n549 , n305 );
xor ( n3983 , n3981 , n3982 );
and ( n3984 , n3576 , n3577 );
and ( n3985 , n3578 , n3581 );
or ( n3986 , n3984 , n3985 );
xor ( n3987 , n3983 , n3986 );
nor ( n3988 , n663 , n336 );
xor ( n3989 , n3987 , n3988 );
and ( n3990 , n3582 , n3583 );
and ( n3991 , n3584 , n3587 );
or ( n3992 , n3990 , n3991 );
xor ( n3993 , n3989 , n3992 );
nor ( n3994 , n795 , n386 );
xor ( n3995 , n3993 , n3994 );
and ( n3996 , n3588 , n3589 );
and ( n3997 , n3590 , n3593 );
or ( n3998 , n3996 , n3997 );
xor ( n3999 , n3995 , n3998 );
nor ( n4000 , n952 , n458 );
xor ( n4001 , n3999 , n4000 );
and ( n4002 , n3594 , n3595 );
and ( n4003 , n3596 , n3599 );
or ( n4004 , n4002 , n4003 );
xor ( n4005 , n4001 , n4004 );
nor ( n4006 , n1126 , n551 );
xor ( n4007 , n4005 , n4006 );
and ( n4008 , n3600 , n3601 );
and ( n4009 , n3602 , n3605 );
or ( n4010 , n4008 , n4009 );
xor ( n4011 , n4007 , n4010 );
nor ( n4012 , n1318 , n665 );
xor ( n4013 , n4011 , n4012 );
and ( n4014 , n3606 , n3607 );
and ( n4015 , n3608 , n3611 );
or ( n4016 , n4014 , n4015 );
xor ( n4017 , n4013 , n4016 );
nor ( n4018 , n1534 , n797 );
xor ( n4019 , n4017 , n4018 );
and ( n4020 , n3612 , n3613 );
and ( n4021 , n3614 , n3617 );
or ( n4022 , n4020 , n4021 );
xor ( n4023 , n4019 , n4022 );
nor ( n4024 , n1771 , n954 );
xor ( n4025 , n4023 , n4024 );
and ( n4026 , n3618 , n3619 );
and ( n4027 , n3620 , n3623 );
or ( n4028 , n4026 , n4027 );
xor ( n4029 , n4025 , n4028 );
nor ( n4030 , n2025 , n1128 );
xor ( n4031 , n4029 , n4030 );
and ( n4032 , n3624 , n3625 );
and ( n4033 , n3626 , n3629 );
or ( n4034 , n4032 , n4033 );
xor ( n4035 , n4031 , n4034 );
nor ( n4036 , n2300 , n1320 );
xor ( n4037 , n4035 , n4036 );
and ( n4038 , n3630 , n3631 );
and ( n4039 , n3632 , n3635 );
or ( n4040 , n4038 , n4039 );
xor ( n4041 , n4037 , n4040 );
nor ( n4042 , n2596 , n1536 );
xor ( n4043 , n4041 , n4042 );
and ( n4044 , n3636 , n3637 );
and ( n4045 , n3638 , n3641 );
or ( n4046 , n4044 , n4045 );
xor ( n4047 , n4043 , n4046 );
nor ( n4048 , n2991 , n1773 );
xor ( n4049 , n4047 , n4048 );
and ( n4050 , n3642 , n3643 );
and ( n4051 , n3644 , n3647 );
or ( n4052 , n4050 , n4051 );
xor ( n4053 , n4049 , n4052 );
nor ( n4054 , n3464 , n2027 );
xor ( n4055 , n4053 , n4054 );
and ( n4056 , n3648 , n3649 );
and ( n4057 , n3650 , n3653 );
or ( n4058 , n4056 , n4057 );
xor ( n4059 , n4055 , n4058 );
nor ( n4060 , n3863 , n2302 );
xor ( n4061 , n4059 , n4060 );
and ( n4062 , n3654 , n3655 );
and ( n4063 , n3656 , n3659 );
or ( n4064 , n4062 , n4063 );
xor ( n4065 , n4061 , n4064 );
and ( n4066 , n3677 , n3681 );
and ( n4067 , n3681 , n3685 );
and ( n4068 , n3677 , n3685 );
or ( n4069 , n4066 , n4067 , n4068 );
and ( n4070 , n3673 , n3686 );
and ( n4071 , n3686 , n3849 );
and ( n4072 , n3673 , n3849 );
or ( n4073 , n4070 , n4071 , n4072 );
xor ( n4074 , n4069 , n4073 );
and ( n4075 , n3691 , n3717 );
and ( n4076 , n3717 , n3848 );
and ( n4077 , n3691 , n3848 );
or ( n4078 , n4075 , n4076 , n4077 );
and ( n4079 , n3705 , n3706 );
and ( n4080 , n3706 , n3708 );
and ( n4081 , n3705 , n3708 );
or ( n4082 , n4079 , n4080 , n4081 );
and ( n4083 , n3695 , n3699 );
and ( n4084 , n3699 , n3716 );
and ( n4085 , n3695 , n3716 );
or ( n4086 , n4083 , n4084 , n4085 );
xor ( n4087 , n4082 , n4086 );
not ( n4088 , n446 );
and ( n4089 , n2406 , n446 );
nor ( n4090 , n4088 , n4089 );
xor ( n4091 , n4087 , n4090 );
xor ( n4092 , n4078 , n4091 );
and ( n4093 , n3722 , n3737 );
and ( n4094 , n3737 , n3847 );
and ( n4095 , n3722 , n3847 );
or ( n4096 , n4093 , n4094 , n4095 );
and ( n4097 , n3704 , n3709 );
and ( n4098 , n3709 , n3715 );
and ( n4099 , n3704 , n3715 );
or ( n4100 , n4097 , n4098 , n4099 );
and ( n4101 , n3726 , n3730 );
and ( n4102 , n3730 , n3736 );
and ( n4103 , n3726 , n3736 );
or ( n4104 , n4101 , n4102 , n4103 );
xor ( n4105 , n4100 , n4104 );
and ( n4106 , n3711 , n3712 );
and ( n4107 , n3712 , n3714 );
and ( n4108 , n3711 , n3714 );
or ( n4109 , n4106 , n4107 , n4108 );
and ( n4110 , n533 , n2138 );
and ( n4111 , n636 , n1864 );
xor ( n4112 , n4110 , n4111 );
and ( n4113 , n782 , n1753 );
xor ( n4114 , n4112 , n4113 );
xor ( n4115 , n4109 , n4114 );
and ( n4116 , n931 , n1396 );
and ( n4117 , n1088 , n1302 );
xor ( n4118 , n4116 , n4117 );
and ( n4119 , n1292 , n1114 );
xor ( n4120 , n4118 , n4119 );
xor ( n4121 , n4115 , n4120 );
xor ( n4122 , n4105 , n4121 );
xor ( n4123 , n4096 , n4122 );
and ( n4124 , n3742 , n3747 );
and ( n4125 , n3747 , n3846 );
and ( n4126 , n3742 , n3846 );
or ( n4127 , n4124 , n4125 , n4126 );
and ( n4128 , n3732 , n3733 );
and ( n4129 , n3733 , n3735 );
and ( n4130 , n3732 , n3735 );
or ( n4131 , n4128 , n4129 , n4130 );
and ( n4132 , n3743 , n3744 );
and ( n4133 , n3744 , n3746 );
and ( n4134 , n3743 , n3746 );
or ( n4135 , n4132 , n4133 , n4134 );
xor ( n4136 , n4131 , n4135 );
and ( n4137 , n1516 , n852 );
and ( n4138 , n1730 , n714 );
xor ( n4139 , n4137 , n4138 );
and ( n4140 , n2001 , n651 );
xor ( n4141 , n4139 , n4140 );
xor ( n4142 , n4136 , n4141 );
xor ( n4143 , n4127 , n4142 );
and ( n4144 , n3749 , n3750 );
and ( n4145 , n3750 , n3845 );
and ( n4146 , n3749 , n3845 );
or ( n4147 , n4144 , n4145 , n4146 );
and ( n4148 , n2286 , n488 );
and ( n4149 , n2581 , n411 );
xor ( n4150 , n4148 , n4149 );
and ( n4151 , n2972 , n375 );
xor ( n4152 , n4150 , n4151 );
xor ( n4153 , n4147 , n4152 );
and ( n4154 , n3445 , n312 );
and ( n4155 , n3844 , n288 );
xor ( n4156 , n4154 , n4155 );
and ( n4157 , n3768 , n3772 );
and ( n4158 , n3772 , n3776 );
and ( n4159 , n3768 , n3776 );
or ( n4160 , n4157 , n4158 , n4159 );
and ( n4161 , n3764 , n3777 );
and ( n4162 , n3777 , n3831 );
and ( n4163 , n3764 , n3831 );
or ( n4164 , n4161 , n4162 , n4163 );
xor ( n4165 , n4160 , n4164 );
and ( n4166 , n3782 , n3808 );
and ( n4167 , n3808 , n3830 );
and ( n4168 , n3782 , n3830 );
or ( n4169 , n4166 , n4167 , n4168 );
and ( n4170 , n3802 , n3803 );
and ( n4171 , n3803 , n3805 );
and ( n4172 , n3802 , n3805 );
or ( n4173 , n4170 , n4171 , n4172 );
and ( n4174 , n3786 , n3790 );
and ( n4175 , n3790 , n3807 );
and ( n4176 , n3786 , n3807 );
or ( n4177 , n4174 , n4175 , n4176 );
xor ( n4178 , n4173 , n4177 );
and ( n4179 , n2206 , n510 );
not ( n4180 , n510 );
nor ( n4181 , n4179 , n4180 );
xor ( n4182 , n4178 , n4181 );
xor ( n4183 , n4169 , n4182 );
and ( n4184 , n3824 , n3829 );
and ( n4185 , n3813 , n3817 );
and ( n4186 , n3817 , n3823 );
and ( n4187 , n3813 , n3823 );
or ( n4188 , n4185 , n4186 , n4187 );
and ( n4189 , n3795 , n3800 );
and ( n4190 , n3800 , n3806 );
and ( n4191 , n3795 , n3806 );
or ( n4192 , n4189 , n4190 , n4191 );
xor ( n4193 , n4188 , n4192 );
and ( n4194 , n3796 , n3797 );
and ( n4195 , n3797 , n3799 );
and ( n4196 , n3796 , n3799 );
or ( n4197 , n4194 , n4195 , n4196 );
and ( n4198 , n917 , n1497 );
and ( n4199 , n1077 , n1261 );
xor ( n4200 , n4198 , n4199 );
and ( n4201 , n1277 , n1048 );
xor ( n4202 , n4200 , n4201 );
xor ( n4203 , n4197 , n4202 );
and ( n4204 , n1458 , n905 );
and ( n4205 , n1713 , n766 );
xor ( n4206 , n4204 , n4205 );
and ( n4207 , n1935 , n607 );
xor ( n4208 , n4206 , n4207 );
xor ( n4209 , n4203 , n4208 );
xor ( n4210 , n4193 , n4209 );
xor ( n4211 , n4184 , n4210 );
not ( n4212 , n431 );
and ( n4213 , n2563 , n431 );
nor ( n4214 , n4212 , n4213 );
and ( n4215 , n3819 , n3820 );
and ( n4216 , n3820 , n3822 );
and ( n4217 , n3819 , n3822 );
or ( n4218 , n4215 , n4216 , n4217 );
and ( n4219 , n3827 , n3828 );
xor ( n4220 , n4218 , n4219 );
and ( n4221 , n521 , n2271 );
and ( n4222 , n625 , n1975 );
xor ( n4223 , n4221 , n4222 );
and ( n4224 , n753 , n1685 );
xor ( n4225 , n4223 , n4224 );
xor ( n4226 , n4220 , n4225 );
xor ( n4227 , n4214 , n4226 );
xor ( n4228 , n4211 , n4227 );
xor ( n4229 , n4183 , n4228 );
xor ( n4230 , n4165 , n4229 );
and ( n4231 , n3755 , n3759 );
and ( n4232 , n3759 , n3832 );
and ( n4233 , n3755 , n3832 );
or ( n4234 , n4231 , n4232 , n4233 );
xor ( n4235 , n4230 , n4234 );
and ( n4236 , n3833 , n3837 );
and ( n4237 , n3838 , n3841 );
or ( n4238 , n4236 , n4237 );
xor ( n4239 , n4235 , n4238 );
buf ( n4240 , n4239 );
buf ( n4241 , n4240 );
and ( n4242 , n4241 , n279 );
xor ( n4243 , n4156 , n4242 );
xor ( n4244 , n4153 , n4243 );
xor ( n4245 , n4143 , n4244 );
xor ( n4246 , n4123 , n4245 );
xor ( n4247 , n4092 , n4246 );
xor ( n4248 , n4074 , n4247 );
and ( n4249 , n3664 , n3668 );
and ( n4250 , n3668 , n3850 );
and ( n4251 , n3664 , n3850 );
or ( n4252 , n4249 , n4250 , n4251 );
xor ( n4253 , n4248 , n4252 );
and ( n4254 , n3851 , n3855 );
and ( n4255 , n3856 , n3859 );
or ( n4256 , n4254 , n4255 );
xor ( n4257 , n4253 , n4256 );
buf ( n4258 , n4257 );
buf ( n4259 , n4258 );
not ( n4260 , n4259 );
nor ( n4261 , n4260 , n2598 );
xor ( n4262 , n4065 , n4261 );
and ( n4263 , n3660 , n3864 );
and ( n4264 , n3865 , n3868 );
or ( n4265 , n4263 , n4264 );
xor ( n4266 , n4262 , n4265 );
buf ( n4267 , n4266 );
buf ( n4268 , n4267 );
not ( n4269 , n4268 );
buf ( n4270 , n261 );
not ( n4271 , n4270 );
nor ( n4272 , n4269 , n4271 );
xor ( n4273 , n3979 , n4272 );
xor ( n4274 , n3880 , n3976 );
nor ( n4275 , n3872 , n4271 );
and ( n4276 , n4274 , n4275 );
xor ( n4277 , n4274 , n4275 );
xor ( n4278 , n3884 , n3974 );
nor ( n4279 , n3473 , n4271 );
and ( n4280 , n4278 , n4279 );
xor ( n4281 , n4278 , n4279 );
xor ( n4282 , n3888 , n3972 );
nor ( n4283 , n3000 , n4271 );
and ( n4284 , n4282 , n4283 );
xor ( n4285 , n4282 , n4283 );
xor ( n4286 , n3892 , n3970 );
nor ( n4287 , n2688 , n4271 );
and ( n4288 , n4286 , n4287 );
xor ( n4289 , n4286 , n4287 );
xor ( n4290 , n3896 , n3968 );
nor ( n4291 , n3008 , n4271 );
and ( n4292 , n4290 , n4291 );
xor ( n4293 , n4290 , n4291 );
xor ( n4294 , n3900 , n3966 );
nor ( n4295 , n3017 , n4271 );
and ( n4296 , n4294 , n4295 );
xor ( n4297 , n4294 , n4295 );
xor ( n4298 , n3904 , n3964 );
nor ( n4299 , n3026 , n4271 );
and ( n4300 , n4298 , n4299 );
xor ( n4301 , n4298 , n4299 );
xor ( n4302 , n3908 , n3962 );
nor ( n4303 , n3035 , n4271 );
and ( n4304 , n4302 , n4303 );
xor ( n4305 , n4302 , n4303 );
xor ( n4306 , n3912 , n3960 );
nor ( n4307 , n3044 , n4271 );
and ( n4308 , n4306 , n4307 );
xor ( n4309 , n4306 , n4307 );
xor ( n4310 , n3916 , n3958 );
nor ( n4311 , n3053 , n4271 );
and ( n4312 , n4310 , n4311 );
xor ( n4313 , n4310 , n4311 );
xor ( n4314 , n3920 , n3956 );
nor ( n4315 , n3062 , n4271 );
and ( n4316 , n4314 , n4315 );
xor ( n4317 , n4314 , n4315 );
xor ( n4318 , n3924 , n3954 );
nor ( n4319 , n3071 , n4271 );
and ( n4320 , n4318 , n4319 );
xor ( n4321 , n4318 , n4319 );
xor ( n4322 , n3928 , n3952 );
nor ( n4323 , n3080 , n4271 );
and ( n4324 , n4322 , n4323 );
xor ( n4325 , n4322 , n4323 );
xor ( n4326 , n3932 , n3950 );
nor ( n4327 , n3089 , n4271 );
and ( n4328 , n4326 , n4327 );
xor ( n4329 , n4326 , n4327 );
xor ( n4330 , n3936 , n3948 );
nor ( n4331 , n3098 , n4271 );
and ( n4332 , n4330 , n4331 );
xor ( n4333 , n4330 , n4331 );
xor ( n4334 , n3941 , n3946 );
nor ( n4335 , n3107 , n4271 );
and ( n4336 , n4334 , n4335 );
xor ( n4337 , n4334 , n4335 );
xor ( n4338 , n3943 , n3944 );
buf ( n4339 , n4338 );
nor ( n4340 , n3116 , n4271 );
and ( n4341 , n4339 , n4340 );
xor ( n4342 , n4339 , n4340 );
nor ( n4343 , n3134 , n3874 );
buf ( n4344 , n4343 );
nor ( n4345 , n3125 , n4271 );
and ( n4346 , n4344 , n4345 );
buf ( n4347 , n4346 );
and ( n4348 , n4342 , n4347 );
or ( n4349 , n4341 , n4348 );
and ( n4350 , n4337 , n4349 );
or ( n4351 , n4336 , n4350 );
and ( n4352 , n4333 , n4351 );
or ( n4353 , n4332 , n4352 );
and ( n4354 , n4329 , n4353 );
or ( n4355 , n4328 , n4354 );
and ( n4356 , n4325 , n4355 );
or ( n4357 , n4324 , n4356 );
and ( n4358 , n4321 , n4357 );
or ( n4359 , n4320 , n4358 );
and ( n4360 , n4317 , n4359 );
or ( n4361 , n4316 , n4360 );
and ( n4362 , n4313 , n4361 );
or ( n4363 , n4312 , n4362 );
and ( n4364 , n4309 , n4363 );
or ( n4365 , n4308 , n4364 );
and ( n4366 , n4305 , n4365 );
or ( n4367 , n4304 , n4366 );
and ( n4368 , n4301 , n4367 );
or ( n4369 , n4300 , n4368 );
and ( n4370 , n4297 , n4369 );
or ( n4371 , n4296 , n4370 );
and ( n4372 , n4293 , n4371 );
or ( n4373 , n4292 , n4372 );
and ( n4374 , n4289 , n4373 );
or ( n4375 , n4288 , n4374 );
and ( n4376 , n4285 , n4375 );
or ( n4377 , n4284 , n4376 );
and ( n4378 , n4281 , n4377 );
or ( n4379 , n4280 , n4378 );
and ( n4380 , n4277 , n4379 );
or ( n4381 , n4276 , n4380 );
xor ( n4382 , n4273 , n4381 );
and ( n4383 , n285 , n548 );
nor ( n4384 , n549 , n4383 );
nor ( n4385 , n663 , n305 );
xor ( n4386 , n4384 , n4385 );
and ( n4387 , n3981 , n3982 );
and ( n4388 , n3983 , n3986 );
or ( n4389 , n4387 , n4388 );
xor ( n4390 , n4386 , n4389 );
nor ( n4391 , n795 , n336 );
xor ( n4392 , n4390 , n4391 );
and ( n4393 , n3987 , n3988 );
and ( n4394 , n3989 , n3992 );
or ( n4395 , n4393 , n4394 );
xor ( n4396 , n4392 , n4395 );
nor ( n4397 , n952 , n386 );
xor ( n4398 , n4396 , n4397 );
and ( n4399 , n3993 , n3994 );
and ( n4400 , n3995 , n3998 );
or ( n4401 , n4399 , n4400 );
xor ( n4402 , n4398 , n4401 );
nor ( n4403 , n1126 , n458 );
xor ( n4404 , n4402 , n4403 );
and ( n4405 , n3999 , n4000 );
and ( n4406 , n4001 , n4004 );
or ( n4407 , n4405 , n4406 );
xor ( n4408 , n4404 , n4407 );
nor ( n4409 , n1318 , n551 );
xor ( n4410 , n4408 , n4409 );
and ( n4411 , n4005 , n4006 );
and ( n4412 , n4007 , n4010 );
or ( n4413 , n4411 , n4412 );
xor ( n4414 , n4410 , n4413 );
nor ( n4415 , n1534 , n665 );
xor ( n4416 , n4414 , n4415 );
and ( n4417 , n4011 , n4012 );
and ( n4418 , n4013 , n4016 );
or ( n4419 , n4417 , n4418 );
xor ( n4420 , n4416 , n4419 );
nor ( n4421 , n1771 , n797 );
xor ( n4422 , n4420 , n4421 );
and ( n4423 , n4017 , n4018 );
and ( n4424 , n4019 , n4022 );
or ( n4425 , n4423 , n4424 );
xor ( n4426 , n4422 , n4425 );
nor ( n4427 , n2025 , n954 );
xor ( n4428 , n4426 , n4427 );
and ( n4429 , n4023 , n4024 );
and ( n4430 , n4025 , n4028 );
or ( n4431 , n4429 , n4430 );
xor ( n4432 , n4428 , n4431 );
nor ( n4433 , n2300 , n1128 );
xor ( n4434 , n4432 , n4433 );
and ( n4435 , n4029 , n4030 );
and ( n4436 , n4031 , n4034 );
or ( n4437 , n4435 , n4436 );
xor ( n4438 , n4434 , n4437 );
nor ( n4439 , n2596 , n1320 );
xor ( n4440 , n4438 , n4439 );
and ( n4441 , n4035 , n4036 );
and ( n4442 , n4037 , n4040 );
or ( n4443 , n4441 , n4442 );
xor ( n4444 , n4440 , n4443 );
nor ( n4445 , n2991 , n1536 );
xor ( n4446 , n4444 , n4445 );
and ( n4447 , n4041 , n4042 );
and ( n4448 , n4043 , n4046 );
or ( n4449 , n4447 , n4448 );
xor ( n4450 , n4446 , n4449 );
nor ( n4451 , n3464 , n1773 );
xor ( n4452 , n4450 , n4451 );
and ( n4453 , n4047 , n4048 );
and ( n4454 , n4049 , n4052 );
or ( n4455 , n4453 , n4454 );
xor ( n4456 , n4452 , n4455 );
nor ( n4457 , n3863 , n2027 );
xor ( n4458 , n4456 , n4457 );
and ( n4459 , n4053 , n4054 );
and ( n4460 , n4055 , n4058 );
or ( n4461 , n4459 , n4460 );
xor ( n4462 , n4458 , n4461 );
nor ( n4463 , n4260 , n2302 );
xor ( n4464 , n4462 , n4463 );
and ( n4465 , n4059 , n4060 );
and ( n4466 , n4061 , n4064 );
or ( n4467 , n4465 , n4466 );
xor ( n4468 , n4464 , n4467 );
and ( n4469 , n4082 , n4086 );
and ( n4470 , n4086 , n4090 );
and ( n4471 , n4082 , n4090 );
or ( n4472 , n4469 , n4470 , n4471 );
and ( n4473 , n4078 , n4091 );
and ( n4474 , n4091 , n4246 );
and ( n4475 , n4078 , n4246 );
or ( n4476 , n4473 , n4474 , n4475 );
xor ( n4477 , n4472 , n4476 );
and ( n4478 , n4096 , n4122 );
and ( n4479 , n4122 , n4245 );
and ( n4480 , n4096 , n4245 );
or ( n4481 , n4478 , n4479 , n4480 );
and ( n4482 , n4110 , n4111 );
and ( n4483 , n4111 , n4113 );
and ( n4484 , n4110 , n4113 );
or ( n4485 , n4482 , n4483 , n4484 );
and ( n4486 , n4100 , n4104 );
and ( n4487 , n4104 , n4121 );
and ( n4488 , n4100 , n4121 );
or ( n4489 , n4486 , n4487 , n4488 );
xor ( n4490 , n4485 , n4489 );
not ( n4491 , n533 );
and ( n4492 , n2406 , n533 );
nor ( n4493 , n4491 , n4492 );
xor ( n4494 , n4490 , n4493 );
xor ( n4495 , n4481 , n4494 );
and ( n4496 , n4127 , n4142 );
and ( n4497 , n4142 , n4244 );
and ( n4498 , n4127 , n4244 );
or ( n4499 , n4496 , n4497 , n4498 );
and ( n4500 , n4109 , n4114 );
and ( n4501 , n4114 , n4120 );
and ( n4502 , n4109 , n4120 );
or ( n4503 , n4500 , n4501 , n4502 );
and ( n4504 , n4131 , n4135 );
and ( n4505 , n4135 , n4141 );
and ( n4506 , n4131 , n4141 );
or ( n4507 , n4504 , n4505 , n4506 );
xor ( n4508 , n4503 , n4507 );
and ( n4509 , n4116 , n4117 );
and ( n4510 , n4117 , n4119 );
and ( n4511 , n4116 , n4119 );
or ( n4512 , n4509 , n4510 , n4511 );
and ( n4513 , n636 , n2138 );
and ( n4514 , n782 , n1864 );
xor ( n4515 , n4513 , n4514 );
and ( n4516 , n931 , n1753 );
xor ( n4517 , n4515 , n4516 );
xor ( n4518 , n4512 , n4517 );
and ( n4519 , n1088 , n1396 );
and ( n4520 , n1292 , n1302 );
xor ( n4521 , n4519 , n4520 );
and ( n4522 , n1516 , n1114 );
xor ( n4523 , n4521 , n4522 );
xor ( n4524 , n4518 , n4523 );
xor ( n4525 , n4508 , n4524 );
xor ( n4526 , n4499 , n4525 );
and ( n4527 , n4147 , n4152 );
and ( n4528 , n4152 , n4243 );
and ( n4529 , n4147 , n4243 );
or ( n4530 , n4527 , n4528 , n4529 );
and ( n4531 , n4137 , n4138 );
and ( n4532 , n4138 , n4140 );
and ( n4533 , n4137 , n4140 );
or ( n4534 , n4531 , n4532 , n4533 );
and ( n4535 , n4148 , n4149 );
and ( n4536 , n4149 , n4151 );
and ( n4537 , n4148 , n4151 );
or ( n4538 , n4535 , n4536 , n4537 );
xor ( n4539 , n4534 , n4538 );
and ( n4540 , n1730 , n852 );
and ( n4541 , n2001 , n714 );
xor ( n4542 , n4540 , n4541 );
and ( n4543 , n2286 , n651 );
xor ( n4544 , n4542 , n4543 );
xor ( n4545 , n4539 , n4544 );
xor ( n4546 , n4530 , n4545 );
and ( n4547 , n4154 , n4155 );
and ( n4548 , n4155 , n4242 );
and ( n4549 , n4154 , n4242 );
or ( n4550 , n4547 , n4548 , n4549 );
and ( n4551 , n2581 , n488 );
and ( n4552 , n2972 , n411 );
xor ( n4553 , n4551 , n4552 );
and ( n4554 , n3445 , n375 );
xor ( n4555 , n4553 , n4554 );
xor ( n4556 , n4550 , n4555 );
and ( n4557 , n3844 , n312 );
and ( n4558 , n4241 , n288 );
xor ( n4559 , n4557 , n4558 );
and ( n4560 , n4173 , n4177 );
and ( n4561 , n4177 , n4181 );
and ( n4562 , n4173 , n4181 );
or ( n4563 , n4560 , n4561 , n4562 );
and ( n4564 , n4169 , n4182 );
and ( n4565 , n4182 , n4228 );
and ( n4566 , n4169 , n4228 );
or ( n4567 , n4564 , n4565 , n4566 );
xor ( n4568 , n4563 , n4567 );
and ( n4569 , n4184 , n4210 );
and ( n4570 , n4210 , n4227 );
and ( n4571 , n4184 , n4227 );
or ( n4572 , n4569 , n4570 , n4571 );
and ( n4573 , n4204 , n4205 );
and ( n4574 , n4205 , n4207 );
and ( n4575 , n4204 , n4207 );
or ( n4576 , n4573 , n4574 , n4575 );
and ( n4577 , n4188 , n4192 );
and ( n4578 , n4192 , n4209 );
and ( n4579 , n4188 , n4209 );
or ( n4580 , n4577 , n4578 , n4579 );
xor ( n4581 , n4576 , n4580 );
and ( n4582 , n2206 , n607 );
not ( n4583 , n607 );
nor ( n4584 , n4582 , n4583 );
xor ( n4585 , n4581 , n4584 );
xor ( n4586 , n4572 , n4585 );
and ( n4587 , n4214 , n4226 );
and ( n4588 , n4218 , n4219 );
and ( n4589 , n4219 , n4225 );
and ( n4590 , n4218 , n4225 );
or ( n4591 , n4588 , n4589 , n4590 );
and ( n4592 , n4197 , n4202 );
and ( n4593 , n4202 , n4208 );
and ( n4594 , n4197 , n4208 );
or ( n4595 , n4592 , n4593 , n4594 );
xor ( n4596 , n4591 , n4595 );
and ( n4597 , n4198 , n4199 );
and ( n4598 , n4199 , n4201 );
and ( n4599 , n4198 , n4201 );
or ( n4600 , n4597 , n4598 , n4599 );
and ( n4601 , n1458 , n1048 );
and ( n4602 , n1713 , n905 );
xor ( n4603 , n4601 , n4602 );
and ( n4604 , n1935 , n766 );
xor ( n4605 , n4603 , n4604 );
xor ( n4606 , n4600 , n4605 );
and ( n4607 , n917 , n1685 );
and ( n4608 , n1077 , n1497 );
xor ( n4609 , n4607 , n4608 );
and ( n4610 , n1277 , n1261 );
xor ( n4611 , n4609 , n4610 );
xor ( n4612 , n4606 , n4611 );
xor ( n4613 , n4596 , n4612 );
xor ( n4614 , n4587 , n4613 );
and ( n4615 , n4221 , n4222 );
and ( n4616 , n4222 , n4224 );
and ( n4617 , n4221 , n4224 );
or ( n4618 , n4615 , n4616 , n4617 );
not ( n4619 , n521 );
and ( n4620 , n2563 , n521 );
nor ( n4621 , n4619 , n4620 );
and ( n4622 , n625 , n2271 );
xor ( n4623 , n4621 , n4622 );
and ( n4624 , n753 , n1975 );
xor ( n4625 , n4623 , n4624 );
xor ( n4626 , n4618 , n4625 );
xor ( n4627 , n4614 , n4626 );
xor ( n4628 , n4586 , n4627 );
xor ( n4629 , n4568 , n4628 );
and ( n4630 , n4160 , n4164 );
and ( n4631 , n4164 , n4229 );
and ( n4632 , n4160 , n4229 );
or ( n4633 , n4630 , n4631 , n4632 );
xor ( n4634 , n4629 , n4633 );
and ( n4635 , n4230 , n4234 );
and ( n4636 , n4235 , n4238 );
or ( n4637 , n4635 , n4636 );
xor ( n4638 , n4634 , n4637 );
buf ( n4639 , n4638 );
buf ( n4640 , n4639 );
and ( n4641 , n4640 , n279 );
xor ( n4642 , n4559 , n4641 );
xor ( n4643 , n4556 , n4642 );
xor ( n4644 , n4546 , n4643 );
xor ( n4645 , n4526 , n4644 );
xor ( n4646 , n4495 , n4645 );
xor ( n4647 , n4477 , n4646 );
and ( n4648 , n4069 , n4073 );
and ( n4649 , n4073 , n4247 );
and ( n4650 , n4069 , n4247 );
or ( n4651 , n4648 , n4649 , n4650 );
xor ( n4652 , n4647 , n4651 );
and ( n4653 , n4248 , n4252 );
and ( n4654 , n4253 , n4256 );
or ( n4655 , n4653 , n4654 );
xor ( n4656 , n4652 , n4655 );
buf ( n4657 , n4656 );
buf ( n4658 , n4657 );
not ( n4659 , n4658 );
nor ( n4660 , n4659 , n2598 );
xor ( n4661 , n4468 , n4660 );
and ( n4662 , n4065 , n4261 );
and ( n4663 , n4262 , n4265 );
or ( n4664 , n4662 , n4663 );
xor ( n4665 , n4661 , n4664 );
buf ( n4666 , n4665 );
buf ( n4667 , n4666 );
not ( n4668 , n4667 );
buf ( n4669 , n262 );
not ( n4670 , n4669 );
nor ( n4671 , n4668 , n4670 );
xor ( n4672 , n4382 , n4671 );
xor ( n4673 , n4277 , n4379 );
nor ( n4674 , n4269 , n4670 );
and ( n4675 , n4673 , n4674 );
xor ( n4676 , n4673 , n4674 );
xor ( n4677 , n4281 , n4377 );
nor ( n4678 , n3872 , n4670 );
and ( n4679 , n4677 , n4678 );
xor ( n4680 , n4677 , n4678 );
xor ( n4681 , n4285 , n4375 );
nor ( n4682 , n3473 , n4670 );
and ( n4683 , n4681 , n4682 );
xor ( n4684 , n4681 , n4682 );
xor ( n4685 , n4289 , n4373 );
nor ( n4686 , n3000 , n4670 );
and ( n4687 , n4685 , n4686 );
xor ( n4688 , n4685 , n4686 );
xor ( n4689 , n4293 , n4371 );
nor ( n4690 , n2688 , n4670 );
and ( n4691 , n4689 , n4690 );
xor ( n4692 , n4689 , n4690 );
xor ( n4693 , n4297 , n4369 );
nor ( n4694 , n3008 , n4670 );
and ( n4695 , n4693 , n4694 );
xor ( n4696 , n4693 , n4694 );
xor ( n4697 , n4301 , n4367 );
nor ( n4698 , n3017 , n4670 );
and ( n4699 , n4697 , n4698 );
xor ( n4700 , n4697 , n4698 );
xor ( n4701 , n4305 , n4365 );
nor ( n4702 , n3026 , n4670 );
and ( n4703 , n4701 , n4702 );
xor ( n4704 , n4701 , n4702 );
xor ( n4705 , n4309 , n4363 );
nor ( n4706 , n3035 , n4670 );
and ( n4707 , n4705 , n4706 );
xor ( n4708 , n4705 , n4706 );
xor ( n4709 , n4313 , n4361 );
nor ( n4710 , n3044 , n4670 );
and ( n4711 , n4709 , n4710 );
xor ( n4712 , n4709 , n4710 );
xor ( n4713 , n4317 , n4359 );
nor ( n4714 , n3053 , n4670 );
and ( n4715 , n4713 , n4714 );
xor ( n4716 , n4713 , n4714 );
xor ( n4717 , n4321 , n4357 );
nor ( n4718 , n3062 , n4670 );
and ( n4719 , n4717 , n4718 );
xor ( n4720 , n4717 , n4718 );
xor ( n4721 , n4325 , n4355 );
nor ( n4722 , n3071 , n4670 );
and ( n4723 , n4721 , n4722 );
xor ( n4724 , n4721 , n4722 );
xor ( n4725 , n4329 , n4353 );
nor ( n4726 , n3080 , n4670 );
and ( n4727 , n4725 , n4726 );
xor ( n4728 , n4725 , n4726 );
xor ( n4729 , n4333 , n4351 );
nor ( n4730 , n3089 , n4670 );
and ( n4731 , n4729 , n4730 );
xor ( n4732 , n4729 , n4730 );
xor ( n4733 , n4337 , n4349 );
nor ( n4734 , n3098 , n4670 );
and ( n4735 , n4733 , n4734 );
xor ( n4736 , n4733 , n4734 );
xor ( n4737 , n4342 , n4347 );
nor ( n4738 , n3107 , n4670 );
and ( n4739 , n4737 , n4738 );
xor ( n4740 , n4737 , n4738 );
xor ( n4741 , n4344 , n4345 );
buf ( n4742 , n4741 );
nor ( n4743 , n3116 , n4670 );
and ( n4744 , n4742 , n4743 );
xor ( n4745 , n4742 , n4743 );
nor ( n4746 , n3134 , n4271 );
buf ( n4747 , n4746 );
nor ( n4748 , n3125 , n4670 );
and ( n4749 , n4747 , n4748 );
buf ( n4750 , n4749 );
and ( n4751 , n4745 , n4750 );
or ( n4752 , n4744 , n4751 );
and ( n4753 , n4740 , n4752 );
or ( n4754 , n4739 , n4753 );
and ( n4755 , n4736 , n4754 );
or ( n4756 , n4735 , n4755 );
and ( n4757 , n4732 , n4756 );
or ( n4758 , n4731 , n4757 );
and ( n4759 , n4728 , n4758 );
or ( n4760 , n4727 , n4759 );
and ( n4761 , n4724 , n4760 );
or ( n4762 , n4723 , n4761 );
and ( n4763 , n4720 , n4762 );
or ( n4764 , n4719 , n4763 );
and ( n4765 , n4716 , n4764 );
or ( n4766 , n4715 , n4765 );
and ( n4767 , n4712 , n4766 );
or ( n4768 , n4711 , n4767 );
and ( n4769 , n4708 , n4768 );
or ( n4770 , n4707 , n4769 );
and ( n4771 , n4704 , n4770 );
or ( n4772 , n4703 , n4771 );
and ( n4773 , n4700 , n4772 );
or ( n4774 , n4699 , n4773 );
and ( n4775 , n4696 , n4774 );
or ( n4776 , n4695 , n4775 );
and ( n4777 , n4692 , n4776 );
or ( n4778 , n4691 , n4777 );
and ( n4779 , n4688 , n4778 );
or ( n4780 , n4687 , n4779 );
and ( n4781 , n4684 , n4780 );
or ( n4782 , n4683 , n4781 );
and ( n4783 , n4680 , n4782 );
or ( n4784 , n4679 , n4783 );
and ( n4785 , n4676 , n4784 );
or ( n4786 , n4675 , n4785 );
xor ( n4787 , n4672 , n4786 );
and ( n4788 , n285 , n662 );
nor ( n4789 , n663 , n4788 );
nor ( n4790 , n795 , n305 );
xor ( n4791 , n4789 , n4790 );
and ( n4792 , n4384 , n4385 );
and ( n4793 , n4386 , n4389 );
or ( n4794 , n4792 , n4793 );
xor ( n4795 , n4791 , n4794 );
nor ( n4796 , n952 , n336 );
xor ( n4797 , n4795 , n4796 );
and ( n4798 , n4390 , n4391 );
and ( n4799 , n4392 , n4395 );
or ( n4800 , n4798 , n4799 );
xor ( n4801 , n4797 , n4800 );
nor ( n4802 , n1126 , n386 );
xor ( n4803 , n4801 , n4802 );
and ( n4804 , n4396 , n4397 );
and ( n4805 , n4398 , n4401 );
or ( n4806 , n4804 , n4805 );
xor ( n4807 , n4803 , n4806 );
nor ( n4808 , n1318 , n458 );
xor ( n4809 , n4807 , n4808 );
and ( n4810 , n4402 , n4403 );
and ( n4811 , n4404 , n4407 );
or ( n4812 , n4810 , n4811 );
xor ( n4813 , n4809 , n4812 );
nor ( n4814 , n1534 , n551 );
xor ( n4815 , n4813 , n4814 );
and ( n4816 , n4408 , n4409 );
and ( n4817 , n4410 , n4413 );
or ( n4818 , n4816 , n4817 );
xor ( n4819 , n4815 , n4818 );
nor ( n4820 , n1771 , n665 );
xor ( n4821 , n4819 , n4820 );
and ( n4822 , n4414 , n4415 );
and ( n4823 , n4416 , n4419 );
or ( n4824 , n4822 , n4823 );
xor ( n4825 , n4821 , n4824 );
nor ( n4826 , n2025 , n797 );
xor ( n4827 , n4825 , n4826 );
and ( n4828 , n4420 , n4421 );
and ( n4829 , n4422 , n4425 );
or ( n4830 , n4828 , n4829 );
xor ( n4831 , n4827 , n4830 );
nor ( n4832 , n2300 , n954 );
xor ( n4833 , n4831 , n4832 );
and ( n4834 , n4426 , n4427 );
and ( n4835 , n4428 , n4431 );
or ( n4836 , n4834 , n4835 );
xor ( n4837 , n4833 , n4836 );
nor ( n4838 , n2596 , n1128 );
xor ( n4839 , n4837 , n4838 );
and ( n4840 , n4432 , n4433 );
and ( n4841 , n4434 , n4437 );
or ( n4842 , n4840 , n4841 );
xor ( n4843 , n4839 , n4842 );
nor ( n4844 , n2991 , n1320 );
xor ( n4845 , n4843 , n4844 );
and ( n4846 , n4438 , n4439 );
and ( n4847 , n4440 , n4443 );
or ( n4848 , n4846 , n4847 );
xor ( n4849 , n4845 , n4848 );
nor ( n4850 , n3464 , n1536 );
xor ( n4851 , n4849 , n4850 );
and ( n4852 , n4444 , n4445 );
and ( n4853 , n4446 , n4449 );
or ( n4854 , n4852 , n4853 );
xor ( n4855 , n4851 , n4854 );
nor ( n4856 , n3863 , n1773 );
xor ( n4857 , n4855 , n4856 );
and ( n4858 , n4450 , n4451 );
and ( n4859 , n4452 , n4455 );
or ( n4860 , n4858 , n4859 );
xor ( n4861 , n4857 , n4860 );
nor ( n4862 , n4260 , n2027 );
xor ( n4863 , n4861 , n4862 );
and ( n4864 , n4456 , n4457 );
and ( n4865 , n4458 , n4461 );
or ( n4866 , n4864 , n4865 );
xor ( n4867 , n4863 , n4866 );
nor ( n4868 , n4659 , n2302 );
xor ( n4869 , n4867 , n4868 );
and ( n4870 , n4462 , n4463 );
and ( n4871 , n4464 , n4467 );
or ( n4872 , n4870 , n4871 );
xor ( n4873 , n4869 , n4872 );
and ( n4874 , n4485 , n4489 );
and ( n4875 , n4489 , n4493 );
and ( n4876 , n4485 , n4493 );
or ( n4877 , n4874 , n4875 , n4876 );
and ( n4878 , n4481 , n4494 );
and ( n4879 , n4494 , n4645 );
and ( n4880 , n4481 , n4645 );
or ( n4881 , n4878 , n4879 , n4880 );
xor ( n4882 , n4877 , n4881 );
and ( n4883 , n4499 , n4525 );
and ( n4884 , n4525 , n4644 );
and ( n4885 , n4499 , n4644 );
or ( n4886 , n4883 , n4884 , n4885 );
and ( n4887 , n4513 , n4514 );
and ( n4888 , n4514 , n4516 );
and ( n4889 , n4513 , n4516 );
or ( n4890 , n4887 , n4888 , n4889 );
and ( n4891 , n4503 , n4507 );
and ( n4892 , n4507 , n4524 );
and ( n4893 , n4503 , n4524 );
or ( n4894 , n4891 , n4892 , n4893 );
xor ( n4895 , n4890 , n4894 );
not ( n4896 , n636 );
and ( n4897 , n2406 , n636 );
nor ( n4898 , n4896 , n4897 );
xor ( n4899 , n4895 , n4898 );
xor ( n4900 , n4886 , n4899 );
and ( n4901 , n4530 , n4545 );
and ( n4902 , n4545 , n4643 );
and ( n4903 , n4530 , n4643 );
or ( n4904 , n4901 , n4902 , n4903 );
and ( n4905 , n4512 , n4517 );
and ( n4906 , n4517 , n4523 );
and ( n4907 , n4512 , n4523 );
or ( n4908 , n4905 , n4906 , n4907 );
and ( n4909 , n4534 , n4538 );
and ( n4910 , n4538 , n4544 );
and ( n4911 , n4534 , n4544 );
or ( n4912 , n4909 , n4910 , n4911 );
xor ( n4913 , n4908 , n4912 );
and ( n4914 , n4519 , n4520 );
and ( n4915 , n4520 , n4522 );
and ( n4916 , n4519 , n4522 );
or ( n4917 , n4914 , n4915 , n4916 );
and ( n4918 , n782 , n2138 );
and ( n4919 , n931 , n1864 );
xor ( n4920 , n4918 , n4919 );
and ( n4921 , n1088 , n1753 );
xor ( n4922 , n4920 , n4921 );
xor ( n4923 , n4917 , n4922 );
and ( n4924 , n1292 , n1396 );
and ( n4925 , n1516 , n1302 );
xor ( n4926 , n4924 , n4925 );
and ( n4927 , n1730 , n1114 );
xor ( n4928 , n4926 , n4927 );
xor ( n4929 , n4923 , n4928 );
xor ( n4930 , n4913 , n4929 );
xor ( n4931 , n4904 , n4930 );
and ( n4932 , n4550 , n4555 );
and ( n4933 , n4555 , n4642 );
and ( n4934 , n4550 , n4642 );
or ( n4935 , n4932 , n4933 , n4934 );
and ( n4936 , n4540 , n4541 );
and ( n4937 , n4541 , n4543 );
and ( n4938 , n4540 , n4543 );
or ( n4939 , n4936 , n4937 , n4938 );
and ( n4940 , n4551 , n4552 );
and ( n4941 , n4552 , n4554 );
and ( n4942 , n4551 , n4554 );
or ( n4943 , n4940 , n4941 , n4942 );
xor ( n4944 , n4939 , n4943 );
and ( n4945 , n2001 , n852 );
and ( n4946 , n2286 , n714 );
xor ( n4947 , n4945 , n4946 );
and ( n4948 , n2581 , n651 );
xor ( n4949 , n4947 , n4948 );
xor ( n4950 , n4944 , n4949 );
xor ( n4951 , n4935 , n4950 );
and ( n4952 , n4557 , n4558 );
and ( n4953 , n4558 , n4641 );
and ( n4954 , n4557 , n4641 );
or ( n4955 , n4952 , n4953 , n4954 );
and ( n4956 , n2972 , n488 );
and ( n4957 , n3445 , n411 );
xor ( n4958 , n4956 , n4957 );
and ( n4959 , n3844 , n375 );
xor ( n4960 , n4958 , n4959 );
xor ( n4961 , n4955 , n4960 );
and ( n4962 , n4241 , n312 );
and ( n4963 , n4640 , n288 );
xor ( n4964 , n4962 , n4963 );
and ( n4965 , n4576 , n4580 );
and ( n4966 , n4580 , n4584 );
and ( n4967 , n4576 , n4584 );
or ( n4968 , n4965 , n4966 , n4967 );
and ( n4969 , n4572 , n4585 );
and ( n4970 , n4585 , n4627 );
and ( n4971 , n4572 , n4627 );
or ( n4972 , n4969 , n4970 , n4971 );
xor ( n4973 , n4968 , n4972 );
and ( n4974 , n4587 , n4613 );
and ( n4975 , n4613 , n4626 );
and ( n4976 , n4587 , n4626 );
or ( n4977 , n4974 , n4975 , n4976 );
and ( n4978 , n4601 , n4602 );
and ( n4979 , n4602 , n4604 );
and ( n4980 , n4601 , n4604 );
or ( n4981 , n4978 , n4979 , n4980 );
and ( n4982 , n4591 , n4595 );
and ( n4983 , n4595 , n4612 );
and ( n4984 , n4591 , n4612 );
or ( n4985 , n4982 , n4983 , n4984 );
xor ( n4986 , n4981 , n4985 );
and ( n4987 , n2206 , n766 );
not ( n4988 , n766 );
nor ( n4989 , n4987 , n4988 );
xor ( n4990 , n4986 , n4989 );
xor ( n4991 , n4977 , n4990 );
and ( n4992 , n4600 , n4605 );
and ( n4993 , n4605 , n4611 );
and ( n4994 , n4600 , n4611 );
or ( n4995 , n4992 , n4993 , n4994 );
and ( n4996 , n4618 , n4625 );
xor ( n4997 , n4995 , n4996 );
and ( n4998 , n4607 , n4608 );
and ( n4999 , n4608 , n4610 );
and ( n5000 , n4607 , n4610 );
or ( n5001 , n4998 , n4999 , n5000 );
and ( n5002 , n917 , n1975 );
and ( n5003 , n1077 , n1685 );
xor ( n5004 , n5002 , n5003 );
and ( n5005 , n1277 , n1497 );
xor ( n5006 , n5004 , n5005 );
xor ( n5007 , n5001 , n5006 );
and ( n5008 , n1458 , n1261 );
and ( n5009 , n1713 , n1048 );
xor ( n5010 , n5008 , n5009 );
and ( n5011 , n1935 , n905 );
xor ( n5012 , n5010 , n5011 );
xor ( n5013 , n5007 , n5012 );
xor ( n5014 , n4997 , n5013 );
and ( n5015 , n4621 , n4622 );
and ( n5016 , n4622 , n4624 );
and ( n5017 , n4621 , n4624 );
or ( n5018 , n5015 , n5016 , n5017 );
not ( n5019 , n625 );
and ( n5020 , n2563 , n625 );
nor ( n5021 , n5019 , n5020 );
and ( n5022 , n753 , n2271 );
xor ( n5023 , n5021 , n5022 );
xor ( n5024 , n5018 , n5023 );
xor ( n5025 , n5014 , n5024 );
xor ( n5026 , n4991 , n5025 );
xor ( n5027 , n4973 , n5026 );
and ( n5028 , n4563 , n4567 );
and ( n5029 , n4567 , n4628 );
and ( n5030 , n4563 , n4628 );
or ( n5031 , n5028 , n5029 , n5030 );
xor ( n5032 , n5027 , n5031 );
and ( n5033 , n4629 , n4633 );
and ( n5034 , n4634 , n4637 );
or ( n5035 , n5033 , n5034 );
xor ( n5036 , n5032 , n5035 );
buf ( n5037 , n5036 );
buf ( n5038 , n5037 );
and ( n5039 , n5038 , n279 );
xor ( n5040 , n4964 , n5039 );
xor ( n5041 , n4961 , n5040 );
xor ( n5042 , n4951 , n5041 );
xor ( n5043 , n4931 , n5042 );
xor ( n5044 , n4900 , n5043 );
xor ( n5045 , n4882 , n5044 );
and ( n5046 , n4472 , n4476 );
and ( n5047 , n4476 , n4646 );
and ( n5048 , n4472 , n4646 );
or ( n5049 , n5046 , n5047 , n5048 );
xor ( n5050 , n5045 , n5049 );
and ( n5051 , n4647 , n4651 );
and ( n5052 , n4652 , n4655 );
or ( n5053 , n5051 , n5052 );
xor ( n5054 , n5050 , n5053 );
buf ( n5055 , n5054 );
buf ( n5056 , n5055 );
not ( n5057 , n5056 );
nor ( n5058 , n5057 , n2598 );
xor ( n5059 , n4873 , n5058 );
and ( n5060 , n4468 , n4660 );
and ( n5061 , n4661 , n4664 );
or ( n5062 , n5060 , n5061 );
xor ( n5063 , n5059 , n5062 );
buf ( n5064 , n5063 );
buf ( n5065 , n5064 );
not ( n5066 , n5065 );
buf ( n5067 , n263 );
not ( n5068 , n5067 );
nor ( n5069 , n5066 , n5068 );
xor ( n5070 , n4787 , n5069 );
xor ( n5071 , n4676 , n4784 );
nor ( n5072 , n4668 , n5068 );
and ( n5073 , n5071 , n5072 );
xor ( n5074 , n5071 , n5072 );
xor ( n5075 , n4680 , n4782 );
nor ( n5076 , n4269 , n5068 );
and ( n5077 , n5075 , n5076 );
xor ( n5078 , n5075 , n5076 );
xor ( n5079 , n4684 , n4780 );
nor ( n5080 , n3872 , n5068 );
and ( n5081 , n5079 , n5080 );
xor ( n5082 , n5079 , n5080 );
xor ( n5083 , n4688 , n4778 );
nor ( n5084 , n3473 , n5068 );
and ( n5085 , n5083 , n5084 );
xor ( n5086 , n5083 , n5084 );
xor ( n5087 , n4692 , n4776 );
nor ( n5088 , n3000 , n5068 );
and ( n5089 , n5087 , n5088 );
xor ( n5090 , n5087 , n5088 );
xor ( n5091 , n4696 , n4774 );
nor ( n5092 , n2688 , n5068 );
and ( n5093 , n5091 , n5092 );
xor ( n5094 , n5091 , n5092 );
xor ( n5095 , n4700 , n4772 );
nor ( n5096 , n3008 , n5068 );
and ( n5097 , n5095 , n5096 );
xor ( n5098 , n5095 , n5096 );
xor ( n5099 , n4704 , n4770 );
nor ( n5100 , n3017 , n5068 );
and ( n5101 , n5099 , n5100 );
xor ( n5102 , n5099 , n5100 );
xor ( n5103 , n4708 , n4768 );
nor ( n5104 , n3026 , n5068 );
and ( n5105 , n5103 , n5104 );
xor ( n5106 , n5103 , n5104 );
xor ( n5107 , n4712 , n4766 );
nor ( n5108 , n3035 , n5068 );
and ( n5109 , n5107 , n5108 );
xor ( n5110 , n5107 , n5108 );
xor ( n5111 , n4716 , n4764 );
nor ( n5112 , n3044 , n5068 );
and ( n5113 , n5111 , n5112 );
xor ( n5114 , n5111 , n5112 );
xor ( n5115 , n4720 , n4762 );
nor ( n5116 , n3053 , n5068 );
and ( n5117 , n5115 , n5116 );
xor ( n5118 , n5115 , n5116 );
xor ( n5119 , n4724 , n4760 );
nor ( n5120 , n3062 , n5068 );
and ( n5121 , n5119 , n5120 );
xor ( n5122 , n5119 , n5120 );
xor ( n5123 , n4728 , n4758 );
nor ( n5124 , n3071 , n5068 );
and ( n5125 , n5123 , n5124 );
xor ( n5126 , n5123 , n5124 );
xor ( n5127 , n4732 , n4756 );
nor ( n5128 , n3080 , n5068 );
and ( n5129 , n5127 , n5128 );
xor ( n5130 , n5127 , n5128 );
xor ( n5131 , n4736 , n4754 );
nor ( n5132 , n3089 , n5068 );
and ( n5133 , n5131 , n5132 );
xor ( n5134 , n5131 , n5132 );
xor ( n5135 , n4740 , n4752 );
nor ( n5136 , n3098 , n5068 );
and ( n5137 , n5135 , n5136 );
xor ( n5138 , n5135 , n5136 );
xor ( n5139 , n4745 , n4750 );
nor ( n5140 , n3107 , n5068 );
and ( n5141 , n5139 , n5140 );
xor ( n5142 , n5139 , n5140 );
xor ( n5143 , n4747 , n4748 );
buf ( n5144 , n5143 );
nor ( n5145 , n3116 , n5068 );
and ( n5146 , n5144 , n5145 );
xor ( n5147 , n5144 , n5145 );
nor ( n5148 , n3134 , n4670 );
buf ( n5149 , n5148 );
nor ( n5150 , n3125 , n5068 );
and ( n5151 , n5149 , n5150 );
buf ( n5152 , n5151 );
and ( n5153 , n5147 , n5152 );
or ( n5154 , n5146 , n5153 );
and ( n5155 , n5142 , n5154 );
or ( n5156 , n5141 , n5155 );
and ( n5157 , n5138 , n5156 );
or ( n5158 , n5137 , n5157 );
and ( n5159 , n5134 , n5158 );
or ( n5160 , n5133 , n5159 );
and ( n5161 , n5130 , n5160 );
or ( n5162 , n5129 , n5161 );
and ( n5163 , n5126 , n5162 );
or ( n5164 , n5125 , n5163 );
and ( n5165 , n5122 , n5164 );
or ( n5166 , n5121 , n5165 );
and ( n5167 , n5118 , n5166 );
or ( n5168 , n5117 , n5167 );
and ( n5169 , n5114 , n5168 );
or ( n5170 , n5113 , n5169 );
and ( n5171 , n5110 , n5170 );
or ( n5172 , n5109 , n5171 );
and ( n5173 , n5106 , n5172 );
or ( n5174 , n5105 , n5173 );
and ( n5175 , n5102 , n5174 );
or ( n5176 , n5101 , n5175 );
and ( n5177 , n5098 , n5176 );
or ( n5178 , n5097 , n5177 );
and ( n5179 , n5094 , n5178 );
or ( n5180 , n5093 , n5179 );
and ( n5181 , n5090 , n5180 );
or ( n5182 , n5089 , n5181 );
and ( n5183 , n5086 , n5182 );
or ( n5184 , n5085 , n5183 );
and ( n5185 , n5082 , n5184 );
or ( n5186 , n5081 , n5185 );
and ( n5187 , n5078 , n5186 );
or ( n5188 , n5077 , n5187 );
and ( n5189 , n5074 , n5188 );
or ( n5190 , n5073 , n5189 );
xor ( n5191 , n5070 , n5190 );
and ( n5192 , n285 , n794 );
nor ( n5193 , n795 , n5192 );
nor ( n5194 , n952 , n305 );
xor ( n5195 , n5193 , n5194 );
and ( n5196 , n4789 , n4790 );
and ( n5197 , n4791 , n4794 );
or ( n5198 , n5196 , n5197 );
xor ( n5199 , n5195 , n5198 );
nor ( n5200 , n1126 , n336 );
xor ( n5201 , n5199 , n5200 );
and ( n5202 , n4795 , n4796 );
and ( n5203 , n4797 , n4800 );
or ( n5204 , n5202 , n5203 );
xor ( n5205 , n5201 , n5204 );
nor ( n5206 , n1318 , n386 );
xor ( n5207 , n5205 , n5206 );
and ( n5208 , n4801 , n4802 );
and ( n5209 , n4803 , n4806 );
or ( n5210 , n5208 , n5209 );
xor ( n5211 , n5207 , n5210 );
nor ( n5212 , n1534 , n458 );
xor ( n5213 , n5211 , n5212 );
and ( n5214 , n4807 , n4808 );
and ( n5215 , n4809 , n4812 );
or ( n5216 , n5214 , n5215 );
xor ( n5217 , n5213 , n5216 );
nor ( n5218 , n1771 , n551 );
xor ( n5219 , n5217 , n5218 );
and ( n5220 , n4813 , n4814 );
and ( n5221 , n4815 , n4818 );
or ( n5222 , n5220 , n5221 );
xor ( n5223 , n5219 , n5222 );
nor ( n5224 , n2025 , n665 );
xor ( n5225 , n5223 , n5224 );
and ( n5226 , n4819 , n4820 );
and ( n5227 , n4821 , n4824 );
or ( n5228 , n5226 , n5227 );
xor ( n5229 , n5225 , n5228 );
nor ( n5230 , n2300 , n797 );
xor ( n5231 , n5229 , n5230 );
and ( n5232 , n4825 , n4826 );
and ( n5233 , n4827 , n4830 );
or ( n5234 , n5232 , n5233 );
xor ( n5235 , n5231 , n5234 );
nor ( n5236 , n2596 , n954 );
xor ( n5237 , n5235 , n5236 );
and ( n5238 , n4831 , n4832 );
and ( n5239 , n4833 , n4836 );
or ( n5240 , n5238 , n5239 );
xor ( n5241 , n5237 , n5240 );
nor ( n5242 , n2991 , n1128 );
xor ( n5243 , n5241 , n5242 );
and ( n5244 , n4837 , n4838 );
and ( n5245 , n4839 , n4842 );
or ( n5246 , n5244 , n5245 );
xor ( n5247 , n5243 , n5246 );
nor ( n5248 , n3464 , n1320 );
xor ( n5249 , n5247 , n5248 );
and ( n5250 , n4843 , n4844 );
and ( n5251 , n4845 , n4848 );
or ( n5252 , n5250 , n5251 );
xor ( n5253 , n5249 , n5252 );
nor ( n5254 , n3863 , n1536 );
xor ( n5255 , n5253 , n5254 );
and ( n5256 , n4849 , n4850 );
and ( n5257 , n4851 , n4854 );
or ( n5258 , n5256 , n5257 );
xor ( n5259 , n5255 , n5258 );
nor ( n5260 , n4260 , n1773 );
xor ( n5261 , n5259 , n5260 );
and ( n5262 , n4855 , n4856 );
and ( n5263 , n4857 , n4860 );
or ( n5264 , n5262 , n5263 );
xor ( n5265 , n5261 , n5264 );
nor ( n5266 , n4659 , n2027 );
xor ( n5267 , n5265 , n5266 );
and ( n5268 , n4861 , n4862 );
and ( n5269 , n4863 , n4866 );
or ( n5270 , n5268 , n5269 );
xor ( n5271 , n5267 , n5270 );
nor ( n5272 , n5057 , n2302 );
xor ( n5273 , n5271 , n5272 );
and ( n5274 , n4867 , n4868 );
and ( n5275 , n4869 , n4872 );
or ( n5276 , n5274 , n5275 );
xor ( n5277 , n5273 , n5276 );
and ( n5278 , n4890 , n4894 );
and ( n5279 , n4894 , n4898 );
and ( n5280 , n4890 , n4898 );
or ( n5281 , n5278 , n5279 , n5280 );
and ( n5282 , n4886 , n4899 );
and ( n5283 , n4899 , n5043 );
and ( n5284 , n4886 , n5043 );
or ( n5285 , n5282 , n5283 , n5284 );
xor ( n5286 , n5281 , n5285 );
and ( n5287 , n4904 , n4930 );
and ( n5288 , n4930 , n5042 );
and ( n5289 , n4904 , n5042 );
or ( n5290 , n5287 , n5288 , n5289 );
and ( n5291 , n4918 , n4919 );
and ( n5292 , n4919 , n4921 );
and ( n5293 , n4918 , n4921 );
or ( n5294 , n5291 , n5292 , n5293 );
and ( n5295 , n4908 , n4912 );
and ( n5296 , n4912 , n4929 );
and ( n5297 , n4908 , n4929 );
or ( n5298 , n5295 , n5296 , n5297 );
xor ( n5299 , n5294 , n5298 );
not ( n5300 , n782 );
and ( n5301 , n2406 , n782 );
nor ( n5302 , n5300 , n5301 );
xor ( n5303 , n5299 , n5302 );
xor ( n5304 , n5290 , n5303 );
and ( n5305 , n4935 , n4950 );
and ( n5306 , n4950 , n5041 );
and ( n5307 , n4935 , n5041 );
or ( n5308 , n5305 , n5306 , n5307 );
and ( n5309 , n4917 , n4922 );
and ( n5310 , n4922 , n4928 );
and ( n5311 , n4917 , n4928 );
or ( n5312 , n5309 , n5310 , n5311 );
and ( n5313 , n4939 , n4943 );
and ( n5314 , n4943 , n4949 );
and ( n5315 , n4939 , n4949 );
or ( n5316 , n5313 , n5314 , n5315 );
xor ( n5317 , n5312 , n5316 );
and ( n5318 , n4924 , n4925 );
and ( n5319 , n4925 , n4927 );
and ( n5320 , n4924 , n4927 );
or ( n5321 , n5318 , n5319 , n5320 );
and ( n5322 , n931 , n2138 );
and ( n5323 , n1088 , n1864 );
xor ( n5324 , n5322 , n5323 );
and ( n5325 , n1292 , n1753 );
xor ( n5326 , n5324 , n5325 );
xor ( n5327 , n5321 , n5326 );
and ( n5328 , n1516 , n1396 );
and ( n5329 , n1730 , n1302 );
xor ( n5330 , n5328 , n5329 );
and ( n5331 , n2001 , n1114 );
xor ( n5332 , n5330 , n5331 );
xor ( n5333 , n5327 , n5332 );
xor ( n5334 , n5317 , n5333 );
xor ( n5335 , n5308 , n5334 );
and ( n5336 , n4955 , n4960 );
and ( n5337 , n4960 , n5040 );
and ( n5338 , n4955 , n5040 );
or ( n5339 , n5336 , n5337 , n5338 );
and ( n5340 , n4945 , n4946 );
and ( n5341 , n4946 , n4948 );
and ( n5342 , n4945 , n4948 );
or ( n5343 , n5340 , n5341 , n5342 );
and ( n5344 , n4956 , n4957 );
and ( n5345 , n4957 , n4959 );
and ( n5346 , n4956 , n4959 );
or ( n5347 , n5344 , n5345 , n5346 );
xor ( n5348 , n5343 , n5347 );
and ( n5349 , n2286 , n852 );
and ( n5350 , n2581 , n714 );
xor ( n5351 , n5349 , n5350 );
and ( n5352 , n2972 , n651 );
xor ( n5353 , n5351 , n5352 );
xor ( n5354 , n5348 , n5353 );
xor ( n5355 , n5339 , n5354 );
and ( n5356 , n4962 , n4963 );
and ( n5357 , n4963 , n5039 );
and ( n5358 , n4962 , n5039 );
or ( n5359 , n5356 , n5357 , n5358 );
and ( n5360 , n3445 , n488 );
and ( n5361 , n3844 , n411 );
xor ( n5362 , n5360 , n5361 );
and ( n5363 , n4241 , n375 );
xor ( n5364 , n5362 , n5363 );
xor ( n5365 , n5359 , n5364 );
and ( n5366 , n4640 , n312 );
and ( n5367 , n5038 , n288 );
xor ( n5368 , n5366 , n5367 );
and ( n5369 , n4981 , n4985 );
and ( n5370 , n4985 , n4989 );
and ( n5371 , n4981 , n4989 );
or ( n5372 , n5369 , n5370 , n5371 );
and ( n5373 , n4977 , n4990 );
and ( n5374 , n4990 , n5025 );
and ( n5375 , n4977 , n5025 );
or ( n5376 , n5373 , n5374 , n5375 );
xor ( n5377 , n5372 , n5376 );
and ( n5378 , n5014 , n5024 );
and ( n5379 , n5008 , n5009 );
and ( n5380 , n5009 , n5011 );
and ( n5381 , n5008 , n5011 );
or ( n5382 , n5379 , n5380 , n5381 );
and ( n5383 , n4995 , n4996 );
and ( n5384 , n4996 , n5013 );
and ( n5385 , n4995 , n5013 );
or ( n5386 , n5383 , n5384 , n5385 );
xor ( n5387 , n5382 , n5386 );
and ( n5388 , n2206 , n905 );
not ( n5389 , n905 );
nor ( n5390 , n5388 , n5389 );
xor ( n5391 , n5387 , n5390 );
xor ( n5392 , n5378 , n5391 );
and ( n5393 , n5001 , n5006 );
and ( n5394 , n5006 , n5012 );
and ( n5395 , n5001 , n5012 );
or ( n5396 , n5393 , n5394 , n5395 );
and ( n5397 , n5018 , n5023 );
xor ( n5398 , n5396 , n5397 );
and ( n5399 , n5002 , n5003 );
and ( n5400 , n5003 , n5005 );
and ( n5401 , n5002 , n5005 );
or ( n5402 , n5399 , n5400 , n5401 );
and ( n5403 , n1458 , n1497 );
and ( n5404 , n1713 , n1261 );
xor ( n5405 , n5403 , n5404 );
and ( n5406 , n1935 , n1048 );
xor ( n5407 , n5405 , n5406 );
xor ( n5408 , n5402 , n5407 );
and ( n5409 , n917 , n2271 );
and ( n5410 , n1077 , n1975 );
xor ( n5411 , n5409 , n5410 );
and ( n5412 , n1277 , n1685 );
xor ( n5413 , n5411 , n5412 );
xor ( n5414 , n5408 , n5413 );
xor ( n5415 , n5398 , n5414 );
and ( n5416 , n5021 , n5022 );
not ( n5417 , n753 );
and ( n5418 , n2563 , n753 );
nor ( n5419 , n5417 , n5418 );
xor ( n5420 , n5416 , n5419 );
xor ( n5421 , n5415 , n5420 );
xor ( n5422 , n5392 , n5421 );
xor ( n5423 , n5377 , n5422 );
and ( n5424 , n4968 , n4972 );
and ( n5425 , n4972 , n5026 );
and ( n5426 , n4968 , n5026 );
or ( n5427 , n5424 , n5425 , n5426 );
xor ( n5428 , n5423 , n5427 );
and ( n5429 , n5027 , n5031 );
and ( n5430 , n5032 , n5035 );
or ( n5431 , n5429 , n5430 );
xor ( n5432 , n5428 , n5431 );
buf ( n5433 , n5432 );
buf ( n5434 , n5433 );
and ( n5435 , n5434 , n279 );
xor ( n5436 , n5368 , n5435 );
xor ( n5437 , n5365 , n5436 );
xor ( n5438 , n5355 , n5437 );
xor ( n5439 , n5335 , n5438 );
xor ( n5440 , n5304 , n5439 );
xor ( n5441 , n5286 , n5440 );
and ( n5442 , n4877 , n4881 );
and ( n5443 , n4881 , n5044 );
and ( n5444 , n4877 , n5044 );
or ( n5445 , n5442 , n5443 , n5444 );
xor ( n5446 , n5441 , n5445 );
and ( n5447 , n5045 , n5049 );
and ( n5448 , n5050 , n5053 );
or ( n5449 , n5447 , n5448 );
xor ( n5450 , n5446 , n5449 );
buf ( n5451 , n5450 );
buf ( n5452 , n5451 );
not ( n5453 , n5452 );
nor ( n5454 , n5453 , n2598 );
xor ( n5455 , n5277 , n5454 );
and ( n5456 , n4873 , n5058 );
and ( n5457 , n5059 , n5062 );
or ( n5458 , n5456 , n5457 );
xor ( n5459 , n5455 , n5458 );
buf ( n5460 , n5459 );
buf ( n5461 , n5460 );
not ( n5462 , n5461 );
buf ( n5463 , n264 );
not ( n5464 , n5463 );
nor ( n5465 , n5462 , n5464 );
xor ( n5466 , n5191 , n5465 );
xor ( n5467 , n5074 , n5188 );
nor ( n5468 , n5066 , n5464 );
and ( n5469 , n5467 , n5468 );
xor ( n5470 , n5467 , n5468 );
xor ( n5471 , n5078 , n5186 );
nor ( n5472 , n4668 , n5464 );
and ( n5473 , n5471 , n5472 );
xor ( n5474 , n5471 , n5472 );
xor ( n5475 , n5082 , n5184 );
nor ( n5476 , n4269 , n5464 );
and ( n5477 , n5475 , n5476 );
xor ( n5478 , n5475 , n5476 );
xor ( n5479 , n5086 , n5182 );
nor ( n5480 , n3872 , n5464 );
and ( n5481 , n5479 , n5480 );
xor ( n5482 , n5479 , n5480 );
xor ( n5483 , n5090 , n5180 );
nor ( n5484 , n3473 , n5464 );
and ( n5485 , n5483 , n5484 );
xor ( n5486 , n5483 , n5484 );
xor ( n5487 , n5094 , n5178 );
nor ( n5488 , n3000 , n5464 );
and ( n5489 , n5487 , n5488 );
xor ( n5490 , n5487 , n5488 );
xor ( n5491 , n5098 , n5176 );
nor ( n5492 , n2688 , n5464 );
and ( n5493 , n5491 , n5492 );
xor ( n5494 , n5491 , n5492 );
xor ( n5495 , n5102 , n5174 );
nor ( n5496 , n3008 , n5464 );
and ( n5497 , n5495 , n5496 );
xor ( n5498 , n5495 , n5496 );
xor ( n5499 , n5106 , n5172 );
nor ( n5500 , n3017 , n5464 );
and ( n5501 , n5499 , n5500 );
xor ( n5502 , n5499 , n5500 );
xor ( n5503 , n5110 , n5170 );
nor ( n5504 , n3026 , n5464 );
and ( n5505 , n5503 , n5504 );
xor ( n5506 , n5503 , n5504 );
xor ( n5507 , n5114 , n5168 );
nor ( n5508 , n3035 , n5464 );
and ( n5509 , n5507 , n5508 );
xor ( n5510 , n5507 , n5508 );
xor ( n5511 , n5118 , n5166 );
nor ( n5512 , n3044 , n5464 );
and ( n5513 , n5511 , n5512 );
xor ( n5514 , n5511 , n5512 );
xor ( n5515 , n5122 , n5164 );
nor ( n5516 , n3053 , n5464 );
and ( n5517 , n5515 , n5516 );
xor ( n5518 , n5515 , n5516 );
xor ( n5519 , n5126 , n5162 );
nor ( n5520 , n3062 , n5464 );
and ( n5521 , n5519 , n5520 );
xor ( n5522 , n5519 , n5520 );
xor ( n5523 , n5130 , n5160 );
nor ( n5524 , n3071 , n5464 );
and ( n5525 , n5523 , n5524 );
xor ( n5526 , n5523 , n5524 );
xor ( n5527 , n5134 , n5158 );
nor ( n5528 , n3080 , n5464 );
and ( n5529 , n5527 , n5528 );
xor ( n5530 , n5527 , n5528 );
xor ( n5531 , n5138 , n5156 );
nor ( n5532 , n3089 , n5464 );
and ( n5533 , n5531 , n5532 );
xor ( n5534 , n5531 , n5532 );
xor ( n5535 , n5142 , n5154 );
nor ( n5536 , n3098 , n5464 );
and ( n5537 , n5535 , n5536 );
xor ( n5538 , n5535 , n5536 );
xor ( n5539 , n5147 , n5152 );
nor ( n5540 , n3107 , n5464 );
and ( n5541 , n5539 , n5540 );
xor ( n5542 , n5539 , n5540 );
xor ( n5543 , n5149 , n5150 );
buf ( n5544 , n5543 );
nor ( n5545 , n3116 , n5464 );
and ( n5546 , n5544 , n5545 );
xor ( n5547 , n5544 , n5545 );
nor ( n5548 , n3134 , n5068 );
buf ( n5549 , n5548 );
nor ( n5550 , n3125 , n5464 );
and ( n5551 , n5549 , n5550 );
buf ( n5552 , n5551 );
and ( n5553 , n5547 , n5552 );
or ( n5554 , n5546 , n5553 );
and ( n5555 , n5542 , n5554 );
or ( n5556 , n5541 , n5555 );
and ( n5557 , n5538 , n5556 );
or ( n5558 , n5537 , n5557 );
and ( n5559 , n5534 , n5558 );
or ( n5560 , n5533 , n5559 );
and ( n5561 , n5530 , n5560 );
or ( n5562 , n5529 , n5561 );
and ( n5563 , n5526 , n5562 );
or ( n5564 , n5525 , n5563 );
and ( n5565 , n5522 , n5564 );
or ( n5566 , n5521 , n5565 );
and ( n5567 , n5518 , n5566 );
or ( n5568 , n5517 , n5567 );
and ( n5569 , n5514 , n5568 );
or ( n5570 , n5513 , n5569 );
and ( n5571 , n5510 , n5570 );
or ( n5572 , n5509 , n5571 );
and ( n5573 , n5506 , n5572 );
or ( n5574 , n5505 , n5573 );
and ( n5575 , n5502 , n5574 );
or ( n5576 , n5501 , n5575 );
and ( n5577 , n5498 , n5576 );
or ( n5578 , n5497 , n5577 );
and ( n5579 , n5494 , n5578 );
or ( n5580 , n5493 , n5579 );
and ( n5581 , n5490 , n5580 );
or ( n5582 , n5489 , n5581 );
and ( n5583 , n5486 , n5582 );
or ( n5584 , n5485 , n5583 );
and ( n5585 , n5482 , n5584 );
or ( n5586 , n5481 , n5585 );
and ( n5587 , n5478 , n5586 );
or ( n5588 , n5477 , n5587 );
and ( n5589 , n5474 , n5588 );
or ( n5590 , n5473 , n5589 );
and ( n5591 , n5470 , n5590 );
or ( n5592 , n5469 , n5591 );
xor ( n5593 , n5466 , n5592 );
and ( n5594 , n285 , n951 );
nor ( n5595 , n952 , n5594 );
nor ( n5596 , n1126 , n305 );
xor ( n5597 , n5595 , n5596 );
and ( n5598 , n5193 , n5194 );
and ( n5599 , n5195 , n5198 );
or ( n5600 , n5598 , n5599 );
xor ( n5601 , n5597 , n5600 );
nor ( n5602 , n1318 , n336 );
xor ( n5603 , n5601 , n5602 );
and ( n5604 , n5199 , n5200 );
and ( n5605 , n5201 , n5204 );
or ( n5606 , n5604 , n5605 );
xor ( n5607 , n5603 , n5606 );
nor ( n5608 , n1534 , n386 );
xor ( n5609 , n5607 , n5608 );
and ( n5610 , n5205 , n5206 );
and ( n5611 , n5207 , n5210 );
or ( n5612 , n5610 , n5611 );
xor ( n5613 , n5609 , n5612 );
nor ( n5614 , n1771 , n458 );
xor ( n5615 , n5613 , n5614 );
and ( n5616 , n5211 , n5212 );
and ( n5617 , n5213 , n5216 );
or ( n5618 , n5616 , n5617 );
xor ( n5619 , n5615 , n5618 );
nor ( n5620 , n2025 , n551 );
xor ( n5621 , n5619 , n5620 );
and ( n5622 , n5217 , n5218 );
and ( n5623 , n5219 , n5222 );
or ( n5624 , n5622 , n5623 );
xor ( n5625 , n5621 , n5624 );
nor ( n5626 , n2300 , n665 );
xor ( n5627 , n5625 , n5626 );
and ( n5628 , n5223 , n5224 );
and ( n5629 , n5225 , n5228 );
or ( n5630 , n5628 , n5629 );
xor ( n5631 , n5627 , n5630 );
nor ( n5632 , n2596 , n797 );
xor ( n5633 , n5631 , n5632 );
and ( n5634 , n5229 , n5230 );
and ( n5635 , n5231 , n5234 );
or ( n5636 , n5634 , n5635 );
xor ( n5637 , n5633 , n5636 );
nor ( n5638 , n2991 , n954 );
xor ( n5639 , n5637 , n5638 );
and ( n5640 , n5235 , n5236 );
and ( n5641 , n5237 , n5240 );
or ( n5642 , n5640 , n5641 );
xor ( n5643 , n5639 , n5642 );
nor ( n5644 , n3464 , n1128 );
xor ( n5645 , n5643 , n5644 );
and ( n5646 , n5241 , n5242 );
and ( n5647 , n5243 , n5246 );
or ( n5648 , n5646 , n5647 );
xor ( n5649 , n5645 , n5648 );
nor ( n5650 , n3863 , n1320 );
xor ( n5651 , n5649 , n5650 );
and ( n5652 , n5247 , n5248 );
and ( n5653 , n5249 , n5252 );
or ( n5654 , n5652 , n5653 );
xor ( n5655 , n5651 , n5654 );
nor ( n5656 , n4260 , n1536 );
xor ( n5657 , n5655 , n5656 );
and ( n5658 , n5253 , n5254 );
and ( n5659 , n5255 , n5258 );
or ( n5660 , n5658 , n5659 );
xor ( n5661 , n5657 , n5660 );
nor ( n5662 , n4659 , n1773 );
xor ( n5663 , n5661 , n5662 );
and ( n5664 , n5259 , n5260 );
and ( n5665 , n5261 , n5264 );
or ( n5666 , n5664 , n5665 );
xor ( n5667 , n5663 , n5666 );
nor ( n5668 , n5057 , n2027 );
xor ( n5669 , n5667 , n5668 );
and ( n5670 , n5265 , n5266 );
and ( n5671 , n5267 , n5270 );
or ( n5672 , n5670 , n5671 );
xor ( n5673 , n5669 , n5672 );
nor ( n5674 , n5453 , n2302 );
xor ( n5675 , n5673 , n5674 );
and ( n5676 , n5271 , n5272 );
and ( n5677 , n5273 , n5276 );
or ( n5678 , n5676 , n5677 );
xor ( n5679 , n5675 , n5678 );
and ( n5680 , n5294 , n5298 );
and ( n5681 , n5298 , n5302 );
and ( n5682 , n5294 , n5302 );
or ( n5683 , n5680 , n5681 , n5682 );
and ( n5684 , n5290 , n5303 );
and ( n5685 , n5303 , n5439 );
and ( n5686 , n5290 , n5439 );
or ( n5687 , n5684 , n5685 , n5686 );
xor ( n5688 , n5683 , n5687 );
and ( n5689 , n5308 , n5334 );
and ( n5690 , n5334 , n5438 );
and ( n5691 , n5308 , n5438 );
or ( n5692 , n5689 , n5690 , n5691 );
and ( n5693 , n5322 , n5323 );
and ( n5694 , n5323 , n5325 );
and ( n5695 , n5322 , n5325 );
or ( n5696 , n5693 , n5694 , n5695 );
and ( n5697 , n5312 , n5316 );
and ( n5698 , n5316 , n5333 );
and ( n5699 , n5312 , n5333 );
or ( n5700 , n5697 , n5698 , n5699 );
xor ( n5701 , n5696 , n5700 );
not ( n5702 , n931 );
and ( n5703 , n2406 , n931 );
nor ( n5704 , n5702 , n5703 );
xor ( n5705 , n5701 , n5704 );
xor ( n5706 , n5692 , n5705 );
and ( n5707 , n5339 , n5354 );
and ( n5708 , n5354 , n5437 );
and ( n5709 , n5339 , n5437 );
or ( n5710 , n5707 , n5708 , n5709 );
and ( n5711 , n5321 , n5326 );
and ( n5712 , n5326 , n5332 );
and ( n5713 , n5321 , n5332 );
or ( n5714 , n5711 , n5712 , n5713 );
and ( n5715 , n5343 , n5347 );
and ( n5716 , n5347 , n5353 );
and ( n5717 , n5343 , n5353 );
or ( n5718 , n5715 , n5716 , n5717 );
xor ( n5719 , n5714 , n5718 );
and ( n5720 , n5328 , n5329 );
and ( n5721 , n5329 , n5331 );
and ( n5722 , n5328 , n5331 );
or ( n5723 , n5720 , n5721 , n5722 );
and ( n5724 , n1088 , n2138 );
and ( n5725 , n1292 , n1864 );
xor ( n5726 , n5724 , n5725 );
and ( n5727 , n1516 , n1753 );
xor ( n5728 , n5726 , n5727 );
xor ( n5729 , n5723 , n5728 );
and ( n5730 , n1730 , n1396 );
and ( n5731 , n2001 , n1302 );
xor ( n5732 , n5730 , n5731 );
and ( n5733 , n2286 , n1114 );
xor ( n5734 , n5732 , n5733 );
xor ( n5735 , n5729 , n5734 );
xor ( n5736 , n5719 , n5735 );
xor ( n5737 , n5710 , n5736 );
and ( n5738 , n5359 , n5364 );
and ( n5739 , n5364 , n5436 );
and ( n5740 , n5359 , n5436 );
or ( n5741 , n5738 , n5739 , n5740 );
and ( n5742 , n5349 , n5350 );
and ( n5743 , n5350 , n5352 );
and ( n5744 , n5349 , n5352 );
or ( n5745 , n5742 , n5743 , n5744 );
and ( n5746 , n5360 , n5361 );
and ( n5747 , n5361 , n5363 );
and ( n5748 , n5360 , n5363 );
or ( n5749 , n5746 , n5747 , n5748 );
xor ( n5750 , n5745 , n5749 );
and ( n5751 , n2581 , n852 );
and ( n5752 , n2972 , n714 );
xor ( n5753 , n5751 , n5752 );
and ( n5754 , n3445 , n651 );
xor ( n5755 , n5753 , n5754 );
xor ( n5756 , n5750 , n5755 );
xor ( n5757 , n5741 , n5756 );
and ( n5758 , n5366 , n5367 );
and ( n5759 , n5367 , n5435 );
and ( n5760 , n5366 , n5435 );
or ( n5761 , n5758 , n5759 , n5760 );
and ( n5762 , n3844 , n488 );
and ( n5763 , n4241 , n411 );
xor ( n5764 , n5762 , n5763 );
and ( n5765 , n4640 , n375 );
xor ( n5766 , n5764 , n5765 );
xor ( n5767 , n5761 , n5766 );
and ( n5768 , n5038 , n312 );
and ( n5769 , n5434 , n288 );
xor ( n5770 , n5768 , n5769 );
and ( n5771 , n5382 , n5386 );
and ( n5772 , n5386 , n5390 );
and ( n5773 , n5382 , n5390 );
or ( n5774 , n5771 , n5772 , n5773 );
and ( n5775 , n5378 , n5391 );
and ( n5776 , n5391 , n5421 );
and ( n5777 , n5378 , n5421 );
or ( n5778 , n5775 , n5776 , n5777 );
xor ( n5779 , n5774 , n5778 );
and ( n5780 , n5415 , n5420 );
and ( n5781 , n5403 , n5404 );
and ( n5782 , n5404 , n5406 );
and ( n5783 , n5403 , n5406 );
or ( n5784 , n5781 , n5782 , n5783 );
and ( n5785 , n5396 , n5397 );
and ( n5786 , n5397 , n5414 );
and ( n5787 , n5396 , n5414 );
or ( n5788 , n5785 , n5786 , n5787 );
xor ( n5789 , n5784 , n5788 );
and ( n5790 , n2206 , n1048 );
not ( n5791 , n1048 );
nor ( n5792 , n5790 , n5791 );
xor ( n5793 , n5789 , n5792 );
xor ( n5794 , n5780 , n5793 );
and ( n5795 , n5402 , n5407 );
and ( n5796 , n5407 , n5413 );
and ( n5797 , n5402 , n5413 );
or ( n5798 , n5795 , n5796 , n5797 );
and ( n5799 , n5416 , n5419 );
xor ( n5800 , n5798 , n5799 );
and ( n5801 , n5409 , n5410 );
and ( n5802 , n5410 , n5412 );
and ( n5803 , n5409 , n5412 );
or ( n5804 , n5801 , n5802 , n5803 );
and ( n5805 , n1458 , n1685 );
and ( n5806 , n1713 , n1497 );
xor ( n5807 , n5805 , n5806 );
and ( n5808 , n1935 , n1261 );
xor ( n5809 , n5807 , n5808 );
xor ( n5810 , n5804 , n5809 );
not ( n5811 , n917 );
and ( n5812 , n2563 , n917 );
nor ( n5813 , n5811 , n5812 );
and ( n5814 , n1077 , n2271 );
xor ( n5815 , n5813 , n5814 );
and ( n5816 , n1277 , n1975 );
xor ( n5817 , n5815 , n5816 );
xor ( n5818 , n5810 , n5817 );
xor ( n5819 , n5800 , n5818 );
xor ( n5820 , n5794 , n5819 );
xor ( n5821 , n5779 , n5820 );
and ( n5822 , n5372 , n5376 );
and ( n5823 , n5376 , n5422 );
and ( n5824 , n5372 , n5422 );
or ( n5825 , n5822 , n5823 , n5824 );
xor ( n5826 , n5821 , n5825 );
and ( n5827 , n5423 , n5427 );
and ( n5828 , n5428 , n5431 );
or ( n5829 , n5827 , n5828 );
xor ( n5830 , n5826 , n5829 );
buf ( n5831 , n5830 );
buf ( n5832 , n5831 );
and ( n5833 , n5832 , n279 );
xor ( n5834 , n5770 , n5833 );
xor ( n5835 , n5767 , n5834 );
xor ( n5836 , n5757 , n5835 );
xor ( n5837 , n5737 , n5836 );
xor ( n5838 , n5706 , n5837 );
xor ( n5839 , n5688 , n5838 );
and ( n5840 , n5281 , n5285 );
and ( n5841 , n5285 , n5440 );
and ( n5842 , n5281 , n5440 );
or ( n5843 , n5840 , n5841 , n5842 );
xor ( n5844 , n5839 , n5843 );
and ( n5845 , n5441 , n5445 );
and ( n5846 , n5446 , n5449 );
or ( n5847 , n5845 , n5846 );
xor ( n5848 , n5844 , n5847 );
buf ( n5849 , n5848 );
buf ( n5850 , n5849 );
not ( n5851 , n5850 );
nor ( n5852 , n5851 , n2598 );
xor ( n5853 , n5679 , n5852 );
and ( n5854 , n5277 , n5454 );
and ( n5855 , n5455 , n5458 );
or ( n5856 , n5854 , n5855 );
xor ( n5857 , n5853 , n5856 );
buf ( n5858 , n5857 );
buf ( n5859 , n5858 );
not ( n5860 , n5859 );
buf ( n5861 , n265 );
not ( n5862 , n5861 );
nor ( n5863 , n5860 , n5862 );
xor ( n5864 , n5593 , n5863 );
xor ( n5865 , n5470 , n5590 );
nor ( n5866 , n5462 , n5862 );
and ( n5867 , n5865 , n5866 );
xor ( n5868 , n5865 , n5866 );
xor ( n5869 , n5474 , n5588 );
nor ( n5870 , n5066 , n5862 );
and ( n5871 , n5869 , n5870 );
xor ( n5872 , n5869 , n5870 );
xor ( n5873 , n5478 , n5586 );
nor ( n5874 , n4668 , n5862 );
and ( n5875 , n5873 , n5874 );
xor ( n5876 , n5873 , n5874 );
xor ( n5877 , n5482 , n5584 );
nor ( n5878 , n4269 , n5862 );
and ( n5879 , n5877 , n5878 );
xor ( n5880 , n5877 , n5878 );
xor ( n5881 , n5486 , n5582 );
nor ( n5882 , n3872 , n5862 );
and ( n5883 , n5881 , n5882 );
xor ( n5884 , n5881 , n5882 );
xor ( n5885 , n5490 , n5580 );
nor ( n5886 , n3473 , n5862 );
and ( n5887 , n5885 , n5886 );
xor ( n5888 , n5885 , n5886 );
xor ( n5889 , n5494 , n5578 );
nor ( n5890 , n3000 , n5862 );
and ( n5891 , n5889 , n5890 );
xor ( n5892 , n5889 , n5890 );
xor ( n5893 , n5498 , n5576 );
nor ( n5894 , n2688 , n5862 );
and ( n5895 , n5893 , n5894 );
xor ( n5896 , n5893 , n5894 );
xor ( n5897 , n5502 , n5574 );
nor ( n5898 , n3008 , n5862 );
and ( n5899 , n5897 , n5898 );
xor ( n5900 , n5897 , n5898 );
xor ( n5901 , n5506 , n5572 );
nor ( n5902 , n3017 , n5862 );
and ( n5903 , n5901 , n5902 );
xor ( n5904 , n5901 , n5902 );
xor ( n5905 , n5510 , n5570 );
nor ( n5906 , n3026 , n5862 );
and ( n5907 , n5905 , n5906 );
xor ( n5908 , n5905 , n5906 );
xor ( n5909 , n5514 , n5568 );
nor ( n5910 , n3035 , n5862 );
and ( n5911 , n5909 , n5910 );
xor ( n5912 , n5909 , n5910 );
xor ( n5913 , n5518 , n5566 );
nor ( n5914 , n3044 , n5862 );
and ( n5915 , n5913 , n5914 );
xor ( n5916 , n5913 , n5914 );
xor ( n5917 , n5522 , n5564 );
nor ( n5918 , n3053 , n5862 );
and ( n5919 , n5917 , n5918 );
xor ( n5920 , n5917 , n5918 );
xor ( n5921 , n5526 , n5562 );
nor ( n5922 , n3062 , n5862 );
and ( n5923 , n5921 , n5922 );
xor ( n5924 , n5921 , n5922 );
xor ( n5925 , n5530 , n5560 );
nor ( n5926 , n3071 , n5862 );
and ( n5927 , n5925 , n5926 );
xor ( n5928 , n5925 , n5926 );
xor ( n5929 , n5534 , n5558 );
nor ( n5930 , n3080 , n5862 );
and ( n5931 , n5929 , n5930 );
xor ( n5932 , n5929 , n5930 );
xor ( n5933 , n5538 , n5556 );
nor ( n5934 , n3089 , n5862 );
and ( n5935 , n5933 , n5934 );
xor ( n5936 , n5933 , n5934 );
xor ( n5937 , n5542 , n5554 );
nor ( n5938 , n3098 , n5862 );
and ( n5939 , n5937 , n5938 );
xor ( n5940 , n5937 , n5938 );
xor ( n5941 , n5547 , n5552 );
nor ( n5942 , n3107 , n5862 );
and ( n5943 , n5941 , n5942 );
xor ( n5944 , n5941 , n5942 );
xor ( n5945 , n5549 , n5550 );
buf ( n5946 , n5945 );
nor ( n5947 , n3116 , n5862 );
and ( n5948 , n5946 , n5947 );
xor ( n5949 , n5946 , n5947 );
nor ( n5950 , n3134 , n5464 );
buf ( n5951 , n5950 );
nor ( n5952 , n3125 , n5862 );
and ( n5953 , n5951 , n5952 );
buf ( n5954 , n5953 );
and ( n5955 , n5949 , n5954 );
or ( n5956 , n5948 , n5955 );
and ( n5957 , n5944 , n5956 );
or ( n5958 , n5943 , n5957 );
and ( n5959 , n5940 , n5958 );
or ( n5960 , n5939 , n5959 );
and ( n5961 , n5936 , n5960 );
or ( n5962 , n5935 , n5961 );
and ( n5963 , n5932 , n5962 );
or ( n5964 , n5931 , n5963 );
and ( n5965 , n5928 , n5964 );
or ( n5966 , n5927 , n5965 );
and ( n5967 , n5924 , n5966 );
or ( n5968 , n5923 , n5967 );
and ( n5969 , n5920 , n5968 );
or ( n5970 , n5919 , n5969 );
and ( n5971 , n5916 , n5970 );
or ( n5972 , n5915 , n5971 );
and ( n5973 , n5912 , n5972 );
or ( n5974 , n5911 , n5973 );
and ( n5975 , n5908 , n5974 );
or ( n5976 , n5907 , n5975 );
and ( n5977 , n5904 , n5976 );
or ( n5978 , n5903 , n5977 );
and ( n5979 , n5900 , n5978 );
or ( n5980 , n5899 , n5979 );
and ( n5981 , n5896 , n5980 );
or ( n5982 , n5895 , n5981 );
and ( n5983 , n5892 , n5982 );
or ( n5984 , n5891 , n5983 );
and ( n5985 , n5888 , n5984 );
or ( n5986 , n5887 , n5985 );
and ( n5987 , n5884 , n5986 );
or ( n5988 , n5883 , n5987 );
and ( n5989 , n5880 , n5988 );
or ( n5990 , n5879 , n5989 );
and ( n5991 , n5876 , n5990 );
or ( n5992 , n5875 , n5991 );
and ( n5993 , n5872 , n5992 );
or ( n5994 , n5871 , n5993 );
and ( n5995 , n5868 , n5994 );
or ( n5996 , n5867 , n5995 );
xor ( n5997 , n5864 , n5996 );
and ( n5998 , n285 , n1125 );
nor ( n5999 , n1126 , n5998 );
nor ( n6000 , n1318 , n305 );
xor ( n6001 , n5999 , n6000 );
and ( n6002 , n5595 , n5596 );
and ( n6003 , n5597 , n5600 );
or ( n6004 , n6002 , n6003 );
xor ( n6005 , n6001 , n6004 );
nor ( n6006 , n1534 , n336 );
xor ( n6007 , n6005 , n6006 );
and ( n6008 , n5601 , n5602 );
and ( n6009 , n5603 , n5606 );
or ( n6010 , n6008 , n6009 );
xor ( n6011 , n6007 , n6010 );
nor ( n6012 , n1771 , n386 );
xor ( n6013 , n6011 , n6012 );
and ( n6014 , n5607 , n5608 );
and ( n6015 , n5609 , n5612 );
or ( n6016 , n6014 , n6015 );
xor ( n6017 , n6013 , n6016 );
nor ( n6018 , n2025 , n458 );
xor ( n6019 , n6017 , n6018 );
and ( n6020 , n5613 , n5614 );
and ( n6021 , n5615 , n5618 );
or ( n6022 , n6020 , n6021 );
xor ( n6023 , n6019 , n6022 );
nor ( n6024 , n2300 , n551 );
xor ( n6025 , n6023 , n6024 );
and ( n6026 , n5619 , n5620 );
and ( n6027 , n5621 , n5624 );
or ( n6028 , n6026 , n6027 );
xor ( n6029 , n6025 , n6028 );
nor ( n6030 , n2596 , n665 );
xor ( n6031 , n6029 , n6030 );
and ( n6032 , n5625 , n5626 );
and ( n6033 , n5627 , n5630 );
or ( n6034 , n6032 , n6033 );
xor ( n6035 , n6031 , n6034 );
nor ( n6036 , n2991 , n797 );
xor ( n6037 , n6035 , n6036 );
and ( n6038 , n5631 , n5632 );
and ( n6039 , n5633 , n5636 );
or ( n6040 , n6038 , n6039 );
xor ( n6041 , n6037 , n6040 );
nor ( n6042 , n3464 , n954 );
xor ( n6043 , n6041 , n6042 );
and ( n6044 , n5637 , n5638 );
and ( n6045 , n5639 , n5642 );
or ( n6046 , n6044 , n6045 );
xor ( n6047 , n6043 , n6046 );
nor ( n6048 , n3863 , n1128 );
xor ( n6049 , n6047 , n6048 );
and ( n6050 , n5643 , n5644 );
and ( n6051 , n5645 , n5648 );
or ( n6052 , n6050 , n6051 );
xor ( n6053 , n6049 , n6052 );
nor ( n6054 , n4260 , n1320 );
xor ( n6055 , n6053 , n6054 );
and ( n6056 , n5649 , n5650 );
and ( n6057 , n5651 , n5654 );
or ( n6058 , n6056 , n6057 );
xor ( n6059 , n6055 , n6058 );
nor ( n6060 , n4659 , n1536 );
xor ( n6061 , n6059 , n6060 );
and ( n6062 , n5655 , n5656 );
and ( n6063 , n5657 , n5660 );
or ( n6064 , n6062 , n6063 );
xor ( n6065 , n6061 , n6064 );
nor ( n6066 , n5057 , n1773 );
xor ( n6067 , n6065 , n6066 );
and ( n6068 , n5661 , n5662 );
and ( n6069 , n5663 , n5666 );
or ( n6070 , n6068 , n6069 );
xor ( n6071 , n6067 , n6070 );
nor ( n6072 , n5453 , n2027 );
xor ( n6073 , n6071 , n6072 );
and ( n6074 , n5667 , n5668 );
and ( n6075 , n5669 , n5672 );
or ( n6076 , n6074 , n6075 );
xor ( n6077 , n6073 , n6076 );
nor ( n6078 , n5851 , n2302 );
xor ( n6079 , n6077 , n6078 );
and ( n6080 , n5673 , n5674 );
and ( n6081 , n5675 , n5678 );
or ( n6082 , n6080 , n6081 );
xor ( n6083 , n6079 , n6082 );
and ( n6084 , n5696 , n5700 );
and ( n6085 , n5700 , n5704 );
and ( n6086 , n5696 , n5704 );
or ( n6087 , n6084 , n6085 , n6086 );
and ( n6088 , n5692 , n5705 );
and ( n6089 , n5705 , n5837 );
and ( n6090 , n5692 , n5837 );
or ( n6091 , n6088 , n6089 , n6090 );
xor ( n6092 , n6087 , n6091 );
and ( n6093 , n5710 , n5736 );
and ( n6094 , n5736 , n5836 );
and ( n6095 , n5710 , n5836 );
or ( n6096 , n6093 , n6094 , n6095 );
and ( n6097 , n5724 , n5725 );
and ( n6098 , n5725 , n5727 );
and ( n6099 , n5724 , n5727 );
or ( n6100 , n6097 , n6098 , n6099 );
and ( n6101 , n5714 , n5718 );
and ( n6102 , n5718 , n5735 );
and ( n6103 , n5714 , n5735 );
or ( n6104 , n6101 , n6102 , n6103 );
xor ( n6105 , n6100 , n6104 );
not ( n6106 , n1088 );
and ( n6107 , n2406 , n1088 );
nor ( n6108 , n6106 , n6107 );
xor ( n6109 , n6105 , n6108 );
xor ( n6110 , n6096 , n6109 );
and ( n6111 , n5741 , n5756 );
and ( n6112 , n5756 , n5835 );
and ( n6113 , n5741 , n5835 );
or ( n6114 , n6111 , n6112 , n6113 );
and ( n6115 , n5723 , n5728 );
and ( n6116 , n5728 , n5734 );
and ( n6117 , n5723 , n5734 );
or ( n6118 , n6115 , n6116 , n6117 );
and ( n6119 , n5745 , n5749 );
and ( n6120 , n5749 , n5755 );
and ( n6121 , n5745 , n5755 );
or ( n6122 , n6119 , n6120 , n6121 );
xor ( n6123 , n6118 , n6122 );
and ( n6124 , n5730 , n5731 );
and ( n6125 , n5731 , n5733 );
and ( n6126 , n5730 , n5733 );
or ( n6127 , n6124 , n6125 , n6126 );
and ( n6128 , n1292 , n2138 );
and ( n6129 , n1516 , n1864 );
xor ( n6130 , n6128 , n6129 );
and ( n6131 , n1730 , n1753 );
xor ( n6132 , n6130 , n6131 );
xor ( n6133 , n6127 , n6132 );
and ( n6134 , n2001 , n1396 );
and ( n6135 , n2286 , n1302 );
xor ( n6136 , n6134 , n6135 );
and ( n6137 , n2581 , n1114 );
xor ( n6138 , n6136 , n6137 );
xor ( n6139 , n6133 , n6138 );
xor ( n6140 , n6123 , n6139 );
xor ( n6141 , n6114 , n6140 );
and ( n6142 , n5761 , n5766 );
and ( n6143 , n5766 , n5834 );
and ( n6144 , n5761 , n5834 );
or ( n6145 , n6142 , n6143 , n6144 );
and ( n6146 , n5751 , n5752 );
and ( n6147 , n5752 , n5754 );
and ( n6148 , n5751 , n5754 );
or ( n6149 , n6146 , n6147 , n6148 );
and ( n6150 , n5762 , n5763 );
and ( n6151 , n5763 , n5765 );
and ( n6152 , n5762 , n5765 );
or ( n6153 , n6150 , n6151 , n6152 );
xor ( n6154 , n6149 , n6153 );
and ( n6155 , n2972 , n852 );
and ( n6156 , n3445 , n714 );
xor ( n6157 , n6155 , n6156 );
and ( n6158 , n3844 , n651 );
xor ( n6159 , n6157 , n6158 );
xor ( n6160 , n6154 , n6159 );
xor ( n6161 , n6145 , n6160 );
and ( n6162 , n5768 , n5769 );
and ( n6163 , n5769 , n5833 );
and ( n6164 , n5768 , n5833 );
or ( n6165 , n6162 , n6163 , n6164 );
and ( n6166 , n4241 , n488 );
and ( n6167 , n4640 , n411 );
xor ( n6168 , n6166 , n6167 );
and ( n6169 , n5038 , n375 );
xor ( n6170 , n6168 , n6169 );
xor ( n6171 , n6165 , n6170 );
and ( n6172 , n5434 , n312 );
and ( n6173 , n5832 , n288 );
xor ( n6174 , n6172 , n6173 );
and ( n6175 , n5784 , n5788 );
and ( n6176 , n5788 , n5792 );
and ( n6177 , n5784 , n5792 );
or ( n6178 , n6175 , n6176 , n6177 );
and ( n6179 , n5780 , n5793 );
and ( n6180 , n5793 , n5819 );
and ( n6181 , n5780 , n5819 );
or ( n6182 , n6179 , n6180 , n6181 );
xor ( n6183 , n6178 , n6182 );
and ( n6184 , n5805 , n5806 );
and ( n6185 , n5806 , n5808 );
and ( n6186 , n5805 , n5808 );
or ( n6187 , n6184 , n6185 , n6186 );
and ( n6188 , n5798 , n5799 );
and ( n6189 , n5799 , n5818 );
and ( n6190 , n5798 , n5818 );
or ( n6191 , n6188 , n6189 , n6190 );
xor ( n6192 , n6187 , n6191 );
and ( n6193 , n2206 , n1261 );
not ( n6194 , n1261 );
nor ( n6195 , n6193 , n6194 );
xor ( n6196 , n6192 , n6195 );
and ( n6197 , n5804 , n5809 );
and ( n6198 , n5809 , n5817 );
and ( n6199 , n5804 , n5817 );
or ( n6200 , n6197 , n6198 , n6199 );
and ( n6201 , n5813 , n5814 );
and ( n6202 , n5814 , n5816 );
and ( n6203 , n5813 , n5816 );
or ( n6204 , n6201 , n6202 , n6203 );
and ( n6205 , n1458 , n1975 );
and ( n6206 , n1713 , n1685 );
xor ( n6207 , n6205 , n6206 );
and ( n6208 , n1935 , n1497 );
xor ( n6209 , n6207 , n6208 );
xor ( n6210 , n6204 , n6209 );
not ( n6211 , n1077 );
and ( n6212 , n2563 , n1077 );
nor ( n6213 , n6211 , n6212 );
and ( n6214 , n1277 , n2271 );
xor ( n6215 , n6213 , n6214 );
xor ( n6216 , n6210 , n6215 );
xor ( n6217 , n6200 , n6216 );
xor ( n6218 , n6196 , n6217 );
xor ( n6219 , n6183 , n6218 );
and ( n6220 , n5774 , n5778 );
and ( n6221 , n5778 , n5820 );
and ( n6222 , n5774 , n5820 );
or ( n6223 , n6220 , n6221 , n6222 );
xor ( n6224 , n6219 , n6223 );
and ( n6225 , n5821 , n5825 );
and ( n6226 , n5826 , n5829 );
or ( n6227 , n6225 , n6226 );
xor ( n6228 , n6224 , n6227 );
buf ( n6229 , n6228 );
buf ( n6230 , n6229 );
and ( n6231 , n6230 , n279 );
xor ( n6232 , n6174 , n6231 );
xor ( n6233 , n6171 , n6232 );
xor ( n6234 , n6161 , n6233 );
xor ( n6235 , n6141 , n6234 );
xor ( n6236 , n6110 , n6235 );
xor ( n6237 , n6092 , n6236 );
and ( n6238 , n5683 , n5687 );
and ( n6239 , n5687 , n5838 );
and ( n6240 , n5683 , n5838 );
or ( n6241 , n6238 , n6239 , n6240 );
xor ( n6242 , n6237 , n6241 );
and ( n6243 , n5839 , n5843 );
and ( n6244 , n5844 , n5847 );
or ( n6245 , n6243 , n6244 );
xor ( n6246 , n6242 , n6245 );
buf ( n6247 , n6246 );
buf ( n6248 , n6247 );
not ( n6249 , n6248 );
nor ( n6250 , n6249 , n2598 );
xor ( n6251 , n6083 , n6250 );
and ( n6252 , n5679 , n5852 );
and ( n6253 , n5853 , n5856 );
or ( n6254 , n6252 , n6253 );
xor ( n6255 , n6251 , n6254 );
buf ( n6256 , n6255 );
buf ( n6257 , n6256 );
not ( n6258 , n6257 );
buf ( n6259 , n266 );
not ( n6260 , n6259 );
nor ( n6261 , n6258 , n6260 );
xor ( n6262 , n5997 , n6261 );
xor ( n6263 , n5868 , n5994 );
nor ( n6264 , n5860 , n6260 );
and ( n6265 , n6263 , n6264 );
xor ( n6266 , n6263 , n6264 );
xor ( n6267 , n5872 , n5992 );
nor ( n6268 , n5462 , n6260 );
and ( n6269 , n6267 , n6268 );
xor ( n6270 , n6267 , n6268 );
xor ( n6271 , n5876 , n5990 );
nor ( n6272 , n5066 , n6260 );
and ( n6273 , n6271 , n6272 );
xor ( n6274 , n6271 , n6272 );
xor ( n6275 , n5880 , n5988 );
nor ( n6276 , n4668 , n6260 );
and ( n6277 , n6275 , n6276 );
xor ( n6278 , n6275 , n6276 );
xor ( n6279 , n5884 , n5986 );
nor ( n6280 , n4269 , n6260 );
and ( n6281 , n6279 , n6280 );
xor ( n6282 , n6279 , n6280 );
xor ( n6283 , n5888 , n5984 );
nor ( n6284 , n3872 , n6260 );
and ( n6285 , n6283 , n6284 );
xor ( n6286 , n6283 , n6284 );
xor ( n6287 , n5892 , n5982 );
nor ( n6288 , n3473 , n6260 );
and ( n6289 , n6287 , n6288 );
xor ( n6290 , n6287 , n6288 );
xor ( n6291 , n5896 , n5980 );
nor ( n6292 , n3000 , n6260 );
and ( n6293 , n6291 , n6292 );
xor ( n6294 , n6291 , n6292 );
xor ( n6295 , n5900 , n5978 );
nor ( n6296 , n2688 , n6260 );
and ( n6297 , n6295 , n6296 );
xor ( n6298 , n6295 , n6296 );
xor ( n6299 , n5904 , n5976 );
nor ( n6300 , n3008 , n6260 );
and ( n6301 , n6299 , n6300 );
xor ( n6302 , n6299 , n6300 );
xor ( n6303 , n5908 , n5974 );
nor ( n6304 , n3017 , n6260 );
and ( n6305 , n6303 , n6304 );
xor ( n6306 , n6303 , n6304 );
xor ( n6307 , n5912 , n5972 );
nor ( n6308 , n3026 , n6260 );
and ( n6309 , n6307 , n6308 );
xor ( n6310 , n6307 , n6308 );
xor ( n6311 , n5916 , n5970 );
nor ( n6312 , n3035 , n6260 );
and ( n6313 , n6311 , n6312 );
xor ( n6314 , n6311 , n6312 );
xor ( n6315 , n5920 , n5968 );
nor ( n6316 , n3044 , n6260 );
and ( n6317 , n6315 , n6316 );
xor ( n6318 , n6315 , n6316 );
xor ( n6319 , n5924 , n5966 );
nor ( n6320 , n3053 , n6260 );
and ( n6321 , n6319 , n6320 );
xor ( n6322 , n6319 , n6320 );
xor ( n6323 , n5928 , n5964 );
nor ( n6324 , n3062 , n6260 );
and ( n6325 , n6323 , n6324 );
xor ( n6326 , n6323 , n6324 );
xor ( n6327 , n5932 , n5962 );
nor ( n6328 , n3071 , n6260 );
and ( n6329 , n6327 , n6328 );
xor ( n6330 , n6327 , n6328 );
xor ( n6331 , n5936 , n5960 );
nor ( n6332 , n3080 , n6260 );
and ( n6333 , n6331 , n6332 );
xor ( n6334 , n6331 , n6332 );
xor ( n6335 , n5940 , n5958 );
nor ( n6336 , n3089 , n6260 );
and ( n6337 , n6335 , n6336 );
xor ( n6338 , n6335 , n6336 );
xor ( n6339 , n5944 , n5956 );
nor ( n6340 , n3098 , n6260 );
and ( n6341 , n6339 , n6340 );
xor ( n6342 , n6339 , n6340 );
xor ( n6343 , n5949 , n5954 );
nor ( n6344 , n3107 , n6260 );
and ( n6345 , n6343 , n6344 );
xor ( n6346 , n6343 , n6344 );
xor ( n6347 , n5951 , n5952 );
buf ( n6348 , n6347 );
nor ( n6349 , n3116 , n6260 );
and ( n6350 , n6348 , n6349 );
xor ( n6351 , n6348 , n6349 );
nor ( n6352 , n3134 , n5862 );
buf ( n6353 , n6352 );
nor ( n6354 , n3125 , n6260 );
and ( n6355 , n6353 , n6354 );
buf ( n6356 , n6355 );
and ( n6357 , n6351 , n6356 );
or ( n6358 , n6350 , n6357 );
and ( n6359 , n6346 , n6358 );
or ( n6360 , n6345 , n6359 );
and ( n6361 , n6342 , n6360 );
or ( n6362 , n6341 , n6361 );
and ( n6363 , n6338 , n6362 );
or ( n6364 , n6337 , n6363 );
and ( n6365 , n6334 , n6364 );
or ( n6366 , n6333 , n6365 );
and ( n6367 , n6330 , n6366 );
or ( n6368 , n6329 , n6367 );
and ( n6369 , n6326 , n6368 );
or ( n6370 , n6325 , n6369 );
and ( n6371 , n6322 , n6370 );
or ( n6372 , n6321 , n6371 );
and ( n6373 , n6318 , n6372 );
or ( n6374 , n6317 , n6373 );
and ( n6375 , n6314 , n6374 );
or ( n6376 , n6313 , n6375 );
and ( n6377 , n6310 , n6376 );
or ( n6378 , n6309 , n6377 );
and ( n6379 , n6306 , n6378 );
or ( n6380 , n6305 , n6379 );
and ( n6381 , n6302 , n6380 );
or ( n6382 , n6301 , n6381 );
and ( n6383 , n6298 , n6382 );
or ( n6384 , n6297 , n6383 );
and ( n6385 , n6294 , n6384 );
or ( n6386 , n6293 , n6385 );
and ( n6387 , n6290 , n6386 );
or ( n6388 , n6289 , n6387 );
and ( n6389 , n6286 , n6388 );
or ( n6390 , n6285 , n6389 );
and ( n6391 , n6282 , n6390 );
or ( n6392 , n6281 , n6391 );
and ( n6393 , n6278 , n6392 );
or ( n6394 , n6277 , n6393 );
and ( n6395 , n6274 , n6394 );
or ( n6396 , n6273 , n6395 );
and ( n6397 , n6270 , n6396 );
or ( n6398 , n6269 , n6397 );
and ( n6399 , n6266 , n6398 );
or ( n6400 , n6265 , n6399 );
xor ( n6401 , n6262 , n6400 );
and ( n6402 , n285 , n1317 );
nor ( n6403 , n1318 , n6402 );
nor ( n6404 , n1534 , n305 );
xor ( n6405 , n6403 , n6404 );
and ( n6406 , n5999 , n6000 );
and ( n6407 , n6001 , n6004 );
or ( n6408 , n6406 , n6407 );
xor ( n6409 , n6405 , n6408 );
nor ( n6410 , n1771 , n336 );
xor ( n6411 , n6409 , n6410 );
and ( n6412 , n6005 , n6006 );
and ( n6413 , n6007 , n6010 );
or ( n6414 , n6412 , n6413 );
xor ( n6415 , n6411 , n6414 );
nor ( n6416 , n2025 , n386 );
xor ( n6417 , n6415 , n6416 );
and ( n6418 , n6011 , n6012 );
and ( n6419 , n6013 , n6016 );
or ( n6420 , n6418 , n6419 );
xor ( n6421 , n6417 , n6420 );
nor ( n6422 , n2300 , n458 );
xor ( n6423 , n6421 , n6422 );
and ( n6424 , n6017 , n6018 );
and ( n6425 , n6019 , n6022 );
or ( n6426 , n6424 , n6425 );
xor ( n6427 , n6423 , n6426 );
nor ( n6428 , n2596 , n551 );
xor ( n6429 , n6427 , n6428 );
and ( n6430 , n6023 , n6024 );
and ( n6431 , n6025 , n6028 );
or ( n6432 , n6430 , n6431 );
xor ( n6433 , n6429 , n6432 );
nor ( n6434 , n2991 , n665 );
xor ( n6435 , n6433 , n6434 );
and ( n6436 , n6029 , n6030 );
and ( n6437 , n6031 , n6034 );
or ( n6438 , n6436 , n6437 );
xor ( n6439 , n6435 , n6438 );
nor ( n6440 , n3464 , n797 );
xor ( n6441 , n6439 , n6440 );
and ( n6442 , n6035 , n6036 );
and ( n6443 , n6037 , n6040 );
or ( n6444 , n6442 , n6443 );
xor ( n6445 , n6441 , n6444 );
nor ( n6446 , n3863 , n954 );
xor ( n6447 , n6445 , n6446 );
and ( n6448 , n6041 , n6042 );
and ( n6449 , n6043 , n6046 );
or ( n6450 , n6448 , n6449 );
xor ( n6451 , n6447 , n6450 );
nor ( n6452 , n4260 , n1128 );
xor ( n6453 , n6451 , n6452 );
and ( n6454 , n6047 , n6048 );
and ( n6455 , n6049 , n6052 );
or ( n6456 , n6454 , n6455 );
xor ( n6457 , n6453 , n6456 );
nor ( n6458 , n4659 , n1320 );
xor ( n6459 , n6457 , n6458 );
and ( n6460 , n6053 , n6054 );
and ( n6461 , n6055 , n6058 );
or ( n6462 , n6460 , n6461 );
xor ( n6463 , n6459 , n6462 );
nor ( n6464 , n5057 , n1536 );
xor ( n6465 , n6463 , n6464 );
and ( n6466 , n6059 , n6060 );
and ( n6467 , n6061 , n6064 );
or ( n6468 , n6466 , n6467 );
xor ( n6469 , n6465 , n6468 );
nor ( n6470 , n5453 , n1773 );
xor ( n6471 , n6469 , n6470 );
and ( n6472 , n6065 , n6066 );
and ( n6473 , n6067 , n6070 );
or ( n6474 , n6472 , n6473 );
xor ( n6475 , n6471 , n6474 );
nor ( n6476 , n5851 , n2027 );
xor ( n6477 , n6475 , n6476 );
and ( n6478 , n6071 , n6072 );
and ( n6479 , n6073 , n6076 );
or ( n6480 , n6478 , n6479 );
xor ( n6481 , n6477 , n6480 );
nor ( n6482 , n6249 , n2302 );
xor ( n6483 , n6481 , n6482 );
and ( n6484 , n6077 , n6078 );
and ( n6485 , n6079 , n6082 );
or ( n6486 , n6484 , n6485 );
xor ( n6487 , n6483 , n6486 );
and ( n6488 , n6100 , n6104 );
and ( n6489 , n6104 , n6108 );
and ( n6490 , n6100 , n6108 );
or ( n6491 , n6488 , n6489 , n6490 );
and ( n6492 , n6096 , n6109 );
and ( n6493 , n6109 , n6235 );
and ( n6494 , n6096 , n6235 );
or ( n6495 , n6492 , n6493 , n6494 );
xor ( n6496 , n6491 , n6495 );
and ( n6497 , n6114 , n6140 );
and ( n6498 , n6140 , n6234 );
and ( n6499 , n6114 , n6234 );
or ( n6500 , n6497 , n6498 , n6499 );
and ( n6501 , n6128 , n6129 );
and ( n6502 , n6129 , n6131 );
and ( n6503 , n6128 , n6131 );
or ( n6504 , n6501 , n6502 , n6503 );
and ( n6505 , n6118 , n6122 );
and ( n6506 , n6122 , n6139 );
and ( n6507 , n6118 , n6139 );
or ( n6508 , n6505 , n6506 , n6507 );
xor ( n6509 , n6504 , n6508 );
not ( n6510 , n1292 );
and ( n6511 , n2406 , n1292 );
nor ( n6512 , n6510 , n6511 );
xor ( n6513 , n6509 , n6512 );
xor ( n6514 , n6500 , n6513 );
and ( n6515 , n6145 , n6160 );
and ( n6516 , n6160 , n6233 );
and ( n6517 , n6145 , n6233 );
or ( n6518 , n6515 , n6516 , n6517 );
and ( n6519 , n6127 , n6132 );
and ( n6520 , n6132 , n6138 );
and ( n6521 , n6127 , n6138 );
or ( n6522 , n6519 , n6520 , n6521 );
and ( n6523 , n6149 , n6153 );
and ( n6524 , n6153 , n6159 );
and ( n6525 , n6149 , n6159 );
or ( n6526 , n6523 , n6524 , n6525 );
xor ( n6527 , n6522 , n6526 );
and ( n6528 , n6134 , n6135 );
and ( n6529 , n6135 , n6137 );
and ( n6530 , n6134 , n6137 );
or ( n6531 , n6528 , n6529 , n6530 );
and ( n6532 , n1516 , n2138 );
and ( n6533 , n1730 , n1864 );
xor ( n6534 , n6532 , n6533 );
and ( n6535 , n2001 , n1753 );
xor ( n6536 , n6534 , n6535 );
xor ( n6537 , n6531 , n6536 );
and ( n6538 , n2286 , n1396 );
and ( n6539 , n2581 , n1302 );
xor ( n6540 , n6538 , n6539 );
and ( n6541 , n2972 , n1114 );
xor ( n6542 , n6540 , n6541 );
xor ( n6543 , n6537 , n6542 );
xor ( n6544 , n6527 , n6543 );
xor ( n6545 , n6518 , n6544 );
and ( n6546 , n6165 , n6170 );
and ( n6547 , n6170 , n6232 );
and ( n6548 , n6165 , n6232 );
or ( n6549 , n6546 , n6547 , n6548 );
and ( n6550 , n6155 , n6156 );
and ( n6551 , n6156 , n6158 );
and ( n6552 , n6155 , n6158 );
or ( n6553 , n6550 , n6551 , n6552 );
and ( n6554 , n6166 , n6167 );
and ( n6555 , n6167 , n6169 );
and ( n6556 , n6166 , n6169 );
or ( n6557 , n6554 , n6555 , n6556 );
xor ( n6558 , n6553 , n6557 );
and ( n6559 , n3445 , n852 );
and ( n6560 , n3844 , n714 );
xor ( n6561 , n6559 , n6560 );
and ( n6562 , n4241 , n651 );
xor ( n6563 , n6561 , n6562 );
xor ( n6564 , n6558 , n6563 );
xor ( n6565 , n6549 , n6564 );
and ( n6566 , n6172 , n6173 );
and ( n6567 , n6173 , n6231 );
and ( n6568 , n6172 , n6231 );
or ( n6569 , n6566 , n6567 , n6568 );
and ( n6570 , n4640 , n488 );
and ( n6571 , n5038 , n411 );
xor ( n6572 , n6570 , n6571 );
and ( n6573 , n5434 , n375 );
xor ( n6574 , n6572 , n6573 );
xor ( n6575 , n6569 , n6574 );
and ( n6576 , n5832 , n312 );
and ( n6577 , n6230 , n288 );
xor ( n6578 , n6576 , n6577 );
and ( n6579 , n6187 , n6191 );
and ( n6580 , n6191 , n6195 );
and ( n6581 , n6187 , n6195 );
or ( n6582 , n6579 , n6580 , n6581 );
and ( n6583 , n6196 , n6217 );
xor ( n6584 , n6582 , n6583 );
and ( n6585 , n6205 , n6206 );
and ( n6586 , n6206 , n6208 );
and ( n6587 , n6205 , n6208 );
or ( n6588 , n6585 , n6586 , n6587 );
and ( n6589 , n6200 , n6216 );
xor ( n6590 , n6588 , n6589 );
and ( n6591 , n2206 , n1497 );
not ( n6592 , n1497 );
nor ( n6593 , n6591 , n6592 );
xor ( n6594 , n6590 , n6593 );
and ( n6595 , n6204 , n6209 );
and ( n6596 , n6209 , n6215 );
and ( n6597 , n6204 , n6215 );
or ( n6598 , n6595 , n6596 , n6597 );
and ( n6599 , n6213 , n6214 );
not ( n6600 , n1277 );
and ( n6601 , n2563 , n1277 );
nor ( n6602 , n6600 , n6601 );
xor ( n6603 , n6599 , n6602 );
and ( n6604 , n1458 , n2271 );
and ( n6605 , n1713 , n1975 );
xor ( n6606 , n6604 , n6605 );
and ( n6607 , n1935 , n1685 );
xor ( n6608 , n6606 , n6607 );
xor ( n6609 , n6603 , n6608 );
xor ( n6610 , n6598 , n6609 );
xor ( n6611 , n6594 , n6610 );
xor ( n6612 , n6584 , n6611 );
and ( n6613 , n6178 , n6182 );
and ( n6614 , n6182 , n6218 );
and ( n6615 , n6178 , n6218 );
or ( n6616 , n6613 , n6614 , n6615 );
xor ( n6617 , n6612 , n6616 );
and ( n6618 , n6219 , n6223 );
and ( n6619 , n6224 , n6227 );
or ( n6620 , n6618 , n6619 );
xor ( n6621 , n6617 , n6620 );
buf ( n6622 , n6621 );
buf ( n6623 , n6622 );
and ( n6624 , n6623 , n279 );
xor ( n6625 , n6578 , n6624 );
xor ( n6626 , n6575 , n6625 );
xor ( n6627 , n6565 , n6626 );
xor ( n6628 , n6545 , n6627 );
xor ( n6629 , n6514 , n6628 );
xor ( n6630 , n6496 , n6629 );
and ( n6631 , n6087 , n6091 );
and ( n6632 , n6091 , n6236 );
and ( n6633 , n6087 , n6236 );
or ( n6634 , n6631 , n6632 , n6633 );
xor ( n6635 , n6630 , n6634 );
and ( n6636 , n6237 , n6241 );
and ( n6637 , n6242 , n6245 );
or ( n6638 , n6636 , n6637 );
xor ( n6639 , n6635 , n6638 );
buf ( n6640 , n6639 );
buf ( n6641 , n6640 );
not ( n6642 , n6641 );
nor ( n6643 , n6642 , n2598 );
xor ( n6644 , n6487 , n6643 );
and ( n6645 , n6083 , n6250 );
and ( n6646 , n6251 , n6254 );
or ( n6647 , n6645 , n6646 );
xor ( n6648 , n6644 , n6647 );
buf ( n6649 , n6648 );
buf ( n6650 , n6649 );
not ( n6651 , n6650 );
buf ( n6652 , n267 );
not ( n6653 , n6652 );
nor ( n6654 , n6651 , n6653 );
xor ( n6655 , n6401 , n6654 );
xor ( n6656 , n6266 , n6398 );
nor ( n6657 , n6258 , n6653 );
and ( n6658 , n6656 , n6657 );
xor ( n6659 , n6656 , n6657 );
xor ( n6660 , n6270 , n6396 );
nor ( n6661 , n5860 , n6653 );
and ( n6662 , n6660 , n6661 );
xor ( n6663 , n6660 , n6661 );
xor ( n6664 , n6274 , n6394 );
nor ( n6665 , n5462 , n6653 );
and ( n6666 , n6664 , n6665 );
xor ( n6667 , n6664 , n6665 );
xor ( n6668 , n6278 , n6392 );
nor ( n6669 , n5066 , n6653 );
and ( n6670 , n6668 , n6669 );
xor ( n6671 , n6668 , n6669 );
xor ( n6672 , n6282 , n6390 );
nor ( n6673 , n4668 , n6653 );
and ( n6674 , n6672 , n6673 );
xor ( n6675 , n6672 , n6673 );
xor ( n6676 , n6286 , n6388 );
nor ( n6677 , n4269 , n6653 );
and ( n6678 , n6676 , n6677 );
xor ( n6679 , n6676 , n6677 );
xor ( n6680 , n6290 , n6386 );
nor ( n6681 , n3872 , n6653 );
and ( n6682 , n6680 , n6681 );
xor ( n6683 , n6680 , n6681 );
xor ( n6684 , n6294 , n6384 );
nor ( n6685 , n3473 , n6653 );
and ( n6686 , n6684 , n6685 );
xor ( n6687 , n6684 , n6685 );
xor ( n6688 , n6298 , n6382 );
nor ( n6689 , n3000 , n6653 );
and ( n6690 , n6688 , n6689 );
xor ( n6691 , n6688 , n6689 );
xor ( n6692 , n6302 , n6380 );
nor ( n6693 , n2688 , n6653 );
and ( n6694 , n6692 , n6693 );
xor ( n6695 , n6692 , n6693 );
xor ( n6696 , n6306 , n6378 );
nor ( n6697 , n3008 , n6653 );
and ( n6698 , n6696 , n6697 );
xor ( n6699 , n6696 , n6697 );
xor ( n6700 , n6310 , n6376 );
nor ( n6701 , n3017 , n6653 );
and ( n6702 , n6700 , n6701 );
xor ( n6703 , n6700 , n6701 );
xor ( n6704 , n6314 , n6374 );
nor ( n6705 , n3026 , n6653 );
and ( n6706 , n6704 , n6705 );
xor ( n6707 , n6704 , n6705 );
xor ( n6708 , n6318 , n6372 );
nor ( n6709 , n3035 , n6653 );
and ( n6710 , n6708 , n6709 );
xor ( n6711 , n6708 , n6709 );
xor ( n6712 , n6322 , n6370 );
nor ( n6713 , n3044 , n6653 );
and ( n6714 , n6712 , n6713 );
xor ( n6715 , n6712 , n6713 );
xor ( n6716 , n6326 , n6368 );
nor ( n6717 , n3053 , n6653 );
and ( n6718 , n6716 , n6717 );
xor ( n6719 , n6716 , n6717 );
xor ( n6720 , n6330 , n6366 );
nor ( n6721 , n3062 , n6653 );
and ( n6722 , n6720 , n6721 );
xor ( n6723 , n6720 , n6721 );
xor ( n6724 , n6334 , n6364 );
nor ( n6725 , n3071 , n6653 );
and ( n6726 , n6724 , n6725 );
xor ( n6727 , n6724 , n6725 );
xor ( n6728 , n6338 , n6362 );
nor ( n6729 , n3080 , n6653 );
and ( n6730 , n6728 , n6729 );
xor ( n6731 , n6728 , n6729 );
xor ( n6732 , n6342 , n6360 );
nor ( n6733 , n3089 , n6653 );
and ( n6734 , n6732 , n6733 );
xor ( n6735 , n6732 , n6733 );
xor ( n6736 , n6346 , n6358 );
nor ( n6737 , n3098 , n6653 );
and ( n6738 , n6736 , n6737 );
xor ( n6739 , n6736 , n6737 );
xor ( n6740 , n6351 , n6356 );
nor ( n6741 , n3107 , n6653 );
and ( n6742 , n6740 , n6741 );
xor ( n6743 , n6740 , n6741 );
xor ( n6744 , n6353 , n6354 );
buf ( n6745 , n6744 );
nor ( n6746 , n3116 , n6653 );
and ( n6747 , n6745 , n6746 );
xor ( n6748 , n6745 , n6746 );
nor ( n6749 , n3134 , n6260 );
buf ( n6750 , n6749 );
nor ( n6751 , n3125 , n6653 );
and ( n6752 , n6750 , n6751 );
buf ( n6753 , n6752 );
and ( n6754 , n6748 , n6753 );
or ( n6755 , n6747 , n6754 );
and ( n6756 , n6743 , n6755 );
or ( n6757 , n6742 , n6756 );
and ( n6758 , n6739 , n6757 );
or ( n6759 , n6738 , n6758 );
and ( n6760 , n6735 , n6759 );
or ( n6761 , n6734 , n6760 );
and ( n6762 , n6731 , n6761 );
or ( n6763 , n6730 , n6762 );
and ( n6764 , n6727 , n6763 );
or ( n6765 , n6726 , n6764 );
and ( n6766 , n6723 , n6765 );
or ( n6767 , n6722 , n6766 );
and ( n6768 , n6719 , n6767 );
or ( n6769 , n6718 , n6768 );
and ( n6770 , n6715 , n6769 );
or ( n6771 , n6714 , n6770 );
and ( n6772 , n6711 , n6771 );
or ( n6773 , n6710 , n6772 );
and ( n6774 , n6707 , n6773 );
or ( n6775 , n6706 , n6774 );
and ( n6776 , n6703 , n6775 );
or ( n6777 , n6702 , n6776 );
and ( n6778 , n6699 , n6777 );
or ( n6779 , n6698 , n6778 );
and ( n6780 , n6695 , n6779 );
or ( n6781 , n6694 , n6780 );
and ( n6782 , n6691 , n6781 );
or ( n6783 , n6690 , n6782 );
and ( n6784 , n6687 , n6783 );
or ( n6785 , n6686 , n6784 );
and ( n6786 , n6683 , n6785 );
or ( n6787 , n6682 , n6786 );
and ( n6788 , n6679 , n6787 );
or ( n6789 , n6678 , n6788 );
and ( n6790 , n6675 , n6789 );
or ( n6791 , n6674 , n6790 );
and ( n6792 , n6671 , n6791 );
or ( n6793 , n6670 , n6792 );
and ( n6794 , n6667 , n6793 );
or ( n6795 , n6666 , n6794 );
and ( n6796 , n6663 , n6795 );
or ( n6797 , n6662 , n6796 );
and ( n6798 , n6659 , n6797 );
or ( n6799 , n6658 , n6798 );
xor ( n6800 , n6655 , n6799 );
and ( n6801 , n285 , n1533 );
nor ( n6802 , n1534 , n6801 );
nor ( n6803 , n1771 , n305 );
xor ( n6804 , n6802 , n6803 );
and ( n6805 , n6403 , n6404 );
and ( n6806 , n6405 , n6408 );
or ( n6807 , n6805 , n6806 );
xor ( n6808 , n6804 , n6807 );
nor ( n6809 , n2025 , n336 );
xor ( n6810 , n6808 , n6809 );
and ( n6811 , n6409 , n6410 );
and ( n6812 , n6411 , n6414 );
or ( n6813 , n6811 , n6812 );
xor ( n6814 , n6810 , n6813 );
nor ( n6815 , n2300 , n386 );
xor ( n6816 , n6814 , n6815 );
and ( n6817 , n6415 , n6416 );
and ( n6818 , n6417 , n6420 );
or ( n6819 , n6817 , n6818 );
xor ( n6820 , n6816 , n6819 );
nor ( n6821 , n2596 , n458 );
xor ( n6822 , n6820 , n6821 );
and ( n6823 , n6421 , n6422 );
and ( n6824 , n6423 , n6426 );
or ( n6825 , n6823 , n6824 );
xor ( n6826 , n6822 , n6825 );
nor ( n6827 , n2991 , n551 );
xor ( n6828 , n6826 , n6827 );
and ( n6829 , n6427 , n6428 );
and ( n6830 , n6429 , n6432 );
or ( n6831 , n6829 , n6830 );
xor ( n6832 , n6828 , n6831 );
nor ( n6833 , n3464 , n665 );
xor ( n6834 , n6832 , n6833 );
and ( n6835 , n6433 , n6434 );
and ( n6836 , n6435 , n6438 );
or ( n6837 , n6835 , n6836 );
xor ( n6838 , n6834 , n6837 );
nor ( n6839 , n3863 , n797 );
xor ( n6840 , n6838 , n6839 );
and ( n6841 , n6439 , n6440 );
and ( n6842 , n6441 , n6444 );
or ( n6843 , n6841 , n6842 );
xor ( n6844 , n6840 , n6843 );
nor ( n6845 , n4260 , n954 );
xor ( n6846 , n6844 , n6845 );
and ( n6847 , n6445 , n6446 );
and ( n6848 , n6447 , n6450 );
or ( n6849 , n6847 , n6848 );
xor ( n6850 , n6846 , n6849 );
nor ( n6851 , n4659 , n1128 );
xor ( n6852 , n6850 , n6851 );
and ( n6853 , n6451 , n6452 );
and ( n6854 , n6453 , n6456 );
or ( n6855 , n6853 , n6854 );
xor ( n6856 , n6852 , n6855 );
nor ( n6857 , n5057 , n1320 );
xor ( n6858 , n6856 , n6857 );
and ( n6859 , n6457 , n6458 );
and ( n6860 , n6459 , n6462 );
or ( n6861 , n6859 , n6860 );
xor ( n6862 , n6858 , n6861 );
nor ( n6863 , n5453 , n1536 );
xor ( n6864 , n6862 , n6863 );
and ( n6865 , n6463 , n6464 );
and ( n6866 , n6465 , n6468 );
or ( n6867 , n6865 , n6866 );
xor ( n6868 , n6864 , n6867 );
nor ( n6869 , n5851 , n1773 );
xor ( n6870 , n6868 , n6869 );
and ( n6871 , n6469 , n6470 );
and ( n6872 , n6471 , n6474 );
or ( n6873 , n6871 , n6872 );
xor ( n6874 , n6870 , n6873 );
nor ( n6875 , n6249 , n2027 );
xor ( n6876 , n6874 , n6875 );
and ( n6877 , n6475 , n6476 );
and ( n6878 , n6477 , n6480 );
or ( n6879 , n6877 , n6878 );
xor ( n6880 , n6876 , n6879 );
nor ( n6881 , n6642 , n2302 );
xor ( n6882 , n6880 , n6881 );
and ( n6883 , n6481 , n6482 );
and ( n6884 , n6483 , n6486 );
or ( n6885 , n6883 , n6884 );
xor ( n6886 , n6882 , n6885 );
and ( n6887 , n6504 , n6508 );
and ( n6888 , n6508 , n6512 );
and ( n6889 , n6504 , n6512 );
or ( n6890 , n6887 , n6888 , n6889 );
and ( n6891 , n6500 , n6513 );
and ( n6892 , n6513 , n6628 );
and ( n6893 , n6500 , n6628 );
or ( n6894 , n6891 , n6892 , n6893 );
xor ( n6895 , n6890 , n6894 );
and ( n6896 , n6518 , n6544 );
and ( n6897 , n6544 , n6627 );
and ( n6898 , n6518 , n6627 );
or ( n6899 , n6896 , n6897 , n6898 );
and ( n6900 , n6532 , n6533 );
and ( n6901 , n6533 , n6535 );
and ( n6902 , n6532 , n6535 );
or ( n6903 , n6900 , n6901 , n6902 );
and ( n6904 , n6522 , n6526 );
and ( n6905 , n6526 , n6543 );
and ( n6906 , n6522 , n6543 );
or ( n6907 , n6904 , n6905 , n6906 );
xor ( n6908 , n6903 , n6907 );
not ( n6909 , n1516 );
and ( n6910 , n2406 , n1516 );
nor ( n6911 , n6909 , n6910 );
xor ( n6912 , n6908 , n6911 );
xor ( n6913 , n6899 , n6912 );
and ( n6914 , n6549 , n6564 );
and ( n6915 , n6564 , n6626 );
and ( n6916 , n6549 , n6626 );
or ( n6917 , n6914 , n6915 , n6916 );
and ( n6918 , n6531 , n6536 );
and ( n6919 , n6536 , n6542 );
and ( n6920 , n6531 , n6542 );
or ( n6921 , n6918 , n6919 , n6920 );
and ( n6922 , n6553 , n6557 );
and ( n6923 , n6557 , n6563 );
and ( n6924 , n6553 , n6563 );
or ( n6925 , n6922 , n6923 , n6924 );
xor ( n6926 , n6921 , n6925 );
and ( n6927 , n6538 , n6539 );
and ( n6928 , n6539 , n6541 );
and ( n6929 , n6538 , n6541 );
or ( n6930 , n6927 , n6928 , n6929 );
and ( n6931 , n1730 , n2138 );
and ( n6932 , n2001 , n1864 );
xor ( n6933 , n6931 , n6932 );
and ( n6934 , n2286 , n1753 );
xor ( n6935 , n6933 , n6934 );
xor ( n6936 , n6930 , n6935 );
and ( n6937 , n2581 , n1396 );
and ( n6938 , n2972 , n1302 );
xor ( n6939 , n6937 , n6938 );
and ( n6940 , n3445 , n1114 );
xor ( n6941 , n6939 , n6940 );
xor ( n6942 , n6936 , n6941 );
xor ( n6943 , n6926 , n6942 );
xor ( n6944 , n6917 , n6943 );
and ( n6945 , n6569 , n6574 );
and ( n6946 , n6574 , n6625 );
and ( n6947 , n6569 , n6625 );
or ( n6948 , n6945 , n6946 , n6947 );
and ( n6949 , n6559 , n6560 );
and ( n6950 , n6560 , n6562 );
and ( n6951 , n6559 , n6562 );
or ( n6952 , n6949 , n6950 , n6951 );
and ( n6953 , n6570 , n6571 );
and ( n6954 , n6571 , n6573 );
and ( n6955 , n6570 , n6573 );
or ( n6956 , n6953 , n6954 , n6955 );
xor ( n6957 , n6952 , n6956 );
and ( n6958 , n3844 , n852 );
and ( n6959 , n4241 , n714 );
xor ( n6960 , n6958 , n6959 );
and ( n6961 , n4640 , n651 );
xor ( n6962 , n6960 , n6961 );
xor ( n6963 , n6957 , n6962 );
xor ( n6964 , n6948 , n6963 );
and ( n6965 , n6576 , n6577 );
and ( n6966 , n6577 , n6624 );
and ( n6967 , n6576 , n6624 );
or ( n6968 , n6965 , n6966 , n6967 );
and ( n6969 , n5038 , n488 );
and ( n6970 , n5434 , n411 );
xor ( n6971 , n6969 , n6970 );
and ( n6972 , n5832 , n375 );
xor ( n6973 , n6971 , n6972 );
xor ( n6974 , n6968 , n6973 );
and ( n6975 , n6230 , n312 );
and ( n6976 , n6623 , n288 );
xor ( n6977 , n6975 , n6976 );
and ( n6978 , n6588 , n6589 );
and ( n6979 , n6589 , n6593 );
and ( n6980 , n6588 , n6593 );
or ( n6981 , n6978 , n6979 , n6980 );
and ( n6982 , n6594 , n6610 );
xor ( n6983 , n6981 , n6982 );
and ( n6984 , n6604 , n6605 );
and ( n6985 , n6605 , n6607 );
and ( n6986 , n6604 , n6607 );
or ( n6987 , n6984 , n6985 , n6986 );
and ( n6988 , n6598 , n6609 );
xor ( n6989 , n6987 , n6988 );
and ( n6990 , n2206 , n1685 );
not ( n6991 , n1685 );
nor ( n6992 , n6990 , n6991 );
xor ( n6993 , n6989 , n6992 );
and ( n6994 , n6599 , n6602 );
and ( n6995 , n6602 , n6608 );
and ( n6996 , n6599 , n6608 );
or ( n6997 , n6994 , n6995 , n6996 );
not ( n6998 , n1458 );
and ( n6999 , n2563 , n1458 );
nor ( n7000 , n6998 , n6999 );
and ( n7001 , n1713 , n2271 );
xor ( n7002 , n7000 , n7001 );
and ( n7003 , n1935 , n1975 );
xor ( n7004 , n7002 , n7003 );
xor ( n7005 , n6997 , n7004 );
xor ( n7006 , n6993 , n7005 );
xor ( n7007 , n6983 , n7006 );
and ( n7008 , n6582 , n6583 );
and ( n7009 , n6583 , n6611 );
and ( n7010 , n6582 , n6611 );
or ( n7011 , n7008 , n7009 , n7010 );
xor ( n7012 , n7007 , n7011 );
and ( n7013 , n6612 , n6616 );
and ( n7014 , n6617 , n6620 );
or ( n7015 , n7013 , n7014 );
xor ( n7016 , n7012 , n7015 );
buf ( n7017 , n7016 );
buf ( n7018 , n7017 );
and ( n7019 , n7018 , n279 );
xor ( n7020 , n6977 , n7019 );
xor ( n7021 , n6974 , n7020 );
xor ( n7022 , n6964 , n7021 );
xor ( n7023 , n6944 , n7022 );
xor ( n7024 , n6913 , n7023 );
xor ( n7025 , n6895 , n7024 );
and ( n7026 , n6491 , n6495 );
and ( n7027 , n6495 , n6629 );
and ( n7028 , n6491 , n6629 );
or ( n7029 , n7026 , n7027 , n7028 );
xor ( n7030 , n7025 , n7029 );
and ( n7031 , n6630 , n6634 );
and ( n7032 , n6635 , n6638 );
or ( n7033 , n7031 , n7032 );
xor ( n7034 , n7030 , n7033 );
buf ( n7035 , n7034 );
buf ( n7036 , n7035 );
not ( n7037 , n7036 );
nor ( n7038 , n7037 , n2598 );
xor ( n7039 , n6886 , n7038 );
and ( n7040 , n6487 , n6643 );
and ( n7041 , n6644 , n6647 );
or ( n7042 , n7040 , n7041 );
xor ( n7043 , n7039 , n7042 );
buf ( n7044 , n7043 );
buf ( n7045 , n7044 );
not ( n7046 , n7045 );
buf ( n7047 , n268 );
not ( n7048 , n7047 );
nor ( n7049 , n7046 , n7048 );
xor ( n7050 , n6800 , n7049 );
xor ( n7051 , n6659 , n6797 );
nor ( n7052 , n6651 , n7048 );
and ( n7053 , n7051 , n7052 );
xor ( n7054 , n7051 , n7052 );
xor ( n7055 , n6663 , n6795 );
nor ( n7056 , n6258 , n7048 );
and ( n7057 , n7055 , n7056 );
xor ( n7058 , n7055 , n7056 );
xor ( n7059 , n6667 , n6793 );
nor ( n7060 , n5860 , n7048 );
and ( n7061 , n7059 , n7060 );
xor ( n7062 , n7059 , n7060 );
xor ( n7063 , n6671 , n6791 );
nor ( n7064 , n5462 , n7048 );
and ( n7065 , n7063 , n7064 );
xor ( n7066 , n7063 , n7064 );
xor ( n7067 , n6675 , n6789 );
nor ( n7068 , n5066 , n7048 );
and ( n7069 , n7067 , n7068 );
xor ( n7070 , n7067 , n7068 );
xor ( n7071 , n6679 , n6787 );
nor ( n7072 , n4668 , n7048 );
and ( n7073 , n7071 , n7072 );
xor ( n7074 , n7071 , n7072 );
xor ( n7075 , n6683 , n6785 );
nor ( n7076 , n4269 , n7048 );
and ( n7077 , n7075 , n7076 );
xor ( n7078 , n7075 , n7076 );
xor ( n7079 , n6687 , n6783 );
nor ( n7080 , n3872 , n7048 );
and ( n7081 , n7079 , n7080 );
xor ( n7082 , n7079 , n7080 );
xor ( n7083 , n6691 , n6781 );
nor ( n7084 , n3473 , n7048 );
and ( n7085 , n7083 , n7084 );
xor ( n7086 , n7083 , n7084 );
xor ( n7087 , n6695 , n6779 );
nor ( n7088 , n3000 , n7048 );
and ( n7089 , n7087 , n7088 );
xor ( n7090 , n7087 , n7088 );
xor ( n7091 , n6699 , n6777 );
nor ( n7092 , n2688 , n7048 );
and ( n7093 , n7091 , n7092 );
xor ( n7094 , n7091 , n7092 );
xor ( n7095 , n6703 , n6775 );
nor ( n7096 , n3008 , n7048 );
and ( n7097 , n7095 , n7096 );
xor ( n7098 , n7095 , n7096 );
xor ( n7099 , n6707 , n6773 );
nor ( n7100 , n3017 , n7048 );
and ( n7101 , n7099 , n7100 );
xor ( n7102 , n7099 , n7100 );
xor ( n7103 , n6711 , n6771 );
nor ( n7104 , n3026 , n7048 );
and ( n7105 , n7103 , n7104 );
xor ( n7106 , n7103 , n7104 );
xor ( n7107 , n6715 , n6769 );
nor ( n7108 , n3035 , n7048 );
and ( n7109 , n7107 , n7108 );
xor ( n7110 , n7107 , n7108 );
xor ( n7111 , n6719 , n6767 );
nor ( n7112 , n3044 , n7048 );
and ( n7113 , n7111 , n7112 );
xor ( n7114 , n7111 , n7112 );
xor ( n7115 , n6723 , n6765 );
nor ( n7116 , n3053 , n7048 );
and ( n7117 , n7115 , n7116 );
xor ( n7118 , n7115 , n7116 );
xor ( n7119 , n6727 , n6763 );
nor ( n7120 , n3062 , n7048 );
and ( n7121 , n7119 , n7120 );
xor ( n7122 , n7119 , n7120 );
xor ( n7123 , n6731 , n6761 );
nor ( n7124 , n3071 , n7048 );
and ( n7125 , n7123 , n7124 );
xor ( n7126 , n7123 , n7124 );
xor ( n7127 , n6735 , n6759 );
nor ( n7128 , n3080 , n7048 );
and ( n7129 , n7127 , n7128 );
xor ( n7130 , n7127 , n7128 );
xor ( n7131 , n6739 , n6757 );
nor ( n7132 , n3089 , n7048 );
and ( n7133 , n7131 , n7132 );
xor ( n7134 , n7131 , n7132 );
xor ( n7135 , n6743 , n6755 );
nor ( n7136 , n3098 , n7048 );
and ( n7137 , n7135 , n7136 );
xor ( n7138 , n7135 , n7136 );
xor ( n7139 , n6748 , n6753 );
nor ( n7140 , n3107 , n7048 );
and ( n7141 , n7139 , n7140 );
xor ( n7142 , n7139 , n7140 );
xor ( n7143 , n6750 , n6751 );
buf ( n7144 , n7143 );
nor ( n7145 , n3116 , n7048 );
and ( n7146 , n7144 , n7145 );
xor ( n7147 , n7144 , n7145 );
nor ( n7148 , n3134 , n6653 );
buf ( n7149 , n7148 );
nor ( n7150 , n3125 , n7048 );
and ( n7151 , n7149 , n7150 );
buf ( n7152 , n7151 );
and ( n7153 , n7147 , n7152 );
or ( n7154 , n7146 , n7153 );
and ( n7155 , n7142 , n7154 );
or ( n7156 , n7141 , n7155 );
and ( n7157 , n7138 , n7156 );
or ( n7158 , n7137 , n7157 );
and ( n7159 , n7134 , n7158 );
or ( n7160 , n7133 , n7159 );
and ( n7161 , n7130 , n7160 );
or ( n7162 , n7129 , n7161 );
and ( n7163 , n7126 , n7162 );
or ( n7164 , n7125 , n7163 );
and ( n7165 , n7122 , n7164 );
or ( n7166 , n7121 , n7165 );
and ( n7167 , n7118 , n7166 );
or ( n7168 , n7117 , n7167 );
and ( n7169 , n7114 , n7168 );
or ( n7170 , n7113 , n7169 );
and ( n7171 , n7110 , n7170 );
or ( n7172 , n7109 , n7171 );
and ( n7173 , n7106 , n7172 );
or ( n7174 , n7105 , n7173 );
and ( n7175 , n7102 , n7174 );
or ( n7176 , n7101 , n7175 );
and ( n7177 , n7098 , n7176 );
or ( n7178 , n7097 , n7177 );
and ( n7179 , n7094 , n7178 );
or ( n7180 , n7093 , n7179 );
and ( n7181 , n7090 , n7180 );
or ( n7182 , n7089 , n7181 );
and ( n7183 , n7086 , n7182 );
or ( n7184 , n7085 , n7183 );
and ( n7185 , n7082 , n7184 );
or ( n7186 , n7081 , n7185 );
and ( n7187 , n7078 , n7186 );
or ( n7188 , n7077 , n7187 );
and ( n7189 , n7074 , n7188 );
or ( n7190 , n7073 , n7189 );
and ( n7191 , n7070 , n7190 );
or ( n7192 , n7069 , n7191 );
and ( n7193 , n7066 , n7192 );
or ( n7194 , n7065 , n7193 );
and ( n7195 , n7062 , n7194 );
or ( n7196 , n7061 , n7195 );
and ( n7197 , n7058 , n7196 );
or ( n7198 , n7057 , n7197 );
and ( n7199 , n7054 , n7198 );
or ( n7200 , n7053 , n7199 );
xor ( n7201 , n7050 , n7200 );
and ( n7202 , n285 , n1770 );
nor ( n7203 , n1771 , n7202 );
nor ( n7204 , n2025 , n305 );
xor ( n7205 , n7203 , n7204 );
and ( n7206 , n6802 , n6803 );
and ( n7207 , n6804 , n6807 );
or ( n7208 , n7206 , n7207 );
xor ( n7209 , n7205 , n7208 );
nor ( n7210 , n2300 , n336 );
xor ( n7211 , n7209 , n7210 );
and ( n7212 , n6808 , n6809 );
and ( n7213 , n6810 , n6813 );
or ( n7214 , n7212 , n7213 );
xor ( n7215 , n7211 , n7214 );
nor ( n7216 , n2596 , n386 );
xor ( n7217 , n7215 , n7216 );
and ( n7218 , n6814 , n6815 );
and ( n7219 , n6816 , n6819 );
or ( n7220 , n7218 , n7219 );
xor ( n7221 , n7217 , n7220 );
nor ( n7222 , n2991 , n458 );
xor ( n7223 , n7221 , n7222 );
and ( n7224 , n6820 , n6821 );
and ( n7225 , n6822 , n6825 );
or ( n7226 , n7224 , n7225 );
xor ( n7227 , n7223 , n7226 );
nor ( n7228 , n3464 , n551 );
xor ( n7229 , n7227 , n7228 );
and ( n7230 , n6826 , n6827 );
and ( n7231 , n6828 , n6831 );
or ( n7232 , n7230 , n7231 );
xor ( n7233 , n7229 , n7232 );
nor ( n7234 , n3863 , n665 );
xor ( n7235 , n7233 , n7234 );
and ( n7236 , n6832 , n6833 );
and ( n7237 , n6834 , n6837 );
or ( n7238 , n7236 , n7237 );
xor ( n7239 , n7235 , n7238 );
nor ( n7240 , n4260 , n797 );
xor ( n7241 , n7239 , n7240 );
and ( n7242 , n6838 , n6839 );
and ( n7243 , n6840 , n6843 );
or ( n7244 , n7242 , n7243 );
xor ( n7245 , n7241 , n7244 );
nor ( n7246 , n4659 , n954 );
xor ( n7247 , n7245 , n7246 );
and ( n7248 , n6844 , n6845 );
and ( n7249 , n6846 , n6849 );
or ( n7250 , n7248 , n7249 );
xor ( n7251 , n7247 , n7250 );
nor ( n7252 , n5057 , n1128 );
xor ( n7253 , n7251 , n7252 );
and ( n7254 , n6850 , n6851 );
and ( n7255 , n6852 , n6855 );
or ( n7256 , n7254 , n7255 );
xor ( n7257 , n7253 , n7256 );
nor ( n7258 , n5453 , n1320 );
xor ( n7259 , n7257 , n7258 );
and ( n7260 , n6856 , n6857 );
and ( n7261 , n6858 , n6861 );
or ( n7262 , n7260 , n7261 );
xor ( n7263 , n7259 , n7262 );
nor ( n7264 , n5851 , n1536 );
xor ( n7265 , n7263 , n7264 );
and ( n7266 , n6862 , n6863 );
and ( n7267 , n6864 , n6867 );
or ( n7268 , n7266 , n7267 );
xor ( n7269 , n7265 , n7268 );
nor ( n7270 , n6249 , n1773 );
xor ( n7271 , n7269 , n7270 );
and ( n7272 , n6868 , n6869 );
and ( n7273 , n6870 , n6873 );
or ( n7274 , n7272 , n7273 );
xor ( n7275 , n7271 , n7274 );
nor ( n7276 , n6642 , n2027 );
xor ( n7277 , n7275 , n7276 );
and ( n7278 , n6874 , n6875 );
and ( n7279 , n6876 , n6879 );
or ( n7280 , n7278 , n7279 );
xor ( n7281 , n7277 , n7280 );
nor ( n7282 , n7037 , n2302 );
xor ( n7283 , n7281 , n7282 );
and ( n7284 , n6880 , n6881 );
and ( n7285 , n6882 , n6885 );
or ( n7286 , n7284 , n7285 );
xor ( n7287 , n7283 , n7286 );
and ( n7288 , n6903 , n6907 );
and ( n7289 , n6907 , n6911 );
and ( n7290 , n6903 , n6911 );
or ( n7291 , n7288 , n7289 , n7290 );
and ( n7292 , n6899 , n6912 );
and ( n7293 , n6912 , n7023 );
and ( n7294 , n6899 , n7023 );
or ( n7295 , n7292 , n7293 , n7294 );
xor ( n7296 , n7291 , n7295 );
and ( n7297 , n6917 , n6943 );
and ( n7298 , n6943 , n7022 );
and ( n7299 , n6917 , n7022 );
or ( n7300 , n7297 , n7298 , n7299 );
and ( n7301 , n6931 , n6932 );
and ( n7302 , n6932 , n6934 );
and ( n7303 , n6931 , n6934 );
or ( n7304 , n7301 , n7302 , n7303 );
and ( n7305 , n6921 , n6925 );
and ( n7306 , n6925 , n6942 );
and ( n7307 , n6921 , n6942 );
or ( n7308 , n7305 , n7306 , n7307 );
xor ( n7309 , n7304 , n7308 );
not ( n7310 , n1730 );
and ( n7311 , n2406 , n1730 );
nor ( n7312 , n7310 , n7311 );
xor ( n7313 , n7309 , n7312 );
xor ( n7314 , n7300 , n7313 );
and ( n7315 , n6948 , n6963 );
and ( n7316 , n6963 , n7021 );
and ( n7317 , n6948 , n7021 );
or ( n7318 , n7315 , n7316 , n7317 );
and ( n7319 , n6930 , n6935 );
and ( n7320 , n6935 , n6941 );
and ( n7321 , n6930 , n6941 );
or ( n7322 , n7319 , n7320 , n7321 );
and ( n7323 , n6952 , n6956 );
and ( n7324 , n6956 , n6962 );
and ( n7325 , n6952 , n6962 );
or ( n7326 , n7323 , n7324 , n7325 );
xor ( n7327 , n7322 , n7326 );
and ( n7328 , n6937 , n6938 );
and ( n7329 , n6938 , n6940 );
and ( n7330 , n6937 , n6940 );
or ( n7331 , n7328 , n7329 , n7330 );
and ( n7332 , n2001 , n2138 );
and ( n7333 , n2286 , n1864 );
xor ( n7334 , n7332 , n7333 );
and ( n7335 , n2581 , n1753 );
xor ( n7336 , n7334 , n7335 );
xor ( n7337 , n7331 , n7336 );
and ( n7338 , n2972 , n1396 );
and ( n7339 , n3445 , n1302 );
xor ( n7340 , n7338 , n7339 );
and ( n7341 , n3844 , n1114 );
xor ( n7342 , n7340 , n7341 );
xor ( n7343 , n7337 , n7342 );
xor ( n7344 , n7327 , n7343 );
xor ( n7345 , n7318 , n7344 );
and ( n7346 , n6968 , n6973 );
and ( n7347 , n6973 , n7020 );
and ( n7348 , n6968 , n7020 );
or ( n7349 , n7346 , n7347 , n7348 );
and ( n7350 , n6958 , n6959 );
and ( n7351 , n6959 , n6961 );
and ( n7352 , n6958 , n6961 );
or ( n7353 , n7350 , n7351 , n7352 );
and ( n7354 , n6969 , n6970 );
and ( n7355 , n6970 , n6972 );
and ( n7356 , n6969 , n6972 );
or ( n7357 , n7354 , n7355 , n7356 );
xor ( n7358 , n7353 , n7357 );
and ( n7359 , n4241 , n852 );
and ( n7360 , n4640 , n714 );
xor ( n7361 , n7359 , n7360 );
and ( n7362 , n5038 , n651 );
xor ( n7363 , n7361 , n7362 );
xor ( n7364 , n7358 , n7363 );
xor ( n7365 , n7349 , n7364 );
and ( n7366 , n6975 , n6976 );
and ( n7367 , n6976 , n7019 );
and ( n7368 , n6975 , n7019 );
or ( n7369 , n7366 , n7367 , n7368 );
and ( n7370 , n5434 , n488 );
and ( n7371 , n5832 , n411 );
xor ( n7372 , n7370 , n7371 );
and ( n7373 , n6230 , n375 );
xor ( n7374 , n7372 , n7373 );
xor ( n7375 , n7369 , n7374 );
and ( n7376 , n6623 , n312 );
and ( n7377 , n7018 , n288 );
xor ( n7378 , n7376 , n7377 );
and ( n7379 , n6987 , n6988 );
and ( n7380 , n6988 , n6992 );
and ( n7381 , n6987 , n6992 );
or ( n7382 , n7379 , n7380 , n7381 );
and ( n7383 , n6993 , n7005 );
xor ( n7384 , n7382 , n7383 );
and ( n7385 , n7000 , n7001 );
and ( n7386 , n7001 , n7003 );
and ( n7387 , n7000 , n7003 );
or ( n7388 , n7385 , n7386 , n7387 );
and ( n7389 , n6997 , n7004 );
xor ( n7390 , n7388 , n7389 );
and ( n7391 , n2206 , n1975 );
not ( n7392 , n1975 );
nor ( n7393 , n7391 , n7392 );
xor ( n7394 , n7390 , n7393 );
not ( n7395 , n1713 );
and ( n7396 , n2563 , n1713 );
nor ( n7397 , n7395 , n7396 );
and ( n7398 , n1935 , n2271 );
xor ( n7399 , n7397 , n7398 );
xor ( n7400 , n7394 , n7399 );
xor ( n7401 , n7384 , n7400 );
and ( n7402 , n6981 , n6982 );
and ( n7403 , n6982 , n7006 );
and ( n7404 , n6981 , n7006 );
or ( n7405 , n7402 , n7403 , n7404 );
xor ( n7406 , n7401 , n7405 );
and ( n7407 , n7007 , n7011 );
and ( n7408 , n7012 , n7015 );
or ( n7409 , n7407 , n7408 );
xor ( n7410 , n7406 , n7409 );
buf ( n7411 , n7410 );
buf ( n7412 , n7411 );
and ( n7413 , n7412 , n279 );
xor ( n7414 , n7378 , n7413 );
xor ( n7415 , n7375 , n7414 );
xor ( n7416 , n7365 , n7415 );
xor ( n7417 , n7345 , n7416 );
xor ( n7418 , n7314 , n7417 );
xor ( n7419 , n7296 , n7418 );
and ( n7420 , n6890 , n6894 );
and ( n7421 , n6894 , n7024 );
and ( n7422 , n6890 , n7024 );
or ( n7423 , n7420 , n7421 , n7422 );
xor ( n7424 , n7419 , n7423 );
and ( n7425 , n7025 , n7029 );
and ( n7426 , n7030 , n7033 );
or ( n7427 , n7425 , n7426 );
xor ( n7428 , n7424 , n7427 );
buf ( n7429 , n7428 );
buf ( n7430 , n7429 );
not ( n7431 , n7430 );
nor ( n7432 , n7431 , n2598 );
xor ( n7433 , n7287 , n7432 );
and ( n7434 , n6886 , n7038 );
and ( n7435 , n7039 , n7042 );
or ( n7436 , n7434 , n7435 );
xor ( n7437 , n7433 , n7436 );
buf ( n7438 , n7437 );
buf ( n7439 , n7438 );
not ( n7440 , n7439 );
buf ( n7441 , n269 );
not ( n7442 , n7441 );
nor ( n7443 , n7440 , n7442 );
xor ( n7444 , n7201 , n7443 );
xor ( n7445 , n7054 , n7198 );
nor ( n7446 , n7046 , n7442 );
and ( n7447 , n7445 , n7446 );
xor ( n7448 , n7445 , n7446 );
xor ( n7449 , n7058 , n7196 );
nor ( n7450 , n6651 , n7442 );
and ( n7451 , n7449 , n7450 );
xor ( n7452 , n7449 , n7450 );
xor ( n7453 , n7062 , n7194 );
nor ( n7454 , n6258 , n7442 );
and ( n7455 , n7453 , n7454 );
xor ( n7456 , n7453 , n7454 );
xor ( n7457 , n7066 , n7192 );
nor ( n7458 , n5860 , n7442 );
and ( n7459 , n7457 , n7458 );
xor ( n7460 , n7457 , n7458 );
xor ( n7461 , n7070 , n7190 );
nor ( n7462 , n5462 , n7442 );
and ( n7463 , n7461 , n7462 );
xor ( n7464 , n7461 , n7462 );
xor ( n7465 , n7074 , n7188 );
nor ( n7466 , n5066 , n7442 );
and ( n7467 , n7465 , n7466 );
xor ( n7468 , n7465 , n7466 );
xor ( n7469 , n7078 , n7186 );
nor ( n7470 , n4668 , n7442 );
and ( n7471 , n7469 , n7470 );
xor ( n7472 , n7469 , n7470 );
xor ( n7473 , n7082 , n7184 );
nor ( n7474 , n4269 , n7442 );
and ( n7475 , n7473 , n7474 );
xor ( n7476 , n7473 , n7474 );
xor ( n7477 , n7086 , n7182 );
nor ( n7478 , n3872 , n7442 );
and ( n7479 , n7477 , n7478 );
xor ( n7480 , n7477 , n7478 );
xor ( n7481 , n7090 , n7180 );
nor ( n7482 , n3473 , n7442 );
and ( n7483 , n7481 , n7482 );
xor ( n7484 , n7481 , n7482 );
xor ( n7485 , n7094 , n7178 );
nor ( n7486 , n3000 , n7442 );
and ( n7487 , n7485 , n7486 );
xor ( n7488 , n7485 , n7486 );
xor ( n7489 , n7098 , n7176 );
nor ( n7490 , n2688 , n7442 );
and ( n7491 , n7489 , n7490 );
xor ( n7492 , n7489 , n7490 );
xor ( n7493 , n7102 , n7174 );
nor ( n7494 , n3008 , n7442 );
and ( n7495 , n7493 , n7494 );
xor ( n7496 , n7493 , n7494 );
xor ( n7497 , n7106 , n7172 );
nor ( n7498 , n3017 , n7442 );
and ( n7499 , n7497 , n7498 );
xor ( n7500 , n7497 , n7498 );
xor ( n7501 , n7110 , n7170 );
nor ( n7502 , n3026 , n7442 );
and ( n7503 , n7501 , n7502 );
xor ( n7504 , n7501 , n7502 );
xor ( n7505 , n7114 , n7168 );
nor ( n7506 , n3035 , n7442 );
and ( n7507 , n7505 , n7506 );
xor ( n7508 , n7505 , n7506 );
xor ( n7509 , n7118 , n7166 );
nor ( n7510 , n3044 , n7442 );
and ( n7511 , n7509 , n7510 );
xor ( n7512 , n7509 , n7510 );
xor ( n7513 , n7122 , n7164 );
nor ( n7514 , n3053 , n7442 );
and ( n7515 , n7513 , n7514 );
xor ( n7516 , n7513 , n7514 );
xor ( n7517 , n7126 , n7162 );
nor ( n7518 , n3062 , n7442 );
and ( n7519 , n7517 , n7518 );
xor ( n7520 , n7517 , n7518 );
xor ( n7521 , n7130 , n7160 );
nor ( n7522 , n3071 , n7442 );
and ( n7523 , n7521 , n7522 );
xor ( n7524 , n7521 , n7522 );
xor ( n7525 , n7134 , n7158 );
nor ( n7526 , n3080 , n7442 );
and ( n7527 , n7525 , n7526 );
xor ( n7528 , n7525 , n7526 );
xor ( n7529 , n7138 , n7156 );
nor ( n7530 , n3089 , n7442 );
and ( n7531 , n7529 , n7530 );
xor ( n7532 , n7529 , n7530 );
xor ( n7533 , n7142 , n7154 );
nor ( n7534 , n3098 , n7442 );
and ( n7535 , n7533 , n7534 );
xor ( n7536 , n7533 , n7534 );
xor ( n7537 , n7147 , n7152 );
nor ( n7538 , n3107 , n7442 );
and ( n7539 , n7537 , n7538 );
xor ( n7540 , n7537 , n7538 );
xor ( n7541 , n7149 , n7150 );
buf ( n7542 , n7541 );
nor ( n7543 , n3116 , n7442 );
and ( n7544 , n7542 , n7543 );
xor ( n7545 , n7542 , n7543 );
nor ( n7546 , n3134 , n7048 );
buf ( n7547 , n7546 );
nor ( n7548 , n3125 , n7442 );
and ( n7549 , n7547 , n7548 );
buf ( n7550 , n7549 );
and ( n7551 , n7545 , n7550 );
or ( n7552 , n7544 , n7551 );
and ( n7553 , n7540 , n7552 );
or ( n7554 , n7539 , n7553 );
and ( n7555 , n7536 , n7554 );
or ( n7556 , n7535 , n7555 );
and ( n7557 , n7532 , n7556 );
or ( n7558 , n7531 , n7557 );
and ( n7559 , n7528 , n7558 );
or ( n7560 , n7527 , n7559 );
and ( n7561 , n7524 , n7560 );
or ( n7562 , n7523 , n7561 );
and ( n7563 , n7520 , n7562 );
or ( n7564 , n7519 , n7563 );
and ( n7565 , n7516 , n7564 );
or ( n7566 , n7515 , n7565 );
and ( n7567 , n7512 , n7566 );
or ( n7568 , n7511 , n7567 );
and ( n7569 , n7508 , n7568 );
or ( n7570 , n7507 , n7569 );
and ( n7571 , n7504 , n7570 );
or ( n7572 , n7503 , n7571 );
and ( n7573 , n7500 , n7572 );
or ( n7574 , n7499 , n7573 );
and ( n7575 , n7496 , n7574 );
or ( n7576 , n7495 , n7575 );
and ( n7577 , n7492 , n7576 );
or ( n7578 , n7491 , n7577 );
and ( n7579 , n7488 , n7578 );
or ( n7580 , n7487 , n7579 );
and ( n7581 , n7484 , n7580 );
or ( n7582 , n7483 , n7581 );
and ( n7583 , n7480 , n7582 );
or ( n7584 , n7479 , n7583 );
and ( n7585 , n7476 , n7584 );
or ( n7586 , n7475 , n7585 );
and ( n7587 , n7472 , n7586 );
or ( n7588 , n7471 , n7587 );
and ( n7589 , n7468 , n7588 );
or ( n7590 , n7467 , n7589 );
and ( n7591 , n7464 , n7590 );
or ( n7592 , n7463 , n7591 );
and ( n7593 , n7460 , n7592 );
or ( n7594 , n7459 , n7593 );
and ( n7595 , n7456 , n7594 );
or ( n7596 , n7455 , n7595 );
and ( n7597 , n7452 , n7596 );
or ( n7598 , n7451 , n7597 );
and ( n7599 , n7448 , n7598 );
or ( n7600 , n7447 , n7599 );
xor ( n7601 , n7444 , n7600 );
and ( n7602 , n285 , n2024 );
nor ( n7603 , n2025 , n7602 );
nor ( n7604 , n2300 , n305 );
xor ( n7605 , n7603 , n7604 );
and ( n7606 , n7203 , n7204 );
and ( n7607 , n7205 , n7208 );
or ( n7608 , n7606 , n7607 );
xor ( n7609 , n7605 , n7608 );
nor ( n7610 , n2596 , n336 );
xor ( n7611 , n7609 , n7610 );
and ( n7612 , n7209 , n7210 );
and ( n7613 , n7211 , n7214 );
or ( n7614 , n7612 , n7613 );
xor ( n7615 , n7611 , n7614 );
nor ( n7616 , n2991 , n386 );
xor ( n7617 , n7615 , n7616 );
and ( n7618 , n7215 , n7216 );
and ( n7619 , n7217 , n7220 );
or ( n7620 , n7618 , n7619 );
xor ( n7621 , n7617 , n7620 );
nor ( n7622 , n3464 , n458 );
xor ( n7623 , n7621 , n7622 );
and ( n7624 , n7221 , n7222 );
and ( n7625 , n7223 , n7226 );
or ( n7626 , n7624 , n7625 );
xor ( n7627 , n7623 , n7626 );
nor ( n7628 , n3863 , n551 );
xor ( n7629 , n7627 , n7628 );
and ( n7630 , n7227 , n7228 );
and ( n7631 , n7229 , n7232 );
or ( n7632 , n7630 , n7631 );
xor ( n7633 , n7629 , n7632 );
nor ( n7634 , n4260 , n665 );
xor ( n7635 , n7633 , n7634 );
and ( n7636 , n7233 , n7234 );
and ( n7637 , n7235 , n7238 );
or ( n7638 , n7636 , n7637 );
xor ( n7639 , n7635 , n7638 );
nor ( n7640 , n4659 , n797 );
xor ( n7641 , n7639 , n7640 );
and ( n7642 , n7239 , n7240 );
and ( n7643 , n7241 , n7244 );
or ( n7644 , n7642 , n7643 );
xor ( n7645 , n7641 , n7644 );
nor ( n7646 , n5057 , n954 );
xor ( n7647 , n7645 , n7646 );
and ( n7648 , n7245 , n7246 );
and ( n7649 , n7247 , n7250 );
or ( n7650 , n7648 , n7649 );
xor ( n7651 , n7647 , n7650 );
nor ( n7652 , n5453 , n1128 );
xor ( n7653 , n7651 , n7652 );
and ( n7654 , n7251 , n7252 );
and ( n7655 , n7253 , n7256 );
or ( n7656 , n7654 , n7655 );
xor ( n7657 , n7653 , n7656 );
nor ( n7658 , n5851 , n1320 );
xor ( n7659 , n7657 , n7658 );
and ( n7660 , n7257 , n7258 );
and ( n7661 , n7259 , n7262 );
or ( n7662 , n7660 , n7661 );
xor ( n7663 , n7659 , n7662 );
nor ( n7664 , n6249 , n1536 );
xor ( n7665 , n7663 , n7664 );
and ( n7666 , n7263 , n7264 );
and ( n7667 , n7265 , n7268 );
or ( n7668 , n7666 , n7667 );
xor ( n7669 , n7665 , n7668 );
nor ( n7670 , n6642 , n1773 );
xor ( n7671 , n7669 , n7670 );
and ( n7672 , n7269 , n7270 );
and ( n7673 , n7271 , n7274 );
or ( n7674 , n7672 , n7673 );
xor ( n7675 , n7671 , n7674 );
nor ( n7676 , n7037 , n2027 );
xor ( n7677 , n7675 , n7676 );
and ( n7678 , n7275 , n7276 );
and ( n7679 , n7277 , n7280 );
or ( n7680 , n7678 , n7679 );
xor ( n7681 , n7677 , n7680 );
nor ( n7682 , n7431 , n2302 );
xor ( n7683 , n7681 , n7682 );
and ( n7684 , n7281 , n7282 );
and ( n7685 , n7283 , n7286 );
or ( n7686 , n7684 , n7685 );
xor ( n7687 , n7683 , n7686 );
and ( n7688 , n7304 , n7308 );
and ( n7689 , n7308 , n7312 );
and ( n7690 , n7304 , n7312 );
or ( n7691 , n7688 , n7689 , n7690 );
and ( n7692 , n7300 , n7313 );
and ( n7693 , n7313 , n7417 );
and ( n7694 , n7300 , n7417 );
or ( n7695 , n7692 , n7693 , n7694 );
xor ( n7696 , n7691 , n7695 );
and ( n7697 , n7318 , n7344 );
and ( n7698 , n7344 , n7416 );
and ( n7699 , n7318 , n7416 );
or ( n7700 , n7697 , n7698 , n7699 );
and ( n7701 , n7332 , n7333 );
and ( n7702 , n7333 , n7335 );
and ( n7703 , n7332 , n7335 );
or ( n7704 , n7701 , n7702 , n7703 );
and ( n7705 , n7322 , n7326 );
and ( n7706 , n7326 , n7343 );
and ( n7707 , n7322 , n7343 );
or ( n7708 , n7705 , n7706 , n7707 );
xor ( n7709 , n7704 , n7708 );
not ( n7710 , n2001 );
and ( n7711 , n2406 , n2001 );
nor ( n7712 , n7710 , n7711 );
xor ( n7713 , n7709 , n7712 );
xor ( n7714 , n7700 , n7713 );
and ( n7715 , n7349 , n7364 );
and ( n7716 , n7364 , n7415 );
and ( n7717 , n7349 , n7415 );
or ( n7718 , n7715 , n7716 , n7717 );
and ( n7719 , n7331 , n7336 );
and ( n7720 , n7336 , n7342 );
and ( n7721 , n7331 , n7342 );
or ( n7722 , n7719 , n7720 , n7721 );
and ( n7723 , n7353 , n7357 );
and ( n7724 , n7357 , n7363 );
and ( n7725 , n7353 , n7363 );
or ( n7726 , n7723 , n7724 , n7725 );
xor ( n7727 , n7722 , n7726 );
and ( n7728 , n7338 , n7339 );
and ( n7729 , n7339 , n7341 );
and ( n7730 , n7338 , n7341 );
or ( n7731 , n7728 , n7729 , n7730 );
and ( n7732 , n2286 , n2138 );
and ( n7733 , n2581 , n1864 );
xor ( n7734 , n7732 , n7733 );
and ( n7735 , n2972 , n1753 );
xor ( n7736 , n7734 , n7735 );
xor ( n7737 , n7731 , n7736 );
and ( n7738 , n3445 , n1396 );
and ( n7739 , n3844 , n1302 );
xor ( n7740 , n7738 , n7739 );
and ( n7741 , n4241 , n1114 );
xor ( n7742 , n7740 , n7741 );
xor ( n7743 , n7737 , n7742 );
xor ( n7744 , n7727 , n7743 );
xor ( n7745 , n7718 , n7744 );
and ( n7746 , n7369 , n7374 );
and ( n7747 , n7374 , n7414 );
and ( n7748 , n7369 , n7414 );
or ( n7749 , n7746 , n7747 , n7748 );
and ( n7750 , n7359 , n7360 );
and ( n7751 , n7360 , n7362 );
and ( n7752 , n7359 , n7362 );
or ( n7753 , n7750 , n7751 , n7752 );
and ( n7754 , n7370 , n7371 );
and ( n7755 , n7371 , n7373 );
and ( n7756 , n7370 , n7373 );
or ( n7757 , n7754 , n7755 , n7756 );
xor ( n7758 , n7753 , n7757 );
and ( n7759 , n4640 , n852 );
and ( n7760 , n5038 , n714 );
xor ( n7761 , n7759 , n7760 );
and ( n7762 , n5434 , n651 );
xor ( n7763 , n7761 , n7762 );
xor ( n7764 , n7758 , n7763 );
xor ( n7765 , n7749 , n7764 );
and ( n7766 , n7376 , n7377 );
and ( n7767 , n7377 , n7413 );
and ( n7768 , n7376 , n7413 );
or ( n7769 , n7766 , n7767 , n7768 );
and ( n7770 , n5832 , n488 );
and ( n7771 , n6230 , n411 );
xor ( n7772 , n7770 , n7771 );
and ( n7773 , n6623 , n375 );
xor ( n7774 , n7772 , n7773 );
xor ( n7775 , n7769 , n7774 );
and ( n7776 , n7018 , n312 );
and ( n7777 , n7412 , n288 );
xor ( n7778 , n7776 , n7777 );
and ( n7779 , n7388 , n7389 );
and ( n7780 , n7389 , n7393 );
and ( n7781 , n7388 , n7393 );
or ( n7782 , n7779 , n7780 , n7781 );
and ( n7783 , n7394 , n7399 );
xor ( n7784 , n7782 , n7783 );
not ( n7785 , n1935 );
and ( n7786 , n2563 , n1935 );
nor ( n7787 , n7785 , n7786 );
and ( n7788 , n7397 , n7398 );
and ( n7789 , n2206 , n2271 );
not ( n7790 , n2271 );
nor ( n7791 , n7789 , n7790 );
xor ( n7792 , n7788 , n7791 );
xor ( n7793 , n7787 , n7792 );
xor ( n7794 , n7784 , n7793 );
and ( n7795 , n7382 , n7383 );
and ( n7796 , n7383 , n7400 );
and ( n7797 , n7382 , n7400 );
or ( n7798 , n7795 , n7796 , n7797 );
xor ( n7799 , n7794 , n7798 );
and ( n7800 , n7401 , n7405 );
and ( n7801 , n7406 , n7409 );
or ( n7802 , n7800 , n7801 );
xor ( n7803 , n7799 , n7802 );
buf ( n7804 , n7803 );
buf ( n7805 , n7804 );
and ( n7806 , n7805 , n279 );
xor ( n7807 , n7778 , n7806 );
xor ( n7808 , n7775 , n7807 );
xor ( n7809 , n7765 , n7808 );
xor ( n7810 , n7745 , n7809 );
xor ( n7811 , n7714 , n7810 );
xor ( n7812 , n7696 , n7811 );
and ( n7813 , n7291 , n7295 );
and ( n7814 , n7295 , n7418 );
and ( n7815 , n7291 , n7418 );
or ( n7816 , n7813 , n7814 , n7815 );
xor ( n7817 , n7812 , n7816 );
and ( n7818 , n7419 , n7423 );
and ( n7819 , n7424 , n7427 );
or ( n7820 , n7818 , n7819 );
xor ( n7821 , n7817 , n7820 );
buf ( n7822 , n7821 );
buf ( n7823 , n7822 );
not ( n7824 , n7823 );
nor ( n7825 , n7824 , n2598 );
xor ( n7826 , n7687 , n7825 );
and ( n7827 , n7287 , n7432 );
and ( n7828 , n7433 , n7436 );
or ( n7829 , n7827 , n7828 );
xor ( n7830 , n7826 , n7829 );
buf ( n7831 , n7830 );
buf ( n7832 , n7831 );
not ( n7833 , n7832 );
buf ( n7834 , n270 );
not ( n7835 , n7834 );
nor ( n7836 , n7833 , n7835 );
xor ( n7837 , n7601 , n7836 );
xor ( n7838 , n7448 , n7598 );
nor ( n7839 , n7440 , n7835 );
and ( n7840 , n7838 , n7839 );
xor ( n7841 , n7838 , n7839 );
xor ( n7842 , n7452 , n7596 );
nor ( n7843 , n7046 , n7835 );
and ( n7844 , n7842 , n7843 );
xor ( n7845 , n7842 , n7843 );
xor ( n7846 , n7456 , n7594 );
nor ( n7847 , n6651 , n7835 );
and ( n7848 , n7846 , n7847 );
xor ( n7849 , n7846 , n7847 );
xor ( n7850 , n7460 , n7592 );
nor ( n7851 , n6258 , n7835 );
and ( n7852 , n7850 , n7851 );
xor ( n7853 , n7850 , n7851 );
xor ( n7854 , n7464 , n7590 );
nor ( n7855 , n5860 , n7835 );
and ( n7856 , n7854 , n7855 );
xor ( n7857 , n7854 , n7855 );
xor ( n7858 , n7468 , n7588 );
nor ( n7859 , n5462 , n7835 );
and ( n7860 , n7858 , n7859 );
xor ( n7861 , n7858 , n7859 );
xor ( n7862 , n7472 , n7586 );
nor ( n7863 , n5066 , n7835 );
and ( n7864 , n7862 , n7863 );
xor ( n7865 , n7862 , n7863 );
xor ( n7866 , n7476 , n7584 );
nor ( n7867 , n4668 , n7835 );
and ( n7868 , n7866 , n7867 );
xor ( n7869 , n7866 , n7867 );
xor ( n7870 , n7480 , n7582 );
nor ( n7871 , n4269 , n7835 );
and ( n7872 , n7870 , n7871 );
xor ( n7873 , n7870 , n7871 );
xor ( n7874 , n7484 , n7580 );
nor ( n7875 , n3872 , n7835 );
and ( n7876 , n7874 , n7875 );
xor ( n7877 , n7874 , n7875 );
xor ( n7878 , n7488 , n7578 );
nor ( n7879 , n3473 , n7835 );
and ( n7880 , n7878 , n7879 );
xor ( n7881 , n7878 , n7879 );
xor ( n7882 , n7492 , n7576 );
nor ( n7883 , n3000 , n7835 );
and ( n7884 , n7882 , n7883 );
xor ( n7885 , n7882 , n7883 );
xor ( n7886 , n7496 , n7574 );
nor ( n7887 , n2688 , n7835 );
and ( n7888 , n7886 , n7887 );
xor ( n7889 , n7886 , n7887 );
xor ( n7890 , n7500 , n7572 );
nor ( n7891 , n3008 , n7835 );
and ( n7892 , n7890 , n7891 );
xor ( n7893 , n7890 , n7891 );
xor ( n7894 , n7504 , n7570 );
nor ( n7895 , n3017 , n7835 );
and ( n7896 , n7894 , n7895 );
xor ( n7897 , n7894 , n7895 );
xor ( n7898 , n7508 , n7568 );
nor ( n7899 , n3026 , n7835 );
and ( n7900 , n7898 , n7899 );
xor ( n7901 , n7898 , n7899 );
xor ( n7902 , n7512 , n7566 );
nor ( n7903 , n3035 , n7835 );
and ( n7904 , n7902 , n7903 );
xor ( n7905 , n7902 , n7903 );
xor ( n7906 , n7516 , n7564 );
nor ( n7907 , n3044 , n7835 );
and ( n7908 , n7906 , n7907 );
xor ( n7909 , n7906 , n7907 );
xor ( n7910 , n7520 , n7562 );
nor ( n7911 , n3053 , n7835 );
and ( n7912 , n7910 , n7911 );
xor ( n7913 , n7910 , n7911 );
xor ( n7914 , n7524 , n7560 );
nor ( n7915 , n3062 , n7835 );
and ( n7916 , n7914 , n7915 );
xor ( n7917 , n7914 , n7915 );
xor ( n7918 , n7528 , n7558 );
nor ( n7919 , n3071 , n7835 );
and ( n7920 , n7918 , n7919 );
xor ( n7921 , n7918 , n7919 );
xor ( n7922 , n7532 , n7556 );
nor ( n7923 , n3080 , n7835 );
and ( n7924 , n7922 , n7923 );
xor ( n7925 , n7922 , n7923 );
xor ( n7926 , n7536 , n7554 );
nor ( n7927 , n3089 , n7835 );
and ( n7928 , n7926 , n7927 );
xor ( n7929 , n7926 , n7927 );
xor ( n7930 , n7540 , n7552 );
nor ( n7931 , n3098 , n7835 );
and ( n7932 , n7930 , n7931 );
xor ( n7933 , n7930 , n7931 );
xor ( n7934 , n7545 , n7550 );
nor ( n7935 , n3107 , n7835 );
and ( n7936 , n7934 , n7935 );
xor ( n7937 , n7934 , n7935 );
xor ( n7938 , n7547 , n7548 );
buf ( n7939 , n7938 );
nor ( n7940 , n3116 , n7835 );
and ( n7941 , n7939 , n7940 );
xor ( n7942 , n7939 , n7940 );
nor ( n7943 , n3134 , n7442 );
buf ( n7944 , n7943 );
nor ( n7945 , n3125 , n7835 );
and ( n7946 , n7944 , n7945 );
buf ( n7947 , n7946 );
and ( n7948 , n7942 , n7947 );
or ( n7949 , n7941 , n7948 );
and ( n7950 , n7937 , n7949 );
or ( n7951 , n7936 , n7950 );
and ( n7952 , n7933 , n7951 );
or ( n7953 , n7932 , n7952 );
and ( n7954 , n7929 , n7953 );
or ( n7955 , n7928 , n7954 );
and ( n7956 , n7925 , n7955 );
or ( n7957 , n7924 , n7956 );
and ( n7958 , n7921 , n7957 );
or ( n7959 , n7920 , n7958 );
and ( n7960 , n7917 , n7959 );
or ( n7961 , n7916 , n7960 );
and ( n7962 , n7913 , n7961 );
or ( n7963 , n7912 , n7962 );
and ( n7964 , n7909 , n7963 );
or ( n7965 , n7908 , n7964 );
and ( n7966 , n7905 , n7965 );
or ( n7967 , n7904 , n7966 );
and ( n7968 , n7901 , n7967 );
or ( n7969 , n7900 , n7968 );
and ( n7970 , n7897 , n7969 );
or ( n7971 , n7896 , n7970 );
and ( n7972 , n7893 , n7971 );
or ( n7973 , n7892 , n7972 );
and ( n7974 , n7889 , n7973 );
or ( n7975 , n7888 , n7974 );
and ( n7976 , n7885 , n7975 );
or ( n7977 , n7884 , n7976 );
and ( n7978 , n7881 , n7977 );
or ( n7979 , n7880 , n7978 );
and ( n7980 , n7877 , n7979 );
or ( n7981 , n7876 , n7980 );
and ( n7982 , n7873 , n7981 );
or ( n7983 , n7872 , n7982 );
and ( n7984 , n7869 , n7983 );
or ( n7985 , n7868 , n7984 );
and ( n7986 , n7865 , n7985 );
or ( n7987 , n7864 , n7986 );
and ( n7988 , n7861 , n7987 );
or ( n7989 , n7860 , n7988 );
and ( n7990 , n7857 , n7989 );
or ( n7991 , n7856 , n7990 );
and ( n7992 , n7853 , n7991 );
or ( n7993 , n7852 , n7992 );
and ( n7994 , n7849 , n7993 );
or ( n7995 , n7848 , n7994 );
and ( n7996 , n7845 , n7995 );
or ( n7997 , n7844 , n7996 );
and ( n7998 , n7841 , n7997 );
or ( n7999 , n7840 , n7998 );
xor ( n8000 , n7837 , n7999 );
and ( n8001 , n285 , n2299 );
nor ( n8002 , n2300 , n8001 );
nor ( n8003 , n2596 , n305 );
xor ( n8004 , n8002 , n8003 );
and ( n8005 , n7603 , n7604 );
and ( n8006 , n7605 , n7608 );
or ( n8007 , n8005 , n8006 );
xor ( n8008 , n8004 , n8007 );
nor ( n8009 , n2991 , n336 );
xor ( n8010 , n8008 , n8009 );
and ( n8011 , n7609 , n7610 );
and ( n8012 , n7611 , n7614 );
or ( n8013 , n8011 , n8012 );
xor ( n8014 , n8010 , n8013 );
nor ( n8015 , n3464 , n386 );
xor ( n8016 , n8014 , n8015 );
and ( n8017 , n7615 , n7616 );
and ( n8018 , n7617 , n7620 );
or ( n8019 , n8017 , n8018 );
xor ( n8020 , n8016 , n8019 );
nor ( n8021 , n3863 , n458 );
xor ( n8022 , n8020 , n8021 );
and ( n8023 , n7621 , n7622 );
and ( n8024 , n7623 , n7626 );
or ( n8025 , n8023 , n8024 );
xor ( n8026 , n8022 , n8025 );
nor ( n8027 , n4260 , n551 );
xor ( n8028 , n8026 , n8027 );
and ( n8029 , n7627 , n7628 );
and ( n8030 , n7629 , n7632 );
or ( n8031 , n8029 , n8030 );
xor ( n8032 , n8028 , n8031 );
nor ( n8033 , n4659 , n665 );
xor ( n8034 , n8032 , n8033 );
and ( n8035 , n7633 , n7634 );
and ( n8036 , n7635 , n7638 );
or ( n8037 , n8035 , n8036 );
xor ( n8038 , n8034 , n8037 );
nor ( n8039 , n5057 , n797 );
xor ( n8040 , n8038 , n8039 );
and ( n8041 , n7639 , n7640 );
and ( n8042 , n7641 , n7644 );
or ( n8043 , n8041 , n8042 );
xor ( n8044 , n8040 , n8043 );
nor ( n8045 , n5453 , n954 );
xor ( n8046 , n8044 , n8045 );
and ( n8047 , n7645 , n7646 );
and ( n8048 , n7647 , n7650 );
or ( n8049 , n8047 , n8048 );
xor ( n8050 , n8046 , n8049 );
nor ( n8051 , n5851 , n1128 );
xor ( n8052 , n8050 , n8051 );
and ( n8053 , n7651 , n7652 );
and ( n8054 , n7653 , n7656 );
or ( n8055 , n8053 , n8054 );
xor ( n8056 , n8052 , n8055 );
nor ( n8057 , n6249 , n1320 );
xor ( n8058 , n8056 , n8057 );
and ( n8059 , n7657 , n7658 );
and ( n8060 , n7659 , n7662 );
or ( n8061 , n8059 , n8060 );
xor ( n8062 , n8058 , n8061 );
nor ( n8063 , n6642 , n1536 );
xor ( n8064 , n8062 , n8063 );
and ( n8065 , n7663 , n7664 );
and ( n8066 , n7665 , n7668 );
or ( n8067 , n8065 , n8066 );
xor ( n8068 , n8064 , n8067 );
nor ( n8069 , n7037 , n1773 );
xor ( n8070 , n8068 , n8069 );
and ( n8071 , n7669 , n7670 );
and ( n8072 , n7671 , n7674 );
or ( n8073 , n8071 , n8072 );
xor ( n8074 , n8070 , n8073 );
nor ( n8075 , n7431 , n2027 );
xor ( n8076 , n8074 , n8075 );
and ( n8077 , n7675 , n7676 );
and ( n8078 , n7677 , n7680 );
or ( n8079 , n8077 , n8078 );
xor ( n8080 , n8076 , n8079 );
nor ( n8081 , n7824 , n2302 );
xor ( n8082 , n8080 , n8081 );
and ( n8083 , n7681 , n7682 );
and ( n8084 , n7683 , n7686 );
or ( n8085 , n8083 , n8084 );
xor ( n8086 , n8082 , n8085 );
and ( n8087 , n7704 , n7708 );
and ( n8088 , n7708 , n7712 );
and ( n8089 , n7704 , n7712 );
or ( n8090 , n8087 , n8088 , n8089 );
and ( n8091 , n7700 , n7713 );
and ( n8092 , n7713 , n7810 );
and ( n8093 , n7700 , n7810 );
or ( n8094 , n8091 , n8092 , n8093 );
xor ( n8095 , n8090 , n8094 );
and ( n8096 , n7718 , n7744 );
and ( n8097 , n7744 , n7809 );
and ( n8098 , n7718 , n7809 );
or ( n8099 , n8096 , n8097 , n8098 );
and ( n8100 , n7732 , n7733 );
and ( n8101 , n7733 , n7735 );
and ( n8102 , n7732 , n7735 );
or ( n8103 , n8100 , n8101 , n8102 );
and ( n8104 , n7722 , n7726 );
and ( n8105 , n7726 , n7743 );
and ( n8106 , n7722 , n7743 );
or ( n8107 , n8104 , n8105 , n8106 );
xor ( n8108 , n8103 , n8107 );
not ( n8109 , n2286 );
and ( n8110 , n2406 , n2286 );
nor ( n8111 , n8109 , n8110 );
xor ( n8112 , n8108 , n8111 );
xor ( n8113 , n8099 , n8112 );
and ( n8114 , n7749 , n7764 );
and ( n8115 , n7764 , n7808 );
and ( n8116 , n7749 , n7808 );
or ( n8117 , n8114 , n8115 , n8116 );
and ( n8118 , n7731 , n7736 );
and ( n8119 , n7736 , n7742 );
and ( n8120 , n7731 , n7742 );
or ( n8121 , n8118 , n8119 , n8120 );
and ( n8122 , n7753 , n7757 );
and ( n8123 , n7757 , n7763 );
and ( n8124 , n7753 , n7763 );
or ( n8125 , n8122 , n8123 , n8124 );
xor ( n8126 , n8121 , n8125 );
and ( n8127 , n7738 , n7739 );
and ( n8128 , n7739 , n7741 );
and ( n8129 , n7738 , n7741 );
or ( n8130 , n8127 , n8128 , n8129 );
and ( n8131 , n2581 , n2138 );
and ( n8132 , n2972 , n1864 );
xor ( n8133 , n8131 , n8132 );
and ( n8134 , n3445 , n1753 );
xor ( n8135 , n8133 , n8134 );
xor ( n8136 , n8130 , n8135 );
and ( n8137 , n3844 , n1396 );
and ( n8138 , n4241 , n1302 );
xor ( n8139 , n8137 , n8138 );
and ( n8140 , n4640 , n1114 );
xor ( n8141 , n8139 , n8140 );
xor ( n8142 , n8136 , n8141 );
xor ( n8143 , n8126 , n8142 );
xor ( n8144 , n8117 , n8143 );
and ( n8145 , n7769 , n7774 );
and ( n8146 , n7774 , n7807 );
and ( n8147 , n7769 , n7807 );
or ( n8148 , n8145 , n8146 , n8147 );
and ( n8149 , n7759 , n7760 );
and ( n8150 , n7760 , n7762 );
and ( n8151 , n7759 , n7762 );
or ( n8152 , n8149 , n8150 , n8151 );
and ( n8153 , n7770 , n7771 );
and ( n8154 , n7771 , n7773 );
and ( n8155 , n7770 , n7773 );
or ( n8156 , n8153 , n8154 , n8155 );
xor ( n8157 , n8152 , n8156 );
and ( n8158 , n5038 , n852 );
and ( n8159 , n5434 , n714 );
xor ( n8160 , n8158 , n8159 );
and ( n8161 , n5832 , n651 );
xor ( n8162 , n8160 , n8161 );
xor ( n8163 , n8157 , n8162 );
xor ( n8164 , n8148 , n8163 );
and ( n8165 , n7776 , n7777 );
and ( n8166 , n7777 , n7806 );
and ( n8167 , n7776 , n7806 );
or ( n8168 , n8165 , n8166 , n8167 );
and ( n8169 , n6230 , n488 );
and ( n8170 , n6623 , n411 );
xor ( n8171 , n8169 , n8170 );
and ( n8172 , n7018 , n375 );
xor ( n8173 , n8171 , n8172 );
xor ( n8174 , n8168 , n8173 );
and ( n8175 , n7412 , n312 );
and ( n8176 , n7805 , n288 );
xor ( n8177 , n8175 , n8176 );
and ( n8178 , n7788 , n7791 );
and ( n8179 , n7787 , n7792 );
xor ( n8180 , n8178 , n8179 );
and ( n8181 , n2205 , n2562 );
xor ( n8182 , n8180 , n8181 );
and ( n8183 , n7782 , n7783 );
and ( n8184 , n7783 , n7793 );
and ( n8185 , n7782 , n7793 );
or ( n8186 , n8183 , n8184 , n8185 );
xor ( n8187 , n8182 , n8186 );
and ( n8188 , n7794 , n7798 );
and ( n8189 , n7799 , n7802 );
or ( n8190 , n8188 , n8189 );
xor ( n8191 , n8187 , n8190 );
buf ( n8192 , n8191 );
buf ( n8193 , n8192 );
and ( n8194 , n8193 , n279 );
xor ( n8195 , n8177 , n8194 );
xor ( n8196 , n8174 , n8195 );
xor ( n8197 , n8164 , n8196 );
xor ( n8198 , n8144 , n8197 );
xor ( n8199 , n8113 , n8198 );
xor ( n8200 , n8095 , n8199 );
and ( n8201 , n7691 , n7695 );
and ( n8202 , n7695 , n7811 );
and ( n8203 , n7691 , n7811 );
or ( n8204 , n8201 , n8202 , n8203 );
xor ( n8205 , n8200 , n8204 );
and ( n8206 , n7812 , n7816 );
and ( n8207 , n7817 , n7820 );
or ( n8208 , n8206 , n8207 );
xor ( n8209 , n8205 , n8208 );
buf ( n8210 , n8209 );
buf ( n8211 , n8210 );
not ( n8212 , n8211 );
nor ( n8213 , n8212 , n2598 );
xor ( n8214 , n8086 , n8213 );
and ( n8215 , n7687 , n7825 );
and ( n8216 , n7826 , n7829 );
or ( n8217 , n8215 , n8216 );
xor ( n8218 , n8214 , n8217 );
buf ( n8219 , n8218 );
buf ( n8220 , n8219 );
not ( n8221 , n8220 );
buf ( n8222 , n271 );
not ( n8223 , n8222 );
nor ( n8224 , n8221 , n8223 );
xor ( n8225 , n8000 , n8224 );
xor ( n8226 , n7841 , n7997 );
nor ( n8227 , n7833 , n8223 );
and ( n8228 , n8226 , n8227 );
xor ( n8229 , n8226 , n8227 );
xor ( n8230 , n7845 , n7995 );
nor ( n8231 , n7440 , n8223 );
and ( n8232 , n8230 , n8231 );
xor ( n8233 , n8230 , n8231 );
xor ( n8234 , n7849 , n7993 );
nor ( n8235 , n7046 , n8223 );
and ( n8236 , n8234 , n8235 );
xor ( n8237 , n8234 , n8235 );
xor ( n8238 , n7853 , n7991 );
nor ( n8239 , n6651 , n8223 );
and ( n8240 , n8238 , n8239 );
xor ( n8241 , n8238 , n8239 );
xor ( n8242 , n7857 , n7989 );
nor ( n8243 , n6258 , n8223 );
and ( n8244 , n8242 , n8243 );
xor ( n8245 , n8242 , n8243 );
xor ( n8246 , n7861 , n7987 );
nor ( n8247 , n5860 , n8223 );
and ( n8248 , n8246 , n8247 );
xor ( n8249 , n8246 , n8247 );
xor ( n8250 , n7865 , n7985 );
nor ( n8251 , n5462 , n8223 );
and ( n8252 , n8250 , n8251 );
xor ( n8253 , n8250 , n8251 );
xor ( n8254 , n7869 , n7983 );
nor ( n8255 , n5066 , n8223 );
and ( n8256 , n8254 , n8255 );
xor ( n8257 , n8254 , n8255 );
xor ( n8258 , n7873 , n7981 );
nor ( n8259 , n4668 , n8223 );
and ( n8260 , n8258 , n8259 );
xor ( n8261 , n8258 , n8259 );
xor ( n8262 , n7877 , n7979 );
nor ( n8263 , n4269 , n8223 );
and ( n8264 , n8262 , n8263 );
xor ( n8265 , n8262 , n8263 );
xor ( n8266 , n7881 , n7977 );
nor ( n8267 , n3872 , n8223 );
and ( n8268 , n8266 , n8267 );
xor ( n8269 , n8266 , n8267 );
xor ( n8270 , n7885 , n7975 );
nor ( n8271 , n3473 , n8223 );
and ( n8272 , n8270 , n8271 );
xor ( n8273 , n8270 , n8271 );
xor ( n8274 , n7889 , n7973 );
nor ( n8275 , n3000 , n8223 );
and ( n8276 , n8274 , n8275 );
xor ( n8277 , n8274 , n8275 );
xor ( n8278 , n7893 , n7971 );
nor ( n8279 , n2688 , n8223 );
and ( n8280 , n8278 , n8279 );
xor ( n8281 , n8278 , n8279 );
xor ( n8282 , n7897 , n7969 );
nor ( n8283 , n3008 , n8223 );
and ( n8284 , n8282 , n8283 );
xor ( n8285 , n8282 , n8283 );
xor ( n8286 , n7901 , n7967 );
nor ( n8287 , n3017 , n8223 );
and ( n8288 , n8286 , n8287 );
xor ( n8289 , n8286 , n8287 );
xor ( n8290 , n7905 , n7965 );
nor ( n8291 , n3026 , n8223 );
and ( n8292 , n8290 , n8291 );
xor ( n8293 , n8290 , n8291 );
xor ( n8294 , n7909 , n7963 );
nor ( n8295 , n3035 , n8223 );
and ( n8296 , n8294 , n8295 );
xor ( n8297 , n8294 , n8295 );
xor ( n8298 , n7913 , n7961 );
nor ( n8299 , n3044 , n8223 );
and ( n8300 , n8298 , n8299 );
xor ( n8301 , n8298 , n8299 );
xor ( n8302 , n7917 , n7959 );
nor ( n8303 , n3053 , n8223 );
and ( n8304 , n8302 , n8303 );
xor ( n8305 , n8302 , n8303 );
xor ( n8306 , n7921 , n7957 );
nor ( n8307 , n3062 , n8223 );
and ( n8308 , n8306 , n8307 );
xor ( n8309 , n8306 , n8307 );
xor ( n8310 , n7925 , n7955 );
nor ( n8311 , n3071 , n8223 );
and ( n8312 , n8310 , n8311 );
xor ( n8313 , n8310 , n8311 );
xor ( n8314 , n7929 , n7953 );
nor ( n8315 , n3080 , n8223 );
and ( n8316 , n8314 , n8315 );
xor ( n8317 , n8314 , n8315 );
xor ( n8318 , n7933 , n7951 );
nor ( n8319 , n3089 , n8223 );
and ( n8320 , n8318 , n8319 );
xor ( n8321 , n8318 , n8319 );
xor ( n8322 , n7937 , n7949 );
nor ( n8323 , n3098 , n8223 );
and ( n8324 , n8322 , n8323 );
xor ( n8325 , n8322 , n8323 );
xor ( n8326 , n7942 , n7947 );
nor ( n8327 , n3107 , n8223 );
and ( n8328 , n8326 , n8327 );
xor ( n8329 , n8326 , n8327 );
xor ( n8330 , n7944 , n7945 );
buf ( n8331 , n8330 );
nor ( n8332 , n3116 , n8223 );
and ( n8333 , n8331 , n8332 );
xor ( n8334 , n8331 , n8332 );
nor ( n8335 , n3134 , n7835 );
buf ( n8336 , n8335 );
nor ( n8337 , n3125 , n8223 );
and ( n8338 , n8336 , n8337 );
buf ( n8339 , n8338 );
and ( n8340 , n8334 , n8339 );
or ( n8341 , n8333 , n8340 );
and ( n8342 , n8329 , n8341 );
or ( n8343 , n8328 , n8342 );
and ( n8344 , n8325 , n8343 );
or ( n8345 , n8324 , n8344 );
and ( n8346 , n8321 , n8345 );
or ( n8347 , n8320 , n8346 );
and ( n8348 , n8317 , n8347 );
or ( n8349 , n8316 , n8348 );
and ( n8350 , n8313 , n8349 );
or ( n8351 , n8312 , n8350 );
and ( n8352 , n8309 , n8351 );
or ( n8353 , n8308 , n8352 );
and ( n8354 , n8305 , n8353 );
or ( n8355 , n8304 , n8354 );
and ( n8356 , n8301 , n8355 );
or ( n8357 , n8300 , n8356 );
and ( n8358 , n8297 , n8357 );
or ( n8359 , n8296 , n8358 );
and ( n8360 , n8293 , n8359 );
or ( n8361 , n8292 , n8360 );
and ( n8362 , n8289 , n8361 );
or ( n8363 , n8288 , n8362 );
and ( n8364 , n8285 , n8363 );
or ( n8365 , n8284 , n8364 );
and ( n8366 , n8281 , n8365 );
or ( n8367 , n8280 , n8366 );
and ( n8368 , n8277 , n8367 );
or ( n8369 , n8276 , n8368 );
and ( n8370 , n8273 , n8369 );
or ( n8371 , n8272 , n8370 );
and ( n8372 , n8269 , n8371 );
or ( n8373 , n8268 , n8372 );
and ( n8374 , n8265 , n8373 );
or ( n8375 , n8264 , n8374 );
and ( n8376 , n8261 , n8375 );
or ( n8377 , n8260 , n8376 );
and ( n8378 , n8257 , n8377 );
or ( n8379 , n8256 , n8378 );
and ( n8380 , n8253 , n8379 );
or ( n8381 , n8252 , n8380 );
and ( n8382 , n8249 , n8381 );
or ( n8383 , n8248 , n8382 );
and ( n8384 , n8245 , n8383 );
or ( n8385 , n8244 , n8384 );
and ( n8386 , n8241 , n8385 );
or ( n8387 , n8240 , n8386 );
and ( n8388 , n8237 , n8387 );
or ( n8389 , n8236 , n8388 );
and ( n8390 , n8233 , n8389 );
or ( n8391 , n8232 , n8390 );
and ( n8392 , n8229 , n8391 );
or ( n8393 , n8228 , n8392 );
xor ( n8394 , n8225 , n8393 );
and ( n8395 , n285 , n2595 );
nor ( n8396 , n2596 , n8395 );
nor ( n8397 , n2991 , n305 );
xor ( n8398 , n8396 , n8397 );
and ( n8399 , n8002 , n8003 );
and ( n8400 , n8004 , n8007 );
or ( n8401 , n8399 , n8400 );
xor ( n8402 , n8398 , n8401 );
nor ( n8403 , n3464 , n336 );
xor ( n8404 , n8402 , n8403 );
and ( n8405 , n8008 , n8009 );
and ( n8406 , n8010 , n8013 );
or ( n8407 , n8405 , n8406 );
xor ( n8408 , n8404 , n8407 );
nor ( n8409 , n3863 , n386 );
xor ( n8410 , n8408 , n8409 );
and ( n8411 , n8014 , n8015 );
and ( n8412 , n8016 , n8019 );
or ( n8413 , n8411 , n8412 );
xor ( n8414 , n8410 , n8413 );
nor ( n8415 , n4260 , n458 );
xor ( n8416 , n8414 , n8415 );
and ( n8417 , n8020 , n8021 );
and ( n8418 , n8022 , n8025 );
or ( n8419 , n8417 , n8418 );
xor ( n8420 , n8416 , n8419 );
nor ( n8421 , n4659 , n551 );
xor ( n8422 , n8420 , n8421 );
and ( n8423 , n8026 , n8027 );
and ( n8424 , n8028 , n8031 );
or ( n8425 , n8423 , n8424 );
xor ( n8426 , n8422 , n8425 );
nor ( n8427 , n5057 , n665 );
xor ( n8428 , n8426 , n8427 );
and ( n8429 , n8032 , n8033 );
and ( n8430 , n8034 , n8037 );
or ( n8431 , n8429 , n8430 );
xor ( n8432 , n8428 , n8431 );
nor ( n8433 , n5453 , n797 );
xor ( n8434 , n8432 , n8433 );
and ( n8435 , n8038 , n8039 );
and ( n8436 , n8040 , n8043 );
or ( n8437 , n8435 , n8436 );
xor ( n8438 , n8434 , n8437 );
nor ( n8439 , n5851 , n954 );
xor ( n8440 , n8438 , n8439 );
and ( n8441 , n8044 , n8045 );
and ( n8442 , n8046 , n8049 );
or ( n8443 , n8441 , n8442 );
xor ( n8444 , n8440 , n8443 );
nor ( n8445 , n6249 , n1128 );
xor ( n8446 , n8444 , n8445 );
and ( n8447 , n8050 , n8051 );
and ( n8448 , n8052 , n8055 );
or ( n8449 , n8447 , n8448 );
xor ( n8450 , n8446 , n8449 );
nor ( n8451 , n6642 , n1320 );
xor ( n8452 , n8450 , n8451 );
and ( n8453 , n8056 , n8057 );
and ( n8454 , n8058 , n8061 );
or ( n8455 , n8453 , n8454 );
xor ( n8456 , n8452 , n8455 );
nor ( n8457 , n7037 , n1536 );
xor ( n8458 , n8456 , n8457 );
and ( n8459 , n8062 , n8063 );
and ( n8460 , n8064 , n8067 );
or ( n8461 , n8459 , n8460 );
xor ( n8462 , n8458 , n8461 );
nor ( n8463 , n7431 , n1773 );
xor ( n8464 , n8462 , n8463 );
and ( n8465 , n8068 , n8069 );
and ( n8466 , n8070 , n8073 );
or ( n8467 , n8465 , n8466 );
xor ( n8468 , n8464 , n8467 );
nor ( n8469 , n7824 , n2027 );
xor ( n8470 , n8468 , n8469 );
and ( n8471 , n8074 , n8075 );
and ( n8472 , n8076 , n8079 );
or ( n8473 , n8471 , n8472 );
xor ( n8474 , n8470 , n8473 );
nor ( n8475 , n8212 , n2302 );
xor ( n8476 , n8474 , n8475 );
and ( n8477 , n8080 , n8081 );
and ( n8478 , n8082 , n8085 );
or ( n8479 , n8477 , n8478 );
xor ( n8480 , n8476 , n8479 );
and ( n8481 , n8103 , n8107 );
and ( n8482 , n8107 , n8111 );
and ( n8483 , n8103 , n8111 );
or ( n8484 , n8481 , n8482 , n8483 );
and ( n8485 , n8099 , n8112 );
and ( n8486 , n8112 , n8198 );
and ( n8487 , n8099 , n8198 );
or ( n8488 , n8485 , n8486 , n8487 );
xor ( n8489 , n8484 , n8488 );
and ( n8490 , n8117 , n8143 );
and ( n8491 , n8143 , n8197 );
and ( n8492 , n8117 , n8197 );
or ( n8493 , n8490 , n8491 , n8492 );
and ( n8494 , n8131 , n8132 );
and ( n8495 , n8132 , n8134 );
and ( n8496 , n8131 , n8134 );
or ( n8497 , n8494 , n8495 , n8496 );
and ( n8498 , n8121 , n8125 );
and ( n8499 , n8125 , n8142 );
and ( n8500 , n8121 , n8142 );
or ( n8501 , n8498 , n8499 , n8500 );
xor ( n8502 , n8497 , n8501 );
not ( n8503 , n2581 );
and ( n8504 , n2406 , n2581 );
nor ( n8505 , n8503 , n8504 );
xor ( n8506 , n8502 , n8505 );
xor ( n8507 , n8493 , n8506 );
and ( n8508 , n8148 , n8163 );
and ( n8509 , n8163 , n8196 );
and ( n8510 , n8148 , n8196 );
or ( n8511 , n8508 , n8509 , n8510 );
and ( n8512 , n8130 , n8135 );
and ( n8513 , n8135 , n8141 );
and ( n8514 , n8130 , n8141 );
or ( n8515 , n8512 , n8513 , n8514 );
and ( n8516 , n8152 , n8156 );
and ( n8517 , n8156 , n8162 );
and ( n8518 , n8152 , n8162 );
or ( n8519 , n8516 , n8517 , n8518 );
xor ( n8520 , n8515 , n8519 );
and ( n8521 , n8137 , n8138 );
and ( n8522 , n8138 , n8140 );
and ( n8523 , n8137 , n8140 );
or ( n8524 , n8521 , n8522 , n8523 );
and ( n8525 , n2972 , n2138 );
and ( n8526 , n3445 , n1864 );
xor ( n8527 , n8525 , n8526 );
and ( n8528 , n3844 , n1753 );
xor ( n8529 , n8527 , n8528 );
xor ( n8530 , n8524 , n8529 );
and ( n8531 , n4241 , n1396 );
and ( n8532 , n4640 , n1302 );
xor ( n8533 , n8531 , n8532 );
and ( n8534 , n5038 , n1114 );
xor ( n8535 , n8533 , n8534 );
xor ( n8536 , n8530 , n8535 );
xor ( n8537 , n8520 , n8536 );
xor ( n8538 , n8511 , n8537 );
and ( n8539 , n8168 , n8173 );
and ( n8540 , n8173 , n8195 );
and ( n8541 , n8168 , n8195 );
or ( n8542 , n8539 , n8540 , n8541 );
and ( n8543 , n8158 , n8159 );
and ( n8544 , n8159 , n8161 );
and ( n8545 , n8158 , n8161 );
or ( n8546 , n8543 , n8544 , n8545 );
and ( n8547 , n8169 , n8170 );
and ( n8548 , n8170 , n8172 );
and ( n8549 , n8169 , n8172 );
or ( n8550 , n8547 , n8548 , n8549 );
xor ( n8551 , n8546 , n8550 );
and ( n8552 , n5434 , n852 );
and ( n8553 , n5832 , n714 );
xor ( n8554 , n8552 , n8553 );
and ( n8555 , n6230 , n651 );
xor ( n8556 , n8554 , n8555 );
xor ( n8557 , n8551 , n8556 );
xor ( n8558 , n8542 , n8557 );
and ( n8559 , n8175 , n8176 );
and ( n8560 , n8176 , n8194 );
and ( n8561 , n8175 , n8194 );
or ( n8562 , n8559 , n8560 , n8561 );
and ( n8563 , n6623 , n488 );
and ( n8564 , n7018 , n411 );
xor ( n8565 , n8563 , n8564 );
and ( n8566 , n7412 , n375 );
xor ( n8567 , n8565 , n8566 );
xor ( n8568 , n8562 , n8567 );
and ( n8569 , n7805 , n312 );
and ( n8570 , n8193 , n288 );
xor ( n8571 , n8569 , n8570 );
and ( n8572 , n8179 , n8181 );
and ( n8573 , n8178 , n8181 );
or ( n8574 , 1'b0 , n8572 , n8573 );
and ( n8575 , n8182 , n8186 );
and ( n8576 , n8187 , n8190 );
or ( n8577 , n8575 , n8576 );
xor ( n8578 , n8574 , n8577 );
buf ( n8579 , n8578 );
buf ( n8580 , n8579 );
not ( n8581 , n8580 );
and ( n8582 , n8581 , n279 );
not ( n8583 , n279 );
nor ( n8584 , n8582 , n8583 );
xor ( n8585 , n8571 , n8584 );
xor ( n8586 , n8568 , n8585 );
xor ( n8587 , n8558 , n8586 );
xor ( n8588 , n8538 , n8587 );
xor ( n8589 , n8507 , n8588 );
xor ( n8590 , n8489 , n8589 );
and ( n8591 , n8090 , n8094 );
and ( n8592 , n8094 , n8199 );
and ( n8593 , n8090 , n8199 );
or ( n8594 , n8591 , n8592 , n8593 );
xor ( n8595 , n8590 , n8594 );
and ( n8596 , n8200 , n8204 );
and ( n8597 , n8205 , n8208 );
or ( n8598 , n8596 , n8597 );
xor ( n8599 , n8595 , n8598 );
buf ( n8600 , n8599 );
buf ( n8601 , n8600 );
not ( n8602 , n8601 );
nor ( n8603 , n8602 , n2598 );
xor ( n8604 , n8480 , n8603 );
and ( n8605 , n8086 , n8213 );
and ( n8606 , n8214 , n8217 );
or ( n8607 , n8605 , n8606 );
xor ( n8608 , n8604 , n8607 );
buf ( n8609 , n8608 );
buf ( n8610 , n8609 );
not ( n8611 , n8610 );
buf ( n8612 , n272 );
not ( n8613 , n8612 );
nor ( n8614 , n8611 , n8613 );
xor ( n8615 , n8394 , n8614 );
xor ( n8616 , n8229 , n8391 );
nor ( n8617 , n8221 , n8613 );
and ( n8618 , n8616 , n8617 );
xor ( n8619 , n8616 , n8617 );
xor ( n8620 , n8233 , n8389 );
nor ( n8621 , n7833 , n8613 );
and ( n8622 , n8620 , n8621 );
xor ( n8623 , n8620 , n8621 );
xor ( n8624 , n8237 , n8387 );
nor ( n8625 , n7440 , n8613 );
and ( n8626 , n8624 , n8625 );
xor ( n8627 , n8624 , n8625 );
xor ( n8628 , n8241 , n8385 );
nor ( n8629 , n7046 , n8613 );
and ( n8630 , n8628 , n8629 );
xor ( n8631 , n8628 , n8629 );
xor ( n8632 , n8245 , n8383 );
nor ( n8633 , n6651 , n8613 );
and ( n8634 , n8632 , n8633 );
xor ( n8635 , n8632 , n8633 );
xor ( n8636 , n8249 , n8381 );
nor ( n8637 , n6258 , n8613 );
and ( n8638 , n8636 , n8637 );
xor ( n8639 , n8636 , n8637 );
xor ( n8640 , n8253 , n8379 );
nor ( n8641 , n5860 , n8613 );
and ( n8642 , n8640 , n8641 );
xor ( n8643 , n8640 , n8641 );
xor ( n8644 , n8257 , n8377 );
nor ( n8645 , n5462 , n8613 );
and ( n8646 , n8644 , n8645 );
xor ( n8647 , n8644 , n8645 );
xor ( n8648 , n8261 , n8375 );
nor ( n8649 , n5066 , n8613 );
and ( n8650 , n8648 , n8649 );
xor ( n8651 , n8648 , n8649 );
xor ( n8652 , n8265 , n8373 );
nor ( n8653 , n4668 , n8613 );
and ( n8654 , n8652 , n8653 );
xor ( n8655 , n8652 , n8653 );
xor ( n8656 , n8269 , n8371 );
nor ( n8657 , n4269 , n8613 );
and ( n8658 , n8656 , n8657 );
xor ( n8659 , n8656 , n8657 );
xor ( n8660 , n8273 , n8369 );
nor ( n8661 , n3872 , n8613 );
and ( n8662 , n8660 , n8661 );
xor ( n8663 , n8660 , n8661 );
xor ( n8664 , n8277 , n8367 );
nor ( n8665 , n3473 , n8613 );
and ( n8666 , n8664 , n8665 );
xor ( n8667 , n8664 , n8665 );
xor ( n8668 , n8281 , n8365 );
nor ( n8669 , n3000 , n8613 );
and ( n8670 , n8668 , n8669 );
xor ( n8671 , n8668 , n8669 );
xor ( n8672 , n8285 , n8363 );
nor ( n8673 , n2688 , n8613 );
and ( n8674 , n8672 , n8673 );
xor ( n8675 , n8672 , n8673 );
xor ( n8676 , n8289 , n8361 );
nor ( n8677 , n3008 , n8613 );
and ( n8678 , n8676 , n8677 );
xor ( n8679 , n8676 , n8677 );
xor ( n8680 , n8293 , n8359 );
nor ( n8681 , n3017 , n8613 );
and ( n8682 , n8680 , n8681 );
xor ( n8683 , n8680 , n8681 );
xor ( n8684 , n8297 , n8357 );
nor ( n8685 , n3026 , n8613 );
and ( n8686 , n8684 , n8685 );
xor ( n8687 , n8684 , n8685 );
xor ( n8688 , n8301 , n8355 );
nor ( n8689 , n3035 , n8613 );
and ( n8690 , n8688 , n8689 );
xor ( n8691 , n8688 , n8689 );
xor ( n8692 , n8305 , n8353 );
nor ( n8693 , n3044 , n8613 );
and ( n8694 , n8692 , n8693 );
xor ( n8695 , n8692 , n8693 );
xor ( n8696 , n8309 , n8351 );
nor ( n8697 , n3053 , n8613 );
and ( n8698 , n8696 , n8697 );
xor ( n8699 , n8696 , n8697 );
xor ( n8700 , n8313 , n8349 );
nor ( n8701 , n3062 , n8613 );
and ( n8702 , n8700 , n8701 );
xor ( n8703 , n8700 , n8701 );
xor ( n8704 , n8317 , n8347 );
nor ( n8705 , n3071 , n8613 );
and ( n8706 , n8704 , n8705 );
xor ( n8707 , n8704 , n8705 );
xor ( n8708 , n8321 , n8345 );
nor ( n8709 , n3080 , n8613 );
and ( n8710 , n8708 , n8709 );
xor ( n8711 , n8708 , n8709 );
xor ( n8712 , n8325 , n8343 );
nor ( n8713 , n3089 , n8613 );
and ( n8714 , n8712 , n8713 );
xor ( n8715 , n8712 , n8713 );
xor ( n8716 , n8329 , n8341 );
nor ( n8717 , n3098 , n8613 );
and ( n8718 , n8716 , n8717 );
xor ( n8719 , n8716 , n8717 );
xor ( n8720 , n8334 , n8339 );
nor ( n8721 , n3107 , n8613 );
and ( n8722 , n8720 , n8721 );
xor ( n8723 , n8720 , n8721 );
xor ( n8724 , n8336 , n8337 );
buf ( n8725 , n8724 );
nor ( n8726 , n3116 , n8613 );
and ( n8727 , n8725 , n8726 );
xor ( n8728 , n8725 , n8726 );
nor ( n8729 , n3134 , n8223 );
buf ( n8730 , n8729 );
nor ( n8731 , n3125 , n8613 );
and ( n8732 , n8730 , n8731 );
buf ( n8733 , n8732 );
and ( n8734 , n8728 , n8733 );
or ( n8735 , n8727 , n8734 );
and ( n8736 , n8723 , n8735 );
or ( n8737 , n8722 , n8736 );
and ( n8738 , n8719 , n8737 );
or ( n8739 , n8718 , n8738 );
and ( n8740 , n8715 , n8739 );
or ( n8741 , n8714 , n8740 );
and ( n8742 , n8711 , n8741 );
or ( n8743 , n8710 , n8742 );
and ( n8744 , n8707 , n8743 );
or ( n8745 , n8706 , n8744 );
and ( n8746 , n8703 , n8745 );
or ( n8747 , n8702 , n8746 );
and ( n8748 , n8699 , n8747 );
or ( n8749 , n8698 , n8748 );
and ( n8750 , n8695 , n8749 );
or ( n8751 , n8694 , n8750 );
and ( n8752 , n8691 , n8751 );
or ( n8753 , n8690 , n8752 );
and ( n8754 , n8687 , n8753 );
or ( n8755 , n8686 , n8754 );
and ( n8756 , n8683 , n8755 );
or ( n8757 , n8682 , n8756 );
and ( n8758 , n8679 , n8757 );
or ( n8759 , n8678 , n8758 );
and ( n8760 , n8675 , n8759 );
or ( n8761 , n8674 , n8760 );
and ( n8762 , n8671 , n8761 );
or ( n8763 , n8670 , n8762 );
and ( n8764 , n8667 , n8763 );
or ( n8765 , n8666 , n8764 );
and ( n8766 , n8663 , n8765 );
or ( n8767 , n8662 , n8766 );
and ( n8768 , n8659 , n8767 );
or ( n8769 , n8658 , n8768 );
and ( n8770 , n8655 , n8769 );
or ( n8771 , n8654 , n8770 );
and ( n8772 , n8651 , n8771 );
or ( n8773 , n8650 , n8772 );
and ( n8774 , n8647 , n8773 );
or ( n8775 , n8646 , n8774 );
and ( n8776 , n8643 , n8775 );
or ( n8777 , n8642 , n8776 );
and ( n8778 , n8639 , n8777 );
or ( n8779 , n8638 , n8778 );
and ( n8780 , n8635 , n8779 );
or ( n8781 , n8634 , n8780 );
and ( n8782 , n8631 , n8781 );
or ( n8783 , n8630 , n8782 );
and ( n8784 , n8627 , n8783 );
or ( n8785 , n8626 , n8784 );
and ( n8786 , n8623 , n8785 );
or ( n8787 , n8622 , n8786 );
and ( n8788 , n8619 , n8787 );
or ( n8789 , n8618 , n8788 );
xor ( n8790 , n8615 , n8789 );
buf ( n8791 , n8790 );
buf ( n8792 , n8791 );
xor ( n8793 , n8619 , n8787 );
buf ( n8794 , n8793 );
buf ( n8795 , n8794 );
xor ( n8796 , n8623 , n8785 );
buf ( n8797 , n8796 );
buf ( n8798 , n8797 );
xor ( n8799 , n8627 , n8783 );
buf ( n8800 , n8799 );
buf ( n8801 , n8800 );
xor ( n8802 , n8631 , n8781 );
buf ( n8803 , n8802 );
buf ( n8804 , n8803 );
xor ( n8805 , n8635 , n8779 );
buf ( n8806 , n8805 );
buf ( n8807 , n8806 );
xor ( n8808 , n8639 , n8777 );
buf ( n8809 , n8808 );
buf ( n8810 , n8809 );
xor ( n8811 , n8643 , n8775 );
buf ( n8812 , n8811 );
buf ( n8813 , n8812 );
xor ( n8814 , n8647 , n8773 );
buf ( n8815 , n8814 );
buf ( n8816 , n8815 );
xor ( n8817 , n8651 , n8771 );
buf ( n8818 , n8817 );
buf ( n8819 , n8818 );
xor ( n8820 , n8655 , n8769 );
buf ( n8821 , n8820 );
buf ( n8822 , n8821 );
xor ( n8823 , n8659 , n8767 );
buf ( n8824 , n8823 );
buf ( n8825 , n8824 );
xor ( n8826 , n8663 , n8765 );
buf ( n8827 , n8826 );
buf ( n8828 , n8827 );
xor ( n8829 , n8667 , n8763 );
buf ( n8830 , n8829 );
buf ( n8831 , n8830 );
xor ( n8832 , n8671 , n8761 );
buf ( n8833 , n8832 );
buf ( n8834 , n8833 );
xor ( n8835 , n8675 , n8759 );
buf ( n8836 , n8835 );
buf ( n8837 , n8836 );
endmodule
|
module add3gt4(input wire[3:0] in_val, output reg[3:0] out_val);
always @(in_val) begin
case (in_val)
4'b0101: out_val <= 4'b1000;
4'b0110: out_val <= 4'b1001;
4'b0111: out_val <= 4'b1010;
4'b1000: out_val <= 4'b1011;
4'b1001: out_val <= 4'b1100;
4'b1010: out_val <= 4'b1101;
4'b1011: out_val <= 4'b1110;
4'b1100: out_val <= 4'b1111;
default: out_val <= in_val;
endcase
end
endmodule
module add3gt4_n #(parameter N = 1)
(input wire [4 * N - 1 : 0] in_val,
output wire [4 * N - 1 : 0] out_val);
genvar i;
generate
for(i = 0; i < N; i = i + 1) begin: gen_add3
add3gt4 add3(in_val[4 * (i + 1) - 1: 4 * i], out_val[4 * (i + 1) - 1: 4 * i]);
end
endgenerate
endmodule
module bin2bcd #(parameter IN_BITS = 8,
parameter OUT_BITS = 10)
(input wire [IN_BITS-1:0] bin_number,
output wire [OUT_BITS-1:0] bcd_number);
genvar bits_shifted;
generate
for (bits_shifted = 3; bits_shifted < IN_BITS; bits_shifted = bits_shifted + 1) begin : gen
wire [IN_BITS + bits_shifted / 3 - 1 : 0] out_wires;
if(bits_shifted == 3) begin
add3gt4_n #(bits_shifted / 3) add3n(
{1'b0, bin_number[IN_BITS - 1 : IN_BITS - 3]},
out_wires[IN_BITS : IN_BITS - 3]
);
assign out_wires[IN_BITS - 4: 0] = bin_number[IN_BITS - 4:0];
end else if(bits_shifted % 3 == 0) begin
add3gt4_n #(bits_shifted / 3) add3n(
{1'b0, gen[bits_shifted - 1].out_wires[IN_BITS + (bits_shifted - 1) / 3 - 1 : IN_BITS - (bits_shifted / 3) * 3]},
out_wires[IN_BITS + bits_shifted / 3 - 1 : IN_BITS - (bits_shifted / 3) * 3]
);
assign out_wires[IN_BITS - (bits_shifted / 3) * 3 - 1: 0] = bin_number[IN_BITS - (bits_shifted / 3) * 3 - 1:0];
end else begin
add3gt4_n #(bits_shifted / 3) add3n(
{gen[bits_shifted - 1].out_wires[IN_BITS + bits_shifted / 3 - 1 - bits_shifted % 3 : IN_BITS - (bits_shifted / 3) * 3 - bits_shifted % 3]},
out_wires[IN_BITS + bits_shifted / 3 - 1 - bits_shifted % 3 : IN_BITS - (bits_shifted / 3) * 3 - bits_shifted % 3]
);
assign out_wires[IN_BITS + bits_shifted / 3 - 1: IN_BITS + bits_shifted / 3 - bits_shifted % 3] = gen[bits_shifted - 1].out_wires[IN_BITS + bits_shifted / 3 - 1 : IN_BITS + bits_shifted / 3 - bits_shifted % 3];
assign out_wires[IN_BITS - (bits_shifted / 3) * 3 - bits_shifted % 3 - 1: 0] = bin_number[IN_BITS - (bits_shifted / 3) * 3 - bits_shifted % 3 - 1:0];
end
end
assign bcd_number = gen[IN_BITS - 1].out_wires;
endgenerate
endmodule
|
`timescale 1 ns / 1 ps
`include "AXI_to_audio_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module AXI_to_audio_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: spll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module spll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 2,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=spll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "spll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`define SMV
`include "ovl_delta_wrapped.v"
`include "ovl_ported/ovl_delta.v"
//`include "globalDefines.vh"
/*
* File: ovl_delta_wrapped_tb.v
* Test bench for ovl_delta_wrapped.v
* Includes assertions for verification.
* Created 2013-10-16
*
* Verified with the following parameters:
* test_expr width min/max width user time system time
* 4 bits 2 bits 0.01 sec 0
* 5 bits 3 bits 0.08 sec 0
* 6 bits 3 bits 0.22 sec 0
* 7 bits 3 bits 0.83 sec 0
* 8 bits 3 bits 2.74 sec 0.01 sec
* 9 bits 3 bits 11.5 sec 0.02 sec
* 10 bits 3 bits 57.42 sec 0.04 sec
* 11 bits 3 bits 249.75 sec 0.06 sec ~2.7M BDD nodes
* 12 bits 3 bits 1070.17 sec 0.1 sec ~5.4M BDD noes
* 15 bits 3 bits Error at ~9M BDD nodes
*/
module main();
//Inputs to DUT
reg clk;
reg rst;
// reg [7:0] min;
// reg [7:0] max;
// reg [31:0] test_expr;
reg [2:0] min;
reg [2:0] max;
reg [11:0] test_expr;
reg prevConfigInvalid;
//Outputs to DUT
wire out;
reg [11:0] test_expr_prev;
ovl_delta_wrapped ovl_dw_t(.clk(clk),
.rst(rst),
.min(min),
.max(max),
.test_expr(test_expr),
.prevConfigInvalid(prevConfigInvalid),
.out(out));
initial begin
clk = 0;
rst = 1;
min = 0;
max = 0;
test_expr = 0;
test_expr_prev = 0;
prevConfigInvalid = 0;
end
always begin
clk = #5 !clk;
end
always @(posedge clk) begin
test_expr_prev <= test_expr;
end
endmodule // main
/* *************** SMV Assertions *****************
//SMV-Assertions
# Spec:
# Let diff = |test_expr@t - test_expr@t-1|.
# diff is only valid when ~reset@t AND ~reset@t-1
# precondition: min <= max
# @time t:
# IF diff != 0 AND (diff < min OR diff > max)
# THEN @t+1, ~prevConfigInvalid -> out
# out is low in the cycle following reset.
\reset_clears_out : assert G(\rst -> X(~\out ));
# prevConfigInvalid and out are never both high.
\prevConfigInvalid_clears_out : assert \rst -> X(G(\out -> ~\prevConfigInvalid ));
# test_expr_prev captures previous value as expected
\test_expr_prev_spec1 : assert \rst -> X(G((\test_expr [0]) -> X(\test_expr_prev [0])));
\test_expr_prev_spec2 : assert \rst -> X(G(~\test_expr [0] -> X(~\test_expr_prev [0])));
# implements the spec
\large_delta_triggers : assert \rst -> X(G(~\rst -> X((\min <= max ) -> (~\rst && (~((((\test_expr_prev - \test_expr ) >= \min ) && ((\test_expr_prev - \test_expr ) <= \max )) || (((\test_expr - \test_expr_prev ) >= \min ) && ((\test_expr - \test_expr_prev ) <= \max )) || (\test_expr_prev = \test_expr ) ))-> X(~\prevConfigInvalid -> \out )))));
# out is never triggered when delta = 0
\delta_0_doesnot_trigger : assert \rst -> X(G((\test_expr = \test_expr_prev ) -> X(~\out )));
//SMV-Assertions
*/
|
`timescale 1ns / 1ps
//
// Validates that updating a pattern works according to design.
//
// In testing on the hardware, PuTTY was having trouble reliably sending and
// receiving the lowercase letter 'a'. Nothing else; the test data here worked
// fine. So this variation attempts to figure out why.
// Wait a random amount of time, then send 'a', repeatedly over and over. If the
// receiver ever receives something other than 'a' back, assert.
module test;
// Inputs
reg clk = 0;
reg rx = 1; // RS-232 idle condition is logic high
reg xmit = 0;
reg recv = 0;
reg write_complete_received = 0;
reg test_step_complete = 0;
integer i = 0;
integer j = 0;
integer random_delay;
reg [7:0] received_byte = 0;
reg [7:0] test_send_vector [0:576];
integer test_send_vector_len = 576;
reg [7:0] test_receive_vector [0:384];
integer test_receive_vector_len = 384;
initial begin
test_send_vector[0] = "i";
test_send_vector[1] = 8'h0;
test_send_vector[2] = 8'h0;
test_send_vector[3] = "i";
test_send_vector[4] = 8'h0;
test_send_vector[5] = 8'h1;
test_send_vector[6] = "i";
test_send_vector[7] = 8'h0;
test_send_vector[8] = 8'h2;
test_send_vector[9] = "i";
test_send_vector[10] = 8'h0;
test_send_vector[11] = 8'h3;
test_send_vector[12] = "i";
test_send_vector[13] = 8'h0;
test_send_vector[14] = 8'h4;
test_send_vector[15] = "i";
test_send_vector[16] = 8'h0;
test_send_vector[17] = 8'h5;
test_send_vector[18] = "i";
test_send_vector[19] = 8'h0;
test_send_vector[20] = 8'h6;
test_send_vector[21] = "i";
test_send_vector[22] = 8'h0;
test_send_vector[23] = 8'h7;
test_send_vector[24] = "i";
test_send_vector[25] = 8'h1;
test_send_vector[26] = 8'h0;
test_send_vector[27] = "i";
test_send_vector[28] = 8'h1;
test_send_vector[29] = 8'h1;
test_send_vector[30] = "i";
test_send_vector[31] = 8'h1;
test_send_vector[32] = 8'h2;
test_send_vector[33] = "i";
test_send_vector[34] = 8'h1;
test_send_vector[35] = 8'h3;
test_send_vector[36] = "i";
test_send_vector[37] = 8'h1;
test_send_vector[38] = 8'h4;
test_send_vector[39] = "i";
test_send_vector[40] = 8'h1;
test_send_vector[41] = 8'h5;
test_send_vector[42] = "i";
test_send_vector[43] = 8'h1;
test_send_vector[44] = 8'h6;
test_send_vector[45] = "i";
test_send_vector[46] = 8'h1;
test_send_vector[47] = 8'h7;
test_send_vector[48] = "i";
test_send_vector[49] = 8'h2;
test_send_vector[50] = 8'h0;
test_send_vector[51] = "i";
test_send_vector[52] = 8'h2;
test_send_vector[53] = 8'h1;
test_send_vector[54] = "i";
test_send_vector[55] = 8'h2;
test_send_vector[56] = 8'h2;
test_send_vector[57] = "i";
test_send_vector[58] = 8'h2;
test_send_vector[59] = 8'h3;
test_send_vector[60] = "i";
test_send_vector[61] = 8'h2;
test_send_vector[62] = 8'h4;
test_send_vector[63] = "i";
test_send_vector[64] = 8'h2;
test_send_vector[65] = 8'h5;
test_send_vector[66] = "i";
test_send_vector[67] = 8'h2;
test_send_vector[68] = 8'h6;
test_send_vector[69] = "i";
test_send_vector[70] = 8'h2;
test_send_vector[71] = 8'h7;
test_send_vector[72] = "i";
test_send_vector[73] = 8'h3;
test_send_vector[74] = 8'h0;
test_send_vector[75] = "i";
test_send_vector[76] = 8'h3;
test_send_vector[77] = 8'h1;
test_send_vector[78] = "i";
test_send_vector[79] = 8'h3;
test_send_vector[80] = 8'h2;
test_send_vector[81] = "i";
test_send_vector[82] = 8'h3;
test_send_vector[83] = 8'h3;
test_send_vector[84] = "i";
test_send_vector[85] = 8'h3;
test_send_vector[86] = 8'h4;
test_send_vector[87] = "i";
test_send_vector[88] = 8'h3;
test_send_vector[89] = 8'h5;
test_send_vector[90] = "i";
test_send_vector[91] = 8'h3;
test_send_vector[92] = 8'h6;
test_send_vector[93] = "i";
test_send_vector[94] = 8'h3;
test_send_vector[95] = 8'h7;
test_send_vector[96] = "i";
test_send_vector[97] = 8'h4;
test_send_vector[98] = 8'h0;
test_send_vector[99] = "i";
test_send_vector[100] = 8'h4;
test_send_vector[101] = 8'h1;
test_send_vector[102] = "i";
test_send_vector[103] = 8'h4;
test_send_vector[104] = 8'h2;
test_send_vector[105] = "i";
test_send_vector[106] = 8'h4;
test_send_vector[107] = 8'h3;
test_send_vector[108] = "i";
test_send_vector[109] = 8'h4;
test_send_vector[110] = 8'h4;
test_send_vector[111] = "i";
test_send_vector[112] = 8'h4;
test_send_vector[113] = 8'h5;
test_send_vector[114] = "i";
test_send_vector[115] = 8'h4;
test_send_vector[116] = 8'h6;
test_send_vector[117] = "i";
test_send_vector[118] = 8'h4;
test_send_vector[119] = 8'h7;
test_send_vector[120] = "i";
test_send_vector[121] = 8'h5;
test_send_vector[122] = 8'h0;
test_send_vector[123] = "i";
test_send_vector[124] = 8'h5;
test_send_vector[125] = 8'h1;
test_send_vector[126] = "i";
test_send_vector[127] = 8'h5;
test_send_vector[128] = 8'h2;
test_send_vector[129] = "i";
test_send_vector[130] = 8'h5;
test_send_vector[131] = 8'h3;
test_send_vector[132] = "i";
test_send_vector[133] = 8'h5;
test_send_vector[134] = 8'h4;
test_send_vector[135] = "i";
test_send_vector[136] = 8'h5;
test_send_vector[137] = 8'h5;
test_send_vector[138] = "i";
test_send_vector[139] = 8'h5;
test_send_vector[140] = 8'h6;
test_send_vector[141] = "i";
test_send_vector[142] = 8'h5;
test_send_vector[143] = 8'h7;
test_send_vector[144] = "i";
test_send_vector[145] = 8'h6;
test_send_vector[146] = 8'h0;
test_send_vector[147] = "i";
test_send_vector[148] = 8'h6;
test_send_vector[149] = 8'h1;
test_send_vector[150] = "i";
test_send_vector[151] = 8'h6;
test_send_vector[152] = 8'h2;
test_send_vector[153] = "i";
test_send_vector[154] = 8'h6;
test_send_vector[155] = 8'h3;
test_send_vector[156] = "i";
test_send_vector[157] = 8'h6;
test_send_vector[158] = 8'h4;
test_send_vector[159] = "i";
test_send_vector[160] = 8'h6;
test_send_vector[161] = 8'h5;
test_send_vector[162] = "i";
test_send_vector[163] = 8'h6;
test_send_vector[164] = 8'h6;
test_send_vector[165] = "i";
test_send_vector[166] = 8'h6;
test_send_vector[167] = 8'h7;
test_send_vector[168] = "i";
test_send_vector[169] = 8'h7;
test_send_vector[170] = 8'h0;
test_send_vector[171] = "i";
test_send_vector[172] = 8'h7;
test_send_vector[173] = 8'h1;
test_send_vector[174] = "i";
test_send_vector[175] = 8'h7;
test_send_vector[176] = 8'h2;
test_send_vector[177] = "i";
test_send_vector[178] = 8'h7;
test_send_vector[179] = 8'h3;
test_send_vector[180] = "i";
test_send_vector[181] = 8'h7;
test_send_vector[182] = 8'h4;
test_send_vector[183] = "i";
test_send_vector[184] = 8'h7;
test_send_vector[185] = 8'h5;
test_send_vector[186] = "i";
test_send_vector[187] = 8'h7;
test_send_vector[188] = 8'h6;
test_send_vector[189] = "i";
test_send_vector[190] = 8'h7;
test_send_vector[191] = 8'h7;
test_send_vector[192] = "i";
test_send_vector[193] = 8'h8;
test_send_vector[194] = 8'h0;
test_send_vector[195] = "i";
test_send_vector[196] = 8'h8;
test_send_vector[197] = 8'h1;
test_send_vector[198] = "i";
test_send_vector[199] = 8'h8;
test_send_vector[200] = 8'h2;
test_send_vector[201] = "i";
test_send_vector[202] = 8'h8;
test_send_vector[203] = 8'h3;
test_send_vector[204] = "i";
test_send_vector[205] = 8'h8;
test_send_vector[206] = 8'h4;
test_send_vector[207] = "i";
test_send_vector[208] = 8'h8;
test_send_vector[209] = 8'h5;
test_send_vector[210] = "i";
test_send_vector[211] = 8'h8;
test_send_vector[212] = 8'h6;
test_send_vector[213] = "i";
test_send_vector[214] = 8'h8;
test_send_vector[215] = 8'h7;
test_send_vector[216] = "i";
test_send_vector[217] = 8'h9;
test_send_vector[218] = 8'h0;
test_send_vector[219] = "i";
test_send_vector[220] = 8'h9;
test_send_vector[221] = 8'h1;
test_send_vector[222] = "i";
test_send_vector[223] = 8'h9;
test_send_vector[224] = 8'h2;
test_send_vector[225] = "i";
test_send_vector[226] = 8'h9;
test_send_vector[227] = 8'h3;
test_send_vector[228] = "i";
test_send_vector[229] = 8'h9;
test_send_vector[230] = 8'h4;
test_send_vector[231] = "i";
test_send_vector[232] = 8'h9;
test_send_vector[233] = 8'h5;
test_send_vector[234] = "i";
test_send_vector[235] = 8'h9;
test_send_vector[236] = 8'h6;
test_send_vector[237] = "i";
test_send_vector[238] = 8'h9;
test_send_vector[239] = 8'h7;
test_send_vector[240] = "i";
test_send_vector[241] = 8'ha;
test_send_vector[242] = 8'h0;
test_send_vector[243] = "i";
test_send_vector[244] = 8'ha;
test_send_vector[245] = 8'h1;
test_send_vector[246] = "i";
test_send_vector[247] = 8'ha;
test_send_vector[248] = 8'h2;
test_send_vector[249] = "i";
test_send_vector[250] = 8'ha;
test_send_vector[251] = 8'h3;
test_send_vector[252] = "i";
test_send_vector[253] = 8'ha;
test_send_vector[254] = 8'h4;
test_send_vector[255] = "i";
test_send_vector[256] = 8'ha;
test_send_vector[257] = 8'h5;
test_send_vector[258] = "i";
test_send_vector[259] = 8'ha;
test_send_vector[260] = 8'h6;
test_send_vector[261] = "i";
test_send_vector[262] = 8'ha;
test_send_vector[263] = 8'h7;
test_send_vector[264] = "i";
test_send_vector[265] = 8'hb;
test_send_vector[266] = 8'h0;
test_send_vector[267] = "i";
test_send_vector[268] = 8'hb;
test_send_vector[269] = 8'h1;
test_send_vector[270] = "i";
test_send_vector[271] = 8'hb;
test_send_vector[272] = 8'h2;
test_send_vector[273] = "i";
test_send_vector[274] = 8'hb;
test_send_vector[275] = 8'h3;
test_send_vector[276] = "i";
test_send_vector[277] = 8'hb;
test_send_vector[278] = 8'h4;
test_send_vector[279] = "i";
test_send_vector[280] = 8'hb;
test_send_vector[281] = 8'h5;
test_send_vector[282] = "i";
test_send_vector[283] = 8'hb;
test_send_vector[284] = 8'h6;
test_send_vector[285] = "i";
test_send_vector[286] = 8'hb;
test_send_vector[287] = 8'h7;
test_send_vector[288] = "i";
test_send_vector[289] = 8'hc;
test_send_vector[290] = 8'h0;
test_send_vector[291] = "i";
test_send_vector[292] = 8'hc;
test_send_vector[293] = 8'h1;
test_send_vector[294] = "i";
test_send_vector[295] = 8'hc;
test_send_vector[296] = 8'h2;
test_send_vector[297] = "i";
test_send_vector[298] = 8'hc;
test_send_vector[299] = 8'h3;
test_send_vector[300] = "i";
test_send_vector[301] = 8'hc;
test_send_vector[302] = 8'h4;
test_send_vector[303] = "i";
test_send_vector[304] = 8'hc;
test_send_vector[305] = 8'h5;
test_send_vector[306] = "i";
test_send_vector[307] = 8'hc;
test_send_vector[308] = 8'h6;
test_send_vector[309] = "i";
test_send_vector[310] = 8'hc;
test_send_vector[311] = 8'h7;
test_send_vector[312] = "i";
test_send_vector[313] = 8'hd;
test_send_vector[314] = 8'h0;
test_send_vector[315] = "i";
test_send_vector[316] = 8'hd;
test_send_vector[317] = 8'h1;
test_send_vector[318] = "i";
test_send_vector[319] = 8'hd;
test_send_vector[320] = 8'h2;
test_send_vector[321] = "i";
test_send_vector[322] = 8'hd;
test_send_vector[323] = 8'h3;
test_send_vector[324] = "i";
test_send_vector[325] = 8'hd;
test_send_vector[326] = 8'h4;
test_send_vector[327] = "i";
test_send_vector[328] = 8'hd;
test_send_vector[329] = 8'h5;
test_send_vector[330] = "i";
test_send_vector[331] = 8'hd;
test_send_vector[332] = 8'h6;
test_send_vector[333] = "i";
test_send_vector[334] = 8'hd;
test_send_vector[335] = 8'h7;
test_send_vector[336] = "i";
test_send_vector[337] = 8'he;
test_send_vector[338] = 8'h0;
test_send_vector[339] = "i";
test_send_vector[340] = 8'he;
test_send_vector[341] = 8'h1;
test_send_vector[342] = "i";
test_send_vector[343] = 8'he;
test_send_vector[344] = 8'h2;
test_send_vector[345] = "i";
test_send_vector[346] = 8'he;
test_send_vector[347] = 8'h3;
test_send_vector[348] = "i";
test_send_vector[349] = 8'he;
test_send_vector[350] = 8'h4;
test_send_vector[351] = "i";
test_send_vector[352] = 8'he;
test_send_vector[353] = 8'h5;
test_send_vector[354] = "i";
test_send_vector[355] = 8'he;
test_send_vector[356] = 8'h6;
test_send_vector[357] = "i";
test_send_vector[358] = 8'he;
test_send_vector[359] = 8'h7;
test_send_vector[360] = "i";
test_send_vector[361] = 8'hf;
test_send_vector[362] = 8'h0;
test_send_vector[363] = "i";
test_send_vector[364] = 8'hf;
test_send_vector[365] = 8'h1;
test_send_vector[366] = "i";
test_send_vector[367] = 8'hf;
test_send_vector[368] = 8'h2;
test_send_vector[369] = "i";
test_send_vector[370] = 8'hf;
test_send_vector[371] = 8'h3;
test_send_vector[372] = "i";
test_send_vector[373] = 8'hf;
test_send_vector[374] = 8'h4;
test_send_vector[375] = "i";
test_send_vector[376] = 8'hf;
test_send_vector[377] = 8'h5;
test_send_vector[378] = "i";
test_send_vector[379] = 8'hf;
test_send_vector[380] = 8'h6;
test_send_vector[381] = "i";
test_send_vector[382] = 8'hf;
test_send_vector[383] = 8'h7;
test_send_vector[384] = "i";
test_send_vector[385] = 8'h10;
test_send_vector[386] = 8'h0;
test_send_vector[387] = "i";
test_send_vector[388] = 8'h10;
test_send_vector[389] = 8'h1;
test_send_vector[390] = "i";
test_send_vector[391] = 8'h10;
test_send_vector[392] = 8'h2;
test_send_vector[393] = "i";
test_send_vector[394] = 8'h10;
test_send_vector[395] = 8'h3;
test_send_vector[396] = "i";
test_send_vector[397] = 8'h10;
test_send_vector[398] = 8'h4;
test_send_vector[399] = "i";
test_send_vector[400] = 8'h10;
test_send_vector[401] = 8'h5;
test_send_vector[402] = "i";
test_send_vector[403] = 8'h10;
test_send_vector[404] = 8'h6;
test_send_vector[405] = "i";
test_send_vector[406] = 8'h10;
test_send_vector[407] = 8'h7;
test_send_vector[408] = "i";
test_send_vector[409] = 8'h11;
test_send_vector[410] = 8'h0;
test_send_vector[411] = "i";
test_send_vector[412] = 8'h11;
test_send_vector[413] = 8'h1;
test_send_vector[414] = "i";
test_send_vector[415] = 8'h11;
test_send_vector[416] = 8'h2;
test_send_vector[417] = "i";
test_send_vector[418] = 8'h11;
test_send_vector[419] = 8'h3;
test_send_vector[420] = "i";
test_send_vector[421] = 8'h11;
test_send_vector[422] = 8'h4;
test_send_vector[423] = "i";
test_send_vector[424] = 8'h11;
test_send_vector[425] = 8'h5;
test_send_vector[426] = "i";
test_send_vector[427] = 8'h11;
test_send_vector[428] = 8'h6;
test_send_vector[429] = "i";
test_send_vector[430] = 8'h11;
test_send_vector[431] = 8'h7;
test_send_vector[432] = "i";
test_send_vector[433] = 8'h12;
test_send_vector[434] = 8'h0;
test_send_vector[435] = "i";
test_send_vector[436] = 8'h12;
test_send_vector[437] = 8'h1;
test_send_vector[438] = "i";
test_send_vector[439] = 8'h12;
test_send_vector[440] = 8'h2;
test_send_vector[441] = "i";
test_send_vector[442] = 8'h12;
test_send_vector[443] = 8'h3;
test_send_vector[444] = "i";
test_send_vector[445] = 8'h12;
test_send_vector[446] = 8'h4;
test_send_vector[447] = "i";
test_send_vector[448] = 8'h12;
test_send_vector[449] = 8'h5;
test_send_vector[450] = "i";
test_send_vector[451] = 8'h12;
test_send_vector[452] = 8'h6;
test_send_vector[453] = "i";
test_send_vector[454] = 8'h12;
test_send_vector[455] = 8'h7;
test_send_vector[456] = "i";
test_send_vector[457] = 8'h13;
test_send_vector[458] = 8'h0;
test_send_vector[459] = "i";
test_send_vector[460] = 8'h13;
test_send_vector[461] = 8'h1;
test_send_vector[462] = "i";
test_send_vector[463] = 8'h13;
test_send_vector[464] = 8'h2;
test_send_vector[465] = "i";
test_send_vector[466] = 8'h13;
test_send_vector[467] = 8'h3;
test_send_vector[468] = "i";
test_send_vector[469] = 8'h13;
test_send_vector[470] = 8'h4;
test_send_vector[471] = "i";
test_send_vector[472] = 8'h13;
test_send_vector[473] = 8'h5;
test_send_vector[474] = "i";
test_send_vector[475] = 8'h13;
test_send_vector[476] = 8'h6;
test_send_vector[477] = "i";
test_send_vector[478] = 8'h13;
test_send_vector[479] = 8'h7;
test_send_vector[480] = "i";
test_send_vector[481] = 8'h14;
test_send_vector[482] = 8'h0;
test_send_vector[483] = "i";
test_send_vector[484] = 8'h14;
test_send_vector[485] = 8'h1;
test_send_vector[486] = "i";
test_send_vector[487] = 8'h14;
test_send_vector[488] = 8'h2;
test_send_vector[489] = "i";
test_send_vector[490] = 8'h14;
test_send_vector[491] = 8'h3;
test_send_vector[492] = "i";
test_send_vector[493] = 8'h14;
test_send_vector[494] = 8'h4;
test_send_vector[495] = "i";
test_send_vector[496] = 8'h14;
test_send_vector[497] = 8'h5;
test_send_vector[498] = "i";
test_send_vector[499] = 8'h14;
test_send_vector[500] = 8'h6;
test_send_vector[501] = "i";
test_send_vector[502] = 8'h14;
test_send_vector[503] = 8'h7;
test_send_vector[504] = "i";
test_send_vector[505] = 8'h15;
test_send_vector[506] = 8'h0;
test_send_vector[507] = "i";
test_send_vector[508] = 8'h15;
test_send_vector[509] = 8'h1;
test_send_vector[510] = "i";
test_send_vector[511] = 8'h15;
test_send_vector[512] = 8'h2;
test_send_vector[513] = "i";
test_send_vector[514] = 8'h15;
test_send_vector[515] = 8'h3;
test_send_vector[516] = "i";
test_send_vector[517] = 8'h15;
test_send_vector[518] = 8'h4;
test_send_vector[519] = "i";
test_send_vector[520] = 8'h15;
test_send_vector[521] = 8'h5;
test_send_vector[522] = "i";
test_send_vector[523] = 8'h15;
test_send_vector[524] = 8'h6;
test_send_vector[525] = "i";
test_send_vector[526] = 8'h15;
test_send_vector[527] = 8'h7;
test_send_vector[528] = "i";
test_send_vector[529] = 8'h16;
test_send_vector[530] = 8'h0;
test_send_vector[531] = "i";
test_send_vector[532] = 8'h16;
test_send_vector[533] = 8'h1;
test_send_vector[534] = "i";
test_send_vector[535] = 8'h16;
test_send_vector[536] = 8'h2;
test_send_vector[537] = "i";
test_send_vector[538] = 8'h16;
test_send_vector[539] = 8'h3;
test_send_vector[540] = "i";
test_send_vector[541] = 8'h16;
test_send_vector[542] = 8'h4;
test_send_vector[543] = "i";
test_send_vector[544] = 8'h16;
test_send_vector[545] = 8'h5;
test_send_vector[546] = "i";
test_send_vector[547] = 8'h16;
test_send_vector[548] = 8'h6;
test_send_vector[549] = "i";
test_send_vector[550] = 8'h16;
test_send_vector[551] = 8'h7;
test_send_vector[552] = "i";
test_send_vector[553] = 8'h17;
test_send_vector[554] = 8'h0;
test_send_vector[555] = "i";
test_send_vector[556] = 8'h17;
test_send_vector[557] = 8'h1;
test_send_vector[558] = "i";
test_send_vector[559] = 8'h17;
test_send_vector[560] = 8'h2;
test_send_vector[561] = "i";
test_send_vector[562] = 8'h17;
test_send_vector[563] = 8'h3;
test_send_vector[564] = "i";
test_send_vector[565] = 8'h17;
test_send_vector[566] = 8'h4;
test_send_vector[567] = "i";
test_send_vector[568] = 8'h17;
test_send_vector[569] = 8'h5;
test_send_vector[570] = "i";
test_send_vector[571] = 8'h17;
test_send_vector[572] = 8'h6;
test_send_vector[573] = "i";
test_send_vector[574] = 8'h17;
test_send_vector[575] = 8'h7;
test_receive_vector[0] = 8'h0;
test_receive_vector[1] = 8'h0;
test_receive_vector[2] = 8'h0;
test_receive_vector[3] = 8'h1;
test_receive_vector[4] = 8'h0;
test_receive_vector[5] = 8'h2;
test_receive_vector[6] = 8'h0;
test_receive_vector[7] = 8'h3;
test_receive_vector[8] = 8'h0;
test_receive_vector[9] = 8'h4;
test_receive_vector[10] = 8'h0;
test_receive_vector[11] = 8'h5;
test_receive_vector[12] = 8'h0;
test_receive_vector[13] = 8'h6;
test_receive_vector[14] = 8'h0;
test_receive_vector[15] = 8'h7;
test_receive_vector[16] = 8'h1;
test_receive_vector[17] = 8'h0;
test_receive_vector[18] = 8'h1;
test_receive_vector[19] = 8'h1;
test_receive_vector[20] = 8'h1;
test_receive_vector[21] = 8'h2;
test_receive_vector[22] = 8'h1;
test_receive_vector[23] = 8'h3;
test_receive_vector[24] = 8'h1;
test_receive_vector[25] = 8'h4;
test_receive_vector[26] = 8'h1;
test_receive_vector[27] = 8'h5;
test_receive_vector[28] = 8'h1;
test_receive_vector[29] = 8'h6;
test_receive_vector[30] = 8'h1;
test_receive_vector[31] = 8'h7;
test_receive_vector[32] = 8'h2;
test_receive_vector[33] = 8'h0;
test_receive_vector[34] = 8'h2;
test_receive_vector[35] = 8'h1;
test_receive_vector[36] = 8'h2;
test_receive_vector[37] = 8'h2;
test_receive_vector[38] = 8'h2;
test_receive_vector[39] = 8'h3;
test_receive_vector[40] = 8'h2;
test_receive_vector[41] = 8'h4;
test_receive_vector[42] = 8'h2;
test_receive_vector[43] = 8'h5;
test_receive_vector[44] = 8'h2;
test_receive_vector[45] = 8'h6;
test_receive_vector[46] = 8'h2;
test_receive_vector[47] = 8'h7;
test_receive_vector[48] = 8'h3;
test_receive_vector[49] = 8'h0;
test_receive_vector[50] = 8'h3;
test_receive_vector[51] = 8'h1;
test_receive_vector[52] = 8'h3;
test_receive_vector[53] = 8'h2;
test_receive_vector[54] = 8'h3;
test_receive_vector[55] = 8'h3;
test_receive_vector[56] = 8'h3;
test_receive_vector[57] = 8'h4;
test_receive_vector[58] = 8'h3;
test_receive_vector[59] = 8'h5;
test_receive_vector[60] = 8'h3;
test_receive_vector[61] = 8'h6;
test_receive_vector[62] = 8'h3;
test_receive_vector[63] = 8'h7;
test_receive_vector[64] = 8'h4;
test_receive_vector[65] = 8'h0;
test_receive_vector[66] = 8'h4;
test_receive_vector[67] = 8'h1;
test_receive_vector[68] = 8'h4;
test_receive_vector[69] = 8'h2;
test_receive_vector[70] = 8'h4;
test_receive_vector[71] = 8'h3;
test_receive_vector[72] = 8'h4;
test_receive_vector[73] = 8'h4;
test_receive_vector[74] = 8'h4;
test_receive_vector[75] = 8'h5;
test_receive_vector[76] = 8'h4;
test_receive_vector[77] = 8'h6;
test_receive_vector[78] = 8'h4;
test_receive_vector[79] = 8'h7;
test_receive_vector[80] = 8'h5;
test_receive_vector[81] = 8'h0;
test_receive_vector[82] = 8'h5;
test_receive_vector[83] = 8'h1;
test_receive_vector[84] = 8'h5;
test_receive_vector[85] = 8'h2;
test_receive_vector[86] = 8'h5;
test_receive_vector[87] = 8'h3;
test_receive_vector[88] = 8'h5;
test_receive_vector[89] = 8'h4;
test_receive_vector[90] = 8'h5;
test_receive_vector[91] = 8'h5;
test_receive_vector[92] = 8'h5;
test_receive_vector[93] = 8'h6;
test_receive_vector[94] = 8'h5;
test_receive_vector[95] = 8'h7;
test_receive_vector[96] = 8'h6;
test_receive_vector[97] = 8'h0;
test_receive_vector[98] = 8'h6;
test_receive_vector[99] = 8'h1;
test_receive_vector[100] = 8'h6;
test_receive_vector[101] = 8'h2;
test_receive_vector[102] = 8'h6;
test_receive_vector[103] = 8'h3;
test_receive_vector[104] = 8'h6;
test_receive_vector[105] = 8'h4;
test_receive_vector[106] = 8'h6;
test_receive_vector[107] = 8'h5;
test_receive_vector[108] = 8'h6;
test_receive_vector[109] = 8'h6;
test_receive_vector[110] = 8'h6;
test_receive_vector[111] = 8'h7;
test_receive_vector[112] = 8'h7;
test_receive_vector[113] = 8'h0;
test_receive_vector[114] = 8'h7;
test_receive_vector[115] = 8'h1;
test_receive_vector[116] = 8'h7;
test_receive_vector[117] = 8'h2;
test_receive_vector[118] = 8'h7;
test_receive_vector[119] = 8'h3;
test_receive_vector[120] = 8'h7;
test_receive_vector[121] = 8'h4;
test_receive_vector[122] = 8'h7;
test_receive_vector[123] = 8'h5;
test_receive_vector[124] = 8'h7;
test_receive_vector[125] = 8'h6;
test_receive_vector[126] = 8'h7;
test_receive_vector[127] = 8'h7;
test_receive_vector[128] = 8'h8;
test_receive_vector[129] = 8'h0;
test_receive_vector[130] = 8'h8;
test_receive_vector[131] = 8'h1;
test_receive_vector[132] = 8'h8;
test_receive_vector[133] = 8'h2;
test_receive_vector[134] = 8'h8;
test_receive_vector[135] = 8'h3;
test_receive_vector[136] = 8'h8;
test_receive_vector[137] = 8'h4;
test_receive_vector[138] = 8'h8;
test_receive_vector[139] = 8'h5;
test_receive_vector[140] = 8'h8;
test_receive_vector[141] = 8'h6;
test_receive_vector[142] = 8'h8;
test_receive_vector[143] = 8'h7;
test_receive_vector[144] = 8'h9;
test_receive_vector[145] = 8'h0;
test_receive_vector[146] = 8'h9;
test_receive_vector[147] = 8'h1;
test_receive_vector[148] = 8'h9;
test_receive_vector[149] = 8'h2;
test_receive_vector[150] = 8'h9;
test_receive_vector[151] = 8'h3;
test_receive_vector[152] = 8'h9;
test_receive_vector[153] = 8'h4;
test_receive_vector[154] = 8'h9;
test_receive_vector[155] = 8'h5;
test_receive_vector[156] = 8'h9;
test_receive_vector[157] = 8'h6;
test_receive_vector[158] = 8'h9;
test_receive_vector[159] = 8'h7;
test_receive_vector[160] = 8'ha;
test_receive_vector[161] = 8'h0;
test_receive_vector[162] = 8'ha;
test_receive_vector[163] = 8'h1;
test_receive_vector[164] = 8'ha;
test_receive_vector[165] = 8'h2;
test_receive_vector[166] = 8'ha;
test_receive_vector[167] = 8'h3;
test_receive_vector[168] = 8'ha;
test_receive_vector[169] = 8'h4;
test_receive_vector[170] = 8'ha;
test_receive_vector[171] = 8'h5;
test_receive_vector[172] = 8'ha;
test_receive_vector[173] = 8'h6;
test_receive_vector[174] = 8'ha;
test_receive_vector[175] = 8'h7;
test_receive_vector[176] = 8'hb;
test_receive_vector[177] = 8'h0;
test_receive_vector[178] = 8'hb;
test_receive_vector[179] = 8'h1;
test_receive_vector[180] = 8'hb;
test_receive_vector[181] = 8'h2;
test_receive_vector[182] = 8'hb;
test_receive_vector[183] = 8'h3;
test_receive_vector[184] = 8'hb;
test_receive_vector[185] = 8'h4;
test_receive_vector[186] = 8'hb;
test_receive_vector[187] = 8'h5;
test_receive_vector[188] = 8'hb;
test_receive_vector[189] = 8'h6;
test_receive_vector[190] = 8'hb;
test_receive_vector[191] = 8'h7;
test_receive_vector[192] = 8'hc;
test_receive_vector[193] = 8'h0;
test_receive_vector[194] = 8'hc;
test_receive_vector[195] = 8'h1;
test_receive_vector[196] = 8'hc;
test_receive_vector[197] = 8'h2;
test_receive_vector[198] = 8'hc;
test_receive_vector[199] = 8'h3;
test_receive_vector[200] = 8'hc;
test_receive_vector[201] = 8'h4;
test_receive_vector[202] = 8'hc;
test_receive_vector[203] = 8'h5;
test_receive_vector[204] = 8'hc;
test_receive_vector[205] = 8'h6;
test_receive_vector[206] = 8'hc;
test_receive_vector[207] = 8'h7;
test_receive_vector[208] = 8'hd;
test_receive_vector[209] = 8'h0;
test_receive_vector[210] = 8'hd;
test_receive_vector[211] = 8'h1;
test_receive_vector[212] = 8'hd;
test_receive_vector[213] = 8'h2;
test_receive_vector[214] = 8'hd;
test_receive_vector[215] = 8'h3;
test_receive_vector[216] = 8'hd;
test_receive_vector[217] = 8'h4;
test_receive_vector[218] = 8'hd;
test_receive_vector[219] = 8'h5;
test_receive_vector[220] = 8'hd;
test_receive_vector[221] = 8'h6;
test_receive_vector[222] = 8'hd;
test_receive_vector[223] = 8'h7;
test_receive_vector[224] = 8'he;
test_receive_vector[225] = 8'h0;
test_receive_vector[226] = 8'he;
test_receive_vector[227] = 8'h1;
test_receive_vector[228] = 8'he;
test_receive_vector[229] = 8'h2;
test_receive_vector[230] = 8'he;
test_receive_vector[231] = 8'h3;
test_receive_vector[232] = 8'he;
test_receive_vector[233] = 8'h4;
test_receive_vector[234] = 8'he;
test_receive_vector[235] = 8'h5;
test_receive_vector[236] = 8'he;
test_receive_vector[237] = 8'h6;
test_receive_vector[238] = 8'he;
test_receive_vector[239] = 8'h7;
test_receive_vector[240] = 8'hf;
test_receive_vector[241] = 8'h0;
test_receive_vector[242] = 8'hf;
test_receive_vector[243] = 8'h1;
test_receive_vector[244] = 8'hf;
test_receive_vector[245] = 8'h2;
test_receive_vector[246] = 8'hf;
test_receive_vector[247] = 8'h3;
test_receive_vector[248] = 8'hf;
test_receive_vector[249] = 8'h4;
test_receive_vector[250] = 8'hf;
test_receive_vector[251] = 8'h5;
test_receive_vector[252] = 8'hf;
test_receive_vector[253] = 8'h6;
test_receive_vector[254] = 8'hf;
test_receive_vector[255] = 8'h7;
test_receive_vector[256] = 8'h10;
test_receive_vector[257] = 8'h0;
test_receive_vector[258] = 8'h10;
test_receive_vector[259] = 8'h1;
test_receive_vector[260] = 8'h10;
test_receive_vector[261] = 8'h2;
test_receive_vector[262] = 8'h10;
test_receive_vector[263] = 8'h3;
test_receive_vector[264] = 8'h10;
test_receive_vector[265] = 8'h4;
test_receive_vector[266] = 8'h10;
test_receive_vector[267] = 8'h5;
test_receive_vector[268] = 8'h10;
test_receive_vector[269] = 8'h6;
test_receive_vector[270] = 8'h10;
test_receive_vector[271] = 8'h7;
test_receive_vector[272] = 8'h11;
test_receive_vector[273] = 8'h0;
test_receive_vector[274] = 8'h11;
test_receive_vector[275] = 8'h1;
test_receive_vector[276] = 8'h11;
test_receive_vector[277] = 8'h2;
test_receive_vector[278] = 8'h11;
test_receive_vector[279] = 8'h3;
test_receive_vector[280] = 8'h11;
test_receive_vector[281] = 8'h4;
test_receive_vector[282] = 8'h11;
test_receive_vector[283] = 8'h5;
test_receive_vector[284] = 8'h11;
test_receive_vector[285] = 8'h6;
test_receive_vector[286] = 8'h11;
test_receive_vector[287] = 8'h7;
test_receive_vector[288] = 8'h12;
test_receive_vector[289] = 8'h0;
test_receive_vector[290] = 8'h12;
test_receive_vector[291] = 8'h1;
test_receive_vector[292] = 8'h12;
test_receive_vector[293] = 8'h2;
test_receive_vector[294] = 8'h12;
test_receive_vector[295] = 8'h3;
test_receive_vector[296] = 8'h12;
test_receive_vector[297] = 8'h4;
test_receive_vector[298] = 8'h12;
test_receive_vector[299] = 8'h5;
test_receive_vector[300] = 8'h12;
test_receive_vector[301] = 8'h6;
test_receive_vector[302] = 8'h12;
test_receive_vector[303] = 8'h7;
test_receive_vector[304] = 8'h13;
test_receive_vector[305] = 8'h0;
test_receive_vector[306] = 8'h13;
test_receive_vector[307] = 8'h1;
test_receive_vector[308] = 8'h13;
test_receive_vector[309] = 8'h2;
test_receive_vector[310] = 8'h13;
test_receive_vector[311] = 8'h3;
test_receive_vector[312] = 8'h13;
test_receive_vector[313] = 8'h4;
test_receive_vector[314] = 8'h13;
test_receive_vector[315] = 8'h5;
test_receive_vector[316] = 8'h13;
test_receive_vector[317] = 8'h6;
test_receive_vector[318] = 8'h13;
test_receive_vector[319] = 8'h7;
test_receive_vector[320] = 8'h14;
test_receive_vector[321] = 8'h0;
test_receive_vector[322] = 8'h14;
test_receive_vector[323] = 8'h1;
test_receive_vector[324] = 8'h14;
test_receive_vector[325] = 8'h2;
test_receive_vector[326] = 8'h14;
test_receive_vector[327] = 8'h3;
test_receive_vector[328] = 8'h14;
test_receive_vector[329] = 8'h4;
test_receive_vector[330] = 8'h14;
test_receive_vector[331] = 8'h5;
test_receive_vector[332] = 8'h14;
test_receive_vector[333] = 8'h6;
test_receive_vector[334] = 8'h14;
test_receive_vector[335] = 8'h7;
test_receive_vector[336] = 8'h15;
test_receive_vector[337] = 8'h0;
test_receive_vector[338] = 8'h15;
test_receive_vector[339] = 8'h1;
test_receive_vector[340] = 8'h15;
test_receive_vector[341] = 8'h2;
test_receive_vector[342] = 8'h15;
test_receive_vector[343] = 8'h3;
test_receive_vector[344] = 8'h15;
test_receive_vector[345] = 8'h4;
test_receive_vector[346] = 8'h15;
test_receive_vector[347] = 8'h5;
test_receive_vector[348] = 8'h15;
test_receive_vector[349] = 8'h6;
test_receive_vector[350] = 8'h15;
test_receive_vector[351] = 8'h7;
test_receive_vector[352] = 8'h16;
test_receive_vector[353] = 8'h0;
test_receive_vector[354] = 8'h16;
test_receive_vector[355] = 8'h1;
test_receive_vector[356] = 8'h16;
test_receive_vector[357] = 8'h2;
test_receive_vector[358] = 8'h16;
test_receive_vector[359] = 8'h3;
test_receive_vector[360] = 8'h16;
test_receive_vector[361] = 8'h4;
test_receive_vector[362] = 8'h16;
test_receive_vector[363] = 8'h5;
test_receive_vector[364] = 8'h16;
test_receive_vector[365] = 8'h6;
test_receive_vector[366] = 8'h16;
test_receive_vector[367] = 8'h7;
test_receive_vector[368] = 8'h17;
test_receive_vector[369] = 8'h0;
test_receive_vector[370] = 8'h17;
test_receive_vector[371] = 8'h1;
test_receive_vector[372] = 8'h17;
test_receive_vector[373] = 8'h2;
test_receive_vector[374] = 8'h17;
test_receive_vector[375] = 8'h3;
test_receive_vector[376] = 8'h17;
test_receive_vector[377] = 8'h4;
test_receive_vector[378] = 8'h17;
test_receive_vector[379] = 8'h5;
test_receive_vector[380] = 8'h17;
test_receive_vector[381] = 8'h6;
test_receive_vector[382] = 8'h17;
test_receive_vector[383] = 8'h7;
end
// Outputs
wire tx;
wire [23:0] leds;
// Instantiate the Unit Under Test (UUT)
lights uut (
.clk(clk),
.rx(rx),
.tx(tx),
.leds(leds)
);
always #20 clk = ~clk;
// Transmission loop
initial begin
// Wait 100 ns for global reset to finish and a little longer for good measure.
#100;
#1234;
for (i=0; i<test_send_vector_len; i=i+1) begin
$display("Send i: %d val: %x", i, test_send_vector[i]);
xmit_byte(test_send_vector[i]);
if ((i+1) % 3 == 0) @ (test_step_complete) test_step_complete = 0; // Wait for module to echo result back to us
// Wait random time
random_delay = $random % 1000000; // Up to 1 ms
#(random_delay);
end
#1000000
if (write_complete_received == 0) $display("Test failed");
else $display("Test passed");
$stop;
end
// Receiver loop
always begin
for (j=0; j<test_receive_vector_len; j=j+1) begin
recv_byte(received_byte);
$display("Recv j: %d expect: %x val: %x", j, test_receive_vector[j], received_byte);
if (received_byte != test_receive_vector[j]) $stop;
if ((j+1) % 2 == 0) test_step_complete = 1;
end
write_complete_received = 1;
end
task xmit_byte();
input [7:0] b;
integer i;
begin
#8681 rx = 0; xmit = 1; // start bit
for (i=0;i<8;i = i+1) begin
#8681 rx = b[0]; xmit = 0; // 0
b = {1'b0, b[7:1]};
end
#8681 rx = 1; // stop bit
end
endtask
task recv_byte();
output [7:0] b;
integer i;
begin
b = 0;
@ (negedge tx); // Wait for start bit
recv = 1;
#4340; // Wait half a bit period to align sampling to middle of transition.
// 8 times, wait a bit period and then sample the value, shifting in from left to right.
for (i=0;i<8;i = i+1) begin
b = {1'b0, b[7:1]};
#8681 b[7] = tx; recv = 0;
end
#4340; // Wait another half a bit period to give the stop bit some time to occur.
end
endtask
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// dma interface
s_axis_s2mm_clk,
s_axis_s2mm_tvalid,
s_axis_s2mm_tdata,
s_axis_s2mm_tkeep,
s_axis_s2mm_tlast,
s_axis_s2mm_tready,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// delay clock
delay_clk,
// debug signals
adc_clk,
adc_mon_valid,
adc_mon_data);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// dma interface
input s_axis_s2mm_clk;
output s_axis_s2mm_tvalid;
output [63:0] s_axis_s2mm_tdata;
output [ 7:0] s_axis_s2mm_tkeep;
output s_axis_s2mm_tlast;
input s_axis_s2mm_tready;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// delay clock
input delay_clk;
// debug signals
output adc_clk;
output adc_mon_valid;
output [111:0] adc_mon_data;
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clocks & resets
wire delay_rst;
wire adc_rst;
wire dma_clk;
wire dma_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [47:0] adc_data_s;
wire adc_or_s;
wire adc_status_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire [63:0] adc_channel_data_s;
wire up_adc_pn_err_s;
wire up_adc_pn_oos_s;
wire up_adc_or_s;
wire [31:0] up_adc_channel_rdata_s;
wire up_adc_channel_ack_s;
wire dma_valid_s;
wire dma_last_s;
wire [63:0] dma_data_s;
wire dma_ready_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_status_s;
wire [31:0] dma_bw_s;
wire dma_start_s;
wire dma_stream_s;
wire [31:0] dma_count_s;
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign dma_clk = s_axis_s2mm_clk;
assign dma_ready_s = s_axis_s2mm_tready;
assign s_axis_s2mm_tvalid = dma_valid_s;
assign s_axis_s2mm_tdata = dma_data_s;
assign s_axis_s2mm_tlast = dma_last_s;
assign s_axis_s2mm_tkeep = 8'hff;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[ 63: 0] = adc_channel_data_s;
assign adc_mon_data[111: 64] = adc_data_s;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_s;
end
end
// main (device interface)
axi_ad9434_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_status (adc_status_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s));
// channel
axi_ad9434_channel i_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_dfmt_data (adc_channel_data_s),
.up_adc_pn_err (up_adc_pn_err_s),
.up_adc_pn_oos (up_adc_pn_oos_s),
.up_adc_or (up_adc_or_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_s),
.up_ack (up_adc_channel_ack_s));
// main (dma interface)
dma_core #(.DATA_WIDTH(64)) i_dma_core (
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_valid (dma_valid_s),
.dma_last (dma_last_s),
.dma_data (dma_data_s),
.dma_ready (dma_ready_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_valid (1'b1),
.adc_data (adc_channel_data_s),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_pn_err_s),
.adc_status_pn_oos (up_adc_pn_oos_s),
.adc_status_or (up_adc_or_s),
.adc_clk_ratio (32'd4),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),
.drp_wr (),
.drp_addr (),
.drp_wdata (),
.drp_rdata (16'd0),
.drp_ack_t (1'd0),
.dma_clk (dma_clk),
.dma_rst (dma_rst),
.dma_start (dma_start_s),
.dma_stream (dma_stream_s),
.dma_count (dma_count_s),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_status (dma_status_s),
.dma_bw (dma_bw_s),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
// up bus interface
up_axi #(
.PCORE_BASEADDR (C_BASEADDR),
.PCORE_HIGHADDR (C_HIGHADDR))
i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's 32x32 multiply for ASIC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// 32x32 multiply for ASIC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_amultp2_32x32.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2003/04/07 01:23:31 lampret
// Added another pipe stage to match gmult. One day second pipe in amult and gmult might be removed to get better performance.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`ifdef OR1200_ASIC_MULTP2_32X32
module PP_LOW ( ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG;
endmodule
module PP_MIDDLE ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
input INC;
input IND;
output PPBIT;
assign PPBIT = ~ (( ~ (INA & TWOPOS)) & ( ~ (INB & TWONEG)) & ( ~ (INC & ONEPOS)) & ( ~ (IND & ONENEG)));
endmodule
module PP_HIGH ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
module R_GATE ( INA, INB, INC, PPBIT );
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = ( ~ (INA & INB)) & INC;
endmodule
module DECODER ( INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG );
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~ ( ~ (INA & INB & ( ~ INC)));
assign TWONEG = ~ ( ~ (( ~ INA) & ( ~ INB) & INC));
assign ONEPOS = (( ~ INA) & INB & ( ~ INC)) | (( ~ INC) & ( ~ INB) & INA);
assign ONENEG = (INA & ( ~ INB) & INC) | (INC & INB & ( ~ INA));
endmodule
module BOOTHCODER_33_32 ( OPA, OPB, SUMMAND );
input [0:32] OPA;
input [0:31] OPB;
output [0:575] SUMMAND;
wire [0:32] INV_MULTIPLICAND;
wire [0:63] INT_MULTIPLIER;
wire LOGIC_ONE, LOGIC_ZERO;
assign LOGIC_ONE = 1;
assign LOGIC_ZERO = 0;
DECODER DEC_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) );
assign INV_MULTIPLICAND[0] = ~ OPA[0];
PP_LOW PPL_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[0]) );
R_GATE RGATE_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .PPBIT (SUMMAND[1]) );
assign INV_MULTIPLICAND[1] = ~ OPA[1];
PP_MIDDLE PPM_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[2]) );
assign INV_MULTIPLICAND[2] = ~ OPA[2];
PP_MIDDLE PPM_1 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[3]) );
assign INV_MULTIPLICAND[3] = ~ OPA[3];
PP_MIDDLE PPM_2 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[6]) );
assign INV_MULTIPLICAND[4] = ~ OPA[4];
PP_MIDDLE PPM_3 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[8]) );
assign INV_MULTIPLICAND[5] = ~ OPA[5];
PP_MIDDLE PPM_4 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[12]) );
assign INV_MULTIPLICAND[6] = ~ OPA[6];
PP_MIDDLE PPM_5 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[15]) );
assign INV_MULTIPLICAND[7] = ~ OPA[7];
PP_MIDDLE PPM_6 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[20]) );
assign INV_MULTIPLICAND[8] = ~ OPA[8];
PP_MIDDLE PPM_7 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[24]) );
assign INV_MULTIPLICAND[9] = ~ OPA[9];
PP_MIDDLE PPM_8 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[30]) );
assign INV_MULTIPLICAND[10] = ~ OPA[10];
PP_MIDDLE PPM_9 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[35]) );
assign INV_MULTIPLICAND[11] = ~ OPA[11];
PP_MIDDLE PPM_10 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[42]) );
assign INV_MULTIPLICAND[12] = ~ OPA[12];
PP_MIDDLE PPM_11 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[48]) );
assign INV_MULTIPLICAND[13] = ~ OPA[13];
PP_MIDDLE PPM_12 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[56]) );
assign INV_MULTIPLICAND[14] = ~ OPA[14];
PP_MIDDLE PPM_13 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[63]) );
assign INV_MULTIPLICAND[15] = ~ OPA[15];
PP_MIDDLE PPM_14 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[72]) );
assign INV_MULTIPLICAND[16] = ~ OPA[16];
PP_MIDDLE PPM_15 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[80]) );
assign INV_MULTIPLICAND[17] = ~ OPA[17];
PP_MIDDLE PPM_16 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[90]) );
assign INV_MULTIPLICAND[18] = ~ OPA[18];
PP_MIDDLE PPM_17 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[99]) );
assign INV_MULTIPLICAND[19] = ~ OPA[19];
PP_MIDDLE PPM_18 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[110]) );
assign INV_MULTIPLICAND[20] = ~ OPA[20];
PP_MIDDLE PPM_19 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[120]) );
assign INV_MULTIPLICAND[21] = ~ OPA[21];
PP_MIDDLE PPM_20 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[132]) );
assign INV_MULTIPLICAND[22] = ~ OPA[22];
PP_MIDDLE PPM_21 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[143]) );
assign INV_MULTIPLICAND[23] = ~ OPA[23];
PP_MIDDLE PPM_22 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[156]) );
assign INV_MULTIPLICAND[24] = ~ OPA[24];
PP_MIDDLE PPM_23 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[168]) );
assign INV_MULTIPLICAND[25] = ~ OPA[25];
PP_MIDDLE PPM_24 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[182]) );
assign INV_MULTIPLICAND[26] = ~ OPA[26];
PP_MIDDLE PPM_25 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[195]) );
assign INV_MULTIPLICAND[27] = ~ OPA[27];
PP_MIDDLE PPM_26 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[210]) );
assign INV_MULTIPLICAND[28] = ~ OPA[28];
PP_MIDDLE PPM_27 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[224]) );
assign INV_MULTIPLICAND[29] = ~ OPA[29];
PP_MIDDLE PPM_28 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[240]) );
assign INV_MULTIPLICAND[30] = ~ OPA[30];
PP_MIDDLE PPM_29 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[255]) );
assign INV_MULTIPLICAND[31] = ~ OPA[31];
PP_MIDDLE PPM_30 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[272]) );
assign INV_MULTIPLICAND[32] = ~ OPA[32];
PP_MIDDLE PPM_31 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[288]) );
PP_HIGH PPH_0 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[304]) );
assign SUMMAND[305] = 1;
DECODER DEC_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) );
PP_LOW PPL_1 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[4]) );
R_GATE RGATE_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .PPBIT (SUMMAND[5]) );
PP_MIDDLE PPM_32 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[7]) );
PP_MIDDLE PPM_33 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[9]) );
PP_MIDDLE PPM_34 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[13]) );
PP_MIDDLE PPM_35 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[16]) );
PP_MIDDLE PPM_36 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[21]) );
PP_MIDDLE PPM_37 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[25]) );
PP_MIDDLE PPM_38 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[31]) );
PP_MIDDLE PPM_39 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[36]) );
PP_MIDDLE PPM_40 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[43]) );
PP_MIDDLE PPM_41 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[49]) );
PP_MIDDLE PPM_42 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[57]) );
PP_MIDDLE PPM_43 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[64]) );
PP_MIDDLE PPM_44 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[73]) );
PP_MIDDLE PPM_45 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[81]) );
PP_MIDDLE PPM_46 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[91]) );
PP_MIDDLE PPM_47 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[100]) );
PP_MIDDLE PPM_48 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[111]) );
PP_MIDDLE PPM_49 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[121]) );
PP_MIDDLE PPM_50 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[133]) );
PP_MIDDLE PPM_51 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[144]) );
PP_MIDDLE PPM_52 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[157]) );
PP_MIDDLE PPM_53 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[169]) );
PP_MIDDLE PPM_54 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[183]) );
PP_MIDDLE PPM_55 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[196]) );
PP_MIDDLE PPM_56 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[211]) );
PP_MIDDLE PPM_57 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[225]) );
PP_MIDDLE PPM_58 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[241]) );
PP_MIDDLE PPM_59 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[256]) );
PP_MIDDLE PPM_60 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[273]) );
PP_MIDDLE PPM_61 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[289]) );
PP_MIDDLE PPM_62 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[306]) );
PP_MIDDLE PPM_63 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[321]) );
assign SUMMAND[322] = LOGIC_ONE;
PP_HIGH PPH_1 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[337]) );
DECODER DEC_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) );
PP_LOW PPL_2 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[10]) );
R_GATE RGATE_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .PPBIT (SUMMAND[11]) );
PP_MIDDLE PPM_64 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[14]) );
PP_MIDDLE PPM_65 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[17]) );
PP_MIDDLE PPM_66 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[22]) );
PP_MIDDLE PPM_67 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[26]) );
PP_MIDDLE PPM_68 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[32]) );
PP_MIDDLE PPM_69 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[37]) );
PP_MIDDLE PPM_70 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[44]) );
PP_MIDDLE PPM_71 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[50]) );
PP_MIDDLE PPM_72 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[58]) );
PP_MIDDLE PPM_73 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[65]) );
PP_MIDDLE PPM_74 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[74]) );
PP_MIDDLE PPM_75 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[82]) );
PP_MIDDLE PPM_76 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[92]) );
PP_MIDDLE PPM_77 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[101]) );
PP_MIDDLE PPM_78 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[112]) );
PP_MIDDLE PPM_79 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[122]) );
PP_MIDDLE PPM_80 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[134]) );
PP_MIDDLE PPM_81 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[145]) );
PP_MIDDLE PPM_82 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[158]) );
PP_MIDDLE PPM_83 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[170]) );
PP_MIDDLE PPM_84 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[184]) );
PP_MIDDLE PPM_85 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[197]) );
PP_MIDDLE PPM_86 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[212]) );
PP_MIDDLE PPM_87 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[226]) );
PP_MIDDLE PPM_88 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[242]) );
PP_MIDDLE PPM_89 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[257]) );
PP_MIDDLE PPM_90 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[274]) );
PP_MIDDLE PPM_91 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[290]) );
PP_MIDDLE PPM_92 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[307]) );
PP_MIDDLE PPM_93 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[323]) );
PP_MIDDLE PPM_94 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[338]) );
PP_MIDDLE PPM_95 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[352]) );
assign SUMMAND[353] = LOGIC_ONE;
PP_HIGH PPH_2 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[367]) );
DECODER DEC_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) );
PP_LOW PPL_3 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[18]) );
R_GATE RGATE_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .PPBIT (SUMMAND[19]) );
PP_MIDDLE PPM_96 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[23]) );
PP_MIDDLE PPM_97 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[27]) );
PP_MIDDLE PPM_98 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[33]) );
PP_MIDDLE PPM_99 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[38]) );
PP_MIDDLE PPM_100 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[45]) );
PP_MIDDLE PPM_101 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[51]) );
PP_MIDDLE PPM_102 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[59]) );
PP_MIDDLE PPM_103 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[66]) );
PP_MIDDLE PPM_104 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[75]) );
PP_MIDDLE PPM_105 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[83]) );
PP_MIDDLE PPM_106 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[93]) );
PP_MIDDLE PPM_107 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[102]) );
PP_MIDDLE PPM_108 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[113]) );
PP_MIDDLE PPM_109 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[123]) );
PP_MIDDLE PPM_110 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[135]) );
PP_MIDDLE PPM_111 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[146]) );
PP_MIDDLE PPM_112 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[159]) );
PP_MIDDLE PPM_113 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[171]) );
PP_MIDDLE PPM_114 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[185]) );
PP_MIDDLE PPM_115 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[198]) );
PP_MIDDLE PPM_116 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[213]) );
PP_MIDDLE PPM_117 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[227]) );
PP_MIDDLE PPM_118 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[243]) );
PP_MIDDLE PPM_119 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[258]) );
PP_MIDDLE PPM_120 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[275]) );
PP_MIDDLE PPM_121 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[291]) );
PP_MIDDLE PPM_122 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[308]) );
PP_MIDDLE PPM_123 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[324]) );
PP_MIDDLE PPM_124 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[339]) );
PP_MIDDLE PPM_125 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[354]) );
PP_MIDDLE PPM_126 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[368]) );
PP_MIDDLE PPM_127 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[381]) );
assign SUMMAND[382] = LOGIC_ONE;
PP_HIGH PPH_3 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[395]) );
DECODER DEC_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) );
PP_LOW PPL_4 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[28]) );
R_GATE RGATE_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .PPBIT (SUMMAND[29]) );
PP_MIDDLE PPM_128 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[34]) );
PP_MIDDLE PPM_129 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[39]) );
PP_MIDDLE PPM_130 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[46]) );
PP_MIDDLE PPM_131 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[52]) );
PP_MIDDLE PPM_132 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[60]) );
PP_MIDDLE PPM_133 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[67]) );
PP_MIDDLE PPM_134 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[76]) );
PP_MIDDLE PPM_135 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[84]) );
PP_MIDDLE PPM_136 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[94]) );
PP_MIDDLE PPM_137 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[103]) );
PP_MIDDLE PPM_138 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[114]) );
PP_MIDDLE PPM_139 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[124]) );
PP_MIDDLE PPM_140 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[136]) );
PP_MIDDLE PPM_141 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[147]) );
PP_MIDDLE PPM_142 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[160]) );
PP_MIDDLE PPM_143 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[172]) );
PP_MIDDLE PPM_144 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[186]) );
PP_MIDDLE PPM_145 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[199]) );
PP_MIDDLE PPM_146 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[214]) );
PP_MIDDLE PPM_147 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[228]) );
PP_MIDDLE PPM_148 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[244]) );
PP_MIDDLE PPM_149 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[259]) );
PP_MIDDLE PPM_150 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[276]) );
PP_MIDDLE PPM_151 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[292]) );
PP_MIDDLE PPM_152 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[309]) );
PP_MIDDLE PPM_153 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[325]) );
PP_MIDDLE PPM_154 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[340]) );
PP_MIDDLE PPM_155 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[355]) );
PP_MIDDLE PPM_156 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[369]) );
PP_MIDDLE PPM_157 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[383]) );
PP_MIDDLE PPM_158 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[396]) );
PP_MIDDLE PPM_159 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[408]) );
assign SUMMAND[409] = LOGIC_ONE;
PP_HIGH PPH_4 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[421]) );
DECODER DEC_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) );
PP_LOW PPL_5 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[40]) );
R_GATE RGATE_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .PPBIT (SUMMAND[41]) );
PP_MIDDLE PPM_160 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[47]) );
PP_MIDDLE PPM_161 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[53]) );
PP_MIDDLE PPM_162 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[61]) );
PP_MIDDLE PPM_163 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[68]) );
PP_MIDDLE PPM_164 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[77]) );
PP_MIDDLE PPM_165 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[85]) );
PP_MIDDLE PPM_166 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[95]) );
PP_MIDDLE PPM_167 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[104]) );
PP_MIDDLE PPM_168 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[115]) );
PP_MIDDLE PPM_169 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[125]) );
PP_MIDDLE PPM_170 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[137]) );
PP_MIDDLE PPM_171 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[148]) );
PP_MIDDLE PPM_172 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[161]) );
PP_MIDDLE PPM_173 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[173]) );
PP_MIDDLE PPM_174 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[187]) );
PP_MIDDLE PPM_175 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[200]) );
PP_MIDDLE PPM_176 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[215]) );
PP_MIDDLE PPM_177 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[229]) );
PP_MIDDLE PPM_178 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[245]) );
PP_MIDDLE PPM_179 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[260]) );
PP_MIDDLE PPM_180 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[277]) );
PP_MIDDLE PPM_181 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[293]) );
PP_MIDDLE PPM_182 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[310]) );
PP_MIDDLE PPM_183 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[326]) );
PP_MIDDLE PPM_184 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[341]) );
PP_MIDDLE PPM_185 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[356]) );
PP_MIDDLE PPM_186 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[370]) );
PP_MIDDLE PPM_187 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[384]) );
PP_MIDDLE PPM_188 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[397]) );
PP_MIDDLE PPM_189 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[410]) );
PP_MIDDLE PPM_190 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[422]) );
PP_MIDDLE PPM_191 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[433]) );
assign SUMMAND[434] = LOGIC_ONE;
PP_HIGH PPH_5 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[445]) );
DECODER DEC_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) );
PP_LOW PPL_6 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[54]) );
R_GATE RGATE_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .PPBIT (SUMMAND[55]) );
PP_MIDDLE PPM_192 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[62]) );
PP_MIDDLE PPM_193 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[69]) );
PP_MIDDLE PPM_194 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[78]) );
PP_MIDDLE PPM_195 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[86]) );
PP_MIDDLE PPM_196 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[96]) );
PP_MIDDLE PPM_197 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[105]) );
PP_MIDDLE PPM_198 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[116]) );
PP_MIDDLE PPM_199 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[126]) );
PP_MIDDLE PPM_200 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[138]) );
PP_MIDDLE PPM_201 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[149]) );
PP_MIDDLE PPM_202 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[162]) );
PP_MIDDLE PPM_203 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[174]) );
PP_MIDDLE PPM_204 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[188]) );
PP_MIDDLE PPM_205 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[201]) );
PP_MIDDLE PPM_206 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[216]) );
PP_MIDDLE PPM_207 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[230]) );
PP_MIDDLE PPM_208 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[246]) );
PP_MIDDLE PPM_209 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[261]) );
PP_MIDDLE PPM_210 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[278]) );
PP_MIDDLE PPM_211 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[294]) );
PP_MIDDLE PPM_212 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[311]) );
PP_MIDDLE PPM_213 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[327]) );
PP_MIDDLE PPM_214 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[342]) );
PP_MIDDLE PPM_215 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[357]) );
PP_MIDDLE PPM_216 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[371]) );
PP_MIDDLE PPM_217 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[385]) );
PP_MIDDLE PPM_218 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[398]) );
PP_MIDDLE PPM_219 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[411]) );
PP_MIDDLE PPM_220 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[423]) );
PP_MIDDLE PPM_221 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[435]) );
PP_MIDDLE PPM_222 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[446]) );
PP_MIDDLE PPM_223 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[456]) );
assign SUMMAND[457] = LOGIC_ONE;
PP_HIGH PPH_6 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[467]) );
DECODER DEC_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) );
PP_LOW PPL_7 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[70]) );
R_GATE RGATE_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .PPBIT (SUMMAND[71]) );
PP_MIDDLE PPM_224 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[79]) );
PP_MIDDLE PPM_225 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[87]) );
PP_MIDDLE PPM_226 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[97]) );
PP_MIDDLE PPM_227 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[106]) );
PP_MIDDLE PPM_228 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[117]) );
PP_MIDDLE PPM_229 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[127]) );
PP_MIDDLE PPM_230 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[139]) );
PP_MIDDLE PPM_231 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[150]) );
PP_MIDDLE PPM_232 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[163]) );
PP_MIDDLE PPM_233 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[175]) );
PP_MIDDLE PPM_234 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[189]) );
PP_MIDDLE PPM_235 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[202]) );
PP_MIDDLE PPM_236 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[217]) );
PP_MIDDLE PPM_237 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[231]) );
PP_MIDDLE PPM_238 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[247]) );
PP_MIDDLE PPM_239 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[262]) );
PP_MIDDLE PPM_240 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[279]) );
PP_MIDDLE PPM_241 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[295]) );
PP_MIDDLE PPM_242 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[312]) );
PP_MIDDLE PPM_243 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[328]) );
PP_MIDDLE PPM_244 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[343]) );
PP_MIDDLE PPM_245 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[358]) );
PP_MIDDLE PPM_246 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[372]) );
PP_MIDDLE PPM_247 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[386]) );
PP_MIDDLE PPM_248 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[399]) );
PP_MIDDLE PPM_249 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[412]) );
PP_MIDDLE PPM_250 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[424]) );
PP_MIDDLE PPM_251 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[436]) );
PP_MIDDLE PPM_252 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[447]) );
PP_MIDDLE PPM_253 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[458]) );
PP_MIDDLE PPM_254 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[468]) );
PP_MIDDLE PPM_255 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[477]) );
assign SUMMAND[478] = LOGIC_ONE;
PP_HIGH PPH_7 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[487]) );
DECODER DEC_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) );
PP_LOW PPL_8 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[88]) );
R_GATE RGATE_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .PPBIT (SUMMAND[89]) );
PP_MIDDLE PPM_256 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[98]) );
PP_MIDDLE PPM_257 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[107]) );
PP_MIDDLE PPM_258 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[118]) );
PP_MIDDLE PPM_259 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[128]) );
PP_MIDDLE PPM_260 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[140]) );
PP_MIDDLE PPM_261 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[151]) );
PP_MIDDLE PPM_262 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[164]) );
PP_MIDDLE PPM_263 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[176]) );
PP_MIDDLE PPM_264 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[190]) );
PP_MIDDLE PPM_265 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[203]) );
PP_MIDDLE PPM_266 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[218]) );
PP_MIDDLE PPM_267 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[232]) );
PP_MIDDLE PPM_268 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[248]) );
PP_MIDDLE PPM_269 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[263]) );
PP_MIDDLE PPM_270 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[280]) );
PP_MIDDLE PPM_271 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[296]) );
PP_MIDDLE PPM_272 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[313]) );
PP_MIDDLE PPM_273 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[329]) );
PP_MIDDLE PPM_274 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[344]) );
PP_MIDDLE PPM_275 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[359]) );
PP_MIDDLE PPM_276 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[373]) );
PP_MIDDLE PPM_277 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[387]) );
PP_MIDDLE PPM_278 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[400]) );
PP_MIDDLE PPM_279 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[413]) );
PP_MIDDLE PPM_280 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[425]) );
PP_MIDDLE PPM_281 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[437]) );
PP_MIDDLE PPM_282 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[448]) );
PP_MIDDLE PPM_283 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[459]) );
PP_MIDDLE PPM_284 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[469]) );
PP_MIDDLE PPM_285 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[479]) );
PP_MIDDLE PPM_286 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[488]) );
PP_MIDDLE PPM_287 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[496]) );
assign SUMMAND[497] = LOGIC_ONE;
PP_HIGH PPH_8 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[505]) );
DECODER DEC_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) );
PP_LOW PPL_9 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[108]) );
R_GATE RGATE_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .PPBIT (SUMMAND[109]) );
PP_MIDDLE PPM_288 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[119]) );
PP_MIDDLE PPM_289 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[129]) );
PP_MIDDLE PPM_290 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[141]) );
PP_MIDDLE PPM_291 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[152]) );
PP_MIDDLE PPM_292 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[165]) );
PP_MIDDLE PPM_293 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[177]) );
PP_MIDDLE PPM_294 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[191]) );
PP_MIDDLE PPM_295 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[204]) );
PP_MIDDLE PPM_296 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[219]) );
PP_MIDDLE PPM_297 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[233]) );
PP_MIDDLE PPM_298 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[249]) );
PP_MIDDLE PPM_299 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[264]) );
PP_MIDDLE PPM_300 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[281]) );
PP_MIDDLE PPM_301 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[297]) );
PP_MIDDLE PPM_302 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[314]) );
PP_MIDDLE PPM_303 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[330]) );
PP_MIDDLE PPM_304 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[345]) );
PP_MIDDLE PPM_305 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[360]) );
PP_MIDDLE PPM_306 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[374]) );
PP_MIDDLE PPM_307 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[388]) );
PP_MIDDLE PPM_308 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[401]) );
PP_MIDDLE PPM_309 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[414]) );
PP_MIDDLE PPM_310 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[426]) );
PP_MIDDLE PPM_311 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[438]) );
PP_MIDDLE PPM_312 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[449]) );
PP_MIDDLE PPM_313 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[460]) );
PP_MIDDLE PPM_314 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[470]) );
PP_MIDDLE PPM_315 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[480]) );
PP_MIDDLE PPM_316 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[489]) );
PP_MIDDLE PPM_317 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[498]) );
PP_MIDDLE PPM_318 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[506]) );
PP_MIDDLE PPM_319 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[513]) );
assign SUMMAND[514] = LOGIC_ONE;
PP_HIGH PPH_9 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[521]) );
DECODER DEC_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) );
PP_LOW PPL_10 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[130]) );
R_GATE RGATE_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .PPBIT (SUMMAND[131]) );
PP_MIDDLE PPM_320 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[142]) );
PP_MIDDLE PPM_321 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[153]) );
PP_MIDDLE PPM_322 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[166]) );
PP_MIDDLE PPM_323 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[178]) );
PP_MIDDLE PPM_324 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[192]) );
PP_MIDDLE PPM_325 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[205]) );
PP_MIDDLE PPM_326 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[220]) );
PP_MIDDLE PPM_327 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[234]) );
PP_MIDDLE PPM_328 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[250]) );
PP_MIDDLE PPM_329 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[265]) );
PP_MIDDLE PPM_330 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[282]) );
PP_MIDDLE PPM_331 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[298]) );
PP_MIDDLE PPM_332 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[315]) );
PP_MIDDLE PPM_333 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[331]) );
PP_MIDDLE PPM_334 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[346]) );
PP_MIDDLE PPM_335 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[361]) );
PP_MIDDLE PPM_336 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[375]) );
PP_MIDDLE PPM_337 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[389]) );
PP_MIDDLE PPM_338 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[402]) );
PP_MIDDLE PPM_339 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[415]) );
PP_MIDDLE PPM_340 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[427]) );
PP_MIDDLE PPM_341 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[439]) );
PP_MIDDLE PPM_342 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[450]) );
PP_MIDDLE PPM_343 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[461]) );
PP_MIDDLE PPM_344 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[471]) );
PP_MIDDLE PPM_345 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[481]) );
PP_MIDDLE PPM_346 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[490]) );
PP_MIDDLE PPM_347 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[499]) );
PP_MIDDLE PPM_348 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[507]) );
PP_MIDDLE PPM_349 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[515]) );
PP_MIDDLE PPM_350 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[522]) );
PP_MIDDLE PPM_351 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[528]) );
assign SUMMAND[529] = LOGIC_ONE;
PP_HIGH PPH_10 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[535]) );
DECODER DEC_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) );
PP_LOW PPL_11 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[154]) );
R_GATE RGATE_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .PPBIT (SUMMAND[155]) );
PP_MIDDLE PPM_352 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[167]) );
PP_MIDDLE PPM_353 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[179]) );
PP_MIDDLE PPM_354 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[193]) );
PP_MIDDLE PPM_355 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[206]) );
PP_MIDDLE PPM_356 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[221]) );
PP_MIDDLE PPM_357 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[235]) );
PP_MIDDLE PPM_358 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[251]) );
PP_MIDDLE PPM_359 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[266]) );
PP_MIDDLE PPM_360 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[283]) );
PP_MIDDLE PPM_361 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[299]) );
PP_MIDDLE PPM_362 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[316]) );
PP_MIDDLE PPM_363 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[332]) );
PP_MIDDLE PPM_364 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[347]) );
PP_MIDDLE PPM_365 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[362]) );
PP_MIDDLE PPM_366 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[376]) );
PP_MIDDLE PPM_367 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[390]) );
PP_MIDDLE PPM_368 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[403]) );
PP_MIDDLE PPM_369 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[416]) );
PP_MIDDLE PPM_370 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[428]) );
PP_MIDDLE PPM_371 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[440]) );
PP_MIDDLE PPM_372 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[451]) );
PP_MIDDLE PPM_373 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[462]) );
PP_MIDDLE PPM_374 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[472]) );
PP_MIDDLE PPM_375 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[482]) );
PP_MIDDLE PPM_376 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[491]) );
PP_MIDDLE PPM_377 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[500]) );
PP_MIDDLE PPM_378 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[508]) );
PP_MIDDLE PPM_379 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[516]) );
PP_MIDDLE PPM_380 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[523]) );
PP_MIDDLE PPM_381 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[530]) );
PP_MIDDLE PPM_382 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[536]) );
PP_MIDDLE PPM_383 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[541]) );
assign SUMMAND[542] = LOGIC_ONE;
PP_HIGH PPH_11 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[547]) );
DECODER DEC_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) );
PP_LOW PPL_12 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[180]) );
R_GATE RGATE_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .PPBIT (SUMMAND[181]) );
PP_MIDDLE PPM_384 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[194]) );
PP_MIDDLE PPM_385 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[207]) );
PP_MIDDLE PPM_386 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[222]) );
PP_MIDDLE PPM_387 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[236]) );
PP_MIDDLE PPM_388 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[252]) );
PP_MIDDLE PPM_389 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[267]) );
PP_MIDDLE PPM_390 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[284]) );
PP_MIDDLE PPM_391 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[300]) );
PP_MIDDLE PPM_392 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[317]) );
PP_MIDDLE PPM_393 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[333]) );
PP_MIDDLE PPM_394 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[348]) );
PP_MIDDLE PPM_395 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[363]) );
PP_MIDDLE PPM_396 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[377]) );
PP_MIDDLE PPM_397 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[391]) );
PP_MIDDLE PPM_398 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[404]) );
PP_MIDDLE PPM_399 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[417]) );
PP_MIDDLE PPM_400 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[429]) );
PP_MIDDLE PPM_401 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[441]) );
PP_MIDDLE PPM_402 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[452]) );
PP_MIDDLE PPM_403 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[463]) );
PP_MIDDLE PPM_404 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[473]) );
PP_MIDDLE PPM_405 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[483]) );
PP_MIDDLE PPM_406 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[492]) );
PP_MIDDLE PPM_407 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[501]) );
PP_MIDDLE PPM_408 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[509]) );
PP_MIDDLE PPM_409 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[517]) );
PP_MIDDLE PPM_410 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[524]) );
PP_MIDDLE PPM_411 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[531]) );
PP_MIDDLE PPM_412 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[537]) );
PP_MIDDLE PPM_413 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[543]) );
PP_MIDDLE PPM_414 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[548]) );
PP_MIDDLE PPM_415 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[552]) );
assign SUMMAND[553] = LOGIC_ONE;
PP_HIGH PPH_12 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[557]) );
DECODER DEC_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) );
PP_LOW PPL_13 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[208]) );
R_GATE RGATE_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .PPBIT (SUMMAND[209]) );
PP_MIDDLE PPM_416 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[223]) );
PP_MIDDLE PPM_417 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[237]) );
PP_MIDDLE PPM_418 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[253]) );
PP_MIDDLE PPM_419 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[268]) );
PP_MIDDLE PPM_420 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[285]) );
PP_MIDDLE PPM_421 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[301]) );
PP_MIDDLE PPM_422 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[318]) );
PP_MIDDLE PPM_423 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[334]) );
PP_MIDDLE PPM_424 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[349]) );
PP_MIDDLE PPM_425 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[364]) );
PP_MIDDLE PPM_426 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[378]) );
PP_MIDDLE PPM_427 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[392]) );
PP_MIDDLE PPM_428 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[405]) );
PP_MIDDLE PPM_429 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[418]) );
PP_MIDDLE PPM_430 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[430]) );
PP_MIDDLE PPM_431 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[442]) );
PP_MIDDLE PPM_432 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[453]) );
PP_MIDDLE PPM_433 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[464]) );
PP_MIDDLE PPM_434 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[474]) );
PP_MIDDLE PPM_435 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[484]) );
PP_MIDDLE PPM_436 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[493]) );
PP_MIDDLE PPM_437 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[502]) );
PP_MIDDLE PPM_438 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[510]) );
PP_MIDDLE PPM_439 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[518]) );
PP_MIDDLE PPM_440 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[525]) );
PP_MIDDLE PPM_441 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[532]) );
PP_MIDDLE PPM_442 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[538]) );
PP_MIDDLE PPM_443 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[544]) );
PP_MIDDLE PPM_444 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[549]) );
PP_MIDDLE PPM_445 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[554]) );
PP_MIDDLE PPM_446 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[558]) );
PP_MIDDLE PPM_447 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[561]) );
assign SUMMAND[562] = LOGIC_ONE;
PP_HIGH PPH_13 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[565]) );
DECODER DEC_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) );
PP_LOW PPL_14 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[238]) );
R_GATE RGATE_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .PPBIT (SUMMAND[239]) );
PP_MIDDLE PPM_448 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[254]) );
PP_MIDDLE PPM_449 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[269]) );
PP_MIDDLE PPM_450 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[286]) );
PP_MIDDLE PPM_451 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[302]) );
PP_MIDDLE PPM_452 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[319]) );
PP_MIDDLE PPM_453 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[335]) );
PP_MIDDLE PPM_454 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[350]) );
PP_MIDDLE PPM_455 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[365]) );
PP_MIDDLE PPM_456 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[379]) );
PP_MIDDLE PPM_457 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[393]) );
PP_MIDDLE PPM_458 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[406]) );
PP_MIDDLE PPM_459 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[419]) );
PP_MIDDLE PPM_460 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[431]) );
PP_MIDDLE PPM_461 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[443]) );
PP_MIDDLE PPM_462 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[454]) );
PP_MIDDLE PPM_463 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[465]) );
PP_MIDDLE PPM_464 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[475]) );
PP_MIDDLE PPM_465 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[485]) );
PP_MIDDLE PPM_466 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[494]) );
PP_MIDDLE PPM_467 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[503]) );
PP_MIDDLE PPM_468 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[511]) );
PP_MIDDLE PPM_469 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[519]) );
PP_MIDDLE PPM_470 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[526]) );
PP_MIDDLE PPM_471 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[533]) );
PP_MIDDLE PPM_472 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[539]) );
PP_MIDDLE PPM_473 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[545]) );
PP_MIDDLE PPM_474 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[550]) );
PP_MIDDLE PPM_475 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[555]) );
PP_MIDDLE PPM_476 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[559]) );
PP_MIDDLE PPM_477 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[563]) );
PP_MIDDLE PPM_478 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[566]) );
PP_MIDDLE PPM_479 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[568]) );
assign SUMMAND[569] = LOGIC_ONE;
PP_HIGH PPH_14 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[571]) );
DECODER DEC_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) );
PP_LOW PPL_15 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[270]) );
R_GATE RGATE_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .PPBIT (SUMMAND[271]) );
PP_MIDDLE PPM_480 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[287]) );
PP_MIDDLE PPM_481 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[303]) );
PP_MIDDLE PPM_482 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[320]) );
PP_MIDDLE PPM_483 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[336]) );
PP_MIDDLE PPM_484 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[351]) );
PP_MIDDLE PPM_485 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[366]) );
PP_MIDDLE PPM_486 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[380]) );
PP_MIDDLE PPM_487 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[394]) );
PP_MIDDLE PPM_488 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[407]) );
PP_MIDDLE PPM_489 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[420]) );
PP_MIDDLE PPM_490 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[432]) );
PP_MIDDLE PPM_491 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[444]) );
PP_MIDDLE PPM_492 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[455]) );
PP_MIDDLE PPM_493 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[466]) );
PP_MIDDLE PPM_494 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[476]) );
PP_MIDDLE PPM_495 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[486]) );
PP_MIDDLE PPM_496 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[495]) );
PP_MIDDLE PPM_497 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[504]) );
PP_MIDDLE PPM_498 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[512]) );
PP_MIDDLE PPM_499 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[520]) );
PP_MIDDLE PPM_500 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[527]) );
PP_MIDDLE PPM_501 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[534]) );
PP_MIDDLE PPM_502 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[540]) );
PP_MIDDLE PPM_503 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[546]) );
PP_MIDDLE PPM_504 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[551]) );
PP_MIDDLE PPM_505 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[556]) );
PP_MIDDLE PPM_506 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[560]) );
PP_MIDDLE PPM_507 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[564]) );
PP_MIDDLE PPM_508 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[567]) );
PP_MIDDLE PPM_509 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[570]) );
PP_MIDDLE PPM_510 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[572]) );
PP_MIDDLE PPM_511 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[573]) );
assign SUMMAND[574] = LOGIC_ONE;
PP_HIGH PPH_15 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[575]) );
endmodule
module FULL_ADDER ( DATA_A, DATA_B, DATA_C, SAVE, CARRY );
input DATA_A;
input DATA_B;
input DATA_C;
output SAVE;
output CARRY;
wire TMP;
assign TMP = DATA_A ^ DATA_B;
assign SAVE = TMP ^ DATA_C;
assign CARRY = ~ (( ~ (TMP & DATA_C)) & ( ~ (DATA_A & DATA_B)));
endmodule
module HALF_ADDER ( DATA_A, DATA_B, SAVE, CARRY );
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
module FLIPFLOP ( DIN, RST, CLK, DOUT );
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @ ( posedge RST or posedge CLK ) begin
if (RST)
DOUT_reg <= 1'b0;
else
DOUT_reg <= #1 DIN;
end
assign DOUT = DOUT_reg;
endmodule
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM );
input [0:575] SUMMAND;
input RST;
input CLK;
output [0:62] CARRY;
output [0:63] SUM;
wire [0:7] LATCHED_PP;
wire [0:523] INT_CARRY;
wire [0:669] INT_SUM;
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SAVE (INT_SUM[0]) , .CARRY (INT_CARRY[0]) );
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[0]) );
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[0]) );
assign INT_SUM[1] = SUMMAND[2];
assign CARRY[1] = 0;
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[1]) );
FULL_ADDER FA_0 (.DATA_A (SUMMAND[3]) , .DATA_B (SUMMAND[4]) , .DATA_C (SUMMAND[5]) , .SAVE (INT_SUM[2]) , .CARRY (INT_CARRY[1]) );
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[2]) );
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[2]) );
HALF_ADDER HA_1 (.DATA_A (SUMMAND[6]) , .DATA_B (SUMMAND[7]) , .SAVE (INT_SUM[3]) , .CARRY (INT_CARRY[2]) );
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[3]) );
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[3]) );
FULL_ADDER FA_1 (.DATA_A (SUMMAND[8]) , .DATA_B (SUMMAND[9]) , .DATA_C (SUMMAND[10]) , .SAVE (INT_SUM[4]) , .CARRY (INT_CARRY[4]) );
assign INT_SUM[5] = SUMMAND[11];
HALF_ADDER HA_2 (.DATA_A (INT_SUM[4]) , .DATA_B (INT_SUM[5]) , .SAVE (INT_SUM[6]) , .CARRY (INT_CARRY[3]) );
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[4]) );
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[4]) );
FULL_ADDER FA_2 (.DATA_A (SUMMAND[12]) , .DATA_B (SUMMAND[13]) , .DATA_C (SUMMAND[14]) , .SAVE (INT_SUM[7]) , .CARRY (INT_CARRY[6]) );
HALF_ADDER HA_3 (.DATA_A (INT_SUM[7]) , .DATA_B (INT_CARRY[4]) , .SAVE (INT_SUM[8]) , .CARRY (INT_CARRY[5]) );
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[5]) );
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[5]) );
FULL_ADDER FA_3 (.DATA_A (SUMMAND[15]) , .DATA_B (SUMMAND[16]) , .DATA_C (SUMMAND[17]) , .SAVE (INT_SUM[9]) , .CARRY (INT_CARRY[8]) );
HALF_ADDER HA_4 (.DATA_A (SUMMAND[18]) , .DATA_B (SUMMAND[19]) , .SAVE (INT_SUM[10]) , .CARRY (INT_CARRY[9]) );
FULL_ADDER FA_4 (.DATA_A (INT_SUM[9]) , .DATA_B (INT_SUM[10]) , .DATA_C (INT_CARRY[6]) , .SAVE (INT_SUM[11]) , .CARRY (INT_CARRY[7]) );
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[6]) );
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[6]) );
FULL_ADDER FA_5 (.DATA_A (SUMMAND[20]) , .DATA_B (SUMMAND[21]) , .DATA_C (SUMMAND[22]) , .SAVE (INT_SUM[12]) , .CARRY (INT_CARRY[11]) );
assign INT_SUM[13] = SUMMAND[23];
FULL_ADDER FA_6 (.DATA_A (INT_SUM[12]) , .DATA_B (INT_SUM[13]) , .DATA_C (INT_CARRY[8]) , .SAVE (INT_SUM[14]) , .CARRY (INT_CARRY[12]) );
assign INT_SUM[15] = INT_CARRY[9];
HALF_ADDER HA_5 (.DATA_A (INT_SUM[14]) , .DATA_B (INT_SUM[15]) , .SAVE (INT_SUM[16]) , .CARRY (INT_CARRY[10]) );
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[7]) );
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[7]) );
FULL_ADDER FA_7 (.DATA_A (SUMMAND[24]) , .DATA_B (SUMMAND[25]) , .DATA_C (SUMMAND[26]) , .SAVE (INT_SUM[17]) , .CARRY (INT_CARRY[14]) );
FULL_ADDER FA_8 (.DATA_A (SUMMAND[27]) , .DATA_B (SUMMAND[28]) , .DATA_C (SUMMAND[29]) , .SAVE (INT_SUM[18]) , .CARRY (INT_CARRY[15]) );
FULL_ADDER FA_9 (.DATA_A (INT_SUM[17]) , .DATA_B (INT_SUM[18]) , .DATA_C (INT_CARRY[11]) , .SAVE (INT_SUM[19]) , .CARRY (INT_CARRY[16]) );
HALF_ADDER HA_6 (.DATA_A (INT_SUM[19]) , .DATA_B (INT_CARRY[12]) , .SAVE (INT_SUM[20]) , .CARRY (INT_CARRY[13]) );
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[8]) );
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[8]) );
FULL_ADDER FA_10 (.DATA_A (SUMMAND[30]) , .DATA_B (SUMMAND[31]) , .DATA_C (SUMMAND[32]) , .SAVE (INT_SUM[21]) , .CARRY (INT_CARRY[18]) );
HALF_ADDER HA_7 (.DATA_A (SUMMAND[33]) , .DATA_B (SUMMAND[34]) , .SAVE (INT_SUM[22]) , .CARRY (INT_CARRY[19]) );
FULL_ADDER FA_11 (.DATA_A (INT_SUM[21]) , .DATA_B (INT_SUM[22]) , .DATA_C (INT_CARRY[14]) , .SAVE (INT_SUM[23]) , .CARRY (INT_CARRY[20]) );
assign INT_SUM[24] = INT_CARRY[15];
FULL_ADDER FA_12 (.DATA_A (INT_SUM[23]) , .DATA_B (INT_SUM[24]) , .DATA_C (INT_CARRY[16]) , .SAVE (INT_SUM[25]) , .CARRY (INT_CARRY[17]) );
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[9]) );
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[9]) );
FULL_ADDER FA_13 (.DATA_A (SUMMAND[35]) , .DATA_B (SUMMAND[36]) , .DATA_C (SUMMAND[37]) , .SAVE (INT_SUM[26]) , .CARRY (INT_CARRY[22]) );
FULL_ADDER FA_14 (.DATA_A (SUMMAND[38]) , .DATA_B (SUMMAND[39]) , .DATA_C (SUMMAND[40]) , .SAVE (INT_SUM[27]) , .CARRY (INT_CARRY[23]) );
assign INT_SUM[28] = SUMMAND[41];
FULL_ADDER FA_15 (.DATA_A (INT_SUM[26]) , .DATA_B (INT_SUM[27]) , .DATA_C (INT_SUM[28]) , .SAVE (INT_SUM[29]) , .CARRY (INT_CARRY[24]) );
HALF_ADDER HA_8 (.DATA_A (INT_CARRY[18]) , .DATA_B (INT_CARRY[19]) , .SAVE (INT_SUM[30]) , .CARRY (INT_CARRY[25]) );
FULL_ADDER FA_16 (.DATA_A (INT_SUM[29]) , .DATA_B (INT_SUM[30]) , .DATA_C (INT_CARRY[20]) , .SAVE (INT_SUM[31]) , .CARRY (INT_CARRY[21]) );
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[10]) );
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[10]) );
FULL_ADDER FA_17 (.DATA_A (SUMMAND[42]) , .DATA_B (SUMMAND[43]) , .DATA_C (SUMMAND[44]) , .SAVE (INT_SUM[32]) , .CARRY (INT_CARRY[27]) );
FULL_ADDER FA_18 (.DATA_A (SUMMAND[45]) , .DATA_B (SUMMAND[46]) , .DATA_C (SUMMAND[47]) , .SAVE (INT_SUM[33]) , .CARRY (INT_CARRY[28]) );
FULL_ADDER FA_19 (.DATA_A (INT_SUM[32]) , .DATA_B (INT_SUM[33]) , .DATA_C (INT_CARRY[22]) , .SAVE (INT_SUM[34]) , .CARRY (INT_CARRY[29]) );
assign INT_SUM[35] = INT_CARRY[23];
FULL_ADDER FA_20 (.DATA_A (INT_SUM[34]) , .DATA_B (INT_SUM[35]) , .DATA_C (INT_CARRY[24]) , .SAVE (INT_SUM[36]) , .CARRY (INT_CARRY[30]) );
assign INT_SUM[37] = INT_CARRY[25];
HALF_ADDER HA_9 (.DATA_A (INT_SUM[36]) , .DATA_B (INT_SUM[37]) , .SAVE (INT_SUM[38]) , .CARRY (INT_CARRY[26]) );
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[11]) );
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[11]) );
FULL_ADDER FA_21 (.DATA_A (SUMMAND[48]) , .DATA_B (SUMMAND[49]) , .DATA_C (SUMMAND[50]) , .SAVE (INT_SUM[39]) , .CARRY (INT_CARRY[32]) );
FULL_ADDER FA_22 (.DATA_A (SUMMAND[51]) , .DATA_B (SUMMAND[52]) , .DATA_C (SUMMAND[53]) , .SAVE (INT_SUM[40]) , .CARRY (INT_CARRY[33]) );
assign INT_SUM[41] = SUMMAND[54];
assign INT_SUM[42] = SUMMAND[55];
FULL_ADDER FA_23 (.DATA_A (INT_SUM[39]) , .DATA_B (INT_SUM[40]) , .DATA_C (INT_SUM[41]) , .SAVE (INT_SUM[43]) , .CARRY (INT_CARRY[34]) );
FULL_ADDER FA_24 (.DATA_A (INT_SUM[42]) , .DATA_B (INT_CARRY[27]) , .DATA_C (INT_CARRY[28]) , .SAVE (INT_SUM[44]) , .CARRY (INT_CARRY[35]) );
FULL_ADDER FA_25 (.DATA_A (INT_SUM[43]) , .DATA_B (INT_SUM[44]) , .DATA_C (INT_CARRY[29]) , .SAVE (INT_SUM[45]) , .CARRY (INT_CARRY[36]) );
HALF_ADDER HA_10 (.DATA_A (INT_SUM[45]) , .DATA_B (INT_CARRY[30]) , .SAVE (INT_SUM[46]) , .CARRY (INT_CARRY[31]) );
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[12]) );
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[12]) );
FULL_ADDER FA_26 (.DATA_A (SUMMAND[56]) , .DATA_B (SUMMAND[57]) , .DATA_C (SUMMAND[58]) , .SAVE (INT_SUM[47]) , .CARRY (INT_CARRY[38]) );
FULL_ADDER FA_27 (.DATA_A (SUMMAND[59]) , .DATA_B (SUMMAND[60]) , .DATA_C (SUMMAND[61]) , .SAVE (INT_SUM[48]) , .CARRY (INT_CARRY[39]) );
assign INT_SUM[49] = SUMMAND[62];
FULL_ADDER FA_28 (.DATA_A (INT_SUM[47]) , .DATA_B (INT_SUM[48]) , .DATA_C (INT_SUM[49]) , .SAVE (INT_SUM[50]) , .CARRY (INT_CARRY[40]) );
HALF_ADDER HA_11 (.DATA_A (INT_CARRY[32]) , .DATA_B (INT_CARRY[33]) , .SAVE (INT_SUM[51]) , .CARRY (INT_CARRY[41]) );
FULL_ADDER FA_29 (.DATA_A (INT_SUM[50]) , .DATA_B (INT_SUM[51]) , .DATA_C (INT_CARRY[34]) , .SAVE (INT_SUM[52]) , .CARRY (INT_CARRY[42]) );
assign INT_SUM[53] = INT_CARRY[35];
FULL_ADDER FA_30 (.DATA_A (INT_SUM[52]) , .DATA_B (INT_SUM[53]) , .DATA_C (INT_CARRY[36]) , .SAVE (INT_SUM[54]) , .CARRY (INT_CARRY[37]) );
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[13]) );
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[13]) );
FULL_ADDER FA_31 (.DATA_A (SUMMAND[63]) , .DATA_B (SUMMAND[64]) , .DATA_C (SUMMAND[65]) , .SAVE (INT_SUM[55]) , .CARRY (INT_CARRY[44]) );
FULL_ADDER FA_32 (.DATA_A (SUMMAND[66]) , .DATA_B (SUMMAND[67]) , .DATA_C (SUMMAND[68]) , .SAVE (INT_SUM[56]) , .CARRY (INT_CARRY[45]) );
FULL_ADDER FA_33 (.DATA_A (SUMMAND[69]) , .DATA_B (SUMMAND[70]) , .DATA_C (SUMMAND[71]) , .SAVE (INT_SUM[57]) , .CARRY (INT_CARRY[46]) );
FULL_ADDER FA_34 (.DATA_A (INT_SUM[55]) , .DATA_B (INT_SUM[56]) , .DATA_C (INT_SUM[57]) , .SAVE (INT_SUM[58]) , .CARRY (INT_CARRY[47]) );
HALF_ADDER HA_12 (.DATA_A (INT_CARRY[38]) , .DATA_B (INT_CARRY[39]) , .SAVE (INT_SUM[59]) , .CARRY (INT_CARRY[48]) );
FULL_ADDER FA_35 (.DATA_A (INT_SUM[58]) , .DATA_B (INT_SUM[59]) , .DATA_C (INT_CARRY[40]) , .SAVE (INT_SUM[60]) , .CARRY (INT_CARRY[49]) );
assign INT_SUM[61] = INT_CARRY[41];
FULL_ADDER FA_36 (.DATA_A (INT_SUM[60]) , .DATA_B (INT_SUM[61]) , .DATA_C (INT_CARRY[42]) , .SAVE (INT_SUM[62]) , .CARRY (INT_CARRY[43]) );
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[14]) );
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[14]) );
FULL_ADDER FA_37 (.DATA_A (SUMMAND[72]) , .DATA_B (SUMMAND[73]) , .DATA_C (SUMMAND[74]) , .SAVE (INT_SUM[63]) , .CARRY (INT_CARRY[51]) );
FULL_ADDER FA_38 (.DATA_A (SUMMAND[75]) , .DATA_B (SUMMAND[76]) , .DATA_C (SUMMAND[77]) , .SAVE (INT_SUM[64]) , .CARRY (INT_CARRY[52]) );
HALF_ADDER HA_13 (.DATA_A (SUMMAND[78]) , .DATA_B (SUMMAND[79]) , .SAVE (INT_SUM[65]) , .CARRY (INT_CARRY[53]) );
FULL_ADDER FA_39 (.DATA_A (INT_SUM[63]) , .DATA_B (INT_SUM[64]) , .DATA_C (INT_SUM[65]) , .SAVE (INT_SUM[66]) , .CARRY (INT_CARRY[54]) );
FULL_ADDER FA_40 (.DATA_A (INT_CARRY[44]) , .DATA_B (INT_CARRY[45]) , .DATA_C (INT_CARRY[46]) , .SAVE (INT_SUM[67]) , .CARRY (INT_CARRY[55]) );
FULL_ADDER FA_41 (.DATA_A (INT_SUM[66]) , .DATA_B (INT_SUM[67]) , .DATA_C (INT_CARRY[47]) , .SAVE (INT_SUM[68]) , .CARRY (INT_CARRY[56]) );
assign INT_SUM[69] = INT_CARRY[48];
FULL_ADDER FA_42 (.DATA_A (INT_SUM[68]) , .DATA_B (INT_SUM[69]) , .DATA_C (INT_CARRY[49]) , .SAVE (INT_SUM[70]) , .CARRY (INT_CARRY[50]) );
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[15]) );
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[15]) );
FULL_ADDER FA_43 (.DATA_A (SUMMAND[80]) , .DATA_B (SUMMAND[81]) , .DATA_C (SUMMAND[82]) , .SAVE (INT_SUM[71]) , .CARRY (INT_CARRY[58]) );
FULL_ADDER FA_44 (.DATA_A (SUMMAND[83]) , .DATA_B (SUMMAND[84]) , .DATA_C (SUMMAND[85]) , .SAVE (INT_SUM[72]) , .CARRY (INT_CARRY[59]) );
FULL_ADDER FA_45 (.DATA_A (SUMMAND[86]) , .DATA_B (SUMMAND[87]) , .DATA_C (SUMMAND[88]) , .SAVE (INT_SUM[73]) , .CARRY (INT_CARRY[60]) );
assign INT_SUM[74] = SUMMAND[89];
FULL_ADDER FA_46 (.DATA_A (INT_SUM[71]) , .DATA_B (INT_SUM[72]) , .DATA_C (INT_SUM[73]) , .SAVE (INT_SUM[75]) , .CARRY (INT_CARRY[61]) );
FULL_ADDER FA_47 (.DATA_A (INT_SUM[74]) , .DATA_B (INT_CARRY[51]) , .DATA_C (INT_CARRY[52]) , .SAVE (INT_SUM[76]) , .CARRY (INT_CARRY[62]) );
assign INT_SUM[77] = INT_CARRY[53];
FULL_ADDER FA_48 (.DATA_A (INT_SUM[75]) , .DATA_B (INT_SUM[76]) , .DATA_C (INT_SUM[77]) , .SAVE (INT_SUM[78]) , .CARRY (INT_CARRY[63]) );
HALF_ADDER HA_14 (.DATA_A (INT_CARRY[54]) , .DATA_B (INT_CARRY[55]) , .SAVE (INT_SUM[79]) , .CARRY (INT_CARRY[64]) );
FULL_ADDER FA_49 (.DATA_A (INT_SUM[78]) , .DATA_B (INT_SUM[79]) , .DATA_C (INT_CARRY[56]) , .SAVE (INT_SUM[80]) , .CARRY (INT_CARRY[57]) );
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[16]) );
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[16]) );
FULL_ADDER FA_50 (.DATA_A (SUMMAND[90]) , .DATA_B (SUMMAND[91]) , .DATA_C (SUMMAND[92]) , .SAVE (INT_SUM[81]) , .CARRY (INT_CARRY[65]) );
FULL_ADDER FA_51 (.DATA_A (SUMMAND[93]) , .DATA_B (SUMMAND[94]) , .DATA_C (SUMMAND[95]) , .SAVE (INT_SUM[82]) , .CARRY (INT_CARRY[66]) );
FULL_ADDER FA_52 (.DATA_A (SUMMAND[96]) , .DATA_B (SUMMAND[97]) , .DATA_C (SUMMAND[98]) , .SAVE (INT_SUM[83]) , .CARRY (INT_CARRY[67]) );
FULL_ADDER FA_53 (.DATA_A (INT_SUM[81]) , .DATA_B (INT_SUM[82]) , .DATA_C (INT_SUM[83]) , .SAVE (INT_SUM[84]) , .CARRY (INT_CARRY[68]) );
FULL_ADDER FA_54 (.DATA_A (INT_CARRY[58]) , .DATA_B (INT_CARRY[59]) , .DATA_C (INT_CARRY[60]) , .SAVE (INT_SUM[85]) , .CARRY (INT_CARRY[69]) );
FULL_ADDER FA_55 (.DATA_A (INT_SUM[84]) , .DATA_B (INT_SUM[85]) , .DATA_C (INT_CARRY[61]) , .SAVE (INT_SUM[86]) , .CARRY (INT_CARRY[70]) );
assign INT_SUM[87] = INT_CARRY[62];
FULL_ADDER FA_56 (.DATA_A (INT_SUM[86]) , .DATA_B (INT_SUM[87]) , .DATA_C (INT_CARRY[63]) , .SAVE (INT_SUM[88]) , .CARRY (INT_CARRY[71]) );
assign INT_SUM[90] = INT_CARRY[64];
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[89]) );
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[91]) );
HALF_ADDER HA_15 (.DATA_A (INT_SUM[89]) , .DATA_B (INT_SUM[91]) , .SAVE (SUM[17]) , .CARRY (CARRY[17]) );
FULL_ADDER FA_57 (.DATA_A (SUMMAND[99]) , .DATA_B (SUMMAND[100]) , .DATA_C (SUMMAND[101]) , .SAVE (INT_SUM[92]) , .CARRY (INT_CARRY[73]) );
FULL_ADDER FA_58 (.DATA_A (SUMMAND[102]) , .DATA_B (SUMMAND[103]) , .DATA_C (SUMMAND[104]) , .SAVE (INT_SUM[93]) , .CARRY (INT_CARRY[74]) );
FULL_ADDER FA_59 (.DATA_A (SUMMAND[105]) , .DATA_B (SUMMAND[106]) , .DATA_C (SUMMAND[107]) , .SAVE (INT_SUM[94]) , .CARRY (INT_CARRY[75]) );
assign INT_SUM[95] = SUMMAND[108];
assign INT_SUM[96] = SUMMAND[109];
FULL_ADDER FA_60 (.DATA_A (INT_SUM[92]) , .DATA_B (INT_SUM[93]) , .DATA_C (INT_SUM[94]) , .SAVE (INT_SUM[97]) , .CARRY (INT_CARRY[76]) );
FULL_ADDER FA_61 (.DATA_A (INT_SUM[95]) , .DATA_B (INT_SUM[96]) , .DATA_C (INT_CARRY[65]) , .SAVE (INT_SUM[98]) , .CARRY (INT_CARRY[77]) );
assign INT_SUM[99] = INT_CARRY[66];
assign INT_SUM[100] = INT_CARRY[67];
FULL_ADDER FA_62 (.DATA_A (INT_SUM[97]) , .DATA_B (INT_SUM[98]) , .DATA_C (INT_SUM[99]) , .SAVE (INT_SUM[101]) , .CARRY (INT_CARRY[78]) );
FULL_ADDER FA_63 (.DATA_A (INT_SUM[100]) , .DATA_B (INT_CARRY[68]) , .DATA_C (INT_CARRY[69]) , .SAVE (INT_SUM[102]) , .CARRY (INT_CARRY[79]) );
FULL_ADDER FA_64 (.DATA_A (INT_SUM[101]) , .DATA_B (INT_SUM[102]) , .DATA_C (INT_CARRY[70]) , .SAVE (INT_SUM[103]) , .CARRY (INT_CARRY[80]) );
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[104]) );
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[72]) );
HALF_ADDER HA_16 (.DATA_A (INT_SUM[104]) , .DATA_B (INT_CARRY[72]) , .SAVE (SUM[18]) , .CARRY (CARRY[18]) );
FULL_ADDER FA_65 (.DATA_A (SUMMAND[110]) , .DATA_B (SUMMAND[111]) , .DATA_C (SUMMAND[112]) , .SAVE (INT_SUM[105]) , .CARRY (INT_CARRY[82]) );
FULL_ADDER FA_66 (.DATA_A (SUMMAND[113]) , .DATA_B (SUMMAND[114]) , .DATA_C (SUMMAND[115]) , .SAVE (INT_SUM[106]) , .CARRY (INT_CARRY[83]) );
FULL_ADDER FA_67 (.DATA_A (SUMMAND[116]) , .DATA_B (SUMMAND[117]) , .DATA_C (SUMMAND[118]) , .SAVE (INT_SUM[107]) , .CARRY (INT_CARRY[84]) );
assign INT_SUM[108] = SUMMAND[119];
FULL_ADDER FA_68 (.DATA_A (INT_SUM[105]) , .DATA_B (INT_SUM[106]) , .DATA_C (INT_SUM[107]) , .SAVE (INT_SUM[109]) , .CARRY (INT_CARRY[85]) );
FULL_ADDER FA_69 (.DATA_A (INT_SUM[108]) , .DATA_B (INT_CARRY[73]) , .DATA_C (INT_CARRY[74]) , .SAVE (INT_SUM[110]) , .CARRY (INT_CARRY[86]) );
assign INT_SUM[111] = INT_CARRY[75];
FULL_ADDER FA_70 (.DATA_A (INT_SUM[109]) , .DATA_B (INT_SUM[110]) , .DATA_C (INT_SUM[111]) , .SAVE (INT_SUM[112]) , .CARRY (INT_CARRY[87]) );
HALF_ADDER HA_17 (.DATA_A (INT_CARRY[76]) , .DATA_B (INT_CARRY[77]) , .SAVE (INT_SUM[113]) , .CARRY (INT_CARRY[88]) );
FULL_ADDER FA_71 (.DATA_A (INT_SUM[112]) , .DATA_B (INT_SUM[113]) , .DATA_C (INT_CARRY[78]) , .SAVE (INT_SUM[114]) , .CARRY (INT_CARRY[89]) );
assign INT_SUM[116] = INT_CARRY[79];
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[115]) );
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[117]) );
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[81]) );
FULL_ADDER FA_72 (.DATA_A (INT_SUM[115]) , .DATA_B (INT_SUM[117]) , .DATA_C (INT_CARRY[81]) , .SAVE (SUM[19]) , .CARRY (CARRY[19]) );
FULL_ADDER FA_73 (.DATA_A (SUMMAND[120]) , .DATA_B (SUMMAND[121]) , .DATA_C (SUMMAND[122]) , .SAVE (INT_SUM[118]) , .CARRY (INT_CARRY[91]) );
FULL_ADDER FA_74 (.DATA_A (SUMMAND[123]) , .DATA_B (SUMMAND[124]) , .DATA_C (SUMMAND[125]) , .SAVE (INT_SUM[119]) , .CARRY (INT_CARRY[92]) );
FULL_ADDER FA_75 (.DATA_A (SUMMAND[126]) , .DATA_B (SUMMAND[127]) , .DATA_C (SUMMAND[128]) , .SAVE (INT_SUM[120]) , .CARRY (INT_CARRY[93]) );
FULL_ADDER FA_76 (.DATA_A (SUMMAND[129]) , .DATA_B (SUMMAND[130]) , .DATA_C (SUMMAND[131]) , .SAVE (INT_SUM[121]) , .CARRY (INT_CARRY[94]) );
FULL_ADDER FA_77 (.DATA_A (INT_SUM[118]) , .DATA_B (INT_SUM[119]) , .DATA_C (INT_SUM[120]) , .SAVE (INT_SUM[122]) , .CARRY (INT_CARRY[95]) );
FULL_ADDER FA_78 (.DATA_A (INT_SUM[121]) , .DATA_B (INT_CARRY[82]) , .DATA_C (INT_CARRY[83]) , .SAVE (INT_SUM[123]) , .CARRY (INT_CARRY[96]) );
assign INT_SUM[124] = INT_CARRY[84];
FULL_ADDER FA_79 (.DATA_A (INT_SUM[122]) , .DATA_B (INT_SUM[123]) , .DATA_C (INT_SUM[124]) , .SAVE (INT_SUM[125]) , .CARRY (INT_CARRY[97]) );
HALF_ADDER HA_18 (.DATA_A (INT_CARRY[85]) , .DATA_B (INT_CARRY[86]) , .SAVE (INT_SUM[126]) , .CARRY (INT_CARRY[98]) );
FULL_ADDER FA_80 (.DATA_A (INT_SUM[125]) , .DATA_B (INT_SUM[126]) , .DATA_C (INT_CARRY[87]) , .SAVE (INT_SUM[127]) , .CARRY (INT_CARRY[99]) );
assign INT_SUM[129] = INT_CARRY[88];
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[128]) );
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[130]) );
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[90]) );
FULL_ADDER FA_81 (.DATA_A (INT_SUM[128]) , .DATA_B (INT_SUM[130]) , .DATA_C (INT_CARRY[90]) , .SAVE (SUM[20]) , .CARRY (CARRY[20]) );
FULL_ADDER FA_82 (.DATA_A (SUMMAND[132]) , .DATA_B (SUMMAND[133]) , .DATA_C (SUMMAND[134]) , .SAVE (INT_SUM[131]) , .CARRY (INT_CARRY[101]) );
FULL_ADDER FA_83 (.DATA_A (SUMMAND[135]) , .DATA_B (SUMMAND[136]) , .DATA_C (SUMMAND[137]) , .SAVE (INT_SUM[132]) , .CARRY (INT_CARRY[102]) );
FULL_ADDER FA_84 (.DATA_A (SUMMAND[138]) , .DATA_B (SUMMAND[139]) , .DATA_C (SUMMAND[140]) , .SAVE (INT_SUM[133]) , .CARRY (INT_CARRY[103]) );
assign INT_SUM[134] = SUMMAND[141];
assign INT_SUM[135] = SUMMAND[142];
FULL_ADDER FA_85 (.DATA_A (INT_SUM[131]) , .DATA_B (INT_SUM[132]) , .DATA_C (INT_SUM[133]) , .SAVE (INT_SUM[136]) , .CARRY (INT_CARRY[104]) );
FULL_ADDER FA_86 (.DATA_A (INT_SUM[134]) , .DATA_B (INT_SUM[135]) , .DATA_C (INT_CARRY[91]) , .SAVE (INT_SUM[137]) , .CARRY (INT_CARRY[105]) );
FULL_ADDER FA_87 (.DATA_A (INT_CARRY[92]) , .DATA_B (INT_CARRY[93]) , .DATA_C (INT_CARRY[94]) , .SAVE (INT_SUM[138]) , .CARRY (INT_CARRY[106]) );
FULL_ADDER FA_88 (.DATA_A (INT_SUM[136]) , .DATA_B (INT_SUM[137]) , .DATA_C (INT_SUM[138]) , .SAVE (INT_SUM[139]) , .CARRY (INT_CARRY[107]) );
HALF_ADDER HA_19 (.DATA_A (INT_CARRY[95]) , .DATA_B (INT_CARRY[96]) , .SAVE (INT_SUM[140]) , .CARRY (INT_CARRY[108]) );
FULL_ADDER FA_89 (.DATA_A (INT_SUM[139]) , .DATA_B (INT_SUM[140]) , .DATA_C (INT_CARRY[97]) , .SAVE (INT_SUM[141]) , .CARRY (INT_CARRY[109]) );
assign INT_SUM[143] = INT_CARRY[98];
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[142]) );
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[144]) );
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[100]) );
FULL_ADDER FA_90 (.DATA_A (INT_SUM[142]) , .DATA_B (INT_SUM[144]) , .DATA_C (INT_CARRY[100]) , .SAVE (SUM[21]) , .CARRY (CARRY[21]) );
FULL_ADDER FA_91 (.DATA_A (SUMMAND[143]) , .DATA_B (SUMMAND[144]) , .DATA_C (SUMMAND[145]) , .SAVE (INT_SUM[145]) , .CARRY (INT_CARRY[111]) );
FULL_ADDER FA_92 (.DATA_A (SUMMAND[146]) , .DATA_B (SUMMAND[147]) , .DATA_C (SUMMAND[148]) , .SAVE (INT_SUM[146]) , .CARRY (INT_CARRY[112]) );
FULL_ADDER FA_93 (.DATA_A (SUMMAND[149]) , .DATA_B (SUMMAND[150]) , .DATA_C (SUMMAND[151]) , .SAVE (INT_SUM[147]) , .CARRY (INT_CARRY[113]) );
FULL_ADDER FA_94 (.DATA_A (SUMMAND[152]) , .DATA_B (SUMMAND[153]) , .DATA_C (SUMMAND[154]) , .SAVE (INT_SUM[148]) , .CARRY (INT_CARRY[114]) );
assign INT_SUM[149] = SUMMAND[155];
FULL_ADDER FA_95 (.DATA_A (INT_SUM[145]) , .DATA_B (INT_SUM[146]) , .DATA_C (INT_SUM[147]) , .SAVE (INT_SUM[150]) , .CARRY (INT_CARRY[115]) );
FULL_ADDER FA_96 (.DATA_A (INT_SUM[148]) , .DATA_B (INT_SUM[149]) , .DATA_C (INT_CARRY[101]) , .SAVE (INT_SUM[151]) , .CARRY (INT_CARRY[116]) );
HALF_ADDER HA_20 (.DATA_A (INT_CARRY[102]) , .DATA_B (INT_CARRY[103]) , .SAVE (INT_SUM[152]) , .CARRY (INT_CARRY[117]) );
FULL_ADDER FA_97 (.DATA_A (INT_SUM[150]) , .DATA_B (INT_SUM[151]) , .DATA_C (INT_SUM[152]) , .SAVE (INT_SUM[153]) , .CARRY (INT_CARRY[118]) );
FULL_ADDER FA_98 (.DATA_A (INT_CARRY[104]) , .DATA_B (INT_CARRY[105]) , .DATA_C (INT_CARRY[106]) , .SAVE (INT_SUM[154]) , .CARRY (INT_CARRY[119]) );
FULL_ADDER FA_99 (.DATA_A (INT_SUM[153]) , .DATA_B (INT_SUM[154]) , .DATA_C (INT_CARRY[107]) , .SAVE (INT_SUM[155]) , .CARRY (INT_CARRY[120]) );
assign INT_SUM[157] = INT_CARRY[108];
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[156]) );
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[158]) );
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[110]) );
FULL_ADDER FA_100 (.DATA_A (INT_SUM[156]) , .DATA_B (INT_SUM[158]) , .DATA_C (INT_CARRY[110]) , .SAVE (SUM[22]) , .CARRY (CARRY[22]) );
FULL_ADDER FA_101 (.DATA_A (SUMMAND[156]) , .DATA_B (SUMMAND[157]) , .DATA_C (SUMMAND[158]) , .SAVE (INT_SUM[159]) , .CARRY (INT_CARRY[122]) );
FULL_ADDER FA_102 (.DATA_A (SUMMAND[159]) , .DATA_B (SUMMAND[160]) , .DATA_C (SUMMAND[161]) , .SAVE (INT_SUM[160]) , .CARRY (INT_CARRY[123]) );
FULL_ADDER FA_103 (.DATA_A (SUMMAND[162]) , .DATA_B (SUMMAND[163]) , .DATA_C (SUMMAND[164]) , .SAVE (INT_SUM[161]) , .CARRY (INT_CARRY[124]) );
FULL_ADDER FA_104 (.DATA_A (SUMMAND[165]) , .DATA_B (SUMMAND[166]) , .DATA_C (SUMMAND[167]) , .SAVE (INT_SUM[162]) , .CARRY (INT_CARRY[125]) );
FULL_ADDER FA_105 (.DATA_A (INT_SUM[159]) , .DATA_B (INT_SUM[160]) , .DATA_C (INT_SUM[161]) , .SAVE (INT_SUM[163]) , .CARRY (INT_CARRY[126]) );
FULL_ADDER FA_106 (.DATA_A (INT_SUM[162]) , .DATA_B (INT_CARRY[111]) , .DATA_C (INT_CARRY[112]) , .SAVE (INT_SUM[164]) , .CARRY (INT_CARRY[127]) );
HALF_ADDER HA_21 (.DATA_A (INT_CARRY[113]) , .DATA_B (INT_CARRY[114]) , .SAVE (INT_SUM[165]) , .CARRY (INT_CARRY[128]) );
FULL_ADDER FA_107 (.DATA_A (INT_SUM[163]) , .DATA_B (INT_SUM[164]) , .DATA_C (INT_SUM[165]) , .SAVE (INT_SUM[166]) , .CARRY (INT_CARRY[129]) );
FULL_ADDER FA_108 (.DATA_A (INT_CARRY[115]) , .DATA_B (INT_CARRY[116]) , .DATA_C (INT_CARRY[117]) , .SAVE (INT_SUM[167]) , .CARRY (INT_CARRY[130]) );
FULL_ADDER FA_109 (.DATA_A (INT_SUM[166]) , .DATA_B (INT_SUM[167]) , .DATA_C (INT_CARRY[118]) , .SAVE (INT_SUM[168]) , .CARRY (INT_CARRY[131]) );
assign INT_SUM[170] = INT_CARRY[119];
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[169]) );
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[171]) );
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[121]) );
FULL_ADDER FA_110 (.DATA_A (INT_SUM[169]) , .DATA_B (INT_SUM[171]) , .DATA_C (INT_CARRY[121]) , .SAVE (SUM[23]) , .CARRY (CARRY[23]) );
FULL_ADDER FA_111 (.DATA_A (SUMMAND[168]) , .DATA_B (SUMMAND[169]) , .DATA_C (SUMMAND[170]) , .SAVE (INT_SUM[172]) , .CARRY (INT_CARRY[133]) );
FULL_ADDER FA_112 (.DATA_A (SUMMAND[171]) , .DATA_B (SUMMAND[172]) , .DATA_C (SUMMAND[173]) , .SAVE (INT_SUM[173]) , .CARRY (INT_CARRY[134]) );
FULL_ADDER FA_113 (.DATA_A (SUMMAND[174]) , .DATA_B (SUMMAND[175]) , .DATA_C (SUMMAND[176]) , .SAVE (INT_SUM[174]) , .CARRY (INT_CARRY[135]) );
FULL_ADDER FA_114 (.DATA_A (SUMMAND[177]) , .DATA_B (SUMMAND[178]) , .DATA_C (SUMMAND[179]) , .SAVE (INT_SUM[175]) , .CARRY (INT_CARRY[136]) );
HALF_ADDER HA_22 (.DATA_A (SUMMAND[180]) , .DATA_B (SUMMAND[181]) , .SAVE (INT_SUM[176]) , .CARRY (INT_CARRY[137]) );
FULL_ADDER FA_115 (.DATA_A (INT_SUM[172]) , .DATA_B (INT_SUM[173]) , .DATA_C (INT_SUM[174]) , .SAVE (INT_SUM[177]) , .CARRY (INT_CARRY[138]) );
FULL_ADDER FA_116 (.DATA_A (INT_SUM[175]) , .DATA_B (INT_SUM[176]) , .DATA_C (INT_CARRY[122]) , .SAVE (INT_SUM[178]) , .CARRY (INT_CARRY[139]) );
FULL_ADDER FA_117 (.DATA_A (INT_CARRY[123]) , .DATA_B (INT_CARRY[124]) , .DATA_C (INT_CARRY[125]) , .SAVE (INT_SUM[179]) , .CARRY (INT_CARRY[140]) );
FULL_ADDER FA_118 (.DATA_A (INT_SUM[177]) , .DATA_B (INT_SUM[178]) , .DATA_C (INT_SUM[179]) , .SAVE (INT_SUM[180]) , .CARRY (INT_CARRY[141]) );
FULL_ADDER FA_119 (.DATA_A (INT_CARRY[126]) , .DATA_B (INT_CARRY[127]) , .DATA_C (INT_CARRY[128]) , .SAVE (INT_SUM[181]) , .CARRY (INT_CARRY[142]) );
FULL_ADDER FA_120 (.DATA_A (INT_SUM[180]) , .DATA_B (INT_SUM[181]) , .DATA_C (INT_CARRY[129]) , .SAVE (INT_SUM[182]) , .CARRY (INT_CARRY[143]) );
assign INT_SUM[184] = INT_CARRY[130];
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[183]) );
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[185]) );
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[132]) );
FULL_ADDER FA_121 (.DATA_A (INT_SUM[183]) , .DATA_B (INT_SUM[185]) , .DATA_C (INT_CARRY[132]) , .SAVE (SUM[24]) , .CARRY (CARRY[24]) );
FULL_ADDER FA_122 (.DATA_A (SUMMAND[182]) , .DATA_B (SUMMAND[183]) , .DATA_C (SUMMAND[184]) , .SAVE (INT_SUM[186]) , .CARRY (INT_CARRY[145]) );
FULL_ADDER FA_123 (.DATA_A (SUMMAND[185]) , .DATA_B (SUMMAND[186]) , .DATA_C (SUMMAND[187]) , .SAVE (INT_SUM[187]) , .CARRY (INT_CARRY[146]) );
FULL_ADDER FA_124 (.DATA_A (SUMMAND[188]) , .DATA_B (SUMMAND[189]) , .DATA_C (SUMMAND[190]) , .SAVE (INT_SUM[188]) , .CARRY (INT_CARRY[147]) );
FULL_ADDER FA_125 (.DATA_A (SUMMAND[191]) , .DATA_B (SUMMAND[192]) , .DATA_C (SUMMAND[193]) , .SAVE (INT_SUM[189]) , .CARRY (INT_CARRY[148]) );
assign INT_SUM[190] = SUMMAND[194];
FULL_ADDER FA_126 (.DATA_A (INT_SUM[186]) , .DATA_B (INT_SUM[187]) , .DATA_C (INT_SUM[188]) , .SAVE (INT_SUM[191]) , .CARRY (INT_CARRY[149]) );
FULL_ADDER FA_127 (.DATA_A (INT_SUM[189]) , .DATA_B (INT_SUM[190]) , .DATA_C (INT_CARRY[133]) , .SAVE (INT_SUM[192]) , .CARRY (INT_CARRY[150]) );
FULL_ADDER FA_128 (.DATA_A (INT_CARRY[134]) , .DATA_B (INT_CARRY[135]) , .DATA_C (INT_CARRY[136]) , .SAVE (INT_SUM[193]) , .CARRY (INT_CARRY[151]) );
assign INT_SUM[194] = INT_CARRY[137];
FULL_ADDER FA_129 (.DATA_A (INT_SUM[191]) , .DATA_B (INT_SUM[192]) , .DATA_C (INT_SUM[193]) , .SAVE (INT_SUM[195]) , .CARRY (INT_CARRY[152]) );
FULL_ADDER FA_130 (.DATA_A (INT_SUM[194]) , .DATA_B (INT_CARRY[138]) , .DATA_C (INT_CARRY[139]) , .SAVE (INT_SUM[196]) , .CARRY (INT_CARRY[153]) );
assign INT_SUM[197] = INT_CARRY[140];
FULL_ADDER FA_131 (.DATA_A (INT_SUM[195]) , .DATA_B (INT_SUM[196]) , .DATA_C (INT_SUM[197]) , .SAVE (INT_SUM[198]) , .CARRY (INT_CARRY[154]) );
HALF_ADDER HA_23 (.DATA_A (INT_CARRY[141]) , .DATA_B (INT_CARRY[142]) , .SAVE (INT_SUM[200]) , .CARRY (INT_CARRY[156]) );
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[199]) );
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[201]) );
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[144]) );
FULL_ADDER FA_132 (.DATA_A (INT_SUM[199]) , .DATA_B (INT_SUM[201]) , .DATA_C (INT_CARRY[144]) , .SAVE (SUM[25]) , .CARRY (CARRY[25]) );
FULL_ADDER FA_133 (.DATA_A (SUMMAND[195]) , .DATA_B (SUMMAND[196]) , .DATA_C (SUMMAND[197]) , .SAVE (INT_SUM[202]) , .CARRY (INT_CARRY[158]) );
FULL_ADDER FA_134 (.DATA_A (SUMMAND[198]) , .DATA_B (SUMMAND[199]) , .DATA_C (SUMMAND[200]) , .SAVE (INT_SUM[203]) , .CARRY (INT_CARRY[159]) );
FULL_ADDER FA_135 (.DATA_A (SUMMAND[201]) , .DATA_B (SUMMAND[202]) , .DATA_C (SUMMAND[203]) , .SAVE (INT_SUM[204]) , .CARRY (INT_CARRY[160]) );
FULL_ADDER FA_136 (.DATA_A (SUMMAND[204]) , .DATA_B (SUMMAND[205]) , .DATA_C (SUMMAND[206]) , .SAVE (INT_SUM[205]) , .CARRY (INT_CARRY[161]) );
FULL_ADDER FA_137 (.DATA_A (SUMMAND[207]) , .DATA_B (SUMMAND[208]) , .DATA_C (SUMMAND[209]) , .SAVE (INT_SUM[206]) , .CARRY (INT_CARRY[162]) );
FULL_ADDER FA_138 (.DATA_A (INT_SUM[202]) , .DATA_B (INT_SUM[203]) , .DATA_C (INT_SUM[204]) , .SAVE (INT_SUM[207]) , .CARRY (INT_CARRY[163]) );
FULL_ADDER FA_139 (.DATA_A (INT_SUM[205]) , .DATA_B (INT_SUM[206]) , .DATA_C (INT_CARRY[145]) , .SAVE (INT_SUM[208]) , .CARRY (INT_CARRY[164]) );
FULL_ADDER FA_140 (.DATA_A (INT_CARRY[146]) , .DATA_B (INT_CARRY[147]) , .DATA_C (INT_CARRY[148]) , .SAVE (INT_SUM[209]) , .CARRY (INT_CARRY[165]) );
FULL_ADDER FA_141 (.DATA_A (INT_SUM[207]) , .DATA_B (INT_SUM[208]) , .DATA_C (INT_SUM[209]) , .SAVE (INT_SUM[210]) , .CARRY (INT_CARRY[166]) );
FULL_ADDER FA_142 (.DATA_A (INT_CARRY[149]) , .DATA_B (INT_CARRY[150]) , .DATA_C (INT_CARRY[151]) , .SAVE (INT_SUM[211]) , .CARRY (INT_CARRY[167]) );
FULL_ADDER FA_143 (.DATA_A (INT_SUM[210]) , .DATA_B (INT_SUM[211]) , .DATA_C (INT_CARRY[152]) , .SAVE (INT_SUM[212]) , .CARRY (INT_CARRY[168]) );
assign INT_SUM[214] = INT_CARRY[153];
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[213]) );
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[215]) );
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[155]) );
FULL_ADDER FA_144 (.DATA_A (INT_SUM[213]) , .DATA_B (INT_SUM[215]) , .DATA_C (INT_CARRY[155]) , .SAVE (INT_SUM[216]) , .CARRY (INT_CARRY[170]) );
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[157]) );
assign INT_SUM[217] = INT_CARRY[157];
HALF_ADDER HA_24 (.DATA_A (INT_SUM[216]) , .DATA_B (INT_SUM[217]) , .SAVE (SUM[26]) , .CARRY (CARRY[26]) );
FULL_ADDER FA_145 (.DATA_A (SUMMAND[210]) , .DATA_B (SUMMAND[211]) , .DATA_C (SUMMAND[212]) , .SAVE (INT_SUM[218]) , .CARRY (INT_CARRY[171]) );
FULL_ADDER FA_146 (.DATA_A (SUMMAND[213]) , .DATA_B (SUMMAND[214]) , .DATA_C (SUMMAND[215]) , .SAVE (INT_SUM[219]) , .CARRY (INT_CARRY[172]) );
FULL_ADDER FA_147 (.DATA_A (SUMMAND[216]) , .DATA_B (SUMMAND[217]) , .DATA_C (SUMMAND[218]) , .SAVE (INT_SUM[220]) , .CARRY (INT_CARRY[173]) );
FULL_ADDER FA_148 (.DATA_A (SUMMAND[219]) , .DATA_B (SUMMAND[220]) , .DATA_C (SUMMAND[221]) , .SAVE (INT_SUM[221]) , .CARRY (INT_CARRY[174]) );
HALF_ADDER HA_25 (.DATA_A (SUMMAND[222]) , .DATA_B (SUMMAND[223]) , .SAVE (INT_SUM[222]) , .CARRY (INT_CARRY[175]) );
FULL_ADDER FA_149 (.DATA_A (INT_SUM[218]) , .DATA_B (INT_SUM[219]) , .DATA_C (INT_SUM[220]) , .SAVE (INT_SUM[223]) , .CARRY (INT_CARRY[176]) );
FULL_ADDER FA_150 (.DATA_A (INT_SUM[221]) , .DATA_B (INT_SUM[222]) , .DATA_C (INT_CARRY[158]) , .SAVE (INT_SUM[224]) , .CARRY (INT_CARRY[177]) );
FULL_ADDER FA_151 (.DATA_A (INT_CARRY[159]) , .DATA_B (INT_CARRY[160]) , .DATA_C (INT_CARRY[161]) , .SAVE (INT_SUM[225]) , .CARRY (INT_CARRY[178]) );
assign INT_SUM[226] = INT_CARRY[162];
FULL_ADDER FA_152 (.DATA_A (INT_SUM[223]) , .DATA_B (INT_SUM[224]) , .DATA_C (INT_SUM[225]) , .SAVE (INT_SUM[227]) , .CARRY (INT_CARRY[179]) );
FULL_ADDER FA_153 (.DATA_A (INT_SUM[226]) , .DATA_B (INT_CARRY[163]) , .DATA_C (INT_CARRY[164]) , .SAVE (INT_SUM[228]) , .CARRY (INT_CARRY[180]) );
assign INT_SUM[229] = INT_CARRY[165];
FULL_ADDER FA_154 (.DATA_A (INT_SUM[227]) , .DATA_B (INT_SUM[228]) , .DATA_C (INT_SUM[229]) , .SAVE (INT_SUM[230]) , .CARRY (INT_CARRY[181]) );
assign INT_SUM[232] = INT_CARRY[166];
assign INT_SUM[234] = INT_CARRY[167];
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[231]) );
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[233]) );
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[235]) );
FULL_ADDER FA_155 (.DATA_A (INT_SUM[231]) , .DATA_B (INT_SUM[233]) , .DATA_C (INT_SUM[235]) , .SAVE (INT_SUM[236]) , .CARRY (INT_CARRY[183]) );
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[169]) );
assign INT_SUM[237] = INT_CARRY[169];
FULL_ADDER FA_156 (.DATA_A (INT_SUM[236]) , .DATA_B (INT_SUM[237]) , .DATA_C (INT_CARRY[170]) , .SAVE (SUM[27]) , .CARRY (CARRY[27]) );
FULL_ADDER FA_157 (.DATA_A (SUMMAND[224]) , .DATA_B (SUMMAND[225]) , .DATA_C (SUMMAND[226]) , .SAVE (INT_SUM[238]) , .CARRY (INT_CARRY[184]) );
FULL_ADDER FA_158 (.DATA_A (SUMMAND[227]) , .DATA_B (SUMMAND[228]) , .DATA_C (SUMMAND[229]) , .SAVE (INT_SUM[239]) , .CARRY (INT_CARRY[185]) );
FULL_ADDER FA_159 (.DATA_A (SUMMAND[230]) , .DATA_B (SUMMAND[231]) , .DATA_C (SUMMAND[232]) , .SAVE (INT_SUM[240]) , .CARRY (INT_CARRY[186]) );
FULL_ADDER FA_160 (.DATA_A (SUMMAND[233]) , .DATA_B (SUMMAND[234]) , .DATA_C (SUMMAND[235]) , .SAVE (INT_SUM[241]) , .CARRY (INT_CARRY[187]) );
FULL_ADDER FA_161 (.DATA_A (SUMMAND[236]) , .DATA_B (SUMMAND[237]) , .DATA_C (SUMMAND[238]) , .SAVE (INT_SUM[242]) , .CARRY (INT_CARRY[188]) );
assign INT_SUM[243] = SUMMAND[239];
FULL_ADDER FA_162 (.DATA_A (INT_SUM[238]) , .DATA_B (INT_SUM[239]) , .DATA_C (INT_SUM[240]) , .SAVE (INT_SUM[244]) , .CARRY (INT_CARRY[189]) );
FULL_ADDER FA_163 (.DATA_A (INT_SUM[241]) , .DATA_B (INT_SUM[242]) , .DATA_C (INT_SUM[243]) , .SAVE (INT_SUM[245]) , .CARRY (INT_CARRY[190]) );
FULL_ADDER FA_164 (.DATA_A (INT_CARRY[171]) , .DATA_B (INT_CARRY[172]) , .DATA_C (INT_CARRY[173]) , .SAVE (INT_SUM[246]) , .CARRY (INT_CARRY[191]) );
assign INT_SUM[247] = INT_CARRY[174];
assign INT_SUM[248] = INT_CARRY[175];
FULL_ADDER FA_165 (.DATA_A (INT_SUM[244]) , .DATA_B (INT_SUM[245]) , .DATA_C (INT_SUM[246]) , .SAVE (INT_SUM[249]) , .CARRY (INT_CARRY[192]) );
FULL_ADDER FA_166 (.DATA_A (INT_SUM[247]) , .DATA_B (INT_SUM[248]) , .DATA_C (INT_CARRY[176]) , .SAVE (INT_SUM[250]) , .CARRY (INT_CARRY[193]) );
assign INT_SUM[251] = INT_CARRY[177];
assign INT_SUM[252] = INT_CARRY[178];
FULL_ADDER FA_167 (.DATA_A (INT_SUM[249]) , .DATA_B (INT_SUM[250]) , .DATA_C (INT_SUM[251]) , .SAVE (INT_SUM[253]) , .CARRY (INT_CARRY[194]) );
FULL_ADDER FA_168 (.DATA_A (INT_SUM[252]) , .DATA_B (INT_CARRY[179]) , .DATA_C (INT_CARRY[180]) , .SAVE (INT_SUM[255]) , .CARRY (INT_CARRY[196]) );
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[254]) );
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[256]) );
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[182]) );
FULL_ADDER FA_169 (.DATA_A (INT_SUM[254]) , .DATA_B (INT_SUM[256]) , .DATA_C (INT_CARRY[182]) , .SAVE (INT_SUM[257]) , .CARRY (INT_CARRY[198]) );
HALF_ADDER HA_26 (.DATA_A (INT_SUM[257]) , .DATA_B (INT_CARRY[183]) , .SAVE (SUM[28]) , .CARRY (CARRY[28]) );
FULL_ADDER FA_170 (.DATA_A (SUMMAND[240]) , .DATA_B (SUMMAND[241]) , .DATA_C (SUMMAND[242]) , .SAVE (INT_SUM[258]) , .CARRY (INT_CARRY[199]) );
FULL_ADDER FA_171 (.DATA_A (SUMMAND[243]) , .DATA_B (SUMMAND[244]) , .DATA_C (SUMMAND[245]) , .SAVE (INT_SUM[259]) , .CARRY (INT_CARRY[200]) );
FULL_ADDER FA_172 (.DATA_A (SUMMAND[246]) , .DATA_B (SUMMAND[247]) , .DATA_C (SUMMAND[248]) , .SAVE (INT_SUM[260]) , .CARRY (INT_CARRY[201]) );
FULL_ADDER FA_173 (.DATA_A (SUMMAND[249]) , .DATA_B (SUMMAND[250]) , .DATA_C (SUMMAND[251]) , .SAVE (INT_SUM[261]) , .CARRY (INT_CARRY[202]) );
FULL_ADDER FA_174 (.DATA_A (SUMMAND[252]) , .DATA_B (SUMMAND[253]) , .DATA_C (SUMMAND[254]) , .SAVE (INT_SUM[262]) , .CARRY (INT_CARRY[203]) );
FULL_ADDER FA_175 (.DATA_A (INT_SUM[258]) , .DATA_B (INT_SUM[259]) , .DATA_C (INT_SUM[260]) , .SAVE (INT_SUM[263]) , .CARRY (INT_CARRY[204]) );
FULL_ADDER FA_176 (.DATA_A (INT_SUM[261]) , .DATA_B (INT_SUM[262]) , .DATA_C (INT_CARRY[184]) , .SAVE (INT_SUM[264]) , .CARRY (INT_CARRY[205]) );
FULL_ADDER FA_177 (.DATA_A (INT_CARRY[185]) , .DATA_B (INT_CARRY[186]) , .DATA_C (INT_CARRY[187]) , .SAVE (INT_SUM[265]) , .CARRY (INT_CARRY[206]) );
assign INT_SUM[266] = INT_CARRY[188];
FULL_ADDER FA_178 (.DATA_A (INT_SUM[263]) , .DATA_B (INT_SUM[264]) , .DATA_C (INT_SUM[265]) , .SAVE (INT_SUM[267]) , .CARRY (INT_CARRY[207]) );
FULL_ADDER FA_179 (.DATA_A (INT_SUM[266]) , .DATA_B (INT_CARRY[189]) , .DATA_C (INT_CARRY[190]) , .SAVE (INT_SUM[268]) , .CARRY (INT_CARRY[208]) );
assign INT_SUM[269] = INT_CARRY[191];
FULL_ADDER FA_180 (.DATA_A (INT_SUM[267]) , .DATA_B (INT_SUM[268]) , .DATA_C (INT_SUM[269]) , .SAVE (INT_SUM[270]) , .CARRY (INT_CARRY[209]) );
HALF_ADDER HA_27 (.DATA_A (INT_CARRY[192]) , .DATA_B (INT_CARRY[193]) , .SAVE (INT_SUM[272]) , .CARRY (INT_CARRY[211]) );
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[271]) );
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[273]) );
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[195]) );
FULL_ADDER FA_181 (.DATA_A (INT_SUM[271]) , .DATA_B (INT_SUM[273]) , .DATA_C (INT_CARRY[195]) , .SAVE (INT_SUM[274]) , .CARRY (INT_CARRY[213]) );
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[197]) );
assign INT_SUM[275] = INT_CARRY[197];
FULL_ADDER FA_182 (.DATA_A (INT_SUM[274]) , .DATA_B (INT_SUM[275]) , .DATA_C (INT_CARRY[198]) , .SAVE (SUM[29]) , .CARRY (CARRY[29]) );
FULL_ADDER FA_183 (.DATA_A (SUMMAND[255]) , .DATA_B (SUMMAND[256]) , .DATA_C (SUMMAND[257]) , .SAVE (INT_SUM[276]) , .CARRY (INT_CARRY[214]) );
FULL_ADDER FA_184 (.DATA_A (SUMMAND[258]) , .DATA_B (SUMMAND[259]) , .DATA_C (SUMMAND[260]) , .SAVE (INT_SUM[277]) , .CARRY (INT_CARRY[215]) );
FULL_ADDER FA_185 (.DATA_A (SUMMAND[261]) , .DATA_B (SUMMAND[262]) , .DATA_C (SUMMAND[263]) , .SAVE (INT_SUM[278]) , .CARRY (INT_CARRY[216]) );
FULL_ADDER FA_186 (.DATA_A (SUMMAND[264]) , .DATA_B (SUMMAND[265]) , .DATA_C (SUMMAND[266]) , .SAVE (INT_SUM[279]) , .CARRY (INT_CARRY[217]) );
FULL_ADDER FA_187 (.DATA_A (SUMMAND[267]) , .DATA_B (SUMMAND[268]) , .DATA_C (SUMMAND[269]) , .SAVE (INT_SUM[280]) , .CARRY (INT_CARRY[218]) );
assign INT_SUM[281] = SUMMAND[270];
assign INT_SUM[282] = SUMMAND[271];
FULL_ADDER FA_188 (.DATA_A (INT_SUM[276]) , .DATA_B (INT_SUM[277]) , .DATA_C (INT_SUM[278]) , .SAVE (INT_SUM[283]) , .CARRY (INT_CARRY[219]) );
FULL_ADDER FA_189 (.DATA_A (INT_SUM[279]) , .DATA_B (INT_SUM[280]) , .DATA_C (INT_SUM[281]) , .SAVE (INT_SUM[284]) , .CARRY (INT_CARRY[220]) );
FULL_ADDER FA_190 (.DATA_A (INT_SUM[282]) , .DATA_B (INT_CARRY[199]) , .DATA_C (INT_CARRY[200]) , .SAVE (INT_SUM[285]) , .CARRY (INT_CARRY[221]) );
FULL_ADDER FA_191 (.DATA_A (INT_CARRY[201]) , .DATA_B (INT_CARRY[202]) , .DATA_C (INT_CARRY[203]) , .SAVE (INT_SUM[286]) , .CARRY (INT_CARRY[222]) );
FULL_ADDER FA_192 (.DATA_A (INT_SUM[283]) , .DATA_B (INT_SUM[284]) , .DATA_C (INT_SUM[285]) , .SAVE (INT_SUM[287]) , .CARRY (INT_CARRY[223]) );
FULL_ADDER FA_193 (.DATA_A (INT_SUM[286]) , .DATA_B (INT_CARRY[204]) , .DATA_C (INT_CARRY[205]) , .SAVE (INT_SUM[288]) , .CARRY (INT_CARRY[224]) );
assign INT_SUM[289] = INT_CARRY[206];
FULL_ADDER FA_194 (.DATA_A (INT_SUM[287]) , .DATA_B (INT_SUM[288]) , .DATA_C (INT_SUM[289]) , .SAVE (INT_SUM[290]) , .CARRY (INT_CARRY[225]) );
HALF_ADDER HA_28 (.DATA_A (INT_CARRY[207]) , .DATA_B (INT_CARRY[208]) , .SAVE (INT_SUM[292]) , .CARRY (INT_CARRY[227]) );
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[291]) );
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[293]) );
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[210]) );
FULL_ADDER FA_195 (.DATA_A (INT_SUM[291]) , .DATA_B (INT_SUM[293]) , .DATA_C (INT_CARRY[210]) , .SAVE (INT_SUM[294]) , .CARRY (INT_CARRY[229]) );
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[212]) );
assign INT_SUM[295] = INT_CARRY[212];
FULL_ADDER FA_196 (.DATA_A (INT_SUM[294]) , .DATA_B (INT_SUM[295]) , .DATA_C (INT_CARRY[213]) , .SAVE (SUM[30]) , .CARRY (CARRY[30]) );
FULL_ADDER FA_197 (.DATA_A (SUMMAND[272]) , .DATA_B (SUMMAND[273]) , .DATA_C (SUMMAND[274]) , .SAVE (INT_SUM[296]) , .CARRY (INT_CARRY[230]) );
FULL_ADDER FA_198 (.DATA_A (SUMMAND[275]) , .DATA_B (SUMMAND[276]) , .DATA_C (SUMMAND[277]) , .SAVE (INT_SUM[297]) , .CARRY (INT_CARRY[231]) );
FULL_ADDER FA_199 (.DATA_A (SUMMAND[278]) , .DATA_B (SUMMAND[279]) , .DATA_C (SUMMAND[280]) , .SAVE (INT_SUM[298]) , .CARRY (INT_CARRY[232]) );
FULL_ADDER FA_200 (.DATA_A (SUMMAND[281]) , .DATA_B (SUMMAND[282]) , .DATA_C (SUMMAND[283]) , .SAVE (INT_SUM[299]) , .CARRY (INT_CARRY[233]) );
FULL_ADDER FA_201 (.DATA_A (SUMMAND[284]) , .DATA_B (SUMMAND[285]) , .DATA_C (SUMMAND[286]) , .SAVE (INT_SUM[300]) , .CARRY (INT_CARRY[234]) );
assign INT_SUM[301] = SUMMAND[287];
FULL_ADDER FA_202 (.DATA_A (INT_SUM[296]) , .DATA_B (INT_SUM[297]) , .DATA_C (INT_SUM[298]) , .SAVE (INT_SUM[302]) , .CARRY (INT_CARRY[235]) );
FULL_ADDER FA_203 (.DATA_A (INT_SUM[299]) , .DATA_B (INT_SUM[300]) , .DATA_C (INT_SUM[301]) , .SAVE (INT_SUM[303]) , .CARRY (INT_CARRY[236]) );
FULL_ADDER FA_204 (.DATA_A (INT_CARRY[214]) , .DATA_B (INT_CARRY[215]) , .DATA_C (INT_CARRY[216]) , .SAVE (INT_SUM[304]) , .CARRY (INT_CARRY[237]) );
assign INT_SUM[305] = INT_CARRY[217];
assign INT_SUM[306] = INT_CARRY[218];
FULL_ADDER FA_205 (.DATA_A (INT_SUM[302]) , .DATA_B (INT_SUM[303]) , .DATA_C (INT_SUM[304]) , .SAVE (INT_SUM[307]) , .CARRY (INT_CARRY[238]) );
FULL_ADDER FA_206 (.DATA_A (INT_SUM[305]) , .DATA_B (INT_SUM[306]) , .DATA_C (INT_CARRY[219]) , .SAVE (INT_SUM[308]) , .CARRY (INT_CARRY[239]) );
FULL_ADDER FA_207 (.DATA_A (INT_CARRY[220]) , .DATA_B (INT_CARRY[221]) , .DATA_C (INT_CARRY[222]) , .SAVE (INT_SUM[309]) , .CARRY (INT_CARRY[240]) );
FULL_ADDER FA_208 (.DATA_A (INT_SUM[307]) , .DATA_B (INT_SUM[308]) , .DATA_C (INT_SUM[309]) , .SAVE (INT_SUM[310]) , .CARRY (INT_CARRY[241]) );
HALF_ADDER HA_29 (.DATA_A (INT_CARRY[223]) , .DATA_B (INT_CARRY[224]) , .SAVE (INT_SUM[312]) , .CARRY (INT_CARRY[243]) );
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[311]) );
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[313]) );
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[226]) );
FULL_ADDER FA_209 (.DATA_A (INT_SUM[311]) , .DATA_B (INT_SUM[313]) , .DATA_C (INT_CARRY[226]) , .SAVE (INT_SUM[314]) , .CARRY (INT_CARRY[245]) );
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[228]) );
assign INT_SUM[315] = INT_CARRY[228];
FULL_ADDER FA_210 (.DATA_A (INT_SUM[314]) , .DATA_B (INT_SUM[315]) , .DATA_C (INT_CARRY[229]) , .SAVE (SUM[31]) , .CARRY (CARRY[31]) );
FULL_ADDER FA_211 (.DATA_A (SUMMAND[288]) , .DATA_B (SUMMAND[289]) , .DATA_C (SUMMAND[290]) , .SAVE (INT_SUM[316]) , .CARRY (INT_CARRY[246]) );
FULL_ADDER FA_212 (.DATA_A (SUMMAND[291]) , .DATA_B (SUMMAND[292]) , .DATA_C (SUMMAND[293]) , .SAVE (INT_SUM[317]) , .CARRY (INT_CARRY[247]) );
FULL_ADDER FA_213 (.DATA_A (SUMMAND[294]) , .DATA_B (SUMMAND[295]) , .DATA_C (SUMMAND[296]) , .SAVE (INT_SUM[318]) , .CARRY (INT_CARRY[248]) );
FULL_ADDER FA_214 (.DATA_A (SUMMAND[297]) , .DATA_B (SUMMAND[298]) , .DATA_C (SUMMAND[299]) , .SAVE (INT_SUM[319]) , .CARRY (INT_CARRY[249]) );
FULL_ADDER FA_215 (.DATA_A (SUMMAND[300]) , .DATA_B (SUMMAND[301]) , .DATA_C (SUMMAND[302]) , .SAVE (INT_SUM[320]) , .CARRY (INT_CARRY[250]) );
assign INT_SUM[321] = SUMMAND[303];
FULL_ADDER FA_216 (.DATA_A (INT_SUM[316]) , .DATA_B (INT_SUM[317]) , .DATA_C (INT_SUM[318]) , .SAVE (INT_SUM[322]) , .CARRY (INT_CARRY[251]) );
FULL_ADDER FA_217 (.DATA_A (INT_SUM[319]) , .DATA_B (INT_SUM[320]) , .DATA_C (INT_SUM[321]) , .SAVE (INT_SUM[323]) , .CARRY (INT_CARRY[252]) );
FULL_ADDER FA_218 (.DATA_A (INT_CARRY[230]) , .DATA_B (INT_CARRY[231]) , .DATA_C (INT_CARRY[232]) , .SAVE (INT_SUM[324]) , .CARRY (INT_CARRY[253]) );
HALF_ADDER HA_30 (.DATA_A (INT_CARRY[233]) , .DATA_B (INT_CARRY[234]) , .SAVE (INT_SUM[325]) , .CARRY (INT_CARRY[254]) );
FULL_ADDER FA_219 (.DATA_A (INT_SUM[322]) , .DATA_B (INT_SUM[323]) , .DATA_C (INT_SUM[324]) , .SAVE (INT_SUM[326]) , .CARRY (INT_CARRY[255]) );
FULL_ADDER FA_220 (.DATA_A (INT_SUM[325]) , .DATA_B (INT_CARRY[235]) , .DATA_C (INT_CARRY[236]) , .SAVE (INT_SUM[327]) , .CARRY (INT_CARRY[256]) );
assign INT_SUM[328] = INT_CARRY[237];
FULL_ADDER FA_221 (.DATA_A (INT_SUM[326]) , .DATA_B (INT_SUM[327]) , .DATA_C (INT_SUM[328]) , .SAVE (INT_SUM[329]) , .CARRY (INT_CARRY[257]) );
FULL_ADDER FA_222 (.DATA_A (INT_CARRY[238]) , .DATA_B (INT_CARRY[239]) , .DATA_C (INT_CARRY[240]) , .SAVE (INT_SUM[331]) , .CARRY (INT_CARRY[259]) );
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[330]) );
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[332]) );
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[242]) );
FULL_ADDER FA_223 (.DATA_A (INT_SUM[330]) , .DATA_B (INT_SUM[332]) , .DATA_C (INT_CARRY[242]) , .SAVE (INT_SUM[333]) , .CARRY (INT_CARRY[261]) );
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[244]) );
assign INT_SUM[334] = INT_CARRY[244];
FULL_ADDER FA_224 (.DATA_A (INT_SUM[333]) , .DATA_B (INT_SUM[334]) , .DATA_C (INT_CARRY[245]) , .SAVE (SUM[32]) , .CARRY (CARRY[32]) );
FULL_ADDER FA_225 (.DATA_A (SUMMAND[304]) , .DATA_B (SUMMAND[305]) , .DATA_C (SUMMAND[306]) , .SAVE (INT_SUM[335]) , .CARRY (INT_CARRY[262]) );
FULL_ADDER FA_226 (.DATA_A (SUMMAND[307]) , .DATA_B (SUMMAND[308]) , .DATA_C (SUMMAND[309]) , .SAVE (INT_SUM[336]) , .CARRY (INT_CARRY[263]) );
FULL_ADDER FA_227 (.DATA_A (SUMMAND[310]) , .DATA_B (SUMMAND[311]) , .DATA_C (SUMMAND[312]) , .SAVE (INT_SUM[337]) , .CARRY (INT_CARRY[264]) );
FULL_ADDER FA_228 (.DATA_A (SUMMAND[313]) , .DATA_B (SUMMAND[314]) , .DATA_C (SUMMAND[315]) , .SAVE (INT_SUM[338]) , .CARRY (INT_CARRY[265]) );
FULL_ADDER FA_229 (.DATA_A (SUMMAND[316]) , .DATA_B (SUMMAND[317]) , .DATA_C (SUMMAND[318]) , .SAVE (INT_SUM[339]) , .CARRY (INT_CARRY[266]) );
assign INT_SUM[340] = SUMMAND[319];
assign INT_SUM[341] = SUMMAND[320];
FULL_ADDER FA_230 (.DATA_A (INT_SUM[335]) , .DATA_B (INT_SUM[336]) , .DATA_C (INT_SUM[337]) , .SAVE (INT_SUM[342]) , .CARRY (INT_CARRY[267]) );
FULL_ADDER FA_231 (.DATA_A (INT_SUM[338]) , .DATA_B (INT_SUM[339]) , .DATA_C (INT_SUM[340]) , .SAVE (INT_SUM[343]) , .CARRY (INT_CARRY[268]) );
FULL_ADDER FA_232 (.DATA_A (INT_SUM[341]) , .DATA_B (INT_CARRY[246]) , .DATA_C (INT_CARRY[247]) , .SAVE (INT_SUM[344]) , .CARRY (INT_CARRY[269]) );
FULL_ADDER FA_233 (.DATA_A (INT_CARRY[248]) , .DATA_B (INT_CARRY[249]) , .DATA_C (INT_CARRY[250]) , .SAVE (INT_SUM[345]) , .CARRY (INT_CARRY[270]) );
FULL_ADDER FA_234 (.DATA_A (INT_SUM[342]) , .DATA_B (INT_SUM[343]) , .DATA_C (INT_SUM[344]) , .SAVE (INT_SUM[346]) , .CARRY (INT_CARRY[271]) );
FULL_ADDER FA_235 (.DATA_A (INT_SUM[345]) , .DATA_B (INT_CARRY[251]) , .DATA_C (INT_CARRY[252]) , .SAVE (INT_SUM[347]) , .CARRY (INT_CARRY[272]) );
assign INT_SUM[348] = INT_CARRY[253];
assign INT_SUM[349] = INT_CARRY[254];
FULL_ADDER FA_236 (.DATA_A (INT_SUM[346]) , .DATA_B (INT_SUM[347]) , .DATA_C (INT_SUM[348]) , .SAVE (INT_SUM[350]) , .CARRY (INT_CARRY[273]) );
FULL_ADDER FA_237 (.DATA_A (INT_SUM[349]) , .DATA_B (INT_CARRY[255]) , .DATA_C (INT_CARRY[256]) , .SAVE (INT_SUM[352]) , .CARRY (INT_CARRY[275]) );
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[351]) );
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[353]) );
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[258]) );
FULL_ADDER FA_238 (.DATA_A (INT_SUM[351]) , .DATA_B (INT_SUM[353]) , .DATA_C (INT_CARRY[258]) , .SAVE (INT_SUM[354]) , .CARRY (INT_CARRY[277]) );
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[260]) );
assign INT_SUM[355] = INT_CARRY[260];
FULL_ADDER FA_239 (.DATA_A (INT_SUM[354]) , .DATA_B (INT_SUM[355]) , .DATA_C (INT_CARRY[261]) , .SAVE (SUM[33]) , .CARRY (CARRY[33]) );
FULL_ADDER FA_240 (.DATA_A (SUMMAND[321]) , .DATA_B (SUMMAND[322]) , .DATA_C (SUMMAND[323]) , .SAVE (INT_SUM[356]) , .CARRY (INT_CARRY[278]) );
FULL_ADDER FA_241 (.DATA_A (SUMMAND[324]) , .DATA_B (SUMMAND[325]) , .DATA_C (SUMMAND[326]) , .SAVE (INT_SUM[357]) , .CARRY (INT_CARRY[279]) );
FULL_ADDER FA_242 (.DATA_A (SUMMAND[327]) , .DATA_B (SUMMAND[328]) , .DATA_C (SUMMAND[329]) , .SAVE (INT_SUM[358]) , .CARRY (INT_CARRY[280]) );
FULL_ADDER FA_243 (.DATA_A (SUMMAND[330]) , .DATA_B (SUMMAND[331]) , .DATA_C (SUMMAND[332]) , .SAVE (INT_SUM[359]) , .CARRY (INT_CARRY[281]) );
FULL_ADDER FA_244 (.DATA_A (SUMMAND[333]) , .DATA_B (SUMMAND[334]) , .DATA_C (SUMMAND[335]) , .SAVE (INT_SUM[360]) , .CARRY (INT_CARRY[282]) );
assign INT_SUM[361] = SUMMAND[336];
FULL_ADDER FA_245 (.DATA_A (INT_SUM[356]) , .DATA_B (INT_SUM[357]) , .DATA_C (INT_SUM[358]) , .SAVE (INT_SUM[362]) , .CARRY (INT_CARRY[283]) );
FULL_ADDER FA_246 (.DATA_A (INT_SUM[359]) , .DATA_B (INT_SUM[360]) , .DATA_C (INT_SUM[361]) , .SAVE (INT_SUM[363]) , .CARRY (INT_CARRY[284]) );
FULL_ADDER FA_247 (.DATA_A (INT_CARRY[262]) , .DATA_B (INT_CARRY[263]) , .DATA_C (INT_CARRY[264]) , .SAVE (INT_SUM[364]) , .CARRY (INT_CARRY[285]) );
assign INT_SUM[365] = INT_CARRY[265];
assign INT_SUM[366] = INT_CARRY[266];
FULL_ADDER FA_248 (.DATA_A (INT_SUM[362]) , .DATA_B (INT_SUM[363]) , .DATA_C (INT_SUM[364]) , .SAVE (INT_SUM[367]) , .CARRY (INT_CARRY[286]) );
FULL_ADDER FA_249 (.DATA_A (INT_SUM[365]) , .DATA_B (INT_SUM[366]) , .DATA_C (INT_CARRY[267]) , .SAVE (INT_SUM[368]) , .CARRY (INT_CARRY[287]) );
FULL_ADDER FA_250 (.DATA_A (INT_CARRY[268]) , .DATA_B (INT_CARRY[269]) , .DATA_C (INT_CARRY[270]) , .SAVE (INT_SUM[369]) , .CARRY (INT_CARRY[288]) );
FULL_ADDER FA_251 (.DATA_A (INT_SUM[367]) , .DATA_B (INT_SUM[368]) , .DATA_C (INT_SUM[369]) , .SAVE (INT_SUM[370]) , .CARRY (INT_CARRY[289]) );
HALF_ADDER HA_31 (.DATA_A (INT_CARRY[271]) , .DATA_B (INT_CARRY[272]) , .SAVE (INT_SUM[372]) , .CARRY (INT_CARRY[291]) );
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[371]) );
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[373]) );
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[274]) );
FULL_ADDER FA_252 (.DATA_A (INT_SUM[371]) , .DATA_B (INT_SUM[373]) , .DATA_C (INT_CARRY[274]) , .SAVE (INT_SUM[374]) , .CARRY (INT_CARRY[293]) );
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[276]) );
assign INT_SUM[375] = INT_CARRY[276];
FULL_ADDER FA_253 (.DATA_A (INT_SUM[374]) , .DATA_B (INT_SUM[375]) , .DATA_C (INT_CARRY[277]) , .SAVE (SUM[34]) , .CARRY (CARRY[34]) );
FULL_ADDER FA_254 (.DATA_A (SUMMAND[337]) , .DATA_B (SUMMAND[338]) , .DATA_C (SUMMAND[339]) , .SAVE (INT_SUM[376]) , .CARRY (INT_CARRY[294]) );
FULL_ADDER FA_255 (.DATA_A (SUMMAND[340]) , .DATA_B (SUMMAND[341]) , .DATA_C (SUMMAND[342]) , .SAVE (INT_SUM[377]) , .CARRY (INT_CARRY[295]) );
FULL_ADDER FA_256 (.DATA_A (SUMMAND[343]) , .DATA_B (SUMMAND[344]) , .DATA_C (SUMMAND[345]) , .SAVE (INT_SUM[378]) , .CARRY (INT_CARRY[296]) );
FULL_ADDER FA_257 (.DATA_A (SUMMAND[346]) , .DATA_B (SUMMAND[347]) , .DATA_C (SUMMAND[348]) , .SAVE (INT_SUM[379]) , .CARRY (INT_CARRY[297]) );
FULL_ADDER FA_258 (.DATA_A (SUMMAND[349]) , .DATA_B (SUMMAND[350]) , .DATA_C (SUMMAND[351]) , .SAVE (INT_SUM[380]) , .CARRY (INT_CARRY[298]) );
FULL_ADDER FA_259 (.DATA_A (INT_SUM[376]) , .DATA_B (INT_SUM[377]) , .DATA_C (INT_SUM[378]) , .SAVE (INT_SUM[381]) , .CARRY (INT_CARRY[299]) );
FULL_ADDER FA_260 (.DATA_A (INT_SUM[379]) , .DATA_B (INT_SUM[380]) , .DATA_C (INT_CARRY[278]) , .SAVE (INT_SUM[382]) , .CARRY (INT_CARRY[300]) );
FULL_ADDER FA_261 (.DATA_A (INT_CARRY[279]) , .DATA_B (INT_CARRY[280]) , .DATA_C (INT_CARRY[281]) , .SAVE (INT_SUM[383]) , .CARRY (INT_CARRY[301]) );
assign INT_SUM[384] = INT_CARRY[282];
FULL_ADDER FA_262 (.DATA_A (INT_SUM[381]) , .DATA_B (INT_SUM[382]) , .DATA_C (INT_SUM[383]) , .SAVE (INT_SUM[385]) , .CARRY (INT_CARRY[302]) );
FULL_ADDER FA_263 (.DATA_A (INT_SUM[384]) , .DATA_B (INT_CARRY[283]) , .DATA_C (INT_CARRY[284]) , .SAVE (INT_SUM[386]) , .CARRY (INT_CARRY[303]) );
assign INT_SUM[387] = INT_CARRY[285];
FULL_ADDER FA_264 (.DATA_A (INT_SUM[385]) , .DATA_B (INT_SUM[386]) , .DATA_C (INT_SUM[387]) , .SAVE (INT_SUM[388]) , .CARRY (INT_CARRY[304]) );
FULL_ADDER FA_265 (.DATA_A (INT_CARRY[286]) , .DATA_B (INT_CARRY[287]) , .DATA_C (INT_CARRY[288]) , .SAVE (INT_SUM[390]) , .CARRY (INT_CARRY[306]) );
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[389]) );
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[391]) );
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[290]) );
FULL_ADDER FA_266 (.DATA_A (INT_SUM[389]) , .DATA_B (INT_SUM[391]) , .DATA_C (INT_CARRY[290]) , .SAVE (INT_SUM[392]) , .CARRY (INT_CARRY[308]) );
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[292]) );
assign INT_SUM[393] = INT_CARRY[292];
FULL_ADDER FA_267 (.DATA_A (INT_SUM[392]) , .DATA_B (INT_SUM[393]) , .DATA_C (INT_CARRY[293]) , .SAVE (SUM[35]) , .CARRY (CARRY[35]) );
FULL_ADDER FA_268 (.DATA_A (SUMMAND[352]) , .DATA_B (SUMMAND[353]) , .DATA_C (SUMMAND[354]) , .SAVE (INT_SUM[394]) , .CARRY (INT_CARRY[309]) );
FULL_ADDER FA_269 (.DATA_A (SUMMAND[355]) , .DATA_B (SUMMAND[356]) , .DATA_C (SUMMAND[357]) , .SAVE (INT_SUM[395]) , .CARRY (INT_CARRY[310]) );
FULL_ADDER FA_270 (.DATA_A (SUMMAND[358]) , .DATA_B (SUMMAND[359]) , .DATA_C (SUMMAND[360]) , .SAVE (INT_SUM[396]) , .CARRY (INT_CARRY[311]) );
FULL_ADDER FA_271 (.DATA_A (SUMMAND[361]) , .DATA_B (SUMMAND[362]) , .DATA_C (SUMMAND[363]) , .SAVE (INT_SUM[397]) , .CARRY (INT_CARRY[312]) );
FULL_ADDER FA_272 (.DATA_A (SUMMAND[364]) , .DATA_B (SUMMAND[365]) , .DATA_C (SUMMAND[366]) , .SAVE (INT_SUM[398]) , .CARRY (INT_CARRY[313]) );
FULL_ADDER FA_273 (.DATA_A (INT_SUM[394]) , .DATA_B (INT_SUM[395]) , .DATA_C (INT_SUM[396]) , .SAVE (INT_SUM[399]) , .CARRY (INT_CARRY[314]) );
FULL_ADDER FA_274 (.DATA_A (INT_SUM[397]) , .DATA_B (INT_SUM[398]) , .DATA_C (INT_CARRY[294]) , .SAVE (INT_SUM[400]) , .CARRY (INT_CARRY[315]) );
FULL_ADDER FA_275 (.DATA_A (INT_CARRY[295]) , .DATA_B (INT_CARRY[296]) , .DATA_C (INT_CARRY[297]) , .SAVE (INT_SUM[401]) , .CARRY (INT_CARRY[316]) );
assign INT_SUM[402] = INT_CARRY[298];
FULL_ADDER FA_276 (.DATA_A (INT_SUM[399]) , .DATA_B (INT_SUM[400]) , .DATA_C (INT_SUM[401]) , .SAVE (INT_SUM[403]) , .CARRY (INT_CARRY[317]) );
FULL_ADDER FA_277 (.DATA_A (INT_SUM[402]) , .DATA_B (INT_CARRY[299]) , .DATA_C (INT_CARRY[300]) , .SAVE (INT_SUM[404]) , .CARRY (INT_CARRY[318]) );
assign INT_SUM[405] = INT_CARRY[301];
FULL_ADDER FA_278 (.DATA_A (INT_SUM[403]) , .DATA_B (INT_SUM[404]) , .DATA_C (INT_SUM[405]) , .SAVE (INT_SUM[406]) , .CARRY (INT_CARRY[319]) );
HALF_ADDER HA_32 (.DATA_A (INT_CARRY[302]) , .DATA_B (INT_CARRY[303]) , .SAVE (INT_SUM[408]) , .CARRY (INT_CARRY[321]) );
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[407]) );
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[409]) );
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[305]) );
FULL_ADDER FA_279 (.DATA_A (INT_SUM[407]) , .DATA_B (INT_SUM[409]) , .DATA_C (INT_CARRY[305]) , .SAVE (INT_SUM[410]) , .CARRY (INT_CARRY[323]) );
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[307]) );
assign INT_SUM[411] = INT_CARRY[307];
FULL_ADDER FA_280 (.DATA_A (INT_SUM[410]) , .DATA_B (INT_SUM[411]) , .DATA_C (INT_CARRY[308]) , .SAVE (SUM[36]) , .CARRY (CARRY[36]) );
FULL_ADDER FA_281 (.DATA_A (SUMMAND[367]) , .DATA_B (SUMMAND[368]) , .DATA_C (SUMMAND[369]) , .SAVE (INT_SUM[412]) , .CARRY (INT_CARRY[324]) );
FULL_ADDER FA_282 (.DATA_A (SUMMAND[370]) , .DATA_B (SUMMAND[371]) , .DATA_C (SUMMAND[372]) , .SAVE (INT_SUM[413]) , .CARRY (INT_CARRY[325]) );
FULL_ADDER FA_283 (.DATA_A (SUMMAND[373]) , .DATA_B (SUMMAND[374]) , .DATA_C (SUMMAND[375]) , .SAVE (INT_SUM[414]) , .CARRY (INT_CARRY[326]) );
FULL_ADDER FA_284 (.DATA_A (SUMMAND[376]) , .DATA_B (SUMMAND[377]) , .DATA_C (SUMMAND[378]) , .SAVE (INT_SUM[415]) , .CARRY (INT_CARRY[327]) );
HALF_ADDER HA_33 (.DATA_A (SUMMAND[379]) , .DATA_B (SUMMAND[380]) , .SAVE (INT_SUM[416]) , .CARRY (INT_CARRY[328]) );
FULL_ADDER FA_285 (.DATA_A (INT_SUM[412]) , .DATA_B (INT_SUM[413]) , .DATA_C (INT_SUM[414]) , .SAVE (INT_SUM[417]) , .CARRY (INT_CARRY[329]) );
FULL_ADDER FA_286 (.DATA_A (INT_SUM[415]) , .DATA_B (INT_SUM[416]) , .DATA_C (INT_CARRY[309]) , .SAVE (INT_SUM[418]) , .CARRY (INT_CARRY[330]) );
FULL_ADDER FA_287 (.DATA_A (INT_CARRY[310]) , .DATA_B (INT_CARRY[311]) , .DATA_C (INT_CARRY[312]) , .SAVE (INT_SUM[419]) , .CARRY (INT_CARRY[331]) );
assign INT_SUM[420] = INT_CARRY[313];
FULL_ADDER FA_288 (.DATA_A (INT_SUM[417]) , .DATA_B (INT_SUM[418]) , .DATA_C (INT_SUM[419]) , .SAVE (INT_SUM[421]) , .CARRY (INT_CARRY[332]) );
FULL_ADDER FA_289 (.DATA_A (INT_SUM[420]) , .DATA_B (INT_CARRY[314]) , .DATA_C (INT_CARRY[315]) , .SAVE (INT_SUM[422]) , .CARRY (INT_CARRY[333]) );
assign INT_SUM[423] = INT_CARRY[316];
FULL_ADDER FA_290 (.DATA_A (INT_SUM[421]) , .DATA_B (INT_SUM[422]) , .DATA_C (INT_SUM[423]) , .SAVE (INT_SUM[424]) , .CARRY (INT_CARRY[334]) );
HALF_ADDER HA_34 (.DATA_A (INT_CARRY[317]) , .DATA_B (INT_CARRY[318]) , .SAVE (INT_SUM[426]) , .CARRY (INT_CARRY[336]) );
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[425]) );
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[427]) );
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[320]) );
FULL_ADDER FA_291 (.DATA_A (INT_SUM[425]) , .DATA_B (INT_SUM[427]) , .DATA_C (INT_CARRY[320]) , .SAVE (INT_SUM[428]) , .CARRY (INT_CARRY[338]) );
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[322]) );
assign INT_SUM[429] = INT_CARRY[322];
FULL_ADDER FA_292 (.DATA_A (INT_SUM[428]) , .DATA_B (INT_SUM[429]) , .DATA_C (INT_CARRY[323]) , .SAVE (SUM[37]) , .CARRY (CARRY[37]) );
FULL_ADDER FA_293 (.DATA_A (SUMMAND[381]) , .DATA_B (SUMMAND[382]) , .DATA_C (SUMMAND[383]) , .SAVE (INT_SUM[430]) , .CARRY (INT_CARRY[339]) );
FULL_ADDER FA_294 (.DATA_A (SUMMAND[384]) , .DATA_B (SUMMAND[385]) , .DATA_C (SUMMAND[386]) , .SAVE (INT_SUM[431]) , .CARRY (INT_CARRY[340]) );
FULL_ADDER FA_295 (.DATA_A (SUMMAND[387]) , .DATA_B (SUMMAND[388]) , .DATA_C (SUMMAND[389]) , .SAVE (INT_SUM[432]) , .CARRY (INT_CARRY[341]) );
FULL_ADDER FA_296 (.DATA_A (SUMMAND[390]) , .DATA_B (SUMMAND[391]) , .DATA_C (SUMMAND[392]) , .SAVE (INT_SUM[433]) , .CARRY (INT_CARRY[342]) );
HALF_ADDER HA_35 (.DATA_A (SUMMAND[393]) , .DATA_B (SUMMAND[394]) , .SAVE (INT_SUM[434]) , .CARRY (INT_CARRY[343]) );
FULL_ADDER FA_297 (.DATA_A (INT_SUM[430]) , .DATA_B (INT_SUM[431]) , .DATA_C (INT_SUM[432]) , .SAVE (INT_SUM[435]) , .CARRY (INT_CARRY[344]) );
FULL_ADDER FA_298 (.DATA_A (INT_SUM[433]) , .DATA_B (INT_SUM[434]) , .DATA_C (INT_CARRY[324]) , .SAVE (INT_SUM[436]) , .CARRY (INT_CARRY[345]) );
FULL_ADDER FA_299 (.DATA_A (INT_CARRY[325]) , .DATA_B (INT_CARRY[326]) , .DATA_C (INT_CARRY[327]) , .SAVE (INT_SUM[437]) , .CARRY (INT_CARRY[346]) );
assign INT_SUM[438] = INT_CARRY[328];
FULL_ADDER FA_300 (.DATA_A (INT_SUM[435]) , .DATA_B (INT_SUM[436]) , .DATA_C (INT_SUM[437]) , .SAVE (INT_SUM[439]) , .CARRY (INT_CARRY[347]) );
FULL_ADDER FA_301 (.DATA_A (INT_SUM[438]) , .DATA_B (INT_CARRY[329]) , .DATA_C (INT_CARRY[330]) , .SAVE (INT_SUM[440]) , .CARRY (INT_CARRY[348]) );
assign INT_SUM[441] = INT_CARRY[331];
FULL_ADDER FA_302 (.DATA_A (INT_SUM[439]) , .DATA_B (INT_SUM[440]) , .DATA_C (INT_SUM[441]) , .SAVE (INT_SUM[442]) , .CARRY (INT_CARRY[349]) );
HALF_ADDER HA_36 (.DATA_A (INT_CARRY[332]) , .DATA_B (INT_CARRY[333]) , .SAVE (INT_SUM[444]) , .CARRY (INT_CARRY[351]) );
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[443]) );
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[445]) );
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[335]) );
FULL_ADDER FA_303 (.DATA_A (INT_SUM[443]) , .DATA_B (INT_SUM[445]) , .DATA_C (INT_CARRY[335]) , .SAVE (INT_SUM[446]) , .CARRY (INT_CARRY[353]) );
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[337]) );
assign INT_SUM[447] = INT_CARRY[337];
FULL_ADDER FA_304 (.DATA_A (INT_SUM[446]) , .DATA_B (INT_SUM[447]) , .DATA_C (INT_CARRY[338]) , .SAVE (SUM[38]) , .CARRY (CARRY[38]) );
FULL_ADDER FA_305 (.DATA_A (SUMMAND[395]) , .DATA_B (SUMMAND[396]) , .DATA_C (SUMMAND[397]) , .SAVE (INT_SUM[448]) , .CARRY (INT_CARRY[354]) );
FULL_ADDER FA_306 (.DATA_A (SUMMAND[398]) , .DATA_B (SUMMAND[399]) , .DATA_C (SUMMAND[400]) , .SAVE (INT_SUM[449]) , .CARRY (INT_CARRY[355]) );
FULL_ADDER FA_307 (.DATA_A (SUMMAND[401]) , .DATA_B (SUMMAND[402]) , .DATA_C (SUMMAND[403]) , .SAVE (INT_SUM[450]) , .CARRY (INT_CARRY[356]) );
FULL_ADDER FA_308 (.DATA_A (SUMMAND[404]) , .DATA_B (SUMMAND[405]) , .DATA_C (SUMMAND[406]) , .SAVE (INT_SUM[451]) , .CARRY (INT_CARRY[357]) );
assign INT_SUM[452] = SUMMAND[407];
FULL_ADDER FA_309 (.DATA_A (INT_SUM[448]) , .DATA_B (INT_SUM[449]) , .DATA_C (INT_SUM[450]) , .SAVE (INT_SUM[453]) , .CARRY (INT_CARRY[358]) );
FULL_ADDER FA_310 (.DATA_A (INT_SUM[451]) , .DATA_B (INT_SUM[452]) , .DATA_C (INT_CARRY[339]) , .SAVE (INT_SUM[454]) , .CARRY (INT_CARRY[359]) );
FULL_ADDER FA_311 (.DATA_A (INT_CARRY[340]) , .DATA_B (INT_CARRY[341]) , .DATA_C (INT_CARRY[342]) , .SAVE (INT_SUM[455]) , .CARRY (INT_CARRY[360]) );
assign INT_SUM[456] = INT_CARRY[343];
FULL_ADDER FA_312 (.DATA_A (INT_SUM[453]) , .DATA_B (INT_SUM[454]) , .DATA_C (INT_SUM[455]) , .SAVE (INT_SUM[457]) , .CARRY (INT_CARRY[361]) );
FULL_ADDER FA_313 (.DATA_A (INT_SUM[456]) , .DATA_B (INT_CARRY[344]) , .DATA_C (INT_CARRY[345]) , .SAVE (INT_SUM[458]) , .CARRY (INT_CARRY[362]) );
assign INT_SUM[459] = INT_CARRY[346];
FULL_ADDER FA_314 (.DATA_A (INT_SUM[457]) , .DATA_B (INT_SUM[458]) , .DATA_C (INT_SUM[459]) , .SAVE (INT_SUM[460]) , .CARRY (INT_CARRY[363]) );
HALF_ADDER HA_37 (.DATA_A (INT_CARRY[347]) , .DATA_B (INT_CARRY[348]) , .SAVE (INT_SUM[462]) , .CARRY (INT_CARRY[365]) );
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[461]) );
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[463]) );
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[350]) );
FULL_ADDER FA_315 (.DATA_A (INT_SUM[461]) , .DATA_B (INT_SUM[463]) , .DATA_C (INT_CARRY[350]) , .SAVE (INT_SUM[464]) , .CARRY (INT_CARRY[367]) );
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[352]) );
assign INT_SUM[465] = INT_CARRY[352];
FULL_ADDER FA_316 (.DATA_A (INT_SUM[464]) , .DATA_B (INT_SUM[465]) , .DATA_C (INT_CARRY[353]) , .SAVE (SUM[39]) , .CARRY (CARRY[39]) );
FULL_ADDER FA_317 (.DATA_A (SUMMAND[408]) , .DATA_B (SUMMAND[409]) , .DATA_C (SUMMAND[410]) , .SAVE (INT_SUM[466]) , .CARRY (INT_CARRY[368]) );
FULL_ADDER FA_318 (.DATA_A (SUMMAND[411]) , .DATA_B (SUMMAND[412]) , .DATA_C (SUMMAND[413]) , .SAVE (INT_SUM[467]) , .CARRY (INT_CARRY[369]) );
FULL_ADDER FA_319 (.DATA_A (SUMMAND[414]) , .DATA_B (SUMMAND[415]) , .DATA_C (SUMMAND[416]) , .SAVE (INT_SUM[468]) , .CARRY (INT_CARRY[370]) );
FULL_ADDER FA_320 (.DATA_A (SUMMAND[417]) , .DATA_B (SUMMAND[418]) , .DATA_C (SUMMAND[419]) , .SAVE (INT_SUM[469]) , .CARRY (INT_CARRY[371]) );
FULL_ADDER FA_321 (.DATA_A (SUMMAND[420]) , .DATA_B (INT_CARRY[354]) , .DATA_C (INT_CARRY[355]) , .SAVE (INT_SUM[470]) , .CARRY (INT_CARRY[372]) );
assign INT_SUM[471] = INT_CARRY[356];
assign INT_SUM[472] = INT_CARRY[357];
FULL_ADDER FA_322 (.DATA_A (INT_SUM[466]) , .DATA_B (INT_SUM[467]) , .DATA_C (INT_SUM[468]) , .SAVE (INT_SUM[473]) , .CARRY (INT_CARRY[373]) );
FULL_ADDER FA_323 (.DATA_A (INT_SUM[469]) , .DATA_B (INT_SUM[470]) , .DATA_C (INT_SUM[471]) , .SAVE (INT_SUM[474]) , .CARRY (INT_CARRY[374]) );
FULL_ADDER FA_324 (.DATA_A (INT_SUM[472]) , .DATA_B (INT_CARRY[358]) , .DATA_C (INT_CARRY[359]) , .SAVE (INT_SUM[475]) , .CARRY (INT_CARRY[375]) );
assign INT_SUM[476] = INT_CARRY[360];
FULL_ADDER FA_325 (.DATA_A (INT_SUM[473]) , .DATA_B (INT_SUM[474]) , .DATA_C (INT_SUM[475]) , .SAVE (INT_SUM[477]) , .CARRY (INT_CARRY[376]) );
FULL_ADDER FA_326 (.DATA_A (INT_SUM[476]) , .DATA_B (INT_CARRY[361]) , .DATA_C (INT_CARRY[362]) , .SAVE (INT_SUM[479]) , .CARRY (INT_CARRY[378]) );
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[478]) );
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[480]) );
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[364]) );
FULL_ADDER FA_327 (.DATA_A (INT_SUM[478]) , .DATA_B (INT_SUM[480]) , .DATA_C (INT_CARRY[364]) , .SAVE (INT_SUM[481]) , .CARRY (INT_CARRY[380]) );
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[366]) );
assign INT_SUM[482] = INT_CARRY[366];
FULL_ADDER FA_328 (.DATA_A (INT_SUM[481]) , .DATA_B (INT_SUM[482]) , .DATA_C (INT_CARRY[367]) , .SAVE (SUM[40]) , .CARRY (CARRY[40]) );
FULL_ADDER FA_329 (.DATA_A (SUMMAND[421]) , .DATA_B (SUMMAND[422]) , .DATA_C (SUMMAND[423]) , .SAVE (INT_SUM[483]) , .CARRY (INT_CARRY[381]) );
FULL_ADDER FA_330 (.DATA_A (SUMMAND[424]) , .DATA_B (SUMMAND[425]) , .DATA_C (SUMMAND[426]) , .SAVE (INT_SUM[484]) , .CARRY (INT_CARRY[382]) );
FULL_ADDER FA_331 (.DATA_A (SUMMAND[427]) , .DATA_B (SUMMAND[428]) , .DATA_C (SUMMAND[429]) , .SAVE (INT_SUM[485]) , .CARRY (INT_CARRY[383]) );
FULL_ADDER FA_332 (.DATA_A (SUMMAND[430]) , .DATA_B (SUMMAND[431]) , .DATA_C (SUMMAND[432]) , .SAVE (INT_SUM[486]) , .CARRY (INT_CARRY[384]) );
FULL_ADDER FA_333 (.DATA_A (INT_SUM[483]) , .DATA_B (INT_SUM[484]) , .DATA_C (INT_SUM[485]) , .SAVE (INT_SUM[487]) , .CARRY (INT_CARRY[385]) );
FULL_ADDER FA_334 (.DATA_A (INT_SUM[486]) , .DATA_B (INT_CARRY[368]) , .DATA_C (INT_CARRY[369]) , .SAVE (INT_SUM[488]) , .CARRY (INT_CARRY[386]) );
FULL_ADDER FA_335 (.DATA_A (INT_CARRY[370]) , .DATA_B (INT_CARRY[371]) , .DATA_C (INT_CARRY[372]) , .SAVE (INT_SUM[489]) , .CARRY (INT_CARRY[387]) );
FULL_ADDER FA_336 (.DATA_A (INT_SUM[487]) , .DATA_B (INT_SUM[488]) , .DATA_C (INT_SUM[489]) , .SAVE (INT_SUM[490]) , .CARRY (INT_CARRY[388]) );
FULL_ADDER FA_337 (.DATA_A (INT_CARRY[373]) , .DATA_B (INT_CARRY[374]) , .DATA_C (INT_CARRY[375]) , .SAVE (INT_SUM[492]) , .CARRY (INT_CARRY[390]) );
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[491]) );
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[493]) );
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[377]) );
FULL_ADDER FA_338 (.DATA_A (INT_SUM[491]) , .DATA_B (INT_SUM[493]) , .DATA_C (INT_CARRY[377]) , .SAVE (INT_SUM[494]) , .CARRY (INT_CARRY[392]) );
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[379]) );
assign INT_SUM[495] = INT_CARRY[379];
FULL_ADDER FA_339 (.DATA_A (INT_SUM[494]) , .DATA_B (INT_SUM[495]) , .DATA_C (INT_CARRY[380]) , .SAVE (SUM[41]) , .CARRY (CARRY[41]) );
FULL_ADDER FA_340 (.DATA_A (SUMMAND[433]) , .DATA_B (SUMMAND[434]) , .DATA_C (SUMMAND[435]) , .SAVE (INT_SUM[496]) , .CARRY (INT_CARRY[393]) );
FULL_ADDER FA_341 (.DATA_A (SUMMAND[436]) , .DATA_B (SUMMAND[437]) , .DATA_C (SUMMAND[438]) , .SAVE (INT_SUM[497]) , .CARRY (INT_CARRY[394]) );
FULL_ADDER FA_342 (.DATA_A (SUMMAND[439]) , .DATA_B (SUMMAND[440]) , .DATA_C (SUMMAND[441]) , .SAVE (INT_SUM[498]) , .CARRY (INT_CARRY[395]) );
FULL_ADDER FA_343 (.DATA_A (SUMMAND[442]) , .DATA_B (SUMMAND[443]) , .DATA_C (SUMMAND[444]) , .SAVE (INT_SUM[499]) , .CARRY (INT_CARRY[396]) );
FULL_ADDER FA_344 (.DATA_A (INT_SUM[496]) , .DATA_B (INT_SUM[497]) , .DATA_C (INT_SUM[498]) , .SAVE (INT_SUM[500]) , .CARRY (INT_CARRY[397]) );
FULL_ADDER FA_345 (.DATA_A (INT_SUM[499]) , .DATA_B (INT_CARRY[381]) , .DATA_C (INT_CARRY[382]) , .SAVE (INT_SUM[501]) , .CARRY (INT_CARRY[398]) );
HALF_ADDER HA_38 (.DATA_A (INT_CARRY[383]) , .DATA_B (INT_CARRY[384]) , .SAVE (INT_SUM[502]) , .CARRY (INT_CARRY[399]) );
FULL_ADDER FA_346 (.DATA_A (INT_SUM[500]) , .DATA_B (INT_SUM[501]) , .DATA_C (INT_SUM[502]) , .SAVE (INT_SUM[503]) , .CARRY (INT_CARRY[400]) );
FULL_ADDER FA_347 (.DATA_A (INT_CARRY[385]) , .DATA_B (INT_CARRY[386]) , .DATA_C (INT_CARRY[387]) , .SAVE (INT_SUM[505]) , .CARRY (INT_CARRY[402]) );
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[504]) );
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[506]) );
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[389]) );
FULL_ADDER FA_348 (.DATA_A (INT_SUM[504]) , .DATA_B (INT_SUM[506]) , .DATA_C (INT_CARRY[389]) , .SAVE (INT_SUM[507]) , .CARRY (INT_CARRY[404]) );
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[391]) );
assign INT_SUM[508] = INT_CARRY[391];
FULL_ADDER FA_349 (.DATA_A (INT_SUM[507]) , .DATA_B (INT_SUM[508]) , .DATA_C (INT_CARRY[392]) , .SAVE (SUM[42]) , .CARRY (CARRY[42]) );
FULL_ADDER FA_350 (.DATA_A (SUMMAND[445]) , .DATA_B (SUMMAND[446]) , .DATA_C (SUMMAND[447]) , .SAVE (INT_SUM[509]) , .CARRY (INT_CARRY[405]) );
FULL_ADDER FA_351 (.DATA_A (SUMMAND[448]) , .DATA_B (SUMMAND[449]) , .DATA_C (SUMMAND[450]) , .SAVE (INT_SUM[510]) , .CARRY (INT_CARRY[406]) );
FULL_ADDER FA_352 (.DATA_A (SUMMAND[451]) , .DATA_B (SUMMAND[452]) , .DATA_C (SUMMAND[453]) , .SAVE (INT_SUM[511]) , .CARRY (INT_CARRY[407]) );
assign INT_SUM[512] = SUMMAND[454];
assign INT_SUM[513] = SUMMAND[455];
FULL_ADDER FA_353 (.DATA_A (INT_SUM[509]) , .DATA_B (INT_SUM[510]) , .DATA_C (INT_SUM[511]) , .SAVE (INT_SUM[514]) , .CARRY (INT_CARRY[408]) );
FULL_ADDER FA_354 (.DATA_A (INT_SUM[512]) , .DATA_B (INT_SUM[513]) , .DATA_C (INT_CARRY[393]) , .SAVE (INT_SUM[515]) , .CARRY (INT_CARRY[409]) );
FULL_ADDER FA_355 (.DATA_A (INT_CARRY[394]) , .DATA_B (INT_CARRY[395]) , .DATA_C (INT_CARRY[396]) , .SAVE (INT_SUM[516]) , .CARRY (INT_CARRY[410]) );
FULL_ADDER FA_356 (.DATA_A (INT_SUM[514]) , .DATA_B (INT_SUM[515]) , .DATA_C (INT_SUM[516]) , .SAVE (INT_SUM[517]) , .CARRY (INT_CARRY[411]) );
FULL_ADDER FA_357 (.DATA_A (INT_CARRY[397]) , .DATA_B (INT_CARRY[398]) , .DATA_C (INT_CARRY[399]) , .SAVE (INT_SUM[519]) , .CARRY (INT_CARRY[413]) );
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[518]) );
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[520]) );
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[401]) );
FULL_ADDER FA_358 (.DATA_A (INT_SUM[518]) , .DATA_B (INT_SUM[520]) , .DATA_C (INT_CARRY[401]) , .SAVE (INT_SUM[521]) , .CARRY (INT_CARRY[415]) );
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[403]) );
assign INT_SUM[522] = INT_CARRY[403];
FULL_ADDER FA_359 (.DATA_A (INT_SUM[521]) , .DATA_B (INT_SUM[522]) , .DATA_C (INT_CARRY[404]) , .SAVE (SUM[43]) , .CARRY (CARRY[43]) );
FULL_ADDER FA_360 (.DATA_A (SUMMAND[456]) , .DATA_B (SUMMAND[457]) , .DATA_C (SUMMAND[458]) , .SAVE (INT_SUM[523]) , .CARRY (INT_CARRY[416]) );
FULL_ADDER FA_361 (.DATA_A (SUMMAND[459]) , .DATA_B (SUMMAND[460]) , .DATA_C (SUMMAND[461]) , .SAVE (INT_SUM[524]) , .CARRY (INT_CARRY[417]) );
FULL_ADDER FA_362 (.DATA_A (SUMMAND[462]) , .DATA_B (SUMMAND[463]) , .DATA_C (SUMMAND[464]) , .SAVE (INT_SUM[525]) , .CARRY (INT_CARRY[418]) );
HALF_ADDER HA_39 (.DATA_A (SUMMAND[465]) , .DATA_B (SUMMAND[466]) , .SAVE (INT_SUM[526]) , .CARRY (INT_CARRY[419]) );
FULL_ADDER FA_363 (.DATA_A (INT_SUM[523]) , .DATA_B (INT_SUM[524]) , .DATA_C (INT_SUM[525]) , .SAVE (INT_SUM[527]) , .CARRY (INT_CARRY[420]) );
FULL_ADDER FA_364 (.DATA_A (INT_SUM[526]) , .DATA_B (INT_CARRY[405]) , .DATA_C (INT_CARRY[406]) , .SAVE (INT_SUM[528]) , .CARRY (INT_CARRY[421]) );
assign INT_SUM[529] = INT_CARRY[407];
FULL_ADDER FA_365 (.DATA_A (INT_SUM[527]) , .DATA_B (INT_SUM[528]) , .DATA_C (INT_SUM[529]) , .SAVE (INT_SUM[530]) , .CARRY (INT_CARRY[422]) );
FULL_ADDER FA_366 (.DATA_A (INT_CARRY[408]) , .DATA_B (INT_CARRY[409]) , .DATA_C (INT_CARRY[410]) , .SAVE (INT_SUM[532]) , .CARRY (INT_CARRY[424]) );
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[531]) );
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[533]) );
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[412]) );
FULL_ADDER FA_367 (.DATA_A (INT_SUM[531]) , .DATA_B (INT_SUM[533]) , .DATA_C (INT_CARRY[412]) , .SAVE (INT_SUM[534]) , .CARRY (INT_CARRY[426]) );
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[414]) );
assign INT_SUM[535] = INT_CARRY[414];
FULL_ADDER FA_368 (.DATA_A (INT_SUM[534]) , .DATA_B (INT_SUM[535]) , .DATA_C (INT_CARRY[415]) , .SAVE (SUM[44]) , .CARRY (CARRY[44]) );
FULL_ADDER FA_369 (.DATA_A (SUMMAND[467]) , .DATA_B (SUMMAND[468]) , .DATA_C (SUMMAND[469]) , .SAVE (INT_SUM[536]) , .CARRY (INT_CARRY[427]) );
FULL_ADDER FA_370 (.DATA_A (SUMMAND[470]) , .DATA_B (SUMMAND[471]) , .DATA_C (SUMMAND[472]) , .SAVE (INT_SUM[537]) , .CARRY (INT_CARRY[428]) );
FULL_ADDER FA_371 (.DATA_A (SUMMAND[473]) , .DATA_B (SUMMAND[474]) , .DATA_C (SUMMAND[475]) , .SAVE (INT_SUM[538]) , .CARRY (INT_CARRY[429]) );
assign INT_SUM[539] = SUMMAND[476];
FULL_ADDER FA_372 (.DATA_A (INT_SUM[536]) , .DATA_B (INT_SUM[537]) , .DATA_C (INT_SUM[538]) , .SAVE (INT_SUM[540]) , .CARRY (INT_CARRY[430]) );
FULL_ADDER FA_373 (.DATA_A (INT_SUM[539]) , .DATA_B (INT_CARRY[416]) , .DATA_C (INT_CARRY[417]) , .SAVE (INT_SUM[541]) , .CARRY (INT_CARRY[431]) );
assign INT_SUM[542] = INT_CARRY[418];
assign INT_SUM[543] = INT_CARRY[419];
FULL_ADDER FA_374 (.DATA_A (INT_SUM[540]) , .DATA_B (INT_SUM[541]) , .DATA_C (INT_SUM[542]) , .SAVE (INT_SUM[544]) , .CARRY (INT_CARRY[432]) );
FULL_ADDER FA_375 (.DATA_A (INT_SUM[543]) , .DATA_B (INT_CARRY[420]) , .DATA_C (INT_CARRY[421]) , .SAVE (INT_SUM[546]) , .CARRY (INT_CARRY[434]) );
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[545]) );
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[547]) );
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[423]) );
FULL_ADDER FA_376 (.DATA_A (INT_SUM[545]) , .DATA_B (INT_SUM[547]) , .DATA_C (INT_CARRY[423]) , .SAVE (INT_SUM[548]) , .CARRY (INT_CARRY[436]) );
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[425]) );
assign INT_SUM[549] = INT_CARRY[425];
FULL_ADDER FA_377 (.DATA_A (INT_SUM[548]) , .DATA_B (INT_SUM[549]) , .DATA_C (INT_CARRY[426]) , .SAVE (SUM[45]) , .CARRY (CARRY[45]) );
FULL_ADDER FA_378 (.DATA_A (SUMMAND[477]) , .DATA_B (SUMMAND[478]) , .DATA_C (SUMMAND[479]) , .SAVE (INT_SUM[550]) , .CARRY (INT_CARRY[437]) );
FULL_ADDER FA_379 (.DATA_A (SUMMAND[480]) , .DATA_B (SUMMAND[481]) , .DATA_C (SUMMAND[482]) , .SAVE (INT_SUM[551]) , .CARRY (INT_CARRY[438]) );
FULL_ADDER FA_380 (.DATA_A (SUMMAND[483]) , .DATA_B (SUMMAND[484]) , .DATA_C (SUMMAND[485]) , .SAVE (INT_SUM[552]) , .CARRY (INT_CARRY[439]) );
assign INT_SUM[553] = SUMMAND[486];
FULL_ADDER FA_381 (.DATA_A (INT_SUM[550]) , .DATA_B (INT_SUM[551]) , .DATA_C (INT_SUM[552]) , .SAVE (INT_SUM[554]) , .CARRY (INT_CARRY[440]) );
FULL_ADDER FA_382 (.DATA_A (INT_SUM[553]) , .DATA_B (INT_CARRY[427]) , .DATA_C (INT_CARRY[428]) , .SAVE (INT_SUM[555]) , .CARRY (INT_CARRY[441]) );
assign INT_SUM[556] = INT_CARRY[429];
FULL_ADDER FA_383 (.DATA_A (INT_SUM[554]) , .DATA_B (INT_SUM[555]) , .DATA_C (INT_SUM[556]) , .SAVE (INT_SUM[557]) , .CARRY (INT_CARRY[442]) );
HALF_ADDER HA_40 (.DATA_A (INT_CARRY[430]) , .DATA_B (INT_CARRY[431]) , .SAVE (INT_SUM[559]) , .CARRY (INT_CARRY[444]) );
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[558]) );
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[560]) );
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[433]) );
FULL_ADDER FA_384 (.DATA_A (INT_SUM[558]) , .DATA_B (INT_SUM[560]) , .DATA_C (INT_CARRY[433]) , .SAVE (INT_SUM[561]) , .CARRY (INT_CARRY[446]) );
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[435]) );
assign INT_SUM[562] = INT_CARRY[435];
FULL_ADDER FA_385 (.DATA_A (INT_SUM[561]) , .DATA_B (INT_SUM[562]) , .DATA_C (INT_CARRY[436]) , .SAVE (SUM[46]) , .CARRY (CARRY[46]) );
FULL_ADDER FA_386 (.DATA_A (SUMMAND[487]) , .DATA_B (SUMMAND[488]) , .DATA_C (SUMMAND[489]) , .SAVE (INT_SUM[563]) , .CARRY (INT_CARRY[447]) );
FULL_ADDER FA_387 (.DATA_A (SUMMAND[490]) , .DATA_B (SUMMAND[491]) , .DATA_C (SUMMAND[492]) , .SAVE (INT_SUM[564]) , .CARRY (INT_CARRY[448]) );
FULL_ADDER FA_388 (.DATA_A (SUMMAND[493]) , .DATA_B (SUMMAND[494]) , .DATA_C (SUMMAND[495]) , .SAVE (INT_SUM[565]) , .CARRY (INT_CARRY[449]) );
FULL_ADDER FA_389 (.DATA_A (INT_SUM[563]) , .DATA_B (INT_SUM[564]) , .DATA_C (INT_SUM[565]) , .SAVE (INT_SUM[566]) , .CARRY (INT_CARRY[450]) );
FULL_ADDER FA_390 (.DATA_A (INT_CARRY[437]) , .DATA_B (INT_CARRY[438]) , .DATA_C (INT_CARRY[439]) , .SAVE (INT_SUM[567]) , .CARRY (INT_CARRY[451]) );
FULL_ADDER FA_391 (.DATA_A (INT_SUM[566]) , .DATA_B (INT_SUM[567]) , .DATA_C (INT_CARRY[440]) , .SAVE (INT_SUM[568]) , .CARRY (INT_CARRY[452]) );
assign INT_SUM[570] = INT_CARRY[441];
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[569]) );
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[571]) );
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[443]) );
FULL_ADDER FA_392 (.DATA_A (INT_SUM[569]) , .DATA_B (INT_SUM[571]) , .DATA_C (INT_CARRY[443]) , .SAVE (INT_SUM[572]) , .CARRY (INT_CARRY[454]) );
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[445]) );
assign INT_SUM[573] = INT_CARRY[445];
FULL_ADDER FA_393 (.DATA_A (INT_SUM[572]) , .DATA_B (INT_SUM[573]) , .DATA_C (INT_CARRY[446]) , .SAVE (SUM[47]) , .CARRY (CARRY[47]) );
FULL_ADDER FA_394 (.DATA_A (SUMMAND[496]) , .DATA_B (SUMMAND[497]) , .DATA_C (SUMMAND[498]) , .SAVE (INT_SUM[574]) , .CARRY (INT_CARRY[455]) );
FULL_ADDER FA_395 (.DATA_A (SUMMAND[499]) , .DATA_B (SUMMAND[500]) , .DATA_C (SUMMAND[501]) , .SAVE (INT_SUM[575]) , .CARRY (INT_CARRY[456]) );
FULL_ADDER FA_396 (.DATA_A (SUMMAND[502]) , .DATA_B (SUMMAND[503]) , .DATA_C (SUMMAND[504]) , .SAVE (INT_SUM[576]) , .CARRY (INT_CARRY[457]) );
FULL_ADDER FA_397 (.DATA_A (INT_SUM[574]) , .DATA_B (INT_SUM[575]) , .DATA_C (INT_SUM[576]) , .SAVE (INT_SUM[577]) , .CARRY (INT_CARRY[458]) );
FULL_ADDER FA_398 (.DATA_A (INT_CARRY[447]) , .DATA_B (INT_CARRY[448]) , .DATA_C (INT_CARRY[449]) , .SAVE (INT_SUM[578]) , .CARRY (INT_CARRY[459]) );
FULL_ADDER FA_399 (.DATA_A (INT_SUM[577]) , .DATA_B (INT_SUM[578]) , .DATA_C (INT_CARRY[450]) , .SAVE (INT_SUM[579]) , .CARRY (INT_CARRY[460]) );
assign INT_SUM[581] = INT_CARRY[451];
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[580]) );
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[582]) );
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[453]) );
FULL_ADDER FA_400 (.DATA_A (INT_SUM[580]) , .DATA_B (INT_SUM[582]) , .DATA_C (INT_CARRY[453]) , .SAVE (INT_SUM[583]) , .CARRY (INT_CARRY[462]) );
HALF_ADDER HA_41 (.DATA_A (INT_SUM[583]) , .DATA_B (INT_CARRY[454]) , .SAVE (SUM[48]) , .CARRY (CARRY[48]) );
FULL_ADDER FA_401 (.DATA_A (SUMMAND[505]) , .DATA_B (SUMMAND[506]) , .DATA_C (SUMMAND[507]) , .SAVE (INT_SUM[584]) , .CARRY (INT_CARRY[463]) );
FULL_ADDER FA_402 (.DATA_A (SUMMAND[508]) , .DATA_B (SUMMAND[509]) , .DATA_C (SUMMAND[510]) , .SAVE (INT_SUM[585]) , .CARRY (INT_CARRY[464]) );
FULL_ADDER FA_403 (.DATA_A (SUMMAND[511]) , .DATA_B (SUMMAND[512]) , .DATA_C (INT_CARRY[455]) , .SAVE (INT_SUM[586]) , .CARRY (INT_CARRY[465]) );
HALF_ADDER HA_42 (.DATA_A (INT_CARRY[456]) , .DATA_B (INT_CARRY[457]) , .SAVE (INT_SUM[587]) , .CARRY (INT_CARRY[466]) );
FULL_ADDER FA_404 (.DATA_A (INT_SUM[584]) , .DATA_B (INT_SUM[585]) , .DATA_C (INT_SUM[586]) , .SAVE (INT_SUM[588]) , .CARRY (INT_CARRY[467]) );
FULL_ADDER FA_405 (.DATA_A (INT_SUM[587]) , .DATA_B (INT_CARRY[458]) , .DATA_C (INT_CARRY[459]) , .SAVE (INT_SUM[590]) , .CARRY (INT_CARRY[469]) );
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[589]) );
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[591]) );
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[461]) );
FULL_ADDER FA_406 (.DATA_A (INT_SUM[589]) , .DATA_B (INT_SUM[591]) , .DATA_C (INT_CARRY[461]) , .SAVE (INT_SUM[592]) , .CARRY (INT_CARRY[471]) );
HALF_ADDER HA_43 (.DATA_A (INT_SUM[592]) , .DATA_B (INT_CARRY[462]) , .SAVE (SUM[49]) , .CARRY (CARRY[49]) );
FULL_ADDER FA_407 (.DATA_A (SUMMAND[513]) , .DATA_B (SUMMAND[514]) , .DATA_C (SUMMAND[515]) , .SAVE (INT_SUM[593]) , .CARRY (INT_CARRY[472]) );
FULL_ADDER FA_408 (.DATA_A (SUMMAND[516]) , .DATA_B (SUMMAND[517]) , .DATA_C (SUMMAND[518]) , .SAVE (INT_SUM[594]) , .CARRY (INT_CARRY[473]) );
assign INT_SUM[595] = SUMMAND[519];
assign INT_SUM[596] = SUMMAND[520];
FULL_ADDER FA_409 (.DATA_A (INT_SUM[593]) , .DATA_B (INT_SUM[594]) , .DATA_C (INT_SUM[595]) , .SAVE (INT_SUM[597]) , .CARRY (INT_CARRY[474]) );
assign INT_SUM[598] = INT_SUM[596];
FULL_ADDER FA_410 (.DATA_A (INT_SUM[597]) , .DATA_B (INT_SUM[598]) , .DATA_C (INT_CARRY[463]) , .SAVE (INT_SUM[599]) , .CARRY (INT_CARRY[475]) );
FULL_ADDER FA_411 (.DATA_A (INT_CARRY[464]) , .DATA_B (INT_CARRY[465]) , .DATA_C (INT_CARRY[466]) , .SAVE (INT_SUM[601]) , .CARRY (INT_CARRY[477]) );
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[600]) );
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[602]) );
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[468]) );
FULL_ADDER FA_412 (.DATA_A (INT_SUM[600]) , .DATA_B (INT_SUM[602]) , .DATA_C (INT_CARRY[468]) , .SAVE (INT_SUM[603]) , .CARRY (INT_CARRY[479]) );
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[470]) );
assign INT_SUM[604] = INT_CARRY[470];
FULL_ADDER FA_413 (.DATA_A (INT_SUM[603]) , .DATA_B (INT_SUM[604]) , .DATA_C (INT_CARRY[471]) , .SAVE (SUM[50]) , .CARRY (CARRY[50]) );
FULL_ADDER FA_414 (.DATA_A (SUMMAND[521]) , .DATA_B (SUMMAND[522]) , .DATA_C (SUMMAND[523]) , .SAVE (INT_SUM[605]) , .CARRY (INT_CARRY[480]) );
FULL_ADDER FA_415 (.DATA_A (SUMMAND[524]) , .DATA_B (SUMMAND[525]) , .DATA_C (SUMMAND[526]) , .SAVE (INT_SUM[606]) , .CARRY (INT_CARRY[481]) );
FULL_ADDER FA_416 (.DATA_A (SUMMAND[527]) , .DATA_B (INT_CARRY[472]) , .DATA_C (INT_CARRY[473]) , .SAVE (INT_SUM[607]) , .CARRY (INT_CARRY[482]) );
FULL_ADDER FA_417 (.DATA_A (INT_SUM[605]) , .DATA_B (INT_SUM[606]) , .DATA_C (INT_SUM[607]) , .SAVE (INT_SUM[608]) , .CARRY (INT_CARRY[483]) );
assign INT_SUM[610] = INT_CARRY[474];
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[609]) );
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[611]) );
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[476]) );
FULL_ADDER FA_418 (.DATA_A (INT_SUM[609]) , .DATA_B (INT_SUM[611]) , .DATA_C (INT_CARRY[476]) , .SAVE (INT_SUM[612]) , .CARRY (INT_CARRY[485]) );
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[478]) );
assign INT_SUM[613] = INT_CARRY[478];
FULL_ADDER FA_419 (.DATA_A (INT_SUM[612]) , .DATA_B (INT_SUM[613]) , .DATA_C (INT_CARRY[479]) , .SAVE (SUM[51]) , .CARRY (CARRY[51]) );
FULL_ADDER FA_420 (.DATA_A (SUMMAND[528]) , .DATA_B (SUMMAND[529]) , .DATA_C (SUMMAND[530]) , .SAVE (INT_SUM[614]) , .CARRY (INT_CARRY[486]) );
FULL_ADDER FA_421 (.DATA_A (SUMMAND[531]) , .DATA_B (SUMMAND[532]) , .DATA_C (SUMMAND[533]) , .SAVE (INT_SUM[615]) , .CARRY (INT_CARRY[487]) );
assign INT_SUM[616] = SUMMAND[534];
FULL_ADDER FA_422 (.DATA_A (INT_SUM[614]) , .DATA_B (INT_SUM[615]) , .DATA_C (INT_SUM[616]) , .SAVE (INT_SUM[617]) , .CARRY (INT_CARRY[488]) );
FULL_ADDER FA_423 (.DATA_A (INT_CARRY[480]) , .DATA_B (INT_CARRY[481]) , .DATA_C (INT_CARRY[482]) , .SAVE (INT_SUM[619]) , .CARRY (INT_CARRY[490]) );
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[618]) );
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[620]) );
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[484]) );
FULL_ADDER FA_424 (.DATA_A (INT_SUM[618]) , .DATA_B (INT_SUM[620]) , .DATA_C (INT_CARRY[484]) , .SAVE (INT_SUM[621]) , .CARRY (INT_CARRY[492]) );
HALF_ADDER HA_44 (.DATA_A (INT_SUM[621]) , .DATA_B (INT_CARRY[485]) , .SAVE (SUM[52]) , .CARRY (CARRY[52]) );
FULL_ADDER FA_425 (.DATA_A (SUMMAND[535]) , .DATA_B (SUMMAND[536]) , .DATA_C (SUMMAND[537]) , .SAVE (INT_SUM[622]) , .CARRY (INT_CARRY[493]) );
FULL_ADDER FA_426 (.DATA_A (SUMMAND[538]) , .DATA_B (SUMMAND[539]) , .DATA_C (SUMMAND[540]) , .SAVE (INT_SUM[623]) , .CARRY (INT_CARRY[494]) );
FULL_ADDER FA_427 (.DATA_A (INT_SUM[622]) , .DATA_B (INT_SUM[623]) , .DATA_C (INT_CARRY[486]) , .SAVE (INT_SUM[624]) , .CARRY (INT_CARRY[495]) );
assign INT_SUM[626] = INT_CARRY[487];
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[625]) );
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[627]) );
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[489]) );
FULL_ADDER FA_428 (.DATA_A (INT_SUM[625]) , .DATA_B (INT_SUM[627]) , .DATA_C (INT_CARRY[489]) , .SAVE (INT_SUM[628]) , .CARRY (INT_CARRY[497]) );
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[491]) );
assign INT_SUM[629] = INT_CARRY[491];
FULL_ADDER FA_429 (.DATA_A (INT_SUM[628]) , .DATA_B (INT_SUM[629]) , .DATA_C (INT_CARRY[492]) , .SAVE (SUM[53]) , .CARRY (CARRY[53]) );
FULL_ADDER FA_430 (.DATA_A (SUMMAND[541]) , .DATA_B (SUMMAND[542]) , .DATA_C (SUMMAND[543]) , .SAVE (INT_SUM[630]) , .CARRY (INT_CARRY[498]) );
FULL_ADDER FA_431 (.DATA_A (SUMMAND[544]) , .DATA_B (SUMMAND[545]) , .DATA_C (SUMMAND[546]) , .SAVE (INT_SUM[631]) , .CARRY (INT_CARRY[499]) );
FULL_ADDER FA_432 (.DATA_A (INT_SUM[630]) , .DATA_B (INT_SUM[631]) , .DATA_C (INT_CARRY[493]) , .SAVE (INT_SUM[632]) , .CARRY (INT_CARRY[500]) );
assign INT_SUM[634] = INT_CARRY[494];
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[633]) );
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[635]) );
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[496]) );
FULL_ADDER FA_433 (.DATA_A (INT_SUM[633]) , .DATA_B (INT_SUM[635]) , .DATA_C (INT_CARRY[496]) , .SAVE (INT_SUM[636]) , .CARRY (INT_CARRY[502]) );
HALF_ADDER HA_45 (.DATA_A (INT_SUM[636]) , .DATA_B (INT_CARRY[497]) , .SAVE (SUM[54]) , .CARRY (CARRY[54]) );
FULL_ADDER FA_434 (.DATA_A (SUMMAND[547]) , .DATA_B (SUMMAND[548]) , .DATA_C (SUMMAND[549]) , .SAVE (INT_SUM[637]) , .CARRY (INT_CARRY[503]) );
HALF_ADDER HA_46 (.DATA_A (SUMMAND[550]) , .DATA_B (SUMMAND[551]) , .SAVE (INT_SUM[638]) , .CARRY (INT_CARRY[504]) );
FULL_ADDER FA_435 (.DATA_A (INT_SUM[637]) , .DATA_B (INT_SUM[638]) , .DATA_C (INT_CARRY[498]) , .SAVE (INT_SUM[639]) , .CARRY (INT_CARRY[505]) );
assign INT_SUM[641] = INT_CARRY[499];
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[640]) );
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[642]) );
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[501]) );
FULL_ADDER FA_436 (.DATA_A (INT_SUM[640]) , .DATA_B (INT_SUM[642]) , .DATA_C (INT_CARRY[501]) , .SAVE (INT_SUM[643]) , .CARRY (INT_CARRY[507]) );
HALF_ADDER HA_47 (.DATA_A (INT_SUM[643]) , .DATA_B (INT_CARRY[502]) , .SAVE (SUM[55]) , .CARRY (CARRY[55]) );
FULL_ADDER FA_437 (.DATA_A (SUMMAND[552]) , .DATA_B (SUMMAND[553]) , .DATA_C (SUMMAND[554]) , .SAVE (INT_SUM[644]) , .CARRY (INT_CARRY[508]) );
HALF_ADDER HA_48 (.DATA_A (SUMMAND[555]) , .DATA_B (SUMMAND[556]) , .SAVE (INT_SUM[645]) , .CARRY (INT_CARRY[509]) );
FULL_ADDER FA_438 (.DATA_A (INT_SUM[644]) , .DATA_B (INT_SUM[645]) , .DATA_C (INT_CARRY[503]) , .SAVE (INT_SUM[646]) , .CARRY (INT_CARRY[510]) );
assign INT_SUM[648] = INT_CARRY[504];
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[647]) );
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[649]) );
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[506]) );
FULL_ADDER FA_439 (.DATA_A (INT_SUM[647]) , .DATA_B (INT_SUM[649]) , .DATA_C (INT_CARRY[506]) , .SAVE (INT_SUM[650]) , .CARRY (INT_CARRY[512]) );
HALF_ADDER HA_49 (.DATA_A (INT_SUM[650]) , .DATA_B (INT_CARRY[507]) , .SAVE (SUM[56]) , .CARRY (CARRY[56]) );
FULL_ADDER FA_440 (.DATA_A (SUMMAND[557]) , .DATA_B (SUMMAND[558]) , .DATA_C (SUMMAND[559]) , .SAVE (INT_SUM[651]) , .CARRY (INT_CARRY[513]) );
FULL_ADDER FA_441 (.DATA_A (SUMMAND[560]) , .DATA_B (INT_CARRY[508]) , .DATA_C (INT_CARRY[509]) , .SAVE (INT_SUM[653]) , .CARRY (INT_CARRY[515]) );
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[652]) );
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[654]) );
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[511]) );
FULL_ADDER FA_442 (.DATA_A (INT_SUM[652]) , .DATA_B (INT_SUM[654]) , .DATA_C (INT_CARRY[511]) , .SAVE (INT_SUM[655]) , .CARRY (INT_CARRY[517]) );
HALF_ADDER HA_50 (.DATA_A (INT_SUM[655]) , .DATA_B (INT_CARRY[512]) , .SAVE (SUM[57]) , .CARRY (CARRY[57]) );
FULL_ADDER FA_443 (.DATA_A (SUMMAND[561]) , .DATA_B (SUMMAND[562]) , .DATA_C (SUMMAND[563]) , .SAVE (INT_SUM[656]) , .CARRY (INT_CARRY[518]) );
assign INT_SUM[658] = SUMMAND[564];
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[657]) );
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[659]) );
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[514]) );
FULL_ADDER FA_444 (.DATA_A (INT_SUM[657]) , .DATA_B (INT_SUM[659]) , .DATA_C (INT_CARRY[514]) , .SAVE (INT_SUM[660]) , .CARRY (INT_CARRY[520]) );
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[516]) );
assign INT_SUM[661] = INT_CARRY[516];
FULL_ADDER FA_445 (.DATA_A (INT_SUM[660]) , .DATA_B (INT_SUM[661]) , .DATA_C (INT_CARRY[517]) , .SAVE (SUM[58]) , .CARRY (CARRY[58]) );
FULL_ADDER FA_446 (.DATA_A (SUMMAND[565]) , .DATA_B (SUMMAND[566]) , .DATA_C (SUMMAND[567]) , .SAVE (INT_SUM[662]) , .CARRY (INT_CARRY[521]) );
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[663]) );
assign INT_SUM[664] = INT_SUM[663];
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[519]) );
assign INT_SUM[665] = INT_CARRY[519];
FULL_ADDER FA_447 (.DATA_A (INT_SUM[664]) , .DATA_B (INT_SUM[665]) , .DATA_C (INT_CARRY[520]) , .SAVE (SUM[59]) , .CARRY (CARRY[59]) );
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[0]) );
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[1]) );
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[2]) );
FULL_ADDER FA_448 (.DATA_A (LATCHED_PP[0]) , .DATA_B (LATCHED_PP[1]) , .DATA_C (LATCHED_PP[2]) , .SAVE (INT_SUM[666]) , .CARRY (INT_CARRY[523]) );
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[522]) );
assign INT_SUM[667] = INT_CARRY[522];
HALF_ADDER HA_51 (.DATA_A (INT_SUM[666]) , .DATA_B (INT_SUM[667]) , .SAVE (SUM[60]) , .CARRY (CARRY[60]) );
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[3]) );
assign INT_SUM[668] = LATCHED_PP[3];
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[4]) );
assign INT_SUM[669] = LATCHED_PP[4];
FULL_ADDER FA_449 (.DATA_A (INT_SUM[668]) , .DATA_B (INT_SUM[669]) , .DATA_C (INT_CARRY[523]) , .SAVE (SUM[61]) , .CARRY (CARRY[61]) );
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[5]) );
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[6]) );
HALF_ADDER HA_52 (.DATA_A (LATCHED_PP[5]) , .DATA_B (LATCHED_PP[6]) , .SAVE (SUM[62]) , .CARRY (CARRY[62]) );
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[7]) );
assign SUM[63] = LATCHED_PP[7];
endmodule
module INVBLOCK ( GIN, PHI, GOUT );
input GIN;
input PHI;
output GOUT;
assign GOUT = ~ GIN;
endmodule
module XXOR1 ( A, B, GIN, PHI, SUM );
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = ( ~ (A ^ B)) ^ GIN;
endmodule
module BLOCK0 ( A, B, PHI, POUT, GOUT );
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (A | B);
assign GOUT = ~ (A & B);
endmodule
module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 | PIN2);
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 & PIN2);
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module PRESTAGE_64 ( A, B, CIN, PHI, POUT, GOUT );
input [0:63] A;
input [0:63] B;
input CIN;
input PHI;
output [0:63] POUT;
output [0:64] GOUT;
BLOCK0 U10 (A[0] , B[0] , PHI , POUT[0] , GOUT[1] );
BLOCK0 U11 (A[1] , B[1] , PHI , POUT[1] , GOUT[2] );
BLOCK0 U12 (A[2] , B[2] , PHI , POUT[2] , GOUT[3] );
BLOCK0 U13 (A[3] , B[3] , PHI , POUT[3] , GOUT[4] );
BLOCK0 U14 (A[4] , B[4] , PHI , POUT[4] , GOUT[5] );
BLOCK0 U15 (A[5] , B[5] , PHI , POUT[5] , GOUT[6] );
BLOCK0 U16 (A[6] , B[6] , PHI , POUT[6] , GOUT[7] );
BLOCK0 U17 (A[7] , B[7] , PHI , POUT[7] , GOUT[8] );
BLOCK0 U18 (A[8] , B[8] , PHI , POUT[8] , GOUT[9] );
BLOCK0 U19 (A[9] , B[9] , PHI , POUT[9] , GOUT[10] );
BLOCK0 U110 (A[10] , B[10] , PHI , POUT[10] , GOUT[11] );
BLOCK0 U111 (A[11] , B[11] , PHI , POUT[11] , GOUT[12] );
BLOCK0 U112 (A[12] , B[12] , PHI , POUT[12] , GOUT[13] );
BLOCK0 U113 (A[13] , B[13] , PHI , POUT[13] , GOUT[14] );
BLOCK0 U114 (A[14] , B[14] , PHI , POUT[14] , GOUT[15] );
BLOCK0 U115 (A[15] , B[15] , PHI , POUT[15] , GOUT[16] );
BLOCK0 U116 (A[16] , B[16] , PHI , POUT[16] , GOUT[17] );
BLOCK0 U117 (A[17] , B[17] , PHI , POUT[17] , GOUT[18] );
BLOCK0 U118 (A[18] , B[18] , PHI , POUT[18] , GOUT[19] );
BLOCK0 U119 (A[19] , B[19] , PHI , POUT[19] , GOUT[20] );
BLOCK0 U120 (A[20] , B[20] , PHI , POUT[20] , GOUT[21] );
BLOCK0 U121 (A[21] , B[21] , PHI , POUT[21] , GOUT[22] );
BLOCK0 U122 (A[22] , B[22] , PHI , POUT[22] , GOUT[23] );
BLOCK0 U123 (A[23] , B[23] , PHI , POUT[23] , GOUT[24] );
BLOCK0 U124 (A[24] , B[24] , PHI , POUT[24] , GOUT[25] );
BLOCK0 U125 (A[25] , B[25] , PHI , POUT[25] , GOUT[26] );
BLOCK0 U126 (A[26] , B[26] , PHI , POUT[26] , GOUT[27] );
BLOCK0 U127 (A[27] , B[27] , PHI , POUT[27] , GOUT[28] );
BLOCK0 U128 (A[28] , B[28] , PHI , POUT[28] , GOUT[29] );
BLOCK0 U129 (A[29] , B[29] , PHI , POUT[29] , GOUT[30] );
BLOCK0 U130 (A[30] , B[30] , PHI , POUT[30] , GOUT[31] );
BLOCK0 U131 (A[31] , B[31] , PHI , POUT[31] , GOUT[32] );
BLOCK0 U132 (A[32] , B[32] , PHI , POUT[32] , GOUT[33] );
BLOCK0 U133 (A[33] , B[33] , PHI , POUT[33] , GOUT[34] );
BLOCK0 U134 (A[34] , B[34] , PHI , POUT[34] , GOUT[35] );
BLOCK0 U135 (A[35] , B[35] , PHI , POUT[35] , GOUT[36] );
BLOCK0 U136 (A[36] , B[36] , PHI , POUT[36] , GOUT[37] );
BLOCK0 U137 (A[37] , B[37] , PHI , POUT[37] , GOUT[38] );
BLOCK0 U138 (A[38] , B[38] , PHI , POUT[38] , GOUT[39] );
BLOCK0 U139 (A[39] , B[39] , PHI , POUT[39] , GOUT[40] );
BLOCK0 U140 (A[40] , B[40] , PHI , POUT[40] , GOUT[41] );
BLOCK0 U141 (A[41] , B[41] , PHI , POUT[41] , GOUT[42] );
BLOCK0 U142 (A[42] , B[42] , PHI , POUT[42] , GOUT[43] );
BLOCK0 U143 (A[43] , B[43] , PHI , POUT[43] , GOUT[44] );
BLOCK0 U144 (A[44] , B[44] , PHI , POUT[44] , GOUT[45] );
BLOCK0 U145 (A[45] , B[45] , PHI , POUT[45] , GOUT[46] );
BLOCK0 U146 (A[46] , B[46] , PHI , POUT[46] , GOUT[47] );
BLOCK0 U147 (A[47] , B[47] , PHI , POUT[47] , GOUT[48] );
BLOCK0 U148 (A[48] , B[48] , PHI , POUT[48] , GOUT[49] );
BLOCK0 U149 (A[49] , B[49] , PHI , POUT[49] , GOUT[50] );
BLOCK0 U150 (A[50] , B[50] , PHI , POUT[50] , GOUT[51] );
BLOCK0 U151 (A[51] , B[51] , PHI , POUT[51] , GOUT[52] );
BLOCK0 U152 (A[52] , B[52] , PHI , POUT[52] , GOUT[53] );
BLOCK0 U153 (A[53] , B[53] , PHI , POUT[53] , GOUT[54] );
BLOCK0 U154 (A[54] , B[54] , PHI , POUT[54] , GOUT[55] );
BLOCK0 U155 (A[55] , B[55] , PHI , POUT[55] , GOUT[56] );
BLOCK0 U156 (A[56] , B[56] , PHI , POUT[56] , GOUT[57] );
BLOCK0 U157 (A[57] , B[57] , PHI , POUT[57] , GOUT[58] );
BLOCK0 U158 (A[58] , B[58] , PHI , POUT[58] , GOUT[59] );
BLOCK0 U159 (A[59] , B[59] , PHI , POUT[59] , GOUT[60] );
BLOCK0 U160 (A[60] , B[60] , PHI , POUT[60] , GOUT[61] );
BLOCK0 U161 (A[61] , B[61] , PHI , POUT[61] , GOUT[62] );
BLOCK0 U162 (A[62] , B[62] , PHI , POUT[62] , GOUT[63] );
BLOCK0 U163 (A[63] , B[63] , PHI , POUT[63] , GOUT[64] );
INVBLOCK U2 (CIN , PHI , GOUT[0] );
endmodule
module DBLC_0_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:62] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , PHI , GOUT[1] );
BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , PHI , POUT[0] , GOUT[2] );
BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , PHI , POUT[1] , GOUT[3] );
BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , PHI , POUT[2] , GOUT[4] );
BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , PHI , POUT[3] , GOUT[5] );
BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , PHI , POUT[4] , GOUT[6] );
BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , PHI , POUT[5] , GOUT[7] );
BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , PHI , POUT[6] , GOUT[8] );
BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , PHI , POUT[7] , GOUT[9] );
BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , PHI , POUT[8] , GOUT[10] );
BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , PHI , POUT[9] , GOUT[11] );
BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , PHI , POUT[10] , GOUT[12] );
BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , PHI , POUT[11] , GOUT[13] );
BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , PHI , POUT[12] , GOUT[14] );
BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , PHI , POUT[13] , GOUT[15] );
BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , PHI , POUT[14] , GOUT[16] );
BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , PHI , POUT[15] , GOUT[17] );
BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , PHI , POUT[16] , GOUT[18] );
BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , PHI , POUT[17] , GOUT[19] );
BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , PHI , POUT[18] , GOUT[20] );
BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , PHI , POUT[19] , GOUT[21] );
BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , PHI , POUT[20] , GOUT[22] );
BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , PHI , POUT[21] , GOUT[23] );
BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , PHI , POUT[22] , GOUT[24] );
BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , PHI , POUT[23] , GOUT[25] );
BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , PHI , POUT[24] , GOUT[26] );
BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , PHI , POUT[25] , GOUT[27] );
BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , PHI , POUT[26] , GOUT[28] );
BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , PHI , POUT[27] , GOUT[29] );
BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , PHI , POUT[28] , GOUT[30] );
BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , PHI , POUT[29] , GOUT[31] );
BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , PHI , POUT[30] , GOUT[32] );
BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , PHI , POUT[31] , GOUT[33] );
BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , PHI , POUT[32] , GOUT[34] );
BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , PHI , POUT[33] , GOUT[35] );
BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , PHI , POUT[34] , GOUT[36] );
BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , PHI , POUT[35] , GOUT[37] );
BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , PHI , POUT[36] , GOUT[38] );
BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , PHI , POUT[37] , GOUT[39] );
BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , PHI , POUT[38] , GOUT[40] );
BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , PHI , POUT[39] , GOUT[41] );
BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , PHI , POUT[40] , GOUT[42] );
BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , PHI , POUT[41] , GOUT[43] );
BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , PHI , POUT[42] , GOUT[44] );
BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , PHI , POUT[43] , GOUT[45] );
BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , PHI , POUT[44] , GOUT[46] );
BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , PHI , POUT[45] , GOUT[47] );
BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , PHI , POUT[46] , GOUT[48] );
BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , PHI , POUT[47] , GOUT[49] );
BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , PHI , POUT[48] , GOUT[50] );
BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , PHI , POUT[49] , GOUT[51] );
BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , PHI , POUT[50] , GOUT[52] );
BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , PHI , POUT[51] , GOUT[53] );
BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , PHI , POUT[52] , GOUT[54] );
BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , PHI , POUT[53] , GOUT[55] );
BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , PHI , POUT[54] , GOUT[56] );
BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , PHI , POUT[55] , GOUT[57] );
BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , PHI , POUT[56] , GOUT[58] );
BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , PHI , POUT[57] , GOUT[59] );
BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , PHI , POUT[58] , GOUT[60] );
BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , PHI , POUT[59] , GOUT[61] );
BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , PHI , POUT[60] , GOUT[62] );
BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , PHI , POUT[61] , GOUT[63] );
BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , PHI , POUT[62] , GOUT[64] );
endmodule
module DBLC_1_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:62] PIN;
input [0:64] GIN;
input PHI;
output [0:60] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , PHI , GOUT[2] );
BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , PHI , GOUT[3] );
BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , PHI , POUT[0] , GOUT[4] );
BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , PHI , POUT[1] , GOUT[5] );
BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , PHI , POUT[2] , GOUT[6] );
BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , PHI , POUT[3] , GOUT[7] );
BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , PHI , POUT[4] , GOUT[8] );
BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , PHI , POUT[5] , GOUT[9] );
BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , PHI , POUT[6] , GOUT[10] );
BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , PHI , POUT[7] , GOUT[11] );
BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , PHI , POUT[8] , GOUT[12] );
BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , PHI , POUT[9] , GOUT[13] );
BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , PHI , POUT[10] , GOUT[14] );
BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , PHI , POUT[11] , GOUT[15] );
BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , PHI , POUT[12] , GOUT[16] );
BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , PHI , POUT[13] , GOUT[17] );
BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , PHI , POUT[14] , GOUT[18] );
BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , PHI , POUT[15] , GOUT[19] );
BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , PHI , POUT[16] , GOUT[20] );
BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , PHI , POUT[17] , GOUT[21] );
BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , PHI , POUT[18] , GOUT[22] );
BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , PHI , POUT[19] , GOUT[23] );
BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , PHI , POUT[20] , GOUT[24] );
BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , PHI , POUT[21] , GOUT[25] );
BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , PHI , POUT[22] , GOUT[26] );
BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , PHI , POUT[23] , GOUT[27] );
BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , PHI , POUT[24] , GOUT[28] );
BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , PHI , POUT[25] , GOUT[29] );
BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , PHI , POUT[26] , GOUT[30] );
BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , PHI , POUT[27] , GOUT[31] );
BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , PHI , POUT[28] , GOUT[32] );
BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , PHI , POUT[29] , GOUT[33] );
BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , PHI , POUT[30] , GOUT[34] );
BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , PHI , POUT[31] , GOUT[35] );
BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , PHI , POUT[32] , GOUT[36] );
BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , PHI , POUT[33] , GOUT[37] );
BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , PHI , POUT[34] , GOUT[38] );
BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , PHI , POUT[35] , GOUT[39] );
BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , PHI , POUT[36] , GOUT[40] );
BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , PHI , POUT[37] , GOUT[41] );
BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , PHI , POUT[38] , GOUT[42] );
BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , PHI , POUT[39] , GOUT[43] );
BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , PHI , POUT[40] , GOUT[44] );
BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , PHI , POUT[41] , GOUT[45] );
BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , PHI , POUT[42] , GOUT[46] );
BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , PHI , POUT[43] , GOUT[47] );
BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , PHI , POUT[44] , GOUT[48] );
BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , PHI , POUT[45] , GOUT[49] );
BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , PHI , POUT[46] , GOUT[50] );
BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , PHI , POUT[47] , GOUT[51] );
BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , PHI , POUT[48] , GOUT[52] );
BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , PHI , POUT[49] , GOUT[53] );
BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , PHI , POUT[50] , GOUT[54] );
BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , PHI , POUT[51] , GOUT[55] );
BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , PHI , POUT[52] , GOUT[56] );
BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , PHI , POUT[53] , GOUT[57] );
BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , PHI , POUT[54] , GOUT[58] );
BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , PHI , POUT[55] , GOUT[59] );
BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , PHI , POUT[56] , GOUT[60] );
BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , PHI , POUT[57] , GOUT[61] );
BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , PHI , POUT[58] , GOUT[62] );
BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , PHI , POUT[59] , GOUT[63] );
BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , PHI , POUT[60] , GOUT[64] );
endmodule
module DBLC_2_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:60] PIN;
input [0:64] GIN;
input PHI;
output [0:56] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , PHI , GOUT[4] );
BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , PHI , GOUT[5] );
BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , PHI , GOUT[6] );
BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , PHI , GOUT[7] );
BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , PHI , POUT[0] , GOUT[8] );
BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , PHI , POUT[1] , GOUT[9] );
BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , PHI , POUT[2] , GOUT[10] );
BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , PHI , POUT[3] , GOUT[11] );
BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , PHI , POUT[4] , GOUT[12] );
BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , PHI , POUT[5] , GOUT[13] );
BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , PHI , POUT[6] , GOUT[14] );
BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , PHI , POUT[7] , GOUT[15] );
BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , PHI , POUT[8] , GOUT[16] );
BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , PHI , POUT[9] , GOUT[17] );
BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , PHI , POUT[10] , GOUT[18] );
BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , PHI , POUT[11] , GOUT[19] );
BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , PHI , POUT[12] , GOUT[20] );
BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , PHI , POUT[13] , GOUT[21] );
BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , PHI , POUT[14] , GOUT[22] );
BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , PHI , POUT[15] , GOUT[23] );
BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , PHI , POUT[16] , GOUT[24] );
BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , PHI , POUT[17] , GOUT[25] );
BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , PHI , POUT[18] , GOUT[26] );
BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , PHI , POUT[19] , GOUT[27] );
BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , PHI , POUT[20] , GOUT[28] );
BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , PHI , POUT[21] , GOUT[29] );
BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , PHI , POUT[22] , GOUT[30] );
BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , PHI , POUT[23] , GOUT[31] );
BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , PHI , POUT[24] , GOUT[32] );
BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , PHI , POUT[25] , GOUT[33] );
BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , PHI , POUT[26] , GOUT[34] );
BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , PHI , POUT[27] , GOUT[35] );
BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , PHI , POUT[28] , GOUT[36] );
BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , PHI , POUT[29] , GOUT[37] );
BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , PHI , POUT[30] , GOUT[38] );
BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , PHI , POUT[31] , GOUT[39] );
BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , PHI , POUT[32] , GOUT[40] );
BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , PHI , POUT[33] , GOUT[41] );
BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , PHI , POUT[34] , GOUT[42] );
BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , PHI , POUT[35] , GOUT[43] );
BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , PHI , POUT[36] , GOUT[44] );
BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , PHI , POUT[37] , GOUT[45] );
BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , PHI , POUT[38] , GOUT[46] );
BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , PHI , POUT[39] , GOUT[47] );
BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , PHI , POUT[40] , GOUT[48] );
BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , PHI , POUT[41] , GOUT[49] );
BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , PHI , POUT[42] , GOUT[50] );
BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , PHI , POUT[43] , GOUT[51] );
BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , PHI , POUT[44] , GOUT[52] );
BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , PHI , POUT[45] , GOUT[53] );
BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , PHI , POUT[46] , GOUT[54] );
BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , PHI , POUT[47] , GOUT[55] );
BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , PHI , POUT[48] , GOUT[56] );
BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , PHI , POUT[49] , GOUT[57] );
BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , PHI , POUT[50] , GOUT[58] );
BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , PHI , POUT[51] , GOUT[59] );
BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , PHI , POUT[52] , GOUT[60] );
BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , PHI , POUT[53] , GOUT[61] );
BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , PHI , POUT[54] , GOUT[62] );
BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , PHI , POUT[55] , GOUT[63] );
BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , PHI , POUT[56] , GOUT[64] );
endmodule
module DBLC_3_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:56] PIN;
input [0:64] GIN;
input PHI;
output [0:48] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , PHI , GOUT[8] );
BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , PHI , GOUT[9] );
BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , PHI , GOUT[10] );
BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , PHI , GOUT[11] );
BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , PHI , GOUT[12] );
BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , PHI , GOUT[13] );
BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , PHI , GOUT[14] );
BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , PHI , GOUT[15] );
BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , PHI , POUT[0] , GOUT[16] );
BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , PHI , POUT[1] , GOUT[17] );
BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , PHI , POUT[2] , GOUT[18] );
BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , PHI , POUT[3] , GOUT[19] );
BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , PHI , POUT[4] , GOUT[20] );
BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , PHI , POUT[5] , GOUT[21] );
BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , PHI , POUT[6] , GOUT[22] );
BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , PHI , POUT[7] , GOUT[23] );
BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , PHI , POUT[8] , GOUT[24] );
BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , PHI , POUT[9] , GOUT[25] );
BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , PHI , POUT[10] , GOUT[26] );
BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , PHI , POUT[11] , GOUT[27] );
BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , PHI , POUT[12] , GOUT[28] );
BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , PHI , POUT[13] , GOUT[29] );
BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , PHI , POUT[14] , GOUT[30] );
BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , PHI , POUT[15] , GOUT[31] );
BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , PHI , POUT[16] , GOUT[32] );
BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , PHI , POUT[17] , GOUT[33] );
BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , PHI , POUT[18] , GOUT[34] );
BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , PHI , POUT[19] , GOUT[35] );
BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , PHI , POUT[20] , GOUT[36] );
BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , PHI , POUT[21] , GOUT[37] );
BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , PHI , POUT[22] , GOUT[38] );
BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , PHI , POUT[23] , GOUT[39] );
BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , PHI , POUT[24] , GOUT[40] );
BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , PHI , POUT[25] , GOUT[41] );
BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , PHI , POUT[26] , GOUT[42] );
BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , PHI , POUT[27] , GOUT[43] );
BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , PHI , POUT[28] , GOUT[44] );
BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , PHI , POUT[29] , GOUT[45] );
BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , PHI , POUT[30] , GOUT[46] );
BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , PHI , POUT[31] , GOUT[47] );
BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , PHI , POUT[32] , GOUT[48] );
BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , PHI , POUT[33] , GOUT[49] );
BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , PHI , POUT[34] , GOUT[50] );
BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , PHI , POUT[35] , GOUT[51] );
BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , PHI , POUT[36] , GOUT[52] );
BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , PHI , POUT[37] , GOUT[53] );
BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , PHI , POUT[38] , GOUT[54] );
BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , PHI , POUT[39] , GOUT[55] );
BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , PHI , POUT[40] , GOUT[56] );
BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , PHI , POUT[41] , GOUT[57] );
BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , PHI , POUT[42] , GOUT[58] );
BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , PHI , POUT[43] , GOUT[59] );
BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , PHI , POUT[44] , GOUT[60] );
BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , PHI , POUT[45] , GOUT[61] );
BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , PHI , POUT[46] , GOUT[62] );
BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , PHI , POUT[47] , GOUT[63] );
BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , PHI , POUT[48] , GOUT[64] );
endmodule
module DBLC_4_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:48] PIN;
input [0:64] GIN;
input PHI;
output [0:32] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , PHI , GOUT[16] );
BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , PHI , GOUT[17] );
BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , PHI , GOUT[18] );
BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , PHI , GOUT[19] );
BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , PHI , GOUT[20] );
BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , PHI , GOUT[21] );
BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , PHI , GOUT[22] );
BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , PHI , GOUT[23] );
BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , PHI , GOUT[24] );
BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , PHI , GOUT[25] );
BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , PHI , GOUT[26] );
BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , PHI , GOUT[27] );
BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , PHI , GOUT[28] );
BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , PHI , GOUT[29] );
BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , PHI , GOUT[30] );
BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , PHI , GOUT[31] );
BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , PHI , POUT[0] , GOUT[32] );
BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , PHI , POUT[1] , GOUT[33] );
BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , PHI , POUT[2] , GOUT[34] );
BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , PHI , POUT[3] , GOUT[35] );
BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , PHI , POUT[4] , GOUT[36] );
BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , PHI , POUT[5] , GOUT[37] );
BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , PHI , POUT[6] , GOUT[38] );
BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , PHI , POUT[7] , GOUT[39] );
BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , PHI , POUT[8] , GOUT[40] );
BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , PHI , POUT[9] , GOUT[41] );
BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , PHI , POUT[10] , GOUT[42] );
BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , PHI , POUT[11] , GOUT[43] );
BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , PHI , POUT[12] , GOUT[44] );
BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , PHI , POUT[13] , GOUT[45] );
BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , PHI , POUT[14] , GOUT[46] );
BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , PHI , POUT[15] , GOUT[47] );
BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , PHI , POUT[16] , GOUT[48] );
BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , PHI , POUT[17] , GOUT[49] );
BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , PHI , POUT[18] , GOUT[50] );
BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , PHI , POUT[19] , GOUT[51] );
BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , PHI , POUT[20] , GOUT[52] );
BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , PHI , POUT[21] , GOUT[53] );
BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , PHI , POUT[22] , GOUT[54] );
BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , PHI , POUT[23] , GOUT[55] );
BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , PHI , POUT[24] , GOUT[56] );
BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , PHI , POUT[25] , GOUT[57] );
BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , PHI , POUT[26] , GOUT[58] );
BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , PHI , POUT[27] , GOUT[59] );
BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , PHI , POUT[28] , GOUT[60] );
BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , PHI , POUT[29] , GOUT[61] );
BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , PHI , POUT[30] , GOUT[62] );
BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , PHI , POUT[31] , GOUT[63] );
BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , PHI , POUT[32] , GOUT[64] );
endmodule
module DBLC_5_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:32] PIN;
input [0:64] GIN;
input PHI;
output [0:0] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
INVBLOCK U116 (GIN[16] , PHI , GOUT[16] );
INVBLOCK U117 (GIN[17] , PHI , GOUT[17] );
INVBLOCK U118 (GIN[18] , PHI , GOUT[18] );
INVBLOCK U119 (GIN[19] , PHI , GOUT[19] );
INVBLOCK U120 (GIN[20] , PHI , GOUT[20] );
INVBLOCK U121 (GIN[21] , PHI , GOUT[21] );
INVBLOCK U122 (GIN[22] , PHI , GOUT[22] );
INVBLOCK U123 (GIN[23] , PHI , GOUT[23] );
INVBLOCK U124 (GIN[24] , PHI , GOUT[24] );
INVBLOCK U125 (GIN[25] , PHI , GOUT[25] );
INVBLOCK U126 (GIN[26] , PHI , GOUT[26] );
INVBLOCK U127 (GIN[27] , PHI , GOUT[27] );
INVBLOCK U128 (GIN[28] , PHI , GOUT[28] );
INVBLOCK U129 (GIN[29] , PHI , GOUT[29] );
INVBLOCK U130 (GIN[30] , PHI , GOUT[30] );
INVBLOCK U131 (GIN[31] , PHI , GOUT[31] );
BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , PHI , GOUT[32] );
BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , PHI , GOUT[33] );
BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , PHI , GOUT[34] );
BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , PHI , GOUT[35] );
BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , PHI , GOUT[36] );
BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , PHI , GOUT[37] );
BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , PHI , GOUT[38] );
BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , PHI , GOUT[39] );
BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , PHI , GOUT[40] );
BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , PHI , GOUT[41] );
BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , PHI , GOUT[42] );
BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , PHI , GOUT[43] );
BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , PHI , GOUT[44] );
BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , PHI , GOUT[45] );
BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , PHI , GOUT[46] );
BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , PHI , GOUT[47] );
BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , PHI , GOUT[48] );
BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , PHI , GOUT[49] );
BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , PHI , GOUT[50] );
BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , PHI , GOUT[51] );
BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , PHI , GOUT[52] );
BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , PHI , GOUT[53] );
BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , PHI , GOUT[54] );
BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , PHI , GOUT[55] );
BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , PHI , GOUT[56] );
BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , PHI , GOUT[57] );
BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , PHI , GOUT[58] );
BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , PHI , GOUT[59] );
BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , PHI , GOUT[60] );
BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , PHI , GOUT[61] );
BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , PHI , GOUT[62] );
BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , PHI , GOUT[63] );
BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , PHI , POUT[0] , GOUT[64] );
endmodule
module XORSTAGE_64 ( A, B, PBIT, PHI, CARRY, SUM, COUT );
input [0:63] A;
input [0:63] B;
input PBIT;
input PHI;
input [0:64] CARRY;
output [0:63] SUM;
output COUT;
XXOR1 U20 (A[0] , B[0] , CARRY[0] , PHI , SUM[0] );
XXOR1 U21 (A[1] , B[1] , CARRY[1] , PHI , SUM[1] );
XXOR1 U22 (A[2] , B[2] , CARRY[2] , PHI , SUM[2] );
XXOR1 U23 (A[3] , B[3] , CARRY[3] , PHI , SUM[3] );
XXOR1 U24 (A[4] , B[4] , CARRY[4] , PHI , SUM[4] );
XXOR1 U25 (A[5] , B[5] , CARRY[5] , PHI , SUM[5] );
XXOR1 U26 (A[6] , B[6] , CARRY[6] , PHI , SUM[6] );
XXOR1 U27 (A[7] , B[7] , CARRY[7] , PHI , SUM[7] );
XXOR1 U28 (A[8] , B[8] , CARRY[8] , PHI , SUM[8] );
XXOR1 U29 (A[9] , B[9] , CARRY[9] , PHI , SUM[9] );
XXOR1 U210 (A[10] , B[10] , CARRY[10] , PHI , SUM[10] );
XXOR1 U211 (A[11] , B[11] , CARRY[11] , PHI , SUM[11] );
XXOR1 U212 (A[12] , B[12] , CARRY[12] , PHI , SUM[12] );
XXOR1 U213 (A[13] , B[13] , CARRY[13] , PHI , SUM[13] );
XXOR1 U214 (A[14] , B[14] , CARRY[14] , PHI , SUM[14] );
XXOR1 U215 (A[15] , B[15] , CARRY[15] , PHI , SUM[15] );
XXOR1 U216 (A[16] , B[16] , CARRY[16] , PHI , SUM[16] );
XXOR1 U217 (A[17] , B[17] , CARRY[17] , PHI , SUM[17] );
XXOR1 U218 (A[18] , B[18] , CARRY[18] , PHI , SUM[18] );
XXOR1 U219 (A[19] , B[19] , CARRY[19] , PHI , SUM[19] );
XXOR1 U220 (A[20] , B[20] , CARRY[20] , PHI , SUM[20] );
XXOR1 U221 (A[21] , B[21] , CARRY[21] , PHI , SUM[21] );
XXOR1 U222 (A[22] , B[22] , CARRY[22] , PHI , SUM[22] );
XXOR1 U223 (A[23] , B[23] , CARRY[23] , PHI , SUM[23] );
XXOR1 U224 (A[24] , B[24] , CARRY[24] , PHI , SUM[24] );
XXOR1 U225 (A[25] , B[25] , CARRY[25] , PHI , SUM[25] );
XXOR1 U226 (A[26] , B[26] , CARRY[26] , PHI , SUM[26] );
XXOR1 U227 (A[27] , B[27] , CARRY[27] , PHI , SUM[27] );
XXOR1 U228 (A[28] , B[28] , CARRY[28] , PHI , SUM[28] );
XXOR1 U229 (A[29] , B[29] , CARRY[29] , PHI , SUM[29] );
XXOR1 U230 (A[30] , B[30] , CARRY[30] , PHI , SUM[30] );
XXOR1 U231 (A[31] , B[31] , CARRY[31] , PHI , SUM[31] );
XXOR1 U232 (A[32] , B[32] , CARRY[32] , PHI , SUM[32] );
XXOR1 U233 (A[33] , B[33] , CARRY[33] , PHI , SUM[33] );
XXOR1 U234 (A[34] , B[34] , CARRY[34] , PHI , SUM[34] );
XXOR1 U235 (A[35] , B[35] , CARRY[35] , PHI , SUM[35] );
XXOR1 U236 (A[36] , B[36] , CARRY[36] , PHI , SUM[36] );
XXOR1 U237 (A[37] , B[37] , CARRY[37] , PHI , SUM[37] );
XXOR1 U238 (A[38] , B[38] , CARRY[38] , PHI , SUM[38] );
XXOR1 U239 (A[39] , B[39] , CARRY[39] , PHI , SUM[39] );
XXOR1 U240 (A[40] , B[40] , CARRY[40] , PHI , SUM[40] );
XXOR1 U241 (A[41] , B[41] , CARRY[41] , PHI , SUM[41] );
XXOR1 U242 (A[42] , B[42] , CARRY[42] , PHI , SUM[42] );
XXOR1 U243 (A[43] , B[43] , CARRY[43] , PHI , SUM[43] );
XXOR1 U244 (A[44] , B[44] , CARRY[44] , PHI , SUM[44] );
XXOR1 U245 (A[45] , B[45] , CARRY[45] , PHI , SUM[45] );
XXOR1 U246 (A[46] , B[46] , CARRY[46] , PHI , SUM[46] );
XXOR1 U247 (A[47] , B[47] , CARRY[47] , PHI , SUM[47] );
XXOR1 U248 (A[48] , B[48] , CARRY[48] , PHI , SUM[48] );
XXOR1 U249 (A[49] , B[49] , CARRY[49] , PHI , SUM[49] );
XXOR1 U250 (A[50] , B[50] , CARRY[50] , PHI , SUM[50] );
XXOR1 U251 (A[51] , B[51] , CARRY[51] , PHI , SUM[51] );
XXOR1 U252 (A[52] , B[52] , CARRY[52] , PHI , SUM[52] );
XXOR1 U253 (A[53] , B[53] , CARRY[53] , PHI , SUM[53] );
XXOR1 U254 (A[54] , B[54] , CARRY[54] , PHI , SUM[54] );
XXOR1 U255 (A[55] , B[55] , CARRY[55] , PHI , SUM[55] );
XXOR1 U256 (A[56] , B[56] , CARRY[56] , PHI , SUM[56] );
XXOR1 U257 (A[57] , B[57] , CARRY[57] , PHI , SUM[57] );
XXOR1 U258 (A[58] , B[58] , CARRY[58] , PHI , SUM[58] );
XXOR1 U259 (A[59] , B[59] , CARRY[59] , PHI , SUM[59] );
XXOR1 U260 (A[60] , B[60] , CARRY[60] , PHI , SUM[60] );
XXOR1 U261 (A[61] , B[61] , CARRY[61] , PHI , SUM[61] );
XXOR1 U262 (A[62] , B[62] , CARRY[62] , PHI , SUM[62] );
XXOR1 U263 (A[63] , B[63] , CARRY[63] , PHI , SUM[63] );
BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , PHI , COUT );
endmodule
module DBLCTREE_64 ( PIN, GIN, PHI, GOUT, POUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:64] GOUT;
output [0:0] POUT;
wire [0:62] INTPROP_0;
wire [0:64] INTGEN_0;
wire [0:60] INTPROP_1;
wire [0:64] INTGEN_1;
wire [0:56] INTPROP_2;
wire [0:64] INTGEN_2;
wire [0:48] INTPROP_3;
wire [0:64] INTGEN_3;
wire [0:32] INTPROP_4;
wire [0:64] INTGEN_4;
DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );
DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) );
DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .PHI(PHI) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) );
DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );
endmodule
module DBLCADDER_64_64 ( OPA, OPB, CIN, PHI, SUM, COUT );
input [0:63] OPA;
input [0:63] OPB;
input CIN;
input PHI;
output [0:63] SUM;
output COUT;
wire [0:63] INTPROP;
wire [0:64] INTGEN;
wire [0:0] PBIT;
wire [0:64] CARRY;
PRESTAGE_64 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
DBLCTREE_64 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , PHI , CARRY[0:64] , SUM , COUT );
endmodule
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, RST, CLK, PHI, RESULT );
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:63] ARESULT;
reg [0:63] RESULT;
assign LOGIC_ZERO = 0;
BOOTHCODER_33_32 B (.OPA(MULTIPLICAND[0:32]) , .OPB(MULTIPLIER[0:31]) , .SUMMAND(PPBIT[0:575]) );
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) );
assign INT_CARRY[0] = LOGIC_ZERO;
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(ARESULT[0:63]), .COUT() );
always @(posedge CLK or posedge RST)
if (RST)
RESULT <= #1 64'h0000_0000_0000_0000;
else
RESULT <= ARESULT;
endmodule
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
module or1200_amultp2_32x32 ( X, Y, RST, CLK, P );
input [31:0] X;
input [31:0] Y;
input RST;
input CLK;
output [63:0] P;
wire [0:32] A;
wire [0:31] B;
wire [0:63] Q;
assign A[0] = X[0];
assign A[1] = X[1];
assign A[2] = X[2];
assign A[3] = X[3];
assign A[4] = X[4];
assign A[5] = X[5];
assign A[6] = X[6];
assign A[7] = X[7];
assign A[8] = X[8];
assign A[9] = X[9];
assign A[10] = X[10];
assign A[11] = X[11];
assign A[12] = X[12];
assign A[13] = X[13];
assign A[14] = X[14];
assign A[15] = X[15];
assign A[16] = X[16];
assign A[17] = X[17];
assign A[18] = X[18];
assign A[19] = X[19];
assign A[20] = X[20];
assign A[21] = X[21];
assign A[22] = X[22];
assign A[23] = X[23];
assign A[24] = X[24];
assign A[25] = X[25];
assign A[26] = X[26];
assign A[27] = X[27];
assign A[28] = X[28];
assign A[29] = X[29];
assign A[30] = X[30];
assign A[31] = X[31];
assign A[32] = X[31];
assign B[0] = Y[0];
assign B[1] = Y[1];
assign B[2] = Y[2];
assign B[3] = Y[3];
assign B[4] = Y[4];
assign B[5] = Y[5];
assign B[6] = Y[6];
assign B[7] = Y[7];
assign B[8] = Y[8];
assign B[9] = Y[9];
assign B[10] = Y[10];
assign B[11] = Y[11];
assign B[12] = Y[12];
assign B[13] = Y[13];
assign B[14] = Y[14];
assign B[15] = Y[15];
assign B[16] = Y[16];
assign B[17] = Y[17];
assign B[18] = Y[18];
assign B[19] = Y[19];
assign B[20] = Y[20];
assign B[21] = Y[21];
assign B[22] = Y[22];
assign B[23] = Y[23];
assign B[24] = Y[24];
assign B[25] = Y[25];
assign B[26] = Y[26];
assign B[27] = Y[27];
assign B[28] = Y[28];
assign B[29] = Y[29];
assign B[30] = Y[30];
assign B[31] = Y[31];
assign P[0] = Q[0];
assign P[1] = Q[1];
assign P[2] = Q[2];
assign P[3] = Q[3];
assign P[4] = Q[4];
assign P[5] = Q[5];
assign P[6] = Q[6];
assign P[7] = Q[7];
assign P[8] = Q[8];
assign P[9] = Q[9];
assign P[10] = Q[10];
assign P[11] = Q[11];
assign P[12] = Q[12];
assign P[13] = Q[13];
assign P[14] = Q[14];
assign P[15] = Q[15];
assign P[16] = Q[16];
assign P[17] = Q[17];
assign P[18] = Q[18];
assign P[19] = Q[19];
assign P[20] = Q[20];
assign P[21] = Q[21];
assign P[22] = Q[22];
assign P[23] = Q[23];
assign P[24] = Q[24];
assign P[25] = Q[25];
assign P[26] = Q[26];
assign P[27] = Q[27];
assign P[28] = Q[28];
assign P[29] = Q[29];
assign P[30] = Q[30];
assign P[31] = Q[31];
assign P[32] = Q[32];
assign P[33] = Q[33];
assign P[34] = Q[34];
assign P[35] = Q[35];
assign P[36] = Q[36];
assign P[37] = Q[37];
assign P[38] = Q[38];
assign P[39] = Q[39];
assign P[40] = Q[40];
assign P[41] = Q[41];
assign P[42] = Q[42];
assign P[43] = Q[43];
assign P[44] = Q[44];
assign P[45] = Q[45];
assign P[46] = Q[46];
assign P[47] = Q[47];
assign P[48] = Q[48];
assign P[49] = Q[49];
assign P[50] = Q[50];
assign P[51] = Q[51];
assign P[52] = Q[52];
assign P[53] = Q[53];
assign P[54] = Q[54];
assign P[55] = Q[55];
assign P[56] = Q[56];
assign P[57] = Q[57];
assign P[58] = Q[58];
assign P[59] = Q[59];
assign P[60] = Q[60];
assign P[61] = Q[61];
assign P[62] = Q[62];
assign P[63] = Q[63];
MULTIPLIER_33_32 U1 (.MULTIPLICAND(A) , .MULTIPLIER(B) , .RST(RST), .CLK(CLK) , .PHI(1'b0) , .RESULT(Q) );
endmodule
`endif
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