text
stringlengths 938
1.05M
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
/**
* udp_dlatch$PR: D-latch, gated clear direct / gate active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_pr.v"
module top();
// Inputs are registered
reg D;
reg RESET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 D = 1'b1;
#80 RESET = 1'b1;
#100 D = 1'b0;
#120 RESET = 1'b0;
#140 RESET = 1'b1;
#160 D = 1'b1;
#180 RESET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$PR dut (.D(D), .RESET(RESET), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_PR_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_1_V
`define SKY130_FD_SC_MS__A221OI_1_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_1_V
|
module testbench();
reg tb_clk;
reg [31:0] l_reg;
reg [31:0] r_reg;
wire [31:0] l_data;
wire [31:0] r_data;
assign l_data = l_reg;
assign r_data = r_reg;
wire LRCK, DAT, MCK, SCK;
//i2s_tx #(.DATA_WIDTH(16), .MCLK_DIV(2), .FS(128)) iis_tx(
i2s_tx #(.DATA_WIDTH(32)) iis_tx(
.clk(tb_clk),
.left_chan(l_data),
.right_chan(r_data),
.sdata(DAT),
.mck(MCK),
.sck(SCK),
.lrclk(LRCK)
);
reg [7:0] ccc;
wire signed [7:0] ccc_s = ccc - 8'b10000000;
initial
begin
$dumpfile("bench.vcd");
$dumpvars(0,testbench);
$display("starting testbench!!!!");
$display("$clog2(2)", $clog2(2+1));
$display("$clog2(4)", $clog2(4+1));
$display("$clog2(6)", $clog2(6+1));
$display("$clog2(8)", $clog2(8+1));
$display("$clog2(10)", $clog2(10+1));
l_reg <= 32'b10000000000000000000000000000001;
r_reg <= 32'b10101011010101011010101101010101;
tb_clk <= 0;
tb_clk <= 0;
ccc <=0;
repeat (10*4000) begin
#10;
tb_clk <= 1;
ccc <= ccc +1'b1;
#10;
tb_clk <= 0;
ccc <= ccc +1'b1;
#10;
tb_clk <= 1;
ccc <= ccc +1'b1;
#10;
tb_clk <= 0;
ccc <= ccc +1'b1;
end
$display("finished OK!");
$finish;
end
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module tlb (
input clk,
input reset,
input flush,
input vm_enable,
input enable,
input [31:0] virtual_address,
output reg [31:0] physical_address,
output reg tlb_hit,
output reg translation_required,
input [31:0] translated_address,
input translation_complete
);
localparam TLB_ENTRIES = 4;
reg [1:0] entry; /* Next one to replace */
reg [40:0] tlb [TLB_ENTRIES-1:0];
integer i, j;
always @ (posedge clk) begin
if (reset || flush) begin
for (j = 0; j < TLB_ENTRIES; j = j + 1) begin
tlb[j] = 41'b0;
end
entry = 0;
end
end
localparam S_CHECK = 0;
localparam S_WAIT = 1;
reg state;
reg next_state;
always @ (posedge clk) begin
if (reset)
state <= S_CHECK;
else
state <= next_state;
end
always @ (*) begin
case (state)
S_CHECK: begin
tlb_hit = 0;
/* Check each TLB entry for a match */
for (i = 0; i < TLB_ENTRIES; i = i + 1) begin
if (virtual_address[31:12] == tlb[i][39:20] && tlb[i][40]) begin
physical_address = {tlb[i][19:0], virtual_address[11:0]};
tlb_hit = 1;
end
end
translation_required = !tlb_hit && enable && vm_enable;
next_state = !translation_required ? S_CHECK : S_WAIT;
end
S_WAIT:
next_state = translation_complete ? S_CHECK : S_WAIT;
default:
next_state = S_CHECK;
endcase
end
always @ (*) begin
if (state == S_WAIT && translation_complete) begin
tlb[entry] = {1'b1, virtual_address[31:12], translated_address[31:12]};
entry = entry + 1;
end
end
endmodule
|
`timescale 1ns / 1ps
// This module is a third order delta/sigma modulator
// It uses no multiply only shifts by 1, 2 or 13
// There are only 7 adders used, it takes around 110 LUTs
module hq_dac
(
input reset,
input clk,
input clk_ena,
input [19:0] pcm_in,
output reg dac_out
);
// ======================================
// ============== Stage #1 ==============
// ======================================
wire [23:0] w_data_in_p0;
wire [23:0] w_data_err_p0;
wire [23:0] w_data_int_p0;
reg [23:0] r_data_fwd_p1;
// PCM input extended to 24 bits
assign w_data_in_p0 = { {4{pcm_in[19]}}, pcm_in };
// Error between the input and the quantizer output
assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
// First integrator adder
assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+ r_data_fwd_p1;
// First integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p1 <= 24'd0;
else if (clk_ena)
r_data_fwd_p1 <= w_data_int_p0;
// ======================================
// ============== Stage #2 ==============
// ======================================
wire [23:0] w_data_fb1_p1;
wire [23:0] w_data_fb2_p1;
wire [23:0] w_data_lpf_p1;
reg [23:0] r_data_lpf_p2;
// Feedback from the quantizer output
assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
- { {3{w_data_qt_p2[23]}}, w_data_qt_p2[22:2] }; // Divide by 4
// Feedback from the third stage
assign w_data_fb2_p1 = w_data_fb1_p1
- { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
// Low pass filter
assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
// Low pass filter feedback delay
always @(posedge reset or posedge clk)
if (reset)
r_data_lpf_p2 <= 24'd0;
else if (clk_ena)
r_data_lpf_p2 <= w_data_lpf_p1;
// ======================================
// ============== Stage #3 ==============
// ======================================
wire [23:0] w_data_fb3_p1;
wire [23:0] w_data_int_p1;
reg [23:0] r_data_fwd_p2;
// Feedback from the quantizer output
assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
- { {2{w_data_qt_p2[23]}}, w_data_qt_p2[22:1] }; // Divide by 2
// Second integrator adder
assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
// Second integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p2 <= 24'd0;
else if (clk_ena)
r_data_fwd_p2 <= w_data_int_p1;
// =====================================
// ========== 1-bit quantizer ==========
// =====================================
wire [23:0] w_data_qt_p2;
assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
always @(posedge reset or posedge clk)
if (reset)
dac_out <= 1'b0;
else if (clk_ena)
dac_out <= ~r_data_fwd_p2[23];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:55:04 12/14/2010
// Design Name:
// Module Name: msu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module msu(
input clkin,
input enable,
input [13:0] pgm_address,
input [7:0] pgm_data,
input pgm_we,
input [2:0] reg_addr,
input [7:0] reg_data_in,
output [7:0] reg_data_out,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
output [7:0] status_out,
output [7:0] volume_out,
output volume_latch_out,
output [31:0] addr_out,
output [15:0] track_out,
input [5:0] status_reset_bits,
input [5:0] status_set_bits,
input status_reset_we,
input [13:0] msu_address_ext,
input msu_address_ext_write,
output DBG_msu_reg_oe_rising,
output DBG_msu_reg_oe_falling,
output DBG_msu_reg_we_rising,
output [13:0] DBG_msu_address,
output DBG_msu_address_ext_write_rising
);
reg [1:0] status_reset_we_r;
always @(posedge clkin) status_reset_we_r = {status_reset_we_r[0], status_reset_we};
wire status_reset_en = (status_reset_we_r == 2'b01);
reg [13:0] msu_address_r;
wire [13:0] msu_address = msu_address_r;
initial msu_address_r = 13'b0;
wire [7:0] msu_data;
reg [7:0] msu_data_r;
reg [2:0] msu_address_ext_write_sreg;
always @(posedge clkin)
msu_address_ext_write_sreg <= {msu_address_ext_write_sreg[1:0], msu_address_ext_write};
wire msu_address_ext_write_rising = (msu_address_ext_write_sreg[2:1] == 2'b01);
reg [31:0] addr_out_r;
assign addr_out = addr_out_r;
reg [15:0] track_out_r;
assign track_out = track_out_r;
reg [7:0] volume_r;
assign volume_out = volume_r;
reg volume_start_r;
assign volume_latch_out = volume_start_r;
reg audio_start_r;
reg audio_busy_r;
reg data_start_r;
reg data_busy_r;
reg ctrl_start_r;
reg audio_error_r;
reg [2:0] audio_ctrl_r;
reg [1:0] audio_status_r;
initial begin
audio_busy_r = 1'b1;
data_busy_r = 1'b1;
audio_error_r = 1'b0;
volume_r = 8'h00;
addr_out_r = 32'h00000000;
track_out_r = 16'h0000;
data_start_r = 1'b0;
audio_start_r = 1'b0;
end
assign DBG_msu_address = msu_address;
assign DBG_msu_reg_oe_rising = reg_oe_rising;
assign DBG_msu_reg_oe_falling = reg_oe_falling;
assign DBG_msu_reg_we_rising = reg_we_rising;
assign DBG_msu_address_ext_write_rising = msu_address_ext_write_rising;
assign status_out = {msu_address_r[13], // 7
audio_start_r, // 6
data_start_r, // 5
volume_start_r, // 4
audio_ctrl_r, // 3:1
ctrl_start_r}; // 0
initial msu_address_r = 14'h1234;
`ifdef MSU_DATA
`ifdef MK2
msu_databuf snes_msu_databuf (
.clka(clkin),
.wea(~pgm_we), // Bus [0 : 0]
.addra(pgm_address), // Bus [13 : 0]
.dina(pgm_data), // Bus [7 : 0]
.clkb(clkin),
.addrb(msu_address), // Bus [13 : 0]
.doutb(msu_data)
); // Bus [7 : 0]
`endif
`ifdef MK3
msu_databuf snes_msu_databuf (
.clock(clkin),
.wren(~pgm_we), // Bus [0 : 0]
.wraddress(pgm_address), // Bus [13 : 0]
.data(pgm_data), // Bus [7 : 0]
.rdaddress(msu_address), // Bus [13 : 0]
.q(msu_data)
); // Bus [7 : 0]
`endif
`endif
reg [7:0] data_out_r;
assign reg_data_out = data_out_r;
always @(posedge clkin) begin
if(msu_address_ext_write_rising)
msu_address_r <= msu_address_ext;
else if(reg_oe_rising & enable & (reg_addr == 3'h1)) begin
msu_address_r <= msu_address_r + 1;
end
end
always @(posedge clkin) begin
if(reg_oe_falling & enable)
case(reg_addr)
3'h0: data_out_r <= {data_busy_r, audio_busy_r, audio_status_r, audio_error_r, 3'b010};
3'h1: data_out_r <= msu_data;
3'h2: data_out_r <= 8'h53;
3'h3: data_out_r <= 8'h2d;
3'h4: data_out_r <= 8'h4d;
3'h5: data_out_r <= 8'h53;
3'h6: data_out_r <= 8'h55;
3'h7: data_out_r <= 8'h31;
endcase
end
always @(posedge clkin) begin
if(reg_we_rising & enable) begin
case(reg_addr)
3'h0: addr_out_r[7:0] <= reg_data_in;
3'h1: addr_out_r[15:8] <= reg_data_in;
3'h2: addr_out_r[23:16] <= reg_data_in;
3'h3: begin
addr_out_r[31:24] <= reg_data_in;
data_start_r <= 1'b1;
data_busy_r <= 1'b1;
end
3'h4: begin
track_out_r[7:0] <= reg_data_in;
end
3'h5: begin
track_out_r[15:8] <= reg_data_in;
audio_start_r <= 1'b1;
audio_busy_r <= 1'b1;
end
3'h6: begin
volume_r <= reg_data_in;
volume_start_r <= 1'b1;
end
3'h7: begin
if(!audio_busy_r) begin
audio_ctrl_r <= reg_data_in[2:0];
ctrl_start_r <= 1'b1;
end
end
endcase
end else if (status_reset_en) begin
audio_busy_r <= (audio_busy_r | status_set_bits[5]) & ~status_reset_bits[5];
if(status_reset_bits[5]) audio_start_r <= 1'b0;
data_busy_r <= (data_busy_r | status_set_bits[4]) & ~status_reset_bits[4];
if(status_reset_bits[4]) data_start_r <= 1'b0;
audio_error_r <= (audio_error_r | status_set_bits[3]) & ~status_reset_bits[3];
audio_status_r <= (audio_status_r | status_set_bits[2:1]) & ~status_reset_bits[2:1];
ctrl_start_r <= (ctrl_start_r | status_set_bits[0]) & ~status_reset_bits[0];
end else begin
volume_start_r <= 1'b0;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram1_ddr1_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram1_ddr1_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_2_V
`define SKY130_FD_SC_HVL__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_2_V
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module soc_for_linux(
input clk_i,
input rst_i,
//ssram interface
output [18:0] ssram_address,
output ssram_oe_n,
output ssram_writeen_n,
output ssram_byteen0_n,
output ssram_byteen1_n,
output ssram_byteen2_n,
output ssram_byteen3_n,
inout [31:0] ssram_data,
output ssram_clk,
//output ssram_mode,
//output ssram_zz,
output ssram_globalw_n,
output ssram_advance_n,
output ssram_adsp_n,
output ssram_adsc_n,
output ssram_ce1_n,
output ssram_ce2,
output ssram_ce3_n,
//sd interface
output sd_clk_o,
inout sd_cmd_io,
inout sd_dat_io,
//serial interface
input uart_rxd,
input uart_rts,
output uart_txd,
output uart_cts,
//debug
output [5:0] sd_debug,
output [7:0] pc_debug
);
assign pc_debug = 8'd0;
/*
MASTER ao68000 connected with SLAVES: ssram, serial_txd
MASTER sd connected with SLAVES: ssram
MASTER early_boot connected with SLAVES: sd
Address space:
SLAVE sd: 0x30000000 - 0x30000003 /not used - point to point connection/
SLAVE ssram: 0x00000000 - 0x00100000
SLAVE serial_txt: 0x38000000 - 0x38000000
*/
/***********************************************************************************************************************
* MASTER ao68000
**********************************************************************************************************************/
//------------------------------------- global wires
//output
wire ao68000_cyc_o;
wire [31:2] ao68000_adr_o;
wire [31:0] ao68000_dat_o;
wire [3:0] ao68000_sel_o;
wire ao68000_stb_o;
wire ao68000_we_o;
ao68000 m_ao68000(
//****************** WISHBONE
.CLK_I(clk_i),
.reset_n((early_boot_loading_finished_o == 1'b1) ? 1'b1 : 1'b0),
.CYC_O(ao68000_cyc_o),
.ADR_O(ao68000_adr_o),
.DAT_O(ao68000_dat_o),
.DAT_I( ssram_dat_o ),
.SEL_O(ao68000_sel_o),
.STB_O(ao68000_stb_o),
.WE_O(ao68000_we_o),
.ACK_I( (ao68000_adr_o[31:2] == 30'h38000000) ? serial_txd_ack_o : ssram_ack_o ),
.ERR_I(1'b0),
.RTY_I(timer_rty_o),
// TAG_TYPE: TGC_O
.SGL_O(),
.BLK_O(),
.RMW_O(),
// TAG_TYPE: TGA_O
.CTI_O(),
.BTE_O(),
// TAG_TYPE: TGC_O
.fc_o(),
//****************** OTHER
/* interrupt acknowlege:
* ACK_I: interrupt vector on DAT_I[7:0]
* ERR_I: spurious interrupt
* RTY_I: autovector
*/
.ipl_i( {2'b00, timer_interrupt_o} ),
.reset_o(),
.blocked_o()
);
/***********************************************************************************************************************
* SLAVE timer
**********************************************************************************************************************/
//------------------------------------- global wires
//output
wire timer_interrupt_o;
wire timer_rty_o;
//input
timer m_timer(
.CLK_I(clk_i),
.RST_I(rst_i),
.ADR_I(ao68000_adr_o),
.CYC_I(ao68000_cyc_o),
.STB_I(ao68000_stb_o),
.WE_I(ao68000_we_o),
.RTY_O(timer_rty_o),
.interrupt_o(timer_interrupt_o)
);
/***********************************************************************************************************************
* SLAVE ssram
**********************************************************************************************************************/
//------------------------------------- global wires
//output
wire [31:0] ssram_dat_o;
wire ssram_ack_o;
//input
ssram m_ssram(
.CLK_I(clk_i),
.RST_I(rst_i),
//slave
.DAT_O(ssram_dat_o),
.DAT_I((early_boot_loading_finished_o == 1'b1) ? ao68000_dat_o : sd_dat_o),
.ACK_O(ssram_ack_o),
.CYC_I((early_boot_loading_finished_o == 1'b1) ?
( (ao68000_adr_o[31:2] >= 30'h0 && ao68000_adr_o[31:2] < 30'h00080000) ? ao68000_cyc_o : 1'b0 ) :
sd_cyc_o
),
.ADR_I((early_boot_loading_finished_o == 1'b1) ? ao68000_adr_o[20:2] : sd_adr_o[20:2]),
.STB_I((early_boot_loading_finished_o == 1'b1) ?
( (ao68000_adr_o[31:2] >= 30'h0 && ao68000_adr_o[31:2] < 30'h00080000) ? ao68000_stb_o : 1'b0 ) :
sd_stb_o
),
.WE_I((early_boot_loading_finished_o == 1'b1) ? ao68000_we_o : sd_we_o),
.SEL_I((early_boot_loading_finished_o == 1'b1) ? ao68000_sel_o : sd_sel_o),
//ssram interface
.ssram_address(ssram_address),
.ssram_oe_n(ssram_oe_n),
.ssram_writeen_n(ssram_writeen_n),
.ssram_byteen0_n(ssram_byteen0_n),
.ssram_byteen1_n(ssram_byteen1_n),
.ssram_byteen2_n(ssram_byteen2_n),
.ssram_byteen3_n(ssram_byteen3_n),
.ssram_data(ssram_data),
.ssram_clk(ssram_clk),
.ssram_mode(), //ssram_mode),
.ssram_zz(), //ssram_zz),
.ssram_globalw_n(ssram_globalw_n),
.ssram_advance_n(ssram_advance_n),
.ssram_adsp_n(ssram_adsp_n),
.ssram_adsc_n(ssram_adsc_n),
.ssram_ce1_n(ssram_ce1_n),
.ssram_ce2(ssram_ce2),
.ssram_ce3_n(ssram_ce3_n)
);
/***********************************************************************************************************************
* MASTER and SLAVE sd
**********************************************************************************************************************/
//------------------------------------- global wires: master
//output
wire sd_cyc_o;
wire [31:0] sd_dat_o;
wire sd_stb_o;
wire sd_we_o;
wire [31:2] sd_adr_o;
wire [3:0] sd_sel_o;
//input
//------------------------------------- global wires: slave
//output
wire [31:0] sd_slave_dat_o;
wire sd_ack_o;
sd m_sd(
.CLK_I(clk_i),
.RST_I(rst_i),
.CYC_O(sd_cyc_o),
.DAT_O(sd_dat_o),
.STB_O(sd_stb_o),
.WE_O(sd_we_o),
.ADR_O(sd_adr_o),
.SEL_O(sd_sel_o),
.DAT_I(ssram_dat_o),
.ACK_I( (early_boot_loading_finished_o == 1'b1) ? 1'b0 : ssram_ack_o),
.ERR_I(1'b0),
.RTY_I(1'b0),
// TAG_TYPE: TGC_O
.SGL_O(),
.BLK_O(),
.RMW_O(),
// TAG_TYPE: TGA_O
.CTI_O(),
.BTE_O(),
//slave
.slave_DAT_O(sd_slave_dat_o),
.slave_DAT_I(early_boot_dat_o),
.ACK_O(sd_ack_o),
.ERR_O(),
.RTY_O(),
.CYC_I(early_boot_cyc_o),
.ADR_I(early_boot_adr_o[3:2]),
.STB_I(early_boot_stb_o),
.WE_I(early_boot_we_o),
.SEL_I(early_boot_sel_o),
//sd bus 1-bit interface
.sd_clk_o(sd_clk_o),
.sd_cmd_io(sd_cmd_io),
.sd_dat_io(sd_dat_io),
.debug_leds(sd_debug)
);
/***********************************************************************************************************************
* SLAVE serial_txd
**********************************************************************************************************************/
//------------------------------------- global wires
//output
wire serial_txd_ack_o;
//input
serial_txd m_serial_txd(
.CLK_I(clk_i),
.RST_I(rst_i),
//slave
.DAT_I( (ao68000_adr_o[31:2] == 30'h38000000) ?
(
(ao68000_sel_o[3] == 1'b1) ? ao68000_dat_o[31:24] :
(ao68000_sel_o[2] == 1'b1) ? ao68000_dat_o[23:16] :
(ao68000_sel_o[1] == 1'b1) ? ao68000_dat_o[15:8] :
(ao68000_sel_o[0] == 1'b1) ? ao68000_dat_o[7:0] :
8'hFF
) :
8'hFE ),
.ACK_O(serial_txd_ack_o),
.CYC_I( (ao68000_adr_o[31:2] == 30'h38000000) ? ao68000_cyc_o : 1'b0 ),
.STB_I( (ao68000_adr_o[31:2] == 30'h38000000) ? ao68000_stb_o : 1'b0 ),
.WE_I( ao68000_we_o ),
//serial interface
.uart_rxd(uart_rxd),
.uart_rts(uart_rts),
.uart_txd(uart_txd),
.uart_cts(uart_cts)
);
/***********************************************************************************************************************
* MASTER early_boot
**********************************************************************************************************************/
//------------------------------------- global wires
//output
wire early_boot_cyc_o;
wire [31:0] early_boot_dat_o;
wire early_boot_stb_o;
wire early_boot_we_o;
wire [31:2] early_boot_adr_o;
wire [3:0] early_boot_sel_o;
wire early_boot_loading_finished_o;
//input
early_boot m_early_boot(
.CLK_I(clk_i),
.RST_I(rst_i),
.CYC_O(early_boot_cyc_o),
.DAT_O(early_boot_dat_o),
.STB_O(early_boot_stb_o),
.WE_O(early_boot_we_o),
.ADR_O(early_boot_adr_o),
.SEL_O(early_boot_sel_o),
.DAT_I(sd_slave_dat_o),
.ACK_I(sd_ack_o),
.ERR_I(1'b0),
.RTY_I(1'b0),
//****************** OTHER
.loading_finished_o(early_boot_loading_finished_o)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlygate4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_SYMBOL_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_SYMBOL_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_di_buffer (
clock,
data,
rdaddress,
wraddress,
wren,
q,
clear);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 4;
parameter NUM_WORDS = 16;
input clock;
input [DATA_WIDTH-1:0] data;
input [ADDR_WIDTH-1:0] rdaddress;
input [ADDR_WIDTH-1:0] wraddress;
input wren;
output [DATA_WIDTH-1:0] q;
input clear;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
// synthesis translate_off
reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] mem [0:NUM_WORDS-1];
integer i;
/*
integer j;
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
for (j = 0; j < DATA_WIDTH/32; j = j+ 1) begin
mem[i][32*j+:32] <= i*(DATA_WIDTH/32) + j;
end
end
end
else begin
q <= mem[rdaddress];
end
end
*/
always @(posedge clock or posedge clear) begin
if (clear) begin
for (i = 0; i < NUM_WORDS; i = i + 1) begin
mem[i] <= 0;
end
end
else begin
if (wren)
mem[wraddress] <= data;
q <= mem[rdaddress];
end
end
// synthesis translate_on
// synthesis read_comments_as_HDL on
// wire [DATA_WIDTH-1:0] sub_wire0;
// wire [DATA_WIDTH-1:0] q = sub_wire0[DATA_WIDTH-1:0];
//
// altsyncram altsyncram_component (
// .address_a (wraddress),
// .clock0 (clock),
// .data_a (data),
// .wren_a (wren),
// .address_b (rdaddress),
// .q_b (sub_wire0),
// .aclr0 (1'b0),
// .aclr1 (1'b0),
// .addressstall_a (1'b0),
// .addressstall_b (1'b0),
// .byteena_a (1'b1),
// .byteena_b (1'b1),
// .clock1 (1'b1),
// .clocken0 (1'b1),
// .clocken1 (1'b1),
// .clocken2 (1'b1),
// .clocken3 (1'b1),
// .data_b ({DATA_WIDTH{1'b1}}),
// .eccstatus (),
// .q_a (),
// .rden_a (1'b1),
// .rden_b ((rdaddress < NUM_WORDS) ? 1'b1 : 1'b0),
// .wren_b (1'b0));
// defparam
// altsyncram_component.address_aclr_b = "NONE",
// altsyncram_component.address_reg_b = "CLOCK0",
// altsyncram_component.clock_enable_input_a = "BYPASS",
// altsyncram_component.clock_enable_input_b = "BYPASS",
// altsyncram_component.clock_enable_output_b = "BYPASS",
// altsyncram_component.intended_device_family = "Stratix III",
// altsyncram_component.lpm_type = "altsyncram",
// altsyncram_component.numwords_a = NUM_WORDS,
// altsyncram_component.numwords_b = NUM_WORDS,
// altsyncram_component.operation_mode = "DUAL_PORT",
// altsyncram_component.outdata_aclr_b = "NONE",
// altsyncram_component.outdata_reg_b = "UNREGISTERED",
// altsyncram_component.power_up_uninitialized = "FALSE",
// altsyncram_component.ram_block_type = "MLAB",
// altsyncram_component.widthad_a = ADDR_WIDTH,
// altsyncram_component.widthad_b = ADDR_WIDTH,
// altsyncram_component.width_a = DATA_WIDTH,
// altsyncram_component.width_b = DATA_WIDTH,
// altsyncram_component.width_byteena_a = 1;
// synthesis read_comments_as_HDL off
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_37x512_hf.v
// /___/ /\ Timestamp: Thu Nov 8 18:46:39 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512_hf.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512_hf.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512_hf.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_37x512_hf.v
// # of Modules : 1
// Design Name : fifo_37x512_hf
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_37x512_hf (
clk, rd_en, empty, wr_en, full, srst, data_count, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [0 : 0] data_count;
output [36 : 0] dout;
input [36 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_60 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_63 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_65 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_67 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_69 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_71 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_73 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_75 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_77 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_125 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_126 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_130 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_132 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_134 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_136 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_138 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_140 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_142 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_144 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [8 : 0] Result;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count ;
wire [8 : 8] \NlwRenamedSig_OI_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_60 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_126 ,
data_count[0] = \NlwRenamedSig_OI_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [8];
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en ),
.D(Result[8]),
.R(srst),
.Q(\NlwRenamedSig_OI_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [8])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<0> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [0]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<0> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [0]),
.O(Result[0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [0]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [1]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [1]),
.O(Result[1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [1]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [2]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [2]),
.O(Result[2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [2]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [3]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [3]),
.O(Result[3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [3]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [4]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [4]),
.O(Result[4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [4]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [5]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [5]),
.O(Result[5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [5]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [6]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [6]),
.O(Result[6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [6]),
.DI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [7]),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [7]),
.O(Result[7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [8]),
.O(Result[8])
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_60 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_125 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_126 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_77 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_75 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_75 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_73 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_73 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_71 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_71 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_69 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_69 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_67 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_67 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_65 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_65 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_63 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_63 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_144 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_142 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_142 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_140 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_140 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_138 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_138 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_136 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_136 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_134 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_134 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_132 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_132 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_130 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_130 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_125 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_125 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_75 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_73 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_71 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_69 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_67 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_65 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_63 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_142 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_140 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_138 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_136 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_134 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_132 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_130 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_77 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_144 )
);
LUT3 #(
.INIT ( 8'h39 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<0> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [0]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [0])
);
LUT3 #(
.INIT ( 8'hC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<1> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [1])
);
LUT3 #(
.INIT ( 8'hC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<2> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [2]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [2])
);
LUT3 #(
.INIT ( 8'hC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<3> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [3])
);
LUT3 #(
.INIT ( 8'hC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<4> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [4]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [4])
);
LUT3 #(
.INIT ( 8'hC6 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<5> (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [5])
);
LUT3 #(
.INIT ( 8'h9A ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<6> (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [6]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I2(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [6])
);
LUT3 #(
.INIT ( 8'h9A ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<7> (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I2(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [7])
);
LUT3 #(
.INIT ( 8'h9A ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut<8> (
.I0(\NlwRenamedSig_OI_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I2(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/dc/Mcount_count_lut [8])
);
LUT4 #(
.INIT ( 16'h6530 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/Mxor_cntr_en_Result1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_58 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_125 ),
.I2(wr_en),
.I3(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.gdc.dc/cntr_en )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({N0, N0, N0, N0, din[36], din[35], din[34], din[33], N0, N0, N0, din[32], din[31], din[30], din[29], din[28], N0, N0, N0, N0, din[27], din[26]
, din[25], din[24], N0, N0, N0, din[23], din[22], din[21], din[20], din[19], N0, N0, N0, N0, din[18], din[17], din[16], din[15], N0, N0, N0, din[14],
din[13], din[12], din[11], din[10], N0, N0, N0, din[9], din[8], din[7], din[6], din[5], N0, N0, N0, din[4], din[3], din[2], din[1], din[0]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<62>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<61>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<60>_UNCONNECTED
, dout[36], dout[35], dout[34], dout[33],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<55>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<54>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<53>_UNCONNECTED
, dout[32], dout[31], dout[30], dout[29], dout[28],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<46>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<45>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<44>_UNCONNECTED
, dout[27], dout[26], dout[25], dout[24],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<39>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<38>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<37>_UNCONNECTED
, dout[23], dout[22], dout[21], dout[20], dout[19],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<30>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<29>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<28>_UNCONNECTED
, dout[18], dout[17], dout[16], dout[15],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<23>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<22>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<21>_UNCONNECTED
, dout[14], dout[13], dout[12], dout[11], dout[10],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<14>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<13>_UNCONNECTED
, dout[9], dout[8], dout[7], dout[6], dout[5],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<5>_UNCONNECTED
, dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2B_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_TB_V
`define SKY130_FD_SC_LP__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_TB_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_TB_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso0p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso0p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_TB_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_7x16_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_7x16_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [6:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [6:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [6:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [6:0] q = sub_wire3[6:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 12,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 7,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "12"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "7"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "7"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "12"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=MLAB"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL "data[6..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL "q[6..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 7 0 data 0 0 7 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 7 0 @q 0 0 7 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_7x16_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:17 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb565_to_rgb888_0_0 -prefix
// system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_1_0_stub.v
// Design : system_rgb565_to_rgb888_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_0_0(rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="rgb_565[15:0],rgb_888[23:0]" */;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
/**
* srdlxtp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ../demo-out/iscachable.v
// {{{
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ./autofpga ./autofpga -d -o ../demo-out -I ../auto-data bkram.txt buserr.txt clkcounter.txt clock.txt enet.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt icape.txt legalgen.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt sdram.txt sdspi.txt spio.txt version.txt wbmouse.txt wboledbw.txt wbpmic.txt wbscopc.txt wbscope.txt wbubus.txt xpander.txt zipmaster.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
//
module iscachable(
// {{{
input wire [30-1:0] i_addr,
output reg o_cachable
// }}}
);
always @(*)
begin
o_cachable = 1'b0;
// Bus master: wb
// Bus master: wb_dio
// Bus master: wb_sio
// bkram
if ((i_addr[29:0] & 30'h3e000000) == 30'h1a000000)
o_cachable = 1'b1;
// flash
if ((i_addr[29:0] & 30'h3e000000) == 30'h1c000000)
o_cachable = 1'b1;
// Bus master: rambus
// sdram
if ((i_addr[29:0] & 30'h20000000) == 30'h20000000)
o_cachable = 1'b1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_TB_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_ps_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SET = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER = 1'b1;
#220 SET = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER = 1'b0;
#360 SET = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 SET = 1'b1;
#520 NOTIFIER = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 SET = 1'bx;
#660 NOTIFIER = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PS_pp$PKG$sN dut (.D(D), .SET(SET), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_SN_TB_V
|
// file: clock_generator.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT2____50.000______0.000______50.0______151.636_____98.575
// CLK_OUT3___100.000______0.000______50.0______130.958_____98.575
// CLK_OUT4___100.000______0.000______50.0______130.958_____98.575
// CLK_OUT5___100.000______0.000______50.0______130.958_____98.575
// CLK_OUT6___100.000______0.000______50.0______130.958_____98.575
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clock_generator,clk_wiz_v3_4,{component_name=clock_generator,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=6,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clock_generator
(// Clock in ports
input sysClk,
// Clock out ports
output cpuClk_o,
output wbClk_o,
output usbClk_o,
output phyClk0_o,
output phyClk1_o,
output fftClk_o,
// Status and control signals
input RESET
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (20),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (10),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (10),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (10),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKOUT5_DIVIDE (10),
.CLKOUT5_PHASE (0.000),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKOUT5_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
// .CLKOUT0 (clkout0),
.CLKOUT0 (cpuClk),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (wbClk),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (usbClk),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (phyClk0),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (phyClk1),
.CLKOUT5 (fftClk),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
// .CLKIN1 (clkin1),
.CLKIN1 (sysClk),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (cpuClk_o),
.I (cpuClk));
BUFG clkout2_buf
(.O (wbClk_o),
.I (wbClk));
BUFG clkout3_buf
(.O (usbClk_o),
.I (usbClk));
BUFG clkout4_buf
(.O (phyClk0_o),
.I (phyClk0));
BUFG clkout5_buf
(.O (phyClk1_o),
.I (phyClk1));
BUFG clkout6_buf
(.O (fftClk_o),
.I (fftClk));
endmodule
|
////////////////////////////////////////////////////////
////Author:
////Date:
////////////////////////////////////////////////////////
module decoder(
input [5:0] opcode,
output reg writeRd,
output reg RegDest,
output reg isDispatch,
output reg mem_wen,
output reg mem_ren,
output reg read_rs,
output reg read_rt,
output reg alloc_RS_en,
output reg ldic,
output reg isSignEx,
output reg isImmed,
output reg alu_ctrl0,
output reg alu_ctrl1,
output reg alu_ctrl2,
output reg alu_ctrl3,
output reg isJump,
output reg isJR,
output reg link
);
localparam NOP = 6'b000000;
localparam ADD = 6'b000001;
localparam ADDI = 6'b000010;
localparam SUB = 6'b000011;
localparam LUI = 6'b000100;
localparam MOV = 6'b000101;
localparam SLL = 6'b000110;
localparam SRA = 6'b000111;
localparam SRL = 6'b001000;
localparam AND = 6'b001001;
localparam ANDI = 6'b001010;
localparam NOT = 6'b001011;
localparam OR = 6'b001100;
localparam ORI = 6'b001101;
localparam XOR = 6'b001110;
localparam XORI = 6'b001111;
localparam LW = 6'b010001;
localparam SW = 6'b010010;
localparam B = 6'b010011;
localparam BEQ = 6'b010100;
localparam BGT = 6'b010101;
localparam BGE = 6'b010110;
localparam BLE = 6'b010111;
localparam BLT = 6'b011000;
localparam BNE = 6'b011001;
localparam J = 6'b011010;
localparam JAL = 6'b011011;
localparam JALR = 6'b011100;
localparam JR = 6'b011101;
localparam STRCNT = 6'b100000;
localparam STPCNT = 6'b100001;
localparam LDCC = 6'b100010;
localparam LDIC = 6'b100011;
localparam TX = 6'b110000;
localparam HALT = 6'b110001;
localparam ADDB = 6'b010100;
localparam ADDBI = 6'b010101;
localparam SUBB = 6'b010110;
localparam SUBBI = 6'b010111;
wire [5:0] ctrl_codes = opcode;
always @(ctrl_codes) begin
case(ctrl_codes)
NOP: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADD: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADDI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 1;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SUB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
LUI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
MOV: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SLL: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SRA: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SRL: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
AND: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ANDI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
NOT: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
OR: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
ORI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
XOR: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
XORI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
LW: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 1;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
SW: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 1;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
B: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BEQ: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BGT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BGE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BLE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BLT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
BNE: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
J: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 0;
link = 0;
end
JAL: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 0;
link = 1;
end
JALR: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 1;
link = 1;
end
JR: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 1;
isJR = 1;
link = 0;
end
STRCNT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
STPCNT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
LDCC: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
LDIC: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 1;
ldic = 1;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
TX: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
HALT: begin
writeRd = 0;
RegDest = 0;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
ADDB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 1;
alu_ctrl2 = 0;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
ADDBI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
SUBB: begin
writeRd = 1;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 1;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 1;
alu_ctrl1 = 0;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
SUBBI: begin
writeRd = 0;
RegDest = 1;
isDispatch = 1;
mem_wen = 0;
mem_ren = 0;
read_rs = 1;
read_rt = 0;
alloc_RS_en = 1;
ldic = 0;
isSignEx = 0;
isImmed = 1;
alu_ctrl0 = 0;
alu_ctrl1 = 1;
alu_ctrl2 = 1;
alu_ctrl3 = 1;
isJump = 0;
isJR = 0;
link = 0;
end
default: begin
writeRd = 0;
RegDest = 0;
isDispatch = 0;
mem_wen = 0;
mem_ren = 0;
read_rs = 0;
read_rt = 0;
alloc_RS_en = 0;
ldic = 0;
isSignEx = 0;
isImmed = 0;
alu_ctrl0 = 0;
alu_ctrl1 = 0;
alu_ctrl2 = 0;
alu_ctrl3 = 0;
isJump = 0;
isJR = 0;
link = 0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconcat_0_0/RAT_xlconcat_0_0_sim_netlist.v
// Design : RAT_xlconcat_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_xlconcat_0_0,xlconcat,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "xlconcat,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_xlconcat_0_0
(In0,
In1,
dout);
input [7:0]In0;
input [1:0]In1;
output [9:0]dout;
wire [7:0]In0;
wire [1:0]In1;
assign dout[9:8] = In1;
assign dout[7:0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1_N (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_N_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTP_FUNCTIONAL_PP_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430_fpga;
//
// Wire & Register definition
//------------------------------
// Clock & Reset
reg oscclk;
reg porst_n;
reg pbrst_n;
// Slide Switches
reg [9:0] switch;
// LEDs
wire [9:0] led;
// UART
wire dbg_uart_rxd;
wire dbg_uart_txd;
reg dbg_uart_rxd_sel;
reg dbg_uart_rxd_dly;
reg dbg_uart_rxd_pre;
reg dbg_uart_rxd_meta;
reg [15:0] dbg_uart_buf;
reg dbg_uart_rx_busy;
reg dbg_uart_tx_busy;
// Core debug signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer i;
integer error;
reg stimulus_done;
wire [11:0] vout_x;
wire [11:0] vout_y;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers.v"
// Debug interface tasks
`include "dbg_uart_tasks.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Program Memory
//------------------------------
initial
begin
// Read memory file
#10 $readmemh("./pmem.mem", pmem);
// Update Actel memory banks
for (i=0; i<512; i=i+1)
begin
dut.dmem_hi.dmem_128B_R0C0.MEM_512_9[i] = {1'b0, 8'h00};
dut.dmem_lo.dmem_128B_R0C0.MEM_512_9[i] = {1'b0, 8'h00};
dut.pmem_hi.pmem_2kB_R0C0.MEM_512_9[i] = {1'b0, pmem[i*4+3][9:8], pmem[i*4+2][9:8], pmem[i*4+1][9:8], pmem[i*4+0][9:8]};
dut.pmem_hi.pmem_2kB_R0C1.MEM_512_9[i] = {1'b0, pmem[i*4+3][11:10], pmem[i*4+2][11:10], pmem[i*4+1][11:10], pmem[i*4+0][11:10]};
dut.pmem_hi.pmem_2kB_R0C2.MEM_512_9[i] = {1'b0, pmem[i*4+3][13:12], pmem[i*4+2][13:12], pmem[i*4+1][13:12], pmem[i*4+0][13:12]};
dut.pmem_hi.pmem_2kB_R0C3.MEM_512_9[i] = {1'b0, pmem[i*4+3][15:14], pmem[i*4+2][15:14], pmem[i*4+1][15:14], pmem[i*4+0][15:14]};
dut.pmem_lo.pmem_2kB_R0C0.MEM_512_9[i] = {1'b0, pmem[i*4+3][1:0], pmem[i*4+2][1:0], pmem[i*4+1][1:0], pmem[i*4+0][1:0]};
dut.pmem_lo.pmem_2kB_R0C1.MEM_512_9[i] = {1'b0, pmem[i*4+3][3:2], pmem[i*4+2][3:2], pmem[i*4+1][3:2], pmem[i*4+0][3:2]};
dut.pmem_lo.pmem_2kB_R0C2.MEM_512_9[i] = {1'b0, pmem[i*4+3][5:4], pmem[i*4+2][5:4], pmem[i*4+1][5:4], pmem[i*4+0][5:4]};
dut.pmem_lo.pmem_2kB_R0C3.MEM_512_9[i] = {1'b0, pmem[i*4+3][7:6], pmem[i*4+2][7:6], pmem[i*4+1][7:6], pmem[i*4+0][7:6]};
end
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
oscclk = 1'b0;
forever #10.4 oscclk <= ~oscclk; // 48 MHz
end
initial
begin
porst_n = 1'b1;
pbrst_n = 1'b1;
#100;
porst_n = 1'b0;
pbrst_n = 1'b0;
#600;
porst_n = 1'b1;
pbrst_n = 1'b1;
end
//
// Global initialization
//------------------------------
initial
begin
error = 0;
stimulus_done = 1;
switch = 10'h000;
dbg_uart_rxd_sel = 1'b0;
dbg_uart_rxd_dly = 1'b1;
dbg_uart_rxd_pre = 1'b1;
dbg_uart_rxd_meta= 1'b0;
dbg_uart_rx_busy = 1'b0;
dbg_uart_tx_busy = 1'b0;
end
//
// openMSP430 FPGA Instance
//----------------------------------
openMSP430_fpga dut (
// OUTPUTs
.din_x (din_x), // SPI Serial Data
.din_y (din_y), // SPI Serial Data
.led (led), // Board LEDs
.sclk_x (sclk_x), // SPI Serial Clock
.sclk_y (sclk_y), // SPI Serial Clock
.sync_n_x (sync_n_x), // SPI Frame synchronization signal (low active)
.sync_n_y (sync_n_y), // SPI Frame synchronization signal (low active)
.uart_tx (dbg_uart_txd), // Board UART TX pin
// INPUTs
.oscclk (oscclk), // Board Oscillator (?? MHz)
.porst_n (porst_n), // Board Power-On reset (active low)
.pbrst_n (pbrst_n), // Board Push-Button reset (active low)
.uart_rx (dbg_uart_rxd), // Board UART RX pin
.switch (switch) // Board Switches
);
//
// 12 BIT DACs
//----------------------------------------
DAC121S101 DAC121S101_x (
// OUTPUTs
.vout (vout_x), // Peripheral data output
// INPUTs
.din (din_x), // SPI Serial Data
.sclk (sclk_x), // SPI Serial Clock
.sync_n (sync_n_x) // SPI Frame synchronization signal (low active)
);
DAC121S101 DAC121S101_y (
// OUTPUTs
.vout (vout_y), // Peripheral data output
// INPUTs
.din (din_y), // SPI Serial Data
.sclk (sclk_y), // SPI Serial Clock
.sync_n (sync_n_y) // SPI Frame synchronization signal (low active)
);
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
// OUTPUTs
.e_state (e_state), // Execution state
.i_state (i_state), // Instruction fetch state
.inst_cycle (inst_cycle), // Cycle number within current instruction
.inst_full (inst_full), // Currently executed instruction (full version)
.inst_number (inst_number), // Instruction number since last system reset
.inst_pc (inst_pc), // Instruction Program counter
.inst_short (inst_short), // Currently executed instruction (short version)
// INPUTs
.mclk (mclk), // Main system clock
.puc_rst (puc_rst) // Main system reset
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
#500000;
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
end
initial // Normal end of test
begin
@(inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule
|
`timescale 1ns / 100ps
`include "parameter.v"
module waveletl3 (r_peak_ref,r_peak_pos_ref,
start_qrs_fin_2,end_qrs_fin_2,
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799,data_in,clk,nReset);
output signed [15:0] r_peak_ref,r_peak_pos_ref,
start_qrs_fin_2,end_qrs_fin_2,
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799;
wire [15:0]
cA0_l3,cA1_l3,cA2_l3,cA3_l3,cA4_l3,cA5_l3,cA6_l3,cA7_l3,cA8_l3,cA9_l3,cA10_l3,cA11_l3,cA12_l3,cA13_l3,cA14_l3,cA15_l3,cA16_l3,cA17_l3,cA18_l3,cA19_l3,cA20_l3,cA21_l3,cA22_l3,cA23_l3,cA24_l3,cA25_l3_l3,cA26_l3,cA27_l3,cA28_l3,cA29_l3,cA30_l3,cA31_l3,cA32_l3,cA33_l3,cA34_l3,cA35_l3,cA36_l3,cA37_l3,cA38_l3,cA39_l3,cA40_l3,cA41_l3,cA42_l3,cA43_l3,cA44_l3,cA45_l3,cA46_l3,cA47_l3,cA48_l3,cA49_l3,cA50_l3,cA51_l3,cA52_l3,cA53_l3,cA54_l3,cA55_l3,cA56_l3,cA57_l3,cA58_l3,cA59_l3,cA60_l3,cA61_l3,cA62_l3,cA63_l3,cA64_l3,cA65_l3,cA66_l3,cA67_l3,cA68_l3,cA69_l3,cA70_l3,cA71_l3,cA72_l3,cA73_l3,cA74_l3,cA75_l3,cA76_l3,cA77_l3,cA78_l3,cA79_l3,cA80_l3,cA81_l3,cA82_l3,cA83_l3,cA84_l3,cA85_l3,cA86_l3,cA87_l3,cA88_l3,cA89_l3,cA90_l3,cA91_l3,cA92_l3,cA93_l3,cA94_l3,cA95_l3,cA96_l3,cA97_l3,cA98_l3,cA99_l3;
input [15:0] data_in;
input clk, nReset;
wire clk, nReset;
wire [3:0] count1_l3;
wire [8:0] count2_l3;
wire signed [15:0] max_pos_l3,min_pos_l3,q_begin_l3,s_end_l3,thr1,thr2,q_begin_l3_temp,s_end_l3_temp,q_begin_ref,
s_end_ref,r_begin_l3,r_end_l3,max_pos_l3_n,min_pos_l3_n;
wire qwindow1_full,swindow1_full,q_begin_l3_flag,s_end_l3_flag,cD_min_found;
level3arch l3_arch(count1_l3,count2_l3,max_pos_l3,min_pos_l3,
q_begin_l3,q_begin_l3_flag,qwindow1_full,s_end_l3,swindow1_full,
s_end_l3_flag,max_pos_l3_n,min_pos_l3_n,cD_min_found,
cA0_l3,cA1_l3,cA2_l3,cA3_l3,cA4_l3,cA5_l3,cA6_l3,cA7_l3,cA8_l3,cA9_l3,cA10_l3,cA11_l3,cA12_l3,cA13_l3,cA14_l3,cA15_l3,cA16_l3,cA17_l3,cA18_l3,cA19_l3,cA20_l3,cA21_l3,cA22_l3,cA23_l3,cA24_l3,cA25_l3_l3,cA26_l3,cA27_l3,cA28_l3,cA29_l3,cA30_l3,cA31_l3,cA32_l3,cA33_l3,cA34_l3,cA35_l3,cA36_l3,cA37_l3,cA38_l3,cA39_l3,cA40_l3,cA41_l3,cA42_l3,cA43_l3,cA44_l3,cA45_l3,cA46_l3,cA47_l3,cA48_l3,cA49_l3,cA50_l3,cA51_l3,cA52_l3,cA53_l3,cA54_l3,cA55_l3,cA56_l3,cA57_l3,cA58_l3,cA59_l3,cA60_l3,cA61_l3,cA62_l3,cA63_l3,cA64_l3,cA65_l3,cA66_l3,cA67_l3,cA68_l3,cA69_l3,cA70_l3,cA71_l3,cA72_l3,cA73_l3,cA74_l3,cA75_l3,cA76_l3,cA77_l3,cA78_l3,cA79_l3,cA80_l3,cA81_l3,cA82_l3,cA83_l3,cA84_l3,cA85_l3,cA86_l3,cA87_l3,cA88_l3,cA89_l3,cA90_l3,cA91_l3,cA92_l3,cA93_l3,cA94_l3,
cA95_l3,cA96_l3,cA97_l3,cA98_l3,cA99_l3,data_in,clk,nReset);
// QRS Refinement*********************************
qrs_refinement1 qrs_ref1(q_begin_ref,s_end_ref,q_begin_l3_temp,s_end_l3_temp,q_begin_l3,s_end_l3,s_end_l3_flag,
count1_l3,count2_l3,clk,nReset,swindow1_full,qwindow1_full,q_begin_l3_flag);
ecg_signal_max ecgmax(thr1,thr2,count1_l3,count2_l3,min_pos_l3,
max_pos_l3,data_in,clk,nReset);
rwave_refine r_ref(r_peak_ref,r_peak_pos_ref,start_qrs_fin_2,end_qrs_fin_2,
ecg0,ecg1,ecg2,ecg3,ecg4,ecg5,ecg6,ecg7,ecg8,ecg9,ecg10,ecg11,ecg12,ecg13,ecg14,ecg15,ecg16,ecg17,ecg18,ecg19,ecg20,ecg21,ecg22,ecg23,ecg24,ecg25,ecg26,ecg27,ecg28,ecg29,ecg30,ecg31,ecg32,ecg33,ecg34,ecg35,ecg36,ecg37,ecg38,ecg39,ecg40,ecg41,ecg42,ecg43,ecg44,ecg45,ecg46,ecg47,ecg48,ecg49,ecg50,ecg51,ecg52,ecg53,ecg54,ecg55,ecg56,ecg57,ecg58,ecg59,ecg60,ecg61,ecg62,ecg63,ecg64,ecg65,ecg66,ecg67,ecg68,ecg69,ecg70,ecg71,ecg72,ecg73,ecg74,ecg75,ecg76,ecg77,ecg78,ecg79,ecg80,ecg81,ecg82,ecg83,ecg84,ecg85,ecg86,ecg87,ecg88,ecg89,ecg90,ecg91,ecg92,ecg93,ecg94,ecg95,ecg96,ecg97,ecg98,ecg99,ecg100,ecg101,ecg102,ecg103,ecg104,ecg105,ecg106,ecg107,ecg108,ecg109,ecg110,ecg111,ecg112,ecg113,ecg114,ecg115,ecg116,ecg117,ecg118,ecg119,ecg120,ecg121,ecg122,ecg123,ecg124,ecg125,ecg126,ecg127,ecg128,ecg129,ecg130,ecg131,ecg132,ecg133,ecg134,ecg135,ecg136,ecg137,ecg138,ecg139,ecg140,ecg141,ecg142,ecg143,ecg144,ecg145,ecg146,ecg147,ecg148,ecg149,ecg150,ecg151,ecg152,ecg153,ecg154,ecg155,ecg156,ecg157,ecg158,ecg159,ecg160,ecg161,ecg162,ecg163,ecg164,ecg165,ecg166,ecg167,ecg168,ecg169,ecg170,ecg171,ecg172,ecg173,ecg174,ecg175,ecg176,ecg177,ecg178,ecg179,ecg180,ecg181,ecg182,ecg183,ecg184,ecg185,ecg186,ecg187,ecg188,ecg189,ecg190,ecg191,ecg192,ecg193,ecg194,ecg195,ecg196,ecg197,ecg198,ecg199,ecg200,ecg201,ecg202,ecg203,ecg204,ecg205,ecg206,ecg207,ecg208,ecg209,ecg210,ecg211,ecg212,ecg213,ecg214,ecg215,ecg216,ecg217,ecg218,ecg219,ecg220,ecg221,ecg222,ecg223,ecg224,ecg225,ecg226,ecg227,ecg228,ecg229,ecg230,ecg231,ecg232,ecg233,ecg234,ecg235,ecg236,ecg237,ecg238,ecg239,ecg240,ecg241,ecg242,ecg243,ecg244,ecg245,ecg246,ecg247,ecg248,ecg249,ecg250,ecg251,ecg252,ecg253,ecg254,ecg255,ecg256,ecg257,ecg258,ecg259,ecg260,ecg261,ecg262,ecg263,ecg264,ecg265,ecg266,ecg267,ecg268,ecg269,ecg270,ecg271,ecg272,ecg273,ecg274,ecg275,ecg276,ecg277,ecg278,ecg279,ecg280,ecg281,ecg282,ecg283,ecg284,ecg285,ecg286,ecg287,ecg288,ecg289,ecg290,ecg291,ecg292,ecg293,ecg294,ecg295,ecg296,ecg297,ecg298,ecg299,ecg300,ecg301,ecg302,ecg303,ecg304,ecg305,ecg306,ecg307,ecg308,ecg309,ecg310,ecg311,ecg312,ecg313,ecg314,ecg315,ecg316,ecg317,ecg318,ecg319,ecg320,ecg321,ecg322,ecg323,ecg324,ecg325,ecg326,ecg327,ecg328,ecg329,ecg330,ecg331,ecg332,ecg333,ecg334,ecg335,ecg336,ecg337,ecg338,ecg339,ecg340,ecg341,ecg342,ecg343,ecg344,ecg345,ecg346,ecg347,ecg348,ecg349,ecg350,ecg351,ecg352,ecg353,ecg354,ecg355,ecg356,ecg357,ecg358,ecg359,ecg360,ecg361,ecg362,ecg363,ecg364,ecg365,ecg366,ecg367,ecg368,ecg369,ecg370,ecg371,ecg372,ecg373,ecg374,ecg375,ecg376,ecg377,ecg378,ecg379,ecg380,ecg381,ecg382,ecg383,ecg384,ecg385,ecg386,ecg387,ecg388,ecg389,ecg390,ecg391,ecg392,ecg393,ecg394,ecg395,ecg396,ecg397,ecg398,ecg399,ecg400,ecg401,ecg402,ecg403,ecg404,ecg405,ecg406,ecg407,ecg408,ecg409,ecg410,ecg411,ecg412,ecg413,ecg414,ecg415,ecg416,ecg417,ecg418,ecg419,ecg420,ecg421,ecg422,ecg423,ecg424,ecg425,ecg426,ecg427,ecg428,ecg429,ecg430,ecg431,ecg432,ecg433,ecg434,ecg435,ecg436,ecg437,ecg438,ecg439,ecg440,ecg441,ecg442,ecg443,ecg444,ecg445,ecg446,ecg447,ecg448,ecg449,ecg450,ecg451,ecg452,ecg453,ecg454,ecg455,ecg456,ecg457,ecg458,ecg459,ecg460,ecg461,ecg462,ecg463,ecg464,ecg465,ecg466,ecg467,ecg468,ecg469,ecg470,ecg471,ecg472,ecg473,ecg474,ecg475,ecg476,ecg477,ecg478,ecg479,ecg480,ecg481,ecg482,ecg483,ecg484,ecg485,ecg486,ecg487,ecg488,ecg489,ecg490,ecg491,ecg492,ecg493,ecg494,ecg495,ecg496,ecg497,ecg498,ecg499,ecg500,ecg501,ecg502,ecg503,ecg504,ecg505,ecg506,ecg507,ecg508,ecg509,ecg510,ecg511,ecg512,ecg513,ecg514,ecg515,ecg516,ecg517,ecg518,ecg519,ecg520,ecg521,ecg522,ecg523,ecg524,ecg525,ecg526,ecg527,ecg528,ecg529,ecg530,ecg531,ecg532,ecg533,ecg534,ecg535,ecg536,ecg537,ecg538,ecg539,ecg540,ecg541,ecg542,ecg543,ecg544,ecg545,ecg546,ecg547,ecg548,ecg549,ecg550,ecg551,ecg552,ecg553,ecg554,ecg555,ecg556,ecg557,ecg558,ecg559,ecg560,ecg561,ecg562,ecg563,ecg564,ecg565,ecg566,ecg567,ecg568,ecg569,ecg570,ecg571,ecg572,ecg573,ecg574,ecg575,ecg576,ecg577,ecg578,ecg579,ecg580,ecg581,ecg582,ecg583,ecg584,ecg585,ecg586,ecg587,ecg588,ecg589,ecg590,ecg591,ecg592,ecg593,ecg594,ecg595,ecg596,ecg597,ecg598,ecg599,
ecg600,ecg601,ecg602,ecg603,ecg604,ecg605,ecg606,ecg607,ecg608,ecg609,ecg610,ecg611,ecg612,ecg613,ecg614,ecg615,ecg616,ecg617,ecg618,ecg619,ecg620,ecg621,ecg622,ecg623,ecg624,ecg625,ecg626,ecg627,ecg628,ecg629,ecg630,ecg631,ecg632,ecg633,ecg634,ecg635,ecg636,ecg637,ecg638,ecg639,ecg640,ecg641,ecg642,ecg643,ecg644,ecg645,ecg646,ecg647,ecg648,ecg649,ecg650,ecg651,ecg652,ecg653,ecg654,ecg655,ecg656,ecg657,ecg658,ecg659,ecg660,ecg661,ecg662,ecg663,ecg664,ecg665,ecg666,ecg667,ecg668,ecg669,ecg670,ecg671,ecg672,ecg673,ecg674,ecg675,ecg676,ecg677,ecg678,ecg679,ecg680,ecg681,ecg682,ecg683,ecg684,ecg685,ecg686,ecg687,ecg688,ecg689,ecg690,ecg691,ecg692,ecg693,ecg694,ecg695,ecg696,ecg697,ecg698,ecg699,ecg700,ecg701,ecg702,ecg703,ecg704,ecg705,ecg706,ecg707,ecg708,ecg709,ecg710,ecg711,ecg712,ecg713,ecg714,ecg715,ecg716,ecg717,ecg718,ecg719,ecg720,ecg721,ecg722,ecg723,ecg724,ecg725,ecg726,ecg727,ecg728,ecg729,ecg730,ecg731,ecg732,ecg733,ecg734,ecg735,ecg736,ecg737,ecg738,ecg739,ecg740,ecg741,ecg742,ecg743,ecg744,ecg745,ecg746,ecg747,ecg748,ecg749,ecg750,ecg751,ecg752,ecg753,ecg754,ecg755,ecg756,ecg757,ecg758,ecg759,ecg760,ecg761,ecg762,ecg763,ecg764,ecg765,ecg766,ecg767,ecg768,ecg769,ecg770,ecg771,ecg772,ecg773,ecg774,ecg775,ecg776,ecg777,ecg778,ecg779,ecg780,ecg781,ecg782,ecg783,ecg784,ecg785,ecg786,ecg787,ecg788,ecg789,ecg790,ecg791,ecg792,ecg793,ecg794,ecg795,ecg796,ecg797,ecg798,ecg799,max_pos_l3_n,min_pos_l3_n,cD_min_found,count1_l3,count2_l3,max_pos_l3,
min_pos_l3,data_in,thr1,thr2,q_begin_l3_temp,s_end_l3_temp,
q_begin_l3_flag,s_end_l3_flag,
cA0_l3,cA1_l3,cA2_l3,cA3_l3,cA4_l3,cA5_l3,cA6_l3,cA7_l3,cA8_l3,cA9_l3,cA10_l3,cA11_l3,cA12_l3,cA13_l3,cA14_l3,cA15_l3,cA16_l3,cA17_l3,cA18_l3,cA19_l3,cA20_l3,cA21_l3,cA22_l3,cA23_l3,cA24_l3,cA25_l3_l3,cA26_l3,cA27_l3,cA28_l3,cA29_l3,cA30_l3,cA31_l3,cA32_l3,cA33_l3,cA34_l3,cA35_l3,cA36_l3,cA37_l3,cA38_l3,cA39_l3,cA40_l3,cA41_l3,cA42_l3,cA43_l3,cA44_l3,cA45_l3,cA46_l3,cA47_l3,cA48_l3,cA49_l3,cA50_l3,cA51_l3,cA52_l3,cA53_l3,cA54_l3,cA55_l3,cA56_l3,cA57_l3,cA58_l3,cA59_l3,cA60_l3,cA61_l3,cA62_l3,cA63_l3,cA64_l3,cA65_l3,cA66_l3,cA67_l3,cA68_l3,cA69_l3,cA70_l3,cA71_l3,cA72_l3,cA73_l3,cA74_l3,cA75_l3,cA76_l3,cA77_l3,cA78_l3,cA79_l3,cA80_l3,cA81_l3,cA82_l3,cA83_l3,cA84_l3,cA85_l3,cA86_l3,cA87_l3,cA88_l3,cA89_l3,cA90_l3,cA91_l3,cA92_l3,cA93_l3,cA94_l3,
cA95_l3,cA96_l3,cA97_l3,cA98_l3,cA99_l3,clk,nReset);
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/17/2010
Version 2.7
This read master module is responsible for reading data from memory and writing
the contents out to a streaming source port. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as the state of the master (reset/stop) is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming
2.1 Fixed bugs in the control logic which was causing too many reads to be posted
2.2 Added burst support and renamed the top level module to read master
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Added early done support for non unaligned or non packet based transfers
2.6 Fixed a flow control issue in the pending reads counter and too many reads pending
signal to avoid potential FIFO overflow issues. The read master now requires the
FIFO depth to be 4x the maximum burst count setting.
2.7 Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
src_data,
src_valid,
src_ready,
src_sop,
src_eop,
src_empty,
src_error,
src_channel,
// data path master port
master_address,
master_read,
master_byteenable,
master_readdata,
master_waitrequest,
master_readdatavalid,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter CHANNEL_ENABLE = 0;
parameter CHANNEL_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when the channel enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set in the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0; // when enabled stride must be disabled, 1 to enable, 0 to disable
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set maximum_burst_count to 1 (will be automatically done by .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(maximum_burst_count) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value "maximum_burst_count" will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
// when packet data is supported then we need to buffer the empty, eop, sop, error, and channel bits
localparam FIFO_WIDTH = DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2 + ERROR_WIDTH + CHANNEL_WIDTH;
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // default stride distance used when stride is disabled. 1 means increment the address by a word (i.e. sequential transfer)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path source port
output wire [DATA_WIDTH-1:0] src_data;
output wire src_valid;
input src_ready;
output wire src_sop;
output wire src_eop;
output wire [NUMBER_OF_SYMBOLS_LOG2-1:0] src_empty;
output wire [ERROR_WIDTH-1:0] src_error;
output wire [CHANNEL_WIDTH-1:0] src_channel;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_read;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
input [DATA_WIDTH-1:0] master_readdata;
input master_readdatavalid;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal signals
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire [7:0] descriptor_channel;
wire descriptor_generate_sop;
wire descriptor_generate_eop;
wire [7:0] descriptor_error;
wire [7:0] descriptor_programmable_burst_count;
wire descriptor_early_done_enable;
wire sw_stop_in;
wire sw_reset_in;
reg early_done_enable_d1;
reg [ERROR_WIDTH-1:0] error_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg generate_sop_d1;
reg generate_eop_d1;
reg [ADDRESS_WIDTH-1:0] address_counter;
reg [LENGTH_WIDTH-1:0] length_counter;
reg [CHANNEL_WIDTH-1:0] channel_d1;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignment the master starts
reg first_access; // used to determine if the first read is occuring
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
reg [FIFO_DEPTH_LOG2:0] pending_reads_counter;
reg [FIFO_DEPTH_LOG2:0] pending_reads_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire too_many_pending_reads;
wire read_complete; // handy signal for determining when a read has occured and completed
wire address_increment_enable;
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire go;
wire done; // asserted when last read is issued
reg done_d1;
wire done_strobe;
wire all_reads_returned; // asserted when last read returns
reg all_reads_returned_d1;
wire all_reads_returned_strobe;
reg all_reads_returned_strobe_d1;
reg all_reads_returned_strobe_d2; // used to trigger src_response_ready later than when the last read returns since the MM to ST has two pipeline stages
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout;
wire [DATA_WIDTH-1:0] MM_to_ST_adapter_dataout_rearranged;
wire MM_to_ST_adapter_sop;
wire MM_to_ST_adapter_eop;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] MM_to_ST_adapter_empty;
wire masked_sop;
wire masked_eop;
reg flush;
reg stopped;
wire length_sync_reset;
wire set_src_response_valid;
reg master_read_reg;
/********************************************* REGISTERS **************************************************/
// registering descriptor information
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error_d1 <= 0;
generate_sop_d1 <= 0;
generate_eop_d1 <= 0;
channel_d1 <= 0;
stride_d1 <= 0;
programmable_burst_count_d1 <= 0;
early_done_enable_d1 <= 0;
end
else if (go == 1)
begin
error_d1 <= descriptor_error[ERROR_WIDTH-1:0];
generate_sop_d1 <= descriptor_generate_sop;
generate_eop_d1 <= descriptor_generate_eop;
channel_d1 <= descriptor_channel[CHANNEL_WIDTH-1:0];
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
early_done_enable_d1 <= ((UNALIGNED_ACCESSES_ENABLE == 1) | (PACKET_ENABLE == 1))? 0 : descriptor_early_done_enable; // early done cannot be used when unaligned data or packet support is enabled
end
end
// master word increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first read of a transaction, this will be used to determine what value will be used to increment the counters
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (address_increment_enable == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1)
begin
length_counter <= 0;
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (address_increment_enable == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// the pending reads counter is used to determine how many outstanding reads are posted. This will be used to determine
// if more reads can be posted based on the number of unused words in the FIFO.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
pending_reads_counter <= 0;
end
else
begin
pending_reads_counter <= pending_reads_mux;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // master is done coming out of reset (need this to be set high so that done_strobe doesn't fire)
end
else
begin
done_d1 <= done;
end
end
// this is the 'final done' condition, since reads are pipelined need to make sure they have all returned before the master is really done.
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_d1 <= 1;
end
else
begin
all_reads_returned_d1 <= all_reads_returned;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
flush <= 0;
end
else
begin
if ((pending_reads_counter == 0) & (flush == 1))
begin
flush <= 0;
end
else if ((sw_reset_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
flush <= 1; // will be used to reset the length counter to 0 and flush out pending reads (by letting them return without buffering them)
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (sw_reset_in == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & ((read_complete == 1) | (snk_command_ready == 1) | (master_read_reg == 0)))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if ((src_response_ready == 1) & (src_response_valid == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_reads_returned_strobe_d1 <= 0;
all_reads_returned_strobe_d2 <= 0;
end
else
begin
all_reads_returned_strobe_d1 <= all_reads_returned_strobe;
all_reads_returned_strobe_d2 <= all_reads_returned_strobe_d1;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (flush == 1)
begin
src_response_valid <= 0;
end
else if (set_src_response_valid == 1) // all the reads have returned with MM to ST adapter latency taken into consideration
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
master_read_reg <= 0;
end
else
begin
if ((done == 0) & (too_many_pending_reads == 0) & (sw_stop_in == 0) & (sw_reset_in == 0))
begin
master_read_reg <= 1;
end
else if ((done == 1) | ((read_complete == 1) & ((too_many_pending_reads == 1) | (sw_stop_in == 1))))
begin
master_read_reg <= 0;
end
end
end
/******************************************* END REGISTERS ************************************************/
/************************************** MODULE INSTANTIATIONS *********************************************/
// This block is pipelined and can't throttle the reads
MM_to_ST_Adapter the_MM_to_ST_adapter (
.clk (clk),
.reset (reset),
.length (descriptor_length[LENGTH_WIDTH-1:0]),
.length_counter (length_counter),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.reads_pending (pending_reads_counter),
.start (go),
.readdata (master_readdata),
.readdatavalid (master_readdatavalid),
.fifo_data (MM_to_ST_adapter_dataout),
.fifo_write (fifo_write),
.fifo_empty (MM_to_ST_adapter_empty),
.fifo_sop (MM_to_ST_adapter_sop),
.fifo_eop (MM_to_ST_adapter_eop)
);
defparam the_MM_to_ST_adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_MM_to_ST_adapter.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_MM_to_ST_adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_MM_to_ST_adapter.BYTE_ADDRESS_WIDTH = BYTE_ENABLE_WIDTH_LOG2;
defparam the_MM_to_ST_adapter.READS_PENDING_WIDTH = FIFO_DEPTH_LOG2 + 1;
defparam the_MM_to_ST_adapter.EMPTY_WIDTH = NUMBER_OF_SYMBOLS_LOG2;
defparam the_MM_to_ST_adapter.PACKET_SUPPORT = PACKET_ENABLE;
defparam the_MM_to_ST_adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
defparam the_MM_to_ST_adapter.FULL_WORD_ACCESS_ONLY = ONLY_FULL_ACCESS_ENABLE;
// buffered sop, eop, empty, data (in that order). sop, eop, and empty are only buffered when packet support is enabled
scfifo the_master_to_st_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used),
.q (fifo_read_data),
.rdreq (fifo_read),
.wrreq (fifo_write)
);
defparam the_master_to_st_fifo.lpm_width = FIFO_WIDTH;
defparam the_master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_master_to_st_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_master_to_st_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_master_to_st_fifo.underflow_checking = "OFF";
defparam the_master_to_st_fifo.overflow_checking = "OFF";
// burst block that takes the length and short access enables and forms a burst count based on them. If any of the short access bits are asserted the block will default to a burst count of 1
read_burst_control the_read_burst_control (
.address (master_address),
.length (length_counter),
.maximum_burst_count (maximum_burst_count),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.burst_count (master_burstcount)
);
defparam the_read_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_read_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_read_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_read_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_read_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_read_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/************************************ END MODULE INSTANTIATIONS *******************************************/
/******************************** CONTROL AND COMBINATIONAL SIGNALS ***************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[140:109], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_channel = snk_command_data[71:64];
assign descriptor_generate_sop = snk_command_data[72];
assign descriptor_generate_eop = snk_command_data[73];
assign descriptor_programmable_burst_count = snk_command_data[83:76];
assign descriptor_stride = snk_command_data[99:84];
assign descriptor_error = snk_command_data[107:100];
assign descriptor_early_done_enable = snk_command_data[108];
assign sw_stop_in = snk_command_data[74];
assign sw_reset_in = snk_command_data[75];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
// swap the bytes if big endian is enabled
generate
if (BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign MM_to_ST_adapter_dataout_rearranged[j +8 -1: j] = MM_to_ST_adapter_dataout[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
end
end
else
begin
assign MM_to_ST_adapter_dataout_rearranged = MM_to_ST_adapter_dataout;
end
endgenerate
assign masked_sop = MM_to_ST_adapter_sop & generate_sop_d1;
assign masked_eop = MM_to_ST_adapter_eop & generate_eop_d1;
assign fifo_write_data = {error_d1, channel_d1, masked_sop, masked_eop, ((masked_eop == 1)? MM_to_ST_adapter_empty : {NUMBER_OF_SYMBOLS_LOG2{1'b0}} ), MM_to_ST_adapter_dataout_rearranged};
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before sending them to the data stream
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign src_data[i +SYMBOL_WIDTH -1: i] = fifo_read_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
assign src_empty = (PACKET_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 - 1) : DATA_WIDTH] : 0;
assign src_eop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2] : 0;
assign src_sop = (PACKET_ENABLE == 1)? fifo_read_data[DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 1] : 0;
assign src_channel = (CHANNEL_ENABLE == 1)? fifo_read_data[(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 1): (DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + 2)] : 0;
assign src_error = (ERROR_ENABLE == 1)? fifo_read_data[(FIFO_WIDTH-1):(DATA_WIDTH + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH + 2)] : 0;
assign short_first_access_size = BYTE_ENABLE_WIDTH - (address_counter & LSB_MASK);
assign short_last_access_size = length_counter & LSB_MASK;
assign short_first_and_last_access_size = length_counter & LSB_MASK;
/* special case transfer enables and counter increment values (address and length counter)
short_first_access_enable is for transfers that start unaligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (aligned or unaligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
assign short_first_access_enable = ((address_counter & LSB_MASK) != 0) & (first_access == 1) & (first_word_boundary_not_reached_d1 == 0);
assign short_last_access_enable = (first_access == 0) & (length_counter < BYTE_ENABLE_WIDTH);
assign short_first_and_last_access_enable = (first_access == 1) & (first_word_boundary_not_reached_d1 == 1);
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH * master_burstcount;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = length_counter < BYTE_ENABLE_WIDTH; // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount * master_burstcount; // stride must be a static '1' when bursting is enabled
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH * master_burstcount; // stride must be a static '1' when bursting is enabled
end
end
endgenerate
// the burst count will be 1 for all short accesses
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size or master_burstcount)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size;
3'b010: bytes_to_transfer_mux = short_last_access_size;
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size;
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH * master_burstcount; // this is the only time master_burstcount can be a value other than 1
endcase
end
always @ (master_readdatavalid or read_complete or pending_reads_counter or master_burstcount)
begin
case ({master_readdatavalid, read_complete})
2'b00: pending_reads_mux = pending_reads_counter; // no read posted and no read data returned
2'b01: pending_reads_mux = (pending_reads_counter + master_burstcount); // read posted and no read data returned
2'b10: pending_reads_mux = (pending_reads_counter - 1'b1); // no read posted but read data returned
2'b11: pending_reads_mux = (pending_reads_counter + master_burstcount - 1'b1); // read posted and read data returned
endcase
end
assign src_valid = (fifo_empty == 0);
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign done = (length_counter == 0); // all reads are posted but the master is not done since there could be reads pending
assign done_strobe = (done == 1) & (done_d1 == 0);
assign fifo_read = (src_valid == 1) & (src_ready == 1);
assign length_sync_reset = (flush == 1) & (pending_reads_counter == 0); // resetting the length counter will trigger the done condition
assign too_many_pending_reads = (({fifo_full,fifo_used} + pending_reads_counter) > (FIFO_DEPTH - (maximum_burst_count << 1))); // making sure a full burst can be posted, using 2x maximum_burst_count since the read signal is pipelined and so this signal will be late using maximum_burst_count alone
assign read_complete = (master_read == 1) & (master_waitrequest == 0);
assign address_increment_enable = read_complete;
assign master_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // master always asserts all byte enables and filters the data as it comes in (may lead to destructive reads in some cases)
generate if (DATA_WIDTH > 8)
begin
assign master_address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign master_address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign master_read = master_read_reg & (done == 0); // need to mask the read with done so that it doesn't issue one extra read at the end
assign all_reads_returned = (done == 1) & (pending_reads_counter == 0);
assign all_reads_returned_strobe = (all_reads_returned == 1) & (all_reads_returned_d1 == 0);
// for now the done and early done strobes are the same. Both will be triggered when the last data returns
generate
if (UNALIGNED_ACCESSES_ENABLE == 1) // need to use the delayed strobe since there are two stages of pipelining in the MM to ST adapter
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe_d2, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
else
begin
assign src_response_data = {{252{1'b0}}, all_reads_returned_strobe, done_strobe, stopped, flush}; // 252 zeros: done strobe: early done strobe: stop state: reset delayed
end
endgenerate
assign set_src_response_valid = (UNALIGNED_ACCESSES_ENABLE == 1)? all_reads_returned_strobe_d2 : // all the reads have returned with MM to ST adapter latency taken into consideration
(early_done_enable_d1 == 1)? done_strobe : all_reads_returned_strobe; // when early done is enabled then the done strobe is sufficient to trigger the next command can enter, otherwise need to wait for the pending reads to return
/****************************** END CONTROL AND COMBINATIONAL SIGNALS *************************************/
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:48:39 2016
/////////////////////////////////////////////////////////////
module ACA_II_N16_Q4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60;
OAI211XLTS U42 ( .A0(in2[7]), .A1(in1[7]), .B0(in2[6]), .C0(in1[6]), .Y(n37)
);
OAI211XLTS U43 ( .A0(in2[9]), .A1(in1[9]), .B0(in2[8]), .C0(in1[8]), .Y(n40)
);
OAI211XLTS U44 ( .A0(in2[11]), .A1(in1[11]), .B0(in2[10]), .C0(in1[10]), .Y(
n46) );
CLKAND2X2TS U45 ( .A(in1[0]), .B(in2[0]), .Y(n56) );
XOR2XLTS U46 ( .A(in1[3]), .B(in2[3]), .Y(n49) );
XOR2XLTS U47 ( .A(in1[5]), .B(in2[5]), .Y(n44) );
XOR2XLTS U48 ( .A(in1[7]), .B(in2[7]), .Y(n35) );
XOR2XLTS U49 ( .A(in1[9]), .B(in2[9]), .Y(n38) );
XOR2XLTS U50 ( .A(in1[11]), .B(in2[11]), .Y(n41) );
XOR2XLTS U51 ( .A(in1[13]), .B(in2[13]), .Y(n47) );
OAI211XLTS U52 ( .A0(in2[13]), .A1(in1[13]), .B0(in2[12]), .C0(in1[12]), .Y(
n58) );
OAI211XLTS U53 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .C0(in1[2]), .Y(n43)
);
OAI211XLTS U54 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[4]), .C0(in1[4]), .Y(n34)
);
AOI2BB1XLTS U55 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n56), .Y(res[0]) );
OAI2BB1X1TS U56 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n34), .Y(n54) );
XOR2XLTS U57 ( .A(n36), .B(n35), .Y(res[7]) );
OAI2BB1X1TS U58 ( .A0N(in1[7]), .A1N(in2[7]), .B0(n37), .Y(n53) );
XOR2XLTS U59 ( .A(n39), .B(n38), .Y(res[9]) );
OAI2BB1X1TS U60 ( .A0N(in1[9]), .A1N(in2[9]), .B0(n40), .Y(n52) );
XOR2XLTS U61 ( .A(n42), .B(n41), .Y(res[11]) );
OAI2BB1X1TS U62 ( .A0N(in1[3]), .A1N(in2[3]), .B0(n43), .Y(n55) );
XOR2XLTS U63 ( .A(n45), .B(n44), .Y(res[5]) );
OAI2BB1X1TS U64 ( .A0N(in1[11]), .A1N(in2[11]), .B0(n46), .Y(n51) );
XOR2XLTS U65 ( .A(n48), .B(n47), .Y(res[13]) );
XOR2XLTS U66 ( .A(n50), .B(n49), .Y(res[3]) );
CMPR32X2TS U67 ( .A(in2[12]), .B(in1[12]), .C(n51), .CO(n48), .S(res[12]) );
CMPR32X2TS U68 ( .A(in1[10]), .B(in2[10]), .C(n52), .CO(n42), .S(res[10]) );
CMPR32X2TS U69 ( .A(in1[8]), .B(in2[8]), .C(n53), .CO(n39), .S(res[8]) );
CMPR32X2TS U70 ( .A(in1[6]), .B(in2[6]), .C(n54), .CO(n36), .S(res[6]) );
CMPR32X2TS U71 ( .A(in1[4]), .B(in2[4]), .C(n55), .CO(n45), .S(res[4]) );
CMPR32X2TS U72 ( .A(in1[1]), .B(in2[1]), .C(n56), .CO(n57), .S(res[1]) );
CMPR32X2TS U73 ( .A(in1[2]), .B(in2[2]), .C(n57), .CO(n50), .S(res[2]) );
OAI2BB1X1TS U74 ( .A0N(in1[13]), .A1N(in2[13]), .B0(n58), .Y(n59) );
CMPR32X2TS U75 ( .A(in1[14]), .B(in2[14]), .C(n59), .CO(n60), .S(res[14]) );
CMPR32X2TS U76 ( .A(in1[15]), .B(in2[15]), .C(n60), .CO(res[16]), .S(res[15]) );
initial $sdf_annotate("ACA_II_N16_Q4_syn.sdf");
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : cabac_mn_1p_16x64.v
// Author : guo yong
// Created : 2013-07
// Description : cabac memory for modules
//
//-------------------------------------------------------------------
module cabac_mn_1p_16x64(
//input
clk ,
//output
r_en ,
r_addr ,
r_data
);
parameter ROM_NUM = 'd0;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable
input [5:0] r_addr ; //read address of memory
output [15:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
`ifndef FPGA_MODEL
rom_1p #(.Addr_Width(6), .Word_Width(16))
rom_1p_16x64(
.clk (clk ),
.cen_i (~r_en ),
.oen_i (~r_en ),
.addr_i (r_addr ),
.data_o (r_data )
);
`endif
`ifdef FPGA_MODEL
generate
if(ROM_NUM == 'd0) begin: g_rom0
rom64x16 #(
.INIT_FILE ("rom0.mif" )
)rom_64x16_0(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd1) begin: g_rom1
rom64x16 #(
.INIT_FILE ("rom1.mif" )
)rom_64x16_1(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd2) begin: g_rom2
rom64x16 #(
.INIT_FILE ("rom2.mif" )
)rom_64x16_2(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd3) begin: g_rom3
rom64x16 #(
.INIT_FILE ("rom3.mif" )
)rom_64x16_3(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd4) begin: g_rom4
rom64x16 #(
.INIT_FILE ("rom4.mif" )
)rom_64x16_4(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
endgenerate
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKINV_FUNCTIONAL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_BLACKBOX_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_BLACKBOX_V
|
// --------------------------------------------------------------------
// Copyright (c) 2007 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: I2C_CCD_Config
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny FAN :| 07/07/09 :| Initial Revision
// --------------------------------------------------------------------
module I2C_CCD_Config ( // Host Side
iCLK,
iRST_N,
iUART_CTRL,
iZOOM_MODE_SW,
iEXPOSURE_ADJ,
iEXPOSURE_DEC_p,
// I2C Side
I2C_SCLK,
I2C_SDAT
);
// Host Side
input iCLK;
input iRST_N;
input iUART_CTRL;
input iZOOM_MODE_SW;
// I2C Side
output I2C_SCLK;
inout I2C_SDAT;
// Internal Registers/Wires
reg [15:0] mI2C_CLK_DIV;
reg [31:0] mI2C_DATA;
reg mI2C_CTRL_CLK;
reg mI2C_GO;
wire mI2C_END;
wire mI2C_ACK;
reg [23:0] LUT_DATA;
reg [5:0] LUT_INDEX;
reg [3:0] mSetup_ST;
////////////// CMOS sensor registers setting //////////////////////
input iEXPOSURE_ADJ;
input iEXPOSURE_DEC_p;
parameter default_exposure = 16'h07c0;
parameter exposure_change_value = 16'd200;
reg [24:0] combo_cnt;
wire combo_pulse;
reg [1:0] izoom_mode_sw_delay;
reg [3:0] iexposure_adj_delay;
wire exposure_adj_set;
wire exposure_adj_reset;
reg [15:0] sensor_exposure;
wire [23:0] sensor_start_row;
wire [23:0] sensor_start_column;
wire [23:0] sensor_row_size;
wire [23:0] sensor_column_size;
wire [23:0] sensor_row_mode;
wire [23:0] sensor_column_mode;
assign sensor_start_row = iZOOM_MODE_SW ? 24'h010036 : 24'h010000;
assign sensor_start_column = iZOOM_MODE_SW ? 24'h020010 : 24'h020000;
assign sensor_row_size = iZOOM_MODE_SW ? 24'h0303BF : 24'h03077F;
//assign sensor_row_size = iZOOM_MODE_SW ? 24'h0301E0 : 24'h0301E0;
assign sensor_column_size = iZOOM_MODE_SW ? 24'h0404FF : 24'h0409FF;
//assign sensor_column_size = iZOOM_MODE_SW ? 24'h040280 : 24'h040280;
assign sensor_row_mode = iZOOM_MODE_SW ? 24'h220000 : 24'h220011;
assign sensor_column_mode = iZOOM_MODE_SW ? 24'h230000 : 24'h230011;
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
begin
iexposure_adj_delay <= 0;
end
else
begin
iexposure_adj_delay <= {iexposure_adj_delay[2:0],iEXPOSURE_ADJ};
end
end
assign exposure_adj_set = ({iexposure_adj_delay[0],iEXPOSURE_ADJ}==2'b10) ? 1 : 0 ;
assign exposure_adj_reset = ({iexposure_adj_delay[3:2]}==2'b10) ? 1 : 0 ;
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
sensor_exposure <= default_exposure;
else if (exposure_adj_set|combo_pulse)
begin
if (iEXPOSURE_DEC_p)
begin
if ((sensor_exposure < exposure_change_value)||
(sensor_exposure == 16'h0))
sensor_exposure <= 0;
else
sensor_exposure <= sensor_exposure - exposure_change_value;
end
else
begin
if (((16'hffff -sensor_exposure) <exposure_change_value)||
(sensor_exposure == 16'hffff))
sensor_exposure <= 16'hffff;
else
sensor_exposure <= sensor_exposure + exposure_change_value;
end
end
end
always@(posedge iCLK or negedge iRST_N)
begin
if (!iRST_N)
combo_cnt <= 0;
else if (!iexposure_adj_delay[3])
combo_cnt <= combo_cnt + 1;
else
combo_cnt <= 0;
end
assign combo_pulse = (combo_cnt == 25'h1fffff) ? 1 : 0;
wire i2c_reset;
assign i2c_reset = iRST_N & ~exposure_adj_reset & ~combo_pulse ;
/////////////////////////////////////////////////////////////////////
// Clock Setting
parameter CLK_Freq = 50000000; // 50 MHz
parameter I2C_Freq = 20000; // 20 KHz
// LUT Data Number
parameter LUT_SIZE = 25;
///////////////////// I2C Control Clock ////////////////////////
always@(posedge iCLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
mI2C_CTRL_CLK <= 0;
mI2C_CLK_DIV <= 0;
end
else
begin
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
else
begin
mI2C_CLK_DIV <= 0;
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
end
end
end
////////////////////////////////////////////////////////////////////
I2C_Controller u0 ( .CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
.I2C_SDAT(I2C_SDAT), // I2C DATA
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
.GO(mI2C_GO), // GO transfor
.END(mI2C_END), // END transfor
.ACK(mI2C_ACK), // ACK
.RESET(i2c_reset) // Reset
);
////////////////////////////////////////////////////////////////////
////////////////////// Config Control ////////////////////////////
//always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
always@(posedge mI2C_CTRL_CLK or negedge i2c_reset)
begin
if(!i2c_reset)
begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0;
end
else if(LUT_INDEX<LUT_SIZE)
begin
case(mSetup_ST)
0: begin
mI2C_DATA <= {8'hBA,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
begin
if(!mI2C_ACK)
mSetup_ST <= 2;
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
////////////////////////////////////////////////////////////////////
///////////////////// Config Data LUT //////////////////////////
always
begin
case(LUT_INDEX)
0 : LUT_DATA <= 24'h000000;
1 : LUT_DATA <= 24'h20c000; // Mirror Row and Columns
2 : LUT_DATA <= {8'h09,sensor_exposure};// Exposure
3 : LUT_DATA <= 24'h050000; // H_Blanking
4 : LUT_DATA <= 24'h060019; // V_Blanking
5 : LUT_DATA <= 24'h0A8000; // change latch
6 : LUT_DATA <= 24'h2B000b; // Green 1 Gain
7 : LUT_DATA <= 24'h2C000f; // Blue Gain
8 : LUT_DATA <= 24'h2D000f; // Red Gain
9 : LUT_DATA <= 24'h2E000b; // Green 2 Gain
//10 : LUT_DATA <= 24'h100051; // set up PLL power on
10 : LUT_DATA <= 24'h100000; // set up PLL power on
11 : LUT_DATA <= 24'h111807; // PLL_m_Factor<<8+PLL_n_Divider
12 : LUT_DATA <= 24'h120002; // PLL_p1_Divider
//13 : LUT_DATA <= 24'h100053; // set USE PLL
13 : LUT_DATA <= 24'h100000; // set up PLL power on
14 : LUT_DATA <= 24'h980000; // disble calibration
`ifdef ENABLE_TEST_PATTERN
15 : LUT_DATA <= 24'hA00001; // Test pattern control
16 : LUT_DATA <= 24'hA10123; // Test green pattern value
17 : LUT_DATA <= 24'hA20456; // Test red pattern value
`else
15 : LUT_DATA <= 24'hA00000; // Test pattern control
16 : LUT_DATA <= 24'hA10000; // Test green pattern value
17 : LUT_DATA <= 24'hA20FFF; // Test red pattern value
`endif
18 : LUT_DATA <= sensor_start_row ; // set start row
19 : LUT_DATA <= sensor_start_column ;// set start column
20 : LUT_DATA <= sensor_row_size; // set row size
21 : LUT_DATA <= sensor_column_size; // set column size
22 : LUT_DATA <= sensor_row_mode; // set row mode in bin mode
23 : LUT_DATA <= sensor_column_mode; // set column mode in bin mode
24 : LUT_DATA <= 24'h4901A8; // row black target
default:LUT_DATA <= 24'h000000;
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9250 (
// jesd interface
// rx_clk is (line-rate/40)
rx_clk,
rx_data,
// dma interface
adc_clk,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_dovf,
adc_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awprot,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arprot,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// jesd interface
// rx_clk is (line-rate/40)
input rx_clk;
input [63:0] rx_data;
// dma interface
output adc_clk;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
input adc_dovf;
input adc_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
input [ 2:0] s_axi_awprot;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
input [ 2:0] s_axi_arprot;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
// internal signals
wire [27:0] adc_data_a_s;
wire [27:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_rack_s[0:2];
wire up_wack_s[0:2];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= | up_status_pn_err_s;
up_status_pn_oos <= | up_status_pn_oos_s;
up_status_or <= | up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
end
end
// adc valid
assign adc_valid_a = 1'b1;
assign adc_valid_b = 1'b1;
// main (device interface)
axi_ad9250_if i_if (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s));
// channel
axi_ad9250_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_data_a),
.adc_enable (adc_enable_a),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad9250_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_data_b),
.adc_enable (adc_enable_b),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFINV_FUNCTIONAL_PP_V
|
// file: dacclk_mmcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___128.008______0.000______50.0______116.987_____95.328
// CLK_OUT2___128.008_____90.000______50.0______116.987_____95.328
// CLK_OUT3___128.008____180.000______50.0______116.987_____95.328
// CLK_OUT4___128.008____270.000______50.0______116.987_____95.328
// CLK_OUT5___256.017______0.000______50.0______102.681_____95.328
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________128.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "dacclk_mmcm,clk_wiz_v3_6,{component_name=dacclk_mmcm,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_ONCHIP,primtype_sel=MMCM_ADV,num_out_clk=5,clkin1_period=7.812,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module dacclk_mmcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
output CLK_OUT5,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (90.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (180.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (8),
.CLKOUT3_PHASE (270.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (4),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (7.812),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
// Output buffering
//-----------------------------------
assign CLK_OUT1 = clkout0;
assign CLK_OUT2 = clkout1;
assign CLK_OUT3 = clkout2;
assign CLK_OUT4 = clkout3;
assign CLK_OUT5 = clkout4;
endmodule
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = (DATA_WIDTH / 8)
)(
input clk,
input rst,
//Write Address Channel
input AXIMS_TVALID,
input [ADDR_WIDTH - 1: 0] AXIMS_TDATA,
output AXIMS_TREADY,
input AXIMS_TLAST,
input [STROBE_WIDTH - 1: 0] AXIMS_TKEEP,
input [STROBE_WIDTH - 1: 0] AXIMS_TSTRB,
input [3:0] AXIMS_TID,
input [31:0] AXIMS_TDEST,
input [3:0] AXIMS_TUSER
);
//Parameters
//Registers
reg r_rst;
always @ (*) r_rst = rst;
//submodules
axi_stream_ingress_demo #(
.ADDR_WIDTH (ADDR_WIDTH ),
.DATA_WIDTH (DATA_WIDTH )
) dut (
.clk (clk ),
.rst (r_rst ),
.i_tvalid (AXIMS_TVALID ),
.i_tdata (AXIMS_TDATA ),
.o_tready (AXIMS_TREADY ),
.i_tlast (AXIMS_TLAST ),
.i_tkeep (AXIMS_TKEEP ),
.i_tstrb (AXIMS_TSTRB ),
.i_tid (AXIMS_TID ),
.i_tdest (AXIMS_TDEST ),
.i_tuser (AXIMS_TUSER )
);
//asynchronus logic
//synchronous logic
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:20:35 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n493, n494, n496, n497, n498,
n499, n500, n501, n502, n526, n527, n528, n529, n530, n531, n532,
n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566,
n567, n568, n569, n570, n571, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n798, n799, n805, n812, n815, n824, n826, n827,
n828, n829, n830, n831, n832, n833, n834, n835, n836, n837, n838,
n839, n840, n841, n842, n843, n844, n845, n846, n847, n848, n849,
n850, n851, n852, n853, n854, n855, n856, n857, n858, n859, n860,
n861, n862, n863, n864, n865, n866, n867, n868, n869, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882,
n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893,
n894, n895, n897, n898, n899, n900, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n915, n916, n917, n918, n919, n920,
n921, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1227, n1228, n1229, n1230,
n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240,
n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250,
n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260,
n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270,
n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280,
n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290,
n1291, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2282, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818;
wire [3:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:3] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:1] LZD_output_NRM2_EW;
wire [30:0] DMP_SFG;
wire [24:1] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n900), .CK(clk), .RN(
n1224), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n2414) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n2440), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n2413) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n899), .CK(clk), .RN(
n1206), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n2416) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n898), .CK(clk), .RN(n2439), .Q(
Shift_reg_FLAGS_7_6), .QN(n2411) );
DFFRX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n897), .CK(clk), .RN(n1218), .Q(
Shift_reg_FLAGS_7_5), .QN(n2418) );
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n895), .CK(clk), .RN(n1204), .Q(
Shift_reg_FLAGS_7[3]), .QN(n2356) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n894), .CK(clk), .RN(n1203), .Q(
Shift_reg_FLAGS_7[2]), .QN(n2360) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n891), .CK(clk), .RN(n911), .Q(
intDX_EWSW[0]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n890), .CK(clk), .RN(n2650), .Q(
intDX_EWSW[1]), .QN(n1192) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n887), .CK(clk), .RN(n1206), .Q(
intDX_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n886), .CK(clk), .RN(n2441), .Q(
intDX_EWSW[5]), .QN(n1076) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n882), .CK(clk), .RN(n1224), .Q(
intDX_EWSW[9]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n881), .CK(clk), .RN(n1216),
.Q(intDX_EWSW[10]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n879), .CK(clk), .RN(n1220),
.Q(intDX_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n878), .CK(clk), .RN(n2633),
.Q(intDX_EWSW[13]), .QN(n1179) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n877), .CK(clk), .RN(n1209),
.Q(intDX_EWSW[14]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n875), .CK(clk), .RN(n1207),
.Q(intDX_EWSW[16]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n874), .CK(clk), .RN(n1208),
.Q(intDX_EWSW[17]), .QN(n1015) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n872), .CK(clk), .RN(n911), .Q(
intDX_EWSW[19]), .QN(n1009) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n871), .CK(clk), .RN(n2634),
.Q(intDX_EWSW[20]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n870), .CK(clk), .RN(n2650),
.Q(intDX_EWSW[21]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n869), .CK(clk), .RN(n911), .Q(
intDX_EWSW[22]), .QN(n1017) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n867), .CK(clk), .RN(n2650),
.Q(intDX_EWSW[24]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n866), .CK(clk), .RN(n1219),
.Q(intDX_EWSW[25]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n865), .CK(clk), .RN(n2648),
.Q(intDX_EWSW[26]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n864), .CK(clk), .RN(n1206),
.Q(intDX_EWSW[27]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n863), .CK(clk), .RN(n1221),
.Q(intDX_EWSW[28]), .QN(n996) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n862), .CK(clk), .RN(n2442),
.Q(intDX_EWSW[29]), .QN(n1058) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n861), .CK(clk), .RN(n1211),
.Q(intDX_EWSW[30]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n858), .CK(clk), .RN(n2640), .Q(
left_right_SHT2), .QN(n1230) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n857), .CK(clk), .RN(n2656), .Q(
intDY_EWSW[0]), .QN(n2351) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n855), .CK(clk), .RN(n2657), .Q(
intDY_EWSW[2]), .QN(n2337) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n854), .CK(clk), .RN(n2657), .Q(
intDY_EWSW[3]), .QN(n2343) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n853), .CK(clk), .RN(n2657), .Q(
intDY_EWSW[4]), .QN(n2336) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n852), .CK(clk), .RN(n2657), .Q(
intDY_EWSW[5]), .QN(n2345) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n851), .CK(clk), .RN(n2657), .Q(
intDY_EWSW[6]), .QN(n2338) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n846), .CK(clk), .RN(n2657),
.Q(intDY_EWSW[11]), .QN(n2335) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n844), .CK(clk), .RN(n2064),
.Q(intDY_EWSW[13]), .QN(n2342) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n841), .CK(clk), .RN(n1203),
.Q(intDY_EWSW[16]), .QN(n2349) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n839), .CK(clk), .RN(n1216),
.Q(intDY_EWSW[18]), .QN(n2348) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n838), .CK(clk), .RN(n2633),
.Q(intDY_EWSW[19]), .QN(n2341) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n837), .CK(clk), .RN(n1207),
.Q(intDY_EWSW[20]), .QN(n2347) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n836), .CK(clk), .RN(n1208),
.Q(intDY_EWSW[21]), .QN(n2334) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n835), .CK(clk), .RN(n2633),
.Q(intDY_EWSW[22]), .QN(n2329) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n834), .CK(clk), .RN(n1202),
.Q(intDY_EWSW[23]), .QN(n2333) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n833), .CK(clk), .RN(n1209),
.Q(intDY_EWSW[24]), .QN(n2328) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n832), .CK(clk), .RN(n1205),
.Q(intDY_EWSW[25]), .QN(n2346) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n830), .CK(clk), .RN(n1207),
.Q(intDY_EWSW[27]), .QN(n2332) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n829), .CK(clk), .RN(n1208),
.Q(intDY_EWSW[28]), .QN(n2330) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n827), .CK(clk), .RN(n1216),
.Q(intDY_EWSW[30]), .QN(n2340) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n795), .CK(clk), .RN(n2637),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n2431) );
DFFRX2TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n794), .CK(clk), .RN(n1208),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n2421) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n792), .CK(clk), .RN(n2637),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n791), .CK(clk), .RN(n2636),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n782), .CK(clk), .RN(n2644), .Q(
DMP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n780), .CK(clk), .RN(n2645), .Q(
DMP_EXP_EWSW[2]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n779), .CK(clk), .RN(n1205), .Q(
DMP_EXP_EWSW[3]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n778), .CK(clk), .RN(n2634), .Q(
DMP_EXP_EWSW[4]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n777), .CK(clk), .RN(n2645), .Q(
DMP_EXP_EWSW[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n776), .CK(clk), .RN(n2651), .Q(
DMP_EXP_EWSW[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n775), .CK(clk), .RN(n2646), .Q(
DMP_EXP_EWSW[7]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n774), .CK(clk), .RN(n2649), .Q(
DMP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n773), .CK(clk), .RN(n1207), .Q(
DMP_EXP_EWSW[9]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n770), .CK(clk), .RN(n2649), .Q(
DMP_EXP_EWSW[12]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n769), .CK(clk), .RN(n2637), .Q(
DMP_EXP_EWSW[13]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n768), .CK(clk), .RN(n2653), .Q(
DMP_EXP_EWSW[14]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n766), .CK(clk), .RN(n2639), .Q(
DMP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n765), .CK(clk), .RN(n2650), .Q(
DMP_EXP_EWSW[17]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n764), .CK(clk), .RN(n2635), .Q(
DMP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n763), .CK(clk), .RN(n2635), .Q(
DMP_EXP_EWSW[19]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n762), .CK(clk), .RN(n2635), .Q(
DMP_EXP_EWSW[20]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n761), .CK(clk), .RN(n2639), .Q(
DMP_EXP_EWSW[21]) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n755), .CK(clk), .RN(n2654), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n753), .CK(clk), .RN(n2656), .Q(
DMP_EXP_EWSW[29]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n752), .CK(clk), .RN(n2656), .Q(
DMP_EXP_EWSW[30]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n750), .CK(clk), .RN(n1222), .Q(
ZERO_FLAG_EXP), .QN(n2361) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n749), .CK(clk), .RN(n1202), .Q(
SIGN_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n748), .CK(clk), .RN(n2644), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n747), .CK(clk), .RN(n2644), .Q(
DMP_SHT2_EWSW[0]), .QN(n2320) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n745), .CK(clk), .RN(n2647), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n744), .CK(clk), .RN(n2647), .Q(
DMP_SHT2_EWSW[1]), .QN(n2316) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n743), .CK(clk), .RN(n2647), .Q(
DMP_SFG[1]), .QN(n2404) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n742), .CK(clk), .RN(n2645), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n741), .CK(clk), .RN(n2645), .Q(
DMP_SHT2_EWSW[2]), .QN(n2319) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n740), .CK(clk), .RN(n2645), .Q(
DMP_SFG[2]), .QN(n2406) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n739), .CK(clk), .RN(n1222), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n738), .CK(clk), .RN(n1222), .Q(
DMP_SHT2_EWSW[3]), .QN(n2301) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n736), .CK(clk), .RN(n2637), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n734), .CK(clk), .RN(n2639), .Q(
DMP_SFG[4]), .QN(n2403) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n733), .CK(clk), .RN(n2645), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n732), .CK(clk), .RN(n2645), .Q(
DMP_SHT2_EWSW[5]), .QN(n2318) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n730), .CK(clk), .RN(n2651), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n729), .CK(clk), .RN(n2651), .Q(
DMP_SHT2_EWSW[6]), .QN(n2300) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n728), .CK(clk), .RN(n2651), .Q(
DMP_SFG[6]), .QN(n2388) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n727), .CK(clk), .RN(n2646), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n726), .CK(clk), .RN(n2646), .Q(
DMP_SHT2_EWSW[7]), .QN(n2317) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n725), .CK(clk), .RN(n2646), .Q(
DMP_SFG[7]), .QN(n2405) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n723), .CK(clk), .RN(n2649), .Q(
DMP_SHT2_EWSW[8]), .QN(n2313) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n722), .CK(clk), .RN(n2649), .Q(
DMP_SFG[8]), .QN(n2402) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n721), .CK(clk), .RN(n1223), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n720), .CK(clk), .RN(n1208), .Q(
DMP_SHT2_EWSW[9]), .QN(n2303) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n718), .CK(clk), .RN(n2642), .Q(
DMP_SHT1_EWSW[10]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n715), .CK(clk), .RN(n2643), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n714), .CK(clk), .RN(n1222), .Q(
DMP_SHT2_EWSW[11]), .QN(n2302) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n712), .CK(clk), .RN(n2649), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n711), .CK(clk), .RN(n2649), .Q(
DMP_SHT2_EWSW[12]), .QN(n2401) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n710), .CK(clk), .RN(n2649), .Q(
DMP_SFG[12]), .QN(n2290) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n709), .CK(clk), .RN(n2647), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n708), .CK(clk), .RN(n2647), .Q(
DMP_SHT2_EWSW[13]), .QN(n2315) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n706), .CK(clk), .RN(n2064), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n704), .CK(clk), .RN(n2636), .Q(
DMP_SFG[14]), .QN(n2311) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n703), .CK(clk), .RN(n2064), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n701), .CK(clk), .RN(n2649), .Q(
DMP_SFG[15]), .QN(n2312) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n700), .CK(clk), .RN(n2636), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n698), .CK(clk), .RN(n2651), .Q(
DMP_SFG[16]), .QN(n2310) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n695), .CK(clk), .RN(n2637), .Q(
DMP_SFG[17]), .QN(n2306) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n694), .CK(clk), .RN(n2634), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n692), .CK(clk), .RN(n2639), .Q(
DMP_SFG[18]), .QN(n2307) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n691), .CK(clk), .RN(n2635), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n690), .CK(clk), .RN(n2635), .Q(
DMP_SHT2_EWSW[19]), .QN(n2305) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n689), .CK(clk), .RN(n2635), .Q(
DMP_SFG[19]), .QN(n2399) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n688), .CK(clk), .RN(n2635), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n687), .CK(clk), .RN(n2635), .Q(
DMP_SHT2_EWSW[20]), .QN(n2304) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n685), .CK(clk), .RN(n2639), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n684), .CK(clk), .RN(n2650), .Q(
DMP_SHT2_EWSW[21]), .QN(n2287) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n683), .CK(clk), .RN(n2635), .Q(
DMP_SFG[21]), .QN(n2387) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n682), .CK(clk), .RN(n2636), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n681), .CK(clk), .RN(n2637), .Q(
DMP_SHT2_EWSW[22]), .QN(n2286) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n680), .CK(clk), .RN(n2634), .Q(
DMP_SFG[22]), .QN(n2385) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n679), .CK(clk), .RN(n2652), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n677), .CK(clk), .RN(n2652), .Q(
DMP_SFG[23]), .QN(n2396) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n676), .CK(clk), .RN(n2652), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n675), .CK(clk), .RN(n2652), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n674), .CK(clk), .RN(n2653), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n673), .CK(clk), .RN(n2652), .Q(
DMP_SHT2_EWSW[24]), .QN(n2298) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n672), .CK(clk), .RN(n2652), .Q(
DMP_SFG[24]), .QN(n2395) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n671), .CK(clk), .RN(n2652), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n670), .CK(clk), .RN(n2652), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n667), .CK(clk), .RN(n2653), .Q(
DMP_SFG[25]), .QN(n2394) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n666), .CK(clk), .RN(n2653), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n665), .CK(clk), .RN(n2653), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n664), .CK(clk), .RN(n2654), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n663), .CK(clk), .RN(n2654), .Q(
DMP_SHT2_EWSW[26]), .QN(n2297) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n661), .CK(clk), .RN(n2653), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n660), .CK(clk), .RN(n2653), .Q(
DMP_exp_NRM2_EW[3]), .QN(n2622) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n659), .CK(clk), .RN(n2654), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n658), .CK(clk), .RN(n2654), .Q(
DMP_SHT2_EWSW[27]), .QN(n2296) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n657), .CK(clk), .RN(n2654), .Q(
DMP_SFG[27]), .QN(n2392) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n656), .CK(clk), .RN(n2654), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n655), .CK(clk), .RN(n2654), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n654), .CK(clk), .RN(n2655), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n653), .CK(clk), .RN(n2655), .Q(
DMP_SHT2_EWSW[28]), .QN(n2295) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n652), .CK(clk), .RN(n2655), .Q(
DMP_SFG[28]), .QN(n2391) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n651), .CK(clk), .RN(n2655), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n650), .CK(clk), .RN(n2655), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1175) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n649), .CK(clk), .RN(n2656), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n648), .CK(clk), .RN(n2655), .Q(
DMP_SHT2_EWSW[29]), .QN(n2294) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n646), .CK(clk), .RN(n2655), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n645), .CK(clk), .RN(n2655), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1083) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n644), .CK(clk), .RN(n2656), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n642), .CK(clk), .RN(n2656), .Q(
DMP_SFG[30]), .QN(n2308) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n641), .CK(clk), .RN(n2656), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n639), .CK(clk), .RN(n2445), .Q(
DmP_EXP_EWSW[0]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n638), .CK(clk), .RN(n2639), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n637), .CK(clk), .RN(n2648), .Q(
DmP_EXP_EWSW[1]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n636), .CK(clk), .RN(n2637), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n635), .CK(clk), .RN(n1216), .Q(
DmP_EXP_EWSW[2]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n634), .CK(clk), .RN(n2648), .Q(
DmP_mant_SHT1_SW[2]), .QN(n2428) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n632), .CK(clk), .RN(n2644), .Q(
DmP_mant_SHT1_SW[3]), .QN(n2358) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n631), .CK(clk), .RN(n2645), .Q(
DmP_EXP_EWSW[4]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n629), .CK(clk), .RN(n912), .Q(
DmP_EXP_EWSW[5]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n628), .CK(clk), .RN(n1198), .Q(
DmP_mant_SHT1_SW[5]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n627), .CK(clk), .RN(n2644), .Q(
DmP_EXP_EWSW[6]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n626), .CK(clk), .RN(n2644), .Q(
DmP_mant_SHT1_SW[6]), .QN(n2429) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n625), .CK(clk), .RN(n2644), .Q(
DmP_EXP_EWSW[7]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n624), .CK(clk), .RN(n2644), .Q(
DmP_mant_SHT1_SW[7]), .QN(n2353) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n623), .CK(clk), .RN(n1198), .Q(
DmP_EXP_EWSW[8]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n622), .CK(clk), .RN(n1198), .Q(
DmP_mant_SHT1_SW[8]), .QN(n2382) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n621), .CK(clk), .RN(n911), .Q(
DmP_EXP_EWSW[9]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n620), .CK(clk), .RN(n1198), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n618), .CK(clk), .RN(n2642), .Q(
DmP_mant_SHT1_SW[10]), .QN(n2381) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n617), .CK(clk), .RN(n911), .Q(
DmP_EXP_EWSW[11]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n616), .CK(clk), .RN(n1198), .Q(
DmP_mant_SHT1_SW[11]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n614), .CK(clk), .RN(n2446), .Q(
DmP_mant_SHT1_SW[12]), .QN(n2380) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n613), .CK(clk), .RN(n1204), .Q(
DmP_EXP_EWSW[13]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n612), .CK(clk), .RN(n1202), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n611), .CK(clk), .RN(n2642), .Q(
DmP_EXP_EWSW[14]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n610), .CK(clk), .RN(n2642), .Q(
DmP_mant_SHT1_SW[14]), .QN(n2357) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n609), .CK(clk), .RN(n2642), .Q(
DmP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n607), .CK(clk), .RN(n2648), .Q(
DmP_EXP_EWSW[16]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n606), .CK(clk), .RN(n2639), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n605), .CK(clk), .RN(n2649), .Q(
DmP_EXP_EWSW[17]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n604), .CK(clk), .RN(n2649), .Q(
DmP_mant_SHT1_SW[17]), .QN(n2384) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n603), .CK(clk), .RN(n1223), .Q(
DmP_EXP_EWSW[18]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n602), .CK(clk), .RN(n2633), .Q(
DmP_mant_SHT1_SW[18]), .QN(n2383) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n597), .CK(clk), .RN(n2650), .Q(
DmP_EXP_EWSW[21]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n596), .CK(clk), .RN(n2637), .Q(
DmP_mant_SHT1_SW[21]), .QN(n2362) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n595), .CK(clk), .RN(n1209), .Q(
DmP_EXP_EWSW[22]) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n594), .CK(clk), .RN(n1203), .Q(
DmP_mant_SHT1_SW[22]), .QN(n2354) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n592), .CK(clk), .RN(n2638), .Q(
DmP_EXP_EWSW[24]), .QN(n1453) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n589), .CK(clk), .RN(n2636), .Q(
DmP_EXP_EWSW[27]) );
DFFRX2TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n586), .CK(clk), .RN(n2064), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n584), .CK(clk), .RN(n1206), .Q(
ZERO_FLAG_SFG), .QN(n2309) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n583), .CK(clk), .RN(n1222), .Q(
ZERO_FLAG_NRM) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n580), .CK(clk), .RN(n2651), .Q(
OP_FLAG_SHT1) );
DFFRX4TS R_0 ( .D(n578), .CK(clk), .RN(n2638), .Q(n2350), .QN(n2620) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n1202), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n576), .CK(clk), .RN(n1204), .Q(
SIGN_FLAG_SHT2), .QN(n2288) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n574), .CK(clk), .RN(n1202), .Q(
SIGN_FLAG_NRM) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n570), .CK(clk), .RN(n2647), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1454) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n568), .CK(clk), .RN(n2646), .Q(
Raw_mant_NRM_SWR[18]), .QN(n2627) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n557), .CK(clk), .RN(n2638), .Q(
DmP_mant_SFG_SWR[1]), .QN(n2386) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n556), .CK(clk), .RN(n2638), .Q(
Raw_mant_NRM_SWR[1]), .QN(n2323) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n554), .CK(clk), .RN(n1207), .Q(
DmP_mant_SFG_SWR[8]), .QN(n2376) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n549), .CK(clk), .RN(n2658), .Q(
DmP_mant_SFG_SWR[2]), .QN(n2369) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n548), .CK(clk), .RN(n2445), .Q(
Raw_mant_NRM_SWR[2]), .QN(n2359) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n546), .CK(clk), .RN(n1211), .Q(
DmP_mant_SFG_SWR[3]), .QN(n2373) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n545), .CK(clk), .RN(n2639), .Q(
Raw_mant_NRM_SWR[3]), .QN(n2285) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n541), .CK(clk), .RN(n2640), .Q(
DmP_mant_SFG_SWR[4]), .QN(n2370) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n540), .CK(clk), .RN(n2064), .Q(
Raw_mant_NRM_SWR[4]), .QN(n2331) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n539), .CK(clk), .RN(n1209), .Q(
DmP_mant_SFG_SWR[10]), .QN(n2375) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n537), .CK(clk), .RN(n2446), .Q(
DmP_mant_SFG_SWR[13]), .QN(n2366) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n535), .CK(clk), .RN(n1216), .Q(
DmP_mant_SFG_SWR[5]), .QN(n2367) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n534), .CK(clk), .RN(n1216), .Q(
Raw_mant_NRM_SWR[5]), .QN(n2324) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n533), .CK(clk), .RN(n1211), .Q(
DmP_mant_SFG_SWR[9]), .QN(n2372) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n531), .CK(clk), .RN(n1217), .Q(
DmP_mant_SFG_SWR[12]), .QN(n2368) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n530), .CK(clk), .RN(n1216), .Q(
Raw_mant_NRM_SWR[12]), .QN(n2624) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n529), .CK(clk), .RN(n1211), .Q(
DmP_mant_SFG_SWR[7]), .QN(n2371) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n528), .CK(clk), .RN(n1211), .Q(
Raw_mant_NRM_SWR[7]), .QN(n2326) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n527), .CK(clk), .RN(n2446), .Q(
DmP_mant_SFG_SWR[11]), .QN(n2365) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n526), .CK(clk), .RN(n2446), .Q(
Raw_mant_NRM_SWR[11]), .QN(n2626) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n497), .CK(clk), .RN(n1207), .Q(
DmP_mant_SFG_SWR[20]), .QN(n2420) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n496), .CK(clk), .RN(n2641), .Q(
DmP_mant_SFG_SWR[21]), .QN(n2419) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n493), .CK(clk), .RN(n2632), .Q(
DmP_mant_SFG_SWR[24]), .QN(n2377) );
DFFSX1TS R_3 ( .D(n2770), .CK(clk), .SN(n1208), .Q(n2616) );
DFFRXLTS R_5 ( .D(final_result_ieee[2]), .CK(clk), .RN(n1200), .Q(n2615) );
DFFSX2TS R_8 ( .D(n2742), .CK(clk), .SN(n2638), .Q(n2613) );
DFFSX1TS R_10 ( .D(n2690), .CK(clk), .SN(n1218), .Q(n2612) );
DFFSX1TS R_11 ( .D(n2691), .CK(clk), .SN(n1217), .Q(n2611) );
DFFSX1TS R_12 ( .D(n2692), .CK(clk), .SN(n1218), .Q(n2610) );
DFFSX1TS R_14 ( .D(n2677), .CK(clk), .SN(n2448), .Q(n2608) );
DFFSX1TS R_15 ( .D(n2678), .CK(clk), .SN(n2448), .Q(n2607) );
DFFSX1TS R_16 ( .D(n2679), .CK(clk), .SN(n2447), .Q(n2606) );
DFFSX1TS R_19 ( .D(n2685), .CK(clk), .SN(n2447), .Q(n2604) );
DFFSX1TS R_20 ( .D(n2686), .CK(clk), .SN(n2447), .Q(n2603) );
DFFSX1TS R_22 ( .D(n2704), .CK(clk), .SN(n2636), .Q(n2601) );
DFFSX1TS R_24 ( .D(n2702), .CK(clk), .SN(n2648), .Q(n2599) );
DFFSX1TS R_23 ( .D(n2703), .CK(clk), .SN(n2448), .Q(n2600) );
DFFSX1TS R_26 ( .D(n2772), .CK(clk), .SN(n2633), .Q(n2598) );
DFFSX1TS R_28 ( .D(n2771), .CK(clk), .SN(n1200), .Q(n2597) );
DFFSX1TS R_30 ( .D(n2790), .CK(clk), .SN(n2440), .Q(n2596) );
DFFSX1TS R_32 ( .D(n2789), .CK(clk), .SN(n2440), .Q(n2595) );
DFFSX4TS R_34 ( .D(n2732), .CK(clk), .SN(n1212), .Q(n2593) );
DFFSX1TS R_35 ( .D(n2745), .CK(clk), .SN(n2063), .Q(n2592) );
DFFSX1TS R_36 ( .D(n2744), .CK(clk), .SN(n2063), .Q(n2591) );
DFFSX1TS R_40 ( .D(n2805), .CK(clk), .SN(n1220), .Q(n2590) );
DFFSX1TS R_42 ( .D(n2786), .CK(clk), .SN(n2439), .Q(n2589) );
DFFSX1TS R_44 ( .D(n2785), .CK(clk), .SN(n2439), .Q(n2588) );
DFFSX1TS R_46 ( .D(n2767), .CK(clk), .SN(n2443), .Q(n2587) );
DFFSX1TS R_48 ( .D(n2619), .CK(clk), .SN(n2633), .Q(n2586) );
DFFSX2TS R_50 ( .D(n2700), .CK(clk), .SN(n1218), .Q(n2584) );
DFFSX2TS R_51 ( .D(n2699), .CK(clk), .SN(n1217), .Q(n2583) );
DFFSX2TS R_52 ( .D(n2698), .CK(clk), .SN(n1218), .Q(n2582) );
DFFRX4TS R_61 ( .D(n532), .CK(clk), .RN(n1211), .Q(n2618), .QN(n2291) );
DFFSX4TS R_60 ( .D(n2577), .CK(clk), .SN(n1212), .Q(n2661), .QN(n2400) );
DFFSX1TS R_63 ( .D(n2774), .CK(clk), .SN(n2443), .Q(n2576) );
DFFSX1TS R_65 ( .D(n2773), .CK(clk), .SN(n2443), .Q(n2575) );
DFFSX1TS R_67 ( .D(n2792), .CK(clk), .SN(n2440), .Q(n2574) );
DFFSX1TS R_69 ( .D(n2791), .CK(clk), .SN(n2440), .Q(n2573) );
DFFSX1TS R_71 ( .D(n2782), .CK(clk), .SN(n2440), .Q(n2572) );
DFFSX1TS R_73 ( .D(n2781), .CK(clk), .SN(n2440), .Q(n2571) );
DFFSX4TS R_77 ( .D(n2714), .CK(clk), .SN(n2444), .Q(n2567) );
DFFSX2TS R_80 ( .D(n2707), .CK(clk), .SN(n2448), .Q(n2564) );
DFFSX1TS R_85 ( .D(n2795), .CK(clk), .SN(n2439), .Q(n2562) );
DFFSX1TS R_83 ( .D(n2796), .CK(clk), .SN(n2439), .Q(n2563) );
DFFSX1TS R_87 ( .D(n2778), .CK(clk), .SN(n2443), .Q(n2561) );
DFFSX1TS R_89 ( .D(n2777), .CK(clk), .SN(n2443), .Q(n2560) );
DFFSX2TS R_91 ( .D(n2726), .CK(clk), .SN(n2444), .Q(n2559) );
DFFSX2TS R_92 ( .D(n2725), .CK(clk), .SN(n2444), .Q(n2558) );
DFFSX2TS R_93 ( .D(n2724), .CK(clk), .SN(n2445), .Q(n2557) );
DFFSX1TS R_95 ( .D(n2804), .CK(clk), .SN(n1221), .Q(n2556) );
DFFSX1TS R_97 ( .D(n2803), .CK(clk), .SN(n1221), .Q(n2555) );
DFFSX1TS R_101 ( .D(n2712), .CK(clk), .SN(n2445), .Q(n2552) );
DFFSX1TS R_103 ( .D(n2710), .CK(clk), .SN(n2634), .Q(n2550) );
DFFSX1TS R_100 ( .D(n2713), .CK(clk), .SN(n2445), .Q(n2553) );
DFFSX1TS R_102 ( .D(n2711), .CK(clk), .SN(n2650), .Q(n2551) );
DFFSX1TS R_105 ( .D(n2788), .CK(clk), .SN(n2440), .Q(n2549) );
DFFSX1TS R_107 ( .D(n2787), .CK(clk), .SN(n2440), .Q(n2548) );
DFFSX1TS R_109 ( .D(n2776), .CK(clk), .SN(n2443), .Q(n2547) );
DFFSX1TS R_111 ( .D(n2775), .CK(clk), .SN(n2443), .Q(n2546) );
DFFSX1TS R_113 ( .D(n2769), .CK(clk), .SN(n1220), .Q(n2545) );
DFFSX1TS R_115 ( .D(n2768), .CK(clk), .SN(n2635), .Q(n2544) );
DFFSX4TS R_125 ( .D(n2543), .CK(clk), .SN(n2648), .Q(n2617), .QN(n917) );
DFFSX1TS R_119 ( .D(n2722), .CK(clk), .SN(n2445), .Q(n2542) );
DFFSX1TS R_120 ( .D(n2721), .CK(clk), .SN(n2445), .Q(n2541) );
DFFSX1TS R_122 ( .D(n2802), .CK(clk), .SN(n1220), .Q(n2540) );
DFFSX1TS R_124 ( .D(n2801), .CK(clk), .SN(n1220), .Q(n2539) );
DFFSX2TS R_129 ( .D(n2675), .CK(clk), .SN(n2447), .Q(n2537) );
DFFSX2TS R_130 ( .D(n2674), .CK(clk), .SN(n2448), .Q(n2536) );
DFFSX2TS R_127 ( .D(n2676), .CK(clk), .SN(n2448), .Q(n2538) );
DFFSX1TS R_134 ( .D(n2808), .CK(clk), .SN(n1221), .Q(n2534) );
DFFSX1TS R_136 ( .D(n2807), .CK(clk), .SN(n1221), .Q(n2533) );
DFFSX1TS R_138 ( .D(n2800), .CK(clk), .SN(n2441), .Q(n2532) );
DFFSX1TS R_140 ( .D(n2799), .CK(clk), .SN(n2441), .Q(n2531) );
DFFSX1TS R_142 ( .D(n2810), .CK(clk), .SN(n1221), .Q(n2530) );
DFFSX1TS R_144 ( .D(n2809), .CK(clk), .SN(n1219), .Q(n2529) );
DFFSX1TS R_146 ( .D(n2798), .CK(clk), .SN(n2441), .Q(n2528) );
DFFSX1TS R_148 ( .D(n2797), .CK(clk), .SN(n2441), .Q(n2527) );
DFFSX1TS R_150 ( .D(n2780), .CK(clk), .SN(n1220), .Q(n2526) );
DFFSX1TS R_152 ( .D(n2779), .CK(clk), .SN(n2643), .Q(n2525) );
DFFSX1TS R_154 ( .D(n2784), .CK(clk), .SN(n2441), .Q(n2524) );
DFFSX1TS R_156 ( .D(n2783), .CK(clk), .SN(n2441), .Q(n2523) );
DFFRX4TS R_160 ( .D(n2672), .CK(clk), .RN(n2641), .Q(n2520) );
DFFSX1TS R_166 ( .D(n2729), .CK(clk), .SN(n1212), .Q(n2516) );
DFFSX1TS R_167 ( .D(n2728), .CK(clk), .SN(n1212), .Q(n2515) );
DFFSX1TS R_165 ( .D(n2730), .CK(clk), .SN(n1212), .Q(n2517) );
DFFSX1TS R_170 ( .D(n2663), .CK(clk), .SN(n912), .Q(n2513) );
DFFSX1TS R_171 ( .D(n2662), .CK(clk), .SN(n912), .Q(n2512) );
DFFSX1TS R_173 ( .D(n2736), .CK(clk), .SN(n1212), .Q(n2510) );
DFFSX1TS R_175 ( .D(n2734), .CK(clk), .SN(n1212), .Q(n2508) );
DFFSX1TS R_174 ( .D(n2735), .CK(clk), .SN(n1212), .Q(n2509) );
DFFSX1TS R_177 ( .D(n2794), .CK(clk), .SN(n2442), .Q(n2507) );
DFFSX1TS R_179 ( .D(n2793), .CK(clk), .SN(n2441), .Q(n2506) );
DFFSX2TS R_187 ( .D(n2682), .CK(clk), .SN(n2448), .Q(n2501) );
DFFRX2TS R_185 ( .D(n2683), .CK(clk), .RN(n2446), .Q(n2502) );
DFFSX2TS R_207 ( .D(n2764), .CK(clk), .SN(n1207), .Q(n2489) );
DFFSX4TS R_213 ( .D(n2694), .CK(clk), .SN(n1218), .Q(n2483) );
DFFSX2TS R_215 ( .D(n2719), .CK(clk), .SN(n2444), .Q(n2481) );
DFFSX2TS R_216 ( .D(n2718), .CK(clk), .SN(n2445), .Q(n2480) );
DFFRX4TS R_226 ( .D(n2706), .CK(clk), .RN(n2638), .Q(n2473) );
DFFSX4TS R_242 ( .D(n2739), .CK(clk), .SN(n2638), .Q(n2460) );
DFFSX4TS R_245 ( .D(n2688), .CK(clk), .SN(n1217), .Q(n2457) );
DFFRX4TS R_249 ( .D(n893), .CK(clk), .RN(n1216), .Q(n2629), .QN(n2292) );
DFFSX4TS R_251 ( .D(n2289), .CK(clk), .SN(n2442), .Q(n2659) );
DFFRX1TS R_254 ( .D(n2720), .CK(clk), .RN(n2064), .Q(n2451) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n702), .CK(clk), .RN(n2442), .Q(
DMP_SHT2_EWSW[15]), .QN(n2435) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n699), .CK(clk), .RN(n2639), .Q(
DMP_SHT2_EWSW[16]), .QN(n2434) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n696), .CK(clk), .RN(n2636), .Q(
DMP_SHT2_EWSW[17]), .QN(n2433) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n693), .CK(clk), .RN(n2637), .Q(
DMP_SHT2_EWSW[18]), .QN(n2432) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n716), .CK(clk), .RN(n2642), .Q(
DMP_SFG[10]), .QN(n2410) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n746), .CK(clk), .RN(n2644), .Q(
DMP_SFG[0]), .QN(n2409) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n731), .CK(clk), .RN(n2645), .Q(
DMP_SFG[5]), .QN(n2408) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n719), .CK(clk), .RN(n1225), .Q(
DMP_SFG[9]), .QN(n2398) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n713), .CK(clk), .RN(n2442), .Q(
DMP_SFG[11]), .QN(n2397) );
DFFRXLTS R_56 ( .D(underflow_flag), .CK(clk), .RN(n1203), .Q(n2578) );
DFFRXLTS R_157 ( .D(final_result_ieee[31]), .CK(clk), .RN(n1203), .Q(n2522)
);
DFFRXLTS R_182 ( .D(final_result_ieee[30]), .CK(clk), .RN(n1205), .Q(n2504)
);
DFFSX1TS R_159 ( .D(n2816), .CK(clk), .SN(n1205), .Q(n2521) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n587), .CK(clk), .RN(n2064), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n790), .CK(clk), .RN(n1219), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n789), .CK(clk), .RN(n1219), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n788), .CK(clk), .RN(n1219), .Q(
final_result_ieee[25]) );
DFFSX2TS R_99 ( .D(n2814), .CK(clk), .SN(n1205), .Q(n2554) );
DFFSX2TS R_132 ( .D(n2813), .CK(clk), .SN(n1203), .Q(n2535) );
DFFSX2TS R_181 ( .D(n2812), .CK(clk), .SN(n1220), .Q(n2505) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n581), .CK(clk), .RN(n2643), .Q(
zero_flag) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n668), .CK(clk), .RN(n2653), .QN(
n2322) );
DFFSX2TS R_234 ( .D(n2749), .CK(clk), .SN(n1200), .Q(n2468) );
DFFSX2TS R_237 ( .D(n2746), .CK(clk), .SN(n1203), .Q(n2465) );
DFFSX2TS R_233 ( .D(n2750), .CK(clk), .SN(n1219), .Q(n2469) );
DFFSX2TS R_236 ( .D(n2747), .CK(clk), .SN(n1204), .Q(n2466) );
DFFSX2TS R_247 ( .D(n2727), .CK(clk), .SN(n2444), .Q(n2455) );
DFFSX2TS R_246 ( .D(n1798), .CK(clk), .SN(n2444), .Q(n2456) );
DFFSX2TS R_191 ( .D(n2757), .CK(clk), .SN(n1200), .Q(n2498) );
DFFSX2TS R_192 ( .D(n2756), .CK(clk), .SN(n1209), .Q(n2497) );
DFFSX2TS R_210 ( .D(n2761), .CK(clk), .SN(n1208), .Q(n2486) );
DFFSX2TS R_235 ( .D(n2631), .CK(clk), .SN(n1200), .Q(n2467) );
DFFSX2TS R_238 ( .D(n2276), .CK(clk), .SN(n1200), .Q(n2464) );
DFFSX2TS R_255 ( .D(n2818), .CK(clk), .SN(n2439), .Q(n2450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n826), .CK(clk), .RN(n2651),
.Q(intDY_EWSW[31]) );
DFFSX2TS R_244 ( .D(n2751), .CK(clk), .SN(n1218), .Q(n2458) );
DFFRX2TS R_224 ( .D(n1232), .CK(clk), .RN(n2446), .Q(n2474) );
DFFRX2TS R_218 ( .D(n1214), .CK(clk), .RN(n2446), .Q(n2478) );
DFFSX1TS R_75 ( .D(n2716), .CK(clk), .SN(n2444), .Q(n2569) );
DFFSX2TS R_202 ( .D(n2754), .CK(clk), .SN(n1200), .Q(n2494) );
DFFSX2TS R_203 ( .D(n2753), .CK(clk), .SN(n1198), .Q(n2493) );
DFFSX2TS R_217 ( .D(n2697), .CK(clk), .SN(n2448), .Q(n2479) );
DFFSX1TS R_184 ( .D(n2815), .CK(clk), .SN(n1204), .Q(n2503) );
DFFSX1TS R_53 ( .D(n2668), .CK(clk), .SN(n1225), .Q(n2581) );
DFFSX2TS R_227 ( .D(n805), .CK(clk), .SN(n2634), .Q(n2472) );
DFFSX2TS R_219 ( .D(n812), .CK(clk), .SN(n2448), .Q(n2477) );
DFFSX2TS R_223 ( .D(n815), .CK(clk), .SN(n2447), .Q(n2475) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n550), .CK(clk), .RN(n2643), .Q(
Raw_mant_NRM_SWR[0]), .QN(n2339) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n560), .CK(clk), .RN(n2633), .Q(
DmP_mant_SFG_SWR[14]), .QN(n2422) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n543), .CK(clk), .RN(n1205), .Q(
Raw_mant_NRM_SWR[6]), .QN(n2293) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n499), .CK(clk), .RN(n1202), .Q(
DmP_mant_SFG_SWR[18]), .QN(n2425) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n542), .CK(clk), .RN(n2441), .Q(
n1094), .QN(n2621) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n798), .CK(clk), .RN(n2641), .Q(
shift_value_SHT2_EWR[3]), .QN(n1052) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n552), .CK(clk), .RN(n1205), .Q(
LZD_output_NRM2_EW[1]), .QN(n2623) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n547), .CK(clk), .RN(n1206), .Q(
LZD_output_NRM2_EW[3]), .QN(n2327) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n565), .CK(clk), .RN(n2646), .Q(
Raw_mant_NRM_SWR[21]), .QN(n2625) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n567), .CK(clk), .RN(n2646), .Q(
Raw_mant_NRM_SWR[19]), .QN(n2325) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n494), .CK(clk), .RN(n1206), .Q(
DmP_mant_SFG_SWR[23]), .QN(n2378) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n558), .CK(clk), .RN(n1206), .Q(
LZD_output_NRM2_EW[4]), .QN(n1457) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n563), .CK(clk), .RN(n2646), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1029) );
DFFRX4TS R_189 ( .D(n2759), .CK(clk), .RN(n2064), .Q(n2500) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n562), .CK(clk), .RN(n2646), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1459) );
DFFRX2TS R_74 ( .D(n2717), .CK(clk), .RN(n1204), .Q(n2570) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n561), .CK(clk), .RN(n2647), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1458) );
DFFRX4TS R_201 ( .D(n2755), .CK(clk), .RN(n2641), .Q(n2495) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n502), .CK(clk), .RN(n2648), .Q(
DmP_mant_SFG_SWR[15]), .QN(n2423) );
DFFRX4TS R_59 ( .D(n553), .CK(clk), .RN(n1207), .Q(Raw_mant_NRM_SWR[8]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n501), .CK(clk), .RN(n1200), .Q(
DmP_mant_SFG_SWR[16]), .QN(n2427) );
DFFSX2TS R_33 ( .D(n2733), .CK(clk), .SN(n1212), .Q(n2594) );
DFFSX2TS R_163 ( .D(n2669), .CK(clk), .SN(n1224), .Q(n2519) );
DFFSX2TS R_212 ( .D(n2695), .CK(clk), .SN(n1217), .Q(n2484) );
DFFRX2TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n859), .CK(clk), .RN(n2651), .Q(
intAS) );
DFFSX2TS R_76 ( .D(n2715), .CK(clk), .SN(n2444), .Q(n2568) );
DFFSRHQX4TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n573), .CK(clk), .SN(1'b1),
.RN(n1225), .Q(SIGN_FLAG_SHT1SHT2) );
DFFSRHQX4TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n724), .CK(clk), .SN(1'b1), .RN(
n1223), .Q(DMP_SHT1_EWSW[8]) );
DFFRHQX2TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n669), .CK(clk), .RN(n1224), .Q(
n2282) );
DFFSRHQX8TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n582), .CK(clk), .SN(1'b1),
.RN(n1225), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n575), .CK(clk), .RN(n1224), .Q(
SIGN_FLAG_SFG) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n686), .CK(clk), .RN(n1225), .Q(
DMP_SFG[20]) );
DFFSX4TS R_250 ( .D(n2289), .CK(clk), .SN(n1223), .Q(n2660), .QN(n920) );
DFFSX1TS R_194 ( .D(n2811), .CK(clk), .SN(n1219), .Q(n2496) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n793), .CK(clk), .RN(n1222),
.QN(n2352) );
DFFSHQX4TS R_126_IP ( .D(n2543), .CK(clk), .SN(n1222), .Q(n2278) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n735), .CK(clk), .RN(n2639), .Q(
DMP_SHT2_EWSW[4]), .QN(n2314) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n717), .CK(clk), .RN(n2642), .Q(
DMP_SHT2_EWSW[10]), .QN(n2321) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n697), .CK(clk), .RN(n2634), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n662), .CK(clk), .RN(n2654), .Q(
DMP_SFG[26]), .QN(n2393) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n647), .CK(clk), .RN(n2655), .Q(
DMP_SFG[29]), .QN(n2390) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n630), .CK(clk), .RN(n2645), .Q(
DmP_mant_SHT1_SW[4]), .QN(n2355) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n600), .CK(clk), .RN(n1216), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n579), .CK(clk), .RN(n2651), .Q(
OP_FLAG_SHT2), .QN(n2364) );
DFFSX1TS R_54 ( .D(n2667), .CK(clk), .SN(n1224), .Q(n2580) );
DFFSX2TS R_214 ( .D(n2693), .CK(clk), .SN(n1217), .Q(n2482) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n585), .CK(clk), .RN(n2632), .Q(
ZERO_FLAG_SHT2), .QN(n2437) );
DFFSX4TS R_252 ( .D(n1304), .CK(clk), .SN(n2444), .Q(n2453) );
DFFRX4TS R_222 ( .D(n2673), .CK(clk), .RN(n2446), .Q(n2476) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n500), .CK(clk), .RN(n2641), .Q(
DmP_mant_SFG_SWR[17]), .QN(n2426) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n796), .CK(clk), .RN(n2640), .Q(
shift_value_SHT2_EWR[4]), .QN(n2344) );
DFFSX2TS R_49 ( .D(n2701), .CK(clk), .SN(n1217), .Q(n2585) );
DFFRX4TS R_13 ( .D(n2680), .CK(clk), .RN(n2447), .Q(n2609) );
DFFRX4TS R_21 ( .D(n2705), .CK(clk), .RN(n2658), .Q(n2602) );
DFFRX4TS R_164 ( .D(n2731), .CK(clk), .RN(n1211), .Q(n2518) );
DFFRX4TS R_256 ( .D(n1072), .CK(clk), .RN(n2439), .Q(n2449) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n892), .CK(clk), .RN(n2443), .Q(
Shift_reg_FLAGS_7[0]), .QN(n2438) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n599), .CK(clk), .RN(n2632), .Q(
n1189) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n888), .CK(clk), .RN(n1218),
.Q(n1186) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n889), .CK(clk), .RN(n1217),
.Q(n1185) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n884), .CK(clk), .RN(n1221),
.Q(n1184) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n876), .CK(clk), .RN(n1219),
.Q(n1183) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n868), .CK(clk), .RN(n1217),
.Q(n1182) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n873), .CK(clk), .RN(n2648),
.Q(n1176) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n828), .CK(clk), .RN(n2634),
.Q(n1173) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n848), .CK(clk), .RN(n2657),
.Q(n1170) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n633), .CK(clk), .RN(n2644), .Q(n1169) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n771), .CK(clk), .RN(n2632), .Q(
n1168) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n559), .CK(clk), .RN(n2643),
.Q(n1166) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n849), .CK(clk), .RN(n2657),
.Q(n1164) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n831), .CK(clk), .RN(n1219),
.Q(n1162) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n569), .CK(clk), .RN(n2647),
.Q(n1160) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n885), .CK(clk), .RN(n1198),
.Q(n1158) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n498), .CK(clk), .RN(n2632), .Q(
DmP_mant_SFG_SWR[19]), .QN(n2424) );
DFFSX1TS R_208 ( .D(n2763), .CK(clk), .SN(n1209), .Q(n2488) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n767), .CK(clk), .RN(n2656), .Q(
n1154) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n754), .CK(clk), .RN(n2655), .Q(
n1153) );
DFFSX2TS R_162 ( .D(n2670), .CK(clk), .SN(n1209), .QN(n1065) );
DFFSX1TS R_188 ( .D(n2681), .CK(clk), .SN(n2448), .QN(n1060) );
DFFSX4TS R_18 ( .D(n2684), .CK(clk), .SN(n2447), .Q(n2605) );
DFFSX2TS R_209 ( .D(n2762), .CK(clk), .SN(n1207), .Q(n2487) );
DFFRX4TS R_168 ( .D(n2665), .CK(clk), .RN(n911), .Q(n2514) );
DFFRX1TS R_17 ( .D(n2687), .CK(clk), .RN(n2447), .QN(n1178) );
DFFSX1TS R_7 ( .D(n2743), .CK(clk), .SN(n2640), .Q(n2614) );
DFFSX1TS R_79 ( .D(n2708), .CK(clk), .SN(n2445), .Q(n2565) );
DFFRX4TS R_172 ( .D(n2737), .CK(clk), .RN(n1212), .Q(n2511) );
DFFSX2TS R_55 ( .D(n2666), .CK(clk), .SN(n1225), .Q(n2579) );
DFFSX2TS R_161 ( .D(n2671), .CK(clk), .SN(n1202), .QN(n1031) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n840), .CK(clk), .RN(n1211),
.Q(n1027) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n564), .CK(clk), .RN(n2443),
.Q(n1025) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n619), .CK(clk), .RN(n2642), .Q(
n1024) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n760), .CK(clk), .RN(n2637), .Q(
n1023) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n781), .CK(clk), .RN(n2647), .Q(n1022) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n536), .CK(clk), .RN(n2446),
.Q(n1020) );
DFFRX4TS R_205 ( .D(n2766), .CK(clk), .RN(n1209), .Q(n2491) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n615), .CK(clk), .RN(n2446), .Q(
n1018) );
DFFRHQX8TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n883), .CK(clk), .RN(n2442),
.Q(n1013) );
DFFSX4TS R_78 ( .D(n2709), .CK(clk), .SN(n2648), .Q(n2566) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n538), .CK(clk), .RN(n1208),
.Q(n1010) );
DFFSX2TS R_190 ( .D(n2758), .CK(clk), .SN(n1200), .Q(n2499) );
DFFSX2TS R_240 ( .D(n2741), .CK(clk), .SN(n2638), .Q(n2462) );
DFFSX2TS R_241 ( .D(n2740), .CK(clk), .SN(n2640), .Q(n2461) );
DFFSX2TS R_239 ( .D(n2738), .CK(clk), .SN(n2640), .Q(n2463) );
DFFSRHQX4TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n751), .CK(clk), .SN(1'b1), .RN(
n1222), .Q(OP_FLAG_EXP) );
DFFSX2TS R_204 ( .D(n2752), .CK(clk), .SN(n1205), .Q(n2492) );
DFFRX2TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n591), .CK(clk), .RN(n2640), .Q(
DmP_EXP_EWSW[25]), .QN(n2363) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n590), .CK(clk), .RN(n2640), .Q(
DmP_EXP_EWSW[26]), .QN(n2412) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n847), .CK(clk), .RN(n2657),
.Q(n1005) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n593), .CK(clk), .RN(n2638), .Q(
DmP_EXP_EWSW[23]), .QN(n2415) );
DFFRX2TS R_206 ( .D(n2765), .CK(clk), .RN(n1208), .Q(n2490) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n571), .CK(clk), .RN(n1198),
.Q(n1000) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n601), .CK(clk), .RN(n1216), .Q(
DmP_EXP_EWSW[19]) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n850), .CK(clk), .RN(n2657),
.Q(n997) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n845), .CK(clk), .RN(n2634),
.Q(n991) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n843), .CK(clk), .RN(n1223),
.Q(n989) );
DFFRHQX4TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n772), .CK(clk), .RN(n2642), .Q(n983) );
DFFSX2TS R_263 ( .D(n1142), .CK(clk), .SN(n912), .Q(n980) );
DFFSX2TS R_264 ( .D(n2429), .CK(clk), .SN(n912), .Q(n979) );
DFFSX2TS R_265 ( .D(n1707), .CK(clk), .SN(n912), .Q(n978) );
DFFSX2TS R_266 ( .D(n1903), .CK(clk), .SN(n912), .Q(n977) );
DFFSX2TS R_276 ( .D(n921), .CK(clk), .SN(n2442), .Q(n974) );
DFFSX2TS R_277 ( .D(n2817), .CK(clk), .SN(n2633), .Q(n973) );
DFFSX2TS R_278 ( .D(n921), .CK(clk), .SN(n2445), .Q(n972) );
DFFSX2TS R_279 ( .D(n1851), .CK(clk), .SN(n1203), .Q(n971), .QN(ready) );
DFFRX2TS R_280 ( .D(n1233), .CK(clk), .RN(n2650), .Q(n969) );
DFFSX2TS R_281 ( .D(n2438), .CK(clk), .SN(n1204), .Q(n968) );
DFFSX4TS R_282 ( .D(n1214), .CK(clk), .SN(n2636), .Q(n967) );
DFFSX4TS R_283 ( .D(n2806), .CK(clk), .SN(n1200), .Q(n966) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n759), .CK(clk), .RN(n2652), .Q(
DMP_EXP_EWSW[23]), .QN(n2417) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n758), .CK(clk), .RN(n2653), .Q(n964) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n757), .CK(clk), .RN(n2653), .Q(n962) );
DFFSX4TS R_232 ( .D(n2630), .CK(clk), .SN(n1202), .Q(n2470) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n737), .CK(clk), .RN(n1222), .Q(
DMP_SFG[3]), .QN(n2389) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n678), .CK(clk), .RN(n2652), .Q(
DMP_SHT2_EWSW[23]), .QN(n2299) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n608), .CK(clk), .RN(n2642), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n544), .CK(clk), .RN(n1206), .Q(
DmP_mant_SFG_SWR[6]), .QN(n2374) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n705), .CK(clk), .RN(n2442), .Q(
DMP_SHT2_EWSW[14]), .QN(n2436) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n643), .CK(clk), .RN(n2656), .Q(
DMP_SHT2_EWSW[30]), .QN(n2430) );
DFFSX4TS R_275 ( .D(n921), .CK(clk), .SN(n2439), .Q(n975) );
DFFRHQX8TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n842), .CK(clk), .RN(n2633),
.Q(n908) );
DFFSX4TS R_231 ( .D(n2748), .CK(clk), .SN(n1207), .Q(n2471) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n707), .CK(clk), .RN(n2647), .Q(
DMP_SFG[13]), .QN(n2407) );
DFFRHQX8TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n566), .CK(clk), .RN(n2646),
.Q(n984) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n856), .CK(clk), .RN(n2656),
.Q(n1190) );
DFFRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n880), .CK(clk), .RN(n1220),
.Q(n1181) );
DFFRHQX4TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n555), .CK(clk), .RN(n1206),
.Q(n994) );
DFFRHQX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n799), .CK(clk), .RN(n1211),
.Q(n1193) );
DFFSX2TS R_243 ( .D(n2689), .CK(clk), .SN(n1218), .Q(n2459) );
DFFRX1TS R_253 ( .D(n1619), .CK(clk), .RN(n1209), .Q(n2452) );
DFFSX1TS R_211 ( .D(n2696), .CK(clk), .SN(n1217), .Q(n2485) );
DFFRHQX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n824), .CK(clk), .RN(n1211), .Q(
n1033) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n640), .CK(clk), .RN(n1222),
.Q(DMP_exp_NRM2_EW[7]) );
DFFSX1TS R_248 ( .D(n2723), .CK(clk), .SN(n2444), .Q(n2454) );
DFFRX2TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n756), .CK(clk), .RN(n2654), .Q(
DMP_EXP_EWSW[26]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n860), .CK(clk), .RN(n2651),
.Q(intDX_EWSW[31]), .QN(n2379) );
DFFSRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n598), .CK(clk), .SN(1'b1),
.RN(n1224), .Q(DmP_mant_SHT1_SW[20]) );
MX2X2TS U912 ( .A(Data_Y[7]), .B(n997), .S0(n2247), .Y(n850) );
INVX2TS U913 ( .A(n910), .Y(n912) );
INVX2TS U914 ( .A(n910), .Y(n911) );
OAI22X2TS U915 ( .A0(n1742), .A1(n2097), .B0(Shift_reg_FLAGS_7_6), .B1(n2361), .Y(n750) );
CLKMX2X3TS U916 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n2248), .Y(n867)
);
NAND3X2TS U917 ( .A(n1883), .B(n1882), .C(n1881), .Y(n756) );
MXI2X2TS U918 ( .A(n2315), .B(n2407), .S0(n2277), .Y(n707) );
AND2X6TS U919 ( .A(n1447), .B(intDY_EWSW[16]), .Y(n1157) );
NAND2X1TS U920 ( .A(n2098), .B(DmP_EXP_EWSW[22]), .Y(n1983) );
NAND2X1TS U921 ( .A(n2098), .B(DmP_EXP_EWSW[1]), .Y(n1992) );
INVX8TS U922 ( .A(n1213), .Y(n1405) );
NAND2XLTS U923 ( .A(n2360), .B(n1016), .Y(n1727) );
NAND2XLTS U924 ( .A(n2098), .B(DMP_EXP_EWSW[30]), .Y(n1927) );
NAND2XLTS U925 ( .A(n2098), .B(DMP_EXP_EWSW[21]), .Y(n1977) );
NAND2XLTS U926 ( .A(n2098), .B(n1153), .Y(n1936) );
NAND2XLTS U927 ( .A(n2098), .B(n1023), .Y(n1974) );
NAND2X1TS U928 ( .A(n2142), .B(DmP_mant_SHT1_SW[11]), .Y(n2161) );
NAND2X1TS U929 ( .A(n2142), .B(DmP_mant_SHT1_SW[9]), .Y(n2163) );
NAND2XLTS U930 ( .A(n2219), .B(n1306), .Y(n1816) );
AOI22X2TS U931 ( .A0(n1859), .A1(n1247), .B0(n1858), .B1(n2060), .Y(n2767)
);
NAND2XLTS U932 ( .A(n2630), .B(n1118), .Y(n1117) );
NAND2XLTS U933 ( .A(n1233), .B(n2191), .Y(n1139) );
CLKINVX6TS U934 ( .A(n2751), .Y(n1046) );
NAND2XLTS U935 ( .A(n2036), .B(n983), .Y(n1942) );
NAND2XLTS U936 ( .A(n1233), .B(n2172), .Y(n944) );
NAND2XLTS U937 ( .A(n2034), .B(DMP_EXP_EWSW[6]), .Y(n1944) );
NAND2XLTS U938 ( .A(n2049), .B(DmP_EXP_EWSW[13]), .Y(n2028) );
NAND2XLTS U939 ( .A(n2044), .B(n1022), .Y(n1939) );
NAND2XLTS U940 ( .A(n1232), .B(n2189), .Y(n1138) );
MXI2X1TS U941 ( .A(n2195), .B(final_result_ieee[24]), .S0(n1851), .Y(n2196)
);
NAND2XLTS U942 ( .A(n1232), .B(n2192), .Y(n1140) );
NAND2XLTS U943 ( .A(n1232), .B(n2137), .Y(n1136) );
NAND2X4TS U944 ( .A(n1394), .B(n1393), .Y(n1072) );
NAND2XLTS U945 ( .A(n1233), .B(n2138), .Y(n1141) );
NAND2XLTS U946 ( .A(n2034), .B(DmP_EXP_EWSW[24]), .Y(n1899) );
NAND2X2TS U947 ( .A(n1379), .B(n1170), .Y(n1967) );
NAND2XLTS U948 ( .A(n2049), .B(DMP_EXP_EWSW[0]), .Y(n1930) );
NAND2XLTS U949 ( .A(n2049), .B(DmP_EXP_EWSW[4]), .Y(n2011) );
NAND2XLTS U950 ( .A(n2049), .B(DMP_EXP_EWSW[5]), .Y(n1947) );
NAND2XLTS U951 ( .A(n2044), .B(DmP_EXP_EWSW[17]), .Y(n2040) );
NAND2XLTS U952 ( .A(n2044), .B(DmP_EXP_EWSW[16]), .Y(n2020) );
NAND2XLTS U953 ( .A(n2044), .B(DmP_EXP_EWSW[21]), .Y(n2045) );
NAND2XLTS U954 ( .A(n2036), .B(DMP_EXP_EWSW[3]), .Y(n1968) );
NAND2XLTS U955 ( .A(n2036), .B(DmP_EXP_EWSW[11]), .Y(n2031) );
NAND2XLTS U956 ( .A(n2036), .B(DmP_EXP_EWSW[15]), .Y(n2037) );
NAND2XLTS U957 ( .A(n2036), .B(n1024), .Y(n1995) );
NAND2XLTS U958 ( .A(n2036), .B(n1168), .Y(n1959) );
NAND2XLTS U959 ( .A(n2049), .B(n1169), .Y(n1998) );
INVX8TS U960 ( .A(n1309), .Y(n1008) );
CLKAND2X2TS U961 ( .A(n2142), .B(DmP_mant_SHT1_SW[2]), .Y(n1087) );
OAI22X2TS U962 ( .A0(n1316), .A1(n1458), .B0(n1510), .B1(n2130), .Y(n2131)
);
OR2X1TS U963 ( .A(n1461), .B(n2223), .Y(n1719) );
NAND2X2TS U964 ( .A(n1447), .B(n1190), .Y(n1941) );
NOR2X2TS U965 ( .A(n1316), .B(n1454), .Y(n2147) );
NAND2XLTS U966 ( .A(n2034), .B(DmP_EXP_EWSW[26]), .Y(n1896) );
NAND2XLTS U967 ( .A(n2139), .B(n1233), .Y(n1137) );
CLKAND2X2TS U968 ( .A(n1233), .B(n2118), .Y(n1084) );
NOR2X2TS U969 ( .A(n1316), .B(n1167), .Y(n2155) );
NAND2X2TS U970 ( .A(n1379), .B(intDX_EWSW[12]), .Y(n1991) );
NAND2X2TS U971 ( .A(n1379), .B(intDY_EWSW[5]), .Y(n1949) );
NAND2X2TS U972 ( .A(n1187), .B(intDY_EWSW[28]), .Y(n1938) );
BUFX8TS U973 ( .A(n2148), .Y(n1672) );
NAND2X4TS U974 ( .A(n1043), .B(n1042), .Y(n1843) );
CLKAND2X2TS U975 ( .A(n2188), .B(n1232), .Y(n1441) );
NOR2X4TS U976 ( .A(n1316), .B(n2331), .Y(n1620) );
CLKAND2X2TS U977 ( .A(n2152), .B(DmP_mant_SHT1_SW[7]), .Y(n1089) );
CLKAND2X2TS U978 ( .A(n2152), .B(DmP_mant_SHT1_SW[8]), .Y(n1090) );
NAND2X2TS U979 ( .A(n1037), .B(n1092), .Y(n1787) );
AOI22X1TS U980 ( .A0(n2126), .A1(n1439), .B0(n1232), .B1(n1228), .Y(n2127)
);
INVX2TS U981 ( .A(n1199), .Y(n910) );
AOI22X1TS U982 ( .A0(n2185), .A1(n1835), .B0(n2178), .B1(n812), .Y(n1526) );
BUFX6TS U983 ( .A(n2023), .Y(n2036) );
BUFX6TS U984 ( .A(n2023), .Y(n2044) );
INVX1TS U985 ( .A(n1020), .Y(n1021) );
OR2X6TS U986 ( .A(n2153), .B(n903), .Y(n1043) );
NAND2X1TS U987 ( .A(n2151), .B(DmP_mant_SHT1_SW[19]), .Y(n1825) );
NAND2X6TS U988 ( .A(n1305), .B(n1016), .Y(n1496) );
NOR2X1TS U989 ( .A(n1233), .B(n2078), .Y(n1872) );
NAND2X1TS U990 ( .A(n2180), .B(n2179), .Y(n2181) );
AOI22X1TS U991 ( .A0(n2185), .A1(n2192), .B0(n2060), .B1(n2059), .Y(n2061)
);
AOI22X1TS U992 ( .A0(n2178), .A1(n2137), .B0(n2053), .B1(n1845), .Y(n1846)
);
CLKAND2X2TS U993 ( .A(n1811), .B(n1809), .Y(n1381) );
INVX2TS U994 ( .A(n1197), .Y(n1199) );
CLKAND2X2TS U995 ( .A(n2049), .B(DmP_EXP_EWSW[6]), .Y(n1079) );
CLKBUFX2TS U996 ( .A(intDX_EWSW[5]), .Y(n1238) );
NAND2BX2TS U997 ( .AN(n2170), .B(n1228), .Y(n2177) );
NAND2X4TS U998 ( .A(n1345), .B(Raw_mant_NRM_SWR[2]), .Y(n1344) );
AOI22X1TS U999 ( .A0(n1210), .A1(DmP_mant_SHT1_SW[2]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1566) );
AOI22X1TS U1000 ( .A0(n1210), .A1(DmP_mant_SHT1_SW[17]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1840) );
INVX4TS U1001 ( .A(n1851), .Y(n921) );
BUFX20TS U1002 ( .A(n1324), .Y(n1316) );
INVX6TS U1003 ( .A(n2080), .Y(n2213) );
INVX2TS U1004 ( .A(n1743), .Y(n1793) );
BUFX6TS U1005 ( .A(n2023), .Y(n2049) );
NAND2X1TS U1006 ( .A(n2174), .B(n1122), .Y(n1112) );
INVX2TS U1007 ( .A(n2140), .Y(n1707) );
INVX12TS U1008 ( .A(n1794), .Y(n2185) );
CLKINVX6TS U1009 ( .A(n2186), .Y(n923) );
NAND2X2TS U1010 ( .A(n1830), .B(n1228), .Y(n1831) );
NOR2X6TS U1011 ( .A(n1670), .B(n1669), .Y(n2170) );
BUFX4TS U1012 ( .A(n2023), .Y(n2034) );
NAND2XLTS U1013 ( .A(n1210), .B(DmP_mant_SHT1_SW[15]), .Y(n1440) );
NOR2BX1TS U1014 ( .AN(DmP_mant_SHT1_SW[11]), .B(n1240), .Y(n1377) );
NAND2X4TS U1015 ( .A(n1334), .B(n953), .Y(n952) );
AND2X2TS U1016 ( .A(n1808), .B(n1811), .Y(n1456) );
NAND2X2TS U1017 ( .A(n1837), .B(n2172), .Y(n1515) );
NOR2X2TS U1018 ( .A(n1552), .B(n1709), .Y(n1558) );
AOI22X1TS U1019 ( .A0(n2176), .A1(n2139), .B0(n1837), .B1(n2137), .Y(n1833)
);
INVX6TS U1020 ( .A(n2153), .Y(n1345) );
AOI22X1TS U1021 ( .A0(n1210), .A1(DmP_mant_SHT1_SW[1]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1495) );
AOI22X1TS U1022 ( .A0(n2152), .A1(DmP_mant_SHT1_SW[16]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1520) );
INVX2TS U1023 ( .A(n1683), .Y(n1685) );
INVX4TS U1024 ( .A(n2156), .Y(n2152) );
NAND2X1TS U1025 ( .A(n1657), .B(n2184), .Y(n1662) );
NOR2X1TS U1026 ( .A(n1455), .B(n2760), .Y(n2136) );
NOR2X6TS U1027 ( .A(n1228), .B(left_right_SHT2), .Y(n2053) );
INVX4TS U1028 ( .A(left_right_SHT2), .Y(n1247) );
NAND2X2TS U1029 ( .A(n2173), .B(n815), .Y(n1542) );
NAND2X2TS U1030 ( .A(n1122), .B(n2140), .Y(n1133) );
NAND2X2TS U1031 ( .A(n1837), .B(n2118), .Y(n1607) );
NAND2X2TS U1032 ( .A(n2176), .B(n2138), .Y(n1130) );
CLKINVX6TS U1033 ( .A(n1510), .Y(n1232) );
XNOR2X2TS U1034 ( .A(n989), .B(n907), .Y(n1640) );
NAND2X1TS U1035 ( .A(n1261), .B(n1260), .Y(n1259) );
NOR2X2TS U1036 ( .A(n963), .B(DmP_EXP_EWSW[25]), .Y(n946) );
BUFX8TS U1037 ( .A(n1527), .Y(n2060) );
NOR2X4TS U1038 ( .A(n1688), .B(n2624), .Y(n1868) );
INVX16TS U1039 ( .A(n1318), .Y(n2153) );
INVX2TS U1040 ( .A(n1010), .Y(n1011) );
INVX2TS U1041 ( .A(n2350), .Y(n2096) );
NAND3X1TS U1042 ( .A(n2559), .B(n2558), .C(n2557), .Y(n1113) );
NAND2X2TS U1043 ( .A(n1664), .B(n1658), .Y(n1499) );
INVX12TS U1044 ( .A(n1523), .Y(n1837) );
INVX12TS U1045 ( .A(n1518), .Y(n2176) );
NAND2X6TS U1046 ( .A(n1716), .B(DMP_SFG[20]), .Y(n2179) );
INVX4TS U1047 ( .A(n2184), .Y(n1606) );
AND2X2TS U1048 ( .A(n1645), .B(n1652), .Y(n1261) );
NAND2X2TS U1049 ( .A(n1453), .B(n964), .Y(n2067) );
CLKXOR2X4TS U1050 ( .A(n1757), .B(n1756), .Y(n2197) );
NAND2X2TS U1051 ( .A(n1717), .B(DMP_SFG[21]), .Y(n1723) );
NAND2X2TS U1052 ( .A(n1559), .B(DMP_SFG[19]), .Y(n1711) );
NAND4X2TS U1053 ( .A(n2553), .B(n2552), .C(n2551), .D(n2550), .Y(n2188) );
BUFX6TS U1054 ( .A(n1674), .Y(n1301) );
INVX12TS U1055 ( .A(n1614), .Y(n1677) );
NOR2X2TS U1056 ( .A(n1779), .B(DMP_exp_NRM2_EW[5]), .Y(n1780) );
NOR2X6TS U1057 ( .A(n1709), .B(n1713), .Y(n1714) );
AOI21X1TS U1058 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2331), .B0(n1675), .Y(n1615) );
NAND2X2TS U1059 ( .A(n1665), .B(n2184), .Y(n1528) );
NAND2X4TS U1060 ( .A(n2594), .B(n2593), .Y(n2168) );
NAND2X6TS U1061 ( .A(n1614), .B(n1481), .Y(n1482) );
NOR2X6TS U1062 ( .A(n1559), .B(DMP_SFG[19]), .Y(n1713) );
OR2X4TS U1063 ( .A(n2490), .B(n2491), .Y(n2184) );
BUFX6TS U1064 ( .A(n1532), .Y(n1664) );
NAND2X2TS U1065 ( .A(n1156), .B(DMP_SFG[17]), .Y(n2109) );
NAND2X4TS U1066 ( .A(n1553), .B(DMP_SFG[16]), .Y(n2105) );
AND2X4TS U1067 ( .A(n1637), .B(n1625), .Y(n1266) );
AND2X2TS U1068 ( .A(n1648), .B(n1649), .Y(n1257) );
NOR2X2TS U1069 ( .A(n1057), .B(n1108), .Y(n1107) );
XNOR2X2TS U1070 ( .A(n1170), .B(n1288), .Y(n1635) );
XNOR2X2TS U1071 ( .A(intDY_EWSW[6]), .B(n1158), .Y(n1650) );
NOR2X4TS U1072 ( .A(n1415), .B(n1414), .Y(n1413) );
XNOR2X1TS U1073 ( .A(n1164), .B(n1013), .Y(n1651) );
XNOR2X1TS U1074 ( .A(n997), .B(n1184), .Y(n1078) );
NAND2X2TS U1075 ( .A(n1771), .B(n1778), .Y(n1852) );
INVX6TS U1076 ( .A(n1242), .Y(n1241) );
OA21X2TS U1077 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[3]), .B0(
n1478), .Y(n1481) );
NOR2X6TS U1078 ( .A(n2268), .B(n2265), .Y(n1415) );
NAND2X6TS U1079 ( .A(n1597), .B(n1596), .Y(n1111) );
NOR2X4TS U1080 ( .A(n1457), .B(DMP_exp_NRM2_EW[4]), .Y(n1781) );
NAND2X1TS U1081 ( .A(n1764), .B(n1387), .Y(n1386) );
NOR2X4TS U1082 ( .A(n1057), .B(n1599), .Y(n1110) );
INVX2TS U1083 ( .A(n1762), .Y(n1750) );
NOR2X4TS U1084 ( .A(n1690), .B(n1693), .Y(n1866) );
INVX3TS U1085 ( .A(n1595), .Y(n1596) );
NOR2X4TS U1086 ( .A(n1580), .B(n1575), .Y(n1280) );
OR3X2TS U1087 ( .A(n2626), .B(n2292), .C(n1062), .Y(n1044) );
NAND2X4TS U1088 ( .A(n1549), .B(DMP_SFG[14]), .Y(n2265) );
NOR2X2TS U1089 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM2_EW[5]), .Y(n1771)
);
NAND2X4TS U1090 ( .A(n995), .B(DMP_exp_NRM2_EW[2]), .Y(n1765) );
OR2X2TS U1091 ( .A(n2349), .B(intDX_EWSW[16]), .Y(n1063) );
AND3X2TS U1092 ( .A(n2661), .B(n1489), .C(n1479), .Y(n1480) );
NAND2X6TS U1093 ( .A(n1578), .B(n1573), .Y(n1580) );
OR2X4TS U1094 ( .A(n2622), .B(LZD_output_NRM2_EW[3]), .Y(n1764) );
NAND2X2TS U1095 ( .A(n1313), .B(n1487), .Y(n1372) );
NOR2X6TS U1096 ( .A(n1296), .B(n1295), .Y(n1294) );
NAND2X4TS U1097 ( .A(n1749), .B(DMP_exp_NRM2_EW[1]), .Y(n1760) );
NOR2X6TS U1098 ( .A(Raw_mant_NRM_SWR[7]), .B(Raw_mant_NRM_SWR[6]), .Y(n1489)
);
INVX2TS U1099 ( .A(n1485), .Y(n1487) );
CLKINVX2TS U1100 ( .A(DMP_SFG[13]), .Y(n1335) );
INVX4TS U1101 ( .A(n1166), .Y(n1167) );
BUFX3TS U1102 ( .A(n1582), .Y(n1287) );
NAND2BX2TS U1103 ( .AN(n1010), .B(n2661), .Y(n958) );
NAND2X6TS U1104 ( .A(n2330), .B(intDX_EWSW[28]), .Y(n1351) );
INVX2TS U1105 ( .A(n1598), .Y(n1419) );
NAND2X2TS U1106 ( .A(n1471), .B(n1863), .Y(n1472) );
NOR2X6TS U1107 ( .A(n1585), .B(n1424), .Y(n1423) );
NOR2X4TS U1108 ( .A(n1330), .B(n1329), .Y(n1578) );
NAND2X1TS U1109 ( .A(n998), .B(n1184), .Y(n1569) );
INVX2TS U1110 ( .A(n1076), .Y(n993) );
NOR2X6TS U1111 ( .A(n909), .B(n1183), .Y(n1330) );
NOR2X2TS U1112 ( .A(n1160), .B(n1000), .Y(n1863) );
AND2X4TS U1113 ( .A(n1017), .B(intDY_EWSW[22]), .Y(n1237) );
NAND2X4TS U1114 ( .A(n1006), .B(intDX_EWSW[10]), .Y(n1147) );
CLKINVX6TS U1115 ( .A(LZD_output_NRM2_EW[1]), .Y(n1749) );
NAND2X2TS U1116 ( .A(n1013), .B(n1165), .Y(n1367) );
NOR2X2TS U1117 ( .A(n1165), .B(n1013), .Y(n1364) );
CLKINVX6TS U1118 ( .A(n1164), .Y(n1165) );
INVX4TS U1119 ( .A(n2278), .Y(n1551) );
AND2X6TS U1120 ( .A(n2337), .B(n1185), .Y(n1357) );
CLKINVX2TS U1121 ( .A(n1173), .Y(n1174) );
CLKINVX2TS U1122 ( .A(n1162), .Y(n1163) );
INVX2TS U1123 ( .A(n1170), .Y(n1171) );
INVX2TS U1124 ( .A(n1028), .Y(n1014) );
INVX2TS U1125 ( .A(n989), .Y(n990) );
INVX2TS U1126 ( .A(n1005), .Y(n1006) );
CLKINVX2TS U1127 ( .A(n991), .Y(n992) );
INVX2TS U1128 ( .A(n908), .Y(n909) );
INVX4TS U1129 ( .A(n1027), .Y(n1028) );
NOR2X2TS U1130 ( .A(n1166), .B(n1160), .Y(n1143) );
INVX4TS U1131 ( .A(n984), .Y(n985) );
NOR2X4TS U1132 ( .A(n998), .B(n1184), .Y(n1570) );
MXI2X2TS U1133 ( .A(n2122), .B(n2386), .S0(n2241), .Y(n557) );
CLKINVX6TS U1134 ( .A(n934), .Y(n933) );
NAND3X6TS U1135 ( .A(n1945), .B(n1946), .C(n1944), .Y(n776) );
NAND2X4TS U1136 ( .A(n2048), .B(n1158), .Y(n1945) );
INVX8TS U1137 ( .A(n1691), .Y(n1692) );
MXI2X4TS U1138 ( .A(n2117), .B(n2116), .S0(n1247), .Y(n2120) );
INVX12TS U1139 ( .A(n1177), .Y(n1835) );
NAND2X6TS U1140 ( .A(n1703), .B(n2225), .Y(n1829) );
NAND4X6TS U1141 ( .A(n1702), .B(n1701), .C(n1700), .D(n1699), .Y(n1703) );
AND2X8TS U1142 ( .A(n1538), .B(n1537), .Y(n2796) );
AOI22X2TS U1143 ( .A0(n2185), .A1(n812), .B0(n2060), .B1(n1835), .Y(n1682)
);
OR2X8TS U1144 ( .A(n1688), .B(n1687), .Y(n1869) );
NAND3X6TS U1145 ( .A(n1734), .B(n1733), .C(n1732), .Y(n2057) );
NAND2X6TS U1146 ( .A(n2519), .B(n1126), .Y(n1125) );
NOR2X6TS U1147 ( .A(n1065), .B(n2520), .Y(n1126) );
AOI22X2TS U1148 ( .A0(n2187), .A1(n923), .B0(n2184), .B1(n2185), .Y(n2747)
);
NAND2X8TS U1149 ( .A(n2177), .B(n1086), .Y(n2187) );
AND4X6TS U1150 ( .A(n1178), .B(n2605), .C(n2604), .D(n2603), .Y(n1177) );
AOI22X2TS U1151 ( .A0(n2187), .A1(n1230), .B0(n2184), .B1(n2178), .Y(n2750)
);
AOI22X2TS U1152 ( .A0(n2121), .A1(n1230), .B0(n1033), .B1(n2178), .Y(n2122)
);
AOI2BB2X4TS U1153 ( .B0(n2178), .B1(n1836), .A0N(n2170), .A1N(n1788), .Y(
n1791) );
INVX8TS U1154 ( .A(shift_value_SHT2_EWR[3]), .Y(n1874) );
INVX16TS U1155 ( .A(n1523), .Y(n1122) );
AND2X6TS U1156 ( .A(n2120), .B(n2119), .Y(n2782) );
NAND2X4TS U1157 ( .A(n2052), .B(n1228), .Y(n1505) );
NAND2X2TS U1158 ( .A(n2052), .B(n2053), .Y(n1120) );
NAND2X8TS U1159 ( .A(n1529), .B(n1528), .Y(n1531) );
NAND4X4TS U1160 ( .A(n1607), .B(n1609), .C(n1608), .D(n1610), .Y(n1706) );
AOI21X2TS U1161 ( .A0(n1230), .A1(n1844), .B0(n1548), .Y(n2776) );
NAND2BX4TS U1162 ( .AN(n1038), .B(n2150), .Y(n2696) );
AND2X4TS U1163 ( .A(n1792), .B(n1247), .Y(n1797) );
OAI2BB1X4TS U1164 ( .A0N(n1865), .A1N(n1866), .B0(n1864), .Y(n1867) );
NAND2X4TS U1165 ( .A(n1310), .B(n1089), .Y(n2718) );
NAND2X4TS U1166 ( .A(n1310), .B(n1091), .Y(n2740) );
NAND2X4TS U1167 ( .A(n1311), .B(n1310), .Y(n2675) );
NAND2X4TS U1168 ( .A(n1310), .B(n1090), .Y(n2688) );
NAND2X4TS U1169 ( .A(n1310), .B(n1087), .Y(n2723) );
MXI2X4TS U1170 ( .A(n2792), .B(n2423), .S0(n2244), .Y(n502) );
AND2X8TS U1171 ( .A(n1824), .B(n1823), .Y(n2792) );
AND2X8TS U1172 ( .A(n2062), .B(n2061), .Y(n2790) );
NAND2X4TS U1173 ( .A(n930), .B(Raw_mant_NRM_SWR[6]), .Y(n934) );
NOR2X8TS U1174 ( .A(n1316), .B(n904), .Y(n1442) );
AOI22X4TS U1175 ( .A0(n2176), .A1(n2188), .B0(n1837), .B1(n805), .Y(n1838)
);
CLKINVX6TS U1176 ( .A(n936), .Y(n935) );
NAND3X6TS U1177 ( .A(n1822), .B(n1821), .C(n1820), .Y(n2116) );
NOR2X4TS U1178 ( .A(n2158), .B(n1312), .Y(n2753) );
NOR2X4TS U1179 ( .A(n1041), .B(n1684), .Y(n1338) );
NAND4X4TS U1180 ( .A(n2463), .B(n2462), .C(n2461), .D(n2460), .Y(n976) );
NAND2X2TS U1181 ( .A(n2178), .B(n805), .Y(n1507) );
OAI21X2TS U1182 ( .A0(n1794), .A1(n1746), .B0(n1745), .Y(n1747) );
NAND2X4TS U1183 ( .A(n1008), .B(n1016), .Y(n2712) );
NAND2X8TS U1184 ( .A(n1032), .B(n1480), .Y(n1049) );
OAI2BB1X4TS U1185 ( .A0N(n1094), .A1N(n1439), .B0(n1036), .Y(n542) );
AOI22X2TS U1186 ( .A0(n2628), .A1(Raw_mant_NRM_SWR[11]), .B0(n1037), .B1(
n1055), .Y(n2684) );
NAND2X8TS U1187 ( .A(n1545), .B(n1135), .Y(n1845) );
INVX12TS U1188 ( .A(n1363), .Y(n1036) );
NAND3X6TS U1189 ( .A(n2015), .B(n2016), .C(n2014), .Y(n621) );
INVX12TS U1190 ( .A(n1395), .Y(n1394) );
NAND2X8TS U1191 ( .A(n1759), .B(n1758), .Y(n1774) );
OAI2BB1X2TS U1192 ( .A0N(n1827), .A1N(n2141), .B0(n1826), .Y(n2717) );
OAI21X2TS U1193 ( .A0(n1510), .A1(n1874), .B0(n1873), .Y(n798) );
NAND3X6TS U1194 ( .A(n1889), .B(n1888), .C(n1887), .Y(n759) );
NAND2X2TS U1195 ( .A(n2128), .B(n2127), .Y(n796) );
NAND4BX4TS U1196 ( .AN(n2609), .B(n2608), .C(n2607), .D(n2606), .Y(n2059) );
AOI2BB2X4TS U1197 ( .B0(n2060), .B1(n2172), .A0N(n1834), .A1N(n1788), .Y(
n1538) );
NOR2X2TS U1198 ( .A(n1333), .B(n1084), .Y(n2701) );
NAND3X6TS U1199 ( .A(n1952), .B(n1951), .C(n1950), .Y(n778) );
NAND2X4TS U1200 ( .A(n2817), .B(n2196), .Y(n789) );
NAND2X4TS U1201 ( .A(n2817), .B(n2198), .Y(n788) );
NAND2X4TS U1202 ( .A(n2817), .B(n2194), .Y(n790) );
AOI22X4TS U1203 ( .A0(n2479), .A1(n2478), .B0(n2477), .B1(n969), .Y(n1512)
);
CLKMX2X4TS U1204 ( .A(n2113), .B(Raw_mant_NRM_SWR[19]), .S0(n2360), .Y(n567)
);
BUFX16TS U1205 ( .A(n1770), .Y(n1782) );
NAND3X4TS U1206 ( .A(n1955), .B(n1954), .C(n1953), .Y(n774) );
BUFX20TS U1207 ( .A(n2134), .Y(n930) );
NAND3X4TS U1208 ( .A(n1964), .B(n1963), .C(n1962), .Y(n775) );
AND4X8TS U1209 ( .A(n1398), .B(n1399), .C(n1482), .D(n1798), .Y(n1059) );
NAND3X4TS U1210 ( .A(n1941), .B(n1940), .C(n1939), .Y(n781) );
NAND4X8TS U1211 ( .A(n2566), .B(n2565), .C(n2564), .D(n1498), .Y(n805) );
NAND2X4TS U1212 ( .A(n1837), .B(n815), .Y(n1733) );
NAND2X4TS U1213 ( .A(n1379), .B(intDY_EWSW[4]), .Y(n1952) );
NAND2X4TS U1214 ( .A(n1379), .B(intDY_EWSW[6]), .Y(n1946) );
AOI22X2TS U1215 ( .A0(n1876), .A1(n1405), .B0(n1232), .B1(n1875), .Y(n2758)
);
NOR2X6TS U1216 ( .A(n1403), .B(n1404), .Y(n2123) );
NAND3X4TS U1217 ( .A(n1920), .B(n1919), .C(n1918), .Y(n765) );
XNOR2X2TS U1218 ( .A(intDY_EWSW[21]), .B(n1293), .Y(n1632) );
NAND3X4TS U1219 ( .A(n1604), .B(n1603), .C(n1602), .Y(n755) );
NAND2X6TS U1220 ( .A(n1359), .B(n907), .Y(n2010) );
BUFX20TS U1221 ( .A(n1421), .Y(n1391) );
NAND3X6TS U1222 ( .A(n2026), .B(n2025), .C(n2024), .Y(n601) );
NAND2X4TS U1223 ( .A(n1841), .B(n947), .Y(n2708) );
NAND3X2TS U1224 ( .A(n1948), .B(n1949), .C(n1947), .Y(n777) );
NAND3X2TS U1225 ( .A(n2012), .B(n2013), .C(n2011), .Y(n631) );
NAND2X8TS U1226 ( .A(n1069), .B(n1050), .Y(n2182) );
NAND2X6TS U1227 ( .A(n1305), .B(n1025), .Y(n1565) );
NAND2X8TS U1228 ( .A(n2325), .B(n1485), .Y(n1693) );
INVX12TS U1229 ( .A(n1378), .Y(n1446) );
NAND2X4TS U1230 ( .A(n2048), .B(n1170), .Y(n2015) );
INVX16TS U1231 ( .A(n1007), .Y(n1142) );
NAND3X4TS U1232 ( .A(n2029), .B(n2030), .C(n2028), .Y(n613) );
NAND3X2TS U1233 ( .A(n2038), .B(n2039), .C(n2037), .Y(n609) );
NAND3X2TS U1234 ( .A(n2021), .B(n2022), .C(n2020), .Y(n607) );
NAND3X2TS U1235 ( .A(n1978), .B(n1979), .C(n1977), .Y(n761) );
CLKBUFX2TS U1236 ( .A(n2627), .Y(n903) );
CLKBUFX2TS U1237 ( .A(n1459), .Y(n904) );
NOR2X4TS U1238 ( .A(n1003), .B(Raw_mant_NRM_SWR[24]), .Y(n1470) );
OAI21X4TS U1239 ( .A0(n2179), .A1(n1722), .B0(n1723), .Y(n1812) );
OR2X8TS U1240 ( .A(n2330), .B(intDX_EWSW[28]), .Y(n1066) );
OR2X8TS U1241 ( .A(n1324), .B(n2323), .Y(n1325) );
CLKINVX12TS U1242 ( .A(n1864), .Y(n1322) );
NAND2X4TS U1243 ( .A(n1903), .B(n1384), .Y(n905) );
CLKINVX12TS U1244 ( .A(intDX_EWSW[14]), .Y(n906) );
INVX16TS U1245 ( .A(n906), .Y(n907) );
MX2X2TS U1246 ( .A(Data_X[14]), .B(n907), .S0(n2253), .Y(n877) );
NAND2X2TS U1247 ( .A(n2050), .B(n1283), .Y(n625) );
NAND2X2TS U1248 ( .A(n1958), .B(n1286), .Y(n780) );
NAND3X2TS U1249 ( .A(n1894), .B(n1895), .C(n1893), .Y(n591) );
NAND3X2TS U1250 ( .A(n1928), .B(n1929), .C(n1927), .Y(n752) );
NAND3X2TS U1251 ( .A(n1922), .B(n1923), .C(n1921), .Y(n763) );
NAND2X4TS U1252 ( .A(n2027), .B(intDX_EWSW[26]), .Y(n1882) );
NAND2X2TS U1253 ( .A(n2048), .B(intDX_EWSW[24]), .Y(n1879) );
NAND2X6TS U1254 ( .A(intDY_EWSW[24]), .B(n2043), .Y(n1900) );
NAND3X4TS U1255 ( .A(n1901), .B(n1900), .C(n1899), .Y(n592) );
NAND2X8TS U1256 ( .A(n1096), .B(n1601), .Y(n1449) );
OAI2BB2X4TS U1257 ( .B0(n1061), .B1(n1332), .A0N(n2342), .A1N(intDX_EWSW[13]), .Y(n1331) );
NAND2X2TS U1258 ( .A(n1422), .B(intDX_EWSW[25]), .Y(n1895) );
OAI22X4TS U1259 ( .A0(n2205), .A1(n2596), .B0(n975), .B1(n2595), .Y(
final_result_ieee[12]) );
OAI22X4TS U1260 ( .A0(n1235), .A1(n2524), .B0(n975), .B1(n2523), .Y(
final_result_ieee[9]) );
OAI22X4TS U1261 ( .A0(n1234), .A1(n2526), .B0(n975), .B1(n2525), .Y(
final_result_ieee[7]) );
OAI22X4TS U1262 ( .A0(n2205), .A1(n2547), .B0(n975), .B1(n2546), .Y(
final_result_ieee[5]) );
OAI22X4TS U1263 ( .A0(n1235), .A1(n2549), .B0(n975), .B1(n2548), .Y(
final_result_ieee[11]) );
NAND2X4TS U1264 ( .A(n1192), .B(n1190), .Y(n1146) );
NAND2X2TS U1265 ( .A(intDX_EWSW[1]), .B(n1191), .Y(n1144) );
CLKBUFX2TS U1266 ( .A(n1183), .Y(n1327) );
NAND2X4TS U1267 ( .A(n2347), .B(intDX_EWSW[20]), .Y(n1584) );
NOR2X2TS U1268 ( .A(n1000), .B(n1020), .Y(n1468) );
AND2X2TS U1269 ( .A(n2326), .B(n2661), .Y(n1430) );
XNOR2X2TS U1270 ( .A(intDY_EWSW[19]), .B(n1303), .Y(n1634) );
INVX2TS U1271 ( .A(n994), .Y(n995) );
NAND2X2TS U1272 ( .A(n1861), .B(n1698), .Y(n1699) );
INVX2TS U1273 ( .A(n1785), .Y(n1404) );
AND2X2TS U1274 ( .A(n1210), .B(DmP_mant_SHT1_SW[18]), .Y(n1091) );
CLKINVX3TS U1275 ( .A(n1374), .Y(n947) );
NAND2X1TS U1276 ( .A(n2036), .B(n1189), .Y(n2017) );
AND2X2TS U1277 ( .A(n1210), .B(DmP_mant_SHT1_SW[0]), .Y(n1088) );
AND2X8TS U1278 ( .A(n1363), .B(Raw_mant_NRM_SWR[0]), .Y(n915) );
AND2X8TS U1279 ( .A(n952), .B(n1440), .Y(n916) );
INVX2TS U1280 ( .A(left_right_SHT2), .Y(n2186) );
AND2X4TS U1281 ( .A(n1706), .B(n1247), .Y(n918) );
AND2X4TS U1282 ( .A(n930), .B(Raw_mant_NRM_SWR[5]), .Y(n919) );
CLKMX2X3TS U1283 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n2248), .Y(n869)
);
CLKMX2X3TS U1284 ( .A(Data_X[27]), .B(intDX_EWSW[27]), .S0(n2248), .Y(n864)
);
CLKMX2X3TS U1285 ( .A(Data_X[19]), .B(n1303), .S0(n2253), .Y(n872) );
CLKMX2X3TS U1286 ( .A(Data_X[1]), .B(intDX_EWSW[1]), .S0(n2251), .Y(n890) );
CLKMX2X3TS U1287 ( .A(Data_X[9]), .B(n1288), .S0(n2252), .Y(n882) );
MXI2X2TS U1288 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[8]), .Y(n2083)
);
CLKMX2X3TS U1289 ( .A(Data_Y[15]), .B(n908), .S0(n2249), .Y(n842) );
CLKMX2X3TS U1290 ( .A(Data_Y[18]), .B(intDY_EWSW[18]), .S0(n2249), .Y(n839)
);
CLKMX2X3TS U1291 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n2249), .Y(n838)
);
CLKMX2X3TS U1292 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n2253), .Y(n878)
);
CLKMX2X3TS U1293 ( .A(Data_Y[22]), .B(n926), .S0(n2251), .Y(n835) );
CLKMX2X3TS U1294 ( .A(Data_X[5]), .B(n1238), .S0(n2252), .Y(n886) );
NAND2X8TS U1295 ( .A(n2176), .B(n1230), .Y(n1794) );
INVX8TS U1296 ( .A(n2156), .Y(n1210) );
BUFX6TS U1297 ( .A(n2250), .Y(n2246) );
NOR2X6TS U1298 ( .A(n1518), .B(n1230), .Y(n1527) );
NOR2X2TS U1299 ( .A(n1739), .B(n2098), .Y(n1740) );
CLKMX2X4TS U1300 ( .A(n2418), .B(n2659), .S0(n2235), .Y(n2289) );
NAND2X1TS U1301 ( .A(n2023), .B(DmP_EXP_EWSW[18]), .Y(n1986) );
NAND2X1TS U1302 ( .A(n2023), .B(DmP_EXP_EWSW[2]), .Y(n1980) );
INVX2TS U1303 ( .A(n938), .Y(n2076) );
OAI22X2TS U1304 ( .A0(n1234), .A1(n2576), .B0(n972), .B1(n2575), .Y(
final_result_ieee[4]) );
OAI22X2TS U1305 ( .A0(n2205), .A1(n2598), .B0(n972), .B1(n2597), .Y(
final_result_ieee[3]) );
OAI22X2TS U1306 ( .A0(n1235), .A1(n2545), .B0(n972), .B1(n2544), .Y(
final_result_ieee[1]) );
OAI22X2TS U1307 ( .A0(n1235), .A1(n2587), .B0(n972), .B1(n2586), .Y(
final_result_ieee[0]) );
INVX2TS U1308 ( .A(n1190), .Y(n1191) );
NAND4X4TS U1309 ( .A(n2485), .B(n2484), .C(n2483), .D(n2482), .Y(n2191) );
INVX2TS U1310 ( .A(n1033), .Y(n1034) );
INVX8TS U1311 ( .A(n2418), .Y(n2230) );
INVX6TS U1312 ( .A(n2145), .Y(n1308) );
INVX8TS U1313 ( .A(n950), .Y(n2145) );
AND2X8TS U1314 ( .A(n930), .B(n1160), .Y(n931) );
INVX2TS U1315 ( .A(n1053), .Y(n2099) );
NAND2X4TS U1316 ( .A(n1524), .B(n1123), .Y(n1679) );
BUFX12TS U1317 ( .A(n1798), .Y(n1903) );
OAI2BB1X2TS U1318 ( .A0N(n2053), .A1N(n1744), .B0(n1507), .Y(n1508) );
NAND2X2TS U1319 ( .A(n1121), .B(n1120), .Y(n1119) );
NAND2X2TS U1320 ( .A(n1744), .B(n1743), .Y(n1745) );
AO22X2TS U1321 ( .A0(n2152), .A1(DmP_mant_SHT1_SW[5]), .B0(n2142), .B1(
DmP_mant_SHT1_SW[4]), .Y(n1477) );
CLKMX2X2TS U1322 ( .A(Data_Y[17]), .B(n1027), .S0(n2249), .Y(n840) );
CLKMX2X2TS U1323 ( .A(Data_X[6]), .B(n1158), .S0(n2252), .Y(n885) );
CLKMX2X2TS U1324 ( .A(Data_X[7]), .B(n1184), .S0(n2252), .Y(n884) );
CLKMX2X2TS U1325 ( .A(Data_X[8]), .B(n1013), .S0(n2252), .Y(n883) );
NAND3X4TS U1326 ( .A(n1634), .B(n1266), .C(n1265), .Y(n1264) );
NAND2X4TS U1327 ( .A(n1448), .B(n1109), .Y(n1108) );
XOR2X2TS U1328 ( .A(n2077), .B(n937), .Y(n2079) );
BUFX12TS U1329 ( .A(n2250), .Y(n2251) );
INVX8TS U1330 ( .A(n1510), .Y(n1233) );
BUFX12TS U1331 ( .A(n2250), .Y(n2248) );
BUFX12TS U1332 ( .A(n2250), .Y(n2252) );
BUFX8TS U1333 ( .A(n1527), .Y(n2178) );
NAND2X6TS U1334 ( .A(n1336), .B(n1335), .Y(n2255) );
NAND2X2TS U1335 ( .A(n2142), .B(DmP_mant_SHT1_SW[21]), .Y(n2162) );
BUFX12TS U1336 ( .A(n2276), .Y(n2630) );
BUFX12TS U1337 ( .A(n2276), .Y(n2237) );
INVX12TS U1338 ( .A(n2273), .Y(n2229) );
INVX6TS U1339 ( .A(n2098), .Y(n1448) );
INVX4TS U1340 ( .A(n1570), .Y(n942) );
AND2X4TS U1341 ( .A(n2075), .B(n938), .Y(n937) );
INVX8TS U1342 ( .A(n1455), .Y(n2151) );
NAND2X4TS U1343 ( .A(n1132), .B(n1131), .Y(n2138) );
INVX12TS U1344 ( .A(n2221), .Y(n2239) );
OAI2BB2X2TS U1345 ( .B0(n1234), .B1(n2616), .A0N(n971), .A1N(n2615), .Y(
final_result_ieee[2]) );
NOR2X4TS U1346 ( .A(n1300), .B(n1299), .Y(n1298) );
NOR2X4TS U1347 ( .A(n958), .B(n1489), .Y(n957) );
INVX12TS U1348 ( .A(n2221), .Y(n2222) );
INVX2TS U1349 ( .A(n2137), .Y(n1547) );
INVX12TS U1350 ( .A(n2221), .Y(n2228) );
AND2X4TS U1351 ( .A(n2599), .B(n2601), .Y(n1132) );
INVX16TS U1352 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1851) );
INVX2TS U1353 ( .A(n1181), .Y(n1159) );
INVX6TS U1354 ( .A(n997), .Y(n998) );
INVX6TS U1355 ( .A(n2659), .Y(n2238) );
INVX2TS U1356 ( .A(n962), .Y(n963) );
OR2X4TS U1357 ( .A(n2412), .B(DMP_EXP_EWSW[26]), .Y(n938) );
INVX2TS U1358 ( .A(n2291), .Y(n953) );
INVX2TS U1359 ( .A(DMP_EXP_EWSW[26]), .Y(n939) );
BUFX8TS U1360 ( .A(intDY_EWSW[13]), .Y(n999) );
INVX2TS U1361 ( .A(n1025), .Y(n1026) );
NOR2X2TS U1362 ( .A(n2292), .B(Raw_mant_NRM_SWR[4]), .Y(n1478) );
INVX2TS U1363 ( .A(n1193), .Y(n1194) );
NAND2X2TS U1364 ( .A(n1829), .B(n1705), .Y(n799) );
NAND2X4TS U1365 ( .A(n1214), .B(n933), .Y(n2739) );
NAND2X6TS U1366 ( .A(n916), .B(n1509), .Y(n1877) );
NAND2X4TS U1367 ( .A(n1310), .B(n935), .Y(n2762) );
NAND2X4TS U1368 ( .A(n1310), .B(n919), .Y(n2694) );
AND2X6TS U1369 ( .A(n930), .B(n1000), .Y(n932) );
INVX4TS U1370 ( .A(n1482), .Y(n1437) );
INVX8TS U1371 ( .A(n1754), .Y(n1759) );
MX2X2TS U1372 ( .A(n2262), .B(n1304), .S0(n2273), .Y(n570) );
NAND2X6TS U1373 ( .A(n2259), .B(n1418), .Y(n1416) );
NAND2X4TS U1374 ( .A(n1679), .B(n1247), .Y(n1246) );
AND4X6TS U1375 ( .A(n1854), .B(n2197), .C(n1853), .D(n2263), .Y(n1855) );
INVX4TS U1376 ( .A(n2197), .Y(n1758) );
NAND2X1TS U1377 ( .A(n2074), .B(n2073), .Y(n538) );
NAND2X1TS U1378 ( .A(n2090), .B(n2089), .Y(n548) );
NAND2X1TS U1379 ( .A(n2092), .B(n2091), .Y(n530) );
NAND2X1TS U1380 ( .A(n2212), .B(n2211), .Y(n536) );
NAND2X6TS U1381 ( .A(n1370), .B(n1372), .Y(n1616) );
NAND2X1TS U1382 ( .A(n2216), .B(n2215), .Y(n526) );
NAND2X4TS U1383 ( .A(n1525), .B(n1124), .Y(n1680) );
NAND2X1TS U1384 ( .A(n2210), .B(n2209), .Y(n534) );
CLKMX2X2TS U1385 ( .A(Data_Y[14]), .B(n989), .S0(n2249), .Y(n843) );
CLKMX2X2TS U1386 ( .A(Data_Y[10]), .B(n1005), .S0(n2247), .Y(n847) );
CLKMX2X2TS U1387 ( .A(Data_Y[12]), .B(n991), .S0(n2249), .Y(n845) );
CLKMX2X2TS U1388 ( .A(Data_Y[9]), .B(n1170), .S0(n2247), .Y(n848) );
CLKMX2X2TS U1389 ( .A(Data_Y[8]), .B(n1164), .S0(n2247), .Y(n849) );
INVX8TS U1390 ( .A(n941), .Y(n1276) );
CLKMX2X2TS U1391 ( .A(Data_Y[21]), .B(intDY_EWSW[21]), .S0(n2249), .Y(n836)
);
CLKMX2X2TS U1392 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n2249), .Y(n837)
);
CLKMX2X2TS U1393 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n2249), .Y(n841)
);
CLKMX2X2TS U1394 ( .A(Data_Y[13]), .B(n999), .S0(n2249), .Y(n844) );
CLKMX2X2TS U1395 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n2247), .Y(n846)
);
CLKMX2X2TS U1396 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n2247), .Y(n851) );
CLKMX2X2TS U1397 ( .A(Data_Y[5]), .B(intDY_EWSW[5]), .S0(n2247), .Y(n852) );
CLKMX2X2TS U1398 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n2247), .Y(n853) );
CLKMX2X2TS U1399 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n2247), .Y(n855) );
CLKMX2X2TS U1400 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n2246), .Y(n857) );
INVX2TS U1401 ( .A(n2160), .Y(n2673) );
CLKMX2X2TS U1402 ( .A(Data_X[25]), .B(intDX_EWSW[25]), .S0(n2248), .Y(n866)
);
MX2X2TS U1403 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n2253), .Y(n875) );
NAND2X6TS U1404 ( .A(n1294), .B(n1297), .Y(n1597) );
NAND2X6TS U1405 ( .A(n2256), .B(n2255), .Y(n1411) );
INVX4TS U1406 ( .A(n2080), .Y(n2207) );
INVX8TS U1407 ( .A(n1510), .Y(n2760) );
INVX12TS U1408 ( .A(n1030), .Y(n2189) );
BUFX12TS U1409 ( .A(n2276), .Y(n2277) );
AND2X2TS U1410 ( .A(n1724), .B(n1723), .Y(n1725) );
NAND2X1TS U1411 ( .A(n2142), .B(DmP_mant_SHT1_SW[7]), .Y(n2689) );
NAND2X6TS U1412 ( .A(n1593), .B(n1420), .Y(n1095) );
NOR2X1TS U1413 ( .A(n2156), .B(n2357), .Y(n2146) );
BUFX12TS U1414 ( .A(n2250), .Y(n2253) );
NAND2X6TS U1415 ( .A(n1145), .B(n1144), .Y(n1278) );
NAND2X1TS U1416 ( .A(n2224), .B(n2203), .Y(n900) );
INVX4TS U1417 ( .A(n1051), .Y(n2208) );
INVX2TS U1418 ( .A(n1835), .Y(n1040) );
INVX12TS U1419 ( .A(n1500), .Y(n1201) );
CLKMX2X3TS U1420 ( .A(DMP_SHT1_EWSW[15]), .B(n1154), .S0(n2239), .Y(n703) );
NAND2X4TS U1421 ( .A(n1544), .B(n2168), .Y(n1135) );
NAND2X2TS U1422 ( .A(n1778), .B(n1775), .Y(n1776) );
INVX12TS U1423 ( .A(n1455), .Y(n2142) );
CLKMX2X2TS U1424 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2222),
.Y(n724) );
INVX6TS U1425 ( .A(n1412), .Y(n1336) );
INVX8TS U1426 ( .A(n1500), .Y(n2171) );
NOR2X6TS U1427 ( .A(n2233), .B(n2232), .Y(n2235) );
INVX12TS U1428 ( .A(n2219), .Y(n2223) );
NAND2X6TS U1429 ( .A(n1467), .B(n1468), .Y(n987) );
NAND2X6TS U1430 ( .A(n2344), .B(n1532), .Y(n1518) );
CLKMX2X3TS U1431 ( .A(DmP_mant_SHT1_SW[10]), .B(n1024), .S0(n2231), .Y(n618)
);
INVX16TS U1432 ( .A(n2225), .Y(n1439) );
INVX2TS U1433 ( .A(n1011), .Y(n949) );
OR2X6TS U1434 ( .A(n2096), .B(n2360), .Y(n1051) );
BUFX12TS U1435 ( .A(n2219), .Y(n2273) );
CLKMX2X3TS U1436 ( .A(DmP_mant_SHT1_SW[3]), .B(n1169), .S0(n2227), .Y(n632)
);
NAND2BX2TS U1437 ( .AN(n939), .B(n2412), .Y(n2075) );
NAND2X6TS U1438 ( .A(n1512), .B(n1115), .Y(n812) );
CLKMX2X2TS U1439 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(busy),
.Y(n723) );
INVX2TS U1440 ( .A(n2201), .Y(n2749) );
XNOR2X2TS U1441 ( .A(n999), .B(intDX_EWSW[13]), .Y(n1639) );
CLKMX2X3TS U1442 ( .A(DmP_mant_SHT1_SW[20]), .B(n1189), .S0(n2231), .Y(n598)
);
INVX2TS U1443 ( .A(n2282), .Y(n2240) );
OR2X4TS U1444 ( .A(n2327), .B(DMP_exp_NRM2_EW[3]), .Y(n1387) );
AND2X4TS U1445 ( .A(n2340), .B(intDX_EWSW[30]), .Y(n1599) );
INVX2TS U1446 ( .A(DmP_mant_SHT1_SW[20]), .Y(n2190) );
NOR2X4TS U1447 ( .A(DMP_EXP_EWSW[23]), .B(n2415), .Y(n2166) );
INVX12TS U1448 ( .A(Shift_reg_FLAGS_7_5), .Y(n2221) );
MXI2X2TS U1449 ( .A(n2414), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2233) );
INVX12TS U1450 ( .A(Shift_reg_FLAGS_7[2]), .Y(n2219) );
NOR2X2TS U1451 ( .A(n2413), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2232) );
INVX2TS U1452 ( .A(n2625), .Y(n951) );
OAI2BB1X2TS U1453 ( .A0N(n2504), .A1N(n968), .B0(n2503), .Y(
final_result_ieee[30]) );
NAND2X2TS U1454 ( .A(n2411), .B(DMP_EXP_EWSW[19]), .Y(n1921) );
NAND3X4TS U1455 ( .A(n2291), .B(n2626), .C(Raw_mant_NRM_SWR[8]), .Y(n1431)
);
OAI2BB1X2TS U1456 ( .A0N(n2522), .A1N(n968), .B0(n2521), .Y(
final_result_ieee[31]) );
INVX2TS U1457 ( .A(n1020), .Y(n959) );
INVX2TS U1458 ( .A(n1000), .Y(n1001) );
OAI2BB1X2TS U1459 ( .A0N(n2578), .A1N(n971), .B0(n973), .Y(underflow_flag)
);
NOR2X2TS U1460 ( .A(n2285), .B(Raw_mant_NRM_SWR[4]), .Y(n1675) );
INVX8TS U1461 ( .A(n2660), .Y(busy) );
NOR2X6TS U1462 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2416), .Y(n2234) );
NAND3X6TS U1463 ( .A(n1417), .B(n1714), .C(n1710), .Y(n1410) );
NOR2X4TS U1464 ( .A(n2260), .B(n2268), .Y(n1418) );
NAND2X2TS U1465 ( .A(n2034), .B(DMP_EXP_EWSW[29]), .Y(n1933) );
NAND2X2TS U1466 ( .A(n2049), .B(DmP_EXP_EWSW[5]), .Y(n2001) );
NAND2X2TS U1467 ( .A(n2036), .B(DmP_EXP_EWSW[9]), .Y(n2014) );
INVX12TS U1468 ( .A(n955), .Y(n1401) );
NOR2X6TS U1469 ( .A(n1003), .B(Raw_mant_NRM_SWR[11]), .Y(n1466) );
BUFX16TS U1470 ( .A(n2134), .Y(n924) );
NAND2X4TS U1471 ( .A(n1190), .B(n2043), .Y(n1993) );
NAND3X6TS U1472 ( .A(n1567), .B(n1566), .C(n1565), .Y(n1786) );
NAND3X6TS U1473 ( .A(n1993), .B(n1994), .C(n1992), .Y(n637) );
AND2X8TS U1474 ( .A(n1188), .B(n1158), .Y(n1195) );
NOR2X6TS U1475 ( .A(n1195), .B(n1079), .Y(n1284) );
INVX12TS U1476 ( .A(n1373), .Y(n1038) );
OAI22X4TS U1477 ( .A0(n1445), .A1(n1443), .B0(n1430), .B1(n1010), .Y(n1429)
);
BUFX20TS U1478 ( .A(n1446), .Y(n1188) );
AOI21X4TS U1479 ( .A0(n1334), .A1(Raw_mant_NRM_SWR[19]), .B0(n1477), .Y(
n1042) );
NAND2X4TS U1480 ( .A(intDY_EWSW[23]), .B(n1379), .Y(n1889) );
NAND2X2TS U1481 ( .A(n2044), .B(DMP_EXP_EWSW[12]), .Y(n1956) );
AOI21X4TS U1482 ( .A0(n1187), .A1(n1184), .B0(n1080), .Y(n1283) );
NAND2X6TS U1483 ( .A(n1285), .B(intDY_EWSW[3]), .Y(n1970) );
BUFX6TS U1484 ( .A(Raw_mant_NRM_SWR[12]), .Y(n925) );
NAND2X4TS U1485 ( .A(n1435), .B(n989), .Y(n2009) );
NOR2X8TS U1486 ( .A(n2818), .B(n2056), .Y(n587) );
INVX8TS U1487 ( .A(n1037), .Y(n2144) );
NAND2X4TS U1488 ( .A(n1164), .B(n2048), .Y(n2005) );
NAND2X4TS U1489 ( .A(n2027), .B(intDX_EWSW[31]), .Y(n1655) );
BUFX6TS U1490 ( .A(intDY_EWSW[22]), .Y(n926) );
NAND2X4TS U1491 ( .A(intDY_EWSW[19]), .B(n2048), .Y(n2025) );
NAND2X4TS U1492 ( .A(n1564), .B(n1214), .Y(n2704) );
NAND2X4TS U1493 ( .A(n1435), .B(n926), .Y(n1984) );
CLKINVX12TS U1494 ( .A(n927), .Y(n1061) );
NAND2X8TS U1495 ( .A(n1179), .B(intDY_EWSW[13]), .Y(n927) );
CLKINVX12TS U1496 ( .A(n928), .Y(n1400) );
NAND4X8TS U1497 ( .A(n2325), .B(n2627), .C(n1143), .D(n985), .Y(n928) );
NOR2X8TS U1498 ( .A(n915), .B(n929), .Y(n2055) );
NAND2X8TS U1499 ( .A(n1325), .B(n1902), .Y(n929) );
NAND2X8TS U1500 ( .A(n924), .B(n1343), .Y(n1342) );
NAND2X4TS U1501 ( .A(n930), .B(Raw_mant_NRM_SWR[11]), .Y(n936) );
NOR2X8TS U1502 ( .A(n1568), .B(n940), .Y(n943) );
NOR2X4TS U1503 ( .A(n2336), .B(intDX_EWSW[4]), .Y(n940) );
NOR2X8TS U1504 ( .A(n2345), .B(intDX_EWSW[5]), .Y(n1568) );
AND2X8TS U1505 ( .A(n943), .B(n1276), .Y(n1068) );
OAI21X4TS U1506 ( .A0(n2338), .A1(n1158), .B0(n942), .Y(n941) );
NAND2X6TS U1507 ( .A(n2336), .B(intDX_EWSW[4]), .Y(n1267) );
AND2X8TS U1508 ( .A(n2325), .B(n1486), .Y(n1371) );
NOR2X8TS U1509 ( .A(Raw_mant_NRM_SWR[23]), .B(n1025), .Y(n1486) );
OAI21X4TS U1510 ( .A0(n2751), .A1(n1828), .B0(n944), .Y(n2720) );
XOR2X4TS U1511 ( .A(n945), .B(n1805), .Y(n1806) );
OAI21X2TS U1512 ( .A0(n2076), .A1(n2077), .B0(n2075), .Y(n945) );
OAI22X4TS U1513 ( .A0(n2071), .A1(n946), .B0(n962), .B1(n2363), .Y(n2077) );
OAI21X4TS U1514 ( .A0(n2166), .A1(n2065), .B0(n2067), .Y(n2071) );
BUFX20TS U1515 ( .A(n1334), .Y(n948) );
NAND2X8TS U1516 ( .A(n948), .B(n949), .Y(n1070) );
NAND2X8TS U1517 ( .A(n948), .B(n951), .Y(n950) );
AND2X8TS U1518 ( .A(n1015), .B(n1014), .Y(n1582) );
AOI21X4TS U1519 ( .A0(n954), .A1(n1808), .B0(n1812), .Y(n1382) );
CLKXOR2X2TS U1520 ( .A(n2181), .B(n954), .Y(n1408) );
NAND2X6TS U1521 ( .A(n1069), .B(n1050), .Y(n954) );
INVX12TS U1522 ( .A(n956), .Y(n1617) );
NAND3X8TS U1523 ( .A(n1401), .B(n1400), .C(n986), .Y(n956) );
NAND2X8TS U1524 ( .A(n1617), .B(n957), .Y(n1674) );
NOR2X8TS U1525 ( .A(n987), .B(n988), .Y(n986) );
NAND2X8TS U1526 ( .A(n1465), .B(n1466), .Y(n955) );
XNOR2X4TS U1527 ( .A(n2617), .B(DmP_mant_SFG_SWR[16]), .Y(n1549) );
NOR2X8TS U1528 ( .A(n1550), .B(DMP_SFG[15]), .Y(n2268) );
XNOR2X4TS U1529 ( .A(n2617), .B(DmP_mant_SFG_SWR[17]), .Y(n1550) );
AOI22X4TS U1530 ( .A0(n1620), .A1(n1037), .B0(n2628), .B1(
Raw_mant_NRM_SWR[3]), .Y(n2714) );
INVX16TS U1531 ( .A(n960), .Y(n2129) );
AOI2BB1X4TS U1532 ( .A0N(n960), .A1N(n959), .B0(n961), .Y(n2691) );
OAI22X4TS U1533 ( .A0(n1314), .A1(n2381), .B0(n1903), .B1(n1801), .Y(n961)
);
NAND2X6TS U1534 ( .A(n1391), .B(n1433), .Y(n1314) );
OR2X8TS U1535 ( .A(n2123), .B(n2153), .Y(n960) );
AND2X8TS U1536 ( .A(n1305), .B(n925), .Y(n1055) );
NAND2X2TS U1537 ( .A(n1037), .B(n1093), .Y(n1826) );
BUFX20TS U1538 ( .A(n1446), .Y(n1422) );
NAND2X4TS U1539 ( .A(n1184), .B(n2048), .Y(n1963) );
NAND2X4TS U1540 ( .A(n1013), .B(n2043), .Y(n1954) );
NAND2X8TS U1541 ( .A(n1275), .B(n1272), .Y(n1281) );
NAND2X4TS U1542 ( .A(n1435), .B(n1176), .Y(n1913) );
INVX12TS U1543 ( .A(n1373), .Y(n1374) );
AOI22X2TS U1544 ( .A0(n2171), .A1(n1033), .B0(n1663), .B1(n1122), .Y(n1124)
);
OA21X4TS U1545 ( .A0(n1713), .A1(n1712), .B0(n1711), .Y(n1050) );
CLKINVX12TS U1546 ( .A(Raw_mant_NRM_SWR[24]), .Y(n1461) );
NOR2X4TS U1547 ( .A(n1690), .B(n1693), .Y(n1039) );
AND2X8TS U1548 ( .A(n1099), .B(Shift_reg_FLAGS_7_6), .Y(n965) );
NAND2X2TS U1549 ( .A(n2628), .B(Raw_mant_NRM_SWR[5]), .Y(n2738) );
OR2X8TS U1550 ( .A(n1421), .B(n1437), .Y(n1384) );
OAI22X1TS U1551 ( .A0(n2205), .A1(n966), .B0(n975), .B1(n2590), .Y(
final_result_ieee[20]) );
NAND2X2TS U1552 ( .A(n973), .B(n2535), .Y(final_result_ieee[28]) );
OAI22X1TS U1553 ( .A0(n2205), .A1(n2563), .B0(n974), .B1(n2562), .Y(
final_result_ieee[15]) );
OAI22X1TS U1554 ( .A0(n2205), .A1(n2589), .B0(n975), .B1(n2588), .Y(
final_result_ieee[10]) );
OAI22X1TS U1555 ( .A0(n1235), .A1(n2574), .B0(n975), .B1(n2573), .Y(
final_result_ieee[13]) );
OAI22X1TS U1556 ( .A0(n1234), .A1(n2572), .B0(n975), .B1(n2571), .Y(
final_result_ieee[8]) );
OAI22X1TS U1557 ( .A0(n1234), .A1(n2561), .B0(n975), .B1(n2560), .Y(
final_result_ieee[6]) );
NAND2X4TS U1558 ( .A(n1664), .B(n1848), .Y(n1611) );
NAND3BX4TS U1559 ( .AN(n976), .B(n2614), .C(n2613), .Y(n1848) );
OA21X4TS U1560 ( .A0(Raw_mant_NRM_SWR[1]), .A1(Raw_mant_NRM_SWR[0]), .B0(
n1861), .Y(n1056) );
AND2X8TS U1561 ( .A(n1099), .B(Shift_reg_FLAGS_7_6), .Y(n981) );
AND2X8TS U1562 ( .A(n1099), .B(Shift_reg_FLAGS_7_6), .Y(n982) );
MX2X4TS U1563 ( .A(Data_Y[3]), .B(intDY_EWSW[3]), .S0(n2247), .Y(n854) );
BUFX20TS U1564 ( .A(n1383), .Y(n1285) );
INVX8TS U1565 ( .A(n1361), .Y(n1360) );
NAND2X6TS U1566 ( .A(n2348), .B(n1176), .Y(n1347) );
NAND2X4TS U1567 ( .A(n1435), .B(intDY_EWSW[25]), .Y(n1894) );
BUFX20TS U1568 ( .A(n1004), .Y(n1187) );
NAND2X4TS U1569 ( .A(n1288), .B(n1187), .Y(n2016) );
NOR2X8TS U1570 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[25]), .Y(
n1467) );
OR2X8TS U1571 ( .A(n1025), .B(Raw_mant_NRM_SWR[16]), .Y(n988) );
NAND2X8TS U1572 ( .A(n1104), .B(n1103), .Y(n1450) );
NAND2X6TS U1573 ( .A(n1783), .B(n1784), .Y(n1403) );
NAND2X2TS U1574 ( .A(n1187), .B(n1293), .Y(n2047) );
NAND2X2TS U1575 ( .A(n1447), .B(n1164), .Y(n1955) );
INVX6TS U1576 ( .A(n2263), .Y(n1753) );
AND2X6TS U1577 ( .A(n2195), .B(n2193), .Y(n1853) );
AND2X8TS U1578 ( .A(n1856), .B(n921), .Y(n2818) );
NAND2X4TS U1579 ( .A(n2818), .B(n2104), .Y(n2815) );
NOR2X8TS U1580 ( .A(n1697), .B(n1067), .Y(n1445) );
NOR2X4TS U1581 ( .A(n1549), .B(DMP_SFG[14]), .Y(n2260) );
OAI2BB2X4TS U1582 ( .B0(n1568), .B1(n1267), .A0N(n993), .A1N(n2345), .Y(
n1274) );
XNOR2X4TS U1583 ( .A(intDY_EWSW[28]), .B(n996), .Y(n1254) );
CLKINVX12TS U1584 ( .A(Raw_mant_NRM_SWR[21]), .Y(n1002) );
INVX16TS U1585 ( .A(n1002), .Y(n1003) );
OAI21X4TS U1586 ( .A0(n1728), .A1(n2360), .B0(n1727), .Y(n563) );
INVX6TS U1587 ( .A(n1035), .Y(n1032) );
OAI2BB2X4TS U1588 ( .B0(n1330), .B1(n1328), .A0N(n909), .A1N(n1327), .Y(
n1326) );
CLKINVX12TS U1589 ( .A(n1378), .Y(n1004) );
CLKINVX12TS U1590 ( .A(n1449), .Y(n1102) );
AND3X8TS U1591 ( .A(n1449), .B(n1107), .C(n1111), .Y(n1064) );
NAND2X4TS U1592 ( .A(intDX_EWSW[25]), .B(n2048), .Y(n1885) );
NAND2X4TS U1593 ( .A(n2027), .B(n1182), .Y(n1888) );
NAND3X8TS U1594 ( .A(n1344), .B(n1342), .C(n1085), .Y(n2150) );
NOR2X4TS U1595 ( .A(n2195), .B(n2193), .Y(n1752) );
NOR2X6TS U1596 ( .A(n1390), .B(n1389), .Y(n1757) );
NAND3X2TS U1597 ( .A(n1046), .B(n2142), .C(DmP_mant_SHT1_SW[17]), .Y(n2741)
);
INVX8TS U1598 ( .A(n1819), .Y(n1229) );
NOR2X6TS U1599 ( .A(n2335), .B(n1181), .Y(n1369) );
NOR2X6TS U1600 ( .A(n2333), .B(n1182), .Y(n1588) );
INVX2TS U1601 ( .A(n1428), .Y(n1047) );
NAND4X4TS U1602 ( .A(n1313), .B(n2627), .C(n1470), .D(n1469), .Y(n1473) );
CLKINVX12TS U1603 ( .A(n1049), .Y(n1614) );
AOI22X2TS U1604 ( .A0(n1201), .A1(n812), .B0(n2176), .B1(n2175), .Y(n1114)
);
NAND2X1TS U1605 ( .A(n1229), .B(n2172), .Y(n1116) );
INVX4TS U1606 ( .A(n1760), .Y(n1389) );
NOR2X4TS U1607 ( .A(n1761), .B(n1762), .Y(n1390) );
INVX2TS U1608 ( .A(n2285), .Y(n1343) );
CLKINVX12TS U1609 ( .A(n1438), .Y(n1373) );
INVX4TS U1610 ( .A(n1858), .Y(n2157) );
INVX6TS U1611 ( .A(n2104), .Y(n1396) );
OR2X4TS U1612 ( .A(n1513), .B(n1113), .Y(n2174) );
NAND2X2TS U1613 ( .A(n1122), .B(n2192), .Y(n1821) );
NOR2X4TS U1614 ( .A(n1230), .B(shift_value_SHT2_EWR[4]), .Y(n1743) );
NAND2X2TS U1615 ( .A(n1744), .B(n1228), .Y(n1517) );
NOR2X4TS U1616 ( .A(n2217), .B(n2290), .Y(n2256) );
NAND2X4TS U1617 ( .A(DMP_SFG[13]), .B(n1412), .Y(n2254) );
INVX2TS U1618 ( .A(n1160), .Y(n1161) );
AND2X4TS U1619 ( .A(n1736), .B(n1735), .Y(n2784) );
MXI2X2TS U1620 ( .A(n2058), .B(n2057), .S0(n1247), .Y(n1736) );
NAND3X6TS U1621 ( .A(n1146), .B(intDX_EWSW[0]), .C(n2351), .Y(n1145) );
NAND2X4TS U1622 ( .A(n992), .B(intDX_EWSW[12]), .Y(n1332) );
NOR2X4TS U1623 ( .A(n1577), .B(n1364), .Y(n1574) );
INVX4TS U1624 ( .A(n1287), .Y(n1426) );
NOR2X4TS U1625 ( .A(n1592), .B(n1402), .Y(n1296) );
NAND2X2TS U1626 ( .A(n1163), .B(intDX_EWSW[26]), .Y(n1402) );
AND2X4TS U1627 ( .A(n2332), .B(intDX_EWSW[27]), .Y(n1295) );
NAND2X4TS U1628 ( .A(n1594), .B(n1593), .Y(n1297) );
NAND2X2TS U1629 ( .A(n2346), .B(intDX_EWSW[25]), .Y(n1589) );
NOR2X2TS U1630 ( .A(Raw_mant_NRM_SWR[5]), .B(n1010), .Y(n1479) );
INVX4TS U1631 ( .A(n2269), .Y(n1414) );
NAND4X2TS U1632 ( .A(n1626), .B(n1651), .C(n1650), .D(n1078), .Y(n1258) );
INVX4TS U1633 ( .A(n1599), .Y(n1109) );
NOR2X4TS U1634 ( .A(n1677), .B(n2331), .Y(n1684) );
NOR2X4TS U1635 ( .A(n1677), .B(n2359), .Y(n1341) );
AND2X4TS U1636 ( .A(n1631), .B(n1636), .Y(n1260) );
NAND2X4TS U1637 ( .A(n2189), .B(n1664), .Y(n1529) );
NAND2X2TS U1638 ( .A(n1122), .B(n1848), .Y(n1818) );
NAND2X1TS U1639 ( .A(n2023), .B(n1018), .Y(n1989) );
NAND2X2TS U1640 ( .A(n2273), .B(n1025), .Y(n1407) );
NAND2X2TS U1641 ( .A(n2765), .B(DmP_mant_SHT1_SW[14]), .Y(n2666) );
OAI22X2TS U1642 ( .A0(n2055), .A1(n2144), .B0(n1034), .B1(n1903), .Y(n824)
);
NAND2X1TS U1643 ( .A(n2411), .B(n1154), .Y(n1915) );
AOI21X2TS U1644 ( .A0(n2259), .A1(n2267), .B0(n2266), .Y(n2272) );
INVX4TS U1645 ( .A(n1774), .Y(n1393) );
NOR2X4TS U1646 ( .A(n2149), .B(n1021), .Y(n1333) );
BUFX8TS U1647 ( .A(Raw_mant_NRM_SWR[16]), .Y(n1304) );
AOI21X2TS U1648 ( .A0(n2129), .A1(Raw_mant_NRM_SWR[1]), .B0(n1432), .Y(n2715) );
NOR2X2TS U1649 ( .A(n1436), .B(n2326), .Y(n2759) );
MX2X4TS U1650 ( .A(n2124), .B(LZD_output_NRM2_EW[3]), .S0(n2292), .Y(n547)
);
AOI21X1TS U1651 ( .A0(DmP_mant_SHT1_SW[10]), .A1(n2151), .B0(n1377), .Y(
n1376) );
NAND2BX2TS U1652 ( .AN(n2144), .B(n2199), .Y(n2761) );
NOR2X6TS U1653 ( .A(n1774), .B(n2438), .Y(n1392) );
NOR2X2TS U1654 ( .A(n1316), .B(n985), .Y(n2706) );
NAND2X2TS U1655 ( .A(n2164), .B(Raw_mant_NRM_SWR[11]), .Y(n2682) );
NAND2X2TS U1656 ( .A(n2129), .B(Raw_mant_NRM_SWR[19]), .Y(n2734) );
AOI22X2TS U1657 ( .A0(n1859), .A1(left_right_SHT2), .B0(n1858), .B1(n2185),
.Y(n2808) );
OAI22X2TS U1658 ( .A0(n1794), .A1(n1547), .B0(n1546), .B1(n1793), .Y(n1548)
);
NOR2X4TS U1659 ( .A(n1442), .B(n1441), .Y(n2711) );
NAND2X2TS U1660 ( .A(n2060), .B(n2174), .Y(n1121) );
NAND2X2TS U1661 ( .A(n2765), .B(DmP_mant_SHT1_SW[3]), .Y(n2707) );
NOR2X2TS U1662 ( .A(n532), .B(n553), .Y(n2577) );
MXI2X4TS U1663 ( .A(n1680), .B(n1679), .S0(left_right_SHT2), .Y(n1681) );
AOI22X2TS U1664 ( .A0(n2169), .A1(n923), .B0(n2168), .B1(n2185), .Y(n2806)
);
CLKINVX3TS U1665 ( .A(n1215), .Y(n1212) );
CLKINVX3TS U1666 ( .A(rst), .Y(n1200) );
OAI21X2TS U1667 ( .A0(n2804), .A1(n2630), .B0(n1117), .Y(n496) );
INVX2TS U1668 ( .A(n2419), .Y(n1118) );
CLKINVX3TS U1669 ( .A(n1215), .Y(n1217) );
CLKBUFX3TS U1670 ( .A(n1223), .Y(n2658) );
NAND2X2TS U1671 ( .A(n1188), .B(intDX_EWSW[24]), .Y(n1901) );
NAND2X2TS U1672 ( .A(n2036), .B(DmP_EXP_EWSW[8]), .Y(n2004) );
NAND2X2TS U1673 ( .A(n1422), .B(n1173), .Y(n1935) );
NAND2X1TS U1674 ( .A(n2411), .B(DMP_EXP_EWSW[20]), .Y(n1906) );
NAND2X1TS U1675 ( .A(n2411), .B(DMP_EXP_EWSW[18]), .Y(n1912) );
BUFX3TS U1676 ( .A(n2658), .Y(n2639) );
NAND2X1TS U1677 ( .A(n2411), .B(DMP_EXP_EWSW[14]), .Y(n1909) );
NAND2X1TS U1678 ( .A(n2023), .B(DMP_EXP_EWSW[9]), .Y(n1965) );
NAND2X1TS U1679 ( .A(n2049), .B(DMP_EXP_EWSW[7]), .Y(n1962) );
BUFX3TS U1680 ( .A(n2658), .Y(n2636) );
BUFX3TS U1681 ( .A(n2658), .Y(n2637) );
INVX3TS U1682 ( .A(n1197), .Y(n1211) );
CLKBUFX3TS U1683 ( .A(n2063), .Y(n2442) );
BUFX3TS U1684 ( .A(n2658), .Y(n2648) );
MX2X1TS U1685 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n2248), .Y(n865) );
BUFX3TS U1686 ( .A(n2658), .Y(n2634) );
CLKINVX3TS U1687 ( .A(rst), .Y(n1208) );
CLKINVX3TS U1688 ( .A(n1197), .Y(n1207) );
CLKBUFX3TS U1689 ( .A(n2658), .Y(n2650) );
NAND4X4TS U1690 ( .A(n1662), .B(n1661), .C(n1660), .D(n1659), .Y(n1789) );
NAND2X4TS U1691 ( .A(n1837), .B(n1835), .Y(n1659) );
NAND2X6TS U1692 ( .A(n1475), .B(n1476), .Y(n1474) );
AND2X8TS U1693 ( .A(n1391), .B(n2136), .Y(n1007) );
AOI21X4TS U1694 ( .A0(n1244), .A1(n1710), .B0(n1715), .Y(n1623) );
NAND2X4TS U1695 ( .A(n1550), .B(DMP_SFG[15]), .Y(n2269) );
NAND2X2TS U1696 ( .A(n1318), .B(n1025), .Y(n1494) );
NAND4BX4TS U1697 ( .AN(n2518), .B(n2517), .C(n2516), .D(n2515), .Y(n2137) );
AND3X6TS U1698 ( .A(n1476), .B(n1475), .C(n2225), .Y(n1315) );
INVX6TS U1699 ( .A(n1619), .Y(n1309) );
NAND2X4TS U1700 ( .A(intDX_EWSW[17]), .B(n1435), .Y(n1919) );
OAI22X4TS U1701 ( .A0(n1347), .A1(n1349), .B0(intDY_EWSW[19]), .B1(n1009),
.Y(n1346) );
NAND2X2TS U1702 ( .A(n1864), .B(n1694), .Y(n1695) );
BUFX8TS U1703 ( .A(n1617), .Y(n1307) );
AND3X2TS U1704 ( .A(n1011), .B(n1307), .C(n2400), .Y(n1041) );
NOR2X4TS U1705 ( .A(n1330), .B(n1329), .Y(n1012) );
NOR2X8TS U1706 ( .A(n990), .B(n907), .Y(n1329) );
NAND2X2TS U1707 ( .A(n1447), .B(n997), .Y(n1964) );
NAND2X2TS U1708 ( .A(n1379), .B(n989), .Y(n1911) );
NAND2X2TS U1709 ( .A(n1422), .B(n1027), .Y(n1920) );
NAND2X2TS U1710 ( .A(n1447), .B(intDY_EWSW[20]), .Y(n1908) );
BUFX20TS U1711 ( .A(Raw_mant_NRM_SWR[23]), .Y(n1016) );
NAND2X4TS U1712 ( .A(n1405), .B(n1786), .Y(n2736) );
NAND2X4TS U1713 ( .A(n1405), .B(n1088), .Y(n2710) );
NAND2X4TS U1714 ( .A(n1405), .B(n931), .Y(n2719) );
NAND2X4TS U1715 ( .A(n1405), .B(n1843), .Y(n2663) );
NOR2BX2TS U1716 ( .AN(n2159), .B(n1213), .Y(n1312) );
NOR2X6TS U1717 ( .A(n2341), .B(intDX_EWSW[19]), .Y(n1349) );
NAND2X4TS U1718 ( .A(n1842), .B(n1214), .Y(n2670) );
NOR2X4TS U1719 ( .A(n2348), .B(n1176), .Y(n1348) );
NOR2X4TS U1720 ( .A(Raw_mant_NRM_SWR[16]), .B(n984), .Y(n1469) );
BUFX20TS U1721 ( .A(n1004), .Y(n1447) );
BUFX20TS U1722 ( .A(n1446), .Y(n1383) );
NOR2X6TS U1723 ( .A(n1019), .B(n1082), .Y(n1286) );
AND2X8TS U1724 ( .A(n1383), .B(intDY_EWSW[2]), .Y(n1019) );
OAI21X4TS U1725 ( .A0(n1798), .A1(n1606), .B0(n1605), .Y(n2766) );
NAND3X6TS U1726 ( .A(n1674), .B(n2226), .C(n1616), .Y(n1151) );
AND2X8TS U1727 ( .A(n1459), .B(n1029), .Y(n1465) );
AOI21X2TS U1728 ( .A0(n2129), .A1(n2618), .B0(n1803), .Y(n2685) );
NAND2X4TS U1729 ( .A(n1686), .B(n1167), .Y(n1688) );
NAND2X4TS U1730 ( .A(n1028), .B(intDX_EWSW[17]), .Y(n1291) );
NOR2X8TS U1731 ( .A(n1125), .B(n1031), .Y(n1030) );
NAND2X4TS U1732 ( .A(n1841), .B(n1405), .Y(n2729) );
OR2X8TS U1733 ( .A(n1073), .B(n1493), .Y(n1841) );
CLKMX2X2TS U1734 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n2253), .Y(n874)
);
XNOR2X2TS U1735 ( .A(n1027), .B(intDX_EWSW[17]), .Y(n1626) );
NAND2X4TS U1736 ( .A(n2134), .B(n1384), .Y(n1239) );
CLKAND2X2TS U1737 ( .A(n1313), .B(n1488), .Y(n1172) );
INVX8TS U1738 ( .A(n1059), .Y(n1213) );
NAND3X4TS U1739 ( .A(n1617), .B(n1490), .C(n1010), .Y(n1150) );
NAND3X8TS U1740 ( .A(n1401), .B(n1400), .C(n986), .Y(n1035) );
NOR2X2TS U1741 ( .A(n2627), .B(n1003), .Y(n1462) );
MX2X4TS U1742 ( .A(n2103), .B(Raw_mant_NRM_SWR[18]), .S0(n2360), .Y(n568) );
NAND2BX4TS U1743 ( .AN(n1374), .B(n2154), .Y(n2756) );
AOI2BB2X2TS U1744 ( .B0(n2164), .B1(n1166), .A0N(n2163), .A1N(n905), .Y(
n2692) );
AOI2BB2X2TS U1745 ( .B0(n2164), .B1(Raw_mant_NRM_SWR[2]), .A0N(n2162), .A1N(
n905), .Y(n2716) );
INVX16TS U1746 ( .A(n1324), .Y(n2134) );
BUFX20TS U1747 ( .A(n1059), .Y(n1037) );
NAND2X4TS U1748 ( .A(n1405), .B(n932), .Y(n2698) );
NAND2X6TS U1749 ( .A(n1488), .B(n1313), .Y(n1690) );
OAI22X4TS U1750 ( .A0(n1314), .A1(n2357), .B0(n1903), .B1(n1040), .Y(n1803)
);
NAND2X8TS U1751 ( .A(n1307), .B(n1010), .Y(n1864) );
NAND2X2TS U1752 ( .A(n1122), .B(n1875), .Y(n1730) );
NAND2BX2TS U1753 ( .AN(n1374), .B(n2135), .Y(n2721) );
NAND2X2TS U1754 ( .A(n1188), .B(intDX_EWSW[17]), .Y(n2042) );
OAI2BB1X4TS U1755 ( .A0N(n1044), .A1N(n1045), .B0(n1686), .Y(n1148) );
OR2X6TS U1756 ( .A(n1491), .B(n1167), .Y(n1045) );
NAND3X4TS U1757 ( .A(n1742), .B(n1738), .C(n1379), .Y(n1656) );
INVX16TS U1758 ( .A(n1324), .Y(n1334) );
AOI2BB2X4TS U1759 ( .B0(n1039), .B1(n1464), .A0N(n1048), .A1N(n1047), .Y(
n1427) );
OA21X4TS U1760 ( .A0(n1003), .A1(n985), .B0(n1054), .Y(n1048) );
NAND2X4TS U1761 ( .A(intDX_EWSW[4]), .B(n2048), .Y(n1951) );
AOI22X4TS U1762 ( .A0(n2155), .A1(n1214), .B0(n2628), .B1(n1020), .Y(n2677)
);
NAND3BX4TS U1763 ( .AN(n2400), .B(n1673), .C(n1307), .Y(n1696) );
XNOR2X4TS U1764 ( .A(n1302), .B(n1083), .Y(n1053) );
AND2X8TS U1765 ( .A(n1461), .B(n1026), .Y(n1054) );
AND2X6TS U1766 ( .A(n1355), .B(n1600), .Y(n1057) );
OR2X4TS U1767 ( .A(Raw_mant_NRM_SWR[12]), .B(n1020), .Y(n1062) );
OR2X4TS U1768 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[3]), .Y(n1067)
);
AND2X8TS U1769 ( .A(n1410), .B(n1409), .Y(n1069) );
AND2X4TS U1770 ( .A(n2134), .B(Raw_mant_NRM_SWR[0]), .Y(n1071) );
AND2X4TS U1771 ( .A(n1363), .B(n1160), .Y(n1073) );
AND2X4TS U1772 ( .A(n1616), .B(n1691), .Y(n1074) );
AND2X2TS U1773 ( .A(n2173), .B(n812), .Y(n1075) );
OR2X2TS U1774 ( .A(n2156), .B(n2358), .Y(n1077) );
AND2X2TS U1775 ( .A(n2049), .B(DmP_EXP_EWSW[7]), .Y(n1080) );
AND2X2TS U1776 ( .A(n2034), .B(DmP_EXP_EWSW[27]), .Y(n1081) );
AND2X2TS U1777 ( .A(n2049), .B(DMP_EXP_EWSW[2]), .Y(n1082) );
OR2X2TS U1778 ( .A(n1240), .B(n2362), .Y(n1085) );
AND3X6TS U1779 ( .A(n1116), .B(n1114), .C(n1112), .Y(n1086) );
AND2X2TS U1780 ( .A(n1210), .B(DmP_mant_SHT1_SW[12]), .Y(n1092) );
INVX8TS U1781 ( .A(n2344), .Y(n1228) );
AND2X2TS U1782 ( .A(n2152), .B(DmP_mant_SHT1_SW[20]), .Y(n1093) );
INVX2TS U1783 ( .A(rst), .Y(n1221) );
CLKINVX3TS U1784 ( .A(n1215), .Y(n1219) );
INVX2TS U1785 ( .A(n2643), .Y(n1197) );
INVX2TS U1786 ( .A(n2640), .Y(n1215) );
CLKBUFX2TS U1787 ( .A(n1223), .Y(n2641) );
CLKBUFX3TS U1788 ( .A(n2063), .Y(n2633) );
INVX2TS U1789 ( .A(n1197), .Y(n1198) );
CLKBUFX2TS U1790 ( .A(n2442), .Y(n2632) );
INVX3TS U1791 ( .A(rst), .Y(n1222) );
INVX2TS U1792 ( .A(rst), .Y(n1225) );
INVX2TS U1793 ( .A(rst), .Y(n1224) );
CLKBUFX2TS U1794 ( .A(n1225), .Y(n2643) );
INVX2TS U1795 ( .A(n1197), .Y(n1205) );
INVX2TS U1796 ( .A(n1215), .Y(n1204) );
INVX2TS U1797 ( .A(rst), .Y(n1203) );
INVX2TS U1798 ( .A(n1197), .Y(n1202) );
NOR2X8TS U1799 ( .A(n1095), .B(n1595), .Y(n1601) );
NAND3X8TS U1800 ( .A(n1419), .B(n1066), .C(n1600), .Y(n1595) );
OAI21X4TS U1801 ( .A0(n1098), .A1(n1236), .B0(n1097), .Y(n1096) );
AOI21X4TS U1802 ( .A0(n1353), .A1(n1354), .B0(n1352), .Y(n1097) );
NAND2X8TS U1803 ( .A(n1354), .B(n1423), .Y(n1236) );
AOI21X4TS U1804 ( .A0(n1290), .A1(n1268), .B0(n1346), .Y(n1098) );
NAND2X8TS U1805 ( .A(n1450), .B(n1100), .Y(n1099) );
NOR2X8TS U1806 ( .A(n1102), .B(n1101), .Y(n1100) );
NAND2X8TS U1807 ( .A(n1110), .B(n1111), .Y(n1101) );
AND2X8TS U1808 ( .A(n1279), .B(n1601), .Y(n1103) );
NAND2X8TS U1809 ( .A(n1243), .B(n1241), .Y(n1104) );
NAND2X4TS U1810 ( .A(n1105), .B(n1574), .Y(n1575) );
AOI21X4TS U1811 ( .A0(n1105), .A1(n1366), .B0(n1365), .Y(n1289) );
NOR2X8TS U1812 ( .A(n1368), .B(n1369), .Y(n1105) );
BUFX20TS U1813 ( .A(n965), .Y(n1106) );
NOR3BX4TS U1814 ( .AN(n2501), .B(n1060), .C(n2502), .Y(n1115) );
NOR2X8TS U1815 ( .A(shift_value_SHT2_EWR[3]), .B(n1193), .Y(n1532) );
AOI21X4TS U1816 ( .A0(n2054), .A1(left_right_SHT2), .B0(n1119), .Y(n2804) );
OAI21X4TS U1817 ( .A0(n1606), .A1(n1668), .B0(n1499), .Y(n2052) );
NAND4BX4TS U1818 ( .AN(n1075), .B(n1515), .C(n1517), .D(n1516), .Y(n2054) );
NAND2X8TS U1819 ( .A(n1193), .B(n1052), .Y(n1668) );
AOI22X4TS U1820 ( .A0(n2171), .A1(n2184), .B0(n1122), .B1(n2189), .Y(n1123)
);
AOI22X4TS U1821 ( .A0(n2121), .A1(n923), .B0(n2185), .B1(n1033), .Y(n2810)
);
NAND2X8TS U1822 ( .A(n1128), .B(n1127), .Y(n2121) );
AND2X8TS U1823 ( .A(n1838), .B(n1839), .Y(n1127) );
OR2X8TS U1824 ( .A(n1834), .B(n2344), .Y(n1128) );
NOR2X8TS U1825 ( .A(n1531), .B(n1530), .Y(n1834) );
NAND2BX4TS U1826 ( .AN(n1129), .B(n1729), .Y(n1859) );
NAND3X8TS U1827 ( .A(n1134), .B(n1133), .C(n1130), .Y(n1129) );
NOR2BX4TS U1828 ( .AN(n2600), .B(n2602), .Y(n1131) );
NAND2X8TS U1829 ( .A(n1845), .B(n1228), .Y(n1134) );
OAI21X4TS U1830 ( .A0(n1798), .A1(n2157), .B0(n1142), .Y(n2158) );
OA21X4TS U1831 ( .A0(n1142), .A1(n2353), .B0(n1136), .Y(n2730) );
OA21X4TS U1832 ( .A0(n1142), .A1(n2358), .B0(n1137), .Y(n2735) );
OA21X4TS U1833 ( .A0(n1142), .A1(n2384), .B0(n1138), .Y(n2671) );
OA21X4TS U1834 ( .A0(n1142), .A1(n2190), .B0(n1139), .Y(n2695) );
OA21X4TS U1835 ( .A0(n1142), .A1(n2357), .B0(n1140), .Y(n2763) );
OA21X4TS U1836 ( .A0(n1142), .A1(n2428), .B0(n1141), .Y(n2703) );
OA22X4TS U1837 ( .A0(n980), .A1(n979), .B0(n978), .B1(n977), .Y(n2664) );
OAI22X4TS U1838 ( .A0(n1369), .A1(n1147), .B0(intDY_EWSW[11]), .B1(n1159),
.Y(n1365) );
NAND2X8TS U1839 ( .A(n1398), .B(n1399), .Y(n1421) );
AND3X8TS U1840 ( .A(n1150), .B(n1148), .C(n1149), .Y(n1399) );
NAND3X4TS U1841 ( .A(n1866), .B(n1490), .C(Raw_mant_NRM_SWR[18]), .Y(n1149)
);
NAND2X8TS U1842 ( .A(n1151), .B(n1490), .Y(n1398) );
NOR2X4TS U1843 ( .A(n2347), .B(intDX_EWSW[20]), .Y(n1424) );
NAND3BX4TS U1844 ( .AN(n1152), .B(n1943), .C(n1942), .Y(n772) );
AND2X4TS U1845 ( .A(n1422), .B(n1005), .Y(n1152) );
NOR2X6TS U1846 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[25]), .Y(
n1471) );
NAND4BX4TS U1847 ( .AN(n2514), .B(n2664), .C(n2513), .D(n2512), .Y(n2140) );
NAND3BX4TS U1848 ( .AN(n1155), .B(n1957), .C(n1956), .Y(n770) );
AND2X4TS U1849 ( .A(n1383), .B(n991), .Y(n1155) );
XOR2X4TS U1850 ( .A(n917), .B(DmP_mant_SFG_SWR[19]), .Y(n1156) );
NAND3BX4TS U1851 ( .AN(n1157), .B(n1905), .C(n1904), .Y(n766) );
AOI22X1TS U1852 ( .A0(n2060), .A1(n2140), .B0(n1830), .B1(n2053), .Y(n1612)
);
NAND3X4TS U1853 ( .A(n1655), .B(n1656), .C(n1654), .Y(n749) );
OR2X6TS U1854 ( .A(n2340), .B(intDX_EWSW[30]), .Y(n1600) );
NOR2X4TS U1855 ( .A(n1716), .B(DMP_SFG[20]), .Y(n1720) );
NAND2X4TS U1856 ( .A(n1555), .B(DMP_SFG[18]), .Y(n1712) );
NAND2X8TS U1857 ( .A(n1271), .B(n1270), .Y(n1269) );
NAND2X6TS U1858 ( .A(n1277), .B(n1278), .Y(n1271) );
NOR2X4TS U1859 ( .A(n1436), .B(n1021), .Y(n2683) );
NOR2X4TS U1860 ( .A(n1766), .B(n1763), .Y(n1768) );
AOI2BB1X4TS U1861 ( .A0N(n1696), .A1N(Raw_mant_NRM_SWR[6]), .B0(n1695), .Y(
n1700) );
NAND2X2TS U1862 ( .A(n1187), .B(intDY_EWSW[18]), .Y(n1914) );
NAND2X2TS U1863 ( .A(n1422), .B(n1162), .Y(n1883) );
NAND2X2TS U1864 ( .A(n1188), .B(n999), .Y(n1973) );
NAND2X2TS U1865 ( .A(n1379), .B(intDY_EWSW[19]), .Y(n1923) );
NAND2X2TS U1866 ( .A(n1422), .B(intDY_EWSW[30]), .Y(n1929) );
NAND2X2TS U1867 ( .A(n1422), .B(intDY_EWSW[21]), .Y(n1979) );
AOI2BB2X4TS U1868 ( .B0(n2164), .B1(Raw_mant_NRM_SWR[4]), .A0N(n1374), .A1N(
n1825), .Y(n2743) );
NOR2X8TS U1869 ( .A(n1361), .B(n1358), .Y(n1277) );
AND2X4TS U1870 ( .A(n1544), .B(n2191), .Y(n1669) );
NOR2X8TS U1871 ( .A(n1572), .B(n1061), .Y(n1573) );
NAND2X4TS U1872 ( .A(n1375), .B(n1786), .Y(n2713) );
NAND2X4TS U1873 ( .A(n1375), .B(n1564), .Y(n2744) );
INVX16TS U1874 ( .A(n1038), .Y(n1375) );
XOR2X4TS U1875 ( .A(n1777), .B(n1175), .Y(n2275) );
AND2X8TS U1876 ( .A(n1180), .B(n1463), .Y(n1320) );
AND2X8TS U1877 ( .A(n1054), .B(n1471), .Y(n1180) );
NOR2X4TS U1878 ( .A(n1016), .B(n984), .Y(n1463) );
OAI22X2TS U1879 ( .A0(n2148), .A1(n2190), .B0(n1903), .B1(n1849), .Y(n1850)
);
OAI22X2TS U1880 ( .A0(n2148), .A1(n2354), .B0(n1802), .B1(n1903), .Y(n1432)
);
NOR2X2TS U1881 ( .A(n1689), .B(n1868), .Y(n1701) );
NOR2X4TS U1882 ( .A(n1685), .B(n1684), .Y(n1702) );
NAND2X4TS U1883 ( .A(n1435), .B(intDX_EWSW[27]), .Y(n1603) );
NAND2X4TS U1884 ( .A(n1667), .B(n1666), .Y(n1670) );
NAND2X2TS U1885 ( .A(n1664), .B(n1663), .Y(n1667) );
OAI2BB1X4TS U1886 ( .A0N(n1544), .A1N(n1858), .B0(n1611), .Y(n1830) );
INVX16TS U1887 ( .A(n1317), .Y(n1318) );
NAND2X4TS U1888 ( .A(n1037), .B(n2134), .Y(n1436) );
AOI22X2TS U1889 ( .A0(n2185), .A1(n2118), .B0(n2178), .B1(n815), .Y(n2119)
);
AOI22X2TS U1890 ( .A0(n2185), .A1(n815), .B0(n2178), .B1(n2118), .Y(n1823)
);
NAND4X4TS U1891 ( .A(n2585), .B(n2584), .C(n2583), .D(n2582), .Y(n2118) );
XNOR2X1TS U1892 ( .A(intDY_EWSW[23]), .B(n1182), .Y(n1638) );
NOR2X4TS U1893 ( .A(intDX_EWSW[10]), .B(n1006), .Y(n1368) );
BUFX8TS U1894 ( .A(Raw_mant_NRM_SWR[25]), .Y(n1306) );
NAND3X4TS U1895 ( .A(n1886), .B(n1885), .C(n1884), .Y(n757) );
NAND3X4TS U1896 ( .A(n1880), .B(n1879), .C(n1878), .Y(n758) );
OAI2BB2X2TS U1897 ( .B0(n1794), .B1(n2727), .A0N(n1743), .A1N(n2052), .Y(
n1519) );
OAI21X4TS U1898 ( .A0(n2153), .A1(n2331), .B0(n2132), .Y(n2154) );
OAI21X4TS U1899 ( .A0(n1036), .A1(n1011), .B0(n2051), .Y(n2199) );
NAND2X4TS U1900 ( .A(n1375), .B(n1877), .Y(n2764) );
NAND2X4TS U1901 ( .A(n2697), .B(n1375), .Y(n2700) );
NAND2X2TS U1902 ( .A(n1375), .B(n2199), .Y(n2681) );
CLKMX2X2TS U1903 ( .A(n2274), .B(n1160), .S0(n2273), .Y(n569) );
NAND2X2TS U1904 ( .A(n1447), .B(intDY_EWSW[0]), .Y(n1932) );
NAND2X4TS U1905 ( .A(n1359), .B(intDX_EWSW[1]), .Y(n1994) );
NAND2X4TS U1906 ( .A(n1359), .B(intDX_EWSW[22]), .Y(n1985) );
NAND2X4TS U1907 ( .A(n1285), .B(intDX_EWSW[13]), .Y(n2030) );
NAND2X4TS U1908 ( .A(n1285), .B(n1013), .Y(n2006) );
NAND2X4TS U1909 ( .A(n1359), .B(n1303), .Y(n2026) );
NAND2X4TS U1910 ( .A(n1071), .B(n1037), .Y(n1605) );
NAND3X4TS U1911 ( .A(n1037), .B(n924), .C(Raw_mant_NRM_SWR[2]), .Y(n1807) );
NOR2X4TS U1912 ( .A(n1196), .B(n1081), .Y(n1282) );
AND2X4TS U1913 ( .A(n1383), .B(intDX_EWSW[27]), .Y(n1196) );
NAND2X2TS U1914 ( .A(n1422), .B(intDY_EWSW[24]), .Y(n1880) );
NAND2X2TS U1915 ( .A(n1188), .B(intDY_EWSW[25]), .Y(n1886) );
NAND2X2TS U1916 ( .A(n1187), .B(intDX_EWSW[4]), .Y(n2013) );
AOI22X2TS U1917 ( .A0(n2628), .A1(Raw_mant_NRM_SWR[19]), .B0(n1214), .B1(
n1678), .Y(n2709) );
NAND2X2TS U1918 ( .A(n1231), .B(n1303), .Y(n1922) );
NAND2X2TS U1919 ( .A(n1231), .B(n907), .Y(n1910) );
NAND2X2TS U1920 ( .A(n1201), .B(n2168), .Y(n1820) );
NAND2X2TS U1921 ( .A(n1201), .B(n1858), .Y(n1732) );
CLKINVX3TS U1922 ( .A(rst), .Y(n1206) );
CLKINVX3TS U1923 ( .A(n1215), .Y(n1209) );
NAND2X2TS U1924 ( .A(n1379), .B(n1183), .Y(n2039) );
NAND2X2TS U1925 ( .A(n1422), .B(n1176), .Y(n1988) );
NAND2X2TS U1926 ( .A(n1187), .B(n1181), .Y(n2033) );
NAND2X2TS U1927 ( .A(n1188), .B(n1185), .Y(n1982) );
INVX12TS U1928 ( .A(n1213), .Y(n1214) );
INVX3TS U1929 ( .A(n1215), .Y(n1216) );
INVX2TS U1930 ( .A(n1215), .Y(n1218) );
INVX2TS U1931 ( .A(rst), .Y(n1220) );
INVX2TS U1932 ( .A(rst), .Y(n1223) );
INVX8TS U1933 ( .A(n2660), .Y(n1227) );
MXI2X2TS U1934 ( .A(n2099), .B(final_result_ieee[29]), .S0(n2438), .Y(n2814)
);
MXI2X2TS U1935 ( .A(n2263), .B(final_result_ieee[26]), .S0(n2438), .Y(n2811)
);
MXI2X2TS U1936 ( .A(n2264), .B(final_result_ieee[27]), .S0(n2438), .Y(n2812)
);
AND2X8TS U1937 ( .A(n1532), .B(shift_value_SHT2_EWR[4]), .Y(n1657) );
AOI22X2TS U1938 ( .A0(n2173), .A1(n2118), .B0(n2192), .B1(n1201), .Y(n1729)
);
AOI22X2TS U1939 ( .A0(n2173), .A1(n1836), .B0(n1201), .B1(n1835), .Y(n1839)
);
AOI22X2TS U1940 ( .A0(n2173), .A1(n2059), .B0(n1201), .B1(n815), .Y(n1832)
);
INVX16TS U1941 ( .A(n1819), .Y(n2173) );
NAND2X8TS U1942 ( .A(n1665), .B(n2344), .Y(n1819) );
MXI2X2TS U1943 ( .A(n2117), .B(n2116), .S0(n923), .Y(n1824) );
MXI2X2TS U1944 ( .A(n2058), .B(n2057), .S0(left_right_SHT2), .Y(n2062) );
BUFX20TS U1945 ( .A(n981), .Y(n1231) );
NOR2X4TS U1946 ( .A(n1232), .B(n1240), .Y(n1433) );
NAND2X6TS U1947 ( .A(n2450), .B(n2449), .Y(n1234) );
NAND2X4TS U1948 ( .A(n2450), .B(n2449), .Y(n1235) );
NAND2X6TS U1949 ( .A(n2450), .B(n2449), .Y(n2205) );
MXI2X2TS U1950 ( .A(n2214), .B(n2213), .S0(n2201), .Y(n2100) );
MXI2X4TS U1951 ( .A(n2469), .B(n2468), .S0(n2467), .Y(n2201) );
NOR2X4TS U1952 ( .A(n1425), .B(n1236), .Y(n1279) );
NOR2X8TS U1953 ( .A(n1588), .B(n1237), .Y(n1354) );
MXI2X4TS U1954 ( .A(n2810), .B(n2377), .S0(n2630), .Y(n493) );
BUFX20TS U1955 ( .A(n1486), .Y(n1313) );
INVX16TS U1956 ( .A(n1239), .Y(n2164) );
BUFX6TS U1957 ( .A(n2156), .Y(n1240) );
OAI21X4TS U1958 ( .A0(n1289), .A1(n1580), .B0(n1579), .Y(n1242) );
NAND2X8TS U1959 ( .A(n1281), .B(n1280), .Y(n1243) );
BUFX6TS U1960 ( .A(n1417), .Y(n1244) );
NOR2BX4TS U1961 ( .AN(n1526), .B(n1245), .Y(n2788) );
OAI2BB1X4TS U1962 ( .A0N(n923), .A1N(n1680), .B0(n1246), .Y(n1245) );
NAND2BX4TS U1963 ( .AN(n1647), .B(n1248), .Y(n1742) );
NOR3X6TS U1964 ( .A(n1249), .B(n1259), .C(n1262), .Y(n1248) );
NAND4BX4TS U1965 ( .AN(n1630), .B(n1644), .C(n1643), .D(n1250), .Y(n1249) );
NOR2X8TS U1966 ( .A(n1258), .B(n1251), .Y(n1250) );
NAND3X8TS U1967 ( .A(n1635), .B(n1257), .C(n1252), .Y(n1251) );
AND2X8TS U1968 ( .A(n1638), .B(n1253), .Y(n1252) );
NOR3X6TS U1969 ( .A(n1256), .B(n1254), .C(n1255), .Y(n1253) );
XOR2X4TS U1970 ( .A(intDY_EWSW[30]), .B(intDX_EWSW[30]), .Y(n1255) );
XOR2X2TS U1971 ( .A(intDY_EWSW[3]), .B(n1186), .Y(n1256) );
NAND4BX4TS U1972 ( .AN(n1629), .B(n1263), .C(n1628), .D(n1633), .Y(n1262) );
NOR2BX4TS U1973 ( .AN(n1632), .B(n1264), .Y(n1263) );
AND2X8TS U1974 ( .A(n1646), .B(n1627), .Y(n1265) );
NAND3X4TS U1975 ( .A(n1426), .B(n1063), .C(n1268), .Y(n1425) );
NOR2X8TS U1976 ( .A(n1348), .B(n1349), .Y(n1268) );
NAND2X8TS U1977 ( .A(n1269), .B(n1068), .Y(n1275) );
AOI21X4TS U1978 ( .A0(n1360), .A1(n1357), .B0(n1356), .Y(n1270) );
AOI21X4TS U1979 ( .A0(n1274), .A1(n1276), .B0(n1273), .Y(n1272) );
OAI21X4TS U1980 ( .A0(n1571), .A1(n1570), .B0(n1569), .Y(n1273) );
NOR2X6TS U1981 ( .A(n1341), .B(n1340), .Y(n1339) );
OAI21X4TS U1982 ( .A0(n1337), .A1(n1056), .B0(n2226), .Y(n2128) );
NAND2X4TS U1983 ( .A(n1282), .B(n2035), .Y(n589) );
AND2X4TS U1984 ( .A(n2343), .B(n1186), .Y(n1356) );
NAND2X4TS U1985 ( .A(n2007), .B(n1284), .Y(n627) );
NAND2X2TS U1986 ( .A(n1187), .B(intDX_EWSW[26]), .Y(n1898) );
NAND2X2TS U1987 ( .A(n1187), .B(n1182), .Y(n1892) );
MXI2X4TS U1988 ( .A(n2782), .B(n2375), .S0(n2631), .Y(n539) );
BUFX6TS U1989 ( .A(intDX_EWSW[9]), .Y(n1288) );
NAND2X4TS U1990 ( .A(n2329), .B(intDX_EWSW[22]), .Y(n1587) );
OAI2BB1X4TS U1991 ( .A0N(n1072), .A1N(n1857), .B0(n2818), .Y(n2816) );
OAI21X4TS U1992 ( .A0(n1350), .A1(n1582), .B0(n1291), .Y(n1290) );
NOR2X4TS U1993 ( .A(n1797), .B(n1796), .Y(n2778) );
NAND4X4TS U1994 ( .A(n1536), .B(n1535), .C(n1534), .D(n1533), .Y(n1792) );
MXI2X4TS U1995 ( .A(n2466), .B(n2465), .S0(n2464), .Y(n2200) );
OAI21X4TS U1996 ( .A0(n2153), .A1(n2293), .B0(n1840), .Y(n1876) );
NOR2X4TS U1997 ( .A(n1163), .B(intDX_EWSW[26]), .Y(n1434) );
MXI2X4TS U1998 ( .A(n2776), .B(n2371), .S0(n2244), .Y(n529) );
NAND3X6TS U1999 ( .A(n2009), .B(n2010), .C(n2008), .Y(n611) );
NAND3X6TS U2000 ( .A(n2005), .B(n2006), .C(n2004), .Y(n623) );
BUFX20TS U2001 ( .A(n1004), .Y(n1379) );
NAND3X6TS U2002 ( .A(n1985), .B(n1984), .C(n1983), .Y(n595) );
NAND2X6TS U2003 ( .A(n2349), .B(intDX_EWSW[16]), .Y(n1350) );
BUFX6TS U2004 ( .A(intDX_EWSW[21]), .Y(n1293) );
NOR2X4TS U2005 ( .A(n992), .B(intDX_EWSW[12]), .Y(n1572) );
AND2X8TS U2006 ( .A(n1847), .B(n1846), .Y(n2798) );
AOI21X4TS U2007 ( .A0(n1748), .A1(n923), .B0(n1508), .Y(n2802) );
NAND4BX2TS U2008 ( .AN(n2511), .B(n2510), .C(n2509), .D(n2508), .Y(n2139) );
NAND2BX4TS U2009 ( .AN(n1514), .B(n1298), .Y(n2172) );
OAI2BB1X4TS U2010 ( .A0N(n2453), .A1N(n2452), .B0(n2542), .Y(n1299) );
NAND2BX4TS U2011 ( .AN(n2451), .B(n2541), .Y(n1300) );
XOR2X4TS U2012 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1738) );
NAND2X2TS U2013 ( .A(n1741), .B(n1740), .Y(n2097) );
AOI22X4TS U2014 ( .A0(n1375), .A1(n1876), .B0(n2164), .B1(
Raw_mant_NRM_SWR[7]), .Y(n2668) );
NAND4X8TS U2015 ( .A(n2538), .B(n1539), .C(n2537), .D(n2536), .Y(n815) );
NAND2X4TS U2016 ( .A(n2264), .B(n1855), .Y(n1856) );
BUFX12TS U2017 ( .A(n2276), .Y(n2244) );
OAI21X4TS U2018 ( .A0(n1766), .A1(n1765), .B0(n1764), .Y(n1767) );
OAI21X4TS U2019 ( .A0(n1782), .A1(n1781), .B0(n1780), .Y(n1302) );
MXI2X4TS U2020 ( .A(n2208), .B(n2207), .S0(DmP_mant_SFG_SWR[9]), .Y(n2081)
);
BUFX6TS U2021 ( .A(intDX_EWSW[19]), .Y(n1303) );
XOR2X4TS U2022 ( .A(n2350), .B(DmP_mant_SFG_SWR[24]), .Y(n1718) );
INVX4TS U2023 ( .A(n1658), .Y(n1802) );
AOI2BB2X4TS U2024 ( .B0(n2164), .B1(n1010), .A0N(n1038), .A1N(n2160), .Y(
n2686) );
OAI22X2TS U2025 ( .A0(n2148), .A1(n2380), .B0(n1799), .B1(n1903), .Y(n1800)
);
OR2X8TS U2026 ( .A(n1522), .B(n1521), .Y(n1842) );
BUFX16TS U2027 ( .A(n1334), .Y(n1305) );
OAI21X4TS U2028 ( .A0(n2751), .A1(n2161), .B0(n1787), .Y(n2687) );
AOI2BB2X4TS U2029 ( .B0(n1451), .B1(n1686), .A0N(n1035), .A1N(n1429), .Y(
n1476) );
BUFX20TS U2030 ( .A(n1037), .Y(n1310) );
OAI2BB1X4TS U2031 ( .A0N(n1308), .A1N(n1077), .B0(n1310), .Y(n2725) );
NAND2BX4TS U2032 ( .AN(n2146), .B(n1070), .Y(n1311) );
AOI2BB2X4TS U2033 ( .B0(n2147), .B1(n1310), .A0N(n1309), .A1N(n1001), .Y(
n2690) );
AOI2BB2X4TS U2034 ( .B0(n1877), .B1(n1310), .A0N(n1511), .A1N(n1510), .Y(
n2667) );
OAI22X4TS U2035 ( .A0(n2149), .A1(n2625), .B0(n2358), .B1(n1314), .Y(n2705)
);
OAI22X4TS U2036 ( .A0(n2149), .A1(n1161), .B0(n2353), .B1(n1314), .Y(n2665)
);
INVX16TS U2037 ( .A(n1315), .Y(n1324) );
OAI22X4TS U2038 ( .A0(n1672), .A1(n2382), .B0(n2149), .B1(n1454), .Y(n2731)
);
NAND2X8TS U2039 ( .A(n1474), .B(n2225), .Y(n1317) );
AND3X8TS U2040 ( .A(n1319), .B(n1318), .C(n1785), .Y(n1619) );
AND2X8TS U2041 ( .A(n1783), .B(n1784), .Y(n1319) );
AND2X8TS U2042 ( .A(n1301), .B(n1074), .Y(n1784) );
NAND2X8TS U2043 ( .A(n1320), .B(n1462), .Y(n1691) );
NOR2X8TS U2044 ( .A(n1322), .B(n1321), .Y(n1783) );
OA21X4TS U2045 ( .A0(n1618), .A1(n1166), .B0(n1686), .Y(n1321) );
NAND2BX4TS U2046 ( .AN(n1615), .B(n1614), .Y(n1785) );
AOI21X4TS U2047 ( .A0(n1331), .A1(n1012), .B0(n1326), .Y(n1579) );
NAND2X4TS U2048 ( .A(n990), .B(n907), .Y(n1328) );
OAI22X4TS U2049 ( .A0(n1672), .A1(n2383), .B0(n2149), .B1(n2293), .Y(n2672)
);
NAND3X4TS U2050 ( .A(n1683), .B(n1339), .C(n1338), .Y(n1337) );
NAND2X4TS U2051 ( .A(n1696), .B(n1301), .Y(n1340) );
AOI22X4TS U2052 ( .A0(n2150), .A1(n1214), .B0(n1232), .B1(n2168), .Y(n2732)
);
NAND2X8TS U2053 ( .A(n1413), .B(n1416), .Y(n1417) );
OAI22X4TS U2054 ( .A0(n1598), .A1(n1351), .B0(n1173), .B1(n1058), .Y(n1355)
);
NOR2X8TS U2055 ( .A(n1174), .B(intDX_EWSW[29]), .Y(n1598) );
OAI21X4TS U2056 ( .A0(n1587), .A1(n1588), .B0(n1586), .Y(n1352) );
OAI21X4TS U2057 ( .A0(n1584), .A1(n1585), .B0(n1583), .Y(n1353) );
NOR2X4TS U2058 ( .A(n2337), .B(n1185), .Y(n1358) );
NOR2X8TS U2059 ( .A(n1186), .B(n2343), .Y(n1361) );
BUFX20TS U2060 ( .A(n1383), .Y(n1359) );
CLKINVX12TS U2061 ( .A(n1362), .Y(n1488) );
NAND2X8TS U2062 ( .A(n1458), .B(n1461), .Y(n1362) );
AOI21X4TS U2063 ( .A0(n1008), .A1(Raw_mant_NRM_SWR[24]), .B0(n2131), .Y(
n2745) );
BUFX20TS U2064 ( .A(n1318), .Y(n1363) );
NOR2BX4TS U2065 ( .AN(n1363), .B(n2326), .Y(n1522) );
NOR2X8TS U2066 ( .A(n1171), .B(intDX_EWSW[9]), .Y(n1577) );
OAI21X4TS U2067 ( .A0(n1577), .A1(n1367), .B0(n1576), .Y(n1366) );
AOI21X4TS U2068 ( .A0(n1371), .A1(n1484), .B0(n1362), .Y(n1370) );
NAND2X8TS U2069 ( .A(n1384), .B(n1903), .Y(n1438) );
OAI21X4TS U2070 ( .A0(n2153), .A1(n2624), .B0(n1376), .Y(n2697) );
NOR2X8TS U2071 ( .A(n984), .B(n1003), .Y(n1485) );
NAND2X8TS U2072 ( .A(n1064), .B(n1450), .Y(n1378) );
OAI21X4TS U2073 ( .A0(n1380), .A1(n2360), .B0(n1719), .Y(n562) );
XOR2X4TS U2074 ( .A(n1382), .B(n1381), .Y(n1380) );
NAND2BX4TS U2075 ( .AN(n2385), .B(n1718), .Y(n1809) );
XNOR2X4TS U2076 ( .A(n2620), .B(DmP_mant_SFG_SWR[21]), .Y(n1559) );
XNOR2X4TS U2077 ( .A(n2620), .B(DmP_mant_SFG_SWR[20]), .Y(n1555) );
NOR2X8TS U2078 ( .A(n1555), .B(DMP_SFG[18]), .Y(n1709) );
NOR2X8TS U2079 ( .A(n2108), .B(n2101), .Y(n1710) );
NOR2X8TS U2080 ( .A(n1554), .B(DMP_SFG[17]), .Y(n2108) );
XOR2X4TS U2081 ( .A(n917), .B(DmP_mant_SFG_SWR[19]), .Y(n1554) );
AOI2BB2X4TS U2082 ( .B0(n2164), .B1(n925), .A0N(n1374), .A1N(n2161), .Y(
n2679) );
CLKINVX12TS U2083 ( .A(n1385), .Y(n1697) );
OAI21X4TS U2084 ( .A0(n2339), .A1(Raw_mant_NRM_SWR[1]), .B0(n2359), .Y(n1385) );
XNOR2X4TS U2085 ( .A(n1388), .B(n1386), .Y(n2263) );
OAI21X4TS U2086 ( .A0(n1757), .A1(n1763), .B0(n1765), .Y(n1388) );
OAI22X4TS U2087 ( .A0(n1672), .A1(n2355), .B0(n2149), .B1(n985), .Y(n2737)
);
NAND2X8TS U2088 ( .A(n2134), .B(n1391), .Y(n2149) );
NAND2X8TS U2089 ( .A(n1394), .B(n1392), .Y(n2817) );
NAND3X8TS U2090 ( .A(n1397), .B(n1396), .C(n1053), .Y(n1395) );
NOR2X8TS U2091 ( .A(n2275), .B(n2264), .Y(n1397) );
INVX12TS U2092 ( .A(n2760), .Y(n1798) );
NOR2X8TS U2093 ( .A(n2332), .B(intDX_EWSW[27]), .Y(n1592) );
NAND2X8TS U2094 ( .A(n1391), .B(n1433), .Y(n2148) );
NOR2X8TS U2095 ( .A(n2226), .B(Shift_amount_SHT1_EWR[1]), .Y(n1491) );
NAND2BX4TS U2096 ( .AN(n2144), .B(n2154), .Y(n2693) );
OAI21X4TS U2097 ( .A0(n1408), .A1(n2273), .B0(n1407), .Y(n564) );
NAND2X4TS U2098 ( .A(n1714), .B(n1715), .Y(n1409) );
NAND2X8TS U2099 ( .A(n1411), .B(n2254), .Y(n2259) );
XOR2X4TS U2100 ( .A(DmP_mant_SFG_SWR[15]), .B(n1551), .Y(n1412) );
NOR2X8TS U2101 ( .A(n1592), .B(n1434), .Y(n1593) );
NOR2X8TS U2102 ( .A(n1581), .B(n1591), .Y(n1420) );
INVX12TS U2103 ( .A(n2141), .Y(n2751) );
AND2X8TS U2104 ( .A(n2141), .B(n2142), .Y(n2765) );
NOR2X8TS U2105 ( .A(n1232), .B(n1391), .Y(n2141) );
NOR2X8TS U2106 ( .A(n2334), .B(intDX_EWSW[21]), .Y(n1585) );
AND2X8TS U2107 ( .A(n1427), .B(n1691), .Y(n1475) );
AOI21X4TS U2108 ( .A0(n1016), .A1(n1459), .B0(n1306), .Y(n1428) );
NOR2X8TS U2109 ( .A(n1473), .B(n1472), .Y(n1686) );
AND2X8TS U2110 ( .A(n1431), .B(n2624), .Y(n1452) );
OAI22X4TS U2111 ( .A0(n2144), .A1(n2143), .B0(n2751), .B1(n2163), .Y(n2680)
);
BUFX20TS U2112 ( .A(n981), .Y(n1435) );
NAND2X8TS U2113 ( .A(n1439), .B(n2659), .Y(n1510) );
OAI2BB1X4TS U2114 ( .A0N(Raw_mant_NRM_SWR[18]), .A1N(n1334), .B0(n1492), .Y(
n1493) );
OAI2BB1X4TS U2115 ( .A0N(Raw_mant_NRM_SWR[8]), .A1N(n1334), .B0(n1520), .Y(
n1521) );
OAI2BB1X4TS U2116 ( .A0N(Raw_mant_NRM_SWR[4]), .A1N(n2324), .B0(n1444), .Y(
n1443) );
NOR2X8TS U2117 ( .A(Raw_mant_NRM_SWR[6]), .B(n1010), .Y(n1444) );
OAI21X4TS U2118 ( .A0(n1452), .A1(n1020), .B0(n1167), .Y(n1451) );
NAND3X6TS U2119 ( .A(n1871), .B(n1870), .C(n1869), .Y(n2124) );
NAND2X2TS U2120 ( .A(n1231), .B(intDY_EWSW[0]), .Y(n1925) );
BUFX20TS U2121 ( .A(n982), .Y(n2027) );
NOR2X8TS U2122 ( .A(DMP_exp_NRM2_EW[1]), .B(n1749), .Y(n1762) );
NAND4BX4TS U2123 ( .AN(n2500), .B(n2499), .C(n2498), .D(n2497), .Y(n1875) );
NAND2X2TS U2124 ( .A(n2135), .B(n1214), .Y(n2699) );
BUFX20TS U2125 ( .A(n982), .Y(n2043) );
AOI21X4TS U2126 ( .A0(n1172), .A1(n1693), .B0(n1692), .Y(n1694) );
MX2X2TS U2127 ( .A(n1624), .B(n984), .S0(n2360), .Y(n566) );
MX2X2TS U2128 ( .A(n1563), .B(n1003), .S0(n2360), .Y(n565) );
NAND4BX4TS U2129 ( .AN(n1501), .B(n2612), .C(n2611), .D(n2610), .Y(n1836) );
OAI21X4TS U2130 ( .A0(n2459), .A1(n2458), .B0(n2457), .Y(n1501) );
AND2X6TS U2131 ( .A(n1750), .B(n1760), .Y(n1751) );
NAND2X4TS U2132 ( .A(n1861), .B(n1860), .Y(n1871) );
XNOR2X4TS U2133 ( .A(n1773), .B(DMP_exp_NRM2_EW[7]), .Y(n2104) );
NOR2X6TS U2134 ( .A(n2621), .B(DMP_exp_NRM2_EW[0]), .Y(n1761) );
BUFX20TS U2135 ( .A(n2629), .Y(n2226) );
BUFX20TS U2136 ( .A(n2629), .Y(n2225) );
MXI2X4TS U2137 ( .A(n2796), .B(n2426), .S0(n2631), .Y(n500) );
NAND2X2TS U2138 ( .A(n1447), .B(intDY_EWSW[27]), .Y(n1604) );
AOI21X4TS U2139 ( .A0(n1244), .A1(n1558), .B0(n1557), .Y(n1562) );
OAI21X4TS U2140 ( .A0(n1556), .A1(n1709), .B0(n1712), .Y(n1557) );
NAND2X2TS U2141 ( .A(n1363), .B(n1003), .Y(n1567) );
NAND4BX4TS U2142 ( .AN(n2495), .B(n2494), .C(n2493), .D(n2492), .Y(n1858) );
OR2X8TS U2143 ( .A(n1668), .B(shift_value_SHT2_EWR[4]), .Y(n1523) );
XNOR2X4TS U2144 ( .A(intDY_EWSW[24]), .B(intDX_EWSW[24]), .Y(n1646) );
NAND2X4TS U2145 ( .A(n2328), .B(intDX_EWSW[24]), .Y(n1590) );
NOR2X4TS U2146 ( .A(n2328), .B(intDX_EWSW[24]), .Y(n1581) );
NAND2X2TS U2147 ( .A(n1188), .B(intDX_EWSW[16]), .Y(n2022) );
NAND2X2TS U2148 ( .A(n1188), .B(n1238), .Y(n2003) );
XNOR2X4TS U2149 ( .A(n926), .B(intDX_EWSW[22]), .Y(n1637) );
NAND2X2TS U2150 ( .A(n2338), .B(n1158), .Y(n1571) );
NAND2X4TS U2151 ( .A(n1171), .B(intDX_EWSW[9]), .Y(n1576) );
XNOR2X4TS U2152 ( .A(intDY_EWSW[5]), .B(intDX_EWSW[5]), .Y(n1649) );
NAND4BX4TS U2153 ( .AN(n2570), .B(n2569), .C(n2568), .D(n2567), .Y(n1658) );
XNOR2X4TS U2154 ( .A(n1190), .B(intDX_EWSW[1]), .Y(n1625) );
OAI21X4TS U2155 ( .A0(n1591), .A1(n1590), .B0(n1589), .Y(n1594) );
NOR2X8TS U2156 ( .A(n1677), .B(Raw_mant_NRM_SWR[3]), .Y(n1861) );
XNOR2X4TS U2157 ( .A(intDY_EWSW[16]), .B(intDX_EWSW[16]), .Y(n1648) );
OAI21X2TS U2158 ( .A0(n2162), .A1(n2751), .B0(n1807), .Y(n2755) );
BUFX20TS U2159 ( .A(n1619), .Y(n2628) );
NOR2X4TS U2160 ( .A(n1553), .B(DMP_SFG[16]), .Y(n2101) );
NAND2X4TS U2161 ( .A(n1495), .B(n1494), .Y(n1497) );
OR2X8TS U2162 ( .A(n1677), .B(n1676), .Y(n1683) );
NAND4X4TS U2163 ( .A(n2489), .B(n2488), .C(n2487), .D(n2486), .Y(n2192) );
NAND2X8TS U2164 ( .A(n1439), .B(Shift_amount_SHT1_EWR[0]), .Y(n2156) );
NOR2X4TS U2165 ( .A(n1304), .B(n1166), .Y(n1862) );
NAND2X8TS U2166 ( .A(n1753), .B(n1752), .Y(n1754) );
OR2X8TS U2167 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2226), .Y(n1455) );
BUFX3TS U2168 ( .A(n1204), .Y(n2649) );
BUFX3TS U2169 ( .A(n1221), .Y(n2653) );
AND2X2TS U2170 ( .A(n1789), .B(n1247), .Y(n1460) );
NAND2X1TS U2171 ( .A(n2173), .B(n1835), .Y(n1504) );
INVX2TS U2172 ( .A(SIGN_FLAG_SHT1SHT2), .Y(n1857) );
BUFX3TS U2173 ( .A(n2064), .Y(n2647) );
NOR2X2TS U2179 ( .A(n1160), .B(n1454), .Y(n1464) );
NOR2X4TS U2180 ( .A(n1160), .B(Raw_mant_NRM_SWR[16]), .Y(n1483) );
NAND2X2TS U2181 ( .A(n1483), .B(n1000), .Y(n1484) );
INVX4TS U2182 ( .A(n1491), .Y(n1490) );
AOI22X1TS U2183 ( .A0(n2152), .A1(DmP_mant_SHT1_SW[6]), .B0(n2142), .B1(
DmP_mant_SHT1_SW[5]), .Y(n1492) );
NAND2BX4TS U2184 ( .AN(n1497), .B(n1496), .Y(n1564) );
AOI22X4TS U2185 ( .A0(n967), .A1(n2473), .B0(n2472), .B1(n969), .Y(n1498) );
NOR2X6TS U2186 ( .A(n1193), .B(n1874), .Y(n1665) );
OR3X6TS U2187 ( .A(n1874), .B(n1194), .C(shift_value_SHT2_EWR[4]), .Y(n1500)
);
NAND2X1TS U2188 ( .A(n1201), .B(n2189), .Y(n1503) );
NAND2X1TS U2189 ( .A(n1837), .B(n1836), .Y(n1502) );
NAND4X4TS U2190 ( .A(n1505), .B(n1504), .C(n1503), .D(n1502), .Y(n1748) );
NAND2X4TS U2191 ( .A(n1664), .B(n2191), .Y(n1506) );
OAI21X4TS U2192 ( .A0(n1668), .A1(n1034), .B0(n1506), .Y(n1744) );
NAND2X8TS U2193 ( .A(n1851), .B(Shift_reg_FLAGS_7[3]), .Y(n2276) );
MXI2X4TS U2194 ( .A(n2802), .B(n2420), .S0(n2630), .Y(n497) );
NAND2X2TS U2195 ( .A(n1363), .B(Raw_mant_NRM_SWR[8]), .Y(n1509) );
NAND3X4TS U2196 ( .A(n2581), .B(n2580), .C(n2579), .Y(n1663) );
INVX2TS U2197 ( .A(n1663), .Y(n1511) );
OAI21X1TS U2198 ( .A0(n2456), .A1(n2455), .B0(n2454), .Y(n1513) );
INVX2TS U2199 ( .A(n2174), .Y(n2727) );
NAND2X1TS U2200 ( .A(n1201), .B(n1663), .Y(n1516) );
NAND2X1TS U2201 ( .A(n2481), .B(n2480), .Y(n1514) );
AOI21X4TS U2202 ( .A0(n1247), .A1(n2054), .B0(n1519), .Y(n2770) );
BUFX12TS U2203 ( .A(n2276), .Y(n2241) );
MXI2X4TS U2204 ( .A(n2770), .B(n2370), .S0(n2241), .Y(n541) );
NAND2X2TS U2205 ( .A(n2173), .B(n1658), .Y(n1524) );
NAND2X2TS U2206 ( .A(n2173), .B(n2191), .Y(n1525) );
MXI2X4TS U2207 ( .A(n2788), .B(n2366), .S0(n2241), .Y(n537) );
NOR2X4TS U2208 ( .A(n1668), .B(n1802), .Y(n1530) );
INVX2TS U2209 ( .A(n2053), .Y(n1788) );
NAND2X1TS U2210 ( .A(n1657), .B(n1033), .Y(n1536) );
NAND2X2TS U2211 ( .A(n1229), .B(n1663), .Y(n1535) );
NAND2X1TS U2212 ( .A(n2171), .B(n2191), .Y(n1534) );
NAND2X4TS U2213 ( .A(n1122), .B(n812), .Y(n1533) );
NAND2X2TS U2214 ( .A(n1792), .B(n923), .Y(n1537) );
AOI22X4TS U2215 ( .A0(n967), .A1(n2476), .B0(n2475), .B1(n2474), .Y(n1539)
);
NAND2X1TS U2216 ( .A(n1657), .B(n1858), .Y(n1543) );
NAND2X1TS U2217 ( .A(n2171), .B(n1848), .Y(n1541) );
NAND2X1TS U2218 ( .A(n1122), .B(n2059), .Y(n1540) );
NAND4X4TS U2219 ( .A(n1540), .B(n1542), .C(n1541), .D(n1543), .Y(n1844) );
INVX2TS U2220 ( .A(n1668), .Y(n1544) );
NAND2X4TS U2221 ( .A(n1664), .B(n1875), .Y(n1545) );
INVX2TS U2222 ( .A(n1845), .Y(n1546) );
XNOR2X4TS U2223 ( .A(n1551), .B(DmP_mant_SFG_SWR[14]), .Y(n2217) );
XOR2X4TS U2224 ( .A(n1551), .B(DmP_mant_SFG_SWR[18]), .Y(n1553) );
INVX2TS U2225 ( .A(n1710), .Y(n1552) );
OAI21X4TS U2226 ( .A0(n2108), .A1(n2105), .B0(n2109), .Y(n1715) );
INVX2TS U2227 ( .A(n1715), .Y(n1556) );
INVX2TS U2228 ( .A(n1713), .Y(n1560) );
NAND2X1TS U2229 ( .A(n1560), .B(n1711), .Y(n1561) );
XOR2X4TS U2230 ( .A(n1562), .B(n1561), .Y(n1563) );
NOR2X8TS U2231 ( .A(n2346), .B(intDX_EWSW[25]), .Y(n1591) );
NAND2X2TS U2232 ( .A(n2334), .B(intDX_EWSW[21]), .Y(n1583) );
NAND2X2TS U2233 ( .A(n2333), .B(n1182), .Y(n1586) );
INVX12TS U2234 ( .A(Shift_reg_FLAGS_7_6), .Y(n2023) );
BUFX20TS U2235 ( .A(n2023), .Y(n2098) );
BUFX20TS U2236 ( .A(n965), .Y(n2048) );
NAND2X2TS U2237 ( .A(n2034), .B(DMP_EXP_EWSW[27]), .Y(n1602) );
NAND2X1TS U2238 ( .A(n1657), .B(n2168), .Y(n1610) );
NAND2X2TS U2239 ( .A(n2173), .B(n2192), .Y(n1609) );
NAND2X2TS U2240 ( .A(n1201), .B(n1875), .Y(n1608) );
NAND2X2TS U2241 ( .A(n1706), .B(n923), .Y(n1613) );
AND2X4TS U2242 ( .A(n1613), .B(n1612), .Y(n2800) );
MXI2X4TS U2243 ( .A(n2800), .B(n2424), .S0(n2630), .Y(n498) );
NOR3X1TS U2244 ( .A(n2626), .B(n1020), .C(n925), .Y(n1618) );
INVX2TS U2245 ( .A(n1709), .Y(n1621) );
NAND2X1TS U2246 ( .A(n1621), .B(n1712), .Y(n1622) );
XOR2X4TS U2247 ( .A(n1623), .B(n1622), .Y(n1624) );
XNOR2X1TS U2248 ( .A(intDY_EWSW[25]), .B(intDX_EWSW[25]), .Y(n1628) );
XNOR2X4TS U2249 ( .A(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1627) );
XOR2X1TS U2250 ( .A(n1173), .B(intDX_EWSW[29]), .Y(n1630) );
XOR2X1TS U2251 ( .A(n1162), .B(intDX_EWSW[26]), .Y(n1629) );
XNOR2X1TS U2252 ( .A(intDY_EWSW[18]), .B(n1176), .Y(n1633) );
XNOR2X1TS U2253 ( .A(intDY_EWSW[20]), .B(intDX_EWSW[20]), .Y(n1631) );
XNOR2X1TS U2254 ( .A(n1005), .B(intDX_EWSW[10]), .Y(n1636) );
XNOR2X1TS U2255 ( .A(n991), .B(intDX_EWSW[12]), .Y(n1642) );
XNOR2X1TS U2256 ( .A(intDY_EWSW[11]), .B(n1181), .Y(n1641) );
NAND4X1TS U2257 ( .A(n1642), .B(n1641), .C(n1640), .D(n1639), .Y(n1647) );
XNOR2X1TS U2258 ( .A(n908), .B(n1183), .Y(n1645) );
XNOR2X1TS U2259 ( .A(intDY_EWSW[2]), .B(n1185), .Y(n1644) );
XNOR2X1TS U2260 ( .A(intDY_EWSW[4]), .B(intDX_EWSW[4]), .Y(n1643) );
XNOR2X1TS U2261 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n1652) );
INVX2TS U2262 ( .A(n1738), .Y(n1653) );
NOR2X4TS U2263 ( .A(n1653), .B(n2379), .Y(n1737) );
MXI2X1TS U2264 ( .A(n1737), .B(SIGN_FLAG_EXP), .S0(n2411), .Y(n1654) );
NAND2X2TS U2265 ( .A(n2173), .B(n2189), .Y(n1661) );
NAND2X2TS U2266 ( .A(n1201), .B(n1658), .Y(n1660) );
INVX2TS U2267 ( .A(n1836), .Y(n1801) );
NAND2X1TS U2268 ( .A(n1665), .B(n1033), .Y(n1666) );
OAI22X2TS U2269 ( .A0(n1794), .A1(n1801), .B0(n2170), .B1(n1793), .Y(n1671)
);
NOR2X4TS U2270 ( .A(n1460), .B(n1671), .Y(n2780) );
MXI2X4TS U2271 ( .A(n2780), .B(n2372), .S0(n2244), .Y(n533) );
NOR3X1TS U2272 ( .A(n2324), .B(Raw_mant_NRM_SWR[7]), .C(n1010), .Y(n1673) );
INVX2TS U2273 ( .A(n1675), .Y(n1676) );
OAI2BB1X4TS U2274 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1439), .B0(n2128),
.Y(n558) );
NOR2X1TS U2275 ( .A(n1240), .B(n2355), .Y(n1678) );
AND2X4TS U2276 ( .A(n1682), .B(n1681), .Y(n2786) );
MXI2X4TS U2277 ( .A(n2786), .B(n2368), .S0(n2241), .Y(n531) );
NOR2X1TS U2278 ( .A(n1020), .B(Raw_mant_NRM_SWR[11]), .Y(n1687) );
INVX2TS U2279 ( .A(n1869), .Y(n1689) );
INVX2TS U2280 ( .A(n1697), .Y(n1698) );
NOR2X1TS U2281 ( .A(n2352), .B(n2226), .Y(n1704) );
MXI2X1TS U2282 ( .A(n1704), .B(n1193), .S0(n1233), .Y(n1705) );
OAI2BB2X2TS U2283 ( .B0(n1794), .B1(n1707), .A0N(n1743), .A1N(n1830), .Y(
n1708) );
NOR2X4TS U2284 ( .A(n918), .B(n1708), .Y(n2774) );
BUFX12TS U2285 ( .A(n2276), .Y(n2631) );
MXI2X4TS U2286 ( .A(n2774), .B(n2374), .S0(n2631), .Y(n544) );
MXI2X4TS U2287 ( .A(n966), .B(n2471), .S0(n2470), .Y(n2183) );
XOR2X4TS U2288 ( .A(n2183), .B(n2350), .Y(n1716) );
XOR2X4TS U2289 ( .A(n2350), .B(DmP_mant_SFG_SWR[23]), .Y(n1717) );
NOR2X4TS U2290 ( .A(n1717), .B(DMP_SFG[21]), .Y(n1722) );
NOR2X4TS U2291 ( .A(n1720), .B(n1722), .Y(n1808) );
OR2X2TS U2292 ( .A(n1718), .B(DMP_SFG[22]), .Y(n1811) );
INVX2TS U2293 ( .A(n1720), .Y(n2180) );
INVX2TS U2294 ( .A(n2179), .Y(n1721) );
AOI21X4TS U2295 ( .A0(n2182), .A1(n2180), .B0(n1721), .Y(n1726) );
INVX2TS U2296 ( .A(n1722), .Y(n1724) );
XOR2X4TS U2297 ( .A(n1726), .B(n1725), .Y(n1728) );
MXI2X4TS U2298 ( .A(n2767), .B(n2369), .S0(n2241), .Y(n549) );
INVX2TS U2299 ( .A(n2168), .Y(n1731) );
OAI21X4TS U2300 ( .A0(n1819), .A1(n1731), .B0(n1730), .Y(n2058) );
NAND2X2TS U2301 ( .A(n1229), .B(n1848), .Y(n1734) );
AOI22X1TS U2302 ( .A0(n2185), .A1(n2059), .B0(n2060), .B1(n2192), .Y(n1735)
);
MXI2X4TS U2303 ( .A(n2784), .B(n2365), .S0(n2241), .Y(n527) );
INVX2TS U2304 ( .A(n1737), .Y(n1741) );
NOR2X1TS U2305 ( .A(n1738), .B(intDX_EWSW[31]), .Y(n1739) );
INVX2TS U2306 ( .A(n805), .Y(n1746) );
AOI21X4TS U2307 ( .A0(n1748), .A1(n1247), .B0(n1747), .Y(n2772) );
MXI2X4TS U2308 ( .A(n2772), .B(n2367), .S0(n2241), .Y(n535) );
NOR2X6TS U2309 ( .A(DMP_exp_NRM2_EW[2]), .B(n995), .Y(n1763) );
XNOR2X4TS U2310 ( .A(n1761), .B(n1751), .Y(n2195) );
XNOR2X2TS U2311 ( .A(DMP_exp_NRM2_EW[0]), .B(n2621), .Y(n2193) );
INVX2TS U2312 ( .A(n1763), .Y(n1755) );
NAND2X4TS U2313 ( .A(n1755), .B(n1765), .Y(n1756) );
OAI21X4TS U2314 ( .A0(n1762), .A1(n1761), .B0(n1760), .Y(n1769) );
NOR2X4TS U2315 ( .A(n2327), .B(DMP_exp_NRM2_EW[3]), .Y(n1766) );
AOI21X4TS U2316 ( .A0(n1769), .A1(n1768), .B0(n1767), .Y(n1770) );
NAND2X4TS U2317 ( .A(n1457), .B(DMP_exp_NRM2_EW[4]), .Y(n1778) );
INVX2TS U2318 ( .A(n1852), .Y(n1772) );
OAI21X4TS U2319 ( .A0(n1782), .A1(n1781), .B0(n1772), .Y(n1773) );
INVX2TS U2320 ( .A(n1781), .Y(n1775) );
XOR2X4TS U2321 ( .A(n1782), .B(n1776), .Y(n2264) );
OAI21X4TS U2322 ( .A0(n1782), .A1(n1781), .B0(n1778), .Y(n1777) );
INVX2TS U2323 ( .A(n1778), .Y(n1779) );
NAND2X2TS U2324 ( .A(n2164), .B(Raw_mant_NRM_SWR[0]), .Y(n2754) );
NAND2X2TS U2325 ( .A(n1789), .B(n923), .Y(n1790) );
AND2X4TS U2326 ( .A(n1791), .B(n1790), .Y(n2794) );
MXI2X4TS U2327 ( .A(n2794), .B(n2427), .S0(n2631), .Y(n501) );
INVX2TS U2328 ( .A(n2172), .Y(n1795) );
OAI22X2TS U2329 ( .A0(n1795), .A1(n1794), .B0(n1834), .B1(n1793), .Y(n1796)
);
INVX2TS U2330 ( .A(n2059), .Y(n1799) );
AOI21X2TS U2331 ( .A0(n2129), .A1(Raw_mant_NRM_SWR[11]), .B0(n1800), .Y(
n2678) );
AOI22X1TS U2332 ( .A0(n2152), .A1(DmP_mant_SHT1_SW[9]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1804) );
OAI21X4TS U2333 ( .A0(n2153), .A1(n1167), .B0(n1804), .Y(n2135) );
NOR2X2TS U2334 ( .A(n964), .B(n1453), .Y(n2065) );
XOR2X1TS U2335 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n1805) );
INVX2TS U2336 ( .A(Shift_amount_SHT1_EWR[4]), .Y(n2125) );
MXI2X4TS U2337 ( .A(n1806), .B(n2125), .S0(n2221), .Y(n791) );
INVX2TS U2338 ( .A(n1809), .Y(n1810) );
AO21X4TS U2339 ( .A0(n1812), .A1(n1811), .B0(n1810), .Y(n1813) );
AOI21X4TS U2340 ( .A0(n2182), .A1(n1456), .B0(n1813), .Y(n1815) );
XNOR2X1TS U2341 ( .A(n2350), .B(n2200), .Y(n1814) );
XOR2X4TS U2342 ( .A(n1815), .B(n1814), .Y(n1817) );
OAI21X4TS U2343 ( .A0(n1817), .A1(n2219), .B0(n1816), .Y(n561) );
OAI21X4TS U2344 ( .A0(n1819), .A1(n2157), .B0(n1818), .Y(n2117) );
NAND2X2TS U2345 ( .A(n1229), .B(n1875), .Y(n1822) );
INVX2TS U2346 ( .A(n1825), .Y(n1827) );
NAND2X1TS U2347 ( .A(n2151), .B(DmP_mant_SHT1_SW[6]), .Y(n1828) );
OAI2BB1X4TS U2348 ( .A0N(n994), .A1N(n1439), .B0(n1829), .Y(n555) );
NAND3X4TS U2349 ( .A(n1833), .B(n1831), .C(n1832), .Y(n2169) );
AOI22X4TS U2350 ( .A0(n2169), .A1(n1247), .B0(n2168), .B1(n2060), .Y(n2769)
);
MXI2X4TS U2351 ( .A(n2769), .B(n2373), .S0(n2244), .Y(n546) );
NAND2BX4TS U2352 ( .AN(n1374), .B(n1842), .Y(n2676) );
NAND2BX4TS U2353 ( .AN(n1374), .B(n1843), .Y(n2726) );
NAND2X4TS U2354 ( .A(n1844), .B(n923), .Y(n1847) );
MXI2X4TS U2355 ( .A(n2798), .B(n2425), .S0(n2631), .Y(n499) );
INVX2TS U2356 ( .A(n1848), .Y(n1849) );
AOI21X2TS U2357 ( .A0(n2129), .A1(Raw_mant_NRM_SWR[3]), .B0(n1850), .Y(n2742) );
NOR2X1TS U2358 ( .A(n1852), .B(DMP_exp_NRM2_EW[7]), .Y(n1854) );
MXI2X4TS U2359 ( .A(n2808), .B(n2378), .S0(n2630), .Y(n494) );
NOR3X1TS U2360 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[4]), .C(n2323),
.Y(n1860) );
AOI21X1TS U2361 ( .A0(n1863), .A1(n1862), .B0(Raw_mant_NRM_SWR[18]), .Y(
n1865) );
NOR2X4TS U2362 ( .A(n1868), .B(n1867), .Y(n1870) );
INVX2TS U2363 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2078) );
MXI2X4TS U2364 ( .A(n2124), .B(n1872), .S0(n1439), .Y(n1873) );
NAND2X2TS U2365 ( .A(n2034), .B(n964), .Y(n1878) );
NAND2X2TS U2366 ( .A(n2034), .B(DMP_EXP_EWSW[26]), .Y(n1881) );
NAND2X1TS U2367 ( .A(n2034), .B(n962), .Y(n1884) );
NAND2X1TS U2368 ( .A(n2034), .B(DMP_EXP_EWSW[23]), .Y(n1887) );
NAND2X2TS U2369 ( .A(n2027), .B(intDY_EWSW[23]), .Y(n1891) );
NAND2X2TS U2370 ( .A(n2044), .B(DmP_EXP_EWSW[23]), .Y(n1890) );
NAND3X2TS U2371 ( .A(n1891), .B(n1892), .C(n1890), .Y(n593) );
NAND2X2TS U2372 ( .A(n2044), .B(DmP_EXP_EWSW[25]), .Y(n1893) );
NAND2X2TS U2373 ( .A(n2027), .B(n1162), .Y(n1897) );
NAND3X2TS U2374 ( .A(n1897), .B(n1898), .C(n1896), .Y(n590) );
AOI21X1TS U2375 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n2292), .B0(n1210), .Y(
n1902) );
NAND2X2TS U2376 ( .A(n1231), .B(intDX_EWSW[16]), .Y(n1905) );
NAND2X2TS U2377 ( .A(n2411), .B(DMP_EXP_EWSW[16]), .Y(n1904) );
NAND2X2TS U2378 ( .A(n1231), .B(intDX_EWSW[20]), .Y(n1907) );
NAND3X2TS U2379 ( .A(n1907), .B(n1908), .C(n1906), .Y(n762) );
NAND3X2TS U2380 ( .A(n1910), .B(n1911), .C(n1909), .Y(n768) );
NAND3X2TS U2381 ( .A(n1914), .B(n1913), .C(n1912), .Y(n764) );
NAND2X1TS U2382 ( .A(n1188), .B(n908), .Y(n1917) );
NAND2X2TS U2383 ( .A(n1435), .B(n1183), .Y(n1916) );
NAND3X2TS U2384 ( .A(n1917), .B(n1916), .C(n1915), .Y(n767) );
NAND2X2TS U2385 ( .A(n2411), .B(DMP_EXP_EWSW[17]), .Y(n1918) );
NAND2X2TS U2386 ( .A(n1187), .B(intDX_EWSW[0]), .Y(n1926) );
NAND2X1TS U2387 ( .A(n2098), .B(DmP_EXP_EWSW[0]), .Y(n1924) );
NAND3X2TS U2388 ( .A(n1925), .B(n1926), .C(n1924), .Y(n639) );
NAND2X2TS U2389 ( .A(n1231), .B(intDX_EWSW[30]), .Y(n1928) );
NAND2X2TS U2390 ( .A(n1106), .B(intDX_EWSW[0]), .Y(n1931) );
NAND3X2TS U2391 ( .A(n1931), .B(n1932), .C(n1930), .Y(n782) );
NAND2X2TS U2392 ( .A(n2043), .B(intDX_EWSW[29]), .Y(n1934) );
NAND3X2TS U2393 ( .A(n1934), .B(n1935), .C(n1933), .Y(n753) );
NAND2X2TS U2394 ( .A(n2027), .B(intDX_EWSW[28]), .Y(n1937) );
NAND3X2TS U2395 ( .A(n1938), .B(n1937), .C(n1936), .Y(n754) );
NAND2X2TS U2396 ( .A(n2043), .B(intDX_EWSW[1]), .Y(n1940) );
NAND2X2TS U2397 ( .A(n1435), .B(intDX_EWSW[10]), .Y(n1943) );
NAND2X2TS U2398 ( .A(n1106), .B(n1238), .Y(n1948) );
NAND2X1TS U2399 ( .A(n2044), .B(DMP_EXP_EWSW[4]), .Y(n1950) );
NAND2X1TS U2400 ( .A(n2044), .B(DMP_EXP_EWSW[8]), .Y(n1953) );
NAND2X2TS U2401 ( .A(n1231), .B(intDX_EWSW[12]), .Y(n1957) );
NAND2X2TS U2402 ( .A(n1435), .B(n1185), .Y(n1958) );
NAND2X1TS U2403 ( .A(n1447), .B(intDY_EWSW[11]), .Y(n1961) );
NAND2X2TS U2404 ( .A(n2048), .B(n1181), .Y(n1960) );
NAND3X2TS U2405 ( .A(n1961), .B(n1960), .C(n1959), .Y(n771) );
NAND2X2TS U2406 ( .A(n1231), .B(n1288), .Y(n1966) );
NAND3X2TS U2407 ( .A(n1966), .B(n1967), .C(n1965), .Y(n773) );
NAND2X2TS U2408 ( .A(n2043), .B(n1186), .Y(n1969) );
NAND3X2TS U2409 ( .A(n1969), .B(n1970), .C(n1968), .Y(n779) );
NAND2X2TS U2410 ( .A(n2043), .B(intDX_EWSW[13]), .Y(n1972) );
NAND2X2TS U2411 ( .A(n2044), .B(DMP_EXP_EWSW[13]), .Y(n1971) );
NAND3X2TS U2412 ( .A(n1972), .B(n1973), .C(n1971), .Y(n769) );
NAND2X1TS U2413 ( .A(n1422), .B(n926), .Y(n1976) );
NAND2X2TS U2414 ( .A(n1106), .B(intDX_EWSW[22]), .Y(n1975) );
NAND3X2TS U2415 ( .A(n1976), .B(n1975), .C(n1974), .Y(n760) );
NAND2X2TS U2416 ( .A(n1106), .B(n1293), .Y(n1978) );
NAND2X2TS U2417 ( .A(n2027), .B(intDY_EWSW[2]), .Y(n1981) );
NAND3X2TS U2418 ( .A(n1981), .B(n1982), .C(n1980), .Y(n635) );
NAND2X2TS U2419 ( .A(n2027), .B(intDY_EWSW[18]), .Y(n1987) );
NAND3X2TS U2420 ( .A(n1987), .B(n1988), .C(n1986), .Y(n603) );
NAND2X2TS U2421 ( .A(n2048), .B(n991), .Y(n1990) );
NAND3X2TS U2422 ( .A(n1991), .B(n1990), .C(n1989), .Y(n615) );
NAND2X1TS U2423 ( .A(n1447), .B(intDX_EWSW[10]), .Y(n1997) );
NAND2X2TS U2424 ( .A(n1106), .B(n1005), .Y(n1996) );
NAND3X2TS U2425 ( .A(n1997), .B(n1996), .C(n1995), .Y(n619) );
NAND2X1TS U2426 ( .A(n1188), .B(n1186), .Y(n2000) );
NAND2X2TS U2427 ( .A(n1106), .B(intDY_EWSW[3]), .Y(n1999) );
NAND3X2TS U2428 ( .A(n2000), .B(n1999), .C(n1998), .Y(n633) );
NAND2X2TS U2429 ( .A(n2043), .B(intDY_EWSW[5]), .Y(n2002) );
NAND3X2TS U2430 ( .A(n2002), .B(n2003), .C(n2001), .Y(n629) );
NAND2X2TS U2431 ( .A(n1106), .B(intDY_EWSW[6]), .Y(n2007) );
NAND2X2TS U2432 ( .A(n2036), .B(DmP_EXP_EWSW[14]), .Y(n2008) );
NAND2X2TS U2433 ( .A(n1106), .B(intDY_EWSW[4]), .Y(n2012) );
NAND2X1TS U2434 ( .A(n1188), .B(intDX_EWSW[20]), .Y(n2019) );
NAND2X2TS U2435 ( .A(n2043), .B(intDY_EWSW[20]), .Y(n2018) );
NAND3X2TS U2436 ( .A(n2019), .B(n2018), .C(n2017), .Y(n599) );
NAND2X2TS U2437 ( .A(n1106), .B(intDY_EWSW[16]), .Y(n2021) );
NAND2X2TS U2438 ( .A(n2023), .B(DmP_EXP_EWSW[19]), .Y(n2024) );
NAND2X2TS U2439 ( .A(n1231), .B(n999), .Y(n2029) );
NAND2X2TS U2440 ( .A(n1231), .B(intDY_EWSW[11]), .Y(n2032) );
NAND3X2TS U2441 ( .A(n2032), .B(n2033), .C(n2031), .Y(n617) );
NAND2X2TS U2442 ( .A(n2027), .B(intDY_EWSW[27]), .Y(n2035) );
NAND2X2TS U2443 ( .A(n1106), .B(n908), .Y(n2038) );
NAND2X2TS U2444 ( .A(n2027), .B(n1027), .Y(n2041) );
NAND3X2TS U2445 ( .A(n2041), .B(n2042), .C(n2040), .Y(n605) );
NAND2X2TS U2446 ( .A(n2043), .B(intDY_EWSW[21]), .Y(n2046) );
NAND3X2TS U2447 ( .A(n2046), .B(n2047), .C(n2045), .Y(n597) );
NAND2X2TS U2448 ( .A(n1435), .B(n997), .Y(n2050) );
AOI22X1TS U2449 ( .A0(n2152), .A1(DmP_mant_SHT1_SW[13]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[12]), .Y(n2051) );
AOI2BB2X4TS U2450 ( .B0(n2765), .B1(DmP_mant_SHT1_SW[20]), .A0N(n1038),
.A1N(n2055), .Y(n2733) );
NOR2X1TS U2451 ( .A(n921), .B(overflow_flag), .Y(n2056) );
MXI2X4TS U2452 ( .A(n2778), .B(n2376), .S0(n2631), .Y(n554) );
MXI2X4TS U2453 ( .A(n2790), .B(n2422), .S0(n2631), .Y(n560) );
CLKBUFX3TS U2454 ( .A(n1208), .Y(n2063) );
CLKBUFX3TS U2455 ( .A(n2063), .Y(n2441) );
CLKBUFX3TS U2456 ( .A(n2063), .Y(n2443) );
CLKBUFX3TS U2457 ( .A(n2063), .Y(n2440) );
CLKBUFX3TS U2458 ( .A(n1223), .Y(n2064) );
BUFX3TS U2459 ( .A(n2447), .Y(n2657) );
BUFX3TS U2460 ( .A(n1204), .Y(n2655) );
BUFX3TS U2461 ( .A(n2447), .Y(n2654) );
BUFX3TS U2462 ( .A(n1219), .Y(n2652) );
BUFX3TS U2463 ( .A(n2063), .Y(n2635) );
BUFX3TS U2464 ( .A(n1225), .Y(n2642) );
BUFX3TS U2465 ( .A(n1209), .Y(n2656) );
BUFX3TS U2466 ( .A(n1224), .Y(n2644) );
BUFX3TS U2467 ( .A(n1223), .Y(n2645) );
BUFX3TS U2468 ( .A(n2063), .Y(n2646) );
CLKBUFX3TS U2469 ( .A(n2063), .Y(n2439) );
CLKBUFX3TS U2470 ( .A(n2658), .Y(n2640) );
CLKBUFX3TS U2471 ( .A(n2658), .Y(n2638) );
BUFX3TS U2472 ( .A(n1225), .Y(n2651) );
OAI21X1TS U2473 ( .A0(n2238), .A1(n1230), .B0(n1439), .Y(n858) );
INVX2TS U2474 ( .A(n2065), .Y(n2066) );
NAND2X1TS U2475 ( .A(n2067), .B(n2066), .Y(n2068) );
XNOR2X1TS U2476 ( .A(n2068), .B(n2166), .Y(n2069) );
MXI2X1TS U2477 ( .A(n2069), .B(n2421), .S0(n2221), .Y(n794) );
NAND2X2TS U2478 ( .A(n2142), .B(DmP_mant_SHT1_SW[13]), .Y(n2160) );
XNOR2X1TS U2479 ( .A(n962), .B(DmP_EXP_EWSW[25]), .Y(n2070) );
XNOR2X1TS U2480 ( .A(n2071), .B(n2070), .Y(n2072) );
MXI2X1TS U2481 ( .A(n2072), .B(n2352), .S0(n2221), .Y(n793) );
CLKMX2X2TS U2482 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n921), .Y(n581) );
BUFX4TS U2483 ( .A(n2223), .Y(n2093) );
MXI2X1TS U2484 ( .A(n1010), .B(DMP_SFG[8]), .S0(n2093), .Y(n2074) );
INVX8TS U2485 ( .A(n1051), .Y(n2214) );
OR2X4TS U2486 ( .A(n2273), .B(n2350), .Y(n2080) );
MXI2X1TS U2487 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[10]), .Y(n2073)
);
MXI2X2TS U2488 ( .A(n2079), .B(n2078), .S0(n2221), .Y(n792) );
MXI2X1TS U2489 ( .A(n2618), .B(DMP_SFG[7]), .S0(n2223), .Y(n2082) );
NAND2X2TS U2490 ( .A(n2082), .B(n2081), .Y(n532) );
MXI2X1TS U2491 ( .A(Raw_mant_NRM_SWR[8]), .B(DMP_SFG[6]), .S0(n2093), .Y(
n2084) );
NAND2X2TS U2492 ( .A(n2084), .B(n2083), .Y(n553) );
MXI2X1TS U2493 ( .A(Raw_mant_NRM_SWR[4]), .B(DMP_SFG[2]), .S0(n2223), .Y(
n2086) );
MXI2X1TS U2494 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[4]), .Y(n2085)
);
NAND2X1TS U2495 ( .A(n2086), .B(n2085), .Y(n540) );
MXI2X1TS U2496 ( .A(Raw_mant_NRM_SWR[3]), .B(DMP_SFG[1]), .S0(n2093), .Y(
n2088) );
MXI2X1TS U2497 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[3]), .Y(n2087)
);
NAND2X1TS U2498 ( .A(n2088), .B(n2087), .Y(n545) );
MXI2X1TS U2499 ( .A(Raw_mant_NRM_SWR[2]), .B(DMP_SFG[0]), .S0(n2093), .Y(
n2090) );
MXI2X1TS U2500 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[2]), .Y(n2089)
);
MXI2X1TS U2501 ( .A(n925), .B(DMP_SFG[10]), .S0(n2093), .Y(n2092) );
MXI2X1TS U2502 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[12]), .Y(n2091)
);
MXI2X1TS U2503 ( .A(Raw_mant_NRM_SWR[7]), .B(DMP_SFG[5]), .S0(n2093), .Y(
n2095) );
MXI2X1TS U2504 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[7]), .Y(n2094)
);
NAND2X1TS U2505 ( .A(n2095), .B(n2094), .Y(n528) );
MXI2X2TS U2506 ( .A(n2364), .B(n2096), .S0(n2237), .Y(n578) );
OAI2BB1X1TS U2507 ( .A0N(OP_FLAG_EXP), .A1N(n2098), .B0(n2097), .Y(n751) );
NAND2X2TS U2508 ( .A(n973), .B(n2554), .Y(final_result_ieee[29]) );
OAI21X1TS U2509 ( .A0(n2229), .A1(n2339), .B0(n2100), .Y(n550) );
INVX2TS U2510 ( .A(n2101), .Y(n2107) );
NAND2X1TS U2511 ( .A(n2107), .B(n2105), .Y(n2102) );
XNOR2X1TS U2512 ( .A(n1244), .B(n2102), .Y(n2103) );
INVX2TS U2513 ( .A(n2105), .Y(n2106) );
AOI21X4TS U2514 ( .A0(n1244), .A1(n2107), .B0(n2106), .Y(n2112) );
INVX2TS U2515 ( .A(n2108), .Y(n2110) );
NAND2X1TS U2516 ( .A(n2110), .B(n2109), .Y(n2111) );
XOR2X4TS U2517 ( .A(n2112), .B(n2111), .Y(n2113) );
MXI2X1TS U2518 ( .A(Raw_mant_NRM_SWR[6]), .B(DMP_SFG[4]), .S0(n2223), .Y(
n2115) );
MXI2X1TS U2519 ( .A(n2208), .B(n2207), .S0(DmP_mant_SFG_SWR[6]), .Y(n2114)
);
NAND2X1TS U2520 ( .A(n2115), .B(n2114), .Y(n543) );
MXI2X1TS U2521 ( .A(n2123), .B(n2623), .S0(n1439), .Y(n552) );
NOR2X1TS U2522 ( .A(n2660), .B(n2125), .Y(n2126) );
NAND2X2TS U2523 ( .A(n2129), .B(n1304), .Y(n2662) );
NAND2X2TS U2524 ( .A(n2129), .B(n984), .Y(n2702) );
NAND2X2TS U2525 ( .A(n2129), .B(n1000), .Y(n2728) );
NAND2X2TS U2526 ( .A(n2129), .B(Raw_mant_NRM_SWR[5]), .Y(n2669) );
NAND2X1TS U2527 ( .A(n2592), .B(n2591), .Y(n2175) );
INVX2TS U2528 ( .A(n2175), .Y(n2130) );
AOI22X1TS U2529 ( .A0(n1210), .A1(DmP_mant_SHT1_SW[19]), .B0(n2151), .B1(
DmP_mant_SHT1_SW[18]), .Y(n2132) );
NAND2X1TS U2530 ( .A(n2152), .B(DmP_mant_SHT1_SW[10]), .Y(n2143) );
NAND2X2TS U2531 ( .A(n2164), .B(n1000), .Y(n2722) );
NAND2X2TS U2532 ( .A(n2164), .B(Raw_mant_NRM_SWR[5]), .Y(n2757) );
NOR2X1TS U2533 ( .A(n1240), .B(n2354), .Y(n2159) );
NOR2X1TS U2534 ( .A(n2417), .B(DmP_EXP_EWSW[23]), .Y(n2165) );
NOR2X1TS U2535 ( .A(n2166), .B(n2165), .Y(n2167) );
MXI2X1TS U2536 ( .A(n2431), .B(n2167), .S0(n2239), .Y(n795) );
INVX2TS U2537 ( .A(n2183), .Y(n2748) );
NAND2X2TS U2538 ( .A(n2628), .B(Raw_mant_NRM_SWR[1]), .Y(n2752) );
MXI2X1TS U2539 ( .A(n2193), .B(final_result_ieee[23]), .S0(n1851), .Y(n2194)
);
MXI2X1TS U2540 ( .A(n2197), .B(final_result_ieee[25]), .S0(n1851), .Y(n2198)
);
CLKBUFX3TS U2541 ( .A(n2636), .Y(n2444) );
CLKBUFX3TS U2542 ( .A(n2634), .Y(n2448) );
CLKBUFX3TS U2543 ( .A(n2648), .Y(n2445) );
CLKBUFX3TS U2544 ( .A(n2650), .Y(n2447) );
BUFX3TS U2545 ( .A(n2636), .Y(n2446) );
INVX2TS U2546 ( .A(n2200), .Y(n2746) );
INVX2TS U2547 ( .A(n2234), .Y(n2224) );
NOR2X1TS U2548 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2202) );
NAND2X2TS U2549 ( .A(n2202), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n2203) );
MXI2X1TS U2550 ( .A(beg_OP), .B(n2414), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2204) );
OAI21X1TS U2551 ( .A0(n2204), .A1(n2234), .B0(n2203), .Y(n899) );
OAI22X1TS U2552 ( .A0(n2205), .A1(n2530), .B0(n974), .B1(n2529), .Y(
final_result_ieee[22]) );
INVX2TS U2553 ( .A(final_result_ieee[22]), .Y(n2809) );
INVX2TS U2554 ( .A(final_result_ieee[3]), .Y(n2771) );
OAI22X1TS U2555 ( .A0(n2205), .A1(n2507), .B0(n974), .B1(n2506), .Y(
final_result_ieee[14]) );
INVX2TS U2556 ( .A(final_result_ieee[14]), .Y(n2793) );
INVX2TS U2557 ( .A(final_result_ieee[12]), .Y(n2789) );
INVX2TS U2558 ( .A(final_result_ieee[5]), .Y(n2775) );
INVX2TS U2559 ( .A(final_result_ieee[20]), .Y(n2805) );
INVX2TS U2560 ( .A(final_result_ieee[15]), .Y(n2795) );
INVX2TS U2561 ( .A(final_result_ieee[10]), .Y(n2785) );
OAI22X1TS U2562 ( .A0(n1234), .A1(n2540), .B0(n974), .B1(n2539), .Y(
final_result_ieee[18]) );
INVX2TS U2563 ( .A(final_result_ieee[18]), .Y(n2801) );
INVX2TS U2564 ( .A(final_result_ieee[0]), .Y(n2619) );
INVX2TS U2565 ( .A(final_result_ieee[8]), .Y(n2781) );
INVX2TS U2566 ( .A(final_result_ieee[9]), .Y(n2783) );
OAI22X1TS U2567 ( .A0(n1234), .A1(n2532), .B0(n974), .B1(n2531), .Y(
final_result_ieee[17]) );
INVX2TS U2568 ( .A(final_result_ieee[17]), .Y(n2799) );
INVX2TS U2569 ( .A(final_result_ieee[13]), .Y(n2791) );
INVX2TS U2570 ( .A(final_result_ieee[6]), .Y(n2777) );
INVX2TS U2571 ( .A(final_result_ieee[11]), .Y(n2787) );
OAI22X1TS U2572 ( .A0(n1234), .A1(n2528), .B0(n974), .B1(n2527), .Y(
final_result_ieee[16]) );
INVX2TS U2573 ( .A(final_result_ieee[16]), .Y(n2797) );
INVX2TS U2574 ( .A(final_result_ieee[1]), .Y(n2768) );
INVX2TS U2575 ( .A(final_result_ieee[4]), .Y(n2773) );
OAI22X1TS U2576 ( .A0(n1235), .A1(n2534), .B0(n974), .B1(n2533), .Y(
final_result_ieee[21]) );
INVX2TS U2577 ( .A(final_result_ieee[21]), .Y(n2807) );
INVX2TS U2578 ( .A(final_result_ieee[7]), .Y(n2779) );
OAI22X1TS U2579 ( .A0(n1235), .A1(n2556), .B0(n974), .B1(n2555), .Y(
final_result_ieee[19]) );
INVX2TS U2580 ( .A(final_result_ieee[19]), .Y(n2803) );
MXI2X1TS U2581 ( .A(n2208), .B(n2207), .S0(DmP_mant_SFG_SWR[1]), .Y(n2206)
);
OAI21X1TS U2582 ( .A0(n2229), .A1(n2323), .B0(n2206), .Y(n556) );
MXI2X1TS U2583 ( .A(Raw_mant_NRM_SWR[5]), .B(DMP_SFG[3]), .S0(n2223), .Y(
n2210) );
MXI2X1TS U2584 ( .A(n2208), .B(n2207), .S0(DmP_mant_SFG_SWR[5]), .Y(n2209)
);
MXI2X1TS U2585 ( .A(n1020), .B(DMP_SFG[11]), .S0(n2229), .Y(n2212) );
MXI2X1TS U2586 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[13]), .Y(n2211)
);
MXI2X1TS U2587 ( .A(Raw_mant_NRM_SWR[11]), .B(DMP_SFG[9]), .S0(n2229), .Y(
n2216) );
MXI2X1TS U2588 ( .A(n2214), .B(n2213), .S0(DmP_mant_SFG_SWR[11]), .Y(n2215)
);
INVX2TS U2589 ( .A(n578), .Y(n2543) );
NAND2X2TS U2590 ( .A(n2628), .B(n984), .Y(n2724) );
NAND2X2TS U2591 ( .A(n2628), .B(n2618), .Y(n2674) );
NAND2X2TS U2592 ( .A(n973), .B(n2496), .Y(final_result_ieee[26]) );
NAND2X2TS U2593 ( .A(n973), .B(n2505), .Y(final_result_ieee[27]) );
INVX2TS U2594 ( .A(n2217), .Y(n2218) );
NOR2X1TS U2595 ( .A(n2218), .B(DMP_SFG[12]), .Y(n2220) );
MXI2X1TS U2596 ( .A(n2220), .B(n1167), .S0(n2219), .Y(n559) );
CLKMX2X2TS U2597 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2226),
.Y(n573) );
CLKMX2X2TS U2598 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n2222),
.Y(n736) );
CLKMX2X2TS U2599 ( .A(DMP_SHT1_EWSW[1]), .B(n1022), .S0(n2222), .Y(n745) );
CLKMX2X2TS U2600 ( .A(DMP_SHT1_EWSW[7]), .B(DMP_EXP_EWSW[7]), .S0(n2222),
.Y(n727) );
CLKMX2X2TS U2601 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n2222),
.Y(n712) );
CLKMX2X2TS U2602 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n2222),
.Y(n709) );
CLKMX2X2TS U2603 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n2222),
.Y(n733) );
CLKMX2X2TS U2604 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2226),
.Y(n640) );
CLKMX2X2TS U2605 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2225),
.Y(n582) );
CLKMX2X2TS U2606 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n2222), .Y(n596) );
CLKMX2X2TS U2607 ( .A(DmP_mant_SHT1_SW[17]), .B(DmP_EXP_EWSW[17]), .S0(n2222), .Y(n604) );
CLKMX2X2TS U2608 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n2222), .Y(n606) );
CLKMX2X2TS U2609 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[29]), .S0(n2223), .Y(
n646) );
CLKMX2X2TS U2610 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[28]), .S0(n2223), .Y(
n651) );
CLKMX2X2TS U2611 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n2223), .Y(n574) );
CLKMX2X2TS U2612 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[30]), .S0(n2223), .Y(
n641) );
CLKMX2X2TS U2613 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n2238),
.Y(n643) );
CLKMX2X2TS U2614 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n2238),
.Y(n702) );
CLKMX2X2TS U2615 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2238),
.Y(n705) );
CLKMX2X2TS U2616 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n2238),
.Y(n693) );
CLKMX2X2TS U2617 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n2238),
.Y(n696) );
CLKMX2X2TS U2618 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n2238), .Y(
n585) );
CLKMX2X2TS U2619 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n2238),
.Y(n699) );
MXI2X1TS U2620 ( .A(n2224), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
CLKMX2X2TS U2621 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2225),
.Y(n655) );
CLKMX2X2TS U2622 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n2225),
.Y(n675) );
CLKMX2X2TS U2623 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2226),
.Y(n665) );
CLKMX2X2TS U2624 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2226),
.Y(n650) );
CLKMX2X2TS U2625 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2225),
.Y(n660) );
CLKMX2X2TS U2626 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2225),
.Y(n645) );
CLKMX2X2TS U2627 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2226),
.Y(n670) );
INVX8TS U2628 ( .A(n2418), .Y(n2227) );
CLKMX2X2TS U2629 ( .A(DMP_SHT1_EWSW[2]), .B(DMP_EXP_EWSW[2]), .S0(n2227),
.Y(n742) );
CLKMX2X2TS U2630 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n2227),
.Y(n748) );
CLKMX2X2TS U2631 ( .A(DMP_SHT1_EWSW[22]), .B(n1023), .S0(n2228), .Y(n682) );
CLKMX2X2TS U2632 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n2228),
.Y(n688) );
CLKMX2X2TS U2633 ( .A(DMP_SHT1_EWSW[21]), .B(DMP_EXP_EWSW[21]), .S0(n2228),
.Y(n685) );
CLKMX2X2TS U2634 ( .A(DMP_SHT1_EWSW[19]), .B(DMP_EXP_EWSW[19]), .S0(n2239),
.Y(n691) );
CLKMX2X2TS U2635 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n2239), .Y(
n577) );
CLKMX2X2TS U2636 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n2227), .Y(
n586) );
CLKMX2X2TS U2637 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n2228), .Y(n594) );
CLKMX2X2TS U2638 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n2228),
.Y(n634) );
CLKMX2X2TS U2639 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n2228), .Y(n600) );
CLKMX2X2TS U2640 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n2228),
.Y(n636) );
CLKMX2X2TS U2641 ( .A(DmP_mant_SHT1_SW[5]), .B(DmP_EXP_EWSW[5]), .S0(n2227),
.Y(n628) );
CLKMX2X2TS U2642 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n2227),
.Y(n626) );
CLKMX2X2TS U2643 ( .A(DmP_mant_SHT1_SW[8]), .B(DmP_EXP_EWSW[8]), .S0(n2227),
.Y(n622) );
CLKMX2X2TS U2644 ( .A(DmP_mant_SHT1_SW[12]), .B(n1018), .S0(n2228), .Y(n614)
);
CLKMX2X2TS U2645 ( .A(DmP_mant_SHT1_SW[7]), .B(DmP_EXP_EWSW[7]), .S0(n2227),
.Y(n624) );
CLKMX2X2TS U2646 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n2228), .Y(n612) );
CLKMX2X2TS U2647 ( .A(DmP_mant_SHT1_SW[4]), .B(DmP_EXP_EWSW[4]), .S0(n2227),
.Y(n630) );
CLKMX2X2TS U2648 ( .A(DmP_mant_SHT1_SW[9]), .B(DmP_EXP_EWSW[9]), .S0(n2227),
.Y(n620) );
CLKMX2X2TS U2649 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n2228),
.Y(n638) );
CLKMX2X2TS U2650 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n2239),
.Y(n644) );
CLKMX2X2TS U2651 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n2239),
.Y(n694) );
CLKMX2X2TS U2652 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n2239),
.Y(n697) );
CLKMX2X2TS U2653 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n2239),
.Y(n706) );
CLKMX2X2TS U2654 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n2239),
.Y(n700) );
CLKMX2X2TS U2655 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n2229), .Y(n583) );
CLKMX2X2TS U2656 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[24]), .S0(n2229), .Y(
n671) );
CLKMX2X2TS U2657 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[23]), .S0(n2229), .Y(
n676) );
CLKMX2X2TS U2658 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[26]), .S0(n2229), .Y(
n661) );
CLKMX2X2TS U2659 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[25]), .S0(n2229), .Y(
n666) );
CLKMX2X2TS U2660 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[27]), .S0(n2229), .Y(
n656) );
CLKMX2X2TS U2661 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n2230),
.Y(n679) );
CLKMX2X2TS U2662 ( .A(DMP_SHT1_EWSW[24]), .B(n964), .S0(n2230), .Y(n674) );
CLKMX2X2TS U2663 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(n2230),
.Y(n659) );
CLKMX2X2TS U2664 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n2230),
.Y(n664) );
CLKMX2X2TS U2665 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2230), .Y(n580)
);
CLKMX2X2TS U2666 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n2230),
.Y(n649) );
CLKMX2X2TS U2667 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n2230),
.Y(n730) );
CLKMX2X2TS U2668 ( .A(DMP_SHT1_EWSW[28]), .B(n1153), .S0(n2230), .Y(n654) );
INVX8TS U2669 ( .A(n2418), .Y(n2231) );
CLKMX2X2TS U2670 ( .A(DMP_SHT1_EWSW[11]), .B(n1168), .S0(n2231), .Y(n715) );
CLKMX2X2TS U2671 ( .A(DMP_SHT1_EWSW[9]), .B(DMP_EXP_EWSW[9]), .S0(n2231),
.Y(n721) );
CLKMX2X2TS U2672 ( .A(DMP_SHT1_EWSW[10]), .B(n983), .S0(n2231), .Y(n718) );
CLKMX2X2TS U2673 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n2231),
.Y(n739) );
CLKMX2X2TS U2674 ( .A(DmP_mant_SHT1_SW[14]), .B(DmP_EXP_EWSW[14]), .S0(n2231), .Y(n610) );
CLKMX2X2TS U2675 ( .A(DmP_mant_SHT1_SW[11]), .B(DmP_EXP_EWSW[11]), .S0(n2231), .Y(n616) );
CLKMX2X2TS U2676 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n2231), .Y(n608) );
CLKMX2X2TS U2677 ( .A(DmP_mant_SHT1_SW[18]), .B(DmP_EXP_EWSW[18]), .S0(n2231), .Y(n602) );
CLKMX2X2TS U2678 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n920),
.Y(n720) );
CLKMX2X2TS U2679 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n920),
.Y(n714) );
CLKMX2X2TS U2680 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n1227),
.Y(n717) );
CLKMX2X2TS U2681 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n920), .Y(
n576) );
CLKMX2X2TS U2682 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n920),
.Y(n684) );
CLKMX2X2TS U2683 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n920),
.Y(n687) );
CLKMX2X2TS U2684 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(busy),
.Y(n690) );
CLKMX2X2TS U2685 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n1227),
.Y(n747) );
CLKMX2X2TS U2686 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(busy),
.Y(n681) );
CLKMX2X2TS U2687 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n1227),
.Y(n738) );
CLKMX2X2TS U2688 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(busy),
.Y(n653) );
CLKMX2X2TS U2689 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n1227),
.Y(n658) );
CLKMX2X2TS U2690 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(busy),
.Y(n663) );
CLKMX2X2TS U2691 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n1227),
.Y(n673) );
CLKMX2X2TS U2692 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(busy),
.Y(n648) );
CLKMX2X2TS U2693 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n1227),
.Y(n678) );
CLKMX2X2TS U2694 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(busy), .Y(n579)
);
CLKMX2X2TS U2695 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(busy),
.Y(n741) );
CLKMX2X2TS U2696 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n1227),
.Y(n729) );
CLKMX2X2TS U2697 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(busy),
.Y(n732) );
MXI2X1TS U2698 ( .A(n2292), .B(n1851), .S0(n2235), .Y(n892) );
MXI2X1TS U2699 ( .A(n2273), .B(n1439), .S0(n2235), .Y(n893) );
MXI2X1TS U2700 ( .A(n2411), .B(n2418), .S0(n2235), .Y(n897) );
MXI2X1TS U2701 ( .A(n2356), .B(n2273), .S0(n2235), .Y(n894) );
MXI2X1TS U2702 ( .A(n2659), .B(n2356), .S0(n2235), .Y(n895) );
MXI2X4TS U2703 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n2234), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n2245) );
CLKINVX1TS U2704 ( .A(n2245), .Y(n2236) );
MXI2X1TS U2705 ( .A(n2236), .B(n2411), .S0(n2235), .Y(n898) );
CLKMX2X2TS U2706 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n1227),
.Y(n711) );
CLKMX2X2TS U2707 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(busy),
.Y(n744) );
CLKMX2X2TS U2708 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(n1227),
.Y(n735) );
CLKMX2X2TS U2709 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(n1227),
.Y(n708) );
CLKMX2X2TS U2710 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n920),
.Y(n726) );
MXI2X1TS U2711 ( .A(n2296), .B(n2392), .S0(n2237), .Y(n657) );
MXI2X1TS U2712 ( .A(n2300), .B(n2388), .S0(n2237), .Y(n728) );
MXI2X1TS U2713 ( .A(n2294), .B(n2390), .S0(n2237), .Y(n647) );
MXI2X1TS U2714 ( .A(n2297), .B(n2393), .S0(n2237), .Y(n662) );
MXI2X1TS U2715 ( .A(n2298), .B(n2395), .S0(n2237), .Y(n672) );
MXI2X1TS U2716 ( .A(n2295), .B(n2391), .S0(n2237), .Y(n652) );
MXI2X1TS U2717 ( .A(n2430), .B(n2308), .S0(n2237), .Y(n642) );
MXI2X1TS U2718 ( .A(n2299), .B(n2396), .S0(n2237), .Y(n677) );
MXI2X1TS U2719 ( .A(n2322), .B(n2394), .S0(n2237), .Y(n667) );
MXI2X1TS U2720 ( .A(n2322), .B(n2240), .S0(n2238), .Y(n668) );
MXI2X1TS U2721 ( .A(n2286), .B(n2385), .S0(n2244), .Y(n680) );
MXI2X1TS U2722 ( .A(n2240), .B(n963), .S0(n2239), .Y(n669) );
MXI2X1TS U2723 ( .A(n2302), .B(n2397), .S0(n2241), .Y(n713) );
MXI2X1TS U2724 ( .A(n2303), .B(n2398), .S0(n2241), .Y(n719) );
MXI2X1TS U2725 ( .A(n2301), .B(n2389), .S0(n2241), .Y(n737) );
INVX2TS U2726 ( .A(SIGN_FLAG_SFG), .Y(n2242) );
MXI2X1TS U2727 ( .A(n2288), .B(n2242), .S0(n2631), .Y(n575) );
MXI2X1TS U2728 ( .A(n2437), .B(n2309), .S0(n2631), .Y(n584) );
MXI2X1TS U2729 ( .A(n2287), .B(n2387), .S0(n2244), .Y(n683) );
INVX2TS U2730 ( .A(DMP_SFG[20]), .Y(n2243) );
MXI2X1TS U2731 ( .A(n2304), .B(n2243), .S0(n2244), .Y(n686) );
MXI2X1TS U2732 ( .A(n2432), .B(n2307), .S0(n2244), .Y(n692) );
MXI2X1TS U2733 ( .A(n2433), .B(n2306), .S0(n2244), .Y(n695) );
MXI2X1TS U2734 ( .A(n2305), .B(n2399), .S0(n2244), .Y(n689) );
MXI2X1TS U2735 ( .A(n2434), .B(n2310), .S0(n2630), .Y(n698) );
MXI2X1TS U2736 ( .A(n2436), .B(n2311), .S0(n2630), .Y(n704) );
MXI2X1TS U2737 ( .A(n2435), .B(n2312), .S0(n2630), .Y(n701) );
NAND2X8TS U2738 ( .A(n2245), .B(beg_OP), .Y(n2250) );
CLKMX2X2TS U2739 ( .A(Data_Y[31]), .B(intDY_EWSW[31]), .S0(n2246), .Y(n826)
);
CLKMX2X2TS U2740 ( .A(add_subt), .B(intAS), .S0(n2246), .Y(n859) );
CLKMX2X2TS U2741 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n2246), .Y(n860)
);
CLKMX2X2TS U2742 ( .A(Data_Y[1]), .B(n1190), .S0(n2246), .Y(n856) );
BUFX12TS U2743 ( .A(n2250), .Y(n2247) );
BUFX12TS U2744 ( .A(n2250), .Y(n2249) );
CLKMX2X2TS U2745 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n2248), .Y(n862)
);
CLKMX2X2TS U2746 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n2248), .Y(n827)
);
CLKMX2X2TS U2747 ( .A(Data_Y[29]), .B(n1173), .S0(n2251), .Y(n828) );
CLKMX2X2TS U2748 ( .A(Data_Y[28]), .B(intDY_EWSW[28]), .S0(n2251), .Y(n829)
);
CLKMX2X2TS U2749 ( .A(Data_Y[27]), .B(intDY_EWSW[27]), .S0(n2251), .Y(n830)
);
CLKMX2X2TS U2750 ( .A(Data_X[23]), .B(n1182), .S0(n2248), .Y(n868) );
CLKMX2X2TS U2751 ( .A(Data_X[20]), .B(intDX_EWSW[20]), .S0(n2253), .Y(n871)
);
CLKMX2X2TS U2752 ( .A(Data_Y[26]), .B(n1162), .S0(n2251), .Y(n831) );
CLKMX2X2TS U2753 ( .A(Data_Y[25]), .B(intDY_EWSW[25]), .S0(n2251), .Y(n832)
);
CLKMX2X2TS U2754 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n2248), .Y(n861)
);
CLKMX2X2TS U2755 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n2251), .Y(n833)
);
CLKMX2X2TS U2756 ( .A(Data_Y[23]), .B(intDY_EWSW[23]), .S0(n2251), .Y(n834)
);
CLKMX2X2TS U2757 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n2248), .Y(n863)
);
CLKMX2X2TS U2758 ( .A(Data_X[21]), .B(n1293), .S0(n2253), .Y(n870) );
CLKMX2X2TS U2759 ( .A(Data_X[3]), .B(n1186), .S0(n2252), .Y(n888) );
CLKMX2X2TS U2760 ( .A(Data_X[15]), .B(n1183), .S0(n2253), .Y(n876) );
CLKMX2X2TS U2761 ( .A(Data_X[18]), .B(n1176), .S0(n2253), .Y(n873) );
CLKMX2X2TS U2762 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n2251), .Y(n891) );
CLKMX2X2TS U2763 ( .A(Data_X[2]), .B(n1185), .S0(n2252), .Y(n889) );
CLKMX2X2TS U2764 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n2252), .Y(n887) );
CLKMX2X2TS U2765 ( .A(Data_X[11]), .B(n1181), .S0(n2252), .Y(n880) );
CLKMX2X2TS U2766 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n2253), .Y(n879)
);
CLKMX2X2TS U2767 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n2252), .Y(n881)
);
NAND2X1TS U2768 ( .A(n2255), .B(n2254), .Y(n2257) );
XNOR2X1TS U2769 ( .A(n2257), .B(n2256), .Y(n2258) );
CLKMX2X2TS U2770 ( .A(n2258), .B(n1000), .S0(n2360), .Y(n571) );
INVX2TS U2771 ( .A(n2260), .Y(n2267) );
NAND2X1TS U2772 ( .A(n2267), .B(n2265), .Y(n2261) );
XNOR2X1TS U2773 ( .A(n2259), .B(n2261), .Y(n2262) );
INVX2TS U2774 ( .A(n2265), .Y(n2266) );
INVX2TS U2775 ( .A(n2268), .Y(n2270) );
NAND2X1TS U2776 ( .A(n2270), .B(n2269), .Y(n2271) );
XOR2X1TS U2777 ( .A(n2272), .B(n2271), .Y(n2274) );
MXI2X1TS U2778 ( .A(n2275), .B(final_result_ieee[28]), .S0(n2438), .Y(n2813)
);
MXI2X1TS U2779 ( .A(n2313), .B(n2402), .S0(n2277), .Y(n722) );
MXI2X1TS U2780 ( .A(n2401), .B(n2290), .S0(n2277), .Y(n710) );
MXI2X1TS U2781 ( .A(n2314), .B(n2403), .S0(n2277), .Y(n734) );
MXI2X1TS U2782 ( .A(n2316), .B(n2404), .S0(n2277), .Y(n743) );
MXI2X1TS U2783 ( .A(n2317), .B(n2405), .S0(n2277), .Y(n725) );
MXI2X1TS U2784 ( .A(n2318), .B(n2408), .S0(n2277), .Y(n731) );
MXI2X1TS U2785 ( .A(n2319), .B(n2406), .S0(n2277), .Y(n740) );
MXI2X1TS U2786 ( .A(n2320), .B(n2409), .S0(n2277), .Y(n746) );
MXI2X1TS U2787 ( .A(n2321), .B(n2410), .S0(n2277), .Y(n716) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_LOA_syn.sdf");
endmodule
|
/*
* Dot Runner
* CSCB58 Winter 2017 Final Project
* Team members:
* Changyu Bi
* Jiachen He
*/
module project(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B,
LEDR
);
input CLOCK_50;
input [9:0] SW;
input [3:0] KEY;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output [9:0] LEDR;
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire resetn = KEY[0];
//wire writeEn = ~KEY[1];
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(1),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
// wire [319:0] new_array = 320'b00000000001000000000010000000001000000000010000000000000000010000000000000000001000000000000000100000000001100000000000000000100000000000000000100000000000000010000000000010000000000001000000000000000010000000000000000110000000000000000100000000000000000010000000000001100000000000011000000000000000001000000000000000011;
wire [27:0] rate = 28'b0000001011011100011011000000;
// wire [159:0] floor = 120'b0;
wire [159:0] draw;
wire start, move;
control c(
.clk(CLOCK_50),
.go(~KEY[2]),
.stop(~KEY[1]),
.start(start),
.resetn(resetn),
.move(move)
);
// key 3 used as jump button
datapath d(
.clk(CLOCK_50),
.start(start),
.move(move),
.jump(~KEY[3]),
.rate(rate),
.resetn(resetn),
.draw(draw),
.LEDR(LEDR[9:0])
);
display d0(
.floor(draw),
.clk(CLOCK_50),
.resetn(resetn),
.x(x),
.y(y),
.colour(colour)
);
endmodule
module control(
input clk,
input go,
input stop,
input resetn,
output reg start,
output reg move
);
reg [5:0] cur, next;
localparam S_READY = 5'd0,
S_READY_WAIT = 5'd1,
S_MOVE = 5'd2,
S_STOP = 5'd3;
always@(*)
begin: state_table
case (cur)
S_READY: next = go ? S_READY_WAIT : S_READY;
S_READY_WAIT: next = S_MOVE;
S_MOVE: next = stop ? S_STOP : S_MOVE;
S_STOP: next = S_READY;
default: next = S_READY;
endcase
end
always @(*)
begin: enable_signals
start = 1'b0;
move = 1'b0;
case (cur)
S_READY: begin
start = 1'b1;
end
S_MOVE: begin
move = 1'b1;
end
default: begin
end
endcase
end
always@(posedge clk)
begin: state_FFs
if (!resetn)
cur <= S_READY;
else
cur <= next;
end
endmodule
module datapath (
input clk,
input start,
input move,
input jump,
input [27:0] rate,
input resetn,
output reg [159:0] draw,
output [9:0] LEDR
);
//1011011100011011000000
reg [27:0] count;
// reg [159:0] out;
reg [319:0] obstacles;
// the height control
reg [1:0] height = 2'b00;
// press jump will only allow the runner to jump once
reg jumpOnce = 1'b0;
// going up or down, add or subtract height by 1
reg going_up = 1'b1;
always@(posedge clk) begin
if (!resetn) begin
count <= rate;
height <= 2'b00;
going_up <= 1'b1;
jumpOnce <= 1'b0;
end
else if (start) begin
count <= rate;
height <= 2'b00;
draw <= 160'b0;
obstacles[319:0] <= 320'b00000000000000000100000000000100000000001000000000000000001000000000000000000100000000000000010000000000110000000000000000010000000000000000010000000000000001000000000001000000000000100000000000000001000000000000000011000000000000000010000000000000000001000000000000110000000000001100000000000000000100000000000000001100;
going_up <= 1'b1;
end
else begin
if (count == 28'b0) begin
count <= rate;
draw = draw << 2;
draw[1:0] = obstacles[319:318];
obstacles[319:0] = {obstacles[317:0], obstacles[319:318]};
// height will change if it is already jumping or jump button
// is pushed
if (jump || (height) != 2'b00) begin
if (height == 2'b11)
going_up = 1'b0;
if (going_up)
height += 1;
else
height -= 1
if (height == 2'b00)
going_up = 1'b1;
end
draw[159:158] = height;
else
count <= count - 1;
/*if (jump) begin
if (height == 2'b11)
going_up = 1'b0;
if (going_up) begin
if (!jumpOnce)
height <= height + 1;
end
else begin
if (!jumpOnce)
height <= height - 1;
end
if (height == 2'b00) begin
if (!going_up)
//going_up = 1'b1;
jumpOnce = 1'b1;
end
// leftmost two digits of draw used as runner
draw[159:158] = height;
end
else
// runner not jumping
draw[159:158] = 2'b00;
jumpOnce = 1'b0;
going_up = 1'b1;
*/
end
end
assign LEDR[4] = jumpOnce;
assign LEDR[6] = going_up;
assign LEDR[9:8] = height;
endmodule
module display (
input [159:0] floor,
input clk,
input resetn,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] colour
);
// initialization
reg [7:0] x_init=8'd2;
reg [6:0] y_init = 7'd80;
reg [2:0] count = 3'b000;
reg [10:0] counter = 11'b0;
// counts from 0 to 9 for the first two pixel for the runner
reg [4:0] runner_count; = 5'b0;
reg [2:0] runner_height = 3'b0;
// copy of floor value, will do left shift on local value
reg [159:0] local_draw;
// reg [159:0] local_draw =
always@(posedge clk) begin
if (!resetn) begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor<<2;
end
else begin
if (counter < 11'd652) begin
// fisrt 20 counts used to display runner
if (counter < 11'd20) begin
// fisrt or second pixel
if counter < 11'd10
x <= 8'd0;
else
x <= 8'd1;
// stands for current display height
runner_count = counter % 10;
y = y_init - runner_count;
// runner's height
runner_height = floor[159:158] * 2;
if (runner_count == 5'd0)
// base line
colour = 3'b110;
else if (runner_count < runner_height || runner_count > runner_height + 3)
// dark part
colour = 3'b000;
else
// runner part
colour = 3'b101;
end
else
// next 632 counts (158 pixels) to display obstacles
begin
count = (counter-20) % 8;
// x_init starts from 2
x <= x_init + count[2];
// the base line case
if (count[1:0] == 2'b00) begin
colour <= 3'b110;
y <= y_init;
end
else begin
/*if (counter < 11'd8) begin
// the runner case
// make the height of runner: draw * 2
y_init = 7'd80 - local_draw[159:158] * 2;
colour = 3'b101;
end
else begin
*/
//y_init = 7'd80;
//if (count[1:0] == 2'b00)
// colour = 3'b110;
//else
if (count[1:0] > local_draw[159:158])
colour = 3'b000;
else
colour = 3'b011;
//end
y <= y_init - count[1:0];
end
if (count == 3'b111)
begin
x_init <= x_init + 2;
local_draw <= local_draw << 2;
end
end
counter = counter + 1;
end
else begin
x_init <= 8'd2;
y_init <= 7'd80;
count <= 3'b000;
counter <= 11'b0;
local_draw <= floor << 2;
end
end
end
endmodule
|
/*
###############################################################
# Generated by: Cadence Innovus 17.17-s050_1
# OS: Linux x86_64(Host ID dfm.ucsd.edu)
# Generated on: Thu Dec 12 16:42:58 2019
# Design: gcd_mem5
# Command: saveNetlist enc//gcd_mem5_placed.v
###############################################################
*/
module gcd_mem5 (
clk,
req_msg,
req_rdy,
req_val,
reset,
resp_msg,
resp_rdy,
resp_val,
mem_out0,
mem_out1,
mem_out2,
mem_out3,
mem_out4);
input clk;
input [31:0] req_msg;
output req_rdy;
input req_val;
input reset;
output [15:0] resp_msg;
input resp_rdy;
output resp_val;
output [6:0] mem_out0;
output [6:0] mem_out1;
output [6:0] mem_out2;
output [6:0] mem_out3;
output [6:0] mem_out4;
// Internal wires
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _055_;
wire _157_;
wire _158_;
wire _161_;
wire _056_;
wire _162_;
wire _163_;
wire _164_;
wire _054_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _246_;
wire _247_;
wire _076_;
wire _250_;
wire _251_;
wire _252_;
wire _254_;
wire _255_;
wire _256_;
wire _083_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _084_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _085_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _086_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _087_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _088_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _089_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _090_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _091_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _077_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _078_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
wire _327_;
wire _328_;
wire _329_;
wire _330_;
wire _079_;
wire _331_;
wire _332_;
wire _333_;
wire _334_;
wire _335_;
wire _336_;
wire _080_;
wire _337_;
wire _338_;
wire _339_;
wire _340_;
wire _341_;
wire _342_;
wire _343_;
wire _344_;
wire _081_;
wire _345_;
wire _346_;
wire _347_;
wire _348_;
wire _349_;
wire _350_;
wire _082_;
wire _351_;
wire _352_;
wire _092_;
wire _354_;
wire _099_;
wire _355_;
wire _100_;
wire _356_;
wire _101_;
wire _357_;
wire _102_;
wire _358_;
wire _103_;
wire _359_;
wire _104_;
wire _360_;
wire _105_;
wire _361_;
wire _106_;
wire _362_;
wire _107_;
wire _363_;
wire _093_;
wire _364_;
wire _094_;
wire _365_;
wire _095_;
wire _366_;
wire _096_;
wire _367_;
wire _097_;
wire _368_;
wire _098_;
wire \ctrl.state.out[2] ;
wire \ctrl.state.out[1] ;
wire _005_;
wire \dpath.a_lt_b$in0[15] ;
wire \dpath.a_lt_b$in1[15] ;
wire \dpath.a_lt_b$in0[14] ;
wire \dpath.a_lt_b$in1[14] ;
wire \dpath.a_lt_b$in0[13] ;
wire \dpath.a_lt_b$in1[13] ;
wire \dpath.a_lt_b$in0[12] ;
wire \dpath.a_lt_b$in1[12] ;
wire \dpath.a_lt_b$in0[11] ;
wire \dpath.a_lt_b$in1[11] ;
wire \dpath.a_lt_b$in0[10] ;
wire \dpath.a_lt_b$in1[10] ;
wire \dpath.a_lt_b$in0[9] ;
wire \dpath.a_lt_b$in1[9] ;
wire \dpath.a_lt_b$in0[8] ;
wire \dpath.a_lt_b$in1[8] ;
wire \dpath.a_lt_b$in0[7] ;
wire \dpath.a_lt_b$in1[7] ;
wire \dpath.a_lt_b$in0[6] ;
wire \dpath.a_lt_b$in1[6] ;
wire \dpath.a_lt_b$in0[5] ;
wire \dpath.a_lt_b$in1[5] ;
wire \dpath.a_lt_b$in0[4] ;
wire \dpath.a_lt_b$in1[4] ;
wire \dpath.a_lt_b$in0[3] ;
wire \dpath.a_lt_b$in1[3] ;
wire \dpath.a_lt_b$in0[2] ;
wire \dpath.a_lt_b$in1[2] ;
wire \dpath.a_lt_b$in0[1] ;
wire \dpath.a_lt_b$in1[1] ;
wire \dpath.a_lt_b$in0[0] ;
wire \dpath.a_lt_b$in1[0] ;
wire _004_;
wire _003_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _422_;
wire _423_;
wire _424_;
wire _425_;
wire _426_;
wire _427_;
wire _428_;
wire _429_;
wire _430_;
wire _431_;
wire _432_;
wire _433_;
wire _434_;
wire _435_;
wire _436_;
wire _437_;
INV_X1 _438_ (.A(\ctrl.state.out[2] ),
.ZN(_142_));
AND3_X1 _439_ (.A1(_142_),
.A2(\ctrl.state.out[1] ),
.A3(_005_),
.ZN(resp_val));
XOR2_X1 _440_ (.A(\dpath.a_lt_b$in0[0] ),
.B(\dpath.a_lt_b$in1[0] ),
.Z(resp_msg[0]));
NOR4_X1 _441_ (.A1(\dpath.a_lt_b$in1[7] ),
.A2(\dpath.a_lt_b$in1[6] ),
.A3(\dpath.a_lt_b$in1[5] ),
.A4(\dpath.a_lt_b$in1[4] ),
.ZN(_143_));
INV_X1 _442_ (.A(\dpath.a_lt_b$in1[3] ),
.ZN(_144_));
INV_X4 _443_ (.A(\dpath.a_lt_b$in1[2] ),
.ZN(_145_));
NOR2_X1 _444_ (.A1(\dpath.a_lt_b$in1[1] ),
.A2(\dpath.a_lt_b$in1[0] ),
.ZN(_146_));
NAND4_X1 _445_ (.A1(_143_),
.A2(_144_),
.A3(_145_),
.A4(_146_),
.ZN(_147_));
NOR4_X1 _446_ (.A1(\dpath.a_lt_b$in1[11] ),
.A2(\dpath.a_lt_b$in1[10] ),
.A3(\dpath.a_lt_b$in1[9] ),
.A4(\dpath.a_lt_b$in1[8] ),
.ZN(_148_));
NOR4_X1 _447_ (.A1(\dpath.a_lt_b$in1[15] ),
.A2(\dpath.a_lt_b$in1[14] ),
.A3(\dpath.a_lt_b$in1[13] ),
.A4(\dpath.a_lt_b$in1[12] ),
.ZN(_149_));
NAND2_X1 _448_ (.A1(_148_),
.A2(_149_),
.ZN(_150_));
NOR2_X1 _449_ (.A1(_147_),
.A2(_150_),
.ZN(_151_));
INV_X1 _450_ (.A(reset),
.ZN(_152_));
INV_X1 _451_ (.A(_004_),
.ZN(_153_));
NAND3_X1 _452_ (.A1(_151_),
.A2(_152_),
.A3(_153_),
.ZN(_154_));
AND2_X1 _453_ (.A1(resp_val),
.A2(resp_rdy),
.ZN(_155_));
OR3_X1 _454_ (.A1(_155_),
.A2(reset),
.A3(_003_),
.ZN(_156_));
NAND2_X1 _455_ (.A1(_154_),
.A2(_156_),
.ZN(_055_));
OAI211_X1 _456_ (.A(_152_),
.B(_153_),
.C1(_147_),
.C2(_150_),
.ZN(_157_));
INV_X2 _457_ (.A(_005_),
.ZN(_158_));
NAND4_X1 _460_ (.A1(_152_),
.A2(_158_),
.A3(req_rdy),
.A4(req_val),
.ZN(_161_));
NAND2_X1 _461_ (.A1(_157_),
.A2(_161_),
.ZN(_056_));
NAND3_X1 _462_ (.A1(resp_val),
.A2(_152_),
.A3(resp_rdy),
.ZN(_162_));
NOR2_X1 _463_ (.A1(_162_),
.A2(_003_),
.ZN(_163_));
AOI211_X1 _464_ (.A(reset),
.B(_005_),
.C1(req_rdy),
.C2(req_val),
.ZN(_164_));
OR3_X1 _465_ (.A1(_163_),
.A2(reset),
.A3(_164_),
.ZN(_054_));
OAI21_X1 _467_ (.A(req_msg[16]),
.B1(_142_),
.B2(_158_),
.ZN(_166_));
INV_X1 _468_ (.A(\dpath.a_lt_b$in0[15] ),
.ZN(_167_));
NAND2_X1 _469_ (.A1(_167_),
.A2(\dpath.a_lt_b$in1[15] ),
.ZN(_168_));
XNOR2_X2 _470_ (.A(\dpath.a_lt_b$in0[7] ),
.B(\dpath.a_lt_b$in1[7] ),
.ZN(_169_));
XNOR2_X2 _471_ (.A(\dpath.a_lt_b$in0[6] ),
.B(\dpath.a_lt_b$in1[6] ),
.ZN(_170_));
AND2_X4 _472_ (.A1(_169_),
.A2(_170_),
.ZN(_171_));
XNOR2_X2 _473_ (.A(\dpath.a_lt_b$in0[3] ),
.B(\dpath.a_lt_b$in1[3] ),
.ZN(_172_));
XNOR2_X2 _474_ (.A(\dpath.a_lt_b$in0[2] ),
.B(\dpath.a_lt_b$in1[2] ),
.ZN(_173_));
AND2_X2 _475_ (.A1(_172_),
.A2(_173_),
.ZN(_174_));
XNOR2_X2 _476_ (.A(\dpath.a_lt_b$in0[5] ),
.B(\dpath.a_lt_b$in1[5] ),
.ZN(_175_));
XNOR2_X2 _477_ (.A(\dpath.a_lt_b$in0[4] ),
.B(\dpath.a_lt_b$in1[4] ),
.ZN(_176_));
AND2_X4 _478_ (.A1(_175_),
.A2(_176_),
.ZN(_177_));
NAND3_X2 _479_ (.A1(_171_),
.A2(_174_),
.A3(_177_),
.ZN(_178_));
INV_X16 _480_ (.A(\dpath.a_lt_b$in1[1] ),
.ZN(_179_));
AND2_X4 _481_ (.A1(_179_),
.A2(\dpath.a_lt_b$in0[1] ),
.ZN(_180_));
NOR2_X1 _482_ (.A1(_179_),
.A2(\dpath.a_lt_b$in0[1] ),
.ZN(_181_));
INV_X1 _483_ (.A(\dpath.a_lt_b$in0[0] ),
.ZN(_182_));
NOR3_X1 _484_ (.A1(_181_),
.A2(_182_),
.A3(\dpath.a_lt_b$in1[0] ),
.ZN(_183_));
OR3_X4 _485_ (.A1(_178_),
.A2(_180_),
.A3(_183_),
.ZN(_184_));
INV_X2 _486_ (.A(\dpath.a_lt_b$in0[4] ),
.ZN(_185_));
AND3_X1 _487_ (.A1(_175_),
.A2(_185_),
.A3(\dpath.a_lt_b$in1[4] ),
.ZN(_186_));
INV_X1 _488_ (.A(\dpath.a_lt_b$in0[5] ),
.ZN(_187_));
AND2_X1 _489_ (.A1(_187_),
.A2(\dpath.a_lt_b$in1[5] ),
.ZN(_188_));
OAI21_X1 _490_ (.A(_171_),
.B1(_186_),
.B2(_188_),
.ZN(_189_));
INV_X1 _491_ (.A(\dpath.a_lt_b$in1[7] ),
.ZN(_190_));
NOR2_X1 _492_ (.A1(_190_),
.A2(\dpath.a_lt_b$in0[7] ),
.ZN(_191_));
INV_X1 _493_ (.A(_191_),
.ZN(_192_));
INV_X16 _494_ (.A(\dpath.a_lt_b$in0[6] ),
.ZN(_193_));
NAND3_X1 _495_ (.A1(_169_),
.A2(_193_),
.A3(\dpath.a_lt_b$in1[6] ),
.ZN(_194_));
AND3_X1 _496_ (.A1(_189_),
.A2(_192_),
.A3(_194_),
.ZN(_195_));
NOR2_X1 _497_ (.A1(_144_),
.A2(\dpath.a_lt_b$in0[3] ),
.ZN(_196_));
AOI211_X1 _498_ (.A(\dpath.a_lt_b$in0[2] ),
.B(_145_),
.C1(\dpath.a_lt_b$in0[3] ),
.C2(_144_),
.ZN(_197_));
OAI211_X1 _499_ (.A(_171_),
.B(_177_),
.C1(_196_),
.C2(_197_),
.ZN(_198_));
NAND3_X1 _500_ (.A1(_184_),
.A2(_195_),
.A3(_198_),
.ZN(_199_));
XNOR2_X2 _501_ (.A(\dpath.a_lt_b$in0[10] ),
.B(\dpath.a_lt_b$in1[10] ),
.ZN(_200_));
XNOR2_X2 _502_ (.A(\dpath.a_lt_b$in0[11] ),
.B(\dpath.a_lt_b$in1[11] ),
.ZN(_201_));
AND2_X4 _503_ (.A1(_200_),
.A2(_201_),
.ZN(_202_));
XNOR2_X2 _504_ (.A(\dpath.a_lt_b$in0[9] ),
.B(\dpath.a_lt_b$in1[9] ),
.ZN(_203_));
XNOR2_X1 _505_ (.A(\dpath.a_lt_b$in0[8] ),
.B(\dpath.a_lt_b$in1[8] ),
.ZN(_204_));
AND3_X4 _506_ (.A1(_202_),
.A2(_203_),
.A3(_204_),
.ZN(_205_));
XNOR2_X1 _507_ (.A(\dpath.a_lt_b$in0[14] ),
.B(\dpath.a_lt_b$in1[14] ),
.ZN(_206_));
XNOR2_X2 _508_ (.A(\dpath.a_lt_b$in0[15] ),
.B(\dpath.a_lt_b$in1[15] ),
.ZN(_207_));
NAND2_X1 _509_ (.A1(_206_),
.A2(_207_),
.ZN(_208_));
XNOR2_X2 _510_ (.A(\dpath.a_lt_b$in0[13] ),
.B(\dpath.a_lt_b$in1[13] ),
.ZN(_209_));
INV_X1 _511_ (.A(_209_),
.ZN(_210_));
XNOR2_X2 _512_ (.A(\dpath.a_lt_b$in0[12] ),
.B(\dpath.a_lt_b$in1[12] ),
.ZN(_211_));
INV_X2 _513_ (.A(_211_),
.ZN(_212_));
NOR3_X1 _514_ (.A1(_208_),
.A2(_210_),
.A3(_212_),
.ZN(_213_));
AND2_X1 _515_ (.A1(_205_),
.A2(_213_),
.ZN(_214_));
NAND2_X1 _516_ (.A1(_199_),
.A2(_214_),
.ZN(_215_));
INV_X1 _517_ (.A(\dpath.a_lt_b$in0[8] ),
.ZN(_216_));
AND3_X1 _518_ (.A1(_203_),
.A2(_216_),
.A3(\dpath.a_lt_b$in1[8] ),
.ZN(_217_));
INV_X1 _519_ (.A(\dpath.a_lt_b$in0[9] ),
.ZN(_218_));
AND2_X1 _520_ (.A1(_218_),
.A2(\dpath.a_lt_b$in1[9] ),
.ZN(_219_));
OAI21_X1 _521_ (.A(_202_),
.B1(_217_),
.B2(_219_),
.ZN(_220_));
INV_X1 _522_ (.A(\dpath.a_lt_b$in0[11] ),
.ZN(_221_));
NOR2_X1 _523_ (.A1(_221_),
.A2(\dpath.a_lt_b$in1[11] ),
.ZN(_222_));
INV_X1 _524_ (.A(\dpath.a_lt_b$in0[10] ),
.ZN(_223_));
AOI22_X1 _525_ (.A1(_221_),
.A2(\dpath.a_lt_b$in1[11] ),
.B1(_223_),
.B2(\dpath.a_lt_b$in1[10] ),
.ZN(_224_));
OAI21_X1 _526_ (.A(_220_),
.B1(_222_),
.B2(_224_),
.ZN(_225_));
NAND2_X1 _527_ (.A1(_225_),
.A2(_213_),
.ZN(_226_));
INV_X1 _528_ (.A(\dpath.a_lt_b$in0[14] ),
.ZN(_227_));
NAND3_X1 _529_ (.A1(_207_),
.A2(_227_),
.A3(\dpath.a_lt_b$in1[14] ),
.ZN(_228_));
AND4_X4 _530_ (.A1(_168_),
.A2(_215_),
.A3(_226_),
.A4(_228_),
.ZN(_229_));
AND2_X1 _531_ (.A1(\ctrl.state.out[2] ),
.A2(_005_),
.ZN(_230_));
INV_X1 _532_ (.A(\dpath.a_lt_b$in0[13] ),
.ZN(_231_));
NOR2_X1 _533_ (.A1(_231_),
.A2(\dpath.a_lt_b$in1[13] ),
.ZN(_232_));
INV_X1 _534_ (.A(\dpath.a_lt_b$in0[12] ),
.ZN(_233_));
AOI22_X1 _535_ (.A1(_231_),
.A2(\dpath.a_lt_b$in1[13] ),
.B1(_233_),
.B2(\dpath.a_lt_b$in1[12] ),
.ZN(_234_));
OR3_X1 _536_ (.A1(_208_),
.A2(_232_),
.A3(_234_),
.ZN(_235_));
NAND4_X1 _537_ (.A1(_229_),
.A2(resp_msg[0]),
.A3(_230_),
.A4(_235_),
.ZN(_236_));
AND2_X2 _538_ (.A1(_171_),
.A2(_177_),
.ZN(_237_));
NAND4_X1 _539_ (.A1(_205_),
.A2(_237_),
.A3(_213_),
.A4(_174_),
.ZN(_238_));
XNOR2_X2 _540_ (.A(\dpath.a_lt_b$in0[1] ),
.B(\dpath.a_lt_b$in1[1] ),
.ZN(_239_));
INV_X1 _541_ (.A(_239_),
.ZN(_240_));
NOR3_X4 _542_ (.A1(_238_),
.A2(resp_msg[0]),
.A3(_240_),
.ZN(_241_));
AOI21_X4 _543_ (.A(_241_),
.B1(_229_),
.B2(_235_),
.ZN(_242_));
NAND2_X4 _544_ (.A1(_242_),
.A2(\ctrl.state.out[2] ),
.ZN(_243_));
OR2_X4 _545_ (.A1(_243_),
.A2(_158_),
.ZN(_244_));
OAI211_X2 _547_ (.A(_166_),
.B(_236_),
.C1(_244_),
.C2(_006_),
.ZN(_246_));
OR2_X1 _548_ (.A1(\ctrl.state.out[2] ),
.A2(req_rdy),
.ZN(_247_));
MUX2_X1 _551_ (.A(\dpath.a_lt_b$in0[0] ),
.B(_246_),
.S(_247_),
.Z(_076_));
OAI21_X1 _552_ (.A(req_msg[17]),
.B1(_142_),
.B2(_158_),
.ZN(_250_));
INV_X1 _553_ (.A(_230_),
.ZN(_251_));
NOR2_X4 _554_ (.A1(_242_),
.A2(_251_),
.ZN(_252_));
NAND2_X2 _556_ (.A1(_182_),
.A2(\dpath.a_lt_b$in1[0] ),
.ZN(_254_));
XOR2_X1 _557_ (.A(_239_),
.B(_254_),
.Z(resp_msg[1]));
NAND2_X2 _558_ (.A1(_252_),
.A2(resp_msg[1]),
.ZN(_255_));
OAI211_X1 _559_ (.A(_250_),
.B(_255_),
.C1(_244_),
.C2(_007_),
.ZN(_256_));
MUX2_X1 _560_ (.A(\dpath.a_lt_b$in0[1] ),
.B(_256_),
.S(_247_),
.Z(_083_));
OAI21_X1 _561_ (.A(req_msg[18]),
.B1(_142_),
.B2(_158_),
.ZN(_257_));
AOI21_X4 _562_ (.A(_180_),
.B1(_239_),
.B2(_254_),
.ZN(_258_));
XNOR2_X1 _563_ (.A(_258_),
.B(_173_),
.ZN(resp_msg[2]));
NAND2_X2 _564_ (.A1(_252_),
.A2(resp_msg[2]),
.ZN(_259_));
OAI211_X1 _565_ (.A(_257_),
.B(_259_),
.C1(_244_),
.C2(_008_),
.ZN(_260_));
MUX2_X1 _566_ (.A(\dpath.a_lt_b$in0[2] ),
.B(_260_),
.S(_247_),
.Z(_084_));
OAI21_X1 _567_ (.A(req_msg[19]),
.B1(_142_),
.B2(_158_),
.ZN(_261_));
INV_X4 _568_ (.A(_258_),
.ZN(_262_));
AND2_X1 _569_ (.A1(_262_),
.A2(_173_),
.ZN(_263_));
AND2_X4 _570_ (.A1(_145_),
.A2(\dpath.a_lt_b$in0[2] ),
.ZN(_264_));
NOR2_X1 _571_ (.A1(_263_),
.A2(_264_),
.ZN(_265_));
XNOR2_X1 _572_ (.A(_265_),
.B(_172_),
.ZN(resp_msg[3]));
NAND2_X2 _573_ (.A1(_252_),
.A2(resp_msg[3]),
.ZN(_266_));
OAI211_X1 _574_ (.A(_261_),
.B(_266_),
.C1(_244_),
.C2(_009_),
.ZN(_267_));
MUX2_X1 _575_ (.A(\dpath.a_lt_b$in0[3] ),
.B(_267_),
.S(_247_),
.Z(_085_));
OAI21_X1 _576_ (.A(req_msg[20]),
.B1(_142_),
.B2(_158_),
.ZN(_268_));
AND2_X2 _577_ (.A1(_172_),
.A2(_264_),
.ZN(_269_));
AOI21_X4 _578_ (.A(_269_),
.B1(\dpath.a_lt_b$in0[3] ),
.B2(_144_),
.ZN(_270_));
NAND2_X2 _579_ (.A1(_262_),
.A2(_174_),
.ZN(_271_));
NAND2_X4 _580_ (.A1(_270_),
.A2(_271_),
.ZN(_272_));
XOR2_X1 _581_ (.A(_272_),
.B(_176_),
.Z(resp_msg[4]));
NAND2_X2 _582_ (.A1(_252_),
.A2(resp_msg[4]),
.ZN(_273_));
OAI211_X1 _583_ (.A(_268_),
.B(_273_),
.C1(_244_),
.C2(_010_),
.ZN(_274_));
MUX2_X1 _584_ (.A(\dpath.a_lt_b$in0[4] ),
.B(_274_),
.S(_247_),
.Z(_086_));
OAI21_X1 _585_ (.A(req_msg[21]),
.B1(_142_),
.B2(_158_),
.ZN(_275_));
AND2_X1 _586_ (.A1(_272_),
.A2(_176_),
.ZN(_276_));
NOR2_X1 _587_ (.A1(_185_),
.A2(\dpath.a_lt_b$in1[4] ),
.ZN(_277_));
NOR3_X1 _588_ (.A1(_276_),
.A2(_175_),
.A3(_277_),
.ZN(_278_));
AOI221_X4 _589_ (.A(_278_),
.B1(_175_),
.B2(_277_),
.C1(_177_),
.C2(_272_),
.ZN(resp_msg[5]));
NAND2_X2 _590_ (.A1(_252_),
.A2(resp_msg[5]),
.ZN(_279_));
OAI211_X1 _591_ (.A(_275_),
.B(_279_),
.C1(_244_),
.C2(_011_),
.ZN(_280_));
MUX2_X1 _592_ (.A(\dpath.a_lt_b$in0[5] ),
.B(_280_),
.S(_247_),
.Z(_087_));
OAI21_X1 _593_ (.A(req_msg[22]),
.B1(_142_),
.B2(_158_),
.ZN(_281_));
NAND2_X1 _594_ (.A1(_175_),
.A2(_277_),
.ZN(_282_));
OAI21_X1 _595_ (.A(_282_),
.B1(_187_),
.B2(\dpath.a_lt_b$in1[5] ),
.ZN(_283_));
AOI21_X1 _596_ (.A(_283_),
.B1(_272_),
.B2(_177_),
.ZN(_284_));
XNOR2_X1 _597_ (.A(_284_),
.B(_170_),
.ZN(resp_msg[6]));
NAND2_X2 _598_ (.A1(_252_),
.A2(resp_msg[6]),
.ZN(_285_));
OAI211_X1 _599_ (.A(_281_),
.B(_285_),
.C1(_244_),
.C2(_012_),
.ZN(_286_));
MUX2_X1 _600_ (.A(\dpath.a_lt_b$in0[6] ),
.B(_286_),
.S(_247_),
.Z(_088_));
OAI21_X1 _601_ (.A(req_msg[23]),
.B1(_142_),
.B2(_158_),
.ZN(_287_));
AND2_X1 _602_ (.A1(_193_),
.A2(\dpath.a_lt_b$in1[6] ),
.ZN(_288_));
NOR2_X4 _603_ (.A1(_193_),
.A2(\dpath.a_lt_b$in1[6] ),
.ZN(_289_));
NOR3_X1 _604_ (.A1(_284_),
.A2(_288_),
.A3(_289_),
.ZN(_290_));
NOR2_X1 _605_ (.A1(_290_),
.A2(_289_),
.ZN(_291_));
XNOR2_X1 _606_ (.A(_291_),
.B(_169_),
.ZN(resp_msg[7]));
NAND2_X2 _607_ (.A1(_252_),
.A2(resp_msg[7]),
.ZN(_292_));
OAI211_X1 _608_ (.A(_287_),
.B(_292_),
.C1(_244_),
.C2(_013_),
.ZN(_293_));
MUX2_X1 _609_ (.A(\dpath.a_lt_b$in0[7] ),
.B(_293_),
.S(_247_),
.Z(_089_));
OAI21_X1 _610_ (.A(req_msg[24]),
.B1(_142_),
.B2(_158_),
.ZN(_294_));
NAND2_X2 _611_ (.A1(_272_),
.A2(_237_),
.ZN(_295_));
AND2_X2 _612_ (.A1(_169_),
.A2(_289_),
.ZN(_296_));
AOI221_X2 _613_ (.A(_296_),
.B1(\dpath.a_lt_b$in0[7] ),
.B2(_190_),
.C1(_283_),
.C2(_171_),
.ZN(_297_));
NAND2_X2 _614_ (.A1(_295_),
.A2(_297_),
.ZN(_298_));
XOR2_X1 _615_ (.A(_298_),
.B(_204_),
.Z(resp_msg[8]));
NAND2_X2 _616_ (.A1(_252_),
.A2(resp_msg[8]),
.ZN(_299_));
OAI211_X1 _617_ (.A(_294_),
.B(_299_),
.C1(_244_),
.C2(_014_),
.ZN(_300_));
MUX2_X1 _618_ (.A(\dpath.a_lt_b$in0[8] ),
.B(_300_),
.S(_247_),
.Z(_090_));
OAI21_X1 _619_ (.A(req_msg[25]),
.B1(_142_),
.B2(_158_),
.ZN(_301_));
AND3_X1 _620_ (.A1(_298_),
.A2(_203_),
.A3(_204_),
.ZN(_302_));
AND2_X1 _621_ (.A1(_298_),
.A2(_204_),
.ZN(_303_));
NOR2_X1 _622_ (.A1(_216_),
.A2(\dpath.a_lt_b$in1[8] ),
.ZN(_304_));
NOR3_X1 _623_ (.A1(_303_),
.A2(_203_),
.A3(_304_),
.ZN(_305_));
AOI211_X1 _624_ (.A(_302_),
.B(_305_),
.C1(_203_),
.C2(_304_),
.ZN(resp_msg[9]));
NAND2_X1 _625_ (.A1(resp_msg[9]),
.A2(_252_),
.ZN(_306_));
OAI211_X1 _626_ (.A(_301_),
.B(_306_),
.C1(_244_),
.C2(_015_),
.ZN(_307_));
MUX2_X1 _627_ (.A(\dpath.a_lt_b$in0[9] ),
.B(_307_),
.S(_247_),
.Z(_091_));
OAI21_X1 _628_ (.A(req_msg[26]),
.B1(_142_),
.B2(_158_),
.ZN(_308_));
NOR2_X1 _629_ (.A1(_218_),
.A2(\dpath.a_lt_b$in1[9] ),
.ZN(_309_));
AOI21_X1 _630_ (.A(_309_),
.B1(_203_),
.B2(_304_),
.ZN(_310_));
INV_X1 _631_ (.A(_310_),
.ZN(_311_));
NOR2_X1 _632_ (.A1(_302_),
.A2(_311_),
.ZN(_312_));
XNOR2_X1 _633_ (.A(_312_),
.B(_200_),
.ZN(resp_msg[10]));
NAND2_X1 _634_ (.A1(_252_),
.A2(resp_msg[10]),
.ZN(_313_));
OAI211_X1 _635_ (.A(_308_),
.B(_313_),
.C1(_244_),
.C2(_016_),
.ZN(_314_));
MUX2_X1 _636_ (.A(\dpath.a_lt_b$in0[10] ),
.B(_314_),
.S(_247_),
.Z(_077_));
OAI21_X1 _637_ (.A(req_msg[27]),
.B1(_142_),
.B2(_158_),
.ZN(_315_));
OAI21_X2 _638_ (.A(_315_),
.B1(_244_),
.B2(_017_),
.ZN(_316_));
OAI21_X1 _639_ (.A(_200_),
.B1(_302_),
.B2(_311_),
.ZN(_317_));
NOR2_X1 _640_ (.A1(_223_),
.A2(\dpath.a_lt_b$in1[10] ),
.ZN(_318_));
INV_X1 _641_ (.A(_318_),
.ZN(_319_));
AND2_X1 _642_ (.A1(_317_),
.A2(_319_),
.ZN(_320_));
XNOR2_X1 _643_ (.A(_320_),
.B(_201_),
.ZN(resp_msg[11]));
AND2_X2 _644_ (.A1(resp_msg[11]),
.A2(_252_),
.ZN(_321_));
OAI21_X1 _645_ (.A(_247_),
.B1(_316_),
.B2(_321_),
.ZN(_322_));
OAI21_X1 _646_ (.A(_322_),
.B1(_221_),
.B2(_247_),
.ZN(_078_));
AND2_X2 _647_ (.A1(_298_),
.A2(_205_),
.ZN(_323_));
INV_X2 _648_ (.A(_323_),
.ZN(_324_));
NAND2_X1 _649_ (.A1(_311_),
.A2(_202_),
.ZN(_325_));
AOI21_X1 _650_ (.A(_222_),
.B1(_201_),
.B2(_318_),
.ZN(_326_));
AND3_X4 _651_ (.A1(_324_),
.A2(_325_),
.A3(_326_),
.ZN(_327_));
XNOR2_X1 _652_ (.A(_327_),
.B(_211_),
.ZN(resp_msg[12]));
NAND2_X1 _653_ (.A1(resp_msg[12]),
.A2(_252_),
.ZN(_328_));
OAI21_X1 _654_ (.A(req_msg[28]),
.B1(_142_),
.B2(_158_),
.ZN(_329_));
OAI211_X1 _655_ (.A(_328_),
.B(_329_),
.C1(_244_),
.C2(_018_),
.ZN(_330_));
MUX2_X1 _656_ (.A(\dpath.a_lt_b$in0[12] ),
.B(_330_),
.S(_247_),
.Z(_079_));
NOR2_X2 _657_ (.A1(_327_),
.A2(_212_),
.ZN(_331_));
NOR2_X1 _658_ (.A1(_233_),
.A2(\dpath.a_lt_b$in1[12] ),
.ZN(_332_));
NOR2_X2 _659_ (.A1(_331_),
.A2(_332_),
.ZN(_333_));
XNOR2_X1 _660_ (.A(_333_),
.B(_209_),
.ZN(resp_msg[13]));
NAND2_X1 _661_ (.A1(resp_msg[13]),
.A2(_252_),
.ZN(_334_));
OAI21_X1 _662_ (.A(req_msg[29]),
.B1(_142_),
.B2(_158_),
.ZN(_335_));
OAI211_X1 _663_ (.A(_334_),
.B(_335_),
.C1(_019_),
.C2(_244_),
.ZN(_336_));
MUX2_X1 _664_ (.A(\dpath.a_lt_b$in0[13] ),
.B(_336_),
.S(_247_),
.Z(_080_));
OR3_X4 _665_ (.A1(_327_),
.A2(_210_),
.A3(_212_),
.ZN(_337_));
INV_X1 _666_ (.A(_206_),
.ZN(_338_));
AOI22_X1 _667_ (.A1(_209_),
.A2(_332_),
.B1(\dpath.a_lt_b$in0[13] ),
.B2(_019_),
.ZN(_339_));
AND3_X1 _668_ (.A1(_337_),
.A2(_338_),
.A3(_339_),
.ZN(_340_));
AOI21_X4 _669_ (.A(_338_),
.B1(_337_),
.B2(_339_),
.ZN(_341_));
NOR2_X1 _670_ (.A1(_340_),
.A2(_341_),
.ZN(resp_msg[14]));
NAND2_X1 _671_ (.A1(resp_msg[14]),
.A2(_252_),
.ZN(_342_));
OAI21_X1 _672_ (.A(req_msg[30]),
.B1(_142_),
.B2(_158_),
.ZN(_343_));
OAI211_X1 _673_ (.A(_342_),
.B(_343_),
.C1(_020_),
.C2(_244_),
.ZN(_344_));
MUX2_X1 _674_ (.A(\dpath.a_lt_b$in0[14] ),
.B(_344_),
.S(_247_),
.Z(_081_));
NOR2_X1 _675_ (.A1(_227_),
.A2(\dpath.a_lt_b$in1[14] ),
.ZN(_345_));
NOR2_X2 _676_ (.A1(_341_),
.A2(_345_),
.ZN(_346_));
XNOR2_X1 _677_ (.A(_346_),
.B(_207_),
.ZN(resp_msg[15]));
AND2_X2 _678_ (.A1(resp_msg[15]),
.A2(_252_),
.ZN(_347_));
OAI21_X1 _679_ (.A(req_msg[31]),
.B1(_142_),
.B2(_158_),
.ZN(_348_));
OAI21_X2 _680_ (.A(_348_),
.B1(_244_),
.B2(_021_),
.ZN(_349_));
OAI21_X1 _681_ (.A(_247_),
.B1(_347_),
.B2(_349_),
.ZN(_350_));
OAI21_X1 _682_ (.A(_350_),
.B1(_167_),
.B2(_247_),
.ZN(_082_));
MUX2_X1 _683_ (.A(\dpath.a_lt_b$in0[0] ),
.B(req_msg[0]),
.S(req_rdy),
.Z(_351_));
NAND2_X4 _684_ (.A1(_243_),
.A2(_005_),
.ZN(_352_));
MUX2_X1 _686_ (.A(\dpath.a_lt_b$in1[0] ),
.B(_351_),
.S(_352_),
.Z(_092_));
MUX2_X1 _687_ (.A(\dpath.a_lt_b$in0[1] ),
.B(req_msg[1]),
.S(req_rdy),
.Z(_354_));
MUX2_X1 _688_ (.A(\dpath.a_lt_b$in1[1] ),
.B(_354_),
.S(_352_),
.Z(_099_));
MUX2_X1 _689_ (.A(\dpath.a_lt_b$in0[2] ),
.B(req_msg[2]),
.S(req_rdy),
.Z(_355_));
MUX2_X1 _690_ (.A(\dpath.a_lt_b$in1[2] ),
.B(_355_),
.S(_352_),
.Z(_100_));
MUX2_X1 _691_ (.A(\dpath.a_lt_b$in0[3] ),
.B(req_msg[3]),
.S(req_rdy),
.Z(_356_));
MUX2_X1 _692_ (.A(\dpath.a_lt_b$in1[3] ),
.B(_356_),
.S(_352_),
.Z(_101_));
MUX2_X1 _693_ (.A(\dpath.a_lt_b$in0[4] ),
.B(req_msg[4]),
.S(req_rdy),
.Z(_357_));
MUX2_X1 _694_ (.A(\dpath.a_lt_b$in1[4] ),
.B(_357_),
.S(_352_),
.Z(_102_));
MUX2_X1 _695_ (.A(\dpath.a_lt_b$in0[5] ),
.B(req_msg[5]),
.S(req_rdy),
.Z(_358_));
MUX2_X1 _696_ (.A(\dpath.a_lt_b$in1[5] ),
.B(_358_),
.S(_352_),
.Z(_103_));
MUX2_X1 _697_ (.A(\dpath.a_lt_b$in0[6] ),
.B(req_msg[6]),
.S(req_rdy),
.Z(_359_));
MUX2_X1 _698_ (.A(\dpath.a_lt_b$in1[6] ),
.B(_359_),
.S(_352_),
.Z(_104_));
MUX2_X1 _699_ (.A(\dpath.a_lt_b$in0[7] ),
.B(req_msg[7]),
.S(req_rdy),
.Z(_360_));
MUX2_X1 _700_ (.A(\dpath.a_lt_b$in1[7] ),
.B(_360_),
.S(_352_),
.Z(_105_));
MUX2_X1 _701_ (.A(\dpath.a_lt_b$in0[8] ),
.B(req_msg[8]),
.S(req_rdy),
.Z(_361_));
MUX2_X1 _702_ (.A(\dpath.a_lt_b$in1[8] ),
.B(_361_),
.S(_352_),
.Z(_106_));
MUX2_X1 _703_ (.A(\dpath.a_lt_b$in0[9] ),
.B(req_msg[9]),
.S(req_rdy),
.Z(_362_));
MUX2_X1 _704_ (.A(\dpath.a_lt_b$in1[9] ),
.B(_362_),
.S(_352_),
.Z(_107_));
MUX2_X1 _705_ (.A(\dpath.a_lt_b$in0[10] ),
.B(req_msg[10]),
.S(req_rdy),
.Z(_363_));
MUX2_X1 _706_ (.A(\dpath.a_lt_b$in1[10] ),
.B(_363_),
.S(_352_),
.Z(_093_));
MUX2_X1 _707_ (.A(\dpath.a_lt_b$in0[11] ),
.B(req_msg[11]),
.S(req_rdy),
.Z(_364_));
MUX2_X1 _708_ (.A(\dpath.a_lt_b$in1[11] ),
.B(_364_),
.S(_352_),
.Z(_094_));
MUX2_X1 _709_ (.A(\dpath.a_lt_b$in0[12] ),
.B(req_msg[12]),
.S(req_rdy),
.Z(_365_));
MUX2_X1 _710_ (.A(\dpath.a_lt_b$in1[12] ),
.B(_365_),
.S(_352_),
.Z(_095_));
MUX2_X1 _711_ (.A(\dpath.a_lt_b$in0[13] ),
.B(req_msg[13]),
.S(req_rdy),
.Z(_366_));
MUX2_X1 _712_ (.A(\dpath.a_lt_b$in1[13] ),
.B(_366_),
.S(_352_),
.Z(_096_));
MUX2_X1 _713_ (.A(\dpath.a_lt_b$in0[14] ),
.B(req_msg[14]),
.S(req_rdy),
.Z(_367_));
MUX2_X1 _714_ (.A(\dpath.a_lt_b$in1[14] ),
.B(_367_),
.S(_352_),
.Z(_097_));
MUX2_X1 _715_ (.A(\dpath.a_lt_b$in0[15] ),
.B(req_msg[15]),
.S(req_rdy),
.Z(_368_));
MUX2_X1 _716_ (.A(\dpath.a_lt_b$in1[15] ),
.B(_368_),
.S(_352_),
.Z(_098_));
DFF_X1 _858_ (.D(_054_),
.CK(clk),
.Q(req_rdy),
.QN(_005_));
DFF_X1 _859_ (.D(_055_),
.CK(clk),
.Q(\ctrl.state.out[1] ),
.QN(_003_));
DFF_X1 _860_ (.D(_056_),
.CK(clk),
.Q(\ctrl.state.out[2] ),
.QN(_004_));
DFF_X1 _861_ (.D(_076_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[0] ),
.QN(_422_));
DFF_X1 _862_ (.D(_083_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[1] ),
.QN(_423_));
DFF_X1 _863_ (.D(_084_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[2] ),
.QN(_424_));
DFF_X1 _864_ (.D(_085_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[3] ),
.QN(_425_));
DFF_X1 _865_ (.D(_086_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[4] ),
.QN(_426_));
DFF_X1 _866_ (.D(_087_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[5] ),
.QN(_427_));
DFF_X1 _867_ (.D(_088_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[6] ),
.QN(_428_));
DFF_X1 _868_ (.D(_089_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[7] ),
.QN(_429_));
DFF_X1 _869_ (.D(_090_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[8] ),
.QN(_430_));
DFF_X1 _870_ (.D(_091_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[9] ),
.QN(_431_));
DFF_X1 _871_ (.D(_077_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[10] ),
.QN(_432_));
DFF_X1 _872_ (.D(_078_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[11] ),
.QN(_433_));
DFF_X1 _873_ (.D(_079_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[12] ),
.QN(_434_));
DFF_X1 _874_ (.D(_080_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[13] ),
.QN(_435_));
DFF_X1 _875_ (.D(_081_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[14] ),
.QN(_436_));
DFF_X1 _876_ (.D(_082_),
.CK(clk),
.Q(\dpath.a_lt_b$in0[15] ),
.QN(_437_));
DFF_X1 _877_ (.D(_092_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[0] ),
.QN(_006_));
DFF_X1 _878_ (.D(_099_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[1] ),
.QN(_007_));
DFF_X1 _879_ (.D(_100_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[2] ),
.QN(_008_));
DFF_X1 _880_ (.D(_101_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[3] ),
.QN(_009_));
DFF_X1 _881_ (.D(_102_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[4] ),
.QN(_010_));
DFF_X1 _882_ (.D(_103_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[5] ),
.QN(_011_));
DFF_X1 _883_ (.D(_104_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[6] ),
.QN(_012_));
DFF_X1 _884_ (.D(_105_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[7] ),
.QN(_013_));
DFF_X1 _885_ (.D(_106_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[8] ),
.QN(_014_));
DFF_X1 _886_ (.D(_107_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[9] ),
.QN(_015_));
DFF_X1 _887_ (.D(_093_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[10] ),
.QN(_016_));
DFF_X1 _888_ (.D(_094_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[11] ),
.QN(_017_));
DFF_X1 _889_ (.D(_095_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[12] ),
.QN(_018_));
DFF_X1 _890_ (.D(_096_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[13] ),
.QN(_019_));
DFF_X1 _891_ (.D(_097_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[14] ),
.QN(_020_));
DFF_X1 _892_ (.D(_098_),
.CK(clk),
.Q(\dpath.a_lt_b$in1[15] ),
.QN(_021_));
fakeram45_64x7 mem0 (.clk(clk),
.rd_out(mem_out0),
.we_in(_006_),
.ce_in(_007_),
.addr_in({ _008_,
_009_,
_010_,
_011_,
_012_,
_013_ }),
.wd_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_,
_020_ }),
.w_mask_in({ _021_,
_076_,
_077_,
_078_,
_079_,
_080_,
_081_ }));
fakeram45_64x7 mem1 (.clk(clk),
.rd_out(mem_out1),
.we_in(_090_),
.ce_in(_091_),
.addr_in({ _092_,
_093_,
_094_,
_095_,
_096_,
_097_ }),
.wd_in({ _098_,
_099_,
_100_,
_101_,
_102_,
_103_,
_104_ }),
.w_mask_in({ _105_,
_106_,
_107_,
_054_,
_055_,
_056_,
_003_ }));
fakeram45_64x7 mem2 (.clk(clk),
.rd_out(mem_out2),
.we_in(_012_),
.ce_in(_013_),
.addr_in({ _014_,
_015_,
_016_,
_017_,
_018_,
_019_ }),
.wd_in({ _020_,
_021_,
_076_,
_077_,
_078_,
_079_,
_080_ }),
.w_mask_in({ _081_,
_082_,
_083_,
_084_,
_085_,
_086_,
_087_ }));
fakeram45_64x7 mem3 (.clk(clk),
.rd_out(mem_out3),
.we_in(_096_),
.ce_in(_097_),
.addr_in({ _098_,
_099_,
_100_,
_101_,
_102_,
_103_ }),
.wd_in({ _104_,
_105_,
_106_,
_107_,
\ctrl.state.out[1] ,
\ctrl.state.out[2] ,
\dpath.a_lt_b$in0[0] }),
.w_mask_in({ \dpath.a_lt_b$in0[10] ,
\dpath.a_lt_b$in0[11] ,
\dpath.a_lt_b$in0[12] ,
\dpath.a_lt_b$in0[13] ,
\dpath.a_lt_b$in0[14] ,
\dpath.a_lt_b$in0[15] ,
\dpath.a_lt_b$in0[1] }));
fakeram45_64x7 mem4 (.clk(clk),
.rd_out(mem_out4),
.we_in(\dpath.a_lt_b$in1[0] ),
.ce_in(\dpath.a_lt_b$in1[10] ),
.addr_in({ \dpath.a_lt_b$in1[11] ,
\dpath.a_lt_b$in1[12] ,
\dpath.a_lt_b$in1[13] ,
\dpath.a_lt_b$in1[14] ,
\dpath.a_lt_b$in1[15] ,
\dpath.a_lt_b$in1[1] }),
.wd_in({ \dpath.a_lt_b$in1[2] ,
\dpath.a_lt_b$in1[3] ,
\dpath.a_lt_b$in1[4] ,
\dpath.a_lt_b$in1[5] ,
\dpath.a_lt_b$in1[6] ,
\dpath.a_lt_b$in1[7] ,
\dpath.a_lt_b$in1[8] }),
.w_mask_in({ \dpath.a_lt_b$in1[9] ,
_142_,
_143_,
_144_,
_145_,
_146_,
_147_ }));
endmodule
|
module ADT7310P16LS32L (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_param="SPICounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i({SPICounterPresetH_i, SPICounterPresetL_i})
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i(PeriodCounterPreset_i)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_BLACKBOX_V
`define SKY130_FD_SC_MS__A22OI_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_BLACKBOX_V
|
`include "../led_ctl.v"
module test;
reg read_n;
reg write_n;
reg reset_n;
reg ce_n;
wire [7:0] data;
wire [7:0] leds;
reg [7:0] write_data;
assign data = (~(write_n)) ? write_data : 8'bz;
led_ctl led1(read_n, write_n, reset_n, ce_n, data, leds);
initial begin
$dumpfile("led_ctl-test.vcd");
$dumpvars(0,test);
// start disabled
ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
reset_n = 1'b1;
write_data = 8'hAA;
// should see:
// data == high z
// reset
#1 reset_n = 1'b0;
#1 reset_n = 1'b1;
// should see:
// led1.leds == ~(0x00)
// write cycle
#1 write_data = 8'hBB;
#1 ce_n = 1'b0;
#1 write_n = 1'b0;
// should see:
// test.data == 0xBB
// led1.leds == ~(0xBB) -> 0x44
// back to disabled
#1 ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
// should see:
// data == high z
// read cycle
#1 ce_n = 1'b0;
#1 read_n = 1'b0;
// should see:
// test.data == ~(0x44) -> 0xBB
// back to disabled
#1 ce_n = 1'b1;
read_n = 1'b1;
write_n = 1'b1;
// should see:
// data == high z
#1;
$finish;
end
endmodule
|
module top();
localparam width_lp = 32;
localparam debug_lp = 0;
// These declarations export the functions from the leaf
// modules. There may be a cleaner way to do this but I haven't
// found it yet.
logic ns_clk, ns_by2_clk, ns_reset, debug_o;
parameter lc_cycle_time_p = 1000000;
bsg_nonsynth_dpi_clock_gen
#(.cycle_time_p(lc_cycle_time_p)
)
core_clk_gen
(.o(ns_clk));
bsg_nonsynth_dpi_clock_gen
#(.cycle_time_p(lc_cycle_time_p/2)
)
core_clk_gen2
(.o(ns_by2_clk));
bsg_nonsynth_reset_gen
#(
.num_clocks_p(1)
,.reset_cycles_lo_p(1)
,.reset_cycles_hi_p(2)
)
reset_gen
(
.clk_i(ns_clk)
,.async_reset_o(ns_reset)
);
int cycle = 0;
always @(posedge ns_by2_clk) begin
cycle <= cycle +1;
if(debug_o)
$display("BSG DBGINFO: top by2 -- Cycle %d", cycle);
end
always @(posedge ns_clk) begin
if(debug_o)
$display("BSG DBGINFO: top -- Cycle %d", cycle);
end
logic [width_lp-1:0] data_i;
logic [width_lp-1:0] data_o;
logic v_o, v_i, ready_o, yumi_i;
bsg_nonsynth_dpi_from_fifo
#(
.width_p (width_lp)
,.debug_p (debug_lp))
f2d_i
(
.yumi_o (yumi_i)
,.debug_o (debug_o)
,.clk_i (ns_clk)
,.reset_i (ns_reset)
,.v_i (v_o)
,.data_i (data_o));
bsg_nonsynth_dpi_to_fifo
#(
.width_p (width_lp)
,.debug_p (debug_lp))
d2f_i
(
.debug_o()
,.v_o(v_i)
,.data_o(data_i)
,.ready_i(ready_o)
,.clk_i(ns_clk)
,.reset_i(ns_reset));
bsg_fifo_1r1w_small_unhardened
#(.els_p(4)
,.width_p(width_lp)
)
fifo_i
(
.clk_i(ns_clk)
,.reset_i(ns_reset)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(data_i)
,.v_o(v_o)
,.data_o(data_o)
,.yumi_i(yumi_i));
endmodule
|
`timescale 1ns/1ns
module usb_tx_data
(input c,
input [7:0] d,
input dv,
output [7:0] sie_d,
output sie_dv);
// no need for FIFO: just delay it one clock (after SYNC) and compute CRC16
// on the fly
localparam ST_IDLE = 4'd0;
localparam ST_SYNC = 4'd1;
localparam ST_DATA = 4'd2;
localparam ST_CRC_HI = 4'd3;
localparam ST_CRC_LO = 4'd4;
localparam ST_DONE = 4'd5;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [7:0] d_d1;
d1 #(8) d_d1_r(.c(c), .d(d), .q(d_d1));
//wire [15:0] crc = 16'h1234;
wire [15:0] crc;
wire crc_dv;
usb_crc16 usb_crc16_inst
(.c(c), .d(d_d1), .dv(crc_dv), .rst(state == ST_IDLE), .crc(crc));
wire [1:0] sie_d_sel;
wire [7:0] sie_mux_z;
gmux #(.DWIDTH(8), .SELWIDTH(2)) sie_d_gmux
(.d({crc, d_d1, 8'b10000000}),
.sel(sie_d_sel),
.z(sie_mux_z));
wire [7:0] sie_d_i = sie_dv_i ? sie_mux_z : 8'h0;
always @* begin
case (state)
ST_IDLE:
if (dv) ctrl = { ST_SYNC , 5'b00_00_1 };
else ctrl = { ST_IDLE , 5'b00_00_0 };
ST_SYNC: ctrl = { ST_DATA , 5'b00_01_1 };
ST_DATA:
if (~dv) ctrl = { ST_CRC_LO, 5'b01_01_1 };
else ctrl = { ST_DATA , 5'b01_01_1 };
ST_CRC_LO: ctrl = { ST_CRC_HI, 5'b00_10_1 };
ST_CRC_HI: ctrl = { ST_DONE , 5'b00_11_1 };
ST_DONE: ctrl = { ST_IDLE , 5'b00_11_0 };
default: ctrl = { ST_IDLE , 5'b00_00_0 };
endcase
end
wire sie_dv_i = ctrl[0];
assign sie_d_sel = ctrl[2:1];
assign crc_dv = ctrl[3];
// help timing a bit
d1 #(8) sie_d1_d_r (.c(c), .d(sie_d_i ), .q(sie_d ));
d1 sie_d1_dv_r(.c(c), .d(sie_dv_i), .q(sie_dv));
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram2_ddr2_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram2_ddr2_rptr( /*AUTOARG*/
// Outputs
io_dram_data_valid_buf, io_dram_ecc_in_buf, io_dram_data_in_buf,
dram_io_cas_l_buf, dram_io_channel_disabled_buf, dram_io_cke_buf,
dram_io_clk_enable_buf, dram_io_drive_data_buf,
dram_io_drive_enable_buf, dram_io_pad_clk_inv_buf,
dram_io_pad_enable_buf, dram_io_ras_l_buf, dram_io_write_en_l_buf,
dram_io_addr_buf, dram_io_bank_buf, dram_io_cs_l_buf,
dram_io_data_out_buf, dram_io_ptr_clk_inv_buf,
// Inputs
io_dram_data_valid, io_dram_ecc_in, io_dram_data_in,
dram_io_cas_l, dram_io_channel_disabled, dram_io_cke,
dram_io_clk_enable, dram_io_drive_data, dram_io_drive_enable,
dram_io_pad_clk_inv, dram_io_pad_enable, dram_io_ras_l,
dram_io_write_en_l, dram_io_addr, dram_io_bank, dram_io_cs_l,
dram_io_data_out, dram_io_ptr_clk_inv
);
/*OUTPUTS*/
output io_dram_data_valid_buf;
output [31:0] io_dram_ecc_in_buf;
output [255:0] io_dram_data_in_buf;
output dram_io_cas_l_buf;
output dram_io_channel_disabled_buf;
output dram_io_cke_buf;
output dram_io_clk_enable_buf;
output dram_io_drive_data_buf;
output dram_io_drive_enable_buf;
output dram_io_pad_clk_inv_buf;
output dram_io_pad_enable_buf;
output dram_io_ras_l_buf;
output dram_io_write_en_l_buf;
output [14:0] dram_io_addr_buf;
output [2:0] dram_io_bank_buf;
output [3:0] dram_io_cs_l_buf;
output [287:0] dram_io_data_out_buf;
output [4:0] dram_io_ptr_clk_inv_buf;
/*INPUTS*/
input io_dram_data_valid;
input [31:0] io_dram_ecc_in;
input [255:0] io_dram_data_in;
input dram_io_cas_l;
input dram_io_channel_disabled;
input dram_io_cke;
input dram_io_clk_enable;
input dram_io_drive_data;
input dram_io_drive_enable;
input dram_io_pad_clk_inv;
input dram_io_pad_enable;
input dram_io_ras_l;
input dram_io_write_en_l;
input [14:0] dram_io_addr;
input [2:0] dram_io_bank;
input [3:0] dram_io_cs_l;
input [287:0] dram_io_data_out;
input [4:0] dram_io_ptr_clk_inv;
/************************* CODE *********************************/
assign io_dram_data_in_buf = io_dram_data_in[255:0];
assign io_dram_data_valid_buf = io_dram_data_valid;
assign io_dram_ecc_in_buf = io_dram_ecc_in[31:0];
assign dram_io_addr_buf = dram_io_addr[14:0];
assign dram_io_bank_buf = dram_io_bank[2:0];
assign dram_io_cas_l_buf = dram_io_cas_l;
assign dram_io_channel_disabled_buf = dram_io_channel_disabled;
assign dram_io_cke_buf = dram_io_cke;
assign dram_io_clk_enable_buf = dram_io_clk_enable;
assign dram_io_cs_l_buf = dram_io_cs_l[3:0];
assign dram_io_data_out_buf = dram_io_data_out[287:0];
assign dram_io_drive_data_buf = dram_io_drive_data;
assign dram_io_drive_enable_buf = dram_io_drive_enable;
assign dram_io_pad_clk_inv_buf = dram_io_pad_clk_inv;
assign dram_io_pad_enable_buf = dram_io_pad_enable;
assign dram_io_ptr_clk_inv_buf = dram_io_ptr_clk_inv[4:0];
assign dram_io_ras_l_buf = dram_io_ras_l;
assign dram_io_write_en_l_buf = dram_io_write_en_l;
endmodule
|
`timescale 1ns/10ps
`include "pipeconnect.h"
module dc_ctrl(input wire clk,
input wire rst,
input wire `REQ dc_ctrl_req,
output wire `RES dc_ctrl_res);
parameter debug = 0;
wire [31:0] addr, q;
reg r_ = 0;
always @(posedge clk) r_ <= rst ? 1'b0 : dc_ctrl_req`R;
assign addr = dc_ctrl_req`A;
assign dc_ctrl_res`RD = r_ ? q : 0;
assign dc_ctrl_res`HOLD = 0;
dcache dc(.clock (clk),
.clken (1),
.address(addr[12:2]),
.wren (dc_ctrl_req`W),
.data (dc_ctrl_req`WD),
.byteena(dc_ctrl_req`WBE),
.q (q));
`ifdef SIMULATE_MAIN
pipechecker check("dc_ctrl", clk, dc_ctrl_req, dc_ctrl_res);
// Debugging
always @(posedge clk) if (debug) begin
if (dc_ctrl_res`HOLD)
$display("%5d D$: Stall x_load %d x_store %d m_stall %d opcode %2x",
$time, dc_ctrl_req`R, dc_ctrl_req`W);
else begin
if (dc_ctrl_req`R)
$display("%5d D$: load [%x]", $time, dc_ctrl_req`A);
if (r_)
$display("%5d D$: load -> %x", $time, dc_ctrl_res`RD);
if (dc_ctrl_req`W)
$display("%5d D$: store %x->[%x] (bytena %x)",
$time, dc_ctrl_req`WD, addr, dc_ctrl_req`WBE);
end
end
`endif
endmodule
|
(*************************************************************************)
(** The simply-typed lambda calculus in Coq. *)
(*************************************************************************)
(** An interactive tutorial on developing programming language
metatheory. This file uses the simply-typed lambda calculus
(STLC) to demonstrate the locally nameless representation of
lambda terms and cofinite quantification in judgments.
This tutorial concentrates on "how" to formalize STLC; for more
details about "why" we use this style of development see:
"Engineering Formal Metatheory", Aydemir, Charguéraud, Pierce,
Pollack, Weirich. POPL 2008.
Tutorial authors: Brian Aydemir and Stephanie Weirich, with help
from Aaron Bohannon, Nate Foster, Benjamin Pierce, Jeffrey
Vaughan, Dimitrios Vytiniotis, and Steve Zdancewic. Adapted from
code by Arthur Charguéraud.
*)
(*************************************************************************)
(** * Contents
- Syntax of STLC
- Substitution
- Free variables
- Open
- Local closure
- Properties about basic operations
- Cofinite quantification
- Tactic support
- Typing environments
- Typing relation
- Weakening
- Substitution
- Values and evaluation
- Preservation
- Progress
- Additional properties
Solutions to exercises are in [STLC_Solutions.v].
*)
(*************************************************************************)
(* First, we import a number of definition from the Metatheory
library (see Metatheory.v). The following command makes those
definitions available in the rest of this file. This command
will only succeed if you have already run "make" in the tutorial
directory to compile the Metatheory library.
*)
Require Import Metatheory.
(*************************************************************************)
(** * Syntax of STLC *)
(*************************************************************************)
(** We use a locally nameless representation for the simply-typed
lambda calculus, where bound variables are represented as natural
numbers (de Bruijn indices) and free variables are represented as
[atom]s. The type [atom], defined in the [Atom] library,
represents names: equality is decidable on atoms (eq_atom_dec),
and it is possible to generate an atom fresh for any given
finite set of atoms (atom_fresh_for_set).
*)
Inductive typ : Set :=
| typ_base : typ
| typ_arrow : typ -> typ -> typ.
Inductive exp : Set :=
| bvar : nat -> exp (* bound variables *)
| fvar : atom -> exp (* free variables *)
| abs : exp -> exp
| app : exp -> exp -> exp.
Coercion bvar : nat >-> exp.
Coercion fvar : atom >-> exp.
(** We declare the constructors for indices and variables to be
coercions. That way, if Coq sees a [nat] where it expects an
[exp], it will implicitly insert an application of [bvar]; and
similarly for [atom]s.
*)
(** For example, we can encode the expression (\x. Y x) as below. *)
(** Because "Y" is free variable in this term, we need to assume an
atom for this name.
*)
Parameter Y : atom.
Definition demo_rep1 := abs (app Y 0).
(** Note that because of the coercions we may write
[abs (app Y 0)] instead of [abs (app (fvar Y) (bvar 0))].
*)
(** Another example: the encoding of (\x. \y. (y x)) *)
Definition demo_rep2 := abs (abs (app 0 1)).
(** *** Exercise [two] *)
(** Convert the following lambda calculus term to locally nameless
representation.
*)
(** "two" \s. \z. s(s z) **)
(** There are two important advantages of the locally nameless
representation:
- Alpha-equivalent terms have a unique representation,
we're always working up to alpha-equivalence.
- Operations such as free variable substitution and free
variable calculation have simple recursive definitions
(and therefore are simple to reason about).
Weighed against these advantages are two drawbacks:
- The [exp] datatype admits terms, such as [abs 3], where
indices are unbound.
A term is called "locally closed" when it contains
no unbound indices.
- We must define *both* bound variable & free variable
substitution and reason about how these operations
interact with eachother.
*)
(*************************************************************************)
(** * Substitution *)
(*************************************************************************)
(** Substitution replaces a free variable with a term. The definition
below is simple for two reasons:
- Because bound variables are represented using indices, there
is no need to worry about variable capture.
- We assume that the term being substituted in is locally
closed. Thus, there is no need to shift indices when
passing under a binder.
*)
Fixpoint subst (z : atom) (u : exp) (e : exp) {struct e} : exp :=
match e with
| bvar i => bvar i
| fvar x => if x == z then u else (fvar x)
| abs e1 => abs (subst z u e1)
| app e1 e2 => app (subst z u e1) (subst z u e2)
end.
(** The Fixpoint keyword defines a Coq function. As all functions in
Coq must be total, the annotation [{struct e}] indicates the termination
metric---all recursive calls in this definition are made to
arguments that are structurally smaller than [e].
*)
(* Note also that subst uses the notation [x == z] for
decidable atom equality. (This notation is defined in
[Metatheory].)
*)
(** We define a notation for free variable substitution that mimics
standard mathematical notation. *)
Notation "[ z ~> u ] e" := (subst z u e) (at level 68).
(** To demonstrate how free variable substitution works, we
need to reason about decidable equality.
*)
Parameter Z : atom.
Check (Y == Z).
(** The decidable atom equality function returns a sum. If the
two atoms are equal, the left branch of the sum is returned,
carrying a proof of the proposition that the atoms are equal.
If they are not equal, the right branch includes a proof of
the disequality.
*)
(** The demo below uses three new tactics:
- The tactic [simpl] reduces a Coq expression to its normal
form.
- The tactic [Case] marks cases in the proof script.
It takes any string as its argument, and puts that string in
the hypothesis list until the case is finished.
- The tactic [destruct (Y==Y)] considers the two possible
results of the equality test.
*)
Lemma demo_subst1: [Y ~> Z] (abs (app 0 Y)) = (abs (app 0 Z)).
Proof.
simpl.
destruct (Y==Y).
Case "left".
auto.
Case "right".
destruct n. auto.
Qed.
(*************************************************************************)
(** * Free variables *)
(*************************************************************************)
(** The function [fv], defined below, calculates the set of free
variables in an expression. Because we are using locally nameless
representation, where bound variables are represented as indices,
any name we see is a free variable of a term. In particular, this
makes the [abs] case simple.
*)
Fixpoint fv (e : exp) {struct e} : atoms :=
match e with
| bvar i => {}
| fvar x => singleton x
| abs e1 => fv e1
| app e1 e2 => (fv e1) `union` (fv e2)
end.
(** The type [atoms] represents a finite set of elements of type [atom],
and the notations for the empty set and infix union are defined in
the Metatheory library.
*)
(** *** EXERCISE [subst_fresh] *)
(** To show the ease of reasoning with these definitions, we will
prove a standard result from lambda calculus: if a variable does
not appear free in a term, then substituting for it has no
effect.
*)
Lemma subst_fresh : forall (x : atom) e u,
x `notin` fv e -> [x ~> u] e = e.
Proof.
(* fill in proof *)
(* GOAL: To step through the details of the subst_fresh lemma. *)
(* HINTS: Prove this lemma by induction on e.
- You will need to use [simpl] in many cases. You can [simpl]
everything everywhere (including hypotheses) with the
pattern [simpl in *].
- Part of this proof includes a false assumption about free variables.
Destructing this hypothesis produces a goal about finite set
membership. The [fsetdec] tactic can show this and other
finite set related goals. (Elsewhere, you may also use the
properties of finite sets found in the [FSets] library.)
- The tactic [f_equal] converts a goal of the form
[f e1 = f e1'] in to one of the form [e1 = e1'], and
similarly for [f e1 e2 = f e1' e2'], etc.
*)
Admitted.
(*************************************************************************)
(** * Opening *)
(*************************************************************************)
(** Opening replaces an index with a term. It corresponds to informal
substitution for a bound variable, such as in the rule for beta
reduction. Note that only "dangling" indices (those that do not
refer to any abstraction) can be opened. Opening has no effect for
terms that are locally closed.
Natural numbers are just an inductive datatype with two
constructors: O and S, defined in Coq.Init.Datatypes.
The notation [k === i] is the decidable equality function for
natural numbers (cf. Coq.Peano_dec.eq_nat_dec).
This notation is defined in the [Metatheory] library.
We make several simplifying assumptions in defining [open_rec].
First, we assume that the argument [u] is locally closed. This
assumption simplifies the implementation since we do not need to
shift indices in [u] when passing under a binder. Second, we
assume that this function is initially called with index zero and
that zero is the only unbound index in the term. This eliminates
the need to possibly subtract one in the case of indices.
There is no need to worry about variable capture because bound
variables are indices.
*)
Fixpoint open_rec (k : nat) (u : exp) (e : exp) {struct e} : exp :=
match e with
| bvar i => if k === i then u else (bvar i)
| fvar x => fvar x
| abs e1 => abs (open_rec (S k) u e1)
| app e1 e2 => app (open_rec k u e1) (open_rec k u e2)
end.
(** We also define a notation for [open_rec].
*)
Notation "{ k ~> u } t" := (open_rec k u t) (at level 67).
(** Many common applications of opening replace index zero with an
expression or variable. The following definition provides a
convenient shorthand for such uses. Note that the order of
arguments is switched relative to the definition above. For
example, [(open e x)] can be read as "substitute the variable [x]
for index [0] in [e]" and "open [e] with the variable [x]."
Recall that the coercions above let us write [x] in place of
[(fvar x)].
*)
Definition open e u := open_rec 0 u e.
(** This next demo shows the operation of 'open'. For example, the
locally nameless representation of the term (\y. (\x. (y x)) y)
is [abs (app (abs (app 1 0)) 0)]. To look at the body
without the outer abstraction, we need to replace the indices that
refer to that abstraction with a name.
Therefore, we show that we can open the body of the abs above
with Y to produce [app (abs (app Y 0)) Y)].
*)
Lemma demo_open :
open (app (abs (app 1 0)) 0) Y =
(app (abs (app Y 0)) Y).
Proof.
(* To show the equality of the two sides below, use the tactics
[unfold], which replaces a definition with its RHS and reduces
it to head form, and [simpl], which reduces the term the rest
of the way.
Then finish up with [auto].
*)
Admitted.
(*************************************************************************)
(* *)
(* Stretch break (5 mins) *)
(* *)
(*************************************************************************)
(*************************************************************************)
(** * Local closure *)
(*************************************************************************)
(** Recall that [exp] admits terms that contain unbound indices.
We say that a term is locally closed,
when no indices appearing in it are unbound. The proposition
[lc e] holds when an expression [e] is locally closed.
The inductive definition below formalizes local closure such that
the resulting induction principle serves as the structural
induction principle over (locally closed) expressions. In
particular, unlike induction for type exp, there is no cases
for bound variables. Thus, the induction principle corresponds more
closely to informal practice than the one arising from the
definition of pre-terms.
*)
Inductive lc : exp -> Prop :=
| lc_var : forall x,
lc (fvar x)
| lc_abs : forall (x:atom) e,
lc (open e x) ->
lc (abs e)
| lc_app : forall e1 e2,
lc e1 ->
lc e2 ->
lc (app e1 e2).
Hint Constructors lc.
(*************************************************************************)
(** Properties about basic operations *)
(*************************************************************************)
(** The first property we would like to show is the analogue to subst_fresh:
that index substitution has no effect for closed terms.
Here is an initial attempt at the proof.
*)
Lemma open_rec_lc_0 : forall k u e,
lc e ->
e = {k ~> u} e.
Proof.
intros k u e LC.
induction LC.
Case "lc_fvar".
simpl. auto.
Case "lc_abs".
simpl.
f_equal.
Admitted.
(** At this point there are two problems. Our goal is about substitution
for index [S k] in term [e], while our induction hypothesis IHLC only
tells use about index [k] in term [open e x].
To solve the first problem, we generalize our IH over all k.
That way, when k is incremented in the abs case, it will still apply.
Below, we use the tactic [generalize dependent] to generalize over
[k] before using induction.
*)
Lemma open_rec_lc_1 : forall k u e,
lc e ->
e = {k ~> u} e.
Proof.
intros k u e LC.
generalize dependent k.
induction LC.
Case "lc_fvar".
simpl. auto.
Case "lc_abs".
simpl.
intro k.
f_equal.
Admitted.
(** At this point we are still stuck because the IH concerns
[open e x] instead of [e]. The result that
we need is that if an index substitution has no effect for
an opened term, then it has no effect for the raw term (as long
as we are *not* substituting for 0, hence S k below).
<<
open e x = {S k ~> u}(open e x) -> e = {S k ~> u} e
>>
In other words, expanding the definition of open:
<<
{0 ~> x}e = {S k ~> u}({0 ~> x} e) -> e = {S k ~> u} e
>>
Of course, to prove this result, we must generalize
0 and S k to be any pair of inequal numbers to get a strong
enough induction hypothesis for the abs case.
*)
Lemma open_rec_lc_core : forall e j v i u,
i <> j ->
{j ~> v} e = {i ~> u} ({j ~> v} e) ->
e = {i ~> u} e.
Proof.
induction e; intros j v i u Neq H; simpl in *.
Case "bvar".
destruct (j === n); destruct (i === n).
Case "j = n = i".
subst n. destruct Neq. auto.
Case "j = n, i <> n".
auto.
Case "j <> n, i = n".
subst n. simpl in H. destruct (i === i). auto. destruct n. auto.
Case "j <> n, i <> n".
auto.
Case "fvar".
auto.
Case "abs".
f_equal.
inversion H.
apply IHe with (j := S j) (u := u) (i := S i) (v := v).
auto.
auto.
Case "app".
inversion H.
f_equal.
eapply IHe1; eauto.
eapply IHe2; eauto.
Qed.
(** With the help of this lemma, we can complete the proof. *)
Lemma open_rec_lc : forall k u e,
lc e ->
e = {k ~> u} e.
Proof.
intros k u e LC.
generalize dependent k.
induction LC.
Case "lc_fvar".
simpl. auto.
Case "lc_abs".
simpl.
intro k.
f_equal.
unfold open in *.
apply open_rec_lc_core with (i := S k) (j := 0) (u := u) (v := x). auto. auto.
Case "lc_app".
intro k. simpl. f_equal. auto. auto.
Qed.
(** *** Take-home Exercise [subst_open_rec] *)
(** The next lemma demonstrates that free variable substitution
distributes over index substitution.
The proof of this lemma is by straightforward induction over
e1. When e1 is a free variable, we need to appeal to
[open_rec_lc], proved above.
*)
Lemma subst_open_rec : forall e1 e2 u x k,
lc u ->
[x ~> u] ({k ~> e2} e1) = {k ~> [x ~> u] e2} ([x ~> u] e1).
Proof.
(* Fill in proof.*)
Admitted.
(** *** Exercise [subst_open_var] *)
(** The lemma above is most often used with k = 0 and
e2 as some fresh variable. Therefore, it simplifies matters
to define the following useful corollary.
*)
Lemma subst_open_var : forall (x y : atom) u e,
y <> x ->
lc u ->
open ([x ~> u] e) y = [x ~> u] (open e y).
Proof.
(* Fill in proof. *)
(* HINT: Do not use induction.
Rewrite with [subst_open_rec] and destruct (y==x). *)
Admitted.
(*************************************************************************)
(** Cofinite quantification *)
(*************************************************************************)
(* In the next example, we will reexamine the definition of
[lc] in the abs case.
The lemma [subst_lc] says that local closure is preserved by
substitution. Let's start working through this proof.
*)
Lemma subst_lc_1 : forall (x : atom) u e,
lc e ->
lc u ->
lc ([x ~> u] e).
Proof.
intros x u e He Hu.
induction He.
Case "lc_fvar".
simpl.
destruct (x0 == x).
auto.
auto.
Case "lc_abs".
simpl.
Print lc_abs.
apply lc_abs with (x:=x0).
Print subst_open_var.
rewrite subst_open_var with (x:=x)(y:=x0).
auto.
Admitted.
(** Here we are stuck. We don't know that x0 is not the same as x.
The solution is to change the *definition* of local closure so that
we get a different induction principle. Currently, in the lc_abs
case, we show that an abstraction is locally closed by showing
that the body is locally closed, after it has been opened with
one particular variable.
<<
| lc_abs : forall (x:atom) e,
lc (open e x) ->
lc (abs e)
>>
Therefore, our induction hypothesis in this case only applies to that
variable. From the hypothesis list in the abs case:
x0 : atom
IHHe : lc ([x ~> u]open e x0)
The problem is that we don't have any assumptions about x0. It
could very well be equal to x.
A stronger induction principle provides an IH that applies to many
variables. In that case, we could pick one that is "fresh enough".
To do so, we need to edit the above definition of lc and
replace the type of lc_abs with this one:
<<
| lc_abs : forall L e,
(forall x:atom, x `notin` L -> lc (open e x)) ->
lc (abs e)
>>
This rule says that to show that an abstraction is locally closed,
we need to show that the body is closed, after it has been opened
by any atom x, *except* those in some set L. With this rule, the
IH in this proof is now:
H0 : forall x0 : atom, x0 `notin` L -> lc ([x ~> u]open e x0)
We call this "cofinite quantification" because the IH applies to
an infinite number of atoms x0, except those in some finite set L.
Changing the rule in this way does not change what terms are locally
closed. (For more details about cofinite-quantification see:
"Engineering Formal Metatheory", Aydemir, Chargu\u00e9raud, Pierce,
Pollack, Weirich. POPL 2008.)
So to complete this proof, make the change to lc_abs above. Note,
that you will need to go back to the proof of [open_rec_lc] and
patch it as well. To fix that proof, add the line
[pick fresh x for L.] immediately before [apply open_rec_lc_core].
This tactic, defined in [Metatheory], introduces a new atom [x] that
is known not to be in the set [L].
You will also have to comment out [subst_lc_1].
Once these changes have been made, we can complete the proof
of subst_lc.
*)
Lemma subst_lc : forall (x : atom) u e,
lc e ->
lc u ->
lc ([x ~> u] e).
Proof.
intros x u e He Hu.
induction He.
Case "lc_var".
simpl.
destruct (x0 == x).
auto.
auto.
Case "lc_abs".
simpl.
(* Finish the proof. *)
(* HINT: apply lc_abs with (L := L `union` singleton x). *)
(* This gives us an atom x0, and a hypothesis that
x0 is fresh for both L and x. *)
Admitted.
(*************************************************************************)
(** * Tactic support *)
(*************************************************************************)
(** When picking a fresh atom or applying a rule that uses cofinite
quantification, choosing a set of atoms to be fresh for can be
tedious. In practice, it is simpler to use a tactic to choose the
set to be as large as possible.
The first tactic we define, [gather_atoms], is used to collect
together all the atoms in the context. It relies on an auxiliary
tactic from [Atom.v], [gather_atoms_with], which collects together
the atoms appearing in objects of a certain type. The argument to
[gather_atoms_with] is a function that should return the set of
atoms appearing in its argument. *)
Ltac gather_atoms :=
let A := gather_atoms_with (fun x : atoms => x) in
let B := gather_atoms_with (fun x : atom => singleton x) in
let C := gather_atoms_with (fun x : list (atom * typ) => dom x) in
let D := gather_atoms_with (fun x : exp => fv x) in
constr:(A `union` B `union` C `union` D).
(** We can use [gather_atoms] to define a variant of the [(pick fresh
x for L)] tactic, which we call [(pick fresh x)]. The tactic
chooses an atom fresh for "everything" in the context. *)
Tactic Notation "pick" "fresh" ident(x) :=
let L := gather_atoms in
(pick fresh x for L).
(** We can also use [gather_atoms] to define a tactic for applying a
rule that is defined using cofinite quantification. The tactic
[(pick fresh x and apply H)] applies a rule [H], just as the
[apply] tactic would. However, the tactic also picks a
sufficiently fresh name [x] to use.
Note: We define this tactic in terms of another tactic, [(pick
fresh x excluding L and apply H)], which is defined and documented
in [Metatheory.v]. *)
Tactic Notation
"pick" "fresh" ident(atom_name) "and" "apply" constr(lemma) :=
let L := gather_atoms in
pick fresh atom_name excluding L and apply lemma.
(** *** Example
Below, we reprove [subst_lc] using [(pick fresh and apply)].
Step through the proof below to see how [(pick fresh and apply)]
works. *)
Lemma subst_lc_alternate_proof : forall (x : atom) u e,
lc e ->
lc u ->
lc ([x ~> u] e).
Proof.
intros x u e He Hu.
induction He.
Case "fvar".
simpl.
destruct (x0 == x).
auto.
auto.
Case "abs".
simpl.
pick fresh y and apply lc_abs.
(* Here, take note of the hypothesis [Fr]. *)
rewrite subst_open_var. auto. auto. auto.
Case "app".
simpl. auto.
Qed.
(*************************************************************************)
(* *)
(* Coffee break (30 mins) *)
(* *)
(*************************************************************************)
(*************************************************************************)
(** * Typing environments *)
(*************************************************************************)
(** We represent environments as association lists (lists of pairs of
keys and values) whose keys are [atom]s. New bindings are added
to the head of the list.
Lists are defined in Coq's standard library. *)
Print list.
(** Here, environments bind [atom]s to [typ]s. We define an
abbreviation [env] for the type of these environments. Coq will
print [list (atom * typ)] as [env], and we can use [env] as a
shorthand for writing [list (atom * typ)]. *)
Notation env := (list (atom * typ)).
(** The [Environment] library, which is included by the [Metatheory]
library, provides functions, predicates, tactics, and lemmas that
simplify working with environments. Note that everything in the
library is polymorphic over the type of objects bound in the
environment. Look in [Environment.v] for additional details about
the functions and predicates that we mention below.
The function [dom] computes the domain of an environment,
returning a finite set of [atom]s. *)
Check dom.
(** The unary predicate [ok] holds when each atom is bound at most
once in an environment. *)
Print ok.
(** The ternary predicate [binds] holds when a given binding is
present in an environment. More specifically, [binds x a E] holds
when the binding for [x] closest to the head of [E] binds [x] to
[a]. *)
Check binds.
(*************************************************************************)
(** * Typing relation *)
(*************************************************************************)
(** The definition of the typing relation is straightforward. In
order to ensure that the relation holds for only well-formed
environments, we check in the [typing_var] case that the
environment is [ok]. The structure of typing derivations
implicitly ensures that the relation holds only for locally closed
expressions. Finally, note the use of cofinite quantification in
the [typing_abs] case. *)
Inductive typing : env -> exp -> typ -> Prop :=
| typing_var : forall E (x : atom) T,
ok E ->
binds x T E ->
typing E (fvar x) T
| typing_abs : forall L E e T1 T2,
(forall x : atom, x `notin` L ->
typing ((x, T1) :: E) (open e x) T2) ->
typing E (abs e) (typ_arrow T1 T2)
| typing_app : forall E e1 e2 T1 T2,
typing E e1 (typ_arrow T1 T2) ->
typing E e2 T1 ->
typing E (app e1 e2) T2.
(** We add the constructors of the typing relation as hints to be used
by the [auto] and [eauto] tactics. *)
Hint Constructors typing.
(*************************************************************************)
(** * Weakening *)
(*************************************************************************)
(** Weakening states that if an expression is typeable in some
environment, then it is typeable in any well-formed extension of
that environment. This property is needed to prove the
substitution lemma.
As stated below, this lemma is not directly proveable. The
natural way to try proving this lemma proceeds by induction on the
typing derivation for [e]. *)
Lemma typing_weakening_0 : forall E F e T,
typing E e T ->
ok (F ++ E) ->
typing (F ++ E) e T.
Proof.
intros E F e T H J.
induction H; eauto.
Case "typing_abs".
pick fresh x and apply typing_abs.
(* ... stuck here ... *)
Admitted.
(** We are stuck in the [typing_abs] case because the induction
hypothesis [H0] applies only when we weaken the environment at its
head. In this case, however, we need to weaken the environment in
the middle; compare the conclusion at the point where we're stuck
to the hypothesis [H], which comes from the given typing derivation.
We can obtain a more useful induction hypothesis by changing the
statement to insert new bindings into the middle of the
environment, instead of at the head. However, the proof still
gets stuck, as can be seen by examining each of the cases in
the proof below.
Note: To view subgoal n in a proof, use the command "[Show n]".
To work on subgoal n instead of the first one, use the command
"[Focus n]". *)
Lemma typing_weakening_strengthened_0 : forall E F G e T,
typing (G ++ E) e T ->
ok (G ++ F ++ E) ->
typing (G ++ F ++ E) e T.
Proof.
intros E F G e T H J.
induction H.
(* ... the E0 looks strange in the [typing_var] case ... *)
(* ... the [typing_abs] case still does not have a strong enough IH ... *)
Admitted.
(** The hypotheses in the [typing_var] case include an environment
[E0] that that has no relation to what we need to prove. The
missing fact we need is that [E0 = (G ++ E)].
The problem here arises from the fact that Coq's [induction]
tactic let's us only prove something about all typing derivations.
While it's clear to us that weakening applies to all typing
derivations, it's not clear to Coq, because the environment is
written using concatenation. The [induction] tactic expects that
all arguments to a judgement are variables. So we see [E0] in the
proof instead of [(G ++ E)].
The solution is to restate the lemma. For example, we can prove
<<
forall E F E' e T, typing E' e T ->
forall G, E' = G ++ E -> ok (G ++ F ++ E) -> typing (G ++ F ++ E) e T.
>>
The equality gets around the problem with Coq's [induction]
tactic. The placement of the [(forall G)] quantifier gives us a
sufficiently strong induction hypothesis in the [typing_abs] case.
However, we prefer not to state the lemma in the way shown above,
since it is not as readable as the original statement. Instead,
we use a tactic to introduce the equality within the proof itself.
The tactic [(remember t as t')] replaces an object [t] with the
identifier [t'] everywhere in the goal and introduces an equality
[t' = t] into the context. It is often combined with [generalize
dependent], as illustrated below. *)
(** *** Exercise
See how we use [remember as] in the proof below for weakening.
Then, complete the proof. *)
Lemma typing_weakening_strengthened : forall E F G e T,
typing (G ++ E) e T ->
ok (G ++ F ++ E) ->
typing (G ++ F ++ E) e T.
Proof.
intros E F G e T H.
remember (G ++ E) as E'.
generalize dependent G.
induction H; intros G Eq Ok; subst.
(* Finish the proof. *)
(* HINTS:
- The [typing_var] case follows from [binds_weaken], the weakening
lemma for the [binds] relation.
- The [typing_abs] case follows from the induction hypothesis, but the
[apply] tactic may be unable to unify things as you might expect.
-- Recall the [pick fresh and apply] tactic.
-- In order to apply the induction hypothesis, use
[cons_concat_assoc] in the [<-] direction to reassociate
the list operations.
-- After applying the induction hypothesis, use [cons_concat_assoc]
in the [->] direction in order to use [ok_cons].
-- Here, use [auto] to solve facts about finite sets of atoms.
[fsetdec] does not work with the [dom] function.
- The [typing_app] case follows directly from the induction
hypotheses.
*)
Admitted.
(** *** Example
We can now prove our original statement of weakening. The only
interesting step is the use of the lemma [nil_concat], which is
defined in [Environment.v]. *)
Lemma typing_weakening : forall E F e T,
typing E e T ->
ok (F ++ E) ->
typing (F ++ E) e T.
Proof.
intros E F e T H J.
rewrite <- (nil_concat _ (F ++ E)).
apply typing_weakening_strengthened; auto.
Qed.
(*************************************************************************)
(** * Substitution *)
(*************************************************************************)
(** Having proved weakening, we can now prove the usual substitution
lemma, which we state both in the form we need and in the
strengthened form needed to make the proof go through.
<<
typing_subst : forall E e u S T z,
typing ((z, S) :: E) e T ->
typing E u S ->
typing E ([z ~> u] e) T
typing_subst_strengthened : forall E F e u S T z,
typing (F ++ (z, S) :: E) e T ->
typing E u S ->
typing (F ++ E) ([z ~> u] e) T
>>
The proof of the strengthened statement proceeds by induction on
the given typing derivation for [e]. The most involved case is
the one for variables; the others follow from the induction
hypotheses. *)
(** *** Exercise
Below, we state what needs to be proved in the [typing_var] case
of the substitution lemma. Fill in the proof.
Proof sketch: The proof proceeds by a case analysis on [(x == z)],
i.e., whether the two variables are the same or not.
- If [(x = z)], then we need to show [(typing (F ++ E) u T)].
This follows from the given typing derivation for [u] by
weakening and the fact that [T] must equal [S].
- If [(x <> z)], then we need to show [(typing (F ++ E) x T)].
This follows by the typing rule for variables. *)
Lemma typing_subst_var_case : forall E F u S T z x,
binds x T (F ++ (z, S) :: E) ->
ok (F ++ (z, S) :: E) ->
typing E u S ->
typing (F ++ E) ([z ~> u] x) T.
Proof.
intros E F u S T z x H J K.
simpl.
(* Finish the proof. *)
(* HINTS:
- In the case where [x=z], use [binds_mid_eq_cons] to conclude
that [T=S].
- In both cases, the lemmas [ok_remove_mid_cons] and
[binds_remove_mid_cons] will be useful for reasoning about
[ok] and [binds].
*)
Admitted.
(** *** Note
The other two cases of the proof of the substitution lemma are
relatively straightforward. However, the case for [typing_abs]
needs the fact that the typing relation holds only for
locally-closed expressions. *)
Lemma typing_regular_lc : forall E e T,
typing E e T -> lc e.
Proof.
intros E e T H. induction H; eauto.
Qed.
(** *** Exercise
Complete the proof of the substitution lemma. The proof proceeds
by induction on the typing derivation for [e]. The initial steps
should use [remember as] and [generalize dependent] in a manner
similar to the proof of weakening. *)
Lemma typing_subst_strengthened : forall E F e u S T z,
typing (F ++ (z, S) :: E) e T ->
typing E u S ->
typing (F ++ E) ([z ~> u] e) T.
Proof.
(* Fill in this proof. *)
(* HINTS:
- Use the lemma proved above for the [typing_var] case.
- The [typing_abs] case follows from the induction hypothesis.
-- Use [simpl] to simplify the substitution.
-- Recall the tactic [pick fresh and apply].
-- In order to use the induction hypothesis, use [subst_open_var]
to push the substitution under the opening operation.
-- Recall the lemmas [typing_regular_lc] and [cons_concat_assoc].
- The [typing_app] case follows from the induction hypotheses.
Use [simpl] to simplify the substitution.
*)
Admitted.
(** *** Exercise
Complete the proof of the substitution lemma stated in the form we
need it. The proof is similar to that of [typing_weakening]. In
particular, recall the lemma [nil_concat]. *)
Lemma typing_subst : forall E e u S T z,
typing ((z, S) :: E) e T ->
typing E u S ->
typing E ([z ~> u] e) T.
Proof.
(* Fill in this proof. *)
(* HINT: You'll need to use [nil_concat] twice, once to prepend [nil],
and once to simplify it away. *)
Admitted.
(*************************************************************************)
(** * Values and Evaluation *)
(*************************************************************************)
(** In order to state the preservation lemma, we first need to define
values and the small-step evaluation relation. These inductive
relations are straightforward to define.
Note the hypotheses which ensure that the relations hold only for
locally closed terms. Below, we prove that this is actually the
case, since it is not completely obvious from the definitions
alone. *)
Inductive value : exp -> Prop :=
| value_abs : forall e,
lc (abs e) ->
value (abs e).
Inductive eval : exp -> exp -> Prop :=
| eval_beta : forall e1 e2,
lc (abs e1) ->
value e2 ->
eval (app (abs e1) e2) (open e1 e2)
| eval_app_1 : forall e1 e1' e2,
lc e2 ->
eval e1 e1' ->
eval (app e1 e2) (app e1' e2)
| eval_app_2 : forall e1 e2 e2',
value e1 ->
eval e2 e2' ->
eval (app e1 e2) (app e1 e2').
(** We add the constructors for these two relations as hints to be used
by Coq's [auto] and [eauto] tactics. *)
Hint Constructors value eval.
(*************************************************************************)
(** * Preservation *)
(*************************************************************************)
(** *** Note
In order to prove preservation, we need one more lemma, which
states that when we open a term, we can instead open the term with
a fresh variable and then substitute for that variable.
Technically, the [(lc u)] hypothesis is not needed to prove the
conclusion. However, it makes the proof simpler. *)
Lemma subst_intro : forall (x : atom) u e,
x `notin` (fv e) ->
lc u ->
open e u = [x ~> u](open e x).
Proof.
intros x u e H J.
unfold open.
rewrite subst_open_rec; auto.
simpl.
destruct (x == x).
Case "x = x".
rewrite subst_fresh; auto.
Case "x <> x".
destruct n; auto.
Qed.
(** *** Exercise
Complete the proof of preservation. In this proof, we proceed by
induction on the given typing derivation. The induction
hypothesis has already been appropriately generalized by the given
proof fragment.
Proof sketch: By induction on the typing derivation for [e].
- [typing_var] case: Variables don't step.
- [typing_abs] case: Abstractions don't step.
- [typing_app] case: By case analysis on how [e] steps. The
[eval_beta] case is interesting, since it follows by the
substitution lemma. The others follow directly from the
induction hypotheses. *)
Lemma preservation : forall E e e' T,
typing E e T ->
eval e e' ->
typing E e' T.
Proof.
intros E e e' T H.
generalize dependent e'.
induction H; intros e' J.
(* Finish the proof. *)
(* HINTS:
- Use [auto] and [eauto], especially with [;], to solve
"uninteresting" subgoals.
- Use [inversion] to perform case analyses and to rule out
impossible cases.
- In the [eval_beta] subcase of the [typing_app] case:
-- Use [inversion] on a typing judgement to obtain a
hypothesis about when the body of the abstraction is
well-typed.
-- Use [subst_intro] to rewrite the [open] operation into an
[open] followed by a [subst]. You'll need to pick a
fresh variable first.
-- The lemma [typing_regular_lc] will be useful to reason
about local closure.
*)
Admitted.
(*************************************************************************)
(** * Progress *)
(*************************************************************************)
(** *** Exercise
Complete the proof of the progress lemma. The induction
hypothesis has already been appropriately generalized by the given
proof fragment.
Proof sketch: By induction on the typing derivation for [e].
- [typing_var] case: Can't happen; the empty environment doesn't
bind anything.
- [typing_abs] case: Abstractions are values.
- [typing_app] case: Applications reduce. The result follows
from an exhaustive case analysis on whether the two components
of the application step or are values and the fact that a
value must be an abstraction. *)
Lemma progress : forall e T,
typing nil e T ->
value e \/ exists e', eval e e'.
Proof.
intros e T H.
(* It will be useful to have a "non-destructed" form of the given
typing derivation, since [induction] takes apart the derivation
it is called on. *)
assert (typing nil e T); auto.
(* [remember nil as E] fails here because [nil] takes an implicit
argument that Coq is unable to infer. By prefixing [nil] with
[@], we can supply the argument to nil explicitly. *)
remember (@nil (atom * typ)) as E.
induction H; subst.
(* Finish the proof. *)
(* HINTS:
- Use [auto] and [eauto], especially with [;], to solve
"uninteresting" subgoals.
- Use [inversion] to rule out impossible cases.
- The lemma [typing_regular_lc] will be useful for reasoning
about local closure.
- In the [typing_app] case:
-- Use [destruct] to perform a case analysis on the
conclusions of the induction hypotheses.
-- Use [inversion] on a [value] judgement to determine that
the value must be an abstraction.
*)
Admitted.
(*************************************************************************)
(** * Additional properties *)
(*************************************************************************)
(** While none of the lemmas below are needed to prove preservation or
progress, they verify that our relations do indeed hold only for
locally closed expressions. This serves as a check that we have
correctly defined the relations. *)
(** *** Example
The lemma directly below, [open_abs], is needed to show that the
evaluation relation holds only for locally closed terms. The
proof is straightforward, but we can use it to illustrate another
feature of Coq's tactic language.
If we start a proof with "[Proof with tac]" instead of simply
"[Proof]", every time we end a step with "[...]", Coq will
automatically apply [tac] to all the subgoals generated by that
step. This makes proof scripts somewhat more concise without
hiding the details of the proof script in some far away
location. *)
Lemma open_abs : forall e u,
lc (abs e) ->
lc u ->
lc (open e u).
Proof with auto using subst_lc.
intros e u H J.
inversion H; subst.
pick fresh y.
rewrite (subst_intro y)...
(* The previous line is equivalent to:
[rewrite (subst_intro y); auto using subst_lc] *)
Qed.
(** *** Note
The three lemmas below are straightforward to prove. They do not
illustrate any new concepts or tactics. *)
Lemma value_regular : forall e,
value e -> lc e.
Proof.
intros e H. induction H; auto.
Qed.
Lemma eval_regular : forall e1 e2,
eval e1 e2 -> lc e1 /\ lc e2.
Proof.
intros e1 e2 H. induction H; intuition; auto using value_regular, open_abs.
Qed.
Lemma typing_regular_ok : forall E e T,
typing E e T -> ok E.
Proof with auto.
induction 1...
Case "typing_abs".
pick fresh x.
assert (ok ((x, T1) :: E))...
inversion H1...
Qed.
(*
*** Local Variables: ***
*** coq-prog-name: "coqtop" ***
*** coq-prog-args: ("-emacs-U") ***
*** End: ***
*)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_TB_V
`define SKY130_FD_SC_MS__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_TB_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_test_expr;
assign valid_test_expr = ~((^test_expr) ^ (^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
reg [width-1:0] last_test_expr;
reg [width:0] temp_expr;
reg r_reset_n;
`ifdef OVL_SYNTHESIS
`else
initial begin
r_reset_n = 1'b0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
r_reset_n <= `OVL_RESET_SIGNAL;
last_test_expr <= test_expr;
// check second clock after reset
if (r_reset_n && (last_test_expr != test_expr)) begin
temp_expr = {1'b0,last_test_expr} - {1'b0,test_expr};
// 2's complement result
if (temp_expr[width-1:0] != value) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is decreased by a value other than specified");
end
end
end
else begin
r_reset_n <= 0;
`ifdef OVL_INIT_REG
last_test_expr <= {width{1'b0}};
temp_expr = {(width+1){1'b0}};
`endif
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @(posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
reg [width-1:0] prev_test_expr;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if (test_expr != prev_test_expr) begin
ovl_cover_t("test_expr_change covered");
end
prev_test_expr <= test_expr;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_test_expr <= {width{1'b0}};
`endif
end
end //always
`endif // OVL_COVER_ON
|
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//************************************************************//
// - a lot work in progress, many thing are useless
// TODO: clean this up and make it more general
// TODO: add comments
//************************************************************//
module spoof(
instruction_opcode,
ex_freeze,
clk_in,
data_out,
reset,
debug_out
);
input [31:0] instruction_opcode;
input ex_freeze;
input clk_in;
input reset;
output data_out;
output debug_out;
localparam STATE_Initial = 3'd0,
STATE_1 = 3'd1,
STATE_2 = 3'd2,
STATE_3 = 3'd3,
STATE_4 = 3'd4,
STATE_5_Placeholder = 3'd5,
STATE_6_Placeholder = 3'd6,
STATE_7_Placeholder = 3'd7;
//OPCODES for sequence recognition
localparam OPCODE_A = 32'h15000000,
OPCODE_B = 32'h15000000,
OPCODE_C = 32'h15000000,
OPCODE_D = 32'h15000000;
wire [31:0] instruction_opcode;
wire ex_freeze;
wire clk_in;
wire reset;
reg data_out;
//state registers
reg[2:0] CurrentState;
reg[2:0] NextState;
reg[31:0] FirstOp;
reg[31:0] FirstOp_Next;
reg[31:0] SecondOp;
reg[31:0] SecondOp_Next;
reg[31:0] ThirdOp;
reg[31:0] ThirdOp_Next;
reg[31:0] CurrentOp;
reg[31:0] debug_out;
//synchronous state transition
always@ (posedge clk_in)
begin: STATE_TRANS
if(reset)
begin
CurrentState <= STATE_Initial;
FirstOp <= 32'h00000000;
SecondOp <= 32'h00000000;
ThirdOp <= 32'h00000000;
end
else
begin
CurrentState <= NextState;
FirstOp <= FirstOp_Next;
SecondOp <= SecondOp_Next;
ThirdOp <= ThirdOp_Next;
end
end
//conditional state transition
always@ (*)
begin
if(ex_freeze) begin
NextState <= CurrentState;
FirstOp_Next <= FirstOp;
SecondOp_Next <= SecondOp;
ThirdOp_Next <= ThirdOp;
end
else begin
FirstOp_Next <= SecondOp;
SecondOp_Next <= ThirdOp;
ThirdOp_Next <= instruction_opcode;
case(CurrentState)
STATE_Initial: begin
NextState <= STATE_1;
end
STATE_1: begin
NextState <= STATE_2;
end
STATE_2: begin
NextState <= STATE_3;
end
STATE_3: begin
if(instruction_opcode == OPCODE_D && FirstOp == OPCODE_A && SecondOp == OPCODE_B && ThirdOp == OPCODE_C) NextState <= STATE_4;
else NextState <= STATE_3;
end
STATE_4: begin
NextState <= STATE_3;
end
STATE_5_Placeholder: begin
end
STATE_6_Placeholder: begin
end
STATE_7_Placeholder: begin
end
endcase
end
end
//output
always@ (*)
begin
data_out = 1'b0;
debug_out <= FirstOp;
if(CurrentState == STATE_4) data_out = 1'b1;
end
endmodule
|
// ---------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- ------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// ---------------------------------------------------------------------------
// -- --
// -- This stage converts register indices into actual values. Register --
// -- indices are also pumped forward to allow resolution in the shift --
// -- stage. PC references must be resolved here since the value gives --
// -- PC + 8. Instructions requiring shifts stall if the target registers --
// -- are in the outputs of this stage. We do not issue a multiply if the --
// -- source is still in the output of this stage just like shifts. That's --
// -- to ensure incorrect registers are not read. --
// -- --
// ---------------------------------------------------------------------------
`default_nettype none
module zap_issue_main
#(
// Parameters.
// Number of physical registers.
parameter PHY_REGS = 46,
// Although ARM mentions only 16 ALU operations, the processor
// internally performs many more operations.
parameter ALU_OPS = 32,
// Number of supported shift operations.
parameter SHIFT_OPS = 5
)
(
// Decompile path
input wire [64*8-1:0] i_decompile,
output reg [64*8-1:0] o_decompile,
// PC in
input wire [31:0] i_pc_ff,
output reg [31:0] o_pc_ff,
// BP signals.
input wire [1:0] i_taken_ff,
output reg [1:0] o_taken_ff,
// Clock and reset.
input wire i_clk, // ZAP clock.
input wire i_reset, // Active high sync.
// CPSR.
input wire [31:0] i_cpu_mode,
// Clear and stall signals.
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
// From decode
input wire [31:0] i_pc_plus_8_ff,
// -----------------------------------
// Inputs from decode.
// Look at the decode stage for the
// meaning of these ports...
// -----------------------------------
input wire [3:0] i_condition_code_ff,
input wire [$clog2(PHY_REGS )-1:0] i_destination_index_ff,
input wire [32:0] i_alu_source_ff,
input wire [$clog2(ALU_OPS)-1:0] i_alu_operation_ff,
input wire [32:0] i_shift_source_ff,
input wire [$clog2(SHIFT_OPS)-1:0] i_shift_operation_ff,
input wire [32:0] i_shift_length_ff,
input wire i_flag_update_ff,
input wire [$clog2(PHY_REGS )-1:0] i_mem_srcdest_index_ff,
input wire i_mem_load_ff,
input wire i_mem_store_ff,
input wire i_mem_pre_index_ff,
input wire i_mem_unsigned_byte_enable_ff,
input wire i_mem_signed_byte_enable_ff,
input wire i_mem_signed_halfword_enable_ff,
input wire i_mem_unsigned_halfword_enable_ff,
input wire i_mem_translate_ff,
input wire i_irq_ff,
input wire i_fiq_ff,
input wire i_abt_ff,
input wire i_swi_ff,
// From register file. Read ports.
input wire [31:0] i_rd_data_0,
input wire [31:0] i_rd_data_1,
input wire [31:0] i_rd_data_2,
input wire [31:0] i_rd_data_3,
// Force 32 bit address alignment.
input wire i_force32align_ff,
output reg o_force32align_ff,
// For undefined instr.
input wire i_und_ff,
output reg o_und_ff,
// ---------------------
// Feedback Network
// ---------------------
//
// Destination index feedback. Each stage is represented as
// combinational logic followed by flops(FFs).
//
// The ALU never changes destination anyway. Destination from shifter.
input wire [$clog2(PHY_REGS )-1:0] i_shifter_destination_index_ff,
// Flopped destination from the ALU.
input wire [$clog2(PHY_REGS )-1:0] i_alu_destination_index_ff,
// Flopped destination from the memory stage.
input wire [$clog2(PHY_REGS )-1:0] i_memory_destination_index_ff,
//
// Data valid(dav) for each stage in the pipeline. Used to validate the
// pipeline vector when sniffing for register values yet to be written.
//
// Taken from alu_nxt instead of shifter_ff because ALU can invalidate
// instructions.
input wire i_alu_dav_nxt,
input wire i_alu_dav_ff,
input wire i_memory_dav_ff,
//
// The actual thing we need (i.e. data),
// the value of stuff we are looking for.
//
// Taken from alu_nxt since ALU can change this.
input wire [31:0] i_alu_destination_value_nxt,
// ALU flopped result.
input wire [31:0] i_alu_destination_value_ff,
// Result in the memory stage of the pipeline.
input wire [31:0] i_memory_destination_value_ff,
//
// For load-store locks and memory acceleration, we need srcdest
// index. Memory loads can be accelerated with a direct load from
// memory stage instead of register stage(WB).
//
input wire [5:0] i_shifter_mem_srcdest_index_ff,
input wire [5:0] i_alu_mem_srcdest_index_ff,
input wire [5:0] i_memory_mem_srcdest_index_ff,
input wire i_shifter_mem_load_ff,//1 if load.
input wire i_alu_mem_load_ff,
input wire i_memory_mem_load_ff,
// Memory accelerator values for loads. External memory bys is
// connected to this.
input wire [31:0] i_memory_mem_srcdest_value_ff,
// ARM to compressed switch.
input wire i_switch_ff,
output reg o_switch_ff,
// Outputs to register file.
output reg [$clog2(PHY_REGS )-1:0] o_rd_index_0,
output reg [$clog2(PHY_REGS )-1:0] o_rd_index_1,
output reg [$clog2(PHY_REGS )-1:0] o_rd_index_2,
output reg [$clog2(PHY_REGS )-1:0] o_rd_index_3,
// Outputs to shifter stage.
output reg [3:0] o_condition_code_ff,
output reg [$clog2(PHY_REGS )-1:0] o_destination_index_ff,
output reg [$clog2(ALU_OPS)-1:0] o_alu_operation_ff,
output reg [$clog2(SHIFT_OPS)-1:0] o_shift_operation_ff,
output reg o_flag_update_ff,
// Memory operation related.
output reg [$clog2(PHY_REGS )-1:0] o_mem_srcdest_index_ff,
output reg o_mem_load_ff,
output reg o_mem_store_ff,
output reg o_mem_pre_index_ff,
output reg o_mem_unsigned_byte_enable_ff,
output reg o_mem_signed_byte_enable_ff,
output reg o_mem_signed_halfword_enable_ff,
output reg o_mem_unsigned_halfword_enable_ff,
output reg o_mem_translate_ff,
// Interrupts.
output reg o_irq_ff,
output reg o_fiq_ff,
output reg o_abt_ff,
output reg o_swi_ff,
// Register values are given here.
// ALU source value would be the value of non-shifted operand in ARM.
output reg [31:0] o_alu_source_value_ff,
// Shifter source value would be the value of the operand to be shifted.
output reg [31:0] o_shift_source_value_ff,
// Shift length i.e., amount to shift i.e, shamt.
output reg [31:0] o_shift_length_value_ff,
// For stores, value to be stored.
output reg [31:0] o_mem_srcdest_value_ff,
//
// Indices/Immeds go here. It might seem odd that we are sending index
// values and register values (above). The issue stage selects
// the appropriate value. Note again that while the above are values,
// these are indexes/immediates.
//
output reg [32:0] o_alu_source_ff,
output reg [32:0] o_shift_source_ff,
// Stall everything before this if 1.
output reg o_stall_from_issue,
// The PC value.
output reg [31:0] o_pc_plus_8_ff,
//
// Shifter disable. In the next stage, the output
// will bypass the shifter. Not actually bypass it but will
// go to the ALU value corrector unit via a MUX essentially bypassing
// the shifter.
//
output reg o_shifter_disable_ff
);
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
reg o_shifter_disable_nxt;
reg [31:0] o_alu_source_value_nxt,
o_shift_source_value_nxt,
o_shift_length_value_nxt,
o_mem_srcdest_value_nxt;
// Individual lock signals. These are ORed to get the final lock.
reg shift_lock;
reg load_lock;
reg lock; // Asserted when an instruction cannot be issued and
// leads to all stages before it stalling.
always @*
lock = shift_lock | load_lock;
task clear;
begin
o_condition_code_ff <= NV;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_abt_ff <= 0;
o_swi_ff <= 0;
o_und_ff <= 0;
o_flag_update_ff <= 0;
end
endtask
always @ (posedge i_clk)
begin
if ( i_reset )
begin
reset;
clear;
end
else if ( i_clear_from_writeback )
begin
clear;
end
else if ( i_data_stall )
begin
// Preserve values.
end
else if ( i_clear_from_alu )
begin
clear;
end
else if ( i_stall_from_shifter )
begin
// Preserve values.
end
else if ( lock )
begin
clear;
end
else
begin
o_condition_code_ff <= i_condition_code_ff;
o_destination_index_ff <= i_destination_index_ff;
o_alu_operation_ff <= i_alu_operation_ff;
o_shift_operation_ff <= i_shift_operation_ff;
o_flag_update_ff <= i_flag_update_ff;
o_mem_srcdest_index_ff <= i_mem_srcdest_index_ff;
o_mem_load_ff <= i_mem_load_ff;
o_mem_store_ff <= i_mem_store_ff;
o_mem_pre_index_ff <= i_mem_pre_index_ff;
o_mem_unsigned_byte_enable_ff <= i_mem_unsigned_byte_enable_ff;
o_mem_signed_byte_enable_ff <= i_mem_signed_byte_enable_ff;
o_mem_signed_halfword_enable_ff <= i_mem_signed_halfword_enable_ff;
o_mem_unsigned_halfword_enable_ff <= i_mem_unsigned_halfword_enable_ff;
o_mem_translate_ff <= i_mem_translate_ff;
o_irq_ff <= i_irq_ff;
o_fiq_ff <= i_fiq_ff;
o_abt_ff <= i_abt_ff;
o_swi_ff <= i_swi_ff;
o_pc_plus_8_ff <= i_pc_plus_8_ff;
o_shifter_disable_ff <= o_shifter_disable_nxt;
o_alu_source_ff <= i_alu_source_ff;
o_shift_source_ff <= i_shift_source_ff;
o_alu_source_value_ff <= o_alu_source_value_nxt;
o_shift_source_value_ff <= o_shift_source_value_nxt;
o_shift_length_value_ff <= o_shift_length_value_nxt;
o_mem_srcdest_value_ff <= o_mem_srcdest_value_nxt;
o_switch_ff <= i_switch_ff;
o_force32align_ff <= i_force32align_ff;
o_und_ff <= i_und_ff;
o_taken_ff <= i_taken_ff;
o_pc_ff <= i_pc_ff;
// For debug
o_decompile <= i_decompile;
end
end
// Get values from the feedback network.
always @*
begin
o_alu_source_value_nxt =
get_register_value ( i_alu_source_ff,
0,
i_shifter_destination_index_ff,
i_alu_dav_nxt,
i_alu_destination_value_nxt,
i_alu_destination_value_ff,
i_alu_destination_index_ff,
i_alu_dav_ff,
i_memory_destination_index_ff,
i_memory_dav_ff,
i_memory_mem_srcdest_index_ff,
i_memory_mem_load_ff,
i_rd_data_0,
i_rd_data_1,
i_rd_data_2,
i_rd_data_3, i_memory_mem_srcdest_value_ff, i_cpu_mode, i_pc_plus_8_ff
);
o_shift_source_value_nxt=
get_register_value ( i_shift_source_ff,
1,
i_shifter_destination_index_ff,
i_alu_dav_nxt,
i_alu_destination_value_nxt,
i_alu_destination_value_ff,
i_alu_destination_index_ff,
i_alu_dav_ff,
i_memory_destination_index_ff,
i_memory_dav_ff,
i_memory_mem_srcdest_index_ff,
i_memory_mem_load_ff,
i_rd_data_0,
i_rd_data_1,
i_rd_data_2,
i_rd_data_3, i_memory_mem_srcdest_value_ff, i_cpu_mode, i_pc_plus_8_ff
);
o_shift_length_value_nxt=
get_register_value ( i_shift_length_ff,
2,
i_shifter_destination_index_ff,
i_alu_dav_nxt,
i_alu_destination_value_nxt,
i_alu_destination_value_ff,
i_alu_destination_index_ff,
i_alu_dav_ff,
i_memory_destination_index_ff,
i_memory_dav_ff,
i_memory_mem_srcdest_index_ff,
i_memory_mem_load_ff,
i_rd_data_0,
i_rd_data_1,
i_rd_data_2,
i_rd_data_3, i_memory_mem_srcdest_value_ff, i_cpu_mode, i_pc_plus_8_ff
);
// Value of a register index, never an immediate.
o_mem_srcdest_value_nxt =
get_register_value ( i_mem_srcdest_index_ff,
3,
i_shifter_destination_index_ff,
i_alu_dav_nxt,
i_alu_destination_value_nxt,
i_alu_destination_value_ff,
i_alu_destination_index_ff,
i_alu_dav_ff,
i_memory_destination_index_ff,
i_memory_dav_ff,
i_memory_mem_srcdest_index_ff,
i_memory_mem_load_ff,
i_rd_data_0,
i_rd_data_1,
i_rd_data_2,
i_rd_data_3, i_memory_mem_srcdest_value_ff, i_cpu_mode, i_pc_plus_8_ff
);
end
// Apply index to register file.
always @*
begin
o_rd_index_0 = i_alu_source_ff;
o_rd_index_1 = i_shift_source_ff;
o_rd_index_2 = i_shift_length_ff;
o_rd_index_3 = i_mem_srcdest_index_ff;
end
//
// Straightforward read feedback function. Looks at all stages of the pipeline
// to extract the latest value of the register.
// There is some complexity here to perform accelerated memory reads.
//
function [31:0] get_register_value (
// The register inex to search for. This might be a constant too.
input [32:0] index,
// Register read port activated for this function.
input [1:0] rd_port,
// Destination on the output of the shifter stage.
input [32:0] i_shifter_destination_index_ff,
// ALU output is valid.
input i_alu_dav_nxt,
// ALU output.
input [31:0] i_alu_destination_value_nxt,
// ALU flopped result.
input [31:0] i_alu_destination_value_ff,
// ALU flopped destination index.
input [$clog2(PHY_REGS)-1:0] i_alu_destination_index_ff,
// Valid flopped (EX stage).
input i_alu_dav_ff,
// Memory stage destination index (pointer)
input [$clog2(PHY_REGS)-1:0] i_memory_destination_index_ff,
// Memory stage valid.
input i_memory_dav_ff,
// Memory stage srcdest index. The srcdest is basically the data
// register index.
input [$clog2(PHY_REGS)-1:0] i_memory_mem_srcdest_index_ff,
// Memory load instruction in memory stage.
input i_memory_mem_load_ff,
// Data read from register file.
input [31:0] i_rd_data_0, i_rd_data_1, i_rd_data_2, i_rd_data_3,
i_memory_mem_srcdest_value_ff, i_cpu_mode, i_pc_plus_8_ff
);
reg [31:0] get;
begin
if ( index[32] ) // Catch constant here.
begin
get = index[31:0];
end
else if ( index == PHY_RAZ_REGISTER ) // Catch RAZ here.
begin
// Return 0.
get = 32'd0;
end
else if ( index == ARCH_PC ) // Catch PC here. ARCH index = PHY index so no problem.
begin
get = i_pc_plus_8_ff;
end
else if ( index == PHY_CPSR ) // Catch CPSR here.
begin
get = i_cpu_mode;
end
// Match in ALU stage.
else if ( index == i_shifter_destination_index_ff && i_alu_dav_nxt )
begin // ALU effectively never changes destination so no need to look at _nxt.
get = i_alu_destination_value_nxt;
end
// Match in output of ALU stage.
else if ( index == i_alu_destination_index_ff && i_alu_dav_ff )
begin
get = i_alu_destination_value_ff;
end
// Match in output of memory stage.
else if ( index == i_memory_destination_index_ff && i_memory_dav_ff )
begin
get = i_memory_destination_value_ff;
end
else // Index not found in the pipeline, fallback to register access.
begin
case ( rd_port )
0: get = i_rd_data_0;
1: get = i_rd_data_1;
2: get = i_rd_data_2;
3: get = i_rd_data_3;
endcase
end
// The memory accelerator. If the required stuff is present in the memory unit, short circuit.
if ( index == i_memory_mem_srcdest_index_ff && i_memory_mem_load_ff && i_memory_dav_ff )
begin
get = i_memory_mem_srcdest_value_ff;
end
get_register_value = get;
end
endfunction
// Stall all previous stages if a lock occurs.
always @*
begin
o_stall_from_issue = lock;
end
always @*
begin
// Look for reads from registers to be loaded from memory. Four
// register sources may cause a load lock.
load_lock = determine_load_lock
( i_alu_source_ff ,
o_mem_srcdest_index_ff,
o_condition_code_ff,
o_mem_load_ff,
i_shifter_mem_srcdest_index_ff,
i_alu_dav_nxt,
i_shifter_mem_load_ff,
i_alu_mem_srcdest_index_ff,
i_alu_dav_ff,
i_alu_mem_load_ff )
||
determine_load_lock
(
i_shift_source_ff,
o_mem_srcdest_index_ff,
o_condition_code_ff,
o_mem_load_ff,
i_shifter_mem_srcdest_index_ff,
i_alu_dav_nxt,
i_shifter_mem_load_ff,
i_alu_mem_srcdest_index_ff,
i_alu_dav_ff,
i_alu_mem_load_ff )
||
determine_load_lock
( i_shift_length_ff,
o_mem_srcdest_index_ff,
o_condition_code_ff,
o_mem_load_ff,
i_shifter_mem_srcdest_index_ff,
i_alu_dav_nxt,
i_shifter_mem_load_ff,
i_alu_mem_srcdest_index_ff,
i_alu_dav_ff,
i_alu_mem_load_ff )
||
determine_load_lock
( i_mem_srcdest_index_ff,
o_mem_srcdest_index_ff,
o_condition_code_ff,
o_mem_load_ff,
i_shifter_mem_srcdest_index_ff,
i_alu_dav_nxt,
i_shifter_mem_load_ff,
i_alu_mem_srcdest_index_ff,
i_alu_dav_ff,
i_alu_mem_load_ff );
// A shift lock occurs if the current instruction requires a shift amount as a register
// other than LSL #0 or RORI if the operands are right on the output of this
// stage because in that case we do not have the register value and thus
// a shift lock.
shift_lock = (!(
i_shift_operation_ff == LSL &&
i_shift_length_ff[31:0] == 32'd0 &&
i_shift_length_ff[32] == IMMED_EN
)
&& // If it is not LSL #0 AND...
!(
i_shift_operation_ff == RORI // The amount to rotate and rotate are self contained.
)
&& // If it is not RORI AND...
(
// Stuff is locked.
shifter_lock_check ( i_shift_source_ff, o_destination_index_ff, o_condition_code_ff ) ||
shifter_lock_check ( i_shift_length_ff, o_destination_index_ff, o_condition_code_ff ) ||
shifter_lock_check ( i_alu_source_ff , o_destination_index_ff, o_condition_code_ff )
)) ||
(
// If it is a multiply and stuff is locked.
(i_alu_operation_ff == UMLALL ||
i_alu_operation_ff == UMLALH ||
i_alu_operation_ff == SMLALL ||
i_alu_operation_ff == SMLALH) &&
(
shifter_lock_check ( i_shift_source_ff, o_destination_index_ff, o_condition_code_ff ) ||
shifter_lock_check ( i_shift_length_ff, o_destination_index_ff, o_condition_code_ff ) ||
shifter_lock_check ( i_alu_source_ff , o_destination_index_ff, o_condition_code_ff ) ||
shifter_lock_check ( i_mem_srcdest_index_ff, o_destination_index_ff, o_condition_code_ff )
)
) // If it is multiply (MAC).
||
( // If the instruction is not LSL #0 and previous instruction has flag
// updates, we stall.
!o_shifter_disable_nxt &&
o_flag_update_ff
);
end
always @*
begin
// Shifter disable.
o_shifter_disable_nxt = (
i_shift_operation_ff == LSL &&
i_shift_length_ff[31:0] == 32'd0 &&
i_shift_length_ff[32] == IMMED_EN
);
// If it is LSL #0, we can disable the shifter.
end
// ----------------------------------------------------------------------------
// Shifter lock check.
function shifter_lock_check (
input [32:0] index,
input [$clog2(PHY_REGS)-1:0] o_destination_index_ff,
input [3:0] o_condition_code_ff
);
begin
// Simply check if the operand index is on the output of this unit
// and that the output is valid.
if ( o_destination_index_ff == index && o_condition_code_ff != NV )
shifter_lock_check = 1'd1;
else
shifter_lock_check = 1'd0;
// If immediate, no lock obviously.
if ( index[32] == IMMED_EN || index == PHY_RAZ_REGISTER )
shifter_lock_check = 1'd0;
end
endfunction
// ----------------------------------------------------------------------------
// Load lock. Activated when a read from a register follows a load to that
// register.
function determine_load_lock (
input [32:0] index,
input [$clog2(PHY_REGS)-1:0] o_mem_srcdest_index_ff,
input [3:0] o_condition_code_ff,
input o_mem_load_ff,
input [$clog2(PHY_REGS)-1:0] i_shifter_mem_srcdest_index_ff,
input i_alu_dav_nxt,
input i_shifter_mem_load_ff,
input [$clog2(PHY_REGS)-1:0] i_alu_mem_srcdest_index_ff,
input i_alu_dav_ff,
input i_alu_mem_load_ff
);
begin
determine_load_lock = 1'd0;
// Look for that load instruction in the required pipeline stages.
// If found, we cannot issue the current instruction since old value
// will be read.
if (
( index == o_mem_srcdest_index_ff &&
o_condition_code_ff != NV &&
o_mem_load_ff ) ||
( index == i_shifter_mem_srcdest_index_ff &&
i_alu_dav_nxt &&
i_shifter_mem_load_ff ) ||
( index == i_alu_mem_srcdest_index_ff &&
i_alu_dav_ff &&
i_alu_mem_load_ff )
)
determine_load_lock = 1'd1;
// Locks occur only for indices...
if ( index[32] == IMMED_EN || index == PHY_RAZ_REGISTER )
determine_load_lock = 1'd0;
end
endfunction
task reset;
begin
o_condition_code_ff <= 0;
o_destination_index_ff <= 0;
o_alu_operation_ff <= 0;
o_shift_operation_ff <= 0;
o_flag_update_ff <= 0;
o_mem_srcdest_index_ff <= 0;
o_mem_load_ff <= 0;
o_mem_store_ff <= 0;
o_mem_pre_index_ff <= 0;
o_mem_unsigned_byte_enable_ff <= 0;
o_mem_signed_byte_enable_ff <= 0;
o_mem_signed_halfword_enable_ff <= 0;
o_mem_unsigned_halfword_enable_ff <= 0;
o_mem_translate_ff <= 0;
o_irq_ff <= 0;
o_fiq_ff <= 0;
o_abt_ff <= 0;
o_swi_ff <= 0;
o_pc_plus_8_ff <= 0;
o_shifter_disable_ff <= 0;
o_alu_source_ff <= 0;
o_shift_source_ff <= 0;
o_alu_source_value_ff <= 0;
o_shift_source_value_ff <= 0;
o_shift_length_value_ff <= 0;
o_mem_srcdest_value_ff <= 0;
o_switch_ff <= 0;
o_force32align_ff <= 0;
o_und_ff <= 0;
o_taken_ff <= 0;
o_pc_ff <= 0;
o_decompile <= 0;
end
endtask
endmodule // zap_issue_main.v
`default_nettype wire
// ----------------------------------------------------------------------------
|
//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_debugaccess,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_read,
cpu_0_jtag_debug_module_readdata,
cpu_0_jtag_debug_module_resetrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_jtag_debug_module_address,
cpu_0_jtag_debug_module_begintransfer,
cpu_0_jtag_debug_module_byteenable,
cpu_0_jtag_debug_module_chipselect,
cpu_0_jtag_debug_module_debugaccess,
cpu_0_jtag_debug_module_readdata_from_sa,
cpu_0_jtag_debug_module_reset_n,
cpu_0_jtag_debug_module_resetrequest_from_sa,
cpu_0_jtag_debug_module_write,
cpu_0_jtag_debug_module_writedata,
d1_cpu_0_jtag_debug_module_end_xfer
)
;
output cpu_0_data_master_granted_cpu_0_jtag_debug_module;
output cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_data_master_requests_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
output [ 8: 0] cpu_0_jtag_debug_module_address;
output cpu_0_jtag_debug_module_begintransfer;
output [ 3: 0] cpu_0_jtag_debug_module_byteenable;
output cpu_0_jtag_debug_module_chipselect;
output cpu_0_jtag_debug_module_debugaccess;
output [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
output cpu_0_jtag_debug_module_reset_n;
output cpu_0_jtag_debug_module_resetrequest_from_sa;
output cpu_0_jtag_debug_module_write;
output [ 31: 0] cpu_0_jtag_debug_module_writedata;
output d1_cpu_0_jtag_debug_module_end_xfer;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_debugaccess;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 23: 0] cpu_0_instruction_master_address_to_slave;
input [ 1: 0] cpu_0_instruction_master_latency_counter;
input cpu_0_instruction_master_read;
input [ 31: 0] cpu_0_jtag_debug_module_readdata;
input cpu_0_jtag_debug_module_resetrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_allgrants;
wire cpu_0_jtag_debug_module_allow_new_arb_cycle;
wire cpu_0_jtag_debug_module_any_bursting_master_saved_grant;
wire cpu_0_jtag_debug_module_any_continuerequest;
reg [ 1: 0] cpu_0_jtag_debug_module_arb_addend;
wire cpu_0_jtag_debug_module_arb_counter_enable;
reg [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter_next_value;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_set_values;
wire [ 1: 0] cpu_0_jtag_debug_module_arb_winner;
wire cpu_0_jtag_debug_module_arbitration_holdoff_internal;
wire cpu_0_jtag_debug_module_beginbursttransfer_internal;
wire cpu_0_jtag_debug_module_begins_xfer;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire [ 3: 0] cpu_0_jtag_debug_module_chosen_master_double_vector;
wire [ 1: 0] cpu_0_jtag_debug_module_chosen_master_rot_left;
wire cpu_0_jtag_debug_module_debugaccess;
wire cpu_0_jtag_debug_module_end_xfer;
wire cpu_0_jtag_debug_module_firsttransfer;
wire [ 1: 0] cpu_0_jtag_debug_module_grant_vector;
wire cpu_0_jtag_debug_module_in_a_read_cycle;
wire cpu_0_jtag_debug_module_in_a_write_cycle;
wire [ 1: 0] cpu_0_jtag_debug_module_master_qreq_vector;
wire cpu_0_jtag_debug_module_non_bursting_master_requests;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
reg cpu_0_jtag_debug_module_reg_firsttransfer;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
reg [ 1: 0] cpu_0_jtag_debug_module_saved_chosen_master_vector;
reg cpu_0_jtag_debug_module_slavearbiterlockenable;
wire cpu_0_jtag_debug_module_slavearbiterlockenable2;
wire cpu_0_jtag_debug_module_unreg_firsttransfer;
wire cpu_0_jtag_debug_module_waits_for_read;
wire cpu_0_jtag_debug_module_waits_for_write;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
reg d1_cpu_0_jtag_debug_module_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
reg last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
wire [ 23: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master;
wire [ 23: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master;
wire wait_for_cpu_0_jtag_debug_module_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~cpu_0_jtag_debug_module_end_xfer;
end
assign cpu_0_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module));
//assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata;
assign cpu_0_data_master_requests_cpu_0_jtag_debug_module = ({cpu_0_data_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
assign cpu_0_jtag_debug_module_arb_share_set_values = 1;
//cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
assign cpu_0_jtag_debug_module_non_bursting_master_requests = cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module |
cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
assign cpu_0_jtag_debug_module_any_bursting_master_saved_grant = 0;
//cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
assign cpu_0_jtag_debug_module_arb_share_counter_next_value = cpu_0_jtag_debug_module_firsttransfer ? (cpu_0_jtag_debug_module_arb_share_set_values - 1) : |cpu_0_jtag_debug_module_arb_share_counter ? (cpu_0_jtag_debug_module_arb_share_counter - 1) : 0;
//cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
assign cpu_0_jtag_debug_module_allgrants = (|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector);
//cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
assign cpu_0_jtag_debug_module_end_xfer = ~(cpu_0_jtag_debug_module_waits_for_read | cpu_0_jtag_debug_module_waits_for_write);
//end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_end_xfer & (~cpu_0_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
assign cpu_0_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & cpu_0_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests);
//cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_share_counter <= 0;
else if (cpu_0_jtag_debug_module_arb_counter_enable)
cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_slavearbiterlockenable <= 0;
else if ((|cpu_0_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests))
cpu_0_jtag_debug_module_slavearbiterlockenable <= |cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign cpu_0_jtag_debug_module_slavearbiterlockenable2 = |cpu_0_jtag_debug_module_arb_share_counter_next_value;
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
assign cpu_0_jtag_debug_module_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_data_master_requests_cpu_0_jtag_debug_module & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_jtag_debug_module_writedata mux, which is an e_mux
assign cpu_0_jtag_debug_module_writedata = cpu_0_data_master_writedata;
assign cpu_0_instruction_master_requests_cpu_0_jtag_debug_module = (({cpu_0_instruction_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_data_master_requests_cpu_0_jtag_debug_module;
assign cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_instruction_master_requests_cpu_0_jtag_debug_module & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0))) | cpu_0_data_master_arbiterlock);
//local readdatavalid cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module = cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read & ~cpu_0_jtag_debug_module_waits_for_read;
//allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/instruction_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[0];
//cpu_0/instruction_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[0] && cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0/data_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[1] = cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/data_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[1];
//cpu_0/data_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[1] && cpu_0_data_master_requests_cpu_0_jtag_debug_module;
//cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_double_vector = {cpu_0_jtag_debug_module_master_qreq_vector, cpu_0_jtag_debug_module_master_qreq_vector} & ({~cpu_0_jtag_debug_module_master_qreq_vector, ~cpu_0_jtag_debug_module_master_qreq_vector} + cpu_0_jtag_debug_module_arb_addend);
//stable onehot encoding of arb winner
assign cpu_0_jtag_debug_module_arb_winner = (cpu_0_jtag_debug_module_allow_new_arb_cycle & | cpu_0_jtag_debug_module_grant_vector) ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
//saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= 0;
else if (cpu_0_jtag_debug_module_allow_new_arb_cycle)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= |cpu_0_jtag_debug_module_grant_vector ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign cpu_0_jtag_debug_module_grant_vector = {(cpu_0_jtag_debug_module_chosen_master_double_vector[1] | cpu_0_jtag_debug_module_chosen_master_double_vector[3]),
(cpu_0_jtag_debug_module_chosen_master_double_vector[0] | cpu_0_jtag_debug_module_chosen_master_double_vector[2])};
//cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_rot_left = (cpu_0_jtag_debug_module_arb_winner << 1) ? (cpu_0_jtag_debug_module_arb_winner << 1) : 1;
//cpu_0/jtag_debug_module's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_addend <= 1;
else if (|cpu_0_jtag_debug_module_grant_vector)
cpu_0_jtag_debug_module_arb_addend <= cpu_0_jtag_debug_module_end_xfer? cpu_0_jtag_debug_module_chosen_master_rot_left : cpu_0_jtag_debug_module_grant_vector;
end
assign cpu_0_jtag_debug_module_begintransfer = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_reset_n assignment, which is an e_assign
assign cpu_0_jtag_debug_module_reset_n = reset_n;
//assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest;
assign cpu_0_jtag_debug_module_chipselect = cpu_0_data_master_granted_cpu_0_jtag_debug_module | cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_firsttransfer = cpu_0_jtag_debug_module_begins_xfer ? cpu_0_jtag_debug_module_unreg_firsttransfer : cpu_0_jtag_debug_module_reg_firsttransfer;
//cpu_0_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_unreg_firsttransfer = ~(cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_jtag_debug_module_any_continuerequest);
//cpu_0_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_reg_firsttransfer <= 1'b1;
else if (cpu_0_jtag_debug_module_begins_xfer)
cpu_0_jtag_debug_module_reg_firsttransfer <= cpu_0_jtag_debug_module_unreg_firsttransfer;
end
//cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign cpu_0_jtag_debug_module_beginbursttransfer_internal = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign cpu_0_jtag_debug_module_arbitration_holdoff_internal = cpu_0_jtag_debug_module_begins_xfer & cpu_0_jtag_debug_module_firsttransfer;
//cpu_0_jtag_debug_module_write assignment, which is an e_mux
assign cpu_0_jtag_debug_module_write = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//cpu_0_jtag_debug_module_address mux, which is an e_mux
assign cpu_0_jtag_debug_module_address = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? (shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master >> 2) :
(shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_cpu_0_jtag_debug_module_end_xfer <= 1;
else
d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
end
//cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_read_cycle = (cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;
//cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & 0;
//cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_write_cycle = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;
assign wait_for_cpu_0_jtag_debug_module_counter = 0;
//cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
assign cpu_0_jtag_debug_module_byteenable = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_byteenable :
-1;
//debugaccess mux, which is an e_mux
assign cpu_0_jtag_debug_module_debugaccess = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_debugaccess :
0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0/jtag_debug_module enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_cpu_0_jtag_debug_module + cpu_0_instruction_master_granted_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_data_master_arbitrator (
// inputs:
cfi_flash_0_s1_wait_counter_eq_0,
cfi_flash_0_s1_wait_counter_eq_1,
clk,
cpu_0_data_master_address,
cpu_0_data_master_byteenable_cfi_flash_0_s1,
cpu_0_data_master_byteenable_sram_avalon_slave_0,
cpu_0_data_master_granted_cfi_flash_0_s1,
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_granted_epcs_epcs_control_port,
cpu_0_data_master_granted_i2c_avalon_slave_0,
cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_granted_lcd_control_slave,
cpu_0_data_master_granted_onchip_memory2_s1,
cpu_0_data_master_granted_sram_avalon_slave_0,
cpu_0_data_master_granted_sysid_0_control_slave,
cpu_0_data_master_granted_timer_s1,
cpu_0_data_master_granted_uart_s1,
cpu_0_data_master_granted_vga_0_avalon_slave_0,
cpu_0_data_master_qualified_request_cfi_flash_0_s1,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_epcs_epcs_control_port,
cpu_0_data_master_qualified_request_i2c_avalon_slave_0,
cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_qualified_request_lcd_control_slave,
cpu_0_data_master_qualified_request_onchip_memory2_s1,
cpu_0_data_master_qualified_request_sram_avalon_slave_0,
cpu_0_data_master_qualified_request_sysid_0_control_slave,
cpu_0_data_master_qualified_request_timer_s1,
cpu_0_data_master_qualified_request_uart_s1,
cpu_0_data_master_qualified_request_vga_0_avalon_slave_0,
cpu_0_data_master_read,
cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_epcs_epcs_control_port,
cpu_0_data_master_read_data_valid_i2c_avalon_slave_0,
cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_lcd_control_slave,
cpu_0_data_master_read_data_valid_onchip_memory2_s1,
cpu_0_data_master_read_data_valid_sram_avalon_slave_0,
cpu_0_data_master_read_data_valid_sysid_0_control_slave,
cpu_0_data_master_read_data_valid_timer_s1,
cpu_0_data_master_read_data_valid_uart_s1,
cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0,
cpu_0_data_master_requests_cfi_flash_0_s1,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_epcs_epcs_control_port,
cpu_0_data_master_requests_i2c_avalon_slave_0,
cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_requests_lcd_control_slave,
cpu_0_data_master_requests_onchip_memory2_s1,
cpu_0_data_master_requests_sram_avalon_slave_0,
cpu_0_data_master_requests_sysid_0_control_slave,
cpu_0_data_master_requests_timer_s1,
cpu_0_data_master_requests_uart_s1,
cpu_0_data_master_requests_vga_0_avalon_slave_0,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_epcs_epcs_control_port_end_xfer,
d1_i2c_avalon_slave_0_end_xfer,
d1_jtag_uart_avalon_jtag_slave_end_xfer,
d1_lcd_control_slave_end_xfer,
d1_onchip_memory2_s1_end_xfer,
d1_sram_avalon_slave_0_end_xfer,
d1_sysid_0_control_slave_end_xfer,
d1_timer_s1_end_xfer,
d1_tri_state_bridge_flash_avalon_slave_end_xfer,
d1_uart_s1_end_xfer,
d1_vga_0_avalon_slave_0_end_xfer,
epcs_epcs_control_port_irq_from_sa,
epcs_epcs_control_port_readdata_from_sa,
i2c_avalon_slave_0_irq_from_sa,
i2c_avalon_slave_0_readdata_from_sa,
i2c_avalon_slave_0_waitrequest_n_from_sa,
incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0,
jtag_uart_avalon_jtag_slave_irq_from_sa,
jtag_uart_avalon_jtag_slave_readdata_from_sa,
jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
lcd_control_slave_readdata_from_sa,
lcd_control_slave_wait_counter_eq_0,
lcd_control_slave_wait_counter_eq_1,
onchip_memory2_s1_readdata_from_sa,
registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1,
reset_n,
sram_avalon_slave_0_readdata_from_sa,
sram_avalon_slave_0_wait_counter_eq_0,
sysid_0_control_slave_readdata_from_sa,
timer_s1_irq_from_sa,
timer_s1_readdata_from_sa,
uart_s1_irq_from_sa,
uart_s1_readdata_from_sa,
vga_0_avalon_slave_0_readdata_from_sa,
vga_0_avalon_slave_0_wait_counter_eq_0,
// outputs:
cpu_0_data_master_address_to_slave,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_16,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_irq,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_readdata,
cpu_0_data_master_waitrequest
)
;
output [ 23: 0] cpu_0_data_master_address_to_slave;
output [ 1: 0] cpu_0_data_master_dbs_address;
output [ 15: 0] cpu_0_data_master_dbs_write_16;
output [ 7: 0] cpu_0_data_master_dbs_write_8;
output [ 31: 0] cpu_0_data_master_irq;
output cpu_0_data_master_no_byte_enables_and_last_term;
output [ 31: 0] cpu_0_data_master_readdata;
output cpu_0_data_master_waitrequest;
input cfi_flash_0_s1_wait_counter_eq_0;
input cfi_flash_0_s1_wait_counter_eq_1;
input clk;
input [ 23: 0] cpu_0_data_master_address;
input cpu_0_data_master_byteenable_cfi_flash_0_s1;
input [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0;
input cpu_0_data_master_granted_cfi_flash_0_s1;
input cpu_0_data_master_granted_cpu_0_jtag_debug_module;
input cpu_0_data_master_granted_epcs_epcs_control_port;
input cpu_0_data_master_granted_i2c_avalon_slave_0;
input cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
input cpu_0_data_master_granted_lcd_control_slave;
input cpu_0_data_master_granted_onchip_memory2_s1;
input cpu_0_data_master_granted_sram_avalon_slave_0;
input cpu_0_data_master_granted_sysid_0_control_slave;
input cpu_0_data_master_granted_timer_s1;
input cpu_0_data_master_granted_uart_s1;
input cpu_0_data_master_granted_vga_0_avalon_slave_0;
input cpu_0_data_master_qualified_request_cfi_flash_0_s1;
input cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_data_master_qualified_request_epcs_epcs_control_port;
input cpu_0_data_master_qualified_request_i2c_avalon_slave_0;
input cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
input cpu_0_data_master_qualified_request_lcd_control_slave;
input cpu_0_data_master_qualified_request_onchip_memory2_s1;
input cpu_0_data_master_qualified_request_sram_avalon_slave_0;
input cpu_0_data_master_qualified_request_sysid_0_control_slave;
input cpu_0_data_master_qualified_request_timer_s1;
input cpu_0_data_master_qualified_request_uart_s1;
input cpu_0_data_master_qualified_request_vga_0_avalon_slave_0;
input cpu_0_data_master_read;
input cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
input cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_data_master_read_data_valid_epcs_epcs_control_port;
input cpu_0_data_master_read_data_valid_i2c_avalon_slave_0;
input cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
input cpu_0_data_master_read_data_valid_lcd_control_slave;
input cpu_0_data_master_read_data_valid_onchip_memory2_s1;
input cpu_0_data_master_read_data_valid_sram_avalon_slave_0;
input cpu_0_data_master_read_data_valid_sysid_0_control_slave;
input cpu_0_data_master_read_data_valid_timer_s1;
input cpu_0_data_master_read_data_valid_uart_s1;
input cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0;
input cpu_0_data_master_requests_cfi_flash_0_s1;
input cpu_0_data_master_requests_cpu_0_jtag_debug_module;
input cpu_0_data_master_requests_epcs_epcs_control_port;
input cpu_0_data_master_requests_i2c_avalon_slave_0;
input cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
input cpu_0_data_master_requests_lcd_control_slave;
input cpu_0_data_master_requests_onchip_memory2_s1;
input cpu_0_data_master_requests_sram_avalon_slave_0;
input cpu_0_data_master_requests_sysid_0_control_slave;
input cpu_0_data_master_requests_timer_s1;
input cpu_0_data_master_requests_uart_s1;
input cpu_0_data_master_requests_vga_0_avalon_slave_0;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_epcs_epcs_control_port_end_xfer;
input d1_i2c_avalon_slave_0_end_xfer;
input d1_jtag_uart_avalon_jtag_slave_end_xfer;
input d1_lcd_control_slave_end_xfer;
input d1_onchip_memory2_s1_end_xfer;
input d1_sram_avalon_slave_0_end_xfer;
input d1_sysid_0_control_slave_end_xfer;
input d1_timer_s1_end_xfer;
input d1_tri_state_bridge_flash_avalon_slave_end_xfer;
input d1_uart_s1_end_xfer;
input d1_vga_0_avalon_slave_0_end_xfer;
input epcs_epcs_control_port_irq_from_sa;
input [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
input i2c_avalon_slave_0_irq_from_sa;
input [ 7: 0] i2c_avalon_slave_0_readdata_from_sa;
input i2c_avalon_slave_0_waitrequest_n_from_sa;
input [ 7: 0] incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
input jtag_uart_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
input [ 7: 0] lcd_control_slave_readdata_from_sa;
input lcd_control_slave_wait_counter_eq_0;
input lcd_control_slave_wait_counter_eq_1;
input [ 31: 0] onchip_memory2_s1_readdata_from_sa;
input registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
input registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1;
input reset_n;
input [ 15: 0] sram_avalon_slave_0_readdata_from_sa;
input sram_avalon_slave_0_wait_counter_eq_0;
input [ 31: 0] sysid_0_control_slave_readdata_from_sa;
input timer_s1_irq_from_sa;
input [ 15: 0] timer_s1_readdata_from_sa;
input uart_s1_irq_from_sa;
input [ 15: 0] uart_s1_readdata_from_sa;
input [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
input vga_0_avalon_slave_0_wait_counter_eq_0;
wire [ 23: 0] cpu_0_data_master_address_to_slave;
reg [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 1: 0] cpu_0_data_master_dbs_increment;
wire [ 15: 0] cpu_0_data_master_dbs_write_16;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire [ 31: 0] cpu_0_data_master_irq;
reg cpu_0_data_master_no_byte_enables_and_last_term;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_run;
reg cpu_0_data_master_waitrequest;
reg [ 15: 0] dbs_16_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_1;
reg [ 7: 0] dbs_8_reg_segment_2;
wire dbs_count_enable;
wire dbs_counter_overflow;
wire last_dbs_term_and_run;
wire [ 1: 0] next_dbs_address;
wire [ 15: 0] p1_dbs_16_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_1;
wire [ 7: 0] p1_dbs_8_reg_segment_2;
wire [ 31: 0] p1_registered_cpu_0_data_master_readdata;
wire pre_dbs_count_enable;
wire r_0;
wire r_1;
wire r_2;
reg [ 31: 0] registered_cpu_0_data_master_readdata;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_epcs_epcs_control_port | ~cpu_0_data_master_requests_epcs_epcs_control_port) & (cpu_0_data_master_granted_epcs_epcs_control_port | ~cpu_0_data_master_qualified_request_epcs_epcs_control_port) & ((~cpu_0_data_master_qualified_request_epcs_epcs_control_port | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_epcs_epcs_control_port | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_i2c_avalon_slave_0 | ~cpu_0_data_master_requests_i2c_avalon_slave_0) & ((~cpu_0_data_master_qualified_request_i2c_avalon_slave_0 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & i2c_avalon_slave_0_waitrequest_n_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_i2c_avalon_slave_0 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & i2c_avalon_slave_0_waitrequest_n_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_lcd_control_slave | ~cpu_0_data_master_read | (1 & lcd_control_slave_wait_counter_eq_1 & cpu_0_data_master_read)));
//cascaded wait assignment, which is an e_assign
assign cpu_0_data_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = ((~cpu_0_data_master_qualified_request_lcd_control_slave | ~cpu_0_data_master_write | (1 & lcd_control_slave_wait_counter_eq_1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_onchip_memory2_s1 | registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 | ~cpu_0_data_master_requests_onchip_memory2_s1) & (cpu_0_data_master_granted_onchip_memory2_s1 | ~cpu_0_data_master_qualified_request_onchip_memory2_s1) & ((~cpu_0_data_master_qualified_request_onchip_memory2_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_onchip_memory2_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_sram_avalon_slave_0 | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_sram_avalon_slave_0 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_sram_avalon_slave_0) & (cpu_0_data_master_granted_sram_avalon_slave_0 | ~cpu_0_data_master_qualified_request_sram_avalon_slave_0) & ((~cpu_0_data_master_qualified_request_sram_avalon_slave_0 | ~cpu_0_data_master_read | (1 & 1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sram_avalon_slave_0 | ~cpu_0_data_master_write | (1 & ~d1_sram_avalon_slave_0_end_xfer & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_sysid_0_control_slave | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sysid_0_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_timer_s1 | ~cpu_0_data_master_requests_timer_s1) & ((~cpu_0_data_master_qualified_request_timer_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_timer_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((cpu_0_data_master_qualified_request_cfi_flash_0_s1 | (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) | ((cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1 & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0])) | ~cpu_0_data_master_requests_cfi_flash_0_s1));
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = (cpu_0_data_master_granted_cfi_flash_0_s1 | ~cpu_0_data_master_qualified_request_cfi_flash_0_s1) & ((~cpu_0_data_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_data_master_write | (1 & cfi_flash_0_s1_wait_counter_eq_1 & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_uart_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_uart_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_vga_0_avalon_slave_0 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_vga_0_avalon_slave_0 | ~cpu_0_data_master_write | (1 & ~d1_vga_0_avalon_slave_0_end_xfer & cpu_0_data_master_write)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[23 : 0];
//cpu_0/data_master readdata mux, which is an e_mux
assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_epcs_epcs_control_port}} | epcs_epcs_control_port_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_i2c_avalon_slave_0}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_lcd_control_slave}} | lcd_control_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_onchip_memory2_s1}} | onchip_memory2_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_sram_avalon_slave_0}} | {sram_avalon_slave_0_readdata_from_sa[15 : 0],
dbs_16_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_sysid_0_control_slave}} | sysid_0_control_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_timer_s1}} | timer_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_cfi_flash_0_s1}} | {incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_uart_s1}} | uart_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_vga_0_avalon_slave_0}} | vga_0_avalon_slave_0_readdata_from_sa);
//actual waitrequest port, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_waitrequest <= ~0;
else
cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
end
//irq assign, which is an e_assign
assign cpu_0_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
i2c_avalon_slave_0_irq_from_sa,
epcs_epcs_control_port_irq_from_sa,
timer_s1_irq_from_sa,
uart_s1_irq_from_sa,
jtag_uart_avalon_jtag_slave_irq_from_sa};
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_0_data_master_readdata <= 0;
else
registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_i2c_avalon_slave_0}} | i2c_avalon_slave_0_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa);
//no_byte_enables_and_last_term, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_no_byte_enables_and_last_term <= 0;
else
cpu_0_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
end
//compute the last dbs term, which is an e_mux
assign last_dbs_term_and_run = (cpu_0_data_master_requests_sram_avalon_slave_0)? (((cpu_0_data_master_dbs_address == 2'b10) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_sram_avalon_slave_0)) :
(((cpu_0_data_master_dbs_address == 2'b11) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1));
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = (((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_sram_avalon_slave_0 & cpu_0_data_master_write & !cpu_0_data_master_byteenable_sram_avalon_slave_0)) |
(cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_read & 1 & 1 & ~d1_sram_avalon_slave_0_end_xfer) |
((cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_write & 1 & 1 & ({sram_avalon_slave_0_wait_counter_eq_0 & ~d1_sram_avalon_slave_0_end_xfer}))) |
(((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_cfi_flash_0_s1 & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1)) |
cpu_0_data_master_read_data_valid_cfi_flash_0_s1 |
((cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_write & 1 & 1 & ({cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_flash_avalon_slave_end_xfer})));
//input to dbs-16 stored 0, which is an e_mux
assign p1_dbs_16_reg_segment_0 = sram_avalon_slave_0_readdata_from_sa;
//dbs register for dbs-16 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_16_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1]) == 0))
dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
end
//mux write dbs 1, which is an e_mux
assign cpu_0_data_master_dbs_write_16 = (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
cpu_0_data_master_writedata[15 : 0];
//dbs count increment, which is an e_mux
assign cpu_0_data_master_dbs_increment = (cpu_0_data_master_requests_sram_avalon_slave_0)? 2 :
(cpu_0_data_master_requests_cfi_flash_0_s1)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_0_data_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_0_data_master_dbs_address + cpu_0_data_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable;
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_0_data_master_dbs_address <= next_dbs_address;
end
//input to dbs-8 stored 0, which is an e_mux
assign p1_dbs_8_reg_segment_0 = incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 0))
dbs_8_reg_segment_0 <= p1_dbs_8_reg_segment_0;
end
//input to dbs-8 stored 1, which is an e_mux
assign p1_dbs_8_reg_segment_1 = incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_1 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 1))
dbs_8_reg_segment_1 <= p1_dbs_8_reg_segment_1;
end
//input to dbs-8 stored 2, which is an e_mux
assign p1_dbs_8_reg_segment_2 = incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
//dbs register for dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_2 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 2))
dbs_8_reg_segment_2 <= p1_dbs_8_reg_segment_2;
end
//mux write dbs 2, which is an e_mux
assign cpu_0_data_master_dbs_write_8 = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_writedata[7 : 0] :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_writedata[15 : 8] :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_writedata[23 : 16] :
cpu_0_data_master_writedata[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_instruction_master_arbitrator (
// inputs:
cfi_flash_0_s1_wait_counter_eq_0,
cfi_flash_0_s1_wait_counter_eq_1,
clk,
cpu_0_instruction_master_address,
cpu_0_instruction_master_granted_cfi_flash_0_s1,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_epcs_epcs_control_port,
cpu_0_instruction_master_granted_onchip_memory2_s1,
cpu_0_instruction_master_granted_sram_avalon_slave_0,
cpu_0_instruction_master_qualified_request_cfi_flash_0_s1,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_epcs_epcs_control_port,
cpu_0_instruction_master_qualified_request_onchip_memory2_s1,
cpu_0_instruction_master_qualified_request_sram_avalon_slave_0,
cpu_0_instruction_master_read,
cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port,
cpu_0_instruction_master_read_data_valid_onchip_memory2_s1,
cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0,
cpu_0_instruction_master_requests_cfi_flash_0_s1,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_epcs_epcs_control_port,
cpu_0_instruction_master_requests_onchip_memory2_s1,
cpu_0_instruction_master_requests_sram_avalon_slave_0,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_epcs_epcs_control_port_end_xfer,
d1_onchip_memory2_s1_end_xfer,
d1_sram_avalon_slave_0_end_xfer,
d1_tri_state_bridge_flash_avalon_slave_end_xfer,
epcs_epcs_control_port_readdata_from_sa,
incoming_tri_state_bridge_flash_data,
onchip_memory2_s1_readdata_from_sa,
reset_n,
sram_avalon_slave_0_readdata_from_sa,
sram_avalon_slave_0_wait_counter_eq_0,
// outputs:
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_dbs_address,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_readdata,
cpu_0_instruction_master_readdatavalid,
cpu_0_instruction_master_waitrequest
)
;
output [ 23: 0] cpu_0_instruction_master_address_to_slave;
output [ 1: 0] cpu_0_instruction_master_dbs_address;
output [ 1: 0] cpu_0_instruction_master_latency_counter;
output [ 31: 0] cpu_0_instruction_master_readdata;
output cpu_0_instruction_master_readdatavalid;
output cpu_0_instruction_master_waitrequest;
input cfi_flash_0_s1_wait_counter_eq_0;
input cfi_flash_0_s1_wait_counter_eq_1;
input clk;
input [ 23: 0] cpu_0_instruction_master_address;
input cpu_0_instruction_master_granted_cfi_flash_0_s1;
input cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_granted_epcs_epcs_control_port;
input cpu_0_instruction_master_granted_onchip_memory2_s1;
input cpu_0_instruction_master_granted_sram_avalon_slave_0;
input cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
input cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_qualified_request_epcs_epcs_control_port;
input cpu_0_instruction_master_qualified_request_onchip_memory2_s1;
input cpu_0_instruction_master_qualified_request_sram_avalon_slave_0;
input cpu_0_instruction_master_read;
input cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
input cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port;
input cpu_0_instruction_master_read_data_valid_onchip_memory2_s1;
input cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0;
input cpu_0_instruction_master_requests_cfi_flash_0_s1;
input cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_requests_epcs_epcs_control_port;
input cpu_0_instruction_master_requests_onchip_memory2_s1;
input cpu_0_instruction_master_requests_sram_avalon_slave_0;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_epcs_epcs_control_port_end_xfer;
input d1_onchip_memory2_s1_end_xfer;
input d1_sram_avalon_slave_0_end_xfer;
input d1_tri_state_bridge_flash_avalon_slave_end_xfer;
input [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
input [ 7: 0] incoming_tri_state_bridge_flash_data;
input [ 31: 0] onchip_memory2_s1_readdata_from_sa;
input reset_n;
input [ 15: 0] sram_avalon_slave_0_readdata_from_sa;
input sram_avalon_slave_0_wait_counter_eq_0;
reg active_and_waiting_last_time;
reg [ 23: 0] cpu_0_instruction_master_address_last_time;
wire [ 23: 0] cpu_0_instruction_master_address_to_slave;
reg [ 1: 0] cpu_0_instruction_master_dbs_address;
wire [ 1: 0] cpu_0_instruction_master_dbs_increment;
reg [ 1: 0] cpu_0_instruction_master_dbs_rdv_counter;
wire [ 1: 0] cpu_0_instruction_master_dbs_rdv_counter_inc;
wire cpu_0_instruction_master_is_granted_some_slave;
reg [ 1: 0] cpu_0_instruction_master_latency_counter;
wire [ 1: 0] cpu_0_instruction_master_next_dbs_rdv_counter;
reg cpu_0_instruction_master_read_but_no_slave_selected;
reg cpu_0_instruction_master_read_last_time;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_readdatavalid;
wire cpu_0_instruction_master_run;
wire cpu_0_instruction_master_waitrequest;
reg [ 15: 0] dbs_16_reg_segment_0;
wire dbs_count_enable;
wire dbs_counter_overflow;
reg [ 7: 0] dbs_latent_8_reg_segment_0;
reg [ 7: 0] dbs_latent_8_reg_segment_1;
reg [ 7: 0] dbs_latent_8_reg_segment_2;
wire dbs_rdv_count_enable;
wire dbs_rdv_counter_overflow;
wire [ 1: 0] latency_load_value;
wire [ 1: 0] next_dbs_address;
wire [ 1: 0] p1_cpu_0_instruction_master_latency_counter;
wire [ 15: 0] p1_dbs_16_reg_segment_0;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_0;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_1;
wire [ 7: 0] p1_dbs_latent_8_reg_segment_2;
wire pre_dbs_count_enable;
wire pre_flush_cpu_0_instruction_master_readdatavalid;
wire r_0;
wire r_1;
wire r_2;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) & (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_read | (1 & ~d1_cpu_0_jtag_debug_module_end_xfer & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_epcs_epcs_control_port | ~cpu_0_instruction_master_requests_epcs_epcs_control_port) & (cpu_0_instruction_master_granted_epcs_epcs_control_port | ~cpu_0_instruction_master_qualified_request_epcs_epcs_control_port) & ((~cpu_0_instruction_master_qualified_request_epcs_epcs_control_port | ~(cpu_0_instruction_master_read) | (1 & ~d1_epcs_epcs_control_port_end_xfer & (cpu_0_instruction_master_read))));
//cascaded wait assignment, which is an e_assign
assign cpu_0_instruction_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_0_instruction_master_qualified_request_onchip_memory2_s1 | ~cpu_0_instruction_master_requests_onchip_memory2_s1) & (cpu_0_instruction_master_granted_onchip_memory2_s1 | ~cpu_0_instruction_master_qualified_request_onchip_memory2_s1) & ((~cpu_0_instruction_master_qualified_request_onchip_memory2_s1 | ~cpu_0_instruction_master_read | (1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 | ~cpu_0_instruction_master_requests_sram_avalon_slave_0) & (cpu_0_instruction_master_granted_sram_avalon_slave_0 | ~cpu_0_instruction_master_qualified_request_sram_avalon_slave_0) & ((~cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 | ~cpu_0_instruction_master_read | (1 & ~d1_sram_avalon_slave_0_end_xfer & (cpu_0_instruction_master_dbs_address[1]) & cpu_0_instruction_master_read)));
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_instruction_master_requests_cfi_flash_0_s1) & (cpu_0_instruction_master_granted_cfi_flash_0_s1 | ~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1) & ((~cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_instruction_master_read | (1 & ((cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_flash_avalon_slave_end_xfer)) & (cpu_0_instruction_master_dbs_address[1] & cpu_0_instruction_master_dbs_address[0]) & cpu_0_instruction_master_read)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_instruction_master_address_to_slave = cpu_0_instruction_master_address[23 : 0];
//cpu_0_instruction_master_read_but_no_slave_selected assignment, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_but_no_slave_selected <= 0;
else
cpu_0_instruction_master_read_but_no_slave_selected <= cpu_0_instruction_master_read & cpu_0_instruction_master_run & ~cpu_0_instruction_master_is_granted_some_slave;
end
//some slave is getting selected, which is an e_mux
assign cpu_0_instruction_master_is_granted_some_slave = cpu_0_instruction_master_granted_cpu_0_jtag_debug_module |
cpu_0_instruction_master_granted_epcs_epcs_control_port |
cpu_0_instruction_master_granted_onchip_memory2_s1 |
cpu_0_instruction_master_granted_sram_avalon_slave_0 |
cpu_0_instruction_master_granted_cfi_flash_0_s1;
//latent slave read data valids which may be flushed, which is an e_mux
assign pre_flush_cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_data_valid_onchip_memory2_s1 |
(cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 & dbs_rdv_counter_overflow);
//latent slave read data valid which is not flushed, which is an e_mux
assign cpu_0_instruction_master_readdatavalid = cpu_0_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_0_instruction_master_readdatavalid |
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module |
cpu_0_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_0_instruction_master_readdatavalid |
cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port |
cpu_0_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_0_instruction_master_readdatavalid |
cpu_0_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_0_instruction_master_readdatavalid |
(cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0 & dbs_counter_overflow) |
cpu_0_instruction_master_read_but_no_slave_selected |
pre_flush_cpu_0_instruction_master_readdatavalid;
//cpu_0/instruction_master readdata mux, which is an e_mux
assign cpu_0_instruction_master_readdata = ({32 {~(cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module & cpu_0_instruction_master_read)}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~(cpu_0_instruction_master_qualified_request_epcs_epcs_control_port & cpu_0_instruction_master_read)}} | epcs_epcs_control_port_readdata_from_sa) &
({32 {~cpu_0_instruction_master_read_data_valid_onchip_memory2_s1}} | onchip_memory2_s1_readdata_from_sa) &
({32 {~(cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 & cpu_0_instruction_master_read)}} | {sram_avalon_slave_0_readdata_from_sa[15 : 0],
dbs_16_reg_segment_0}) &
({32 {~cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1}} | {incoming_tri_state_bridge_flash_data[7 : 0],
dbs_latent_8_reg_segment_2,
dbs_latent_8_reg_segment_1,
dbs_latent_8_reg_segment_0});
//actual waitrequest port, which is an e_assign
assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;
//latent max counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_latency_counter <= 0;
else
cpu_0_instruction_master_latency_counter <= p1_cpu_0_instruction_master_latency_counter;
end
//latency counter load mux, which is an e_mux
assign p1_cpu_0_instruction_master_latency_counter = ((cpu_0_instruction_master_run & cpu_0_instruction_master_read))? latency_load_value :
(cpu_0_instruction_master_latency_counter)? cpu_0_instruction_master_latency_counter - 1 :
0;
//read latency load values, which is an e_mux
assign latency_load_value = ({2 {cpu_0_instruction_master_requests_onchip_memory2_s1}} & 1) |
({2 {cpu_0_instruction_master_requests_cfi_flash_0_s1}} & 2);
//input to dbs-16 stored 0, which is an e_mux
assign p1_dbs_16_reg_segment_0 = sram_avalon_slave_0_readdata_from_sa;
//dbs register for dbs-16 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_16_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_0_instruction_master_dbs_address[1]) == 0))
dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
end
//dbs count increment, which is an e_mux
assign cpu_0_instruction_master_dbs_increment = (cpu_0_instruction_master_requests_sram_avalon_slave_0)? 2 :
(cpu_0_instruction_master_requests_cfi_flash_0_s1)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_0_instruction_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_0_instruction_master_dbs_address + cpu_0_instruction_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable;
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_0_instruction_master_dbs_address <= next_dbs_address;
end
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = (cpu_0_instruction_master_granted_sram_avalon_slave_0 & cpu_0_instruction_master_read & 1 & 1 & ~d1_sram_avalon_slave_0_end_xfer) |
((cpu_0_instruction_master_granted_cfi_flash_0_s1 & cpu_0_instruction_master_read & 1 & 1 & ({cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_flash_avalon_slave_end_xfer})));
//input to latent dbs-8 stored 0, which is an e_mux
assign p1_dbs_latent_8_reg_segment_0 = incoming_tri_state_bridge_flash_data;
//dbs register for latent dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_0 <= 0;
else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 0))
dbs_latent_8_reg_segment_0 <= p1_dbs_latent_8_reg_segment_0;
end
//input to latent dbs-8 stored 1, which is an e_mux
assign p1_dbs_latent_8_reg_segment_1 = incoming_tri_state_bridge_flash_data;
//dbs register for latent dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_1 <= 0;
else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 1))
dbs_latent_8_reg_segment_1 <= p1_dbs_latent_8_reg_segment_1;
end
//input to latent dbs-8 stored 2, which is an e_mux
assign p1_dbs_latent_8_reg_segment_2 = incoming_tri_state_bridge_flash_data;
//dbs register for latent dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_latent_8_reg_segment_2 <= 0;
else if (dbs_rdv_count_enable & ((cpu_0_instruction_master_dbs_rdv_counter[1 : 0]) == 2))
dbs_latent_8_reg_segment_2 <= p1_dbs_latent_8_reg_segment_2;
end
//p1 dbs rdv counter, which is an e_assign
assign cpu_0_instruction_master_next_dbs_rdv_counter = cpu_0_instruction_master_dbs_rdv_counter + cpu_0_instruction_master_dbs_rdv_counter_inc;
//cpu_0_instruction_master_rdv_inc_mux, which is an e_mux
assign cpu_0_instruction_master_dbs_rdv_counter_inc = 1;
//master any slave rdv, which is an e_mux
assign dbs_rdv_count_enable = cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
//dbs rdv counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_dbs_rdv_counter <= 0;
else if (dbs_rdv_count_enable)
cpu_0_instruction_master_dbs_rdv_counter <= cpu_0_instruction_master_next_dbs_rdv_counter;
end
//dbs rdv counter overflow, which is an e_assign
assign dbs_rdv_counter_overflow = cpu_0_instruction_master_dbs_rdv_counter[1] & ~cpu_0_instruction_master_next_dbs_rdv_counter[1];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0_instruction_master_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_address_last_time <= 0;
else
cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
end
//cpu_0/instruction_master waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
end
//cpu_0_instruction_master_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
$stop;
end
end
//cpu_0_instruction_master_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_last_time <= 0;
else
cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
end
//cpu_0_instruction_master_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module epcs_epcs_control_port_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_read,
epcs_epcs_control_port_dataavailable,
epcs_epcs_control_port_endofpacket,
epcs_epcs_control_port_irq,
epcs_epcs_control_port_readdata,
epcs_epcs_control_port_readyfordata,
reset_n,
// outputs:
cpu_0_data_master_granted_epcs_epcs_control_port,
cpu_0_data_master_qualified_request_epcs_epcs_control_port,
cpu_0_data_master_read_data_valid_epcs_epcs_control_port,
cpu_0_data_master_requests_epcs_epcs_control_port,
cpu_0_instruction_master_granted_epcs_epcs_control_port,
cpu_0_instruction_master_qualified_request_epcs_epcs_control_port,
cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port,
cpu_0_instruction_master_requests_epcs_epcs_control_port,
d1_epcs_epcs_control_port_end_xfer,
epcs_epcs_control_port_address,
epcs_epcs_control_port_chipselect,
epcs_epcs_control_port_dataavailable_from_sa,
epcs_epcs_control_port_endofpacket_from_sa,
epcs_epcs_control_port_irq_from_sa,
epcs_epcs_control_port_read_n,
epcs_epcs_control_port_readdata_from_sa,
epcs_epcs_control_port_readyfordata_from_sa,
epcs_epcs_control_port_reset_n,
epcs_epcs_control_port_write_n,
epcs_epcs_control_port_writedata
)
;
output cpu_0_data_master_granted_epcs_epcs_control_port;
output cpu_0_data_master_qualified_request_epcs_epcs_control_port;
output cpu_0_data_master_read_data_valid_epcs_epcs_control_port;
output cpu_0_data_master_requests_epcs_epcs_control_port;
output cpu_0_instruction_master_granted_epcs_epcs_control_port;
output cpu_0_instruction_master_qualified_request_epcs_epcs_control_port;
output cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port;
output cpu_0_instruction_master_requests_epcs_epcs_control_port;
output d1_epcs_epcs_control_port_end_xfer;
output [ 8: 0] epcs_epcs_control_port_address;
output epcs_epcs_control_port_chipselect;
output epcs_epcs_control_port_dataavailable_from_sa;
output epcs_epcs_control_port_endofpacket_from_sa;
output epcs_epcs_control_port_irq_from_sa;
output epcs_epcs_control_port_read_n;
output [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
output epcs_epcs_control_port_readyfordata_from_sa;
output epcs_epcs_control_port_reset_n;
output epcs_epcs_control_port_write_n;
output [ 31: 0] epcs_epcs_control_port_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 23: 0] cpu_0_instruction_master_address_to_slave;
input [ 1: 0] cpu_0_instruction_master_latency_counter;
input cpu_0_instruction_master_read;
input epcs_epcs_control_port_dataavailable;
input epcs_epcs_control_port_endofpacket;
input epcs_epcs_control_port_irq;
input [ 31: 0] epcs_epcs_control_port_readdata;
input epcs_epcs_control_port_readyfordata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_epcs_epcs_control_port;
wire cpu_0_data_master_qualified_request_epcs_epcs_control_port;
wire cpu_0_data_master_read_data_valid_epcs_epcs_control_port;
wire cpu_0_data_master_requests_epcs_epcs_control_port;
wire cpu_0_data_master_saved_grant_epcs_epcs_control_port;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_epcs_epcs_control_port;
wire cpu_0_instruction_master_qualified_request_epcs_epcs_control_port;
wire cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port;
wire cpu_0_instruction_master_requests_epcs_epcs_control_port;
wire cpu_0_instruction_master_saved_grant_epcs_epcs_control_port;
reg d1_epcs_epcs_control_port_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_epcs_epcs_control_port;
wire [ 8: 0] epcs_epcs_control_port_address;
wire epcs_epcs_control_port_allgrants;
wire epcs_epcs_control_port_allow_new_arb_cycle;
wire epcs_epcs_control_port_any_bursting_master_saved_grant;
wire epcs_epcs_control_port_any_continuerequest;
reg [ 1: 0] epcs_epcs_control_port_arb_addend;
wire epcs_epcs_control_port_arb_counter_enable;
reg [ 2: 0] epcs_epcs_control_port_arb_share_counter;
wire [ 2: 0] epcs_epcs_control_port_arb_share_counter_next_value;
wire [ 2: 0] epcs_epcs_control_port_arb_share_set_values;
wire [ 1: 0] epcs_epcs_control_port_arb_winner;
wire epcs_epcs_control_port_arbitration_holdoff_internal;
wire epcs_epcs_control_port_beginbursttransfer_internal;
wire epcs_epcs_control_port_begins_xfer;
wire epcs_epcs_control_port_chipselect;
wire [ 3: 0] epcs_epcs_control_port_chosen_master_double_vector;
wire [ 1: 0] epcs_epcs_control_port_chosen_master_rot_left;
wire epcs_epcs_control_port_dataavailable_from_sa;
wire epcs_epcs_control_port_end_xfer;
wire epcs_epcs_control_port_endofpacket_from_sa;
wire epcs_epcs_control_port_firsttransfer;
wire [ 1: 0] epcs_epcs_control_port_grant_vector;
wire epcs_epcs_control_port_in_a_read_cycle;
wire epcs_epcs_control_port_in_a_write_cycle;
wire epcs_epcs_control_port_irq_from_sa;
wire [ 1: 0] epcs_epcs_control_port_master_qreq_vector;
wire epcs_epcs_control_port_non_bursting_master_requests;
wire epcs_epcs_control_port_read_n;
wire [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
wire epcs_epcs_control_port_readyfordata_from_sa;
reg epcs_epcs_control_port_reg_firsttransfer;
wire epcs_epcs_control_port_reset_n;
reg [ 1: 0] epcs_epcs_control_port_saved_chosen_master_vector;
reg epcs_epcs_control_port_slavearbiterlockenable;
wire epcs_epcs_control_port_slavearbiterlockenable2;
wire epcs_epcs_control_port_unreg_firsttransfer;
wire epcs_epcs_control_port_waits_for_read;
wire epcs_epcs_control_port_waits_for_write;
wire epcs_epcs_control_port_write_n;
wire [ 31: 0] epcs_epcs_control_port_writedata;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_epcs_epcs_control_port;
reg last_cycle_cpu_0_instruction_master_granted_slave_epcs_epcs_control_port;
wire [ 23: 0] shifted_address_to_epcs_epcs_control_port_from_cpu_0_data_master;
wire [ 23: 0] shifted_address_to_epcs_epcs_control_port_from_cpu_0_instruction_master;
wire wait_for_epcs_epcs_control_port_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~epcs_epcs_control_port_end_xfer;
end
assign epcs_epcs_control_port_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_epcs_epcs_control_port | cpu_0_instruction_master_qualified_request_epcs_epcs_control_port));
//assign epcs_epcs_control_port_readdata_from_sa = epcs_epcs_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_epcs_control_port_readdata_from_sa = epcs_epcs_control_port_readdata;
assign cpu_0_data_master_requests_epcs_epcs_control_port = ({cpu_0_data_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03800) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign epcs_epcs_control_port_dataavailable_from_sa = epcs_epcs_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_epcs_control_port_dataavailable_from_sa = epcs_epcs_control_port_dataavailable;
//assign epcs_epcs_control_port_readyfordata_from_sa = epcs_epcs_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_epcs_control_port_readyfordata_from_sa = epcs_epcs_control_port_readyfordata;
//epcs_epcs_control_port_arb_share_counter set values, which is an e_mux
assign epcs_epcs_control_port_arb_share_set_values = 1;
//epcs_epcs_control_port_non_bursting_master_requests mux, which is an e_mux
assign epcs_epcs_control_port_non_bursting_master_requests = cpu_0_data_master_requests_epcs_epcs_control_port |
cpu_0_instruction_master_requests_epcs_epcs_control_port |
cpu_0_data_master_requests_epcs_epcs_control_port |
cpu_0_instruction_master_requests_epcs_epcs_control_port;
//epcs_epcs_control_port_any_bursting_master_saved_grant mux, which is an e_mux
assign epcs_epcs_control_port_any_bursting_master_saved_grant = 0;
//epcs_epcs_control_port_arb_share_counter_next_value assignment, which is an e_assign
assign epcs_epcs_control_port_arb_share_counter_next_value = epcs_epcs_control_port_firsttransfer ? (epcs_epcs_control_port_arb_share_set_values - 1) : |epcs_epcs_control_port_arb_share_counter ? (epcs_epcs_control_port_arb_share_counter - 1) : 0;
//epcs_epcs_control_port_allgrants all slave grants, which is an e_mux
assign epcs_epcs_control_port_allgrants = (|epcs_epcs_control_port_grant_vector) |
(|epcs_epcs_control_port_grant_vector) |
(|epcs_epcs_control_port_grant_vector) |
(|epcs_epcs_control_port_grant_vector);
//epcs_epcs_control_port_end_xfer assignment, which is an e_assign
assign epcs_epcs_control_port_end_xfer = ~(epcs_epcs_control_port_waits_for_read | epcs_epcs_control_port_waits_for_write);
//end_xfer_arb_share_counter_term_epcs_epcs_control_port arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_epcs_epcs_control_port = epcs_epcs_control_port_end_xfer & (~epcs_epcs_control_port_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//epcs_epcs_control_port_arb_share_counter arbitration counter enable, which is an e_assign
assign epcs_epcs_control_port_arb_counter_enable = (end_xfer_arb_share_counter_term_epcs_epcs_control_port & epcs_epcs_control_port_allgrants) | (end_xfer_arb_share_counter_term_epcs_epcs_control_port & ~epcs_epcs_control_port_non_bursting_master_requests);
//epcs_epcs_control_port_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_epcs_control_port_arb_share_counter <= 0;
else if (epcs_epcs_control_port_arb_counter_enable)
epcs_epcs_control_port_arb_share_counter <= epcs_epcs_control_port_arb_share_counter_next_value;
end
//epcs_epcs_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_epcs_control_port_slavearbiterlockenable <= 0;
else if ((|epcs_epcs_control_port_master_qreq_vector & end_xfer_arb_share_counter_term_epcs_epcs_control_port) | (end_xfer_arb_share_counter_term_epcs_epcs_control_port & ~epcs_epcs_control_port_non_bursting_master_requests))
epcs_epcs_control_port_slavearbiterlockenable <= |epcs_epcs_control_port_arb_share_counter_next_value;
end
//cpu_0/data_master epcs/epcs_control_port arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = epcs_epcs_control_port_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//epcs_epcs_control_port_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign epcs_epcs_control_port_slavearbiterlockenable2 = |epcs_epcs_control_port_arb_share_counter_next_value;
//cpu_0/data_master epcs/epcs_control_port arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = epcs_epcs_control_port_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master epcs/epcs_control_port arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = epcs_epcs_control_port_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master epcs/epcs_control_port arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = epcs_epcs_control_port_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted epcs/epcs_control_port last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_epcs_epcs_control_port <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_epcs_epcs_control_port <= cpu_0_instruction_master_saved_grant_epcs_epcs_control_port ? 1 : (epcs_epcs_control_port_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_epcs_epcs_control_port) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_epcs_epcs_control_port;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_epcs_epcs_control_port & cpu_0_instruction_master_requests_epcs_epcs_control_port;
//epcs_epcs_control_port_any_continuerequest at least one master continues requesting, which is an e_mux
assign epcs_epcs_control_port_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_epcs_epcs_control_port = cpu_0_data_master_requests_epcs_epcs_control_port & ~(cpu_0_instruction_master_arbiterlock);
//epcs_epcs_control_port_writedata mux, which is an e_mux
assign epcs_epcs_control_port_writedata = cpu_0_data_master_writedata;
//assign epcs_epcs_control_port_endofpacket_from_sa = epcs_epcs_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_epcs_control_port_endofpacket_from_sa = epcs_epcs_control_port_endofpacket;
assign cpu_0_instruction_master_requests_epcs_epcs_control_port = (({cpu_0_instruction_master_address_to_slave[23 : 11] , 11'b0} == 24'hb03800) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted epcs/epcs_control_port last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_epcs_epcs_control_port <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_epcs_epcs_control_port <= cpu_0_data_master_saved_grant_epcs_epcs_control_port ? 1 : (epcs_epcs_control_port_arbitration_holdoff_internal | ~cpu_0_data_master_requests_epcs_epcs_control_port) ? 0 : last_cycle_cpu_0_data_master_granted_slave_epcs_epcs_control_port;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_epcs_epcs_control_port & cpu_0_data_master_requests_epcs_epcs_control_port;
assign cpu_0_instruction_master_qualified_request_epcs_epcs_control_port = cpu_0_instruction_master_requests_epcs_epcs_control_port & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0))) | cpu_0_data_master_arbiterlock);
//local readdatavalid cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port = cpu_0_instruction_master_granted_epcs_epcs_control_port & cpu_0_instruction_master_read & ~epcs_epcs_control_port_waits_for_read;
//allow new arb cycle for epcs/epcs_control_port, which is an e_assign
assign epcs_epcs_control_port_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for epcs/epcs_control_port, which is an e_assign
assign epcs_epcs_control_port_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_epcs_epcs_control_port;
//cpu_0/instruction_master grant epcs/epcs_control_port, which is an e_assign
assign cpu_0_instruction_master_granted_epcs_epcs_control_port = epcs_epcs_control_port_grant_vector[0];
//cpu_0/instruction_master saved-grant epcs/epcs_control_port, which is an e_assign
assign cpu_0_instruction_master_saved_grant_epcs_epcs_control_port = epcs_epcs_control_port_arb_winner[0] && cpu_0_instruction_master_requests_epcs_epcs_control_port;
//cpu_0/data_master assignment into master qualified-requests vector for epcs/epcs_control_port, which is an e_assign
assign epcs_epcs_control_port_master_qreq_vector[1] = cpu_0_data_master_qualified_request_epcs_epcs_control_port;
//cpu_0/data_master grant epcs/epcs_control_port, which is an e_assign
assign cpu_0_data_master_granted_epcs_epcs_control_port = epcs_epcs_control_port_grant_vector[1];
//cpu_0/data_master saved-grant epcs/epcs_control_port, which is an e_assign
assign cpu_0_data_master_saved_grant_epcs_epcs_control_port = epcs_epcs_control_port_arb_winner[1] && cpu_0_data_master_requests_epcs_epcs_control_port;
//epcs/epcs_control_port chosen-master double-vector, which is an e_assign
assign epcs_epcs_control_port_chosen_master_double_vector = {epcs_epcs_control_port_master_qreq_vector, epcs_epcs_control_port_master_qreq_vector} & ({~epcs_epcs_control_port_master_qreq_vector, ~epcs_epcs_control_port_master_qreq_vector} + epcs_epcs_control_port_arb_addend);
//stable onehot encoding of arb winner
assign epcs_epcs_control_port_arb_winner = (epcs_epcs_control_port_allow_new_arb_cycle & | epcs_epcs_control_port_grant_vector) ? epcs_epcs_control_port_grant_vector : epcs_epcs_control_port_saved_chosen_master_vector;
//saved epcs_epcs_control_port_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_epcs_control_port_saved_chosen_master_vector <= 0;
else if (epcs_epcs_control_port_allow_new_arb_cycle)
epcs_epcs_control_port_saved_chosen_master_vector <= |epcs_epcs_control_port_grant_vector ? epcs_epcs_control_port_grant_vector : epcs_epcs_control_port_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign epcs_epcs_control_port_grant_vector = {(epcs_epcs_control_port_chosen_master_double_vector[1] | epcs_epcs_control_port_chosen_master_double_vector[3]),
(epcs_epcs_control_port_chosen_master_double_vector[0] | epcs_epcs_control_port_chosen_master_double_vector[2])};
//epcs/epcs_control_port chosen master rotated left, which is an e_assign
assign epcs_epcs_control_port_chosen_master_rot_left = (epcs_epcs_control_port_arb_winner << 1) ? (epcs_epcs_control_port_arb_winner << 1) : 1;
//epcs/epcs_control_port's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_epcs_control_port_arb_addend <= 1;
else if (|epcs_epcs_control_port_grant_vector)
epcs_epcs_control_port_arb_addend <= epcs_epcs_control_port_end_xfer? epcs_epcs_control_port_chosen_master_rot_left : epcs_epcs_control_port_grant_vector;
end
//epcs_epcs_control_port_reset_n assignment, which is an e_assign
assign epcs_epcs_control_port_reset_n = reset_n;
assign epcs_epcs_control_port_chipselect = cpu_0_data_master_granted_epcs_epcs_control_port | cpu_0_instruction_master_granted_epcs_epcs_control_port;
//epcs_epcs_control_port_firsttransfer first transaction, which is an e_assign
assign epcs_epcs_control_port_firsttransfer = epcs_epcs_control_port_begins_xfer ? epcs_epcs_control_port_unreg_firsttransfer : epcs_epcs_control_port_reg_firsttransfer;
//epcs_epcs_control_port_unreg_firsttransfer first transaction, which is an e_assign
assign epcs_epcs_control_port_unreg_firsttransfer = ~(epcs_epcs_control_port_slavearbiterlockenable & epcs_epcs_control_port_any_continuerequest);
//epcs_epcs_control_port_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
epcs_epcs_control_port_reg_firsttransfer <= 1'b1;
else if (epcs_epcs_control_port_begins_xfer)
epcs_epcs_control_port_reg_firsttransfer <= epcs_epcs_control_port_unreg_firsttransfer;
end
//epcs_epcs_control_port_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign epcs_epcs_control_port_beginbursttransfer_internal = epcs_epcs_control_port_begins_xfer;
//epcs_epcs_control_port_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign epcs_epcs_control_port_arbitration_holdoff_internal = epcs_epcs_control_port_begins_xfer & epcs_epcs_control_port_firsttransfer;
//~epcs_epcs_control_port_read_n assignment, which is an e_mux
assign epcs_epcs_control_port_read_n = ~((cpu_0_data_master_granted_epcs_epcs_control_port & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_epcs_epcs_control_port & cpu_0_instruction_master_read));
//~epcs_epcs_control_port_write_n assignment, which is an e_mux
assign epcs_epcs_control_port_write_n = ~(cpu_0_data_master_granted_epcs_epcs_control_port & cpu_0_data_master_write);
assign shifted_address_to_epcs_epcs_control_port_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//epcs_epcs_control_port_address mux, which is an e_mux
assign epcs_epcs_control_port_address = (cpu_0_data_master_granted_epcs_epcs_control_port)? (shifted_address_to_epcs_epcs_control_port_from_cpu_0_data_master >> 2) :
(shifted_address_to_epcs_epcs_control_port_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_epcs_epcs_control_port_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_epcs_epcs_control_port_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_epcs_epcs_control_port_end_xfer <= 1;
else
d1_epcs_epcs_control_port_end_xfer <= epcs_epcs_control_port_end_xfer;
end
//epcs_epcs_control_port_waits_for_read in a cycle, which is an e_mux
assign epcs_epcs_control_port_waits_for_read = epcs_epcs_control_port_in_a_read_cycle & epcs_epcs_control_port_begins_xfer;
//epcs_epcs_control_port_in_a_read_cycle assignment, which is an e_assign
assign epcs_epcs_control_port_in_a_read_cycle = (cpu_0_data_master_granted_epcs_epcs_control_port & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_epcs_epcs_control_port & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = epcs_epcs_control_port_in_a_read_cycle;
//epcs_epcs_control_port_waits_for_write in a cycle, which is an e_mux
assign epcs_epcs_control_port_waits_for_write = epcs_epcs_control_port_in_a_write_cycle & epcs_epcs_control_port_begins_xfer;
//epcs_epcs_control_port_in_a_write_cycle assignment, which is an e_assign
assign epcs_epcs_control_port_in_a_write_cycle = cpu_0_data_master_granted_epcs_epcs_control_port & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = epcs_epcs_control_port_in_a_write_cycle;
assign wait_for_epcs_epcs_control_port_counter = 0;
//assign epcs_epcs_control_port_irq_from_sa = epcs_epcs_control_port_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign epcs_epcs_control_port_irq_from_sa = epcs_epcs_control_port_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//epcs/epcs_control_port enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_epcs_epcs_control_port + cpu_0_instruction_master_granted_epcs_epcs_control_port > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_epcs_epcs_control_port + cpu_0_instruction_master_saved_grant_epcs_epcs_control_port > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module i2c_avalon_slave_0_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
i2c_avalon_slave_0_irq,
i2c_avalon_slave_0_readdata,
i2c_avalon_slave_0_waitrequest_n,
reset_n,
// outputs:
cpu_0_data_master_granted_i2c_avalon_slave_0,
cpu_0_data_master_qualified_request_i2c_avalon_slave_0,
cpu_0_data_master_read_data_valid_i2c_avalon_slave_0,
cpu_0_data_master_requests_i2c_avalon_slave_0,
d1_i2c_avalon_slave_0_end_xfer,
i2c_avalon_slave_0_address,
i2c_avalon_slave_0_chipselect,
i2c_avalon_slave_0_irq_from_sa,
i2c_avalon_slave_0_readdata_from_sa,
i2c_avalon_slave_0_reset,
i2c_avalon_slave_0_waitrequest_n_from_sa,
i2c_avalon_slave_0_write,
i2c_avalon_slave_0_writedata
)
;
output cpu_0_data_master_granted_i2c_avalon_slave_0;
output cpu_0_data_master_qualified_request_i2c_avalon_slave_0;
output cpu_0_data_master_read_data_valid_i2c_avalon_slave_0;
output cpu_0_data_master_requests_i2c_avalon_slave_0;
output d1_i2c_avalon_slave_0_end_xfer;
output [ 2: 0] i2c_avalon_slave_0_address;
output i2c_avalon_slave_0_chipselect;
output i2c_avalon_slave_0_irq_from_sa;
output [ 7: 0] i2c_avalon_slave_0_readdata_from_sa;
output i2c_avalon_slave_0_reset;
output i2c_avalon_slave_0_waitrequest_n_from_sa;
output i2c_avalon_slave_0_write;
output [ 7: 0] i2c_avalon_slave_0_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input i2c_avalon_slave_0_irq;
input [ 7: 0] i2c_avalon_slave_0_readdata;
input i2c_avalon_slave_0_waitrequest_n;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_i2c_avalon_slave_0;
wire cpu_0_data_master_qualified_request_i2c_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_i2c_avalon_slave_0;
wire cpu_0_data_master_requests_i2c_avalon_slave_0;
wire cpu_0_data_master_saved_grant_i2c_avalon_slave_0;
reg d1_i2c_avalon_slave_0_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_i2c_avalon_slave_0;
wire [ 2: 0] i2c_avalon_slave_0_address;
wire i2c_avalon_slave_0_allgrants;
wire i2c_avalon_slave_0_allow_new_arb_cycle;
wire i2c_avalon_slave_0_any_bursting_master_saved_grant;
wire i2c_avalon_slave_0_any_continuerequest;
wire i2c_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] i2c_avalon_slave_0_arb_share_counter;
wire [ 2: 0] i2c_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] i2c_avalon_slave_0_arb_share_set_values;
wire i2c_avalon_slave_0_beginbursttransfer_internal;
wire i2c_avalon_slave_0_begins_xfer;
wire i2c_avalon_slave_0_chipselect;
wire i2c_avalon_slave_0_end_xfer;
wire i2c_avalon_slave_0_firsttransfer;
wire i2c_avalon_slave_0_grant_vector;
wire i2c_avalon_slave_0_in_a_read_cycle;
wire i2c_avalon_slave_0_in_a_write_cycle;
wire i2c_avalon_slave_0_irq_from_sa;
wire i2c_avalon_slave_0_master_qreq_vector;
wire i2c_avalon_slave_0_non_bursting_master_requests;
wire i2c_avalon_slave_0_pretend_byte_enable;
wire [ 7: 0] i2c_avalon_slave_0_readdata_from_sa;
reg i2c_avalon_slave_0_reg_firsttransfer;
wire i2c_avalon_slave_0_reset;
reg i2c_avalon_slave_0_slavearbiterlockenable;
wire i2c_avalon_slave_0_slavearbiterlockenable2;
wire i2c_avalon_slave_0_unreg_firsttransfer;
wire i2c_avalon_slave_0_waitrequest_n_from_sa;
wire i2c_avalon_slave_0_waits_for_read;
wire i2c_avalon_slave_0_waits_for_write;
wire i2c_avalon_slave_0_write;
wire [ 7: 0] i2c_avalon_slave_0_writedata;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_i2c_avalon_slave_0_from_cpu_0_data_master;
wire wait_for_i2c_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~i2c_avalon_slave_0_end_xfer;
end
assign i2c_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_i2c_avalon_slave_0));
//assign i2c_avalon_slave_0_readdata_from_sa = i2c_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign i2c_avalon_slave_0_readdata_from_sa = i2c_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_i2c_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 5] , 5'b0} == 24'hb04040) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign i2c_avalon_slave_0_waitrequest_n_from_sa = i2c_avalon_slave_0_waitrequest_n so that symbol knows where to group signals which may go to master only, which is an e_assign
assign i2c_avalon_slave_0_waitrequest_n_from_sa = i2c_avalon_slave_0_waitrequest_n;
//i2c_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign i2c_avalon_slave_0_arb_share_set_values = 1;
//i2c_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign i2c_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_i2c_avalon_slave_0;
//i2c_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
assign i2c_avalon_slave_0_any_bursting_master_saved_grant = 0;
//i2c_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign i2c_avalon_slave_0_arb_share_counter_next_value = i2c_avalon_slave_0_firsttransfer ? (i2c_avalon_slave_0_arb_share_set_values - 1) : |i2c_avalon_slave_0_arb_share_counter ? (i2c_avalon_slave_0_arb_share_counter - 1) : 0;
//i2c_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign i2c_avalon_slave_0_allgrants = |i2c_avalon_slave_0_grant_vector;
//i2c_avalon_slave_0_end_xfer assignment, which is an e_assign
assign i2c_avalon_slave_0_end_xfer = ~(i2c_avalon_slave_0_waits_for_read | i2c_avalon_slave_0_waits_for_write);
//end_xfer_arb_share_counter_term_i2c_avalon_slave_0 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_i2c_avalon_slave_0 = i2c_avalon_slave_0_end_xfer & (~i2c_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//i2c_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign i2c_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_i2c_avalon_slave_0 & i2c_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_i2c_avalon_slave_0 & ~i2c_avalon_slave_0_non_bursting_master_requests);
//i2c_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i2c_avalon_slave_0_arb_share_counter <= 0;
else if (i2c_avalon_slave_0_arb_counter_enable)
i2c_avalon_slave_0_arb_share_counter <= i2c_avalon_slave_0_arb_share_counter_next_value;
end
//i2c_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i2c_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|i2c_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_i2c_avalon_slave_0) | (end_xfer_arb_share_counter_term_i2c_avalon_slave_0 & ~i2c_avalon_slave_0_non_bursting_master_requests))
i2c_avalon_slave_0_slavearbiterlockenable <= |i2c_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master i2c/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = i2c_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//i2c_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign i2c_avalon_slave_0_slavearbiterlockenable2 = |i2c_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master i2c/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = i2c_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//i2c_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign i2c_avalon_slave_0_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_i2c_avalon_slave_0 = cpu_0_data_master_requests_i2c_avalon_slave_0 & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//i2c_avalon_slave_0_writedata mux, which is an e_mux
assign i2c_avalon_slave_0_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_i2c_avalon_slave_0 = cpu_0_data_master_qualified_request_i2c_avalon_slave_0;
//cpu_0/data_master saved-grant i2c/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_i2c_avalon_slave_0 = cpu_0_data_master_requests_i2c_avalon_slave_0;
//allow new arb cycle for i2c/avalon_slave_0, which is an e_assign
assign i2c_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign i2c_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign i2c_avalon_slave_0_master_qreq_vector = 1;
//~i2c_avalon_slave_0_reset assignment, which is an e_assign
assign i2c_avalon_slave_0_reset = ~reset_n;
assign i2c_avalon_slave_0_chipselect = cpu_0_data_master_granted_i2c_avalon_slave_0;
//i2c_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign i2c_avalon_slave_0_firsttransfer = i2c_avalon_slave_0_begins_xfer ? i2c_avalon_slave_0_unreg_firsttransfer : i2c_avalon_slave_0_reg_firsttransfer;
//i2c_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
assign i2c_avalon_slave_0_unreg_firsttransfer = ~(i2c_avalon_slave_0_slavearbiterlockenable & i2c_avalon_slave_0_any_continuerequest);
//i2c_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i2c_avalon_slave_0_reg_firsttransfer <= 1'b1;
else if (i2c_avalon_slave_0_begins_xfer)
i2c_avalon_slave_0_reg_firsttransfer <= i2c_avalon_slave_0_unreg_firsttransfer;
end
//i2c_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign i2c_avalon_slave_0_beginbursttransfer_internal = i2c_avalon_slave_0_begins_xfer;
//i2c_avalon_slave_0_write assignment, which is an e_mux
assign i2c_avalon_slave_0_write = ((cpu_0_data_master_granted_i2c_avalon_slave_0 & cpu_0_data_master_write)) & i2c_avalon_slave_0_pretend_byte_enable;
assign shifted_address_to_i2c_avalon_slave_0_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//i2c_avalon_slave_0_address mux, which is an e_mux
assign i2c_avalon_slave_0_address = shifted_address_to_i2c_avalon_slave_0_from_cpu_0_data_master >> 2;
//d1_i2c_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_i2c_avalon_slave_0_end_xfer <= 1;
else
d1_i2c_avalon_slave_0_end_xfer <= i2c_avalon_slave_0_end_xfer;
end
//i2c_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign i2c_avalon_slave_0_waits_for_read = i2c_avalon_slave_0_in_a_read_cycle & ~i2c_avalon_slave_0_waitrequest_n_from_sa;
//i2c_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign i2c_avalon_slave_0_in_a_read_cycle = cpu_0_data_master_granted_i2c_avalon_slave_0 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = i2c_avalon_slave_0_in_a_read_cycle;
//i2c_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign i2c_avalon_slave_0_waits_for_write = i2c_avalon_slave_0_in_a_write_cycle & ~i2c_avalon_slave_0_waitrequest_n_from_sa;
//i2c_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign i2c_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_i2c_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = i2c_avalon_slave_0_in_a_write_cycle;
assign wait_for_i2c_avalon_slave_0_counter = 0;
//i2c_avalon_slave_0_pretend_byte_enable byte enable port mux, which is an e_mux
assign i2c_avalon_slave_0_pretend_byte_enable = (cpu_0_data_master_granted_i2c_avalon_slave_0)? cpu_0_data_master_byteenable :
-1;
//assign i2c_avalon_slave_0_irq_from_sa = i2c_avalon_slave_0_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign i2c_avalon_slave_0_irq_from_sa = i2c_avalon_slave_0_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//i2c/avalon_slave_0 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_avalon_jtag_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
jtag_uart_avalon_jtag_slave_dataavailable,
jtag_uart_avalon_jtag_slave_irq,
jtag_uart_avalon_jtag_slave_readdata,
jtag_uart_avalon_jtag_slave_readyfordata,
jtag_uart_avalon_jtag_slave_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave,
d1_jtag_uart_avalon_jtag_slave_end_xfer,
jtag_uart_avalon_jtag_slave_address,
jtag_uart_avalon_jtag_slave_chipselect,
jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
jtag_uart_avalon_jtag_slave_irq_from_sa,
jtag_uart_avalon_jtag_slave_read_n,
jtag_uart_avalon_jtag_slave_readdata_from_sa,
jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
jtag_uart_avalon_jtag_slave_reset_n,
jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
jtag_uart_avalon_jtag_slave_write_n,
jtag_uart_avalon_jtag_slave_writedata
)
;
output cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
output cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
output cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
output cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
output d1_jtag_uart_avalon_jtag_slave_end_xfer;
output jtag_uart_avalon_jtag_slave_address;
output jtag_uart_avalon_jtag_slave_chipselect;
output jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
output jtag_uart_avalon_jtag_slave_irq_from_sa;
output jtag_uart_avalon_jtag_slave_read_n;
output [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
output jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
output jtag_uart_avalon_jtag_slave_reset_n;
output jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
output jtag_uart_avalon_jtag_slave_write_n;
output [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input jtag_uart_avalon_jtag_slave_dataavailable;
input jtag_uart_avalon_jtag_slave_irq;
input [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
input jtag_uart_avalon_jtag_slave_readyfordata;
input jtag_uart_avalon_jtag_slave_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
reg d1_jtag_uart_avalon_jtag_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire jtag_uart_avalon_jtag_slave_address;
wire jtag_uart_avalon_jtag_slave_allgrants;
wire jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
wire jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
wire jtag_uart_avalon_jtag_slave_any_continuerequest;
wire jtag_uart_avalon_jtag_slave_arb_counter_enable;
reg [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
wire [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
wire [ 2: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
wire jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
wire jtag_uart_avalon_jtag_slave_begins_xfer;
wire jtag_uart_avalon_jtag_slave_chipselect;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_end_xfer;
wire jtag_uart_avalon_jtag_slave_firsttransfer;
wire jtag_uart_avalon_jtag_slave_grant_vector;
wire jtag_uart_avalon_jtag_slave_in_a_read_cycle;
wire jtag_uart_avalon_jtag_slave_in_a_write_cycle;
wire jtag_uart_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_avalon_jtag_slave_master_qreq_vector;
wire jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
wire jtag_uart_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
reg jtag_uart_avalon_jtag_slave_reg_firsttransfer;
wire jtag_uart_avalon_jtag_slave_reset_n;
reg jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
wire jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
wire jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_avalon_jtag_slave_waits_for_read;
wire jtag_uart_avalon_jtag_slave_waits_for_write;
wire jtag_uart_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
wire [ 23: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_0_data_master;
wire wait_for_jtag_uart_avalon_jtag_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
end
assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
//assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;
assign cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_0_data_master_address_to_slave[23 : 3] , 3'b0} == 24'hb04070) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;
//assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;
//assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;
//jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;
//jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
//jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;
//jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;
//jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;
//jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);
//end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);
//jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
end
//jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
end
//cpu_0/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
//cpu_0/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
//cpu_0/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
//allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign jtag_uart_avalon_jtag_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;
//jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;
assign jtag_uart_avalon_jtag_slave_chipselect = cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
//jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;
//jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);
//jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
else if (jtag_uart_avalon_jtag_slave_begins_xfer)
jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
end
//jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;
//~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_0_data_master_read);
//~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_0_data_master_write);
assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_0_data_master >> 2;
//d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
else
d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
end
//jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;
//jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;
assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
//assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lcd_control_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
lcd_control_slave_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_lcd_control_slave,
cpu_0_data_master_qualified_request_lcd_control_slave,
cpu_0_data_master_read_data_valid_lcd_control_slave,
cpu_0_data_master_requests_lcd_control_slave,
d1_lcd_control_slave_end_xfer,
lcd_control_slave_address,
lcd_control_slave_begintransfer,
lcd_control_slave_read,
lcd_control_slave_readdata_from_sa,
lcd_control_slave_reset_n,
lcd_control_slave_wait_counter_eq_0,
lcd_control_slave_wait_counter_eq_1,
lcd_control_slave_write,
lcd_control_slave_writedata
)
;
output cpu_0_data_master_granted_lcd_control_slave;
output cpu_0_data_master_qualified_request_lcd_control_slave;
output cpu_0_data_master_read_data_valid_lcd_control_slave;
output cpu_0_data_master_requests_lcd_control_slave;
output d1_lcd_control_slave_end_xfer;
output [ 1: 0] lcd_control_slave_address;
output lcd_control_slave_begintransfer;
output lcd_control_slave_read;
output [ 7: 0] lcd_control_slave_readdata_from_sa;
output lcd_control_slave_reset_n;
output lcd_control_slave_wait_counter_eq_0;
output lcd_control_slave_wait_counter_eq_1;
output lcd_control_slave_write;
output [ 7: 0] lcd_control_slave_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 7: 0] lcd_control_slave_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_lcd_control_slave;
wire cpu_0_data_master_qualified_request_lcd_control_slave;
wire cpu_0_data_master_read_data_valid_lcd_control_slave;
wire cpu_0_data_master_requests_lcd_control_slave;
wire cpu_0_data_master_saved_grant_lcd_control_slave;
reg d1_lcd_control_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_lcd_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] lcd_control_slave_address;
wire lcd_control_slave_allgrants;
wire lcd_control_slave_allow_new_arb_cycle;
wire lcd_control_slave_any_bursting_master_saved_grant;
wire lcd_control_slave_any_continuerequest;
wire lcd_control_slave_arb_counter_enable;
reg [ 2: 0] lcd_control_slave_arb_share_counter;
wire [ 2: 0] lcd_control_slave_arb_share_counter_next_value;
wire [ 2: 0] lcd_control_slave_arb_share_set_values;
wire lcd_control_slave_beginbursttransfer_internal;
wire lcd_control_slave_begins_xfer;
wire lcd_control_slave_begintransfer;
wire [ 5: 0] lcd_control_slave_counter_load_value;
wire lcd_control_slave_end_xfer;
wire lcd_control_slave_firsttransfer;
wire lcd_control_slave_grant_vector;
wire lcd_control_slave_in_a_read_cycle;
wire lcd_control_slave_in_a_write_cycle;
wire lcd_control_slave_master_qreq_vector;
wire lcd_control_slave_non_bursting_master_requests;
wire lcd_control_slave_pretend_byte_enable;
wire lcd_control_slave_read;
wire [ 7: 0] lcd_control_slave_readdata_from_sa;
reg lcd_control_slave_reg_firsttransfer;
wire lcd_control_slave_reset_n;
reg lcd_control_slave_slavearbiterlockenable;
wire lcd_control_slave_slavearbiterlockenable2;
wire lcd_control_slave_unreg_firsttransfer;
reg [ 5: 0] lcd_control_slave_wait_counter;
wire lcd_control_slave_wait_counter_eq_0;
wire lcd_control_slave_wait_counter_eq_1;
wire lcd_control_slave_waits_for_read;
wire lcd_control_slave_waits_for_write;
wire lcd_control_slave_write;
wire [ 7: 0] lcd_control_slave_writedata;
wire [ 23: 0] shifted_address_to_lcd_control_slave_from_cpu_0_data_master;
wire wait_for_lcd_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~lcd_control_slave_end_xfer;
end
assign lcd_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_lcd_control_slave));
//assign lcd_control_slave_readdata_from_sa = lcd_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign lcd_control_slave_readdata_from_sa = lcd_control_slave_readdata;
assign cpu_0_data_master_requests_lcd_control_slave = ({cpu_0_data_master_address_to_slave[23 : 4] , 4'b0} == 24'hb04060) & (cpu_0_data_master_read | cpu_0_data_master_write);
//lcd_control_slave_arb_share_counter set values, which is an e_mux
assign lcd_control_slave_arb_share_set_values = 1;
//lcd_control_slave_non_bursting_master_requests mux, which is an e_mux
assign lcd_control_slave_non_bursting_master_requests = cpu_0_data_master_requests_lcd_control_slave;
//lcd_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign lcd_control_slave_any_bursting_master_saved_grant = 0;
//lcd_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign lcd_control_slave_arb_share_counter_next_value = lcd_control_slave_firsttransfer ? (lcd_control_slave_arb_share_set_values - 1) : |lcd_control_slave_arb_share_counter ? (lcd_control_slave_arb_share_counter - 1) : 0;
//lcd_control_slave_allgrants all slave grants, which is an e_mux
assign lcd_control_slave_allgrants = |lcd_control_slave_grant_vector;
//lcd_control_slave_end_xfer assignment, which is an e_assign
assign lcd_control_slave_end_xfer = ~(lcd_control_slave_waits_for_read | lcd_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_lcd_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_lcd_control_slave = lcd_control_slave_end_xfer & (~lcd_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//lcd_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign lcd_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_lcd_control_slave & lcd_control_slave_allgrants) | (end_xfer_arb_share_counter_term_lcd_control_slave & ~lcd_control_slave_non_bursting_master_requests);
//lcd_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_control_slave_arb_share_counter <= 0;
else if (lcd_control_slave_arb_counter_enable)
lcd_control_slave_arb_share_counter <= lcd_control_slave_arb_share_counter_next_value;
end
//lcd_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_control_slave_slavearbiterlockenable <= 0;
else if ((|lcd_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_lcd_control_slave) | (end_xfer_arb_share_counter_term_lcd_control_slave & ~lcd_control_slave_non_bursting_master_requests))
lcd_control_slave_slavearbiterlockenable <= |lcd_control_slave_arb_share_counter_next_value;
end
//cpu_0/data_master lcd/control_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = lcd_control_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//lcd_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign lcd_control_slave_slavearbiterlockenable2 = |lcd_control_slave_arb_share_counter_next_value;
//cpu_0/data_master lcd/control_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = lcd_control_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//lcd_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign lcd_control_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_lcd_control_slave = cpu_0_data_master_requests_lcd_control_slave;
//lcd_control_slave_writedata mux, which is an e_mux
assign lcd_control_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_lcd_control_slave = cpu_0_data_master_qualified_request_lcd_control_slave;
//cpu_0/data_master saved-grant lcd/control_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_lcd_control_slave = cpu_0_data_master_requests_lcd_control_slave;
//allow new arb cycle for lcd/control_slave, which is an e_assign
assign lcd_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign lcd_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign lcd_control_slave_master_qreq_vector = 1;
assign lcd_control_slave_begintransfer = lcd_control_slave_begins_xfer;
//lcd_control_slave_reset_n assignment, which is an e_assign
assign lcd_control_slave_reset_n = reset_n;
//lcd_control_slave_firsttransfer first transaction, which is an e_assign
assign lcd_control_slave_firsttransfer = lcd_control_slave_begins_xfer ? lcd_control_slave_unreg_firsttransfer : lcd_control_slave_reg_firsttransfer;
//lcd_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign lcd_control_slave_unreg_firsttransfer = ~(lcd_control_slave_slavearbiterlockenable & lcd_control_slave_any_continuerequest);
//lcd_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_control_slave_reg_firsttransfer <= 1'b1;
else if (lcd_control_slave_begins_xfer)
lcd_control_slave_reg_firsttransfer <= lcd_control_slave_unreg_firsttransfer;
end
//lcd_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign lcd_control_slave_beginbursttransfer_internal = lcd_control_slave_begins_xfer;
//lcd_control_slave_read assignment, which is an e_mux
assign lcd_control_slave_read = ((cpu_0_data_master_granted_lcd_control_slave & cpu_0_data_master_read))& ~lcd_control_slave_begins_xfer & (lcd_control_slave_wait_counter < 13);
//lcd_control_slave_write assignment, which is an e_mux
assign lcd_control_slave_write = ((cpu_0_data_master_granted_lcd_control_slave & cpu_0_data_master_write)) & ~lcd_control_slave_begins_xfer & (lcd_control_slave_wait_counter >= 13) & (lcd_control_slave_wait_counter < 26) & lcd_control_slave_pretend_byte_enable;
assign shifted_address_to_lcd_control_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//lcd_control_slave_address mux, which is an e_mux
assign lcd_control_slave_address = shifted_address_to_lcd_control_slave_from_cpu_0_data_master >> 2;
//d1_lcd_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_lcd_control_slave_end_xfer <= 1;
else
d1_lcd_control_slave_end_xfer <= lcd_control_slave_end_xfer;
end
//lcd_control_slave_wait_counter_eq_1 assignment, which is an e_assign
assign lcd_control_slave_wait_counter_eq_1 = lcd_control_slave_wait_counter == 1;
//lcd_control_slave_waits_for_read in a cycle, which is an e_mux
assign lcd_control_slave_waits_for_read = lcd_control_slave_in_a_read_cycle & wait_for_lcd_control_slave_counter;
//lcd_control_slave_in_a_read_cycle assignment, which is an e_assign
assign lcd_control_slave_in_a_read_cycle = cpu_0_data_master_granted_lcd_control_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = lcd_control_slave_in_a_read_cycle;
//lcd_control_slave_waits_for_write in a cycle, which is an e_mux
assign lcd_control_slave_waits_for_write = lcd_control_slave_in_a_write_cycle & wait_for_lcd_control_slave_counter;
//lcd_control_slave_in_a_write_cycle assignment, which is an e_assign
assign lcd_control_slave_in_a_write_cycle = cpu_0_data_master_granted_lcd_control_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = lcd_control_slave_in_a_write_cycle;
assign lcd_control_slave_wait_counter_eq_0 = lcd_control_slave_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
lcd_control_slave_wait_counter <= 0;
else
lcd_control_slave_wait_counter <= lcd_control_slave_counter_load_value;
end
assign lcd_control_slave_counter_load_value = ((lcd_control_slave_in_a_read_cycle & lcd_control_slave_begins_xfer))? 24 :
((lcd_control_slave_in_a_write_cycle & lcd_control_slave_begins_xfer))? 37 :
(~lcd_control_slave_wait_counter_eq_0)? lcd_control_slave_wait_counter - 1 :
0;
assign wait_for_lcd_control_slave_counter = lcd_control_slave_begins_xfer | ~lcd_control_slave_wait_counter_eq_0;
//lcd_control_slave_pretend_byte_enable byte enable port mux, which is an e_mux
assign lcd_control_slave_pretend_byte_enable = (cpu_0_data_master_granted_lcd_control_slave)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//lcd/control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory2_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_read,
onchip_memory2_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_onchip_memory2_s1,
cpu_0_data_master_qualified_request_onchip_memory2_s1,
cpu_0_data_master_read_data_valid_onchip_memory2_s1,
cpu_0_data_master_requests_onchip_memory2_s1,
cpu_0_instruction_master_granted_onchip_memory2_s1,
cpu_0_instruction_master_qualified_request_onchip_memory2_s1,
cpu_0_instruction_master_read_data_valid_onchip_memory2_s1,
cpu_0_instruction_master_requests_onchip_memory2_s1,
d1_onchip_memory2_s1_end_xfer,
onchip_memory2_s1_address,
onchip_memory2_s1_byteenable,
onchip_memory2_s1_chipselect,
onchip_memory2_s1_clken,
onchip_memory2_s1_readdata_from_sa,
onchip_memory2_s1_reset,
onchip_memory2_s1_write,
onchip_memory2_s1_writedata,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1
)
;
output cpu_0_data_master_granted_onchip_memory2_s1;
output cpu_0_data_master_qualified_request_onchip_memory2_s1;
output cpu_0_data_master_read_data_valid_onchip_memory2_s1;
output cpu_0_data_master_requests_onchip_memory2_s1;
output cpu_0_instruction_master_granted_onchip_memory2_s1;
output cpu_0_instruction_master_qualified_request_onchip_memory2_s1;
output cpu_0_instruction_master_read_data_valid_onchip_memory2_s1;
output cpu_0_instruction_master_requests_onchip_memory2_s1;
output d1_onchip_memory2_s1_end_xfer;
output [ 9: 0] onchip_memory2_s1_address;
output [ 3: 0] onchip_memory2_s1_byteenable;
output onchip_memory2_s1_chipselect;
output onchip_memory2_s1_clken;
output [ 31: 0] onchip_memory2_s1_readdata_from_sa;
output onchip_memory2_s1_reset;
output onchip_memory2_s1_write;
output [ 31: 0] onchip_memory2_s1_writedata;
output registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 23: 0] cpu_0_instruction_master_address_to_slave;
input [ 1: 0] cpu_0_instruction_master_latency_counter;
input cpu_0_instruction_master_read;
input [ 31: 0] onchip_memory2_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_onchip_memory2_s1;
wire cpu_0_data_master_qualified_request_onchip_memory2_s1;
wire cpu_0_data_master_read_data_valid_onchip_memory2_s1;
reg cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register;
wire cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register_in;
wire cpu_0_data_master_requests_onchip_memory2_s1;
wire cpu_0_data_master_saved_grant_onchip_memory2_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_onchip_memory2_s1;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_s1;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_s1;
reg cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register_in;
wire cpu_0_instruction_master_requests_onchip_memory2_s1;
wire cpu_0_instruction_master_saved_grant_onchip_memory2_s1;
reg d1_onchip_memory2_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_onchip_memory2_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_s1;
wire [ 9: 0] onchip_memory2_s1_address;
wire onchip_memory2_s1_allgrants;
wire onchip_memory2_s1_allow_new_arb_cycle;
wire onchip_memory2_s1_any_bursting_master_saved_grant;
wire onchip_memory2_s1_any_continuerequest;
reg [ 1: 0] onchip_memory2_s1_arb_addend;
wire onchip_memory2_s1_arb_counter_enable;
reg [ 2: 0] onchip_memory2_s1_arb_share_counter;
wire [ 2: 0] onchip_memory2_s1_arb_share_counter_next_value;
wire [ 2: 0] onchip_memory2_s1_arb_share_set_values;
wire [ 1: 0] onchip_memory2_s1_arb_winner;
wire onchip_memory2_s1_arbitration_holdoff_internal;
wire onchip_memory2_s1_beginbursttransfer_internal;
wire onchip_memory2_s1_begins_xfer;
wire [ 3: 0] onchip_memory2_s1_byteenable;
wire onchip_memory2_s1_chipselect;
wire [ 3: 0] onchip_memory2_s1_chosen_master_double_vector;
wire [ 1: 0] onchip_memory2_s1_chosen_master_rot_left;
wire onchip_memory2_s1_clken;
wire onchip_memory2_s1_end_xfer;
wire onchip_memory2_s1_firsttransfer;
wire [ 1: 0] onchip_memory2_s1_grant_vector;
wire onchip_memory2_s1_in_a_read_cycle;
wire onchip_memory2_s1_in_a_write_cycle;
wire [ 1: 0] onchip_memory2_s1_master_qreq_vector;
wire onchip_memory2_s1_non_bursting_master_requests;
wire [ 31: 0] onchip_memory2_s1_readdata_from_sa;
reg onchip_memory2_s1_reg_firsttransfer;
wire onchip_memory2_s1_reset;
reg [ 1: 0] onchip_memory2_s1_saved_chosen_master_vector;
reg onchip_memory2_s1_slavearbiterlockenable;
wire onchip_memory2_s1_slavearbiterlockenable2;
wire onchip_memory2_s1_unreg_firsttransfer;
wire onchip_memory2_s1_waits_for_read;
wire onchip_memory2_s1_waits_for_write;
wire onchip_memory2_s1_write;
wire [ 31: 0] onchip_memory2_s1_writedata;
wire p1_cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register;
wire p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1;
wire [ 23: 0] shifted_address_to_onchip_memory2_s1_from_cpu_0_data_master;
wire [ 23: 0] shifted_address_to_onchip_memory2_s1_from_cpu_0_instruction_master;
wire wait_for_onchip_memory2_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~onchip_memory2_s1_end_xfer;
end
assign onchip_memory2_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_onchip_memory2_s1 | cpu_0_instruction_master_qualified_request_onchip_memory2_s1));
//assign onchip_memory2_s1_readdata_from_sa = onchip_memory2_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign onchip_memory2_s1_readdata_from_sa = onchip_memory2_s1_readdata;
assign cpu_0_data_master_requests_onchip_memory2_s1 = ({cpu_0_data_master_address_to_slave[23 : 12] , 12'b0} == 24'hb01000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register_in;
//onchip_memory2_s1_arb_share_counter set values, which is an e_mux
assign onchip_memory2_s1_arb_share_set_values = 1;
//onchip_memory2_s1_non_bursting_master_requests mux, which is an e_mux
assign onchip_memory2_s1_non_bursting_master_requests = cpu_0_data_master_requests_onchip_memory2_s1 |
cpu_0_instruction_master_requests_onchip_memory2_s1 |
cpu_0_data_master_requests_onchip_memory2_s1 |
cpu_0_instruction_master_requests_onchip_memory2_s1;
//onchip_memory2_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign onchip_memory2_s1_any_bursting_master_saved_grant = 0;
//onchip_memory2_s1_arb_share_counter_next_value assignment, which is an e_assign
assign onchip_memory2_s1_arb_share_counter_next_value = onchip_memory2_s1_firsttransfer ? (onchip_memory2_s1_arb_share_set_values - 1) : |onchip_memory2_s1_arb_share_counter ? (onchip_memory2_s1_arb_share_counter - 1) : 0;
//onchip_memory2_s1_allgrants all slave grants, which is an e_mux
assign onchip_memory2_s1_allgrants = (|onchip_memory2_s1_grant_vector) |
(|onchip_memory2_s1_grant_vector) |
(|onchip_memory2_s1_grant_vector) |
(|onchip_memory2_s1_grant_vector);
//onchip_memory2_s1_end_xfer assignment, which is an e_assign
assign onchip_memory2_s1_end_xfer = ~(onchip_memory2_s1_waits_for_read | onchip_memory2_s1_waits_for_write);
//end_xfer_arb_share_counter_term_onchip_memory2_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_onchip_memory2_s1 = onchip_memory2_s1_end_xfer & (~onchip_memory2_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//onchip_memory2_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign onchip_memory2_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_memory2_s1 & onchip_memory2_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_memory2_s1 & ~onchip_memory2_s1_non_bursting_master_requests);
//onchip_memory2_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_s1_arb_share_counter <= 0;
else if (onchip_memory2_s1_arb_counter_enable)
onchip_memory2_s1_arb_share_counter <= onchip_memory2_s1_arb_share_counter_next_value;
end
//onchip_memory2_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_s1_slavearbiterlockenable <= 0;
else if ((|onchip_memory2_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_memory2_s1) | (end_xfer_arb_share_counter_term_onchip_memory2_s1 & ~onchip_memory2_s1_non_bursting_master_requests))
onchip_memory2_s1_slavearbiterlockenable <= |onchip_memory2_s1_arb_share_counter_next_value;
end
//cpu_0/data_master onchip_memory2/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = onchip_memory2_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//onchip_memory2_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign onchip_memory2_s1_slavearbiterlockenable2 = |onchip_memory2_s1_arb_share_counter_next_value;
//cpu_0/data_master onchip_memory2/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = onchip_memory2_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master onchip_memory2/s1 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = onchip_memory2_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master onchip_memory2/s1 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = onchip_memory2_s1_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted onchip_memory2/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_s1 <= cpu_0_instruction_master_saved_grant_onchip_memory2_s1 ? 1 : (onchip_memory2_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_onchip_memory2_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_s1 & cpu_0_instruction_master_requests_onchip_memory2_s1;
//onchip_memory2_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign onchip_memory2_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_onchip_memory2_s1 = cpu_0_data_master_requests_onchip_memory2_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register_in = cpu_0_data_master_granted_onchip_memory2_s1 & cpu_0_data_master_read & ~onchip_memory2_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register = {cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register, cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register_in};
//cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_onchip_memory2_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_s1_shift_register;
//onchip_memory2_s1_writedata mux, which is an e_mux
assign onchip_memory2_s1_writedata = cpu_0_data_master_writedata;
//mux onchip_memory2_s1_clken, which is an e_mux
assign onchip_memory2_s1_clken = 1'b1;
assign cpu_0_instruction_master_requests_onchip_memory2_s1 = (({cpu_0_instruction_master_address_to_slave[23 : 12] , 12'b0} == 24'hb01000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted onchip_memory2/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_s1 <= cpu_0_data_master_saved_grant_onchip_memory2_s1 ? 1 : (onchip_memory2_s1_arbitration_holdoff_internal | ~cpu_0_data_master_requests_onchip_memory2_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_s1 & cpu_0_data_master_requests_onchip_memory2_s1;
assign cpu_0_instruction_master_qualified_request_onchip_memory2_s1 = cpu_0_instruction_master_requests_onchip_memory2_s1 & ~((cpu_0_instruction_master_read & ((1 < cpu_0_instruction_master_latency_counter))) | cpu_0_data_master_arbiterlock);
//cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register_in = cpu_0_instruction_master_granted_onchip_memory2_s1 & cpu_0_instruction_master_read & ~onchip_memory2_s1_waits_for_read;
//shift register p1 cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register = {cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register, cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register_in};
//cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register <= 0;
else
cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register;
end
//local readdatavalid cpu_0_instruction_master_read_data_valid_onchip_memory2_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_s1 = cpu_0_instruction_master_read_data_valid_onchip_memory2_s1_shift_register;
//allow new arb cycle for onchip_memory2/s1, which is an e_assign
assign onchip_memory2_s1_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for onchip_memory2/s1, which is an e_assign
assign onchip_memory2_s1_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_onchip_memory2_s1;
//cpu_0/instruction_master grant onchip_memory2/s1, which is an e_assign
assign cpu_0_instruction_master_granted_onchip_memory2_s1 = onchip_memory2_s1_grant_vector[0];
//cpu_0/instruction_master saved-grant onchip_memory2/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_onchip_memory2_s1 = onchip_memory2_s1_arb_winner[0] && cpu_0_instruction_master_requests_onchip_memory2_s1;
//cpu_0/data_master assignment into master qualified-requests vector for onchip_memory2/s1, which is an e_assign
assign onchip_memory2_s1_master_qreq_vector[1] = cpu_0_data_master_qualified_request_onchip_memory2_s1;
//cpu_0/data_master grant onchip_memory2/s1, which is an e_assign
assign cpu_0_data_master_granted_onchip_memory2_s1 = onchip_memory2_s1_grant_vector[1];
//cpu_0/data_master saved-grant onchip_memory2/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_onchip_memory2_s1 = onchip_memory2_s1_arb_winner[1] && cpu_0_data_master_requests_onchip_memory2_s1;
//onchip_memory2/s1 chosen-master double-vector, which is an e_assign
assign onchip_memory2_s1_chosen_master_double_vector = {onchip_memory2_s1_master_qreq_vector, onchip_memory2_s1_master_qreq_vector} & ({~onchip_memory2_s1_master_qreq_vector, ~onchip_memory2_s1_master_qreq_vector} + onchip_memory2_s1_arb_addend);
//stable onehot encoding of arb winner
assign onchip_memory2_s1_arb_winner = (onchip_memory2_s1_allow_new_arb_cycle & | onchip_memory2_s1_grant_vector) ? onchip_memory2_s1_grant_vector : onchip_memory2_s1_saved_chosen_master_vector;
//saved onchip_memory2_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_s1_saved_chosen_master_vector <= 0;
else if (onchip_memory2_s1_allow_new_arb_cycle)
onchip_memory2_s1_saved_chosen_master_vector <= |onchip_memory2_s1_grant_vector ? onchip_memory2_s1_grant_vector : onchip_memory2_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign onchip_memory2_s1_grant_vector = {(onchip_memory2_s1_chosen_master_double_vector[1] | onchip_memory2_s1_chosen_master_double_vector[3]),
(onchip_memory2_s1_chosen_master_double_vector[0] | onchip_memory2_s1_chosen_master_double_vector[2])};
//onchip_memory2/s1 chosen master rotated left, which is an e_assign
assign onchip_memory2_s1_chosen_master_rot_left = (onchip_memory2_s1_arb_winner << 1) ? (onchip_memory2_s1_arb_winner << 1) : 1;
//onchip_memory2/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_s1_arb_addend <= 1;
else if (|onchip_memory2_s1_grant_vector)
onchip_memory2_s1_arb_addend <= onchip_memory2_s1_end_xfer? onchip_memory2_s1_chosen_master_rot_left : onchip_memory2_s1_grant_vector;
end
//~onchip_memory2_s1_reset assignment, which is an e_assign
assign onchip_memory2_s1_reset = ~reset_n;
assign onchip_memory2_s1_chipselect = cpu_0_data_master_granted_onchip_memory2_s1 | cpu_0_instruction_master_granted_onchip_memory2_s1;
//onchip_memory2_s1_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_s1_firsttransfer = onchip_memory2_s1_begins_xfer ? onchip_memory2_s1_unreg_firsttransfer : onchip_memory2_s1_reg_firsttransfer;
//onchip_memory2_s1_unreg_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_s1_unreg_firsttransfer = ~(onchip_memory2_s1_slavearbiterlockenable & onchip_memory2_s1_any_continuerequest);
//onchip_memory2_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_s1_reg_firsttransfer <= 1'b1;
else if (onchip_memory2_s1_begins_xfer)
onchip_memory2_s1_reg_firsttransfer <= onchip_memory2_s1_unreg_firsttransfer;
end
//onchip_memory2_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign onchip_memory2_s1_beginbursttransfer_internal = onchip_memory2_s1_begins_xfer;
//onchip_memory2_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign onchip_memory2_s1_arbitration_holdoff_internal = onchip_memory2_s1_begins_xfer & onchip_memory2_s1_firsttransfer;
//onchip_memory2_s1_write assignment, which is an e_mux
assign onchip_memory2_s1_write = cpu_0_data_master_granted_onchip_memory2_s1 & cpu_0_data_master_write;
assign shifted_address_to_onchip_memory2_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//onchip_memory2_s1_address mux, which is an e_mux
assign onchip_memory2_s1_address = (cpu_0_data_master_granted_onchip_memory2_s1)? (shifted_address_to_onchip_memory2_s1_from_cpu_0_data_master >> 2) :
(shifted_address_to_onchip_memory2_s1_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_onchip_memory2_s1_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_onchip_memory2_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_onchip_memory2_s1_end_xfer <= 1;
else
d1_onchip_memory2_s1_end_xfer <= onchip_memory2_s1_end_xfer;
end
//onchip_memory2_s1_waits_for_read in a cycle, which is an e_mux
assign onchip_memory2_s1_waits_for_read = onchip_memory2_s1_in_a_read_cycle & 0;
//onchip_memory2_s1_in_a_read_cycle assignment, which is an e_assign
assign onchip_memory2_s1_in_a_read_cycle = (cpu_0_data_master_granted_onchip_memory2_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_onchip_memory2_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = onchip_memory2_s1_in_a_read_cycle;
//onchip_memory2_s1_waits_for_write in a cycle, which is an e_mux
assign onchip_memory2_s1_waits_for_write = onchip_memory2_s1_in_a_write_cycle & 0;
//onchip_memory2_s1_in_a_write_cycle assignment, which is an e_assign
assign onchip_memory2_s1_in_a_write_cycle = cpu_0_data_master_granted_onchip_memory2_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = onchip_memory2_s1_in_a_write_cycle;
assign wait_for_onchip_memory2_s1_counter = 0;
//onchip_memory2_s1_byteenable byte enable port mux, which is an e_mux
assign onchip_memory2_s1_byteenable = (cpu_0_data_master_granted_onchip_memory2_s1)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//onchip_memory2/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_onchip_memory2_s1 + cpu_0_instruction_master_granted_onchip_memory2_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_onchip_memory2_s1 + cpu_0_instruction_master_saved_grant_onchip_memory2_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sram_avalon_slave_0_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_16,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_dbs_address,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_read,
reset_n,
sram_avalon_slave_0_readdata,
// outputs:
cpu_0_data_master_byteenable_sram_avalon_slave_0,
cpu_0_data_master_granted_sram_avalon_slave_0,
cpu_0_data_master_qualified_request_sram_avalon_slave_0,
cpu_0_data_master_read_data_valid_sram_avalon_slave_0,
cpu_0_data_master_requests_sram_avalon_slave_0,
cpu_0_instruction_master_granted_sram_avalon_slave_0,
cpu_0_instruction_master_qualified_request_sram_avalon_slave_0,
cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0,
cpu_0_instruction_master_requests_sram_avalon_slave_0,
d1_sram_avalon_slave_0_end_xfer,
sram_avalon_slave_0_address,
sram_avalon_slave_0_byteenable_n,
sram_avalon_slave_0_chipselect_n,
sram_avalon_slave_0_read_n,
sram_avalon_slave_0_readdata_from_sa,
sram_avalon_slave_0_reset_n,
sram_avalon_slave_0_wait_counter_eq_0,
sram_avalon_slave_0_write_n,
sram_avalon_slave_0_writedata
)
;
output [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0;
output cpu_0_data_master_granted_sram_avalon_slave_0;
output cpu_0_data_master_qualified_request_sram_avalon_slave_0;
output cpu_0_data_master_read_data_valid_sram_avalon_slave_0;
output cpu_0_data_master_requests_sram_avalon_slave_0;
output cpu_0_instruction_master_granted_sram_avalon_slave_0;
output cpu_0_instruction_master_qualified_request_sram_avalon_slave_0;
output cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0;
output cpu_0_instruction_master_requests_sram_avalon_slave_0;
output d1_sram_avalon_slave_0_end_xfer;
output [ 17: 0] sram_avalon_slave_0_address;
output [ 1: 0] sram_avalon_slave_0_byteenable_n;
output sram_avalon_slave_0_chipselect_n;
output sram_avalon_slave_0_read_n;
output [ 15: 0] sram_avalon_slave_0_readdata_from_sa;
output sram_avalon_slave_0_reset_n;
output sram_avalon_slave_0_wait_counter_eq_0;
output sram_avalon_slave_0_write_n;
output [ 15: 0] sram_avalon_slave_0_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input [ 1: 0] cpu_0_data_master_dbs_address;
input [ 15: 0] cpu_0_data_master_dbs_write_16;
input cpu_0_data_master_no_byte_enables_and_last_term;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 23: 0] cpu_0_instruction_master_address_to_slave;
input [ 1: 0] cpu_0_instruction_master_dbs_address;
input [ 1: 0] cpu_0_instruction_master_latency_counter;
input cpu_0_instruction_master_read;
input reset_n;
input [ 15: 0] sram_avalon_slave_0_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0;
wire [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_0;
wire [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_1;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sram_avalon_slave_0;
wire cpu_0_data_master_qualified_request_sram_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_sram_avalon_slave_0;
wire cpu_0_data_master_requests_sram_avalon_slave_0;
wire cpu_0_data_master_saved_grant_sram_avalon_slave_0;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_sram_avalon_slave_0;
wire cpu_0_instruction_master_qualified_request_sram_avalon_slave_0;
wire cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0;
wire cpu_0_instruction_master_requests_sram_avalon_slave_0;
wire cpu_0_instruction_master_saved_grant_sram_avalon_slave_0;
reg d1_reasons_to_wait;
reg d1_sram_avalon_slave_0_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sram_avalon_slave_0;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_sram_avalon_slave_0;
reg last_cycle_cpu_0_instruction_master_granted_slave_sram_avalon_slave_0;
wire [ 23: 0] shifted_address_to_sram_avalon_slave_0_from_cpu_0_data_master;
wire [ 23: 0] shifted_address_to_sram_avalon_slave_0_from_cpu_0_instruction_master;
wire [ 17: 0] sram_avalon_slave_0_address;
wire sram_avalon_slave_0_allgrants;
wire sram_avalon_slave_0_allow_new_arb_cycle;
wire sram_avalon_slave_0_any_bursting_master_saved_grant;
wire sram_avalon_slave_0_any_continuerequest;
reg [ 1: 0] sram_avalon_slave_0_arb_addend;
wire sram_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] sram_avalon_slave_0_arb_share_counter;
wire [ 2: 0] sram_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] sram_avalon_slave_0_arb_share_set_values;
wire [ 1: 0] sram_avalon_slave_0_arb_winner;
wire sram_avalon_slave_0_arbitration_holdoff_internal;
wire sram_avalon_slave_0_beginbursttransfer_internal;
wire sram_avalon_slave_0_begins_xfer;
wire [ 1: 0] sram_avalon_slave_0_byteenable_n;
wire sram_avalon_slave_0_chipselect_n;
wire [ 3: 0] sram_avalon_slave_0_chosen_master_double_vector;
wire [ 1: 0] sram_avalon_slave_0_chosen_master_rot_left;
wire sram_avalon_slave_0_counter_load_value;
wire sram_avalon_slave_0_end_xfer;
wire sram_avalon_slave_0_firsttransfer;
wire [ 1: 0] sram_avalon_slave_0_grant_vector;
wire sram_avalon_slave_0_in_a_read_cycle;
wire sram_avalon_slave_0_in_a_write_cycle;
wire [ 1: 0] sram_avalon_slave_0_master_qreq_vector;
wire sram_avalon_slave_0_non_bursting_master_requests;
wire sram_avalon_slave_0_read_n;
wire [ 15: 0] sram_avalon_slave_0_readdata_from_sa;
reg sram_avalon_slave_0_reg_firsttransfer;
wire sram_avalon_slave_0_reset_n;
reg [ 1: 0] sram_avalon_slave_0_saved_chosen_master_vector;
reg sram_avalon_slave_0_slavearbiterlockenable;
wire sram_avalon_slave_0_slavearbiterlockenable2;
wire sram_avalon_slave_0_unreg_firsttransfer;
reg sram_avalon_slave_0_wait_counter;
wire sram_avalon_slave_0_wait_counter_eq_0;
wire sram_avalon_slave_0_waits_for_read;
wire sram_avalon_slave_0_waits_for_write;
wire sram_avalon_slave_0_write_n;
wire [ 15: 0] sram_avalon_slave_0_writedata;
wire wait_for_sram_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sram_avalon_slave_0_end_xfer;
end
assign sram_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sram_avalon_slave_0 | cpu_0_instruction_master_qualified_request_sram_avalon_slave_0));
//assign sram_avalon_slave_0_readdata_from_sa = sram_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sram_avalon_slave_0_readdata_from_sa = sram_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_sram_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 19] , 19'b0} == 24'ha80000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//sram_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign sram_avalon_slave_0_arb_share_set_values = (cpu_0_data_master_granted_sram_avalon_slave_0)? 2 :
(cpu_0_instruction_master_granted_sram_avalon_slave_0)? 2 :
(cpu_0_data_master_granted_sram_avalon_slave_0)? 2 :
(cpu_0_instruction_master_granted_sram_avalon_slave_0)? 2 :
1;
//sram_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign sram_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_sram_avalon_slave_0 |
cpu_0_instruction_master_requests_sram_avalon_slave_0 |
cpu_0_data_master_requests_sram_avalon_slave_0 |
cpu_0_instruction_master_requests_sram_avalon_slave_0;
//sram_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
assign sram_avalon_slave_0_any_bursting_master_saved_grant = 0;
//sram_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign sram_avalon_slave_0_arb_share_counter_next_value = sram_avalon_slave_0_firsttransfer ? (sram_avalon_slave_0_arb_share_set_values - 1) : |sram_avalon_slave_0_arb_share_counter ? (sram_avalon_slave_0_arb_share_counter - 1) : 0;
//sram_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign sram_avalon_slave_0_allgrants = (|sram_avalon_slave_0_grant_vector) |
(|sram_avalon_slave_0_grant_vector) |
(|sram_avalon_slave_0_grant_vector) |
(|sram_avalon_slave_0_grant_vector);
//sram_avalon_slave_0_end_xfer assignment, which is an e_assign
assign sram_avalon_slave_0_end_xfer = ~(sram_avalon_slave_0_waits_for_read | sram_avalon_slave_0_waits_for_write);
//end_xfer_arb_share_counter_term_sram_avalon_slave_0 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sram_avalon_slave_0 = sram_avalon_slave_0_end_xfer & (~sram_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sram_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign sram_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_sram_avalon_slave_0 & sram_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_sram_avalon_slave_0 & ~sram_avalon_slave_0_non_bursting_master_requests);
//sram_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_arb_share_counter <= 0;
else if (sram_avalon_slave_0_arb_counter_enable)
sram_avalon_slave_0_arb_share_counter <= sram_avalon_slave_0_arb_share_counter_next_value;
end
//sram_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|sram_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_sram_avalon_slave_0) | (end_xfer_arb_share_counter_term_sram_avalon_slave_0 & ~sram_avalon_slave_0_non_bursting_master_requests))
sram_avalon_slave_0_slavearbiterlockenable <= |sram_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master sram/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sram_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sram_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sram_avalon_slave_0_slavearbiterlockenable2 = |sram_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master sram/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sram_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master sram/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = sram_avalon_slave_0_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master sram/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = sram_avalon_slave_0_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted sram/avalon_slave_0 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_sram_avalon_slave_0 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_sram_avalon_slave_0 <= cpu_0_instruction_master_saved_grant_sram_avalon_slave_0 ? 1 : (sram_avalon_slave_0_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_sram_avalon_slave_0) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_sram_avalon_slave_0;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_sram_avalon_slave_0 & cpu_0_instruction_master_requests_sram_avalon_slave_0;
//sram_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_mux
assign sram_avalon_slave_0_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_sram_avalon_slave_0 = cpu_0_data_master_requests_sram_avalon_slave_0 & ~(((cpu_0_data_master_no_byte_enables_and_last_term | !cpu_0_data_master_byteenable_sram_avalon_slave_0) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//sram_avalon_slave_0_writedata mux, which is an e_mux
assign sram_avalon_slave_0_writedata = cpu_0_data_master_dbs_write_16;
assign cpu_0_instruction_master_requests_sram_avalon_slave_0 = (({cpu_0_instruction_master_address_to_slave[23 : 19] , 19'b0} == 24'ha80000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted sram/avalon_slave_0 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_sram_avalon_slave_0 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_sram_avalon_slave_0 <= cpu_0_data_master_saved_grant_sram_avalon_slave_0 ? 1 : (sram_avalon_slave_0_arbitration_holdoff_internal | ~cpu_0_data_master_requests_sram_avalon_slave_0) ? 0 : last_cycle_cpu_0_data_master_granted_slave_sram_avalon_slave_0;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_sram_avalon_slave_0 & cpu_0_data_master_requests_sram_avalon_slave_0;
assign cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 = cpu_0_instruction_master_requests_sram_avalon_slave_0 & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0))) | cpu_0_data_master_arbiterlock);
//local readdatavalid cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0 = cpu_0_instruction_master_granted_sram_avalon_slave_0 & cpu_0_instruction_master_read & ~sram_avalon_slave_0_waits_for_read;
//allow new arb cycle for sram/avalon_slave_0, which is an e_assign
assign sram_avalon_slave_0_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for sram/avalon_slave_0, which is an e_assign
assign sram_avalon_slave_0_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_sram_avalon_slave_0;
//cpu_0/instruction_master grant sram/avalon_slave_0, which is an e_assign
assign cpu_0_instruction_master_granted_sram_avalon_slave_0 = sram_avalon_slave_0_grant_vector[0];
//cpu_0/instruction_master saved-grant sram/avalon_slave_0, which is an e_assign
assign cpu_0_instruction_master_saved_grant_sram_avalon_slave_0 = sram_avalon_slave_0_arb_winner[0] && cpu_0_instruction_master_requests_sram_avalon_slave_0;
//cpu_0/data_master assignment into master qualified-requests vector for sram/avalon_slave_0, which is an e_assign
assign sram_avalon_slave_0_master_qreq_vector[1] = cpu_0_data_master_qualified_request_sram_avalon_slave_0;
//cpu_0/data_master grant sram/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_granted_sram_avalon_slave_0 = sram_avalon_slave_0_grant_vector[1];
//cpu_0/data_master saved-grant sram/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_sram_avalon_slave_0 = sram_avalon_slave_0_arb_winner[1] && cpu_0_data_master_requests_sram_avalon_slave_0;
//sram/avalon_slave_0 chosen-master double-vector, which is an e_assign
assign sram_avalon_slave_0_chosen_master_double_vector = {sram_avalon_slave_0_master_qreq_vector, sram_avalon_slave_0_master_qreq_vector} & ({~sram_avalon_slave_0_master_qreq_vector, ~sram_avalon_slave_0_master_qreq_vector} + sram_avalon_slave_0_arb_addend);
//stable onehot encoding of arb winner
assign sram_avalon_slave_0_arb_winner = (sram_avalon_slave_0_allow_new_arb_cycle & | sram_avalon_slave_0_grant_vector) ? sram_avalon_slave_0_grant_vector : sram_avalon_slave_0_saved_chosen_master_vector;
//saved sram_avalon_slave_0_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_saved_chosen_master_vector <= 0;
else if (sram_avalon_slave_0_allow_new_arb_cycle)
sram_avalon_slave_0_saved_chosen_master_vector <= |sram_avalon_slave_0_grant_vector ? sram_avalon_slave_0_grant_vector : sram_avalon_slave_0_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign sram_avalon_slave_0_grant_vector = {(sram_avalon_slave_0_chosen_master_double_vector[1] | sram_avalon_slave_0_chosen_master_double_vector[3]),
(sram_avalon_slave_0_chosen_master_double_vector[0] | sram_avalon_slave_0_chosen_master_double_vector[2])};
//sram/avalon_slave_0 chosen master rotated left, which is an e_assign
assign sram_avalon_slave_0_chosen_master_rot_left = (sram_avalon_slave_0_arb_winner << 1) ? (sram_avalon_slave_0_arb_winner << 1) : 1;
//sram/avalon_slave_0's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_arb_addend <= 1;
else if (|sram_avalon_slave_0_grant_vector)
sram_avalon_slave_0_arb_addend <= sram_avalon_slave_0_end_xfer? sram_avalon_slave_0_chosen_master_rot_left : sram_avalon_slave_0_grant_vector;
end
//sram_avalon_slave_0_reset_n assignment, which is an e_assign
assign sram_avalon_slave_0_reset_n = reset_n;
assign sram_avalon_slave_0_chipselect_n = ~(cpu_0_data_master_granted_sram_avalon_slave_0 | cpu_0_instruction_master_granted_sram_avalon_slave_0);
//sram_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign sram_avalon_slave_0_firsttransfer = sram_avalon_slave_0_begins_xfer ? sram_avalon_slave_0_unreg_firsttransfer : sram_avalon_slave_0_reg_firsttransfer;
//sram_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
assign sram_avalon_slave_0_unreg_firsttransfer = ~(sram_avalon_slave_0_slavearbiterlockenable & sram_avalon_slave_0_any_continuerequest);
//sram_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_reg_firsttransfer <= 1'b1;
else if (sram_avalon_slave_0_begins_xfer)
sram_avalon_slave_0_reg_firsttransfer <= sram_avalon_slave_0_unreg_firsttransfer;
end
//sram_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sram_avalon_slave_0_beginbursttransfer_internal = sram_avalon_slave_0_begins_xfer;
//sram_avalon_slave_0_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign sram_avalon_slave_0_arbitration_holdoff_internal = sram_avalon_slave_0_begins_xfer & sram_avalon_slave_0_firsttransfer;
//~sram_avalon_slave_0_read_n assignment, which is an e_mux
assign sram_avalon_slave_0_read_n = ~(((cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sram_avalon_slave_0 & cpu_0_instruction_master_read))& ~sram_avalon_slave_0_begins_xfer);
//~sram_avalon_slave_0_write_n assignment, which is an e_mux
assign sram_avalon_slave_0_write_n = ~(((cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_write)) & ~sram_avalon_slave_0_begins_xfer & (sram_avalon_slave_0_wait_counter >= 1));
assign shifted_address_to_sram_avalon_slave_0_from_cpu_0_data_master = {cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1],
{1 {1'b0}}};
//sram_avalon_slave_0_address mux, which is an e_mux
assign sram_avalon_slave_0_address = (cpu_0_data_master_granted_sram_avalon_slave_0)? (shifted_address_to_sram_avalon_slave_0_from_cpu_0_data_master >> 1) :
(shifted_address_to_sram_avalon_slave_0_from_cpu_0_instruction_master >> 1);
assign shifted_address_to_sram_avalon_slave_0_from_cpu_0_instruction_master = {cpu_0_instruction_master_address_to_slave >> 2,
cpu_0_instruction_master_dbs_address[1],
{1 {1'b0}}};
//d1_sram_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sram_avalon_slave_0_end_xfer <= 1;
else
d1_sram_avalon_slave_0_end_xfer <= sram_avalon_slave_0_end_xfer;
end
//sram_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign sram_avalon_slave_0_waits_for_read = sram_avalon_slave_0_in_a_read_cycle & sram_avalon_slave_0_begins_xfer;
//sram_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign sram_avalon_slave_0_in_a_read_cycle = (cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sram_avalon_slave_0 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sram_avalon_slave_0_in_a_read_cycle;
//sram_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign sram_avalon_slave_0_waits_for_write = sram_avalon_slave_0_in_a_write_cycle & wait_for_sram_avalon_slave_0_counter;
//sram_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign sram_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_sram_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sram_avalon_slave_0_in_a_write_cycle;
assign sram_avalon_slave_0_wait_counter_eq_0 = sram_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sram_avalon_slave_0_wait_counter <= 0;
else
sram_avalon_slave_0_wait_counter <= sram_avalon_slave_0_counter_load_value;
end
assign sram_avalon_slave_0_counter_load_value = ((sram_avalon_slave_0_in_a_write_cycle & sram_avalon_slave_0_begins_xfer))? 1 :
(~sram_avalon_slave_0_wait_counter_eq_0)? sram_avalon_slave_0_wait_counter - 1 :
0;
assign wait_for_sram_avalon_slave_0_counter = sram_avalon_slave_0_begins_xfer | ~sram_avalon_slave_0_wait_counter_eq_0;
//~sram_avalon_slave_0_byteenable_n byte enable port mux, which is an e_mux
assign sram_avalon_slave_0_byteenable_n = ~((cpu_0_data_master_granted_sram_avalon_slave_0)? cpu_0_data_master_byteenable_sram_avalon_slave_0 :
-1);
assign {cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_1,
cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_0} = cpu_0_data_master_byteenable;
assign cpu_0_data_master_byteenable_sram_avalon_slave_0 = ((cpu_0_data_master_dbs_address[1] == 0))? cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_0 :
cpu_0_data_master_byteenable_sram_avalon_slave_0_segment_1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sram/avalon_slave_0 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_sram_avalon_slave_0 + cpu_0_instruction_master_granted_sram_avalon_slave_0 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_sram_avalon_slave_0 + cpu_0_instruction_master_saved_grant_sram_avalon_slave_0 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sysid_0_control_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
reset_n,
sysid_0_control_slave_readdata,
// outputs:
cpu_0_data_master_granted_sysid_0_control_slave,
cpu_0_data_master_qualified_request_sysid_0_control_slave,
cpu_0_data_master_read_data_valid_sysid_0_control_slave,
cpu_0_data_master_requests_sysid_0_control_slave,
d1_sysid_0_control_slave_end_xfer,
sysid_0_control_slave_address,
sysid_0_control_slave_readdata_from_sa,
sysid_0_control_slave_reset_n
)
;
output cpu_0_data_master_granted_sysid_0_control_slave;
output cpu_0_data_master_qualified_request_sysid_0_control_slave;
output cpu_0_data_master_read_data_valid_sysid_0_control_slave;
output cpu_0_data_master_requests_sysid_0_control_slave;
output d1_sysid_0_control_slave_end_xfer;
output sysid_0_control_slave_address;
output [ 31: 0] sysid_0_control_slave_readdata_from_sa;
output sysid_0_control_slave_reset_n;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input reset_n;
input [ 31: 0] sysid_0_control_slave_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sysid_0_control_slave;
wire cpu_0_data_master_qualified_request_sysid_0_control_slave;
wire cpu_0_data_master_read_data_valid_sysid_0_control_slave;
wire cpu_0_data_master_requests_sysid_0_control_slave;
wire cpu_0_data_master_saved_grant_sysid_0_control_slave;
reg d1_reasons_to_wait;
reg d1_sysid_0_control_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sysid_0_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_sysid_0_control_slave_from_cpu_0_data_master;
wire sysid_0_control_slave_address;
wire sysid_0_control_slave_allgrants;
wire sysid_0_control_slave_allow_new_arb_cycle;
wire sysid_0_control_slave_any_bursting_master_saved_grant;
wire sysid_0_control_slave_any_continuerequest;
wire sysid_0_control_slave_arb_counter_enable;
reg [ 2: 0] sysid_0_control_slave_arb_share_counter;
wire [ 2: 0] sysid_0_control_slave_arb_share_counter_next_value;
wire [ 2: 0] sysid_0_control_slave_arb_share_set_values;
wire sysid_0_control_slave_beginbursttransfer_internal;
wire sysid_0_control_slave_begins_xfer;
wire sysid_0_control_slave_end_xfer;
wire sysid_0_control_slave_firsttransfer;
wire sysid_0_control_slave_grant_vector;
wire sysid_0_control_slave_in_a_read_cycle;
wire sysid_0_control_slave_in_a_write_cycle;
wire sysid_0_control_slave_master_qreq_vector;
wire sysid_0_control_slave_non_bursting_master_requests;
wire [ 31: 0] sysid_0_control_slave_readdata_from_sa;
reg sysid_0_control_slave_reg_firsttransfer;
wire sysid_0_control_slave_reset_n;
reg sysid_0_control_slave_slavearbiterlockenable;
wire sysid_0_control_slave_slavearbiterlockenable2;
wire sysid_0_control_slave_unreg_firsttransfer;
wire sysid_0_control_slave_waits_for_read;
wire sysid_0_control_slave_waits_for_write;
wire wait_for_sysid_0_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sysid_0_control_slave_end_xfer;
end
assign sysid_0_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sysid_0_control_slave));
//assign sysid_0_control_slave_readdata_from_sa = sysid_0_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sysid_0_control_slave_readdata_from_sa = sysid_0_control_slave_readdata;
assign cpu_0_data_master_requests_sysid_0_control_slave = (({cpu_0_data_master_address_to_slave[23 : 3] , 3'b0} == 24'hb04078) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//sysid_0_control_slave_arb_share_counter set values, which is an e_mux
assign sysid_0_control_slave_arb_share_set_values = 1;
//sysid_0_control_slave_non_bursting_master_requests mux, which is an e_mux
assign sysid_0_control_slave_non_bursting_master_requests = cpu_0_data_master_requests_sysid_0_control_slave;
//sysid_0_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign sysid_0_control_slave_any_bursting_master_saved_grant = 0;
//sysid_0_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign sysid_0_control_slave_arb_share_counter_next_value = sysid_0_control_slave_firsttransfer ? (sysid_0_control_slave_arb_share_set_values - 1) : |sysid_0_control_slave_arb_share_counter ? (sysid_0_control_slave_arb_share_counter - 1) : 0;
//sysid_0_control_slave_allgrants all slave grants, which is an e_mux
assign sysid_0_control_slave_allgrants = |sysid_0_control_slave_grant_vector;
//sysid_0_control_slave_end_xfer assignment, which is an e_assign
assign sysid_0_control_slave_end_xfer = ~(sysid_0_control_slave_waits_for_read | sysid_0_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_sysid_0_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sysid_0_control_slave = sysid_0_control_slave_end_xfer & (~sysid_0_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sysid_0_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign sysid_0_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_0_control_slave & sysid_0_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_0_control_slave & ~sysid_0_control_slave_non_bursting_master_requests);
//sysid_0_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_0_control_slave_arb_share_counter <= 0;
else if (sysid_0_control_slave_arb_counter_enable)
sysid_0_control_slave_arb_share_counter <= sysid_0_control_slave_arb_share_counter_next_value;
end
//sysid_0_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_0_control_slave_slavearbiterlockenable <= 0;
else if ((|sysid_0_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_0_control_slave) | (end_xfer_arb_share_counter_term_sysid_0_control_slave & ~sysid_0_control_slave_non_bursting_master_requests))
sysid_0_control_slave_slavearbiterlockenable <= |sysid_0_control_slave_arb_share_counter_next_value;
end
//cpu_0/data_master sysid_0/control_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sysid_0_control_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sysid_0_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sysid_0_control_slave_slavearbiterlockenable2 = |sysid_0_control_slave_arb_share_counter_next_value;
//cpu_0/data_master sysid_0/control_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sysid_0_control_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//sysid_0_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign sysid_0_control_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_sysid_0_control_slave = cpu_0_data_master_requests_sysid_0_control_slave;
//master is always granted when requested
assign cpu_0_data_master_granted_sysid_0_control_slave = cpu_0_data_master_qualified_request_sysid_0_control_slave;
//cpu_0/data_master saved-grant sysid_0/control_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_sysid_0_control_slave = cpu_0_data_master_requests_sysid_0_control_slave;
//allow new arb cycle for sysid_0/control_slave, which is an e_assign
assign sysid_0_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign sysid_0_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign sysid_0_control_slave_master_qreq_vector = 1;
//sysid_0_control_slave_reset_n assignment, which is an e_assign
assign sysid_0_control_slave_reset_n = reset_n;
//sysid_0_control_slave_firsttransfer first transaction, which is an e_assign
assign sysid_0_control_slave_firsttransfer = sysid_0_control_slave_begins_xfer ? sysid_0_control_slave_unreg_firsttransfer : sysid_0_control_slave_reg_firsttransfer;
//sysid_0_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign sysid_0_control_slave_unreg_firsttransfer = ~(sysid_0_control_slave_slavearbiterlockenable & sysid_0_control_slave_any_continuerequest);
//sysid_0_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_0_control_slave_reg_firsttransfer <= 1'b1;
else if (sysid_0_control_slave_begins_xfer)
sysid_0_control_slave_reg_firsttransfer <= sysid_0_control_slave_unreg_firsttransfer;
end
//sysid_0_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sysid_0_control_slave_beginbursttransfer_internal = sysid_0_control_slave_begins_xfer;
assign shifted_address_to_sysid_0_control_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//sysid_0_control_slave_address mux, which is an e_mux
assign sysid_0_control_slave_address = shifted_address_to_sysid_0_control_slave_from_cpu_0_data_master >> 2;
//d1_sysid_0_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sysid_0_control_slave_end_xfer <= 1;
else
d1_sysid_0_control_slave_end_xfer <= sysid_0_control_slave_end_xfer;
end
//sysid_0_control_slave_waits_for_read in a cycle, which is an e_mux
assign sysid_0_control_slave_waits_for_read = sysid_0_control_slave_in_a_read_cycle & sysid_0_control_slave_begins_xfer;
//sysid_0_control_slave_in_a_read_cycle assignment, which is an e_assign
assign sysid_0_control_slave_in_a_read_cycle = cpu_0_data_master_granted_sysid_0_control_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sysid_0_control_slave_in_a_read_cycle;
//sysid_0_control_slave_waits_for_write in a cycle, which is an e_mux
assign sysid_0_control_slave_waits_for_write = sysid_0_control_slave_in_a_write_cycle & 0;
//sysid_0_control_slave_in_a_write_cycle assignment, which is an e_assign
assign sysid_0_control_slave_in_a_write_cycle = cpu_0_data_master_granted_sysid_0_control_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sysid_0_control_slave_in_a_write_cycle;
assign wait_for_sysid_0_control_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sysid_0/control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
timer_s1_irq,
timer_s1_readdata,
// outputs:
cpu_0_data_master_granted_timer_s1,
cpu_0_data_master_qualified_request_timer_s1,
cpu_0_data_master_read_data_valid_timer_s1,
cpu_0_data_master_requests_timer_s1,
d1_timer_s1_end_xfer,
timer_s1_address,
timer_s1_chipselect,
timer_s1_irq_from_sa,
timer_s1_readdata_from_sa,
timer_s1_reset_n,
timer_s1_write_n,
timer_s1_writedata
)
;
output cpu_0_data_master_granted_timer_s1;
output cpu_0_data_master_qualified_request_timer_s1;
output cpu_0_data_master_read_data_valid_timer_s1;
output cpu_0_data_master_requests_timer_s1;
output d1_timer_s1_end_xfer;
output [ 2: 0] timer_s1_address;
output timer_s1_chipselect;
output timer_s1_irq_from_sa;
output [ 15: 0] timer_s1_readdata_from_sa;
output timer_s1_reset_n;
output timer_s1_write_n;
output [ 15: 0] timer_s1_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
input timer_s1_irq;
input [ 15: 0] timer_s1_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_timer_s1;
wire cpu_0_data_master_qualified_request_timer_s1;
wire cpu_0_data_master_read_data_valid_timer_s1;
wire cpu_0_data_master_requests_timer_s1;
wire cpu_0_data_master_saved_grant_timer_s1;
reg d1_reasons_to_wait;
reg d1_timer_s1_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_timer_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_timer_s1_from_cpu_0_data_master;
wire [ 2: 0] timer_s1_address;
wire timer_s1_allgrants;
wire timer_s1_allow_new_arb_cycle;
wire timer_s1_any_bursting_master_saved_grant;
wire timer_s1_any_continuerequest;
wire timer_s1_arb_counter_enable;
reg [ 2: 0] timer_s1_arb_share_counter;
wire [ 2: 0] timer_s1_arb_share_counter_next_value;
wire [ 2: 0] timer_s1_arb_share_set_values;
wire timer_s1_beginbursttransfer_internal;
wire timer_s1_begins_xfer;
wire timer_s1_chipselect;
wire timer_s1_end_xfer;
wire timer_s1_firsttransfer;
wire timer_s1_grant_vector;
wire timer_s1_in_a_read_cycle;
wire timer_s1_in_a_write_cycle;
wire timer_s1_irq_from_sa;
wire timer_s1_master_qreq_vector;
wire timer_s1_non_bursting_master_requests;
wire [ 15: 0] timer_s1_readdata_from_sa;
reg timer_s1_reg_firsttransfer;
wire timer_s1_reset_n;
reg timer_s1_slavearbiterlockenable;
wire timer_s1_slavearbiterlockenable2;
wire timer_s1_unreg_firsttransfer;
wire timer_s1_waits_for_read;
wire timer_s1_waits_for_write;
wire timer_s1_write_n;
wire [ 15: 0] timer_s1_writedata;
wire wait_for_timer_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~timer_s1_end_xfer;
end
assign timer_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_timer_s1));
//assign timer_s1_readdata_from_sa = timer_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign timer_s1_readdata_from_sa = timer_s1_readdata;
assign cpu_0_data_master_requests_timer_s1 = ({cpu_0_data_master_address_to_slave[23 : 5] , 5'b0} == 24'hb04020) & (cpu_0_data_master_read | cpu_0_data_master_write);
//timer_s1_arb_share_counter set values, which is an e_mux
assign timer_s1_arb_share_set_values = 1;
//timer_s1_non_bursting_master_requests mux, which is an e_mux
assign timer_s1_non_bursting_master_requests = cpu_0_data_master_requests_timer_s1;
//timer_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign timer_s1_any_bursting_master_saved_grant = 0;
//timer_s1_arb_share_counter_next_value assignment, which is an e_assign
assign timer_s1_arb_share_counter_next_value = timer_s1_firsttransfer ? (timer_s1_arb_share_set_values - 1) : |timer_s1_arb_share_counter ? (timer_s1_arb_share_counter - 1) : 0;
//timer_s1_allgrants all slave grants, which is an e_mux
assign timer_s1_allgrants = |timer_s1_grant_vector;
//timer_s1_end_xfer assignment, which is an e_assign
assign timer_s1_end_xfer = ~(timer_s1_waits_for_read | timer_s1_waits_for_write);
//end_xfer_arb_share_counter_term_timer_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_timer_s1 = timer_s1_end_xfer & (~timer_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//timer_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign timer_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_timer_s1 & timer_s1_allgrants) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests);
//timer_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_arb_share_counter <= 0;
else if (timer_s1_arb_counter_enable)
timer_s1_arb_share_counter <= timer_s1_arb_share_counter_next_value;
end
//timer_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_slavearbiterlockenable <= 0;
else if ((|timer_s1_master_qreq_vector & end_xfer_arb_share_counter_term_timer_s1) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests))
timer_s1_slavearbiterlockenable <= |timer_s1_arb_share_counter_next_value;
end
//cpu_0/data_master timer/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = timer_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//timer_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign timer_s1_slavearbiterlockenable2 = |timer_s1_arb_share_counter_next_value;
//cpu_0/data_master timer/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = timer_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//timer_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign timer_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_timer_s1 = cpu_0_data_master_requests_timer_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//timer_s1_writedata mux, which is an e_mux
assign timer_s1_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_timer_s1 = cpu_0_data_master_qualified_request_timer_s1;
//cpu_0/data_master saved-grant timer/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_timer_s1 = cpu_0_data_master_requests_timer_s1;
//allow new arb cycle for timer/s1, which is an e_assign
assign timer_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign timer_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign timer_s1_master_qreq_vector = 1;
//timer_s1_reset_n assignment, which is an e_assign
assign timer_s1_reset_n = reset_n;
assign timer_s1_chipselect = cpu_0_data_master_granted_timer_s1;
//timer_s1_firsttransfer first transaction, which is an e_assign
assign timer_s1_firsttransfer = timer_s1_begins_xfer ? timer_s1_unreg_firsttransfer : timer_s1_reg_firsttransfer;
//timer_s1_unreg_firsttransfer first transaction, which is an e_assign
assign timer_s1_unreg_firsttransfer = ~(timer_s1_slavearbiterlockenable & timer_s1_any_continuerequest);
//timer_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timer_s1_reg_firsttransfer <= 1'b1;
else if (timer_s1_begins_xfer)
timer_s1_reg_firsttransfer <= timer_s1_unreg_firsttransfer;
end
//timer_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign timer_s1_beginbursttransfer_internal = timer_s1_begins_xfer;
//~timer_s1_write_n assignment, which is an e_mux
assign timer_s1_write_n = ~(cpu_0_data_master_granted_timer_s1 & cpu_0_data_master_write);
assign shifted_address_to_timer_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//timer_s1_address mux, which is an e_mux
assign timer_s1_address = shifted_address_to_timer_s1_from_cpu_0_data_master >> 2;
//d1_timer_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_timer_s1_end_xfer <= 1;
else
d1_timer_s1_end_xfer <= timer_s1_end_xfer;
end
//timer_s1_waits_for_read in a cycle, which is an e_mux
assign timer_s1_waits_for_read = timer_s1_in_a_read_cycle & timer_s1_begins_xfer;
//timer_s1_in_a_read_cycle assignment, which is an e_assign
assign timer_s1_in_a_read_cycle = cpu_0_data_master_granted_timer_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = timer_s1_in_a_read_cycle;
//timer_s1_waits_for_write in a cycle, which is an e_mux
assign timer_s1_waits_for_write = timer_s1_in_a_write_cycle & 0;
//timer_s1_in_a_write_cycle assignment, which is an e_assign
assign timer_s1_in_a_write_cycle = cpu_0_data_master_granted_timer_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = timer_s1_in_a_write_cycle;
assign wait_for_timer_s1_counter = 0;
//assign timer_s1_irq_from_sa = timer_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign timer_s1_irq_from_sa = timer_s1_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//timer/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tri_state_bridge_flash_avalon_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_dbs_address,
cpu_0_instruction_master_latency_counter,
cpu_0_instruction_master_read,
reset_n,
// outputs:
cfi_flash_0_s1_wait_counter_eq_0,
cfi_flash_0_s1_wait_counter_eq_1,
cpu_0_data_master_byteenable_cfi_flash_0_s1,
cpu_0_data_master_granted_cfi_flash_0_s1,
cpu_0_data_master_qualified_request_cfi_flash_0_s1,
cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
cpu_0_data_master_requests_cfi_flash_0_s1,
cpu_0_instruction_master_granted_cfi_flash_0_s1,
cpu_0_instruction_master_qualified_request_cfi_flash_0_s1,
cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1,
cpu_0_instruction_master_requests_cfi_flash_0_s1,
d1_tri_state_bridge_flash_avalon_slave_end_xfer,
incoming_tri_state_bridge_flash_data,
incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0,
registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1,
select_n_to_the_cfi_flash_0,
tri_state_bridge_flash_address,
tri_state_bridge_flash_data,
tri_state_bridge_flash_readn,
write_n_to_the_cfi_flash_0
)
;
output cfi_flash_0_s1_wait_counter_eq_0;
output cfi_flash_0_s1_wait_counter_eq_1;
output cpu_0_data_master_byteenable_cfi_flash_0_s1;
output cpu_0_data_master_granted_cfi_flash_0_s1;
output cpu_0_data_master_qualified_request_cfi_flash_0_s1;
output cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
output cpu_0_data_master_requests_cfi_flash_0_s1;
output cpu_0_instruction_master_granted_cfi_flash_0_s1;
output cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
output cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
output cpu_0_instruction_master_requests_cfi_flash_0_s1;
output d1_tri_state_bridge_flash_avalon_slave_end_xfer;
output [ 7: 0] incoming_tri_state_bridge_flash_data;
output [ 7: 0] incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
output registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
output select_n_to_the_cfi_flash_0;
output [ 21: 0] tri_state_bridge_flash_address;
inout [ 7: 0] tri_state_bridge_flash_data;
output tri_state_bridge_flash_readn;
output write_n_to_the_cfi_flash_0;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input [ 1: 0] cpu_0_data_master_dbs_address;
input [ 7: 0] cpu_0_data_master_dbs_write_8;
input cpu_0_data_master_no_byte_enables_and_last_term;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 23: 0] cpu_0_instruction_master_address_to_slave;
input [ 1: 0] cpu_0_instruction_master_dbs_address;
input [ 1: 0] cpu_0_instruction_master_latency_counter;
input cpu_0_instruction_master_read;
input reset_n;
wire [ 2: 0] cfi_flash_0_s1_counter_load_value;
wire cfi_flash_0_s1_in_a_read_cycle;
wire cfi_flash_0_s1_in_a_write_cycle;
wire cfi_flash_0_s1_pretend_byte_enable;
reg [ 2: 0] cfi_flash_0_s1_wait_counter;
wire cfi_flash_0_s1_wait_counter_eq_0;
wire cfi_flash_0_s1_wait_counter_eq_1;
wire cfi_flash_0_s1_waits_for_read;
wire cfi_flash_0_s1_waits_for_write;
wire cfi_flash_0_s1_with_write_latency;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_0;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_1;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_2;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_3;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_cfi_flash_0_s1;
wire cpu_0_data_master_qualified_request_cfi_flash_0_s1;
wire cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
reg [ 1: 0] cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register;
wire cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in;
wire cpu_0_data_master_requests_cfi_flash_0_s1;
wire cpu_0_data_master_saved_grant_cfi_flash_0_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_cfi_flash_0_s1;
wire cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
wire cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
reg [ 1: 0] cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register;
wire cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in;
wire cpu_0_instruction_master_requests_cfi_flash_0_s1;
wire cpu_0_instruction_master_saved_grant_cfi_flash_0_s1;
reg d1_in_a_write_cycle /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 7: 0] d1_outgoing_tri_state_bridge_flash_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg d1_reasons_to_wait;
reg d1_tri_state_bridge_flash_avalon_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg [ 7: 0] incoming_tri_state_bridge_flash_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
wire incoming_tri_state_bridge_flash_data_bit_0_is_x;
wire incoming_tri_state_bridge_flash_data_bit_1_is_x;
wire incoming_tri_state_bridge_flash_data_bit_2_is_x;
wire incoming_tri_state_bridge_flash_data_bit_3_is_x;
wire incoming_tri_state_bridge_flash_data_bit_4_is_x;
wire incoming_tri_state_bridge_flash_data_bit_5_is_x;
wire incoming_tri_state_bridge_flash_data_bit_6_is_x;
wire incoming_tri_state_bridge_flash_data_bit_7_is_x;
wire [ 7: 0] incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
reg last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1;
wire [ 7: 0] outgoing_tri_state_bridge_flash_data;
wire [ 1: 0] p1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register;
wire [ 1: 0] p1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register;
wire p1_select_n_to_the_cfi_flash_0;
wire [ 21: 0] p1_tri_state_bridge_flash_address;
wire p1_tri_state_bridge_flash_readn;
wire p1_write_n_to_the_cfi_flash_0;
wire registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
reg select_n_to_the_cfi_flash_0 /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire time_to_write;
reg [ 21: 0] tri_state_bridge_flash_address /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire tri_state_bridge_flash_avalon_slave_allgrants;
wire tri_state_bridge_flash_avalon_slave_allow_new_arb_cycle;
wire tri_state_bridge_flash_avalon_slave_any_bursting_master_saved_grant;
wire tri_state_bridge_flash_avalon_slave_any_continuerequest;
reg [ 1: 0] tri_state_bridge_flash_avalon_slave_arb_addend;
wire tri_state_bridge_flash_avalon_slave_arb_counter_enable;
reg [ 2: 0] tri_state_bridge_flash_avalon_slave_arb_share_counter;
wire [ 2: 0] tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value;
wire [ 2: 0] tri_state_bridge_flash_avalon_slave_arb_share_set_values;
wire [ 1: 0] tri_state_bridge_flash_avalon_slave_arb_winner;
wire tri_state_bridge_flash_avalon_slave_arbitration_holdoff_internal;
wire tri_state_bridge_flash_avalon_slave_beginbursttransfer_internal;
wire tri_state_bridge_flash_avalon_slave_begins_xfer;
wire [ 3: 0] tri_state_bridge_flash_avalon_slave_chosen_master_double_vector;
wire [ 1: 0] tri_state_bridge_flash_avalon_slave_chosen_master_rot_left;
wire tri_state_bridge_flash_avalon_slave_end_xfer;
wire tri_state_bridge_flash_avalon_slave_firsttransfer;
wire [ 1: 0] tri_state_bridge_flash_avalon_slave_grant_vector;
wire [ 1: 0] tri_state_bridge_flash_avalon_slave_master_qreq_vector;
wire tri_state_bridge_flash_avalon_slave_non_bursting_master_requests;
wire tri_state_bridge_flash_avalon_slave_read_pending;
reg tri_state_bridge_flash_avalon_slave_reg_firsttransfer;
reg [ 1: 0] tri_state_bridge_flash_avalon_slave_saved_chosen_master_vector;
reg tri_state_bridge_flash_avalon_slave_slavearbiterlockenable;
wire tri_state_bridge_flash_avalon_slave_slavearbiterlockenable2;
wire tri_state_bridge_flash_avalon_slave_unreg_firsttransfer;
wire tri_state_bridge_flash_avalon_slave_write_pending;
wire [ 7: 0] tri_state_bridge_flash_data;
reg tri_state_bridge_flash_readn /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
wire wait_for_cfi_flash_0_s1_counter;
reg write_n_to_the_cfi_flash_0 /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~tri_state_bridge_flash_avalon_slave_end_xfer;
end
assign tri_state_bridge_flash_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_cfi_flash_0_s1 | cpu_0_instruction_master_qualified_request_cfi_flash_0_s1));
assign cpu_0_data_master_requests_cfi_flash_0_s1 = ({cpu_0_data_master_address_to_slave[23 : 22] , 22'b0} == 24'h400000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//~select_n_to_the_cfi_flash_0 of type chipselect to ~p1_select_n_to_the_cfi_flash_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
select_n_to_the_cfi_flash_0 <= ~0;
else
select_n_to_the_cfi_flash_0 <= p1_select_n_to_the_cfi_flash_0;
end
assign tri_state_bridge_flash_avalon_slave_write_pending = 0;
//tri_state_bridge_flash/avalon_slave read pending calc, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_read_pending = 0;
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 = cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0];
//tri_state_bridge_flash_avalon_slave_arb_share_counter set values, which is an e_mux
assign tri_state_bridge_flash_avalon_slave_arb_share_set_values = (cpu_0_data_master_granted_cfi_flash_0_s1)? 4 :
(cpu_0_instruction_master_granted_cfi_flash_0_s1)? 4 :
(cpu_0_data_master_granted_cfi_flash_0_s1)? 4 :
(cpu_0_instruction_master_granted_cfi_flash_0_s1)? 4 :
1;
//tri_state_bridge_flash_avalon_slave_non_bursting_master_requests mux, which is an e_mux
assign tri_state_bridge_flash_avalon_slave_non_bursting_master_requests = cpu_0_data_master_requests_cfi_flash_0_s1 |
cpu_0_instruction_master_requests_cfi_flash_0_s1 |
cpu_0_data_master_requests_cfi_flash_0_s1 |
cpu_0_instruction_master_requests_cfi_flash_0_s1;
//tri_state_bridge_flash_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign tri_state_bridge_flash_avalon_slave_any_bursting_master_saved_grant = 0;
//tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value = tri_state_bridge_flash_avalon_slave_firsttransfer ? (tri_state_bridge_flash_avalon_slave_arb_share_set_values - 1) : |tri_state_bridge_flash_avalon_slave_arb_share_counter ? (tri_state_bridge_flash_avalon_slave_arb_share_counter - 1) : 0;
//tri_state_bridge_flash_avalon_slave_allgrants all slave grants, which is an e_mux
assign tri_state_bridge_flash_avalon_slave_allgrants = (|tri_state_bridge_flash_avalon_slave_grant_vector) |
(|tri_state_bridge_flash_avalon_slave_grant_vector) |
(|tri_state_bridge_flash_avalon_slave_grant_vector) |
(|tri_state_bridge_flash_avalon_slave_grant_vector);
//tri_state_bridge_flash_avalon_slave_end_xfer assignment, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_end_xfer = ~(cfi_flash_0_s1_waits_for_read | cfi_flash_0_s1_waits_for_write);
//end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave = tri_state_bridge_flash_avalon_slave_end_xfer & (~tri_state_bridge_flash_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//tri_state_bridge_flash_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave & tri_state_bridge_flash_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave & ~tri_state_bridge_flash_avalon_slave_non_bursting_master_requests);
//tri_state_bridge_flash_avalon_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_avalon_slave_arb_share_counter <= 0;
else if (tri_state_bridge_flash_avalon_slave_arb_counter_enable)
tri_state_bridge_flash_avalon_slave_arb_share_counter <= tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value;
end
//tri_state_bridge_flash_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_avalon_slave_slavearbiterlockenable <= 0;
else if ((|tri_state_bridge_flash_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave) | (end_xfer_arb_share_counter_term_tri_state_bridge_flash_avalon_slave & ~tri_state_bridge_flash_avalon_slave_non_bursting_master_requests))
tri_state_bridge_flash_avalon_slave_slavearbiterlockenable <= |tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value;
end
//cpu_0/data_master tri_state_bridge_flash/avalon_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = tri_state_bridge_flash_avalon_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//tri_state_bridge_flash_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_slavearbiterlockenable2 = |tri_state_bridge_flash_avalon_slave_arb_share_counter_next_value;
//cpu_0/data_master tri_state_bridge_flash/avalon_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = tri_state_bridge_flash_avalon_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master tri_state_bridge_flash/avalon_slave arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = tri_state_bridge_flash_avalon_slave_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master tri_state_bridge_flash/avalon_slave arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = tri_state_bridge_flash_avalon_slave_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted cfi_flash_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 <= cpu_0_instruction_master_saved_grant_cfi_flash_0_s1 ? 1 : (tri_state_bridge_flash_avalon_slave_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_cfi_flash_0_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & cpu_0_instruction_master_requests_cfi_flash_0_s1;
//tri_state_bridge_flash_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_mux
assign tri_state_bridge_flash_avalon_slave_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_cfi_flash_0_s1 = cpu_0_data_master_requests_cfi_flash_0_s1 & ~((cpu_0_data_master_read & (tri_state_bridge_flash_avalon_slave_write_pending | (tri_state_bridge_flash_avalon_slave_read_pending) | (|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register))) | ((tri_state_bridge_flash_avalon_slave_read_pending | cpu_0_data_master_no_byte_enables_and_last_term | !cpu_0_data_master_byteenable_cfi_flash_0_s1) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in = cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_read & ~cfi_flash_0_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register = {cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register, cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register_in};
//cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_cfi_flash_0_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_cfi_flash_0_s1 = cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1];
//tri_state_bridge_flash_data register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
incoming_tri_state_bridge_flash_data <= 0;
else
incoming_tri_state_bridge_flash_data <= tri_state_bridge_flash_data;
end
//cfi_flash_0_s1_with_write_latency assignment, which is an e_assign
assign cfi_flash_0_s1_with_write_latency = in_a_write_cycle & (cpu_0_data_master_qualified_request_cfi_flash_0_s1 | cpu_0_instruction_master_qualified_request_cfi_flash_0_s1);
//time to write the data, which is an e_mux
assign time_to_write = (cfi_flash_0_s1_with_write_latency)? 1 :
0;
//d1_outgoing_tri_state_bridge_flash_data register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_outgoing_tri_state_bridge_flash_data <= 0;
else
d1_outgoing_tri_state_bridge_flash_data <= outgoing_tri_state_bridge_flash_data;
end
//write cycle delayed by 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_in_a_write_cycle <= 0;
else
d1_in_a_write_cycle <= time_to_write;
end
//d1_outgoing_tri_state_bridge_flash_data tristate driver, which is an e_assign
assign tri_state_bridge_flash_data = (d1_in_a_write_cycle)? d1_outgoing_tri_state_bridge_flash_data:{8{1'bz}};
//outgoing_tri_state_bridge_flash_data mux, which is an e_mux
assign outgoing_tri_state_bridge_flash_data = cpu_0_data_master_dbs_write_8;
assign cpu_0_instruction_master_requests_cfi_flash_0_s1 = (({cpu_0_instruction_master_address_to_slave[23 : 22] , 22'b0} == 24'h400000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted cfi_flash_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 <= cpu_0_data_master_saved_grant_cfi_flash_0_s1 ? 1 : (tri_state_bridge_flash_avalon_slave_arbitration_holdoff_internal | ~cpu_0_data_master_requests_cfi_flash_0_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 & cpu_0_data_master_requests_cfi_flash_0_s1;
assign cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 = cpu_0_instruction_master_requests_cfi_flash_0_s1 & ~((cpu_0_instruction_master_read & (tri_state_bridge_flash_avalon_slave_write_pending | (tri_state_bridge_flash_avalon_slave_read_pending) | (2 < cpu_0_instruction_master_latency_counter))) | cpu_0_data_master_arbiterlock);
//cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in = cpu_0_instruction_master_granted_cfi_flash_0_s1 & cpu_0_instruction_master_read & ~cfi_flash_0_s1_waits_for_read;
//shift register p1 cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register = {cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register, cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in};
//cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register <= 0;
else
cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register;
end
//local readdatavalid cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 = cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1];
//allow new arb cycle for tri_state_bridge_flash/avalon_slave, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for cfi_flash_0/s1, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
//cpu_0/instruction_master grant cfi_flash_0/s1, which is an e_assign
assign cpu_0_instruction_master_granted_cfi_flash_0_s1 = tri_state_bridge_flash_avalon_slave_grant_vector[0];
//cpu_0/instruction_master saved-grant cfi_flash_0/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_cfi_flash_0_s1 = tri_state_bridge_flash_avalon_slave_arb_winner[0] && cpu_0_instruction_master_requests_cfi_flash_0_s1;
//cpu_0/data_master assignment into master qualified-requests vector for cfi_flash_0/s1, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_master_qreq_vector[1] = cpu_0_data_master_qualified_request_cfi_flash_0_s1;
//cpu_0/data_master grant cfi_flash_0/s1, which is an e_assign
assign cpu_0_data_master_granted_cfi_flash_0_s1 = tri_state_bridge_flash_avalon_slave_grant_vector[1];
//cpu_0/data_master saved-grant cfi_flash_0/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_cfi_flash_0_s1 = tri_state_bridge_flash_avalon_slave_arb_winner[1] && cpu_0_data_master_requests_cfi_flash_0_s1;
//tri_state_bridge_flash/avalon_slave chosen-master double-vector, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_chosen_master_double_vector = {tri_state_bridge_flash_avalon_slave_master_qreq_vector, tri_state_bridge_flash_avalon_slave_master_qreq_vector} & ({~tri_state_bridge_flash_avalon_slave_master_qreq_vector, ~tri_state_bridge_flash_avalon_slave_master_qreq_vector} + tri_state_bridge_flash_avalon_slave_arb_addend);
//stable onehot encoding of arb winner
assign tri_state_bridge_flash_avalon_slave_arb_winner = (tri_state_bridge_flash_avalon_slave_allow_new_arb_cycle & | tri_state_bridge_flash_avalon_slave_grant_vector) ? tri_state_bridge_flash_avalon_slave_grant_vector : tri_state_bridge_flash_avalon_slave_saved_chosen_master_vector;
//saved tri_state_bridge_flash_avalon_slave_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_avalon_slave_saved_chosen_master_vector <= 0;
else if (tri_state_bridge_flash_avalon_slave_allow_new_arb_cycle)
tri_state_bridge_flash_avalon_slave_saved_chosen_master_vector <= |tri_state_bridge_flash_avalon_slave_grant_vector ? tri_state_bridge_flash_avalon_slave_grant_vector : tri_state_bridge_flash_avalon_slave_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign tri_state_bridge_flash_avalon_slave_grant_vector = {(tri_state_bridge_flash_avalon_slave_chosen_master_double_vector[1] | tri_state_bridge_flash_avalon_slave_chosen_master_double_vector[3]),
(tri_state_bridge_flash_avalon_slave_chosen_master_double_vector[0] | tri_state_bridge_flash_avalon_slave_chosen_master_double_vector[2])};
//tri_state_bridge_flash/avalon_slave chosen master rotated left, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_chosen_master_rot_left = (tri_state_bridge_flash_avalon_slave_arb_winner << 1) ? (tri_state_bridge_flash_avalon_slave_arb_winner << 1) : 1;
//tri_state_bridge_flash/avalon_slave's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_avalon_slave_arb_addend <= 1;
else if (|tri_state_bridge_flash_avalon_slave_grant_vector)
tri_state_bridge_flash_avalon_slave_arb_addend <= tri_state_bridge_flash_avalon_slave_end_xfer? tri_state_bridge_flash_avalon_slave_chosen_master_rot_left : tri_state_bridge_flash_avalon_slave_grant_vector;
end
assign p1_select_n_to_the_cfi_flash_0 = ~(cpu_0_data_master_granted_cfi_flash_0_s1 | cpu_0_instruction_master_granted_cfi_flash_0_s1);
//tri_state_bridge_flash_avalon_slave_firsttransfer first transaction, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_firsttransfer = tri_state_bridge_flash_avalon_slave_begins_xfer ? tri_state_bridge_flash_avalon_slave_unreg_firsttransfer : tri_state_bridge_flash_avalon_slave_reg_firsttransfer;
//tri_state_bridge_flash_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_unreg_firsttransfer = ~(tri_state_bridge_flash_avalon_slave_slavearbiterlockenable & tri_state_bridge_flash_avalon_slave_any_continuerequest);
//tri_state_bridge_flash_avalon_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_avalon_slave_reg_firsttransfer <= 1'b1;
else if (tri_state_bridge_flash_avalon_slave_begins_xfer)
tri_state_bridge_flash_avalon_slave_reg_firsttransfer <= tri_state_bridge_flash_avalon_slave_unreg_firsttransfer;
end
//tri_state_bridge_flash_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_beginbursttransfer_internal = tri_state_bridge_flash_avalon_slave_begins_xfer;
//tri_state_bridge_flash_avalon_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign tri_state_bridge_flash_avalon_slave_arbitration_holdoff_internal = tri_state_bridge_flash_avalon_slave_begins_xfer & tri_state_bridge_flash_avalon_slave_firsttransfer;
//~tri_state_bridge_flash_readn of type read to ~p1_tri_state_bridge_flash_readn, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_readn <= ~0;
else
tri_state_bridge_flash_readn <= p1_tri_state_bridge_flash_readn;
end
//~p1_tri_state_bridge_flash_readn assignment, which is an e_mux
assign p1_tri_state_bridge_flash_readn = ~(((cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cfi_flash_0_s1 & cpu_0_instruction_master_read))& ~tri_state_bridge_flash_avalon_slave_begins_xfer & (cfi_flash_0_s1_wait_counter < 5));
//~write_n_to_the_cfi_flash_0 of type write to ~p1_write_n_to_the_cfi_flash_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
write_n_to_the_cfi_flash_0 <= ~0;
else
write_n_to_the_cfi_flash_0 <= p1_write_n_to_the_cfi_flash_0;
end
//~p1_write_n_to_the_cfi_flash_0 assignment, which is an e_mux
assign p1_write_n_to_the_cfi_flash_0 = ~(((cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_write)) & ~tri_state_bridge_flash_avalon_slave_begins_xfer & (cfi_flash_0_s1_wait_counter >= 2) & (cfi_flash_0_s1_wait_counter < 7) & cfi_flash_0_s1_pretend_byte_enable);
//tri_state_bridge_flash_address of type address to p1_tri_state_bridge_flash_address, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tri_state_bridge_flash_address <= 0;
else
tri_state_bridge_flash_address <= p1_tri_state_bridge_flash_address;
end
//p1_tri_state_bridge_flash_address mux, which is an e_mux
assign p1_tri_state_bridge_flash_address = (cpu_0_data_master_granted_cfi_flash_0_s1)? ({cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1 : 0]}) :
({cpu_0_instruction_master_address_to_slave >> 2,
cpu_0_instruction_master_dbs_address[1 : 0]});
//d1_tri_state_bridge_flash_avalon_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_tri_state_bridge_flash_avalon_slave_end_xfer <= 1;
else
d1_tri_state_bridge_flash_avalon_slave_end_xfer <= tri_state_bridge_flash_avalon_slave_end_xfer;
end
//cfi_flash_0_s1_wait_counter_eq_1 assignment, which is an e_assign
assign cfi_flash_0_s1_wait_counter_eq_1 = cfi_flash_0_s1_wait_counter == 1;
//cfi_flash_0_s1_waits_for_read in a cycle, which is an e_mux
assign cfi_flash_0_s1_waits_for_read = cfi_flash_0_s1_in_a_read_cycle & wait_for_cfi_flash_0_s1_counter;
//cfi_flash_0_s1_in_a_read_cycle assignment, which is an e_assign
assign cfi_flash_0_s1_in_a_read_cycle = (cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cfi_flash_0_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cfi_flash_0_s1_in_a_read_cycle;
//cfi_flash_0_s1_waits_for_write in a cycle, which is an e_mux
assign cfi_flash_0_s1_waits_for_write = cfi_flash_0_s1_in_a_write_cycle & wait_for_cfi_flash_0_s1_counter;
//cfi_flash_0_s1_in_a_write_cycle assignment, which is an e_assign
assign cfi_flash_0_s1_in_a_write_cycle = cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cfi_flash_0_s1_in_a_write_cycle;
assign cfi_flash_0_s1_wait_counter_eq_0 = cfi_flash_0_s1_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cfi_flash_0_s1_wait_counter <= 0;
else
cfi_flash_0_s1_wait_counter <= cfi_flash_0_s1_counter_load_value;
end
assign cfi_flash_0_s1_counter_load_value = ((cfi_flash_0_s1_in_a_write_cycle & tri_state_bridge_flash_avalon_slave_begins_xfer))? 7 :
((cfi_flash_0_s1_in_a_read_cycle & tri_state_bridge_flash_avalon_slave_begins_xfer))? 5 :
(~cfi_flash_0_s1_wait_counter_eq_0)? cfi_flash_0_s1_wait_counter - 1 :
0;
assign wait_for_cfi_flash_0_s1_counter = tri_state_bridge_flash_avalon_slave_begins_xfer | ~cfi_flash_0_s1_wait_counter_eq_0;
//cfi_flash_0_s1_pretend_byte_enable byte enable port mux, which is an e_mux
assign cfi_flash_0_s1_pretend_byte_enable = (cpu_0_data_master_granted_cfi_flash_0_s1)? cpu_0_data_master_byteenable_cfi_flash_0_s1 :
-1;
assign {cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_3,
cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_2,
cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_1,
cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_0} = cpu_0_data_master_byteenable;
assign cpu_0_data_master_byteenable_cfi_flash_0_s1 = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_0 :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_1 :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_2 :
cpu_0_data_master_byteenable_cfi_flash_0_s1_segment_3;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//incoming_tri_state_bridge_flash_data_bit_0_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_0_is_x = ^(incoming_tri_state_bridge_flash_data[0]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[0] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[0] = incoming_tri_state_bridge_flash_data_bit_0_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[0];
//incoming_tri_state_bridge_flash_data_bit_1_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_1_is_x = ^(incoming_tri_state_bridge_flash_data[1]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[1] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[1] = incoming_tri_state_bridge_flash_data_bit_1_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[1];
//incoming_tri_state_bridge_flash_data_bit_2_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_2_is_x = ^(incoming_tri_state_bridge_flash_data[2]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[2] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[2] = incoming_tri_state_bridge_flash_data_bit_2_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[2];
//incoming_tri_state_bridge_flash_data_bit_3_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_3_is_x = ^(incoming_tri_state_bridge_flash_data[3]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[3] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[3] = incoming_tri_state_bridge_flash_data_bit_3_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[3];
//incoming_tri_state_bridge_flash_data_bit_4_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_4_is_x = ^(incoming_tri_state_bridge_flash_data[4]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[4] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[4] = incoming_tri_state_bridge_flash_data_bit_4_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[4];
//incoming_tri_state_bridge_flash_data_bit_5_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_5_is_x = ^(incoming_tri_state_bridge_flash_data[5]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[5] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[5] = incoming_tri_state_bridge_flash_data_bit_5_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[5];
//incoming_tri_state_bridge_flash_data_bit_6_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_6_is_x = ^(incoming_tri_state_bridge_flash_data[6]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[6] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[6] = incoming_tri_state_bridge_flash_data_bit_6_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[6];
//incoming_tri_state_bridge_flash_data_bit_7_is_x x check, which is an e_assign_is_x
assign incoming_tri_state_bridge_flash_data_bit_7_is_x = ^(incoming_tri_state_bridge_flash_data[7]) === 1'bx;
//Crush incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[7] Xs to 0, which is an e_assign
assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0[7] = incoming_tri_state_bridge_flash_data_bit_7_is_x ? 1'b0 : incoming_tri_state_bridge_flash_data[7];
//cfi_flash_0/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_cfi_flash_0_s1 + cpu_0_instruction_master_granted_cfi_flash_0_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_cfi_flash_0_s1 + cpu_0_instruction_master_saved_grant_cfi_flash_0_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0 = incoming_tri_state_bridge_flash_data;
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module tri_state_bridge_flash_bridge_arbitrator
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module uart_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
uart_s1_dataavailable,
uart_s1_irq,
uart_s1_readdata,
uart_s1_readyfordata,
// outputs:
cpu_0_data_master_granted_uart_s1,
cpu_0_data_master_qualified_request_uart_s1,
cpu_0_data_master_read_data_valid_uart_s1,
cpu_0_data_master_requests_uart_s1,
d1_uart_s1_end_xfer,
uart_s1_address,
uart_s1_begintransfer,
uart_s1_chipselect,
uart_s1_dataavailable_from_sa,
uart_s1_irq_from_sa,
uart_s1_read_n,
uart_s1_readdata_from_sa,
uart_s1_readyfordata_from_sa,
uart_s1_reset_n,
uart_s1_write_n,
uart_s1_writedata
)
;
output cpu_0_data_master_granted_uart_s1;
output cpu_0_data_master_qualified_request_uart_s1;
output cpu_0_data_master_read_data_valid_uart_s1;
output cpu_0_data_master_requests_uart_s1;
output d1_uart_s1_end_xfer;
output [ 2: 0] uart_s1_address;
output uart_s1_begintransfer;
output uart_s1_chipselect;
output uart_s1_dataavailable_from_sa;
output uart_s1_irq_from_sa;
output uart_s1_read_n;
output [ 15: 0] uart_s1_readdata_from_sa;
output uart_s1_readyfordata_from_sa;
output uart_s1_reset_n;
output uart_s1_write_n;
output [ 15: 0] uart_s1_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
input uart_s1_dataavailable;
input uart_s1_irq;
input [ 15: 0] uart_s1_readdata;
input uart_s1_readyfordata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_uart_s1;
wire cpu_0_data_master_qualified_request_uart_s1;
wire cpu_0_data_master_read_data_valid_uart_s1;
wire cpu_0_data_master_requests_uart_s1;
wire cpu_0_data_master_saved_grant_uart_s1;
reg d1_reasons_to_wait;
reg d1_uart_s1_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_uart_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_uart_s1_from_cpu_0_data_master;
wire [ 2: 0] uart_s1_address;
wire uart_s1_allgrants;
wire uart_s1_allow_new_arb_cycle;
wire uart_s1_any_bursting_master_saved_grant;
wire uart_s1_any_continuerequest;
wire uart_s1_arb_counter_enable;
reg [ 2: 0] uart_s1_arb_share_counter;
wire [ 2: 0] uart_s1_arb_share_counter_next_value;
wire [ 2: 0] uart_s1_arb_share_set_values;
wire uart_s1_beginbursttransfer_internal;
wire uart_s1_begins_xfer;
wire uart_s1_begintransfer;
wire uart_s1_chipselect;
wire uart_s1_dataavailable_from_sa;
wire uart_s1_end_xfer;
wire uart_s1_firsttransfer;
wire uart_s1_grant_vector;
wire uart_s1_in_a_read_cycle;
wire uart_s1_in_a_write_cycle;
wire uart_s1_irq_from_sa;
wire uart_s1_master_qreq_vector;
wire uart_s1_non_bursting_master_requests;
wire uart_s1_read_n;
wire [ 15: 0] uart_s1_readdata_from_sa;
wire uart_s1_readyfordata_from_sa;
reg uart_s1_reg_firsttransfer;
wire uart_s1_reset_n;
reg uart_s1_slavearbiterlockenable;
wire uart_s1_slavearbiterlockenable2;
wire uart_s1_unreg_firsttransfer;
wire uart_s1_waits_for_read;
wire uart_s1_waits_for_write;
wire uart_s1_write_n;
wire [ 15: 0] uart_s1_writedata;
wire wait_for_uart_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~uart_s1_end_xfer;
end
assign uart_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_uart_s1));
//assign uart_s1_readdata_from_sa = uart_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign uart_s1_readdata_from_sa = uart_s1_readdata;
assign cpu_0_data_master_requests_uart_s1 = ({cpu_0_data_master_address_to_slave[23 : 5] , 5'b0} == 24'hb04000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign uart_s1_dataavailable_from_sa = uart_s1_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign uart_s1_dataavailable_from_sa = uart_s1_dataavailable;
//assign uart_s1_readyfordata_from_sa = uart_s1_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign uart_s1_readyfordata_from_sa = uart_s1_readyfordata;
//uart_s1_arb_share_counter set values, which is an e_mux
assign uart_s1_arb_share_set_values = 1;
//uart_s1_non_bursting_master_requests mux, which is an e_mux
assign uart_s1_non_bursting_master_requests = cpu_0_data_master_requests_uart_s1;
//uart_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign uart_s1_any_bursting_master_saved_grant = 0;
//uart_s1_arb_share_counter_next_value assignment, which is an e_assign
assign uart_s1_arb_share_counter_next_value = uart_s1_firsttransfer ? (uart_s1_arb_share_set_values - 1) : |uart_s1_arb_share_counter ? (uart_s1_arb_share_counter - 1) : 0;
//uart_s1_allgrants all slave grants, which is an e_mux
assign uart_s1_allgrants = |uart_s1_grant_vector;
//uart_s1_end_xfer assignment, which is an e_assign
assign uart_s1_end_xfer = ~(uart_s1_waits_for_read | uart_s1_waits_for_write);
//end_xfer_arb_share_counter_term_uart_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_uart_s1 = uart_s1_end_xfer & (~uart_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//uart_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign uart_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_uart_s1 & uart_s1_allgrants) | (end_xfer_arb_share_counter_term_uart_s1 & ~uart_s1_non_bursting_master_requests);
//uart_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
uart_s1_arb_share_counter <= 0;
else if (uart_s1_arb_counter_enable)
uart_s1_arb_share_counter <= uart_s1_arb_share_counter_next_value;
end
//uart_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
uart_s1_slavearbiterlockenable <= 0;
else if ((|uart_s1_master_qreq_vector & end_xfer_arb_share_counter_term_uart_s1) | (end_xfer_arb_share_counter_term_uart_s1 & ~uart_s1_non_bursting_master_requests))
uart_s1_slavearbiterlockenable <= |uart_s1_arb_share_counter_next_value;
end
//cpu_0/data_master uart/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = uart_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//uart_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign uart_s1_slavearbiterlockenable2 = |uart_s1_arb_share_counter_next_value;
//cpu_0/data_master uart/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = uart_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//uart_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign uart_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_uart_s1 = cpu_0_data_master_requests_uart_s1;
//uart_s1_writedata mux, which is an e_mux
assign uart_s1_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_uart_s1 = cpu_0_data_master_qualified_request_uart_s1;
//cpu_0/data_master saved-grant uart/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_uart_s1 = cpu_0_data_master_requests_uart_s1;
//allow new arb cycle for uart/s1, which is an e_assign
assign uart_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign uart_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign uart_s1_master_qreq_vector = 1;
assign uart_s1_begintransfer = uart_s1_begins_xfer;
//uart_s1_reset_n assignment, which is an e_assign
assign uart_s1_reset_n = reset_n;
assign uart_s1_chipselect = cpu_0_data_master_granted_uart_s1;
//uart_s1_firsttransfer first transaction, which is an e_assign
assign uart_s1_firsttransfer = uart_s1_begins_xfer ? uart_s1_unreg_firsttransfer : uart_s1_reg_firsttransfer;
//uart_s1_unreg_firsttransfer first transaction, which is an e_assign
assign uart_s1_unreg_firsttransfer = ~(uart_s1_slavearbiterlockenable & uart_s1_any_continuerequest);
//uart_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
uart_s1_reg_firsttransfer <= 1'b1;
else if (uart_s1_begins_xfer)
uart_s1_reg_firsttransfer <= uart_s1_unreg_firsttransfer;
end
//uart_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign uart_s1_beginbursttransfer_internal = uart_s1_begins_xfer;
//~uart_s1_read_n assignment, which is an e_mux
assign uart_s1_read_n = ~(cpu_0_data_master_granted_uart_s1 & cpu_0_data_master_read);
//~uart_s1_write_n assignment, which is an e_mux
assign uart_s1_write_n = ~(cpu_0_data_master_granted_uart_s1 & cpu_0_data_master_write);
assign shifted_address_to_uart_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//uart_s1_address mux, which is an e_mux
assign uart_s1_address = shifted_address_to_uart_s1_from_cpu_0_data_master >> 2;
//d1_uart_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_uart_s1_end_xfer <= 1;
else
d1_uart_s1_end_xfer <= uart_s1_end_xfer;
end
//uart_s1_waits_for_read in a cycle, which is an e_mux
assign uart_s1_waits_for_read = uart_s1_in_a_read_cycle & uart_s1_begins_xfer;
//uart_s1_in_a_read_cycle assignment, which is an e_assign
assign uart_s1_in_a_read_cycle = cpu_0_data_master_granted_uart_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = uart_s1_in_a_read_cycle;
//uart_s1_waits_for_write in a cycle, which is an e_mux
assign uart_s1_waits_for_write = uart_s1_in_a_write_cycle & uart_s1_begins_xfer;
//uart_s1_in_a_write_cycle assignment, which is an e_assign
assign uart_s1_in_a_write_cycle = cpu_0_data_master_granted_uart_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = uart_s1_in_a_write_cycle;
assign wait_for_uart_s1_counter = 0;
//assign uart_s1_irq_from_sa = uart_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign uart_s1_irq_from_sa = uart_s1_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//uart/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module vga_0_avalon_slave_0_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
vga_0_avalon_slave_0_readdata,
// outputs:
cpu_0_data_master_granted_vga_0_avalon_slave_0,
cpu_0_data_master_qualified_request_vga_0_avalon_slave_0,
cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0,
cpu_0_data_master_requests_vga_0_avalon_slave_0,
d1_vga_0_avalon_slave_0_end_xfer,
vga_0_avalon_slave_0_address,
vga_0_avalon_slave_0_chipselect,
vga_0_avalon_slave_0_read,
vga_0_avalon_slave_0_readdata_from_sa,
vga_0_avalon_slave_0_reset_n,
vga_0_avalon_slave_0_wait_counter_eq_0,
vga_0_avalon_slave_0_write,
vga_0_avalon_slave_0_writedata
)
;
output cpu_0_data_master_granted_vga_0_avalon_slave_0;
output cpu_0_data_master_qualified_request_vga_0_avalon_slave_0;
output cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0;
output cpu_0_data_master_requests_vga_0_avalon_slave_0;
output d1_vga_0_avalon_slave_0_end_xfer;
output [ 18: 0] vga_0_avalon_slave_0_address;
output vga_0_avalon_slave_0_chipselect;
output vga_0_avalon_slave_0_read;
output [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
output vga_0_avalon_slave_0_reset_n;
output vga_0_avalon_slave_0_wait_counter_eq_0;
output vga_0_avalon_slave_0_write;
output [ 15: 0] vga_0_avalon_slave_0_writedata;
input clk;
input [ 23: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
input [ 15: 0] vga_0_avalon_slave_0_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_vga_0_avalon_slave_0;
wire cpu_0_data_master_qualified_request_vga_0_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0;
wire cpu_0_data_master_requests_vga_0_avalon_slave_0;
wire cpu_0_data_master_saved_grant_vga_0_avalon_slave_0;
reg d1_reasons_to_wait;
reg d1_vga_0_avalon_slave_0_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_vga_0_avalon_slave_0;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 23: 0] shifted_address_to_vga_0_avalon_slave_0_from_cpu_0_data_master;
wire [ 18: 0] vga_0_avalon_slave_0_address;
wire vga_0_avalon_slave_0_allgrants;
wire vga_0_avalon_slave_0_allow_new_arb_cycle;
wire vga_0_avalon_slave_0_any_bursting_master_saved_grant;
wire vga_0_avalon_slave_0_any_continuerequest;
wire vga_0_avalon_slave_0_arb_counter_enable;
reg [ 2: 0] vga_0_avalon_slave_0_arb_share_counter;
wire [ 2: 0] vga_0_avalon_slave_0_arb_share_counter_next_value;
wire [ 2: 0] vga_0_avalon_slave_0_arb_share_set_values;
wire vga_0_avalon_slave_0_beginbursttransfer_internal;
wire vga_0_avalon_slave_0_begins_xfer;
wire vga_0_avalon_slave_0_chipselect;
wire vga_0_avalon_slave_0_counter_load_value;
wire vga_0_avalon_slave_0_end_xfer;
wire vga_0_avalon_slave_0_firsttransfer;
wire vga_0_avalon_slave_0_grant_vector;
wire vga_0_avalon_slave_0_in_a_read_cycle;
wire vga_0_avalon_slave_0_in_a_write_cycle;
wire vga_0_avalon_slave_0_master_qreq_vector;
wire vga_0_avalon_slave_0_non_bursting_master_requests;
wire vga_0_avalon_slave_0_read;
wire [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
reg vga_0_avalon_slave_0_reg_firsttransfer;
wire vga_0_avalon_slave_0_reset_n;
reg vga_0_avalon_slave_0_slavearbiterlockenable;
wire vga_0_avalon_slave_0_slavearbiterlockenable2;
wire vga_0_avalon_slave_0_unreg_firsttransfer;
reg vga_0_avalon_slave_0_wait_counter;
wire vga_0_avalon_slave_0_wait_counter_eq_0;
wire vga_0_avalon_slave_0_waits_for_read;
wire vga_0_avalon_slave_0_waits_for_write;
wire vga_0_avalon_slave_0_write;
wire [ 15: 0] vga_0_avalon_slave_0_writedata;
wire wait_for_vga_0_avalon_slave_0_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~vga_0_avalon_slave_0_end_xfer;
end
assign vga_0_avalon_slave_0_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_vga_0_avalon_slave_0));
//assign vga_0_avalon_slave_0_readdata_from_sa = vga_0_avalon_slave_0_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign vga_0_avalon_slave_0_readdata_from_sa = vga_0_avalon_slave_0_readdata;
assign cpu_0_data_master_requests_vga_0_avalon_slave_0 = ({cpu_0_data_master_address_to_slave[23 : 21] , 21'b0} == 24'h800000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//vga_0_avalon_slave_0_arb_share_counter set values, which is an e_mux
assign vga_0_avalon_slave_0_arb_share_set_values = 1;
//vga_0_avalon_slave_0_non_bursting_master_requests mux, which is an e_mux
assign vga_0_avalon_slave_0_non_bursting_master_requests = cpu_0_data_master_requests_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_any_bursting_master_saved_grant mux, which is an e_mux
assign vga_0_avalon_slave_0_any_bursting_master_saved_grant = 0;
//vga_0_avalon_slave_0_arb_share_counter_next_value assignment, which is an e_assign
assign vga_0_avalon_slave_0_arb_share_counter_next_value = vga_0_avalon_slave_0_firsttransfer ? (vga_0_avalon_slave_0_arb_share_set_values - 1) : |vga_0_avalon_slave_0_arb_share_counter ? (vga_0_avalon_slave_0_arb_share_counter - 1) : 0;
//vga_0_avalon_slave_0_allgrants all slave grants, which is an e_mux
assign vga_0_avalon_slave_0_allgrants = |vga_0_avalon_slave_0_grant_vector;
//vga_0_avalon_slave_0_end_xfer assignment, which is an e_assign
assign vga_0_avalon_slave_0_end_xfer = ~(vga_0_avalon_slave_0_waits_for_read | vga_0_avalon_slave_0_waits_for_write);
//end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 = vga_0_avalon_slave_0_end_xfer & (~vga_0_avalon_slave_0_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//vga_0_avalon_slave_0_arb_share_counter arbitration counter enable, which is an e_assign
assign vga_0_avalon_slave_0_arb_counter_enable = (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & vga_0_avalon_slave_0_allgrants) | (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & ~vga_0_avalon_slave_0_non_bursting_master_requests);
//vga_0_avalon_slave_0_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_arb_share_counter <= 0;
else if (vga_0_avalon_slave_0_arb_counter_enable)
vga_0_avalon_slave_0_arb_share_counter <= vga_0_avalon_slave_0_arb_share_counter_next_value;
end
//vga_0_avalon_slave_0_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_slavearbiterlockenable <= 0;
else if ((|vga_0_avalon_slave_0_master_qreq_vector & end_xfer_arb_share_counter_term_vga_0_avalon_slave_0) | (end_xfer_arb_share_counter_term_vga_0_avalon_slave_0 & ~vga_0_avalon_slave_0_non_bursting_master_requests))
vga_0_avalon_slave_0_slavearbiterlockenable <= |vga_0_avalon_slave_0_arb_share_counter_next_value;
end
//cpu_0/data_master vga_0/avalon_slave_0 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = vga_0_avalon_slave_0_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//vga_0_avalon_slave_0_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign vga_0_avalon_slave_0_slavearbiterlockenable2 = |vga_0_avalon_slave_0_arb_share_counter_next_value;
//cpu_0/data_master vga_0/avalon_slave_0 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = vga_0_avalon_slave_0_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//vga_0_avalon_slave_0_any_continuerequest at least one master continues requesting, which is an e_assign
assign vga_0_avalon_slave_0_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_vga_0_avalon_slave_0 = cpu_0_data_master_requests_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_writedata mux, which is an e_mux
assign vga_0_avalon_slave_0_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_vga_0_avalon_slave_0 = cpu_0_data_master_qualified_request_vga_0_avalon_slave_0;
//cpu_0/data_master saved-grant vga_0/avalon_slave_0, which is an e_assign
assign cpu_0_data_master_saved_grant_vga_0_avalon_slave_0 = cpu_0_data_master_requests_vga_0_avalon_slave_0;
//allow new arb cycle for vga_0/avalon_slave_0, which is an e_assign
assign vga_0_avalon_slave_0_allow_new_arb_cycle = 1;
//placeholder chosen master
assign vga_0_avalon_slave_0_grant_vector = 1;
//placeholder vector of master qualified-requests
assign vga_0_avalon_slave_0_master_qreq_vector = 1;
//vga_0_avalon_slave_0_reset_n assignment, which is an e_assign
assign vga_0_avalon_slave_0_reset_n = reset_n;
assign vga_0_avalon_slave_0_chipselect = cpu_0_data_master_granted_vga_0_avalon_slave_0;
//vga_0_avalon_slave_0_firsttransfer first transaction, which is an e_assign
assign vga_0_avalon_slave_0_firsttransfer = vga_0_avalon_slave_0_begins_xfer ? vga_0_avalon_slave_0_unreg_firsttransfer : vga_0_avalon_slave_0_reg_firsttransfer;
//vga_0_avalon_slave_0_unreg_firsttransfer first transaction, which is an e_assign
assign vga_0_avalon_slave_0_unreg_firsttransfer = ~(vga_0_avalon_slave_0_slavearbiterlockenable & vga_0_avalon_slave_0_any_continuerequest);
//vga_0_avalon_slave_0_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_reg_firsttransfer <= 1'b1;
else if (vga_0_avalon_slave_0_begins_xfer)
vga_0_avalon_slave_0_reg_firsttransfer <= vga_0_avalon_slave_0_unreg_firsttransfer;
end
//vga_0_avalon_slave_0_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign vga_0_avalon_slave_0_beginbursttransfer_internal = vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_read assignment, which is an e_mux
assign vga_0_avalon_slave_0_read = ((cpu_0_data_master_granted_vga_0_avalon_slave_0 & cpu_0_data_master_read))& ~vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_write assignment, which is an e_mux
assign vga_0_avalon_slave_0_write = ((cpu_0_data_master_granted_vga_0_avalon_slave_0 & cpu_0_data_master_write)) & ~vga_0_avalon_slave_0_begins_xfer & (vga_0_avalon_slave_0_wait_counter >= 1);
assign shifted_address_to_vga_0_avalon_slave_0_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//vga_0_avalon_slave_0_address mux, which is an e_mux
assign vga_0_avalon_slave_0_address = shifted_address_to_vga_0_avalon_slave_0_from_cpu_0_data_master >> 2;
//d1_vga_0_avalon_slave_0_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_vga_0_avalon_slave_0_end_xfer <= 1;
else
d1_vga_0_avalon_slave_0_end_xfer <= vga_0_avalon_slave_0_end_xfer;
end
//vga_0_avalon_slave_0_waits_for_read in a cycle, which is an e_mux
assign vga_0_avalon_slave_0_waits_for_read = vga_0_avalon_slave_0_in_a_read_cycle & vga_0_avalon_slave_0_begins_xfer;
//vga_0_avalon_slave_0_in_a_read_cycle assignment, which is an e_assign
assign vga_0_avalon_slave_0_in_a_read_cycle = cpu_0_data_master_granted_vga_0_avalon_slave_0 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = vga_0_avalon_slave_0_in_a_read_cycle;
//vga_0_avalon_slave_0_waits_for_write in a cycle, which is an e_mux
assign vga_0_avalon_slave_0_waits_for_write = vga_0_avalon_slave_0_in_a_write_cycle & wait_for_vga_0_avalon_slave_0_counter;
//vga_0_avalon_slave_0_in_a_write_cycle assignment, which is an e_assign
assign vga_0_avalon_slave_0_in_a_write_cycle = cpu_0_data_master_granted_vga_0_avalon_slave_0 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = vga_0_avalon_slave_0_in_a_write_cycle;
assign vga_0_avalon_slave_0_wait_counter_eq_0 = vga_0_avalon_slave_0_wait_counter == 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
vga_0_avalon_slave_0_wait_counter <= 0;
else
vga_0_avalon_slave_0_wait_counter <= vga_0_avalon_slave_0_counter_load_value;
end
assign vga_0_avalon_slave_0_counter_load_value = ((vga_0_avalon_slave_0_in_a_write_cycle & vga_0_avalon_slave_0_begins_xfer))? 1 :
(~vga_0_avalon_slave_0_wait_counter_eq_0)? vga_0_avalon_slave_0_wait_counter - 1 :
0;
assign wait_for_vga_0_avalon_slave_0_counter = vga_0_avalon_slave_0_begins_xfer | ~vga_0_avalon_slave_0_wait_counter_eq_0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//vga_0/avalon_slave_0 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE2_SoPC_reset_clk_50_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE2_SoPC (
// 1) global signals:
clk_50,
reset_n,
// the_i2c
scl_pad_io_to_and_from_the_i2c,
sda_pad_io_to_and_from_the_i2c,
// the_lcd
LCD_E_from_the_lcd,
LCD_RS_from_the_lcd,
LCD_RW_from_the_lcd,
LCD_data_to_and_from_the_lcd,
// the_sram
SRAM_ADDR_from_the_sram,
SRAM_CE_N_from_the_sram,
SRAM_DQ_to_and_from_the_sram,
SRAM_LB_N_from_the_sram,
SRAM_OE_N_from_the_sram,
SRAM_UB_N_from_the_sram,
SRAM_WE_N_from_the_sram,
// the_tri_state_bridge_flash_avalon_slave
select_n_to_the_cfi_flash_0,
tri_state_bridge_flash_address,
tri_state_bridge_flash_data,
tri_state_bridge_flash_readn,
write_n_to_the_cfi_flash_0,
// the_uart
rxd_to_the_uart,
txd_from_the_uart,
// the_vga_0
VGA_BLANK_from_the_vga_0,
VGA_B_from_the_vga_0,
VGA_CLK_from_the_vga_0,
VGA_G_from_the_vga_0,
VGA_HS_from_the_vga_0,
VGA_R_from_the_vga_0,
VGA_SYNC_from_the_vga_0,
VGA_VS_from_the_vga_0,
iCLK_25_to_the_vga_0
)
;
output LCD_E_from_the_lcd;
output LCD_RS_from_the_lcd;
output LCD_RW_from_the_lcd;
inout [ 7: 0] LCD_data_to_and_from_the_lcd;
output [ 17: 0] SRAM_ADDR_from_the_sram;
output SRAM_CE_N_from_the_sram;
inout [ 15: 0] SRAM_DQ_to_and_from_the_sram;
output SRAM_LB_N_from_the_sram;
output SRAM_OE_N_from_the_sram;
output SRAM_UB_N_from_the_sram;
output SRAM_WE_N_from_the_sram;
output VGA_BLANK_from_the_vga_0;
output [ 9: 0] VGA_B_from_the_vga_0;
output VGA_CLK_from_the_vga_0;
output [ 9: 0] VGA_G_from_the_vga_0;
output VGA_HS_from_the_vga_0;
output [ 9: 0] VGA_R_from_the_vga_0;
output VGA_SYNC_from_the_vga_0;
output VGA_VS_from_the_vga_0;
inout scl_pad_io_to_and_from_the_i2c;
inout sda_pad_io_to_and_from_the_i2c;
output select_n_to_the_cfi_flash_0;
output [ 21: 0] tri_state_bridge_flash_address;
inout [ 7: 0] tri_state_bridge_flash_data;
output tri_state_bridge_flash_readn;
output txd_from_the_uart;
output write_n_to_the_cfi_flash_0;
input clk_50;
input iCLK_25_to_the_vga_0;
input reset_n;
input rxd_to_the_uart;
wire LCD_E_from_the_lcd;
wire LCD_RS_from_the_lcd;
wire LCD_RW_from_the_lcd;
wire [ 7: 0] LCD_data_to_and_from_the_lcd;
wire [ 17: 0] SRAM_ADDR_from_the_sram;
wire SRAM_CE_N_from_the_sram;
wire [ 15: 0] SRAM_DQ_to_and_from_the_sram;
wire SRAM_LB_N_from_the_sram;
wire SRAM_OE_N_from_the_sram;
wire SRAM_UB_N_from_the_sram;
wire SRAM_WE_N_from_the_sram;
wire VGA_BLANK_from_the_vga_0;
wire [ 9: 0] VGA_B_from_the_vga_0;
wire VGA_CLK_from_the_vga_0;
wire [ 9: 0] VGA_G_from_the_vga_0;
wire VGA_HS_from_the_vga_0;
wire [ 9: 0] VGA_R_from_the_vga_0;
wire VGA_SYNC_from_the_vga_0;
wire VGA_VS_from_the_vga_0;
wire cfi_flash_0_s1_wait_counter_eq_0;
wire cfi_flash_0_s1_wait_counter_eq_1;
wire clk_50_reset_n;
wire [ 23: 0] cpu_0_data_master_address;
wire [ 23: 0] cpu_0_data_master_address_to_slave;
wire [ 3: 0] cpu_0_data_master_byteenable;
wire cpu_0_data_master_byteenable_cfi_flash_0_s1;
wire [ 1: 0] cpu_0_data_master_byteenable_sram_avalon_slave_0;
wire [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 15: 0] cpu_0_data_master_dbs_write_16;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire cpu_0_data_master_debugaccess;
wire cpu_0_data_master_granted_cfi_flash_0_s1;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_granted_epcs_epcs_control_port;
wire cpu_0_data_master_granted_i2c_avalon_slave_0;
wire cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_granted_lcd_control_slave;
wire cpu_0_data_master_granted_onchip_memory2_s1;
wire cpu_0_data_master_granted_sram_avalon_slave_0;
wire cpu_0_data_master_granted_sysid_0_control_slave;
wire cpu_0_data_master_granted_timer_s1;
wire cpu_0_data_master_granted_uart_s1;
wire cpu_0_data_master_granted_vga_0_avalon_slave_0;
wire [ 31: 0] cpu_0_data_master_irq;
wire cpu_0_data_master_no_byte_enables_and_last_term;
wire cpu_0_data_master_qualified_request_cfi_flash_0_s1;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_epcs_epcs_control_port;
wire cpu_0_data_master_qualified_request_i2c_avalon_slave_0;
wire cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_lcd_control_slave;
wire cpu_0_data_master_qualified_request_onchip_memory2_s1;
wire cpu_0_data_master_qualified_request_sram_avalon_slave_0;
wire cpu_0_data_master_qualified_request_sysid_0_control_slave;
wire cpu_0_data_master_qualified_request_timer_s1;
wire cpu_0_data_master_qualified_request_uart_s1;
wire cpu_0_data_master_qualified_request_vga_0_avalon_slave_0;
wire cpu_0_data_master_read;
wire cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_epcs_epcs_control_port;
wire cpu_0_data_master_read_data_valid_i2c_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_lcd_control_slave;
wire cpu_0_data_master_read_data_valid_onchip_memory2_s1;
wire cpu_0_data_master_read_data_valid_sram_avalon_slave_0;
wire cpu_0_data_master_read_data_valid_sysid_0_control_slave;
wire cpu_0_data_master_read_data_valid_timer_s1;
wire cpu_0_data_master_read_data_valid_uart_s1;
wire cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_requests_cfi_flash_0_s1;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_epcs_epcs_control_port;
wire cpu_0_data_master_requests_i2c_avalon_slave_0;
wire cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
wire cpu_0_data_master_requests_lcd_control_slave;
wire cpu_0_data_master_requests_onchip_memory2_s1;
wire cpu_0_data_master_requests_sram_avalon_slave_0;
wire cpu_0_data_master_requests_sysid_0_control_slave;
wire cpu_0_data_master_requests_timer_s1;
wire cpu_0_data_master_requests_uart_s1;
wire cpu_0_data_master_requests_vga_0_avalon_slave_0;
wire cpu_0_data_master_waitrequest;
wire cpu_0_data_master_write;
wire [ 31: 0] cpu_0_data_master_writedata;
wire [ 23: 0] cpu_0_instruction_master_address;
wire [ 23: 0] cpu_0_instruction_master_address_to_slave;
wire [ 1: 0] cpu_0_instruction_master_dbs_address;
wire cpu_0_instruction_master_granted_cfi_flash_0_s1;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_granted_epcs_epcs_control_port;
wire cpu_0_instruction_master_granted_onchip_memory2_s1;
wire cpu_0_instruction_master_granted_sram_avalon_slave_0;
wire [ 1: 0] cpu_0_instruction_master_latency_counter;
wire cpu_0_instruction_master_qualified_request_cfi_flash_0_s1;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_epcs_epcs_control_port;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_s1;
wire cpu_0_instruction_master_qualified_request_sram_avalon_slave_0;
wire cpu_0_instruction_master_read;
wire cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_s1;
wire cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_readdatavalid;
wire cpu_0_instruction_master_requests_cfi_flash_0_s1;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_epcs_epcs_control_port;
wire cpu_0_instruction_master_requests_onchip_memory2_s1;
wire cpu_0_instruction_master_requests_sram_avalon_slave_0;
wire cpu_0_instruction_master_waitrequest;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire cpu_0_jtag_debug_module_debugaccess;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
wire d1_cpu_0_jtag_debug_module_end_xfer;
wire d1_epcs_epcs_control_port_end_xfer;
wire d1_i2c_avalon_slave_0_end_xfer;
wire d1_jtag_uart_avalon_jtag_slave_end_xfer;
wire d1_lcd_control_slave_end_xfer;
wire d1_onchip_memory2_s1_end_xfer;
wire d1_sram_avalon_slave_0_end_xfer;
wire d1_sysid_0_control_slave_end_xfer;
wire d1_timer_s1_end_xfer;
wire d1_tri_state_bridge_flash_avalon_slave_end_xfer;
wire d1_uart_s1_end_xfer;
wire d1_vga_0_avalon_slave_0_end_xfer;
wire [ 8: 0] epcs_epcs_control_port_address;
wire epcs_epcs_control_port_chipselect;
wire epcs_epcs_control_port_dataavailable;
wire epcs_epcs_control_port_dataavailable_from_sa;
wire epcs_epcs_control_port_endofpacket;
wire epcs_epcs_control_port_endofpacket_from_sa;
wire epcs_epcs_control_port_irq;
wire epcs_epcs_control_port_irq_from_sa;
wire epcs_epcs_control_port_read_n;
wire [ 31: 0] epcs_epcs_control_port_readdata;
wire [ 31: 0] epcs_epcs_control_port_readdata_from_sa;
wire epcs_epcs_control_port_readyfordata;
wire epcs_epcs_control_port_readyfordata_from_sa;
wire epcs_epcs_control_port_reset_n;
wire epcs_epcs_control_port_write_n;
wire [ 31: 0] epcs_epcs_control_port_writedata;
wire [ 2: 0] i2c_avalon_slave_0_address;
wire i2c_avalon_slave_0_chipselect;
wire i2c_avalon_slave_0_irq;
wire i2c_avalon_slave_0_irq_from_sa;
wire [ 7: 0] i2c_avalon_slave_0_readdata;
wire [ 7: 0] i2c_avalon_slave_0_readdata_from_sa;
wire i2c_avalon_slave_0_reset;
wire i2c_avalon_slave_0_waitrequest_n;
wire i2c_avalon_slave_0_waitrequest_n_from_sa;
wire i2c_avalon_slave_0_write;
wire [ 7: 0] i2c_avalon_slave_0_writedata;
wire [ 7: 0] incoming_tri_state_bridge_flash_data;
wire [ 7: 0] incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0;
wire jtag_uart_avalon_jtag_slave_address;
wire jtag_uart_avalon_jtag_slave_chipselect;
wire jtag_uart_avalon_jtag_slave_dataavailable;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_irq;
wire jtag_uart_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
wire jtag_uart_avalon_jtag_slave_reset_n;
wire jtag_uart_avalon_jtag_slave_waitrequest;
wire jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
wire [ 1: 0] lcd_control_slave_address;
wire lcd_control_slave_begintransfer;
wire lcd_control_slave_read;
wire [ 7: 0] lcd_control_slave_readdata;
wire [ 7: 0] lcd_control_slave_readdata_from_sa;
wire lcd_control_slave_reset_n;
wire lcd_control_slave_wait_counter_eq_0;
wire lcd_control_slave_wait_counter_eq_1;
wire lcd_control_slave_write;
wire [ 7: 0] lcd_control_slave_writedata;
wire [ 9: 0] onchip_memory2_s1_address;
wire [ 3: 0] onchip_memory2_s1_byteenable;
wire onchip_memory2_s1_chipselect;
wire onchip_memory2_s1_clken;
wire [ 31: 0] onchip_memory2_s1_readdata;
wire [ 31: 0] onchip_memory2_s1_readdata_from_sa;
wire onchip_memory2_s1_reset;
wire onchip_memory2_s1_write;
wire [ 31: 0] onchip_memory2_s1_writedata;
wire registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1;
wire reset_n_sources;
wire scl_pad_io_to_and_from_the_i2c;
wire sda_pad_io_to_and_from_the_i2c;
wire select_n_to_the_cfi_flash_0;
wire [ 17: 0] sram_avalon_slave_0_address;
wire [ 1: 0] sram_avalon_slave_0_byteenable_n;
wire sram_avalon_slave_0_chipselect_n;
wire sram_avalon_slave_0_read_n;
wire [ 15: 0] sram_avalon_slave_0_readdata;
wire [ 15: 0] sram_avalon_slave_0_readdata_from_sa;
wire sram_avalon_slave_0_reset_n;
wire sram_avalon_slave_0_wait_counter_eq_0;
wire sram_avalon_slave_0_write_n;
wire [ 15: 0] sram_avalon_slave_0_writedata;
wire sysid_0_control_slave_address;
wire sysid_0_control_slave_clock;
wire [ 31: 0] sysid_0_control_slave_readdata;
wire [ 31: 0] sysid_0_control_slave_readdata_from_sa;
wire sysid_0_control_slave_reset_n;
wire [ 2: 0] timer_s1_address;
wire timer_s1_chipselect;
wire timer_s1_irq;
wire timer_s1_irq_from_sa;
wire [ 15: 0] timer_s1_readdata;
wire [ 15: 0] timer_s1_readdata_from_sa;
wire timer_s1_reset_n;
wire timer_s1_write_n;
wire [ 15: 0] timer_s1_writedata;
wire [ 21: 0] tri_state_bridge_flash_address;
wire [ 7: 0] tri_state_bridge_flash_data;
wire tri_state_bridge_flash_readn;
wire txd_from_the_uart;
wire [ 2: 0] uart_s1_address;
wire uart_s1_begintransfer;
wire uart_s1_chipselect;
wire uart_s1_dataavailable;
wire uart_s1_dataavailable_from_sa;
wire uart_s1_irq;
wire uart_s1_irq_from_sa;
wire uart_s1_read_n;
wire [ 15: 0] uart_s1_readdata;
wire [ 15: 0] uart_s1_readdata_from_sa;
wire uart_s1_readyfordata;
wire uart_s1_readyfordata_from_sa;
wire uart_s1_reset_n;
wire uart_s1_write_n;
wire [ 15: 0] uart_s1_writedata;
wire [ 18: 0] vga_0_avalon_slave_0_address;
wire vga_0_avalon_slave_0_chipselect;
wire vga_0_avalon_slave_0_read;
wire [ 15: 0] vga_0_avalon_slave_0_readdata;
wire [ 15: 0] vga_0_avalon_slave_0_readdata_from_sa;
wire vga_0_avalon_slave_0_reset_n;
wire vga_0_avalon_slave_0_wait_counter_eq_0;
wire vga_0_avalon_slave_0_write;
wire [ 15: 0] vga_0_avalon_slave_0_writedata;
wire write_n_to_the_cfi_flash_0;
cpu_0_jtag_debug_module_arbitrator the_cpu_0_jtag_debug_module
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_debugaccess (cpu_0_data_master_debugaccess),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.cpu_0_jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.cpu_0_jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.cpu_0_jtag_debug_module_chipselect (cpu_0_jtag_debug_module_chipselect),
.cpu_0_jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.cpu_0_jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.cpu_0_jtag_debug_module_reset_n (cpu_0_jtag_debug_module_reset_n),
.cpu_0_jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.cpu_0_jtag_debug_module_resetrequest_from_sa (cpu_0_jtag_debug_module_resetrequest_from_sa),
.cpu_0_jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.cpu_0_jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.reset_n (clk_50_reset_n)
);
cpu_0_data_master_arbitrator the_cpu_0_data_master
(
.cfi_flash_0_s1_wait_counter_eq_0 (cfi_flash_0_s1_wait_counter_eq_0),
.cfi_flash_0_s1_wait_counter_eq_1 (cfi_flash_0_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_0_data_master_address (cpu_0_data_master_address),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable_cfi_flash_0_s1 (cpu_0_data_master_byteenable_cfi_flash_0_s1),
.cpu_0_data_master_byteenable_sram_avalon_slave_0 (cpu_0_data_master_byteenable_sram_avalon_slave_0),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_16 (cpu_0_data_master_dbs_write_16),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_cfi_flash_0_s1 (cpu_0_data_master_granted_cfi_flash_0_s1),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_granted_epcs_epcs_control_port (cpu_0_data_master_granted_epcs_epcs_control_port),
.cpu_0_data_master_granted_i2c_avalon_slave_0 (cpu_0_data_master_granted_i2c_avalon_slave_0),
.cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_granted_lcd_control_slave (cpu_0_data_master_granted_lcd_control_slave),
.cpu_0_data_master_granted_onchip_memory2_s1 (cpu_0_data_master_granted_onchip_memory2_s1),
.cpu_0_data_master_granted_sram_avalon_slave_0 (cpu_0_data_master_granted_sram_avalon_slave_0),
.cpu_0_data_master_granted_sysid_0_control_slave (cpu_0_data_master_granted_sysid_0_control_slave),
.cpu_0_data_master_granted_timer_s1 (cpu_0_data_master_granted_timer_s1),
.cpu_0_data_master_granted_uart_s1 (cpu_0_data_master_granted_uart_s1),
.cpu_0_data_master_granted_vga_0_avalon_slave_0 (cpu_0_data_master_granted_vga_0_avalon_slave_0),
.cpu_0_data_master_irq (cpu_0_data_master_irq),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_cfi_flash_0_s1 (cpu_0_data_master_qualified_request_cfi_flash_0_s1),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_epcs_epcs_control_port (cpu_0_data_master_qualified_request_epcs_epcs_control_port),
.cpu_0_data_master_qualified_request_i2c_avalon_slave_0 (cpu_0_data_master_qualified_request_i2c_avalon_slave_0),
.cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_lcd_control_slave (cpu_0_data_master_qualified_request_lcd_control_slave),
.cpu_0_data_master_qualified_request_onchip_memory2_s1 (cpu_0_data_master_qualified_request_onchip_memory2_s1),
.cpu_0_data_master_qualified_request_sram_avalon_slave_0 (cpu_0_data_master_qualified_request_sram_avalon_slave_0),
.cpu_0_data_master_qualified_request_sysid_0_control_slave (cpu_0_data_master_qualified_request_sysid_0_control_slave),
.cpu_0_data_master_qualified_request_timer_s1 (cpu_0_data_master_qualified_request_timer_s1),
.cpu_0_data_master_qualified_request_uart_s1 (cpu_0_data_master_qualified_request_uart_s1),
.cpu_0_data_master_qualified_request_vga_0_avalon_slave_0 (cpu_0_data_master_qualified_request_vga_0_avalon_slave_0),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_cfi_flash_0_s1 (cpu_0_data_master_read_data_valid_cfi_flash_0_s1),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_read_data_valid_epcs_epcs_control_port (cpu_0_data_master_read_data_valid_epcs_epcs_control_port),
.cpu_0_data_master_read_data_valid_i2c_avalon_slave_0 (cpu_0_data_master_read_data_valid_i2c_avalon_slave_0),
.cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_read_data_valid_lcd_control_slave (cpu_0_data_master_read_data_valid_lcd_control_slave),
.cpu_0_data_master_read_data_valid_onchip_memory2_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_s1),
.cpu_0_data_master_read_data_valid_sram_avalon_slave_0 (cpu_0_data_master_read_data_valid_sram_avalon_slave_0),
.cpu_0_data_master_read_data_valid_sysid_0_control_slave (cpu_0_data_master_read_data_valid_sysid_0_control_slave),
.cpu_0_data_master_read_data_valid_timer_s1 (cpu_0_data_master_read_data_valid_timer_s1),
.cpu_0_data_master_read_data_valid_uart_s1 (cpu_0_data_master_read_data_valid_uart_s1),
.cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0 (cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0),
.cpu_0_data_master_readdata (cpu_0_data_master_readdata),
.cpu_0_data_master_requests_cfi_flash_0_s1 (cpu_0_data_master_requests_cfi_flash_0_s1),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_epcs_epcs_control_port (cpu_0_data_master_requests_epcs_epcs_control_port),
.cpu_0_data_master_requests_i2c_avalon_slave_0 (cpu_0_data_master_requests_i2c_avalon_slave_0),
.cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_requests_lcd_control_slave (cpu_0_data_master_requests_lcd_control_slave),
.cpu_0_data_master_requests_onchip_memory2_s1 (cpu_0_data_master_requests_onchip_memory2_s1),
.cpu_0_data_master_requests_sram_avalon_slave_0 (cpu_0_data_master_requests_sram_avalon_slave_0),
.cpu_0_data_master_requests_sysid_0_control_slave (cpu_0_data_master_requests_sysid_0_control_slave),
.cpu_0_data_master_requests_timer_s1 (cpu_0_data_master_requests_timer_s1),
.cpu_0_data_master_requests_uart_s1 (cpu_0_data_master_requests_uart_s1),
.cpu_0_data_master_requests_vga_0_avalon_slave_0 (cpu_0_data_master_requests_vga_0_avalon_slave_0),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_epcs_epcs_control_port_end_xfer (d1_epcs_epcs_control_port_end_xfer),
.d1_i2c_avalon_slave_0_end_xfer (d1_i2c_avalon_slave_0_end_xfer),
.d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer),
.d1_lcd_control_slave_end_xfer (d1_lcd_control_slave_end_xfer),
.d1_onchip_memory2_s1_end_xfer (d1_onchip_memory2_s1_end_xfer),
.d1_sram_avalon_slave_0_end_xfer (d1_sram_avalon_slave_0_end_xfer),
.d1_sysid_0_control_slave_end_xfer (d1_sysid_0_control_slave_end_xfer),
.d1_timer_s1_end_xfer (d1_timer_s1_end_xfer),
.d1_tri_state_bridge_flash_avalon_slave_end_xfer (d1_tri_state_bridge_flash_avalon_slave_end_xfer),
.d1_uart_s1_end_xfer (d1_uart_s1_end_xfer),
.d1_vga_0_avalon_slave_0_end_xfer (d1_vga_0_avalon_slave_0_end_xfer),
.epcs_epcs_control_port_irq_from_sa (epcs_epcs_control_port_irq_from_sa),
.epcs_epcs_control_port_readdata_from_sa (epcs_epcs_control_port_readdata_from_sa),
.i2c_avalon_slave_0_irq_from_sa (i2c_avalon_slave_0_irq_from_sa),
.i2c_avalon_slave_0_readdata_from_sa (i2c_avalon_slave_0_readdata_from_sa),
.i2c_avalon_slave_0_waitrequest_n_from_sa (i2c_avalon_slave_0_waitrequest_n_from_sa),
.incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0 (incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0),
.jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa),
.jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
.lcd_control_slave_readdata_from_sa (lcd_control_slave_readdata_from_sa),
.lcd_control_slave_wait_counter_eq_0 (lcd_control_slave_wait_counter_eq_0),
.lcd_control_slave_wait_counter_eq_1 (lcd_control_slave_wait_counter_eq_1),
.onchip_memory2_s1_readdata_from_sa (onchip_memory2_s1_readdata_from_sa),
.registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1),
.reset_n (clk_50_reset_n),
.sram_avalon_slave_0_readdata_from_sa (sram_avalon_slave_0_readdata_from_sa),
.sram_avalon_slave_0_wait_counter_eq_0 (sram_avalon_slave_0_wait_counter_eq_0),
.sysid_0_control_slave_readdata_from_sa (sysid_0_control_slave_readdata_from_sa),
.timer_s1_irq_from_sa (timer_s1_irq_from_sa),
.timer_s1_readdata_from_sa (timer_s1_readdata_from_sa),
.uart_s1_irq_from_sa (uart_s1_irq_from_sa),
.uart_s1_readdata_from_sa (uart_s1_readdata_from_sa),
.vga_0_avalon_slave_0_readdata_from_sa (vga_0_avalon_slave_0_readdata_from_sa),
.vga_0_avalon_slave_0_wait_counter_eq_0 (vga_0_avalon_slave_0_wait_counter_eq_0)
);
cpu_0_instruction_master_arbitrator the_cpu_0_instruction_master
(
.cfi_flash_0_s1_wait_counter_eq_0 (cfi_flash_0_s1_wait_counter_eq_0),
.cfi_flash_0_s1_wait_counter_eq_1 (cfi_flash_0_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_0_instruction_master_address (cpu_0_instruction_master_address),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_dbs_address (cpu_0_instruction_master_dbs_address),
.cpu_0_instruction_master_granted_cfi_flash_0_s1 (cpu_0_instruction_master_granted_cfi_flash_0_s1),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_granted_epcs_epcs_control_port (cpu_0_instruction_master_granted_epcs_epcs_control_port),
.cpu_0_instruction_master_granted_onchip_memory2_s1 (cpu_0_instruction_master_granted_onchip_memory2_s1),
.cpu_0_instruction_master_granted_sram_avalon_slave_0 (cpu_0_instruction_master_granted_sram_avalon_slave_0),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 (cpu_0_instruction_master_qualified_request_cfi_flash_0_s1),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_qualified_request_epcs_epcs_control_port (cpu_0_instruction_master_qualified_request_epcs_epcs_control_port),
.cpu_0_instruction_master_qualified_request_onchip_memory2_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_s1),
.cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 (cpu_0_instruction_master_qualified_request_sram_avalon_slave_0),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port (cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_s1),
.cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0 (cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0),
.cpu_0_instruction_master_readdata (cpu_0_instruction_master_readdata),
.cpu_0_instruction_master_readdatavalid (cpu_0_instruction_master_readdatavalid),
.cpu_0_instruction_master_requests_cfi_flash_0_s1 (cpu_0_instruction_master_requests_cfi_flash_0_s1),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_epcs_epcs_control_port (cpu_0_instruction_master_requests_epcs_epcs_control_port),
.cpu_0_instruction_master_requests_onchip_memory2_s1 (cpu_0_instruction_master_requests_onchip_memory2_s1),
.cpu_0_instruction_master_requests_sram_avalon_slave_0 (cpu_0_instruction_master_requests_sram_avalon_slave_0),
.cpu_0_instruction_master_waitrequest (cpu_0_instruction_master_waitrequest),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_epcs_epcs_control_port_end_xfer (d1_epcs_epcs_control_port_end_xfer),
.d1_onchip_memory2_s1_end_xfer (d1_onchip_memory2_s1_end_xfer),
.d1_sram_avalon_slave_0_end_xfer (d1_sram_avalon_slave_0_end_xfer),
.d1_tri_state_bridge_flash_avalon_slave_end_xfer (d1_tri_state_bridge_flash_avalon_slave_end_xfer),
.epcs_epcs_control_port_readdata_from_sa (epcs_epcs_control_port_readdata_from_sa),
.incoming_tri_state_bridge_flash_data (incoming_tri_state_bridge_flash_data),
.onchip_memory2_s1_readdata_from_sa (onchip_memory2_s1_readdata_from_sa),
.reset_n (clk_50_reset_n),
.sram_avalon_slave_0_readdata_from_sa (sram_avalon_slave_0_readdata_from_sa),
.sram_avalon_slave_0_wait_counter_eq_0 (sram_avalon_slave_0_wait_counter_eq_0)
);
cpu_0 the_cpu_0
(
.clk (clk_50),
.d_address (cpu_0_data_master_address),
.d_byteenable (cpu_0_data_master_byteenable),
.d_irq (cpu_0_data_master_irq),
.d_read (cpu_0_data_master_read),
.d_readdata (cpu_0_data_master_readdata),
.d_waitrequest (cpu_0_data_master_waitrequest),
.d_write (cpu_0_data_master_write),
.d_writedata (cpu_0_data_master_writedata),
.i_address (cpu_0_instruction_master_address),
.i_read (cpu_0_instruction_master_read),
.i_readdata (cpu_0_instruction_master_readdata),
.i_readdatavalid (cpu_0_instruction_master_readdatavalid),
.i_waitrequest (cpu_0_instruction_master_waitrequest),
.jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.jtag_debug_module_debugaccess_to_roms (cpu_0_data_master_debugaccess),
.jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.jtag_debug_module_select (cpu_0_jtag_debug_module_chipselect),
.jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.reset_n (cpu_0_jtag_debug_module_reset_n)
);
epcs_epcs_control_port_arbitrator the_epcs_epcs_control_port
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_epcs_epcs_control_port (cpu_0_data_master_granted_epcs_epcs_control_port),
.cpu_0_data_master_qualified_request_epcs_epcs_control_port (cpu_0_data_master_qualified_request_epcs_epcs_control_port),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_epcs_epcs_control_port (cpu_0_data_master_read_data_valid_epcs_epcs_control_port),
.cpu_0_data_master_requests_epcs_epcs_control_port (cpu_0_data_master_requests_epcs_epcs_control_port),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_epcs_epcs_control_port (cpu_0_instruction_master_granted_epcs_epcs_control_port),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_epcs_epcs_control_port (cpu_0_instruction_master_qualified_request_epcs_epcs_control_port),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port (cpu_0_instruction_master_read_data_valid_epcs_epcs_control_port),
.cpu_0_instruction_master_requests_epcs_epcs_control_port (cpu_0_instruction_master_requests_epcs_epcs_control_port),
.d1_epcs_epcs_control_port_end_xfer (d1_epcs_epcs_control_port_end_xfer),
.epcs_epcs_control_port_address (epcs_epcs_control_port_address),
.epcs_epcs_control_port_chipselect (epcs_epcs_control_port_chipselect),
.epcs_epcs_control_port_dataavailable (epcs_epcs_control_port_dataavailable),
.epcs_epcs_control_port_dataavailable_from_sa (epcs_epcs_control_port_dataavailable_from_sa),
.epcs_epcs_control_port_endofpacket (epcs_epcs_control_port_endofpacket),
.epcs_epcs_control_port_endofpacket_from_sa (epcs_epcs_control_port_endofpacket_from_sa),
.epcs_epcs_control_port_irq (epcs_epcs_control_port_irq),
.epcs_epcs_control_port_irq_from_sa (epcs_epcs_control_port_irq_from_sa),
.epcs_epcs_control_port_read_n (epcs_epcs_control_port_read_n),
.epcs_epcs_control_port_readdata (epcs_epcs_control_port_readdata),
.epcs_epcs_control_port_readdata_from_sa (epcs_epcs_control_port_readdata_from_sa),
.epcs_epcs_control_port_readyfordata (epcs_epcs_control_port_readyfordata),
.epcs_epcs_control_port_readyfordata_from_sa (epcs_epcs_control_port_readyfordata_from_sa),
.epcs_epcs_control_port_reset_n (epcs_epcs_control_port_reset_n),
.epcs_epcs_control_port_write_n (epcs_epcs_control_port_write_n),
.epcs_epcs_control_port_writedata (epcs_epcs_control_port_writedata),
.reset_n (clk_50_reset_n)
);
epcs the_epcs
(
.address (epcs_epcs_control_port_address),
.chipselect (epcs_epcs_control_port_chipselect),
.clk (clk_50),
.dataavailable (epcs_epcs_control_port_dataavailable),
.endofpacket (epcs_epcs_control_port_endofpacket),
.irq (epcs_epcs_control_port_irq),
.read_n (epcs_epcs_control_port_read_n),
.readdata (epcs_epcs_control_port_readdata),
.readyfordata (epcs_epcs_control_port_readyfordata),
.reset_n (epcs_epcs_control_port_reset_n),
.write_n (epcs_epcs_control_port_write_n),
.writedata (epcs_epcs_control_port_writedata)
);
i2c_avalon_slave_0_arbitrator the_i2c_avalon_slave_0
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_i2c_avalon_slave_0 (cpu_0_data_master_granted_i2c_avalon_slave_0),
.cpu_0_data_master_qualified_request_i2c_avalon_slave_0 (cpu_0_data_master_qualified_request_i2c_avalon_slave_0),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_i2c_avalon_slave_0 (cpu_0_data_master_read_data_valid_i2c_avalon_slave_0),
.cpu_0_data_master_requests_i2c_avalon_slave_0 (cpu_0_data_master_requests_i2c_avalon_slave_0),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_i2c_avalon_slave_0_end_xfer (d1_i2c_avalon_slave_0_end_xfer),
.i2c_avalon_slave_0_address (i2c_avalon_slave_0_address),
.i2c_avalon_slave_0_chipselect (i2c_avalon_slave_0_chipselect),
.i2c_avalon_slave_0_irq (i2c_avalon_slave_0_irq),
.i2c_avalon_slave_0_irq_from_sa (i2c_avalon_slave_0_irq_from_sa),
.i2c_avalon_slave_0_readdata (i2c_avalon_slave_0_readdata),
.i2c_avalon_slave_0_readdata_from_sa (i2c_avalon_slave_0_readdata_from_sa),
.i2c_avalon_slave_0_reset (i2c_avalon_slave_0_reset),
.i2c_avalon_slave_0_waitrequest_n (i2c_avalon_slave_0_waitrequest_n),
.i2c_avalon_slave_0_waitrequest_n_from_sa (i2c_avalon_slave_0_waitrequest_n_from_sa),
.i2c_avalon_slave_0_write (i2c_avalon_slave_0_write),
.i2c_avalon_slave_0_writedata (i2c_avalon_slave_0_writedata),
.reset_n (clk_50_reset_n)
);
i2c the_i2c
(
.scl_pad_io (scl_pad_io_to_and_from_the_i2c),
.sda_pad_io (sda_pad_io_to_and_from_the_i2c),
.wb_ack_o (i2c_avalon_slave_0_waitrequest_n),
.wb_adr_i (i2c_avalon_slave_0_address),
.wb_clk_i (clk_50),
.wb_dat_i (i2c_avalon_slave_0_writedata),
.wb_dat_o (i2c_avalon_slave_0_readdata),
.wb_inta_o (i2c_avalon_slave_0_irq),
.wb_rst_i (i2c_avalon_slave_0_reset),
.wb_stb_i (i2c_avalon_slave_0_chipselect),
.wb_we_i (i2c_avalon_slave_0_write)
);
jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_jtag_uart_avalon_jtag_slave_end_xfer (d1_jtag_uart_avalon_jtag_slave_end_xfer),
.jtag_uart_avalon_jtag_slave_address (jtag_uart_avalon_jtag_slave_address),
.jtag_uart_avalon_jtag_slave_chipselect (jtag_uart_avalon_jtag_slave_chipselect),
.jtag_uart_avalon_jtag_slave_dataavailable (jtag_uart_avalon_jtag_slave_dataavailable),
.jtag_uart_avalon_jtag_slave_dataavailable_from_sa (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
.jtag_uart_avalon_jtag_slave_irq (jtag_uart_avalon_jtag_slave_irq),
.jtag_uart_avalon_jtag_slave_irq_from_sa (jtag_uart_avalon_jtag_slave_irq_from_sa),
.jtag_uart_avalon_jtag_slave_read_n (jtag_uart_avalon_jtag_slave_read_n),
.jtag_uart_avalon_jtag_slave_readdata (jtag_uart_avalon_jtag_slave_readdata),
.jtag_uart_avalon_jtag_slave_readdata_from_sa (jtag_uart_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_avalon_jtag_slave_readyfordata (jtag_uart_avalon_jtag_slave_readyfordata),
.jtag_uart_avalon_jtag_slave_readyfordata_from_sa (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
.jtag_uart_avalon_jtag_slave_reset_n (jtag_uart_avalon_jtag_slave_reset_n),
.jtag_uart_avalon_jtag_slave_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
.jtag_uart_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
.jtag_uart_avalon_jtag_slave_write_n (jtag_uart_avalon_jtag_slave_write_n),
.jtag_uart_avalon_jtag_slave_writedata (jtag_uart_avalon_jtag_slave_writedata),
.reset_n (clk_50_reset_n)
);
jtag_uart the_jtag_uart
(
.av_address (jtag_uart_avalon_jtag_slave_address),
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect),
.av_irq (jtag_uart_avalon_jtag_slave_irq),
.av_read_n (jtag_uart_avalon_jtag_slave_read_n),
.av_readdata (jtag_uart_avalon_jtag_slave_readdata),
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
.av_write_n (jtag_uart_avalon_jtag_slave_write_n),
.av_writedata (jtag_uart_avalon_jtag_slave_writedata),
.clk (clk_50),
.dataavailable (jtag_uart_avalon_jtag_slave_dataavailable),
.readyfordata (jtag_uart_avalon_jtag_slave_readyfordata),
.rst_n (jtag_uart_avalon_jtag_slave_reset_n)
);
lcd_control_slave_arbitrator the_lcd_control_slave
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_lcd_control_slave (cpu_0_data_master_granted_lcd_control_slave),
.cpu_0_data_master_qualified_request_lcd_control_slave (cpu_0_data_master_qualified_request_lcd_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_lcd_control_slave (cpu_0_data_master_read_data_valid_lcd_control_slave),
.cpu_0_data_master_requests_lcd_control_slave (cpu_0_data_master_requests_lcd_control_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_lcd_control_slave_end_xfer (d1_lcd_control_slave_end_xfer),
.lcd_control_slave_address (lcd_control_slave_address),
.lcd_control_slave_begintransfer (lcd_control_slave_begintransfer),
.lcd_control_slave_read (lcd_control_slave_read),
.lcd_control_slave_readdata (lcd_control_slave_readdata),
.lcd_control_slave_readdata_from_sa (lcd_control_slave_readdata_from_sa),
.lcd_control_slave_reset_n (lcd_control_slave_reset_n),
.lcd_control_slave_wait_counter_eq_0 (lcd_control_slave_wait_counter_eq_0),
.lcd_control_slave_wait_counter_eq_1 (lcd_control_slave_wait_counter_eq_1),
.lcd_control_slave_write (lcd_control_slave_write),
.lcd_control_slave_writedata (lcd_control_slave_writedata),
.reset_n (clk_50_reset_n)
);
lcd the_lcd
(
.LCD_E (LCD_E_from_the_lcd),
.LCD_RS (LCD_RS_from_the_lcd),
.LCD_RW (LCD_RW_from_the_lcd),
.LCD_data (LCD_data_to_and_from_the_lcd),
.address (lcd_control_slave_address),
.begintransfer (lcd_control_slave_begintransfer),
.clk (clk_50),
.read (lcd_control_slave_read),
.readdata (lcd_control_slave_readdata),
.reset_n (lcd_control_slave_reset_n),
.write (lcd_control_slave_write),
.writedata (lcd_control_slave_writedata)
);
onchip_memory2_s1_arbitrator the_onchip_memory2_s1
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_onchip_memory2_s1 (cpu_0_data_master_granted_onchip_memory2_s1),
.cpu_0_data_master_qualified_request_onchip_memory2_s1 (cpu_0_data_master_qualified_request_onchip_memory2_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_onchip_memory2_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_s1),
.cpu_0_data_master_requests_onchip_memory2_s1 (cpu_0_data_master_requests_onchip_memory2_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_onchip_memory2_s1 (cpu_0_instruction_master_granted_onchip_memory2_s1),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_onchip_memory2_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_s1),
.cpu_0_instruction_master_requests_onchip_memory2_s1 (cpu_0_instruction_master_requests_onchip_memory2_s1),
.d1_onchip_memory2_s1_end_xfer (d1_onchip_memory2_s1_end_xfer),
.onchip_memory2_s1_address (onchip_memory2_s1_address),
.onchip_memory2_s1_byteenable (onchip_memory2_s1_byteenable),
.onchip_memory2_s1_chipselect (onchip_memory2_s1_chipselect),
.onchip_memory2_s1_clken (onchip_memory2_s1_clken),
.onchip_memory2_s1_readdata (onchip_memory2_s1_readdata),
.onchip_memory2_s1_readdata_from_sa (onchip_memory2_s1_readdata_from_sa),
.onchip_memory2_s1_reset (onchip_memory2_s1_reset),
.onchip_memory2_s1_write (onchip_memory2_s1_write),
.onchip_memory2_s1_writedata (onchip_memory2_s1_writedata),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_s1),
.reset_n (clk_50_reset_n)
);
onchip_memory2 the_onchip_memory2
(
.address (onchip_memory2_s1_address),
.byteenable (onchip_memory2_s1_byteenable),
.chipselect (onchip_memory2_s1_chipselect),
.clk (clk_50),
.clken (onchip_memory2_s1_clken),
.readdata (onchip_memory2_s1_readdata),
.reset (onchip_memory2_s1_reset),
.write (onchip_memory2_s1_write),
.writedata (onchip_memory2_s1_writedata)
);
sram_avalon_slave_0_arbitrator the_sram_avalon_slave_0
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_byteenable_sram_avalon_slave_0 (cpu_0_data_master_byteenable_sram_avalon_slave_0),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_16 (cpu_0_data_master_dbs_write_16),
.cpu_0_data_master_granted_sram_avalon_slave_0 (cpu_0_data_master_granted_sram_avalon_slave_0),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_sram_avalon_slave_0 (cpu_0_data_master_qualified_request_sram_avalon_slave_0),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sram_avalon_slave_0 (cpu_0_data_master_read_data_valid_sram_avalon_slave_0),
.cpu_0_data_master_requests_sram_avalon_slave_0 (cpu_0_data_master_requests_sram_avalon_slave_0),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_dbs_address (cpu_0_instruction_master_dbs_address),
.cpu_0_instruction_master_granted_sram_avalon_slave_0 (cpu_0_instruction_master_granted_sram_avalon_slave_0),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_sram_avalon_slave_0 (cpu_0_instruction_master_qualified_request_sram_avalon_slave_0),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0 (cpu_0_instruction_master_read_data_valid_sram_avalon_slave_0),
.cpu_0_instruction_master_requests_sram_avalon_slave_0 (cpu_0_instruction_master_requests_sram_avalon_slave_0),
.d1_sram_avalon_slave_0_end_xfer (d1_sram_avalon_slave_0_end_xfer),
.reset_n (clk_50_reset_n),
.sram_avalon_slave_0_address (sram_avalon_slave_0_address),
.sram_avalon_slave_0_byteenable_n (sram_avalon_slave_0_byteenable_n),
.sram_avalon_slave_0_chipselect_n (sram_avalon_slave_0_chipselect_n),
.sram_avalon_slave_0_read_n (sram_avalon_slave_0_read_n),
.sram_avalon_slave_0_readdata (sram_avalon_slave_0_readdata),
.sram_avalon_slave_0_readdata_from_sa (sram_avalon_slave_0_readdata_from_sa),
.sram_avalon_slave_0_reset_n (sram_avalon_slave_0_reset_n),
.sram_avalon_slave_0_wait_counter_eq_0 (sram_avalon_slave_0_wait_counter_eq_0),
.sram_avalon_slave_0_write_n (sram_avalon_slave_0_write_n),
.sram_avalon_slave_0_writedata (sram_avalon_slave_0_writedata)
);
sram the_sram
(
.SRAM_ADDR (SRAM_ADDR_from_the_sram),
.SRAM_CE_N (SRAM_CE_N_from_the_sram),
.SRAM_DQ (SRAM_DQ_to_and_from_the_sram),
.SRAM_LB_N (SRAM_LB_N_from_the_sram),
.SRAM_OE_N (SRAM_OE_N_from_the_sram),
.SRAM_UB_N (SRAM_UB_N_from_the_sram),
.SRAM_WE_N (SRAM_WE_N_from_the_sram),
.iADDR (sram_avalon_slave_0_address),
.iBE_N (sram_avalon_slave_0_byteenable_n),
.iCE_N (sram_avalon_slave_0_chipselect_n),
.iCLK (clk_50),
.iDATA (sram_avalon_slave_0_writedata),
.iOE_N (sram_avalon_slave_0_read_n),
.iRST_N (sram_avalon_slave_0_reset_n),
.iWE_N (sram_avalon_slave_0_write_n),
.oDATA (sram_avalon_slave_0_readdata)
);
sysid_0_control_slave_arbitrator the_sysid_0_control_slave
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_sysid_0_control_slave (cpu_0_data_master_granted_sysid_0_control_slave),
.cpu_0_data_master_qualified_request_sysid_0_control_slave (cpu_0_data_master_qualified_request_sysid_0_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sysid_0_control_slave (cpu_0_data_master_read_data_valid_sysid_0_control_slave),
.cpu_0_data_master_requests_sysid_0_control_slave (cpu_0_data_master_requests_sysid_0_control_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_sysid_0_control_slave_end_xfer (d1_sysid_0_control_slave_end_xfer),
.reset_n (clk_50_reset_n),
.sysid_0_control_slave_address (sysid_0_control_slave_address),
.sysid_0_control_slave_readdata (sysid_0_control_slave_readdata),
.sysid_0_control_slave_readdata_from_sa (sysid_0_control_slave_readdata_from_sa),
.sysid_0_control_slave_reset_n (sysid_0_control_slave_reset_n)
);
sysid_0 the_sysid_0
(
.address (sysid_0_control_slave_address),
.clock (sysid_0_control_slave_clock),
.readdata (sysid_0_control_slave_readdata),
.reset_n (sysid_0_control_slave_reset_n)
);
timer_s1_arbitrator the_timer_s1
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_timer_s1 (cpu_0_data_master_granted_timer_s1),
.cpu_0_data_master_qualified_request_timer_s1 (cpu_0_data_master_qualified_request_timer_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_timer_s1 (cpu_0_data_master_read_data_valid_timer_s1),
.cpu_0_data_master_requests_timer_s1 (cpu_0_data_master_requests_timer_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_timer_s1_end_xfer (d1_timer_s1_end_xfer),
.reset_n (clk_50_reset_n),
.timer_s1_address (timer_s1_address),
.timer_s1_chipselect (timer_s1_chipselect),
.timer_s1_irq (timer_s1_irq),
.timer_s1_irq_from_sa (timer_s1_irq_from_sa),
.timer_s1_readdata (timer_s1_readdata),
.timer_s1_readdata_from_sa (timer_s1_readdata_from_sa),
.timer_s1_reset_n (timer_s1_reset_n),
.timer_s1_write_n (timer_s1_write_n),
.timer_s1_writedata (timer_s1_writedata)
);
timer the_timer
(
.address (timer_s1_address),
.chipselect (timer_s1_chipselect),
.clk (clk_50),
.irq (timer_s1_irq),
.readdata (timer_s1_readdata),
.reset_n (timer_s1_reset_n),
.write_n (timer_s1_write_n),
.writedata (timer_s1_writedata)
);
tri_state_bridge_flash_avalon_slave_arbitrator the_tri_state_bridge_flash_avalon_slave
(
.cfi_flash_0_s1_wait_counter_eq_0 (cfi_flash_0_s1_wait_counter_eq_0),
.cfi_flash_0_s1_wait_counter_eq_1 (cfi_flash_0_s1_wait_counter_eq_1),
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_byteenable_cfi_flash_0_s1 (cpu_0_data_master_byteenable_cfi_flash_0_s1),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_cfi_flash_0_s1 (cpu_0_data_master_granted_cfi_flash_0_s1),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_cfi_flash_0_s1 (cpu_0_data_master_qualified_request_cfi_flash_0_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_cfi_flash_0_s1 (cpu_0_data_master_read_data_valid_cfi_flash_0_s1),
.cpu_0_data_master_requests_cfi_flash_0_s1 (cpu_0_data_master_requests_cfi_flash_0_s1),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_dbs_address (cpu_0_instruction_master_dbs_address),
.cpu_0_instruction_master_granted_cfi_flash_0_s1 (cpu_0_instruction_master_granted_cfi_flash_0_s1),
.cpu_0_instruction_master_latency_counter (cpu_0_instruction_master_latency_counter),
.cpu_0_instruction_master_qualified_request_cfi_flash_0_s1 (cpu_0_instruction_master_qualified_request_cfi_flash_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1 (cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1),
.cpu_0_instruction_master_requests_cfi_flash_0_s1 (cpu_0_instruction_master_requests_cfi_flash_0_s1),
.d1_tri_state_bridge_flash_avalon_slave_end_xfer (d1_tri_state_bridge_flash_avalon_slave_end_xfer),
.incoming_tri_state_bridge_flash_data (incoming_tri_state_bridge_flash_data),
.incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0 (incoming_tri_state_bridge_flash_data_with_Xs_converted_to_0),
.registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1),
.reset_n (clk_50_reset_n),
.select_n_to_the_cfi_flash_0 (select_n_to_the_cfi_flash_0),
.tri_state_bridge_flash_address (tri_state_bridge_flash_address),
.tri_state_bridge_flash_data (tri_state_bridge_flash_data),
.tri_state_bridge_flash_readn (tri_state_bridge_flash_readn),
.write_n_to_the_cfi_flash_0 (write_n_to_the_cfi_flash_0)
);
uart_s1_arbitrator the_uart_s1
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_uart_s1 (cpu_0_data_master_granted_uart_s1),
.cpu_0_data_master_qualified_request_uart_s1 (cpu_0_data_master_qualified_request_uart_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_uart_s1 (cpu_0_data_master_read_data_valid_uart_s1),
.cpu_0_data_master_requests_uart_s1 (cpu_0_data_master_requests_uart_s1),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_uart_s1_end_xfer (d1_uart_s1_end_xfer),
.reset_n (clk_50_reset_n),
.uart_s1_address (uart_s1_address),
.uart_s1_begintransfer (uart_s1_begintransfer),
.uart_s1_chipselect (uart_s1_chipselect),
.uart_s1_dataavailable (uart_s1_dataavailable),
.uart_s1_dataavailable_from_sa (uart_s1_dataavailable_from_sa),
.uart_s1_irq (uart_s1_irq),
.uart_s1_irq_from_sa (uart_s1_irq_from_sa),
.uart_s1_read_n (uart_s1_read_n),
.uart_s1_readdata (uart_s1_readdata),
.uart_s1_readdata_from_sa (uart_s1_readdata_from_sa),
.uart_s1_readyfordata (uart_s1_readyfordata),
.uart_s1_readyfordata_from_sa (uart_s1_readyfordata_from_sa),
.uart_s1_reset_n (uart_s1_reset_n),
.uart_s1_write_n (uart_s1_write_n),
.uart_s1_writedata (uart_s1_writedata)
);
uart the_uart
(
.address (uart_s1_address),
.begintransfer (uart_s1_begintransfer),
.chipselect (uart_s1_chipselect),
.clk (clk_50),
.dataavailable (uart_s1_dataavailable),
.irq (uart_s1_irq),
.read_n (uart_s1_read_n),
.readdata (uart_s1_readdata),
.readyfordata (uart_s1_readyfordata),
.reset_n (uart_s1_reset_n),
.rxd (rxd_to_the_uart),
.txd (txd_from_the_uart),
.write_n (uart_s1_write_n),
.writedata (uart_s1_writedata)
);
vga_0_avalon_slave_0_arbitrator the_vga_0_avalon_slave_0
(
.clk (clk_50),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_vga_0_avalon_slave_0 (cpu_0_data_master_granted_vga_0_avalon_slave_0),
.cpu_0_data_master_qualified_request_vga_0_avalon_slave_0 (cpu_0_data_master_qualified_request_vga_0_avalon_slave_0),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0 (cpu_0_data_master_read_data_valid_vga_0_avalon_slave_0),
.cpu_0_data_master_requests_vga_0_avalon_slave_0 (cpu_0_data_master_requests_vga_0_avalon_slave_0),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_vga_0_avalon_slave_0_end_xfer (d1_vga_0_avalon_slave_0_end_xfer),
.reset_n (clk_50_reset_n),
.vga_0_avalon_slave_0_address (vga_0_avalon_slave_0_address),
.vga_0_avalon_slave_0_chipselect (vga_0_avalon_slave_0_chipselect),
.vga_0_avalon_slave_0_read (vga_0_avalon_slave_0_read),
.vga_0_avalon_slave_0_readdata (vga_0_avalon_slave_0_readdata),
.vga_0_avalon_slave_0_readdata_from_sa (vga_0_avalon_slave_0_readdata_from_sa),
.vga_0_avalon_slave_0_reset_n (vga_0_avalon_slave_0_reset_n),
.vga_0_avalon_slave_0_wait_counter_eq_0 (vga_0_avalon_slave_0_wait_counter_eq_0),
.vga_0_avalon_slave_0_write (vga_0_avalon_slave_0_write),
.vga_0_avalon_slave_0_writedata (vga_0_avalon_slave_0_writedata)
);
vga_0 the_vga_0
(
.VGA_B (VGA_B_from_the_vga_0),
.VGA_BLANK (VGA_BLANK_from_the_vga_0),
.VGA_CLK (VGA_CLK_from_the_vga_0),
.VGA_G (VGA_G_from_the_vga_0),
.VGA_HS (VGA_HS_from_the_vga_0),
.VGA_R (VGA_R_from_the_vga_0),
.VGA_SYNC (VGA_SYNC_from_the_vga_0),
.VGA_VS (VGA_VS_from_the_vga_0),
.iADDR (vga_0_avalon_slave_0_address),
.iCLK (clk_50),
.iCLK_25 (iCLK_25_to_the_vga_0),
.iCS (vga_0_avalon_slave_0_chipselect),
.iDATA (vga_0_avalon_slave_0_writedata),
.iRD (vga_0_avalon_slave_0_read),
.iRST_N (vga_0_avalon_slave_0_reset_n),
.iWR (vga_0_avalon_slave_0_write),
.oDATA (vga_0_avalon_slave_0_readdata)
);
//reset is asserted asynchronously and deasserted synchronously
DE2_SoPC_reset_clk_50_domain_synch_module DE2_SoPC_reset_clk_50_domain_synch
(
.clk (clk_50),
.data_in (1'b1),
.data_out (clk_50_reset_n),
.reset_n (reset_n_sources)
);
//reset sources mux, which is an e_mux
assign reset_n_sources = ~(~reset_n |
0 |
cpu_0_jtag_debug_module_resetrequest_from_sa |
cpu_0_jtag_debug_module_resetrequest_from_sa);
//sysid_0_control_slave_clock of type clock does not connect to anything so wire it to default (0)
assign sysid_0_control_slave_clock = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cfi_flash_0_lane0_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 7: 0] q;
input [ 7: 0] data;
input [ 21: 0] rdaddress;
input rdclken;
input [ 21: 0] wraddress;
input wrclock;
input wren;
reg [ 7: 0] mem_array [4194303: 0];
wire [ 7: 0] q;
reg [ 21: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("cfi_flash_0.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "cfi_flash_0.mif",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 8,
// lpm_ram_dp_component.lpm_widthad = 22,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cfi_flash_0 (
// inputs:
address,
read_n,
select_n,
write_n,
// outputs:
data
)
;
inout [ 7: 0] data;
input [ 21: 0] address;
input read_n;
input select_n;
input write_n;
wire [ 7: 0] data;
wire [ 7: 0] data_0;
wire [ 7: 0] logic_vector_gasket;
wire [ 7: 0] q_0;
//s1, which is an e_ptf_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign logic_vector_gasket = data;
assign data_0 = logic_vector_gasket[7 : 0];
//cfi_flash_0_lane0, which is an e_ram
cfi_flash_0_lane0_module cfi_flash_0_lane0
(
.data (data_0),
.q (q_0),
.rdaddress (address),
.rdclken (1'b1),
.wraddress (address),
.wrclock (write_n),
.wren (~select_n)
);
assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
//synthesis translate_off
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above
// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif
`include "c:/altera/12.0/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/12.0/quartus/eda/sim_lib/220model.v"
`include "c:/altera/12.0/quartus/eda/sim_lib/sgate.v"
`include "ip/SRAM_16Bit_512K/hdl/SRAM_16Bit_512K.v"
`include "sram.v"
`include "ip/opencores_i2c/opencores_i2c.v"
`include "ip/opencores_i2c/i2c_master_bit_ctrl.v"
`include "ip/opencores_i2c/i2c_master_byte_ctrl.v"
`include "ip/opencores_i2c/i2c_master_defines.v"
`include "ip/opencores_i2c/i2c_master_top.v"
`include "ip/opencores_i2c/timescale.v"
`include "i2c.v"
`include "ip/Binary_VGA_Controller/hdl/Img_RAM.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_Controller.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v"
`include "ip/Binary_VGA_Controller/hdl/VGA_OSD_RAM.v"
`include "vga_0.v"
`include "uart.v"
`include "cpu_0_test_bench.v"
`include "cpu_0_mult_cell.v"
`include "cpu_0_oci_test_bench.v"
`include "cpu_0_jtag_debug_module_tck.v"
`include "cpu_0_jtag_debug_module_sysclk.v"
`include "cpu_0_jtag_debug_module_wrapper.v"
`include "cpu_0.v"
`include "timer.v"
`include "sysid_0.v"
`include "onchip_memory2.v"
`include "epcs.v"
`include "jtag_uart.v"
`include "lcd.v"
`timescale 1ns / 1ps
module test_bench
;
wire LCD_E_from_the_lcd;
wire LCD_RS_from_the_lcd;
wire LCD_RW_from_the_lcd;
wire [ 7: 0] LCD_data_to_and_from_the_lcd;
wire [ 17: 0] SRAM_ADDR_from_the_sram;
wire SRAM_CE_N_from_the_sram;
wire [ 15: 0] SRAM_DQ_to_and_from_the_sram;
wire SRAM_LB_N_from_the_sram;
wire SRAM_OE_N_from_the_sram;
wire SRAM_UB_N_from_the_sram;
wire SRAM_WE_N_from_the_sram;
wire VGA_BLANK_from_the_vga_0;
wire [ 9: 0] VGA_B_from_the_vga_0;
wire VGA_CLK_from_the_vga_0;
wire [ 9: 0] VGA_G_from_the_vga_0;
wire VGA_HS_from_the_vga_0;
wire [ 9: 0] VGA_R_from_the_vga_0;
wire VGA_SYNC_from_the_vga_0;
wire VGA_VS_from_the_vga_0;
wire clk;
reg clk_50;
wire epcs_epcs_control_port_dataavailable_from_sa;
wire epcs_epcs_control_port_endofpacket_from_sa;
wire epcs_epcs_control_port_readyfordata_from_sa;
wire iCLK_25_to_the_vga_0;
wire jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
reg reset_n;
wire rxd_to_the_uart;
wire scl_pad_io_to_and_from_the_i2c;
wire sda_pad_io_to_and_from_the_i2c;
wire select_n_to_the_cfi_flash_0;
wire sysid_0_control_slave_clock;
wire [ 21: 0] tri_state_bridge_flash_address;
wire [ 7: 0] tri_state_bridge_flash_data;
wire tri_state_bridge_flash_readn;
wire txd_from_the_uart;
wire uart_s1_dataavailable_from_sa;
wire uart_s1_readyfordata_from_sa;
wire write_n_to_the_cfi_flash_0;
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
//Set us up the Dut
DE2_SoPC DUT
(
.LCD_E_from_the_lcd (LCD_E_from_the_lcd),
.LCD_RS_from_the_lcd (LCD_RS_from_the_lcd),
.LCD_RW_from_the_lcd (LCD_RW_from_the_lcd),
.LCD_data_to_and_from_the_lcd (LCD_data_to_and_from_the_lcd),
.SRAM_ADDR_from_the_sram (SRAM_ADDR_from_the_sram),
.SRAM_CE_N_from_the_sram (SRAM_CE_N_from_the_sram),
.SRAM_DQ_to_and_from_the_sram (SRAM_DQ_to_and_from_the_sram),
.SRAM_LB_N_from_the_sram (SRAM_LB_N_from_the_sram),
.SRAM_OE_N_from_the_sram (SRAM_OE_N_from_the_sram),
.SRAM_UB_N_from_the_sram (SRAM_UB_N_from_the_sram),
.SRAM_WE_N_from_the_sram (SRAM_WE_N_from_the_sram),
.VGA_BLANK_from_the_vga_0 (VGA_BLANK_from_the_vga_0),
.VGA_B_from_the_vga_0 (VGA_B_from_the_vga_0),
.VGA_CLK_from_the_vga_0 (VGA_CLK_from_the_vga_0),
.VGA_G_from_the_vga_0 (VGA_G_from_the_vga_0),
.VGA_HS_from_the_vga_0 (VGA_HS_from_the_vga_0),
.VGA_R_from_the_vga_0 (VGA_R_from_the_vga_0),
.VGA_SYNC_from_the_vga_0 (VGA_SYNC_from_the_vga_0),
.VGA_VS_from_the_vga_0 (VGA_VS_from_the_vga_0),
.clk_50 (clk_50),
.iCLK_25_to_the_vga_0 (iCLK_25_to_the_vga_0),
.reset_n (reset_n),
.rxd_to_the_uart (rxd_to_the_uart),
.scl_pad_io_to_and_from_the_i2c (scl_pad_io_to_and_from_the_i2c),
.sda_pad_io_to_and_from_the_i2c (sda_pad_io_to_and_from_the_i2c),
.select_n_to_the_cfi_flash_0 (select_n_to_the_cfi_flash_0),
.tri_state_bridge_flash_address (tri_state_bridge_flash_address),
.tri_state_bridge_flash_data (tri_state_bridge_flash_data),
.tri_state_bridge_flash_readn (tri_state_bridge_flash_readn),
.txd_from_the_uart (txd_from_the_uart),
.write_n_to_the_cfi_flash_0 (write_n_to_the_cfi_flash_0)
);
cfi_flash_0 the_cfi_flash_0
(
.address (tri_state_bridge_flash_address),
.data (tri_state_bridge_flash_data),
.read_n (tri_state_bridge_flash_readn),
.select_n (select_n_to_the_cfi_flash_0),
.write_n (write_n_to_the_cfi_flash_0)
);
initial
clk_50 = 1'b0;
always
#10 clk_50 <= ~clk_50;
initial
begin
reset_n <= 0;
#200 reset_n <= 1;
end
endmodule
//synthesis translate_on
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02.10.2016 22:00:26
// Design Name:
// Module Name: dragsterCaptureUnit_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module linescanner_image_capture_unit_testbench;
reg
main_clock_source,
n_reset,
lval,
end_adc,
enable;
reg[7:0] data;
wire
main_clock,
rst_cvc,
rst_cds,
sample,
load_pulse,
pixel_captured,
pixel_clock;
wire[7:0] pixel_data;
linescanner_image_capture_unit l(
.enable,
.data,
.rst_cvc,
.rst_cds,
.sample,
.end_adc,
.lval,
.pixel_clock,
.main_clock_source,
.main_clock,
.n_reset,
.load_pulse,
.pixel_data,
.pixel_captured);
initial begin
enable <= 1'b1;
main_clock_source <= 1'b0;
lval <= 1'b0;
data <= 0;
end_adc <= 1'b0;
n_reset <= 1'b0;
#25 n_reset <= 1'b1;
#920 enable <= 1'b0;
#4000 enable <= 1'b1;
end
always #10 main_clock_source <= ~main_clock_source;
assign pixel_clock = main_clock;
always @ (negedge rst_cds) #160 end_adc <= 1'b1;
always @ (negedge sample) #120 end_adc <= 1'b0;
always @ (posedge load_pulse) begin
#1000 lval <= 1'b1;
data <= 255;
end
always @ (posedge lval) begin
#2000 lval <= 1'b0;
data <= 0;
end
endmodule
|
(* src = "../../verilog/extadc.v:1", top = 1 *)
module ExtADC (
(* intersynth_port = "Reset_n_i", src = "../../verilog/extadc.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/extadc.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/extadc.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/extadc.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:11" *)
output SensorPower_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:13" *)
output SensorStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "Inputs_i", src = "../../verilog/extadc.v:15" *)
input SensorReady_i,
(* intersynth_conntype = "Bit", intersynth_port = "AdcDoConvert_o", src = "../../verilog/extadc.v:17" *)
output AdcStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "AdcConvComplete_i", src = "../../verilog/extadc.v:19" *)
input AdcDone_i,
(* intersynth_conntype = "Word", intersynth_port = "AdcValue_i", src = "../../verilog/extadc.v:21" *)
input[15:0] AdcValue_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/extadc.v:23" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/extadc.v:25" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/extadc.v:27" *)
input[15:0] Threshold_i
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$extract$\AddSubCmp_Greater_Direct$728.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$extract$\AddSubCmp_Greater_Direct$728.Zero_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:14" *)
wire [15:0] \$extract$\Counter_RV1_Timer$725.D_s ;
(* src = "../../../../counter/verilog/counter_rv1.v:15" *)
wire \$extract$\Counter_RV1_Timer$725.Overflow_s ;
(* src = "../../verilog/extadc.v:167" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/extadc.v:43" *)
wire StoreNewValue;
(* src = "../../verilog/extadc.v:41" *)
wire TimerEnable;
(* src = "../../verilog/extadc.v:39" *)
wire TimerOvfl;
(* src = "../../verilog/extadc.v:40" *)
wire TimerPreset;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
AbsDiff \$extract$\AbsDiff$726 (
.A_i(AdcValue_i),
.B_i(SensorValue_o),
.D_o(AbsDiffResult)
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$extract$\AddSubCmp_Greater_Direct$728.ThisAddSubCmp (
.A_i(AbsDiffResult),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.D_o(\$extract$\AddSubCmp_Greater_Direct$728.D_s ),
.Overflow_o(\$extract$\AddSubCmp_Greater_Direct$728.Overflow_s ),
.Sign_o(\$extract$\AddSubCmp_Greater_Direct$728.Sign_s ),
.Zero_o(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s )
);
(* src = "../../../../counter/verilog/counter_rv1.v:20" *)
Counter \$extract$\Counter_RV1_Timer$725.ThisCounter (
.Clk_i(Clk_i),
.D_o(\$extract$\Counter_RV1_Timer$725.D_s ),
.Direction_i(1'b1),
.Enable_i(TimerEnable),
.Overflow_o(\$extract$\Counter_RV1_Timer$725.Overflow_s ),
.PresetVal_i(PeriodCounterPreset_i),
.Preset_i(TimerPreset),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(TimerOvfl)
);
WordRegister \$extract$\WordRegister$727 (
.Clk_i(Clk_i),
.D_i(AdcValue_i),
.Enable_i(StoreNewValue),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(AdcDone_i),
.In1_i(Enable_i),
.In2_i(SensorReady_i),
.In3_i(TimerOvfl),
.In4_i(\$extract$\AddSubCmp_Greater_Direct$728.Carry_s ),
.In5_i(\$extract$\AddSubCmp_Greater_Direct$728.Zero_s ),
.Out0_o(CpuIntr_o),
.Out1_o(SensorStart_o),
.Out2_o(StoreNewValue),
.Out3_o(AdcStart_o),
.Out4_o(SensorPower_o),
.Out5_o(TimerEnable),
.Out6_o(TimerPreset),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_PP_BLACKBOX_V
|
reg reset;
reg clock;
wire [7:0] fifo_data;
wire fifo_data_read;
wire fifo_data_start;
wire fifo_data_end;
reg fifo_data_available;
wire fifo_retry;
reg mode;
reg carrier_sense;
reg collision;
wire tx_enable;
wire [7:0] tx_data;
reg [7:0] tempdata;
reg expected_tx_enable;
tx_sm U_tx_sm(
.reset(reset),
.clock(clock),
.fifo_data(fifo_data),
.fifo_data_read(fifo_data_read),
.fifo_data_start(fifo_data_start),
.fifo_data_end(fifo_data_end),
.fifo_data_available(fifo_data_available),
.fifo_retry(fifo_retry),
.mode(mode),
.carrier_sense(carrier_sense),
.collision(collision),
.tx_enable(tx_enable),
.tx_data(tx_data)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
util (
.data_in(1'b0),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(clock)
);
utilities #(.OUT_WIDTH (8),
.IN_WIDTH (8))
data (
.data_in(tx_data),
.data_in_enable(),
.data_out(fifo_data),
.data_out_enable(),
.clock(clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_start (
.data_in(),
.data_in_enable(),
.data_out(fifo_data_start),
.data_out_enable(),
.clock(clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_end (
.data_in(),
.data_in_enable(),
.data_out(fifo_data_end),
.data_out_enable(),
.clock(clock)
);
monitor #(.WIDTH(1))
tx_enable_monitor(
.data(tx_enable),
.expected(expected_tx_enable),
.clock(clock));
initial
begin
clock = 0;
reset = 1;
mode = 1;
collision = 0;
carrier_sense = 0;
fifo_count = 0;
expected_tx_enable = 0;
end
always
#5 clock = ~clock;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_TB_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv3sd3.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv3sd3 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_HS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__buf (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUF_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DIODE_8_V
`define SKY130_FD_SC_HDLL__DIODE_8_V
/**
* diode: Antenna tie-down diode.
*
* Verilog wrapper for diode with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_8 (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__diode_8 (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__diode base (
.DIODE(DIODE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DIODE_8_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but free simulators won't let me do.
* So I put it in a module so as not to make other code unreadable.
*/
module hpdmc_iddr32 #(
parameter DDR_CLK_EDGE = "SAME_EDGE",
parameter INIT_Q1 = 1'b0,
parameter INIT_Q2 = 1'b0,
parameter SRTYPE = "SYNC"
) (
output [31:0] Q1,
output [31:0] Q2,
input C,
input CE,
input [31:0] D,
input R,
input S
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr0 (
.Q1(Q1[0]),
.Q2(Q2[0]),
.C(C),
.CE(CE),
.D(D[0]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr1 (
.Q1(Q1[1]),
.Q2(Q2[1]),
.C(C),
.CE(CE),
.D(D[1]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr2 (
.Q1(Q1[2]),
.Q2(Q2[2]),
.C(C),
.CE(CE),
.D(D[2]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr3 (
.Q1(Q1[3]),
.Q2(Q2[3]),
.C(C),
.CE(CE),
.D(D[3]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr4 (
.Q1(Q1[4]),
.Q2(Q2[4]),
.C(C),
.CE(CE),
.D(D[4]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr5 (
.Q1(Q1[5]),
.Q2(Q2[5]),
.C(C),
.CE(CE),
.D(D[5]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr6 (
.Q1(Q1[6]),
.Q2(Q2[6]),
.C(C),
.CE(CE),
.D(D[6]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr7 (
.Q1(Q1[7]),
.Q2(Q2[7]),
.C(C),
.CE(CE),
.D(D[7]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr8 (
.Q1(Q1[8]),
.Q2(Q2[8]),
.C(C),
.CE(CE),
.D(D[8]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr9 (
.Q1(Q1[9]),
.Q2(Q2[9]),
.C(C),
.CE(CE),
.D(D[9]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr10 (
.Q1(Q1[10]),
.Q2(Q2[10]),
.C(C),
.CE(CE),
.D(D[10]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr11 (
.Q1(Q1[11]),
.Q2(Q2[11]),
.C(C),
.CE(CE),
.D(D[11]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr12 (
.Q1(Q1[12]),
.Q2(Q2[12]),
.C(C),
.CE(CE),
.D(D[12]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr13 (
.Q1(Q1[13]),
.Q2(Q2[13]),
.C(C),
.CE(CE),
.D(D[13]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr14 (
.Q1(Q1[14]),
.Q2(Q2[14]),
.C(C),
.CE(CE),
.D(D[14]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr15 (
.Q1(Q1[15]),
.Q2(Q2[15]),
.C(C),
.CE(CE),
.D(D[15]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr16 (
.Q1(Q1[16]),
.Q2(Q2[16]),
.C(C),
.CE(CE),
.D(D[16]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr17 (
.Q1(Q1[17]),
.Q2(Q2[17]),
.C(C),
.CE(CE),
.D(D[17]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr18 (
.Q1(Q1[18]),
.Q2(Q2[18]),
.C(C),
.CE(CE),
.D(D[18]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr19 (
.Q1(Q1[19]),
.Q2(Q2[19]),
.C(C),
.CE(CE),
.D(D[19]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr20 (
.Q1(Q1[20]),
.Q2(Q2[20]),
.C(C),
.CE(CE),
.D(D[20]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr21 (
.Q1(Q1[21]),
.Q2(Q2[21]),
.C(C),
.CE(CE),
.D(D[21]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr22 (
.Q1(Q1[22]),
.Q2(Q2[22]),
.C(C),
.CE(CE),
.D(D[22]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr23 (
.Q1(Q1[23]),
.Q2(Q2[23]),
.C(C),
.CE(CE),
.D(D[23]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr24 (
.Q1(Q1[24]),
.Q2(Q2[24]),
.C(C),
.CE(CE),
.D(D[24]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr25 (
.Q1(Q1[25]),
.Q2(Q2[25]),
.C(C),
.CE(CE),
.D(D[25]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr26 (
.Q1(Q1[26]),
.Q2(Q2[26]),
.C(C),
.CE(CE),
.D(D[26]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr27 (
.Q1(Q1[27]),
.Q2(Q2[27]),
.C(C),
.CE(CE),
.D(D[27]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr28 (
.Q1(Q1[28]),
.Q2(Q2[28]),
.C(C),
.CE(CE),
.D(D[28]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr29 (
.Q1(Q1[29]),
.Q2(Q2[29]),
.C(C),
.CE(CE),
.D(D[29]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr30 (
.Q1(Q1[30]),
.Q2(Q2[30]),
.C(C),
.CE(CE),
.D(D[30]),
.R(R),
.S(S)
);
IDDR #(
.DDR_CLK_EDGE(DDR_CLK_EDGE),
.INIT_Q1(INIT_Q1),
.INIT_Q2(INIT_Q2),
.SRTYPE(SRTYPE)
) iddr31 (
.Q1(Q1[31]),
.Q2(Q2[31]),
.C(C),
.CE(CE),
.D(D[31]),
.R(R),
.S(S)
);
endmodule
|
`timescale 1ns / 1ns
module computer;
// Inputs
reg clk50;
reg rst;
reg RxD;
// Outputs
wire sram_sramEnable_o;
wire sram_writeEnable_o;
wire sram_readEnable_o;
wire [19:0] sram_addr_o;
wire flash_flashByte_o;
wire flash_flashVpen_o;
wire flash_flashRP_o;
wire flash_flashSTS_o;
wire flash_flashEnable_o;
wire flash_flashCE1_o;
wire flash_flashCE2_o;
wire flash_readEnable_o;
wire flash_writeEnable_o;
wire [22:0] flash_addr_o;
wire TxD;
// Bidirs
wire [31:0] sram_data_io;
wire [15:0] flash_data_io;
// Instantiate the Unit Under Test (UUT)
cpu Lx (
.clk50(clk50),
.rst(rst),
.sram_sramEnable_o(sram_sramEnable_o),
.sram_writeEnable_o(sram_writeEnable_o),
.sram_readEnable_o(sram_readEnable_o),
.sram_addr_o(sram_addr_o),
.sram_data_io(sram_data_io),
.flash_flashByte_o(flash_flashByte_o),
.flash_flashVpen_o(flash_flashVpen_o),
.flash_flashRP_o(flash_flashRP_o),
.flash_flashSTS_o(flash_flashSTS_o),
.flash_flashEnable_o(flash_flashEnable_o),
.flash_flashCE1_o(flash_flashCE1_o),
.flash_flashCE2_o(flash_flashCE2_o),
.flash_readEnable_o(flash_readEnable_o),
.flash_writeEnable_o(flash_writeEnable_o),
.flash_addr_o(flash_addr_o),
.flash_data_io(flash_data_io),
.RxD(RxD),
.TxD(TxD)
);
sram SRAM (
.addr_i(sram_addr_o),
.en_i(sram_sramEnable_o),
.oe_i(sram_readEnable_o),
.we_i(sram_writeEnable_o),
.data_io(sram_data_io)
);
initial begin
// Initialize Inputs
clk50 = 0;
rst = 0;
RxD = 1;
// Wait 100 ns for global reset to finish
#100 rst = 1;
// Add stimulus here
end
initial begin
forever #1 clk50 = ~clk50;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Samuel A. Falvo II
//
// Create Date: 17:14:59 10/29/2011
// Design Name: UXA 1A
// Module Name: M_uxa_ps2_shfreg
// Project Name: Kestrel-2
// Target Devices: Nexys2
// Tool versions:
// Description:
// Shift register which accepts PS/2 signal input and
// deserializes the bitstream into bytes.
//
// We discard the parity bit, on the assumption that
// modern equipment and cabling standards helps ensure
// proper reception.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module M_uxa_ps2_shfreg(
input ps2_d_i,
input ps2_c_i,
output [7:0] d_o,
output frame_o,
input reset_i,
input sys_clk_i
);
// The actual shift register sampling data on ps2_d_i.
reg [10:0] data;
// We want to sample the PS/2 data line on the rising edge
// of the PS/2 clock. We discover this event by ANDing the
// current ps2_c_i state with its immediately previously
// sampled value suitably inverted.
reg curr_ps2_c;
reg prev_ps2_c;
wire sample_evt = curr_ps2_c & ~prev_ps2_c;
// The d_o bus always reflects the state of the shift
// register's data sub-field.
assign d_o = data[8:1];
// We have proper framing when our start bit is 0 and
// our stop bit is 1.
reg frame;
assign frame_o = frame;
always @(posedge sys_clk_i) begin
if(!reset_i) begin
prev_ps2_c <= curr_ps2_c;
curr_ps2_c <= ps2_c_i;
if(sample_evt) data <= {ps2_d_i, data[10:1]};
else data <= data;
frame <= data[10] & (~data[0]);
end else begin
data <= 11'h7FF;
frame <= 0;
prev_ps2_c <= 1;
curr_ps2_c <= 1;
end
end
endmodule
|
/* Module from the schematic_gui program written by Andreas Ehliar <[email protected]>
This Verilog file is licensed under the CC0 license. */
module mux6 #(parameter WIREWIDTH = 1) (input wire [2:0] s,
input wire [WIREWIDTH:0] d0, d1, d2,d3, d4,d5,
output reg [WIREWIDTH:0] o);
initial begin
$schematic_boundingbox(40,280);
$schematic_polygonstart;
$schematic_coord(10,10);
$schematic_coord(30,30);
$schematic_coord(30,250);
$schematic_coord(10,270);
$schematic_polygonend;
$schematic_linestart;
$schematic_coord(20,19);
$schematic_coord(20,10);
$schematic_lineend;
$schematic_connector(d0,0,40);
$schematic_connector(d1,0,80);
$schematic_connector(d2,0,120);
$schematic_connector(d3,0,160);
$schematic_connector(d4,0,200);
$schematic_connector(d5,0,240);
$schematic_connector(o,40,140);
$schematic_connector(s,20,0);
$schematic_symboltext("0", 20,40);
$schematic_symboltext("1", 20,80);
$schematic_symboltext("2", 20,120);
$schematic_symboltext("3", 20,160);
$schematic_symboltext("4", 20,200);
$schematic_symboltext("5", 20,240);
end
always @* begin
case(s)
0: o = d0;
1: o = d1;
2: o = d2;
3: o = d3;
4: o = d4;
default: o = d5;
endcase
end
endmodule
|
/**
\file "inverters-backwards.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$from_prsim("in4", "TOP.out3"); // backwards -- OK
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$to_prsim("TOP.out", "out4"); // backwards -- diagnostic
end
initial #15 $finish;
/**
// optional: produce vector file for dump
initial begin
$dumpfile ("test.dump");
$dumpvars(0,TOP);
end
**/
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
`include "bsg_defines.v"
//
// Converts a wormhole router stream into a higher level protocol without
// deserializing the data. This module can be used for converting various
// DMA formats to wormhole flits efficently and with minimal buffering.
// It can also be used to forward data between wormholes on different
// networks, or to convert between multiple protocol formats.
//
// Example use cases:
// - bsg_cache {dma_pkt, data/v/yumi} format <-> wormhole
// - SRAM read/write <-> bsg_wormhole_stream_in/out <-> Wormhole Network
// - Wide Network <-> bsg_wormhole_stream_in/out <-> Narrow Network
//
// Assumptions:
// Usage of this module requires correctly formed wormhole headers. The length
// field of the wormhole message determines how many protocol data beats are
// expected (some multiple or divisor of the flit_width). We expect most
// link and protocol data widths to be powers of 2 (32, 64, 512), so this
// length restriction is lenient.
//
// - data width is a multiple of flit width (would be easy to add support)
// - header width is a multiple of flit width (would be more challenging)
// - header width == wormhole header width + protocol header width
// - wormhole packets are laid out like the following:
// ---------------------------------------------------------------
// | data | data | data | data | protocol info | len cord |
// ---------------------------------------------------------------
// - header flits do not contain any data
//
// Header will arrive at or before data and either can be acked at any time.
// Typical users of this module will simply ack the header to learn the
// protocol information of the impending transaction, begin the transaction,
// and then forward or accept all of the data serially.
//
module bsg_wormhole_stream_out
#(// The wormhole router protocol information
// flit_width_p: number of physical data wires between links
// cord_width_p: the width of the {y,x} coordinate of the destination
// len_width_p : the width of the length field, denoting #flits+1
// cid_width : the width of the concentrator id of the destination
// Default to 0 for cord and cid, so that this module can be used either
// for concentrator or router
parameter `BSG_INV_PARAM(flit_width_p)
, parameter cord_width_p = 0
, parameter `BSG_INV_PARAM(len_width_p)
, parameter cid_width_p = 0
// Higher level protocol information
, parameter `BSG_INV_PARAM(pr_hdr_width_p)
, parameter `BSG_INV_PARAM(pr_data_width_p)
, parameter `BSG_INV_PARAM(pr_len_width_p)
// Size of the wormhole header + the protocol header. The data starts afterwards.
// Users may set this directly rather than relying on the protocol header derived default
, parameter hdr_width_p = cord_width_p + len_width_p + cid_width_p + pr_hdr_width_p
)
(input clk_i
, input reset_i
// The output of a wormhole network
, input [flit_width_p-1:0] link_data_i
, input link_v_i
, output link_ready_and_o
// The wormhole and protocol header information
, output [hdr_width_p-1:0] hdr_o
, output hdr_v_o
, input hdr_ready_and_i
// number of protocol message data in arriving wormhole message
// arrives late when hdr_v_o & hdr_ready_and_i
// value is len-1 (i.e., zero based)
, input [pr_len_width_p-1:0] pr_data_beats_i
// The protocol data information
, output [pr_data_width_p-1:0] data_o
, output data_v_o
, input data_ready_and_i
);
wire is_hdr, is_data;
localparam [len_width_p-1:0] hdr_len_lp = `BSG_CDIV(hdr_width_p, flit_width_p);
logic hdr_v_li, hdr_ready_lo;
// Aggregate flits until we have a full header-worth of data, then let the
// client process it
assign hdr_v_li = is_hdr & link_v_i;
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p)
,.els_p(hdr_len_lp)
)
hdr_sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(hdr_v_li)
,.ready_and_o(hdr_ready_lo)
,.data_o(hdr_o)
,.v_o(hdr_v_o)
,.ready_and_i(hdr_ready_and_i)
);
logic data_v_li, data_ready_lo;
assign data_v_li = is_data & link_v_i;
// Protocol data is less than a single flit-sized. We accept a large
// wormhole flit, then let the client process it piecemeal
if (flit_width_p > pr_data_width_p)
begin : narrow
// flit_width_p > pr_data_width_p -> multiple protocol data per link flit
// and it is possible that last link flit is not completely filled with valid
// protocol data.
// number of protocol data per full link flit
localparam [len_width_p-1:0] max_els_lp = `BSG_CDIV(flit_width_p, pr_data_width_p);
localparam lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_lp);
// PISO len_i is zero-based, i.e., input is len-1
localparam [lg_max_els_lp-1:0] piso_full_len_lp = max_els_lp - 1;
// PISO inputs
logic piso_first_lo;
logic [lg_max_els_lp-1:0] piso_len_li;
// count of protocol data packets to consume after current
// set late when hdr_v_o & hdr_ready_i
// set value is provided by consumer, derived from output header
logic [pr_len_width_p-1:0] pr_data_cnt;
wire pr_data_consumed = (pr_data_cnt == '0);
bsg_counter_set_down
#(.width_p(pr_len_width_p)
,.init_val_p('0)
,.set_and_down_exclusive_p(0)
)
pr_data_counter
(.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(hdr_v_o & hdr_ready_and_i)
,.val_i(pr_data_beats_i)
,.down_i(data_v_o & data_ready_and_i & ~pr_data_consumed)
,.count_r_o(pr_data_cnt)
);
// for each PISO transaction, provide number of protocol data to expect
assign piso_len_li = (pr_data_cnt >= piso_full_len_lp)
? piso_full_len_lp
: lg_max_els_lp'(pr_data_cnt);
bsg_parallel_in_serial_out_passthrough_dynamic
#(.width_p(pr_data_width_p)
,.max_els_p(max_els_lp)
)
data_piso
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(data_v_li)
,.ready_and_o(data_ready_lo)
,.data_o(data_o)
,.v_o(data_v_o)
,.ready_and_i(data_ready_and_i)
,.first_o(piso_first_lo)
// must be presented when ready_and_i & first_o
,.len_i(piso_len_li)
);
end
else
// Protocol data is 1 or multiple flit-sized. We aggregate wormhole data
// until we have a full protocol data and then let the client process it
begin : wide
localparam [len_width_p-1:0] data_len_lp = `BSG_CDIV(pr_data_width_p, flit_width_p);
bsg_serial_in_parallel_out_passthrough
#(.width_p(flit_width_p)
,.els_p(data_len_lp)
)
data_sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_data_i)
,.v_i(data_v_li)
,.ready_and_o(data_ready_lo)
,.data_o(data_o)
,.v_o(data_v_o)
,.ready_and_i(data_ready_and_i)
);
end
// Identifies which flits are header vs data flits
bsg_wormhole_stream_control
#(.len_width_p(len_width_p)
,.hdr_len_p(hdr_len_lp)
)
stream_control
(.clk_i(clk_i)
,.reset_i(reset_i)
,.len_i(link_data_i[cord_width_p+:len_width_p])
,.link_accept_i(link_ready_and_o & link_v_i)
,.is_hdr_o(is_hdr)
,.is_data_o(is_data)
);
assign link_ready_and_o = is_hdr ? hdr_ready_lo : data_ready_lo;
//synopsys translate_off
if (hdr_width_p % flit_width_p != 0)
$fatal("Header width: %d must be multiple of flit width: %d", hdr_width_p, flit_width_p);
if ((pr_data_width_p % flit_width_p != 0) && (flit_width_p % pr_data_width_p != 0))
$fatal("Protocol data width: %d must be multiple of flit width: %d", pr_data_width_p, flit_width_p);
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_stream_out)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_TB_V
`define SKY130_FD_SC_LP__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
`define SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:39:51 03/23/2016
// Design Name:
// Module Name: compm4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Comparador de magnitudes de 4 bits.
module compm4(
input A0,
input A1,
input A2,
input A3,
input B0,
input B1,
input B2,
input B3,
output GT,
output LT
);
assign GT = {A3,A2,A1,A0} > {B3,B2,B1,B0};
assign LT = {A3,A2,A1,A0} < {B3,B2,B1,B0};
//assign GT = (A3&(~B3)) | ((~(A3^B3))&A2&(~B2)) | ((~(A3^B3))&(~(A2^B2))&A1&(~B1)) | ((~(A3^B3))&(~(A2^B2))&(~(A1^B1))&A0&(~B0));
//assign LT = ((~A3)&B3) | ((~(A3^B3))&(~A2)&B2) | ((~(A3^B3))&(~(A2^B2))&(~A1)&B1) | ((~(A3^B3))&(~(A2^B2))&(~(A1^B1))&(~A0)&B0);
endmodule
|
// diseño de una fifo ciclica, para implementar en cada bloque de proyecto
// ferney alberto beltran 2016 electrónica digital 1 universidad Nacional
module fifo
#(
parameter adr_width = 10,
parameter dat_width = 8
)
(
input clk_div, reset,
input wr,rd,
input [dat_width-1:0] data_in,
output [dat_width-1:0] data_out,
output empty,
output full
);
parameter depth = (1 << adr_width);
//declaración de registros
reg [dat_width-1:0] array_reg [depth-1:0];// register array FIFO
reg [adr_width-1:0] w_ptr_reg, w_ptr_next;
reg [adr_width-1:0] r_ptr_reg, r_ptr_next;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
assign data_out = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
assign full = full_reg;
assign empty = empty_reg;
always @(posedge clk_div) begin
if (wr_en)
array_reg[w_ptr_reg] <= data_in;
end
// fifo control logic
// register for read and write pointers
always @(posedge clk_div, posedge reset) begin
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
end
always @(*)
begin
if (reset) begin
w_ptr_next = 0;
r_ptr_next = 0;
end else begin
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_reg + 1;
full_next = 1'b0;
if (r_ptr_next==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_reg + 1;
empty_next = 1'b0;
if (w_ptr_next==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_reg + 1;
r_ptr_next = r_ptr_reg + 1;
end
endcase
end
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_win_change (clock, reset, enable, start_event, test_expr, end_event, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event;
input [width-1:0] test_expr;
input end_event;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_WIN_CHANGE";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_win_change_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_win_change_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_win_change_psl_logic.v"
`else
`endmodule // ovl_win_change
`endif
|
// Controller module
// Copyright 2010 University of Washington
// License: http://creativecommons.org/licenses/by/3.0/
// 2008 Dan Yeager
// This is the high level smarts of the RFID tag.
// It decides if and what to send upon a
// packet complete signal from the rx module.
// If we should transmit, it starts up the tx module
// and waits for it to indicate that it is finished.
// We also return a data select signal to the 'top' module
// which mux'es the epc, rn, and adc into the tx module.
// A couple features have been added for EPC compatibility
// 1. Handle persistence
// During a Write command, the reader asks for two successive
// req_rn's. The first is to be our handle. The second is the
// write data cover code. We store the handle as our current handle
// and this condition is kept in a reg tagisopen.
// For reference, see EPC spec - Annex K
//
// 2. Q-slotting for TDMA based on the rng
// Query, QueryAdj and QueryRep commands are used to manage
// the number of time slots. Query and QueryAdj load
// the slotcounter with Q bits of the RN from the rng.
// If slotcounter == 0, tag should TX its RN.
// QueryRep commands cause tag to decrement slotcounter.
// This feature is enabled via the use_q input.
// EPC spec - see Annex J
//
// 3. Unique ID
// Tags should have unique ID's (uid). However, the UID
// should not change in time unless the reader rewrites the ID.
// Ying's ID generator has unstable bits, which violates SPEC
// so we have another option to use a static ID.
// This feature is enabled via the use_uid input.
// use_uid=1 -> Ying's ID, use_uid=0 -> static ID
module controller (reset, clk, rx_overflow, rx_cmd, currentrn, currenthandle,
packet_complete, txsetupdone, tx_done,
rx_en, tx_en, docrc, handlematch,
bitsrcselect, readfrommsp, readwriteptr, rx_q, rx_updn,
use_uid, use_q, comm_enable);
parameter QUERYREP = 9'b000000001;
parameter ACK = 9'b000000010;
parameter QUERY = 9'b000000100;
parameter QUERYADJ = 9'b000001000;
parameter SELECT = 9'b000010000;
parameter NACK = 9'b000100000;
parameter REQRN = 9'b001000000;
parameter READ = 9'b010000000;
parameter WRITE = 9'b100000000;
parameter bitsrcselect_RNG = 2'd0;
parameter bitsrcselect_EPC = 2'd1;
parameter bitsrcselect_ADC = 2'd2;
parameter bitsrcselect_UID = 2'd3;
input reset, clk, rx_overflow, packet_complete, txsetupdone, tx_done;
input [8:0] rx_cmd;
input [15:0] currentrn;
output [15:0] currenthandle;
output rx_en, tx_en, docrc; // current_mode 0: rx mode, 1: tx mode
output [1:0] bitsrcselect;
input [7:0] readwriteptr;
output readfrommsp;
input use_uid, use_q;
input [3:0] rx_q;
input [2:0] rx_updn;
input handlematch, comm_enable;
reg [3:0] rx_q_reg;
reg readfrommsp;
reg [15:0] storedhandle;
reg [1:0] bitsrcselect;
reg docrc;
reg rx_en, tx_en;
reg commstate;
parameter STATE_RX = 1'b0;
parameter STATE_TX = 1'b1;
// See EPC spec Annex K
// First request RN sets our handle
// Second request RN sets the current cover code
// For write data
reg tagisopen;
assign currenthandle = tagisopen ? storedhandle : currentrn;
// Code to handle Q slotting for time-division multiplexing
// We TX our RN when slot counter == 0 for any of the following commands:
// They also have special behaviors:
// Query -> draw new rn, take Q bits of rn as init slot counter
// QueryAdj -> draw new rn, adjust stored Q value as per cmd,
// take Q bits of rn as init slot counter (like a query)
// QueryRep -> decrement existing slot counter value
reg [14:0] slotcounter;
// For query adjust, we will init slot counter based on q_adj
wire [3:0] q_adj, q_up, q_dn;
assign q_up = (rx_q_reg < 4'd15 && rx_updn[2] && rx_updn[1]) ? rx_q_reg + 4'd1 : rx_q_reg;
assign q_dn = (rx_q_reg > 4'd0 && rx_updn[0] && rx_updn[1]) ? rx_q_reg - 4'd1 : rx_q_reg;
assign q_adj = rx_updn[0] ? q_dn : q_up;
// For query, we init slot counter based on rx_q (from the parser module)
// This code takes Q bits of our rn as the new slot counter.
// If we get a query or queryAdj, the state machine will
// set slotcounter = newslotcounter as defined here:
wire [14:0] newslotcounter;
wire [3:0] q_ctl;
assign q_ctl = (rx_cmd == QUERY) ? rx_q : q_adj;
reg [14:0] slotcountermask;
always @ (q_ctl) begin
case(q_ctl)
0: slotcountermask = 15'b000000000000000;
1: slotcountermask = 15'b000000000000001;
2: slotcountermask = 15'b000000000000011;
3: slotcountermask = 15'b000000000000111;
4: slotcountermask = 15'b000000000001111;
5: slotcountermask = 15'b000000000011111;
6: slotcountermask = 15'b000000000111111;
7: slotcountermask = 15'b000000001111111;
8: slotcountermask = 15'b000000011111111;
9: slotcountermask = 15'b000000111111111;
10: slotcountermask = 15'b000001111111111;
11: slotcountermask = 15'b000011111111111;
12: slotcountermask = 15'b000111111111111;
13: slotcountermask = 15'b001111111111111;
14: slotcountermask = 15'b011111111111111;
15: slotcountermask = 15'b111111111111111;
default: slotcountermask = 15'b000000000000000;
endcase
end
assign newslotcounter = currentrn[14:0] & slotcountermask;
always @ (posedge clk or posedge reset) begin
if (reset) begin
commstate <= STATE_RX;
bitsrcselect <= 2'd0;
docrc <= 0;
tx_en <= 0;
rx_en <= 0;
tagisopen <= 0;
rx_q_reg <= 0;
slotcounter <= 0;
storedhandle <= 0;
readfrommsp <= 0;
end else if (commstate == STATE_TX) begin
if(txsetupdone) begin
rx_en <= 0;
end
if(tx_done) begin // tx_done
tx_en <= 0;
commstate <= STATE_RX;
end else begin
tx_en <= 1;
end
end else if (commstate == STATE_RX) begin // rx mode
if(packet_complete) begin
case (rx_cmd)
QUERYREP: begin
tagisopen <= 0;
slotcounter <= slotcounter - 15'd1;
if (comm_enable & ((slotcounter-15'd1)==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
ACK: begin
tagisopen <= 0;
if (comm_enable && handlematch) begin
commstate <= STATE_TX; // send ack.
bitsrcselect <= use_uid ? bitsrcselect_UID : bitsrcselect_EPC;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
QUERY: begin
tagisopen <= 0;
rx_q_reg <= rx_q;
// load slot counter
slotcounter <= newslotcounter;
if (comm_enable & (newslotcounter==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
QUERYADJ: begin
tagisopen <= 0;
rx_q_reg <= q_adj;
// load slot counter
slotcounter <= newslotcounter;
if (comm_enable & (newslotcounter==0 | ~use_q)) begin
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 0;
end else begin
rx_en <= 0; // reset rx
end
end
SELECT: begin
tagisopen <= 0;
rx_en <= 0; // reset rx
end
NACK: begin
tagisopen <= 0;
rx_en <= 0; // reset rx
end
REQRN: begin
if (comm_enable && handlematch) begin
// First request RN opens tag, sets handle
if (!tagisopen) begin
storedhandle <= currentrn;
tagisopen <= 1;
end
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_RNG;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
READ: begin
if (comm_enable && handlematch) begin
if (readwriteptr == 0) readfrommsp <= 0;
else readfrommsp <= 1;
commstate <= STATE_TX;
bitsrcselect <= bitsrcselect_ADC;
docrc <= 1;
end else begin
rx_en <= 0; // reset rx
end
end
WRITE: begin
rx_en <= 0; // reset rx
end
default begin
rx_en <= 0; // reset rx
end
endcase
end else if(rx_overflow) begin
rx_en <= 0;
end else begin
rx_en <= 1;
tx_en <= 0;
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ncio_prqq_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: PIO Control module
// Top level Module: jbi_ncio_prqq_ctl
// Where Instantiated: jbi_ncio
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ncio_prqq_ctl (/*AUTOARG*/
// Outputs
ncio_csr_write, ncio_csr_write_addr, ncio_csr_write_data,
ncio_csr_read_addr, ncio_csr_perf_pio_rd_out, ncio_csr_perf_pio_wr,
ncio_csr_perf_pio_rd_latency, pio_ucbp_req_acpted, ncio_pio_req,
ncio_pio_req_rw, ncio_pio_req_dest, ncio_pio_ue, ncio_pio_be,
ncio_pio_ad, ncio_yid, ncio_prqq_level, prqq_csn_wr, prqq_csn_rd,
prqq_waddr, prqq_wdata, prqq_raddr, prqq_ack, prqq_ack_thr_id,
prqq_ack_buf_id, prqq_rd16_thr_id, prqq_rd16_buf_id, prqq_stall_rd16,
// Inputs
clk, rst_l, csr_jbi_config2_max_pio, ucbp_rd_req_vld,
ucbp_wr_req_vld, ucbp_thr_id_in, ucbp_buf_id_in, ucbp_size_in,
ucbp_addr_in, ucbp_data_in, ucbp_ack_busy, mout_pio_pop,
mout_pio_req_adv, prqq_rdata, prtq_decr_rd_pend_cnt, prtq_rcv_rtrn16
);
input clk;
input rst_l;
// CSR Interface
input [3:0] csr_jbi_config2_max_pio;
output ncio_csr_write;
output [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_write_addr;
output [`JBI_CSR_WIDTH-1:0] ncio_csr_write_data;
output [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_read_addr;
output ncio_csr_perf_pio_rd_out;
output ncio_csr_perf_pio_wr;
output [4:0] ncio_csr_perf_pio_rd_latency;
// ucbp Interface.
input ucbp_rd_req_vld;
input ucbp_wr_req_vld;
input [`UCB_THR_HI-`UCB_THR_LO:0] ucbp_thr_id_in;
input [`UCB_BUF_HI-`UCB_BUF_LO:0] ucbp_buf_id_in;
input [`UCB_SIZE_HI-`UCB_SIZE_LO:0] ucbp_size_in;
input [`UCB_ADDR_HI-`UCB_ADDR_LO:0] ucbp_addr_in;
input [`UCB_DATA_HI-`UCB_DATA_LO:0] ucbp_data_in;
input ucbp_ack_busy;
output pio_ucbp_req_acpted;
// Memory Out (mout) Interface
input mout_pio_pop;
input mout_pio_req_adv;
output ncio_pio_req;
output ncio_pio_req_rw;
output [1:0] ncio_pio_req_dest;
output ncio_pio_ue;
output [15:0] ncio_pio_be;
output [63:0] ncio_pio_ad;
output [`JBI_YID_WIDTH-1:0] ncio_yid;
output [`JBI_PRQQ_ADDR_WIDTH:0] ncio_prqq_level;
//PRQQ Interface
input [`JBI_PRQQ_WIDTH-1:0] prqq_rdata;
output prqq_csn_wr;
output prqq_csn_rd;
output [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_waddr;
output [`JBI_PRQQ_WIDTH-1:0] prqq_wdata;
output [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_raddr;
// PIO Return Data Queue Interface
input prtq_decr_rd_pend_cnt;
input prtq_rcv_rtrn16; //eco6592
output prqq_ack;
output [`UCB_THR_HI-`UCB_THR_LO:0] prqq_ack_thr_id;
output [`UCB_BUF_HI-`UCB_BUF_LO:0] prqq_ack_buf_id;
output [`UCB_THR_HI-`UCB_THR_LO:0] prqq_rd16_thr_id; //eco6592
output [`UCB_BUF_HI-`UCB_BUF_LO:0] prqq_rd16_buf_id; //eco6592
output prqq_stall_rd16; //eco6592
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire ncio_csr_write;
wire [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_write_addr;
wire [`JBI_CSR_ADDR_WIDTH-1:0] ncio_csr_read_addr;
wire ncio_csr_perf_pio_rd_out;
wire ncio_csr_perf_pio_wr;
wire [4:0] ncio_csr_perf_pio_rd_latency;
wire pio_ucbp_req_acpted;
wire ncio_pio_req;
wire ncio_pio_req_rw;
wire [1:0] ncio_pio_req_dest;
wire ncio_pio_ue;
reg [15:0] ncio_pio_be;
wire [63:0] ncio_pio_ad;
wire [`JBI_YID_WIDTH-1:0] ncio_yid;
wire [`JBI_PRQQ_ADDR_WIDTH:0] ncio_prqq_level;
wire prqq_csn_wr;
wire prqq_csn_rd;
wire [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_waddr;
wire [`JBI_PRQQ_WIDTH-1:0] prqq_wdata;
wire [`JBI_PRQQ_ADDR_WIDTH-1:0] prqq_raddr;
wire prqq_ack;
wire [`UCB_THR_HI-`UCB_THR_LO:0] prqq_ack_thr_id;
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] prqq_ack_buf_id;
wire [`UCB_THR_HI-`UCB_THR_LO:0] prqq_rd16_thr_id; //eco6592
wire [`UCB_BUF_HI-`UCB_BUF_LO:0] prqq_rd16_buf_id; //eco6592
wire prqq_stall_rd16; //eco6592
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter PUSH_IDLE = 2'b00,
PUSH_HDR = 2'b01,
PUSH_DATA = 2'b10,
PUSH_HDR_BIT = 0,
PUSH_DATA_BIT = 1,
PUSH_SM_WIDTH = 2;
wire [PUSH_SM_WIDTH-1:0] push_sm;
wire [`JBI_PRQQ_ADDR_WIDTH:0] wptr;
wire [`JBI_PRQQ_ADDR_WIDTH:0] rptr;
wire [`JBI_PRQQ_ADDR_WIDTH:0] level;
wire [`JBI_PRQQ_ADDR_WIDTH:0] entry_wptr;
wire [`JBI_PRQQ_ADDR_WIDTH:0] entry_rptr;
wire [`JBI_PRQQ_DEPTH-1:0] entry_rw;
wire [`JBI_PRQQ_DEPTH-1:0] entry_dest0;
wire [`JBI_PRQQ_DEPTH-1:0] entry_dest1;
wire [`JBI_PRQQ_ADDR_WIDTH:0] rd_pend_cnt;
reg [PUSH_SM_WIDTH-1:0] next_push_sm;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_wptr;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_rptr;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_level;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_entry_wptr;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_entry_rptr;
reg [`JBI_PRQQ_DEPTH-1:0] next_entry_rw;
reg [`JBI_PRQQ_DEPTH-1:0] next_entry_dest0;
reg [`JBI_PRQQ_DEPTH-1:0] next_entry_dest1;
reg [`JBI_PRQQ_ADDR_WIDTH:0] next_rd_pend_cnt;
wire next_ncio_csr_perf_pio_rd_out;
wire next_ncio_csr_perf_pio_wr;
wire prqq_push;
reg [42:0] addr;
reg [63:0] data;
wire prqq_push_hdr;
wire prqq_push_data;
wire prqq_full;
wire [`UCB_SIZE_WIDTH-1:0] pio_size;
wire pio_dword;
wire pio_word;
reg [7:0] pre_be;
wire [7:0] shift_be;
wire incr_rd_pend_cnt;
wire stall_rd;
reg [1:0] dest;
wire [`JBI_PRQQ_ADDR_WIDTH:0] entry_wptr_d1;
wire csr_addr_match;
//eco6592
wire [`JBI_PRQQ_DEPTH-1:0] entry_dword;
reg [`JBI_PRQQ_DEPTH-1:0] next_entry_dword;
wire next_prqq_stall_rd16;
reg [`UCB_THR_HI-`UCB_THR_LO:0] next_prqq_rd16_thr_id;
reg [`UCB_BUF_HI-`UCB_BUF_LO:0] next_prqq_rd16_buf_id;
wire prqq_stall_rd16_rst_l;
wire pio_req_dword;
//
// Code start here
//
//*******************************************************************************
// Push Transaction into Request Queue
//*******************************************************************************
//-------------------
// Push State Machine
//-------------------
always @ ( /*AUTOSENSE*/csr_addr_match or prqq_full or push_sm
or ucbp_rd_req_vld or ucbp_wr_req_vld) begin
case (push_sm)
PUSH_IDLE: begin
if (~prqq_full
& ~csr_addr_match
& (ucbp_wr_req_vld | ucbp_rd_req_vld))
next_push_sm = PUSH_HDR;
else
next_push_sm = PUSH_IDLE;
end
PUSH_HDR: begin
if (ucbp_wr_req_vld)
next_push_sm = PUSH_DATA;
else
next_push_sm = PUSH_IDLE;
end
PUSH_DATA: next_push_sm = PUSH_IDLE;
// CoverMeter line_off
default: begin
next_push_sm = {PUSH_SM_WIDTH{1'bx}};
//synopsys translate_off
$dispmon ("jbi_ncio_prqq_ctl", 49,"%d %m: push_sm = %b", $time, push_sm);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
assign pio_ucbp_req_acpted = (push_sm[PUSH_HDR_BIT] & ~ucbp_wr_req_vld)
| push_sm[PUSH_DATA_BIT]
| (~ucbp_ack_busy & prqq_ack)
| (push_sm == PUSH_IDLE & ucbp_wr_req_vld & csr_addr_match);
//accept all writes; drop if appropriate
//-------------------
// Push Data
//-------------------
assign prqq_push_hdr = push_sm[PUSH_HDR_BIT] & ~csr_addr_match;
assign prqq_push_data = push_sm[PUSH_DATA_BIT];
assign prqq_push = prqq_push_hdr | prqq_push_data;
assign prqq_csn_wr = ~prqq_push;
always @ ( /*AUTOSENSE*/ucbp_addr_in) begin
if (ucbp_addr_in[39:32] == 8'h80) begin
if (ucbp_addr_in[31:28] == 4'h0) begin
addr[42:0] = { 15'h400_0, ucbp_addr_in[27:0]}; //ucbp_addr_in[39:24] == 16'h80_0E | 16'h80_0F
if (ucbp_addr_in[27:24] == 4'hE)
dest = `JBI_PRQQ_DEST_4;
else if (ucbp_addr_in[27:24] == 4'hF)
dest = `JBI_PRQQ_DEST_5;
else
dest = `JBI_PRQQ_DEST_OTH;
end
else begin
addr[42:0] = { 11'h600, ucbp_addr_in[31:0] }; //ucbp_addr_in[39:28] == 12'h80_1 to 12'h80_F
dest = `JBI_PRQQ_DEST_0;
end
end
else begin
addr[42:0] = { 3'h7, ucbp_addr_in[39:0] };
if (ucbp_addr_in[39:38] == 2'b11) begin //ucbp_addr_in[39:36] == 4'hC | 4'hD | 4'hE | 4'hF
if (ucbp_addr_in[37])
dest = `JBI_PRQQ_DEST_5;
else
dest = `JBI_PRQQ_DEST_4;
end
else
dest = `JBI_PRQQ_DEST_OTH; // all other unmapped
end
end
always @ ( /*AUTOSENSE*/addr or push_sm or ucbp_data_in) begin
if (push_sm[PUSH_DATA_BIT])
data = ucbp_data_in;
else
data = { {21{1'b0}}, addr[42:0] };
end
assign prqq_wdata[`JBI_PRQQ_D_HI:`JBI_PRQQ_D_LO] = data;
assign prqq_wdata[`JBI_PRQQ_THR_HI:`JBI_PRQQ_THR_LO] = ucbp_thr_id_in;
assign prqq_wdata[`JBI_PRQQ_BUF_HI:`JBI_PRQQ_BUF_LO] = ucbp_buf_id_in;
assign prqq_wdata[`JBI_PRQQ_DWORD] = ucbp_size_in == `UCB_SIZE_16B;
assign prqq_wdata[`JBI_PRQQ_WORD] = ucbp_addr_in[3];
assign prqq_wdata[`JBI_PRQQ_SZ_HI:`JBI_PRQQ_SZ_LO] = ucbp_size_in;
assign prqq_waddr = wptr[`JBI_PRQQ_ADDR_WIDTH-1:0];
//-------------------
// Pointer Management
//-------------------
always @ ( /*AUTOSENSE*/prqq_push or wptr) begin
if (prqq_push)
next_wptr = wptr + 1'b1;
else
next_wptr = wptr;
end
//-------------------
// Pointer Management
//-------------------
always @ ( /*AUTOSENSE*/level or mout_pio_pop or prqq_push) begin
case ({prqq_push, mout_pio_pop})
2'b00,
2'b11: next_level = level;
2'b01: next_level = level - 1'b1;
2'b10: next_level = level + 1'b1;
default: next_level = {`JBI_PRQQ_ADDR_WIDTH+1{1'bx}};
endcase
end
assign prqq_full = level > 5'd14;
assign ncio_prqq_level = level;
//-------------------
// CSR Management
//-------------------
assign csr_addr_match = ucbp_addr_in[39:24] == 16'h80_00;
assign ncio_csr_write = push_sm == PUSH_IDLE
& ucbp_wr_req_vld
& csr_addr_match;
assign ncio_csr_write_addr = ucbp_addr_in[`JBI_CSR_ADDR_WIDTH-1:0];
assign ncio_csr_write_data = ucbp_data_in[`JBI_CSR_WIDTH-1:0];
assign ncio_csr_read_addr = ucbp_addr_in[`JBI_CSR_ADDR_WIDTH-1:0];
// immediately request prtq to ack a csr read
assign prqq_ack = push_sm == PUSH_IDLE
& ucbp_rd_req_vld
& csr_addr_match;
assign prqq_ack_thr_id = ucbp_thr_id_in;
assign prqq_ack_buf_id = ucbp_buf_id_in;
//*******************************************************************************
// PIO Req
// - A separate JBI_PRQQ_DEPTHx2 array kepts track if the entry is a read or write,
// and destination. Logic steps thru each entry and determines
// if each entry is an "issue-able" transaction and conveys that info to mout.
// An entry is not "issue-able" if it is a read and the max number of outstanding
// PIO reads is reached. The logic will stall an unissueable read until it can be
// issued.
//*******************************************************************************
//-------------------
// Push
//-------------------
always @ ( /*AUTOSENSE*/entry_rw or entry_wptr or prqq_push_hdr
or ucbp_rd_req_vld) begin
next_entry_rw = entry_rw;
if (prqq_push_hdr)
next_entry_rw[entry_wptr[`JBI_PRQQ_ADDR_WIDTH-1:0]] = ucbp_rd_req_vld;
end
//eco6592
always @ ( /*AUTOSENSE*/entry_dword or entry_wptr or prqq_push_hdr
or prqq_wdata) begin
next_entry_dword = entry_dword;
if (prqq_push_hdr)
next_entry_dword[entry_wptr[`JBI_PRQQ_ADDR_WIDTH-1:0]] = prqq_wdata[`JBI_PRQQ_DWORD];
end
always @ ( /*AUTOSENSE*/dest or entry_dest0 or entry_wptr
or prqq_push_hdr) begin
next_entry_dest0 = entry_dest0;
if (prqq_push_hdr)
next_entry_dest0[entry_wptr[`JBI_PRQQ_ADDR_WIDTH-1:0]] = dest[0];
end
always @ ( /*AUTOSENSE*/dest or entry_dest1 or entry_wptr
or prqq_push_hdr) begin
next_entry_dest1 = entry_dest1;
if (prqq_push_hdr)
next_entry_dest1[entry_wptr[`JBI_PRQQ_ADDR_WIDTH-1:0]] = dest[1];
end
always @ ( /*AUTOSENSE*/entry_wptr or prqq_push_hdr) begin
if (prqq_push_hdr)
next_entry_wptr = entry_wptr + 1'b1;
else
next_entry_wptr = entry_wptr;
end
//-------------------
// Pop
//-------------------
always @ ( /*AUTOSENSE*/entry_rptr or mout_pio_req_adv) begin
if (mout_pio_req_adv) //advance to next txn
next_entry_rptr = entry_rptr + 1'b1;
else
next_entry_rptr = entry_rptr;
end
assign ncio_pio_req_rw = entry_rw[entry_rptr[`JBI_PRQQ_ADDR_WIDTH-1:0]];
assign ncio_pio_req_dest = { entry_dest1[entry_rptr[`JBI_PRQQ_ADDR_WIDTH-1:0]],
entry_dest0[entry_rptr[`JBI_PRQQ_ADDR_WIDTH-1:0]] };
assign pio_req_dword = entry_dword[entry_rptr[`JBI_PRQQ_ADDR_WIDTH-1:0]]; //eco6592
assign ncio_pio_req = entry_rptr != entry_wptr_d1
& ~(ncio_pio_req_rw
& (stall_rd
| (prqq_stall_rd16 & pio_req_dword))); //eco6592
//& ~(ncio_pio_req_rw & stall_rd);
//*******************************************************************************
// Pop Transaction from Request Queue
//*******************************************************************************
assign ncio_pio_ad = prqq_rdata[`JBI_PRQQ_D_HI:`JBI_PRQQ_D_LO];
assign ncio_yid = prqq_rdata[`JBI_PRQQ_YID_HI:`JBI_PRQQ_YID_LO];
assign ncio_pio_ue = 1'b0;
assign pio_size = prqq_rdata[`JBI_PRQQ_SZ_HI:`JBI_PRQQ_SZ_LO];
assign pio_dword = prqq_rdata[`JBI_PRQQ_DWORD];
assign pio_word = prqq_rdata[`JBI_PRQQ_WORD];
always @ ( /*AUTOSENSE*/pio_size) begin
case (pio_size)
`UCB_SIZE_1B: pre_be = 8'h01;
`UCB_SIZE_2B: pre_be = 8'h03;
`UCB_SIZE_4B: pre_be = 8'h0f;
default: pre_be = 8'hff;
endcase
end
assign shift_be = pre_be << ncio_pio_ad[2:0];
always @ ( /*AUTOSENSE*/pio_dword or pio_word or shift_be) begin
if (pio_dword)
ncio_pio_be = 16'hffff;
else begin
if (pio_word)
ncio_pio_be = {shift_be, 8'h00};
else
ncio_pio_be = {8'h00, shift_be};
end
end
//-------------------
// Pointer Management
//-------------------
always @ ( /*AUTOSENSE*/mout_pio_pop or rptr) begin
if (mout_pio_pop)
next_rptr = rptr + 1'b1;
else
next_rptr = rptr;
end
// account for 2 cycle delay in csn_wr assertion and propagation to rdata
//assign prqq_drdy = ~(rptr == wptr_d1);
//assign ncio_pio_req = prqq_drdy
// & ~(prtq_stall_pio_rd & ncio_pio_rw);
assign prqq_raddr = next_rptr[`JBI_PRQQ_ADDR_WIDTH-1:0];
assign prqq_csn_rd = next_rptr == wptr;
//*******************************************************************************
// Flow Control
// - must guarantee space for read returns
// - stall issuing reads if reached max outstanding pio reads
// - stall issuing 16-byte reads if one is already outstanding
//*******************************************************************************
assign incr_rd_pend_cnt = mout_pio_req_adv
& ncio_pio_req_rw;
always @ ( /*AUTOSENSE*/incr_rd_pend_cnt or prtq_decr_rd_pend_cnt
or rd_pend_cnt) begin
if (rd_pend_cnt == {`JBI_PRTQ_ADDR_WIDTH+1{1'b0}}
& prtq_decr_rd_pend_cnt)
next_rd_pend_cnt = rd_pend_cnt;
else begin
case ({incr_rd_pend_cnt, prtq_decr_rd_pend_cnt})
2'b00,
2'b11: next_rd_pend_cnt = rd_pend_cnt;
2'b01: next_rd_pend_cnt = rd_pend_cnt - 1'b1;
2'b10: next_rd_pend_cnt = rd_pend_cnt + 1'b1;
default: next_rd_pend_cnt = {`JBI_PRTQ_ADDR_WIDTH+1{1'bx}};
endcase
end
end
assign stall_rd = rd_pend_cnt > {1'b0, csr_jbi_config2_max_pio};
//eco6592
assign prqq_stall_rd16_rst_l = rst_l & ~(prqq_stall_rd16 & prtq_rcv_rtrn16);
assign next_prqq_stall_rd16 = (mout_pio_req_adv & pio_req_dword & ncio_pio_req_rw)
| prqq_stall_rd16;
always @ ( /*AUTOSENSE*/mout_pio_req_adv or ncio_pio_req_rw
or pio_req_dword or prqq_rd16_buf_id or prqq_rd16_thr_id
or prqq_rdata) begin
if (mout_pio_req_adv & pio_req_dword & ncio_pio_req_rw) begin
next_prqq_rd16_thr_id = prqq_rdata[`JBI_PRQQ_THR_HI:`JBI_PRQQ_THR_LO];
next_prqq_rd16_buf_id = prqq_rdata[`JBI_PRQQ_BUF_HI:`JBI_PRQQ_BUF_LO];
end
else begin
next_prqq_rd16_thr_id = prqq_rd16_thr_id;
next_prqq_rd16_buf_id = prqq_rd16_buf_id;
end
end
//*******************************************************************************
// Performance Counter
//*******************************************************************************
// PIO Read Transactions
assign next_ncio_csr_perf_pio_rd_out = mout_pio_req_adv & ncio_pio_req_rw;
// PIO Write Transactions
assign next_ncio_csr_perf_pio_wr = mout_pio_req_adv & ~ncio_pio_req_rw;
// PIO Read Latency
assign ncio_csr_perf_pio_rd_latency = rd_pend_cnt[4:0];
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dff_entry_wptr_d1
(.din(entry_wptr),
.clk(clk),
.q(entry_wptr_d1)
);
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
dffrl_ns #(PUSH_SM_WIDTH) u_dffrl_push_sm
(.din(next_push_sm),
.clk(clk),
.rst_l(rst_l),
.q(push_sm)
);
dffrl_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dffrl_wptr
(.din(next_wptr),
.clk(clk),
.rst_l(rst_l),
.q(wptr)
);
dffrl_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dffrl_rptr
(.din(next_rptr),
.clk(clk),
.rst_l(rst_l),
.q(rptr)
);
dffrl_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dffrl_level
(.din(next_level),
.clk(clk),
.rst_l(rst_l),
.q(level)
);
dffrl_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dffrl_entry_wptr
(.din(next_entry_wptr),
.clk(clk),
.rst_l(rst_l),
.q(entry_wptr)
);
dffrl_ns #(`JBI_PRQQ_ADDR_WIDTH+1) u_dffrl_entry_rptr
(.din(next_entry_rptr),
.clk(clk),
.rst_l(rst_l),
.q(entry_rptr)
);
dffrl_ns #(`JBI_PRQQ_DEPTH) u_dffrl_entry_rw
(.din(next_entry_rw),
.clk(clk),
.rst_l(rst_l),
.q(entry_rw)
);
dffrl_ns #(`JBI_PRQQ_DEPTH) u_dffrl_entry_dest0
(.din(next_entry_dest0),
.clk(clk),
.rst_l(rst_l),
.q(entry_dest0)
);
dffrl_ns #(`JBI_PRQQ_DEPTH) u_dffrl_entry_dest1
(.din(next_entry_dest1),
.clk(clk),
.rst_l(rst_l),
.q(entry_dest1)
);
dffrl_ns #(`JBI_PRTQ_ADDR_WIDTH+1) u_dffrl_rd_pend_cnt
(.din(next_rd_pend_cnt),
.clk(clk),
.rst_l(rst_l),
.q(rd_pend_cnt)
);
dffrl_ns #(1) u_dffrl_ncio_csr_perf_pio_rd_out
(.din(next_ncio_csr_perf_pio_rd_out),
.clk(clk),
.rst_l(rst_l),
.q(ncio_csr_perf_pio_rd_out)
);
dffrl_ns #(1) u_dffrl_ncio_csr_perf_pio_wr
(.din(next_ncio_csr_perf_pio_wr),
.clk(clk),
.rst_l(rst_l),
.q(ncio_csr_perf_pio_wr)
);
//eco6592
dffrl_ns #(`JBI_PRQQ_DEPTH) u_dffrl_entry_dword_eco6592
(.din(next_entry_dword),
.clk(clk),
.rst_l(rst_l),
.q(entry_dword)
);
dffrl_ns #(1) u_dffrl_prqq_stall_rd16_eco6592
(.din(next_prqq_stall_rd16),
.clk(clk),
.rst_l(prqq_stall_rd16_rst_l),
.q(prqq_stall_rd16)
);
dffrl_ns #(`UCB_THR_HI-`UCB_THR_LO+1) u_dffrl_prqq_rd16_thr_id_eco6592
(.din(next_prqq_rd16_thr_id),
.clk(clk),
.rst_l(rst_l),
.q(prqq_rd16_thr_id)
);
dffrl_ns #(`UCB_BUF_HI-`UCB_BUF_LO+1) u_dffrl_prqq_rd16_buf_id_eco6592
(.din(next_prqq_rd16_buf_id),
.clk(clk),
.rst_l(rst_l),
.q(prqq_rd16_buf_id)
);
//synopsys translate_off
//*******************************************************************************
// Rule Checks
//*******************************************************************************
wire rc_prqq_empty = rptr == wptr;
wire rc_prqq_full = wptr[`JBI_PRQQ_ADDR_WIDTH] != rptr[`JBI_PRQQ_ADDR_WIDTH]
& wptr[`JBI_PRQQ_ADDR_WIDTH-1:0] == rptr[`JBI_PRQQ_ADDR_WIDTH-1:0];
always @ ( /*AUTOSENSE*/prqq_push or rc_prqq_full) begin
@clk;
if (rc_prqq_full && prqq_push)
$dispmon ("jbi_ncio_prqq_ctl", 49,"%d %m: ERROR - PRQQ overflow!", $time);
end
always @ ( /*AUTOSENSE*/mout_pio_pop or rc_prqq_empty) begin
@clk;
if (rc_prqq_empty && mout_pio_pop)
$dispmon ("jbi_ncio_prqq_ctl", 49,"%d %m: ERROR - PRQQ underflow!", $time);
end
// account for 2 cycle delay in csn_wr assertion and propagation to rdata
reg [`JBI_PRQQ_ADDR_WIDTH:0] wptr_d1;
always @ (posedge clk) begin
wptr_d1 <= wptr;
end
wire rc_prqq_drdy = ~(rptr == wptr_d1);
always @ ( /*AUTOSENSE*/mout_pio_pop or rc_prqq_drdy) begin
@clk;
if (mout_pio_pop & ~rc_prqq_drdy)
$dispmon ("jbi_ncio_prqq_ctl", 49,"%d %m: ERROR - mout pops txn before data is ready", $time);
end
always @ ( /*AUTOSENSE*/push_sm or ucbp_addr_in or ucbp_rd_req_vld
or ucbp_wr_req_vld) begin
@clk;
if (push_sm == PUSH_IDLE
&& (ucbp_wr_req_vld || ucbp_rd_req_vld)
&& ( ( ucbp_addr_in[39:28] == 16'h80_0
&& ucbp_addr_in[27:24] != 4'h0
&& ucbp_addr_in[27:24] != 4'hE
&& ucbp_addr_in[27:24] != 4'hF)
|| ( ucbp_addr_in[39:32] != 8'h80
&& ucbp_addr_in[39:38] != 2'b11)
|| ucbp_addr_in[39:32] == 8'hFF ))
$dispmon ("jbi_ncio_prqq_ctl", 0,"%d %m: WARNING - IOB request to unexpected address 0x%x",
$time, ucbp_addr_in[39:0]);
end
always @ ( /*AUTOSENSE*/prtq_decr_rd_pend_cnt or rd_pend_cnt) begin
@clk;
if (rd_pend_cnt == 5'd0 & prtq_decr_rd_pend_cnt)
$dispmon ("jbi_ncio_prtq_ctl", 49,"%d %m: ERROR - PIO Read Pend Count underflow!", $time);
end
always @ ( /*AUTOSENSE*/incr_rd_pend_cnt or rd_pend_cnt) begin
@clk;
if (&rd_pend_cnt & incr_rd_pend_cnt)
$dispmon ("jbi_ncio_prtq_ctl", 49,"%d %m: ERROR - PIO Read Pend Count overflow!", $time);
end
//*******************************************************************************
// Event Coverage Signals
//*******************************************************************************
wire ec_entry_drdy = entry_rptr != entry_wptr_d1;
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Oct 20 23:55:19 2016
/////////////////////////////////////////////////////////////
module RegisterAdd_W1_8 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n5, n1, n2, n3;
DFFRXLTS Q_reg_0_ ( .D(n2), .CK(clk), .RN(n1), .Q(n5), .QN(n3) );
INVX2TS U2 ( .A(n3), .Y(Q[0]) );
OR2X1TS U3 ( .A(n5), .B(load), .Y(n2) );
INVX2TS U4 ( .A(rst), .Y(n1) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module RegisterAdd_W64_2 ( clk, rst, load, D, Q );
input [63:0] D;
output [63:0] Q;
input clk, rst, load;
wire n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93,
n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127,
n128, n129, n130, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19, n20, n21, n22;
DFFRXLTS Q_reg_63_ ( .D(n130), .CK(clk), .RN(n17), .Q(Q[63]) );
DFFRXLTS Q_reg_62_ ( .D(n128), .CK(clk), .RN(n22), .Q(Q[62]) );
DFFRXLTS Q_reg_61_ ( .D(n127), .CK(clk), .RN(n22), .Q(Q[61]) );
DFFRXLTS Q_reg_60_ ( .D(n126), .CK(clk), .RN(n22), .Q(Q[60]) );
DFFRXLTS Q_reg_59_ ( .D(n125), .CK(clk), .RN(n22), .Q(Q[59]) );
DFFRXLTS Q_reg_58_ ( .D(n124), .CK(clk), .RN(n21), .Q(Q[58]) );
DFFRXLTS Q_reg_57_ ( .D(n123), .CK(clk), .RN(n21), .Q(Q[57]) );
DFFRXLTS Q_reg_56_ ( .D(n122), .CK(clk), .RN(n21), .Q(Q[56]) );
DFFRXLTS Q_reg_55_ ( .D(n121), .CK(clk), .RN(n21), .Q(Q[55]) );
DFFRXLTS Q_reg_54_ ( .D(n120), .CK(clk), .RN(n21), .Q(Q[54]) );
DFFRXLTS Q_reg_53_ ( .D(n119), .CK(clk), .RN(n21), .Q(Q[53]) );
DFFRXLTS Q_reg_52_ ( .D(n118), .CK(clk), .RN(n21), .Q(Q[52]) );
DFFRXLTS Q_reg_51_ ( .D(n117), .CK(clk), .RN(n21), .Q(Q[51]) );
DFFRXLTS Q_reg_50_ ( .D(n116), .CK(clk), .RN(n21), .Q(Q[50]) );
DFFRXLTS Q_reg_49_ ( .D(n115), .CK(clk), .RN(n21), .Q(Q[49]) );
DFFRXLTS Q_reg_48_ ( .D(n114), .CK(clk), .RN(n20), .Q(Q[48]) );
DFFRXLTS Q_reg_47_ ( .D(n113), .CK(clk), .RN(n20), .Q(Q[47]) );
DFFRXLTS Q_reg_46_ ( .D(n112), .CK(clk), .RN(n20), .Q(Q[46]) );
DFFRXLTS Q_reg_45_ ( .D(n111), .CK(clk), .RN(n20), .Q(Q[45]) );
DFFRXLTS Q_reg_44_ ( .D(n110), .CK(clk), .RN(n20), .Q(Q[44]) );
DFFRXLTS Q_reg_43_ ( .D(n109), .CK(clk), .RN(n20), .Q(Q[43]) );
DFFRXLTS Q_reg_42_ ( .D(n108), .CK(clk), .RN(n20), .Q(Q[42]) );
DFFRXLTS Q_reg_41_ ( .D(n107), .CK(clk), .RN(n20), .Q(Q[41]) );
DFFRXLTS Q_reg_40_ ( .D(n106), .CK(clk), .RN(n20), .Q(Q[40]) );
DFFRXLTS Q_reg_39_ ( .D(n105), .CK(clk), .RN(n20), .Q(Q[39]) );
DFFRXLTS Q_reg_38_ ( .D(n104), .CK(clk), .RN(n22), .Q(Q[38]) );
DFFRXLTS Q_reg_37_ ( .D(n103), .CK(clk), .RN(n129), .Q(Q[37]) );
DFFRXLTS Q_reg_36_ ( .D(n102), .CK(clk), .RN(n129), .Q(Q[36]) );
DFFRXLTS Q_reg_35_ ( .D(n101), .CK(clk), .RN(n129), .Q(Q[35]) );
DFFRXLTS Q_reg_34_ ( .D(n100), .CK(clk), .RN(n129), .Q(Q[34]) );
DFFRXLTS Q_reg_33_ ( .D(n99), .CK(clk), .RN(n22), .Q(Q[33]) );
DFFRXLTS Q_reg_32_ ( .D(n98), .CK(clk), .RN(n22), .Q(Q[32]) );
DFFRXLTS Q_reg_31_ ( .D(n97), .CK(clk), .RN(n22), .Q(Q[31]) );
DFFRXLTS Q_reg_30_ ( .D(n96), .CK(clk), .RN(n22), .Q(Q[30]) );
DFFRXLTS Q_reg_29_ ( .D(n95), .CK(clk), .RN(n22), .Q(Q[29]) );
DFFRXLTS Q_reg_28_ ( .D(n94), .CK(clk), .RN(n19), .Q(Q[28]) );
DFFRXLTS Q_reg_27_ ( .D(n93), .CK(clk), .RN(n19), .Q(Q[27]) );
DFFRXLTS Q_reg_26_ ( .D(n92), .CK(clk), .RN(n19), .Q(Q[26]) );
DFFRXLTS Q_reg_25_ ( .D(n91), .CK(clk), .RN(n19), .Q(Q[25]) );
DFFRXLTS Q_reg_24_ ( .D(n90), .CK(clk), .RN(n19), .Q(Q[24]) );
DFFRXLTS Q_reg_23_ ( .D(n89), .CK(clk), .RN(n19), .Q(Q[23]) );
DFFRXLTS Q_reg_22_ ( .D(n88), .CK(clk), .RN(n19), .Q(Q[22]) );
DFFRXLTS Q_reg_21_ ( .D(n87), .CK(clk), .RN(n19), .Q(Q[21]) );
DFFRXLTS Q_reg_20_ ( .D(n86), .CK(clk), .RN(n19), .Q(Q[20]) );
DFFRXLTS Q_reg_19_ ( .D(n85), .CK(clk), .RN(n19), .Q(Q[19]) );
DFFRXLTS Q_reg_18_ ( .D(n84), .CK(clk), .RN(n18), .Q(Q[18]) );
DFFRXLTS Q_reg_17_ ( .D(n83), .CK(clk), .RN(n18), .Q(Q[17]) );
DFFRXLTS Q_reg_16_ ( .D(n82), .CK(clk), .RN(n18), .Q(Q[16]) );
DFFRXLTS Q_reg_15_ ( .D(n81), .CK(clk), .RN(n18), .Q(Q[15]) );
DFFRXLTS Q_reg_14_ ( .D(n80), .CK(clk), .RN(n18), .Q(Q[14]) );
DFFRXLTS Q_reg_13_ ( .D(n79), .CK(clk), .RN(n18), .Q(Q[13]) );
DFFRXLTS Q_reg_12_ ( .D(n78), .CK(clk), .RN(n18), .Q(Q[12]) );
DFFRXLTS Q_reg_11_ ( .D(n77), .CK(clk), .RN(n18), .Q(Q[11]) );
DFFRXLTS Q_reg_10_ ( .D(n76), .CK(clk), .RN(n18), .Q(Q[10]) );
DFFRXLTS Q_reg_9_ ( .D(n75), .CK(clk), .RN(n18), .Q(Q[9]) );
DFFRXLTS Q_reg_8_ ( .D(n74), .CK(clk), .RN(n17), .Q(Q[8]) );
DFFRXLTS Q_reg_7_ ( .D(n73), .CK(clk), .RN(n17), .Q(Q[7]) );
DFFRXLTS Q_reg_6_ ( .D(n72), .CK(clk), .RN(n17), .Q(Q[6]) );
DFFRXLTS Q_reg_5_ ( .D(n71), .CK(clk), .RN(n17), .Q(Q[5]) );
DFFRXLTS Q_reg_4_ ( .D(n70), .CK(clk), .RN(n17), .Q(Q[4]) );
DFFRXLTS Q_reg_3_ ( .D(n69), .CK(clk), .RN(n17), .Q(Q[3]) );
DFFRXLTS Q_reg_2_ ( .D(n68), .CK(clk), .RN(n17), .Q(Q[2]) );
DFFRXLTS Q_reg_1_ ( .D(n67), .CK(clk), .RN(n17), .Q(Q[1]) );
DFFRXLTS Q_reg_0_ ( .D(n66), .CK(clk), .RN(n17), .Q(Q[0]) );
AO22XLTS U2 ( .A0(n9), .A1(D[0]), .B0(n10), .B1(Q[0]), .Y(n66) );
AO22XLTS U3 ( .A0(n6), .A1(D[1]), .B0(n10), .B1(Q[1]), .Y(n67) );
AO22XLTS U4 ( .A0(n2), .A1(D[2]), .B0(n10), .B1(Q[2]), .Y(n68) );
AO22XLTS U5 ( .A0(n4), .A1(D[3]), .B0(n10), .B1(Q[3]), .Y(n69) );
AO22XLTS U6 ( .A0(n7), .A1(D[4]), .B0(n10), .B1(Q[4]), .Y(n70) );
AO22XLTS U7 ( .A0(n2), .A1(D[5]), .B0(n10), .B1(Q[5]), .Y(n71) );
AO22XLTS U8 ( .A0(n2), .A1(D[6]), .B0(n10), .B1(Q[6]), .Y(n72) );
AO22XLTS U9 ( .A0(n6), .A1(D[7]), .B0(n10), .B1(Q[7]), .Y(n73) );
AO22XLTS U10 ( .A0(n3), .A1(D[8]), .B0(n10), .B1(Q[8]), .Y(n74) );
AO22XLTS U11 ( .A0(n4), .A1(D[9]), .B0(n10), .B1(Q[9]), .Y(n75) );
AO22XLTS U12 ( .A0(n7), .A1(D[10]), .B0(n11), .B1(Q[10]), .Y(n76) );
AO22XLTS U13 ( .A0(n9), .A1(D[11]), .B0(n11), .B1(Q[11]), .Y(n77) );
AO22XLTS U14 ( .A0(n7), .A1(D[12]), .B0(n11), .B1(Q[12]), .Y(n78) );
AO22XLTS U15 ( .A0(n3), .A1(D[13]), .B0(n11), .B1(Q[13]), .Y(n79) );
AO22XLTS U16 ( .A0(n6), .A1(D[14]), .B0(n11), .B1(Q[14]), .Y(n80) );
AO22XLTS U17 ( .A0(n7), .A1(D[15]), .B0(n11), .B1(Q[15]), .Y(n81) );
AO22XLTS U18 ( .A0(n3), .A1(D[16]), .B0(n11), .B1(Q[16]), .Y(n82) );
AO22XLTS U19 ( .A0(n4), .A1(D[17]), .B0(n11), .B1(Q[17]), .Y(n83) );
AO22XLTS U20 ( .A0(n6), .A1(D[18]), .B0(n11), .B1(Q[18]), .Y(n84) );
AO22XLTS U21 ( .A0(n3), .A1(D[19]), .B0(n11), .B1(Q[19]), .Y(n85) );
AO22XLTS U22 ( .A0(n8), .A1(D[20]), .B0(n12), .B1(Q[20]), .Y(n86) );
AO22XLTS U23 ( .A0(n7), .A1(D[21]), .B0(n12), .B1(Q[21]), .Y(n87) );
AO22XLTS U24 ( .A0(n9), .A1(D[22]), .B0(n12), .B1(Q[22]), .Y(n88) );
AO22XLTS U25 ( .A0(n6), .A1(D[23]), .B0(n12), .B1(Q[23]), .Y(n89) );
AO22XLTS U26 ( .A0(n2), .A1(D[24]), .B0(n12), .B1(Q[24]), .Y(n90) );
AO22XLTS U27 ( .A0(n3), .A1(D[25]), .B0(n12), .B1(Q[25]), .Y(n91) );
AO22XLTS U28 ( .A0(n7), .A1(D[26]), .B0(n12), .B1(Q[26]), .Y(n92) );
AO22XLTS U29 ( .A0(n8), .A1(D[27]), .B0(n12), .B1(Q[27]), .Y(n93) );
AO22XLTS U30 ( .A0(n4), .A1(D[28]), .B0(n12), .B1(Q[28]), .Y(n94) );
AO22XLTS U31 ( .A0(n6), .A1(D[29]), .B0(n12), .B1(Q[29]), .Y(n95) );
AO22XLTS U32 ( .A0(n4), .A1(D[30]), .B0(n14), .B1(Q[30]), .Y(n96) );
AO22XLTS U33 ( .A0(n2), .A1(D[31]), .B0(n14), .B1(Q[31]), .Y(n97) );
AO22XLTS U34 ( .A0(n7), .A1(D[32]), .B0(n16), .B1(Q[32]), .Y(n98) );
AO22XLTS U35 ( .A0(n2), .A1(D[33]), .B0(n14), .B1(Q[33]), .Y(n99) );
AO22XLTS U36 ( .A0(n9), .A1(D[34]), .B0(n16), .B1(Q[34]), .Y(n100) );
AO22XLTS U37 ( .A0(n2), .A1(D[35]), .B0(n14), .B1(Q[35]), .Y(n101) );
AO22XLTS U38 ( .A0(n8), .A1(D[36]), .B0(n16), .B1(Q[36]), .Y(n102) );
AO22XLTS U39 ( .A0(n8), .A1(D[37]), .B0(n16), .B1(Q[37]), .Y(n103) );
AO22XLTS U40 ( .A0(n6), .A1(D[38]), .B0(n16), .B1(Q[38]), .Y(n104) );
AO22XLTS U41 ( .A0(n4), .A1(D[39]), .B0(n16), .B1(Q[39]), .Y(n105) );
AO22XLTS U42 ( .A0(n7), .A1(D[40]), .B0(n13), .B1(Q[40]), .Y(n106) );
AO22XLTS U43 ( .A0(n3), .A1(D[41]), .B0(n13), .B1(Q[41]), .Y(n107) );
AO22XLTS U44 ( .A0(n3), .A1(D[42]), .B0(n13), .B1(Q[42]), .Y(n108) );
AO22XLTS U45 ( .A0(n7), .A1(D[43]), .B0(n13), .B1(Q[43]), .Y(n109) );
AO22XLTS U46 ( .A0(n9), .A1(D[44]), .B0(n13), .B1(Q[44]), .Y(n110) );
AO22XLTS U47 ( .A0(n2), .A1(D[45]), .B0(n13), .B1(Q[45]), .Y(n111) );
AO22XLTS U48 ( .A0(n8), .A1(D[46]), .B0(n13), .B1(Q[46]), .Y(n112) );
AO22XLTS U49 ( .A0(n3), .A1(D[47]), .B0(n13), .B1(Q[47]), .Y(n113) );
AO22XLTS U50 ( .A0(n4), .A1(D[48]), .B0(n13), .B1(Q[48]), .Y(n114) );
AO22XLTS U51 ( .A0(n4), .A1(D[49]), .B0(n13), .B1(Q[49]), .Y(n115) );
AO22XLTS U52 ( .A0(n6), .A1(D[50]), .B0(n15), .B1(Q[50]), .Y(n116) );
AO22XLTS U53 ( .A0(n8), .A1(D[51]), .B0(n15), .B1(Q[51]), .Y(n117) );
AO22XLTS U54 ( .A0(n8), .A1(D[52]), .B0(n15), .B1(Q[52]), .Y(n118) );
AO22XLTS U55 ( .A0(n7), .A1(D[53]), .B0(n15), .B1(Q[53]), .Y(n119) );
AO22XLTS U56 ( .A0(n6), .A1(D[54]), .B0(n15), .B1(Q[54]), .Y(n120) );
AO22XLTS U57 ( .A0(n4), .A1(D[55]), .B0(n15), .B1(Q[55]), .Y(n121) );
AO22XLTS U58 ( .A0(n3), .A1(D[56]), .B0(n15), .B1(Q[56]), .Y(n122) );
AO22XLTS U59 ( .A0(n6), .A1(D[57]), .B0(n15), .B1(Q[57]), .Y(n123) );
AO22XLTS U60 ( .A0(n8), .A1(D[58]), .B0(n15), .B1(Q[58]), .Y(n124) );
AO22XLTS U61 ( .A0(n8), .A1(D[59]), .B0(n15), .B1(Q[59]), .Y(n125) );
AO22XLTS U62 ( .A0(n2), .A1(D[60]), .B0(n16), .B1(Q[60]), .Y(n126) );
AO22XLTS U63 ( .A0(n9), .A1(D[61]), .B0(n16), .B1(Q[61]), .Y(n127) );
AO22XLTS U64 ( .A0(n2), .A1(D[62]), .B0(n16), .B1(Q[62]), .Y(n128) );
AO22XLTS U65 ( .A0(n9), .A1(D[63]), .B0(n16), .B1(Q[63]), .Y(n130) );
INVX2TS U66 ( .A(n5), .Y(n2) );
INVX2TS U67 ( .A(n5), .Y(n3) );
INVX2TS U68 ( .A(n5), .Y(n4) );
INVX2TS U69 ( .A(load), .Y(n5) );
INVX2TS U70 ( .A(n5), .Y(n6) );
INVX2TS U71 ( .A(n5), .Y(n7) );
INVX2TS U72 ( .A(n5), .Y(n8) );
INVX2TS U73 ( .A(n5), .Y(n9) );
INVX2TS U74 ( .A(rst), .Y(n129) );
CLKBUFX2TS U75 ( .A(n129), .Y(n17) );
CLKBUFX2TS U76 ( .A(n129), .Y(n18) );
CLKBUFX2TS U77 ( .A(n129), .Y(n19) );
CLKBUFX2TS U78 ( .A(n129), .Y(n20) );
CLKBUFX2TS U79 ( .A(n129), .Y(n21) );
CLKBUFX2TS U80 ( .A(n129), .Y(n22) );
INVX2TS U81 ( .A(n9), .Y(n14) );
CLKBUFX2TS U82 ( .A(n14), .Y(n10) );
CLKBUFX2TS U83 ( .A(n14), .Y(n11) );
CLKBUFX2TS U84 ( .A(n14), .Y(n12) );
CLKBUFX2TS U85 ( .A(n14), .Y(n16) );
CLKBUFX2TS U86 ( .A(n14), .Y(n13) );
CLKBUFX2TS U87 ( .A(n14), .Y(n15) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module RegisterAdd_W1_1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4, n2;
DFFRXLTS Q_reg_0_ ( .D(n4), .CK(clk), .RN(n3), .Q(Q[0]) );
AO22XLTS U2 ( .A0(n2), .A1(Q[0]), .B0(load), .B1(D[0]), .Y(n4) );
INVX2TS U3 ( .A(rst), .Y(n3) );
INVX2TS U4 ( .A(load), .Y(n2) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Multiplexer_AC_W11_1 ( ctrl, D0, D1, S );
input [10:0] D0;
input [10:0] D1;
output [10:0] S;
input ctrl;
wire n1, n2, n3;
AO22XLTS U1 ( .A0(ctrl), .A1(D1[0]), .B0(n2), .B1(D0[0]), .Y(S[0]) );
AO22XLTS U2 ( .A0(n1), .A1(D1[9]), .B0(n3), .B1(D0[9]), .Y(S[9]) );
AO22XLTS U3 ( .A0(ctrl), .A1(D1[7]), .B0(n3), .B1(D0[7]), .Y(S[7]) );
AO22XLTS U4 ( .A0(ctrl), .A1(D1[5]), .B0(n3), .B1(D0[5]), .Y(S[5]) );
AO22XLTS U5 ( .A0(n1), .A1(D1[10]), .B0(n2), .B1(D0[10]), .Y(S[10]) );
AO22XLTS U6 ( .A0(ctrl), .A1(D1[8]), .B0(n2), .B1(D0[8]), .Y(S[8]) );
AO22XLTS U7 ( .A0(ctrl), .A1(D1[6]), .B0(n2), .B1(D0[6]), .Y(S[6]) );
AO22XLTS U8 ( .A0(ctrl), .A1(D1[4]), .B0(n2), .B1(D0[4]), .Y(S[4]) );
AO22XLTS U9 ( .A0(ctrl), .A1(D1[2]), .B0(n2), .B1(D0[2]), .Y(S[2]) );
AO22XLTS U10 ( .A0(ctrl), .A1(D1[3]), .B0(n3), .B1(D0[3]), .Y(S[3]) );
AO22XLTS U11 ( .A0(ctrl), .A1(D1[1]), .B0(n2), .B1(D0[1]), .Y(S[1]) );
INVX2TS U12 ( .A(n3), .Y(n1) );
INVX2TS U13 ( .A(n1), .Y(n2) );
INVX2TS U14 ( .A(ctrl), .Y(n3) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Mux_3x1_W11 ( ctrl, D0, D1, D2, S );
input [1:0] ctrl;
input [10:0] D0;
input [10:0] D1;
input [10:0] D2;
output [10:0] S;
wire n17, n18, n19;
AO22XLTS U2 ( .A0(n19), .A1(D1[5]), .B0(n18), .B1(D0[5]), .Y(S[5]) );
AO22XLTS U3 ( .A0(n19), .A1(D1[4]), .B0(n18), .B1(D0[4]), .Y(S[4]) );
AO22XLTS U4 ( .A0(n19), .A1(D1[2]), .B0(n18), .B1(D0[2]), .Y(S[2]) );
NOR2XLTS U5 ( .A(ctrl[0]), .B(ctrl[1]), .Y(n18) );
AO22XLTS U6 ( .A0(n19), .A1(D1[3]), .B0(n18), .B1(D0[3]), .Y(S[3]) );
AO22XLTS U7 ( .A0(n19), .A1(D1[1]), .B0(n18), .B1(D0[1]), .Y(S[1]) );
CLKAND2X2TS U8 ( .A(n18), .B(D0[6]), .Y(S[6]) );
CLKAND2X2TS U9 ( .A(n18), .B(D0[7]), .Y(S[7]) );
CLKAND2X2TS U10 ( .A(n18), .B(D0[8]), .Y(S[8]) );
CLKAND2X2TS U11 ( .A(n18), .B(D0[9]), .Y(S[9]) );
CLKAND2X2TS U12 ( .A(n18), .B(D0[10]), .Y(S[10]) );
NOR2XLTS U13 ( .A(ctrl[1]), .B(D0[0]), .Y(n17) );
NOR2BX1TS U14 ( .AN(ctrl[0]), .B(ctrl[1]), .Y(n19) );
OAI2BB2XLTS U15 ( .B0(ctrl[0]), .B1(n17), .A0N(D1[0]), .A1N(n19), .Y(S[0])
);
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Exp_Operation_EW11 ( clk, rst, load_a_i, load_b_i, Data_A_i, Data_B_i,
Add_Subt_i, Data_Result_o, Overflow_flag_o, Underflow_flag_o );
input [10:0] Data_A_i;
input [10:0] Data_B_i;
output [10:0] Data_Result_o;
input clk, rst, load_a_i, load_b_i, Add_Subt_i;
output Overflow_flag_o, Underflow_flag_o;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
DP_OP_11J2_122_2824_n26, DP_OP_11J2_122_2824_n25,
DP_OP_11J2_122_2824_n24, DP_OP_11J2_122_2824_n23,
DP_OP_11J2_122_2824_n22, DP_OP_11J2_122_2824_n21,
DP_OP_11J2_122_2824_n20, DP_OP_11J2_122_2824_n19,
DP_OP_11J2_122_2824_n18, DP_OP_11J2_122_2824_n17,
DP_OP_11J2_122_2824_n16, DP_OP_11J2_122_2824_n11,
DP_OP_11J2_122_2824_n10, DP_OP_11J2_122_2824_n9,
DP_OP_11J2_122_2824_n8, DP_OP_11J2_122_2824_n7,
DP_OP_11J2_122_2824_n6, DP_OP_11J2_122_2824_n5,
DP_OP_11J2_122_2824_n4, DP_OP_11J2_122_2824_n3,
DP_OP_11J2_122_2824_n2, DP_OP_11J2_122_2824_n1, n1, n2, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32;
wire [10:0] Data_S;
DFFRXLTS exp_result_Q_reg_0_ ( .D(n16), .CK(clk), .RN(n15), .Q(
Data_Result_o[0]) );
DFFRXLTS exp_result_Q_reg_1_ ( .D(n14), .CK(clk), .RN(n18), .Q(
Data_Result_o[1]) );
DFFRXLTS exp_result_Q_reg_2_ ( .D(n13), .CK(clk), .RN(n15), .Q(
Data_Result_o[2]) );
DFFRXLTS exp_result_Q_reg_3_ ( .D(n12), .CK(clk), .RN(n18), .Q(
Data_Result_o[3]) );
DFFRXLTS exp_result_Q_reg_4_ ( .D(n11), .CK(clk), .RN(n15), .Q(
Data_Result_o[4]) );
DFFRXLTS exp_result_Q_reg_5_ ( .D(n10), .CK(clk), .RN(n18), .Q(
Data_Result_o[5]) );
DFFRXLTS exp_result_Q_reg_6_ ( .D(n9), .CK(clk), .RN(n15), .Q(
Data_Result_o[6]) );
DFFRXLTS exp_result_Q_reg_7_ ( .D(n8), .CK(clk), .RN(n18), .Q(
Data_Result_o[7]) );
DFFRXLTS exp_result_Q_reg_8_ ( .D(n7), .CK(clk), .RN(n15), .Q(
Data_Result_o[8]) );
DFFRXLTS exp_result_Q_reg_9_ ( .D(n6), .CK(clk), .RN(n18), .Q(
Data_Result_o[9]) );
DFFRXLTS exp_result_Q_reg_10_ ( .D(n5), .CK(clk), .RN(n15), .Q(
Data_Result_o[10]) );
CMPR32X2TS DP_OP_11J2_122_2824_U12 ( .A(Data_A_i[0]), .B(Add_Subt_i), .C(
DP_OP_11J2_122_2824_n26), .CO(DP_OP_11J2_122_2824_n11), .S(Data_S[0])
);
CMPR32X2TS DP_OP_11J2_122_2824_U11 ( .A(DP_OP_11J2_122_2824_n25), .B(
Data_A_i[1]), .C(DP_OP_11J2_122_2824_n11), .CO(DP_OP_11J2_122_2824_n10), .S(Data_S[1]) );
CMPR32X2TS DP_OP_11J2_122_2824_U10 ( .A(DP_OP_11J2_122_2824_n24), .B(
Data_A_i[2]), .C(DP_OP_11J2_122_2824_n10), .CO(DP_OP_11J2_122_2824_n9),
.S(Data_S[2]) );
CMPR32X2TS DP_OP_11J2_122_2824_U9 ( .A(DP_OP_11J2_122_2824_n23), .B(
Data_A_i[3]), .C(DP_OP_11J2_122_2824_n9), .CO(DP_OP_11J2_122_2824_n8),
.S(Data_S[3]) );
CMPR32X2TS DP_OP_11J2_122_2824_U8 ( .A(DP_OP_11J2_122_2824_n22), .B(
Data_A_i[4]), .C(DP_OP_11J2_122_2824_n8), .CO(DP_OP_11J2_122_2824_n7),
.S(Data_S[4]) );
CMPR32X2TS DP_OP_11J2_122_2824_U7 ( .A(DP_OP_11J2_122_2824_n21), .B(
Data_A_i[5]), .C(DP_OP_11J2_122_2824_n7), .CO(DP_OP_11J2_122_2824_n6),
.S(Data_S[5]) );
CMPR32X2TS DP_OP_11J2_122_2824_U6 ( .A(DP_OP_11J2_122_2824_n20), .B(
Data_A_i[6]), .C(DP_OP_11J2_122_2824_n6), .CO(DP_OP_11J2_122_2824_n5),
.S(Data_S[6]) );
CMPR32X2TS DP_OP_11J2_122_2824_U5 ( .A(DP_OP_11J2_122_2824_n19), .B(
Data_A_i[7]), .C(DP_OP_11J2_122_2824_n5), .CO(DP_OP_11J2_122_2824_n4),
.S(Data_S[7]) );
CMPR32X2TS DP_OP_11J2_122_2824_U4 ( .A(DP_OP_11J2_122_2824_n18), .B(
Data_A_i[8]), .C(DP_OP_11J2_122_2824_n4), .CO(DP_OP_11J2_122_2824_n3),
.S(Data_S[8]) );
CMPR32X2TS DP_OP_11J2_122_2824_U3 ( .A(DP_OP_11J2_122_2824_n17), .B(
Data_A_i[9]), .C(DP_OP_11J2_122_2824_n3), .CO(DP_OP_11J2_122_2824_n2),
.S(Data_S[9]) );
CMPR32X2TS DP_OP_11J2_122_2824_U2 ( .A(DP_OP_11J2_122_2824_n16), .B(
Data_A_i[10]), .C(DP_OP_11J2_122_2824_n2), .CO(DP_OP_11J2_122_2824_n1),
.S(Data_S[10]) );
DFFRXLTS Underflow_Q_reg_0_ ( .D(n4), .CK(clk), .RN(n18), .Q(
Underflow_flag_o) );
DFFRXLTS Overflow_Q_reg_0_ ( .D(n3), .CK(clk), .RN(n15), .Q(Overflow_flag_o)
);
NOR4BXLTS U1 ( .AN(load_b_i), .B(Data_S[2]), .C(Data_S[1]), .D(Data_S[0]),
.Y(n25) );
XOR2XLTS U2 ( .A(Add_Subt_i), .B(Data_B_i[0]), .Y(DP_OP_11J2_122_2824_n26)
);
XOR2XLTS U3 ( .A(DP_OP_11J2_122_2824_n1), .B(Add_Subt_i), .Y(n27) );
XOR2XLTS U4 ( .A(Add_Subt_i), .B(Data_B_i[5]), .Y(DP_OP_11J2_122_2824_n21)
);
XOR2XLTS U5 ( .A(Add_Subt_i), .B(Data_B_i[10]), .Y(DP_OP_11J2_122_2824_n16)
);
XOR2XLTS U6 ( .A(Add_Subt_i), .B(Data_B_i[4]), .Y(DP_OP_11J2_122_2824_n22)
);
XOR2XLTS U7 ( .A(Add_Subt_i), .B(Data_B_i[2]), .Y(DP_OP_11J2_122_2824_n24)
);
XOR2XLTS U8 ( .A(Add_Subt_i), .B(Data_B_i[3]), .Y(DP_OP_11J2_122_2824_n23)
);
XOR2XLTS U9 ( .A(Add_Subt_i), .B(Data_B_i[1]), .Y(DP_OP_11J2_122_2824_n25)
);
CLKAND2X2TS U10 ( .A(Data_S[0]), .B(load_a_i), .Y(n31) );
NAND4XLTS U11 ( .A(Data_S[9]), .B(Data_S[8]), .C(Data_S[7]), .D(n20), .Y(n22) );
INVX2TS U12 ( .A(Data_S[10]), .Y(n23) );
AO21XLTS U13 ( .A0(Underflow_flag_o), .A1(n30), .B0(n29), .Y(n4) );
NOR4BXLTS U14 ( .AN(n28), .B(n27), .C(Data_S[10]), .D(Data_S[9]), .Y(n29) );
NOR4BXLTS U15 ( .AN(n26), .B(Data_S[8]), .C(Data_S[7]), .D(Data_S[6]), .Y(
n28) );
AO22XLTS U16 ( .A0(Data_S[10]), .A1(n1), .B0(n17), .B1(Data_Result_o[10]),
.Y(n5) );
AO22XLTS U17 ( .A0(Data_S[9]), .A1(n1), .B0(n17), .B1(Data_Result_o[9]), .Y(
n6) );
AO22XLTS U18 ( .A0(Data_S[8]), .A1(n1), .B0(n32), .B1(Data_Result_o[8]), .Y(
n7) );
AO22XLTS U19 ( .A0(Data_S[7]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[7]), .Y(n8) );
AO22XLTS U20 ( .A0(Data_S[6]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[6]), .Y(n9) );
AO22XLTS U21 ( .A0(Data_S[5]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[5]), .Y(n10) );
AO22XLTS U22 ( .A0(Data_S[4]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[4]), .Y(n11) );
AO22XLTS U23 ( .A0(Data_S[3]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[3]), .Y(n12) );
AO22XLTS U24 ( .A0(Data_S[2]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[2]), .Y(n13) );
AO22XLTS U25 ( .A0(Data_S[1]), .A1(load_a_i), .B0(n32), .B1(Data_Result_o[1]), .Y(n14) );
AO21XLTS U26 ( .A0(n17), .A1(Data_Result_o[0]), .B0(n31), .Y(n16) );
CLKBUFX2TS U27 ( .A(load_a_i), .Y(n1) );
CLKBUFX2TS U28 ( .A(Add_Subt_i), .Y(n2) );
CLKBUFX2TS U29 ( .A(n32), .Y(n17) );
INVX2TS U30 ( .A(rst), .Y(n18) );
NOR4BXLTS U31 ( .AN(n25), .B(Data_S[5]), .C(Data_S[4]), .D(Data_S[3]), .Y(
n26) );
INVX2TS U32 ( .A(n27), .Y(n24) );
AND4X1TS U33 ( .A(Data_S[3]), .B(Data_S[2]), .C(Data_S[1]), .D(n31), .Y(n19)
);
AND4X1TS U34 ( .A(Data_S[6]), .B(Data_S[5]), .C(Data_S[4]), .D(n19), .Y(n20)
);
INVX2TS U35 ( .A(load_a_i), .Y(n32) );
NAND2X1TS U36 ( .A(Overflow_flag_o), .B(n32), .Y(n21) );
OAI31X1TS U37 ( .A0(n24), .A1(n23), .A2(n22), .B0(n21), .Y(n3) );
XOR2XLTS U38 ( .A(n2), .B(Data_B_i[6]), .Y(DP_OP_11J2_122_2824_n20) );
XOR2XLTS U39 ( .A(n2), .B(Data_B_i[7]), .Y(DP_OP_11J2_122_2824_n19) );
XOR2XLTS U40 ( .A(n2), .B(Data_B_i[8]), .Y(DP_OP_11J2_122_2824_n18) );
XOR2XLTS U41 ( .A(n2), .B(Data_B_i[9]), .Y(DP_OP_11J2_122_2824_n17) );
INVX2TS U42 ( .A(load_b_i), .Y(n30) );
INVX2TS U43 ( .A(rst), .Y(n15) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Multiplexer_AC_W1_439 ( ctrl, D0, D1, S );
input [0:0] D0;
input [0:0] D1;
output [0:0] S;
input ctrl;
NOR2BX1TS U1 ( .AN(D0[0]), .B(ctrl), .Y(S[0]) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Multiplexer_AC_W55_0 ( ctrl, D0, D1, S );
input [54:0] D0;
input [54:0] D1;
output [54:0] S;
input ctrl;
assign S[2] = ctrl;
assign S[54] = 1'b0;
assign S[53] = 1'b0;
assign S[52] = 1'b0;
assign S[51] = 1'b0;
assign S[50] = 1'b0;
assign S[49] = 1'b0;
assign S[48] = 1'b0;
assign S[47] = 1'b0;
assign S[46] = 1'b0;
assign S[45] = 1'b0;
assign S[44] = 1'b0;
assign S[43] = 1'b0;
assign S[42] = 1'b0;
assign S[41] = 1'b0;
assign S[40] = 1'b0;
assign S[39] = 1'b0;
assign S[38] = 1'b0;
assign S[37] = 1'b0;
assign S[36] = 1'b0;
assign S[35] = 1'b0;
assign S[34] = 1'b0;
assign S[33] = 1'b0;
assign S[32] = 1'b0;
assign S[31] = 1'b0;
assign S[30] = 1'b0;
assign S[29] = 1'b0;
assign S[28] = 1'b0;
assign S[27] = 1'b0;
assign S[26] = 1'b0;
assign S[25] = 1'b0;
assign S[24] = 1'b0;
assign S[23] = 1'b0;
assign S[22] = 1'b0;
assign S[21] = 1'b0;
assign S[20] = 1'b0;
assign S[19] = 1'b0;
assign S[18] = 1'b0;
assign S[17] = 1'b0;
assign S[16] = 1'b0;
assign S[15] = 1'b0;
assign S[14] = 1'b0;
assign S[13] = 1'b0;
assign S[12] = 1'b0;
assign S[11] = 1'b0;
assign S[10] = 1'b0;
assign S[9] = 1'b0;
assign S[8] = 1'b0;
assign S[7] = 1'b0;
assign S[6] = 1'b0;
assign S[5] = 1'b0;
assign S[4] = 1'b0;
assign S[3] = 1'b0;
assign S[1] = 1'b0;
assign S[0] = 1'b0;
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module LZD_SWR55_EWR6 ( clk, rst, load_i, Add_subt_result_i, Shift_Value_o );
input [54:0] Add_subt_result_i;
output [5:0] Shift_Value_o;
input clk, rst, load_i;
wire n8, n9, n10, n11, n12, n13, n14, n1, n2, n3, n4, n5, n6, n7, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138;
DFFRXLTS Output_Reg_Q_reg_0_ ( .D(n14), .CK(clk), .RN(n13), .Q(
Shift_Value_o[0]), .QN(n138) );
DFFRXLTS Output_Reg_Q_reg_1_ ( .D(n12), .CK(clk), .RN(n13), .Q(
Shift_Value_o[1]), .QN(n137) );
DFFRXLTS Output_Reg_Q_reg_2_ ( .D(n11), .CK(clk), .RN(n13), .Q(
Shift_Value_o[2]), .QN(n136) );
DFFRXLTS Output_Reg_Q_reg_3_ ( .D(n10), .CK(clk), .RN(n13), .Q(
Shift_Value_o[3]) );
DFFRXLTS Output_Reg_Q_reg_4_ ( .D(n9), .CK(clk), .RN(n13), .Q(
Shift_Value_o[4]), .QN(n135) );
DFFRXLTS Output_Reg_Q_reg_5_ ( .D(n8), .CK(clk), .RN(n13), .Q(
Shift_Value_o[5]) );
AO22XLTS U1 ( .A0(load_i), .A1(n20), .B0(n132), .B1(Shift_Value_o[5]), .Y(n8) );
AO22XLTS U2 ( .A0(load_i), .A1(n38), .B0(n132), .B1(Shift_Value_o[3]), .Y(
n10) );
NOR2XLTS U3 ( .A(Add_subt_result_i[52]), .B(Add_subt_result_i[51]), .Y(n54)
);
NOR2XLTS U4 ( .A(Add_subt_result_i[53]), .B(Add_subt_result_i[54]), .Y(n57)
);
AOI31XLTS U5 ( .A0(n80), .A1(Add_subt_result_i[47]), .A2(n79), .B0(n78), .Y(
n81) );
NOR2XLTS U6 ( .A(Add_subt_result_i[46]), .B(n50), .Y(n77) );
NOR2XLTS U7 ( .A(Add_subt_result_i[13]), .B(Add_subt_result_i[14]), .Y(n21)
);
OR2X1TS U8 ( .A(Add_subt_result_i[42]), .B(n53), .Y(n114) );
NOR2XLTS U9 ( .A(n52), .B(n2), .Y(n1) );
NOR2XLTS U10 ( .A(n26), .B(n50), .Y(n29) );
NOR2XLTS U11 ( .A(Add_subt_result_i[38]), .B(n52), .Y(n119) );
NOR2XLTS U12 ( .A(Add_subt_result_i[26]), .B(n6), .Y(n121) );
NOR2XLTS U13 ( .A(Add_subt_result_i[18]), .B(n41), .Y(n127) );
OR2X1TS U14 ( .A(n33), .B(n32), .Y(n45) );
AOI31XLTS U15 ( .A0(Add_subt_result_i[8]), .A1(n126), .A2(n72), .B0(n71),
.Y(n103) );
INVX2TS U16 ( .A(rst), .Y(n13) );
NOR2XLTS U17 ( .A(Add_subt_result_i[24]), .B(Add_subt_result_i[25]), .Y(n15)
);
NOR3XLTS U18 ( .A(Add_subt_result_i[27]), .B(Add_subt_result_i[28]), .C(
Add_subt_result_i[29]), .Y(n24) );
NOR4XLTS U19 ( .A(Add_subt_result_i[40]), .B(Add_subt_result_i[42]), .C(
Add_subt_result_i[39]), .D(Add_subt_result_i[41]), .Y(n31) );
OR4X2TS U20 ( .A(Add_subt_result_i[44]), .B(Add_subt_result_i[45]), .C(
Add_subt_result_i[43]), .D(Add_subt_result_i[46]), .Y(n26) );
NOR4XLTS U21 ( .A(Add_subt_result_i[48]), .B(Add_subt_result_i[49]), .C(
Add_subt_result_i[47]), .D(Add_subt_result_i[50]), .Y(n43) );
NOR4XLTS U22 ( .A(Add_subt_result_i[53]), .B(Add_subt_result_i[54]), .C(
Add_subt_result_i[52]), .D(Add_subt_result_i[51]), .Y(n79) );
NAND2X1TS U23 ( .A(n43), .B(n79), .Y(n50) );
NAND2X1TS U24 ( .A(n31), .B(n29), .Y(n52) );
NOR4XLTS U25 ( .A(Add_subt_result_i[36]), .B(Add_subt_result_i[37]), .C(
Add_subt_result_i[35]), .D(Add_subt_result_i[38]), .Y(n17) );
INVX2TS U26 ( .A(n17), .Y(n2) );
NOR3XLTS U27 ( .A(Add_subt_result_i[32]), .B(Add_subt_result_i[34]), .C(
Add_subt_result_i[33]), .Y(n4) );
NAND2X1TS U28 ( .A(n1), .B(n4), .Y(n88) );
NOR3XLTS U29 ( .A(Add_subt_result_i[31]), .B(Add_subt_result_i[30]), .C(n88),
.Y(n120) );
NAND2X1TS U30 ( .A(n24), .B(n120), .Y(n6) );
NAND2X1TS U31 ( .A(n15), .B(n121), .Y(n5) );
NOR2XLTS U32 ( .A(Add_subt_result_i[23]), .B(n5), .Y(n20) );
INVX2TS U33 ( .A(load_i), .Y(n132) );
NOR2BX1TS U34 ( .AN(n120), .B(n24), .Y(n19) );
INVX2TS U35 ( .A(Add_subt_result_i[31]), .Y(n3) );
AOI211XLTS U36 ( .A0(n4), .A1(n3), .B0(n2), .C0(n52), .Y(n46) );
NAND2BXLTS U37 ( .AN(n5), .B(Add_subt_result_i[23]), .Y(n86) );
INVX2TS U38 ( .A(Add_subt_result_i[26]), .Y(n7) );
AO21XLTS U39 ( .A0(n15), .A1(n7), .B0(n6), .Y(n16) );
NAND2X1TS U40 ( .A(n86), .B(n16), .Y(n32) );
INVX2TS U41 ( .A(Add_subt_result_i[30]), .Y(n74) );
OAI22X1TS U42 ( .A0(n17), .A1(n52), .B0(n88), .B1(n74), .Y(n18) );
NOR4XLTS U43 ( .A(n19), .B(n46), .C(n32), .D(n18), .Y(n22) );
NOR2XLTS U44 ( .A(Add_subt_result_i[16]), .B(Add_subt_result_i[17]), .Y(n40)
);
NAND2BXLTS U45 ( .AN(Add_subt_result_i[22]), .B(n20), .Y(n125) );
NOR3XLTS U46 ( .A(Add_subt_result_i[20]), .B(Add_subt_result_i[21]), .C(n125), .Y(n91) );
NAND2BXLTS U47 ( .AN(Add_subt_result_i[19]), .B(n91), .Y(n41) );
NAND2X1TS U48 ( .A(n40), .B(n127), .Y(n47) );
NOR2XLTS U49 ( .A(Add_subt_result_i[15]), .B(n47), .Y(n34) );
NAND2X1TS U50 ( .A(n34), .B(n21), .Y(n28) );
NOR2XLTS U51 ( .A(Add_subt_result_i[12]), .B(n28), .Y(n35) );
NAND2BXLTS U52 ( .AN(Add_subt_result_i[11]), .B(n35), .Y(n49) );
NOR4XLTS U53 ( .A(Add_subt_result_i[8]), .B(Add_subt_result_i[9]), .C(
Add_subt_result_i[10]), .D(Add_subt_result_i[7]), .Y(n30) );
NAND2BXLTS U54 ( .AN(n49), .B(n30), .Y(n39) );
AOI32X1TS U55 ( .A0(n22), .A1(load_i), .A2(n39), .B0(n135), .B1(n132), .Y(n9) );
INVX2TS U56 ( .A(n50), .Y(n27) );
INVX2TS U57 ( .A(Add_subt_result_i[14]), .Y(n23) );
AND3X1TS U58 ( .A(n23), .B(Add_subt_result_i[13]), .C(n34), .Y(n131) );
AOI211XLTS U59 ( .A0(n24), .A1(n74), .B0(Add_subt_result_i[31]), .C0(n88),
.Y(n25) );
AOI211XLTS U60 ( .A0(n27), .A1(n26), .B0(n131), .C0(n25), .Y(n37) );
NOR2BX1TS U61 ( .AN(Add_subt_result_i[12]), .B(n28), .Y(n66) );
INVX2TS U62 ( .A(n29), .Y(n53) );
OAI22X1TS U63 ( .A0(n31), .A1(n53), .B0(n30), .B1(n49), .Y(n33) );
AOI211XLTS U64 ( .A0(Add_subt_result_i[14]), .A1(n34), .B0(n66), .C0(n45),
.Y(n36) );
NAND2X1TS U65 ( .A(Add_subt_result_i[11]), .B(n35), .Y(n96) );
NAND3XLTS U66 ( .A(n37), .B(n36), .C(n96), .Y(n38) );
NOR2XLTS U67 ( .A(Add_subt_result_i[6]), .B(n39), .Y(n104) );
NOR2BX1TS U68 ( .AN(n104), .B(Add_subt_result_i[5]), .Y(n101) );
NOR2BX1TS U69 ( .AN(n101), .B(Add_subt_result_i[4]), .Y(n92) );
NOR2BX1TS U70 ( .AN(n92), .B(Add_subt_result_i[3]), .Y(n73) );
INVX2TS U71 ( .A(n79), .Y(n109) );
NOR2BX1TS U72 ( .AN(n40), .B(Add_subt_result_i[18]), .Y(n42) );
OAI22X1TS U73 ( .A0(n43), .A1(n109), .B0(n42), .B1(n41), .Y(n44) );
NOR4XLTS U74 ( .A(n73), .B(n46), .C(n45), .D(n44), .Y(n48) );
NAND2BXLTS U75 ( .AN(n47), .B(Add_subt_result_i[15]), .Y(n97) );
AOI32X1TS U76 ( .A0(n48), .A1(load_i), .A2(n97), .B0(n136), .B1(n132), .Y(
n11) );
NOR2XLTS U77 ( .A(Add_subt_result_i[10]), .B(n49), .Y(n126) );
INVX2TS U78 ( .A(Add_subt_result_i[9]), .Y(n72) );
NAND2X1TS U79 ( .A(Add_subt_result_i[24]), .B(n121), .Y(n70) );
INVX2TS U80 ( .A(Add_subt_result_i[29]), .Y(n65) );
INVX2TS U81 ( .A(Add_subt_result_i[20]), .Y(n63) );
INVX2TS U82 ( .A(Add_subt_result_i[45]), .Y(n113) );
NOR2XLTS U83 ( .A(Add_subt_result_i[34]), .B(Add_subt_result_i[33]), .Y(n51)
);
AOI21X1TS U84 ( .A0(Add_subt_result_i[32]), .A1(n51), .B0(
Add_subt_result_i[36]), .Y(n60) );
INVX2TS U85 ( .A(n119), .Y(n59) );
NOR2XLTS U86 ( .A(Add_subt_result_i[41]), .B(n114), .Y(n76) );
INVX2TS U87 ( .A(Add_subt_result_i[48]), .Y(n55) );
OAI31X1TS U88 ( .A0(Add_subt_result_i[49]), .A1(Add_subt_result_i[50]), .A2(
n55), .B0(n54), .Y(n56) );
AOI22X1TS U89 ( .A0(Add_subt_result_i[40]), .A1(n76), .B0(n57), .B1(n56),
.Y(n58) );
OAI31X1TS U90 ( .A0(Add_subt_result_i[37]), .A1(n60), .A2(n59), .B0(n58),
.Y(n61) );
AOI31XLTS U91 ( .A0(Add_subt_result_i[44]), .A1(n77), .A2(n113), .B0(n61),
.Y(n62) );
OAI31X1TS U92 ( .A0(Add_subt_result_i[21]), .A1(n125), .A2(n63), .B0(n62),
.Y(n64) );
AOI31XLTS U93 ( .A0(Add_subt_result_i[28]), .A1(n120), .A2(n65), .B0(n64),
.Y(n69) );
INVX2TS U94 ( .A(Add_subt_result_i[17]), .Y(n67) );
AOI31XLTS U95 ( .A0(Add_subt_result_i[16]), .A1(n127), .A2(n67), .B0(n66),
.Y(n68) );
OAI211XLTS U96 ( .A0(Add_subt_result_i[25]), .A1(n70), .B0(n69), .C0(n68),
.Y(n71) );
NOR2BX1TS U97 ( .AN(n73), .B(Add_subt_result_i[2]), .Y(n105) );
NOR2BX1TS U98 ( .AN(n105), .B(Add_subt_result_i[1]), .Y(n100) );
NOR2XLTS U99 ( .A(Add_subt_result_i[28]), .B(Add_subt_result_i[29]), .Y(n75)
);
AOI31XLTS U100 ( .A0(n75), .A1(Add_subt_result_i[27]), .A2(n74), .B0(
Add_subt_result_i[31]), .Y(n89) );
NOR2XLTS U101 ( .A(Add_subt_result_i[36]), .B(Add_subt_result_i[37]), .Y(n85) );
INVX2TS U102 ( .A(Add_subt_result_i[39]), .Y(n83) );
INVX2TS U103 ( .A(n76), .Y(n82) );
NOR3XLTS U104 ( .A(Add_subt_result_i[48]), .B(Add_subt_result_i[49]), .C(
Add_subt_result_i[50]), .Y(n80) );
INVX2TS U105 ( .A(n77), .Y(n112) );
NOR4BXLTS U106 ( .AN(Add_subt_result_i[43]), .B(Add_subt_result_i[44]), .C(
Add_subt_result_i[45]), .D(n112), .Y(n78) );
OAI31X1TS U107 ( .A0(Add_subt_result_i[40]), .A1(n83), .A2(n82), .B0(n81),
.Y(n84) );
AOI31XLTS U108 ( .A0(n85), .A1(Add_subt_result_i[35]), .A2(n119), .B0(n84),
.Y(n87) );
OAI211XLTS U109 ( .A0(n89), .A1(n88), .B0(n87), .C0(n86), .Y(n90) );
AOI21X1TS U110 ( .A0(Add_subt_result_i[19]), .A1(n91), .B0(n90), .Y(n99) );
NOR2XLTS U111 ( .A(Add_subt_result_i[8]), .B(Add_subt_result_i[9]), .Y(n95)
);
INVX2TS U112 ( .A(Add_subt_result_i[0]), .Y(n93) );
AO22XLTS U113 ( .A0(n93), .A1(n100), .B0(Add_subt_result_i[3]), .B1(n92),
.Y(n94) );
AOI31XLTS U114 ( .A0(n95), .A1(Add_subt_result_i[7]), .A2(n126), .B0(n94),
.Y(n98) );
NAND4XLTS U115 ( .A(n99), .B(n98), .C(n97), .D(n96), .Y(n130) );
AOI211XLTS U116 ( .A0(n101), .A1(Add_subt_result_i[4]), .B0(n100), .C0(n130),
.Y(n102) );
AOI32X1TS U117 ( .A0(n103), .A1(load_i), .A2(n102), .B0(n137), .B1(n132),
.Y(n12) );
AOI22X1TS U118 ( .A0(Add_subt_result_i[1]), .A1(n105), .B0(n104), .B1(
Add_subt_result_i[5]), .Y(n134) );
INVX2TS U119 ( .A(Add_subt_result_i[21]), .Y(n124) );
INVX2TS U120 ( .A(Add_subt_result_i[33]), .Y(n107) );
INVX2TS U121 ( .A(Add_subt_result_i[37]), .Y(n106) );
OAI31X1TS U122 ( .A0(Add_subt_result_i[36]), .A1(Add_subt_result_i[34]),
.A2(n107), .B0(n106), .Y(n118) );
INVX2TS U123 ( .A(Add_subt_result_i[52]), .Y(n108) );
AOI21X1TS U124 ( .A0(Add_subt_result_i[51]), .A1(n108), .B0(
Add_subt_result_i[53]), .Y(n111) );
NOR2XLTS U125 ( .A(Add_subt_result_i[50]), .B(n109), .Y(n110) );
OAI2BB2XLTS U126 ( .B0(Add_subt_result_i[54]), .B1(n111), .A0N(
Add_subt_result_i[49]), .A1N(n110), .Y(n117) );
INVX2TS U127 ( .A(Add_subt_result_i[41]), .Y(n115) );
OAI22X1TS U128 ( .A0(n115), .A1(n114), .B0(n113), .B1(n112), .Y(n116) );
AOI211XLTS U129 ( .A0(n119), .A1(n118), .B0(n117), .C0(n116), .Y(n123) );
AOI22X1TS U130 ( .A0(Add_subt_result_i[25]), .A1(n121), .B0(
Add_subt_result_i[29]), .B1(n120), .Y(n122) );
OAI211XLTS U131 ( .A0(n125), .A1(n124), .B0(n123), .C0(n122), .Y(n129) );
AO22XLTS U132 ( .A0(Add_subt_result_i[17]), .A1(n127), .B0(
Add_subt_result_i[9]), .B1(n126), .Y(n128) );
NOR4XLTS U133 ( .A(n131), .B(n130), .C(n129), .D(n128), .Y(n133) );
AOI32X1TS U134 ( .A0(n134), .A1(load_i), .A2(n133), .B0(n138), .B1(n132),
.Y(n14) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Round_Sgf_Dec ( Data_i, Round_Type_i, Sign_Result_i, Round_Flag_o );
input [1:0] Data_i;
input [1:0] Round_Type_i;
input Sign_Result_i;
output Round_Flag_o;
assign Round_Flag_o = 1'b0;
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Tenth_Phase_W64_EW11_SW52 ( clk, rst, load_i, sel_a_i, sel_b_i, sign_i,
exp_ieee_i, sgf_ieee_i, final_result_ieee_o );
input [10:0] exp_ieee_i;
input [51:0] sgf_ieee_i;
output [63:0] final_result_ieee_o;
input clk, rst, load_i, sel_a_i, sel_b_i, sign_i;
wire n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n129, n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19;
DFFRXLTS Final_Result_IEEE_Q_reg_63_ ( .D(n66), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[63]) );
DFFRXLTS Final_Result_IEEE_Q_reg_52_ ( .D(n77), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[52]) );
DFFRXLTS Final_Result_IEEE_Q_reg_53_ ( .D(n76), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[53]) );
DFFRXLTS Final_Result_IEEE_Q_reg_54_ ( .D(n75), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[54]) );
DFFRXLTS Final_Result_IEEE_Q_reg_55_ ( .D(n74), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[55]) );
DFFRXLTS Final_Result_IEEE_Q_reg_56_ ( .D(n73), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[56]) );
DFFRXLTS Final_Result_IEEE_Q_reg_57_ ( .D(n72), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[57]) );
DFFRXLTS Final_Result_IEEE_Q_reg_58_ ( .D(n71), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[58]) );
DFFRXLTS Final_Result_IEEE_Q_reg_59_ ( .D(n70), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[59]) );
DFFRXLTS Final_Result_IEEE_Q_reg_60_ ( .D(n69), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[60]) );
DFFRXLTS Final_Result_IEEE_Q_reg_61_ ( .D(n68), .CK(clk), .RN(n5), .Q(
final_result_ieee_o[61]) );
DFFRXLTS Final_Result_IEEE_Q_reg_62_ ( .D(n67), .CK(clk), .RN(n129), .Q(
final_result_ieee_o[62]) );
OA21XLTS U3 ( .A0(sel_a_i), .A1(sel_b_i), .B0(n2), .Y(n1) );
CLKBUFX2TS U4 ( .A(load_i), .Y(n2) );
INVX2TS U5 ( .A(n1), .Y(n3) );
INVX2TS U6 ( .A(n1), .Y(n4) );
INVX2TS U7 ( .A(rst), .Y(n5) );
CLKBUFX2TS U8 ( .A(n18), .Y(n6) );
INVX2TS U9 ( .A(rst), .Y(n129) );
OAI21XLTS U10 ( .A0(sel_b_i), .A1(sign_i), .B0(n2), .Y(n7) );
INVX2TS U11 ( .A(load_i), .Y(n18) );
OAI2BB2XLTS U12 ( .B0(sel_a_i), .B1(n7), .A0N(final_result_ieee_o[63]),
.A1N(n6), .Y(n66) );
AOI22X1TS U13 ( .A0(load_i), .A1(exp_ieee_i[10]), .B0(
final_result_ieee_o[62]), .B1(n18), .Y(n8) );
NAND2X1TS U14 ( .A(n8), .B(n3), .Y(n67) );
AOI22X1TS U15 ( .A0(load_i), .A1(exp_ieee_i[9]), .B0(final_result_ieee_o[61]), .B1(n18), .Y(n9) );
NAND2X1TS U16 ( .A(n9), .B(n4), .Y(n68) );
AOI22X1TS U17 ( .A0(load_i), .A1(exp_ieee_i[8]), .B0(final_result_ieee_o[60]), .B1(n18), .Y(n10) );
NAND2X1TS U18 ( .A(n10), .B(n3), .Y(n69) );
AOI22X1TS U19 ( .A0(load_i), .A1(exp_ieee_i[7]), .B0(final_result_ieee_o[59]), .B1(n18), .Y(n11) );
NAND2X1TS U20 ( .A(n11), .B(n4), .Y(n70) );
AOI22X1TS U21 ( .A0(load_i), .A1(exp_ieee_i[6]), .B0(final_result_ieee_o[58]), .B1(n18), .Y(n12) );
NAND2X1TS U22 ( .A(n12), .B(n3), .Y(n71) );
AOI22X1TS U23 ( .A0(load_i), .A1(exp_ieee_i[5]), .B0(final_result_ieee_o[57]), .B1(n18), .Y(n13) );
NAND2X1TS U24 ( .A(n13), .B(n4), .Y(n72) );
AOI22X1TS U25 ( .A0(load_i), .A1(exp_ieee_i[4]), .B0(final_result_ieee_o[56]), .B1(n18), .Y(n14) );
NAND2X1TS U26 ( .A(n14), .B(n3), .Y(n73) );
AOI22X1TS U27 ( .A0(load_i), .A1(exp_ieee_i[3]), .B0(final_result_ieee_o[55]), .B1(n18), .Y(n15) );
NAND2X1TS U28 ( .A(n15), .B(n4), .Y(n74) );
AOI22X1TS U29 ( .A0(n2), .A1(exp_ieee_i[2]), .B0(final_result_ieee_o[54]),
.B1(n18), .Y(n16) );
NAND2X1TS U30 ( .A(n16), .B(n3), .Y(n75) );
AOI22X1TS U31 ( .A0(n2), .A1(exp_ieee_i[1]), .B0(final_result_ieee_o[53]),
.B1(n6), .Y(n17) );
NAND2X1TS U32 ( .A(n17), .B(n4), .Y(n76) );
AOI22X1TS U33 ( .A0(n2), .A1(exp_ieee_i[0]), .B0(final_result_ieee_o[52]),
.B1(n6), .Y(n19) );
NAND2X1TS U34 ( .A(n19), .B(n3), .Y(n77) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module RegisterAdd_W64_1 ( clk, rst, load, D, Q );
input [63:0] D;
output [63:0] Q;
input clk, rst, load;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n87, n88, n89, n90, n91, n92, n93,
n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105,
n106, n107;
DFFRXLTS Q_reg_63_ ( .D(n22), .CK(clk), .RN(n21), .Q(Q[63]) );
DFFRXLTS Q_reg_62_ ( .D(n24), .CK(clk), .RN(n21), .Q(Q[62]) );
DFFRXLTS Q_reg_61_ ( .D(n25), .CK(clk), .RN(n21), .Q(Q[61]) );
DFFRXLTS Q_reg_60_ ( .D(n26), .CK(clk), .RN(n21), .Q(Q[60]) );
DFFRXLTS Q_reg_59_ ( .D(n27), .CK(clk), .RN(n20), .Q(Q[59]) );
DFFRXLTS Q_reg_58_ ( .D(n28), .CK(clk), .RN(n20), .Q(Q[58]) );
DFFRXLTS Q_reg_57_ ( .D(n29), .CK(clk), .RN(n20), .Q(Q[57]) );
DFFRXLTS Q_reg_56_ ( .D(n30), .CK(clk), .RN(n20), .Q(Q[56]) );
DFFRXLTS Q_reg_55_ ( .D(n31), .CK(clk), .RN(n20), .Q(Q[55]) );
DFFRXLTS Q_reg_54_ ( .D(n32), .CK(clk), .RN(n20), .Q(Q[54]) );
DFFRXLTS Q_reg_53_ ( .D(n33), .CK(clk), .RN(n20), .Q(Q[53]) );
DFFRXLTS Q_reg_52_ ( .D(n34), .CK(clk), .RN(n20), .Q(Q[52]) );
DFFRXLTS Q_reg_51_ ( .D(n35), .CK(clk), .RN(n20), .Q(Q[51]) );
DFFRXLTS Q_reg_50_ ( .D(n36), .CK(clk), .RN(n20), .Q(Q[50]) );
DFFRXLTS Q_reg_49_ ( .D(n37), .CK(clk), .RN(n19), .Q(Q[49]) );
DFFRXLTS Q_reg_48_ ( .D(n38), .CK(clk), .RN(n19), .Q(Q[48]) );
DFFRXLTS Q_reg_47_ ( .D(n39), .CK(clk), .RN(n19), .Q(Q[47]) );
DFFRXLTS Q_reg_46_ ( .D(n40), .CK(clk), .RN(n19), .Q(Q[46]) );
DFFRXLTS Q_reg_45_ ( .D(n41), .CK(clk), .RN(n19), .Q(Q[45]) );
DFFRXLTS Q_reg_44_ ( .D(n42), .CK(clk), .RN(n19), .Q(Q[44]) );
DFFRXLTS Q_reg_43_ ( .D(n43), .CK(clk), .RN(n19), .Q(Q[43]) );
DFFRXLTS Q_reg_42_ ( .D(n44), .CK(clk), .RN(n19), .Q(Q[42]) );
DFFRXLTS Q_reg_41_ ( .D(n45), .CK(clk), .RN(n19), .Q(Q[41]) );
DFFRXLTS Q_reg_40_ ( .D(n46), .CK(clk), .RN(n19), .Q(Q[40]) );
DFFRXLTS Q_reg_39_ ( .D(n47), .CK(clk), .RN(n21), .Q(Q[39]) );
DFFRXLTS Q_reg_38_ ( .D(n48), .CK(clk), .RN(n23), .Q(Q[38]) );
DFFRXLTS Q_reg_37_ ( .D(n49), .CK(clk), .RN(n23), .Q(Q[37]) );
DFFRXLTS Q_reg_36_ ( .D(n50), .CK(clk), .RN(n23), .Q(Q[36]) );
DFFRXLTS Q_reg_35_ ( .D(n51), .CK(clk), .RN(n23), .Q(Q[35]) );
DFFRXLTS Q_reg_34_ ( .D(n52), .CK(clk), .RN(n21), .Q(Q[34]) );
DFFRXLTS Q_reg_33_ ( .D(n53), .CK(clk), .RN(n21), .Q(Q[33]) );
DFFRXLTS Q_reg_32_ ( .D(n54), .CK(clk), .RN(n21), .Q(Q[32]) );
DFFRXLTS Q_reg_31_ ( .D(n55), .CK(clk), .RN(n21), .Q(Q[31]) );
DFFRXLTS Q_reg_30_ ( .D(n56), .CK(clk), .RN(n21), .Q(Q[30]) );
DFFRXLTS Q_reg_29_ ( .D(n57), .CK(clk), .RN(n18), .Q(Q[29]) );
DFFRXLTS Q_reg_28_ ( .D(n58), .CK(clk), .RN(n18), .Q(Q[28]) );
DFFRXLTS Q_reg_27_ ( .D(n59), .CK(clk), .RN(n18), .Q(Q[27]) );
DFFRXLTS Q_reg_26_ ( .D(n60), .CK(clk), .RN(n18), .Q(Q[26]) );
DFFRXLTS Q_reg_25_ ( .D(n61), .CK(clk), .RN(n18), .Q(Q[25]) );
DFFRXLTS Q_reg_24_ ( .D(n62), .CK(clk), .RN(n18), .Q(Q[24]) );
DFFRXLTS Q_reg_23_ ( .D(n63), .CK(clk), .RN(n18), .Q(Q[23]) );
DFFRXLTS Q_reg_22_ ( .D(n64), .CK(clk), .RN(n18), .Q(Q[22]) );
DFFRXLTS Q_reg_21_ ( .D(n65), .CK(clk), .RN(n18), .Q(Q[21]) );
DFFRXLTS Q_reg_20_ ( .D(n87), .CK(clk), .RN(n18), .Q(Q[20]) );
DFFRXLTS Q_reg_19_ ( .D(n88), .CK(clk), .RN(n17), .Q(Q[19]) );
DFFRXLTS Q_reg_18_ ( .D(n89), .CK(clk), .RN(n17), .Q(Q[18]) );
DFFRXLTS Q_reg_17_ ( .D(n90), .CK(clk), .RN(n17), .Q(Q[17]) );
DFFRXLTS Q_reg_16_ ( .D(n91), .CK(clk), .RN(n17), .Q(Q[16]) );
DFFRXLTS Q_reg_15_ ( .D(n92), .CK(clk), .RN(n17), .Q(Q[15]) );
DFFRXLTS Q_reg_14_ ( .D(n93), .CK(clk), .RN(n17), .Q(Q[14]) );
DFFRXLTS Q_reg_13_ ( .D(n94), .CK(clk), .RN(n17), .Q(Q[13]) );
DFFRXLTS Q_reg_12_ ( .D(n95), .CK(clk), .RN(n17), .Q(Q[12]) );
DFFRXLTS Q_reg_11_ ( .D(n96), .CK(clk), .RN(n17), .Q(Q[11]) );
DFFRXLTS Q_reg_10_ ( .D(n97), .CK(clk), .RN(n17), .Q(Q[10]) );
DFFRXLTS Q_reg_9_ ( .D(n98), .CK(clk), .RN(n16), .Q(Q[9]) );
DFFRXLTS Q_reg_8_ ( .D(n99), .CK(clk), .RN(n16), .Q(Q[8]) );
DFFRXLTS Q_reg_7_ ( .D(n100), .CK(clk), .RN(n16), .Q(Q[7]) );
DFFRXLTS Q_reg_6_ ( .D(n101), .CK(clk), .RN(n16), .Q(Q[6]) );
DFFRXLTS Q_reg_5_ ( .D(n102), .CK(clk), .RN(n16), .Q(Q[5]) );
DFFRXLTS Q_reg_4_ ( .D(n103), .CK(clk), .RN(n16), .Q(Q[4]) );
DFFRXLTS Q_reg_3_ ( .D(n104), .CK(clk), .RN(n16), .Q(Q[3]) );
DFFRXLTS Q_reg_2_ ( .D(n105), .CK(clk), .RN(n16), .Q(Q[2]) );
DFFRXLTS Q_reg_1_ ( .D(n106), .CK(clk), .RN(n16), .Q(Q[1]) );
DFFRXLTS Q_reg_0_ ( .D(n107), .CK(clk), .RN(n16), .Q(Q[0]) );
AO22XLTS U2 ( .A0(n8), .A1(D[0]), .B0(n9), .B1(Q[0]), .Y(n107) );
AO22XLTS U3 ( .A0(n8), .A1(D[1]), .B0(n9), .B1(Q[1]), .Y(n106) );
AO22XLTS U4 ( .A0(n2), .A1(D[2]), .B0(n9), .B1(Q[2]), .Y(n105) );
AO22XLTS U5 ( .A0(n4), .A1(D[3]), .B0(n9), .B1(Q[3]), .Y(n104) );
AO22XLTS U6 ( .A0(n6), .A1(D[4]), .B0(n9), .B1(Q[4]), .Y(n103) );
AO22XLTS U7 ( .A0(n2), .A1(D[5]), .B0(n9), .B1(Q[5]), .Y(n102) );
AO22XLTS U8 ( .A0(n2), .A1(D[6]), .B0(n9), .B1(Q[6]), .Y(n101) );
AO22XLTS U9 ( .A0(n8), .A1(D[7]), .B0(n9), .B1(Q[7]), .Y(n100) );
AO22XLTS U10 ( .A0(n3), .A1(D[8]), .B0(n9), .B1(Q[8]), .Y(n99) );
AO22XLTS U11 ( .A0(n4), .A1(D[9]), .B0(n9), .B1(Q[9]), .Y(n98) );
AO22XLTS U12 ( .A0(n6), .A1(D[10]), .B0(n10), .B1(Q[10]), .Y(n97) );
AO22XLTS U13 ( .A0(n8), .A1(D[11]), .B0(n10), .B1(Q[11]), .Y(n96) );
AO22XLTS U14 ( .A0(n6), .A1(D[12]), .B0(n10), .B1(Q[12]), .Y(n95) );
AO22XLTS U15 ( .A0(n3), .A1(D[13]), .B0(n10), .B1(Q[13]), .Y(n94) );
AO22XLTS U16 ( .A0(n3), .A1(D[14]), .B0(n10), .B1(Q[14]), .Y(n93) );
AO22XLTS U17 ( .A0(n6), .A1(D[15]), .B0(n10), .B1(Q[15]), .Y(n92) );
AO22XLTS U18 ( .A0(n3), .A1(D[16]), .B0(n10), .B1(Q[16]), .Y(n91) );
AO22XLTS U19 ( .A0(n4), .A1(D[17]), .B0(n10), .B1(Q[17]), .Y(n90) );
AO22XLTS U20 ( .A0(load), .A1(D[18]), .B0(n10), .B1(Q[18]), .Y(n89) );
AO22XLTS U21 ( .A0(n3), .A1(D[19]), .B0(n10), .B1(Q[19]), .Y(n88) );
AO22XLTS U22 ( .A0(n7), .A1(D[20]), .B0(n11), .B1(Q[20]), .Y(n87) );
AO22XLTS U23 ( .A0(n6), .A1(D[21]), .B0(n11), .B1(Q[21]), .Y(n65) );
AO22XLTS U24 ( .A0(n8), .A1(D[22]), .B0(n11), .B1(Q[22]), .Y(n64) );
AO22XLTS U25 ( .A0(load), .A1(D[23]), .B0(n11), .B1(Q[23]), .Y(n63) );
AO22XLTS U26 ( .A0(n2), .A1(D[24]), .B0(n11), .B1(Q[24]), .Y(n62) );
AO22XLTS U27 ( .A0(n3), .A1(D[25]), .B0(n11), .B1(Q[25]), .Y(n61) );
AO22XLTS U28 ( .A0(n6), .A1(D[26]), .B0(n11), .B1(Q[26]), .Y(n60) );
AO22XLTS U29 ( .A0(n7), .A1(D[27]), .B0(n11), .B1(Q[27]), .Y(n59) );
AO22XLTS U30 ( .A0(n4), .A1(D[28]), .B0(n11), .B1(Q[28]), .Y(n58) );
AO22XLTS U31 ( .A0(n4), .A1(D[29]), .B0(n11), .B1(Q[29]), .Y(n57) );
AO22XLTS U32 ( .A0(n4), .A1(D[30]), .B0(n13), .B1(Q[30]), .Y(n56) );
AO22XLTS U33 ( .A0(n2), .A1(D[31]), .B0(n13), .B1(Q[31]), .Y(n55) );
AO22XLTS U34 ( .A0(n6), .A1(D[32]), .B0(n15), .B1(Q[32]), .Y(n54) );
AO22XLTS U35 ( .A0(n2), .A1(D[33]), .B0(n13), .B1(Q[33]), .Y(n53) );
AO22XLTS U36 ( .A0(n8), .A1(D[34]), .B0(n15), .B1(Q[34]), .Y(n52) );
AO22XLTS U37 ( .A0(n2), .A1(D[35]), .B0(n13), .B1(Q[35]), .Y(n51) );
AO22XLTS U38 ( .A0(n7), .A1(D[36]), .B0(n15), .B1(Q[36]), .Y(n50) );
AO22XLTS U39 ( .A0(n7), .A1(D[37]), .B0(n15), .B1(Q[37]), .Y(n49) );
AO22XLTS U40 ( .A0(load), .A1(D[38]), .B0(n15), .B1(Q[38]), .Y(n48) );
AO22XLTS U41 ( .A0(n4), .A1(D[39]), .B0(n15), .B1(Q[39]), .Y(n47) );
AO22XLTS U42 ( .A0(n6), .A1(D[40]), .B0(n12), .B1(Q[40]), .Y(n46) );
AO22XLTS U43 ( .A0(n3), .A1(D[41]), .B0(n12), .B1(Q[41]), .Y(n45) );
AO22XLTS U44 ( .A0(n3), .A1(D[42]), .B0(n12), .B1(Q[42]), .Y(n44) );
AO22XLTS U45 ( .A0(n6), .A1(D[43]), .B0(n12), .B1(Q[43]), .Y(n43) );
AO22XLTS U46 ( .A0(n8), .A1(D[44]), .B0(n12), .B1(Q[44]), .Y(n42) );
AO22XLTS U47 ( .A0(n2), .A1(D[45]), .B0(n12), .B1(Q[45]), .Y(n41) );
AO22XLTS U48 ( .A0(n7), .A1(D[46]), .B0(n12), .B1(Q[46]), .Y(n40) );
AO22XLTS U49 ( .A0(n3), .A1(D[47]), .B0(n12), .B1(Q[47]), .Y(n39) );
AO22XLTS U50 ( .A0(n4), .A1(D[48]), .B0(n12), .B1(Q[48]), .Y(n38) );
AO22XLTS U51 ( .A0(n4), .A1(D[49]), .B0(n12), .B1(Q[49]), .Y(n37) );
AO22XLTS U52 ( .A0(load), .A1(D[50]), .B0(n14), .B1(Q[50]), .Y(n36) );
AO22XLTS U53 ( .A0(n7), .A1(D[51]), .B0(n14), .B1(Q[51]), .Y(n35) );
AO22XLTS U54 ( .A0(n7), .A1(D[52]), .B0(n14), .B1(Q[52]), .Y(n34) );
AO22XLTS U55 ( .A0(n6), .A1(D[53]), .B0(n14), .B1(Q[53]), .Y(n33) );
AO22XLTS U56 ( .A0(load), .A1(D[54]), .B0(n14), .B1(Q[54]), .Y(n32) );
AO22XLTS U57 ( .A0(n4), .A1(D[55]), .B0(n14), .B1(Q[55]), .Y(n31) );
AO22XLTS U58 ( .A0(n3), .A1(D[56]), .B0(n14), .B1(Q[56]), .Y(n30) );
AO22XLTS U59 ( .A0(n7), .A1(D[57]), .B0(n14), .B1(Q[57]), .Y(n29) );
AO22XLTS U60 ( .A0(n7), .A1(D[58]), .B0(n14), .B1(Q[58]), .Y(n28) );
AO22XLTS U61 ( .A0(n7), .A1(D[59]), .B0(n14), .B1(Q[59]), .Y(n27) );
AO22XLTS U62 ( .A0(n2), .A1(D[60]), .B0(n15), .B1(Q[60]), .Y(n26) );
AO22XLTS U63 ( .A0(n8), .A1(D[61]), .B0(n15), .B1(Q[61]), .Y(n25) );
AO22XLTS U64 ( .A0(n2), .A1(D[62]), .B0(n15), .B1(Q[62]), .Y(n24) );
AO22XLTS U65 ( .A0(n8), .A1(D[63]), .B0(n15), .B1(Q[63]), .Y(n22) );
INVX2TS U66 ( .A(n5), .Y(n2) );
INVX2TS U67 ( .A(n5), .Y(n3) );
INVX2TS U68 ( .A(n5), .Y(n4) );
INVX2TS U69 ( .A(load), .Y(n5) );
INVX2TS U70 ( .A(n5), .Y(n6) );
INVX2TS U71 ( .A(n5), .Y(n7) );
INVX2TS U72 ( .A(n5), .Y(n8) );
INVX2TS U73 ( .A(rst), .Y(n23) );
CLKBUFX2TS U74 ( .A(n23), .Y(n16) );
CLKBUFX2TS U75 ( .A(n23), .Y(n17) );
CLKBUFX2TS U76 ( .A(n23), .Y(n19) );
CLKBUFX2TS U77 ( .A(n23), .Y(n20) );
CLKBUFX2TS U78 ( .A(n23), .Y(n21) );
CLKBUFX2TS U79 ( .A(n23), .Y(n18) );
INVX2TS U80 ( .A(n8), .Y(n13) );
CLKBUFX2TS U81 ( .A(n13), .Y(n9) );
CLKBUFX2TS U82 ( .A(n13), .Y(n10) );
CLKBUFX2TS U83 ( .A(n13), .Y(n11) );
CLKBUFX2TS U84 ( .A(n13), .Y(n15) );
CLKBUFX2TS U85 ( .A(n13), .Y(n12) );
CLKBUFX2TS U86 ( .A(n13), .Y(n14) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module Multiplexer_AC_W55_1 ( ctrl, D0, D1, S );
input [54:0] D0;
input [54:0] D1;
output [54:0] S;
input ctrl;
wire n4, n5, n6, n7, n8, n9, n10;
assign S[1] = 1'b0;
assign S[0] = 1'b0;
INVX2TS U1 ( .A(n6), .Y(n4) );
INVX2TS U2 ( .A(n6), .Y(n5) );
INVX2TS U3 ( .A(S[54]), .Y(n6) );
INVX2TS U4 ( .A(n6), .Y(n7) );
INVX2TS U5 ( .A(n6), .Y(n8) );
INVX2TS U6 ( .A(n6), .Y(n9) );
INVX2TS U7 ( .A(n6), .Y(n10) );
INVX2TS U8 ( .A(ctrl), .Y(S[54]) );
CLKAND2X2TS U10 ( .A(D0[2]), .B(n8), .Y(S[2]) );
CLKAND2X2TS U11 ( .A(D0[3]), .B(n7), .Y(S[3]) );
CLKAND2X2TS U12 ( .A(D0[4]), .B(n10), .Y(S[4]) );
CLKAND2X2TS U13 ( .A(D0[5]), .B(n4), .Y(S[5]) );
CLKAND2X2TS U14 ( .A(D0[6]), .B(n10), .Y(S[6]) );
CLKAND2X2TS U15 ( .A(D0[7]), .B(n8), .Y(S[7]) );
CLKAND2X2TS U16 ( .A(D0[8]), .B(n9), .Y(S[8]) );
CLKAND2X2TS U17 ( .A(D0[9]), .B(n5), .Y(S[9]) );
CLKAND2X2TS U18 ( .A(D0[10]), .B(n9), .Y(S[10]) );
CLKAND2X2TS U19 ( .A(D0[11]), .B(n10), .Y(S[11]) );
CLKAND2X2TS U20 ( .A(D0[12]), .B(n7), .Y(S[12]) );
CLKAND2X2TS U21 ( .A(D0[13]), .B(n4), .Y(S[13]) );
CLKAND2X2TS U22 ( .A(D0[14]), .B(n7), .Y(S[14]) );
CLKAND2X2TS U23 ( .A(D0[15]), .B(n9), .Y(S[15]) );
CLKAND2X2TS U24 ( .A(D0[16]), .B(n8), .Y(S[16]) );
CLKAND2X2TS U25 ( .A(D0[17]), .B(n5), .Y(S[17]) );
CLKAND2X2TS U26 ( .A(D0[18]), .B(n8), .Y(S[18]) );
CLKAND2X2TS U27 ( .A(D0[19]), .B(n7), .Y(S[19]) );
CLKAND2X2TS U28 ( .A(D0[20]), .B(n10), .Y(S[20]) );
CLKAND2X2TS U29 ( .A(D0[21]), .B(n4), .Y(S[21]) );
CLKAND2X2TS U30 ( .A(D0[22]), .B(n10), .Y(S[22]) );
CLKAND2X2TS U31 ( .A(D0[23]), .B(n8), .Y(S[23]) );
CLKAND2X2TS U32 ( .A(D0[24]), .B(n9), .Y(S[24]) );
CLKAND2X2TS U33 ( .A(D0[25]), .B(n5), .Y(S[25]) );
CLKAND2X2TS U34 ( .A(D0[26]), .B(n9), .Y(S[26]) );
CLKAND2X2TS U35 ( .A(D0[27]), .B(n10), .Y(S[27]) );
CLKAND2X2TS U36 ( .A(D0[28]), .B(n7), .Y(S[28]) );
CLKAND2X2TS U37 ( .A(D0[29]), .B(n4), .Y(S[29]) );
CLKAND2X2TS U38 ( .A(D0[30]), .B(n7), .Y(S[30]) );
CLKAND2X2TS U39 ( .A(D0[31]), .B(n9), .Y(S[31]) );
CLKAND2X2TS U40 ( .A(D0[32]), .B(n8), .Y(S[32]) );
CLKAND2X2TS U41 ( .A(D0[33]), .B(n5), .Y(S[33]) );
CLKAND2X2TS U42 ( .A(D0[34]), .B(n8), .Y(S[34]) );
CLKAND2X2TS U43 ( .A(D0[35]), .B(n7), .Y(S[35]) );
CLKAND2X2TS U44 ( .A(D0[36]), .B(n10), .Y(S[36]) );
CLKAND2X2TS U45 ( .A(D0[37]), .B(n4), .Y(S[37]) );
CLKAND2X2TS U46 ( .A(D0[38]), .B(n10), .Y(S[38]) );
CLKAND2X2TS U47 ( .A(D0[39]), .B(n8), .Y(S[39]) );
CLKAND2X2TS U48 ( .A(D0[40]), .B(n9), .Y(S[40]) );
CLKAND2X2TS U49 ( .A(D0[41]), .B(n5), .Y(S[41]) );
CLKAND2X2TS U50 ( .A(D0[42]), .B(n9), .Y(S[42]) );
CLKAND2X2TS U51 ( .A(D0[43]), .B(n10), .Y(S[43]) );
CLKAND2X2TS U52 ( .A(D0[44]), .B(n7), .Y(S[44]) );
CLKAND2X2TS U53 ( .A(D0[45]), .B(n4), .Y(S[45]) );
CLKAND2X2TS U54 ( .A(D0[46]), .B(n7), .Y(S[46]) );
CLKAND2X2TS U55 ( .A(D0[47]), .B(n9), .Y(S[47]) );
CLKAND2X2TS U56 ( .A(D0[48]), .B(n8), .Y(S[48]) );
CLKAND2X2TS U57 ( .A(D0[49]), .B(n5), .Y(S[49]) );
CLKAND2X2TS U58 ( .A(D0[50]), .B(n8), .Y(S[50]) );
CLKAND2X2TS U59 ( .A(D0[51]), .B(n7), .Y(S[51]) );
CLKAND2X2TS U60 ( .A(D0[52]), .B(n10), .Y(S[52]) );
CLKAND2X2TS U61 ( .A(D0[53]), .B(n4), .Y(S[53]) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module RegisterAdd_W1_6 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4;
DFFRXLTS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n4), .Q(Q[0]) );
OR2X1TS U2 ( .A(Q[0]), .B(load), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n4) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module RegisterAdd_W1_7 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n4;
DFFRXLTS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n4), .Q(Q[0]) );
INVX2TS U2 ( .A(rst), .Y(n4) );
OR2X1TS U3 ( .A(Q[0]), .B(load), .Y(n3) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_C, add_overflow_flag, round_flag,
FSM_op_start_in_load_a, FSM_op_start_in_load_b,
FSM_exp_operation_load_diff, FSM_exp_operation_load_OU,
FSM_exp_operation_A_S, FSM_barrel_shifter_L_R, FSM_barrel_shifter_B_S,
FSM_Add_Subt_Sgf_load, FSM_LZA_load, FSM_Final_Result_load,
selector_A, load_b, selector_C, selector_D, rst_int, FSM_selector_A,
FSM_selector_D, intAS, real_op, sign_final_result, S_A_S_op, n4,
net10806, net10807, net10808, net10809, net10810, net10811, net10812,
net10813, net10814, net10815, net10816, net10817, net10818, net10819,
net10820, net10821, net10822, net10823, net10824, net10825, net10826,
net10827, net10828, net10829, net10830, net10831, net10832, net10833,
net10834, net10835, net10836, net10837, net10838, net10839, net10840,
net10841, net10842, net10843, net10844, net10845, net10846, net10847,
net10848, net10849, net10850, net10851, net10852, net10853, net10854,
net10855, net10856, net10857, net10858, net10859, net10860, net10861,
net10862, net10863, net10864, net10865, net10866, net10867, net10868,
net10869, net10870, net10871, net10872, net10873, net10874, net10875,
net10876, net10877, net10878, net10879, net10880, net10881, net10882,
net10883, net10884, net10885, net10886, net10887, net10888, net10889,
net10890, net10891, net10892, net10893, net10894, net10895, net10896,
net10897, net10898, net10899, net10900, net10901, net10902, net10903,
net10904, net10905, net10906, net10907, net10908, net10909, net10910,
net10911, net10912, net10913, net10914, net10915, net10916, net10917,
net10918, net10919, net10920, net10921, net10922, net10923, net10924,
net10925, net10926, net10927, net10928, net10929, net10930, net10931,
net10932, net10933, net10934, net10935, net10936, net10937, net10938,
net10939, net10940, net10941, net10942, net10943, net10944, net10945,
net10946, net10947, net10948, net10949, net10950, net10951, net10952,
net10953, net10954, net10955, net10956, net10957, net10958, net10959,
net10960, net10961, net10962, net10963, net10964, net10965, net10966,
net10967, net10968, net10969, net10970, net10971,
SYNOPSYS_UNCONNECTED_1, SYNOPSYS_UNCONNECTED_2,
SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4,
SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6,
SYNOPSYS_UNCONNECTED_7, SYNOPSYS_UNCONNECTED_8,
SYNOPSYS_UNCONNECTED_9, SYNOPSYS_UNCONNECTED_10,
SYNOPSYS_UNCONNECTED_11, SYNOPSYS_UNCONNECTED_12,
SYNOPSYS_UNCONNECTED_13, SYNOPSYS_UNCONNECTED_14,
SYNOPSYS_UNCONNECTED_15, SYNOPSYS_UNCONNECTED_16,
SYNOPSYS_UNCONNECTED_17, SYNOPSYS_UNCONNECTED_18,
SYNOPSYS_UNCONNECTED_19, SYNOPSYS_UNCONNECTED_20,
SYNOPSYS_UNCONNECTED_21, SYNOPSYS_UNCONNECTED_22,
SYNOPSYS_UNCONNECTED_23, SYNOPSYS_UNCONNECTED_24,
SYNOPSYS_UNCONNECTED_25, SYNOPSYS_UNCONNECTED_26,
SYNOPSYS_UNCONNECTED_27, SYNOPSYS_UNCONNECTED_28,
SYNOPSYS_UNCONNECTED_29, SYNOPSYS_UNCONNECTED_30,
SYNOPSYS_UNCONNECTED_31, SYNOPSYS_UNCONNECTED_32,
SYNOPSYS_UNCONNECTED_33, SYNOPSYS_UNCONNECTED_34,
SYNOPSYS_UNCONNECTED_35, SYNOPSYS_UNCONNECTED_36,
SYNOPSYS_UNCONNECTED_37, SYNOPSYS_UNCONNECTED_38,
SYNOPSYS_UNCONNECTED_39, SYNOPSYS_UNCONNECTED_40,
SYNOPSYS_UNCONNECTED_41, SYNOPSYS_UNCONNECTED_42,
SYNOPSYS_UNCONNECTED_43, SYNOPSYS_UNCONNECTED_44,
SYNOPSYS_UNCONNECTED_45, SYNOPSYS_UNCONNECTED_46,
SYNOPSYS_UNCONNECTED_47, SYNOPSYS_UNCONNECTED_48,
SYNOPSYS_UNCONNECTED_49, SYNOPSYS_UNCONNECTED_50,
SYNOPSYS_UNCONNECTED_51, SYNOPSYS_UNCONNECTED_52;
wire [1:0] selector_B;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [10:0] S_Oper_A_exp;
wire [10:0] S_Oper_B_exp;
wire [5:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] S_A_S_Oper_A;
wire [54:0] S_A_S_Oper_B;
wire [54:0] Add_Subt_LZD;
assign final_result_ieee[51] = 1'b0;
assign final_result_ieee[50] = 1'b0;
assign final_result_ieee[49] = 1'b0;
assign final_result_ieee[48] = 1'b0;
assign final_result_ieee[47] = 1'b0;
assign final_result_ieee[46] = 1'b0;
assign final_result_ieee[45] = 1'b0;
assign final_result_ieee[44] = 1'b0;
assign final_result_ieee[43] = 1'b0;
assign final_result_ieee[42] = 1'b0;
assign final_result_ieee[41] = 1'b0;
assign final_result_ieee[40] = 1'b0;
assign final_result_ieee[39] = 1'b0;
assign final_result_ieee[38] = 1'b0;
assign final_result_ieee[37] = 1'b0;
assign final_result_ieee[36] = 1'b0;
assign final_result_ieee[35] = 1'b0;
assign final_result_ieee[34] = 1'b0;
assign final_result_ieee[33] = 1'b0;
assign final_result_ieee[32] = 1'b0;
assign final_result_ieee[31] = 1'b0;
assign final_result_ieee[30] = 1'b0;
assign final_result_ieee[29] = 1'b0;
assign final_result_ieee[28] = 1'b0;
assign final_result_ieee[27] = 1'b0;
assign final_result_ieee[26] = 1'b0;
assign final_result_ieee[25] = 1'b0;
assign final_result_ieee[24] = 1'b0;
assign final_result_ieee[23] = 1'b0;
assign final_result_ieee[22] = 1'b0;
assign final_result_ieee[21] = 1'b0;
assign final_result_ieee[20] = 1'b0;
assign final_result_ieee[19] = 1'b0;
assign final_result_ieee[18] = 1'b0;
assign final_result_ieee[17] = 1'b0;
assign final_result_ieee[16] = 1'b0;
assign final_result_ieee[15] = 1'b0;
assign final_result_ieee[14] = 1'b0;
assign final_result_ieee[13] = 1'b0;
assign final_result_ieee[12] = 1'b0;
assign final_result_ieee[11] = 1'b0;
assign final_result_ieee[10] = 1'b0;
assign final_result_ieee[9] = 1'b0;
assign final_result_ieee[8] = 1'b0;
assign final_result_ieee[7] = 1'b0;
assign final_result_ieee[6] = 1'b0;
assign final_result_ieee[5] = 1'b0;
assign final_result_ieee[4] = 1'b0;
assign final_result_ieee[3] = 1'b0;
assign final_result_ieee[2] = 1'b0;
assign final_result_ieee[1] = 1'b0;
assign final_result_ieee[0] = 1'b0;
FSM_Add_Subtract FS_Module ( .clk(clk), .rst(rst), .rst_FSM(ack_FSM),
.beg_FSM(beg_FSM), .zero_flag_i(zero_flag), .norm_iteration_i(
FSM_selector_C), .add_overflow_i(add_overflow_flag), .round_i(
round_flag), .load_1_o(FSM_op_start_in_load_a), .load_2_o(
FSM_op_start_in_load_b), .load_3_o(FSM_exp_operation_load_diff),
.load_8_o(FSM_exp_operation_load_OU), .A_S_op_o(FSM_exp_operation_A_S),
.left_right_o(FSM_barrel_shifter_L_R), .bit_shift_o(
FSM_barrel_shifter_B_S), .load_5_o(FSM_Add_Subt_Sgf_load), .load_6_o(
FSM_LZA_load), .load_7_o(FSM_Final_Result_load), .ctrl_a_o(selector_A),
.ctrl_b_o(selector_B), .ctrl_b_load_o(load_b), .ctrl_c_o(selector_C),
.ctrl_d_o(selector_D), .rst_int(rst_int), .ready(ready) );
RegisterAdd_W1_8 Sel_A ( .clk(clk), .rst(rst_int), .load(selector_A), .D(
1'b1), .Q(FSM_selector_A) );
RegisterAdd_W1_7 Sel_C ( .clk(clk), .rst(rst_int), .load(selector_C), .D(
1'b1), .Q(FSM_selector_C) );
RegisterAdd_W1_6 Sel_D ( .clk(clk), .rst(rst_int), .load(selector_D), .D(
1'b1), .Q(FSM_selector_D) );
RegisterAdd Sel_B ( .clk(clk), .rst(rst_int), .load(load_b), .D(selector_B),
.Q(FSM_selector_B) );
RegisterAdd_W64_2 XRegister ( .clk(clk), .rst(rst), .load(n4), .D(Data_X),
.Q(intDX) );
RegisterAdd_W64_1 YRegister ( .clk(clk), .rst(rst), .load(n4), .D(Data_Y),
.Q(intDY) );
RegisterAdd_W1_1 ASRegister ( .clk(clk), .rst(rst), .load(n4), .D(add_subt),
.Q(intAS) );
Oper_Start_In_2 Oper_Start_in_module ( .clk(clk), .rst(rst), .load_b_i(
FSM_op_start_in_load_b), .intAS(intAS), .intDX(intDX), .intDY(intDY),
.DMP_o(DMP), .DmP_o(DmP), .zero_flag_o(zero_flag), .real_op_o(real_op),
.sign_final_result_o(sign_final_result) );
Multiplexer_AC_W11_1 Exp_Oper_A_mux ( .ctrl(FSM_selector_A), .D0(DMP[62:52]),
.D1(exp_oper_result), .S(S_Oper_A_exp) );
Mux_3x1_W11 Exp_Oper_B_mux ( .ctrl(FSM_selector_B), .D0(DmP[62:52]), .D1({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, LZA_output}), .D2({1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}), .S(S_Oper_B_exp) );
Exp_Operation_EW11 Exp_Operation_Module ( .clk(clk), .rst(rst), .load_a_i(
FSM_exp_operation_load_diff), .load_b_i(FSM_exp_operation_load_OU),
.Data_A_i(S_Oper_A_exp), .Data_B_i(S_Oper_B_exp), .Add_Subt_i(
FSM_exp_operation_A_S), .Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag), .Underflow_flag_o(underflow_flag) );
Multiplexer_AC_W1_439 Add_Sub_Sgf_op_mux ( .ctrl(FSM_selector_D), .D0(
real_op), .D1(1'b0), .S(S_A_S_op) );
Multiplexer_AC_W55_1 Add_Sub_Sgf_Oper_A_mux ( .ctrl(FSM_selector_D), .D0({
1'b1, DMP[51:0], 1'b0, 1'b0}), .D1({net10917, net10918, net10919,
net10920, net10921, net10922, net10923, net10924, net10925, net10926,
net10927, net10928, net10929, net10930, net10931, net10932, net10933,
net10934, net10935, net10936, net10937, net10938, net10939, net10940,
net10941, net10942, net10943, net10944, net10945, net10946, net10947,
net10948, net10949, net10950, net10951, net10952, net10953, net10954,
net10955, net10956, net10957, net10958, net10959, net10960, net10961,
net10962, net10963, net10964, net10965, net10966, net10967, net10968,
net10969, net10970, net10971}), .S(S_A_S_Oper_A) );
Multiplexer_AC_W55_0 Add_Sub_Sgf_Oper_B_mux ( .ctrl(FSM_selector_D), .D0({
net10862, net10863, net10864, net10865, net10866, net10867, net10868,
net10869, net10870, net10871, net10872, net10873, net10874, net10875,
net10876, net10877, net10878, net10879, net10880, net10881, net10882,
net10883, net10884, net10885, net10886, net10887, net10888, net10889,
net10890, net10891, net10892, net10893, net10894, net10895, net10896,
net10897, net10898, net10899, net10900, net10901, net10902, net10903,
net10904, net10905, net10906, net10907, net10908, net10909, net10910,
net10911, net10912, net10913, net10914, net10915, net10916}), .D1({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0}), .S(S_A_S_Oper_B) );
Add_Subt Add_Subt_Sgf_module ( .clk(clk), .rst(rst), .load_i(
FSM_Add_Subt_Sgf_load), .Add_Sub_op_i(S_A_S_op), .Data_A_i(
S_A_S_Oper_A), .PreData_B_i(S_A_S_Oper_B), .Data_Result_o(
Add_Subt_result), .FSM_C_o(add_overflow_flag) );
LZD_SWR55_EWR6 Leading_Zero_Detector_Module ( .clk(clk), .rst(rst), .load_i(
FSM_LZA_load), .Add_subt_result_i(Add_Subt_LZD), .Shift_Value_o(
LZA_output) );
Round_Sgf_Dec Rounding_Decoder ( .Data_i({net10858, net10859}),
.Round_Type_i({net10860, net10861}), .Sign_Result_i(sign_final_result),
.Round_Flag_o(round_flag) );
Tenth_Phase_W64_EW11_SW52 final_result_ieee_Module ( .clk(clk), .rst(rst),
.load_i(FSM_Final_Result_load), .sel_a_i(overflow_flag), .sel_b_i(
underflow_flag), .sign_i(sign_final_result), .exp_ieee_i(
exp_oper_result), .sgf_ieee_i({net10806, net10807, net10808, net10809,
net10810, net10811, net10812, net10813, net10814, net10815, net10816,
net10817, net10818, net10819, net10820, net10821, net10822, net10823,
net10824, net10825, net10826, net10827, net10828, net10829, net10830,
net10831, net10832, net10833, net10834, net10835, net10836, net10837,
net10838, net10839, net10840, net10841, net10842, net10843, net10844,
net10845, net10846, net10847, net10848, net10849, net10850, net10851,
net10852, net10853, net10854, net10855, net10856, net10857}),
.final_result_ieee_o({final_result_ieee[63:52], SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4,
SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6, SYNOPSYS_UNCONNECTED_7,
SYNOPSYS_UNCONNECTED_8, SYNOPSYS_UNCONNECTED_9,
SYNOPSYS_UNCONNECTED_10, SYNOPSYS_UNCONNECTED_11,
SYNOPSYS_UNCONNECTED_12, SYNOPSYS_UNCONNECTED_13,
SYNOPSYS_UNCONNECTED_14, SYNOPSYS_UNCONNECTED_15,
SYNOPSYS_UNCONNECTED_16, SYNOPSYS_UNCONNECTED_17,
SYNOPSYS_UNCONNECTED_18, SYNOPSYS_UNCONNECTED_19,
SYNOPSYS_UNCONNECTED_20, SYNOPSYS_UNCONNECTED_21,
SYNOPSYS_UNCONNECTED_22, SYNOPSYS_UNCONNECTED_23,
SYNOPSYS_UNCONNECTED_24, SYNOPSYS_UNCONNECTED_25,
SYNOPSYS_UNCONNECTED_26, SYNOPSYS_UNCONNECTED_27,
SYNOPSYS_UNCONNECTED_28, SYNOPSYS_UNCONNECTED_29,
SYNOPSYS_UNCONNECTED_30, SYNOPSYS_UNCONNECTED_31,
SYNOPSYS_UNCONNECTED_32, SYNOPSYS_UNCONNECTED_33,
SYNOPSYS_UNCONNECTED_34, SYNOPSYS_UNCONNECTED_35,
SYNOPSYS_UNCONNECTED_36, SYNOPSYS_UNCONNECTED_37,
SYNOPSYS_UNCONNECTED_38, SYNOPSYS_UNCONNECTED_39,
SYNOPSYS_UNCONNECTED_40, SYNOPSYS_UNCONNECTED_41,
SYNOPSYS_UNCONNECTED_42, SYNOPSYS_UNCONNECTED_43,
SYNOPSYS_UNCONNECTED_44, SYNOPSYS_UNCONNECTED_45,
SYNOPSYS_UNCONNECTED_46, SYNOPSYS_UNCONNECTED_47,
SYNOPSYS_UNCONNECTED_48, SYNOPSYS_UNCONNECTED_49,
SYNOPSYS_UNCONNECTED_50, SYNOPSYS_UNCONNECTED_51,
SYNOPSYS_UNCONNECTED_52}) );
INVX2TS U27 ( .A(Add_Subt_result[23]), .Y(Add_Subt_LZD[23]) );
INVX2TS U28 ( .A(Add_Subt_result[24]), .Y(Add_Subt_LZD[24]) );
INVX2TS U29 ( .A(Add_Subt_result[25]), .Y(Add_Subt_LZD[25]) );
INVX2TS U30 ( .A(Add_Subt_result[26]), .Y(Add_Subt_LZD[26]) );
INVX2TS U31 ( .A(Add_Subt_result[27]), .Y(Add_Subt_LZD[27]) );
INVX2TS U32 ( .A(Add_Subt_result[28]), .Y(Add_Subt_LZD[28]) );
INVX2TS U33 ( .A(Add_Subt_result[29]), .Y(Add_Subt_LZD[29]) );
INVX2TS U35 ( .A(Add_Subt_result[31]), .Y(Add_Subt_LZD[31]) );
INVX2TS U34 ( .A(Add_Subt_result[30]), .Y(Add_Subt_LZD[30]) );
INVX2TS U44 ( .A(Add_Subt_result[40]), .Y(Add_Subt_LZD[40]) );
INVX2TS U46 ( .A(Add_Subt_result[42]), .Y(Add_Subt_LZD[42]) );
INVX2TS U43 ( .A(Add_Subt_result[39]), .Y(Add_Subt_LZD[39]) );
INVX2TS U45 ( .A(Add_Subt_result[41]), .Y(Add_Subt_LZD[41]) );
INVX2TS U48 ( .A(Add_Subt_result[44]), .Y(Add_Subt_LZD[44]) );
INVX2TS U49 ( .A(Add_Subt_result[45]), .Y(Add_Subt_LZD[45]) );
INVX2TS U47 ( .A(Add_Subt_result[43]), .Y(Add_Subt_LZD[43]) );
INVX2TS U50 ( .A(Add_Subt_result[46]), .Y(Add_Subt_LZD[46]) );
INVX2TS U52 ( .A(Add_Subt_result[48]), .Y(Add_Subt_LZD[48]) );
INVX2TS U53 ( .A(Add_Subt_result[49]), .Y(Add_Subt_LZD[49]) );
INVX2TS U51 ( .A(Add_Subt_result[47]), .Y(Add_Subt_LZD[47]) );
INVX2TS U54 ( .A(Add_Subt_result[50]), .Y(Add_Subt_LZD[50]) );
INVX2TS U57 ( .A(Add_Subt_result[53]), .Y(Add_Subt_LZD[53]) );
INVX2TS U58 ( .A(Add_Subt_result[54]), .Y(Add_Subt_LZD[54]) );
INVX2TS U56 ( .A(Add_Subt_result[52]), .Y(Add_Subt_LZD[52]) );
INVX2TS U55 ( .A(Add_Subt_result[51]), .Y(Add_Subt_LZD[51]) );
INVX2TS U40 ( .A(Add_Subt_result[36]), .Y(Add_Subt_LZD[36]) );
INVX2TS U41 ( .A(Add_Subt_result[37]), .Y(Add_Subt_LZD[37]) );
INVX2TS U39 ( .A(Add_Subt_result[35]), .Y(Add_Subt_LZD[35]) );
INVX2TS U42 ( .A(Add_Subt_result[38]), .Y(Add_Subt_LZD[38]) );
INVX2TS U36 ( .A(Add_Subt_result[32]), .Y(Add_Subt_LZD[32]) );
INVX2TS U38 ( .A(Add_Subt_result[34]), .Y(Add_Subt_LZD[34]) );
INVX2TS U37 ( .A(Add_Subt_result[33]), .Y(Add_Subt_LZD[33]) );
INVX2TS U18 ( .A(Add_Subt_result[14]), .Y(Add_Subt_LZD[14]) );
INVX2TS U17 ( .A(Add_Subt_result[13]), .Y(Add_Subt_LZD[13]) );
INVX2TS U19 ( .A(Add_Subt_result[15]), .Y(Add_Subt_LZD[15]) );
INVX2TS U20 ( .A(Add_Subt_result[16]), .Y(Add_Subt_LZD[16]) );
INVX2TS U21 ( .A(Add_Subt_result[17]), .Y(Add_Subt_LZD[17]) );
INVX2TS U22 ( .A(Add_Subt_result[18]), .Y(Add_Subt_LZD[18]) );
INVX2TS U23 ( .A(Add_Subt_result[19]), .Y(Add_Subt_LZD[19]) );
INVX2TS U24 ( .A(Add_Subt_result[20]), .Y(Add_Subt_LZD[20]) );
INVX2TS U25 ( .A(Add_Subt_result[21]), .Y(Add_Subt_LZD[21]) );
INVX2TS U26 ( .A(Add_Subt_result[22]), .Y(Add_Subt_LZD[22]) );
INVX2TS U16 ( .A(Add_Subt_result[12]), .Y(Add_Subt_LZD[12]) );
INVX2TS U12 ( .A(Add_Subt_result[8]), .Y(Add_Subt_LZD[8]) );
INVX2TS U13 ( .A(Add_Subt_result[9]), .Y(Add_Subt_LZD[9]) );
INVX2TS U14 ( .A(Add_Subt_result[10]), .Y(Add_Subt_LZD[10]) );
INVX2TS U11 ( .A(Add_Subt_result[7]), .Y(Add_Subt_LZD[7]) );
INVX2TS U15 ( .A(Add_Subt_result[11]), .Y(Add_Subt_LZD[11]) );
INVX2TS U10 ( .A(Add_Subt_result[6]), .Y(Add_Subt_LZD[6]) );
INVX2TS U9 ( .A(Add_Subt_result[5]), .Y(Add_Subt_LZD[5]) );
INVX2TS U8 ( .A(Add_Subt_result[4]), .Y(Add_Subt_LZD[4]) );
INVX2TS U7 ( .A(Add_Subt_result[3]), .Y(Add_Subt_LZD[3]) );
INVX2TS U6 ( .A(Add_Subt_result[2]), .Y(Add_Subt_LZD[2]) );
INVX2TS U5 ( .A(Add_Subt_result[1]), .Y(Add_Subt_LZD[1]) );
INVX2TS U4 ( .A(Add_Subt_result[0]), .Y(Add_Subt_LZD[0]) );
CLKBUFX2TS U60 ( .A(FSM_op_start_in_load_a), .Y(n4) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_minimac();
/* 100MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 25MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #20 phy_rx_clk = ~phy_rx_clk;
/* 25MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #20 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire [31:0] wbrx_adr_o;
wire [2:0] wbrx_cti_o;
wire wbrx_cyc_o;
wire wbrx_stb_o;
reg wbrx_ack_i;
wire [31:0] wbrx_dat_o;
wire [31:0] wbtx_adr_o;
wire [2:0] wbtx_cti_o;
wire wbtx_cyc_o;
wire wbtx_stb_o;
reg wbtx_ack_i;
reg [31:0] wbtx_dat_i;
reg [3:0] phy_rx_data;
reg phy_dv;
reg phy_rx_er;
wire phy_tx_en;
wire [3:0] phy_tx_data;
wire irq_rx;
wire irq_tx;
minimac #(
.csr_addr(4'h0)
) ethernet (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.wbrx_adr_o(wbrx_adr_o),
.wbrx_cti_o(wbrx_cti_o),
.wbrx_cyc_o(wbrx_cyc_o),
.wbrx_stb_o(wbrx_stb_o),
.wbrx_ack_i(wbrx_ack_i),
.wbrx_dat_o(wbrx_dat_o),
.wbtx_adr_o(wbtx_adr_o),
.wbtx_cti_o(wbtx_cti_o),
.wbtx_cyc_o(wbtx_cyc_o),
.wbtx_stb_o(wbtx_stb_o),
.wbtx_ack_i(wbtx_ack_i),
.wbtx_dat_i(wbtx_dat_i),
.irq_rx(irq_rx),
.irq_tx(irq_tx),
.phy_tx_clk(phy_tx_clk),
.phy_tx_data(phy_tx_data),
.phy_tx_en(phy_tx_en),
.phy_tx_er(),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.phy_col(),
.phy_crs(),
.phy_mii_clk(),
.phy_mii_data()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
always @(posedge sys_clk) begin
if(wbrx_cyc_o & wbrx_stb_o & ~wbrx_ack_i & (($random % 5) == 0)) begin
$display("Write: %x <- %x", wbrx_adr_o, wbrx_dat_o);
wbrx_ack_i = 1'b1;
end else
wbrx_ack_i = 1'b0;
end
always @(posedge sys_clk) begin
if(wbtx_cyc_o & wbtx_stb_o & ~wbtx_ack_i & (($random % 5) == 0)) begin
wbtx_dat_i = $random;
$display("Read : %x -> %x", wbtx_adr_o, wbtx_dat_i);
wbtx_ack_i = 1'b1;
end else
wbtx_ack_i = 1'b0;
end
always @(posedge phy_rx_clk) begin
phy_rx_er <= 1'b0;
phy_rx_data <= $random;
if(phy_dv) begin
//$display("rx: %x", phy_rx_data);
if(($random % 125) == 0) begin
phy_dv <= 1'b0;
//$display("** stopping transmission");
end
end else begin
if(($random % 12) == 0) begin
phy_dv <= 1'b1;
//$display("** starting transmission");
end
end
end
always @(posedge phy_tx_clk) begin
if(phy_tx_en)
$display("tx: %x", phy_tx_data);
end
initial begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
phy_dv = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
/*csrwrite(32'h00, 0);
csrwrite(32'h0C, 32'h10000000);
csrwrite(32'h08, 1);
#3000;
csrread(32'h00);
csrread(32'h14);
csrread(32'h20);
csrread(32'h2C);
csrread(32'h38);*/
waitclock;
waitclock;
waitclock;
waitclock;
csrwrite(32'h00, 1);
csrwrite(32'h3C, 72);
csrread(32'h3C);
@(posedge irq_tx);
#30000;
$finish;
end
endmodule
|
`include "alu4bit.v"
module tb4alu;
reg [3:0] A, B;
reg CIN, BINV;
reg [1:0] OP;
wire COUT;
wire [3:0] Y;
alu4bit alu4bit00 (A, B, CIN, BINV, OP, COUT, Y);
initial begin
A = 4'b0000;
B = 4'b0000;
CIN = 1'b0;
BINV = 1'b0;
OP = 2'b00;
#10
A = 4'b0101;
B = 4'b1111;
OP = 2'b00;
#10
A = 4'b1010;
B = 4'b1111;
OP = 2'b00;
#10
A = 4'b0101;
B = 4'b0000;
OP = 2'b01;
#10
A = 4'b1010;
B = 4'b0000;
OP = 2'b01;
#10
A = 4'b0111;
B = 4'b0101;
CIN = 1'b0;
BINV = 1'b0;
OP = 2'b10;
#10
A = 4'b0100;
B = 4'b0010;
CIN = 1'b1;
BINV = 1'b0;
OP = 2'b10;
#10
A = 4'b0101;
B = 4'b0010;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b10;
#10
A = 4'b0100;
B = 4'b0101;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b10;
#10
A = 4'b0111;
B = 4'b0110;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b11;
#10
A = 4'b0011;
B = 4'b0111;
CIN = 1'b1;
BINV = 1'b1;
OP = 2'b11;
#10
$stop;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:33:12 03/30/2015
// Design Name:
// Module Name: CU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CU(CU_in,MBR_we,IR_we,PC_inc,PC_jump,RF_we,Acc_we,MAR_we,RAM_we,
ALU_mux,RF_mux,ALU_out_mux,MAR_mux,MBR_mux,Select,Func,CU_clk,State,
Zero, Sign, Overflow, Carry,Update,SP_en,RAM_in,SP_inc,SP_dec,Condition_update
);
input[7:0] CU_in;
output MBR_we,IR_we,PC_inc,PC_jump,RF_we,Acc_we,MAR_we,RAM_we,ALU_mux,RF_mux,ALU_out_mux,MAR_mux,MBR_mux,Update,SP_en,SP_inc,SP_dec,Condition_update;
output[2:0] Select,Func;
output[1:0] RAM_in;
input CU_clk;
output[7:0] State;
input Zero, Sign, Overflow, Carry;
reg MBR_we,IR_we,PC_inc,PC_jump,RF_we,Acc_we,MAR_we,RAM_we,ALU_mux,RF_mux,ALU_out_mux,MAR_mux,MBR_mux,Update,SP_en,SP_inc,SP_dec,Condition_update;
reg[2:0] Select,Func;
reg[1:0] RAM_in;
reg[7:0] State=0,nextstate;
parameter s0=0, s1=1, s2=2, s3=3, s4=4, s5=5, s6=6, s7=7, s8=8, s9=9, s10=10, s11=11, s12=12, s13=13, s14=14, s15=15,
s16=16, s17=17, s18=18, s19=19, s20=20, s21=21, s22=22, s23=23, s24=24, s25=25, s26=26, s27=27, s28=28,
s29=29, s30=30, s31=31, s32=32, s33=33, s34=34, s35=35, s36=36, s37=37, s38=38, s39=39, s40=40;
always @(posedge CU_clk)
begin
State <= nextstate;
end
always @(State)
begin
case(State)
s0:
begin
RAM_we=0;
MBR_we=0;
IR_we=0;
PC_inc=0;
PC_jump=0;
RF_we=0;
Acc_we=0;
MAR_we=1;
ALU_mux=0;
RF_mux=0;
ALU_out_mux=0;
MAR_mux=0;
MBR_mux=0;
Update=0;
RAM_in=2'b00;
SP_en=0;
SP_inc=0;
SP_dec=0;
Condition_update = 0;
nextstate = s1; //PAPAM
end
s1:
begin
MBR_we=1;
PC_inc=1;
MAR_we=0;
nextstate = s2;
end
s2:
begin
MBR_we=0;
IR_we=1;
PC_inc=0;
nextstate=s3;
end
s3: //Decoder
begin
IR_we=0;
if( CU_in[7:6] == 2'b00)
begin
if( (CU_in[5:3]==3'b111) || (CU_in[2:0] == 3'b111) )
nextstate = s6; // MOV M REG || MOV REG M
else
nextstate = s4; // MOV REG REG
end
else if(CU_in[7:6] == 2'b01)
begin
if(CU_in[2:0] == 3'b111)
nextstate = s13; // ADD M
else
nextstate = s12;// ADD REG
end
else if(CU_in[7:6] == 2'b10)
begin
if(CU_in[5:3] == 3'b111)
nextstate = s16; //MVI
else
nextstate =s19; // ADDI
end
else
begin
if(CU_in[5] == 0)
nextstate = s24; // JUMP UNCONDITIONAL
if(CU_in[5:0] == 6'b111111)
nextstate = s11; // HALT
else if(CU_in[5:0] == 6'b111001) //CALL
nextstate = s24;
else if(CU_in[5:0] == 6'b111000) // PUSH
nextstate = s9;
else if(CU_in[5:0] == 6'b111010) // POP
begin
nextstate = s7;
SP_dec=1;
end
else if(CU_in[5:0] == 6'b111100)//NOP
begin
nextstate = s0;
end
else if(CU_in[5:0] == 6'b111011)//RETURN
begin
nextstate = s36;
SP_dec=1;
end
else
begin
if(CU_in[4:3] == 2'b00)
nextstate = Zero ? s24: s31; // JUMP ON EQUAL
else if(CU_in[4:3] == 2'b01)
nextstate = Zero ? s31: (Sign ? s24: s31); // JUMP ON LESS THAN
else if(CU_in[4:3] == 2'b10)
nextstate = Zero ? s31: (Sign ? s31: s24); // JUMP ON GREATER THAN
end
end
end
s4:
begin
Acc_we=1;
ALU_out_mux=1;
Select = CU_in[2:0];
nextstate = s5;
end
s5:
begin
RF_we=1;
Acc_we=0;
RF_mux= 1;
ALU_out_mux=0;
Select = CU_in[5:3];
nextstate = s0;
end
s6: //MAR <= FG
begin
MAR_we=1;
MAR_mux=1;
if(CU_in[2:0] == 3'b111)
nextstate = s7;
else
nextstate = s9;
end
s7: //MBR <= RAM[MAR]
begin
MBR_we=1;
MAR_we=0;
MAR_mux=0;
if(CU_in[7:0] == 8'b11111010)
begin
SP_en=1;
SP_dec=0;
end
nextstate = s8;
end
s8: //REG <= MBR
begin
MBR_we=0;
RF_we=1;
Select = CU_in[5:3];
if(CU_in[7:0] == 8'b11111010)
begin
Select = 3'b000;
end
SP_en=0;
nextstate = s0;
end
s9: //MBR <= REG
begin
MBR_we=1;
MAR_we=0;
MAR_mux=0;
MBR_mux=1;
Select = CU_in[2:0];
nextstate = s10;
end
s10: //RAM[MAR] <= MBR
begin
RAM_we=1;
MBR_we=0;
MBR_mux=0;
if(CU_in[7:0] == 8'b11111000)
begin
SP_en=1;
SP_inc=1;
end
nextstate = s0;
end
s11: //halt
begin
nextstate = s11;
end
s12: // Alu reg
begin
Acc_we=1;
ALU_mux=1;
Select = CU_in[2:0];
Func = CU_in[5:3];
Update = 1;
nextstate = s0;
end
s13:
begin
MAR_we=1;
MAR_mux=1;
nextstate = s14;
end
s14:
begin
MBR_we=1;
MAR_we=0;
MAR_mux=0;
nextstate = s15;
end
s15:
begin
MBR_we=0;
Acc_we=1;
Func = CU_in[5:3];
Update = 1;
nextstate = s0;
end
s16: //MAR <= PC
begin
MAR_we=1;
Select = CU_in[2:0];
nextstate = s17;
end
s17: //MBR <= RAM[MAR] , PC++
begin
MBR_we=1;
PC_inc=1;
MAR_we=0;
nextstate = s18;
end
s18:
begin
MBR_we=0;
PC_inc=0;
RF_we=1;
nextstate = s0;
end
s19: // ACC <= REG
begin
Acc_we=1;
ALU_out_mux=1;
Select = CU_in[2:0];
nextstate = s20;
end
s20: //MAR <=PC
begin
Acc_we=0;
MAR_we=1;
ALU_out_mux=0;
Func = CU_in[5:3];
nextstate = s21;
end
s21:
begin
MBR_we=1;
PC_inc=1;
MAR_we=0;
nextstate = s22;
end
s22:
begin
MBR_we=0;
PC_inc=0;
Acc_we=1;
nextstate = s23;
end
s23:
begin
RF_we=1;
Acc_we=0;
RF_mux=1;
nextstate = s0;
end
s24: //MAR = PC
begin
MAR_we=1;
RAM_in=2'b00;
SP_en=0;
SP_inc=0;
nextstate = s25;
end
s25: // MBR = RAM
begin
MBR_we=1;
PC_inc=1;
MAR_we=0;
nextstate = s26;
end
s26: //F = MBR
begin
MBR_we=0;
PC_inc=0;
RF_we=1;
Select = 3'b101;
nextstate = s27;
end
s27:
begin
RF_we=0;
MAR_we=1;
nextstate = s28;
end
s28:
begin
MBR_we=1;
PC_inc=1;
MAR_we=0;
nextstate = s29;
end
s29:
begin
MBR_we=0;
PC_inc=0;
RF_we=1;
Select = 3'b110;
if(CU_in[5:0] == 6'b111001)
nextstate = s33;
else
nextstate = s30;
end
s30:
begin
RAM_we=0;
PC_jump=1;
RF_we=0;
RAM_in=2'b00;
SP_en=0;
SP_inc=0;
nextstate = s0;
end
s31: // PC++
begin
PC_inc=1;
nextstate = s32;
end
s32: //PC++
begin
nextstate = s0;
end
s33:
begin
RAM_we=1;
RF_we=0;
RAM_in=2'b01;
SP_en=1;
SP_inc=1;
nextstate = s34;
end
s34:
begin
RAM_in=2'b10;
nextstate = s35;
end
s35:
begin
RAM_in=2'b11;
nextstate = s30;
end
s36:
begin
SP_en = 1;
SP_dec =1;
Condition_update = 1;
nextstate = s37;
end
s37:
begin
MBR_we=1;
Condition_update = 0;
nextstate = s38;
end
s38:
begin
RF_we=1;
SP_dec = 0;
Select = 3'b101;
nextstate = s39;
end
s39:
begin
MBR_we=0;
SP_en = 0;
Select = 3'b110;
nextstate = s40;
end
s40:
begin
PC_jump=1;
RF_we=0;
nextstate = s0;
end
endcase
end
endmodule
|
// Module m_paper implements all features of the 2-bit paper processor.
module m_paper;
reg r_low = 1'b0; // logic low register
reg r_high = 1'b1; // logic high register
reg r_clock = 1'b0; // clock pulse register
reg r_reset = 1'b1; // reset value register
wire w_low, w_high, w_clock, w_reset; // low, high, clock, and reset wires
assign w_low = r_low; // assign low wire to low register
assign w_high = r_high; // assign high wire to high register
assign w_clock = r_clock; // assign clock wire to clock register
assign w_reset = r_reset; // assign reset wire to reset register
wire [1:0] w_bus_addr; // address bus/program counter output bus)
wire [1:0] w_bus_data; // data bus
wire w_inc, w_jno, w_hlt, w_nop; // inc, jno, hlt, and nop wires
wire [1:0] w_bus_pc_in; // program counter input bus
wire [1:0] w_bus_pr_out, w_bus_pr_in; // program register i/o buses
wire w_sr_out, w_sr_in; // status register i/o wires
m_memory mem_0 (w_bus_data, w_bus_addr); // instantiate memory module
m_program_counter pc_0 (w_bus_addr, w_bus_pc_in, w_clock, w_reset); // instantiate program counter
m_program_register pr_0 (w_bus_pr_out, w_bus_pr_in, w_clock, w_reset); // instantiate program register
m_status_register sr_0 (w_sr_out, w_sr_in, w_clock, w_reset); // instantiate status register
m_opdecode opdc_0 (w_inc, w_jno, w_hlt, w_nop, w_bus_data); // instantiate opdecode module
m_ckt_inc ckt_inc_0 (w_bus_pr_in, w_sr_in, w_bus_pr_out, w_inc, w_low); // instantiate increment circuit
m_ckt_jno ckt_jno_0 (w_bus_pc_in, w_bus_addr, w_bus_data, w_jno, w_sr_out, w_clock, w_reset); // instantiate jump if not overflowed circuit
//m_ckt_hlt ckt_hlt_0 (); // instantiate halt circuit
//m_ckt_nop ckt_nop_0 (); // instantiate no operation circuit
initial begin // do initially:
$dumpfile ("paper.vcd"); // dump output to paper.vcd
$dumpvars (0, m_paper); // dump variables from mpaper module
$monitor ("pc: %b, pr: %b, s: %b, data: %b", w_bus_addr, w_bus_pr_out, w_sr_out, w_bus_data);
#2 r_reset = 1'b0; // wait 2s, reset all circuit elements
end
always #1 begin // every 1s:
r_clock = ~w_clock; // invert clock signal
if (w_hlt) begin
$display ("HLT call: Halting system.");
$finish; // halt simulation if hlt called
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_1_V
`define SKY130_FD_SC_HVL__O21AI_1_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_1_V
|
`include "hglobal.v"
`default_nettype none
`define NS_DBG_NXT_ADDR(adr) ((adr >= MAX_ADDR)?(MIN_ADDR):(adr + 1))
`define NS_DBG_SRC_ADDR 3
`define NS_DBG_INIT_CK 14
`define NS_DBG_INIT_DAT 5
`define NS_DBG_INIT_RED 15
`define NS_DBG_MAX_SRC_CASE 4
module pakout_io
#(parameter
MIN_ADDR=1,
MAX_ADDR=1,
PSZ=`NS_PACKET_SIZE,
FSZ=`NS_PACKIN_FSZ,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input wire src_clk,
input wire snk_clk,
input wire reset,
// SRC_0
`NS_DECLARE_OUT_CHNL(o0),
// SNK_0
`NS_DECLARE_PAKIN_CHNL(i0),
`NS_DECLARE_DBG_CHNL(dbg)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(src_clk, reset, o0)
`NS_DEBOUNCER_REQ(snk_clk, reset, i0)
localparam TOT_PKS = ((`NS_FULL_MSG_SZ / PSZ) + 1);
localparam FIFO_IDX_WIDTH = ((($clog2(FSZ)-1) >= 0)?($clog2(FSZ)-1):(0));
localparam PACKETS_IDX_WIDTH = ((($clog2(TOT_PKS)-1) >= 0)?($clog2(TOT_PKS)-1):(0));
reg [3:0] cnt_0 = `NS_DBG_INIT_DAT;
// SRC regs
reg [0:0] ro0_has_dst = `NS_OFF;
reg [0:0] ro0_has_dat = `NS_OFF;
reg [0:0] ro0_has_red = `NS_OFF;
reg [ASZ-1:0] ro0_src = `NS_DBG_SRC_ADDR;
reg [ASZ-1:0] ro0_dst = MIN_ADDR;
reg [DSZ-1:0] ro0_dat = `NS_DBG_INIT_DAT;
reg [RSZ-1:0] ro0_red = `NS_DBG_INIT_RED;
reg [0:0] ro0_req = `NS_OFF;
wire [RSZ-1:0] ro0_redun;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
r1 (ro0_src, ro0_dst, ro0_dat, ro0_redun);
// SNK_0 regs
reg [0:0] has_inp0 = `NS_OFF;
reg [0:0] inp0_has_redun = `NS_OFF;
reg [0:0] inp0_done_cks = `NS_OFF;
wire [RSZ-1:0] inp0_calc_redun;
reg [RSZ-1:0] inp0_redun = 0;
calc_redun #(.ASZ(ASZ), .DSZ(DSZ), .RSZ(RSZ))
md_calc_red0 (inp0_src, inp0_dst, inp0_dat, inp0_calc_redun);
reg [0:0] inp0_err_0 = `NS_OFF;
reg [0:0] inp0_err_1 = `NS_OFF;
reg [0:0] inp0_err_2 = `NS_OFF;
reg [0:0] inp0_err_3 = `NS_OFF;
reg [0:0] sink_started = 0;
`NS_DECLARE_REG_MSG(inp0)
`NS_DECLARE_FIFO(bf0)
`NS_DECLARE_REG_PACKETS(rgi0)
reg [0:0] rgi0_ack = `NS_OFF;
reg [DSZ-1:0] inp0_bak_dat = 15;
`NS_DECLARE_REG_DBG(rg_dbg)
//SRC_0
always @(posedge src_clk)
begin
if((! ro0_req) && (! o0_ckd_ack)) begin
if(! ro0_has_dst) begin
ro0_has_dst <= `NS_ON;
ro0_dst <= `NS_DBG_NXT_ADDR(ro0_dst);
end
else
if(! ro0_has_dat) begin
ro0_has_dat <= `NS_ON;
ro0_dat[3:0] <= cnt_0;
cnt_0 <= cnt_0 + 1;
end
else
if(! ro0_has_red) begin
ro0_has_red <= `NS_ON;
ro0_red <= ro0_redun;
end
if(ro0_has_red) begin
ro0_req <= `NS_ON;
end
end
if(ro0_req && o0_ckd_ack) begin
ro0_has_dst <= `NS_OFF;
ro0_has_dat <= `NS_OFF;
ro0_has_red <= `NS_OFF;
ro0_req <= `NS_OFF;
end
end
//SNK_0
always @(posedge snk_clk)
begin
if(! sink_started) begin
sink_started <= 1;
inp0_err_0 <= `NS_OFF;
inp0_err_1 <= `NS_OFF;
inp0_err_2 <= `NS_OFF;
inp0_err_3 <= `NS_OFF;
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
`NS_FIFO_INIT(bf0)
`NS_PACKETS_INIT(rgi0, `NS_ON)
rgi0_ack <= `NS_OFF;
end else begin
`NS_PACKIN_TRY_INC(rgi0, i0, bf0, rgi0_ack)
`NS_FIFO_TRY_INC_TAIL(bf0, inp0, has_inp0)
else if(has_inp0) begin
if(! inp0_has_redun) begin
inp0_has_redun <= `NS_ON;
inp0_redun <= inp0_calc_redun;
end
else
if(! inp0_done_cks) begin
inp0_done_cks <= `NS_ON;
if(! inp0_err_0) begin
if(inp0_src != `NS_DBG_SRC_ADDR) begin
inp0_err_0 <= `NS_ON;
rg_dbg_disp0 <= inp0_src[3:0];
end
end
if(! inp0_err_1) begin
if((inp0_bak_dat <= 14) && ((inp0_bak_dat + 1) != inp0_dat)) begin
inp0_err_1 <= `NS_ON;
rg_dbg_disp0 <= inp0_dst[3:0];
end else begin
inp0_bak_dat <= inp0_dat;
end
end
if(! inp0_err_2) begin
if(inp0_red != inp0_redun) begin
inp0_err_2 <= `NS_ON;
rg_dbg_disp0 <= inp0_red[3:0];
end
end
end
if(inp0_done_cks) begin
if(! inp0_err_0 && ! inp0_err_1 && ! inp0_err_2) begin
rg_dbg_disp0 <= inp0_dat[3:0];
rg_dbg_disp1 <= inp0_red[3:0];
end
has_inp0 <= `NS_OFF;
inp0_has_redun <= `NS_OFF;
inp0_done_cks <= `NS_OFF;
end
end
end
end
//SRC_0
`NS_ASSIGN_MSG(o0, ro0)
assign o0_req_out = ro0_req;
//SNK_0
assign i0_ack_out = rgi0_ack;
assign dbg_leds[0:0] = inp0_err_0;
assign dbg_leds[1:1] = inp0_err_1;
assign dbg_leds[2:2] = inp0_err_2;
assign dbg_leds[3:3] = 0;
assign dbg_disp0 = rg_dbg_disp0;
assign dbg_disp1 = rg_dbg_disp1;
endmodule
|
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
/*
Copyright (c) 2015-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* si5324_i2c_init
*/
module si5324_i2c_init (
input wire clk,
input wire rst,
/*
* I2C master interface
*/
output wire [6:0] cmd_address,
output wire cmd_start,
output wire cmd_read,
output wire cmd_write,
output wire cmd_write_multiple,
output wire cmd_stop,
output wire cmd_valid,
input wire cmd_ready,
output wire [7:0] data_out,
output wire data_out_valid,
input wire data_out_ready,
output wire data_out_last,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire start
);
/*
Generic module for I2C bus initialization. Good for use when multiple devices
on an I2C bus must be initialized on system start without intervention of a
general-purpose processor.
Copy this file and change init_data and INIT_DATA_LEN as needed.
This module can be used in two modes: simple device initalization, or multiple
device initialization. In multiple device mode, the same initialization sequence
can be performed on multiple different device addresses.
To use single device mode, only use the start write to address and write data commands.
The module will generate the I2C commands in sequential order. Terminate the list
with a 0 entry.
To use the multiple device mode, use the start data and start address block commands
to set up lists of initialization data and device addresses. The module enters
multiple device mode upon seeing a start data block command. The module stores the
offset of the start of the data block and then skips ahead until it reaches a start
address block command. The module will store the offset to the address block and
read the first address in the block. Then it will jump back to the data block
and execute it, substituting the stored address for each current address write
command. Upon reaching the start address block command, the module will read out the
next address and start again at the top of the data block. If the module encounters
a start data block command while looking for an address, then it will store a new data
offset and then look for a start address block command. Terminate the list with a 0
entry. Normal address commands will operate normally inside a data block.
Commands:
00 0000000 : stop
00 0000001 : exit multiple device mode
00 0000011 : start write to current address
00 0001000 : start address block
00 0001001 : start data block
00 1000001 : send I2C stop
01 aaaaaaa : start write to address
1 dddddddd : write 8-bit data
Examples
write 0x11223344 to register 0x0004 on device at 0x50
01 1010000 start write to 0x50
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
0 00000000 stop
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
00 0001001 start data block
00 0000011 start write to current address
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
00 0001000 start address block
01 1010000 address 0x50
01 1010000 address 0x51
01 1010000 address 0x52
01 1010000 address 0x53
00 0000000 stop
*/
// init_data ROM
localparam INIT_DATA_LEN = 37;
reg [8:0] init_data [INIT_DATA_LEN-1:0];
initial begin
// init Si5324 registers
init_data[0] = {2'b01, 7'h74}; // start write to 0x74 (I2C mux)
init_data[1] = {1'b1, 8'h10}; // select Si5324
init_data[2] = {2'b00, 7'b1000001}; // I2C stop
init_data[3] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[4] = {1'b1, 8'd0}; // register 0
init_data[5] = {1'b1, 8'h54}; // Reg 0: Free run, Clock off before ICAL, Bypass off (normal operation)
init_data[6] = {1'b1, 8'hE4}; // Reg 1: CKIN2 second priority, CKIN1 first priority
init_data[7] = {1'b1, 8'h12}; // Reg 2: BWSEL = 1
init_data[8] = {1'b1, 8'h15}; // Reg 3: CKIN1 selected, Digital Hold off, Output clocks disabled during ICAL
init_data[9] = {1'b1, 8'h92}; // Reg 4: Automatic Revertive, HIST_DEL = 0x12
init_data[10] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[11] = {1'b1, 8'd10}; // register 10
init_data[12] = {1'b1, 8'h08}; // Reg 10: CKOUT2 disabled, CKOUT1 enabled
init_data[13] = {1'b1, 8'h40}; // Reg 11: CKIN2 enabled, CKIN1 enabled
init_data[14] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[15] = {1'b1, 8'd25}; // register 25
init_data[16] = {1'b1, 8'hA0}; // Reg 25: N1_HS = 9
init_data[17] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[18] = {1'b1, 8'd31}; // register 31
init_data[19] = {1'b1, 8'h00}; // Regs 31,32,33: NC1_LS = 4
init_data[20] = {1'b1, 8'h00};
init_data[21] = {1'b1, 8'h03};
init_data[22] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[23] = {1'b1, 8'd40}; // register 40
init_data[24] = {1'b1, 8'hC2}; // Regs 40,41,42: N2_HS = 10, N2_LS = 150000
init_data[25] = {1'b1, 8'h49};
init_data[26] = {1'b1, 8'hEF};
init_data[27] = {1'b1, 8'h00}; // Regs 43,44,45: N31 = 30475
init_data[28] = {1'b1, 8'h77};
init_data[29] = {1'b1, 8'h0B};
init_data[30] = {1'b1, 8'h00}; // Regs 46,47,48: N32 = 30475
init_data[31] = {1'b1, 8'h77};
init_data[32] = {1'b1, 8'h0B};
init_data[33] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[34] = {1'b1, 8'd136}; // register 136
init_data[35] = {1'b1, 8'h40}; // Reg 136: ICAL = 1
init_data[36] = 9'd0; // stop
end
localparam [3:0]
STATE_IDLE = 3'd0,
STATE_RUN = 3'd1,
STATE_TABLE_1 = 3'd2,
STATE_TABLE_2 = 3'd3,
STATE_TABLE_3 = 3'd4;
reg [4:0] state_reg = STATE_IDLE, state_next;
parameter AW = $clog2(INIT_DATA_LEN);
reg [8:0] init_data_reg = 9'd0;
reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;
reg [6:0] cur_address_reg = 7'd0, cur_address_next;
reg [6:0] cmd_address_reg = 7'd0, cmd_address_next;
reg cmd_start_reg = 1'b0, cmd_start_next;
reg cmd_write_reg = 1'b0, cmd_write_next;
reg cmd_stop_reg = 1'b0, cmd_stop_next;
reg cmd_valid_reg = 1'b0, cmd_valid_next;
reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;
reg start_flag_reg = 1'b0, start_flag_next;
reg busy_reg = 1'b0;
assign cmd_address = cmd_address_reg;
assign cmd_start = cmd_start_reg;
assign cmd_read = 1'b0;
assign cmd_write = cmd_write_reg;
assign cmd_write_multiple = 1'b0;
assign cmd_stop = cmd_stop_reg;
assign cmd_valid = cmd_valid_reg;
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = 1'b1;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
address_next = address_reg;
address_ptr_next = address_ptr_reg;
data_ptr_next = data_ptr_reg;
cur_address_next = cur_address_reg;
cmd_address_next = cmd_address_reg;
cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready);
cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready);
cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready);
cmd_valid_next = cmd_valid_reg & ~cmd_ready;
data_out_next = data_out_reg;
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
start_flag_next = start_flag_reg;
if (cmd_valid | data_out_valid) begin
// wait for output registers to clear
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// wait for start signal
if (~start_flag_reg & start) begin
address_next = {AW{1'b0}};
start_flag_next = 1'b1;
state_next = STATE_RUN;
end else begin
state_next = STATE_IDLE;
end
end
STATE_RUN: begin
// process commands
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b001000001) begin
// send stop
cmd_write_next = 1'b0;
cmd_start_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_RUN;
end
end
STATE_TABLE_1: begin
// find address table start
if (init_data_reg == 9'b000001000) begin
// address table start
address_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end
end
STATE_TABLE_2: begin
// find next address
if (init_data_reg[8:7] == 2'b01) begin
// write address command
// store address and move to data table
cur_address_next = init_data_reg[6:0];
address_ptr_next = address_reg + 1;
address_next = data_ptr_reg;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end
end
STATE_TABLE_3: begin
// process data table with selected address
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000000011) begin
// write current address
cmd_address_next = cur_address_reg;
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b001000001) begin
// send stop
cmd_write_next = 1'b0;
cmd_start_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'b000001000) begin
// address table start
address_next = address_ptr_reg;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
init_data_reg <= 9'd0;
address_reg <= {AW{1'b0}};
address_ptr_reg <= {AW{1'b0}};
data_ptr_reg <= {AW{1'b0}};
cur_address_reg <= 7'd0;
cmd_valid_reg <= 1'b0;
data_out_valid_reg <= 1'b0;
start_flag_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
// read init_data ROM
init_data_reg <= init_data[address_next];
address_reg <= address_next;
address_ptr_reg <= address_ptr_next;
data_ptr_reg <= data_ptr_next;
cur_address_reg <= cur_address_next;
cmd_valid_reg <= cmd_valid_next;
data_out_valid_reg <= data_out_valid_next;
start_flag_reg <= start & start_flag_next;
busy_reg <= (state_reg != STATE_IDLE);
end
cmd_address_reg <= cmd_address_next;
cmd_start_reg <= cmd_start_next;
cmd_write_reg <= cmd_write_next;
cmd_stop_reg <= cmd_stop_next;
data_out_reg <= data_out_next;
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : mc_ctrl.v
// Author : Yufeng Bai
// Email : [email protected]
// Created On : 2015-01-19
//
//-------------------------------------------------------------------
//
// Modified : 2015-08-31 by HLL
// Description : mvd added
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module mc_ctrl (
clk ,
rstn ,
mc_start_i ,
mc_done_o ,
mvd_access_o ,
chroma_start_o ,
chroma_sel_o ,
chroma_done_i ,
tq_start_o ,
tq_sel_o ,
tq_done_i
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] mc_start_i ; // mc start
output [1-1:0] mc_done_o ; // mc done
output mvd_access_o ;
output [1-1:0] chroma_start_o ; // chroma interpolation start
output [1-1:0] chroma_sel_o ; // chroma interpolation select: 0:cb, 1:cr
input [1-1:0] chroma_done_i ; // chroma interpolation done
output [1-1:0] tq_start_o ; // tq start
output [2-1:0] tq_sel_o ; // tq sel: 00:luma, 10:cb, 11:cr
input [1-1:0] tq_done_i ; // tq done
// ********************************************
//
// PARAMETER DECLARATION
//
// ********************************************
parameter IDLE = 3'd0;
parameter TQ_LUMA = 3'd1;
parameter MC_CB = 3'd2;
parameter TQ_CB = 3'd3;
parameter MC_CR = 3'd4;
parameter TQ_CR = 3'd5;
parameter DONE = 3'd6;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg [3-1:0] current_state, next_state;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always @(*) begin
next_state = IDLE;
case(current_state)
IDLE : begin
if ( mc_start_i)
next_state = TQ_LUMA;
else
next_state = IDLE;
end
TQ_LUMA: begin
if ( tq_done_i)
next_state = MC_CB;
else
next_state = TQ_LUMA;
end
MC_CB: begin
if ( chroma_done_i)
next_state = TQ_CB;
else
next_state = MC_CB;
end
TQ_CB: begin
if ( tq_done_i)
next_state = MC_CR;
else
next_state = TQ_CB;
end
MC_CR: begin
if ( chroma_done_i)
next_state = TQ_CR;
else
next_state = MC_CR;
end
TQ_CR: begin
if ( tq_done_i)
next_state = DONE;
else
next_state = TQ_CR;
end
DONE: begin
next_state = IDLE;
end
endcase
end
assign mc_done_o = (current_state == DONE);
assign chroma_start_o = (current_state == TQ_LUMA && next_state == MC_CB) ||
(current_state == TQ_CB && next_state == MC_CR) ;
assign chroma_sel_o = (current_state == MC_CR) ? 1'b1 : 1'b0;
assign tq_start_o = (current_state == IDLE && next_state == TQ_LUMA)||
(current_state == MC_CB && next_state == TQ_CB) ||
(current_state == MC_CR && next_state == TQ_CR) ;
assign tq_sel_o = (current_state == TQ_LUMA) ? 2'b00 :
(current_state == TQ_CB ) ? 2'b10 :
(current_state == TQ_CR ) ? 2'b11 : 2'b00;
assign mvd_access_o = ( current_state == TQ_LUMA );
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
current_state <= IDLE;
end
else begin
current_state <= next_state;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_2_V
`define SKY130_FD_SC_MS__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrtp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_2_V
|
`define WIDTH_P 4
/********************************** TEST RATIONALE *************************
1. STATE SPACE
Since the values of the data inputs have little influence on functioning
of the bitwise mux, they are fixed to be 11...1 & 00...0 and not varied.
Hence for each bit, output equals its corresponding select value. The
select input is varied to cover all the bit combinations.
2. PARAMETERIZATION
Since the UUT implements same algorithm for all widths, an arbitrary set
of tests that include edge cases would suffice. So the minimum set of tests
might be WIDTH_P=1,2,3,4.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=0,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", width_p);
end
logic [width_p-1:0] test_input_A,
test_input_B,
test_input_sel,
test_output,
test_input_sel_r;
always_ff @(posedge clk)
begin
if(reset)
begin
test_input_A <= {width_p{1'b1}};
test_input_B <= 0;
test_input_sel <= 0;
end
else
test_input_sel <= test_input_sel+1;
test_input_sel_r <= test_input_sel;
end
always_ff @(posedge clk)
begin
if(!reset)
assert (test_output==test_input_sel)
else $error("mismatch on input %x", test_input_sel);
/*$display("\ntest_input_A: %b test_input_B: %b test_input_sel: %b test_output: %b"
, test_input_A, test_input_B, test_input_sel, test_output);*/
if((&test_input_sel_r) & (~|test_input_sel))
begin
$display("==============================================================\n");
$finish;
end
end
bsg_mux_bitwise #(
.width_p(width_p)
) DUT (
.data0_i(test_input_A)
,.data1_i(test_input_B)
,.sel_i(test_input_sel)
,.data_o(test_output)
);
endmodule
|
module Computer_System (
adc_sclk,
adc_cs_n,
adc_dout,
adc_din,
audio_ADCDAT,
audio_ADCLRCK,
audio_BCLK,
audio_DACDAT,
audio_DACLRCK,
audio_clk_clk,
audio_pll_ref_clk_clk,
audio_pll_ref_reset_reset,
av_config_SDAT,
av_config_SCLK,
expansion_jp1_export,
expansion_jp2_export,
hex3_hex0_export,
hex5_hex4_export,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c0_inst_SDA,
hps_io_hps_io_i2c0_inst_SCL,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO09,
hps_io_hps_io_gpio_inst_GPIO35,
hps_io_hps_io_gpio_inst_GPIO40,
hps_io_hps_io_gpio_inst_GPIO41,
hps_io_hps_io_gpio_inst_GPIO48,
hps_io_hps_io_gpio_inst_GPIO53,
hps_io_hps_io_gpio_inst_GPIO54,
hps_io_hps_io_gpio_inst_GPIO61,
irda_TXD,
irda_RXD,
leds_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
ps2_port_CLK,
ps2_port_DAT,
ps2_port_dual_CLK,
ps2_port_dual_DAT,
pushbuttons_export,
sdram_addr,
sdram_ba,
sdram_cas_n,
sdram_cke,
sdram_cs_n,
sdram_dq,
sdram_dqm,
sdram_ras_n,
sdram_we_n,
sdram_clk_clk,
slider_switches_export,
system_pll_ref_clk_clk,
system_pll_ref_reset_reset,
vga_CLK,
vga_HS,
vga_VS,
vga_BLANK,
vga_SYNC,
vga_R,
vga_G,
vga_B,
vga_pll_ref_clk_clk,
vga_pll_ref_reset_reset,
video_in_TD_CLK27,
video_in_TD_DATA,
video_in_TD_HS,
video_in_TD_VS,
video_in_clk27_reset,
video_in_TD_RESET,
video_in_overflow_flag);
output adc_sclk;
output adc_cs_n;
input adc_dout;
output adc_din;
input audio_ADCDAT;
input audio_ADCLRCK;
input audio_BCLK;
output audio_DACDAT;
input audio_DACLRCK;
output audio_clk_clk;
input audio_pll_ref_clk_clk;
input audio_pll_ref_reset_reset;
inout av_config_SDAT;
output av_config_SCLK;
inout [31:0] expansion_jp1_export;
inout [31:0] expansion_jp2_export;
output [31:0] hex3_hex0_export;
output [15:0] hex5_hex4_export;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_qspi_inst_IO0;
inout hps_io_hps_io_qspi_inst_IO1;
inout hps_io_hps_io_qspi_inst_IO2;
inout hps_io_hps_io_qspi_inst_IO3;
output hps_io_hps_io_qspi_inst_SS0;
output hps_io_hps_io_qspi_inst_CLK;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
output hps_io_hps_io_spim1_inst_CLK;
output hps_io_hps_io_spim1_inst_MOSI;
input hps_io_hps_io_spim1_inst_MISO;
output hps_io_hps_io_spim1_inst_SS0;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
inout hps_io_hps_io_i2c0_inst_SDA;
inout hps_io_hps_io_i2c0_inst_SCL;
inout hps_io_hps_io_i2c1_inst_SDA;
inout hps_io_hps_io_i2c1_inst_SCL;
inout hps_io_hps_io_gpio_inst_GPIO09;
inout hps_io_hps_io_gpio_inst_GPIO35;
inout hps_io_hps_io_gpio_inst_GPIO40;
inout hps_io_hps_io_gpio_inst_GPIO41;
inout hps_io_hps_io_gpio_inst_GPIO48;
inout hps_io_hps_io_gpio_inst_GPIO53;
inout hps_io_hps_io_gpio_inst_GPIO54;
inout hps_io_hps_io_gpio_inst_GPIO61;
output irda_TXD;
input irda_RXD;
output [9:0] leds_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
inout ps2_port_CLK;
inout ps2_port_DAT;
inout ps2_port_dual_CLK;
inout ps2_port_dual_DAT;
input [3:0] pushbuttons_export;
output [12:0] sdram_addr;
output [1:0] sdram_ba;
output sdram_cas_n;
output sdram_cke;
output sdram_cs_n;
inout [15:0] sdram_dq;
output [1:0] sdram_dqm;
output sdram_ras_n;
output sdram_we_n;
output sdram_clk_clk;
input [9:0] slider_switches_export;
input system_pll_ref_clk_clk;
input system_pll_ref_reset_reset;
output vga_CLK;
output vga_HS;
output vga_VS;
output vga_BLANK;
output vga_SYNC;
output [7:0] vga_R;
output [7:0] vga_G;
output [7:0] vga_B;
input vga_pll_ref_clk_clk;
input vga_pll_ref_reset_reset;
input video_in_TD_CLK27;
input [7:0] video_in_TD_DATA;
input video_in_TD_HS;
input video_in_TD_VS;
input video_in_clk27_reset;
output video_in_TD_RESET;
output video_in_overflow_flag;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_1_V
`define SKY130_FD_SC_HD__EDFXTP_1_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog wrapper for edfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__edfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxtp_1 (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__edfxtp_1 (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_1_V
|
// nios_design_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module nios_design_mm_interconnect_0 (
input wire pll_0_outclk0_clk, // pll_0_outclk0.clk
input wire custom_math_0_reset_reset_bridge_in_reset_reset, // custom_math_0_reset_reset_bridge_in_reset.reset
input wire [31:0] custom_math_0_avm_m0_address, // custom_math_0_avm_m0.address
output wire custom_math_0_avm_m0_waitrequest, // .waitrequest
input wire custom_math_0_avm_m0_read, // .read
output wire [31:0] custom_math_0_avm_m0_readdata, // .readdata
input wire custom_math_0_avm_m0_write, // .write
input wire [31:0] custom_math_0_avm_m0_writedata, // .writedata
input wire [18:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
output wire nios2_gen2_0_data_master_readdatavalid, // .readdatavalid
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [18:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire nios2_gen2_0_instruction_master_readdatavalid, // .readdatavalid
output wire [3:0] custom_math_0_avs_s0_address, // custom_math_0_avs_s0.address
output wire custom_math_0_avs_s0_write, // .write
output wire custom_math_0_avs_s0_read, // .read
input wire [31:0] custom_math_0_avs_s0_readdata, // .readdata
output wire [31:0] custom_math_0_avs_s0_writedata, // .writedata
input wire custom_math_0_avs_s0_waitrequest, // .waitrequest
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [15:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [0:0] sysid_qsys_0_control_slave_address, // sysid_qsys_0_control_slave.address
input wire [31:0] sysid_qsys_0_control_slave_readdata, // .readdata
output wire [2:0] timer_0_s1_address, // timer_0_s1.address
output wire timer_0_s1_write, // .write
input wire [15:0] timer_0_s1_readdata, // .readdata
output wire [15:0] timer_0_s1_writedata, // .writedata
output wire timer_0_s1_chipselect // .chipselect
);
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_waitrequest; // custom_math_0_avm_m0_agent:av_waitrequest -> custom_math_0_avm_m0_translator:uav_waitrequest
wire [31:0] custom_math_0_avm_m0_translator_avalon_universal_master_0_readdata; // custom_math_0_avm_m0_agent:av_readdata -> custom_math_0_avm_m0_translator:uav_readdata
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_debugaccess; // custom_math_0_avm_m0_translator:uav_debugaccess -> custom_math_0_avm_m0_agent:av_debugaccess
wire [31:0] custom_math_0_avm_m0_translator_avalon_universal_master_0_address; // custom_math_0_avm_m0_translator:uav_address -> custom_math_0_avm_m0_agent:av_address
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_read; // custom_math_0_avm_m0_translator:uav_read -> custom_math_0_avm_m0_agent:av_read
wire [3:0] custom_math_0_avm_m0_translator_avalon_universal_master_0_byteenable; // custom_math_0_avm_m0_translator:uav_byteenable -> custom_math_0_avm_m0_agent:av_byteenable
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_readdatavalid; // custom_math_0_avm_m0_agent:av_readdatavalid -> custom_math_0_avm_m0_translator:uav_readdatavalid
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_lock; // custom_math_0_avm_m0_translator:uav_lock -> custom_math_0_avm_m0_agent:av_lock
wire custom_math_0_avm_m0_translator_avalon_universal_master_0_write; // custom_math_0_avm_m0_translator:uav_write -> custom_math_0_avm_m0_agent:av_write
wire [31:0] custom_math_0_avm_m0_translator_avalon_universal_master_0_writedata; // custom_math_0_avm_m0_translator:uav_writedata -> custom_math_0_avm_m0_agent:av_writedata
wire [2:0] custom_math_0_avm_m0_translator_avalon_universal_master_0_burstcount; // custom_math_0_avm_m0_translator:uav_burstcount -> custom_math_0_avm_m0_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> custom_math_0_avm_m0_agent:rp_valid
wire [107:0] rsp_mux_src_data; // rsp_mux:src_data -> custom_math_0_avm_m0_agent:rp_data
wire rsp_mux_src_ready; // custom_math_0_avm_m0_agent:rp_ready -> rsp_mux:src_ready
wire [4:0] rsp_mux_src_channel; // rsp_mux:src_channel -> custom_math_0_avm_m0_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> custom_math_0_avm_m0_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> custom_math_0_avm_m0_agent:rp_endofpacket
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [31:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [108:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [108:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [107:0] cmd_mux_src_data; // cmd_mux:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux:src_ready
wire [4:0] cmd_mux_src_channel; // cmd_mux:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [107:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [4:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] custom_math_0_avs_s0_agent_m0_readdata; // custom_math_0_avs_s0_translator:uav_readdata -> custom_math_0_avs_s0_agent:m0_readdata
wire custom_math_0_avs_s0_agent_m0_waitrequest; // custom_math_0_avs_s0_translator:uav_waitrequest -> custom_math_0_avs_s0_agent:m0_waitrequest
wire custom_math_0_avs_s0_agent_m0_debugaccess; // custom_math_0_avs_s0_agent:m0_debugaccess -> custom_math_0_avs_s0_translator:uav_debugaccess
wire [31:0] custom_math_0_avs_s0_agent_m0_address; // custom_math_0_avs_s0_agent:m0_address -> custom_math_0_avs_s0_translator:uav_address
wire [3:0] custom_math_0_avs_s0_agent_m0_byteenable; // custom_math_0_avs_s0_agent:m0_byteenable -> custom_math_0_avs_s0_translator:uav_byteenable
wire custom_math_0_avs_s0_agent_m0_read; // custom_math_0_avs_s0_agent:m0_read -> custom_math_0_avs_s0_translator:uav_read
wire custom_math_0_avs_s0_agent_m0_readdatavalid; // custom_math_0_avs_s0_translator:uav_readdatavalid -> custom_math_0_avs_s0_agent:m0_readdatavalid
wire custom_math_0_avs_s0_agent_m0_lock; // custom_math_0_avs_s0_agent:m0_lock -> custom_math_0_avs_s0_translator:uav_lock
wire [31:0] custom_math_0_avs_s0_agent_m0_writedata; // custom_math_0_avs_s0_agent:m0_writedata -> custom_math_0_avs_s0_translator:uav_writedata
wire custom_math_0_avs_s0_agent_m0_write; // custom_math_0_avs_s0_agent:m0_write -> custom_math_0_avs_s0_translator:uav_write
wire [2:0] custom_math_0_avs_s0_agent_m0_burstcount; // custom_math_0_avs_s0_agent:m0_burstcount -> custom_math_0_avs_s0_translator:uav_burstcount
wire custom_math_0_avs_s0_agent_rf_source_valid; // custom_math_0_avs_s0_agent:rf_source_valid -> custom_math_0_avs_s0_agent_rsp_fifo:in_valid
wire [108:0] custom_math_0_avs_s0_agent_rf_source_data; // custom_math_0_avs_s0_agent:rf_source_data -> custom_math_0_avs_s0_agent_rsp_fifo:in_data
wire custom_math_0_avs_s0_agent_rf_source_ready; // custom_math_0_avs_s0_agent_rsp_fifo:in_ready -> custom_math_0_avs_s0_agent:rf_source_ready
wire custom_math_0_avs_s0_agent_rf_source_startofpacket; // custom_math_0_avs_s0_agent:rf_source_startofpacket -> custom_math_0_avs_s0_agent_rsp_fifo:in_startofpacket
wire custom_math_0_avs_s0_agent_rf_source_endofpacket; // custom_math_0_avs_s0_agent:rf_source_endofpacket -> custom_math_0_avs_s0_agent_rsp_fifo:in_endofpacket
wire custom_math_0_avs_s0_agent_rsp_fifo_out_valid; // custom_math_0_avs_s0_agent_rsp_fifo:out_valid -> custom_math_0_avs_s0_agent:rf_sink_valid
wire [108:0] custom_math_0_avs_s0_agent_rsp_fifo_out_data; // custom_math_0_avs_s0_agent_rsp_fifo:out_data -> custom_math_0_avs_s0_agent:rf_sink_data
wire custom_math_0_avs_s0_agent_rsp_fifo_out_ready; // custom_math_0_avs_s0_agent:rf_sink_ready -> custom_math_0_avs_s0_agent_rsp_fifo:out_ready
wire custom_math_0_avs_s0_agent_rsp_fifo_out_startofpacket; // custom_math_0_avs_s0_agent_rsp_fifo:out_startofpacket -> custom_math_0_avs_s0_agent:rf_sink_startofpacket
wire custom_math_0_avs_s0_agent_rsp_fifo_out_endofpacket; // custom_math_0_avs_s0_agent_rsp_fifo:out_endofpacket -> custom_math_0_avs_s0_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> custom_math_0_avs_s0_agent:cp_valid
wire [107:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> custom_math_0_avs_s0_agent:cp_data
wire cmd_mux_002_src_ready; // custom_math_0_avs_s0_agent:cp_ready -> cmd_mux_002:src_ready
wire [4:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> custom_math_0_avs_s0_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> custom_math_0_avs_s0_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> custom_math_0_avs_s0_agent:cp_endofpacket
wire [31:0] sysid_qsys_0_control_slave_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_agent:m0_readdata
wire sysid_qsys_0_control_slave_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_agent:m0_waitrequest
wire sysid_qsys_0_control_slave_agent_m0_debugaccess; // sysid_qsys_0_control_slave_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
wire [31:0] sysid_qsys_0_control_slave_agent_m0_address; // sysid_qsys_0_control_slave_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
wire [3:0] sysid_qsys_0_control_slave_agent_m0_byteenable; // sysid_qsys_0_control_slave_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
wire sysid_qsys_0_control_slave_agent_m0_read; // sysid_qsys_0_control_slave_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
wire sysid_qsys_0_control_slave_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_agent:m0_readdatavalid
wire sysid_qsys_0_control_slave_agent_m0_lock; // sysid_qsys_0_control_slave_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
wire [31:0] sysid_qsys_0_control_slave_agent_m0_writedata; // sysid_qsys_0_control_slave_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
wire sysid_qsys_0_control_slave_agent_m0_write; // sysid_qsys_0_control_slave_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
wire [2:0] sysid_qsys_0_control_slave_agent_m0_burstcount; // sysid_qsys_0_control_slave_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
wire sysid_qsys_0_control_slave_agent_rf_source_valid; // sysid_qsys_0_control_slave_agent:rf_source_valid -> sysid_qsys_0_control_slave_agent_rsp_fifo:in_valid
wire [108:0] sysid_qsys_0_control_slave_agent_rf_source_data; // sysid_qsys_0_control_slave_agent:rf_source_data -> sysid_qsys_0_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_0_control_slave_agent_rf_source_ready; // sysid_qsys_0_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_agent:rf_source_ready
wire sysid_qsys_0_control_slave_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_agent_rsp_fifo:in_startofpacket
wire sysid_qsys_0_control_slave_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_0_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_agent:rf_sink_valid
wire [108:0] sysid_qsys_0_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_agent:rf_sink_data
wire sysid_qsys_0_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_agent:rf_sink_ready -> sysid_qsys_0_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_0_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_agent:rf_sink_startofpacket
wire sysid_qsys_0_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sysid_qsys_0_control_slave_agent:cp_valid
wire [107:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sysid_qsys_0_control_slave_agent:cp_data
wire cmd_mux_003_src_ready; // sysid_qsys_0_control_slave_agent:cp_ready -> cmd_mux_003:src_ready
wire [4:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sysid_qsys_0_control_slave_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sysid_qsys_0_control_slave_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sysid_qsys_0_control_slave_agent:cp_endofpacket
wire [31:0] timer_0_s1_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_agent:m0_readdata
wire timer_0_s1_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_agent:m0_waitrequest
wire timer_0_s1_agent_m0_debugaccess; // timer_0_s1_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
wire [31:0] timer_0_s1_agent_m0_address; // timer_0_s1_agent:m0_address -> timer_0_s1_translator:uav_address
wire [3:0] timer_0_s1_agent_m0_byteenable; // timer_0_s1_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
wire timer_0_s1_agent_m0_read; // timer_0_s1_agent:m0_read -> timer_0_s1_translator:uav_read
wire timer_0_s1_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_agent:m0_readdatavalid
wire timer_0_s1_agent_m0_lock; // timer_0_s1_agent:m0_lock -> timer_0_s1_translator:uav_lock
wire [31:0] timer_0_s1_agent_m0_writedata; // timer_0_s1_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
wire timer_0_s1_agent_m0_write; // timer_0_s1_agent:m0_write -> timer_0_s1_translator:uav_write
wire [2:0] timer_0_s1_agent_m0_burstcount; // timer_0_s1_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
wire timer_0_s1_agent_rf_source_valid; // timer_0_s1_agent:rf_source_valid -> timer_0_s1_agent_rsp_fifo:in_valid
wire [108:0] timer_0_s1_agent_rf_source_data; // timer_0_s1_agent:rf_source_data -> timer_0_s1_agent_rsp_fifo:in_data
wire timer_0_s1_agent_rf_source_ready; // timer_0_s1_agent_rsp_fifo:in_ready -> timer_0_s1_agent:rf_source_ready
wire timer_0_s1_agent_rf_source_startofpacket; // timer_0_s1_agent:rf_source_startofpacket -> timer_0_s1_agent_rsp_fifo:in_startofpacket
wire timer_0_s1_agent_rf_source_endofpacket; // timer_0_s1_agent:rf_source_endofpacket -> timer_0_s1_agent_rsp_fifo:in_endofpacket
wire timer_0_s1_agent_rsp_fifo_out_valid; // timer_0_s1_agent_rsp_fifo:out_valid -> timer_0_s1_agent:rf_sink_valid
wire [108:0] timer_0_s1_agent_rsp_fifo_out_data; // timer_0_s1_agent_rsp_fifo:out_data -> timer_0_s1_agent:rf_sink_data
wire timer_0_s1_agent_rsp_fifo_out_ready; // timer_0_s1_agent:rf_sink_ready -> timer_0_s1_agent_rsp_fifo:out_ready
wire timer_0_s1_agent_rsp_fifo_out_startofpacket; // timer_0_s1_agent_rsp_fifo:out_startofpacket -> timer_0_s1_agent:rf_sink_startofpacket
wire timer_0_s1_agent_rsp_fifo_out_endofpacket; // timer_0_s1_agent_rsp_fifo:out_endofpacket -> timer_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> timer_0_s1_agent:cp_valid
wire [107:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> timer_0_s1_agent:cp_data
wire cmd_mux_004_src_ready; // timer_0_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [4:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> timer_0_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> timer_0_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> timer_0_s1_agent:cp_endofpacket
wire custom_math_0_avm_m0_agent_cp_valid; // custom_math_0_avm_m0_agent:cp_valid -> router:sink_valid
wire [107:0] custom_math_0_avm_m0_agent_cp_data; // custom_math_0_avm_m0_agent:cp_data -> router:sink_data
wire custom_math_0_avm_m0_agent_cp_ready; // router:sink_ready -> custom_math_0_avm_m0_agent:cp_ready
wire custom_math_0_avm_m0_agent_cp_startofpacket; // custom_math_0_avm_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire custom_math_0_avm_m0_agent_cp_endofpacket; // custom_math_0_avm_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [107:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [4:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
wire [107:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [107:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_003:sink_valid
wire [107:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_003:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_003:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [107:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [4:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [107:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [107:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [4:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire custom_math_0_avs_s0_agent_rp_valid; // custom_math_0_avs_s0_agent:rp_valid -> router_005:sink_valid
wire [107:0] custom_math_0_avs_s0_agent_rp_data; // custom_math_0_avs_s0_agent:rp_data -> router_005:sink_data
wire custom_math_0_avs_s0_agent_rp_ready; // router_005:sink_ready -> custom_math_0_avs_s0_agent:rp_ready
wire custom_math_0_avs_s0_agent_rp_startofpacket; // custom_math_0_avs_s0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire custom_math_0_avs_s0_agent_rp_endofpacket; // custom_math_0_avs_s0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [107:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [4:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire sysid_qsys_0_control_slave_agent_rp_valid; // sysid_qsys_0_control_slave_agent:rp_valid -> router_006:sink_valid
wire [107:0] sysid_qsys_0_control_slave_agent_rp_data; // sysid_qsys_0_control_slave_agent:rp_data -> router_006:sink_data
wire sysid_qsys_0_control_slave_agent_rp_ready; // router_006:sink_ready -> sysid_qsys_0_control_slave_agent:rp_ready
wire sysid_qsys_0_control_slave_agent_rp_startofpacket; // sysid_qsys_0_control_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire sysid_qsys_0_control_slave_agent_rp_endofpacket; // sysid_qsys_0_control_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [107:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [4:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire timer_0_s1_agent_rp_valid; // timer_0_s1_agent:rp_valid -> router_007:sink_valid
wire [107:0] timer_0_s1_agent_rp_data; // timer_0_s1_agent:rp_data -> router_007:sink_data
wire timer_0_s1_agent_rp_ready; // router_007:sink_ready -> timer_0_s1_agent:rp_ready
wire timer_0_s1_agent_rp_startofpacket; // timer_0_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire timer_0_s1_agent_rp_endofpacket; // timer_0_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_004:sink_valid
wire [107:0] router_007_src_data; // router_007:src_data -> rsp_demux_004:sink_data
wire router_007_src_ready; // rsp_demux_004:sink_ready -> router_007:src_ready
wire [4:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_004:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_gen2_0_data_master_limiter:cmd_sink_valid
wire [107:0] router_001_src_data; // router_001:src_data -> nios2_gen2_0_data_master_limiter:cmd_sink_data
wire router_001_src_ready; // nios2_gen2_0_data_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [4:0] router_001_src_channel; // router_001:src_channel -> nios2_gen2_0_data_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_gen2_0_data_master_limiter:cmd_sink_endofpacket
wire [107:0] nios2_gen2_0_data_master_limiter_cmd_src_data; // nios2_gen2_0_data_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire nios2_gen2_0_data_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_gen2_0_data_master_limiter:cmd_src_ready
wire [4:0] nios2_gen2_0_data_master_limiter_cmd_src_channel; // nios2_gen2_0_data_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_gen2_0_data_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire nios2_gen2_0_data_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_data_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_limiter:rsp_sink_valid
wire [107:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_data_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_data_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [4:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_valid; // nios2_gen2_0_data_master_limiter:rsp_src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [107:0] nios2_gen2_0_data_master_limiter_rsp_src_data; // nios2_gen2_0_data_master_limiter:rsp_src_data -> nios2_gen2_0_data_master_agent:rp_data
wire nios2_gen2_0_data_master_limiter_rsp_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> nios2_gen2_0_data_master_limiter:rsp_src_ready
wire [4:0] nios2_gen2_0_data_master_limiter_rsp_src_channel; // nios2_gen2_0_data_master_limiter:rsp_src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire nios2_gen2_0_data_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire nios2_gen2_0_data_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_data_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire router_002_src_valid; // router_002:src_valid -> nios2_gen2_0_instruction_master_limiter:cmd_sink_valid
wire [107:0] router_002_src_data; // router_002:src_data -> nios2_gen2_0_instruction_master_limiter:cmd_sink_data
wire router_002_src_ready; // nios2_gen2_0_instruction_master_limiter:cmd_sink_ready -> router_002:src_ready
wire [4:0] router_002_src_channel; // router_002:src_channel -> nios2_gen2_0_instruction_master_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:cmd_sink_endofpacket
wire [107:0] nios2_gen2_0_instruction_master_limiter_cmd_src_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire nios2_gen2_0_instruction_master_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> nios2_gen2_0_instruction_master_limiter:cmd_src_ready
wire [4:0] nios2_gen2_0_instruction_master_limiter_cmd_src_channel; // nios2_gen2_0_instruction_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_limiter:rsp_sink_valid
wire [107:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // nios2_gen2_0_instruction_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [4:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_limiter:rsp_sink_endofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_valid; // nios2_gen2_0_instruction_master_limiter:rsp_src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [107:0] nios2_gen2_0_instruction_master_limiter_rsp_src_data; // nios2_gen2_0_instruction_master_limiter:rsp_src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire nios2_gen2_0_instruction_master_limiter_rsp_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> nios2_gen2_0_instruction_master_limiter:rsp_src_ready
wire [4:0] nios2_gen2_0_instruction_master_limiter_rsp_src_channel; // nios2_gen2_0_instruction_master_limiter:rsp_src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket; // nios2_gen2_0_instruction_master_limiter:rsp_src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [107:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [4:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [107:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [4:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
wire [107:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
wire [4:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [107:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [4:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [107:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [4:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire [107:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire [4:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
wire [107:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
wire [4:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
wire [107:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
wire [4:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [107:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [4:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [107:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [4:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
wire [107:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
wire [4:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
wire [107:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
wire [4:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
wire [107:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
wire [4:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [107:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [4:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [107:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [4:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire [107:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire [4:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire [4:0] nios2_gen2_0_data_master_limiter_cmd_valid_data; // nios2_gen2_0_data_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire [4:0] nios2_gen2_0_instruction_master_limiter_cmd_valid_data; // nios2_gen2_0_instruction_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire custom_math_0_avs_s0_agent_rdata_fifo_src_valid; // custom_math_0_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] custom_math_0_avs_s0_agent_rdata_fifo_src_data; // custom_math_0_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire custom_math_0_avs_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> custom_math_0_avs_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> custom_math_0_avs_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> custom_math_0_avs_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // custom_math_0_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> custom_math_0_avs_s0_agent:rdata_fifo_sink_error
wire sysid_qsys_0_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] sysid_qsys_0_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire sysid_qsys_0_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> sysid_qsys_0_control_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> sysid_qsys_0_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> sysid_qsys_0_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // sysid_qsys_0_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> sysid_qsys_0_control_slave_agent:rdata_fifo_sink_error
wire timer_0_s1_agent_rdata_fifo_src_valid; // timer_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] timer_0_s1_agent_rdata_fifo_src_data; // timer_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire timer_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> timer_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> timer_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> timer_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // timer_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> timer_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) custom_math_0_avm_m0_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (custom_math_0_avm_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (custom_math_0_avm_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (custom_math_0_avm_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (custom_math_0_avm_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (custom_math_0_avm_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (custom_math_0_avm_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (custom_math_0_avm_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (custom_math_0_avm_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (custom_math_0_avm_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (custom_math_0_avm_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (custom_math_0_avm_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (custom_math_0_avm_m0_address), // avalon_anti_master_0.address
.av_waitrequest (custom_math_0_avm_m0_waitrequest), // .waitrequest
.av_read (custom_math_0_avm_m0_read), // .read
.av_readdata (custom_math_0_avm_m0_readdata), // .readdata
.av_write (custom_math_0_avm_m0_write), // .write
.av_writedata (custom_math_0_avm_m0_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_data_master_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_gen2_0_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (4),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) custom_math_0_avs_s0_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (custom_math_0_avs_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (custom_math_0_avs_s0_agent_m0_burstcount), // .burstcount
.uav_read (custom_math_0_avs_s0_agent_m0_read), // .read
.uav_write (custom_math_0_avs_s0_agent_m0_write), // .write
.uav_waitrequest (custom_math_0_avs_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (custom_math_0_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (custom_math_0_avs_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (custom_math_0_avs_s0_agent_m0_readdata), // .readdata
.uav_writedata (custom_math_0_avs_s0_agent_m0_writedata), // .writedata
.uav_lock (custom_math_0_avs_s0_agent_m0_lock), // .lock
.uav_debugaccess (custom_math_0_avs_s0_agent_m0_debugaccess), // .debugaccess
.av_address (custom_math_0_avs_s0_address), // avalon_anti_slave_0.address
.av_write (custom_math_0_avs_s0_write), // .write
.av_read (custom_math_0_avs_s0_read), // .read
.av_readdata (custom_math_0_avs_s0_readdata), // .readdata
.av_writedata (custom_math_0_avs_s0_writedata), // .writedata
.av_waitrequest (custom_math_0_avs_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_0_control_slave_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_0_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_0_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_0_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_0_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_0_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_0_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_0_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_0_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_0_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_0_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_0_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_0_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_0_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_0_s1_translator (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (timer_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (timer_0_s1_agent_m0_read), // .read
.uav_write (timer_0_s1_agent_m0_write), // .write
.uav_waitrequest (timer_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (timer_0_s1_agent_m0_writedata), // .writedata
.uav_lock (timer_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (timer_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (timer_0_s1_address), // avalon_anti_slave_0.address
.av_write (timer_0_s1_write), // .write
.av_readdata (timer_0_s1_readdata), // .readdata
.av_writedata (timer_0_s1_writedata), // .writedata
.av_chipselect (timer_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.ST_DATA_W (108),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) custom_math_0_avm_m0_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (custom_math_0_avm_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (custom_math_0_avm_m0_translator_avalon_universal_master_0_write), // .write
.av_read (custom_math_0_avm_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (custom_math_0_avm_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (custom_math_0_avm_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (custom_math_0_avm_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (custom_math_0_avm_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (custom_math_0_avm_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (custom_math_0_avm_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (custom_math_0_avm_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (custom_math_0_avm_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (custom_math_0_avm_m0_agent_cp_valid), // cp.valid
.cp_data (custom_math_0_avm_m0_agent_cp_data), // .data
.cp_startofpacket (custom_math_0_avm_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (custom_math_0_avm_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (custom_math_0_avm_m0_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.ST_DATA_W (108),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (88),
.PKT_QOS_L (88),
.PKT_DATA_SIDEBAND_H (86),
.PKT_DATA_SIDEBAND_L (86),
.PKT_ADDR_SIDEBAND_H (85),
.PKT_ADDR_SIDEBAND_L (85),
.PKT_BURST_TYPE_H (84),
.PKT_BURST_TYPE_L (83),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.ST_DATA_W (108),
.ST_CHANNEL_W (5),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) custom_math_0_avs_s0_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (custom_math_0_avs_s0_agent_m0_address), // m0.address
.m0_burstcount (custom_math_0_avs_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (custom_math_0_avs_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (custom_math_0_avs_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (custom_math_0_avs_s0_agent_m0_lock), // .lock
.m0_readdata (custom_math_0_avs_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (custom_math_0_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (custom_math_0_avs_s0_agent_m0_read), // .read
.m0_waitrequest (custom_math_0_avs_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (custom_math_0_avs_s0_agent_m0_writedata), // .writedata
.m0_write (custom_math_0_avs_s0_agent_m0_write), // .write
.rp_endofpacket (custom_math_0_avs_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (custom_math_0_avs_s0_agent_rp_ready), // .ready
.rp_valid (custom_math_0_avs_s0_agent_rp_valid), // .valid
.rp_data (custom_math_0_avs_s0_agent_rp_data), // .data
.rp_startofpacket (custom_math_0_avs_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (custom_math_0_avs_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (custom_math_0_avs_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (custom_math_0_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (custom_math_0_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (custom_math_0_avs_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (custom_math_0_avs_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (custom_math_0_avs_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (custom_math_0_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (custom_math_0_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (custom_math_0_avs_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (custom_math_0_avs_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (custom_math_0_avs_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (custom_math_0_avs_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) custom_math_0_avs_s0_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (custom_math_0_avs_s0_agent_rf_source_data), // in.data
.in_valid (custom_math_0_avs_s0_agent_rf_source_valid), // .valid
.in_ready (custom_math_0_avs_s0_agent_rf_source_ready), // .ready
.in_startofpacket (custom_math_0_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (custom_math_0_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (custom_math_0_avs_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (custom_math_0_avs_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (custom_math_0_avs_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (custom_math_0_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (custom_math_0_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sysid_qsys_0_control_slave_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_0_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_0_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_0_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_0_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_0_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_0_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_0_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_0_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_0_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_0_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_0_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_0_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_0_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_0_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_0_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_0_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (sysid_qsys_0_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_0_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_0_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_0_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_0_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_0_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_0_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_0_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_0_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_0_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_0_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_0_control_slave_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_0_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_0_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_0_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_0_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_0_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_0_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_0_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_0_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_0_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_0_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (82),
.PKT_BURST_SIZE_L (80),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (87),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (79),
.PKT_BURSTWRAP_L (77),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (5),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) timer_0_s1_agent (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (timer_0_s1_agent_m0_address), // m0.address
.m0_burstcount (timer_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_0_s1_agent_m0_lock), // .lock
.m0_readdata (timer_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_0_s1_agent_m0_read), // .read
.m0_waitrequest (timer_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_0_s1_agent_m0_writedata), // .writedata
.m0_write (timer_0_s1_agent_m0_write), // .write
.rp_endofpacket (timer_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_0_s1_agent_rp_ready), // .ready
.rp_valid (timer_0_s1_agent_rp_valid), // .valid
.rp_data (timer_0_s1_agent_rp_data), // .data
.rp_startofpacket (timer_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (timer_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (timer_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_0_s1_agent_rsp_fifo (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_0_s1_agent_rf_source_data), // in.data
.in_valid (timer_0_s1_agent_rf_source_valid), // .valid
.in_ready (timer_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (timer_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_design_mm_interconnect_0_router router (
.sink_ready (custom_math_0_avm_m0_agent_cp_ready), // sink.ready
.sink_valid (custom_math_0_avm_m0_agent_cp_valid), // .valid
.sink_data (custom_math_0_avm_m0_agent_cp_data), // .data
.sink_startofpacket (custom_math_0_avm_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (custom_math_0_avm_m0_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_003 router_003 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_004 router_004 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_005 router_005 (
.sink_ready (custom_math_0_avs_s0_agent_rp_ready), // sink.ready
.sink_valid (custom_math_0_avs_s0_agent_rp_valid), // .valid
.sink_data (custom_math_0_avs_s0_agent_rp_data), // .data
.sink_startofpacket (custom_math_0_avs_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (custom_math_0_avs_s0_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_005 router_006 (
.sink_ready (sysid_qsys_0_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_0_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_0_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_0_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_0_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_router_005 router_007 (
.sink_ready (timer_0_s1_agent_rp_ready), // sink.ready
.sink_valid (timer_0_s1_agent_rp_valid), // .valid
.sink_data (timer_0_s1_agent_rp_data), // .data
.sink_startofpacket (timer_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (108),
.ST_CHANNEL_W (5),
.VALID_WIDTH (5),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_data_master_limiter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (92),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (89),
.PKT_BYTE_CNT_H (76),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (108),
.ST_CHANNEL_W (5),
.VALID_WIDTH (5),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) nios2_gen2_0_instruction_master_limiter (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_gen2_0_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_gen2_0_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_gen2_0_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_gen2_0_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_gen2_0_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
nios_design_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_gen2_0_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_gen2_0_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_gen2_0_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_gen2_0_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_mux cmd_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src1_valid), // .valid
.sink0_channel (cmd_demux_001_src1_channel), // .channel
.sink0_data (cmd_demux_001_src1_data), // .data
.sink0_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_rsp_demux rsp_demux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_demux rsp_demux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_demux rsp_demux_003 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_cmd_demux rsp_demux_004 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (pll_0_outclk0_clk), // clk.clk
.reset (custom_math_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_src2_valid), // .valid
.sink0_channel (rsp_demux_src2_channel), // .channel
.sink0_data (rsp_demux_src2_data), // .data
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (custom_math_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
nios_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (custom_math_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
nios_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (custom_math_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (custom_math_0_avs_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (custom_math_0_avs_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (custom_math_0_avs_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
nios_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (custom_math_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sysid_qsys_0_control_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sysid_qsys_0_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sysid_qsys_0_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
nios_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (pll_0_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (custom_math_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (timer_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (timer_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (timer_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module ad_pps_receiver (
input clk,
input rst,
input gps_pps,
input up_clk,
input up_rstn,
output reg [31:0] up_pps_rcounter,
output reg up_pps_status,
input up_irq_mask,
output reg up_irq);
// *************************************************************************
// 1PPS reception and reporting counter implementation
// Note: this module should run on the core clock
// *************************************************************************
reg [ 2:0] gps_pps_m = 3'b0;
reg [ 2:0] up_pps_m = 3'b0;
reg up_pps_status_m = 1'b0;
reg pps_toggle = 1'b0;
reg [31:0] free_rcounter = 32'b0;
reg [31:0] pps_rcounter = 32'b0;
reg pps_status = 1'b0;
wire pps_posedge_s;
wire up_pps_posedge_s;
// gps_pps is asynchronous from the clk
always @(posedge clk) begin
if (rst == 1'b1) begin
gps_pps_m <= 3'b0;
end else begin
gps_pps_m <= {gps_pps_m[1:0], gps_pps};
end
end
assign pps_posedge_s = ~gps_pps_m[2] & gps_pps_m[1];
always @(posedge clk) begin
if (rst == 1'b1) begin
free_rcounter <= 32'b0;
pps_rcounter <= 32'b0;
pps_status <= 1'b1;
end else if (pps_posedge_s == 1'b1) begin
free_rcounter <= 32'b0;
pps_rcounter <= free_rcounter;
pps_status <= 1'b0;
end else begin
free_rcounter <= free_rcounter + 32'b1;
if (free_rcounter[28] == 1'b1) begin
pps_status <= 1'b1;
end
end
end
// up_tdd_pps_rcounter CDC
always @(posedge clk) begin
if (rst == 1'b1) begin
pps_toggle <= 1'b0;
end else if (pps_posedge_s == 1'b1) begin
pps_toggle <= ~pps_toggle;
end
end
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_pps_m <= 3'b0;
up_pps_rcounter <= 1'b0;
up_pps_status_m <= 1'b1;
up_pps_status <= 1'b1;
end else begin
up_pps_m <= {up_pps_m[1:0], pps_toggle};
up_pps_status_m <= pps_status;
up_pps_status <= up_pps_status_m;
if ((up_pps_m[2] ^ up_pps_m[1]) == 1'b1) begin
up_pps_rcounter <= pps_rcounter;
end
end
end
assign up_pps_posedge_s = ~up_pps_m[2] & up_pps_m[1];
// IRQ generation
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_irq <= 1'b0;
end else begin
up_irq <= up_pps_posedge_s & ~up_irq_mask;
end
end
endmodule
|
`timescale 1ns / 1ps
//------------------------------------------------
module UPCOUNTER_POSEDGE # (parameter SIZE=16)
(
input wire Clock, Reset,
input wire [SIZE-1:0] Initial,
input wire Enable,
output reg [SIZE-1:0] Q
);
always @(posedge Clock )
begin
if (Reset)
Q = Initial;
else
begin
if (Enable)
Q = Q + 1;
end
end
endmodule
//----------------------------------------------------
module mux (in0,in1,in2,in3, sel, out);
input wire [7:0] in0,in1,in2,in3;
input wire [1:0] sel;
output reg [7:0] out;
always @ (*)
begin
case (sel)
0: out<=in0;
1: out<=in1;
2: out<=in2;
3: out<=in3;
default: out<=0;
endcase
end
endmodule
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=8 )
(
input wire Clock,
input wire Reset,
input wire Enable,
input wire [SIZE-1:0] D,
output reg [SIZE-1:0] Q
);
always @ (posedge Clock)
begin
if ( Reset )
Q <= 0;
else
begin
if (Enable)
Q <= D;
end
end//always
endmodule
//----------------------------------------------------------------------
module FULL_ADDER # (parameter SIZE=4)
(
input wire[SIZE-1:0] wA,
input wire[SIZE-1:0] wB,
input wire wCi,
output wire [SIZE-1:0] wR ,
output wire wCo
);
assign {wCo,wR} = wA + wB + wCi;
endmodule
//----------------------------------------------------------------------
module arrayMUL
(
input wire [3:0] A,
input wire [3:0] B,
output reg [7:0] out
);
reg rC1, rC2, rC3; //registros para los llevos
reg [2:0] rT1, rT2; //registros temporales
always @ (*) begin
//R0
out[0] =A[0] & B[0];
//R1
{rC1, out[1]} = (A[0] & B[1]) + (A[1] & B[0]);
//R2
{rC1, rT1[0]} = (A[2] & B[0]) + (A[1] & B[1]) + rC1;
{rC2, out[2]} = (A[0] & B[2]) + rT1[0];
//R3
{rC1, rT1[1]} = (A[3] & B[0]) + (A[2] & B[1]) + rC1;
{rC2, rT2[0]} = (A[1] & B[2]) + rT1[1] + rC2;
{rC3, out[3]} = (A[0] & B[3]) + rT2[0];
//R4
{rC1, rT1[2]} = (A[3] & B[1]) + rC1;
{rC2, rT2[1]} = (A[2] & B[2]) + rT1[2] + rC2;
{rC3, out[4]} = (A[1] & B[3]) + rT2[1] + rC3;
//R5
{rC2, rT2[2]} = (A[3] & B[2]) + rC2 + rC1;
{rC3, out[5]} = (A[2] & B[3]) + rT2[2] + rC3;
//R6 y R7.
{out[7], out[6]} = (A[3] & B[3]) + rC2 + rC3;
end
endmodule
//----------------------------------------------------------------------
module muxMUL (ia,ib,o);
input wire [3:0] ib,ia;
output [7:0] o;
wire [7:0] iaR,iaRA;
wire [7:0] o0,o1;
wire [7:0] o1R ;
assign iaR=ia<<1; // A desplazado0 una posicion a la izquierda
assign iaRA=iaR+ia; // A desplazado una posicion a la izquierda mas A
mux mux0 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[1],ib[0]}),.out(o0));
mux mux1 (.in0(8'b0),.in1({4'b0,ia}),.in2(iaR),.in3(iaRA),.sel({ib[3],ib[2]}),.out(o1));
assign o1R=o1<<2; // Salida desplazada 2 posiciones a la izquierda
assign o = o0+o1R;
endmodule
//----------------------------------------------------------------------
module arrayMUL_GEN # (parameter SIZE = 16)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire [(SIZE-2):0] wCarry[SIZE:0];
wire [(SIZE-2):0] wResult[(SIZE-1):0];
wire [(SIZE-2):0] wInput1[(SIZE-1):0];
wire [(SIZE-2):0] wInput2[(SIZE-1):0];
assign wInput2[SIZE-1][0]= 1'b0;
genvar CurrentRow, CurrentCol;
generate
for ( CurrentCol = 0; CurrentCol < (SIZE-1); CurrentCol = CurrentCol + 1)
begin : MUL_COL
for ( CurrentRow =0; CurrentRow < (SIZE-2); CurrentRow = CurrentRow + 1)
begin : MUL_ROW
assign wInput1[CurrentCol][CurrentRow]= A[CurrentCol] & B[CurrentRow+1];
if(CurrentCol==0)
begin
assign wCarry[0][CurrentRow]=1'b0;
end
if(CurrentRow==0 && CurrentCol!=SIZE-1)
begin
assign wInput2[CurrentCol][0]= A[CurrentCol+1] & B[CurrentRow];
end
else if(CurrentCol==(SIZE-1))
begin
assign wInput2[CurrentCol][CurrentRow]=wCarry[CurrentCol +1][CurrentRow-1];
end
else
begin
assign wInput2[CurrentCol][CurrentRow]= wResult[CurrentCol+1][CurrentRow-1];
end
FULL_ADDER # (1) add
(
.wA(wInput1 [CurrentCol][CurrentRow]),
.wB(wInput2[CurrentCol][CurrentRow]),
.wCi(wCarry[CurrentCol][CurrentRow]),
.wCo(wCarry[CurrentCol +1 ][CurrentRow]),
.wR (wResult[CurrentCol][CurrentRow])
);
end
end
endgenerate
wire wR0 = A[0] & B [0];
assign R = {wResult[0], wR0};
endmodule
/*
module arrayMUL_GEN # (parameter SIZE = 4)(
input wire [SIZE-1:0] A,B,
output wire [(2*SIZE)-1:0] R
);
wire[(SIZE-1):0] wCarry[(SIZE-1):0];
//wire[(SIZE-1):0] iResult[(SIZE-1):0];
wire iResult[(SIZE-1):0];
assign R[0] = A[0] & B[0] ;
//genvar CurrentRow, CurrentCol;
genvar i,j;
wire[SIZE-1:0] twCi; //temporal para wCi
assign twCi[0] = 1'b0;
generate
for (i = 0; i <= 0; i = i + 1 )
begin
for(j = 0; j < (SIZE-1); j = j +1 )
begin
if (j != 0)
assign twCi[j] = wCarry[j-1][i];
FULL_ADDER # (1) add
(
.wA(A[j+1]&B[i]),
.wB(A[j]&B[i+1]),
.wCo(wCarry[j+1][i]),
.wR(iResult[j+1]),
.wCi(twCi[j])
);
end //for j
end //for i
endgenerate
//assign R = {wCarry[2][3],iResult[2][3],iResult[2][2],iResult[2][1],
// iResult[2][0],iResult[1][0],iResult[0][0], A[0]&B[0]};
endmodule
*/
//----------------------------------------------------------------------
module multiplicador4bits(
input wire [3:0] iMultiplicador,
input wire [7:0] iMultiplicando,
output reg [7:0] oResult );
always @(*)
case(iMultiplicador)
0:oResult=0;
1:oResult=iMultiplicando;
2:oResult=iMultiplicando<<1;
3:oResult=(iMultiplicando<<1) +iMultiplicando;
4:oResult=(iMultiplicando<<2);
5:oResult=(iMultiplicando<<2)+iMultiplicando;
6:oResult=(iMultiplicando<<2)+(iMultiplicando<<1);
7:oResult=(iMultiplicando<<2)+(iMultiplicando<<1)+iMultiplicando;
8:oResult=iMultiplicando<<3;
9:oResult=(iMultiplicando<<3)+iMultiplicando;
10:oResult=(iMultiplicando<<3)+(iMultiplicando<<1);
11:oResult=(iMultiplicando<<3)+(iMultiplicando<<1)+iMultiplicando;
12:oResult=(iMultiplicando<<3)+(iMultiplicando<<2);
13:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ iMultiplicando;
14:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ (iMultiplicando<<1);
15:oResult=(iMultiplicando<<3)+(iMultiplicando<<2)+ (iMultiplicando<<1) + iMultiplicando;
endcase
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_top.v
// Version : 1.3
// Description: Solution wrapper for Virtex7 Hard Block for PCI Express
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_top # (
// PCIE_2_1 params
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter [11:0] AER_BASE_PTR = 12'h140,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [15:0] AER_CAP_ID = 16'h0001,
parameter AER_CAP_MULTIHEADER = "FALSE",
parameter [11:0] AER_CAP_NEXTPTR = 12'h178,
parameter AER_CAP_ON = "FALSE",
parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000,
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter [3:0] AER_CAP_VERSION = 4'h1,
parameter ALLOW_X8_GEN2 = "FALSE",
parameter [31:0] BAR0 = 32'hFFFFFF00,
parameter [31:0] BAR1 = 32'hFFFF0000,
parameter [31:0] BAR2 = 32'hFFFF000C,
parameter [31:0] BAR3 = 32'hFFFFFFFF,
parameter [31:0] BAR4 = 32'h00000000,
parameter [31:0] BAR5 = 32'h00000000,
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1,
parameter KEEP_WIDTH = C_DATA_WIDTH / 8,
parameter [7:0] CAPABILITIES_PTR = 8'h40,
parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000,
parameter [23:0] CLASS_CODE = 24'h000000,
parameter CFG_ECRC_ERR_CPLSTAT = 0,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0,
parameter [6:0] CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE",
parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE",
parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE",
parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE",
parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE",
parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0,
parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE",
parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter integer DEV_CAP_RSVD_14_12 = 0,
parameter integer DEV_CAP_RSVD_17_16 = 0,
parameter integer DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ERR_MSG = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_LANE_REVERSAL = "FALSE",
parameter DISABLE_LOCKED_FILTER = "FALSE",
parameter DISABLE_PPM_FILTER = "FALSE",
parameter DISABLE_RX_POISONED_RESP = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [11:0] DSN_BASE_PTR = 12'h100,
parameter [15:0] DSN_CAP_ID = 16'h0003,
parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C,
parameter DSN_CAP_ON = "TRUE",
parameter [3:0] DSN_CAP_VERSION = 4'h1,
parameter [10:0] ENABLE_MSG_ROUTE = 11'h000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE",
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter [31:0] EXPANSION_ROM = 32'hFFFFF001,
parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F,
parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter [7:0] HEADER_TYPE = 8'h00,
parameter [4:0] INFER_EI = 5'h00,
parameter [7:0] INTERRUPT_PIN = 8'h01,
parameter INTERRUPT_STAT_AUTO = "TRUE",
parameter IS_SWITCH = "FALSE",
parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE",
parameter integer LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1,
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter integer LINK_CAP_RSVD_23 = 0,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter integer LINK_CONTROL_RCB = 0,
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [14:0] LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01,
parameter MPS_FORCE = "FALSE",
parameter [7:0] MSIX_BASE_PTR = 8'h9C,
parameter [7:0] MSIX_CAP_ID = 8'h11,
parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00,
parameter MSIX_CAP_ON = "FALSE",
parameter integer MSIX_CAP_PBA_BIR = 0,
parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000,
parameter [7:0] MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter [7:0] MSI_CAP_ID = 8'h05,
parameter integer MSI_CAP_MULTIMSGCAP = 0,
parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter [7:0] MSI_CAP_NEXTPTR = 8'h60,
parameter MSI_CAP_ON = "FALSE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE",
parameter integer N_FTS_COMCLK_GEN1 = 255,
parameter integer N_FTS_COMCLK_GEN2 = 255,
parameter integer N_FTS_GEN1 = 255,
parameter integer N_FTS_GEN2 = 255,
parameter [7:0] PCIE_BASE_PTR = 8'h60,
parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0,
parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C,
parameter PCIE_CAP_ON = "TRUE",
parameter integer PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter integer PCIE_REVISION = 2,
parameter integer PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000,
parameter PM_ASPML0S_TIMEOUT_EN = "FALSE",
parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0,
parameter PM_ASPM_FASTEXIT = "FALSE",
parameter [7:0] PM_BASE_PTR = 8'h40,
parameter integer PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_D1SUPPORT = "TRUE",
parameter PM_CAP_D2SUPPORT = "TRUE",
parameter PM_CAP_DSI = "FALSE",
parameter [7:0] PM_CAP_ID = 8'h01,
parameter [7:0] PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_ON = "TRUE",
parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter integer PM_CAP_RSVD_04 = 0,
parameter integer PM_CAP_VERSION = 3,
parameter PM_CSR_B2B3 = "FALSE",
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter [7:0] PM_DATA0 = 8'h01,
parameter [7:0] PM_DATA1 = 8'h01,
parameter [7:0] PM_DATA2 = 8'h01,
parameter [7:0] PM_DATA3 = 8'h01,
parameter [7:0] PM_DATA4 = 8'h01,
parameter [7:0] PM_DATA5 = 8'h01,
parameter [7:0] PM_DATA6 = 8'h01,
parameter [7:0] PM_DATA7 = 8'h01,
parameter [1:0] PM_DATA_SCALE0 = 2'h1,
parameter [1:0] PM_DATA_SCALE1 = 2'h1,
parameter [1:0] PM_DATA_SCALE2 = 2'h1,
parameter [1:0] PM_DATA_SCALE3 = 2'h1,
parameter [1:0] PM_DATA_SCALE4 = 2'h1,
parameter [1:0] PM_DATA_SCALE5 = 2'h1,
parameter [1:0] PM_DATA_SCALE6 = 2'h1,
parameter [1:0] PM_DATA_SCALE7 = 2'h1,
parameter PM_MF = "FALSE",
parameter [11:0] RBAR_BASE_PTR = 12'h178,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00,
parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00,
parameter [15:0] RBAR_CAP_ID = 16'h0015,
parameter [2:0] RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX2 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX3 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX4 = 3'h0,
parameter [2:0] RBAR_CAP_INDEX5 = 3'h0,
parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000,
parameter RBAR_CAP_ON = "FALSE",
parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000,
parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000,
parameter [3:0] RBAR_CAP_VERSION = 4'h1,
parameter [2:0] RBAR_NUM = 3'h1,
parameter integer RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter [1:0] RP_AUTO_SPD = 2'h1,
parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1f,
parameter SELECT_DLL_IF = "FALSE",
parameter SIM_VERSION = "1.0",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SSL_MESSAGE_AUTO = "FALSE",
parameter TECRC_EP_INV = "FALSE",
parameter TL_RBYPASS = "FALSE",
parameter integer TL_RX_RAM_RADDR_LATENCY = 0,
parameter integer TL_RX_RAM_RDATA_LATENCY = 2,
parameter integer TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter integer TL_TX_RAM_RADDR_LATENCY = 0,
parameter integer TL_TX_RAM_RDATA_LATENCY = 2,
parameter integer TL_TX_RAM_WRITE_LATENCY = 0,
parameter TRN_DW = "FALSE",
parameter TRN_NP_FC = "FALSE",
parameter UPCONFIG_CAPABLE = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_ATOMIC = "TRUE",
parameter UR_CFG1 = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter UR_PRS_RESPONSE = "TRUE",
parameter USER_CLK2_DIV2 = "FALSE",
parameter integer USER_CLK_FREQ = 3,
parameter USE_RID_PINS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF,
parameter integer VC0_TOTAL_CREDITS_CD = 127,
parameter integer VC0_TOTAL_CREDITS_CH = 31,
parameter integer VC0_TOTAL_CREDITS_NPD = 24,
parameter integer VC0_TOTAL_CREDITS_NPH = 12,
parameter integer VC0_TOTAL_CREDITS_PD = 288,
parameter integer VC0_TOTAL_CREDITS_PH = 32,
parameter integer VC0_TX_LASTPACKET = 31,
parameter [11:0] VC_BASE_PTR = 12'h10C,
parameter [15:0] VC_CAP_ID = 16'h0002,
parameter [11:0] VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter [3:0] VC_CAP_VERSION = 4'h1,
parameter [11:0] VSEC_BASE_PTR = 12'h128,
parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234,
parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018,
parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1,
parameter [15:0] VSEC_CAP_ID = 16'h000B,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140,
parameter VSEC_CAP_ON = "FALSE",
parameter [3:0] VSEC_CAP_VERSION = 4'h1
)
(
// wrapper input
// Common
output user_clk_out,
input user_reset,
input user_lnk_up,
output trn_lnk_up,
output user_rst_n,
// Tx
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
output s_axis_tx_tready,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input [3:0] s_axis_tx_tuser,
input s_axis_tx_tlast,
input s_axis_tx_tvalid,
input tx_cfg_gnt,
// Rx
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
input wire [1:0] pl_directed_link_change,
input wire [1:0] pl_directed_link_width,
input wire pl_directed_link_speed,
input wire pl_directed_link_auton,
input wire pl_upstream_prefer_deemph,
input wire pl_downstream_deemph_source,
input wire pl_directed_ltssm_new_vld,
input wire [5:0] pl_directed_ltssm_new,
input wire pl_directed_ltssm_stall,
input wire cm_rst_n,
input wire func_lvl_rst_n,
input wire pl_transmit_hot_rst,
input wire [31:0] cfg_mgmt_di,
input wire [3:0] cfg_mgmt_byte_en_n,
input wire [9:0] cfg_mgmt_dwaddr,
input wire cfg_mgmt_wr_rw1c_as_rw_n,
input wire cfg_mgmt_wr_readonly_n,
input wire cfg_mgmt_wr_en_n,
input wire cfg_mgmt_rd_en_n,
input wire cfg_err_malformed_n,
input wire cfg_err_cor_n,
input wire cfg_err_ur_n,
input wire cfg_err_ecrc_n,
input wire cfg_err_cpl_timeout_n,
input wire cfg_err_cpl_abort_n,
input wire cfg_err_cpl_unexpect_n,
input wire cfg_err_poisoned_n,
input wire cfg_err_acs_n,
input wire cfg_err_atomic_egress_blocked_n,
input wire cfg_err_mc_blocked_n,
input wire cfg_err_internal_uncor_n,
input wire cfg_err_internal_cor_n,
input wire cfg_err_posted_n,
input wire cfg_err_locked_n,
input wire cfg_err_norecovery_n,
input wire [127:0] cfg_err_aer_headerlog,
input wire [47:0] cfg_err_tlp_cpl_header,
input wire cfg_interrupt_n,
input wire [7:0] cfg_interrupt_di,
input wire cfg_interrupt_assert_n,
input wire cfg_interrupt_stat_n,
input wire [7:0] cfg_ds_bus_number,
input wire [4:0] cfg_ds_device_number,
input wire [2:0] cfg_ds_function_number,
input wire [7:0] cfg_port_number,
input wire cfg_pm_halt_aspm_l0s_n,
input wire cfg_pm_halt_aspm_l1_n,
input wire cfg_pm_force_state_en_n,
input wire [1:0] cfg_pm_force_state,
input wire cfg_pm_wake_n,
input wire cfg_turnoff_ok,
input wire cfg_pm_send_pme_to_n,
input wire [4:0] cfg_pciecap_interrupt_msgnum,
input wire cfg_trn_pending,
input wire [2:0] cfg_force_mps,
input wire cfg_force_common_clock_off,
input wire cfg_force_extended_sync_on,
input wire [63:0] cfg_dsn,
input wire [4:0] cfg_aer_interrupt_msgnum,
input wire [15:0] cfg_dev_id,
input wire [15:0] cfg_vend_id,
input wire [7:0] cfg_rev_id,
input wire [15:0] cfg_subsys_id,
input wire [15:0] cfg_subsys_vend_id,
input wire drp_clk,
input wire drp_en,
input wire drp_we,
input wire [8:0] drp_addr,
input wire [15:0] drp_di,
input wire [1:0] dbg_mode,
input wire dbg_sub_mode,
input wire [2:0] pl_dbg_mode ,
output wire pl_sel_lnk_rate,
output wire [1:0] pl_sel_lnk_width,
output wire [5:0] pl_ltssm_state,
output wire [1:0] pl_lane_reversal_mode,
output wire pl_phy_lnk_up,
output wire [2:0] pl_tx_pm_state,
output wire [1:0] pl_rx_pm_state,
output wire pl_link_upcfg_cap,
output wire pl_link_gen2_cap,
output wire pl_link_partner_gen2_supported,
output wire [2:0] pl_initial_link_width,
output wire pl_directed_change_done,
output wire pl_received_hot_rst,
output wire lnk_clk_en,
output wire [31:0] cfg_mgmt_do,
output wire cfg_mgmt_rd_wr_done,
output wire cfg_err_aer_headerlog_set,
output wire cfg_err_cpl_rdy,
output wire cfg_interrupt_rdy,
output wire [2:0] cfg_interrupt_mmenable,
output wire cfg_interrupt_msienable,
output wire [7:0] cfg_interrupt_do,
output wire cfg_interrupt_msixenable,
output wire cfg_interrupt_msixfm,
output wire [7:0] cfg_bus_number,
output wire [4:0] cfg_device_number,
output wire [2:0] cfg_function_number,
output wire [15:0] cfg_status,
output wire [15:0] cfg_command,
output wire [15:0] cfg_dstatus,
output wire [15:0] cfg_dcommand,
output wire [15:0] cfg_lstatus,
output wire [15:0] cfg_lcommand,
output wire [15:0] cfg_dcommand2,
output wire cfg_received_func_lvl_rst,
output wire cfg_msg_received,
output wire [15:0] cfg_msg_data,
output wire cfg_msg_received_err_cor,
output wire cfg_msg_received_err_non_fatal,
output wire cfg_msg_received_err_fatal,
output wire cfg_msg_received_assert_int_a,
output wire cfg_msg_received_deassert_int_a,
output wire cfg_msg_received_assert_int_b,
output wire cfg_msg_received_deassert_int_b,
output wire cfg_msg_received_assert_int_c,
output wire cfg_msg_received_deassert_int_c,
output wire cfg_msg_received_assert_int_d,
output wire cfg_msg_received_deassert_int_d,
output wire cfg_msg_received_pm_pme,
output wire cfg_msg_received_pme_to_ack,
output wire cfg_msg_received_pme_to,
output wire cfg_msg_received_setslotpowerlimit,
output wire cfg_msg_received_unlock,
output wire cfg_msg_received_pm_as_nak,
output wire cfg_to_turnoff,
output wire [2:0] cfg_pcie_link_state,
output wire cfg_pm_rcv_as_req_l1_n,
output wire cfg_pm_rcv_enter_l1_n,
output wire cfg_pm_rcv_enter_l23_n,
output wire cfg_pm_rcv_req_ack_n,
output wire [1:0] cfg_pmcsr_powerstate,
output wire cfg_pmcsr_pme_en,
output wire cfg_pmcsr_pme_status,
output wire cfg_transaction,
output wire cfg_transaction_type,
output wire [6:0] cfg_transaction_addr,
output wire cfg_command_io_enable,
output wire cfg_command_mem_enable,
output wire cfg_command_bus_master_enable,
output wire cfg_command_interrupt_disable,
output wire cfg_command_serr_en,
output wire cfg_bridge_serr_en,
output wire cfg_dev_status_corr_err_detected,
output wire cfg_dev_status_non_fatal_err_detected,
output wire cfg_dev_status_fatal_err_detected,
output wire cfg_dev_status_ur_detected,
output wire cfg_dev_control_corr_err_reporting_en,
output wire cfg_dev_control_non_fatal_reporting_en,
output wire cfg_dev_control_fatal_err_reporting_en,
output wire cfg_dev_control_ur_err_reporting_en,
output wire cfg_dev_control_enable_ro,
output wire [2:0] cfg_dev_control_max_payload,
output wire cfg_dev_control_ext_tag_en,
output wire cfg_dev_control_phantom_en,
output wire cfg_dev_control_aux_power_en,
output wire cfg_dev_control_no_snoop_en,
output wire [2:0] cfg_dev_control_max_read_req,
output wire [1:0] cfg_link_status_current_speed,
output wire [3:0] cfg_link_status_negotiated_width,
output wire cfg_link_status_link_training,
output wire cfg_link_status_dll_active,
output wire cfg_link_status_bandwidth_status,
output wire cfg_link_status_auto_bandwidth_status,
output wire [1:0] cfg_link_control_aspm_control,
output wire cfg_link_control_rcb,
output wire cfg_link_control_link_disable,
output wire cfg_link_control_retrain_link,
output wire cfg_link_control_common_clock,
output wire cfg_link_control_extended_sync,
output wire cfg_link_control_clock_pm_en,
output wire cfg_link_control_hw_auto_width_dis,
output wire cfg_link_control_bandwidth_int_en,
output wire cfg_link_control_auto_bandwidth_int_en,
output wire [3:0] cfg_dev_control2_cpl_timeout_val,
output wire cfg_dev_control2_cpl_timeout_dis,
output wire cfg_dev_control2_ari_forward_en,
output wire cfg_dev_control2_atomic_requester_en,
output wire cfg_dev_control2_atomic_egress_block,
output wire cfg_dev_control2_ido_req_en,
output wire cfg_dev_control2_ido_cpl_en,
output wire cfg_dev_control2_ltr_en,
output wire cfg_dev_control2_tlp_prefix_block,
output wire cfg_slot_control_electromech_il_ctl_pulse,
output wire cfg_root_control_syserr_corr_err_en,
output wire cfg_root_control_syserr_non_fatal_err_en,
output wire cfg_root_control_syserr_fatal_err_en,
output wire cfg_root_control_pme_int_en,
output wire cfg_aer_ecrc_check_en,
output wire cfg_aer_ecrc_gen_en,
output wire cfg_aer_rooterr_corr_err_reporting_en,
output wire cfg_aer_rooterr_non_fatal_err_reporting_en,
output wire cfg_aer_rooterr_fatal_err_reporting_en,
output wire cfg_aer_rooterr_corr_err_received,
output wire cfg_aer_rooterr_non_fatal_err_received,
output wire cfg_aer_rooterr_fatal_err_received,
output wire [6:0] cfg_vc_tcvc_map,
output wire drp_rdy,
output wire [15:0] drp_do,
output wire [63:0] dbg_vec_a,
output wire [63:0] dbg_vec_b,
output wire [11:0] dbg_vec_c,
output wire dbg_sclr_a,
output wire dbg_sclr_b,
output wire dbg_sclr_c,
output wire dbg_sclr_d,
output wire dbg_sclr_e,
output wire dbg_sclr_f,
output wire dbg_sclr_g,
output wire dbg_sclr_h,
output wire dbg_sclr_i,
output wire dbg_sclr_j,
output wire dbg_sclr_k,
output wire [63:0] trn_rdllp_data,
output wire [1:0] trn_rdllp_src_rdy,
output wire [11:0] pl_dbg_vec,
input phy_rdy_n,
input pipe_clk,
input user_clk,
input user_clk2,
output wire pipe_rx0_polarity_gt,
output wire pipe_rx1_polarity_gt,
output wire pipe_rx2_polarity_gt,
output wire pipe_rx3_polarity_gt,
output wire pipe_rx4_polarity_gt,
output wire pipe_rx5_polarity_gt,
output wire pipe_rx6_polarity_gt,
output wire pipe_rx7_polarity_gt,
output wire pipe_tx_deemph_gt,
output wire [2:0] pipe_tx_margin_gt,
output wire pipe_tx_rate_gt,
output wire pipe_tx_rcvr_det_gt,
output wire [1:0] pipe_tx0_char_is_k_gt,
output wire pipe_tx0_compliance_gt,
output wire [15:0] pipe_tx0_data_gt,
output wire pipe_tx0_elec_idle_gt,
output wire [1:0] pipe_tx0_powerdown_gt,
output wire [1:0] pipe_tx1_char_is_k_gt,
output wire pipe_tx1_compliance_gt,
output wire [15:0] pipe_tx1_data_gt,
output wire pipe_tx1_elec_idle_gt,
output wire [1:0] pipe_tx1_powerdown_gt,
output wire [1:0] pipe_tx2_char_is_k_gt,
output wire pipe_tx2_compliance_gt,
output wire [15:0] pipe_tx2_data_gt,
output wire pipe_tx2_elec_idle_gt,
output wire [1:0] pipe_tx2_powerdown_gt,
output wire [1:0] pipe_tx3_char_is_k_gt,
output wire pipe_tx3_compliance_gt,
output wire [15:0] pipe_tx3_data_gt,
output wire pipe_tx3_elec_idle_gt,
output wire [1:0] pipe_tx3_powerdown_gt,
output wire [1:0] pipe_tx4_char_is_k_gt,
output wire pipe_tx4_compliance_gt,
output wire [15:0] pipe_tx4_data_gt,
output wire pipe_tx4_elec_idle_gt,
output wire [1:0] pipe_tx4_powerdown_gt,
output wire [1:0] pipe_tx5_char_is_k_gt,
output wire pipe_tx5_compliance_gt,
output wire [15:0] pipe_tx5_data_gt,
output wire pipe_tx5_elec_idle_gt,
output wire [1:0] pipe_tx5_powerdown_gt,
output wire [1:0] pipe_tx6_char_is_k_gt,
output wire pipe_tx6_compliance_gt,
output wire [15:0] pipe_tx6_data_gt,
output wire pipe_tx6_elec_idle_gt,
output wire [1:0] pipe_tx6_powerdown_gt,
output wire [1:0] pipe_tx7_char_is_k_gt,
output wire pipe_tx7_compliance_gt,
output wire [15:0] pipe_tx7_data_gt,
output wire pipe_tx7_elec_idle_gt,
output wire [1:0] pipe_tx7_powerdown_gt,
input wire pipe_rx0_chanisaligned_gt,
input wire [1:0] pipe_rx0_char_is_k_gt,
input wire [15:0] pipe_rx0_data_gt,
input wire pipe_rx0_elec_idle_gt,
input wire pipe_rx0_phy_status_gt,
input wire [2:0] pipe_rx0_status_gt,
input wire pipe_rx0_valid_gt,
input wire pipe_rx1_chanisaligned_gt,
input wire [1:0] pipe_rx1_char_is_k_gt,
input wire [15:0] pipe_rx1_data_gt,
input wire pipe_rx1_elec_idle_gt,
input wire pipe_rx1_phy_status_gt,
input wire [2:0] pipe_rx1_status_gt,
input wire pipe_rx1_valid_gt,
input wire pipe_rx2_chanisaligned_gt,
input wire [1:0] pipe_rx2_char_is_k_gt,
input wire [15:0] pipe_rx2_data_gt,
input wire pipe_rx2_elec_idle_gt,
input wire pipe_rx2_phy_status_gt,
input wire [2:0] pipe_rx2_status_gt,
input wire pipe_rx2_valid_gt,
input wire pipe_rx3_chanisaligned_gt,
input wire [1:0] pipe_rx3_char_is_k_gt,
input wire [15:0] pipe_rx3_data_gt,
input wire pipe_rx3_elec_idle_gt,
input wire pipe_rx3_phy_status_gt,
input wire [2:0] pipe_rx3_status_gt,
input wire pipe_rx3_valid_gt,
input wire pipe_rx4_chanisaligned_gt,
input wire [1:0] pipe_rx4_char_is_k_gt,
input wire [15:0] pipe_rx4_data_gt,
input wire pipe_rx4_elec_idle_gt,
input wire pipe_rx4_phy_status_gt,
input wire [2:0] pipe_rx4_status_gt,
input wire pipe_rx4_valid_gt,
input wire pipe_rx5_chanisaligned_gt,
input wire [1:0] pipe_rx5_char_is_k_gt,
input wire [15:0] pipe_rx5_data_gt,
input wire pipe_rx5_elec_idle_gt,
input wire pipe_rx5_phy_status_gt,
input wire [2:0] pipe_rx5_status_gt,
input wire pipe_rx5_valid_gt,
input wire pipe_rx6_chanisaligned_gt,
input wire [1:0] pipe_rx6_char_is_k_gt,
input wire [15:0] pipe_rx6_data_gt,
input wire pipe_rx6_elec_idle_gt,
input wire pipe_rx6_phy_status_gt,
input wire [2:0] pipe_rx6_status_gt,
input wire pipe_rx6_valid_gt,
input wire pipe_rx7_chanisaligned_gt,
input wire [1:0] pipe_rx7_char_is_k_gt,
input wire [15:0] pipe_rx7_data_gt,
input wire pipe_rx7_elec_idle_gt,
input wire pipe_rx7_phy_status_gt,
input wire [2:0] pipe_rx7_status_gt,
input wire pipe_rx7_valid_gt
);
//wire declaration
// TRN Interface
wire [C_DATA_WIDTH-1:0] trn_td;
wire [REM_WIDTH-1:0] trn_trem;
wire trn_tsof;
wire trn_teof;
wire trn_tsrc_rdy;
wire trn_tsrc_dsc;
wire trn_terrfwd;
wire trn_tecrc_gen;
wire trn_tstr;
wire trn_tcfg_gnt;
wire [C_DATA_WIDTH-1:0] trn_rd;
wire [REM_WIDTH-1:0] trn_rrem;
wire trn_rdst_rdy;
wire trn_rsof;
wire trn_reof;
wire trn_rsrc_rdy;
wire trn_rsrc_dsc;
wire trn_rerrfwd;
wire [7:0] trn_rbar_hit;
wire sys_reset_n_d;
wire [1:0] pipe_rx0_char_is_k;
wire [1:0] pipe_rx1_char_is_k;
wire [1:0] pipe_rx2_char_is_k;
wire [1:0] pipe_rx3_char_is_k;
wire [1:0] pipe_rx4_char_is_k;
wire [1:0] pipe_rx5_char_is_k;
wire [1:0] pipe_rx6_char_is_k;
wire [1:0] pipe_rx7_char_is_k;
wire pipe_rx0_valid;
wire pipe_rx1_valid;
wire pipe_rx2_valid;
wire pipe_rx3_valid;
wire pipe_rx4_valid;
wire pipe_rx5_valid;
wire pipe_rx6_valid;
wire pipe_rx7_valid;
wire [15:0] pipe_rx0_data;
wire [15:0] pipe_rx1_data;
wire [15:0] pipe_rx2_data;
wire [15:0] pipe_rx3_data;
wire [15:0] pipe_rx4_data;
wire [15:0] pipe_rx5_data;
wire [15:0] pipe_rx6_data;
wire [15:0] pipe_rx7_data;
wire pipe_rx0_chanisaligned;
wire pipe_rx1_chanisaligned;
wire pipe_rx2_chanisaligned;
wire pipe_rx3_chanisaligned;
wire pipe_rx4_chanisaligned;
wire pipe_rx5_chanisaligned;
wire pipe_rx6_chanisaligned;
wire pipe_rx7_chanisaligned;
wire [2:0] pipe_rx0_status;
wire [2:0] pipe_rx1_status;
wire [2:0] pipe_rx2_status;
wire [2:0] pipe_rx3_status;
wire [2:0] pipe_rx4_status;
wire [2:0] pipe_rx5_status;
wire [2:0] pipe_rx6_status;
wire [2:0] pipe_rx7_status;
wire pipe_rx0_phy_status;
wire pipe_rx1_phy_status;
wire pipe_rx2_phy_status;
wire pipe_rx3_phy_status;
wire pipe_rx4_phy_status;
wire pipe_rx5_phy_status;
wire pipe_rx6_phy_status;
wire pipe_rx7_phy_status;
wire pipe_rx0_elec_idle;
wire pipe_rx1_elec_idle;
wire pipe_rx2_elec_idle;
wire pipe_rx3_elec_idle;
wire pipe_rx4_elec_idle;
wire pipe_rx5_elec_idle;
wire pipe_rx6_elec_idle;
wire pipe_rx7_elec_idle;
wire pipe_tx_reset;
wire pipe_tx_rate;
wire pipe_tx_deemph;
wire [2:0] pipe_tx_margin;
wire pipe_rx0_polarity;
wire pipe_rx1_polarity;
wire pipe_rx2_polarity;
wire pipe_rx3_polarity;
wire pipe_rx4_polarity;
wire pipe_rx5_polarity;
wire pipe_rx6_polarity;
wire pipe_rx7_polarity;
wire pipe_tx0_compliance;
wire pipe_tx1_compliance;
wire pipe_tx2_compliance;
wire pipe_tx3_compliance;
wire pipe_tx4_compliance;
wire pipe_tx5_compliance;
wire pipe_tx6_compliance;
wire pipe_tx7_compliance;
wire [1:0] pipe_tx0_char_is_k;
wire [1:0] pipe_tx1_char_is_k;
wire [1:0] pipe_tx2_char_is_k;
wire [1:0] pipe_tx3_char_is_k;
wire [1:0] pipe_tx4_char_is_k;
wire [1:0] pipe_tx5_char_is_k;
wire [1:0] pipe_tx6_char_is_k;
wire [1:0] pipe_tx7_char_is_k;
wire [15:0] pipe_tx0_data;
wire [15:0] pipe_tx1_data;
wire [15:0] pipe_tx2_data;
wire [15:0] pipe_tx3_data;
wire [15:0] pipe_tx4_data;
wire [15:0] pipe_tx5_data;
wire [15:0] pipe_tx6_data;
wire [15:0] pipe_tx7_data;
wire pipe_tx0_elec_idle;
wire pipe_tx1_elec_idle;
wire pipe_tx2_elec_idle;
wire pipe_tx3_elec_idle;
wire pipe_tx4_elec_idle;
wire pipe_tx5_elec_idle;
wire pipe_tx6_elec_idle;
wire pipe_tx7_elec_idle;
wire [1:0] pipe_tx0_powerdown;
wire [1:0] pipe_tx1_powerdown;
wire [1:0] pipe_tx2_powerdown;
wire [1:0] pipe_tx3_powerdown;
wire [1:0] pipe_tx4_powerdown;
wire [1:0] pipe_tx5_powerdown;
wire [1:0] pipe_tx6_powerdown;
wire [1:0] pipe_tx7_powerdown;
wire cfg_received_func_lvl_rst_n;
wire cfg_err_cpl_rdy_n;
wire cfg_interrupt_rdy_n;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
wire cfg_mgmt_rd_wr_done_n;
wire pl_phy_lnk_up_n;
wire cfg_err_aer_headerlog_set_n;
assign cfg_received_func_lvl_rst = ~cfg_received_func_lvl_rst_n;
assign cfg_err_cpl_rdy = ~cfg_err_cpl_rdy_n;
assign cfg_interrupt_rdy = ~cfg_interrupt_rdy_n;
assign cfg_mgmt_rd_wr_done = ~cfg_mgmt_rd_wr_done_n;
assign pl_phy_lnk_up = ~pl_phy_lnk_up_n;
assign cfg_err_aer_headerlog_set = ~cfg_err_aer_headerlog_set_n;
assign cfg_to_turnoff = cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_command_interrupt_disable,
1'b0,
cfg_command_serr_en,
5'b0,
cfg_command_bus_master_enable,
cfg_command_mem_enable,
cfg_command_io_enable};
assign cfg_dstatus = {10'h0,
cfg_trn_pending,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_non_fatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_no_snoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_max_payload,
cfg_dev_control_enable_ro,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_auto_bandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {4'b0,
cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_link_disable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {4'b0,
cfg_dev_control2_tlp_prefix_block,
cfg_dev_control2_ltr_en,
cfg_dev_control2_ido_cpl_en,
cfg_dev_control2_ido_req_en,
cfg_dev_control2_atomic_egress_block,
cfg_dev_control2_atomic_requester_en,
cfg_dev_control2_ari_forward_en,
cfg_dev_control2_cpl_timeout_dis,
cfg_dev_control2_cpl_timeout_val};
// Capture Bus/Device/Function number
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_bus_number_d <= 8'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_bus_number_d <= cfg_msg_data[15:8];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_device_number_d <= 5'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_device_number_d <= cfg_msg_data[7:3];
end // if (~cfg_msg_received)
end
always @(posedge user_clk_out) begin
if (~user_lnk_up)
begin
cfg_function_number_d <= 3'b0;
end // if (~user_lnk_up)
else if (~cfg_msg_received)
begin
cfg_function_number_d <= cfg_msg_data[2:0];
end // if (~cfg_msg_received)
end
pcie_7x_v1_3_axi_basic_top #(
.C_DATA_WIDTH (C_DATA_WIDTH), // RX/TX interface data width
.C_FAMILY ("X7"), // Targeted FPGA family
.C_ROOT_PORT ("FALSE"), // PCIe block is in root port mode
.C_PM_PRIORITY ("FALSE") // Disable TX packet boundary thrtl
) axi_basic_top (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
.s_axis_tx_tdata (s_axis_tx_tdata), // input
.s_axis_tx_tvalid (s_axis_tx_tvalid), // input
.s_axis_tx_tready (s_axis_tx_tready), // output
.s_axis_tx_tkeep (s_axis_tx_tkeep), // input
.s_axis_tx_tlast (s_axis_tx_tlast), // input
.s_axis_tx_tuser (s_axis_tx_tuser), // input
// AXI RX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata), // output
.m_axis_rx_tvalid (m_axis_rx_tvalid), // output
.m_axis_rx_tready (m_axis_rx_tready), // input
.m_axis_rx_tkeep (m_axis_rx_tkeep), // output
.m_axis_rx_tlast (m_axis_rx_tlast), // output
.m_axis_rx_tuser (m_axis_rx_tuser), // output
// User Misc.
//-----------
.user_turnoff_ok (cfg_turnoff_ok), // input
.user_tcfg_gnt (tx_cfg_gnt), // input
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
.trn_td (trn_td), // output
.trn_tsof (trn_tsof), // output
.trn_teof (trn_teof), // output
.trn_tsrc_rdy (trn_tsrc_rdy), // output
.trn_tdst_rdy (trn_tdst_rdy), // input
.trn_tsrc_dsc (trn_tsrc_dsc), // output
.trn_trem (trn_trem), // output
.trn_terrfwd (trn_terrfwd), // output
.trn_tstr (trn_tstr), // output
.trn_tbuf_av (tx_buf_av), // input
.trn_tecrc_gen (trn_tecrc_gen), // output
// TRN RX
//-----------
.trn_rd (trn_rd), // input
.trn_rsof (trn_rsof), // input
.trn_reof (trn_reof), // input
.trn_rsrc_rdy (trn_rsrc_rdy), // input
.trn_rdst_rdy (trn_rdst_rdy), // output
.trn_rsrc_dsc (trn_rsrc_dsc), // input
.trn_rrem (trn_rrem), // input
.trn_rerrfwd (trn_rerrfwd), // input
.trn_rbar_hit (trn_rbar_hit), // input
.trn_recrc_err (trn_recrc_err), // input
// TRN Misc.
//-----------
.trn_tcfg_req ( tx_cfg_req ), // input
.trn_tcfg_gnt ( trn_tcfg_gnt), // output
.trn_lnk_up ( user_lnk_up), // input
// Fuji3/Virtex6 PM
//-----------
.cfg_pcie_link_state (cfg_pcie_link_state), // input
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to (1'b0), // input NOT USED FOR EP
.cfg_pmcsr_powerstate (cfg_pmcsr_powerstate), // input
.trn_rdllp_data (32'b0), // input - Not used in 7-series
.trn_rdllp_src_rdy (1'b0), // input -- Not used in 7-series
// Power Mgmt for S6/V6
//-----------
.cfg_to_turnoff (cfg_to_turnoff), // input
.cfg_turnoff_ok (cfg_turnoff_ok_w), // output
// System
//-----------
.user_clk (user_clk_out), // input
.user_rst (user_reset), // input
.np_counter () // output
);
//-------------------------------------------------------
// PCI Express Pipe Wrapper
//-------------------------------------------------------
pcie_7x_v1_3_pcie_7x # (
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_MULTIHEADER ( AER_CAP_MULTIHEADER ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_OPTIONAL_ERR_SUPPORT ( AER_CAP_OPTIONAL_ERR_SUPPORT ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 (ALLOW_X8_GEN2),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.CAPABILITIES_PTR( CAPABILITIES_PTR ),
.CFG_ECRC_ERR_CPLSTAT ( CFG_ECRC_ERR_CPLSTAT ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS (CRM_MODULE_RSTS),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEV_CONTROL_EXT_TAG_DEFAULT ( DEV_CONTROL_EXT_TAG_DEFAULT ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_POISONED_RESP (DISABLE_RX_POISONED_RESP),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.DEV_CAP2_ARI_FORWARDING_SUPPORTED(DEV_CAP2_ARI_FORWARDING_SUPPORTED),
.DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED (DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED),
.DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED (DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED),
.DEV_CAP2_CAS128_COMPLETER_SUPPORTED (DEV_CAP2_CAS128_COMPLETER_SUPPORTED),
.DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED (DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED),
.DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED (DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED),
.DEV_CAP2_LTR_MECHANISM_SUPPORTED (DEV_CAP2_LTR_MECHANISM_SUPPORTED),
.DEV_CAP2_MAX_ENDEND_TLP_PREFIXES (DEV_CAP2_MAX_ENDEND_TLP_PREFIXES),
.DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING (DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING),
.DEV_CAP2_TPH_COMPLETER_SUPPORTED (DEV_CAP2_TPH_COMPLETER_SUPPORTED),
.DISABLE_ERR_MSG (DISABLE_ERR_MSG),
.DISABLE_LOCKED_FILTER (DISABLE_LOCKED_FILTER),
.DISABLE_PPM_FILTER (DISABLE_PPM_FILTER),
.ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED (ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED),
.ENABLE_MSG_ROUTE( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0( ENTER_RVRY_EI_L0 ),
.EXIT_LOOPBACK_ON_EI (EXIT_LOOPBACK_ON_EI),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.INTERRUPT_STAT_AUTO (INTERRUPT_STAT_AUTO),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_OPTIONALITY ( LINK_CAP_ASPM_OPTIONALITY ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP (LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23( LINK_CAP_RSVD_23 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MPS_FORCE (MPS_FORCE),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_NEXTPTR( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML0S_TIMEOUT_EN ( PM_ASPML0S_TIMEOUT_EN ),
.PM_ASPML0S_TIMEOUT_FUNC ( PM_ASPML0S_TIMEOUT_FUNC ),
.PM_ASPM_FASTEXIT ( PM_ASPM_FASTEXIT ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_D1SUPPORT( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT( PM_CAP_D2SUPPORT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_NOSOFTRST( PM_CSR_NOSOFTRST ),
.PM_DATA0( PM_DATA0 ),
.PM_DATA1( PM_DATA1 ),
.PM_DATA2( PM_DATA2 ),
.PM_DATA3( PM_DATA3 ),
.PM_DATA4( PM_DATA4 ),
.PM_DATA5( PM_DATA5 ),
.PM_DATA6( PM_DATA6 ),
.PM_DATA7( PM_DATA7 ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_MF (PM_MF),
.RBAR_BASE_PTR (RBAR_BASE_PTR),
.RBAR_CAP_CONTROL_ENCODEDBAR0 (RBAR_CAP_CONTROL_ENCODEDBAR0),
.RBAR_CAP_CONTROL_ENCODEDBAR1 (RBAR_CAP_CONTROL_ENCODEDBAR1),
.RBAR_CAP_CONTROL_ENCODEDBAR2 (RBAR_CAP_CONTROL_ENCODEDBAR2),
.RBAR_CAP_CONTROL_ENCODEDBAR3 (RBAR_CAP_CONTROL_ENCODEDBAR3),
.RBAR_CAP_CONTROL_ENCODEDBAR4 (RBAR_CAP_CONTROL_ENCODEDBAR4),
.RBAR_CAP_CONTROL_ENCODEDBAR5 (RBAR_CAP_CONTROL_ENCODEDBAR5),
.RBAR_CAP_ID (RBAR_CAP_ID),
.RBAR_CAP_INDEX0 (RBAR_CAP_INDEX0),
.RBAR_CAP_INDEX1 (RBAR_CAP_INDEX1),
.RBAR_CAP_INDEX2 (RBAR_CAP_INDEX2),
.RBAR_CAP_INDEX3 (RBAR_CAP_INDEX3),
.RBAR_CAP_INDEX4 (RBAR_CAP_INDEX4),
.RBAR_CAP_INDEX5 (RBAR_CAP_INDEX5),
.RBAR_CAP_NEXTPTR (RBAR_CAP_NEXTPTR),
.RBAR_CAP_ON (RBAR_CAP_ON),
.RBAR_CAP_SUP0 (RBAR_CAP_SUP0),
.RBAR_CAP_SUP1 (RBAR_CAP_SUP1),
.RBAR_CAP_SUP2 (RBAR_CAP_SUP2),
.RBAR_CAP_SUP3 (RBAR_CAP_SUP3),
.RBAR_CAP_SUP4 (RBAR_CAP_SUP4),
.RBAR_CAP_SUP5 (RBAR_CAP_SUP5),
.RBAR_CAP_VERSION (RBAR_CAP_VERSION),
.RBAR_NUM (RBAR_NUM),
.RECRC_CHK (RECRC_CHK),
.RECRC_CHK_TRIM (RECRC_CHK_TRIM),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.RP_AUTO_SPD ( RP_AUTO_SPD ),
.RP_AUTO_SPD_LOOPCNT ( RP_AUTO_SPD_LOOPCNT ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SSL_MESSAGE_AUTO (SSL_MESSAGE_AUTO),
.TECRC_EP_INV ( TECRC_EP_INV ),
.TL_RBYPASS(TL_RBYPASS),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.TRN_DW (TRN_DW),
.TRN_NP_FC (TRN_NP_FC),
.UPCONFIG_CAPABLE( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.UR_ATOMIC (UR_ATOMIC),
.UR_CFG1 (UR_CFG1),
.UR_INV_REQ(UR_INV_REQ),
.UR_PRS_RESPONSE (UR_PRS_RESPONSE),
.USER_CLK2_DIV2 (USER_CLK2_DIV2),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.USE_RID_PINS (USE_RID_PINS),
.VC0_CPL_INFINITE( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPD (VC0_TOTAL_CREDITS_NPD),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION( VSEC_CAP_VERSION )
) pcie_7x_i (
.trn_lnk_up ( trn_lnk_up ),
.trn_clk ( user_clk_out ),
.lnk_clk_en ( lnk_clk_en),
.user_rst_n ( user_rst_n ),
.received_func_lvl_rst_n ( cfg_received_func_lvl_rst_n ),
.sys_rst_n (~phy_rdy_n),
.pl_rst_n ( 1'b1 ),
.dl_rst_n ( 1'b1 ),
.tl_rst_n ( 1'b1 ),
.cm_sticky_rst_n ( 1'b1 ),
.func_lvl_rst_n ( func_lvl_rst_n ),
.cm_rst_n ( cm_rst_n ),
.trn_rbar_hit ( trn_rbar_hit ),
.trn_rd ( trn_rd ),
.trn_recrc_err ( trn_recrc_err ),
.trn_reof ( trn_reof ),
.trn_rerrfwd ( trn_rerrfwd ),
.trn_rrem ( trn_rrem ),
.trn_rsof ( trn_rsof ),
.trn_rsrc_dsc ( trn_rsrc_dsc ),
.trn_rsrc_rdy ( trn_rsrc_rdy ),
.trn_rdst_rdy ( trn_rdst_rdy ),
.trn_rnp_ok ( rx_np_ok ),
.trn_rnp_req ( rx_np_req ),
.trn_rfcp_ret ( 1'b1 ),
.trn_tbuf_av ( tx_buf_av ),
.trn_tcfg_req ( tx_cfg_req ),
.trn_tdllp_dst_rdy ( ),
.trn_tdst_rdy ( trn_tdst_rdy ),
.trn_terr_drop ( tx_err_drop ),
.trn_tcfg_gnt ( trn_tcfg_gnt ),
.trn_td ( trn_td ),
.trn_tdllp_data ( 32'b0 ),
.trn_tdllp_src_rdy ( 1'b0 ),
.trn_tecrc_gen ( trn_tecrc_gen ),
.trn_teof ( trn_teof ),
.trn_terrfwd ( trn_terrfwd ),
.trn_trem ( trn_trem),
.trn_tsof ( trn_tsof ),
.trn_tsrc_dsc ( trn_tsrc_dsc ),
.trn_tsrc_rdy ( trn_tsrc_rdy ),
.trn_tstr ( trn_tstr ),
.trn_fc_cpld ( fc_cpld ),
.trn_fc_cplh ( fc_cplh ),
.trn_fc_npd ( fc_npd ),
.trn_fc_nph ( fc_nph ),
.trn_fc_pd ( fc_pd ),
.trn_fc_ph ( fc_ph ),
.trn_fc_sel ( fc_sel ),
.cfg_dev_id (cfg_dev_id),
.cfg_vend_id (cfg_vend_id),
.cfg_rev_id (cfg_rev_id),
.cfg_subsys_id (cfg_subsys_id),
.cfg_subsys_vend_id (cfg_subsys_vend_id),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bridge_serr_en (cfg_bridge_serr_en),
.cfg_command_bus_master_enable ( cfg_command_bus_master_enable ),
.cfg_command_interrupt_disable ( cfg_command_interrupt_disable ),
.cfg_command_io_enable ( cfg_command_io_enable ),
.cfg_command_mem_enable ( cfg_command_mem_enable ),
.cfg_command_serr_en ( cfg_command_serr_en ),
.cfg_dev_control_aux_power_en ( cfg_dev_control_aux_power_en ),
.cfg_dev_control_corr_err_reporting_en ( cfg_dev_control_corr_err_reporting_en ),
.cfg_dev_control_enable_ro ( cfg_dev_control_enable_ro ),
.cfg_dev_control_ext_tag_en ( cfg_dev_control_ext_tag_en ),
.cfg_dev_control_fatal_err_reporting_en ( cfg_dev_control_fatal_err_reporting_en ),
.cfg_dev_control_max_payload ( cfg_dev_control_max_payload ),
.cfg_dev_control_max_read_req ( cfg_dev_control_max_read_req ),
.cfg_dev_control_non_fatal_reporting_en ( cfg_dev_control_non_fatal_reporting_en ),
.cfg_dev_control_no_snoop_en ( cfg_dev_control_no_snoop_en ),
.cfg_dev_control_phantom_en ( cfg_dev_control_phantom_en ),
.cfg_dev_control_ur_err_reporting_en ( cfg_dev_control_ur_err_reporting_en ),
.cfg_dev_control2_cpl_timeout_dis ( cfg_dev_control2_cpl_timeout_dis ),
.cfg_dev_control2_cpl_timeout_val ( cfg_dev_control2_cpl_timeout_val ),
.cfg_dev_control2_ari_forward_en ( cfg_dev_control2_ari_forward_en),
.cfg_dev_control2_atomic_requester_en ( cfg_dev_control2_atomic_requester_en),
.cfg_dev_control2_atomic_egress_block ( cfg_dev_control2_atomic_egress_block),
.cfg_dev_control2_ido_req_en ( cfg_dev_control2_ido_req_en),
.cfg_dev_control2_ido_cpl_en ( cfg_dev_control2_ido_cpl_en),
.cfg_dev_control2_ltr_en ( cfg_dev_control2_ltr_en),
.cfg_dev_control2_tlp_prefix_block ( cfg_dev_control2_tlp_prefix_block),
.cfg_dev_status_corr_err_detected ( cfg_dev_status_corr_err_detected ),
.cfg_dev_status_fatal_err_detected ( cfg_dev_status_fatal_err_detected ),
.cfg_dev_status_non_fatal_err_detected ( cfg_dev_status_non_fatal_err_detected ),
.cfg_dev_status_ur_detected ( cfg_dev_status_ur_detected ),
.cfg_mgmt_do ( cfg_mgmt_do ),
.cfg_err_aer_headerlog_set_n ( cfg_err_aer_headerlog_set_n),
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog),
.cfg_err_cpl_rdy_n ( cfg_err_cpl_rdy_n ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_rdy_n ( cfg_interrupt_rdy_n ),
.cfg_link_control_rcb ( cfg_link_control_rcb ),
.cfg_link_control_aspm_control ( cfg_link_control_aspm_control ),
.cfg_link_control_auto_bandwidth_int_en ( cfg_link_control_auto_bandwidth_int_en ),
.cfg_link_control_bandwidth_int_en ( cfg_link_control_bandwidth_int_en ),
.cfg_link_control_clock_pm_en ( cfg_link_control_clock_pm_en ),
.cfg_link_control_common_clock ( cfg_link_control_common_clock ),
.cfg_link_control_extended_sync ( cfg_link_control_extended_sync ),
.cfg_link_control_hw_auto_width_dis ( cfg_link_control_hw_auto_width_dis ),
.cfg_link_control_link_disable ( cfg_link_control_link_disable ),
.cfg_link_control_retrain_link ( cfg_link_control_retrain_link ),
.cfg_link_status_auto_bandwidth_status ( cfg_link_status_auto_bandwidth_status ),
.cfg_link_status_bandwidth_status ( cfg_link_status_bandwidth_status ),
.cfg_link_status_current_speed ( cfg_link_status_current_speed ),
.cfg_link_status_dll_active ( cfg_link_status_dll_active ),
.cfg_link_status_link_training ( cfg_link_status_link_training ),
.cfg_link_status_negotiated_width ( cfg_link_status_negotiated_width),
.cfg_msg_data ( cfg_msg_data ),
.cfg_msg_received ( cfg_msg_received ),
.cfg_msg_received_assert_int_a ( cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b ( cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c ( cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d ( cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a ( cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b ( cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c ( cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d ( cfg_msg_received_deassert_int_d),
.cfg_msg_received_err_cor ( cfg_msg_received_err_cor),
.cfg_msg_received_err_fatal ( cfg_msg_received_err_fatal),
.cfg_msg_received_err_non_fatal ( cfg_msg_received_err_non_fatal),
.cfg_msg_received_pm_as_nak ( cfg_msg_received_pm_as_nak),
.cfg_msg_received_pme_to ( cfg_msg_received_pme_to ),
.cfg_msg_received_pme_to_ack ( cfg_msg_received_pme_to_ack),
.cfg_msg_received_pm_pme ( cfg_msg_received_pm_pme),
.cfg_msg_received_setslotpowerlimit ( cfg_msg_received_setslotpowerlimit),
.cfg_msg_received_unlock ( cfg_msg_received_unlock),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate ( cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status ( cfg_pmcsr_pme_status),
.cfg_pm_rcv_as_req_l1_n ( cfg_pm_rcv_as_req_l1_n),
.cfg_pm_rcv_enter_l1_n ( cfg_pm_rcv_enter_l1_n),
.cfg_pm_rcv_enter_l23_n ( cfg_pm_rcv_enter_l23_n),
.cfg_pm_rcv_req_ack_n ( cfg_pm_rcv_req_ack_n),
.cfg_mgmt_rd_wr_done_n ( cfg_mgmt_rd_wr_done_n ),
.cfg_slot_control_electromech_il_ctl_pulse (cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en ( cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en ( cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en ( cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en ( cfg_root_control_pme_int_en ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
.cfg_aer_rooterr_corr_err_reporting_en ( cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en( cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en ( cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received ( cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received ( cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received ( cfg_aer_rooterr_fatal_err_received),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_transaction ( cfg_transaction),
.cfg_transaction_addr ( cfg_transaction_addr),
.cfg_transaction_type ( cfg_transaction_type),
.cfg_vc_tcvc_map ( cfg_vc_tcvc_map),
.cfg_mgmt_byte_en_n ( cfg_mgmt_byte_en_n ),
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_ds_bus_number ( cfg_ds_bus_number ),
.cfg_ds_device_number ( cfg_ds_device_number ),
.cfg_ds_function_number ( cfg_ds_function_number ),
.cfg_dsn ( cfg_dsn ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_err_acs_n ( 1'b1 ),
.cfg_err_cor_n ( cfg_err_cor_n ),
.cfg_err_cpl_abort_n ( cfg_err_cpl_abort_n ),
.cfg_err_cpl_timeout_n ( cfg_err_cpl_timeout_n ),
.cfg_err_cpl_unexpect_n ( cfg_err_cpl_unexpect_n ),
.cfg_err_ecrc_n ( cfg_err_ecrc_n ),
.cfg_err_locked_n ( cfg_err_locked_n ),
.cfg_err_posted_n ( cfg_err_posted_n ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_ur_n ( cfg_err_ur_n ),
.cfg_err_malformed_n ( cfg_err_malformed_n ),
.cfg_err_poisoned_n ( cfg_err_poisoned_n),
.cfg_err_atomic_egress_blocked_n ( cfg_err_atomic_egress_blocked_n ),
.cfg_err_mc_blocked_n ( cfg_err_mc_blocked_n ),
.cfg_err_internal_uncor_n ( cfg_err_internal_uncor_n ),
.cfg_err_internal_cor_n ( cfg_err_internal_cor_n ),
.cfg_err_norecovery_n ( cfg_err_norecovery_n ),
.cfg_interrupt_assert_n ( cfg_interrupt_assert_n ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_n ( cfg_interrupt_n ),
.cfg_interrupt_stat_n ( cfg_interrupt_stat_n),
.cfg_pm_send_pme_to_n ( cfg_pm_send_pme_to_n ),
.cfg_pm_turnoff_ok_n ( cfg_turnoff_ok_w ),
.cfg_pm_wake_n ( cfg_pm_wake_n ),
.cfg_pm_halt_aspm_l0s_n ( cfg_pm_halt_aspm_l0s_n ),
.cfg_pm_halt_aspm_l1_n ( cfg_pm_halt_aspm_l1_n ),
.cfg_pm_force_state_en_n ( cfg_pm_force_state_en_n ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_force_mps ( cfg_force_mps ),
.cfg_force_common_clock_off ( cfg_force_common_clock_off ),
.cfg_force_extended_sync_on ( cfg_force_extended_sync_on ),
.cfg_port_number ( cfg_port_number ),
.cfg_mgmt_rd_en_n ( cfg_mgmt_rd_en_n ),
.cfg_trn_pending_n ( ~cfg_trn_pending ),
.cfg_mgmt_wr_en_n ( cfg_mgmt_wr_en_n ),
.cfg_mgmt_wr_readonly_n ( cfg_mgmt_wr_readonly_n ),
.cfg_mgmt_wr_rw1c_as_rw_n ( cfg_mgmt_wr_rw1c_as_rw_n ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_phy_lnk_up_n ( pl_phy_lnk_up_n ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_rx_pm_state ( pl_rx_pm_state ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_tx_pm_state ( pl_tx_pm_state ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_downstream_deemph_source ( pl_downstream_deemph_source ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_transmit_hot_rst ( pl_transmit_hot_rst ),
.pl_directed_ltssm_new_vld ( pl_directed_ltssm_new_vld ),
.pl_directed_ltssm_new ( pl_directed_ltssm_new ),
.pl_directed_ltssm_stall ( pl_directed_ltssm_stall ),
.pl_directed_change_done ( pl_directed_change_done ),
.dbg_sclr_a ( dbg_sclr_a ),
.dbg_sclr_b ( dbg_sclr_b ),
.dbg_sclr_c ( dbg_sclr_c ),
.dbg_sclr_d ( dbg_sclr_d ),
.dbg_sclr_e ( dbg_sclr_e ),
.dbg_sclr_f ( dbg_sclr_f ),
.dbg_sclr_g ( dbg_sclr_g ),
.dbg_sclr_h ( dbg_sclr_h ),
.dbg_sclr_i ( dbg_sclr_i ),
.dbg_sclr_j ( dbg_sclr_j ),
.dbg_sclr_k ( dbg_sclr_k ),
.dbg_vec_a ( dbg_vec_a ),
.dbg_vec_b ( dbg_vec_b ),
.dbg_vec_c ( dbg_vec_c ),
.pl_dbg_vec ( pl_dbg_vec ),
.dbg_mode ( dbg_mode ),
.dbg_sub_mode ( dbg_sub_mode ),
.pl_dbg_mode ( pl_dbg_mode ),
.drp_do ( drp_do ),
.drp_rdy ( drp_rdy ),
.drp_clk ( drp_clk ),
.drp_addr ( drp_addr ),
.drp_en ( drp_en ),
.drp_di ( drp_di ),
.drp_we ( drp_we ),
.ll2_tlp_rcv ( 1'b0 ),
.ll2_send_enter_l1 ( 1'b0 ),
.ll2_send_enter_l23 ( 1'b0 ),
.ll2_send_as_req_l1 ( 1'b0 ),
.ll2_send_pm_ack ( 1'b0 ),
.ll2_suspend_now ( 1'b0 ),
.ll2_tfc_init1_seq ( ),
.ll2_tfc_init2_seq ( ),
.ll2_suspend_ok ( ),
.ll2_tx_idle ( ),
.ll2_link_status ( ),
.ll2_receiver_err ( ),
.ll2_protocol_err ( ),
.ll2_bad_tlp_err ( ),
.ll2_bad_dllp_err ( ),
.ll2_replay_ro_err ( ),
.ll2_replay_to_err ( ),
.tl2_ppm_suspend_req ( 1'b0 ),
.tl2_aspm_suspend_credit_check ( 1'b0 ),
.tl2_ppm_suspend_ok ( ),
.tl2_aspm_suspend_req ( ),
.tl2_aspm_suspend_credit_check_ok ( ),
.tl2_err_hdr ( ),
.tl2_err_malformed ( ),
.tl2_err_rxoverflow ( ),
.tl2_err_fcpe ( ),
.pl2_directed_lstate ( 5'b0 ),
.pl2_suspend_ok ( ),
.pl2_recovery ( ),
.pl2_rx_elec_idle ( ),
.pl2_rx_pm_state ( ),
.pl2_l0_req ( ),
.pl2_link_up ( ),
.pl2_receiver_err ( ),
.trn_rdllp_data (trn_rdllp_data ),
.trn_rdllp_src_rdy (trn_rdllp_src_rdy ),
.pipe_clk ( pipe_clk ),
.user_clk2 ( user_clk2 ),
.user_clk ( user_clk ),
.user_clk_prebuf ( 1'b0 ),
.user_clk_prebuf_en ( 1'b0 ),
.pipe_rx0_polarity ( pipe_rx0_polarity ),
.pipe_rx1_polarity ( pipe_rx1_polarity ),
.pipe_rx2_polarity ( pipe_rx2_polarity ),
.pipe_rx3_polarity ( pipe_rx3_polarity ),
.pipe_rx4_polarity ( pipe_rx4_polarity ),
.pipe_rx5_polarity ( pipe_rx5_polarity ),
.pipe_rx6_polarity ( pipe_rx6_polarity ),
.pipe_rx7_polarity ( pipe_rx7_polarity ),
.pipe_tx0_compliance ( pipe_tx0_compliance ),
.pipe_tx1_compliance ( pipe_tx1_compliance ),
.pipe_tx2_compliance ( pipe_tx2_compliance ),
.pipe_tx3_compliance ( pipe_tx3_compliance ),
.pipe_tx4_compliance ( pipe_tx4_compliance ),
.pipe_tx5_compliance ( pipe_tx5_compliance ),
.pipe_tx6_compliance ( pipe_tx6_compliance ),
.pipe_tx7_compliance ( pipe_tx7_compliance ),
.pipe_tx0_char_is_k ( pipe_tx0_char_is_k ),
.pipe_tx1_char_is_k ( pipe_tx1_char_is_k ),
.pipe_tx2_char_is_k ( pipe_tx2_char_is_k ),
.pipe_tx3_char_is_k ( pipe_tx3_char_is_k ),
.pipe_tx4_char_is_k ( pipe_tx4_char_is_k ),
.pipe_tx5_char_is_k ( pipe_tx5_char_is_k ),
.pipe_tx6_char_is_k ( pipe_tx6_char_is_k ),
.pipe_tx7_char_is_k ( pipe_tx7_char_is_k ),
.pipe_tx0_data ( pipe_tx0_data ),
.pipe_tx1_data ( pipe_tx1_data ),
.pipe_tx2_data ( pipe_tx2_data ),
.pipe_tx3_data ( pipe_tx3_data ),
.pipe_tx4_data ( pipe_tx4_data ),
.pipe_tx5_data ( pipe_tx5_data ),
.pipe_tx6_data ( pipe_tx6_data ),
.pipe_tx7_data ( pipe_tx7_data ),
.pipe_tx0_elec_idle ( pipe_tx0_elec_idle ),
.pipe_tx1_elec_idle ( pipe_tx1_elec_idle ),
.pipe_tx2_elec_idle ( pipe_tx2_elec_idle ),
.pipe_tx3_elec_idle ( pipe_tx3_elec_idle ),
.pipe_tx4_elec_idle ( pipe_tx4_elec_idle ),
.pipe_tx5_elec_idle ( pipe_tx5_elec_idle ),
.pipe_tx6_elec_idle ( pipe_tx6_elec_idle ),
.pipe_tx7_elec_idle ( pipe_tx7_elec_idle ),
.pipe_tx0_powerdown ( pipe_tx0_powerdown ),
.pipe_tx1_powerdown ( pipe_tx1_powerdown ),
.pipe_tx2_powerdown ( pipe_tx2_powerdown ),
.pipe_tx3_powerdown ( pipe_tx3_powerdown ),
.pipe_tx4_powerdown ( pipe_tx4_powerdown ),
.pipe_tx5_powerdown ( pipe_tx5_powerdown ),
.pipe_tx6_powerdown ( pipe_tx6_powerdown ),
.pipe_tx7_powerdown ( pipe_tx7_powerdown ),
.pipe_rx0_char_is_k ( pipe_rx0_char_is_k ),
.pipe_rx1_char_is_k ( pipe_rx1_char_is_k ),
.pipe_rx2_char_is_k ( pipe_rx2_char_is_k ),
.pipe_rx3_char_is_k ( pipe_rx3_char_is_k ),
.pipe_rx4_char_is_k ( pipe_rx4_char_is_k ),
.pipe_rx5_char_is_k ( pipe_rx5_char_is_k ),
.pipe_rx6_char_is_k ( pipe_rx6_char_is_k ),
.pipe_rx7_char_is_k ( pipe_rx7_char_is_k ),
.pipe_rx0_valid ( pipe_rx0_valid ),
.pipe_rx1_valid ( pipe_rx1_valid ),
.pipe_rx2_valid ( pipe_rx2_valid ),
.pipe_rx3_valid ( pipe_rx3_valid ),
.pipe_rx4_valid ( pipe_rx4_valid ),
.pipe_rx5_valid ( pipe_rx5_valid ),
.pipe_rx6_valid ( pipe_rx6_valid ),
.pipe_rx7_valid ( pipe_rx7_valid ),
.pipe_rx0_data ( pipe_rx0_data ),
.pipe_rx1_data ( pipe_rx1_data ),
.pipe_rx2_data ( pipe_rx2_data ),
.pipe_rx3_data ( pipe_rx3_data ),
.pipe_rx4_data ( pipe_rx4_data ),
.pipe_rx5_data ( pipe_rx5_data ),
.pipe_rx6_data ( pipe_rx6_data ),
.pipe_rx7_data ( pipe_rx7_data ),
.pipe_rx0_chanisaligned ( pipe_rx0_chanisaligned ),
.pipe_rx1_chanisaligned ( pipe_rx1_chanisaligned ),
.pipe_rx2_chanisaligned ( pipe_rx2_chanisaligned ),
.pipe_rx3_chanisaligned ( pipe_rx3_chanisaligned ),
.pipe_rx4_chanisaligned ( pipe_rx4_chanisaligned ),
.pipe_rx5_chanisaligned ( pipe_rx5_chanisaligned ),
.pipe_rx6_chanisaligned ( pipe_rx6_chanisaligned ),
.pipe_rx7_chanisaligned ( pipe_rx7_chanisaligned ),
.pipe_rx0_status ( pipe_rx0_status ),
.pipe_rx1_status ( pipe_rx1_status ),
.pipe_rx2_status ( pipe_rx2_status ),
.pipe_rx3_status ( pipe_rx3_status ),
.pipe_rx4_status ( pipe_rx4_status ),
.pipe_rx5_status ( pipe_rx5_status ),
.pipe_rx6_status ( pipe_rx6_status ),
.pipe_rx7_status ( pipe_rx7_status ),
.pipe_rx0_phy_status ( pipe_rx0_phy_status ),
.pipe_rx1_phy_status ( pipe_rx1_phy_status ),
.pipe_rx2_phy_status ( pipe_rx2_phy_status ),
.pipe_rx3_phy_status ( pipe_rx3_phy_status ),
.pipe_rx4_phy_status ( pipe_rx4_phy_status ),
.pipe_rx5_phy_status ( pipe_rx5_phy_status ),
.pipe_rx6_phy_status ( pipe_rx6_phy_status ),
.pipe_rx7_phy_status ( pipe_rx7_phy_status ),
.pipe_tx_deemph ( pipe_tx_deemph ),
.pipe_tx_margin ( pipe_tx_margin ),
.pipe_tx_reset ( pipe_tx_reset ),
.pipe_tx_rcvr_det ( pipe_tx_rcvr_det ),
.pipe_tx_rate ( pipe_tx_rate ),
.pipe_rx0_elec_idle ( pipe_rx0_elec_idle ),
.pipe_rx1_elec_idle ( pipe_rx1_elec_idle ),
.pipe_rx2_elec_idle ( pipe_rx2_elec_idle ),
.pipe_rx3_elec_idle ( pipe_rx3_elec_idle ),
.pipe_rx4_elec_idle ( pipe_rx4_elec_idle ),
.pipe_rx5_elec_idle ( pipe_rx5_elec_idle ),
.pipe_rx6_elec_idle ( pipe_rx6_elec_idle ),
.pipe_rx7_elec_idle ( pipe_rx7_elec_idle )
);
//------------------------------------------------------------------------------------------------------------------//
// PIPE Interface PIPELINE Module //
//------------------------------------------------------------------------------------------------------------------//
pcie_7x_v1_3_pcie_pipe_pipeline # (
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES )
)
pcie_pipe_pipeline_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i (pipe_tx_rcvr_det),
.pipe_tx_reset_i (1'b0), //MV?
.pipe_tx_rate_i (pipe_tx_rate),
.pipe_tx_deemph_i (pipe_tx_deemph),
.pipe_tx_margin_i (pipe_tx_margin),
.pipe_tx_swing_i (1'b0),
.pipe_tx_rcvr_det_o (pipe_tx_rcvr_det_gt),
.pipe_tx_reset_o ( ),
.pipe_tx_rate_o (pipe_tx_rate_gt),
.pipe_tx_deemph_o (pipe_tx_deemph_gt),
.pipe_tx_margin_o (pipe_tx_margin_gt),
.pipe_tx_swing_o ( ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o (pipe_rx0_char_is_k ),
.pipe_rx0_data_o (pipe_rx0_data ),
.pipe_rx0_valid_o (pipe_rx0_valid ),
.pipe_rx0_chanisaligned_o (pipe_rx0_chanisaligned ),
.pipe_rx0_status_o (pipe_rx0_status ),
.pipe_rx0_phy_status_o (pipe_rx0_phy_status ),
.pipe_rx0_elec_idle_i (pipe_rx0_elec_idle_gt ),
.pipe_rx0_polarity_i (pipe_rx0_polarity ),
.pipe_tx0_compliance_i (pipe_tx0_compliance ),
.pipe_tx0_char_is_k_i (pipe_tx0_char_is_k ),
.pipe_tx0_data_i (pipe_tx0_data ),
.pipe_tx0_elec_idle_i (pipe_tx0_elec_idle ),
.pipe_tx0_powerdown_i (pipe_tx0_powerdown ),
.pipe_rx0_char_is_k_i (pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_i (pipe_rx0_data_gt ),
.pipe_rx0_valid_i (pipe_rx0_valid_gt ),
.pipe_rx0_chanisaligned_i (pipe_rx0_chanisaligned_gt),
.pipe_rx0_status_i (pipe_rx0_status_gt ),
.pipe_rx0_phy_status_i (pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle_o (pipe_rx0_elec_idle ),
.pipe_rx0_polarity_o (pipe_rx0_polarity_gt ),
.pipe_tx0_compliance_o (pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k_o (pipe_tx0_char_is_k_gt ),
.pipe_tx0_data_o (pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_o (pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_o (pipe_tx0_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o (pipe_rx1_char_is_k ),
.pipe_rx1_data_o (pipe_rx1_data ),
.pipe_rx1_valid_o (pipe_rx1_valid ),
.pipe_rx1_chanisaligned_o (pipe_rx1_chanisaligned ),
.pipe_rx1_status_o (pipe_rx1_status ),
.pipe_rx1_phy_status_o (pipe_rx1_phy_status ),
.pipe_rx1_elec_idle_i (pipe_rx1_elec_idle_gt ),
.pipe_rx1_polarity_i (pipe_rx1_polarity ),
.pipe_tx1_compliance_i (pipe_tx1_compliance ),
.pipe_tx1_char_is_k_i (pipe_tx1_char_is_k ),
.pipe_tx1_data_i (pipe_tx1_data ),
.pipe_tx1_elec_idle_i (pipe_tx1_elec_idle ),
.pipe_tx1_powerdown_i (pipe_tx1_powerdown ),
.pipe_rx1_char_is_k_i (pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_i (pipe_rx1_data_gt ),
.pipe_rx1_valid_i (pipe_rx1_valid_gt ),
.pipe_rx1_chanisaligned_i (pipe_rx1_chanisaligned_gt),
.pipe_rx1_status_i (pipe_rx1_status_gt ),
.pipe_rx1_phy_status_i (pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle_o (pipe_rx1_elec_idle ),
.pipe_rx1_polarity_o (pipe_rx1_polarity_gt ),
.pipe_tx1_compliance_o (pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k_o (pipe_tx1_char_is_k_gt ),
.pipe_tx1_data_o (pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_o (pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_o (pipe_tx1_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o (pipe_rx2_char_is_k ),
.pipe_rx2_data_o (pipe_rx2_data ),
.pipe_rx2_valid_o (pipe_rx2_valid ),
.pipe_rx2_chanisaligned_o (pipe_rx2_chanisaligned ),
.pipe_rx2_status_o (pipe_rx2_status ),
.pipe_rx2_phy_status_o (pipe_rx2_phy_status ),
.pipe_rx2_elec_idle_i (pipe_rx2_elec_idle_gt ),
.pipe_rx2_polarity_i (pipe_rx2_polarity ),
.pipe_tx2_compliance_i (pipe_tx2_compliance ),
.pipe_tx2_char_is_k_i (pipe_tx2_char_is_k ),
.pipe_tx2_data_i (pipe_tx2_data ),
.pipe_tx2_elec_idle_i (pipe_tx2_elec_idle ),
.pipe_tx2_powerdown_i (pipe_tx2_powerdown ),
.pipe_rx2_char_is_k_i (pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_i (pipe_rx2_data_gt ),
.pipe_rx2_valid_i (pipe_rx2_valid_gt ),
.pipe_rx2_chanisaligned_i (pipe_rx2_chanisaligned_gt),
.pipe_rx2_status_i (pipe_rx2_status_gt ),
.pipe_rx2_phy_status_i (pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle_o (pipe_rx2_elec_idle ),
.pipe_rx2_polarity_o (pipe_rx2_polarity_gt ),
.pipe_tx2_compliance_o (pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k_o (pipe_tx2_char_is_k_gt ),
.pipe_tx2_data_o (pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_o (pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_o (pipe_tx2_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o (pipe_rx3_char_is_k ),
.pipe_rx3_data_o (pipe_rx3_data ),
.pipe_rx3_valid_o (pipe_rx3_valid ),
.pipe_rx3_chanisaligned_o (pipe_rx3_chanisaligned ),
.pipe_rx3_status_o (pipe_rx3_status ),
.pipe_rx3_phy_status_o (pipe_rx3_phy_status ),
.pipe_rx3_elec_idle_i (pipe_rx3_elec_idle_gt ),
.pipe_rx3_polarity_i (pipe_rx3_polarity ),
.pipe_tx3_compliance_i (pipe_tx3_compliance ),
.pipe_tx3_char_is_k_i (pipe_tx3_char_is_k ),
.pipe_tx3_data_i (pipe_tx3_data ),
.pipe_tx3_elec_idle_i (pipe_tx3_elec_idle ),
.pipe_tx3_powerdown_i (pipe_tx3_powerdown ),
.pipe_rx3_char_is_k_i (pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_i (pipe_rx3_data_gt ),
.pipe_rx3_valid_i (pipe_rx3_valid_gt ),
.pipe_rx3_chanisaligned_i (pipe_rx3_chanisaligned_gt),
.pipe_rx3_status_i (pipe_rx3_status_gt ),
.pipe_rx3_phy_status_i (pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle_o (pipe_rx3_elec_idle ),
.pipe_rx3_polarity_o (pipe_rx3_polarity_gt ),
.pipe_tx3_compliance_o (pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k_o (pipe_tx3_char_is_k_gt ),
.pipe_tx3_data_o (pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_o (pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_o (pipe_tx3_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o (pipe_rx4_char_is_k ),
.pipe_rx4_data_o (pipe_rx4_data ),
.pipe_rx4_valid_o (pipe_rx4_valid ),
.pipe_rx4_chanisaligned_o (pipe_rx4_chanisaligned ),
.pipe_rx4_status_o (pipe_rx4_status ),
.pipe_rx4_phy_status_o (pipe_rx4_phy_status ),
.pipe_rx4_elec_idle_i (pipe_rx4_elec_idle_gt ),
.pipe_rx4_polarity_i (pipe_rx4_polarity ),
.pipe_tx4_compliance_i (pipe_tx4_compliance ),
.pipe_tx4_char_is_k_i (pipe_tx4_char_is_k ),
.pipe_tx4_data_i (pipe_tx4_data ),
.pipe_tx4_elec_idle_i (pipe_tx4_elec_idle ),
.pipe_tx4_powerdown_i (pipe_tx4_powerdown ),
.pipe_rx4_char_is_k_i (pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_i (pipe_rx4_data_gt ),
.pipe_rx4_valid_i (pipe_rx4_valid_gt ),
.pipe_rx4_chanisaligned_i (pipe_rx4_chanisaligned_gt),
.pipe_rx4_status_i (pipe_rx4_status_gt ),
.pipe_rx4_phy_status_i (pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle_o (pipe_rx4_elec_idle ),
.pipe_rx4_polarity_o (pipe_rx4_polarity_gt ),
.pipe_tx4_compliance_o (pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k_o (pipe_tx4_char_is_k_gt ),
.pipe_tx4_data_o (pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_o (pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_o (pipe_tx4_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o (pipe_rx5_char_is_k ),
.pipe_rx5_data_o (pipe_rx5_data ),
.pipe_rx5_valid_o (pipe_rx5_valid ),
.pipe_rx5_chanisaligned_o (pipe_rx5_chanisaligned ),
.pipe_rx5_status_o (pipe_rx5_status ),
.pipe_rx5_phy_status_o (pipe_rx5_phy_status ),
.pipe_rx5_elec_idle_i (pipe_rx5_elec_idle_gt ),
.pipe_rx5_polarity_i (pipe_rx5_polarity ),
.pipe_tx5_compliance_i (pipe_tx5_compliance ),
.pipe_tx5_char_is_k_i (pipe_tx5_char_is_k ),
.pipe_tx5_data_i (pipe_tx5_data ),
.pipe_tx5_elec_idle_i (pipe_tx5_elec_idle ),
.pipe_tx5_powerdown_i (pipe_tx5_powerdown ),
.pipe_rx5_char_is_k_i (pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_i (pipe_rx5_data_gt ),
.pipe_rx5_valid_i (pipe_rx5_valid_gt ),
.pipe_rx5_chanisaligned_i (pipe_rx5_chanisaligned_gt),
.pipe_rx5_status_i (pipe_rx5_status_gt ),
.pipe_rx5_phy_status_i (pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle_o (pipe_rx5_elec_idle ),
.pipe_rx5_polarity_o (pipe_rx5_polarity_gt ),
.pipe_tx5_compliance_o (pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k_o (pipe_tx5_char_is_k_gt ),
.pipe_tx5_data_o (pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_o (pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_o (pipe_tx5_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o (pipe_rx6_char_is_k ),
.pipe_rx6_data_o (pipe_rx6_data ),
.pipe_rx6_valid_o (pipe_rx6_valid ),
.pipe_rx6_chanisaligned_o (pipe_rx6_chanisaligned ),
.pipe_rx6_status_o (pipe_rx6_status ),
.pipe_rx6_phy_status_o (pipe_rx6_phy_status ),
.pipe_rx6_elec_idle_i (pipe_rx6_elec_idle_gt ),
.pipe_rx6_polarity_i (pipe_rx6_polarity ),
.pipe_tx6_compliance_i (pipe_tx6_compliance ),
.pipe_tx6_char_is_k_i (pipe_tx6_char_is_k ),
.pipe_tx6_data_i (pipe_tx6_data ),
.pipe_tx6_elec_idle_i (pipe_tx6_elec_idle ),
.pipe_tx6_powerdown_i (pipe_tx6_powerdown ),
.pipe_rx6_char_is_k_i (pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_i (pipe_rx6_data_gt ),
.pipe_rx6_valid_i (pipe_rx6_valid_gt ),
.pipe_rx6_chanisaligned_i (pipe_rx6_chanisaligned_gt),
.pipe_rx6_status_i (pipe_rx6_status_gt ),
.pipe_rx6_phy_status_i (pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle_o (pipe_rx6_elec_idle ),
.pipe_rx6_polarity_o (pipe_rx6_polarity_gt ),
.pipe_tx6_compliance_o (pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k_o (pipe_tx6_char_is_k_gt ),
.pipe_tx6_data_o (pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_o (pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_o (pipe_tx6_powerdown_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o (pipe_rx7_char_is_k ),
.pipe_rx7_data_o (pipe_rx7_data ),
.pipe_rx7_valid_o (pipe_rx7_valid ),
.pipe_rx7_chanisaligned_o (pipe_rx7_chanisaligned ),
.pipe_rx7_status_o (pipe_rx7_status ),
.pipe_rx7_phy_status_o (pipe_rx7_phy_status ),
.pipe_rx7_elec_idle_i (pipe_rx7_elec_idle_gt ),
.pipe_rx7_polarity_i (pipe_rx7_polarity ),
.pipe_tx7_compliance_i (pipe_tx7_compliance ),
.pipe_tx7_char_is_k_i (pipe_tx7_char_is_k ),
.pipe_tx7_data_i (pipe_tx7_data ),
.pipe_tx7_elec_idle_i (pipe_tx7_elec_idle ),
.pipe_tx7_powerdown_i (pipe_tx7_powerdown ),
.pipe_rx7_char_is_k_i (pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_i (pipe_rx7_data_gt ),
.pipe_rx7_valid_i (pipe_rx7_valid_gt ),
.pipe_rx7_chanisaligned_i (pipe_rx7_chanisaligned_gt),
.pipe_rx7_status_i (pipe_rx7_status_gt ),
.pipe_rx7_phy_status_i (pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle_o (pipe_rx7_elec_idle ),
.pipe_rx7_polarity_o (pipe_rx7_polarity_gt ),
.pipe_tx7_compliance_o (pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k_o (pipe_tx7_char_is_k_gt ),
.pipe_tx7_data_o (pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_o (pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_o (pipe_tx7_powerdown_gt ),
// Non PIPE signals
.pipe_clk (pipe_clk ),
.rst_n (phy_rdy_n )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A2BB2OI_PP_BLACKBOX_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2OI_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 22:59:40 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mul_16_32/mul_16_32_sim_netlist.v
// Design : mul_16_32
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mul_16_32,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module mul_16_32
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [15:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [31:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [47:0]P;
wire [15:0]A;
wire [31:0]B;
wire CLK;
wire [47:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "32" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "47" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mul_16_32_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "16" *) (* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "32" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "4" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "47" *)
(* C_OUT_LOW = "0" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* ORIG_REF_NAME = "mult_gen_v12_0_12" *)
(* downgradeipidentifiedwarnings = "yes" *)
module mul_16_32_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [15:0]A;
input [31:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [47:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [15:0]A;
wire [31:0]B;
wire CLK;
wire [47:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "32" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "47" *)
(* C_OUT_LOW = "0" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mul_16_32_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
fPF16TcpNgM9dNC6nyb4WjUK+7bY8P+I62AEEiiM/KOMhIKuPOHBoWeWL2UjxSNO68WLeYIZp8lA
I7rHN/CieA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
E6OKJxjnDRUVVFwAhrQMAtoyRVVpuMKsXlca4m9CcIt6QI8vnYN0tf7gH3uVuxZ90322B7kUeFw5
Pu0UeqAoBaSyysHuDqXazxHy7oyk4BIWChvcrp7LULlVLcL76obtSwsXi1ORVmpdTi5b+AcD+WUo
OP1PSFj5jpodG+LwXm4=
`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
x+agogSsgbiI6PGyBpMY8RQCDzLctIr3EaG23mH5kJHlNmNKNolnP54yJ8Y7nIFi6yl6tlyOLMoF
/kxU0pyFmIj8QM0/MArMxPTiemXbDLS2VKtonyK9dDH7VbjFnRWwzK0Ngkas0+nbW3TqGPAY98x3
251QPjQoZCw3A7W9PDc=
`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
KNs7hA49BKKrboRSEkqIGldOa3ndCnhjRkSn8lL1xFfKUn+p+Wbc09ogKV6YYnPU/RaF1LbzyoE4
udPSNea4bST+08IjO5GAxXqUugcig44J+hzpGKmh7oO0TuyNbYq1CnYcsZXaD9vsmNYz8fBDoW2S
VK/mYa21mBKTOuTdQ1yp3wi73aJ1G9N6Ngt7ovDUrjyd5oNxxNlvWU8JkJDinbEnci0qjZ3Wu9Wg
y44pHUXf6xqwFYJpZ1ZcGRKl83P8p74+pLzt19lw9TPlTfKI++IowVjb6wo36ztNDJS0QjQE5Riv
hwbPU/Bt3S82MVCY5NAA6bKC/8NnoWMbmX8Wiw==
`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
QaRubtGbYrmCghuFdQuTgTEtoVYYLcPnD5z0C7mo18fwCG17qy0y8mj8xWiwE6bo49IP1/JXSIw7
rTBwHFOVrmbm926sWNrF1r3IHB83C5cstprQ1om7vnkw9XX87SjkscphhkrHmi08jjzW4qX96m61
/ymclz5TlAocMQJGz/jwscvIMOrrbuH4SkWQOLQnRfx9GIOv5Y7PM+w/wuDSeFXsAXz7Ahq3/qmU
cylNfSufW7/zfN4RZB4u+d28AXsuFe03aSF1dpW+uBK1xtNZccvj9h9NMN0cuwxt8ZUlLJw8l6e2
hqRfTTZl1F4qnnrJu6w8h8uEGrmgnQG1AW0epg==
`pragma protect key_keyowner="Xilinx", key_keyname="xilinx_2016_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
XXj6Nc59BeA5Kznlx14IKravf7ohERw7h0fbO7pT7/HsiPDCWh2DlTGpFUcnbNZslPN2RfE0nJNX
WMzLQtaHK4Bm6kxY71OsXEKm7MAIjEdLwOMtJTtlZrbm7chBbSxcW6sjWvI36jk5De3Yct9Ao1py
DpQ9NICUtRTwGG8SAiRkAXRh2Jv3rKvnookQrlVxIkNRSBMSgbwuTbq1ze/KMUZebBWwJNUVIC9r
RV/i9wjYXBOeCCUk+cGDC5uSpwdLXYV9ZxhQUU6C1ufAaK2m4OIUeBqPc2ski2O0qQYQ67c35k50
ynO8H9PTEROPEOn5c37S7feU+36OcOOAsVBTBA==
`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
AKMJ+dq8Y4B5s3c8G7TEcxNvr2z7MGLeOiDu8SRfmdvOzgdjT94VW/V4WrWq8t1CPLkZsKgt8oKo
jCpl8GbL30+4J1QCxtcIGwJ12BB7g47o9M5TTSSylt9nG4fbT5G8JAbAVh+HkZ0NFUGfgOr4NLtk
/K+zJXU3XJo20pkypM86J2S8T3FuSgmIyrNtRfns+XQWJMPYYbvf2aLc8cGsYcOEmVTIE7bzVO8v
FkENIho92nJZvH9CtaXHWGPBbHz9YUbFvqJ2ArCqmhEzShHYB7UoBZXithATEUIJf2BsK64tMcIL
QT8Lpm/1Yqvliv1DI8Va9loAkmt6kmd4XvBABA==
`pragma protect key_keyowner="Synplicity", key_keyname="SYNP05_001", key_method="rsa"
`pragma protect encoding = (enctype="base64", line_length=76, bytes=256)
`pragma protect key_block
JEXlb/ZJWFKyLfNB516F+okTLNG2T3hB4/dIKClqxSWUaivORsMxHbYDvTrONJdkrONjSrlJ+gEf
dph8yZblXYPCMK6HiWb+fm+EnW/QzlkS3NJ5gGBdhgA5dMCt0ch7EEdRoRJB0YAwzEC8/92K+ok6
uIlZak8iSz4jP1PlcoXEPo5QZMDi8uY1UsSKzFMLVrvi8J+63t/+xsKI9syK1pH+X0MGlo9zqXSI
BKAkwFIS66XYrzuxxCJWZAWWXirBXaMK17MsDZ6Ja9OW+uKq5tLUbxp2CKgc/ACtZnW0GIViyfdC
M/hYiLLpYdE3YTdXv3DucVGlo0wqegBpvGW3yA==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 614432)
`pragma protect data_block
v6N9pW/3B+VglCIzORmlyt3n8tEr50jRugP3lzTPXn/zGbQNgnLj7LUGPFCTZYk1yqUuhPePPE+u
tNb4xRciOl3KPP8O4YfzvbPwOfOEptJbB2zAbVAylz1XD65saeWpRl/pK4V6ywGaw3xm7OpE1n2B
/5D0vm4XpS3lreJuag9/HWO0ijuJT8sNGRh0kwkmWtbnkS2VqXtPALJc2HoiHKIKw7U85hMUxjh5
LhaYZfV0sJ7Ebe5GqcaoM9Jd/3HGwEPWwLlZi5SH3kzxSge7lrNkiagr6VMUynravOdUQDWXAwzE
DN7nb/BgbXcvOYvU3rRz8FVlJwUZvao8/lf3AASPg0jq6OP25LJVouHu6A8hBxupzLDXozEw8KDK
B7c8VrbsvCnA+m+t0rO939XNJ1xP3VChrcBQmIDDbhi7B+cDb3bzVCcn8/WdGeCuSJo+9nnIP8jo
rO3OE8pW6YirpCSz5onpAJpZ2LMpyrqUkh9tNhUOQgDzodh6TDKouTuCcpp41/r0BJyR5KUpOljp
+pSfRehxMmEy/KpxDzMBXmAF38xGdxz1Gmq2GJqjMH8U0km3Ogivo3BdMk1N70vs0cfwPWHvZIF2
mcfDr2QiAeFjPBB/f1wV9BlTdOuqDeekHcSFtzDxNTlpvtdYn7/u3VgLgD7BD/8LMgtRfnMeq7rt
BgaTnZWczqQfCtfYzVGaXS8wEQD/FBrHIKSdXk4SQjMDTFI5ETFrAR4eRNA/f+nKMRo5zhGt6frv
Comz+yYiBOEZYqAvJ1T4YV2rdu5F/A56//YMHqJDOs29Rrj190KLhvRVK8EwxtelVRCMzY/fz4KB
DZJOYUESqchE+1bcRkE4yMJ/VJ9ltgdVTCsfmtNqy84B5cefwXc11csiEOAh50rl30XS71OIDh+i
qEjzm/w5nw0YuCwKF41FkfPSYoR/wH7220iiVLNYIHaIfFNscpys3SD6XFonJYrCW8uur8y+4WNT
60n/mvJPBquQ0/tH5/F85PcbU8/cjaGjnA2MZjy8IGt/vnbQSWOmPF1hqtQXo2y8dZpTnFdxbdbr
wb1Q/MchhquAfQXHzeJqZXwVUOrbB1uo4RMn1f/QnT5dXUcd3O1ewa9Xtird0Yh+Qlv+CTPUVzCW
e4PEHDcYCPU+3YLkayoK7vWXT7zZx7R8HaL//iqExOtgi4mWdN3CMHu3aPRS+/b/LRQdSyXEFgnm
7rV+3Dc+NmZA4SZPcdYzYZZ7+kPXqtv3GfCNy/9ZmLP2Jul6uXFiDmK4l+XLO9BAj4W+mdTkaxpe
cHW1hB4LhYOoPs9tYlWTFhXm8b8jRbrczyvX6yk4UpIcfcePLBc1JxihESKvrAnua9B9Am43zfu/
rdOZQ1mi3Tq5JJBqR3tD/Oq55z8ZF+OSbbjTFKNo80lokFPOuganYQSi5CXVu1yPch30DeHrXjX2
BVhd/zyyou8h7w3ockhb46C+jc8hssQDtWVh+kxvakmJFLN3zrP+yF3wNG39YUwvLUhKvENTn8YF
W076YiMJAMN5PpuZbjk6+EGFEBMEFZ+EPyTBodr307H4mebDVP6eknp68uSMPfSp6l0jYuillJ/u
5RNR3Je6d/1HFyTIr0OeUk9gG+EPLKFNebauWrFLy8xD3Tu/Fc0hqCRI8Xte1ApBeB3GBNWuwUOo
XadxvXaDvRoN0JxoGlxUnh9UeEdvnM0YnkY/TTH4Dc6jAKnKT8UDEFImEH/3H7RuHtKKvWd8MIOh
V9Y3skcn8gYe/0rUqca35RgVjUnQuVs5fUq1BehErGaN7yQVZ5DwF4rOuruSV522ueMXMIjjULe+
uSjPmn0x5JV0CM53PsKYeIZR1bxabKasaV6HhtjhUg53iqeSYark1QhJw+eyGNaz/To1QwMNz+7T
J5ytORVk0LHl79l/YGkWUp49cDtve+OOeiwMMHvawgsf3dWa8bvJ5Q9CdZh3Y00mH8ItIkraN1VN
VzEU+e/HSHJT7WT3hP2pY58KHeRdGS4KYZb2wOsqVuIuVHP4L/paCF0K/7RnrKnrGE8HQbW3WK3B
7GORhHEJT6bUNZi5/ZOlP41zX05m3IHS8UYL/hRjFgRB6WXjYAQQmirwdyOxhpfyjTpgUWF8Yww2
BpGX6mahnZF8MQTZTfmCSbtwz0Q4hhCaCysoXR3MpfpwbX70F7eArja3E9hSOEEL4YA2WIglxwOK
l4q/s6Z/1bGFQ2Y1apHqhnsbVSEWIwYK+5dMaIzKeOZsuR3bFlqasCYvnrYFlgcVIv7DHIw7ssQ0
12l43JzwkmNWYwk/epHYnap3N0Xv+XWFjvXiUcE7zSA7mXvSg38sJovbtRn3qLQYF4CqDy/DXJT7
I91eilh+hEaBRZwBaQaWsMEhj40hMJU2M/rNEhgsl3/xeNaTgKkZOQh7CaPGA+a6Fj2LK49gpcdK
z6QHrBWbUTNahF/fofq1arSn25iW9ZFhCeLRdp7qmmqpBQSOF0S33qHxYhByGUpdh7Dgc9Oxr2Zj
FIvQ6Ne+ZzVGY0ras8DhtT14arcQHstHtxk0OR5DZWPCspxsDduik9Cb5VPPxqnBgrRdFxgdRd7+
9MMMISpTICcDTaoKyPzITMF9gcEkBmaxGdLL5QpF6KuL3f/gBxqnCPH1Pw0KvZX7eWUpxD7N1jga
t0047QTbOeCF5HHHt+4PSrYXmC/Mk0lB8f66Hjb7F27k+55c9OmppUpyzsVyrhBxQmgnhaqduOhC
tR086WVB7J8fjiRgXjimFSEe/NSvWreddUGNRAvKUtge6/j+XnbWT1KMe5UjPBnXfeFNueGopap3
GhuWU0OHEYcUkjYGc9xQeon+61LiObUE5VnK/1XtScHrK0nz2QTIlQYOScmQsFaKroAgi/gLUZDx
ejnOqZQRu56KwLUrwufdABEUe4JiA12+jG4ZSqTrQ3NMZ9aC+Dd2Ouw7hgox6fvisCaqSZWIX8I5
jwnYVC17WCjFJACQeVG5ks3xQsrCO5KasYI9RJYueIwXqx6IkI6KmKr8VPYpxq2nUZdiZx4zzb8+
wooCg3+FywLn2ubS6ybIEC3js8WDQsJBiufMhfVNVctpsorzr9s5K5pUwESkexTMPuU+m8ck9J50
JGoAN7Tr4GUJtRxgyr0uneF5J4ntDH87Gm9gjJeEWosBwJdNHa4hWD1YLrvW6MEZKstaiPg7Z0Yn
n+MkFB+HpHgxEKShv2DuIea8VA377bQSvu+BhsbZdTNO0agWc4eFXviSZOYh4jr1CVBWzh/OCKxy
dOQP2fCPLgs23WyWxEiqvLSXwEirYC4DYgrB/PgKaiSbY+e3gjy7lFQFlygAXnceL9iPQzAFoCvR
bocOy3sIb+zwBJh6F5S1sZDYw3ThP3hkRbUKH+kSRg1XPQAphL3OPShzihdn6oHK3RvTVitBcnBP
eQZiaU2M+1F6jrfzPyZx4o2yl3ywBKNImCiakZ3uZLHPCEYEwVMF42MqGnz+svtbMb0aUyhx+1YT
PL8xUYIwQWGOC4G/fvPENH7VXm6+FyHJKILvhliS9eJbkuZQNNOQa9AAqBz98XU0Qy2K+9tArh2B
8WBQ0N0rI1869jEaHVWqR6Ixp7ie+lj1kBnmIkWZiaG5Ihof2WqayDhp7U05n9Lthrfm2MRuWs4t
x4Il8sh6d0l1UVrXbl+kMH2pl4FTqPCKgnZU+M024kOkA0zLhicGsEUrkY0KDZdRbMTTUzluI7Up
FIj5x+jvgvwM7Bj4k9uHJlHAqdL2qzIfVTYb12UjOv0aRaEiqUbDLFeJ7Fgkhfc5JMbHJsh7mR+k
tYlG1zuLslNJKRIxEKPEGTw/IjtunBLO2sNKll87CMfx4SERdyQGs7sv1KZwFnsaIOZZUMMJAOi/
5sqbzU34kfZ8d6e2omyjXEB+7AASZa9hhQHa0buGQq+fpgfVOQcOtCiwWTfIAsB/zpbqprB9C91F
t3JlrfnPMwpPn1QGcoRUAo1vD1IZi6lilj24GR79bf1J0ae8slcH4woo/8aLBvKZgBaBXjhW2gPf
hceMPYuVjB8u9FFCVzN0uE2/miOtDHCwPmWdZqQziXhfwvCTGyCtXyoM5qA+Gb0OZ39XeBATn3CQ
YZPiIOD1OWcTW/lfGheddAhcIeLF16PNehdxB10mDda/Hx3KIqjeL2sl90Ck/rr/4TuSFjQHVcdl
74dw8oQ/Fyy4dfvxr5L1RwcNoOBh7Eeir8O/TIb4+ksmKlzD7cgGAvfXGLByVg+44REZcA3+yP3h
QbwHbi4jnYJi2cxVHmE+CHJZgXrlOTXqDlULNhJUC/mKsGrvV0uadg//ypKoshFi2DRA4ufr5esu
poJKsR28Wvjy5dc+PpYYmZR3It265Uz7FWOhSLHGhPn7X6tuyVczHjiHh+8BiQLAmDCGTcFkFAQz
Bk/VzA6KBRPpshERdV5tDEdDdOLvzOxBNbapBwmnkU8hK4aWYxHq4XyJPJ6V+tzRSgQUdU9ITpEk
aPe1aQEDfX/eO8Hu277XL1OZzs9gQ4FzPek0GEMye1M/Fl7zi8Bc8LOYo9JQzGRaW9nj4BwDd/Q7
9YYfqWmAM9ZwKIjDyqVbAdwNQl5osK80kScattd+A/4edj9Yay6K/8EdluDoXKQt91HiX4uKYQhK
zvI1oFpHhl0hvBxWWGn1D4KymcAtMHa54z70I1L2220edQP8FXRQblOhCfWBbBYi8poyj+Yrj3Cm
vErGtNyYN/HtEIgIQrsKxztQjIgMJRzWPVT6XTehTTZ8l2/TreU1QCIJmk5nKvzrw2d0hWONh7lR
Efcj9rvxWQM6gaSDqE1u2XRqi6gvDKwPSS+0Hjq4aFRKPlwiGX9xRALJ+/8eYURb+HmiV/YwVZtd
n8EdBrdz2DbLjtkel+vYzs9eTvKtFGqsbEOzVP9SEQDpYDBm2HzJkPWaeOFuFvYrFeMg+mWVyIbd
VP9TryBCO12OVnY3833lwce1WezU2FOGKTV9LHIJKn3xAMuBllt6y5kyUaV8cRgdUn23Zww10rsw
De+H6iMq8Nj7YnR7NMIORNWQBjHO/ILPawBGDUU0mpXFQqUvAZq0nnW/qz8WLZupBCs8s5B57UZn
IBb3m7XCxsPQ+6w8dI5Fm6I0ti11hUEFw3iePlf3Z18YioiCK65lvmBXCLiHlzRPxRjnqIO/MQQh
JWtZWGIwHueTrWrLLNY/0LNPhZLmABaSBEbZfvDOJvAoIZ2gBH4jaCV00JADSPRKZ9brmdEXe/ky
Y2HTb7kyZYVwqaGhkNxeu/bDWW+23QOM65oyHeliEjeDgNTMwSTmb28eCA58Yrt9y8RQD7p2gmgp
t8JjlBbk1UbecTx5nHSDvNY7Lsx8JsbJMRAW+TTzVpURPoh03ZAgeYKo5leZbu+WNfT7hiF8Exm3
AmTjnIHM6pBF/AfJZC6+b3VM+43ukrsj3IvG//to5i2ZNohwyS9JDvrHPsqtWlnZLtTNBw0qkiSx
71sU1O6k80oP0QbaTB97vRRqHQhNWsCO/PVjVAil2AdgXATciN85mJeMy5r1SHKO3nzt8UXimdAU
u8FEb+fu3PZXgTcODkZCt8kjxMbZkmGMOhzXsDZcjdZ4G+j1Ne8l/c10K8xKD/izrkkwrI5HCtGe
rdFiAXNWwfGUHj+Yusi4Wv6j8oLDeHub2W149h1uVTC7mXv/wKGdXdfKS9CMmK4vwfGeAxVUt8Ow
hIBVD6+1eUEtmEMFmVDCWq/QyHJXTkHTPxxaxxTNiFbmhRpbGxlrEnVAON+6DkvzC3zS+PnOa9pj
H2F6+EpAV65aeWNxcuqxSawknfZs8u6gVV1DKs0rmwDEAJrddwchTvUrsJMu4DAXB+gD0Yrijy1L
5LwC5ad1PkiOjVj3PNezcfqWt1sYmLZndW1OoCqIIV3i/CtgM7hAa+XurHjKg89FGRCMQT1FV1zB
xyC1qchBlKDAyEncMjtWFvKhsiG4ckLAgHQE4R/QBOcWh6vE27bXKe59Q+T0ZP7F6in4L4rxUh+p
x00yE8/lQbcZXNcP7P6Ak/DiRrzeZcPWD4hfrjZS4aY+VO8S1/aXPCgecISgYNGhGLtBcS7PD7k8
XLe3bYrPwo6JexxZyWAuZHqwMuyXwozRV5zBucVbneqaBvfK2aTx/IoVTasZ9qVOQ7urQMj+ygeO
IQruQae6NtZU0Cym77es6xiY6nvdqM/t8knIEErlzm3Lsfwj9N+gZxIl4MiZkmXOMPdPEWzCs+BZ
VSdC7svrpPh0kM9TZ3A4RKYC7UPcnbR4eWzA7vsmtbyhO7kw2jy9/rdP6/cOnoiC411ryw0O82NK
bhOogJKJikrKE7VArGXiTot9q9SYY+yttkmE23TpIVs5DYY9Ud+jdueSq3gRjlwio5a/4KuWtGKV
r1QOQBM0W9ON6chy13cK7REWGks/K5f0w2B/yL6o7VSuRQkNP3yHRjCeIKnZFE2WtZnEbz3yNX2Y
fFbb8x5KBn3GIvj/vKnBwarIMEO68h3PpTf2ayVSnfqKC4YLXeDwrHCCeyeE68ghgVsRujh4LYD+
E5b17FGzmwm2UDw7frBBhw2gkuFiNBF1v++oMkFaJLBawRI2jVvfMZnvqRwFfA0+WwpwXL+Er9vz
pflA8/pyitO2yA4pBc+sDqRVkGtOqsPRLLRnrQFSlW6Yoj9W041wjgVSDLrmlIqRVvsRe53/iRzD
88NyCHO6U0LCeyO7COfD2U1l2wzU7PophhQ2GMiQ6u7w4HnDcaHwlHW4rfCT9nlfi5EdSQfsowry
+GkEQ63AGfMhLJz5FpU9BANE2epBx1WevoZqQFYRPhsHU8d+7kDe221dGQcS+gNr5/LC9ulHOU42
OxT/v6QCRFfD9nYbv5KewOcJ+sabb8k0cj6r18XwlbiqKwnM4UIFVnFva9J4RpqK8Txbripgk7I/
bNr++KE4qhUn0ACEiHEKql7wgqIlqkQK11cAzG9cM9PfHyrsM06Sa7aISA/lZYaaTvALuuP+9RzR
6qpEwcgjJXqlMMzVi8e5jBLx0jGudmi865vIv3hK3fumBxCLMCR0I9EWRsnVxU6qrPtog0+2AAND
l8+UmBq3C32mJeK5vTfW0Pr4wztg8nCegtU5shdGeollFdmGmnLBxazommt0xLjHVk9VLje6YMKs
Omsn7X+QhZK193AHx0+Ewk3pt+b5VQUjwA3tOfx3hvgqamL2RYpeFfmCkCYfwkE/W6UmFBJsU9Tk
eOg+QUBwvPp/CulMTnfBI9y5wdVh4oNrDglZeyy5mEqEk8pRH5LCG8CpJ3ro9C1sTBP5xQ3XEdAd
4tDDsUzy64wrBpUoRuRR8dcSVcvBX+LARymVZBlNIMMbd/ZMuitsRV+Dk4/6k13R3sTNczG5Cxa+
5acFpX1kXUZjFAidv54SYf56TwDIMQMhehYpvQdNj3vQeMR81J06fzQ7MhFBQs+b+qc0Vlos9dRy
m6LoNjD0S5s0bols58ssjitJ9cRmZiGk1C8b6OSTmBZBIS16C1YlRZ/qm/cZ60N03uoG+AmJzQXc
HgyLaqWVX5u93CCU1uhrJEBsAvSYn2nSF5cXxggj2Aa8FKwHnoSePf0eLoqSLavk20uigcZkjoI3
gMuN0tQY61eBjs4RAy5fv2nU5pwHh9XbS7jMKG08FSMKmoxxMm6DvIRGzbBqhmoiiW6FjanpXWS5
eZevVbgQraiOOd7fz0eO/YIe+GQlG4Pe3f3CvOh2G9i4pSJKeg3xu5zrUdob02lMkTIT2FSWou1v
Mg8h/iNgvOLtRVIPW6meNc/QIzWk6Vrxkn+RxweBvIRwM6QpUCS09Tm6EF2ea0YY7FYiJKs3QcMU
1n+NutA6CzK9Jk78XVaC/IONmMY6sN5J3zzoOsk+RJFWqx6lCbbyr7e1dNezFmz8y2asyBP7eYt1
DFzx3b2usimWctwr8gceb3PLl2VsHqB2jK9WKr248NoRhse1yenFGfG7cJDyAgdO2tV60B/Fpe+t
/5pZivGKMaw+fTMgKJJLeh84c5y1bs1L5tuQ+2fNfmq8jjbdmgWZsO6dRz/AQ12VM1/S81Bp5Tqh
PV1bt3e7fstlPi42qOg4vN5yATJjkryZrOcVJJ+vHuQ7HS42Ta6ficpniMXGbVSVggzlnqU4kWSg
Un4YcEXqgE1kN/cIXVsyrfeznRedd4ZOE35gHfa0lvdHdWELvox9Mp/Y9YO6+FcUIAX+Ezi3u0du
LIZnb5RSQWv8Y0kFQXxggvIQNYzM+IRbjmHKnQymcPXD5ebFQhUF+NTzkL9ES+znA8Fx2uyyxXcr
PsdjR5gLE4nTUV+toxrBiFnRlhuYRDWJEHytKBomUNCoQPvPH8bwmdq6wr+bI1DI4fl1wKWIpCjB
n9iY5Jfgj5VjcT7aebmflslI09zXcq6hEu3hOK78pUUfUuJb7duMHTynwWjO6Q1KEb4nvGyTf4f1
6oZVxQOYTJ8RN+IeouEQfBNqTZ1G7mxF0hokBPFZ71RfcljI9klMN9H4Z9hicuWI99UbwWRmIZSW
XeBAA1/NPnLJfhDi4q4pvKWhRnD/9lGMfLaDC2JUhGx55GYta4asbyM0O6/Mpv99KGHB71VoDZA5
KsRr03eNnFp7xBEdlA2DULXUaPd+NR/AMFhK+yxzAcwJYiwda8jrWoFWM+Fpk7PRZ9SFA11hIEk4
CcKsM2d5pWLF/0OXcm1Dou8CtEJeqJ9r4p4fwrjbLF2zQBu2Ghrv3rbGqtZzhlcdwv1VJJsmRF+z
Lheb7KiVTXvNLt1/NLnaqzkyjWdn+8ePlOHlJ1B4ixID2e17Sr4Qafy0odxTchCEhTYCq0svYW6f
jLW5NoLXlZQd4tVXLVyTm2RqpobzinWzY+3uQjgdf2sQxT4ko2bzXksE4xKcn92UWxs4f2RNEEkn
QiPcuYnFXiizu+cxicDztgygr6doIDArwn8R9QHSTMRVo7SeMikwI98RQjFKYab3xWjVRz1h7CxL
Y+6Qnhbzr7RqMwBdKhulJ73wklYEVP3/WCTqkiK+HvMdG9SFyDwIAFPAyvUsyg2lfG0KtgTzobz2
0WnamnW02f4PhzkOka96/0ac/aKDH8EH2Q2PjyGXiqGfxGxDhAvVOpSIJAduVEo5hk6qBAA2ImNU
Oj8VN9LRgOTbhv2SBvjD6tTZ2kfSgXdBk6hsMMzr7WeiObAVzVP7jsFLQpA5P6n5R7Lr7yWK8je3
XEEe+SH2Z1yltKk5XgYR1keXygpFsCZWDgmQf9XBCEjts2W1CD56YIouqCM5dMv2U+HsJWBGEwPV
rp2rtmqSrRux6blpnoUq9DIQkMq7XosON4+OSHLRUngpBSxxjy0dj1h673zBF58G8vjEQpd5AZTg
0hOK0dEOc00z/5+A5YcAytAevW56UyPfmPqqRy1/cow6lmJsTnXyDX+06rtXyFuka76azOsCONC1
cMJG6j6VldXgJnS0X3N/8dk4dUYuHROxxYXOZI2Q4lBKDqHrkxuTivC9n5+WjEQguk7flVrZcF9L
J9iW9S4H26EAq8uQ4qryQEAAr4zr1LfP9kYNv3z59RNLYevGl3finBwZ87wYlyyv8uhOv2VKvxDF
mK/u7JJW0GlB43ey1V/iNlztnpY7XEtgjKNPbZ6Cg8pKrVH8umqB5KXBvI2HH6uQNVzJkDRUApnq
//9398WPXirPbFYjR62WtJONYDhJTMfOUEFDhVU8ASL1e4oTmwwPZh8UDU9x/5ipNeOgyfRdbBa6
Fty2sdTmQyQ2XkGRDtAbXkqzFGnWDcgSEzpZEf8d16QJVR1/l/GPHvEcXi8j+Nx8MwX5TR6oB/y9
8uVVaPFKxK+1h2svKZsYQNJXl3L1YwvbQ2Zdm+6gEGK58yeFmEUDAwzlgqS6ghYKE/d5d2EgLonp
5ZpuLNwMERp26EXUj/Tgxqk6iJyiVAjKJuvgbYXpTyb0C8uz488cq6I3qA0zJBbzzWy7YuJWWP/A
zBLG+NWDbmHuOGIYhZ7cJIVC0mYdPkzNx8S4Xw6meMjVA5z9MJHJ7gSmiI1oAzm3cX28vuzqQzRV
Ld0OPyz4jaxqA+Jf5aM7OsBiF56mV93u/nU/QIwShlmWyvMzbiXbP9fj7KGHbhiXp+r89ws8vJFG
wWXPY9/nkAkA4hQi+UxSpijCTqzDccQDKXLKTtMbZqkMBy4yuvS/YuqDI+3GzHcMFN7z4MnjXWdA
W50H81/liEBSkRm9fjHEv6ei2FlfeRovAbNYzPz/mmd7gBClx1KiyjDBmeRoNHkmwV83YNmvDnam
kGZZCuCziWOrnB/W2xx1vOD5w3AkNMLzepTW+W7vHmGDexulY7KeTuN0Cev9189HT1euMIrsMMBU
LIOtRdf5JlH35qqhnDcATxmEuI+VtNcl4ujMM4oQZofRAySQKmG/UktatQcHgf/q/VSyS34KVUd2
9snmIwS+y4eyA6/BiKbyrmZ6IVR+A3PeIkq8jle3oHs5G0A5XhLP3qXyqJUEcBpk121rP+U4u5Ac
jfRdf/85BR4ckc/Bf6z7WPwO40rsmzYnKNr6pkX3U72Acgi8jOLDMEUx8FhtWkRGzdsV+6OhOj9E
ofRsUo71XE3s78sqtHb0rB0xAXDVmecljFOOVwOmE41Veki0LVBgeZGpW5vE2cG3SNP3Ok4AZJDx
Y/e9CQCwWJbcGSWCICKZBq2lq6QRgdgKc22PbEESPvvqAe5qEp30ubhEx6VUgBvh84Z/y4Z/yC1F
08GEq+eJ40Hqo1pylZkjgNP4j3t8seIAJ82dzr9cyNXZ95TH2l2NmhA+QULoXlJwO1IO8FS4KY1m
1O/QmoT/cp3gydCnBrJAOulY4bGSMi91Hf4Ju/YLNs+TFxYiq4oUX1I1kRrXwLX/6PkjENssR95z
dZjHCm4DhIA0P+l1fs7WLcwfPW90+FBtxoPJqhnoSL3gHGcOpoN1kLofym2Hhdx19HznfGqXFUtn
Dd43Am1aY56lGhf/erOqFlePpiJWrLMz4T7PgXzOnpd9zuF6HWeUSvIuFM0+gaWNVlcHD99huoE2
kC8mZpzsqK4TzjtGNhw15E2jFkJv47r7DHvzv6kDVyXnJJ4slef2IvD8cdUpqEagBWtO1wl4ASQd
PhbiguLyjIz5wES9zdIroT+c7KhVnrMNjROStiLau3k+kXc4zYnlqgC/mahAhmIkb8uIqqde8qgz
RbjNiMKkUtmZ1Xv+owgOE8Xr2ZU6TgYpqPIzF285d/vn2JYx6pLLCgf0o5SlYvfLYllQXQic5p0i
u3DKCDF0IyAV7AIx0h2rvMtzpX+vy/5RIHRec3e62P18ERRdv93xrOVlpUrG4//nB24X+xiejuc2
jxMStM0zz4eYkxZx4JfsOCaBT6muko7UJJ/sg/cVKCbhnf17EX4q+d0pKSWlFT3zlvtviE8i6qjp
zK6IxwBz3421MZsbEG0pMP58n4WqRT6tinx7CtVDOUUgffPnIz/8hUrgkDYpv0EkJmtUaqYM4v/8
wJLLVOS0cWqrdu+dfcbyNPwjwTHo8By3SKwOh9Oe0BbGTLzYZMvTczJxKSvuXLfc1J41Bd8dyd5P
hrqG6W33PQZCIgj09ZjxjQ73eEYjs2HZ94oq7WZe6OMXMs4meoam2S1XfkQrYhiqyhXNsVDxircO
aTlFkKKH8t6PKxIsCg23FI1HhPaMk1SRoaNDPDEFo05W0WwYiREMshjzzgVBXE7jrdF55S8GzZaR
Sv05zdjOLCB1GAAmhyFsJNjmhg9hNXrDGUfT8Ve7gy3wIL3w/LMHtn+Jp17/6VKR8G5NMsoRNnoc
begTKem3dCx+Vg7fbWdGdenQfVUT9iA94KxzJN6REozPyvU8KLGaiTXgAuozh70WAASp/ps6MwEW
pD7SkttvqJe5TEUp2/LTPSyivQgBdI6erBlMpwPmSVcpURiVxwue5rXQexfjkPLP2h+A21iz2fMa
YJrmGbpSlwlOcqZFlNgZOIP5wgBPxkgMuB05R1zShQh5evfR5GgS96kqXK0dHXMjdhHsr8DaYuEC
fSdBzts3pFiowe2Es5VPjVlMErm+B25zz0CGqPbTJUa9+Jvga1bxFBNWx5RBCNR23tyghLb0CosV
/h7U5vaP5HosRgZw5/t3rmBbHxjU1GEKDCbn7Fx+SzGPXHi4rIUs16bk9hjW4naZ7JFykXg42VmQ
PFuaDRzB3E2UK0GJfL1tEK6S/1b9IBJgF3FhK5+eSArwvVV2orSIsIYOf1wJn2edts+7lFrIOQ+T
ZoRujS0pzNtwfgC8o2eZEizJA9/r3f2+a1WHT1U4J6Y8tViOxOQgb2+hgAiSd1lFiwozRpJkp7yz
1GLv8qD+B+R9ZYa6CECAmMmqtIVCS6lhtaGA2a2Qcdq75jKAf2WU2mVWrbC5TJDbVTnE6lgPyJyM
g+KfNuIwBjlH12fLJDBFRD4gEeHOuqSYA4Pi3TVbFQupGk+rFCzJfiHE9bTBm5JPekOpAhL+IGac
bIc7j0TJhMFLAXcFl+YAxIHl4WdtAOb5cS8Z1hXBwRfoLRcEg5qnwFyWB4WUfcJcw0c0xj3ecypB
PiDb4ZQ6tUPzAd1z2UcoK9suJ2ZSG2TY58cmP9A0cbIYlMtem0jCrOm4Sze9/lkdj7waFHJcSP6r
OFvKRe/7FVnA/AF4mpnc+AnIfbtTfsTNOEz6ldBNmCECG9pnFAnuj0FzXozwiUVZ+3lY5NxkKNuA
9l4Qm1bFM346VeIxou89+uznPg47xRRag1pUQiZXtNnWAqwIrZ4OlCCcYwnX78EegLDwNYHJxv3a
GzUpKhovoAsU8eUO4YQxMXe5GHcsQNcPcRA436HmMsURN2EgnqkGxkng6WdjpnuxN3u0UTP/+sjY
0vdHyKzl2cXUkyPRg6T9GOxYuE4HsIRBDjJHqcyL84LcWPIIS5Ieh4EKA1H0Zc9yA6OpzFBcbNO5
KuxYE1oSOVg65YqtzkpsLFTEKmYNOyqWkCprgvHv5L1/IINcaAaoZKAsfgfMx+Lb5+upk28z/qs0
kYAMxC27EO77f+IaGhWqI4XW8PZCp9IDKU9c9jhxO6lL+St/ZJkjq0GuwbMpH5G4NvqPIUjcEors
W3MDUa930FtUEVBn1XDf+dCuCikrVAq4jwJAgQvG5LF4xHv1+cWIXm4oVayuCW+2slrw+YqdnrA/
L8aJZLczvQwGXzziTJOJGjLURvGY5ZpD4F6VDVIf/wjnzgQSiuFTbdTQ97r7xeCYgQUX7LMnljgo
PH2GSdl28779MXoC6XINX8JCsWmo0R6OFEgToLLj2i3jF4GNMAXHE+v6QoGWBV91J8aai48RvShp
quD0mu6v+35qg3zIGtR9pIIM0njO6IKQ8/avVvVb4qO/etmEKXTzLwJ3bKwXFHxP4AKIcnPQDI4H
BO+jezYMorDgxgpbv6uDIrJVGd4tdTex4/CsGvJoFyNQZ5cJlM4nZ+OwwH7RH7Gt3VBKoYUxSX1L
DN8MEXMCr6p8UCfFoldFCGpJ3/j9jhrYAc5VSJjm43cflIt5PLh9OwQndByQKj5sHakpJqfLllZp
XKl7LHX+WvaexaFEBn2XhwqiPe65Zm2RqEHIEI2eGiqey7PJupOgUjCZFuPU+xLGmNEcAUCVSwsg
NHsg+4xJpa9m3BKhC2QXjoPQHWqsTvJiw/FwyqW1IdAxXG75lcvTneneifRwGOPKfgL72fe1T/Yy
ciaZOWpPWnYolMtgw6RkzYgQ3aXo4+8wkxLbr44KvhKTaCCQHimCATm+uaskWSzpGDg3UAzjc6xo
J5fTjsZQJXavW/qlEYBE7EFGmcLzhacL6LUzEgeaGsq8K2c/T8EvKDVyz9aGPPhP+eTQPBfw8IxL
hOe0hSCRBDP3fZO3jJ0YyDQ5K82AJnYISKFquKYRsEe5Oize5yUZKs0QmJJiLatnCt0LW/Gy/8JX
SZJ9TYMKVkuI/V6OPgrVNSaBhJvG5dsux0aE/+c7R0lOPYoqaMI6rpDP+7JFzB3iwFpki0Eo2KR/
tu2cC2g5WH5VLJcDKcPBMvrxIjEhxgU3UA5JSzpmI8IT8IvhXLZmuEkBySYFAWlieU5UNy0y1+xj
VusS2iEFeUhwfAf+9m3/27kbCfXvDdkCQs1Sfh/bvagZHcHM0gEjtA+hagqly9cEiIMm8bCBMMY2
QW9G2UmQ68MMGtz25+WNc+ufnmDZrDLZsKdFUeuizidPmUzJYBOhnms8s9KSL4tJQ2Tpkz+S995J
pgK71RzEvKtA+646/mpdTU7XN4dWGyvsgHbM4m2VPEm9edWs2gURcCGYB+9UJC/QRN+7k0RhNAwU
nqlOdy/loTsC5sMKgkIpv1G+j1kuXKCXsNLd0hP2tmfip8LL3bzLzXiZLXTn6QmkMp+GwGWzrwVI
dDNoHJCEq0z27Tu0HewxemnU1LT1eBBsMtDUvrhxOUdYvkKC8k4reBpIsKFyWznGFa1xhL5FQtz8
Z2QmZICxSHg7X3SaMe11Wvbyuf7IvQ1b0U3EvUur8gKKq5L/ktAUoqmhKxp03LmyiHoLNc8ns6ME
XR73667rRHZnKnzSzXsMZOZ5LwQHky5D48cZhqEDU792os6cFq9N3LWRK3vymsgG4RlNMRPM59ai
fJJcZQTnCbxPzojARaoqjaRWwZJbxKHVn+NgycH5um7ickrBXw0/NLs/bQTQc4kmvOpcIYRewBgX
00lr741N3kP1nuMd7qdD8tK7lxLE/XC46omEpJmQbDVXvtTdTXQargdcoIk6oWuGF6HrQn6+IXw0
/e18pLoAIOwVt/oPQHm0eS5BHrdxoXqXxb2N5rB4tCKP62gnK+jGSB/uJ6ViCGazes7w2UDGG6Se
1mvT1uN1f/U455RqM6rndpXE2KQC/eGzx9v20r2jI6vvXfUaAjuDZ5rkhk5GEw/6vm6M06yUf+lW
EwE7D7BKCVss3Yl0aNldiLbVyP3TrDzBFaagN4nH8ZhyVxAUIHWopUaunMdDDhCLQ2NHWeyKA7Y0
fGLxxhuFmkQKSRq0KQQ5Xct5sM92PvtgkR9wjWld3C8i+fwSK7ogmu+jUUOib77OOnIRXN9XNdHu
GubZ8jEuOSrTivSGJh/EHZIrSk3/aXyquRMnd6ZZZH6r4Ry+o8ahkAQLmOLtthx49Obzpd7hqU01
CEllvKUk57C629a/aDvqIySAFi6G44mUJOoKXZ9+ePpGiIjok5hTyd247uZtwXZNPXyM//0bOqr5
3hsDKsKTZ42GlegMr7N/9x6o7Lnu3QaWf3LWCRK7/F2jo/Ze/GKgwsrzUiDRx8/0Kj6h3wACOl8w
4K6UtC0gS1kFCjOuZt/qfLEFY4IhtpMWsvuYHsAF9uvr8LkZ1Vq1DIqXo4Uvw2N5q6kvy4URSmsE
u5a64TNHqR57K05Z7CY2rRWgvY+b+myBCEqQ/gIz6ZyosSiA8Euqo5go5YT7w122fojtXiiXSmHv
H1i3uAseA04zPqHmj4j1fMK3626A1p6nOgLk1yOsbqQsBompMX2PDwI5w6jQfZP18pSvF87nky3y
G2OLnVVDMJnoSvuoN4Jur9VHUVm0vm8v0YW6b+pG1BwkHuWQHQ3uTndGMsu4a8VxYIQATbzwkWW1
zD/KUaw/uCKzmkxG+rpR3A62G3MO7mbTwSLLZZ/xmx/uA6yZCrWuS08dB/nhG7SMpSoudgVxHZvP
O01xgn5c66vpQRcgB2N45rk57QnvJDWcxf4qdMwKaLh6+NqbFeJvRQQ2lltbXr/T4sItLMW5pynf
j65GdYWzVq22UmJEmKXv5mKAC73T4GTFMsTSf0G0X5b5p+07SfrkkkQfs9KYGXwN5uuVRJoSKSFr
LW5Rq3g+cbwZ17idz+KEspIXCN5+A0lMTRmcSVpVUUPUV9YeKm5HUMux0Je40dp7u1xa7GqCBKb5
GnWim82eyPPejjfHdY9w35d/XQ5S5UbC6OTkAop3la2BUfaGj4a9a1WmWaxBU21m1MiadOGha1DW
lUP74zpIj+t9LmrvdMWmPxMRoKUv3/lipXIpPQQIZJvP6MeRbfE8RCjVc/W7ZTqEMu9BRhB/OZfY
clZpTatblDX2clS+1IL/VFJkyRtpY8Gl04d9PKpCcOarUg6BSHKrGoWoWiYExmqFwpxrUTyr46Ba
y/HdwxD0o6FrCUERDbB0FpP2g2EglS2oB6nGzbxK5eQxsUBiCD+yC9wmUOTNjEDz2WZFHLqGos4F
LBPiH5gkrAZ4dMXc6Vrm+XBzoJpe4371W/sfi7QN4SVH3SxecP2AGXbLwAippNhb4hu/RV2FW2ZO
KpAeJ3c4lRQw1lnm68sPQbt37xksfFDElJO/REaLfjxDhGSu5tx6A8tPTq8twY5G9GvoQwIpZMtn
nhZJjQcwbYdkQAcSRM6A9ZPGRMVUG6hMVUiD25/1Fj+0oCxN469MheEooiixZbRvDvLFsgkrf65Q
zQhZsDPA5xjwkJ7giKo4vKqZRxhx6AB6+6BdlDABkQtwbxx8+aGsp9V5GoomOmPAt1RPqrO9ZP88
mKkdcX1+CFf7v+O32BXvvoOOD1ADkBjrjPdgVH7uZuAeLO1m6N/7uxE/Pav4BPgyhg7bR0cx1oT4
8VEFjw8zdrPQILRxC0W2x6JE4utc2p58AdIO5LCuNcxzc569Q6Gn/To4crJLBFRAJmtztBp2hqC/
42MIfxne2UqTBlJrxq2lLhyRH6TC305iHoC/53urWKTZDEDDS+NaaNzxPQ5vlcM/bVdMgSK63nAq
Zavq1YPPu9sohuQ561TP/53RNCRIBvwxYU+nKZzWIcK5iBAu8+Trn1Fo3nFO5oelVrdwIp7pT2iv
idnFnmuKNutDKZB3Vyjnsbj0ipbC9ACIcM1wOkKAbOjNlazB/iCqf27RriAixEILXQFhBetsktdi
TtqoujVTv06r8D9E+eepLny8giLIomWWErRYThmusu3tZEYyxdKSFf7y2leuDCOUiwoCoiV9nC3E
PIvgMOVXBkFBd6Lxqn7FyePqc0l8X8oL6UVc6RcXLEH8nfGPzRWP9wZKuMhPkr8GZMvGFJhrOA5n
aWSemAbTVIws1LAf29yKoI0pd/orgYBdvY6jkNyPtug9djrU6BusRDwTh1KaeNoBtNEs66+RccaY
IPavhDsvNiVuTLZsjsAhnvepphtgHSwZ5NHzK6GJWUsYkuzNf1yye55OUgTpcKvpvFvfxoYFzvna
VCUZ5U+6kbcL5eJY8rHLRYRSlZSaOCz/GVorysOiUJJ2QtQ2IQ/Oae5t1u/Mqx9SdJ3L1UEFR7uE
mxwaJnDvmUYKfrE3Afm2NWzSBFyMzMXUqHIslgO38g6oHf/eLlJPDK7DheTq19JPmb2xGhmSt1K0
GQW/ts+QbY+phDzHh7kN+GeeudVM87/uUGnQGhcUIed08gTMRG2WuvILcvkDIK/flBjjWct4YxpI
AlH67vtNIV1aMCEaaqL8yivplf41jYt26pqS33yjiMW/p7qJ3Av1N21hBAOYCw/d+JyNC+YRLHNO
crkSh2WddEO6K/jyNXlX6QJW7YfT9zS0L02suUi0bmKAXpgOGr8iNalTic9mfz15QJZ09ygqf0bT
UgS56Fvs4aZoKO4EoB2Uyg9T7+xAgl4pJSo53XMeccXDrDi22+lU9kbDSFN+kaW7baZdPMZWNJD/
U03nqdPnGPZ5dUPwYLXS5g9KcaeNLMYRNSRN+0MVxNGPVlM8JMk92ndk9hItC9r+KVjoqc1rpUBe
4wcR/NmXMexXHMgd/vNwUCZn/imS3v860qdZ6tTdyhF8aFKUwhlTVeqr5TdN8ZLd48sYy7hEP/cE
9CrcXD/QpfO1f1jam42GSQwR7k8TiTaksr9cc6vaGmiPrSACkagDpJE8shsN6cxSligprH/+k81N
qNA/QYKLWYH89UFUcKpkF83VHP151jG6M3uHQMIg6SMQznqW1Pomx7cyXFqsrBGtWTbPaZiLfVf/
Ak0Y7u6hCx6wytQl/lFZr11wCzxyP6+nhHGfdIXO71nhGIbpgz3V89x1Pm3F2LeDCFLtDo2CZ2Cp
y5GPxGxJTksjyxAbd8Ghsz+SDrXRHZ+Jorg2HPyBhG+QgpiOGWWVYGLm16J11Nn8yjsknWZEyAMv
hG3YhoY9z0V+kxT8CztUgK7Hsm7v8mLFznIic9H7puJjRcG09nUjJ+39cWljoEicl/MObsb0OLjM
Ly7F1nKurtH9Hj61EI92Zf7mSJ/qvoew+vobewW7Vqq6xhSIsY1M3xssqtNYPGvoOxBLhNbI2ztw
IiGFmP/gkX2ayMfUZZP4vDcOEVJdz/IU/hamzKnwQd3pfMy43C/5fENxuMU3bqENs99lrb2UCn7l
Dy3aMGfH32ENg52b1rLCLMdYSEORo2sdHydQSpmhlVlwc3g9fdOOpInclOJBldRG9GxQh22hVTH1
UOjBXmyeXdyfQ2qStE7wXu2QOt50O7eLaGf8ZWZq9m33k5yuDIpTSV1w/MIeFVEAT7a+eHnhARWY
8qYx+iAgqOz24D4W+rtC28hKO4s9vqoRANHVWjzbl/bKP3/BhhzltHiXEAZwaGdS6CuuyoNcpDOS
aGzsLAdcbMih2TLJ7etsbiZLDQY0/0nimoesBOEKkdHozCSubDiz4M9ylrojhNyn73pYswn+K4gr
XubXfmIiIgWTqa/1qHFhNtDtdz1BcwIFE+DC2H0lIkCZr16mBFPIw92vUa66f+Ar8HgGMtin+M1u
oLYvZsIDr7qcDJWI4TX6gq+TzzZMlV7TfB+rU9fujuVH6fSUyYOFZIk/EJSXc9CclK0ZfkaiUucs
V5ClVUdf9AA7F0QYEr3WTSbrJ+/iLjp/dcS4aCSXc2YkrciUgRHdQEbocgBOLVOHVHcKidVjSWQG
Mv+fTR6o2XxqDHoY089UYo3xesRY+F3NmkKZ69B6zrBqUY3YcQearao47j9FyJzWJRI5IPHBgoDG
ovgSZKdgc6bvO/BkWF6jCVqsDvC0vcZe3FfN9HIn53vkSdai56x78Sc4P8J0/DrINCItuSDn5eUo
EGls63+V59pMACyyo7nPCp9xOD1H2mfYc5aEH79tSfWR8c7dxmzOp/wrWSeU4O5bCM4+18f50Ebd
JvTTv7koUulr06jHIR6eCEaxVp6+mOYaPqr2FSaiEq41XTwyZMeVW+R8tSCgVK7qX0jN4qm7xNXV
R8w9eK4Flf3gO6gs4SfhvvbZlLImqiVZGAhl2QEFCbimk2b8s2Nx8EITrOxSeoG6WjIBAVksf4Jo
eH3SfjbNCaS8EyIsFXbOg0PVSoZwT4Xr3h/IL3ptWS9UyajLd4lckq5/BhRMbnSY9KIbsXDfv+G7
My18Gw9Cg65HXZQOIOJrGmy/1Ec3wqcjbp1/ntt3U75sCnSkRvX78AwdQD1Szy9sl+fg8KMLRgQQ
kWppYmIo3fpxLRRK8kwtgnLx/OplCv5gKhSIDvsK+TaxU9x+hkDvgECZt2yKViFtjbjZk0pT/IHu
ERvuX7V5yLNVDZkfwcahro2oyeMF5UtuKAgHBNM569/KKJ9V85qlxi38Gs4TceP5u33X/CeZeZCH
TizKdg//gbfNsBIYXXVf1T/tO1jBvHWa61Q/stvjJ/KVi0EVeIuUjF7nVeMATBD+9HKp4CGyCltV
M2PULF0HnEfGhS1K65TVgfxk/LLd9x6ieMyUWoL9InvUWl+8S/2voTYzoeBBAzk2/kU62fFgGgVJ
jEDs1tDErIhdDuLQp73ciRy3neau+ha0uvtv6DVccQrZU0q/sRqU9XrQgA3Lj6HJJMQFya4LIxRs
5anku3uhG+tI+KiYwC45lJOQGOSrKAHscbiptV02XRYcK2fcZKArA/4lQXlVl8GB3BcErLKZMe//
3W3RsTpHlvvz+duExNg7zkvGcY2+AGsnFswMOaLySWYsI+OWsEl+MC6snXT9XonDjrUo25UrtVh9
eeDUgLl8bM0R3Acf8MypeWOSFMyKEuh0Ef5AubJkCuKpc23h4hxZ3D9UTYCeP3fm+lQUaRBhZOLO
6cnlNnQT887o/Q/4Gxl4mUtwc2/v9SeiE180PCrEtLCHjXNWYHSE3tnVLnsvVHHtaZm7QnMvoWxt
0LYsflAWwHOk9ZhOynpc5LHfxOaFImGUGatISkOs/BdWh0xat6Rv5S4qK8/tWgx/SFkj+0/heDoe
ncDqEAAiA1V5VKumzBhTGRh0tymc+UTP0npBlHG3Cl5YkSkpCent+UXQ1iTRQf7g1pTJ/C3Q64FH
knRFkFQDN2ZhvyfRRVAONfK6Z449qIsM1+oEXkOImlTcDJxubOYUYj+k40kDwUkFeTuIDZ7f1NmZ
AAP2eehY8zyjW8JQHjMRZsXllSe4lJDsANsqKe1s3QkXSVR4juZSEMARPBT0TmvWC00uBalk96P/
CsD25FVFUfKWrKyd+CXzSjy99hu88oncFW+RHZK3V+HQLf8eD6wYuqvuHtW4aI1st/yY1S+soitk
UdfgFAXRxBFX+XMMIiQkxu+7KCa0Y9ACh9NY8cMcIpIEz19/Sqhl1FAoiK8aALiCYEqHsv2VAwFz
shpx/3x/cZHQR0X7XEmKXjNym6tn5fz6YqYfQdfQ4s3kmkQHWj0thJjl3lCS87O87DrIhDt5rrWd
QDam9hfXD37QUPgRm1d55pCFtGiNB4mNKPFx/nT0K0BroMFCeVir9fc2aJtvvYQ+DCPU1IOOdKqN
Z2DiWrtJaV4FJcw4CGXcEDNcvD7viutk5GhMg5W8BBTOtuV1LRXiOdoyFwq5RAMIkrCI7q4Cmg/s
aWSP6zauVAokQcIHTC0Sex+Ap4puShE366CdNOEPQdIY1Fb+5bG3l0uyZEEPMjUb9LAuzIJY18Xy
Isj6mlzg35UIO0pGojw8YVOZWLosrBgyZQSGQ5tySE/LyXH8duDIylQOKq9F5dvlrrptS12kU6Ps
00pHxYd0RsQtuD3UbbLJg1PZBeIv4047UwkGO7zMN16CnQqm9mPJyv+ijdYGtAgR3681zM3lTkPw
C3G4PUjuYNCUrKjca4ZmZEHFTTD0spGpj58Nh53VGvfdHEhf+Y+OSeWmstX3f6weVI8gS4CEQx2U
eehUBiLXrT8/o585EqLdNMMzZwkObc8u8IiO/xh8yqAmUCpV/AoGWtkYCv6FL+dky6j6KAW9yza0
umVYcYRAvsOWxTrTJRPx+64GlyxwA1riGjr3hGHvGpZGsRiEv0rULXAlGbRSbbSL+uLroSCftEJY
KcK3qJLAX/r7YH69Rdng7kFHZF6A6w1ECR7Fosdiuz36dgiPsB7ZtWlYDh9civL2yRKkeMP73YWw
Q82m3wnq0UFt7DWkWk8Dr9iyv7UbuPZElQuoiEKkl/yiBE9tiDnCzBeNRWsYL0ibOk+GrNUiGYUf
mAUc6geT6kfgWPbU94o40SKhqeVxfGtiTif1+pGg0OGq7++1z58+PW6/HoiEyvy/JeP3goRjMhZR
j2dm/u//CGKfv5DfDMBPpW5hwTyQPDrS8lwKeyehSu1bCSfPeBlv1YD0o26IZemMSpfLcrTkzkQ3
FzGMgaZ/49C5fUAQIzzzg/mWyNuP1wGjmjGYFzzz9HVTHydwwzvOtaSqxhDCk4bvjzimeD0gO0AX
f/GJOVmoqftCrSk7wt90AVVsE1pUK0tZ5/SF8r6vKNsEOeTWke5Ntpf6/bhpNRr5y1E4QT49vDwy
OFZAUUFYrZX9nBQUAeKH70RTFSk8WxxQEI4kEPlt8R0+xKuDBH22UaQeJuPKyb7mRipCkSaT6y4z
YPxfzK1o477WDVoBAzNkV4zTMpeBxX3tm/hGRF5Xcw5Sio9Ab9H5k9rNi+x0q0cSQZkoZwF8fAWp
/g2mhS0ieReNJ3VaUBHRUKbgedLi7ay99R8ychO55O1l3gLXCu1LbEz6Hfmsqmg53DjvUdj1EVeq
0yyIgVqsPkGTpWoPtnax+W2WJffi5jr35vwMMEtuTK/DKydpkEBP8TE4O1yIKk84aRTv2dfdesi9
lQiHsRR1Jh3ctkFgTsiVAS3NJaWH5LQJQR9GtZeFxIbW5sK5QB24eU+42kfeYuWeXk9AuwYqweEI
sW/hQKkQKdJZEmqKDZf2DuV04TrpNaUzuMY6f9HRjwCmqe8eKDXsgRZgXJzdLP9pgP4AiROGLUHo
SIQajjuSKNlHSBpmNff0A8+lWJ2J5X6O6f7AjW8BtXenCznzqYtJEfQ2PTWhoila5rUJEBuA1n7+
5IxY/13dzA97WLkBK69BcnToFPl/Huyb9etP3469K7DEL6YhUPxnDlr0XnR7QuruFV3zrdaygQHJ
8OWiagYwuAhhN53fDptHvez/dhLuEjBJCqur0uAYpJNOhboVNQt11YuzcvywPZTck1nbsnTdUSiP
BRvmdPCDNqD5IKX9tFjEnLoxW6MECqUiXkGZHMZBEupRxV94zafn32tJ8lgRLK3N84gcv+kKcSeA
3IdlpdhUnhprXM4fGJkGZfXBGbZqOva1RSbMGUqxFz124gu2w1YTZUFm/spVYaGPrAufTq6xFIG+
Bst4Oz11kBTzkLzTrlEytK2eFoTc3NfBQmNZq0YiJ0u4ZQ1sQ3djeyrGaTF11jSLHnEqpM1A3KPX
ozgcxub5GKTzNNM9VgRM+t2g3zJD6cf2r4taqxskW3wjqJI5+m7YOT4CVlGNyTnQesMnljVeQIZu
hwXQ/0EEowTdjYvp8M6O/5YqyBzIimjxluFBlYmNDg4XQ/avu/jlLhGfA7q9WzsWZ04AdDaToEJL
nU2T1EElY05Pg3lNHMeqhsg3gpquFs1fTPxyjFMYnFtq4p8YigWAcYeE70v8YyK7FxbWhgrmpPo5
VyjBvj7QgzJcuce7U0+9t6UDzk0U1cGliq5xedS95mY+U2XRVGo//WMpaP03mdfbKUSXi6uqRQRC
pMWtcT8nzRd4HZdMfV+eSUrtLAiTN/QnqL4NacPj8DU1ZObX3dIHWTuPn24Ax+2x8BE2Uty6egjS
LG8PCo6MB9Lsn+PjO+PqiPbMyT+LqHdiHEdbO/IH0ZD8vEO1oh6U5HzSI4G6KFhJNQ3H6Xbcso6v
jc821Ue146zqBng/ddDDPKrBZbXFbc0hxjrX+hhdKX6SRoeKZBz4EOT4445xUd2x1UtrjoU753Ul
XvzFDsA7MFn+iyIKMO1JZ6qgNyl9TcVty54f3KqiuKxdtCysRfmI2r0OuR95AiQqi9dwGOKC2A6s
PxafHZKhFUnuaa+cIofsC2+M4WCqhF3ob2sho18ocPyvUvdXBJxAikPnBwoZYA0/BPjO2n+pGR2r
/Jj3in21Qbdih+xYj+jhiDO8riIOiGKp6ek+seN6lm5tcyE4NaNf/Y4nvReMd6Bpx0xZZqu6poot
dwObS4JDMhSWC+UacZKq98Yw/8E7LzOIVJkiT2AlJfYPpFZGKOnTyFYYOSYwwlDpeAOS7qbhY2Ba
XOLsyR6NlyOBGfOp09X/w2hwv/PyOdPZdmgKbOPt0bi/0N0nBt5jXLdBY1eR/PrAmt+HStQHNlQ7
R6m8DiLh3qv04IcNHGzIXr2+9LNx1hh4HfsOh+elvIy9jngQWZ/Z3jFTwdzDvPMmIFlWQCYR9NTv
kTAO4BJHQfKbccdXziB5AiFAOhMtU1Ba1l2Ud8eMg58i0bkB8nPPHNDd+LDaU4uzAXb+UeisP129
8z0O8Vh66KHwMoA99g4IF2AOksFBP1HGbyCF2jJbdttY6J2EN7i6cX2mIBBf6kKtgS6RWdnXf67h
pw18kHhC1LlVr4hnXWOmjSTtWaQPxLDMMsXbGI8p7njIIIOqki1HrDpo8ewXexY2AVpEX8CTUzgj
+LVZtR6exKn7DDwWcAU6CgelWDlx89mYvvaOozRbbQlVc9DTZ8jzEMmUxbxn7fozm4GhL4GYYSgb
K/RmGBQst3QXiEgS3bQrEm+acsM69bBdbL8qoqrwdKzljEb0FcSIBkKQMPNAUABb0Dg1u4pUqJte
9k5sXPchbmvnqB64dKEzMKq7Dg4jH3bCNE7wbeDjU2w8PNyas7zRZoGA9MManceo0dotHOmupZOq
CNA/mqokV9hFc7E7ZUUhhjYDGFwH8DVUnz1jYiWo4HOiwFHHjL9RxFiv633rbcKSskD+EMSTzDF+
9CIWrOvYnYMD4I4YZUIwF7GSjChW/bcXck1z8RsGXREm8i2Nzp9A9jWMQPmXtg2BZq2lL+WexwWE
27WuH+ZRCThaAB1mUHUvZhfYmaHPHkM9E3mmia6w6nJDq+mNpr66TD24Bq1WOYklpJv9tB/bVle3
xb/Q+tGunCYEL9nXvd9SCeYxRviLiD2Z1i2B94U/BdsExawpJu/g43jBEIYmvsYHT7/LmgTBKJRA
eLOJkzIknjK1xOLp9aFIJK2W1m/WXoNYhQ0DbgM4ZILXJCveuZoeATAiVbXteB9mdanydvxICdO2
hNeE2yC55agOtBGW7a8VgLdQrZLLV4oMZuMmRRVGcZRo6b3Oj3S+QMC/Cop6u/zmTfANGdXk8Otp
b+8ROj81OlwHrL4gP6BJwPeCvhd72Gfp9D9kTwIK1tm/xacu2bAzAovGJ/CSdZ5499UoPqFcBNOZ
dR2GROmAWAslbVTaPVWY/4bff9tjYBdHb6RXa2yvxRVxy4Ldl7nPjcIZLg+oh4NQ1SI5VNNTFwKP
ao0VOwyqbI8edztIPlJ4eJCMVzTt0s8K6O7Zp8EqgvBo9TkpDFLqCXKDmW920+vt5V0+w0KxA537
35UrFgE2OEYDSH0GutWkILd8m5qVyShuSdsoiafI7HnBEOVOYVQVQ6h025YPUhgtdmQu0wlsZL5c
nz5bTiMHy50Ue9x9a8V1G2NJaojCQHWYOWvO62SO5Qd1/D8Xau1eKsmgu6ligs4ilUcr1zSicGWZ
foCj2jY+maqWB5ypfIhSq+obnyEbGCTubTpThq3XY0Vllmv9yYq6fWg2rklAJhO+1m1Z2DY86dUK
Bhl2ckcMkRb/qi5gqujyZc7Cnplzx4ltCj5i6yXcU0aRqq5owlvwNpm4PFyzoWwt8rt6kGrW3+hK
t+32Xbl36arc7Mjv5iQWfCPXlTtYHh1cXLrg7LmqmDr5K1V3jh5/UitZUZlzI7lPiolGMBVBe58x
Am3w4OCgkG9s+9QX34mySQLAZdhl/UshcMcTftPJAd/PuP8uruvD2sqo9Y/x9xPj4GjB2tLEfvju
GNt9NjoCfUoVx019VV/2vxrzgOl5JbEzvZkmcGxjP7GV3FRHMYjtPn6japaYozXu7Zc4fZSE4BqB
ii1Ws1/Iv1ida6Ybf/db0tUlPtYWHOw83Y/cKm2Ajqvh/PsJoAGD9lLUK+3msRU6vWp8I0B5M+Lc
MDy7kuxc9svi/5GbjYkMMIcyYyQnVB1bh4GGaBWkuvctlsU30RMikXjlhT6I4kyRmNgDI2x+Vq9y
HyJ5QB3MQgaTf5T9VQC9XN24JLyqenSGyFJhILX03hjA8kw8qsLmjmA01kTJo+wBGJCMsvvyVVbr
lOu3efe81X8JHEtXqshf20QhZmAqACLW5nuT473+te7EIMv+UyWGVKutWX4e0/dcA7C2dahQcWyA
4UpjnVh7wCFwJt3k/cysp2SoKhpPFKGXmYRIFm2Fj/n1VcXbJqNoYFpGRykh5+L9SJObLsFmgg4O
2gQOLQRKDol/KIEEmDzabvMdwZXf7YJhLNWBwVvn9qi4gAFrrfKUij9ApUWqyCMJqjT3Wt15pYj7
A9n9jWi/7BQPLSkwUeBY/apWU/CYHP7ftQj7Csv8x2e44FhpWmsN7Ixm9r1GVYYnFT1hM3yZVqNa
/d9P/yuV21X8LRjJinH0nCrlaD1xiC4X6NNkBcYoPKD5Zv289WRT2AlAeI5IuTUUvstdbAMqZ7Fs
PibhWVGrg5SIV+D4nz0KovzlVfsER9N7HVFzQ8s2qGjjatAwgZddCT3j8V7xqwVKwpK7Dovkh6o4
QAL9GzSgTAiIsKWzUHvZtOHzvXqQHwghVekOVoHf3r0l9BcMy3lcCk6LZPraY9CZTCVwgodT7ZS+
X37gkivolO5UmeWkyZnKZKmU3uTH5PD5hUf/8/72mDRECVSQdd5u00WfM8V/CRv+pwf8D4jn61EJ
PQaFri3T755iXcsnvv/TBQ37BWexfr5DX4VR3NkjXim78yD0gjx79FlVsuYU5ukmlr6D9fEZec37
7xVuDSQieDSj0c6ZdgPkT03rCOMrwRaoN8neqRSKHcwoWyqkdZcAEvpZQOFtng6QOp7yXPzXKE87
ohVIxnD/soGwCvRRDyqJJVr6dwaVj76nfkkV/BeDlLWiUWVXQa8bOORGVMTSR7KgQlvBC6w9uSL6
XhrJ1OayFziTqyTQJEp9H1APWzHLcmp4rY4Nvr4N/mRzdJxykpk9GskusnYCMN2FxXdg9AL/6ZsY
USfMpVlX5q4VVyz1lJmD7QIv2FXt0W66c3qKbmvqkUpRmzRo11000OWeCc6hqQvRSDU5h4vHk8OC
v/KVt4GAhErLuBGcdK2R39Lnl+lrQ2OyPj0XW9NxATYdaDC/L11iItv+6MHIIXXgJIxkfqWAwkfb
xkqfHkVTSkstvUp61iuMXGA9wpRv9ax6fSkv6xxjkDjFdeAOBsBM42f9cav2knsAR5zfJiDmMjCx
3JI5ZkyOohHlBw8liJX/LjKZyKEU41LISN0TviXZ6/3RJTxBoOKDbs9WG0yqSy6xZTHB8X4MnAiy
/05K2PWhtfY7BJCr2oFxIq4sj3ITJrqPLfOVwRij9lK0fLBhvC0AZvzWPcoXvy/tvKFZqDU/acor
OsO/NhVi87wMHLPukgklYD9/PPB92nOfhuC7ZpglyCzrHI6kvVj50xAte0xG3XKbbqL6S7SuB7/d
4YQhVGTcG0rtDzvf+AKq7Kc14T1Hw/ZgcC+vNe1lEJ8JqdYAtKqEwQ+tO6URl0+soytn6w07bNFj
VikrsSMp7OGHGI0piH6+ZISRS03jM2MmZa9sqNSIeU46/lolW/nZg8iWoC0EL6agarPqzlGEw6+x
B/olnxGqchPxHzQKvkoS6geA30npnABkmoyKG/REGHOYvn71kIrlEMKiYv5GXrg4B080DyXlDS8i
bzQ+58Ct9XRuJR3itO9vRT9IvDKOO02EdyENjKeeSBx6YF/USq1eTXZ3wPbG5Z30fzd4juOvfLAH
cLX6oEHXSUecSju5qmWr4K9xxH+/wu1vR4vRLaZz1VQwP/Fj5is8oDgqi5+kDp7qu5WMWNaMiOW2
dVSKWPUpDxDgAyxzGOIM8Q5vkZ4gatWqozbcWWyyt9AUUbh7qrUQ++bsQZhts6MQ0IU2yXcZOlDW
iAe1vw4Mm9KMc2cQa7mKxlJQ9egi9ykKdCsX0kqU+K+uaUvRpiaQbXhmoOtQWYdJEcr9qrDlyAOu
X1o26yLT7uxeeucEGPT5O8HJRDMEMmLpqEKVYDoiOV1bXwQEdNQpOavpYI/EVIbTWpwQlUvkU6RZ
crBDOvf85XXjAHYmSTAlZ8k0U6oHfeUfOlGFrkcNAGyo4YeCncQC0jXVJiqZH6PfOmdSetjeyW+R
87NEfWshDRoBUUTJo1QvbpceTuOScvjQa6qlRMA+GBsJcvJE8j8CSzPk6uAcmkDzWdcdmNc+bG4h
bjEXxmkcGwDBUYIELa36sSpPaCYk/PQ8X8+MGrQv3WxYGolDcqqbzsfwtejrxF8PXezt2kWIX+/Y
8RW9LX9z7ho3+Nnlqo+xsbZmH1Hw94oD/PvxNNxeGB6ACHVVshvD/Y+gWbLZI8U4QOgEpXaToDKZ
ueLQ82eq8L2OG5yW6kbTDomUfZO9n2NIPhDaGs8ClqfWzC+5wuyaPmBZxR4JkF9IP4kZqtkFEJJR
nyN/o3J8JmYgiEJZ+JhOCdeZhOsTW5B/QU3EeQWFDOU5s1FMa44L08arDZ3B2FKcXC+DPym4iqjX
XvElKRAL9TUWC30GkSou78mH52xB8tWOcuIXXb+NvQjB8tJBcdcDhq2Er/B6aUrwoiCi8MejpAqh
mzz0vdrw1+UdRS/Zi733eGVRImItHZjVFDzfwiEc4ZvTxTfo/rI/+NK0KUHgEyFb1knyqGeKj84m
LU19mRE1pCS83ujdGQvx0q6HBiEymHBOQdYu/ONgB/V8jScrvV0nmcZ94y28S0xg+E+uHpaYPKzu
AXsAwEYhIEc1ha+WrtiUPcuGsiTftEUjW1x6qQFqzTa8G06wRwiZuJgfJf96wnjS4PpOeaTEcIF/
MiDqwccB7NQ+RyOzx5NL8vkgcABbW2Q5VBbPDODAhbkbmQ9l4Qd2EddnksG3u/tFoSUdg+wEuJM3
dvHNRepOQutTzo83OKs3XXSE6RFF/6yUmjoUKdP7sAGAEpeqAnl9cXKqoZGaYgCK30LwFlauMR+5
kYAfWwwRv6U2XhIB7GmsTmOHjCb8+oSofZ4T8+LkkwGyqcdbrc4sbN2pg23TjVGpMSk/VkUhwh9D
ZCIX5gSb2RJleTGxho+aLbh94rEGsXvseJQQjmn/3U/KXkdW7xSr2XHcj1UfYIp7a8u2vZdGXcxl
gnBFE9OfmYn0LjUnkzsxslhQv+ormamEBHOqPUjL6bav26Mg237up9fU4P01I51nirR8v4KY2Q90
tfs/7ycsrb3WS9dc5N69rjc7t2CB//Bi3CnbWpkAJ7S39pSymz0Nmv35IIrVHUa25a5BiX5yKbqv
XQzuvs8AcfJkDFWqKXIfq2GuBCM5ThNSZ9bbG0GX/Y4JzwMB5wHzuKS9f/X1ZmNdHsBqSsgNLO3s
ELXmIvu1yc7iTuOS8uZD1HRq2ELOasCmg25ew6//TJ7CrBCxtJAli6WIFBjnNFzbuHd+IVPGeAjC
Jnz8h9iVvbGh8mLfGw4n3Zf0Bqeot8meePvqtaQ6JeNWcVtm4wtaajU2u78trCPWSaa9zP9TJFDh
NFNYpczGSjow69wgvmhxhnAohQFyAyByL0OYNrNXwE6Fj8E7wuTUNutcuTtQ4luZasCsRNzF3n/X
/qkEDVlVGaRlNV/Nx6YINZ27jPEp5dgaGnDydbn1Da4at1vs5dZatCQYD91TQ3puUhh6EZaBbnSt
c+RkVse6MTwzyC4UAQUEUtUBJ3TpOqJIuPaRHF98i2iwEac6FpAtf8qgZo5/d16pkMlCdkbKB/zt
PcId3iWXOH5HvNanURfX1rKIhgWsfMUp9CexTD0XzNd/EkdaHh7jDaNpSqm/k/zsFjMeJLIk6D8q
cM9fZGotghmWhQ5ReaRMxdWkWEkdDjFLTKu3jX1oj7/rTogWH+oM2b1RI9dfQLg/7oxLSNqTi9QL
rAC+9Phaa+STcYHqFu6RYg8L7LenZM0/zjSXEFD/7TtnBiQZhCLB+wb15dUyqRER51vPbmXUkZxZ
FAuyLt5fwWJr6RV36KtEJ1ntU3Bq5k+guD+owJ9qvdSDNz1S9XhY/tFnWuDjuRcvodoyWHL0gT1R
P5QslGdp8G8MsVuVx2cjDZuGCXi6t+iMpsIPyvkp8xxhBneHgBHS6nOA039nbcbHrOfEYHdRPyBs
P5maitWhYu9ga+WOUfZ/LjXNjqlED7DQWVw6F2r76ubL4GTm6UwKFgCM35hmlEZ46f/kc+DMmrE/
4gZu5vNAkJgf0huUJXTgJTNvM32KHIk9AFKudYcQr1K2PcRoz63ua40OJ0Z5XbKgNpOOh8NFKMb6
fc5x5zk7en7pdUOKdzRMrG8UJoIYyjjVnvvKbbJKJWGiToFlJRmqHr9bRnkw0Qx25agSnSiqm7kP
605N39hRxeE21dDZemkEADHrdiS0nxY53ACxsSMx2dAKI/RR00YqKtgriJv7yOb94Ldzs/fh/fVe
NqCDB6a3+VwlKjWiLayrUx9yCAwaeMsLUNJJVKK2GtOMDgG6F8pOL/1VWgqYbn8L9KSbSp+ONJKe
Rp2l+NoryQ2Qe9plmHMzUltJStSXSp9Sto31zZHwSkQsLEcXI/GMYmebiiBMaN92T1bkd1waQ7fE
0QofX4xLZj3IjxYSfpz0Ak7M2Xvz5/bRNKx4nITkFZPvt4vQf+zFFC6FOXU3NjQcNRflvzFNsXuw
i8Pc1/nZkzJMk2F/4bP5YQARGWV0W5viduLP3tbCQVnmK80+cXgN2u1BT6Yz4aeR9OCBsFPPYzw0
xBGHAzLLQLXkR4fUb+pv2tS1UoDaKR/B4PbTkQ3144dhoQBEThTDATIwHUTvmp/dFZol6Oirc6mg
xOZCb2KlIw2d03ZCNgw1VxqFz9cP3W0wjrfiKXTLFE9pmg9Sb4W7CZk+ITqzwj7q/lb8+Yjjs5hJ
9XJi3ImVtBCp99MG5slCpzydnC0uxhj+rxwJ86h45C/kZWa4d3/lqH8qsUR6EiJzym8c4Br9WEeV
2GpUp3FSo8asne9Fa8ftHkWAbvRDyzmWd5A4r0k3gLNT6aJnBEj31Aa71YV9Q1JnUSrsTHEptkPC
lf46E4g6ijjgGSV50FYkjTmCAwgmod5eS7w/Zqv7u8OFhN0Xp1CnQeGW5qze+m/rtn31ky3vcLzS
nZgqgb3NL61nBKLIgbdM6e17sqCLFMownQ4hy5mTaI22ay36rhN5qIMKvDb3kyr9ACv6BRxppZQ0
5XqcXTMWabZAz4REUqag5IVrtibp3mjFgEJhqqLkPqLTWiFHFnRD5hSZS/6EMIbDaz6ZMssFUuHk
Sw1yLTUOhbCugbf22g28vUpBWlfYkExQ/KguDMvjQ2hZR8uiEcnOf3WPd46uw5hxWIRODUsdk3+E
QdPr4w190TLky89oN7vaMrExElmg9TK//l53NyHsZHT4fVIxVofvFYo910ezJB9ELq2oaQnZfsE0
pMkxW/evVg7uIXLRVSAqQkC/zJUo5rFpY55lcFNqyBV5OHh3v6xgCDw6E67P9VzvFMAdhTOZ2Unt
6pqMg7AcC8wHTtoRV4p9460pa/gMYlVe9CyUo9GgY2t7kb84ZrhL+zFTA0W2jKcI5/sFxmXSfXyp
9npnFOP54XuJrZ6Kma4YjoiEnuGLlHizSmtnz6aYzKMEUkVxoUbJHZii0KB9ymlI14abZbyqvJM+
i5Un26hxxPoQDH9LxHXIFgIBirBFUlMAHjyYvZtvkVfM3YtVhJVfnd1YoGqzigebdVEttcFh1xdq
7FjdoW/ISzBg8xnWh/o8FTpD0ZLJLgtzwLhS2OmQhlzUXyXdN7shlPfoiSsltNi0EkJ4DydpQDwr
yEskn03xNGnPbEEW5WMUXCTViiRDpLCsIM2eJiirxGJTv6fX/jfe1Vy29P0knRo68i7XSQEaqhd8
DkTm+3Vx/RYTpvcZmHcRG4owRAYb7vnUzVferMb6ZjuF50LNdP+L0u39xL46QeyndNw0w9dZHpxL
2s7iKZwvIAcBDk30O+ahfjELEd7hDxcMuRzA0JD7n3K3Yf/nZirRtibLbf9ubm7N/7OdPnBD7+pn
F/uDd5HI9k0RbuEpe7bm0NvsJraOEHIrzEcvaCKKFSGrdbZ+/PrPOR+BdqTcS5prLxUfW0AZ+L3E
FSP/eYPl7BLuev7ILpDNgKacWXshzEp0PEAiijhdyAOs+RQMjwGyIP8m7uDA1/v1/IeGwxNowidL
wXAlYd4UHWFpYyrgiPQLObprGJESU1aU1IVsDTH6U1Xmsrebywt+SlgZtcwH4mu0j09x5CGy7e7D
E73nCRFXGUGPiKJhRsiTDRCKAT4ySjVrtQYAIFHLnlmwc0v7e6ND9QFzaij2My9JUvHXuVbbKR8p
wSnHc6c1eb8YLBpfX9ppAhsAi8+JxYNgyh3jNs0noFT1cB3QMLr/BGFM1Cyk4kjGUCn/xv0X5uEL
pS7H55MTVuWrZ82y0c2EdjaqSzW+7IIptmbergC43pjZBhW6a0wKXwqttWiiXv8Glrs492boJd3X
T29JZXbn6bqqPbcLZiGSc+1w9vHEy37MEmnFe4Co1sBs8pODTiUzFtcRTflwtnhvQTTcvaag0VRb
VfTfhAUKMf1zBd8Zg1/HQsHV/mWfgRAwB1cwMCDJWOQo9NSaZDxATeGPVhjkyXme4UCWSK263rdI
EB7rdI8mZgM9RBq+hjJ+TINyKj5p9xvJCbgr0PDAIzH2hHmDqAfdbvJA6KiPgPjvxBiOqQXqaUX/
3Xcv7DiXtEo1KeCd9vsw/foRz6IQ1SegJVWJslC2inSp/D44VX97GxjiD01UN1dAGzYAnfJrKawg
hlsUIl5BvJP5CfGD9H1mLU/mW17epetlWj3vey2+9fRsDLdop7XLYeD9GirsyPv8Rp/CBQDV7dEt
ysk+/BrISYPuWruIljGVBh57+Ss9l/aG5cILmz1CC5a1qruBR8HyYXmhNzdszodnaNToPUV0xRsA
sB73Ps8MgOFjkW0XE9HIJovaDBJDRlLrcnkM3YaF8OChbEenpKpcw4OTvlzvHTCAjWlo3Quf26jv
6EBElJZg3AvA2h0n+cGxVhEFSUTT6qaNAsDrcClnFVPNe5zN3sRLFNOGzlV/vMG+t4eKUebN35Gu
0qnzKByUVT/kufeZ9ksem6BBZi0AkCouaa5VB2z8uqYUpFjvwBYJADfb6OwUX24P2O/XIF6yrFCA
BpSK3/L5A16JuxErRDkroIrtBJ2jZNGIDTqUnJ1qEMV8JPvdZxPie0jvffeBK4ASQmJJ5l0NEnHF
E0qEwmLlHQ5tXTV7wGib4e7bdknKQIIUe4VUiX3IcyW0E8qnSeQnIZ5X5SCNBeStD6wyKRUb/uWq
lLwNfpF3x31KIiUzPs4j5knyHIB1y7CrtRP2slakQbhzYyWUc/egmTdCyaxl+UQFfUphdxkxiClV
7OqfEX5Cxxmrn8ADY7CAUx3sgXVUiRgVDitjsXxZuuO1rGjJEeMpprSmjPY4aX03k2VEJJ3chi5h
3FZFgaIk6Dy+AqLrIR2WoVx8y9mwMZ44wrksd1ul2YD4G9SlApo7i64BnidSi19x6T5xtS7MkTMz
RW2wJDdt5g+TK52gp/zQOAFtPXMTDUtTYyUW0B5swoLnD4AouRz92ic6U66XeyKYllq7qWeGLKKV
1Td4F3e348mFCz3Qd/pBMWsB4hmN95WaOEvTR9KxDQUaczSRIhgtpWtcdtCY4G0ndfIp0jMQtqHZ
AJQbt4EvaiwlG/FxKey8+P7j/K9pTvVZpZmmcTNPkNjd52QGPy4OUEcwWSj1FUjAwQu+sokErerY
MAihUCE7UQFxJCrBHpBwZ8lZjKR+LORjVxebqYwUp34f1DADgfZT5tBSdhlnQgcSSzEnfW8TqHzj
JILtP9J01v7vO91rbwXo9/KhEvcnVl7fTNCgnqiQd79px/HHbeS0m4cSUBiSmxMaASJnKcv/Olk5
AgdioTS1gymXRnWFiWnXurrK8aFnUfCTUAkwgITyIeg5QOTMs+AEIrIdUcqjVRmKzPgyCOKnTGDW
jHGKFUXlffEgP86AZ9FMAFGsM8DkV2UYL7p069TjUhnGlpLCZytVLuU2q/hMb6T9yNewy/WRtdl1
PIK/guUdhi7TPeWjn3Bg9T6du0AOE7yX8RUwthq8H34ddEFwqor32IPb3xY5l519aRwR25wciREF
jNF65WuBgTEho+DbSQrgLeJPU1NSSOddL62IzB8A6bzSi9gN0eWFVDVxu3RU/yaEj/yvJNwUTrBH
MhZVDmIwPkt3avoXptobYkOF1ml1lgRewsG/QRsq1H6se8ekYZsvIL7i54tnm8O7MonEUl4msWiu
ZHB9f9MHyzSodiasFYPNd8jWR/EYb98AasShBe+04jbbKAd5lyPC2mbX242ABdKnrxBWuoFCtqMm
dsA1yg7BjMsK11kDgvGXP5fYbX6pPpoBL8FycioW2kKOBpbV63oJ6v0U2tuPigKgEH81VGKqFLmd
eSKe0+7XXo/MWGBH90U+q1uVScVaHX9jWZ7VDpMmQOE2lj8Q19PwX47CZZifFTCl5+aSnw1DY1Pk
80STjJ8eWqxlMDb5FV8v+/rUTJwLC8Y+OgGs/Lhy1o6103DpG5nvqarhmhBW/3hDwwqzd084I/Wk
dCbMxdKJ05vBvW5bJ74jack2Zmjb0iAOGPB4PReMkuHeGlb50Iy788k6V+BKIQNOK4my6PSpefWO
DvbXfrRuXdCZZvXIGeHC0tarEEUUbbnC97+nGrVBESK6kKYO1gMG7hDh9u0zKUwUajjz371k2qrT
RdDiu2gc9iFR4DcBXgpw2YpJNY0/QzUQhS98AjXYNK9uIkr5myKTiRm20ni69+BO6u2U/XKJfBjO
M5KiOMmhIActOaIu1e+D9zbVewTBeGXK6H4b4Wd1qUBNKkINMbxPVoDQ0WDJbR1ZgmG3KZCh9Atp
iKJSvNsBOpvZp0PC3930vtGRuubefwMIYhwmuE9b+9M0N8+DzTbD06QISLRnF/c3AEUAleE488km
oaiYQ3jnMnPsT++TNyiW6Lwsdq6WF5bowNNvJ1INrvWEjpnXbc289gn2NKLqaRKuhJy3D4w5z/xq
NKMvjsnrgzn+HNTRC2214unLEvIFHcsSFgA2zuxeLW4UkTYqyGDH/WQFcw/ZmZ78B0Ys31rtRsjN
nUjDjN+dE1EaKmnA0GI/tj7fw3USPzPjsA5y9gQXZowcL0x8Qlqg9fg+tY40KLKi++WXI9+hpspQ
2aPLJLIUOuk0sA/D2dS16d7cVsCl7SMClsc4NyRfv7DY+dN1sQeoEoNP+yOcE+fdxosPucw0MVVN
rTZHEo2HYDaQ9ol+O6Eya0vCd3aHCCg0ss0BDU13eR9Fikmytsr9hbbEFsRSGzimv+uMongEVIZZ
1p+10Qg3HuPkQtCjnOEVxnjvxED49Y5Otq8FmZo2jkMAVNGS3vDNm7kv4k5TMFT0yVXrEjbWUb8X
9c/BHogzNXJ6hkG0RQyOLUC4gaK7AyW1KDWEX8uWdfIsa6DLPVp2Kv5Jo1JtZAtoBF4frXK4Sqme
S1in08KmknBZdxq20bHvGoNoAzjRPTJV2D+YoL2OuIgyyS1wx7AznPVSJqyTitbQq8icmdb9Trye
EtuVOoWB3p8WpTEzV7D3Q+/sYqNoazFHKRYmQA/mtlfYi5B1Rr/AatWcp3fiMBoHJCyqX/1svCXv
XRar1AGL9tNJZnGdoojk3ixFxIIj9qnLVLpKKZhGdF743FpGb9oc4/oVlYx+uk2llgOZswyrLChT
2iOCfYPEd77I8JeVvrduXemGmxs2jJiZRFjSPUXSycBOL47d1ZpwCEZb/5hjiu814ZCd+sfj3ILq
gM07DWsr4XJlswNiBdPV6hrp7K5NnFk8qm0tHbSvA3UQhNSMzDYXpnhdoNVTn8yRDpgUKSpvazs1
65kr6W+8pYwxCG2Nc8a7SZwxlc7YB4wcPQ4OOwWIpCBsvceQjUt4iK/CXi5MeC4EFtabmgFD4sMP
CWsg+f/6Ml5olefyFOn3Du3ZKYlYM8s34SH0k5gHxC9JCnQdGZTQ6RPkBo16xlUN/bMaDh7qLnOO
dQZeHi4vMGEBKbldNEgK8ndV4U/yQXaxPOCPOEhhjwMWiDG70ZTSjwdsDJYkf+CyE1+IZTuziH1C
PbkTylYDqor8euLLt5VolAj+FpEVVQINAbwJAD5dVhcMpQlIHr8kYUf0H3jszc6L+rXSlzTQAr51
NP0P2qWP9bGHHy+H3RzkI1+bqw/gzK/l6RQfdawOhz5yzasqUZpJTd84IhuMWQOEn8ldGxrdqCd2
3K9yIczoB515HCaX9RdfzP8c0bbrNIpwtdJ3UI5sVCGFAhpPxo5fVHRNVf6JFrHkBs34gibZM79w
XrsRvLq3Et3IOOPwhZmohmgahspH3fDV/qAE3RPkCO2aQNf2aDpo4p+8kaZsZarPvN2vyDxe9pmb
9XFPS9hmzCirwTJnrerhBLgyj9MhweHnCIG2AjDY5wq+0z5BoF5tlIcQGIPtLJLzYq+F8ymKtEHf
1k4BuVQwyoTO7ed3G1C6oUTkv6Nvnt1iVLNhGhL3+xbNK6LyxjLgBvke+CrUdQ+7UKWPr3gxAgNr
gwemCielYM3YwSqybSxDJT2NKWvKkiUfwOSEVJiC/gWVwdxEF/UHhc8VD8SkoQUpzV93+zPSS3HL
9a89FTBho2FDaPnTequeMPpnnMMjG4kk85EKKcq4aRCBtDc/Jn6+tVCFr01Ma+xHt+vnzZuYVEvW
LLRSETXIcAkQlyu9MZvGRRRuBftLENuRYzl8kpKNeorY0qjW2geGgI+N7WXX3BNPW/4UNhhKbcIy
MepK/j3389RyX50x7iLN2NRr4tVyplCYi9FCPJ5daBvVIxTx4k/8/PA6v60e8leiUB2ZQV4M6X2h
uZAQOtv4L0tq9vEWgjaqTJfeEThc04dwTwMR29WjePYJewZ2JxlZHILXteOlXFKJEgcX+Ewf8WVj
o/FzaJ4zmXBjdUpDVzzVdae4MzjVTR4VuT0fASsE/0UNXy+raC8JnCINH6fqujtYTFeF7+xEzD1/
pNmJZ36b4M1mAfNJMwG/67UCXPzTvN7ZepTfTncMFapj3sSFUElrM/QsW+104Dm0MRmf+18N9jIC
3pIn9C2ehxI6yUo0cZa322vxB4mWPU0e2QOELeAUTB844e9FRytvKQUQQcsqhhlLl6dDD2SxReIO
eLVm/0ZOzBpIAvbDDssR/694nDIaYn+40m7ecRo1Muo5r97g58YWN/k6FJzXKYguKhkducjZr9Em
C+epAwuL8YeNHG1gyS+PZoH05xmiNmy/pYde6M3PIqP0Z0Pk6R4qaM9hp30El+5lldAqC3NNfLhB
TfG1fuYzo7+SA4OiZusxXSSpPmMraJmDQnxqRTy75MQxZkBKD4+UwgSi9wqmWQq1Fg4g6XHPcB+v
WE5OwF2AGb4eylcXZFNSpwYPgWMQ2DVxnhPNKwBab3YziUEEFPb+NufAO5SZMy9E3KBgGwm7OuMq
xOsBto3VKjaV3mE7zGsP1tEpb0VrBFq98xtrhIkHS9RZLyBo7yAkVeRMheXQcHAXrjfVBXXtMGNw
K1jMrncRcIx6bAP3rt1dZscgPSS/AE7N3Q6fuYhOPEMtsJGnYi4G50BzteNJuWMMLL8LxfTKSvyb
dnqvnKXvTadCvGRw0iwBcs2f0UIwUCsv78uEjyVnmnPXu13ijXjFQbpgAvjWxLLzreURUEJhzf3X
SJ1J6hyOPJzpoXUHCOkuMR5jxiCYERNmabrWJ730Iia/oTF6sJHpho/yt2F7DskqKPmZBEqEEE35
ERtDLFQ6tAMfYekFy9Tcos/HVMTG5CXXplvyCJZL2rxqC1ygMTQ0OrtL7LWj/ena00Yc38t9Q6n7
i6z4RwGZ34ryptsUdKVBFpk21/3TrOBGC85rakcG+bj6VvfHRiEj+9Yk2OyrZG/h5TUzNENu2nuc
vlcafmwzHnrX16Eo6gS5m7ZNQ+JRb0o+5jj8vwlsnFJgPQ1SmpUybgSlRjY1VNz6h1XBSR/ZKE1g
6xqYdooTLm42ykNE+JSOaYmlGx90hriR1ihla1QS5wGDfohO65cm0UWSpCtfaMP+qY/oWBnymebA
RNJrs+Uj2YIZEPXzbYQMSasNLaEEP3f5y763Lekm5WeiXKUPx9tARMKUhzyvtQ4p9HGgdVAV5H3W
LEkzbMi0t/KbbIuPwzPQQOLmzdicXQf19LJCgmwMRmwHe8g5neYWnUDKlXF12sYuGJ7G4Y/Jz3xM
ld3jKNXZG0gpaePeGWknon/MbD+Wskiz6Qt/KaQ3C8r4TKrMz+ynjLiznfrJtBfaZW+aL5rsJ7Xr
p5q4zyv9jXK7PxoeaFzuTrE8oCzfGU//920icyXRizFyOnnvTT/H0EogJDbNjd1GEGgBfB5bJx5a
5R4zXsYyqKtmlczxGM4ayF6wO6HIdvrMJFKmr9UqEYOpEsM9t+4ihqyroH63T3zc3IPnL9g506f1
NSMaNP+BhgjkB2cGvsmFEkS/kZdElVMzP4itLmPuSopaWUI8E7ZHE2fPzpJRok/4T7pXpWeNUXmR
20adtGvkjuYv2NekwRifBn78rjl8JAlcqQ6g93hr8I3immg4oSgomXGpFlDZuXMe/eDGfkrmi4ns
gzle2YNwyOqpnqdlMaSE01tiKKxySDDabW4VszOWZe7+8Grim2aQuzg0PiKzCDmuYKOf5iYQJynh
C0HxiYteFEpBAxQhYztl6MKaz3hDZVaaLRyWBx6aAkAiwTlx7jX2zxkVi04Wx7/vICxm15pl8/P1
eG81OsJfwuTWvPHqs4F0ehQQQblfSg3KK/eFEvJDz1dv3UmJmohLezjtoUrRUC2TTc0t9IxWHsXK
Z+lMYD14DBhpXPv4DScRm631Mp6kjLOV8ZFwjpb7HAs8MmuZhTe7fP+n1jX3r4ImB7HW2Lj6E1We
84PKGJnBcTpoJMwxxecrFDY6BZ78tDJ9vF/ktQMs0HnilXeIfLf3LSi7WhofMMXgTY+OLe8hOdr0
0tYhTcW0WDyQdjZ2n9m0R362GRHnk+8pComjPP3YFtbuhH4gtnkxo3hDDu4zyhk0uJ+G1OlfarLi
vs6+YHRRlAmEfomUwq0m4rMrbWlStN0e53SmLM9NPDrpzf1+5R0KhgFD5oM3KqBO/WvVQjsihsqD
yD7a8RRn28Y2bE57YfOwUMZBTuz+5VNWjr6dWMl2tyA1TDf9TZbqT0xPu9Y6hmOVdQKr7lKmmMYM
AbLXtF5/Yyn28fl8xPScAmPt6VDPluyO2MqzjAlbVXkxviUlt5fN0yUKF0dBRBxp1Wk/sxiKv26g
B1MIXQPOezvTxbOR6N9u5M3E2EQ9EZkWg2GVV6I7Olp4QUMLaoNtoAUNi6Pe6Ywr/WGPvsXJXU9B
TCbamJBf7jD/M2AjaSj44EA6VQYDI6jmQ7w2DI6kr+JRud33vjfhx3niIEVvwYDshdBQ5g/on3mL
KUO3NEFl74NNZEGVT7m4a3TQ9SjJzA6phK/lXh71HjQYpBVSKH2uKpMv+Vbq0x1ZnubMvjmwRUyz
K624ijfQX6KQp1ZLxgO1bzNb54m40rK/PRtOTnBI7W6AgpTCgwJXF2Wf2XJDyD0JqHDwATVjYbpY
ZsYUzZyqUoeBJr4tn3xeb33+qbX3yo2PzYsslqFp67kKciNG/QgdCxhAsh2S6caI+ui5/DQvIRRI
VDYdJTsdDOD08XbUL9/P9hrBnbgJrjKzw+N5XJwD5BburpaNW5RR3aQD1xryKMWI7Vpx+soZR3Df
4RkfT/2OWuKBnitAyeVlhwZ7rfW9ntzB1zHNPzNZ/vcMv5647s8LVlDg3YNB1Qd9OUFC8uea2tU7
ASyQpwfloGIOgHWlagBVOf46sfpRY7tFWAxqeMT7CsNEulvv5qsJuahdlM8be+AjWgO9XJHwxMag
Um7b982XnIZ9VpbUAnkDlYlTTsqiGw7fM/W8hjRWyvxpiv47MVDXzGGp1saIh7ycFRuyqcL4xpk0
QP/zKZCnnnaBODMAq2NYKgiEpI1aquqTmJmWIMl8arAuEHghq0SOM8KsNW1JH/VncFPG6TkRc3ux
U+H6e68oSPKw+YEvyhgUHXMa/OXdSSqPzrMdBEtIzWZ4/OlUccVREZhRXtY3Ifgx73HAwT0k7P3/
33+pB/90GCJ+rbGvpzK5YfHbapcoc7aEM02g0w4ksuFj7lU2kbymnvl51KW42eisAifGO/yCmquO
fI7jzu4LEY0/orMjwUaaB8JQSv/3wzk+AypItXg3rwb0+CcxerOmF3RN97R8iu87FzZ88cnsNsEm
A2OsaZAS+PO2kOJc/sYUEDI9PyYpLo65LpW4cc0SjNXMAp5/KlnxgmxSx3igaOkPbvMVYD+sZeDZ
M7tic4tbcTPZXl+RCXrFRIMBRMNuq+E5C7Fram8MjRUlzegW+Khp3SZqyrn6le2M4EOjiXoXuhHm
V3iXpp+B7tAAPff8x9tmQc9ARvb2qnhpDqkBkDXfgXc4ZSlGdBUwmwpkXCd3SmsAsZtKjaFru5B2
8h2qm/aBmzscW/g+RX6C8QQRMeEs8PCO7Mfr4WAqRnJHsFrmySrQsOXxu9/D+C9OodkrVAltRa/T
za05wsPvlqT9LiflHmtVrPkm4bO5+sIqLfh8albxzaLOe/45H1sJNvItKFIhBsLnqmoUan+3sI5S
PkzGU29ddcZ7Q+SaOTD6v039hokkuxuboSiZuqyv+gykU8JOZkaXUc3uM9JijQyLpo3SqWa68E+L
lD7OHFktIsC0WfJBsAHzr+0jl578V3Uo8DX0CGqGDcAAvMp7W/aL8slJyo1eHIgBFCeRPAsPQZcG
Yn08/TbGUDrZX0nZMGc35o8TQwjl0HK8LNr6XuUApT43/K5YM6KSp3BA24lkHEPeeMgmUKGpem2U
8OMIg+bzpxhO5NVWBD/tCkPjXCVbL/kBk8p8N9I02SvwZcR88c57WDt9gjbHZHikK5eI2m/zFKGd
EvaQVP/kTmA3h8QwmU6+csULTmM1il9FkbEoDE8Nc01fp7W/YzK3rgyUOLghF1dTawOOG8m4KRVt
3J4kUzIzdrYwSNaH50R0zPCekIzETTTSWqAep+evNizud+0ZSBmltga87S8ImCJU55K8yp2ZQRIP
BzABAubP9vwpuWrNW2lOtMChtDdtAK6Sb+nQ0svAD9/fjOHAZxx8x32r+Jc118cydol960u1JRz9
trcK7rbTuG5cotGt+Yi8pEnYXinnv1b7GKP0JJ1Qt1BBwzx3SI2/luiLEZZ09XjnI0mXqpYOgQvf
lZ1odkaXB7qR0Smh+i7ukly1t09rcCZIbkEU3YReCOQC7xvfumxJKNHvhN/mI8SHeAXqxoDcwmAX
XYcxItb9k/d8YjNOzY7zSGeyF6AxGv83dAjO7Akwh1mDe+VAWVKBYpT3kcU3IU/jcOmmR2mmbngf
Je4Jp3fhG1ejC0GFLzArRMVpXLaBIfCBVet1fEcfAKjGDaHVClWSROXVJJX+IFZx0BxZRnGKT5TL
Jhc/F9Al7uqwJp8rnICKPWqWev/AW786fA02sr8lxU1pSIzGv0wmja9s4Wl+Ie+1jkQfgMoLx/Qr
V6zfBoWjZshzqW8V3j62fZ6Jst+ay/6JAS5fGa6e7mR5JObvscxIVVa0BM7X6hXJjIv9YW3m9Kq8
4IdesiJY0pxQyIYX167aKsAfchOnwWbbbYt4TzE23bzwPZwyORXT5+odWUprAdMdAs44SoX6SJiv
8fS5g5TW99MmAnupTLndmEuqXQMwcluNLLBZA3ZOJg1ECiDgrGGPYwB7pL2W8od80HqDVJi0ckIw
gIVi5PSuuejG9Oi/q8maTSezVSqh+rQ7CIy9LWH7SjC2xsuMsxI2uoMBruxRuiHilNYD+f4zwIOF
omSW32R9woXtXvWl+MHrty8Nakfjzf8EFw8ku/6ls3ra95Mn6AmSzLGKQ+TzhWnHq1+G0jFhNdd3
ozja9cSOOalw76T1B5GkAAvW2JzSRZUN0c7nJr28OO+2KeCof5uYdhjOjVJcclYF8f805KAcEHUv
1OdhD++PyFJzN1Y84kcecmQl0LjW00xkDC0h/B+Unaq90l0LHyTlROXc7TkKrpEM70H9FbeMh0mG
k3McOq1pE5V8Ufuto6jDSbSo8U43hRQXW2N9fecjTUUNgYRaM33HAmS+TL9c5JaUnMofTrbTp2aW
KImAuvGUuHYod7bXBvwzuUZApJddw1HG8TI9/VzZL+/4qBZTVrftbrVQQsLlbbOkJ2mZl8LVHSh0
dp0hF5o/Uf9xlDZUDBpDKHPrkFGlwADaTHpE5dlob3e3cOKTvCgXfo6OtCvf+Peacluj9vQmEN0s
dBMK3cElHhwkNX+WyAbFGiLllas0grNKCnEvcqzSbAMw3tcRSLrWdtXPNHdve0Ln7/KZzGnY/Cjl
1lniXdxAzEVqf8Wt3XXwI1bQQ+qMjdVCFZ2U9MWw1/XgLCQM4kyui8SDKlajWyLtHEBh3GBCM8zB
z4c9a8j8RekcYFCLRUcAbqlyoYXjNutsOH4ccGsgZSg5G+9JFYbeDHUeVWP9fVaG+DVpzTjoM5B6
21uGLfIjy9T9mbRTGMVtZyM4kJG5nTnSTKOpXCG2wuwM+ADISP/Us6Sanr1/7bqCGUre/Rxz4hX6
m7V/98wf4VGC6s8FjkJfBE6LjxyvjKZJlP3x+xjYBGottpJPYzBtKvfXbbU3kfbDDnZE0HNA58V9
t8AykO+F9UDSuqdrjktBP63x1N3ZiDVa0kyYSz8+QC/VjBr/uuMYgsqgl1VEuQ8YapMSiM8tJl1G
2czudY0i5+ZxG0prxENgx9jTbADcKfYMRn1ULO16mWJJ4BUruq64Z8XL0US0nHlV8+LmGNReFJ5X
IkcAI+PRYVEFk7kSIssvffEVSA4JnVLgTdDC6bbZd1GRY9XXsgXygQ/abPXwR9BnEYKEiJQB7V3G
w+5NDyW6/fJZqrLtsOBLFKQ/AoaMWKG2Ac1QYosgo4RoyX1FxoObkEJ/dajpy6fi11WJWi2p8nkn
2QTjPHsTYLtVF3YOU46ex4CitEbUuPchHIJdzQrqna5PaXR4MlW+8+kTsUaCKNbQRtHQJbwUphHJ
KrkvcTrHamTYNbp0p8IXBDV3Bt/fNDy0eE4ofoQBdKXf9aEqN9BG6ZWa7BBLASxXvgi/KwgjuIsu
zE5U7vT4Ab21O68MB17YKadSrDMXc0zrW0+co5U8uK/66Gxm+DjhO0JYWl45eJrxZAGo63kU8tAY
PRvZZ3XFp4NVoYwzxB8wfeAwIwkdA2CfZWecgrWPlaBPmVxKk2UuBEXf9bZu9VEKo8dejfp69g46
ksVXoUydeNDjb/GQpjSJ/bE66L3hQk0LGuVJV3iVUkfmLxM7P1NQ1vqPRIIPAgutcPutvQf9lioV
7JGGTzFufc3EPMxX4M9TDYQ+a8S95oI7QmQyZjXIeJD74GDZEB0PRvivbID5ylYGWKxHPG8BDIiW
bG8e5yEQlxwsHQLOLTtyLp1P3DqbwuphCEgsN2vJd/yb90ClXqS3X6vEOFQAIa2IXXQCzNKAOMOr
qZhwKup2ze7BLLuPR8U19DvE8JX6Utn8EmsKOCj4LjyFeGoxzoERU/T37ywKkAke1mBtMgr2ijvv
rQQKxf2V+qXFjJK4Y5TvwLhNiTv1koeElQrZVaTfqyEBv325t4ahrF7SMPAJmHnOq/xg/Pv/3cDP
cKOv47yv21kBvZDBIc3zEXN2LaWc4+64PGHsV5UQI0yd9EWYeGRrixyhM45mcFZX+285Y2Uw7SKH
Vh8W1uHKEAA7jkwg3z6bbfx2z41tqeyq7GhnjsAhKe3vsbfxkiz4pZwAdHNSTI9GmR1OYNcX2rV/
uPe5RB163L5rEcdtcWGRkrsPY5tLpcZSkrDa2wMFOOyYKZ+lLfAHorD5h0SsDHhSNorCwYusEY+0
P93qTY/rqDrCKnz2W0izrCsM8fODWSOVfqjFo6VIJYk8GcrTXQRsr5Jo5ykQe0g8eIOgVkuVkAIW
FuzmW2c2hD4YfnlJloLtTp/Zkmoym4k7WvtNJuLTuyGI9rOAnPnbtqrCs2VOPejOaDeq4Zb4gNpO
a+euDcoDavV8eee4eixxl1XSc96FKM5+31n+qhxlF9qNg5TMcsUAE4g1NwOMek18n1pkSb/s3PYG
8ttq78vx35fKxGwZUQ3FIY1im21AOs+oO1F2lV+i+n2npFhTtDYKDrDiwD0U+/VJpUviIaNgBLzj
tU3MQFDpkfdyQG/qyGMmF6Ed0+0YYfoziAGGGVBoIcY1s0Ho9e6SyAWJh8Anj/oxrgEBh8YuxVu5
0ab5HhYBeshRcog/Whbs+b7HbYH3ZL80d8t/8ZyOLu/LZ8jBi2NIOO/FisNx/p63nSYhp68AYp8I
dAiSEVQ1UHAUiGePuSKzkjZ4vuCSsW4QWmc5YmO4WvgKE8XvyIE0wqsb3+Lh1SRgwMqgqiogrQp7
0q0SUJh9PknWkFgvs3sleHcTWrrBfxMwIZ+RUXxUKxGwWu2B8fWrbVw+837hNU8ShjQczE5PzL5t
J9mVCUwpyxaIuEneOAoFGRGJb3H+d3siYEpfAcrbjhp5slOXdUvjalSGKK7gZtxNLvoXaZpQt3ya
qBgo4l/rlvj6Urn0i4CWU2ZK+WJTIEpyVBUwIf8phEs0CqhlPooDFo7CrVzOABcH+/fHq0bl9cT0
q2eDjF4RqPiaqmwE9v1rYh577EUN7dwryOAvyCgzw/uEAWGxaM9yKq4GCsKpu0uqfC1OFAR52pbO
i+v9lTiARwBSRN06BEozdrEcfNo6sJHaBe/3GltZL9awgS6gU2Jw8cLbl5F5SZgbv3/dQk3SFtWL
R+qVQsdQ0aEp3BHN5fjj6XWeDW1NZTjFcCUhrjEPDjSBj6g+NAAAcaDUBGoh/BbgadODlwC2DVNO
WuZg15PKfQ3ibWyZewMFQmRMOSL2JhsuFPrmtcpkBSUnCOzxkRK4NCo3T+gBblshPIvpmfD3c3x8
QroI2zcpthjGwkiE+YbdqPncB/9lNg2EHoWQ8+zBf2ouQQ86ikliOyyWgJuSKvaFuNm8M+5K2BIf
f/P/Y20bV25v2UOLx1LE8lQJ24DBZ6tnqxg0hiKm+91z6vkYt4rdPoODldV4OR9AJjAD+ujCYsKI
BGn1uVy4qJKXGfj400AGtQivrlWG3bFFS0sYbn5lQz9kDvsctwBhw9BzwxZXvwxv284cfeJPKJTz
u7oDzgWzSNywKaD9+BSzW2d6OrGkm7ZTULg9OrK+NhGDIzzxzz+h2GqlczypJ2lv8Dic7nL92x3W
dIymKSLzbqSF7eAKES2Tc+dfyRlec2s6VMQ719wRiDAYmR6Fxa2f8+XRnnvqlQ4SY+fkhARUSA9G
AQ618OZzQ3R4bktB2SAePG9SwsUloNhXRWgWCKhmuT6HoQtpAcwIa92mYIPOdEA9RrFo6jttQXgu
8eHRb3L0c4Uza+iWIC8EAv4R1UwoMx9Nfk4pUZ0c44B6reVWFtqc/aUpPRh5OzcQYptJ7koamS0C
cTalF4tPXpwzIwegRZQrgSELcLeWEq3Kc9kxPrySSzShfCLVLCIwHNzIcX52ax5c9qWQR3/D9VcO
ZNIOSdskFGuZwWbZbcvz/IGmg7Xl1sQra2gmxqqA/cSaP9ZkBUfKNuZL1Kt94QfVfz1Zfyokp0si
TnI0f14oMt45EH2f9yYLwlfuJQKZSMkggpu1qdjy3WBuGETjcCcr87oxW8ZJ35tYL+py0jOxcdLY
tzJ6SzhrOTL3e80xU1bKCZArz+O7Fqxfzv3BxcaaRgFmPtZZVUWCUcQQdOXh1DLjMuqMeLqJ5m9G
3SW9U8ZPS33hNgunK5j+tOW3uLrgaAWZw8pzCfs68enmFJ4DLtDzQjNxeOt64cegMJS7XncFN6mr
jR5KRje0Bq0+7rzGibYgMMgCTU6rN/2LSa+xN58/NSK1kdu3KAA2QzTGvFJIp1FD8ur5wZBXIjSB
peU3dRFjsib88rzGLszcDYR6mPFTl0r8B5L11VcIIRlBlr8AdLv/qsXInbAAyrs+enXi7MriwlLf
F768OfY69+SbjSDphlzyqafDUtuDYB9mqk2kyYr3k41fi/qRVPovmTeoO5Xul5bkPYh74XAiA+o7
MOmCsK1IQWywCI2apJszuHrden3oCkDPOX0+7hhD94JmOBV5/NG8kLj/qYQwbeVfMEaPMCGuc0OI
IfJ2moY85pSnEXfIAmvqdgxDbAbu5g4eMsJ1L1KGrww6virHzObndCNMzy24ISiMLtp8PsC5Dd4t
h/QjCuy2a7cqTJraDyeqGVVW3NaSOh3bco64zC8TWfLn4fcOr53H8w2+HZi2mpOl5zWUNVoakyAu
wownb7Y4/Pnvd8fodFj/nM1TLsRsPXJgtyDJ8xPoNSlcX4NV4KvrhF/rd8nfeiM32nWnhVimnEs5
lXFCvoWz+Gqu9npjIG2ntr9Kzxw3HOtYCH6aUK0xzTwlPBKIbXbZQc2y3+8AZtQzHLI2vkFBT6xX
n1usSQcI2zielx2x660AePUUKSoLimMLEkNEG2FVM3UdlRReVhHJ2TM+iuo3faPydj96xDlaw6K+
X4Tui/fiF/HM3f9tNDLVTgWrA32//wQInIamiF0KUcg+HaYwAHVmPFyXJY9znHJo/RbM04C5URU2
UJS678D4s/P+hGWSzwo345fRzGBB5hRnTRXgKYDelmL7GG92MGC59XbC462xV8OQc1M0Es2R3iWI
SfAp52e1gjYMdCNKJVWfLkAEAECXEx28S4eyMkzpntP2j57qvjdJigbAN6NhBkIzCIMzXP6LWmES
EUNN3XPjBMe63QRRd6/N/HyI4HEgL5fb01vaJE22Ic6GIr8R13KO8VFxYuFc50NulvjhJmpsEnc4
92mZkV4T5THJUusjNibyZk0Bd9Iw02IwMBK3lWXWex1JjzcON55FwpUdfiU59yh1mKFaHGk/wODL
gFAiSLQCaq8GLSM+3xWgGieILOZjYrCpxPtSziUjp7pyzBeDwPv0nTIirYuGhBjk9KFZW617nMBr
u54buVf4O3mORRgaeTLgbEdM9mSIMzYuKUs/GJe35G6g2A04WMs0gnlaaxJ+8qNSlAMm8Yci4Pif
M7HC22poLoLV7aDKgO7ecmdX15c3jiA9P3715/KA53uZqpP4VaGAOn95hV2l9EqeL05PoqCd42I6
lXeZBTOS1Ecc/l9l6CbLEOQyUp/c1Zipaae5PQxkzG2Zo/wrgaFWR7RKI6vQEKW+7aAGj5v1iRZQ
uXzL/bvuuHkw69dYDeIzpuiGxSK7f85l+L46bU4TYsqWfVv3Nh/xX5TvGwyzAIFqg3APr3p/9pJD
neiUxdWlZY7fdCqwC+INcWj2wB7ZDHwHivs0KVhp2PubmF+tivu1StBmz+C2s+UqIjxCHcSxdl1P
jUqF3RR6KksuZbmi1Bm7/GamYZTOKCdhWPYl5Jb+VtihxjekDcfokBFYMckrQNtGGmivSRBFZU3g
mwg1w729pNE8ct1ugWO1Cfo+kZ8AyA16bF6KVeqZK7C+0ehCVq5CC9T+5Ul322IT66GgPOpsMRhK
vtMpE5KD2VWVpMWZC/YhzmFiuvnDNaFvpiS4DKjKGzNF50rzBg9zTPNC8hgbidz37H8ewoMxa6qT
Nu9mqio/2pv1kd6mDRXyOW7pCrS+6GVoD6CDbJ+6YjQis1thwMc8lAUw2RPPDfD3DNKNCREusDMr
+l/JFo0WfDKTZhzz9QEzWS+l6M7wU3lzWmlZb//5qzbrSSELywJVdZFSOSrGzeudyDiHhW7q/jM3
G882o1BhH/5bmV/5TAtfcJdRPpJtjwVUKMpQBQhldqbktan44rYv64M9QJ7fMkyh8NY063beOuWf
f6CKPu+TQL6CDI3zq0JRER/1rE+uVXiTgngNerUgLcXTB5q9QG5+BtqlL9nH6U6mGyt3Q8NtF6ZB
S5gaTIb2yYm2smzTHVRxBgJ1U34tUJJaa5FtYDfzlpVjoGYVFDp3KVT0y/VfZN/cpbOUjA159psi
Q3Pp/0mlEBuz70XVaTJBePSgW01G+lMwDMJ3Ijg61f/3Q4+pvxy7qQe3OeuKM1tyWVbIdRc7VqUy
btaYETbgNJ7k72YkgsFTmwNwQWOlvAWQ+AXujSoM+kC7iZ71DN8UaXlRZwu0LVuD5Tdr5K1GFNWe
jqxQmbNs/pAV9Sm0OO1ekS6juZzi9nQ326gEoxcy83UjZxPZa2kpCPLkNjvJz2PD2+GirlKpgLV0
cjWJwvWes+EfBFQkEh0xE8mWcHYceTruSaMotEOqQdFHImqhZ74YhdVOaaiXFz5Lnrs1+RkFWSAb
yIowG6PfHuzGQw4HiMbYNIotp+nY8mYugEOYGJdBDyOhxQR2aPbPYw9pPzpuhezE9S6tncuyDwkb
L0QZTvO8X087tFfkGQsUaMFQn0TNzI8ZSPdwWlde254qkmSthjtWQuXVHWFndMX2K/3tITzAgdk6
jmPnTsMmJAqrjRSBOxCxJt82zvJBe66beRrz6LyFQTfkgfzpPzEfo8r21d7vtLbBVXmLmRTd9y2Y
hHuJuwQht9HdSW9A9Gaxy7fihvOFLMSIawOmB1OqKLR6VuEj4pzMoDEdw3FYWN3iVWGvaycJx24U
Hp9q+wpd8Ej7Audq/T4bF1L6o29bwQU6zMftb41TFzlxiZdj8uAKwisagudkiOEik6XuA14eq/S5
26ugeZI3Y8cX8jiNDizbciEwwdEc6CuwD2hbElfNoDkg6NfIYVXMnhszvuhZmR2hWNZBjyv+Nt1h
Ai57bLO/Ll4oRm4rJ/brim5yLxyJi2PvoW8Di6RUzV0b3HaJjb62PnLae8xUOtjMwAiL/jO0O4eK
Ieop4wjt+2CsZks9m8Y8mB8wEPfA2Zjkk9mX+OgBC3+yrre4GJO/idBZmaB8tsqjb6NyvR5AYrhi
jOzqcekDVPXzSUxU9ohJybucz6MsfJJWiJGMdxD/WYJiwnCAu3zWiNnXzlEsy4I/QTCFHqrlbJgs
6+OkfVTvp0mDznpOLFNK7BCNn1KUzWAX33vwh2IG4O2Vq8AjEE6ChvhQqwNzypar1CnsrJhSpa2h
O5FfEUxQEx/fPzyCgSVqjA7cmNfPl3YYmsb061cPM/OReQNhR2avBskHO3IT2u6kUPh2OBTUXsJP
QP4JN9olt2Ohy6cKQnhL1mtNIa5DrrAr5OI5jfscz0lWEf1PdFzqGHc988XjHOZEjNMdsThfDAmc
CcFI1SQaMcRxQeL5MqfexfyUY97OroUTPmdyq5MVgz8guoPg9Lqzwts13KaUEtupGXZh/RclyPfi
pchMOPeCrld7RmLCl9kZZi6mSCpzwQlW+6oxypvV00LF1+jEWDWO/6z2h6mvv2zb0p86PnPQswIt
XijRVxVkhgNBkI4iRKFqC2R8csXhSvcWJ1X8xnkheuxO0Z8KhgLM60016V7WacRNKYMzR0C4f89L
gyCL68psnzHQIdxrclZAElr4e6OfQCBOEYZjsaDVHcufejPo0SaOh2yeKHS1gMx0NxnjtQK9iWA7
B0NkgUbOf9MuInCDVoJCu9GAPMiwjO4WJDHUrVhepOx9DrJGwhO3MIaEHPutqZPmzGwRqiwNrTTd
GQJcqocE+0AoxZ7MrChX6CnnTA2NIGo6uSPArPTYAC48ozjto+9X0L465vPtgkCaSysD8Rh5pdo+
Gyi8l79B5BaYiJWG1SpyXbFBOLKj0nlzY0IdDjChVvHIdQVJ8uKqSooP6Wkzcuh9KWLAfC1xM0le
bF5XNeIVJnjUkMsFqXPZyJQXghk5FQcR/T0kSHu3r0GA77c2HCz1SILvUepQjgqOF/NLk4zh2lKI
ikrMx6uMQD+tdZnZZtuh8CuPilkVFE+nGqlWEGUkD5D5T5tyl5eW6Ubj10cGTHoX2prBbK7zAM2W
JnUwG8yViKlJMaV3xiWScv+56NUFV8TfWRhZQGeqkxjDs8MyhoOxQnvv5ChA+An3Lz6shlQ+TZFx
+v54df7iK3ABP46asHTfLmKjdc/OSB6NiStCNsugaSLPC6OvbWET8ykCrPMZvCb8QHPzck3hVnCV
iZQj1YV7+yBabhqF/feDSN0MhaOyK6HAzUs2f/qO0TrK18OPn9yWft6vbGGqycBIIlF4JZys6Mws
q1Z5HfTcgPQEUxd84ohql/LarbKZwvLB/lJR9//+6+b+VVLmBMe+rucXP/7FLvrI/01h+5CZfx7h
y96f20BR4oJVgM1ODXNo1TCb/sukVkUzzeOQV7uq+PM+Nfzt3mHuVKfuaw412NZms0P3kmDfmemE
5j09Dp+MsHcauG1phN5U705mlJStY1ETh4kIv0cNU9fbBbkp3fZ/HIFyjbeBEulDH9YcGC242uA8
bfO8IvbagFtCj+v0hJFu4tRCcufcbS+3K/JSnHOVCRyt2EdS1GfM/0CAMcMxR6z2LvprbcG8010P
U3Xn1IUbDH6mfJubn8wQLT3AAztVVhtxFHUgMMpJLIvhppzCKyRcnX9+oyVrBA/7c0VTVEzkCXEm
Lcv9Mix0IZec5780duiWDB8VlEbxzgNkl5Zi3TpvuAhrWULVJogbqbAp8VHXPiTes0MfgmqYaU3U
FcODWHvbSH8HLN7bSBdPQTE8P6zswv3IcP/Y1lYP5/Ex2oZAOKxZiyVeTBgf+rZfFMsQ5sSDMUuD
JuOUYXjA0RoI83PWpHD+IdbxOIi/nrGKYpBuVnSVAW3H2xwSTI1zB3YIANpkRNNInfUkIO9usLY7
jUPjEY6YYEDLxpqHyPa7AvCGFH8hVOXabNTfYZCshCs/poJaGngr7kDlQsWbMIL5UO/GOx5Ak2r/
3HUA8GpSe2wyj4fSKj3md1SUNntpYN78Uy+ZtbJnzytOym6C2RwB4MFG6uBxnUdXT9PQ5RNTbGPg
+AdGekChXZX/Sc6R8eV7NOcVI1dbh/Vbl/TX6hxh0wQeYP6HGu7lLdradQt2lGpvcaGHL73vwtwF
LXKVPyls5C0dG2Q186vtETLXVCRl/N2KFcc7PLNBfyXtkhINgWg8KPMWOaXUCuXqGIYnh+WeMoTy
1dvmywSxstYJoUEO3cmA1bvxXT3qWOXrHgKm/bLJcxKsUqzVQQJLpjbZ2aVV1TvUuqMNc3LLDU+A
I4UQma50KsSx3bBBwaatsZBRi4xzevHeU5dHsIl20olNJA3XdE2GjZvTyY3Rfnyziq1NSotE/JCh
95Dej/dxrvpF9pvHoNJt5POThcx0s0Xazckf/aoxum5OhgxiNJWPcYYeYayRiaWRqVQOtXQUUl1r
6qSB/lvEBCH6ECHCmvjVnDgkVRM7b9Isnm8vxH3QUa2Qftrm0W3TzgGTnC0WjpDjN1RzF1c3yGAs
CAcd1vBxL2UrL4JL9skQ0RD0HdL5Pm/b/jpez8E03apAvISaw0L2FGxbZtxnwXCVprwwoG7tnwYD
kez5Ht0yy7rNlLeqLFWgzmnZeAnebFHhNyD2Q9H2wPHtCO90hchvBeC2z03o9ok438UyVNg+QAL4
biCOkmKpD9AnH+2/ibpqlU08tgJxKHbEJnI9aV/6p+74s9EHWAj6cDUJuFq6vQo/2zJuqx14A6Ky
p7smhKyZAIJL0fZsaqwul0d1oBk7h8oQqWZ6s/toyevlmZHiCD74OYO0tNHMOoFfAR84bpsNJoNi
KSDrgZ/t3WIc/X4oDeHSNgZ12ZLFtLive6deNpr2hLPCYsrYsN2nIza0bKe7nBvp1dkX0C3DqF7/
3ucmZmn+9HtZj0EbjgaAQOBTfllzJrgd+vPa3i+Hz9CiivEqlQHEz/ecb7BEwYA8jFFKqj8aQy1+
0f6sZXfqV7wYvArGditBDzZwSN8dMmjpCDW3/poY0c6DIAeReWwNQR0eH5+n1JDF+fv1EHkyuNCH
RYlaGlc4qS1scnWwT9GvQvwhdX808UxSTCI/4KjagGXHV289GVqX6vJKa2vUTPxrvYsijVduMpye
74fMlEHd7g0kIX/70CdX2gR/xcFK1Ab9BNK6KFhewlcqGWmP7hQPOTdlnWO9YtCXwxp1uKi0zR+t
BpFe4AlriONRvgtS2PdPDGXg4O18cJeFV3GNGKbNtHfjrLXAOiqUeknXoQ1D/R5KBC1AuJ0U+So+
F5WyozLSeV521f7tfzD1b6sFgcrB41qmUvw/PzcyXlZ0i2GEUqiRWSF/prCLm975CeZGqAuyhn/q
C0HbBRpqDffYuGtR1Drnf2MHL77DTM4w/8kkZ6Cxsomzk97spU7AIuE/jNnU8gUyghpEDWYCFAeq
BiBAPshwNGN0QCjfMV5OFM81DkN+s0CZScTC76sN0A5On3tdqh8gj1BF37rvIlZBXL4UepQ3d49C
9fQ08SoWdz1HTCg2rnZG1AsxHkeTRMlxSmRD+0kcuYEhDqNltNntrm5GfOo3Tl7m/xHK68QqZfg/
dc2lzOUcDkOuHrgdR45eI1Tct9CVxhGjp1Bl2MUqAxHDp+uZJRVnENyhKBc4u4b3J/eRsjm1qHjK
6YZ3ZpleOAsOyi1360DcYB0JfCkYM7hSvDDcMwS5A8I19KUX9VGW28jSiCfAHeLYm5J8UHx/NLKF
+iKxsgTwk339LBvHsjWNr26Dt1ujCijkGWgF3G7hED/VuWTlHGdRIDHuZavbBGTSjA7QstjAgiir
3HQaP3Vc6lx+KFYQGWVtAAJHq52MCMYphex6OK5YTMWF3tQj/goVraOOxJlSyrRDfa3NJ8Klfz3f
tm6CAU0yrMGFF7Zjj11haAgOqYDo1bmRRn+iJ9bgB48F01I2t2jjDh6RDhZ1Y/DBNOZ4OK02Soxi
ldIsRTQtT3AV9fmqO8vvFHM2A3GNOkLtD5hGKfJvamKtoKU0cbJJbd9z6912MXsQjHZvKeBEFJot
AadmpiIjQ6m5jjDFjGtdF1R7HfKBeMXIFRtJUZO8lREO2REoKCl83hRT9afkEyVHgMc58CdOUCqN
aNIk7tLZXANmI/gmELT83+KY2e4k4ZhNYumHN7OF7jE/LcuN/8fpVFPOCgM3uEwk6d+5yIYTUZcp
ZpQ8qPXxs3NgyXzjt99ZcaPw1uU7CmAjbomxEFf4EiBYdheI43RiSLc7EiPpu16gBJYfdWCAH3zS
qAb3pI7Z/MDRHRHO6zuS9rZa9BJXLktNOivGMIIbG7dbtpb0GBZir3BUtYHR52K+QGaNBu3dt7oX
Jbx5b1ByMovz289KVKUQhJ+uLGtVVN52gVatRGB+f55EM3lna/2h8i264TtfhP9Sni7MimbBSv6V
+gvpG/Ch6/aPuSD+SL1gFzV/ss5BvlksBIlDhZ5E66veHe8nPgIYMgXWjJ/DWDsf5rSUSz5Hz+8D
RQxVc1Nji0FCwi4taBCa4cv4iy4Vv6W1sn5aDiaoZhk3iqusk/7YJ1gI4Cf2cHl083eD60o3SgfW
QixDuSQ1MmGACZwOU0Z3AuBE6/aS3GmDtlvSyl2oFDM6DBRLBv1D64UtqM/2jmZkUxpKbKrMmsnS
2PFaP/yMJpr0pjMSzxwBm6331WZuPKXUnUqVQzRnNddW9NRQMEDxAPVqoYsQU5mtmFmdSFqpRizQ
6px6gjBMfh+6dRwzZvxUFL5QPOnjXn+aYw2ljsL1yydrEAgSCIGBp33pRk9mst6tmwVvpVhFRjXD
rRMQVUSDju7dpKEObdpS8n9UXXaMcdkCLp1FE/1m8YFqhl8Y6nXEPZNVUGe20M3vTFD3+Ji7wKl+
7J0f3AOONJr6KMqBxyicxppyTeUZhHd3HJ+5SnVUMSMmdiDzU1o47O0NpIuw5AfL0uPUsFmbqo+C
vUdWZaEu4DNjVDKMP0dOExzAczcXMFp3/s4bGs/lnlczsNaooofgz/jqYxEV8mIax6XPf+cCvU/k
abj/4fZMnb8AEK0VxL5bJtpC+6DhyFZb5tJHi94jk/Ayhdd2eQxyeMdFmFPaLTokLzOuSZhX9HV/
snE3jomDPgEUtTfMfcUIGyTcrLzgTdZI6ViTAm6j9soppdkOceoYIUyA5OtsGl5cfDZd9eyX1HRt
FFh6ZYH0UaWJKCANW5ylNNOKP6LofrdQRyG18fJ/WOHYEf9eUwUdLl+rgNWUwHLy5Yofm0ZKv8M4
h+NiduZs4wypVaaMCZ6pk/on/b7wB/oCB2n5t0iI7hIKIWXm99/r5p5yIgiFwpE2/Tc4aicFIwlF
viRm7LGlOOkAze4+haLcUDbIdwAlkN2Na6vPGGUp0n2JJK4aX6zggesuuQxpqBlEgLMFlIArncic
t9fepOECK/io+fiRuQg00WHUv2KXGnfPBHIltHMxWeOCfJUoAlW1NTltHummISxm65q6giZdtYJz
f0W/dgLIa0B5Sl/rjYy38eJa+Y344/kg+AQvhdSOBHXRSBbm5KFZkBuCjOY16MW5TeaIk2+s+snp
SETaJeUWMpSmU/dZlhcyoFXYkR2O1tr3uORurb1TorsVZKuyy+0AIKEwgtoV3XXieezWTIxAt1kU
oklpaJ68jCCe08u/odLUu1bslHZ4cistH3qTJ2Vdjh4wKeyEc2d70DWOBerOmgjlnKK2kRrnuVcx
79+jRwDlwVfY7R2yx5ZACzOJQoOnyBZXOnG+Y3OnRsqhT/fKzkOpk9+3PmfLjrCWr7m6tMnPiXFW
cCWlq+3yIjYR5/xi0xJ1tf6nyhW6j4dk7R1K+h6LJjwzx9blJFaNvRP3ULUt9Vh+YTnz847A39Ly
1/QYfv+Gqa6ipb0IjTclxFGUOjXlIbxC0wGXcVtj0BqNxlzQo6TMkSHjuC3K2sb77BE0jlAOMVtB
gQHeZnC1CvVmVqTz/+gqNH7JqMfaHFdh4WiP9bOWcuTrgyT2/BgUzzc+IOvjq0rz66mHQgbZw5Dn
hjEQGr0tgZJRVeM0tmGoavXSGme0K280EAqp/gvHaDbVMm6P9y85zcmWdqEToW+H9SGgXkdvxQB6
HzmUeR2N8HduPrsZVkVWvIWBk9DbllinetuPJKki3whuSXvOs+FzXd8QszsXPAiX3RRrGC9uyxsL
bWhzLL96O32EeiXbn9hnvPQHiXfP3O9nFFJNdeih42DhGI7z3eKTTYZS2WItIQ9Q1b6DG94KMYDC
bDr8tn7rAYbF33lJy68BnNrWOzHnncMCFGFV0S2HGKQaTmekfp7Y3GqLH+A4m7d/xTiN1eQ3/py7
UwkuMZEwlXqt9OS3QmRUXnaT8MqQVYLTXVsqzDQPesaHaIBCY1MoBSAmf1r9UJENA5MWY3g5IKA7
b6b9SJljYNaOZGw5zD8I6saYXE+qRlzhI7EHBc7xpdltdVyDSo9LsUwpqiB+gwfNBwBzLHsVmQEi
bwatvrVao1Yk7+LWZWYLfnAV6zRJghm4t3EC5GrDzMA/QnqySLPhboorafzMHRqa5c0O0J8GuUgD
9Tk5XGx1TTPwOVv7P3eU38bz+mXhNvxyw627kFjK6sdX+6J8Dn5slv7pgM7vBhMROCLRtqJi6oIl
mGORULFVKuQwpHm8ALSEvdx+njVWXmJrCHMcWimz/G37NLEkH9seMb/TLYSdc2qI17+Sj+UKGcqy
GxHSnKLlZyqFTBlVk30ZOcx0mukhVvQLSIkwyctU1geA3JXAZyS/AZ2+Ad3yZhVcfYhcTGzLg7ka
LbgRUH+4t3wdAQL5EPga30DiP9c8r1GAfoz7TDmSieiVFl8y/g3ImD3hDnJd10vQGw/yjUvW5/8M
xav2DJADCN+KCfB0GpxLkBd0Abvyo0rqC2s5iSFDiR1ElISMg5qbG7wIgvumVpPMvuwROdY8E/8T
ANVDkNQxXo9qd0aOzQH6XdrT0DJZpBq+qB5YeQ1GscvAoiYKzIsWpwQvHRHLFGq6E+2xWviz6rV3
OALnOcdKMKS+H5MkRPiLYcllmnTD5uPxMWRLREfnYagv/JLvW69cWv+hvcKr91WdjG0tlMm69h+J
4KYTKGbfDSd6upnrfxWVMUOaaY5Agnxf2JLyIjhbgmHGcZT3uu1oOoCJp+hQFNF1Ro3CZH35LJST
ruU0Ew2JvpdWNd73HMH/113YihKCFCag4qjbTHnidRplSwQQ26MFctu57Z2jui/fpjzaLtRLnv1W
4BIYFgZI402v+1tWFLaxH2OptEYeLQnT69xbGNFgLAt6XtJfwNManTVJvLEfCmSd7IGJrb8A0K0C
e/lKFWeMMDk549aWa0/m+1x5q7Fot9Wy3dORoB/++ZzLqzzNKWiiMASL40NsQWpKbgWJGcgLPwNR
LiyJJycR1RJy6Uv/Wjt+6QJKRwt8/EdUxE519SNDFIMEfX+wQlXsxsh9jb0DDP8Sw6Sytse/2YWy
wZBrdbshTMfPdl6eOGvH5pIPYsXaOGz3U3MDtrZfIe7gxLNcTbmMFkHpRwwgoXp8lEnV4hOM161G
qgVKzW/Tow5OD5s3iCX31vLTNghbKn2nLD4uWqrG1hyKFx/iLh+IzzUevk9Q/Kavq6HWl+8oaC8+
Ni6WgIITmvN0eKbrikrQ5fX9xHVAu0QvMyctyaFCYeDJj5RjqPfdN+I0U1f1BDgk7bny8qf/uxbh
RMh81E+SANh8JCok2FCosPWgG1HEEPCAcBV8nYM+zNOerCvW0KqXgkQmqbLuVRtvFoNIwS5yfn2X
7fZVfjTTooJu/mQZFfwxs/DdmEZad9uHEdTccgWXmsvuX7QPSHc3aUG/1YZBdi8lwMKBZcep2mfj
UK9pSYkAezEY8U46W/+mrRvSFF5USn6WcINeJ9ymzWS3zi3IBOoQzlH27awPqDCFP3fheu6Ypvpx
9ES6lFF2i72ESD4zhI7hn8J85nVhIGzfc0NNth9TtgWhHYukbGuVoLS22PiVqHuXbc8j2ggLR2v+
KDqCXT1dkpXdcNtPjo/yJ3uB+ZKwQUGmU6kmwGxecdEKgJHGKimKmdKkEncsEckBCZ+oWpY+9brU
7sfoyC6a6rHp9vkYv3bXH1UXqqu6Al+pRKBwx48AkNlEw7KuPh2HPzgmurcHgPHnYubILkwqW7Tu
6zmX6zXcdM2XdZgSd4X2skV7No4MfG9/NZXhsUxrKHHPfskGElr+JSm+Xkgu+MOeNgSMicw42akg
qs5bA+13v1sQnpPhU2NhLvNIX2iLEO3YeCAFMrt/J33ubyjfjdZZHbmOFiMt140Syij+fhqBb2u+
AK6dxMnSL391SZ9ltq2HM3dqis6GiKUQyVIIhyraeuXy40DFKCqmR87jvCuVpAy4Q6x18JoMQuo4
G2PPeJjrBVQ7ElPEzGSFBfnGQt65/y1usvdXL5udtGiO7z9Sx7qi6lr2B41ob+Cdze3LXhsvlz4O
k1oadjEbbqfG3IW/Ac0pztn7X3vyXbiHbV05+TpMlWVl38Z6DWBNgCiHsfJmBmRRoqPzdkIxnzRY
DKHKWA/crB3dpl0xuW6yLQjIpaHz6xGmhylU/o6VkkukoyAgijm3YHCfBwGg8kRJ6sLnMPOl5QM2
OJwnaWPSyoK+cGlkZHMtHE7MBFgT4BaLt0W4zfD4JVNdUyfUQlrmptGsrV/aXBwmZKkOo2/FnCXb
5gLemRAXEuPqKdGSabZCANvyTSebgfvV42POy5DtLdyChEDqMwOitR1MZEwTE8TCVdmgKXba8t1Q
b4ILttzx6QkMlmJVxErXDk4DuJnSNdTOQv1NZCLSTccGLWkrVZnGiEQGHO2ijOXCBd+HD5/3vD3V
weGwj1oLYr9PVJAb59fndqFNmoiOp7WHtSX93pqS2t8Azw6J/EYWynoXbS4wdYSjDvACPjQ2FCdq
Zn/kVBVdi/AqU7mFtxGb9r1rMUrijzFNBz8QUef/vpoUGiHAQBAEf9Vt+wV97BxKocpkdnoHWHhS
hnNxP1tDXIa4gEAV2j7q015fnWdQ4bQPjw6EXrNDwO923xg6nYFHRvguHasQUQKBTzhf0UEr2U0T
jXs9wlcw9wAhhHdu2E+MQgt1WJY41abGKQuHdxd9y/ibRz7kIlmXj7Wo6WxZijDaX8xoA5wn72tH
dOX6olOh2vl8k+frj/rqnIMk/P0gM5DHY+QWhmnuyOJ9Zy5JoOyTTsvrYzEqGZ+XK8ns2coK8bjc
NAoCDcWmZ757G7ZDzmZt1rUOm0cs0+Icv3W24opPhenklqkbaFm3g4BieC0HB4joSyZoxHgcqs5F
GG/F3s0PfhJIRq3BjRRBwxVO1aFmEOQNY9zUdZL1eAjJeTa8OiCFndH3Z1tXtfY9/gzp+ZtTgdJl
ol3kTNLc8D+z/LYC1z1rdnKuNwdcA8DxasQtOkUgn0qsvFRyQVW8pxkfdk4uABIAikpaMO6n5hdv
EVYO+lF5bhmIrSHC5CiOS8uNIhdbZzjmB1tVWvhnqEAoDhSwtcKyiO2FSnVrM8wVucpUpKcO/jgK
WdLeAymEu5LX86wYrx4scKSTJ6fjmpuE6I/UasbCko5NNvjwsiST0kNtA66UJ9tMNJvlxnV7C6mQ
5H3g8lXWIslP/fb9VjWvtLvlsIOHD3MlqDoQY0MkZ9YF9X6y0VvlxbRAVAQhvRdDLx/xaGP1Ewr9
yr1UXUrtNRA1OmjY73dZr/NSOr6KDygW+Fz9vvZOujDNDUj0vAbJwSADBq1TeyZNzKVxXTjVIW/y
g777l+JsHYJjQOGuWsN3URTDlh3w1yLA9+vqi3UXAV7qQxXClVeAFmh4f04d4BMGcbkEDofEEWq1
hHuQtQzBZXkxaymCaEHmzfOTdKP0u9avrMyeCHR62YcglXvQqKZWTHGlHYaJ2pjMyR0UUVh7OmKS
HkLpeEda8/nDTwjwS/YxSLyya66Iu97E+m9HWi+2CF4bxfJ/GH/J87t0aMHmqMw4ZQMpOxE4bRSK
EpZSU4orctDTF7bv3Sn7XFP93I2ZdKalXZg0XSIJg1O8hrYBxK/YeKXqd3ei6MpsmgUGg8Y+NoWl
DLvfSSNbOsdrK4JjVcQZXxyEo7zbHS5RZq0K5+YKdlUYQG1b7vXuU9OvoBVmMzhsPB7VhD6sdjO2
bCIjtKhQ0knEy1ubtEkTKVXcN1E73rrNA9wMM8xx42wmtYlZ//4Jq9otOTHNAQXloUr8kqaCZFgo
821w7LdpZM+Rzj9a5KIJihb/JVGFGis22D3biBB9vsLdjexHaMFPicAJT47g6K/s+hbn1Ho3AG11
ZJoark8J2lUAWGCtFuIRELl0xJpwhGP0Vbb3K9/NLlyDwpnNGcfvvub5mvYnnfE5En7nu91Sijgf
1NhUQM4CTe87aXAsIXjiM556SZsmWHqqjkazlRS4owzS6PcSKs9+uF+MbEv3j8YONyjsoh1HVk9e
e11WVqaRipCjTnDtw3ky0CFVcoeCqC4dudxumHuHHwR5apZQqQZVnLKq8YmBfrfh//AjV7d8R4r5
190F7DPNWNKQDrgg7yJPidzVDi0MZAtfgMAfUBanFjFbV14gDC59L+R9mxNIGt/JBtOIjltOWK5D
BYOsKcKwYGKAdDAp2pZCHbkyOzDG/S1JqPVuE8nFHdl+3bZ2X4ghVWx/RSdZ99JVnedWhE3gU7Hr
xhKK/kEZeoT5sbW1rlEWcqj6AyfKERxM4LcQfRcqCPUd7TJw7Rs3MCsjpbL0OJMmSS7eepGUgkGa
JZZ3YIxD45tX1sa8nqqumbROjkePooC9I2uIQ9iqsi7pUGy6+iLrZ1P6/cwwg7NPq2UHC/YJdC45
/CGm+6sKwjcFQX562La05GqmSwB0MAtklAwInnkJUGiwFfNdW8E29vQNzA3iEQG8N2xeF/3gNCkp
DLS1n73Q9j54tLeU0GqhekgxeSIm0prqzRUpxxxe9yvgO7zY+cpdrfevgG5Rkv9RUIhRsUip7KA5
OYEjKKmuHMAZVIC7/URavCLylKCAJl2VGAaMeQA2BjPotYXGnUO4IFQW0UIa7JXsmpuyos2liREO
3bXLPAZ9j/dVvPA+mwYQFB5X9Vy0Bk7+4GHmtUHnNS3lIcHlkb3Ij1vk3StzqioBfsO7XZq4U4pc
Lrb+CrnSKC2ZUK+dNv7OhZHw+a/feAP/F0oq75+xMfWjDKkKBCJuKQVIiKY2Mzxc1DIGUGg5vUWE
KmP3o1FE44sVaLBsXDMJ6FIu2iBTwYrdq7pkDBB/t4ZDykaxOV9+fJdYPAbj2RUYLoZpRgy2BaGZ
Rk6jxfHEwNAiGV1o0Pn2kabjJP5kZmsWgT57T4AmvnuQMCdee/nBnD7w7zxna++nhCpKUWsnnh+v
C3jTs2lO9sRIIYfRREzcL5FN/aFO8++1YwSovK0qBZ5k3z1NXQj0rf0FDpy/4oQiUaWzBSsMXpi7
RWHD+loE/7E7JvryoVUfXPFV2tVgO/gu35xfbWVer2i1kXMHGlMXZsZHeLtj2CyKcLgy5z/PiWSq
PNBGuf3R+BEASt6nrkwN8rhhtefMcw338fT+S4owlTH25CNfSaMhws6V4l9/iA31IpUf/IP5I3Lp
NcmKafH3/6bD0wX5bU/5U7uov8W4w39+1iD4iOcEyhZAlilng3YlN/v7p79A92aM1VdfWLTGIyzB
uz1bGxRFm5WHXnfoVZ9InBVsnqHDLnP7mQ15i8BnrCiV1qkfcbjF+hQNgcHHtboYigHiCDj5Tx+I
yXdA7jvKdve2K1wVMxn15p/l8idNO/hG98Y7x70oV40IWLdZazAFZaO3jfOoA21ox81/Pe2VMG8/
7BtWaWlo8v2hFQLX/Y+P7Jh+ksz5SPh4rwf/oSglMmF7PuB7EvO1Ep/xqn7+i5cwGj3RvyF+nyry
O6Zfbe3LhjqxvvPstlqBZaME75E3adRUtsv3n2yeLrKtrwkhwUoJ9UaC7In7Zg6VxgEIxMUxQkZT
lJKBOyapTnK5Xu50cTJCcBgCw4Ayyn2CA3YXcDA63hao+yBhJONiXaX+TBm+qP3Dh8nOBphnS22z
QCxPKt4j9MKdW4EirsacbxG549+NAgVBHWXHVU7B+eSVisc/+oIskq24gB2llr1xfMvYHjaxTEUj
hFrHPrFQpNBJZreZrqP9Vt4HqwvGFayvHLqZOGUWknI4kCJkZ45GSCOq9ivTYW3iY4ns0rG3P3ia
WpwKzchXS3khG6FtfG5VWbQ26CsA16GY+TL6sPQmZxQ6g6iL65LSfKf19XOlz+jgH1u2ToWDmkwy
zfkz64rdL+Gil0Oz6X3XbnNYkHR2MwrLnw/9gBBk97/7M9sRrfckckwSdmsnuIN3zmj4CvvNrV8v
vwv0dbtw6WUncp8TJPh2JtiWJ+DLUfv42mYjolg+z7xlBBr4BXX7KRu1pI7xKN7CSwTrkxHdcTlS
vdYgIda5IZmNN/03QdvgxN/NgLkKLCBOPIdf2hM+HZK2d8Dlf8EBBVYWKIy0y8G4c8OKgbY2W7iw
+nymMi8kd5GX4hFrlA2kXVUbq+oeRHICimknmkAlvmm9/OUVvqXOZw1pLm1zz8fFw3z64eC2SgeW
3mqckBtTkyH4zVe7isjDWDe9ZeSYQhIMfNiJl/j2EVQsFHHoZl82hGfnDPV0kkdctbiQ7xyYeIZA
u05SbL9t5Z/q140WI/CGbR7HPsq8h82aML2PuTj/acO4nM+5fwtMCBOM53S0riOlxKNQKjf6KYzy
+raoJFrHZMJe8MzQBFxFDE845gLF1TrC8nE1GHM9yCWSqaJmv+EX4+sJhVxV7EytHtKuNCJ5N5CO
X0RD7wsN9VWs2EkP7BT07GlUlwBVZFhEaG+FBL2EKah6/AVkJeeeiEYuyt42ObaVvGt/hE7HdYz5
CaoXek+ZlPCV6/UOeh2uj9Vmz62ub39SnPHOgDbhYQpqMdhNQ6xgJ9yveccbd/nlwkvXUCPp6X3e
ln86TjILPA4v2RONq5LoFZWTRfIA1uKFOAOhCJEhsIUpRAdQRtxCN5nE7Pb7lDb8QM4IdtQM2CYe
W4QlhCmQr9HeSsAcZijzfupUaVhrH7aKMZnJ82/uOR/dNDgO4l/fSUu9w/q15ckduhEAZl0wCj1o
Sk75KKpLA8tC7EG+JiYcgN11tbxWO/RCkLjL7INus1fcabd0h2PCsEgaKlPA8et+GeEE7eqq+atj
Mk4bmqAS8VGPqdvSOx+g/UjFOcN+NgjEr2LMYXkUre8vtJbLEjOeGuruT2k0OIIoH3KFKBcuBphR
038QJlwt3bqd/KaEyuby1ohKvTOjND37IwR1YXBL0WC7n5DCPi0Za3eoOZWTkMEFslUM/wbbvPjG
yppePx51HUwEPg1Jlmaq7YXmTm0CUs+Zb7OlpVmY5qkzbX/qaNVtXnthF2/twFs+ANePDn/H94sc
xLpHHVEenEhuO0V1vLFZsC66Oi2Smft1YKVqGB5F5XM/b85ZBtQenRyUGAeL7htWzjJN9itF2o3t
xyyaIMRlW2mO67ZCReJVra1nYDO05BGr82iub4aoA7OZUxiQ8XdBIAobLjA4YFzkS27Wz7FvEijd
F+J82Np3dqPfsneHLnHVZ45TEed5GxO3rX++Vyed9ihc3Zf4OOqCeHnhyOE17afRVZmS2tP9R8PN
6cD9jTqbPK76HORNw2Rj5mt4J+LIVLAE61zYHaef+elQiF+fx/+LQ9A5+7z/OLh5Tgfz6a/APoO4
JAzOLblJ/pwZUI32PCADcRd4u/bFAHqej+xVbLlkc0aEWJi+18HlT+Fgd3Ptq6p7aCIt6sLmVRjQ
uN+htpnpe1gTezVA5M8gGg2aIIVXq5i9qeIO1dsOY0yEN4aU/dhhoUgvakygE1IkDz6UEGjkVjE2
FHdZb5LcQBxpmlW68Fzw2B1P+WiCoeVj5CjiLOVerOiKdR8x8BA63tShg512PBKuLaGB1VLJU11K
WlGrWtWqA2GexNxpABiBsnGnYGE2CgU8DvT7R2Mz6p4cmqVc9slaBAjvTa15Qsnuov3E8HjNdXfK
pHiWOrMaMuOOMVmgKn/0tPnZ0iK8RNyrysdZSOqyLMHCQMoqI0vcTTuM2CjNsZL5h/Q2SB7OZMdR
CqsJ5hX2/AETn8gfSe9YxlhraTiHmmSHqrqmF6/AXmBNesD2qfAqyPxx3S1eWMqwtIojBLsDNz5n
6JVzrYIFu0I4f+iGuHwsi9dNxm03o6bbibqDxcfFwglSe6+Sx7pSNhDva42pC9r7gJvF+2Jva9Eg
e7Wl2aB8B9WHlpor4HKFMr3mKJGF9SQ+ICZ8t+dfUwXAYDgd6KGyIxlCx/FNqZ5D05Da9i4i1Lrh
8Ix0v3peHAr7iQS6A9dzC+stSsossTaACCqoJXLXZGfLHJzwxnbN4EHeYgEJHpH/Nff/gUEqZHmU
10xPOhg+CNvqDoANGUj86yaoJ9jED+lXLUy3rwVw8JdbI+dmUX9sTVZcgDR551Wox5GxrAMThq8b
EJd5pu6Z0DTxGtdngguSSr8xjIw8deVaSF7/msrTloTU7efbN+x4fZxPiqEKbu2DLG/G/xLyXHwE
KtYId/pQVjJV4XbKXIAxTNq1DWwdsJU97pWuQs+R8+/fU2k0nQw1oJHDDAKqwC/UEAKhDi8XpZVF
ijInWqmks2M88l0af5IF29RmA9pIqC6elyLb7Su/bhpX9DgGKSgf41GFdrLspC8kety915xOAPDF
A6/qsF3Sg9y8eAiaXXx6edYrVGQj2dTfLB/bfrK0awZyR/mcNGrA6fTA53LZxcFmxf63YZDlJmZQ
92syG8E9eYMZ/HBuOepJCNmjpwq/WrCgCuu+6fEi+rk/doQ5eNLJTJ6i4KiRTzZygBix+Mt734WK
eV30Dq8+mUszuwxMdTdgM2+DpTX6g49q7jFegbRUjGffaW4Q8qHqeVrm9eYKjKinUzcQf6XGCSN0
+jS3zSy12ZrFDzvF/jC4QgnCW5LIUFe21B+3aKxHLHpI2K14EY6ibjzdRTteqz4Asil0aZs+vVDc
DMSfHwJgRAZNBdzXClzdKcK2sli1Tw8aUkPz/XoVHoBwAQmBtV1hVAYjUNpEkHSzbvg7cin0ekRg
dqgrQnJx2wPUzAoRJHsFzU1fF23hWLZ3MHwzZpd+WnSktfLA6RW0CmiarxC0PXYNOhoK1KIoo8nm
gG8KWk3k87peeop8jMKmideMo+FNBfmPLSrI03rdswOU2QqtH4lSlqlFa+oqveY8lygTEewLFX8K
Qtg5tm9rwZpdTtcCAW/DGT7AbJxo2XGGCm6+DnLA2HXNteqjjbwsPmD1WClrcoNkOm2ebrWLYecS
zKAZ5sP3V73gWi0VQ7lX6g2gClvj90Hc8zWC6cjBIFGc5LTe5lhs3Ds1DzXzkrrUnraWlxyRB3zR
YZtdpUXQ93jhbTI3jMzCYW14/tgidPDrIvQKgawycvyXjMUE4s3V7W1Gi+r+gVodT7UO8V2yrwLy
6K1U/JPDB/v+GmauR38m0XX9hZ1mWQGl1Db5JL0J9Vc3Q/eqyRjJ4KblTBr2GoUym36jKfU0YcHi
e/MLQqbls+q6FrjfB2VeWzsF7exhK3WHplLeOJOfysxNXjUaipnUk1UMepg0kkAjIMNtqRyIIRK/
Tdd49xM3HxhnK/RuydlIHImblBS8Icl+VjWBj/Z0m/HWc6Osp+L+4SoUnzkG7pGnTwcy7WzhIo6K
+zhtWUwh6FRq93172oqUmr+KiBQn4qX7VfFpg5EDCSRQ7aDUjkdtXdbskF2bjF02jY2ljIHymzgA
NQe+S5heT52WfrCvDYK6/eiPTMEsM8Tj9qRW2z4Lvsc1em6MEKJyowkgYWrsuTyQffmdGdzut3yL
oHwY+zzQFuh6jCrOfF3zF0SWq66zKKUPw+hCE6PgQkB6I/iQz0Jhdie5jDVFjIceJhEsU0SA2v9U
UKfFI9q2WID/ufkjB8fdZce5uoFJhX+VlorDPntvm8IDhgn4l/o3OV5IO3YuOOt0LAjxYeEf69Ys
b1UJwgNmp+oqWu9+GrPwacsNLvEPfvlCX/BkmTx3//OHISCXXBtjzBcVwDvv3fIq/05qWU6iYa0i
wCl/TqewLCCscDYhzeh3S+vCsmc8NqJmF8W9QW7u0TzyVd8yAasqZ1JIYxpIbEk8d7wyZgSXWQ1T
KJzn7En24MJRQRzYoW1wlsFtYfuTGaPklALyQuSEOt5zOvwRq+iJvmKSiZy+rnGdLAO/kAOrApnB
bAv8QO1LlmU3rYyVPonXKPoYDgN3iBZoI4i45zvJhmqo0unpcVgjMXioBr9xNwhFEpiq+0RsspG2
7Z8YMPdqHSBbTK5MA4/9DXw7hUC7gIWL/PwhA8w8aW9s3yqLTa7HDdcTL/f9at+xZ0FOMB08i3nE
HOA02gJ//1B6RmsLgV5bcXGRz+vquvxsyrB5/2MsSM5ywWCdiupai08S+M6IOHAHDks5K9+lrj5d
6ZYcbKB4m7WyJgd4EE1aUQGy3xn3LGndIxcRaLJDM2J+Wx7e1ROHuVJ+OIW+4WYIVXC+xtFdFS9n
ZEIzVrYFKPC8z+KbEPZ02j4fnqd9/JQCD7KmdCJzxWlvL+YZD4/DjRuOSPLVO6EQtrkS/6GCNWvs
KnaH5aSaE7LF9ZNVijY0JiNXxLGHOMaZ7pBMGCekkrzaC/g5UJ7Lt9XMrb+NNPJ8/gsuubZUz+Vp
Oobv8W5u3i7FS+N4TuzPzrM9ktrUl0p2FADMvs5E48F3h0ehnnFX0Q2EdBFPcEbIrFBCbeisN9qh
anbg+o38BqtTE1HfpmN14iw6EQzg6Mj0/wTro89z/vtYBNQ7sRMqqGQL/UsyicfIS+qgnwb6BUzl
Ktd4ccAo2bN6BN60FInWEG+LWMGrzmE/rF225wMPCqN6ifmQENyXKThY/2wPMkxpxJunX41K6ACb
tVx4hSHie411ARkYHxpcN3ssw+NMyV0+J8nYcbTcogKJGkgNykXDuh/yMhaGc6uk5pT4VOJlkq/z
bpdAjaTcDPmygNjjy6FRnTUjZ1OTT/AAAUVrWdT5+vc0e+yeDvhcugFFRkp4vnPEanGV+c/3Hhs3
W7cJaRBW0R7Hl62ozUIhzr4/XXVh07AIA/yP1Z1an+KaFCLnpl/u4AYHjUxLo09V4hZi2Jd0lEhX
L7Rt+V9+77houamRAFtQS5qLHKdcVTTxlqBb7JLgEM/XJrm/5U/nhyjlH8UTi5mSFSaNvSpEUNia
ssslENZ1q1Y7AnrNw3uZZJIvElZi2lP421yK0SVWy4GyUOiaBw9ouUSwuD4TRc57GTsSA/zk9kVX
48eQ0wFq036s1yBzX/0Mx2zRv1heZt9SnlstSJRrcrLMH7sUPdKU9OtHGHapjh95AQBskbHNhsic
4GkxwRD3+JdnUN/zQ/rLQTmLv+TuaiU2qk0Xljej499aBD679ghfJEX9HI0pe3F5m0Wys5UrsTIV
+XN0K4ZTu4jdxnGzVY7IqHm+TsWwjdtbmwK6IOsrdmHgj+6jCfkDuzm3R8X1YZS7U/BwS4CwwJX3
sUs3xAQLCtBFYKAWz5L6s3T0aCOPdMkF/qS4yo5I0aUBvczlwoka0npBR3RnneAyZOt4CNg1qVA1
ruG7/WV0KSAYRptkWIwvBAYnpKbpNB0GyW1DAuyhrU1z3bpaJUkr44CKlNqbff89cTULVg+S+ukF
0fOoilV0UqX3MlcEJcAFExqfvEd6YZwB4HeaDc/9xrw4pHTohaQTK6dzIPFvbFssj2WLL4upaFHG
oNvvGxeqHm6p75yH+AiH2GUeL1mHkYNn1nwoWKalhW7AYQpJc4qPOS/OcrzrCOyZA1XdZy44x3Pl
/FTJrN1Q7xuhJsMd8MyD9vMNLPkzFAQlIIMT3WFSGURqTojE5ZQ3vMkBVdd7otckJaX5xPIDHNiZ
eIjuT21SkbjtA9jPDgRUXx6xDwj7Ofl85wapHLvIAnRwnGCVu09Tw1M/yrBwt4uPlpsP77dSjHbS
LsaERX7J9BzqbHAfOs8pVrz8sueGjgKmxatoXufmPysQMm5siduHzoJ7W6mAxjgKyusnoOdHdoZT
XIG7C2D8IgdTHI/njcURKG3h0WB/MolHpeZpvmhNMpfnOBU8y76+kfdRgHC/sRREbhfUzfbbzO8m
GTHicFYA2j136yBPGvgEI8QvG4cdMKgNku3dV9NAWAdg4FfJOuZOlD/jdqCPk8Zo/N6qeZKCAaBt
pOjQQearWyDtEKo33YEwiTccGSy4QpOum8hp0Mf2mcgX7j2r1LRJcuYKJYn+24U72FqGhIwHjGDG
MYa48cwfqvNBqonQQ+c44gjZvF0a5fXSF9r49O8voSvwk7MPIf75CcX+tFdeiDnZstA/sVnAtDrT
c/PglMUNnEf1PwGgPlrJjmjuNgNVpcq7AiSqRvaOxb1sYnyCnZUWMe4GEe+eo1ce/n4SXtrZYL8y
bR2Bs5trBvAzJ2+1jTiaAoYhEdgIa0mVj0lml6vDyXd1NdWFkm4ibKuChF4A+tvDLV3i5yi8vLNE
l3IcvQ1Ur3FHRBrd5y+H/5wwjwt240lnSt8/MfHDtJ7cGxpeBxCKwycraCV0iSGRf9sBTB9DhBDX
4RihQoEjyZtjCTJcYD+yjicg7mZgBKwc/EsjiyBBuvBK9jJRAoOrKDaeY6Pseix1GPxqNVbKH72J
GNr+xCr0WGYOpiojx0JI7mW8WTOZSHGL3LYyFivgclqRhH7LhQmuX7OGFN9zzJh0qbWfQRpqiwL9
w1J6w9gmPolHEctXGLc2ib42Svf5rtpNw0Xn5hfYFTBZ+dbHKl8j3RDmgVxIckVx5BJuB2bl7tVK
UH8iR68xubzysFsoXmTerCUSJrlQxPq+F4nKPLHwBlcx9tfvWen10o/ua6lHmYzm5k2MHgSY1Fsx
ulm/BeYUCQpHE3aDc8/cvn2YB6mcik5PSgIQVWpoWxBLNGyat/VEEpditZGMOhV1J6K1+iXbyMM9
KTa/MZCJSeQtEYjYWfp6i6PcufqmHwdwoEC03z3ffF6SHCNHYb3pmt/dYFvGkpEcHMBKAwMwqPtt
U/OJ8ZamQcdVall9VMEoYjK0O88/YtEB+R1VS+HR59hR2ne4vWhsBJUpKKq1mjlbnNeaBDU9rx/F
MGBjKMGlzzJD/Y86yX7nLkqurdrNHshj/Gk4ZKuFR0l/27qWxOs6+rMeslXLUqxMaoU34rqHbDiF
56f5M+lnn7cXRIOFlAF23yDDqb2LsSGb0dU0mH7qAW7nImBEVkTKSpcqrvzYhTg59UUMEFvaTEBS
d08RPBrUXkTNS+ZUX6xOyeWA7yTodRoNPcrvDAc++7wSynAI0jDGvSrzRRDv0DwR6GxPkAPI5PaG
V9PRpkuHtdL7DoyWkuhRsnn2ytCqfGK+gG+A8hHzgAeNwaNMoueaftXBXlu8GXk8yD3ujbYDGWJ3
pSq181m1RECZ0ttj1Dhutw05/DmJYqlY1SV+gir5lk84wjpLo+h6aj+PddXDxHLVWIu0yzRVVCI4
kIkMnUkuuVLOypSf5SxG1pJwtBfZgcWMXb8EQFf2xP/nJK/a5DeTZzzrTczaRDsKDSoHk31Wq0gx
W7XO2fIduuysgzRpIVbX6lo/YfHOSYMRdgPDD58JxD6a3XMutltN5fGX1Gm2tvIcYBg/5OfIlHwh
GESkxdP0lLupFje9Kcsvc58fo3opES5Qf7kLmS2oK4R9wVn9wpyw77bkkLwjljeXA1flYWuZJoxA
AXFUTBF4pM8A4ZnO8FAmGrdVQkn6xgsxq2HFAcwV1y7g6e9oQUp7k2OnMJRoZA32wY6tJxxkSfAL
4HEa+iqqskdNWmhMDZ6dKyLZjMpru6qQkGe/+rZjl2aJEgc1C12AmOoi5+bcuFzr9RQP2Wt4mKWN
5SlUpY/d1/bqtU859C6xIZX0YaMT5ayg0KJI+0BV6v7NwFJnmGw2kE0LsArB+ia5fLQQNxpCBMCj
RHRaIiWd/X1+yRz1xHriHsBoO4nNZFPumYbCA5BIpWveHVWY0BSXuAWS9tRTcDfp6Nv4UicisQlA
hRGEU4udXPyfPorwOeuU1NT2vKop+RFHEZoHMa45g3iHgpBQtdFWqmiGZ85FWYoPKJQzjltEWuSr
Qw0H5LLH9auRm1da9Jyld+7JCXrpbIuVfAwIY76QbUqZKu408MCLxX9quha0bSjMI7Uc+NRg5IQ8
wzSTY/pOgiVQb6VnM8oVPdeY2v1fV4L/UI7Bj5Y/7v09ML8K+zW6JTs6/dwRCzqtPbSEc5A0ubz/
VcLIBrgQ+5cqULFmavNKSkLgkHUkp9GxIXeP0esOcZZuBzIKVV6fu0yYS5D7CXNgvEIFqMDpZzkV
6Q0q6cd4ABcxpyNseUA9S3GgN93QRZXbemozhLkOrhwh353sbDwTgk8gyI3XurkNq+aJnJCbyFZt
HDPPFhsoQxJe/P/xsls0uf/F87S7tnAndFUdhCP9KsO24FbNk1c6en8D5PBMlqSiDBjpLTmdXjtC
+YiWy/p+CzTeuInx1Y5KWKNzanEqHGaUDIbzxdUT4Y2DZxxHvGlNF9zbwBndwqAZV0MdaWQlwZBz
W9GWP+o6ji5FHUpBiV6mh9W3sWpHjUxXA9O9K9HtTx6CyKUuG60yC0xAuqBx8Q8Z3vVD8wFtlrvX
J0gO9hamiQwUtCaMGiftCprlNRW0yJLzFOSGP4jJXc5lfJrsC1skb/L6QT/No3CUIN1ymYgpKFAE
mHRNYOF13i/riacrEK5QkHyooEg07BNkxgMWpPatZhmS4vw9dAXsPaAGy24kB/LO6EEtwy9zqztB
F1O9zzVWNlo3rEAfO8m47KsFbjBBM1U5OweMo6VaZalbeWPQZo5cDkcKW0v+S4rSutxqtkvW1NmD
MaKAa45+LYefxg2dWgyg3k00IZFldk84aZCGxkX4mQFtHw/71c8mko5knhgWxAkFG9mQdlGJZb6+
T0KJLawjG+nmvUEhgAhRf/PTOfEAS2Vv0rn7zOtabOEiv1GXEbH1x0Vvgh/E/BNmRZON7XZe08qx
Muymlo+sR9b5Ltanuo7Y1FJteNFaYyzC4OElnaNCOVDCShtFRNOJ3p5WjWkICm+ocgpK1Q+czOom
AetFz9KjstVVg1s2l5yPRAckAFqzgBWba5MLAChrrWWDtdEmVVWyrrd4tINSxDVDmymATgTAz22j
x4n0aChv0GolSo00VpGc7HewfSczTOsZXPN8xEPJLiCnp8QgFl1eWJYbR0MuCyEOzSmsjpNlLtai
dg7b4oaP1S4S5ioCq6oc83BzHpg4QQb/V4llHGf+6iSMOBWECn4cnJeXxDooKsdpV2qTuXf6qblZ
Rc3IujScEbnaT+z+2P2TEK10RuhYqyEQu2LqU3/pXNsHuoFcGzU5SLfk1FpfXtZrMX5ASp0HW6M1
gwlGdeQUw5a46oG5QHySlNswaymvPOK3tI4+9CHyqdyrFgjeK+HOGLLUnMPNCboolTqhI/MHGqxd
/GUcBHNPdsKrF+G2BVKXRQ8B1tRfKSdCu745XJj/zspSZMGuM7oblaUcK0mWUeYKsGg0iE3MMXf3
k21szBihDg8WauOOxL27wYQLNgrWotkprlkhz8tzgZLyoEiZbw/+PAYjglzAVtTLrUhsyrbZz3e8
jl2Ty4SJUEoO13NiJ0wieDzqA83gmqQVsNj6fqNHV0u+o9kxGst8Ld8GmZqfqmCtwG1x+MEytspB
AMvsWLvLRZo68ST3aEvqgRdNlAnh56GmNfU4jUyHKNQwofVqZ4FhWfiXMyRtgIvQc1G1Q/WAkGpo
y7N9AQyU7pOEAMzJ5c/IX2nOsLMCiZsRZ6gQ4Sk2RzYYWkm1jJQ6I/iZPqXIAN4A7xyHWf7OETUT
fK/SFZBaLP+J84ML/+Blover9uFQn2/IE2ls6j9Xsd7UKoiH09BsJ1nhk078YFU8H+JCS3H15zdR
MZI+NuaU99JI/qKZqvqApDEjXKo9T0zLPOR0GuZvNIqJLGt6fZ079K8rwrXu2wvsYISjiUBamiST
M9toIzameB+krFC306EUScM3XmNTa/H9W0BWR4PT7PYy9MqbRuI1yf7xNBhqw/2FY+S8HFi8Nci5
w4fi1IBd1ef6J2zZbHO8hi0dylJkj3djsH6COQkeEy0kd5UkbxZ1SUgpn7oj5Aunwwcv9eIJkpdg
msOP8aOlrrC3odpnwFiF5H2KByZX4xLmKHo3cfMPnqC9X8GF9odVR7tBCEuvLRRMy9pGPXsFxo7w
CjFuCimHAs+rdvpkAojetKlLVsGdPBmbxakEwQL6wR6Ox1shvrthUgjoP3tup3jyTUKn8OCnFErM
haQEtEx4oloXzfryidS1UCya0oX1cn+NJ19B98UCe78GEo/Mls/2AOjWh4nK1PeZXY60czVye8Ng
zRRQ/ujq+00395e+IXh4VwAld/x0/CTaHtv/ploZPqlowxifie/xz5j3PW/lTr+gjtowyA5woRHr
BnXcZzf/90hsFbxR6KYlrKd6y6xi+0JnAF2ytK6BTBQ5KDnAioyHtfWmgJrz56cHVC2ZqKNPoZ0l
1A6q1C3b2qqpZc6HbTD2DLm6d4uBYwUWoRIVtqVDMshP2iTIFlp47DTuwh81tqC5t6EgbrAr6Dvf
As4dkIqwkZPT9R79IpT8oGpeLLSKEoVZlQ2XOFwz+t6niG9tCwS25egOxq3fOux3ZcqbwsgTzhDz
Bx4gb72Ezjet2hltNfrPN+hFb5J6Ls4PXcdCiIFz13b9MdYXl+sxmQWNdjfbNjDepv9kJYYss822
GPEEWF4ptQP7bu58hGbX5wVRQl2bWOW6WMGGhFyyjhbnyL3clPLifQVgO7wkCsU8SPYQ5Co3QaY2
6xSjR9j34yvNEH6dB96W9+4lW3Ik3HEV5RFUGoNMza5S3FC3C4lLdJ8dFtS5VCkCc2QcYwn+1Lgb
F1vlfi7RoYUyoyBOVAX6PkXnLd14B0gAeBhjJ5CyPAXoLjB2Ql1xj6dww4/VeQdKjhzcHDrYeCd3
5EbMx5wvXSLOzTq9MDDxj+8NAlB2+IVz1mLmfnLbeJt0KSu6AFmb0jR+rCxBrfb/PDnaqfts1/m/
VDXM1yk/gMjkaggX8o8SoMXHesEhGJSWRMIUNJXaBAeVWAz88+K9vlUHsgGQFlS2Sbjhn0cGhVlw
/S2SfsXxbx9e2nQnNzh4c8YR9V03tfuB5igawuNOVuaHRnGAtZ50FjyXk19dvEnlGhqJxR7DLcbn
SQyrgUisuKiDnWGDfyZ3nSf5huAtwcKHKe3JJXaOsldu09L6KujAlFghIEgamxfBAytP7ZHWOCIV
amj0gcOb1aNAdni4DdCVGRvymfD31q+E72NpXg/LLixT/adypVjlT9NsKSkQax7RkMeDqIplA6zo
r1ZNXU8y2Vk4B5S23NOShl28yewE2Tcot7MOsa41T+aS1+dqAw4S2v+c5U+mMxMRsp98AWDMbQHw
IfPrONzNPPMDz7Dg2w2JIWnrCgWzo6bC98jTYun+1g5Jn4tqcm/jiUrqUvGqwAKJLU1t+UXf0ONq
+vGLSo05rF8sFTENbjP7Y3+pvK3SCGxuJgICRm+IAfBdoWOlenV+XLsMpum1Q91V7yfv/tUoZPbO
lHJMOIrKiVdgm3yhiMgaL+rt2GRkqCKqoaFAEpJLIx1m8yQuE+k1n28odmduSYb7cEmQuk6YNLvD
N3z7NvDC2M+52S3Keyy9ADMygmaPVH0Pt26OXmRtECwOgVcsB8O8mFN/HszzkNUPUUxUvgNS22DR
ViOMQUvM7Lu9OHdAumNTqhwnmCFjAUwXSCbfiRRXnd1/L/pwAPZp13JwpQ0hiAySL9r0PSDc4wOs
cSb9J4GvpfA7pfKMrJVOHxSK2atZ7zkSSpuCUDt9wL7hkIKifrAKlNmNYUScAGgwRNyQGweesUnX
EWfgsy6qUnxS8cTRoaU/RpmH3zntn1s0Ut6a4zDp6SIvwaiHb7hw6dinFB2PCt4+8euMYAzreq9U
oJ6IDT/CqE9SvNebfylrOeoJkuEwYzmXA8LUB0F8Dmxwh/um5L97ONic1LfZJtYzDYJCZN9oFWmY
MSEXnG1rVx1D1MWWc3b+wgeXxSVmyCDeXkbGhVZvpvdmGzHUQdQUkEOgJaelEGHwKUftvNnfPnfW
SiQ8XmYAg0qKViBHOUGghvu1oIfs7CNWntZBjNYxNZEhKo7kBCINvSaRhp/7VCMtUyica0LMAJKT
jpkAgQW/KCcLu2rbKYh2F4VMlPWG2XB8sfUXaf+7ceWRLIS546HLDIgLkF16kjE84PqUvSZL8cni
g0bA/BoRZ6tKlqFu7BLEfmoZUkEnjD1qg4hzJ914nQ3wjDrUHYNLetX5TtgydRlHnQa11faPDfL3
8af9nuLSc8Ifh1+HrgC0cWl67uL/t0t+mTt/1K+EKetSg6XMAo/OvXlmH3Kit5b4j6d5QjUgjlz6
uwZuJfHfOT3Ri7owF+S9Zy5ecZTlrI8vNo//59CrTT3O163NsxVZStXPq4KsOmDbfnBDrfVp4XIo
5Fiujxi4d45V8nVJAjig3X9Wx5FJOC5oG8NFCmKEhZINXfwaJo3DJ7Ox65NALNwo8zEWueZv0kpT
mzMYK7yg0eZ/xGlqV0A5qcMcs6rqWngpHSNBIXQshe5Nn4Ha4g9nGqYOg7qnQ1uR9gGcrpqQq6rg
LRmKIY9jmyrNXLZCVndg47r/zHXtQo6t/4aWMuRZPGn6M2ZgfR7ZZPzUePpSc7CF9O1XArvPvzNn
mboi9b+gQRc3jcn66enyidaTyHYCEtg2P73TmKrEsP7OriCRqFsKL+UfrSBm4oKE5qgCVpW7dlWG
vsHr3O68SDc/u/Ju8/cPyu5qsEwPwklc+5n2KdSPnAVmRSU2aoIwrhYyJSKdf4sey078V/syib3p
X/j904WlOsMLHt410DQqJolm1cOXPA8eBOzInbsZNZzc20ULCtuWK/72SGtTR9QTlhcp4+ieDSq7
UDtFDhG0QyqMv+sc83Ds8cCq1LdJtBtJbGbRx/60GLnFFb0YxmoGRgMAKcMW7HHdFdBu1VxSo6UG
v6VU4jAQfqAyA9CPKbzfPnwniMmH0DbWdqHCzuG7bA+kCoF3n84csbjqITbwSwCI9pt30jDksigf
+v8OPbvCy5tgbRxJrIMZnG1/3PdI6TtxgnVZ6pf9dW4KKzv3+TzXSGoe3t1/l65gCuuZN6xYkyUm
9G6cVHZXCJJjfbQ9FDBfT9wsjLmrxXmsbxokItMo/MJsjG4/B8mlZUBeADKb4mexgMSBIa1ZCEGY
yRoR9g5g+ZpN8YxoKelD06hgcXvI6hohm6hSpAG6frJplCXNozsp+oYQxINdgHqBhvpfLve33V8F
WghzueYSbc+NvY5k+OWhjjzn1o+p+hs7A20vm0iZdQVg5ZV4PnblUiROqoqnCQoTeq8jo+DHPeHj
HBRYJGHaTJQZr4aHgT7A/M6ngVaeveOufDT7zkHWzXAO5O1bg/+k5MJmmggVDPZaUdTaooHk3F1k
dThNbfSWPkvJjuD4C3u/K8qjTAtCL7hnIoHJ1swA7jur6UCmebA8vq01bljFLmg4qttfyJtAOPX5
echmCu+Vb17AVlBcuuCmxTR6t6oxYbvr/JEfK6VnYbScS81sGgnnWAQ1mH9MZNePpOtIqyqEUScT
PCGWBwAQkNPcCOL5Gir7N48k4WZrWwm6sVLU8zamPFqX2lGI3zFVou6UMEK11CJcopA2YLJL+asK
SidfuuMQWGHsK3o3+NzH1/NTPTuAbsI71KJIgLHXAmBq5/KuHGtCb+MFSVPjdNwA7iagXWMza2We
ySt+YJnwMnKxZcPe5W0HXZHGOMBOf+sCsE4+A4vzBMQk8pkGpoeaT/Xc+ma4cGuO3HxIYNYPNh0I
cAUFBNN4ZKnSYajnS8YQrMIiNWxXjEI86n3sJjOhIlbPPUfPIsEmlzph3rAsVwbVtCEOb3rAfatX
oY3VbUr3vogUR+NMVSY4RbVhrIC90nqyPj47rCAZWUxJbyQ6pux8oqyvRGDbNVqKG1Lq0t0Btq/E
JsUKqPzsbDt3jkwox1Tu7/jc09dHOkOo0ZUtDlILh1rA4JtA6XlV20rsJyBH6ghQyiIG+VhPkviT
LmAKavPRiFSbb2/JV9JwuK0PXcr5amct2/CT0kYcujRhdbYNcxrokkJqaK7DPRr0PX2yIGVVxpll
bhMBKF49GdcuLvPuaziP3zmVh7p9SnT4bIJDYDBJzn5XnwTgNF8DEKUpTlvRyK5b6O20XUgFwOnr
PqEL2uLM8JkQSWVMQoN9dBJ6XlKzhDE6pCWWSUoir+dXiZnZpsvf5PWHMvVdMo4vDOw1DZgo1LoW
8R6OuWpMFfV3ea0hMO7Lqwwgqqn7MYBlveaEvC8DsAEhofaaxemJoLL8rLAUMS25H1Hshz1iz209
TrRXYdInEUobzuAIGKB68eFhjeQpSRUo2Pp5xN3Eq0hAklJp+TwJpc/PA7YA1AHgPdjEVmdfu0Y2
liKCCxEktNJA4UShou4E8/ytGhHnYuzi4SCH3zf/UhkDJ0eOeQMqvt7L4hNpwzKREWZYozGoBdpC
/aEGpHO0Q8QhpydefBzmoposg4p5zGAfKgGZcQVUh4HodB0yEq41aTSzjSgKHo91RPH54xHxgOs5
fjUaMiL0lxlR3aDrIVGik+osQDzF+7Gf/2l/y45yiZxub/GwuiRx8MCfxbAw6DStmFYj5K2Xl99I
EX3KrzuKhrO+PV9MXsRzT4xmOxGi/L4W9UGSDeYZOyomzimHOM/vDbw+X56HBV9aeoQ/oem4ieHc
hwMHXjAmaEAwMh8oTmtSK+Po25CrUulAX8horb2bHw/Codg0zoX0u8KUUWWOI3YEnYxNGSoi929t
xSh79ei008etYbg7ZUZBcvifo9L70x5JtC6SNykvwtWJFpHRlD6D8wKjWGFeSLVLwAXOPmWkgJsJ
uwksK8D1ocB3bNugAKd9PBQq+tXRVpRYiZ+hwg6QKeV1CYkhCoHUC99UcW5OYlPoZ0O7NVKKwQTe
cVkp0EmCTK1Fc8uqnutJmhMSYgZHbR++JF0ovqWqrshwcpws+ysd/nulsqDfm+lUKBLQ//LGy7qZ
FhSh9nmnCqeLM5ZpelqoyF2bRbvBRjNHZOGRtwa8fF4NTxYpaiAAo2ILGa3ciKMkaRXHRQIKB9NW
NTTv0gqVasrn/x1wTI3altt8LUK0edMSEs9lRp5m/9hw3nyYeHPSi94neW8dUlIwYvRAcV5/46e0
KCdiKIlirEQgu7N2D8YlIMSo4LgQTEfqdaNf7RuKojsghpXk01ObATnU0zjNGHBxIgR69pcc5DKz
PULH9Jf2KUN2zDW+mTu9EM+U8QZbJFz9zo5Quc4lNQaGRGLkE6g+X8zjdAXLhiIhwP83y5CmqUrO
EExgRi7HUDzZ4HKz9coRQKigScW8U5oq0Vja3emnP0izuHjS4MFxLrcaTp5jl/w8D4xuPbFGqOwN
a77qBz4f7jY0FmiXanO/jbOIOgBbyfXrcQjL5bSj5PR85Qutx9AbwSmVVYCV4PlttR9HkgW66FXh
kH85Z63Rq4q9sB1ep97kXov4YIdrBaDGmyiF4w0TXVHiZa5/l09jJRcgnIshNkGoDqknBmAkL2oe
MsfTGoEoGjS1thG72ic3ZB18aMKzY4NRsLS29clsuydnNpYP14j8jUekAqP6anX8rsL1dM8dO2V4
K2MJ1O7oi5lYOd2x3caMilZwRkYYviq1RV16DMUX50Q4m17+whHgcPcBe7Ymfgv0NUOsi8mdjc/7
B6sjniepnWZQH1ltAl7ksd4Xnl/Lq8u4abJ+oK5FSqCWR0tiwcB1EGD7RY/Vp8jvMsXBL0ohYEn3
MityYLkbr/ndPj+3XHerZojPEbkO9RY2GAQC8YyZM20lURHezk2ynhUNknEgvBoBcEgG4udEfdVp
dOyAS6ZmvzEHXm4hfyT6le6BiJRKNPoUWc0v6RJLo4hocOwupxzICE0VMD7x/iIATHuGBDBdXQdv
4aUwoKRjBEDUjpfWITdhGOS+6oKk6R00dWy9VdApuUzr0P2xz0y3MIXJPZ/QLchpkzVpWCd7NKOQ
D0hWVR4KeRXePXHnsTrBsXYwpt1V6giVpQh7hjV5RKhR6/8sUt1fsfOdmbK8Vl6PG7MKAGXWp1bC
Ql0USwaTY9Md7ji3MMyAPBkhNQ+w9MP0vjucXGghY0olmB4fG5xfsgKZUoEsJSz8wB+8mSqf4OIA
I1o2tjf/gY6BomU7LAp8Wf7SdU6OItjRgQUWjPLsJO+zVTYiYatmOC9dVl11/i1yly0JO1rOsynn
VO2dO8N+xUUy8jvfVLY/k5WDn3ttzJd0sfC9EQGi2YAN6NIGO0oMBLlUQ3kFk0d5L3dvzNrKgOtw
JdThKLQFE9yuAI8H+sFaBZK6tJ7DBU7v5PZQ+AcF02lsWnxrYuUbfSjZoysQjJ7g1FOqyJCljMAZ
KP3khTWvtHMUBGbR5Hmx+69WlpCel/mOozgkFZj3dzlWF7EpFhYuy4bT1w4ArZwos5DIfzY1sdZN
UnWfrfBS/uBmu/etLWtLFHI0kaNrVDhghUrqMe4Ai130QIy2KF5idsCWvxr7WiTPLbRkejTILr+E
HROqrBnWT55Iku7Hu/08YWwBlqnaQpAwbVdVZeEZ8ThcJq21oEZ9/8BHogT1hHZtRULlLReMxpBd
kPyjlcEzPcDmD7V39m0FWh3cHU6Bu1jfDgWVN1lr+MOVqg0M701XpGLgqccqsDYbCJiMARuXKTfx
CIx/SCeBYN89k7Y+3/S/tQdK29HZgbkHDjnnGIy4XlDwvh1ulpz5A877nvzCbPp0vDBWLQ/Lt7rF
N6QY5ETMDqK4oGk/YZ8o4bvKG1mMS2g7NvRmHCpSGRAYyI6nXR/zFPby8jEKkcXXy4Iszj8DwDkv
9ppPYKovkLlquAM4JQLjcbmYgf/wdhDGqjZXfX8pkgO7tbOvgxTvWXZvPPR3ALi1K5j4qDHSjs38
lekpuOHJ4Pz7V7mLx++Qvezzm0fALwgUSv+JUsZ0RInZoPIJQuk5yMf5btosGHOhMDroqYNtwXLa
DH4u90/dmVluNAr/iRzMtSmVMr/+y1Nu6dQDcZ8AEjAaMimVqeclgJ230QZKuBV//2FhS19mWOUc
04HQ6KYoTS3VjWkaX9KyHHtub2y2UobODPRDJwf5IyQeK8UnZu9ifR4B1Hr//WWT7JE9webrlHl2
diEivhmM4kdI0moiP+AQAElylHxGMZElzlLZk8h+tP3pBhN4bH+Cfwix3p7oNNYURKb8NoUkblV0
Kv3ZOzQiP8tnOgvpkOuJXm2LUllmS5fwiD1btV+tdXo80Zirpmb14q+s6vT/+ZmhkikAt3876N+B
D0Xbm91viQXursjHBAJsgcrCQO9LwVDZeZJ3SjiQBob1BwVfsW3Y41a32q9eTXwkwbrXyrrlqFdx
lF4YduU+n4ckeVQnWehphd5O6tqj81NQMiO1Cdgi1bN+zCtADaACuKGVIJTNVjlBwICiteTAJdOV
ltfLCL9hZxtlEF5SBRcgN8U2zVP6EdEi/QoEfwkh2Nwz/HFzf3wqLzLmR2hkCaVaW4UvYILUD3Ir
Wp5VSy7QQBt40vHCmy+VOed6l7M/DmN28jUKxJZduP6IH1CGxESDGjpsiTcGka26cnyEecCi4a6E
F3MSUMVzFkBbEfAYiQv3nex9ufUPJSqpW6sOdEbXuHwyKvKOkre6kzLqSSgD+yYi2o31KMG+lE9K
XMtMLPGK+QtSUNe2xr7hkQK0TIeJsl/2jXEbyg8GQQz+/osIm4pyrsd8/njuw1czcdGIavTtQ/W8
9UdKaQtjwQLjJ8xBtodQnMChEgS2a1Y6diODzfTGbyd45sBOb1up7aLBzKy/6rYxuv7PuFj7RwUl
gPmvRFT41+Y2NZ6LH01Mt52x7Ymbmcv1YzyFJAFQ3UpjpytEDyaRs9DtnyKexV2DFuMkizeYUjbE
nbgAuDFcKrKZKSEOA12/NF0iQ1L0WH41Um8Ii70V/mARLg+B8YMvBAV04GYw/MKofkckOeN4Elxs
F1YJjjjavqWUpYG3YmSoIembC9bUyVcIBob651FxYkD6xw4/1aCQWOiwYXsUu0cudR1j8DeO98Aj
12GQzLGANHSWHY0ZK8PdCkNWdksB/eWYfiFBoiRrbjAtGyYLILW/1YqpL4nwZO3YplXdJsgS8EZW
JnGt9QzZG2BiycGqxIaWYzwDMyqSTCpXzZpGKUr28Py64Qwu/RXwNaKcX/KsOcwUG/7dPdlfCPy3
MwPN7w3sdmkmh6U6NR1qP2gcZkFtVahpRB4KmsreR0R+ohbmozKiL+oT7KZgRoO5dQIyxrnnKYt+
omsBMFcDoqJnOnyDEIiLl/QbXF1bLQ8PZNmYMEZqn3NUBvRYQVNKi6mB7puZBRWAQ1NFPxEmxKDv
/SBy/j6HzNmNFu22vbg3DBIFJnxoMogJdK57YPVvGMgxiPpjOr4/vXkvvXA5uT3N18a89EYKxAD4
rr+vvgqclgNuCDaDjwZLZxuXsUXaJZskDqfG5Saiw0cvm+ipMjKtu20rbCoXAJSnNHdUKilHItHd
7fWpijYJAX5RFOQ74/9TCcgUw7R5ZZygH6VqVnaQYF8PJcmpjCu0P04z5nYV0u9e7qxIo5NnrpEo
Wjf8HQJ/r3o4+VnzvXZjC6ZLXcExKWxejYad1DUxHr2Ir2J3keflysaFGo0LURVRWwsJ2oEDs6Jf
BWvvq2q+/V7yErcgzPIkojdf/ie4p1wa1NMi+D+u6m1rrQ2NTctzUun48UbE7tvboYsIoLtkoI3B
eG6jQeo1yp/Za3MaB3uinlUQiz5UvfFnCRec8shSlxOz8ykKqMnva3oC8EIKdy4KUAE6fKNYWRhS
CR/VL8gEobimL94N04siKJGS79BHKuAM/wMIR+cHpTEZUsLwvES00YrmaT/WBnCodjjWhJmOPnDT
P7ArNoU2OevpSrvkSznHMjcP9vm5wSI8azGYLJReaxQXdt2ESVA/QQT8oM7OsjSlK+nN8Y3ZNdCN
sFOGGXtsjTVa23Ni6yirSPjLMEcMfG5/JCJGWOhY+YHnlsB+mw51WP55sTZ+P5aZjkZ5hq+97CTD
uewZGXaFbzoY+pofTPXJr+yT/7dYPsOSUj8RStkgRD8H6ekVIRuHnrMS/Ox94Knr0sHO3evhjwja
DF5Jq7ryKfYHZ7BfSwwSXzFSrF1oSuUIh8Uqg9i61Jlaxh0SQlJAvP997yH3X1MAuIMOEzxdYUEj
z+p2mUxHuSfVJbW2DOnfsmRkguFsmA9r0AVaQA6swIhe12jV6exL1CpEfaRbPl/SDk+1FYxWzasm
ZezcbMRZa5uXZuUGEzhA+wDx7ekspEsRlWMSgiXjmzfQQqwl5xDFn0lQrrKNkqUqLSuVqcEx4dxH
/ISm641aQf/GAkNNBvlYPIKIostzVSf/vUYNTIJPbFmFsQnBRfAFyLjQcyw6GS5DW59lkFTl0vEy
DW2DcriWc3os9p05fB5Vf9z7ivrbeaNX+cX0irgc2ONXVMogk6ZhvcowhjJR2T+0RSaqmayF5FLf
0Bc548S86RxBcfa29tiA85FzYUDIAPiZAy/zKOj50N1eXbeKfQBqvZS1mcDHkQvEO5/j9I6r1oYl
dUHeIdh4KPot7d3Pvu+6y+FGwnvIIoeqr0vrPf/satmCETnzLGYvMG91ftblI7MlY/c+kdnqDkwz
MC3GtoOZT6PpqI/XUlSzVCAOoclqjukV6YOz+fJrqAFDxZADdeQkNY2FGSZiXxFNOVpO0D1Qp87T
1Brfb06Hzo/Mzj0SoPRYrCn8zBaDxZ4JG0xBabootuAqAOMkyjJOoSANykCJe47IhQJAkyz/EGcL
0dkgSaj1HZ1PsOJ8Si9XH0+RrjmMHzBmTnx4VJS9/WRWf9ccqURGRYZp7Ht2MSBxuonxG0Ghy4pc
GGxjfzEuSKoA89hZ7pW4BUGfMHFJQC6OReezSwgqxp83H9sUtcQFS7wYSZCxOfVE9nboe7CU/BH5
saS3iq1FXej34eXAq9DOtN92pSKjSUVf0iD68YE9tOGSBDE7pHfQie4HMlIoQOVUq6MTBtAuXUYk
cz++ys7Z4chRAC3E1IxMc1blXKYKCn5B3MssIegOvkO+jpzm2qKmj7ORCeEfFCK4h+K7WQhJp2Xb
d9IDT6teNfvCc8bFbvc6bVBVGnp8yE8fN5WLotM2ir+i2jjImTJ9DIWBb21AhW8rixVCn73gySK4
nhgLBLN8RSLTmrQvB3bueGfHla3BNtcaNvitLInRDd527zGZQegSKXiTiiA/rdoaiee496BiXyJX
Zxvh6CfzGS7G3XIgv7e+FvSu8D7cMbb5ptjbQZ2QXMz7pWu+WzVolPsJIg9l9p+zfGSMJHbQ8k/p
lZPnvlRmC1gfYr/X1z2em7kOXDd3DHlTR2xL95u+1drCHUMj7PVcbYxfAFdKV+TXlxWKztv8sjKO
HBubI+VPHZEeCV0HuDE42J2EH8CULSFbj1HkxwjXVQNbjOT2ArDk8UL4DXhBP1bOyocQas5oTSXb
g2sYC/7z2vA7sCWehV1JuO+U0Tbb5G61463roIqw8r7ys9pj8szJcQqsj8eRMKk/7DV5K8cw96hW
Aokw14+pLXfcGN3AoOx8fXz8c0A+QksJSQwAKi5KWEFN7lQ7ixXj6yubeuV4hDsgN45ZQYH+mWer
g3gQ+O8i2tB/nf7xALOJ8t8CBByzjjRfzE3zzZ71x+M1vXsqdskPl4huYs6mdGRXQsOW7rhm7NOo
v+5jjYLkLKFedlF/ZnOtWeIwjqsK6HPWDCFjv9Dfzj4nLzOqFrlrKnRDFkS5Gd5KvfMd69Aq6lM+
XO+HpQpJBzf+m4DRpr2ZCWV9Sr14TKab5vNdnkq5TahSkqULS/UjNTvZHtSwUkXB3M2XdBA9RixS
vzYi4m7yA9uq3uOtYJFGRycXP9hIjxmjjXWJ/9UA3l8w7ByqY8F5IWqTBQrAFWLOeIKDnLOnq/z7
NFTwxdF00AAJ5OwZFUfjNrorbwDdVv0zXAIWxI2zoNigsCcfAIQ5AlCtgHT9hiRRpOxnnfoyvNg8
NkwDWioJKtBQP26wPYcOQirkokiiItDSpmELc0hg1dURsisVWsv+KsKQHio7qwH4cGJjYUegTDV5
95lXz2BZ9TGhnEStvooGq/pD4BNC3/Z2SO1vN+YaP9D/MYOQwv9pzJyitvPMR2vwFyHhEKNAH/OG
x+TOp+fh15vmE7fM3ozpoiotYzJ2vKIGchLq7gTfPDagpRUcwmDnpNQHaipdxMNMhBigsjdBZiZk
3Bt6eeJy+UFnKBW2YI7WhEQmrIAEZ+nI5yQTcacqFBd5WerYIfzwEK+QW3Zg6lik++7wuoDonicW
YdiW/2LfMEemDT631Rj2Y4iIPy3zzzUkHCoGEf/PurYevrSkw2GtJfC7OpN2pSqzyASZFlLLAaFY
tF1CEWOKMxogZ1u4J9AdAso64ZF8Wh5nQ/DVEkPvKqeWnXM1kwor5JY75okp4hSTRUjuHIe0kdlE
5lEmkPqS6Kv7VPcGFoVNkKxw8/jHEqRnHcJvSblU7vhZkAqxJWSdf/xRtfJjOPtrAO3hPDUcQsh7
SnHeWalYUjvTfMA9Hjl/1ojPts6lR8PHVhA31rNWB7y/LOU7ZAqcGOhH/aH0Tms9O5vx5KAGyRtb
HmiA7vKBMwOLqyJNwa5cLu46YKEGXBZXXPArraLkrgibhd/s+XC6pFAH2vnrrcBniLOlAi7lB7/L
W2FgW2SLU40s+Pq53hC7yPyyQXKPslEvn1jxwCag9NHZMB/q1qVm9o0f3SfeAbauwDSS4ymGbNhQ
FfzTj4AEbB8a1T4UD2kZFczpCNodvfHnxrFeMWqGD4DokXgKl/mRlvYtHQlB5ohYTrz2B/2WbjVk
u8MjjTcktp9jyUort2S636KjpK31l/BjxEdAKMT3avO8jXblUxVLC34Y5F0LzWpPC0QNZkwKttrX
fRy0nMw3oXPDOrwslMbDngxERQ/tBKvk5gHr2NYyKFB5pLMrp9jrvEpCM4DLW+1l8LVpALjnO4XF
k839pP5vwnsyMSa6LM0XGxmOo6r4xkFNGVmssIRJ5HjnXcuZ+iynbGlQva2jPLQkzmc/8FB69lvR
4aQrBOo44023ASZkb2IMSlVQgdo2UCPBqN4iopceXPCOr0n60wl+krRwhwmlgisiixwHpBFyIeKe
SRJ62WTQrsv63n95tyd7DEgTBlS5SBPLL7KyBeUrf8upQrnYkXEmOkx+CHCUpYQM6HjGxw7esMIL
o/0ywacf16JoJQnneBuBLoGcmfrNNqN1ZBAClrQF1TLs+OjJOjLAGKMvFRIWKBmfwKlABzV+iUIY
58ahGQenMwu8FXc69c/gaaBNaSalk3TB3ryqjB1OvFs27D/pLTopC1OGIH80nBPltSXgxaHuneMe
gz0SnjbyhxgskQW6FZFYgMc/jys6wziYOLe7F6g5JY24RGWXdNLKik2zdW8KkOB/g76Ih3PhsCIc
WSUxP68StQoj0Ivws/mqkp5rIacrDbEs6SF3kx0rcK4X9IAEQlZzr/OHSdqdMY8lfSOp1ZmH1VZB
b+OzHpG8XVxpUsyniAli5IKrM8tOxM44Zv5eKXr/Q6onjQl1It1o4LhPlXr5/cXO9etmF0rxGKCJ
K8qbEOAVMjswwC1pZr6HIr/4kc6aA4myEZXiKYsBV3C6LRyvH2NDNTsLGuys74vtJvHTS+xmpwGg
jiqrsUENWH0G5cPYqcNBOtm9oWdWsPpjvCX8/xlX8YDig3UTPY03lbFvO/4w5Fcft/83UkHwtFrE
I7XJFZMwOyCNnssr5CMXPZPycG1Uop6q5bRV0P6NNNLs0IFqGZXpaARX8PbzWxhm8B9enuUWN2ba
C/gLh19Uppapi1RIwe/sMyjAu2A9ynKj8RkeoGrCjMtOQX65lp6MKSc9hcn1XRY4EuH5Y1iWoDtg
p2QakyWfA5c3fI9/7OufdV9S1KDt7ycBxngLbCKTotsKsuqVwE3SIrZ5W2oJNr5rQ/1E4DfWLvin
idRa86AOj5RkGijT1ayaHa0MlxMmbqAbduCw2Em9eJ+EFIjsO1AfLGQBQK0vldy36AdgP9Y6XeDD
ul9JA4YQQAMVLA35cDbFOxDjT7CE0hVQ3hedCpaC/2oUt/0WMJdwjuOv3YmW47xK6C2kPYUP16Ry
Xl+w75fA6NTmwfVhwb06Oii8o+pORDT+fhGSoCcHHYFKTB31qm86ajyT4R39LeAWXIw0rJyNYjPO
NIaCBtqQ8UEjLF6Qj2trqAZe5Pu9MvgZKsoBucPrgt27OYSY5xjefVr5hfC+TRe8H3zYVx3cWnPY
+fkzWLLJPffbJyGNbK4WyaDVpHFOpB00Q7XxSPufR5yXiGKYRSWY7KDoODCNSWXEl04bT8Kh5Zg2
eHnyrsM2+G5tvhGtP0Jy6BCISaUeFhMRNU2+BiHJPAJIDUGnZMeGeUIblhj0QGMge54m+9SxpCpz
+uvFqbFgoxGhHKwKmx1KaDPlUJhg0YrkcGTxil1QbC5nA8QhHC43BiQ39eZRCQu7dyVyKEi406Ld
GMCGqsz6dGsGOmFLuizCSMxhEvw3BTUpKOSl+qOUcvqclGn3mqMNUZpANHeY2hS1N7KQJyccnr6S
PACYL5xDquVVwDVq3swe6Ba+ujB1cvYVRcyoNpUyHJV+W86JhLg5ScWLwB1wX8eSfAvNNzW6lh3K
Dc3jvOejxS3evSFCUNiWI/BNd5fiVyhIzI8K5MGd5Q5YxTPltSEWqdK28EJ4PGdMT7CK2wdWDrDT
6tnFr9ZXZI1ybecdhDLVVMWXRhP9feue33G21kSCyeRq3ZKWvXIZTZNtYye6oY+2zWq3am558+X+
E7wCSC+pVTpaTI5+leewOop8YzpTOq7m5fNYJ9KnZF1AS4BpEZVCbMiKHMs5AoSkOKJRNi8kDEbX
6E3XPej+Sk/nnPfPT6LwN3W7d+nGtPbTrgwlorN5+JwjgrXNvw51PPFISnBbXhD1tUtDQZkuWQol
Z9dbk6T+F06SjOSLpA/BoeEDSf7+APruiV1uulLiZKRzrUy15pG3jhLV/G8bISvfWyV6zQC6KNLJ
e4jPLs/DgJ3p7UzV1pssa5C8SL77fHIECd3O9qO1XlRfyV0ZCeCAi4Ii6insdTZrd7vCy9lfAT+x
QFuLhe+/1kHYBf1l364AcjEkIz3wwazZV44G719ttVACd3kd1gegdBy1jpQSNBDDGsozs1lyfIGy
GT5K4yL1m8XcixX2k4PsaTB0vDxiUy6cjrR4hI+qUlwb7VzZHynm3KBRiwBF1uZjbnLQi58sSaGV
nfMye/JaMKfCRw7ZHBsDVCY7zzmBEErtmQWSWGcyVCqm2rWCA8yTUcNWo3tzTEUDAvLrmVAKptc9
QsiOh5M5xczdp/RaM6/ULpGoM2RPZGn9PfrJPkc8r/OSNwARYkxnmc6wldQQdH1JCBrKu1+UUSNZ
rhiDHeKmdssGp5aLgnfIqXczIO528bpdb26CIB/enf/xwdF/YfIeXdP12X4YahjJVJ3Uxjf2cDCX
Pb+bbCmMAZ7cE9gRyryvPMebNMDPWwsDnMfQO4U1kPIMk0zfBoSfOj0Nu3BNi/Y/hHBaTbCFSr3A
SoJP64ZGOvady4dil+XYysCYIAvlYNC3C37ZpFfUialyBIg24H7uIgLf3a6rRnzf8udb7TPou2AB
G+8ccz8yjl5vw31cK4tpLJEQrIFzYmjmiai9FO/7Lu1ZS8+2PXNpslfCJJqXymcKuOKDWpajoEOz
azEkw+6gA0AM84lr4xbblKqcKbELtkIoqFT9BkgPHhwbEWEOXBFdOg+tMcHL9TOr/runwfm2ZGRn
yA7U11QaHPMbECBCJWk2w0A3XaUp7XSDDoto19oeCZ8vBxJz4yY1uLf+oBNqE2WfZ5gtIheqIBb0
a3DQKhuaoYwNYnwKDboPuaWQfT3xA05wBRSI3mOG6mHruRZOQI6AxGni5mh+U+ZHA8Hwt7pDw8PK
6eLV/f7dnHnaFggOHH8JboHecNMemkXDkNTnS5v5r03Zybyd4wip5qcVxa71kwoSnA4fo40y728m
oeQjMsOHeXzP9r+BSKnayMZz+gQ4Aib/nKUDupaFOTjiL2cK/d7smd2zRexPJ6A1kRmqsYk2vv1T
wFQo5SCrlX8XTmRmR07s6byN1Kd10kt5BztqRR3TlDFS2+9S5s/HTP3ov/6z7CjFH6uEqfCipp3q
iUz80Z9kErHxMzyVAD8+e87Eu4otsV9gK9R4OnwVHjV2YhZhnGXwjqsmmC18PubaZif7tSUVxyFA
TohhJfuD4YQ8Ueg9CGjiCiTbcILpgKN7KrD9PPZYp/mXHXJ7o0wbP24yQNtyBVy9JFG6wYwMHUlQ
de6IyBbc2q62drJ3qrli52/4Snvv1+icGXXpQS7ZZptJ6O8gWjqpA40EuiZfPGrzrrK5p2rTQa4l
/gBe5/yJZKQ0HSdSR8/vq/2YMmczH+cvx8hjyl701ftRC6gax6zkDmW7UV6rzQ8SKnfkQcAUSjm8
JBA4sQYp+Da3qY8o2p2z/PJQsOnxNW6VX+6h5UQuYkM7MHZxwxvMRVhKgaKQ8fCLGiR9elVzXE3w
DXny4wdP/WjHKsdmhLGYjARKWVGo6uzkrbckUy0wFG5BlaK60oRIHXAS08DrQnVbxBajlk6dm8HF
0It+T17owEXR2x8OkFMnFY1VgMcoT++b4y6nUbvcsthlMIetZkjQpdawI+VCyF3lUF9dwnBdhzO5
EUlxLTKyP1fI3UyJ+59+1o8tTREVYtaxjYm16lSHqGb8lV2DAymKcXeohbYhPcy6r3E44LvDVXwF
buMEANDrFRCiiD9Ar1EKWrqXOuNgitIdxuCCl8SqWS8OtXkLca4F5y0+NVwYPKNCUzn8knTYfIsD
1BQErImPxrjNJ1WOEvl/1Ej+YspMQTt9mNJC97ZjlaorgB51cZa4d7C9+w1xFVSJWsul1DsFyoJn
/pcmF6jqIR1E+OMHk3CnDOsGjpNxMlXNWV0TnFafozyJ9/N2RVxmt587z8bLuQRuDdqbyIOWoF7q
qZNroRDgLSF5ZKNCn2VPOhSFqZ3e+tqI2yDy3Pw1Ge+l7mL9ZtwnLb+GMbHZmVK3tAaIJDEOsFA9
IQtO+40tZebJrPiUY9sLfPzQVwSqUxrM1tuNBL4KoBqfJn0mFMeIxgYrE0Vkd95+yZbvc1AERbJB
ouCYMng84dl9LGAzoPWLOFIYBmLOBeTzDcH9u4YWzBxi2TD1/noNw49ylLqcomOXM8eEuJfPsp/q
xtxnCTEY3gXkaxrPNw8WAd/ZFzfRZ6L6R5/6z+M8zUBgJwgAtKdAFuMynAuOJTl3aOHvtLo3WYnL
YzmvtM0mNZtWTZZpy73BSb9FA1i5NfT7gGyiRqHAF5r9CGlhtjz58Xobmp5JsZn3A7yLCM3PlVwD
MVjFISmgaamKl1D+Z13MNdgOdIiCvJs2v32HhtyQjZwwJouT5F9m6gloKKKfrVvtah2jzXL9/74T
5C/hvx+UKhAGhx1GsKrlvwj2t4LjRfE+PkB4qQy/GRuInZ9NLvFBVonaRcOHtW31knZZ5/8oMzfq
bPAK7NKNquKmi7H7Fv0hx+uDvJtrbF9w/481R969Bxx6tH9tkHuENjnSErb8EDHjSRsY799Y6Qqp
B7QxvUlZJnhtI0T4/diW50mPSTZZT0S0mxaFJIm2vJtfwRE7zPHlW702xnHHTkUATRHJthZEDYzO
dZ2QEFHAvmhB2DtMzpKOmAk7PWUFQqbpNH7xjQ/w+EIjg3y8FvAGihDW6Gkhrexhkf4DHlcRfPXF
Zi53/It84MzzdNXMKHpcGh5aqOWAg6Z1Krsf3zg9ucio7W/1F5COzwk9ohK8c665LaUvW4w4wG9T
szKh2xfni3THieP9cV33YW8tTQxmZcps3qebUzeuSEthwObFdm3pWqg3sCwmW1xRMpZMh0xCKh3Z
Zp0boz9diurV34ZnwT1YwUQgh8i/8+DVZBjSyxYtl5BaeXNn+LgdCsLGnTbvKkfuGKbgFdAOUv8w
VpKb9u3rtJagQ3t2wHaTMz4gwfVu0ZyJjiXvOWVaae4uDjXUv5tHykr56fcYa3mjZkv2u06KFH2m
owIBxlFKSgtCQJX/6NkYbtxJZ2RtLUnUsEheTTVi3Q+MJL/3FGW2/MmbhqTIJ/8Ejru5wpnmBj7G
KrYFIYZWN0XZjl44N7qiiI/nVT/T8LiEQ+K2WvzoBWh6QEsgnRVx47J3X4XF+IGa/eXb+vkEAU37
kWOhQygoKHfX+Of/RVfcB7nadQ3ovXngsjMYN6Kou82kqmYktJPP+ollMsgvIZ5wxnVgh8HRLtF0
vd2VgxbD3JGHWHsb/LthNynOHQnZP+h0JEgyYRgALPC079rzAn4YfrJwzYcTUo5EpeATMuWHK6jj
vbTf/xc8bd5ZR8uc4UTYlJYNR9U1XpaxHTlaS/DpsWrNdLt7peNwyVQljg8W6jP20ahMNl3CYHn8
LTWdSGVVOiFeznMo4DDlZFrB7epSctbklcwIl6ae4XpIR6ATEApgMICEJlVfNqfwN90zVozGOcjJ
+yc9OLTO3+GjWG7KsRTC8rr07rgUqgh6HQFZVZuKALrUPVdDOG6GELM671TfeQ34/N8f5CeZKABD
H8IrlKVARVfvFFZRBCoFCI0ziN57u9BKu7Ojwy+BaF4lv8x4kxVCfgGwaiXw/O/+SA0aRttvY5lZ
ISbX1LjX/dyc0FLCfzvsZ3dNW7T4/nZQDr8GKurSHA5rMKR+Q5cFjb79fw6wEwX4oFoZ1RPwRzlT
arRynMEEERc0K66RtuxvU0lOsTh6qWDHC7sihzdyMhHvG/q6i3YN0UpT5+681+lkRbF9fwPEUUUX
wjO6syEvX2yNdF45nTkc0kTTUNNfHYVF7Q5howuHJN82izkwxkDWW6Fxp3FydyD7d9ztm15ppZ1P
bPqIAJDrYHoGCwqWJW1a/9V7dd8a9K61oQ03sTWbsWLoaavWpsopvtSurBC+VwvTZio+J2l98Ib4
jaGxNPEPDj84n08fViqWnpOhtANVNkSzvDc1tSOEwxDOImpVjuEf1fiYgu7L7yok8a39b94o675P
IdT06s+mKgrwig+i/Ey/F15LAfWjCO+fwYZB9/8dpzgIcZTysF5cahmqN5TOXHgh55fPRuRz9sKc
etv658OOBuhGC5j36M2d79rUChLbqfPVPDmPAsjt7VX3gTfgqPA0ArUjlMvuQ6iffHMELK4LCy+1
/SfNt3aBGpQF8mjfVcNwKmaH2n9uEmOMtZFnoOwz1iKoexDbKZU028glz0BcXq0nQctMDrEL92bk
FQ3if7Tqn/WQifZ9jo3G14w3sZaXxn9t3o3dhDJRTlRcyI8a1HwqL9NjqOEk9kOtIhzRzVHXcxGZ
2ecB+OzybVZhQPl74kJ/8uLtgeX2frd1YMe2WhxxMw7rtJc0ZN+KsrmDubkBMJmcX9fNdV22QvdA
bBZPkaA8cqeA3DrSMWzVfGPcyUH/1PqHV0q6aSsvjgrW0XSObrKpFN+YaZG6c9BqDpK6wcysDDd7
N21qwhr+qMzDwKuGdyDQ/evVaS9Bl+hCYSfJ+qi+XAkzkC0OPd43bTGQOwINDwS6e0W3eg1G868D
ReNm3m8+X0VRIh2QCDJjHPrxk/9mD1+YM1CDvsY1yHNcRVfU5JsstwSg/XqrzLIqqXZeirTmJXrU
CN8Do2ArSHNUq9KHFTVhlbVhEOOC6QxM/Q1djZbtdk3c/ALmCQ7R5hna2dUQzl0FsrhYfu1X4VBE
n9wH541KsduA78rS0pOJK0dCSdrS0TDn3h2tLK6pbHi0BMbhak0dMLFSbo9ThIDMUGoEaMDL4nL5
A+tB1mly4XGJZErk7Pu0kmXNKI2PZ0uOwfVaOzVeo0Q3fyYkIJiiH8uXEFOO3KLwdg6yHsZqPo3h
AnjGtFs247fZ2ZMCE7UkZkf8g2kaiYMtrQ44qXQDnPoKzipyFSElfX34YGy3ba9iLqVuL8AxLN4T
BXjUJZzxkof5FO0zUxj9omvVf0/hrcMtn2iy+GBBpjXOj1izhsklhmn3mBYSiFcPf/GJMdA0iCG9
RqAKl2F5CjNGoVT9Qb1Hw3gZ2u+CPZlsXfijSMW3UW0UBh3zCUmlgcdKJhN7qEfIrWsOFpfnm6Se
hHLoQbdc4qkr4wLaBuXfjMHboHu435fOCT1gk6X/DAAIKeUvRWG48W6tmpVsm0ZyyxY1fcW5RKps
uz5BvfLIcpHxbNY1NkpyPjjsrv7h+o5vUfo3tLANHCJthNvjmHG45V9J354aj6K6D2o3tl35hmSh
2E/Hn6gdNB/M7HVCnK7bqh9uRelhYam2u5EXDsTwa77wN8dvkTAdH2R4JUV0LvNYXWc8eCdbJhF3
VEzfr27p1p7dHjTYmLNB0dwwvygZYcai4T+tTF5Bkk+2pgy81w0r9VZ+Ee99osbCDol18xPJI5U+
7OM1So6WwhFUA7avC1wYYagG3r3gcSyve13jtwwlf6rCPpXBgxlAIDkNyd+3tH0K+TF4uCQquCRt
SRbwmjorhKstA1BmuGc8BRy3W+mTIG+Kew09EC0VOySYtQZ4wwtXRP2E/qMBVFUggRRfX4383PcB
UU9Hz/KYpDCA+bF8ZEkvDBo2R4LJI5zSBwmJ5Z9Mgnu7QTIf9XT7KMj+AXoQ6fbHbRRZvRYGbnFz
vNFF/BONmRLGv1oCbx0n4F8SVVtNYSN/5fQ2pQDc4xVpBek3Qd3gzgVys6U7Hz8o3c5wMbV+X46l
IZh0mH3c54Hf0gR7+mSyNIXwprdpAQhiLAcvsq6yedcx7aJmVtzLu63kUue3Y39r8AdOPlyszRBz
PfnZWE2VA4btGeUW/IXESnXIH/9XaOb+l71YNh1ETYx33dprsNAM2ho7Lml9rSAcXIYBxBcoER0o
PIbRCGBU96GD7kMwjdGlnPecl6PD3oFMY0SiWf5f1BeAuJ8kgTNJB0hRfnl50GRG9AcK8JlXbq9b
GEPw7tRqhKVMDv2ojm07TyIX3/1f/rToKdJ6hDShxEurnMb1AcKo2DpDXMQb8YYWmbcVpoZfSEl1
YhDyI2V+GcsKv7/ntzpAOPlFyO2IXAD6vrMXUX0fhLNI469il9sk5cVpGFV/oHuGJAg1eYUXOzLg
ZYoT2zJmOvVhPqy6fD2I+hONekQFD8NkrkdzOOpm0Q9ieeKWdT6u3HMEiCZaYLbPYWYVLouYnZfj
UxbEE9FVdlWBczBqy4YMS+mn49JWg0dFsOKDPAuUjfD5oPlZvNu+2rieVCZt0mo2i+vQXh9MUYDj
R8hqHE3GFYmY5/T4ZQeAFYnZ8vR1eM+0g4mvfZ6hFs9woYW7Y/CYf8YzystLe6pzSnmo3iAh4DUg
iHBg82P4ipX7mQb98TkcMCXnpGmjP1CiOrgnBvRPPVWoBddd9Y4AbSQ2RE+fF5zuKjb7qKT5/e/z
T6Z686wfdt1mBWA/jAP4AdxmOI593VULYu/bPBxrbL3XgcgJa+M9i/tVnsdQsSKsb9JxZ64mhAFB
fMnswpUXJMQQ1krHwJip9qsmoeN1Huh2hmISVObBNTj/60zxLuG3pAU4JsmBvlE2vWBOMAT69u4S
FNyAU2dXSeypvLUv+IdIwy3QXGwfCpMJ0g+prczF9O32aZaSjmIcYcGb9I2uh+iOi0a6vF6jjjju
VTPWpO3tHc7siy9GhfvfOv3QaORvoQJjU4J5IHswm06CbHTOjswhkE5+wU3dGBWbFPA9fSWWhM1p
J8ABqKBUNJWXbeWuEUSXO8cua3qO0iqHPPu0k4SwXtiQlczUL26gWG8pI0DfrHbxsP0owmVALBE9
DoIoSyosLXbml39lmGyobAr21C5NHZCtSh1ew5QPr43qsYe6XV9CQBpYdaW6JjyPKeSAXD3ywKeA
dAy/KGYnL4i938uMIzFgta8iVWTFnDcUjn9o/9IhuDtlHF4RkK3pXztaZG8kxn4Z/m2txUPM3ADC
B913ynSP4dceKJScxHbKXrogoQ5iB2U8X0TU2mPzHwMvjC14MQdscfPDh2tgT1ESuDdg4MQtVepx
EgWVfiqsd31m1ZP4z0zhr+XBN8tZBZ8JBojKzFKkwdfyZ87t30dHnYfZqhs5+w9oE4dATmJhCBiz
WSjnXl6wMJYRmWVBD6i4ezxbFh+0QicKED0U/CDJ2VRJ08Oj1ZjMRltCi5tkwfLZTK95MWM0Gcqe
R7sDvFQ1FrNR+28Aj//pBWvUxgccFvQ772YRjAHoeqGEyUEk4ZN6EClkAjhuTFKnQl3eSGry37kj
Wcj7c/QxVnwcYa8fDP8MBkHXzlb3LEToRVkTg3nlfO3GWc5I2my3gXXHuQIRCw9iovp3a+bWxgFk
/E7zWmUxheLwgzRpB+klAM04IbALlShsqOAJ/aQyeRUFs62w0Epz1s2axbekVw6A/Qc9Jg9/YFUo
u2cabOjHbw9ZFr4jh55+6zri4Q2S5hcYtcra7wdRanKdeFlV8xeAAWJxWgrN0CcW56hslaqnEFKS
4sAxNyDXTcIUdqxiOkt4am5BywPaO0I4DPJ6raGK8hfsCcFbx8eUc98QD07l1WszgSh3UO6dJ4wM
sbmr0RGy/ttltO2rtbyPcl7xWNnGzhqfc3YGNhw1O8eN7VLiOgU4kL2lIBxHbPT9yfaf45JaZLrw
Ik/dBCTA+6R6yuJ2YaiJ6IZhBnL8fYId+2U57UCRhR78fTG2ePBI4LeeTxcBr4XvoD2oDXp12JsJ
ByS1dTrMsx2nLVMLyLYShSkGMqg5LHvxALcu8LxprVzE9OBg7CkV6UIR9KpsXNYjGHxmsgO2qMTu
bKIVFiAXBhKpgekGBgAJdv2dUYxIckdaAjA8ghshpw0aXMIcPSj/4LaS1+oohmczCPVGB7JQOges
SEnBfZZtb+8foCDbsuk3DeK5XRHViFn8AgXSKNYJE1koysrGbjPwUKtUA10wxegfnEp8u1y7+bvq
i/OfqfskZs0Zo/WfNlgXXRD7+Wxz4XYTR9Ia9YvvyOqdp7csigAgSXyoycRhQFSHTGAKuZa8LaWN
3DPvLkxTH/pLFkFfX95Xyqi4mWSZpJiabTMMXrSyYo9fM12L4RrGabv90xzQZzu+0yGeBg4RR6Fp
r2ngLQI3kECHifAZJp6933qtDR5ZH+DTxwtjbXatW+Yx+yJcVhsStJcRiix1h4BqOVbjsp+gy4eX
NDGk++oFyo+58WLNzyDr49liQ6Ak32ml5qiW8tymJQenDdSySvt/t85M6IhJLDudOoiV81lYNHcm
Gqm+AwBsvaqHGFmCOi0VDu1pI+GO1XVsuVS+aRj+6ijgVGmGFn6SrrFILwG+u/ULFwdn/sxnQAGO
FqfZl/eB2YFnK7UMMxduN7oWSToTTjz52M5cNA7ZFL/B50wfSr3uqDDrddhxKTEUndTlYTucGYxH
nfshdn2Fz/ELbXhhZmRpvj84OYR5Loxz9T4rvM5Td4d6jQgCvmUIWzBVM5O2kpo0bhrgvQ0aMHuq
7L+hSzS5RLgkEMSlAbRKMsZTdlkBygvxcKvrvjPmD6HFwL9xCKCQBnoyMwbdA0saq6jXF382eidl
0Y84kdKH5z6jpM3ftuPXeLHn8GitObLokYa2t/44nBLrGmM9yfqtYn+6Oi1M/khH+np6/b72TSEB
O3S+TyCaRN6iVINnRNXifLry0tXw/x2U5I9Ve32eQBf6448KOWGY3XgmdbtRD73a0ypczxyFe09l
1OeQ9fRpmpd5Y0EUSGoMHzBPXRlNawJoqp4gdYTjK41Innmv0KuWioXKz1BPt/JLss1S+joyzTVg
rR9l+T5NfmbiEPoM/qhmvuoYN+GRyxBWwowEZZxQDBgd4TxTQmiDf58bp78dbmZupwCMaZHvXQ/3
0B4tn0JFHUZE59GFP2xb/tlGXvW07eXdu6H1kLqBAJ6ciKgLemfCYS5NZRFhrB0+zAbfMS2HFYuV
H7YHZbDoJKgPJglbP9UQHURlzLhtBD5Iq37Adt7DOZNgRtGWl87/UpZrMPmslbxb7l6hn8g/TF46
z1QR1x15GjDFT5ft2u4UXvSCBsFDg0/9B1Q/R0z0HAv9TPubsiFTfMiLs0Tf8nWTiWsxPOx10FEF
3mcSZuk9COoYLSJaogoU891tNI3n207RUAA5EdbJlm+OL8H/HcPBqouuNYTIQ8VbvQKmKh6Cvw7v
3rUiDPyO2Ehiubs6iR1gZ16rEB7cL5rL1+9KA5x+26ULat7r6MjH51a7jcwotKInta601G74aKlb
LIOHrd0j0Sz3HmerWJzbK8X1tvqiwva64K67/NB/SaSJnizXs8v8kMyf/spF2PwC8cRaRbirzJfh
uA0Vl29r6b9gXi5o4pG7w/LiYNhAsP4/Lkqa+NYQIT2yMBfaVNYi5lUDHaZKB7WC0NZLMu8o/kZn
aYqNrurdOV5lLovzBwseBfsybmrFs2GINm/sONmmIoOPhNRbe+S4oaMyfO5LSKE6QX5LZk21lNlT
VdjGtF1T9qJ0qmoJN5yungl0BTTvSJ/FSXtblmTYOco6IC4BrnGGiYYcT+v22frVzA1uIoYX9vHK
IbgmXYn/B+uSEdfZIkx/cNxe6kGcHxxcSw2tkjkarQlAo6E5vux8OV1w0/V7Okbyp/jLIzgeau4p
Wi0jfCEm3cYJHnNyC/kfz8mWeqmCjoOB1hFdcMKe1GdZdXHp4kXsipfmtRSUdqgfRruJJXghblKh
8sGOeSReQBlw5+SYsya8au7X5eJn2UBx/E7bLxovg6HiZmhuDcFM1O3NNFOYpE4sVpwGV3ddXYGE
VmdpnnvVlocOYjZVG9VLmOLsNT5h1tM2u2sTyPPfn1Ft+csLJ8H7bdGgOaHg+Qh6gynBkVxq5jb5
Psj/a+wqlI4of8viCT4ZOkFHyz7X1GdX9LrcSujrdyTonLEITnF17gIujwsVIs7m2E6lfN/P3oSI
+fex0ghXkp7CHmfvtMPkompz6FyiyAYk37wM8jnMvtvnsiwU+aFdgL+PfYTLBvPXJyQqdz9gcuqV
Ec7KbEpMeUSsPymWubnsRSq0JbSR6VqePAPFPkWge/KffegjXPSG8tsC4PqBz4C0MQ7M9fFV8ISG
TPayv404PChVvF0Foy/D8KBNi+BBFuVR0VWZaorhppQ7fYsbhm/bl/cOZhpCc4QGVCC1BFh5+kNR
qIEW1BB01IHZuICPtQamuCaQM7qdR0/cFKb0RtoOBQVr3ErKUZNR0iDRu6FR5+eod+dCFE+B2zns
8WywoSawMcijhZWYGJUannFgFV4KtuwRuW+Ij4h9Kg7MkhqbkuOcS46IQRzmxCMWl7AysQBkdYXq
nG+dEhqgEijP6do9j07VIqgcM2T78U+JJw3k6YcYct2wCkMa/ObZfGUcv0XV/LDj1ZZ+hQjSLrhp
jAaaQ14bv/+HbNPTvaMM7L9i0/KTB/tpS23vIdbnxcfcl0Qbnzuqht4JiEAonIetXkNmRiCar7Cu
IPxFUcc0pfsltUa4TKbZgQT/4xNV8T+vmkxtEgDZAvUvfnEoKIijdC4dD2xsLFuQKnrQUQ/r14LS
1U9gP+1UCXjEvXm0ewxmyaHhX9GnxNH8rEYhMNq+IOt1qGRelL+EpPLQkRRHOBsf9zCDeEn7oTsK
pZVeaGUkMgiPOdrxnOi2rIIIej+EwELtCSpaF11O8VnBoS1tDKr+5ymXuJJI3D7f36EHxohnsP+/
LhfNTkjxRrepPrWlqdHOXTubMpZy3NnJyAk9jAv0S/CeGroNFnbTZBz4sWVX/qr5Wqh+jHnLIJwv
ahtrUxBFjZD4j/rDJnT8UEOQ8/sOHaDPk0LG5bKfbeq3F/rXdPcFR7y7dPMPl7O3haDCibv6UG++
we2454RR8nAzn66MiT9L3TmQcwaX6wF/3WI6vZ9B2LhNqWBAwSOaKQzVCKhc0MzVtGga0DEQs/tE
mpxMM8oxq0Xyz51yQDUtYYF95g8s5hrxM7vjL5HcwixrvvHtsJt7kdPzuiWGFDSR2c8vJ5d5W2d3
G7N5x7VU6vH5hQ7DM/K362Ss6OSsDpbUJvIS1aiqr5IzlqyYdEs/hpn6Wu8YVsSFT4TUzsom9e4P
L1vTRMn8uFNyHiaSZOdBhAAwiDFFYIa4yChJcxNHDkjr+zzHoP8NEDKKnA0seZXrO0VGeknIbBYg
efgb8DUWo0lqLE5YawY600vggOHegnl/DwPrmd0/9hrGnN3hupDVSBZLSS8MjJqRylVprUhFvMxk
IyFJfFr/5mpkGssZyQDcrgRaGzMY/CqxW+S4eL2Mpn8K3peeJPa+stg7J2De2Do18NULO1yKzZV+
yo+4sA3ZNL5I3HQAKhzGrWA5GXzV5+jXwwHUBQozRcYnUANFKUyV6ro2/bCvi4bm0ks6LGTuBySI
Hwhnu+5yaiXnIYRhvhTuPjQ7IOmmSkGUQ386FXa27882SAtXym90A8Aq0Oum41LP9QGiSPXBK3KP
8fP5SjWjFgRdM568WhEh+wBmem4B2H5ZixgPUeV0VhbrjHBDpMfFEcxYLDc3R3x85+StaPqBENNa
VMnObLewg7k1a0rPWZwMMqLC9dpTmmnz1jWF2JfpOLqtCFPfYtdbgMd5T+2xS+1YylLb+6oD9QxH
fUezeDli/Xaae4ihDS2zDolb+/HAP2ILUSdczPWH1KZZwKaUw1dK32WlvOMFjM2rAPy+2YpWQbc2
E2AR7UUNadzI6j0YqEgxbU9ugGhvDsIploVFOuOuce6ujPMbagESzVrK3xomoqoSviiVGul0if8E
zswjs74QfRHHhOAtzsTv4zam3AJntEBI92MUnIkvW6gq2nPRvzYWYqwEYHtW48/bN8JyC01RAbqa
GLf3O10q1nLdu+uZtE3cU1eJimHTHr7YsX8p6T+bfmY/n2Nqg3/zc3+LLtS54YpXzXKcsq0+iHgY
3lQEoClN3nstSSef+jcDmjk3nRoYl05356Z3Wf75c04Hg8yDJElskG3Nfcpn+pXcBTI4gqAqba+M
Vgykn6QxtHI8D6pirfeb169YfkVSnd36vKE/nOmvkcl9uzL0ApHUubfh6c9UWjdsjBAb9plyBuaM
yI1q032DexmrDmNoxjDkh5AUYH90RqCirRCQsi4+ZyzlCsdANzT2Q1VYVFw34qO/JQ6g08vFownu
/A2TQ376oNDNeO61GbdUb33HZ9mf4zLUduC7WaLmdp4UTyLOjTmbQ9M4prly5APU7QJNYbyoJrmo
f57Uy61NsLCZIVbNlNHW1sVDHkgzKImPD3oH2KO6+fCQPRdQ0NpIvCzBkqtB0gzr4QoXjR/kLgLm
gW+Wdn9A1kPEIT2FRH7HRVpmngnhzBh91/38x81NzSqqbCoIQMcdsyhxycUHQjAWDUFYhsd3U8yO
a6O7gxYKy79omGxmmT2ZDeYPxgcNFtPyRFhayGHwTNn/PP/bJ8YWQzzBMtrkeGeO2xx4BVC23gQu
djCtQ2lrQnxXaaNKEUY9lNqCuTHcEYvO/VSYqLgKA0TRRHDBmKOty/6EqmVBs+qnAy4HzkTl2DPt
kAVlhE47uLG2PYD7wVA/uVE9NN2ymHUb+zlDfnf6In1OpbhYgmg0NlYlYFQ3u41jsDAho25TLb6a
HLW4cWHdDcaduiFz+wFp/GGGqMjwGSDDEBJjlc9c720ARGGeTXOIQ5JXCHtJ1X1Aypq29QS12Vdl
cb8kr3IfvFevD4WtCLbtm7miRXcklGos3WrOmQoYuCN0+tIV3z6ruAnJbZ6ApOrov+XpqCBC9osI
JmaPbJtDZjWSVJF4jYrCukVguL40hNdAeVsabhc2LdScvndx9Xj3hMDApK4hgNkWxSxWNHceVjdA
pdn1O1ROiOGGoOF6N5acsuuu6wi+ORJQ4umJ+TmLcmGAa1TIRj5GqbKwyu9mfUl4Gsf+dfAyhW+/
VRpH3uJ0WTF01uULdmuGZL7iKcHJLJKKihSDhYbZqac7Shbc7NROoQXKXK7S1niMme5uKPj8E7p3
oSX51X/MvJ9xkecwj83qfGi2yHptF+JhO+gzzaqBTy65xYiNwQJhhmMH0KieWMwIauBjP3j639r6
DS6sMIbVRRNt1F1Zg8lheUYsri5qBGHEqZ0PS0jV29uI9hzqHKx2ZKRS6TcGkuCQtVeH+EQkgQVv
Z+HzGjuuQ15lWMs8deTY1qdDts6wnvGBWVdo/l6tUyMao0+DQYFB6bn78Han8pn1eT29dqUTD9Xx
F8d40aR77NRohJ7SSf9DkSgAh8zb7B2cyI89O/oPLGnnHktxx8qfg9+cYuW0iehQoa8DwBcT1Sws
tX0n0GlItZOXvJ3TAjhPp2KijCwVWK5msuM1vn2eUEQ4RKrWO7gC/iHsALiOVs2fzN++OEWRG5Uh
akddRcWvVeJjVyr1VoAv7DhuL/XpjfnYCuzvZw4AzKE9DZws1PkIPNgGdchCG7lh9HxRjPBc+3rr
Y7USIyyI0/fqxFd4qOU3ZU9f2O9rM928nO37hVkbH8TgN+r/VCCiW4c9Tg7AVeV8hxQfdOuQpITB
Y3ROV4GIct4BYvb1LtGfpbzE/bWI/b2n/SVLpgvLDsGv6pmr04HEkBWkrpS6UHzasJU+6Vh4GDH0
QKy50CbJk4MZzyzKcrOBtfocOjdc3+e8lwJyvtSraE84H+v1ipB6RkKFgBgR/dTHi6EdBUXBFt5P
118esSfw39AghXM3sMbkYXWaHBQ5HGa+spRpJylQKGK3G7rgp+mOQGWICkE3OQkdbOO+/hRxJY+i
l7WMT6Zp5s54/MZmFzAV4FCM+GbGpKJpclQgAsF6gS0vOiAYybVZeFARt0j78hmq14S1TA9j6c14
sg6rYBhCRXcnm1B970xCtGR29DzQXDjSp7937zNpM4GxvFrvAJwwSFKtTbK+kf5gId1Azl0iCJcI
UmyV3kqkVgQaw5aAEvXEe001OQkJqURFVPyM+rHgFGAEHcsMjQW5fCmTYw37C9la1lbEKscO1rns
Ll0BHmrKQZQ7G8DC9ikOqrdV02WKhyyZ5uCZ1CFs+owGwawE/RVeum/HtgTi01ZdakQLFdzhC4uY
WTg7pcQ/2o0Dp9LcacqlW2gB4sId4YRrLUu3GGKpBt/8IZmC0U19EifBx1yWhjotSmAmgR9pQgsG
Ge9dwqSobVUKkOhPQGJhg8xEBUNg0MyYH2o6gfXcd2hBKSVHnxc4VJRUNXNcppgkq80RMxGcOdks
3rB/7yIUJuKjkNMXKzfcxkWjKUQEl7KmY1QafQ5a8EoYk9weEm9mcUXyQfyFxVK9fCSSeWFJ/wjQ
PUsX/j6tXRqjoIBoEM2kAFO734QIHcgwz8C1ZBsxAbu8Qquum9F4vn9EHiD32dDSakHFuTS6T9Cm
TrOetcmQr/sDeZnmKOck81w9FDAovh4ZxgZQ2O00NLKvFUS93XWUtZrGmHhu+lhR7lw8qSN3KA+T
R+3oYEUfAzryGoTDhsvTAMTcwP2qHdF144DeQd5pwODh+VIm1YDVJchygZ6+Zu2gkhFuV4g4/Buc
MJdXzR2b9azCyzEzFkbtqwA4BBpznJv/POAVmZzO29Xacv27WWNMinH8Q+N9+Jgt93uZOCE3RSFH
dyC2pAEq9M+tOu2eKQlrAB41qmREsnBZTNW+Jtegv2L+NT417NTcwk9IK/lIAV9s8y5BKn+e8+it
LRwPSUon9cae/SQSzz+tXMMuu7O8IMljCjEkxgYR5MNL4rOe54erELIb6MH6Ngxs6QyeonT7J9as
xpAHHxLFcv3wNG61bcaLOGmOBlLkpjFlRx3bBEx6x4DZjiU2rd7P9I+gmEpt/an2NMZUC2CK8+k+
BostR86o94VOREZh4TPSdcHO6tVv2G+JCy8xQAy1Uz6waafXZfyWRpPCHkZdDnDKFyWjvY69zqID
wo15gE7eX7ybBdv1gyy1nu3mW3K5kb4OUeIH5R7rbOci/sB52JfiZ7PyvrCFKCW+H/4LbyOB8/qP
5mq4oi4ySJfhsvUCc7kLUdwVwQBuSQj6mS8nM004Hs3V2Y6efSmjPXaNteGgjqTBjx7YlZAGq6wd
fetKderQ0yNJKZ5EwFQImDO5v0HN5wNenaLdsqlh+OVHxnBDK8HjYVB0v5uejiNC0IPA1wC+8DEM
IPu7861/bT04BoZso0P3LefR1pdmFxONAv1s5mzzyHIDfjF2OJ38hJPZqNUQ8XfXWS6QiNm6h999
5ieZh+JlLOpRIXz5x1BVtEtJ0JG26JKWyVzwIdld/gDLI1ka3Aq59HyDSdMSDDYTw3DkGlFa0VG4
ZsERIgoEyhGxmLaG4EoggItYEMIORqw0wDz4Rz88J3SEcfXC9aBHS8n42+xJMB52opiPfIO+LMPP
2hXj2NSqdB9zsQJgg6IlnzIiG45rWUAj4CsjXxBsXDcl86ZQBJ+av6Vpkk223vB/LfbNSuQJS0Pg
UzK2CfcjvPA4vH2tqSYrzPYRKDaEKGarR4rScGkh9G/CuiMuBPAGXwoEtMVzPcApMKcPsEsK8qDH
C3nFlWNwGZjBaAz/MTDV3yQD9HATOiTAYab6cJdnzFwN0jFaskVpX3vENcQNARDQTS624OE4unXJ
FDcOrxXy1NZ+ie7C2RwnHAXaiC4pbTWQq1wQT01nGBm1ytOdd4eesPDSl/K3M49cHM8HUbv50zVb
6cKVIUiW6qZw1y9THucF6QzNQG67Eoz9BvEElfUy6FCsSL/1kj4fZ60VVl9OXALQQcSdsgFPz4db
TlLufwuGgSTgKaW1cG6+NPvq4gVlm2GVmglcOKKcm/OMxs9BK8DM9jWGT45lmQeq6dk+g7LZmbcH
nqICtxtZkgOX2SqiL7ZkFHV9W/1Kdcz5uWs6dTpCHHeMoYYxr/v/jSd2Qd3OLXZDccpGn2ZHM1xF
MoKkMGTu9Tz5wCIiWaelAOOnR00V3wiyGxH6vt0reR4XL+YjrwCFvwKbSr4zcehuz3WN/ODUjuni
jIdzcYcwZPLy1A0dyUT7n2xipTcR+vFumrpJtcLUhxy6pUOdb81l6egnhp0EDF1fbJjaroPUxmBu
qI4H8dkk66iLH+sNq1GPKNPNUZ2Tof7GmDpcBrH6CPXgGhZLiz9NLq6jp0bdlCpQo2Y06ysAeL1M
fEW7My2m7VB1aFzCPyTXypoBp4xsNFovV7ld3vYWhICccyJMIWIZknWiIUWgENFiwCa6Mn09x5fs
gkaAwDXOjdl/PkvY/UoOGFsyYXgQdj6JTgdJ4zB3FOLC9R0EPi1sRE0M+ao0aDo8utA5SgfPdJ/H
H+jRopFK1E2ki1uE8yMg4iXfjdkTHvNwWEP20kntxqty6B7FP/I/6mpPKX/dbhs795dR1S9hgyAI
RYQBwtdKfk2CHUG313bAx2zUkDebUpqi7noTJ5GFG9mzomDyn3C7tqcv6HwGWzER6UKNV/NEgkae
jnCtudgQkK9VtDYORKyOAB1sJYBsA3FkNe05keCErycm7dY7+9jv5rA12WjSnE1g6JFYYbmxJ9hb
yT41W7oVXcV8T7ipdz9+IXDX1r/ruI7hPLg8DYDBF/jPDtygM99mooSZ3czNeHa7uYMpFTdsGovm
P9Quubdreionr1gqDdNP7TXkSeSw0ug6YHi/g0zcGdhLLH5aL6kCnZ3TUq4KOhht4JbCmC3+GcU9
SilXCuBahIP0nslWRW2gmOvIVoLv8vEgvXnBCOHmZS+vJ3QlDfYSq8RPN2cyLBQ5OoaVmRY1ctrn
DRHnR/g49MQDQfymqQqvZQoeSnqPUCgNAmNgivr/E9BgQRiEbcmCMOCuTA0zdUY124lQbEoxRy7x
V/juYYHto+iBPrYr7tN5YiqOTTeayeDokC3nXL+8GF4wpw1GXCivkWSJvV9IqbsZDMRVNKA7QwcH
TBDKkl7MLzLJCfkJ377+CpktpJQUXcgIk+g45AqSpnIoBhb8q2SAKJLbwwKrSI1X4xuix/ZMbuJW
GuIbei01OV4EwVjKmwUfa1T1Q60qVlAdC3MQgc/et3GFbFkz/Z3fDNgtsyTaJnmfsuwD+R530RAY
vWI0hUXnUerhOHtZa1G8S+flzTujBbOAYYpy2ydvT/IVcHXL97nZNrygnB1WIRaM5UL0vrU4jADf
TF5JKPDv7DR0ErsEsS8pPxfw8eQHEdUyIks4N6l1bSmgfNoS0XnEIxJMNUqzy1HMBSpyQ8ANK/jJ
lwZgLmzLtfVuK190PbR1ANVty7fBbUqIL8filwZVHHQyZK9UiwvNR0pS9fHIHesJnehl+Uq8Dl9N
gcuyhimYF2eYAlbAIeGCqVs8An26BpINU7mVUswWaKiNtltz5TPUmaAJBHyhKXi4tvFrXEmoDqlf
DKJ4eYiP13tTEZyiGH2z82pl+KvXf4aZ0jEgLFF/6hE9zyD3l7NVr6J/32Jtus/4Kpw+DkL8rY8v
GxVUnQsEbEvuQgnP6JTiKf0n7xv/va2Pcaty+0KpjB3qKkVuf0hjXHN/3ko2sXHA7ZyK9NZfkQJj
WnyzAiv+nACH1ISqtGbvt2ebsgQbP53S4DOQK3pFIfK1i0G9u3U8YyBfyfX1p4tB8c6C2L1bWtqc
IwdmqkJRHTK/Wp19aksXVzoQwjpSfqc6LKQHM5g27eNryHiTg6evsZ9r/hjEpNo7N1YykHVQu58T
Jr5bS9YrpSt9Hwkwp2vlgBzBUW83N31ig/sNxCwwPFbMKrKjckpAP62921Y98NK4e6bz4gWkpYk2
mstif+rZrw+bAZDewSy9ApSwyIqJGDoUpm5rSlrZJUNgWQ5Ymvo0wU+WVTLGdzPQ0er34GB8nEN9
tF3b0ibgdXQ4e4FKB5vLCMoaG8ynSMKmZN6T9AM0vjVbZbIJQoau8+JmQqP6hxqI89kiYvfjd5t0
dLCKXEvzwTc2tyixDXchw6Um5XVyo1EYtXXk0uZN8MW5jct8GG3ka7k7Tk5hYg9WfZPxGrkvstu6
YRrzm75f5+8GKSN+XCLDidcjy2m5pwEBFSUXoDxHqcMf+Yt9k+jLypiQ8gSAsWsMP+0CdjquL27k
sU1Fm9J+ryE/v45Qq1jh2Fb/Rnv+oSXvu6Q7Fgc6qTOoXQJfxPCzMYyWOkU5NhlAedMCDSsxdaPb
RWDs+XFGnmKJGA47O9IhbPrZigS3OqkBF/V2nr2MdNN0k6Cv9a01hLlpJx8SXrAYxAEWEiAmHPCH
li3JDueo7QiUZtFDDUlVnv8KVyIyBLRNTp9OlJi52aL38QSPetRtRIE+IANAikQlnJn1z3hcFfvr
Wlp8h7byu3A/3IE2Umpgy7ylfFamFWhUg11nNyci+mDT3cXOOPwESL0cKTV05WL4fw2ehQDb5FMc
5Ob012kw8V5UPrfKvgP2Ggv3fZO4dqIh+FSdTRGrezA8lV0kPvgLfa/9I+QCo8aF+bbtxJXtCnvJ
5wJnBofVpFqY5Z8wl9N+4CKbc2S58/E5blCYoIq3/PcwZaKB6vcwWMh2chozpRdrQ24JN041iZmq
8RtcFIjXPxlDPsu0MHeuC80kkQ/EG8oLMNmwTrLfoFxNz16HFQ6QmzJPJmVXGmnUJeLxrhDJUVUM
hLrWcS0u50ARgQN5UjTp4mqNxEjcQfUpyLSAKT2WoKaJUx7V5p47mSf0QreGMDBhSRANgVVKTUjM
4VIap6HcHgWVtky7Do5Zqx3F8inRi4q/nf0YvVYRlioQgvmQuwTIpMh6eIQGVCXhFmrFupZ5SwxI
YcR5smAvNvnutpPHG4mWsbYBFISSg3F5EoF36U8e9+pwN0eaa2K+F122JGkKzEHthJte1997pdQT
2V6iHIn8QVhh/ypJfMbOv1YyEE/eVZqW5LdkS8rjvJLwPWM7nfsZFOtZWPR8gwJpJ7adJqxYt8ot
z2GSaWFmxqgWdWOgD3fQ7JfeelPFvvWXL69nqQ9GrERwP0MYfBy6mi5jpyvHqdrwU4yn/7LgWbz5
QXby5Cih34BZfoI6a0vhLkSUKCJKsYKB+Q9H1XV7uCCkqBbm0vpnY/x32SvCA9LbmtVrC81+Q/Q7
gJNLWxiAMhnMJcHhpVDUyK9565go85FxefYVI+fC2gJqtHuDIlJAnYnWrRihp0gE5HQByVlxLRsW
9ArIbeYwxFMCzRTb52+GdneGqftsXbxxAVZLSaqeY1tstPyWPZc+LFxihEcNqXzeNlQuz9m20eTE
WErsxTBjGlhklSY0xTA285Ov6vsbWBA6egCYxumLw5mVIpUwBoh7ttOcgxfSUjw/8Q4oSbao3S8d
Mpuoowk7DMd4FAfIXBvMnRz0tVIlwVRdc0EH5kccYAaFLzgYypcAVoIlrBKHTzM/DNTxYP7IIzgY
/dApjaN21oYl0+35IQm2OKpHzZ+je5JO+DPZu5v+AJFguaTpUpaxlFAvteypp3fMF5tn9NegJNCD
lo5LZvy0u28TaIoCZYJPh4O6S3YabEpNtXnosD+pA9TjLeanGvZP67IpFeLYa3kX9KArZdljiJ57
F0MsjrWASX9EP3C5Z+mQ382nyKUHWTbMOpp6uFZ56lIxckv0AEXnlKK+mqL2ErO+Cbbxwow1p7T7
i1XS5nlYcUxR5rQP0Ak76swkp8YhthoqKqWSgOGtV31g/0Z9CsPqtKZM0ts9DvAq/sCCHuUaNthT
vvpjJd/nTPZbOLW3lY8DX6ws71a1GAtUymGStE6fn/mLSBhl2U3a5yNfaZtaFnyNLlvU3pujQmkT
v3+jUeZxOtqAHyTRiUp4jQx2MAA5XEyu3/ihK761VHhSrR2OmOaK7JJ2k66n/FHM20ppBx4aI5hk
TuBMrFfm4whjLJ3y2866UB+wIK4Iuf6/c642lFtJt+NkCn5QoDmFJUsfKZGbp/ITQZTALM9+oXvb
UpEKRRe9vN0RBjNuL1UT5lXxorxffa6H3gu0MY6sYkxgWUlJ9S2yY0+ZbcmGgQNc08zoov0A9FZ8
88FQzGVjbhTC3zGFElSvLQm38SKKceZbII2d9hiVWUJ+gmDk/hZYRHnMcErc2e4tqerBpgu7SoIO
VoY5OWgOrH6mmbAQMvcs67xgqE7eQZqI+7sT29BicZGSLyVFRPc6guz08VIkFjtpeFABRGiQdxMg
ZUDUbRyA/EIi+6vvh3fDSR0pPq1yxNf/Y5XbOk2Ea0a79133NqCgsnl6IDCvbduiQx+MGYaddorp
a5rsPK2dZlIGWkgZYuZF/bHp5MUUHqjfENuQb6/vM60IZCAnIoD/IpWeRgfmJr8LUGZTKC/d2TtW
hKex4qNPXArQJw9MPzTmeIaAh7MOsIGas5kpsqYM+bJAN84t99Qa2H/1YxwZrqSG0kV2im6Am+rl
pOgjs6W7UTuv8dBrwsSmtByOkxVBiCdJyI/9XFvpvfUKJxR8nAR90cWgPleB7eQyPrHIjnp6IsLe
S79Wlfy1LYt99Lc/OYT8t9SnLZwVXGYCGd4C0MhJaeQfxovUjGAu9CG3zusJ6uGUaIwiwDF/ZoUx
ZtduJm9ScCTUI7gCmLRYd64QgsnkzCgNa/X0KY2hWL5UB7wU6OKTiKhHoAchyRcKBCHlfOU8oaMT
QlK10qhENaQww1B6cfjJF5jRDM72Rry6BMhxlAiXwQ80YMlWZnRhmLhVuZf5a91zda7kz6DnmcPS
avJSptbc4VgKHvErXkEzRLF7KzZtDSV9PnT/1J2dUq6q/+xthRV6MMGTn/bOnlC4f6xSDmoLdb5p
0qppLRP9Jz+QHNUkunjbcPkAZVApY49tVeib/VQLpq//HK/uwireGDHbqoD4D9jY82Yt5Hq0A7Pw
nFZ5jadkNryNMFavcAbYjFvSJbb0sAIJXBxsbrBrIvhCWMCBygF+CduXFnCLgQkFnTemkszxLxJx
PIHduvwtgyd2p2Wl1d7pFiWyuqc6nj6IzOeZFHe83ng+NiMsiISC8wdUZnVJfLCmFLYC1cAhXMxO
4ekrqww5UI/o/aZAcS0mJw4c1besRZUaNsRBLqhkudYYYh20QDdZA5OC9KovZgWm6N36Q1XTto0g
q4sFfGcAHJGpOmu66+pr3mhjIGlqzTpjfiRsWtH+rVZog9nxzNAmcg0MdGAFj2EpgRpAyhZVZ5GU
Pl6inzQdZDoby6M/4JwA3PDPBgKwnliLpLWF08wNtX6CJCGS4Bmfet7p0cogi9p+adKhPorz1D+r
BXqBjfinhGeAhEwy5dTgjqCRkEjAMCtc8YYz3VLF/Q764qvJRIrxVhOsL8/HSk/E4BYCpdKAEOc0
E3N9rkuYnjbRkcbAEz/3HW5cI/T8ci9uw0R0PwfBKfRe/wSdRKruEnnQDrCV9dWRj3WY1MxyLP+g
j6dEP9niWr+aR81xDKJETUsjMJfudf87nTezHh7pQ5ZU7kEPZjXXlQ3B6jLrHYqgJ4TpoPwOXNL2
wOARWmks8ZW/2KtcB214qwQUrkGOC0i+DhHYKgpSVV0B/P6Z20p8geq2u1r5XnVtdWvCJJQU6//m
kTXgl5LpaachXAT+NmU6HDc11rc7FzMc3Vo1Xk6LeELVOYfO+q7WThBVD7IjW39U5MrQ5uyibR7+
3arh4Xra+3w4+rQwcmLql1SfO+NBZB4pDyD7EsJ3OC0uY1VFmTxQdGwmzsuiULmYVymhRzl5wVnZ
uhjHV/w5kqnpd9puiMvZ4uwuuT0NuWO8q7HksTwzTRVJi0gR+tuGRSQjlB0ykK8A+tVo6I0HDl5c
Y/fsAmNuz0zlV9wdy/Lde/xUv7NR3k7zgZv41xHRXZYrTacIVtBhKIx5TrQJY9wljQ9Pu0rOAi6R
vQVM625mfEloi8BqCKPsXANvVgQtXk+7sfQeb2J7g0H6CbmyRI1+x5FHU6B6zmVJPxHK5KcCry6K
WbmCviwiMeSszOlSDCsRQEzs4bWXdKrXq1ItCXVp2PfaOJkZxktWNgohDlplBVVmF/XAXikK4FTJ
2PgKDkRjymnlHW3u1dBThRRJWluCYcT/NobycdgvMw5GAN+AtNn6xUbCYXhnzrijalu+RQkpC1Re
O3EVxOZkmxAG9et2PbOp+CJwkRrlT5PHu9WYd4d9IsKDAncNt/4l3p8ORUAPCqzJvQObeOPIlfjR
9EoPjSA90+SkTVqmGCiF+AkfpGET6WIzjGmLAjSL6JOMrT04Hn91+P2nKeNk9q4nsw7Lm0AtqmIu
SIt/vdKYczbZfHfWkTpGj/P5El0wRKI5OaUEQYKbbVNaSr6MQ6Wn7Ba5kVZJFVblij+Wxh4Hgusq
E+xujhFo9VHqOHc4b+UPjqk/BkEPrbOpUXd28QAseqfb90yEO+vB32/2VPk7ZsbV6k1sPNg62iru
OrlV1Q2W2mdWnY/UMZH0ftbybzkHkaj5I30bqOANQpPW+tuG92RHG5uIL0NZf6z8+NDr2LZJ9o5t
9A5adJJ3917Y7TbR4YGyhaApL6J9MPehHfmEB/wXXI6XjuYBiCun07nZxuHzdophU3KTfL2svl+T
a547AmudmcA/WnesVWyo/0Wyu3k0iobfPVpl8E5CtmBD7AgBMlQdgBv+587Vs2KVOoE+6W1wKUnk
WBp18yrE4dVjTCGkCI3nKemaO49JVomdkJyjn7vBJH20JRYiYN/rFn8CgvJqng4KBMm7BEgkjgrQ
IMa5a6ywci7rjtewFiHPbYJ1xrmE/QdseM2VYzd+K4hFw6ACMuYW/vJxFlSfftCAHlOXZocZGxc6
O0c7MzcOHGnwC4yJ9nHct6RyCvZftMfnnM7pa7jsAbv34ZGH8wjGSVvpU9BQw8rrU2EPtmat/2tm
6Av3ryiGWpiIvIErF2oi/vYDwiU2QKtNvUMEbMlDGhzc+qOy1qdSmDLZpGkSL+0nCBPsBlieBASX
cQ3sOkzyIJAk1w9PIOH1685pidm3fhwZE+9yuATqJe5vAIJAUSu+CS44aKrvdI8FQvxXH/vChJkD
AX9JvRh66uiMiIB5OeWRBCG3q104ndmb/1uZzuslHAiW1yJI4bO/+lWlyVDZsWmCEa/Q10O0LETD
3JyA/wV1s0beI9olwsCcaRmiRcByKgaPwTYaINaTvNWnfbfhX0MsALttTHsR8c4uyMYelsGFjUuZ
R0Mh+gQiz5Hb7rNJEcY0/t9SHIqoxSSFuHvlj7RKHSClCsekxvgByT3XJC8SRE1K/qkIEiNANc/H
y2gd7I6i7aFSnkG0Tl4SkrQlTcYy4rt9E7lntXmU1VewE+uOody2dH/2PEv+dZj4YpHktxNVYy80
ZcFTvtlJQhHnzEMnVOLzSypxOPzCz2UbdzlgnsNrZDRKOV9oopQqFpoPB9/Z99LZMjP4rrmiRaRo
2njSaIMJOra7219Y2VWH/IRZp7ekkIPob7NFWgbWiVX0vf1mKPEc3YZMe3Vq7EQ5XYV5I8S0aU+K
WavVJ0kmrFAISzb6P/LE0y9ot4QPVt+L3Zu4497FsM5toH2q4y3g1U8qujFQI09OkR0iojadjaCV
jzqqzqjNVXBPyQUM25tanuGqHWRLnSVjCHV17Ps2NMNBXuaF9xczZKE1pisgFtE4VG8tpTsVzVLw
zfjxQ6ypxLEEQWWnhJgW2+kAei0mRmm04u2vSBazUwxoyeQDQB7SleIVTNZ9Rvo2dKvQB4vUg/UX
nVRdkMFpSE83MTlXjZlxRTB5eYEOsmMY8Tv2Q/hmi4tprgI+1EP/X339bChG9xYAMrFNdU4aYD1d
XkRIjYEk6V8lxehkF8Huk+sf+KiqpiX649U4NMeosJjgj2FPlptoOM7tVa9OY4BRbatpym0CZqCR
NFQ6TcMyPTD52jTMFWkDtIKR4Xo6b+HjFu2gozh0Yh9VZElelEFCdH/WsV+3kjshDRYUmPLWdw5w
AabGccDygNVNAoLShtUK/X6ll055M5ySxDF6iTE/mWrvYKMeF6U0TRz0kgVSiUsRqAKlvClTDIBD
kIuPIRblg+MYUtCkXfp5zxQHGZrKkGBw/QxP6SuOZDwe9cm1qLlQVK1K+qtdW6Em69yymsUwDbM6
IIT0WQ2rtE1tt5zCdmcV3izahiQp80sU6h+6UB7aC6MBIYEuP+b/E0Xmx5Ox/b1LkoNvLcokFqcI
k3CIeVsvBftJDu6ksz/efwpzEDgDH8fHgQCXyAIPc6TpaeatWpJ11Xr81J4QFrX5fRgw4Gk5igKq
Cl7e0x+ca7h3GxZSkjwwESfqF3fXS40HV5er7JW6ntm8y3kXp33gCZbLVrzHsThKE81zuaRFFvBU
9dU8fANp0jv/qSArnbYxtSIUTSP3FBwyDVWo51iTmeOzRGugUO0or37zvm6d2bT0ZMZnvtN00I9P
YpEnbvPEZBVBRUliffuop0aQkLaw+wxToe8Cg95eu9d88XnpW4BWJwziJ6+Dsej1G0lZuNuHvp20
j1mFG/CyRrstryI+zFKTgKcLWQFXejMG1ml3NhYDt3A7QNra7Aa1+8y0EdOrxWR55skBCxvCteAv
F+/lHJyUfAZCRLjXEJcyuExjT3pn+1Rf4DAtAXD4R1SI6sSQ+OZR+z1pDv8Wfe43kW6vvV6rthmP
pf+83/sSR6sxVt7kAkUQA5ynCn1VP6mcnTvlihVkA8+bxf6TR8BgPFPrHlX0UFCbNOeVlC4rx3ed
lV4hQcxTIV+UiO5h5+PP/KO84AxTwYnxvaOufQZsezFJpharATRWbUB1lUbfGCjrgq+bbHY9zZU5
PWCBvGk662bK/L0y4xI/xUiL72JPBCG6HOXgyExSFuVCXTRAAQNh1QhN4ZtknPuYDqSFfbqFyhZ7
C/vSWWb5oZ+VZl5cm0t0CRg825ql0b1ZENH65YydEjC7ZdAvG1wKxaKnqepXbgZUmZjYFlblwMyO
+Xi0WV767EmgKHF04x5OXXFloIrEe2ta7LqVhrTVtVuJdoOS90jEuzWDJWiPcJn0mxcnYhPYIoou
uhZMbi+WRbzeoWlR3KsWDHYuxPVIxvU16BKsaIXuW+q8i2fZmmfzrNuO3g3J6kJfWzt34CLjrQEk
sKb1CLuGvW729uBCoaR3eLERQz7802P0m9+4HneAX913+YpAC4gH5BBhP3xLN9Chgce58uRxB03f
baxuu6qL0nvgkRLpyzoUXOQMGKx1xcCZ6FQU4aXt6wZk6D12qpD0MYHk2Hn619w97P+0YHyve7xd
xUp6QVDpAbeliKy15+TPg9Vn4fOw7Pul1WGF3NnBP5EIWj6D18u+njXgP02JU8ENt2BuOX35x/HF
hI7+kSIVEoEw7yuqmYDCFYqQGsQ/0lAuK6iqjLplhtL0ktBSZOz7zYzIholcdvmGbxB90CQ5ILiA
AbQaKGKy4w8YtuER4Y1d3tb4PgObRwP3ReiC5BAKX+VpbLANLxyniqttAppusHNQZe1CdCDdfxgp
hdQVTHu0gWUHG8a2Rgi8dEsXN71llh/V9lTijAVDUtYWtKxMpBjLh6UQJtVSFOosnlwl30HxJmyv
DTwDbgNUa1tGaerKZoj34w5hrHO3qEDG60xLY1gYGg0ihi6RpD2wov0e38j1KXsNZqTIlfWo95mU
RlfcTAvuq+MB/UvUNlGleVmb3PCMUsK6lvuNcGhdDNTpr/pYCnmb/bKKM3JODbVF2NnGZTVNuAll
cSGj+DMKBVP+swcVYZHhEjzzDTScD+dA2pFkPA20l+B/40SJ8fsBaC7tLQHnk3RK/YbFkPEJzgZt
eFaTsK9h2lHTDySsaLcnGXjjYx/1cQ/OTYHTF1IQznYxCGEowRVO4iUEm+fHOEq8NXG2WlNuLLAz
jnKmk26CytiTf8BtVsSEFlffN+a+u1KWznz+Dj9Bq2pt8tv40Q3gJ1FYjlJ332a2kRC5BNvzmLMt
kyesJjFTPU1FcCt0zxHfBlxDJYGtPphlhvTgb1g7eAUk+ST9j7XM3L3MhlviFShQzgtlNXAY9ens
d+o1d+wsaGB1hMZRjZe5Z/XQ0OzFB6+FIYQMWhkToMiGZkjgSiGwVkdDBaN0rUc9oj9EyIxcLKG/
mh4wUlZq1b7t2af7mHS+uuPa83U6GVQOAUYoRaUoay1DK4wUI9Zq1rlf0vm/j9mqfkolvrhLatBr
3XCGFlFSaLNlGwCWlQpgeHmZ7mkrGd/36zPywp22HraiWCK8krWBtwNRraFSiHR+IR6Z+x0WT2sJ
8qJzc5l/qyIheg96s7khchAUwWrzsEKeHf52OWF64OHNhPL9zC04BkCEpGlqJwU4xKlnVZwHULDN
l4YOjawl6N6zZwwRjPhez72TY0e37XO/+fTl2xPKMgDmNH0qwpbNEMFf7nN/KmaY5jG9OpaOSiTu
d6CxtuIkwfK2HIuE9HzsdxaTGyvWH+g2/NxPVc/TFiv5+9ov/j1hgVkxhji0WTQaW5mtNBUgOCHv
uhUkNkoKMGsTAh1sHEseZRS1pYqC89YEVrEa3EywLFMwFiwZSl6kGk7Os17FD3+qzOkJ4n3Qqmdb
/FiUAMz2m/kiWzOjiH1T9wfp2eqWgDVkAJ1U7QEISs66evXyVkAVDVU/fk2BC0/Fc9vt5p3jeZs6
W7l9Iz42lj4v3zwzobM/f2ovFYLU/LeYhXrm1lrV+W05QAJVDfLhctajPTmgGlkT+fb2SJ8D3rlL
vSG5DggezKQef7ndp0RK9Gam+ErSP66jHfpsaGbTWIBkl4qQiQfNEkDWHLSQ7/9c/kUXKXFmb3lt
n7DJTVNCJSGYh042YyDMt8kcWxUeLaP4OTjG/sylmVKJ3Ej4zNWlG0gaScgZMEG4GMfwrYaM62Pp
b/u1LlmGtQgWkRDn0SfOlByQP3JCcdmuDmgshZLPC0yB+peWWqP6TktMTO09IrHVj16vUvIkka7m
RgQ1D7pCu9sQwzdEt02Y0uvV1O/G15QmWtY8Tjy6PsrJPcphOl+Dk8vlY19L0qP8J11PAa2COR29
FW4IXP8kyCgMQeGIiJJdCxyWezYOM/eIgItOh1I29WGzE183kW/SlHMlAgUvneMV+Kw81p5fgoOw
DUAjUquqx430JlYiaZ0SyN3KgdkQRcgMkgANPuAVgf+Nm1L9sfWKXY2m20Tck5M4GsaH9KX9O17e
alybv0RQWeGp1hk1rOc06J3awniYECx3JO5rQ9xY6WZeDeKoqnPtKHbd/rNEP3o5v3subljKC0qB
6Lb/Txxh6BElFHY3QkNstx8yuGC4hbgxHGQvAqYoMuWZ7GarzoUYDKRZ57h1FhaR/F8KFZe8/N/T
bBiVhiPNPPfuPcj+bMxrsKMoZAdgzp6+Ej0jRepwHGg5uiCd/IrZh1iUyEyedMpZf8AeQ0isnAZ5
CvPX9826jfUwi0oB5e7Wx2ipvHXPWW55jSmDDHuKzMZUTTMJJ1bOblMVHcGMnWIJaLgvDx0S3cwe
8M2JtknTkHOxdIPMy5SB1mjsu0PLRu396NGRsLWtITBKdxsBkKGSwv/hB1U69/34x8pQrwb2MaKg
eAgE8mJBbCybMQiLwSIiQmlRxL6Dpkyo5boXwTQSLSbE5a40ncwaj7TqxAaQeDSG7RlfhZL5Y/We
+bv2F+rJqp/keFG7YwNgkMVLjFJ3TMsFU9lvGTHC8eR0KR7ZLz0UpbmF8BvnSvhtuSBfmSiZT7rA
F4Iu5msUkrVd697a5HWM6LRHvqiCLa0f5DFxaQujkvLDUpb8MwvZ0i10Z868jeFXmAg9azCNN1Sm
zoORdeCag1hPqTHPWl9wEKw4HYPdb/IIHquyLQ8T+8QeaBbiPT/XDlTksNWUj/LV4kf/HnALgLQ2
DuXQhxN+2eV6lAqkd2aCuePfH/0PiBlimYCVpZGTginmqAKlmZWU0gaJ4Mnq85qOGUkcDArPOCLS
QqQOjCkTMM2q7fP4xgmDdivfDNPtKo3DKizHQ5NLdPSXSw/qedmcnQSWHrVATr8U7F+LiWuWqafz
+7Vm7D7k6sqGzIB8HdSnNJPpNsHALAZQiJ8dVJIMltNBMt/bV6Enz408GXykXSc3lwao6kPPiovs
ZlVU1dm4GAqyZs7+oZA3izsK7tECRU4N03hO96s2n6eGWi1RBaP59kx8uNSdYx4vJHGx5QqOUzU2
I+GLv8lIYPMQOEi+JHnL1T2DiPFxcJvcuRscAQ0UCf40/m03ctVgRwGXLkn8jB+ZLuPVBQfD6+PE
O6r1Hd2WW9pvCUou8pVhUZeRYQzvVtB6wfRj+jIMb6XM2MSJItMAsjtt/p0ieGdgx6BHzp6uTnjK
NCumCK57YaVZ/dCYiGnZ2kGvwkW4by1iicmez7bLnv4G6J4niMv6VyZ2HjOzKsEE6eqOxcfwmOd1
QKqD9WRbu3usoE/Kkczguk3mNZJT3OBysxbiTBC4yU5ndELxL68rd9GhlJMyNbq5cGEnL69C+Iqy
FXJQfz6y961a7RnDJibeLFO9RH8mTvhecmE887kwCxvPH2RKFBXsqP7vkbWbQfzqiu5GhzsBnLl9
V8P7hrczWbd3pSHHLOgKZqoZO1s4hpARRWoJSHTCnnDn7dIpHxQKQ4WqKqLSxA5i7hgnPzYIpADx
4OQ4HFhJZVqPccCFu9AesZbRccffQZl7NKLnWWL1h0hl1BPhkurYrAF5o/fins9m6aXqc3VkiHMp
vRZYmfhoUwG6Hwwlp7AtiA2hHshRaCyktD+uYFezcKrPHCHs1SEc4/MMfIsDW+Kd1BHJXRHro7fe
SBkdSAjaDDRU25WaU6DBNc/qCL1l5C9bqi3kyDwcSTdJFKb4PdHnJ3gjzHaAMVQ8cKLFlk4AA1vO
ow733N2UID58xZkLgyqE7iLdycXxxkpfxOLe8CsRR8VXrlFCFRUdasnPYT8Rkl8jWo+AZBHomai6
T+01vY4O6yzaNowtX83ZlVyCsqXSy7ojrTtgr/w8sikJKZjizm+t4PTlFcs1BQYsP5nTOQruKtrL
/PPIuDoD/mK3OvfklS8ZLoCBuMkuKfeXk+htbn+ApSJpTWQ8C7f+et+ZzQgio8RGGfQkb+vHidzr
Q1ytaxikKS/bhZLORDCsSCtIPPxtLxPYC9jTsN6Whgcmsjpl/YugTsJiR2aDVcIqU/FBQGHkyi8L
l3gDL8Yk7od5loaTl0uJuUskWIsd9F/uRZqCPCaJ82QPWhfApSFoRIxIttfAe6RD+7XYfURFSTTX
yRtOQAbWJvfp1XLR2jBZ1mn2fHBZdkkKRhalW8jM2udz7BD9I4ue95svPZlz9MygXiI6/sSVD0a3
JQz1zCzDIOdAnxFJ0s7FiiKTMafOfvdt4jk0QPDZfM3jvi97lEGn7foGbeh/Y/QW34bw1G9/5+3G
aJvc6e/9NHUlYdIgYa2lrwlZneiAibqJpB8fYeRP0+pmYIS3XfNV5iFuLvBd/1Ru01e+NdMb1iyy
QVg4TeW8sUTbFG6nsbVxhjcpeUuax+9LuFNJgWnGbitZGq1vUgD/tGFHx4efgK9siHdjmmMHy+rQ
r5WERQW9u3/u6TwDXvQxrMJxV+1b/u23Upa9cdqmYmLl+2jkFkSBt4ysb6V3gpV8ML75h5B+7qdy
l4UUp0I9HHNQsl6+wiGtiR4K7I8XVGcEFkswwRoI0ELO5I+Smfn79JK5IfZy9iaoLDpYiB81Gdom
LIXP9lxVwaomDahtf6RPsTj+qpmnfm2GptKs0t9KcyDDrcvRR+ufAO2XUSVUX7REE+/EAOwvR/cU
Xig3/Xl97RQx8oFEyYSqsqgyFay0L3fx0taIp045IGYWletCHDKP4MhvtI4/I6qsUG1Tks8Isgtc
fjg271IW0iS2i/cIUbqnE0jR+VDajpp6FBmovBhVMYAkT1tFR4SfLDGrYrUzbnNXm9k3foLI5QNz
2FloVrBLHQImzCTiRLsjljUDYNupnamgrn1O0lACh66y3vumzCFkKrlm/VL89itplVgcplovBnaB
4RKaaLSUQCANNaqAIziE/uzWq/IFsVZGJHD9uj1a4uwbjCLRIN7U10PAvaWJ2q+c9/LxsIPTHQSc
XZiMbCiUl3ClguSDwVjHmTfLcdi4Eb7Yn0oEKqwMyrZErCA3mT2F8M4Pa56/IbvWMbk4QYpt9lN4
2zxBGShrEBjDR/VL1Y2l5P6MvUVuTVK5Awl/ixmrSTGef8e7xGzMbVHnm7CWnvIK7nlwnFn/5YLz
6PSsnyNIesyPbQJDxpaoaGde7wYiwDwrBGEyMhS6c5JSO960Iikw5jJhmcxQAYNt3vMWVBMNzs+M
kbzFs6OGB432BXg8Zqk9ABfGZpeQSZyncH08VgO0CFCZEzf23BiaXiPTaYcYCnMJdvLZTZ7kxyYC
nkZ76VyhOJVuo4gt2kwcmTzG0wSQ73TQWEzepotyrqnhjGDeMM60XMA+E7ZuN8McAbzHRV15+jMP
7vnbfxGJZRP/LPoW56maof+8z5ous0y17Ao8Gy/dYYQ/pQ2iJFosFizNP4hof0RYwuCHRZDLdOfh
cnOSGzMl7F2Zpcd38EbyiZc4i7kMBX7PTaHyxsSoDTeiR/5FG5cdtNGAdlI2ZwCyhNJOkXKthV6T
McAWnJeRWq2ADRbP42DhVmDRRUU7Y1hp1h8KvOEdDQ5dVpHjOTX0MDcMrzEZ6pT6OiPGqk4V26H+
NwkS/FJreE+Eyn19pmYy6pZeCWK3JDVKbAx7jCJ5t5fRahSrFgPWbzWi00iFuN62tWASL2HiClRG
ACGTNeSZksZIDrq3elsYJbKo+gMCuDp5yfmqx5DKzSstOHSwS515eUVTMC6+sRMpDWEljR8SNPuq
/M4vbbJgiHRwJU7KtwPhLGyUuzHu10NVCU6cpDFmeuiHvbroPt0+ldBlIhZo6SVYSVprjk1SIXxA
1I9vBRAgZtqpyPDSZtqoh/MD7sHJllVjmjhCOKWjNXJP+3hEoPLpj+QyWW/XQutC9wIX4AQAVGoh
KmPr9QurZU6Vmeuw2kNWjaNUQg3mCj58ArQmJOmqjvBDFIuI0ILKygNgNc4X0AiuNBXTxMwmkTDo
YMf6kQAtSrQmA4kFjWwRcYhmkxSMpxndIIErOwL0PDTx9vqRQdQalcqmDz5pGOUFNAIKMUcuXaE2
rGlxQ49I3h9hSHusEwWKKvPvHIIypp0uCmTAMs5hd3Xvgmi44lUx8r53QEq6v7Ih+02rt1hZ9k+X
a3LFKMrocXYtHBFxQJx1ANPtsfSOYiIfjSdC38D4V0WT8vKrDX6R6A7I83TGXgmsL+Xp48zeWJrI
+yWTQePJZX5hdcVDHf3JAy+XzChtKXCHP7OS7eQMSGocKygNvHaMmJvYELoiKqmVYXEQFvxKiE7G
YEkXjeI/zublJIBxuyCqlxFH1N6jUOW3IzzGO8B5tIcv2TKXKPTv8b97lOYpQXiqz6/plxWVZXBZ
7xDLeoq6eTbMq9y2rbActwJyMdSCK1LXUAjpqIMuadMAorR3rBN7rk3SVTjREEtSVlifuDfbFT/Q
YfOVECdmYGaG7PPZsMWBr5guoZJnZN+FBSGxzbIyoKci4wTR99j66I06sS0Y1QSX+4Pm1H83kn3T
xcEgHDweM1yLfvrfjeExSOL38lLHvlXk7O/MOWKWO1xrtvVCDFba8tRduzRlkJRQSqTZtR/18QXI
5GSlipPV933uVQtiMIA+hxVGEVTZ1WkNrHkI4gQuMRGEDyItVrWpde+ul2h5R6v+xuAq6NJ6g+bd
ui/uNPF06KWLZN8IFBjkMNmrjVGwV79HyJAkAJZJl2DB2gKCEOVZ+VJErrgX13CyH3JTX36MjbmS
bfJRVTEKErcgSqyN+qTNTsdb/HegHqeELkSCXeOK1h1AFbid2+pJxvqqOiOwjZRiUz6j7Cc2JeQ8
PJdF7fdKg+Axzz7QNVlDVTjniG9MHR5UA6RflGBHVqFrrVHDrI+cAW5EwqiptmR8dkK/0Kq0hflZ
Shqd0kjysM7S0tbiT2A/jbcnjulBgrUyWfBBx4ojRHFgYgN7Dvv2ZorQZobsx4k+H+FllzdOkmq2
61XppE4XRAVczpMqq4KF1ovqD1UQqXbbmJ8A/stcm7fg7kqI0RiL/40t8T5tJ/STOTH6HgLSHFa1
x5BiGQWtpKC2op93jKIvHno/znnN20Gm7PoO03BRFEcQrN3sOofP+/QcqOOy+A/I6Ll/dmFTPrXp
q1EQXtppdnQk16+uP8M8zpG1zT6pUrhQmrBpKWxOOpC0gRwthtbNFR3jNQI4Vft4PI00/LxuyjKB
6Hf4FRc+N/GZd3Q1Yvq61+1+hF0Yr36i58ij1eKHT3j0WgTjlCs+3GfRYd+JGUwQbm3jbVzVelPS
//6rKY8oNH/4jBg8UKK99KV5kwa2RjDMabFvRpSgsrH1GjyxNTda19L8qXNiFFj8qwo+SU2wRzms
Kc1rfWqlWwzmEV201LPpVv/cOwC+mfQUmRUt7WDLlcCgGCy/V4Pxgiv+PzhkUrVt72/8x3Tf+8MZ
UifZQICc2inS3CMfTZq64hl9rTzdq6ASc2xCGgFV8DLKtzVf5DKrS3C1OV9fo1XCttHkg1V8d2Fd
xfnNCeYv6hySkyMn9QgSqbGy5JCjsMywBUraEhk9/6KuT++ocOmB8UGFpaPnNu3xexARH60GrVAf
blzKaK/P32HSGIz4bPK95wPkZyOLn3WaMXS/lEcNFgF0l4oE0HJJS4uvdjDNczLQwN98SV13Cdwb
kbG84trAAgLEoL1SlKvDgUPTev0zfndKVnOCTYGwuLGi+U9hJXXfEJ72y8F5W31QAv1J7DzHQRPI
6iekX0uIAjBY+Fiu3XsfdwjSVXJC2IccgmnBrrrzf0PKR+2Kf7KZl1vsKylclnLLyjZ+ia5Cmmvz
H11iWAUXiXOad9FzH4Uyi8BEqf2CJs0jxX8yHyALqsflH8clElWcqR4fjQucuO2tvZXwLIXvtlvX
TCF5nEavfPrt+TRW7fGh9woaD9c2RkEz1Be3xgETFi2sHkc6O8iEcfs6JZTsg0L4I1AvTkWydDKW
XgbprzOSd1tICj4WTKUhHYKOTF9Ihvi3nlj3t/aiamGZzQKLRvVjnykdxZUX6Ry8xMHMRoJErieT
wrvVJ2TNBYDHTpTCe5Y5QQKbOFVQc99bNE9klLszD00iR6p1G4t9+xggsWEYd5d1o/5PUkR1GHA4
/NSc926xOqMbU1YSOmR9F2G7Uho+N47Lhs9lfhVnK5P3b626HO+Sd3TupnomTWO7uBsQIJplrJAr
Jy95gtKumkGCq+/5BqbxdkalzCzPaSAJin8W/Gz3oqGonGCW6JrO/Im2mKJiNOXgSD1jP/0suDqT
tjVvl4hJ+eCjaFIQCbsep1wOiXcmuaWOZ0UVGVCc8n2G5iGkrS8ujxt7Ny2RBIdLsgfV1VY4GfwV
oSTVCK7TN9BFWnv9Lw7gXYYymziGWf55y/14HKvb2+swX7VW87LnlIFTcM8W/wBrvCi/hRwLTEDz
vwfRlkbF9UhWMR4RQHRpqyh+rlAzNyLa2zfJidG/FVHXgbu5tGQebnq94nBVuJRSAaKksO43dk+W
kE56DMCdz3Hkr9M8qLS8BeFFSK79BQJ+yMJJfKlfdeIQJgMzaWEo8md9FP0uW+VpP8BF9hSw4Yjb
YpfXEvt+vnKWENk+jzc0sjZblNMWTVaWIExFHD8JxLjYfPEuhj55VJlEUBuT1U+V64B/sWIbqIcL
B1Id4EYyM60fsxMt+XLeuqUNiDeaC+N2+niSxG35cAN8lUijelCbn9Ag9XlHox8DKrFj5EO0uIu9
xVvsd3sFtroLifaTCuiE/6uvfod9GU07gSc5p9+2XKghGLB9DaMVlXhdrEfNJwaEqxurkDamIXRZ
R4gCgdeENZYUN17oyOhufGa5Dtu1wTvocgMKtyX9O2/tdX1zYbMmKnbybc1iXeWcjrYviBNVvlF+
JYab20RbrMa5zA4tQ8euUqwHGETJGRUDv662BWcDp+Dv1iDZPA3hh+YrB1cZXXZ5Mr1z9Rr1eVz8
waVNTke5g4yhVNT+N8h02OfawXU7AOdGuSKq443OuftNLtymn/YJg/tHXUVPw1uLrOSRNOUTac7C
mdETtyR/7uqax+qni97A4sfAnttDKCes0atAvUSQz2/8EAluILJGcs/GEdW8N2U9vw9WwwmwjJBa
Jpl7oWwW1e6y0HQ+QsR/8dIPABkb9i+eI5R3wNBcJpwcGOBuvFmcNQnoNVD2u/0mi9w6n/tHGSa5
8N7+6A28luJuqsVZUjLSUKmJzvmioSl5q61efUuF+ZctT7aakBzRfFYL1/lvPo2Igfz8eY4mcx3w
+54Hlw/TIpHo+8Nrj+NTmQa0pVhfzkhYHbMr5FGhOGMcbPNWm8/v70aeDAgP1TtnSCilhzhKUcgY
cNXqi9dkoara7eEyPGSQHssXmGj2xcilwv+y24hKDjF1BmHf5bWFXZmu9fmlB+TDePdZ/DvnQaDV
35Br6EeYvoy/gLIYygCX3OLc/eHrowuPWAA9GP8omIWVDGfa7zrRDY1tezkUN781sDnPV4VHx65y
CSkWbql44oL9sKwnmBPIn4Y5q9Tofn0YRVB12nE9NAW88leCvbYfFu8OTiWTmCutoiGFqSZgM8av
N+k6NZSLIyIFtfq5PWxoFP98h/41dBV5DAKPj4xq0Qr+Larb2UMjbAhwFBqarSpsc+mpdFNxu5Xt
6I4Js8pY83UUY3uMfqTJixueT5lR77+uX4tIUvX1TqlAo9pfll8+wdTMiZAlUUHx1vGyYuAUXKCt
u09mt8pGyPDmOBZQyZa5wZp6cUy/ApEt4P0jPGjOd8dYJUMmduLa1kHzby3enmUkBqSr4dRSUMzv
DOe76hAeE/0Q7M3K6d4z+mgGf7Wbv2vn4TL5TGC7zlzilqLP+8xcrMx9JTOiqAYhrhsHqiwF33Cd
vIIks4+hcTUfPPtKBXGTwvet/LPYPflwLCsipT+olsfJCMu6iEnc+PnGsQ8tQLUDHfi0wQi7v2mX
0qjXEx6fbY7hYOaXB6neoMNpi3FP2UsM8X3cjwDVF7z4uYgQNx+MBYMM/jAOGRkzc1LhD3ddjwIQ
j6WUi4L32i89hn2j172GqH963hTx5ov7MhLR4lNp9Nwqo3AgcbXP6X4tTkHHJe5QWqV7dP4FS7Fg
cRHCpTueM8kdej2YIIdpZQ+JMrQpGG1qaI+AtQsawbYCqcE5H97BMfw2/KEwyyP5ebpcEXGQzWmr
M4TKCjtxTnbRuB0SN0duU5K0UDyBDVB26Gsx75Dvui7v4UbHRpN8JNZSVRJ1V3Ge2X7ErVQiR8q4
1jw2yYxXkvdt3Y+7TcXpFF8aLoxfJuawvqrToEqzlRd+O23qF+pf9UP7a/SzYe9AiYyalUxS98Re
qs3Tsq2TPCTgbOzjGGnf4deQIGorhzrwXKM5Kzhrw6xHHnewBPnQGQfn8ZNej7Sfsae6FvGCZI9Z
GFTbzzFKgk11gsIYccke32h0Ii7BePndlNBtTlKDVU0Tqb93KTY68stLIjP6cj82TR2lH/SbhHn4
OA2QU11KOjz2oSRxc+F33RUUZn4DRkQxDTwOVWq/RzXYJrsqZ/OsWaINlKfkjQo9CKlMOLhMqrjM
ItR02LMm9HsQJdwEkOQi1y8EFcEXWfLihojpBfDo/rYPfcRpnHAJCW7E88NOF6gDG5sQorm3Jowi
9jcc1523FrOSKz921kCZ7TnmiIoZGoPXEoJo+JbQ2RLz1DifGRgBOSo3BQaFnkNtW34nLQAwO5LT
dlAdJCiGGa63a8VkibfSjlxpnaPSSDS1wdkD2Tsyx79NWMhIukhPqLtlrAz4RVgYPTN9hv3PVSs8
ouGirvFfSqsOgpY+IS8b7qgqUFj8wZ8k6zjvjrkY1plcWwFUcmE+bv4g0xlC2sVPsoPSQnsuB4pd
h0Fz9HB5Tmw3CewV/W9Y7G+mRofU5om0v0IDO7iXva4X2oGq+05Xs0FEivD/MX9DMroiQQQ1qmvX
u4j2z09Qq1n56etePolxrtVmG2BBPCJvYX1R6XZ42RbUYiXHGsCh2nbGH27UD+HAqtNEh9+M9Dmq
3gYlaqfhuooRwU5HIckiilpO1S2gtMZu6XlZstsX9t3w7W8sDhSq+X7S62LIg1K7sBD3eRygN18E
chryC9REcTweAxcHrMiz32WD5YrwEbVpY6pviBiaiKg+UPdqdCZMF0I46s3xQ4ZttqC+Pwy5A4S/
bzRCFJ8ly50pPPRWhaYy3LepgH7zpVYT6lN9PjbCnzbB8IbW8GETyNBxSZZQCQeOj4S97D1AmHke
P8G9wGL7trETamATpbCi3DUEbTNBEaR9/4AvxZ5eEF/XMtlD+Xzu4g6U7pA9ydfzJnTIjXT4HBWc
0ukwhEzrY2HbhQhb7C7r4BXvWOtLNqTKFUBFP+LxhtRHCHnLzdNjJH3aPaJRH7HAJA+T/hz2p/LP
oOKNTdcBfAzlRA/bOxptDjTWCdPUh7b8ZdiSwCtb5YFYJ+Obet4d49qg5BFLf7Gi4ijYHObDO7/p
DBw/PJRXU7MreVGVVo11np+KwyrDJw+0roQmt17LE/OfMve5efZyb8QKdtw9LzYvrgOo0iPdaND8
/DnS3h3npOkEgXWJ6uXdWhq7EsmbpPW2REfBmMeqwiQ2L9w1I/4hBVxgyqHTTEvXmP6L63NFGZ1x
r4cu0WHDVeqJZId9hPPeFqh9uw0x3XqWqHcH4rKxtmAnz9eIs2yPU1hT6b/YYOCTD5zrWGd6yomp
+0m1EqxRlbEqq+iFIeo1Npe4iLJdfgubbpqBBruOd/ePluB98c4Se2lSjNnkmav6qsZBAg07n4md
skvH1jp8DiN0pVEyw3e8LAdiKqFXxVYTvG6RxNAGqeGEQt6rPGLmqybauih5lti63n3fVjtI4fQ+
ORCMEAjVER+kNyvtWOno1w3fM/EK7VKvjTI5axPrUReKLg/rhH0A5WQ3NlDNvQvLTH3J1Xewcp8E
dC0YGzEaPINY9kfS0o+CB9kjEbEMcsVZOCBEVtHZzUy4QWRscAnz3r7IwpLH+BuhPlmEOLk+CYa5
z1ZOInxqXQEAAifbI47ah37rmPxQcPyxbBjybbKXVrxmb3p/jnh+fsiFhtFW6TujnufRlllHBy5w
6zhOVd5dp47zL3k44aE7xcF1S3RXZa9zcfVU4YG9+i2H0hODT6tJXknGD2Q/TjApcGgcI6hi2G9X
evaYGiGWa+/4XvNq58jJYobO21UXHDcRgE1ouoi3wlwu1adKL3rNP7UfLD2hgpC/245SHRFqw4hx
QpIq9sW6YqngA3tas099YHf3eIH3kI0OreTIEoRFYilbjdb1ox4EkrsqFb8z4Dy+GrejbQc6e5JC
P/MTqHvNZ8Kyzu+SkHNKTuk7y8t58zQi+1z/ccOHO8AOtwi2bgMsJrNDKzeJukIKCvhLhqVDV+Os
koYRMVo04x3AD0hExJ0g+iG5p9ppi+3r/U/yDHdLMDzD6RyYtqQRNbQZCrhzZJ+vnoL2kun4m5HE
8kWvEZj0Z8ZPOK1ZDtqYj+LyQOG3Y9aa5FvAU8IMCSLVSNoXh/q2mU+fUIh9QOi1J7oeTIMgld7F
PlujiIZKhHNAHsXXiCbtIDRYIIcwmIm6C74dhDjuLV4kPPJQAgne75KhsjRHQ+Pcg68b+gshmz3j
Qc64rADMcdIiYs9Q/0qzoHzRI0+0fOl2gblUc0XQWi0u6f7/f+9iRIN4+DJ3D7+LDv6iiLZDaZPg
+pvS+17/Dev5Hz3R9EQlMdpY3IvO41fQ0NyVb7jqXZusPIvVb+LH2tzuK/nBdu8bDep52dxX5QAD
+GjChqwCr9JFdMNjkkK/XBWxB//ObOlcGY/1hfP5Pbu3f4Zp3utTwI4TrcNabv23/rgs6w8xACqJ
aNU1Mr1JKBuqYkj4YdVprMixCxEaru765+b+60c17naBqA1ynMH+hzGO9sPJwJJ72AsnEU/lYQhO
cg/pElA6mO4NTvUZz5Qu2AfSq44Pi4XCSUdcbQ3/WRJBsA3yI8phoD8MMJytQBtB+NCog+zIJ4V8
GrmTiC7bCdKe6cyk24tvx1w8DMH/xnooxE/ei/uDyBQPI38mMKg5eAlUZv5uyWuJK+6vz4SaXQib
QOkIH7b8HI+xuLaXldQYEUI4kUNpyl1EytR6nybhJ3d5LV+Y1n2Nr8re7iTR6fcW5xe7m8ENbiM9
GEhEo+kQ9ASHsB+BWXwr2grq2t2cjsJKwl2tRi/I+8XlH5h8Wf9TPUxcPo97ibf8WB3g/jxndWf4
dg0fSt/Pn6xDNFgA8tPWotQGk2AHaxP1lEuJWi2cXXKfpnCF629E9D3BYjlQXUJPF0scwIfkoOO+
Mf7M5K2KKjuyvDomLIKKTOkpJEgXUaGcWTceCEk574UiT8CgrrMROSP/YQbyFOpE9JbAc2xpxsDh
Xnw570Ww8vLOsERjBbUdy8FEDMyNF/27wwxhXzvdQndWOH5u2sUJ2TwHAZcpBfp9YPmzC3JGIwJk
Gq4BV53oPTbb4Ib4xU2G3o1y5UoOSegN8Jv9Ip+H+h/oxdEhTNkkF4hkGLAZ7BoMx97vH9CnGS5R
TP8UWniW5SpPNQeLjVASgVjw1ivX5o+NpW+nY9VGOjui+0W6DmthrODjSceceIkgQodPYGqU2dL3
B19xTy989OxRMshclBk18HvjwXg8BYPs1TG4ItOqfk6nqryL3OmtEbTOzq8+Om+ZUlhR/mJiz1xK
KFk2ib49UDZF9DQ4ChrHYIrMWlfDAuEsgOGDb7ua+4MszBXNorXHetRg6UCO2tfRQOC7FIe4fvtS
MiDaox7NWpZsSEVsLyqGcC495EKqazUwRTDxDZmO4cVztdCkYmOSbFf1l+nR6Df9I5TwtLAy/Kkd
aVwX9M1yqQD6NPrUyyWZxyho5StFqyhZW4x9L0wR5xNKtIuzHW8MzLC5mlRR9QMRg2j3GRbAFdGa
nUBgUPZHv3SwXUEML8Hspl8E8CwWYlrZVZ67k3sZqrH8qbDVU2S+l77h0EkDTk9D9jzVSC2sW27Z
EW+LdROHIQZckNIb6LLa3TEPYQu8jmVYTS8wHq2gaMjaAQ4NxncuH6CK5Ikkw4h95iUbG7L05L7l
OVE/5ElYZIVESd4sYzMSElGVtWcGJCwvvkdfhZAN01dk/5Q7q0qnS4+eZsbVCV/dkUQ1e066qNur
NcCwfcRLEvO6vHEuj8EL8u6tEg1ghBfPmE7vmqQuIQwl6pDmuXEkWvpZ54fp0ZxJ4MjpPU3IJo9j
Bwpx4VQgI3W5HH5e4n0wJWj28nDJ3t9lrB93i6HfNkwW9radeE7TewbQZSJjphjNfnBxbDhno7kb
NCumKuTIfO+JbSDcp1O4eA2Q/Ddk9YGOC3F2CwJ2CGpYbMXv3sEJpg95f1Bxxx+IrVqMIQP7yM6p
39XCt9+WuDlEKk+bpJL39IvLPcnPczaAZlF168uceU5NNunvvAche/PHkWgPtzVc9U+6CA+MXsUN
J+HFh/8Yehqjz5CyMh9kg60z6MqC2DzJKkIE6xRPeFapxPh6nwMlqOVAN/DG5j++CdqCe7D8iBkC
DgmwM/yEO079pdgu78Ny2wXMUH2b2kk6BZVQs9GFMBE7bo41NYCc3p6rpQmY9+25PL3YdNd8ac0h
0LJGX2wKEIL2kGq1I9c8PmUEG3ca9owwBAtZk3r7dNtWCQWeeCciR9hU4kY8FPf4bsmSXC9zIZkS
9t8fxd0NW3pCS3qCjx8BGXus3Kz908J6uxX30BFJrKtqL6ZXtg95fBI5+Qi52DwnDpoM1uRtxyNs
4tUmGCw4WD7VORMbqcTkkfezjbbrXnw0AHU0AVTHf7DnI7na5ED2EVxPaOSK592riikz/tP1Y7Bk
ASM8f2gnW62DtW3ighLQ1glc4PQZ4iATsuaFfCa5EBpP4AbRIxlUSFiQK0usfDK7Bq66O7aSGh5M
CPzyIKyiPk7Po9EJfV4/M7zu5JNaylfQOds9Cwwv/4kHXlW4MwhVJZoPYKgwO4fokReXKDdyRHv4
wJPqLTQT+TyW4VjCFe2djF2qHqYhsjB1KNYfbErDH2w8ncVM+KBD1Z39LcLXJ/9g+v5v0I3CtMH4
x2o7nSo1xWnmYVjJYXMeC8Q3KvofH9sm9uZcPi2MBmWy1qp4msmx1Wuy5gwycFsvm+xp8E6qi99J
FegouuzT80Z6ucZjIvKkSxibOlU5bNVnemS3RhNLGKbiBw+wN9osrO/y5o059nyHbMTINHRTpyRP
u68wpZKzYma0q26gRtbHAbk3Pvai2DAOYePN5T+aMNGcm1Slv9JW6s6wx2UdPbsSCG7CF/2P53R6
5DCDGDas3ereTlekRtWcRYqSXZmoZmNS1laDznvy9Cj6Nmd2t1OyJCDGQjciHd2xTggOBAX2CIHm
a0frt+re84f1tR+EcGLt1MD4pwFalHB7OWNV3IQHZmNjG4XCFwa6mmCGtvw7sreR/qiV63aBgdUA
NCc03Jro5BFlZscJW89u3A+PMm/8yilHDhlw8UkONQWLDlcwxuFGSLDmN1SNx+cOmQ5f/w6lHX13
qNzGBU1rNnFqc0/L03TUpVyA/3V8yghP1PNckF1SwZ1+heyXkoybgpRsQoFDU9uDgyTPzztyF/Xg
wwPnIx5htqsrkmi8Sxul5OCec7ixed6jt+AUZyExtnnL7/p+vU19vrmKjLsTbWAih6HlhmVN8rjJ
399VzM9p/68dUKi2BzJMeBHKjYTY4acldCUZui3vc+y+X+seYmK47ch2TDOt0J9efX8tTkLraI1H
pKwVR/Kvoqtzquw3DxC+OHK3kbCLOhzMKEmYlbFZtqER4Cga6oh+7lYWAn7Be7YULp9gGAlSdVXv
AXE9C12cV1eriuOueemseftQX12sJl4qNrUi9lWloN8ZdZ7+oIHH13Ue1+Jz2ANud5iOIUrYbqCi
Zg18AH6tymeQOHcF8UrKrSLvUT3fGrVwoJBdgCnGK9iUiGdbZ7tlXZ9aa9aEfgSOJIXtOlUnZaJY
RoGX6FvRWB+aqjW82nbINZTWsYJCaP6A0v81vA8ZB3n35FROgwjIShursEIbdKWEJYBp1uG6Qy3l
MunGvpFqlM4nPEWxsrDcDdUH0AmwqUGsCmTEY5zWiQe32FVJ3nL4ahqXbCoBGWu+ZVnUEyM5LdOL
hstAeV/tjk4gR/DaL5v2QqcUHnN+Nk4ybNdZRei03IYTakFNr4yFI+MBBbhaylIjsaTFNVaKR/Nr
Y/+RkCJibz10vHl8K9+VQncV1WcEmX0cOmfMEt0f4jAdiG4CKn+7PSgF6KgkhAUE3QIF25GRsPqJ
TyPBdCvMQvZau8mKkLsABOuBdJivC2vnLFO89v/+rGQbccRSSbO/HcZCgzeHzNACdkQBj6MyUlaU
WZc1WJdyKCNtXtDaQaHetHrTUhBATtwaK0kvVLLaZFi0vbtE8rIF5FONiDgX4YGqalwLxe+Q7aDt
zZ62gan4oPDF2Lf/06bcFwMIBiti3eqetudnqe9BR672YjkSTAMe6jLYQlx7sVC4iXshxq95JtKh
t6ckEXoI6R6TmtZhTxc15GK22n9keapUNBMdE7xMKpWBsrV7jxnPTsqfTXXzIuJCJPUKpxCJdyEp
S/GjLliFAQVWql5BaSUjcd6icZuXtmkMr+x4V7cR8Pwv8hBd0PCLbVz4YQXqXp799GjptFwXcfEe
bi6abetgQCVjpJasdCId9KrnaibHur0Y1I9FDvubixtpgVQXs5keiYYDIX74Wd2sKTMps16MyHfR
305h0pjuFmNdwWGIaLFd9iBTGl3PF9e5iyXgDulhy5c6UqGJ26nUDRo/l9Pji0AamPhouyTCMHtv
0/QyYBzzCygN9HOCX9/UO76KsUNoP3ymHaZjzqrXPUSbZg0sPUZicCEkZBpJhGtd+tNuXLen4BSM
/+uTfKEC8BM5tOX+65Xc1F4Y5jgb+mXIo8WVFhwyT287hbNHAW8naQOEUf1wHmq2OufgRpQr+e9O
d9Fp6UV9P6zufJpeUkR5cI4e5ygerEBlElOhiAB+wVa5lXuLhAmZDpeYfkQF6rsB9liMjEBAGcL6
Dcr7OUYb0qv8SfIbHSqOPom9lbRKjM9wUnFvYe/qv/bR9RFeFGGRjcrtopKC8kmaEmDCgIIUarqW
SIKrm9mbSLQJ4GLUz77ZPpN3UBQyFQPY6eQktgB4LWCpUBZMG7WJ4Ob8sRlxfK4z3F1zXQXI5/9o
Y0hQk4IBnB1XO+iJduPXlPadhvSBE1ZV2QHdKpxmA5u+hSJuq3i4Rh9X64hdgMAEhdl7A/ulaI7f
MyP1U74d6ta55wrjMzb6ZyUKeoOehyPLPWTQ/k4bcJrwUWZOeaeJWJVpshecCFSylKfur+KUIzga
AipIhXYYtfG11z7RMsvho5xQexz4hxFZQDnHRLLyjqPWB6fdYGpJVcJ4447btdaYE+JT7KlzbjJn
cIbX7kYIVkHx1BmIMDy49Kt7NHKu5H97LVa4lmsdBSNV6sfEmLo3MQ9tq5hUKpOAZr6PeWPyzZr5
dgl0r1w3h/SS7ViWgJ56wwkKGcLAjgBjmNI3t/zuwtWL7OnCcfAKDqGd1zCwRXlAD28T58eJD8Tw
8u9FvFfn8EqshwbzGaWtrtT0zDVU+9sYPA1D0OhUtNU2ZOQrfBSTBarBg5l1lQ+r+osUSKMS7Qus
bGcO3yuiJ2IuHmsLloy16EDCcCWD/lLUF5yGZSfZvAkAHVVs7mgzr+CuyNKerP/nDUYS/eTV8Duu
43bl303b96WQ45ujCQHvdrpseQK9Qih6q9ge+SooBj82RzThtLT9YEa+fu1bYOPhBDUAS0XIpByE
gdVGF7WaaMmiIwY8vwBBJV00UwbijASsbk+qRKHvLba+cG+zif1vbiV7fykv97YD/gNlyCqZKDMh
yW0FqeWeA0v4OhQUXNB6+xdItcsabRzZnLKBmgEWaaeo+n/mRxjlGp2UqmtCpJ4AYj14Jg4fm8PJ
9lH0rrF7SgtFIqUtIqrYToieAnjW8aDu+ZLRKwfhDQ76xxldpQhZncmWuybt+IM7gG9yUQIXGz42
4xzbPkMQ7g57Qgx7t5d9kUJX4MD6bkD6901lkeeR2j7Y3FMPFhm0wqj1NUgep/GVBfGpEYiSK/Lr
/nTh8ItuB6d7cN3c/O0QI1JZG4VHNrTY5oYTIW2aN8dikJTOS2miUC4yzJ2KcP4rqFk0yVjcjEJT
I4nDymIPHQzcnpAnbSZBrPykZz+B98ovI2lOhncDysWpmAsu3JLuPSFl9BCePjDvq7s4/p0MgCzk
9yHIvhLVTohNQHNv9qAwiSkiairQY3QU6uTFWeKzBKw56NRscVVjwkTjKY3534wElO/SMG5PWevH
9o/i86e/juOdXT1kiBUZiu3KEb/updhK7fqBLetc0iLjIP17p/UZmoTAtIaNUua+oesTOIknKIz9
+1JFANXyf5I6VE9tHRbDQhvsRb6IrPuENZel1JIs/smaFLBht9+LfLMaRswChy8TKjrqsnC4vW7g
nZ9Mct9u1apx1LrChERe86iopIKDBJs9PbGUXUwwhyIoVbUQ5ZQxEGFRdF20ugqiUriwhIfBT6Pd
FMPcAxZMr5wckg0Ijj9ViqIiTUVc2/JaYAPq6gNTrzmWVg5OoMyDEEoxbQ5w5opoZRiy3JcFk0J3
h5Ou2094K0pIBj4faSVNqTV0MTXsHezbCVEPsC41s5VOb6Nz45WDCPlahuSXmvCm7Ge+7jWykTfD
qCVmfdcg4ygE25Cl34+M/OO/UBGj0vsAMr5cZ0yY/wqxnkdwxWchx+KBhZ5oEJxmMomn4gN2fnm+
UshIzQ3VxT/XoklqygdvtTAckKuBg4/KvNCirnJ9otMYRBo7xyz5co8jfLC4adxqv2HULjg6b+4u
BD6E6QvSfJEt5HfiPozL3r6/LCFwWjlSA4hwuDB9R/0khyC8lnmWtsHyJB74Tjbp7CRHZoN0fFPF
NjTePIWZktOgJTXOZL1tN2KqJXNC4nAx6Z5TuqazRDoj2Ye5JZs7X1dgwhm+JuhiPlQy2CCM4WFP
lJJXPjsuqabnF2a9xESGSqKd6isD6nRcA7xQSVVKX2w4H//QGgfEdA5agNCbKro6AisCE6mJ6kLY
mwZj1DKLpi6xJMUs6YrT4q45gEInaVWpNdAOz41sEU3val8S/bVZzo5V32w2RuqiwnQ2wY5i5Fhe
uAlWG3Ugg8D9m7ipvyp4KFBN1rCC9rqmSKxK056xK5b2cYYmdIFw4o5NhVpMrQBlrVHyAfyMrDo1
PHTIm5vy0fofr1P7lpCPnEaZaPXGlYo79bRnc/ihoB/8gVzx+yAxWS564/oLEU7q+9evlGnAuah+
dWKCu/QQKStI6Ip0nnTUhjSK1SZD4rCsEOpnypzsJSg1DzIHgiAAf1ceZIuw7TGeqyA5Y0oWyKo9
EaVn+uZ2e1POGI3Shc61F8OPChw9NT1wpljn7HACkGhdMBEevnqwDGnJ7NAEKUhAnwch1pQHlOF7
Z5aiqVMrkOpGhDlATwktdoKvbPUHqNxR6BAzPyvUdri5ctV+KzHGD8ydfA3kV/9KDbMIekd9Yl67
jSXerlOBVhyiVr+CBF87V9Vvgmkn3wVICjD+vcSKGcCWaIRn2BpCV8HMVSouD/Wdrxzuo7048g9Z
NGeZ0Fb/W//DFBy0M3Pxph109augJPrpqBa1lTTPeScbOfzmkoZYkU5Axw+fFjTXxoyz6TVHz9+P
yjzQ3YD3SlE4MO7fXKYTcPQnqSSYSKsUwODPCrIyxjFuIB4mtPwbdnMPC8fQWfshSESeWHO7aDGM
do52B/l3MLdYZZU8iAbBxlOJeHarKMd31/CN/7AJ1OxeJlm2G7qVaikcABWvOhtcXyo6yWKzjBER
BQtQL0Sxf8ZUMb9DVCi+YWtw30UE3HtXGwkGhBqBOO679Zx43BgIOqoRRp1gFo0rnXwn7yJn8Wau
ANS5a8phxQXg3lHxyyBaVN9SqIdOSVewzVDDPSFseDqzLVtqApbQv7oRwR5C7ZuJujTe0+iH3ci8
e5rxlOweWx04zMHLpusiijiSb3MY3dEmX/qFcXUpuhsdi7dWoke+4QZwUPPXJvhtz1doDzUytpLk
OBDPaSNCpSwaZvTfwgdpfqaKwaaH7rEMKp+g0bWVRlha2uIpozKFBY0fklbwD+ehB331pTsbwvkt
uN6sokzHG2x3AvfSuasg61wcG3pNtpnIEH6BiKVLAk89zGDCuz2mwHvAnAr1HUzLVpzxcgmV2SB+
Dm3Xe2HokmYwj+fhVQoPtq205z9VboM7yosP8a1ukLN1Kd2zg8XNwk9PmfjzswbPM9VshKA7jRnI
1EnAvXuSEIW4JUIdMq2PIHPDevlLCMC3pc0LmpOYYEhviHQ9Y+OAKtAOIFQGYxXDj0pzYxU2zWMZ
IFZrbzvSx4u9MorNhPK8K1f1WBY9AGFuD6UJ5U4DUzKaGbns4Q+d8wuAWVdSAKWD0ERLskbNB+eQ
kjj1WEWgD0tGMUWwit8AKdJpim5+PQwNImsSx46OGZVSn/GaX9nJCvTHfIWIN5Z9u4y+qItTvCqm
AtO+1sqONiW0DZOAcB2MN2a9AqVR9GBv/+5csfTp8U5d9LKgBVQbpk8vxU/+phfxCWCu7e5z8oNC
kUF+KNqJzuZIyOXcl80ZapxZAFPlRZIwml2hxBYJFszlx2aCI5Me4z+OUYAEHBESv/YjDQzNDjtt
vUv+1BF6A81CFEVsHe5K02zOov3OuMKaGNGM0o2U+c4Zv0VJi1yCeFoUB7AAXCTuyg8h68lV2U8S
JikeSUG7kg18tHKZQSLXIvl545CBnIuhXQP8/pJXUQZLSaJMFx19b5qjh+MKvlG5gGRjBJFFYh98
bJGLCwilhpNwTG1LiqQNLdJjEMDXqReO2lKy7n0QONEstCfS9O91rJd90ZTc10+ALyFpewWhNxrc
BGNWSnFimohPB44fXZFEG/AToTwwJnyA8s0BV/XL5tzf/xfAR+Z8XmWwNciiniB9gRa/CWKgZ4eO
dY42sqjGSzIJ6IkOUNgo61ML6Gvq3h5IJAcB1VAqoMwALBN/pfHNpHd+md5t306QCGlLQTUMojgK
bl35TgnTuugTcE6bohFpS0C4T0qKG+2CNJm8H4WoApIg68a+iLw/bMSx2fY4NmJw9ezPe6EWCfT+
y2yyWTAYlGtV/4Z6VyLeqqLM9B1dWC6LGy3jpMIccCFOZBesxw9KH1UilNtKwzULnX/VnVCKVZvU
CpAlGysAGnoCCAMaD9gtryh4BO1QaNTGuS44Z6WXcOHLOo6ysrjHItTw4HAgZajww6/LYYgIEFB+
eTNpVQ3bT8Wi+Z4hrnRRK2JTUci2ZMCmB5fkxBDmRhWHHt0J5IaCvO/tkNDh/bxz/PadxscDLQA+
I2/ZLsoxD/h3PylyLTveTcKrcno97wvci2PZPp0uV8Lw2dFZmIESdS4dffuj4n3JrdPM70sC2iN+
g1f/zrT/mM3srUV+TFilQx39IBGjWfzKW4zBjAkE/1liSF3kT2R3sRCkckYHJhUhbnX4olfiuuWg
XZoX6L91SGNvbQPJJzJzn1Lrfj+DPZ7tsXYFAPGxpZib8Q1D63RfhuP2wCTnQqLggVqSyGA64UPn
Lwc0Q6TX4zvUQtO5NajCp+tzv90uno9jLnaoCxUV0cg8mZD/OWDpJIXE04i55i181v1d+8w+00v3
riXoTu9rlgEltlcytVFAtMrf7zKQ5oESix1iFo+CVL96HJxrKVXw8JXAb/ru9a+WrEQRWQjK4QTm
34qgQfLNJQI78ryqJYHCCskp90s1v7QwwGs7SwiPafJ2oH+fusv6fgrw2MQn1Izbt/Q58kMXitvX
/s+oZtO0pc6WPrwXjNqyr4fsSnKlGN2PBY/4brCM/girR7U7gcqE0g2cvd9HJa9YwQ77okekai4/
VS8hZAj1M0cmGpCKGeu15Zq8uadKGIt50/7ByVozc90dFxO9cAlE4+FsmR8vIjeirCKny1d3V2WH
HBV79D2wHC0xhskg9e+n+RKyKLf7RkegdW4qUldGfCFQz9yH2olI5UfOKyElwlq+AzTfBRVYRMLc
xrVjRT6jrTiItY/T6JlWQS986wc0R1OC37cJzN486kXC02q4YtGtqeavyxOsLV8bAc7Ee48KCRvK
Oo9aCOfQvlOlPWoDReDcH/pc9Q7za4TZpLYBXu61NjkzUqxi+Si679pbc6dsZxBWyfElSIqEwC/A
lPd63s7Wr+/jnF7DsuomsffcLx2eF7Qsr1kJsQOrpOe1lDbvK97pUt2/UOFbYTcGVp1MG4t3exfn
eZzI4UZe8EZk5XvuMDjr0DBEPeBaHWc1cZZBYjuSjI2zTdhTl9ISlqC9oR9YXckJYlubB3jfaCSB
XQYM5FXJtKTPlvXP/po2lr3MbD+G9KvGlrNSiSK2ViwRQxngW2i+Jh689I8B5EH7/cyQX20WSj5o
Ux8l2jd4+mz7O00bVNkWm2ePqTVYHvj2oFkSu9GFbDX1FWkWcDjtboKYHN6EfeglTfYwcB/nLcep
sZBZvBhsyFjOxFMoHpybRuqqH0fQU2eO9zSnYltPl2GqJ9KaTKZG1Tg84J5lvJbDl80+eC818lfF
KiC2UeDTV9UfXEmR2TaqzqIx810y4wbynN2AktX+NzjT8LicOpK2u6e01bS/n+zerA8wnW3b2Zgc
hWAnPQwks5qs/tjItzRPyRxoZ6XEQwvg+OboLjpqbtIFJoc+6AY9S7yp7x//NdPVZfzvGOQLiukX
mPsCext/ZTRAlu63E4S09CchaJ1fy9saA6LnAIPyiB6bYfHEYSRu4OXHSm4DxqPMfDMkO6di9PCf
KYMvmDqlBfHT8FjDEo2jO/gyXkA4cj11vfmh/zXz6cGValj8iXHx27bz1FyOCxUlFKwRhJrYYWoI
ax81hcNXSC8Iq7iXcm/CluFoNWOGyGGXJ913zsLCgp7GrMwkbeUvGGd0o2znJE5dxTdZlNMt/f58
P234ARm+EIQcecZWB3x24ku5n6IhGVHKEG3TTUvA4PHrRJ2XIqg8xKuCv3uftRFupEUgxPl8xtky
H0Bx8Ko55UAcph+zyZUMYaJ7E5JqTxrhNPJr6vPYh0idlQfLJcxqkO8UnRp2OjoA3iRXitH1PX7X
FAPPZPHNvAw8xsqYRFK0ok7zxoAhlbjId+L9Wr4xMXPjCrR0/GoUjdWwkN3lkCx2fdXx0SHUpwZe
iNPkmSLyi5HGaP5NR54hTf8l7nDX2jTogatLoC/fwJdIe8dNKkjjwLRU125EyQok0C/k1s6sMDB0
KbT0by+kmioeSPnMpwq265lqfDC8WLSoe2lvqysKugp7SbtunuMpS5vWzLMAFYbDGuVtZfsjpClv
FLgUO267xm1QnAYL0XtYOtOxruObIy8Z98nnv3f5NVgWsaOfh+9KOAoMr1TxFrR8iB14D0L/dD/i
IlnWwHT+Yb2p56hpZlvXp6iHNwJfmV2EhM1FQbo4cwmVQcM1rtHzkZXFM1T9P7IzvVsW4qi/7Rnh
XBd8Q3umeyTNGPL9CF54lJ8dAuldX7JQ0e3NwwyYJ+IPFmqW0YyAvOdRx718Gbrsqsis9Bsb3oIf
aaD+q/Wm30xm/Avyr3RezqryhPlgJI7Pwjmnw1Sjcx5dAugtO+6upyJQGaC5LZNJNCqSu1h/igbx
D16IXSB9ke74JzKk1QlSxWX7V9wspjWkGPGsmrul4cmDJNXJ6KNvNx1zEY8OwszFHibF6hXSzTcI
K9U6GAI1rGNrys2z1AMJ6OQZx5tfUXrWGM7275tCdMwqVX5O4rJeVQnmzLKSEUNnD6fXS2yuLJJM
KMgxdJ89Gyfh4A4P2NVUGo2AuKxqlj6ZLtBNY5X0M5nT/Hm8/6lD54GDWRVU9GF7XCDORwas6T34
9Zu3Hj2ce9b9t8DQbCbAd4pB7/hjn2Cd93dn3m8oulRI7MXFAlK8EdcP3yrPpHelCPPZCMrZPC5D
oqV9WDNMrzAjczBSlQQJ+v+KpW3Um24hmySxnSAyKd3EztUmDBPcIZ6WhRDJkfvMN2XmrMXAm5cp
pyiEPanWRzMQfuIKdKbxokDaYDWfDLuoaCZxHSWbmfnroxGIkKtxlJ/P8QHKMKPY7m0wCjYF76QB
8IREOrFboYAK4EJG7R1FMBvkVp+adt6RnOrz6zAbMi8wA1iN7+6fIjeHM9SiCIHmQlE6TJATGD35
rfWSkWHgv9BilgF2a/ie9gf/Ixl7UHIukR4apHnN+CQvHDqyWiduQLhltjbQO7wDW/keUNHEAy3q
Us5+AWDK9vKByhjwSJY6876BSBkFqMNs4RC1javEho0fOn7U6dP3qbRgyL8v+vxYO0kpUEriIUgG
P3b2HzVUVHjWYrA0ERz3SGBSzCqap3ekNTCcoDFwfPSo/g894NMpv6cKBzN6LDCFJiq+J6L4BQJf
DMTtxkjHaGef24Xl8udXk+QpRNqzYrKjmwRcCcci8qcS/WklidP9ImoAKblJb4mq0SYL4CKM5dBI
ccj0gu/fT2Xo3pNvbQN4eZNiKIlArV1NpESfKNZUs5O04XkD1TkHfIg4ngyQ46WVHYCKaj2vTCN9
HqzXoa8CQpnvMaPDwF1wm9Vxw2jIyMmBEXJxMZV4c/qGhJoTNK1x+/umT0FB8HK23vhJm2MCRDZt
7p58YRuMuB9NlrJlzTVChK4t4DkEN7k5x1aXByV0u4U40m701lnbwtbD8JreIIoYytEGas9mxZOi
HC5HZ2cW2eopkeBjuIqLjO4AwquKukFMKJgeqnUgOknDWHEED968KLu7PVWCxEb5t6mb+0sVKNDV
H0Sf3T5cho5ctOF1BF7Rot9bA7JeaBcVVmL0Lo2w5caUgi6K3v5RcTBfOUlcqKgx/4luVa9nxfVx
TkwPJZkfbfJuuyTvvq3k7Kd6Dfog/9G5Ojy4akLjaqo6T8IVegBqivrkHGZFjj07+vt1/zp/b1Yy
YpRiBxrxi/4WVYi6gDcTS5OoGFFIcL37dBHp66/ihix9fAOV0phPAN/qbUtqhH6/PCIvDw5e/1xj
xTQ1MpKWTDyDJJdXk2raTayqwpnwYeJ4ozmaxD+Ba4HnVmvoHJBWM1Q7QeFSyRdbebWCo54WDYSw
EyrEIqmMVUKQHZ3eFtB132ONhH/X/IdAN4FywlsXcn1sxofkUjeJ5pTDL1hNb0YvjIBCRlFBHuOU
guSYFcVFXbczzD9VIK53mmbtc9C/2bM7MSDiHFr9xgMzfroUqL+BRYNPOKes/9pExx5yDoHey7sL
ZM8MIgm9QJ6A0/itC6xfCKQKJPpepJ9BZz0qMPMKaQW1H/901djOiipV/+DijgrTrPoSbdb5H11r
/FX09ev/M5OKu1EFxg00/QowTFmJEvquzEL060Zic+bXFIESXiB+sAteeuX5pnm7IrjiWLxYGGWi
Fzvsnc2e6zeqq6rW/lRMC5VxJPcpbz1Qudj1mddkKhwAc9YEct0rDpdZPvnH6EC20XqI3bXe8sLR
0YZQuqO3P3uytjW9f/tcafB/PxqXzHg+Rz+xFi6+EWMYtJyGW7UMGSpyW0lO6ugRD15rp7nTlI/b
k0sz0OgpUm3yd3/z9hCxI4c/bqw0oh1EJSQjfhLmZz5EBt2lsC4AnbeaHElXZCeUlbuagtaviiCl
2o6oO1Osbi8nwixKb5xMoEQW/VAmfi36QEDYGdXnp1NBzv+LVSVFcxfm0x7zscMVSJ/mIy43cQeH
Q/vQOjV3PVhF46mdufOTEeGl8hULqTI6QPjYh5adSG+rQ3u2cYeCPvQFK9ipDl1qnnbYNpjWxXd7
nHVHXHZSllPGB/6viKnWgWYvdV4qsEwBXDMGUNY0Kyke4OiMMrab5pD7ok14rXhHboVizQYrz3/h
lZYt9kDIMfvF5cA7y6cyLha6n2xsaxAsxB3SuQpqrzUZfHCnu8WiXsByOa/J1t3ZcJXAr7DKcQJh
VgLalbC0H19s5rCngNDuHYlZgb4EHOH0COdjxsPN0xengXcxJU9sgMX79IBYrhh0HeEkQKL29a0T
k5r5yeQWATpakOpLrbK2Y3hIhJJvMDu7zvRblrVLn1t5oJDGo2XvVv60cFcjhjpaQOram/YZMce1
ap0KkbKGf8nL06hGC0SURkWq1bDknzxxVQoO9nSx09dP9aa8wbnjCG0LrIo29G3gykYNUBnEyomx
nvE/UtaoI7zUcMVfXQcZ4583XBhIdjZRUrZ1XTns7Owb9ph9dlCXyQwo/w45Gn95Xy+iJ/Vjsjth
hAi74Yr/1fnmOz2xI4vnF/R7AGcBghgXX1F4eGPcU9c+NvLbwM3s3J5KeZahmJts1nDmyZ838War
iJS736478lmM94NzKqNKW8dBzckTWGGAnfMHtHK8CiYgaHlMxVdcr7GAx77sqVQ+uERJ93QoxsaA
HyT3OHbFdeoy/ahJPlB5VGXa0N4bEKqspECMNHxdRDg9PphAWAUZ9LqZATEc/v6ozT3hdy2aTKQT
MBOOZt8lR4qGWF3jvHGdnE5EmDhy98+rJRLYXvxDylTVfqnipJD6ofpi6REBts4n7Mk1n8K+1+TH
Q6pvk/m3apdYlcvz3IOgyQcjoc0EhyY0xWyjbwGBZ5Sy1Z4NCRC8NJu8WqYX9LTVYxHnTqTTAE5C
JNniJQ2thYuHXE4MKr+9bxihOo4VimroKEJiPOvtd1QcxZSAeRjOIy4FEcYZiIDI3OgcI6hvPb5x
sP23V0BgJU3a1yF+6oPE3j168zrYZoRZDBUANUUIXLBbupFo8qnZKlhu3mDwEEQFIiG2AyWWEKvV
rRmx+2BnQEm3EhjSwbxvjshRwbkwUnVrQC79vAO59MzkaU1itB8VbBYSLnRUgA9hTjPMbA4n12UO
w3MDTWWNVtMHoF6SaTnlZV0fKYwDqNUjFonEUafI5lnLpn9XYSuE14Ru/fxbLGvSOpejKFWDdizb
uo87EphsgegHnrqtuqTe+cfYwGhZrYaNVSMhK4n8QuxLC/jSRp16JgShxToPaY9zDi7NtM7ItwYW
n06KPC4DMvvPkLZVMbBhWHw+yAAyDpJFG1WROKKPXf0q/2PwlQJaJXmp7TEry4tQgo811QF5ce1+
ZFBoCEAAqY9vTK5HQzrpgtNjyHyhvvXjF/IqshJ/uxbCJV56A6WIBEplp/0Q6/3I6SDiZY6c45IV
MhYUf0QOnE66iit4MdEDwjjTZSXrla/OTtY4dWf4OyKl/jb1IfP366woik2QueMpIA+TWwxNeAcy
dXgB23iVKefXPiG0Q0R726oEH+JTs1jx5vg4VOZW/9LT2ENwBUkG4oWMxZB+QR6XK3Bakm8fO4lM
+crCetHzlNbTGWpx2mACHrAl8jzKlaVbd85ofY2qzaa5b2RbztPwZ5VrVxgG5r/nCNfWMbLhBhy5
ulhVQ2Ia3IIiRlVfWfIFN1QkbdBBzdn6qEIM3G/X2sSTku68zlsy4g2N7nn5P9Q7OgirLZgePzJ4
PMUKE7olo9oDtEPPDHojE/NtATYo8l7k36SC75cUQm2zUpEcWEd336NwmzIf9OnLIKRVwXIPz0Bx
nU2Jtp58/4X8CaFJuueXSogb/4QJ5KBKIkwB9O9VYhWCKEgsg/EMwUGPBEPZgH9Z5wLObdkFRlwI
krPQNH0tuikn6B6QGYx1y7PASoB/2IFo7bdkGq9KbMIAvHxV0NmLf93h+c5QOsMcc9tcqgWzINc2
oGw3NwByHkR+7NVTrpoNtsHsVuQxw3faTb/hdw+vlaJIQa5ilHun0uCRe5vdaN7boszSP2FtOx23
+d+C7re0F83Zwedil6sCLiO0fwHSPzppMRBFgqnHe7/kkjdKLUSIFFa2tjLgcFR1kdHohTwMNN8k
/yKaHOkerYRidEQA2q1Hl6+e9mEPpQ7WkTEJRY15O7+iceRcOLPhebEzdswH04Gx1pMtyj/utPtT
CD771Yfto54Up4KAX4htY0S/5d94T8VSIwAeQn5ZsQ7jSXGwZItoVnJgdp46hf1GmLhVfHlIw1I6
w2uyjnJY6rs8U31RwTDzWlSimTtDaeV27kgnsFz7R7B4UOadxHMrvWwucUFp+3POpnUXO8KaXtg6
m9GpLeaLZyGwjSzYmYRQAwXTrkFBU/7fUw6/mXe/LxIUqcb2ZipvotzDtsBIO/6ApKBSwQx7wou2
EGT/Fqkr2n+B8YUlFMqOvUSUvm/uUkyVY6Y6BuY4gohR6o7aebwFp2unU9kqC0wq4NGjC6q62ss2
GwonRnmNOc4slIBoP+zXxP2Y6V6xumqE4gqUh4N0kcQA637cuCpBoGSmeYS3viWRlNspmcBOw/Mn
ak+GlaMvo/V/Uq4gy2Rht0mKa4I9LyIqCbDOeLJe1kyTnnepdPx7Ehez7RtJK7Z3WTFculsaRLSs
1Ll7bJk9TtMQeiHXRMQFW5TUzwnpiE9LtbdFS9Pf4l8ms8WbsECBNG4Pv2JuBwzIJWCQEnzWLhMk
Al6HAJJYc8y6Osqdt8GaOCF/L1XqFaupONFqrB6pHrddQ3PPhzGdgVXMk24hneJRrt7mZ4kWKbmg
qly265Ly1otxG4l31CZdswYufhQZTub3rPVfXb1GwistNkuScSrGc1R/Ojrtl6XxQSyEtusWbZNT
BeFC87p5+SUr+qZ8naXFpkiKcWpr1c/H0fjgBaxPxE45ZbdvffVb+E+k1HnDn9eC6N/34WRbL5F2
lt5KJujaHvSHAPeZObe35iOLeqFcLwsBZAdduWCgLZ9sbUe4BJBIKYzH0Nfi6JWACTksPjWmyOgs
J47VcInFDNp1zQN+8eeqth8RLxzadCWSoVPrlXPkogldPAg7c+/QG59QlfAb5Dr6hV9gBpTDpUKg
0oMzPtgmuwLQ9cOlKnWsbyLnKKktV8q+LEUl+obqCpoRNvoBSlJDXPL2ixtnHnKrJ8DbptpB/38g
0NjU4lB+ZvBTTtfChjPsmaRJDSHgX7WW0Yo9Bb1j6HdDVwdPPBsPSuzbrdkYSdAySoLu5RtA6C3v
ZLD3IRMG6vSnU5M9eOJAFNo+BH+YG6XmyzVLIgWwJNVEYfT1tmKO0z3qPSleO/Bu8Mj4ukus5UPs
L15mNQk6b90OcijeG0YZBR92AFZFLCPWSp3BdNoQxg6GxyA41FxJbRLdcDV+Z4ODKXB4E8RHD/vy
3XQ0owSd//EUGY2bLQAHsLLbz8g4nWH3e++rs+z0lXmfv+UBcD72B86vO3Nkgd6b1UbkhXqGBvwd
V8pOB0i61wSpV2pI/Qo0fUF5ZEsfhECHoxF25ApGu8M2fGCBhvxGn3GIkNyHzSoFbjvCeScN8zcj
WW7qyOiDVETUkSXFDya9ophSSq8XIVMREg/UVrs9xlPO184F+QEmhzgI2fsbZHvbzsMVe48PRRwr
Qx7Da99KU6xkNW4nkq033g1lFOuU7vFfSVSjyEnJBNLKZvPjTYxpQAe/+sLNpw+IALubMDAO1bWK
tIB+n8p8UxqvEQh2cRNHsEJzC/k7iSfCupL+uXTPvJWlLDiGexi8q5hagIdLrbZIWApHvcsbDOKa
PdpFBCUnGLJ3mB2MXZglOA/1AcloGX/k63S8c8djHCLqL+m+flEyM7U4IKIER9Ee3s4RkMWPNutO
gDj/w4kNB/u1M4sLdrpWjYLreD6XOFscnm4x5UhlpRhsWzosDqKoiVWc3XDBERfWMRP+W2EAxlfU
DWWX6/XBobjOclShXeOIrDXlDE+XCK65cTehaZc3nVb5ANcaEZLsQCC3aRiMM0O6322uXWCumjlD
68japSt/E9tn6sYUIRU9yGEtmyv9774MnQZAgWQrwF2j6dc9EHUoBjORmd6b5HlD+eFXEZRBIbCY
sPVqNPFDOeMpJN0BFjqcYzKAf0ulx2tF1vyyWBpE/SwEY21QQbtnkhiwyCis2vySJibRwLMQ1fob
B5F0r11dp0shqiu8wbARygd/6uIa/6IezqhmrpXfzoSksDAOGibiSUsqMP3aml54adsbeOhKFxZy
dNkRqjzA3f9Y65CpNAAk8itC7MEP3Ew3f6T/X8KYJGXkBaICTnI/XKbbWYk7KyaueE7ssswrIBAH
BPNIPAPGhJJG8EHJw/W9eXbkt8e9+QTFuDvM3yRrg/08Fhk62QhTC0LCFllIpcp/6GYqeTbTE4Ol
nApCeL2aNaxT09On0Wl/yMW/pEGjlrl2lHigq63hngvZcq8WiHQmanasP1s8uLJOkG8RoR24ex+C
wN8ls1CDq2Ld4SQwSIKkONKhIOIau7xX2mBqr6qQJhMAbyO89QKum7aWkqxyM17YQ5GIoV1i7pmT
9PGLS27LgI81+vKZ1BedtIMlMPnhF+/NA4qtBfrbRC80ihiJ57OOWT7pWjQEBDSW62Mt8mvk/1Op
o9hS75giyCgRS+TbdNZ+UUZQcAJWAfHSOz9jJd3DTmkEK2u3faPhvi0ZyQoPqAsxE2Go+BJX7h2T
lkxJshpm/36qgrNt2PjCS3pceXCRuhXuRRQznVpw/+kcSs17AkS8eb0No8DUITaYzhlL58YDISnP
PZoKKbxZKoCxpkqLM/Y0wk21T82zhYupCQkcld1BS2dGHkMW6oy3KZMeSKR8OIB++c9vC+gbFQYA
fZ+UMsiDTLTtwa/b4+UGpqG3UEGwGKBvhdFk1eE2Wyy2pEU1S6QtL1XldpoxEOqndslDu8FN/Sh1
Xe7uRRnReDs3SJhtTlQdhUUDyUBgIbNyvqremB3/ZVL1WnPmoeNyd5at8eKaMiOgZbnQnOe5JPvf
AbNSLfhoKVjbH8i1xENX8O1dipxBJ3IP87riideyAyPLbVTz0HTN350z+A39+E9D7g8CPKASNnvr
T8qaDqzzNEo9/sXq8ARBKxjd5sluaL5rIQYMnDAus8FHuF+6emqO3YihS2bOjPHq9bNAZilRAzFT
rV1LVh7IXmuUPrDZ/q5CA27jDj0WCfUWo+IkbEIqglcPFEJog2cU1PyUl33Kst8F9gOWe95fPq10
1rOMGwLFFJC9VZdj7E1w8Z7DFlw8VOLo6+GZJyOEOy+i9uvurMKRv+VW4Tflp+BMNcpXIpIJIms5
F5P7DNKigvyLOfhhzvSc/hlmWxZ9vPtU98EIMM33RnGIITw0/VfBx2TpvXY9QFAXX9iQHl4qAS7f
Mwb8xn/AQf7D/uuA0AHbeKJLSYJYtCEKc0rhDYJWqUjfoxFVOG+ZFcBE7M1f3Qw0QWJ9HP6mc/pJ
hAL764JBurY6w25uxlGpMoFkjKHnVr7VMhhV8xAQqS5iKdxBXOBtXG0YBmyhXj9lpy5MDd8zI9Ai
fPYxMfKebIvTMNC/RbYKg39Pn8j0sgkXuplhQHVuW/41lbHCpZobliJ74Ocjic8mkTZfRvK+4OlR
PyVzQPVRsKAveSwP+YPULTIHWrcIHsMkgNIAOZjYvmxI8popKwNrukxDNbzY/SWq8+kEYqLvtIga
ETngnoejH+87xHptiXU5Xj5grrLpLWyNnj4EQn6ljkSEu+4m0ENu3yvTaglB2LtoQdSLVcAYSwTv
sm/D0Bl0k7lcM4jiOST/zPheUied7OtYnIPLaE99eznLmfB/rlURbdn21geFO8/Uvpu8Ot87GJOo
Ckjtt0dWLBAs+nURvGUnX1lrHSABnxdLq0J6u8DsvozMY+o5Q1tVoQcFjT5Ez63Ec5MrxRPmRgUA
ncMV4G6q9Eq88ymYxGFjRasjjClwPgG9kUtCRsG6IAAeNcQ1E7QhToq/GZNXG8Gmx/UYRLw1Kx93
IkMsseV2vD+8EDUh02TXqmX6cNlBmsH3pnbgi2Qu8LUYJA4f/P5zhj5eGcBTeJWASWncM8/lEjGe
0Jw+HYzEAXtlNeKvkDie8zeU3gYbY5jmaQw6TJ+IjidYopgPdydhAXgE/PvpaAylUJacv+DDMqSZ
TYDb5UaGkWABWLiRrbJoAIQdfEsQZ2KIdvNo22RGivSSy3YjBPDOWe12URwpztGkx9auFddyRBB0
Fck64Mk5XjhlEk4dE4L6XM2uPA2bfk6Pjf1jjx1fj56b+P6ZZdxClEr8ePikupOXyyFeKopTiLn5
9fdu2rGQ2yLHMh//odltsXOV6BiwMQjWB2a+vyoXvMyaLMtWFJDzl6rB+ssTUpMs7UIl4BJ/wfKd
K9igwbRVx4O3b51AbQq98oEprEB5/ebiEcVhuFYiCChT96feezoHQeJMsHWyyz+fs7OzMu+9rQay
dovbdUA/QQu0XH0VhfQ/5/4/6oK4dIR4et7HNufAjxLktg7FJTRDPbsdFELvBUYg6UDUFLNGpCL5
G6ii24fFZCtfld4zBwo8Aw323TfkZu8+ifaupxP+XfGtLzLK2JIsi9t9ypRY/ASEH9x6fkq7B6dF
HWe4jCviIqhHMRVQAT8qnVvDd7M+y6YP1FW9jNculFeVA+BKLhPUySWnc3cI0KROZidT88y1suIx
ddXedA+VunEVElZn0qCcoQGbrYVKFVoarbIcjdsRn5Ii8W9C2m+kJaxixZh7N9ECKJUFF+hNccPl
ceQC+DJ0vQAwqf2SQz/3lcgQ56iT+2aWENmjZrefPay234+XoDOQXtKQlDrsbsIne6IkIV1VS74A
5fEt+nnjhetmztV8DaM/V13Ne0AFi0mZtdu7/NJVPzRyW/NTcTfMcry1cppLLDm8SvEHD3Ys0m82
S+EXGdSJvhy+WZQlsgbctL5MxGTSPtQZHuPDbeJH4xwfsTxiv0XraBTlruTju+Io1l9ztpu0imSG
g7EeedNRTqwXkC+AHH4TbQMM5sQUEDzSd5VjOIdZdc0H1pp3i8vbIB8WOkkV/JfOkDihEXx1KZNd
qquUNUuV1Jihg81dggEKqG/s7eqa4Za7W4p4bbTqvkbpwxd8XszV3sNfEn5hROqQAdUZkb6b8Ibg
nhw42Kmu/qT36msEIIAO9QSlrBLdno6p/YNEExYUuQbpvuomCNdSZTi0bqj/L6M1zrupXBBFLMEI
5DM1X6ih8L6ypaLDRnts1KaAz3yMWVZDIW9mQVq/E/XOmIUhQmSTnWIAYKj9U2raL/KDyc2YV9w1
a1k4Ud/ez7Qr/PGp7L+TO1uIjP6Nlw27/MWBU4eD1qXSFUEULDyRJPkrD7lQxRFUwxXE7He69jqf
34lrmYCVn+ZcUzpVABcq2Yf4XeGbqnA0ZNIShn80HvEBDXulOAhei+GbLSq2T4Csu08t/SjtGehU
ms8qJzpgD6ENGariDyfp1TW/golZ9yOFybrnv1hNWZeWzCr+FPg4r0c0dqoHm3SKLAIlV3aVSNug
lhWSYJXfkarcKpioJ8Nht0eR1pzh+ecSZm6MR7dBSmTSljD2itATxmCk5T4uiPHgVLVbdo8m4DCn
/UJ5/2W5pECNVGNlhrdxnQrs25RrYSDnHNrV7qHfQ53fBcy+KkUDWswRdjAn0YqDkMHhfqRDTXwJ
zfnm6ZIQHhAoij+gAUqSb3Y2jw/9vqV0S/G2z42BV/gydyfoBqAzH8VxUwieWr4pWP+uFaFDRT0W
2Ni9JXJdEGGf/Eb9B8jrC76mGU2B1j/nchUGqr2QXt0uJa3vBao5I76eFp9GUC1H6VHXxNkUl2uN
ZYW0Fg0q+Fxt00bweE9a+gAMp855MZtV6KE+50qeq4Wly5FC39q/s5mY8HrXLxnHYbulyHhgOB9o
TKeDGZmDRvlBZswOh5e7nuq2UhGK295Am7guUvOLDFLXvUNqtziQa+GRJglgRN7hj2IfLRyfvOGp
Vl2HVH7pNVVgeVo0bEGeQgarAN88HtzcrMjKiDKsCVBYObqypOzQJRO8gcLII76Acg1I1ueZs2rB
J7HueoMIw+hF3LakDeN9/11ymlEyoEE4fjAgFzOHJH5CLiB8sgl3QVFpZtnOT5V+EnjsDsS6Yvvz
bU6qJ7N3fal7jyat+WXlMAyLfYHwzVSEXQzk4PzI0gHkOzdB9eM0XSQwmuYwpIvLbGoC2VKIV6kd
KEKVNhuxJfdI1XVAMvzXzd8iBQg65yif8doZFYWFsfxUzFDIp72Ew4IVU2OBvECXFYI7BFQ37fNQ
+X0xNZMp8hb4NgwMkWEN8nsGMotbcJT/0Oh7morbTPqoOcVXqq/pqsqPm+TziEk+9ikd75Llp34Y
SEQnrYFPvSlwDzA25kaAufjjCDX1K7ChEDe5soXr/AOt2u7TPHk7+N9iZYlW4zp4UjDyHOAyZHDY
zOimF2x+Sm4AOqrhjHhEeKKZFWSBrzmK01q6RY+APrO2bzcg2+CkdzxcUJh08T09IV+XO7WUcFK3
k3N9F1qh/F8eanCUvfGcIJcWsblu2+vGCSx4WkUZGeyVl+8jR95/EvtHSC0o3XNUZo3yh+MIoDBV
iOfbfePes4/Y/HlAAtK+FIc9+qnH2xryUAezi+PwFLK/4oZZbVazoOVFhtppG3M6DawdY7I7E/Z9
BA0ukb/1+sKxGm8UNXPvcO3iWh0FQcIqDDdyqiiNOgFE0f+ZOICmek9ceU2qecT9JoD3WCoFgVBA
S8OC81tgMLSCRne80HJmvZ65WlHjpMFvPxn5JWDax+f4zZdCQXbMq9Z7Xps9OcY9mat4gjOvfQ6P
IJTwcQBj3HBX+natzudojlHyEzJXjSF5K+7gI+qi28avSunHeEXelcZ3uai3DcCrhy5SjwMmCb8y
XiD9hpUXASk7jGaaP8QCxZi/WCTonDoNuJRCPg9U+kReD7d9zt4BTtwWD/MHxmwBqfABbjAGO/hS
VnlnzEcrlRNus7CpId5RPbiy0FWyb2U727tBnfnLasZow3j9s4O69DI2bz0XaHT7tDQoadqxb7GA
vBsJ4C9UamWA3QdwAsxeG4aci7dDZ+QCdEU4FrCtvLTOQNYWiGk4taRJXOL8kARsjo/hzG0PcNPs
CZENWTR/gHHofVuct1Zh4K8Y1UJHTR4qzNpGVHoITYYTvQWzQn/AzBqXMHWbWfkrLdOu/V+zJGXF
nRPnneCWozqrR3pVgfC01cVOo50psOf+LKwAFnJ2sXIwwv1OVauCYOj47af7sgg4XZqz4YWiouKK
PX/W3r+fjklUuKnRBmyU9/4wuU+2FHAWAj5Yga04e2ksQx7688OUGAiYdBk5BKBi51cfxzpZOQWU
G2U26WWlwzxMt9Rj2b/z79MVvwVeiY2fFSKnzl3ockgHernnaYUdDyBYxRUJ1YgPxCzocQBukp0W
swLntkghPIkVttc77EHxBy555pympSkvvut+9FpUfQNsDYHptPjnzGV0L2zIufm+MfV24owuB8P8
ZBzH0fmOcY1O3LISAsEiW24xSu1WeKcqpgP2vn3eoAlVZNxXSuA8V3IjUee+smK8UYMNusSFDjQD
rnL6FWH1Dpa6xPIdt1M2NV8O00OYPcmSrgsTQlcXUO2DIdPSLAFCCVPNVYHP0gzp8+t6Cgt1b+9u
eGt9YthnYZP3ASAy8wSdJiqy+zIgNWlKiTpqDWRHjYOVNjUqHgVsB/C5VBh5kWoxMO0saypCmMrz
+orcEN4bA82+IyoO2+tY329CSM/Lpzc/mroNAYwUNcleu6nIkGAW9NOQnez4MPZw1yl2r3itK+Fh
QOc7cXDZ0eR6goDD4kq3Na/pP9ZjL+O13n6XQyeNZu8t7FgOX6yna/0YdYoOJUMR/uAGABkhv3Qw
JB8zmzwmkjg1L6omVhS5ffVKKHJYTMGBr/nsHW9t+KHlwuE5bo87V0tXGBhsuWKLWNazESUa7W1I
zgiK7zdycAQDJZRnpBXDtThSs6Jlvg/Z6RU/Igrw/Ce/uOCCQO3WImbWsCugzqs1RZvQF3R1wRrZ
d6dNc6JbBrXVl2UBa17ZCcOfXl/9yHJG6/8Shf3uzEVq8e6wSzZF9aIPojiRSRRYxLKfDFfipuJ3
TmIJ8US77IxUIfEQuksewhODsKA1cbDMzzOzwtLK9CXuJpMC75apEnqf37ibePW2heDJaNkOJPdt
LdKaKjxVlM3m+OMER6fxOjvEDDGBL+3+Q+2EnEoLgVuHz8WipkyXGkEq8jq7sT0K5NN3fRd2l8N4
1OZ85YVIuLcb3e4RaJPfasfymEWhOqMKKbdNB/y7JkSpQiNlHL0O0Z5VMBzHuABEjreq5PVKxszG
LpFDcC1T30L9G64CNCY+6ku09NvVXeh+65sZ4wmZGiEQ+2IJRvxhvAc4PQeVhYL9BYWM0q0lClwU
CPRbkFyvIVrN9OPRS2GvvN+rtDHGhbzrA2yjzZMCAxbpu/Ur0kKkxUXLlTuTZyyNFh2sKS01hFxw
vj+4yaNK+A81ME0WxR2CxUxtGY9wtR3snDViBHdDvei+ijdX5s+GJfMVS03Yh2BZi3Vl7b9+Kj0W
6J8qMavwxxiaxc2hCcRcyBjMALwv65GdCEIOTq/lgZRDXCCltLMriI4vZBJQ7pcUDz3FfMEBJwyt
uCy66oR9vbvFRE1QUzypjVVTGZfvyfJdEBImAB5HQDh1cQi/uEUAaagi8GjXitCoVPh57b7W/jM/
+kxdGTYDC/EquNpkFzf/aDnHgbrJNEBObd40R6AreOdqBbnwqq/903Ej0OP5M5hcarsrO4S1CwwI
wN76X82wg5SyowBhZ+K5dZcwDOO2XvplJ624s/q7rKea5GOoLVdkv6Xd6GHx/jWRqhnPndPB5ius
apFgmLbNREW0Vhm/9nL6AA8ARYSyrqNvUc8DqxTVF4dr0ubl4iZzNW1eDuW7zjdLDWhspjy+5zB3
pK4rpWJ7QwUbv+Wmln8JgK0J8t1nTZTeiA2z6EhHLYymT5PC6aPuQ4Mlh8+LAJtFR8cB8mCVIQEA
KrQV/8R+nQBbE8YHilSKDIMJcNrxjh8Zx59DndVTfVAtW7M2S4em+x7ZF3RB/Gsy1r9cN/XSpvVO
PvbRI9a5SOoOrld0PMZ6qZqlS05Ey41+NjcWGNmnGvpTYZ7lSr2YWb8IknrnkwQz5vBLaV0UYSma
rtEIPakxxD4cOhOYhwiWuHoFzxxjDhWuMETIcPFIae2mQ65slgddexZ+Lamj4KPUahFZB/JDilaB
2apXBjbtdjlrPBY+B+8PsGKCObsNa0Ubz70dLfSvOnCVqubUKylPnCHNTPYs5dDHVYQ2GzTC81bd
SMB1UMXy2BQ9/l1nmM8XqVnC6XO5b8PJvT4j7srpta1gYH60mX5af6QXdCPx/TBSHXnE3TugpcpV
jjR090czE1I/o0Uw1ouFzY8dxb5itKkV2wu0LDoeeIGsZkJ9+M2sDSFXWma8qufbvghhhHoZBCwh
vjg/Gm1i8SsblYKjCFqGjx9J2jkLjHKiAsVJBqydAEBGu7ev8SZNw5mN3dSL2UIBORfx9Pcqk20a
BiCM6730MKds7ZiTGP3bHrWTC9jFHAGTtxErab7y2ygAv2KuxM1/NOP1Wzf5x798HGbQFsxq6AYW
c0hGFNEOkfEgqqatC2FZCI9frP0r1YyWHlFV+TkY41NpFGkIEBHu1nsjHd0MJaL+S1oKf/b0rFHk
wvPIGr5cnoSeiYYMYUiatWopk1ZwTbw+btBtClB+zSY6th8/JkFsHVv1XFCo2Zy8a4957Wls/O3h
TIbhNYLjnqOINjjR3R34EqLc8FUQIhDTVoXW7EWsfALg9CkSmUCagu3xTcBgQwuJxf3o1lZ58BTz
2bLolLflrLs95/Zx5gand5FfScALkuq1OvOlD7JlUd5LFtOy5NX3F7zBuAZPFWGJk3WwHmlPqcs0
tCqr9JWOvjFfL48pGR6EKy2gID6MneNUFvzYzhj56KTJZ4CRmZN2s+g+46NjJkaN8yzu+cQHSDiy
3gKC7hVS+2LD2861dUEV9uYvKC7NYeT/5J9Y7iEIrSo6G5vrgHTBfFHx0FxRJUQEjW8vpLAN3h3M
4A/KFQFE5ZtWWnjOYb/vOyBKxJD1Q68NinfKBDQucc+luZZm8GBxroSPUIVpFki7241/MeuZialh
S7/mOa3yOnKuJXgW1aBvrMe/ABAJaT6QVx98sZMZTnw2qZEyGqh+Klnf8QH0TYP+nmAvd+qKCOH+
5h8sjpetFMqrgUV4kYE32qZL9njfvaUcLq+HdYECgY26YBfmQg2hiJYPLNkdcQy9/ob0FR78KLH1
aLBa2QsOxLCs8oxUzNAUzCfFX2rZIBXRZoJwq79P8bTC5gYk/lZnHKYDxPNYTTyfd17B8hYtkzG7
izSjHu7stgVfLs+sXPVl1+f2tBFRINDo8enWh24d6PHPetqs00rxeeerTRWo8WAz27mWkcFO9Ie/
Lil7tTOJEQQq4UUVEpTW9G1KDWZOyLwUFzqWhdzIgeTj0LeX7SsBz753HA8PAIuh2BHHTjLPc4vx
yorshuUK8Xw30F+a2dmRHwcxZi5zKPM9RKaNeILzngwJQlQCjo56JWwOcBlq7Oc1HrHyNSBzfaYN
sjYubflTJ+vdMRFDSKs4e1lOHD5br9gqa1+ctZnMSh5dAaL1dgrPWXp/W+fZ4ZjgF2SxuYBBqI8K
s/ey8F4jMrC3oqRHUorVWdMEyNFsNxXYzWz1sI4JHv/TOmn1xYYp7mSiFX+TeYiOSP+dOjzgcYkL
8hbhei7reMfCN+JMV/xQKP3REr0RBQEhHJWWScZrKYFN+zay3ibB+W+/XS4UJvVEIn9F8r1211Al
2C1a8kEhyYPLmiTDlTg7EsuCdfNB3MgJU2m+sV8vWRqGifGMifBG5q7lwh+iPWxd1tOBSeQtrnVt
sqlE+dBIh4SQAbqINg6AUkk6R0RbWyisLyc5yGy7SRO++U1scRqYeFtpyYPPU5eXQ9GGAFBkBLQt
IHY+IR+7ZrXc0gGsNdXTJagjALGGD/45l8CLNFt/s78RHKtbaLYS4dz8RDlhs5r55kQFOhdkgC0s
EdIZR154qopU78T57uI08RXek0xgfKSmCVGtjdHhEXRS8DDyQHq1J0Nv/hQ830mBs4zpZHRKiQ02
tQ60WdhWuGyOAtepPr+foUSB3KAC9c/bPyx8bU1KUpZdt3loRXbylE1moZmiUOuWYN6v9xfjjUDL
vs8UnajrZKruWRyoiEpEYcE9018E5LssH5bDN3dWn9HTOtLpObGfmFgryCz4yUB3T5z8U3VNDasJ
KMYsh/wEdgMDFaPU2U1oO1A9RMtl/TZQNz478zHWoBQAQ/77Zz2ubUchI9xE8HdvLonoJkHjlbaD
n5go9x6oYxSHpOMhqJrEauzjEhInJsZVh4BJFmM3TktaeSektnmRXgPEclHY/WA0y634QeYl5M9c
bYbeFNF/OvfIXMLG0dzTyIxzuqCyJb4d1XV2/FAWokOQNXsp7k5agOc3SR6ziSC01xaiV0ISnf4R
GEXmECkL775AA2X3/lJzSYU2uqU+O5VaNK7vvyC1frZrOsGEI4JGHtovSugB1TPjfqqNMEf8mwl1
oea98DenQ+XS9p/XsL7XkiZNSRBi7hvpk0pwQWl5Sc4cd1oOkW1avl8Bf3n4WvS7LECVl3P0uAVN
HYnI+cRYtg/cY7J9VDtpf/TrJq8grU9t6BoN/leugCBhGE+Ho99UbQnCqcpG7eZ28Nq/V8sstzlC
bWKChsKQFsS+hGylouv4VHgQGjeTFPhdWidd7o8N9uVWg/hrLUuLTacRzuVecZ48kQrJYS9Zj96a
jijoJFE+6K1N5Gy/Qu1TOXQVp23UzlSRELulsMYxacBum3sdRq7F8sSuVLmhXxCh8ieR9V7ycGzQ
gvvsMyLiDkOh423fB0w0cfejH9FglkyfNRX2MQEqlPq2v6Q5krCdHa1GjKFvuh9GVXIlmyUC9cOI
0yYHKdcZQfpaYqfRkuvTxpFPIsLENQ/ry7pfTq3+1FZoa2jH1CR+4oH1WHK/hnzPYnlRwjUbfW7+
/Zy7NZAoH2RjScsjnTx7FI5hlzhmSeoVaKUZrYWU6ZIs95HkebAPG3esZcXFeU3++nZNlagMlKOy
mOIouEsM8Jr6TeYfUmagiMpEG7WYa5A+gkAUEuwr2OUoMI+EWWBacl+9QIgG5CXAhRTvIs1IGbi3
i9Byw6BY+BBbxeeSsMpNVm1lG+L/xqTQHqVgD4GGcK9M+vMulR2/L1HePiqH/+VcC1FIbzUriSKz
wOTnsz25eUTPtKBR3PPW1qaR95Mjx5FRQqkckfFi5ym5JdapiOfkMOE/UDDMumWsmA+Vur2nmXGU
/LA7Y+2ta1T2FZHsCWFcL1XUhCpZDIIvVagNSHfncFgLusjm7k+Gnx0K/9IXonZJhCw0jdgBErZP
enna6bB0u+qPprOdmC6CkxeHJxAvWCCH+GL6eFkpKMZhYQkNbFi13Da4F9FFkzTkdck6v4trDmuo
BRsB75XaXW0iOmoJZW7+wCVvBZ+DWYyGfZVIgxktL4PUKpFMBnIftkoNoX82AfOu3oBbDvNHW4MT
C+Bq9oLxyUBIeEvKYeOMKQRT/mw9FXPf6rWYU9S0IjovwPsgTgKvol4yIETt4yehtuw5NYUakBQ4
cTx7BeF42QG7MhIKIpYFGC2Ch/RTuH5DC/sORslUGZpyscp/o2qODWjyAmp08zyKbTBEtxKvhTtg
snhgI+UkSG31sncndWsNpKXUJ1arp7TYmeJjUUywV7jAHFulWr0MR/VUXDXQgxQtCZR2fxGU//ml
D//4Yz38rHZIViwA4VhFPq2dMfT417OP81mfRojm2h0VYJeZTzKOnWgBKDQBkZ6Ur07Xv5BzALS+
4gNQNh+2zZ3LUfDch2gIkpT3XsYXh9QR4TVUdXLHizuIxC73RuUoh/xYhq8gu3R6QEDscO/OREEu
bgCp2gF6IGxOpXV50KXkqpcLTULnWm/yi7vsdl0zoPSaiYE4I4UEKCKSiZBWfLJT5DqTdYfJZr1T
/s1dXnquf07n/jMa+mVp/yu7eYyMolqxarhYXFbpwcepRnGbowQaliAn4CGU+uBMzBqM/4v8tRdm
T0b87R1tA+TI4k/px4EcU1LVPU1oH2//3GwG9VtZa+Z/JJ7BIx9iR/yZhHOdoEDScKfCwTmphQXY
xRKAAf0Pdq0Ekts1OOw/1ZAeoU95qcrHUcnr2Ll9BRs5l8l/xMeDEV51wUH3xPailVYDuf21X6cB
eTNwjsC74QmCR7YY/PBsXZ4mavITLfeg0fERU6DRMwarFq+1L6iumoPTxKduPzW6ULcGwvgG3lyQ
V96U40gc5T7xC5MGgCvJzeLyckxfLFLB1DNtLPTs9oOFRJhWwd3WtaTE6pO65heYKRkoVhZvqfYN
s4Qaq29PN9YDSRiHzvn8AJsKjvYDAzYQDAmIyUlBvM0cFn6HgXCI2gIRM5a5Kc6dqPoZjdkECkgK
wTVr0Jy/Nf7m9GIBcYQuAIPv8L5MMdIWtpv/hjjDz7NhL9sPI/1xZsZTIIff5DasxqGnTE8Cle3E
hXAkf9DB1f2BRlzIOg4EEKRN9JQmbC7MbIUCBIXJ7W0LcnFsyyMSOiOX+aB86W52Q3isU/gTVzK4
ORfROq+vpdUb/y/2WedzAJGpC81c6ZRYfQ/vpVb2ydkiGIhRDJtVV02z7mWoZjMK5NPYQg8LMQvq
fTW8tNA/ScJ96/J+oQD7hB4i6G6It/yoB2v0eKecJ1I936zuOVDw4NlcMQge/0QJYBWuVsbXQnoH
tjJvWNZUfKHY7nayucnnKFbTcye6S9Pv9ktxrZXj0evFVhhqqLxBGjGmmefg8SD/nmsxZqI/8Ce+
0HnuRT2/HDT5Pb6Lh8+rSXq9XqvHzd0Iab/sNwhzC2WgAOEF7cKbVJl+ILnHn2lJ41kaYdhb/pxA
JdtN2kA3H7Je521G5vUjwdnDpVn3Bed4DW2lxndQtBE50ASbbTojVxKrXzvMQnTLmuvleZrCNThT
mNFJTSWozEiXXkG1OOcbcPqP1QSTNIUNaMTfLKxDkHF118jbOKoKDUJ1nTMebZvnx86utz4M1piD
EMVQ0miJkKI2t8C82jhowq1eD50lK2/WqKKBegZaB5GWS5tvfKUNGkDAporcmuXSAPc2+U/2Apiq
0lwziKDleH8Ajq70LTKPr0aQ0d9MXbWmZb2ghbm2vWkfxZfaZCBdMh7oVJMH2hglG8jGRFyE6ty3
s/MQhOsNyM8XZvlF86xsULnYgTPVjKg2UNTLZQnRDvdBdnfDQP2equFl/v8kyKxdnr6FP3YXCpIl
eHZq/PWwhVt/V6FXJ92MHbFnk0mMzKVJ6e7z/Xw8reL/iu5kfl8xIccdyiiksUzSg/3/wbZLO0rh
Qyd1S6bISeFhg7FdwlDFFVznP1mhd836hLRvhkczp9Jdu4n5Oe+JJngnFUGhS5YyrNAWV4PcZRoc
3h9xJMgzeM2QK8bZQZgzh6hNliCX7bVIkU42qUWKHm0rcViBhGA5Hm32u+q3To4sYCAWdCkCH8Dn
d75n6pR5MrIc47YSsOMBfWsjOz4NUGaZdBCTJij4unt03qEG9ymdmHwONsgyWYDbmSzU1glIgthG
CNcJSw/HHFJt9ThtvV89yn0OEDpacuH/dVYMKcHeEefdld/N33oNRCPpdMMBTtRgxOtvONvIy42O
f4/K/N57cKWuOnzRm98qc8lkzLyVv1wBQfpieNV5xXXwcwSeq+NDO4/BKa3LqSBADMkidKIMmWwN
0P9AxEpdpr1Z4/h3Mr1IxSD8VL6ZyPjCPOmy5zo/r00XVh57weiFkj95yZXV+pNUKFedp+SzUzCc
TBD8l6h7UDyptUpp9RlhdcXoHlgtCXUwfGSQ3bAHcILGiQAv3oKGT9idOaCn6SOL2y36fcOl+Eo1
zFMdXMDxs13L//zIVgJC4cE6QmVdYsDrj9ZdUjvK7Rv+9UrFqyZde5p8JjR/bRYdbi0bM42k6JJn
TogbGErDcc0wD6zyzFeu33+/RopgehWIbXHdTnOAZ2ZegdIr0ov0pViw1TFNG6ToiZP3cYI/oDMn
kTT4i8CfHuQ+dxEC/iSATmDP/o/rQGyNUEESFX6quxVHEL2tglpKwAvWSJwZYMW/xxtNdPN9SbBu
wYHRzH8OGSlvo6rX1kFCJQPHVL9EwNMPZANe6MuKz6u3YXCg3KFmaWm/dCm+aOr5BSBn90Of6ti4
FITCiKha/bgEaWLB2PSnl5SZ/+hWiiFzMBN2KljI1+Q74OeYkPfwm0WaSy69tJpQIELTJ5v4Hl4l
CNx1ioUASUmhPRXMMJg7dG0n4Y5Z28U8AG9HlH2VhUu/4zuaixLPvOIOwM/2mh8NabxBhy8XMw6T
a/oTEKIoHr/NBUIxWHnk6gyyWtT2kkXa6pRXe365QapykwZDlM7AnnGkMezQqkWr7BX1X9R7BDK1
42bVMD4H1dkp3mySM1+fgaZWSPClg4I4HNJuqNv/cP9FK/b9RYoiri5QaSU2pukDolkQLyUQPWWN
G4G2D6kp0/ZUXiqW1r5y/ogovaaLDRdwTbKSwHSWYZIpbQVH4rS4OZxs0D7yiQPCjIuAtczdZanb
jEioUhUB+Dv5QJVMIBjPm8TpR8t7/KbMagOb5ZeB+cRLQV59Ipxtf/ICTXAi5AbPMrpRgx7b9+11
VdCQOc2KCsO62wLmCA7pLtXHQjBeHW4pQ8QzpJjES0Dy4zCIugWjAdXy11jh0IOkVvnzlmn2VaGM
UzYPiOpjah2vICKty22cdU0W6yOGzYbGV3ca/fr6owy4vl1JFiX8f7XjW45JkNf5TPsiYUzA4HSv
xCO2DrnlI6M34WiAPYeyuOM2BlclePLQJ7BYLyYmEctTRzAG/PIDPhJYGO4RV0u1hzsq9WEs735a
DXUdfhrVJv3zmYS33Fuu4ElLTLnYiW57VtKzC542bpTstLhio0q9AmcWjt5tRkPngT1Y/Try7zN5
aaY4EhyMXe3mLNXEWbD9w2h4pwvRDulqaMho0T0L8zCMbekO5dQsgsG4fi3bspi6Wyk7049+YnwE
VL0aNWwLrlqeZfE3BoBpLKP4lW36MCJGCBrO2XlG3gq3iLhx7AS+RalxE9cNcXhAki5LxJssJdh7
pjFz2cR57uMPA/WijFvdhf5sCt+ki5ONni5WIIdKinng3QReXuW0nV4W+Kb93hBbMsd4aelxoqRd
xWQ8tzQ8CLXAriaeNd7uTtnlkQjo0gsUzwItiFIV9oKmqEfw56zdM5Z4Z53VWZHvKEiGQ4QMtNc9
uKXyqnCd6iINcbagqFtwsSXCU/IqxR+77H500FEJw9Bgbm3y977Kn1raGimaoiXT0Q+50vkm2rER
Tdl5L80qHsW3GONTWyLBbbcgdu87/XKlQRkfqGYIMRYX6MXi9IHylqdAzcY5uKaFi0axMeLhVCYu
2dKC9VgGO8NxXRC7wrHq3OOM+wGtbk3JW55xmgqn9ADRd9NFHahQXesmWAC8EyWkHwBLVstpKK71
p+JYI+yQZlG2HHqhTZMGIpjZzo4Ik3GoC19fS0YryP/smF+tIvd3X3iBUwrDz8Y17Hm2OgpZf06Q
sF22rQ1m/UOoyflUw+kodUw+YaRW9I+x2NIiU5Mgs7VWljzLIfGY1wPhI/54uKJSrS9DtNinwJzJ
a/Hz5dAcDThQONF9Vf5n/+svNAnExiZiFHIwXed3UFq4xdPXUw+D4QPDu6X/98cuRy4zEF+liRCe
eBu0W7QtAfdSz0Q+mxaj0V63LkfcEw8xsqairxNwXvuzdElG+2ZqVbwQYAWWP4ZlbM3Fm+vNno9C
BpfOV0FSaB/gRMTEMx0cWYAaYKQpWZfxChEo0VicaB0v8KRehQp2SIvtKEyt1kxJjTUEK/fvVpUD
LLmsgijLWoNHP/V+3D7D4VjjW4pYgfuTnQk9JR4F7MggfbW8q3sssbmy+tuCZiKkL0YmJuCovTGI
YdxdjdIYfD82x808JXbZDnoNN98sacypwoWKSgXo1vNlSgtWUVszzkyGdSu7ZkvdU7mJGoovttfT
9owvYILITwIKBuMn/BadwjJxskx/K2CI/8ErQAzG4kV2OmHR23Vi9n6ar0Hd/+DzRX8XvuAY/wXC
f7YGHcErIukUp+OK7exglEIpKmQIBRTKvTvg+3vP6YhLYrvxAOv1ia9gWye3BqWL6Ds46dVwY/g9
pCZibmirJhXc1Rag/6iFRL4hkiRWnu778RBOiKtkYq8NL1wO3FRWZyMHvPvdwOAt65sBWPa8OnGJ
4o5P+R0lKGhZVzqVo0FsyPiAp1N4Jfr5mUY6rpDwChd5jiWMEz3Ut+Nl6LClzvMqI67pgmhhBswk
t5oOcyNgRSogIc69rxHuawwONhDXq/1D3h+WPn1DywNaUZCZ4t98gxRSW54vTZVeR/zL8Fiy9FK0
X9CO0rCrZtsc8xOhulySXRUqPK5QytMOcV7HLdrv8zfMqc9BdAiPB/+RDcWQnm2ky4u7jsI921xt
RnsV99xensCZcFOzBe15HsD505fn94MW6RMvMqomMjg0jMXLRjtgEPrWAaWbi61Rc3f4Tqvi9d0e
R1k5ONVCP9hJOKgPFq4j96s/nlhwFU4PmXy2gjiQ1b7oIR+V0k5YSzhO2uG/qsZGKwrzpSqqBSrY
2ZldPcsp9yjgDMMIsqG7bX5lnTRbqeJIFGE3hv1QrPSIcx1cAZ10cuKP7kLEn0wZUJAUglb2E6uR
AXFeYAuUxFU3/eTaklGg0tk/OV9bLAqcfXKm98yMdo87DczKv+sO/BqO9mfGMvzmJ2jQrC8Cu1vP
T5SuNULgiN9LlMD2c80jEPNrJo4sgmCkPIh+I7QgdqJa/rimc+qTnMIF7lDozsAfLFmjjpL3bs4x
XwkVuX8uAGN4JZi/fN2tuVrrjiGusEV4zhZqODkJOjJuqixksK9hfAJnV8UJcJBoHuBpOqsKdqZY
Wnu9ApNu50X4F04mA6zdQWN+cGscBujzw5xq9k0fmsBgLa08xsQAFfGrig6t8jABSt3DzBgHhIU6
r4zCgwgSIi9JlhG/V4fCc+XVQP2D62HeZIXcU77L5l+XuOEuQObvocIWxvYQAOQZSLrvlx0s4OFk
PMnuPM5ZNreu4CFPWDlRsMIqX0XsNBkR2OSebNGvntQyMfFZXDDNCLzg+IDLMeoo860P5G8uvVkY
FeephYJSvIIz8VMY+Tm5zW5R2/VHcBOEO09JrgeCyvlryF920Z7KVhmy9cesDlVY+67Qin96DIW8
KUsxIXrbaiVi63yvN2bIYyLu2ng96r6/tdk4M2aA4STn84Tw6z8gjgeCthcaxa2ydxjgrGOUc/Mt
hDbw914Vv0vFiIi29EDUolQ8LFUn7l+KY/mT6+MBqo0QfREOfnG08NA0NF1bNTHMyufkpkV1LdyO
L+M94bfExyRmDk1nmXG03KpLe+zyElsPjtx27bguXRKIg6C1lahc1cs3YZaOvJHFba6EMqiSor9I
qMdOYUQEXrabS1CJL6yJ7uCIC0698u5/mYjrlaRGLTZNYaplWThS7XKWRxt66J+AwiTvaDoR6+YH
u+xwqZ0s0VFi7zvcScfoqapsK14iMmPNE0hbQ30GvEYNbXegB4Qyb1U0dbiWpXLtBSsyOYR8zr49
/Q1pybaNM6a83psiJTxiHXx/uvTdWb6DWnu2w/sCsDVywxx2kpSYWLT48uX1Ry06azojKUebmIWL
M8XVuOeTP4lorGLaiJodFlkcmp3er81diHecc00lcV2eBxlpPhyMj9J86JSi2EWkIBVdSF4aLc/3
Qth7CT/NADsbXsp9zwZEGIHnYNbXBKZsB2vKA9IBfDOc1VNCky08D94IitbnBbB2vVUAoODG09qH
6JZx2rOQfFF7sfmxr+Tc3BdOELF/tFfKsIez7bBeBrGsjGRICfnP5WkKLdcXpzKDZLbTXuLvUHMm
b9BvlPmfWxvbRzp2UC3zY2opbnroeqqLKCYXkHgAwjYYtYRE9NniwseJJwWKoyCi4D/VALY2PvAV
r1Hy2N/H9o1DRaeW+AzdMFWlyrXA8nrSzyXnxczreRdICfnfGyApiq6NaQOxp+46H0zr5xe4qQgZ
iZDVGjptov8pi6bImTznjpPfZZToGQlxtSFoVaEFHAQczG2UbsPoyS/+3b93Yk1Mdwf9vkWxE2e5
y1Qmc7jWPGHLdCG5IeP45b8iIIcYaRIad4xVQbQpiSteGGp6SrJ5JHnHqF7wWgE+WoI1l/PX/x2W
Kxceigfa1cjNM5rPU6PDngqZgmaa4hT3/xJkJTiMlBYSEEkb8A1T8SRCesUpZN9+tVHSJRrl/Rna
mI6IPRvKFujVNtcGBxjr9Z5RuIubeFnwtBvtvrBvUmGZiQEjEd927hi1icRMW+uZi63uwxr7fms9
kjqAwqUxhs7d69xUkOA7uR6SNjTpbii0KxDSLOrovRc2/9Gbq58iNuB98rnmt3idRgGDIq4MVfDh
a+4PB6w+Gwi02qibAjxxhs2/RYl1TE4SP6qJ+D/ZQJxXmygaszhaq60xd3cpBivPIWFsBTOWSeQt
ByharNccx18Sm/Do0MDf1tKn5/QsWktkvC+5TuD9sLty9W8LLWwNL1mH8smslPo3o7FNsMRatHHJ
JZi13fGIUEsA50hhV+V3Q6w37frG4oaxoNkU7JBt03wweYgUsceZ9t81h4sT5lxFgR2jwB9PByZL
aCueknzspbnnXlWoGvKmyXJ3fw8OP2x8NeEmVXNl4I1ylUM7BecAH0VosrtDzKu4oWIm6OS3acMq
8oBkyGrOF7ETq12irG5xA0PMY2LxWOQQ9Cxm1t6WIExTbfC5oXo+R0aMa7vsnw/1QfWbEetHiK1u
VgZo+O2s+4FuAW0ckB/dfxN6uWc1OX7njRyn6IHrmH3f5QKpS6SWJNGgRcJfTfh4OZr2kQ4F8z6l
qQxHb3+t/unAai95NICKEpWuasldCmcDywY4caadzqGzPLWVU96v/dQJLRJJV2M+XF9HgRqNCv4Y
wI905lQrjj+hA/BWlqM6IOFeb3JP3iLvUtSMVyImepz+lRg60Ml1i22RArRwmExiA+8QBuYzSfMF
IZgRvgU24gaNzJJgUGOV9UWaKo32QXZH+2muzPB0h2VdiY9/yIuHDpBtOq6klhm5qUA5AxD8abWw
DduXJ/iHk413YAxyrPpOHl+nFz+AqH7SqKBABWfyi+Zh8c+3VfF5MVhkNczjX4WQI95/qLDC/Mu2
sYyjXl3yju+VAdP+ZAZKE9ytZn7fzrGECiJZGbOxJp93/WaGM259LOhsgak6XfwjABIbEY5gZeCe
HNrXUtzt5qSFBb1z4vWenUT4eIi8HwhQlo7pEmo3yGA0ljBCROXtJCiQHcve5gXyoe67xRy08dA4
MzvLnMsWNa5ObIhluTqGkS9vt0AvwH9Pi0NL9WjBx4ngVeJlqKOmaq81QKD2yB6NfeknOok956Q/
CALmwdQfbv5IKAyopZkY5FC6sgvm5V0dHSd7GGMxSGg9+95X+N5qpZ+4nNdchXiuNQ9h9B4cJLts
JH2446iCXKvwp6k6qlrCjeBXpz6d7TQOTV1F7JcqFZPL7VPTgfx/ht5dBKaVplB9SJJXnmF22gg2
ssGaDcCse0zQgQ/Dq/lXn3jPy6RCFZqucR9er4BfqyD6uIFRNcM1RE+wCP+trQlzDNHmkMocjHAs
Dr3XSZRGGl+VSu3qlVezZNDmYCJTVecQXC4SNX8GdTKGLwcwHPmYr6AWgNydq43SYTP6OwOhpkzE
PvES3W6tdUeTn6WbhXVuHMhIgoPkzUyKPAz0y1TRfOAgVU3Dq6/8CDvJ8IQd3IdH4rlZ0LQBi1ny
P4V82zR6chATwm/5G09znO3QoSJlSiUnc/xaT88Bi+5LySDMw8eYANsf4PMfflTe9o80JdocVtxm
7RKJIZ0lwysz8MR+Mywgun9hbxVKyWjn4d7FLYriRHMFms9qMYDZ4VSQERc3jwE8vX+JaJg2J0NN
YWMmbh0fD4JDVEkDEXcwFQTIqdbuLuIw0IaFW4/JWR+lxVxC2WL5IDodTcp7ixVH2BhAT8CYrgKK
5NNl4ByfcjNjJ4a/Hd/rS5tzw2x+bTWp1qlfSihxQEkLIhtizxk7MiMP+xpG9SNU1gxEKDfeuLDv
s7MJCiEUs0lh5Ilp5p3LY1X7J+VCyM8AE0SCc1E/f60/tTrHfi1FrIeiuJ7njwAxQb6hACAklLe0
6PxvYw4Dgbwl13zmhAmKL7h0v3GgyJHj7XMNtlgIj2R+H6ym3C8ZvWs7PxQqm1qNTvg6N12oA1MU
M2i+Mmh49y3sJ8wC3rhJO/VM6MiFymQ4Xcy1Gc/umNpSBF6oaHZouyanPifwzxLtTn7Fk60CqXmi
9llI15IdQfuXXs2Hpd3LvLOZyjOxP0IxjjOG19t6adYkKqsDILEXKokvBUQC22vgZM2bEDqlCgMG
bWZ4DWfmkg+IWUlHE3ut/Bn+XvsDB1FHfnuDQu9a+v4So5/koVbDokVeEbnCKe3+zhyvyOFENkV7
0kX3VeFxHIXpafdOegyPd4j3UeJYwqFSvpXHcybwPDL1A8vYONakhHbbLTl7I4SdrSLpbmfxg1Zh
QI4Et3TRlXCQxginBECT8enXZ/Zd0c2cH45nW8Nt7USSSt/szFzo+sV5xenuCQtM2mXszRmK74H5
a6DgBjVXKPQTp8o8YyI3PmoL/0/0XKVAzVhU0lHBQBfWS+uZJmIpwLk12azD8VpgmGS8YZEmakVo
vM/IoqmZKhJHIkLr13/jDQI51SyHPBhYetjR9MIYjoBHr+W1lUqfuAfGW2Btv2SumqZvqZ8CgD3u
JbAQD8HI0pDwhWU8BYBrBZXvU5s3XwUtJBRqhP2skK+IPUvbmdbbaLN6bKfalny2VppziFYSwZqY
I8dxLdJJCo+cnYSlfs5P0OVMtYoAGspj2wTESP2YxWgDvuKxmC2hIhH1vuwqIoshbfkBuuPixq0G
Bm07PoTwY/Fn1bIUpYNwyrD5EXVoJfGW/07jfKJSNUpi5zXs2rGayRrOmMKLrKGfKhyKtnM2FKSa
VJm9V05B5LbLsmSB5zFVC4b5Cpoe8LVLLWuWGf3UdYt48s97Rv+ogC2D78H2koCSicRaKrqZZSbx
/3aTSogEl6BKFxRmG5E/p4yHFFYz9nxBaNPHTdC8CaUyCTSCX/bTRvWcHOqGK6jS9GNYz/f+zbTC
ggSYqiMyIjN9MgkiPO5M3kCUHpRBgIXGuf8J6nILoLnOrza2MQsnBiPcpeSt8lQfk3j9SCDuvFof
B0ekftilRPa06FoeTfHxM0h81qE38RNgSD2k6q8i+QNqbY5I6nlve+BbQfeC607YG532CxDK7+PF
z3K2xU7JFfGAvaBIQnXwbEnWqqBuQqGbLJhIUQAig7Ph+DbmSKXHDI6sUBLwCTcn559NcbKcSa51
Uf+zNHLcgM0cydRxTg/lS4UfvleplrJ6zB8ajF+NNAm443M6vWxRg2IKZB8+VZS2a24Zby0uiUni
QXQqB6RFdTLZBJm+q7SBh/yconeT622By9cEXBKEWMfV3rBvD7+i3m55uPUCrmhorMzmgTAypWDP
vpoYPVNeCyXbL8Mi2fr8G02RjeYkx0l3/orkSdHJkAo1cibMfayDAEumDXcot6p9epqpUeUnCtVp
bNj4Ode9MEckQ3SNkS/D7Ih1ASTi/OKeDmT8fO4PMTRUoq5u93pbeTwLgiRsJN4UD/bUCLoWiehJ
cRG6DIEer0odFeAVDdHf44mH5RjQtrB1gGa5KgYCBYpYldG4YFvKhiND23rQCSl2C1/FqVkOy3rn
naWnGFg5AO7kOWN69ZcfGb5DAhCXmJILg7a0gANMmT09uf7pP9wrLzV/F/NRxtVN01u0UnJUGkJ2
S0it6QiuYX1PHfGx68UrEoV8oxJgzpUD+nX93OijzDrVfvd1jKGbjqnqa8TgmrODV/qlf8znDcMy
nYZIktocZmkhXJLRC9qc0CnjaoTLDJIVTWBd376MaydGuIqNueQ9EysEDMdkKS1HxBUW7wB9XLWz
2mShsJbYavh8RwYQcA4skUX3ViQaoovr3JzdBDe48DaD+bMv7CVgXdO+7zdmXTfv0EYUsvsYEQg0
WUqfN1i8eVOTMN56miwuWSSogBLoFsevgCoHXWWDkaxY5U8Rg8AIR1rXt85owAa3LSUXjLBMeTzs
RDaPWJu6XnvM8AylFmCaHxhKx5s0apicHaZ+37NSvu7OPIhRbaGXzLyExl64wZLkuxUtp8l3ahlu
BpkwbZDSdR+JsRlcgLPCfIEi0XGc+dNisuK4/8XhGqJHArs8cZ9ZkS2YJZrkObXU7vDweBH4IF4v
QswaTQaoOplrG7wfSm1f3XRTWhPlV+3I+8gwTInEcDUiL6GY03eV8AsKDC+EtZE7XPgpSewl6e4J
Kzo1o8QJQvmAX+nD1F96tdeutpW1PkFJkejb4jMIqbeZcrZS8pBDOsadJfokGR7xCwVL8HLsXcXx
DZh5mOz7MSSS/k/kn0wQ3Wznv81EQhxcwPOaw0yivYGUHWalYQ1V9H3+mEftwWL4CQ2YsQ85XYFJ
NaovmMm36OE9u9lLQlyu8/inEZq2pXWWjowzFG1IsY8J3v7M6+jDadX+h9RC1oebQpUKiJV6P+6y
cK16hiW7A5umNsJEtnchZo/+CPzqh+q37b3xUgE+S+5Vu41xVPPvsCXVclvqCtnNMfSRr7AfYipo
YTcoL1HmJZChD0az6GXM9EkgtXAeGsWLESJ+BD8NpfcdCaDz0X4J61VDATijnNgHAG6PKbEEyTlI
8OoVBqwW5iNEY1emLMRZw6d4B2lpgWE/Gw27u6ueUG6n9nhGwv/VsWCnV4zMutbgOfEGZd6SPCox
xygK9haSSDlMjnnA93+XVoHxrdHgAYs0Pw3l1DVBTAMWHROGi0pFtf/CZ7D1zM3mumy2Kz9lxUeP
rkpIu1gdcUh5zvXzUI0c6c+QgBQ9ps3xUKfydDq17K7WVAkVovbhLZesk4zrwoNDn4vwtoJ1SVTB
RZz+qqEe+Z+2wk9kBRQ56vR8bCNiilxuozyxzAuIq79DLFuFtZBv3qH0kU9qvE6vnTVrRYmB8jCk
qazw++rHrrgl+OnGCGxzy+AP66svopG6iQWHLfLDIPxO41st+gZeJbgGxGUy4Of5iDBAZxlscFzB
Ia2Zmo3gBaGxn4IVcPQmZZV1oTzKJYClVkRnf9Xe81JjdpEVvfDRn9F/lr8DoIqaT35LnkhN4gd7
+/nFAMsKMTFTzYiSjWo7BdmiWuBE38KhB8RLG3vHQwxCuRUbJf43XxiHgNUtd4/DGuKUKkuxH9zY
z7YO+KHxlo3FOA7uWYwI+s5nSdxalEthPk2DJgTNcuHTbWe6RfpFSlKkh8sCXFeH2v8nCw4Cz4BB
3d3TWVzYP+f36PVkPDlEPpdBGIDTZNcw8LDvlwgXYKkFBmFdo83TQTA4dbMV77QHHnU3i5niRlHw
mfZu3n/Jd0obsYQBBD01/kcoMuH6nXdUGLSJgLJhlwytI83KvNp3mJh7rZ5IMAtDhoNeEklchDxI
/NGyoITwFU1cogd+Wli+l8DXAdL+I57FjYO9sGQsUtw1jaV6ynJfMcqKvNUhERt1ID8jUUYOf1bT
1BmuWdYGihts6FoZ12hxCXXfaw9/uat7/yb+3wyLk9IcdYhMTP4NrJxdxTwXR246B6r5D22k1Gdg
KKA+82miIzsVpJyNTDb3OxlXGh09HdnaEESSa0Z0YXlyGLuc+DBt3WZ/X3KxqbqFDS1A7ghyQvff
zNqbcc+REYfyryq7GeGUkhiiF8j1uQLh+EcotxLP3k0wrhHcNo1u2qLwYG9jtS6MtaySg2FV7a5v
KOkMstdAgbGJsyIxM7gW2p/ufjUshZtGJHopweH/sGtpJvhQKttv3BTjxe8x7ZdHiVqbh2426gCA
17XursFfzPp2JbAWe2RjjAS5HaF8V7VYl3lhK/w5Oz43JyHHH0MJXzqzk+PHj+KaI79EUTT/hc28
LEDV6QaLtwPVnMGiORZsA1Xy8jc7axCOlU6rByl5j2VDcrq0x36rT+Cu92By0luXuJPCFjrRMoEU
TBAJSUFK3oOz4wBXNj6562cLLOyqVA4+IhfF8itgH9eAJGIkEwr0/dsXtG3i8mzIxadDZByo3oS5
KL2kcjJyI5RXDG7EE4tIN1GTSitwlh5FQtLvQS9ZmOcs/Ro5BZwaw6A03zreV9UwsEoUH2TIE7dC
Ekwj93XMfUjMsNxjLWT3bOL9+F3e/PvbHEzoid+zO43eROHmNfFJ0YVM62B39RB7Ykd7XMCyCH5I
13EqV7dBNYRS1F9R0KXVe0xAwpai29aIU9c/r3hWqU4Lsxjfzb9OH3NIhneAvsC/3Z3n7sg3Qtvs
S8Yy2zdRSNPVg/V5snKJvGg+7pyQpZIfPqLD5uIccW9OIvAs7OtIZ14hrWYSe4sgxUPOk7mHP7V4
JRMpg7hcpxLaGXIYh9UC6QwlzCbTig5VE1osePmwpoTkbi7z0tTEwxD9rDD29/QD/WaGv/Die21U
bNIo8oQ+WBAnGuAYT7Y5hL9UrA+48frOn+SZol4yGX/B5qdTzWtmwaK0+diHhSDXHWXwaKaKuYBW
RoRa43v8Gf3ZvHIfzEK7VKHx9JFkhrkJqYkolmuco+mG3kJycGG/gaM3J1lZgTzMo97gioUGr7h8
WWYUFX43FK6qSRM3VF0LRqek1Sr5wwLLC7FY1UPCjtg0ldpP1UcZuN6/k4/XNZQz7UfKGgg2w6JX
Kniy5Vc4ouipIiYJTJHbxCmebCWckRTGl78xMq0gwwP3dGgWeqoeou0TzEW9acUVONwvnWIMCrLe
f+QCfdKPI2Wx8JAGzVXAMPwcG/FGVqFyFAJcjEA07b7+8z9Cut/JLt6MH3RDeE9eov2VFhjZa9wl
RVzKHRvRR2pMXFGFMhiNRjvatOa3BK0x7FAcFLNqMYtLZp7ACtUAuTmB1E+GSuTp8Z26IY+aYT+J
23450mpvjlPv5OX3FGCwkOlHrcx54Yp95meQGAwnOclye/fO8dv/whgVpoAIxZa2m281rdt/saaL
MZkDhMQEyvLbqYcYF4xExgUA7EHJRS6KprdxE3ZPMOp93kZTGm0G9j37mAuKMJY0DKmrB4qw5u8/
sgs6Yad7pW0+wpr16Qu7k3LQdzPW2E2hV3y64Ayr8Muds5biLjTjNufRzfHY3VEIESPsfZ3P5O8j
KkRtPpwEBC8QDoZmi2W93VrdPmNgCr+JaR80RaM47rd/NLagojgGNRJzz8Mg3wDj/H+YxiDFfliM
YQ4n+1v9TZsYWG2cXiLHBDoPj76JLdKLCqyV0bCpCUT8xAgN8u4IlLm26Q8q5nzs+EM7i0crGB1C
3siks01hHi/aJgDXNEydI7S2RHQfzzalMaBw0df5z76yyevBSLfBfL8LmTDdsDzahaK6beiirjgm
YwajQ50ALqQCYQjxgf2mSMwu+e5o2cInEUru/e6vhD5VzZoKzjMvupw3z6TuSL+hx1LnDJMXVeVk
7WoVruX8QTgMmSwCmxMYVb3KyrW9R/Rzv+XGc8dV+OCbIXud4QaILYT0GRwoSw10e8nvJAot7Wdo
lw0br79JgWsFUy78gbFFkwTZ+jFvY/T/FS/gEYzwTUm5ZlhRQzFvxHwt0MidbKFrK7Qs3V8a0Es7
Tu+zaaSUFkB13VgrvdXcMWTF1gen/OToMu6QsYx7NzIXeD6E52kshUGHpd+1L0wXhnF9rsEniruh
QqkmHcKZRsuCUaFsGFxM/Rfj0P+sbq0/v/wKzs502JEGWBlmtl0uVuCCX/3OfiGWYRrFa64cTTL1
QVvyrCe0fs4CbyoHjnAHlgjPbE1IYnbVOfbb+TI/ZewtqdfHng1Q80Iv8lb3aCHps3VLrJF6hf80
vuoO1bhZezGiZBY7uzeuVEJliTAfcbR6OLV5uPJ6+Twq8aekDnIGT2RRKHrStQgizVWM8DYKZRyU
6UXVEK9cwXgNC18AuwbLZhlUExmev2+1mReMz64LQSzoeD1X9hGWmsemRbWNuxcVWhFdW3JB2rX4
sa8HVNF+Hp9HuYKg7fsjOxVS8ZW5dWFTafOxUPch7FFciWjrP5irxCxJrdoDoZmi6gQaE8+JQjj5
wVgs0/ffZ7kxA7mp/SlpnCnyiKaHBfscYCJMDVKG2aodoHJZJSU2853Fdxa7AEr3Ahz98Z8whO2w
PRjThmSI8Xit4e3zQ5k/3R46l5ouBLutE1tNMuEjgfNT8RRd73i578tugCtmGuhYMTyCh+H57zvE
wNDprVS+Iiz7GQnUL/MpVJXUqtvTmfU67XGZVM3iJxcIRuCK+/YFNFXFTyNd+DiUrPR6XbWJ3Zzt
t+n4PSspoAyOFE3k0a3YySKM+ZGfDr++VDxPIlsuDmgP1a1o8QM1A1mtydvHiLtRrxROsjc9vRYS
3ouGnYmgAXRmUmNpDd0yNsKUxqr2QsU222Pg7vkutkF8U/4YqXfGjx2sz9ibIFhJTEy//Muxxh0a
AgxsSiNie0F7p7q3hg2EiKey8BkyHNKRY9oN4JXetmjAInE/TNDUUkYpCrH/Oa7Kt1y1kKNSmpCc
nvCw/hv84kcD13gTNyzuv8jJPpmOUHTYDi2z6OjGi1V+z6C2O9fSkTcMzrE7TAYBgmFA8XpP5nIo
sDAks+tO21nbXDEFsr+Kz1R+eYlP5y3hRhI6K12a/QFdbiGv5hn9T2wmy7ZSK1GaqcFkgDqMT3ta
jNWGvJCZdR86/hgk8tdQINz/x6LzQjd3OyhECUyAJGgCWbkmt/yim02dh3V4Ek09HMn5BZbaDFn3
gsnppg2apMvD5zIOGU70K6m1hU7AwuJQQbmypc3FT9qtsCqQW66N2F9PMmF7yP8HcctHSCCkv1JY
hlwqADxGsN99KOdG4mXofPd0n34OP5tnLHKanlituuaTJK9Uf6RAZv5XpM/99Dok5qXOIvqYFm/b
0XwDmwVvnFfNrtfTlHKqWv0/ZMyLT6mGNaGGADgKmOLox4xqo1jmHLKvKOGJX87/lmJc6zwotN5V
38EfQzZJPnqyT0tciWKw5tBHEBrZjOHewzj8fZHAjqTB2avOSLZQQvrKXLNc1utyrySJklAdvKVm
VIj6wjY2cdoEdP+ClneYGsOpOcmFgt281LpMn/7iLYl7jC2qr+AVCz9c+RzysnfdSuRTLz2UQqu5
RTC5MMnPOdNHm1XyH8atdVqeNhO2Q9VJObnO4IqjKeCwcGpTreIIunlmWN1IAvTqnVFAIxWaOQw1
I2iRq3i4lAS7WAF0zddPlhEq7G9IKIeOqfmzSQQ2rX9f7SphLTkKLDhpa/VV0CRDLj2lZqX1RJD7
JhlxPTMhUH9u1QOtjVxbho1iiZ0MxbBAIlfTgqn6O790tY0Jez4YgsBvRMEnZOytMdC8/pQimvn9
a7ivmT5Ylu/tuMuqwguuA8ebRoneVLIIEArgw4nfFZ7s2i8ubtfJjChcocksvgN0e3QOLiOr2BJd
oGwtkCBe1L2IFghzp1uvYobv8g1iR34in9eCrxOSWSwW/eEuv7qRltKrpdd0hHZu0qjPPN0PvqCV
kd+bsCeATAkISvk8rEW5AkY/ZNK3hU0oHQIB0cW+WloOaBCL4LGwHFlfmP9w0Ijq0F4LKtq+xBcZ
oUUiBEmnyvIX0lofacL1vo8yI8DL3aYQCt/1axgMQO4WavKdMkTNxAiCp37vW/cOVAXaGInnBrGD
E7ztL8VDoH3PqL1wFyExofQ+gL+WN3cbOwWRYute7brg2qeKmdFCGW4HmMU5JeDCXBdC1lOPcvFP
VskkbQotRMCoKSccSPYhXC/BT2dqqRp5zDNjrQLHKBmSM4hMN6WE2ZTpSpzSLPHjUMDMlMSIQIWs
Mr5f8PnpDIrECbjXE3cbFHomlp1SEVr3BoaO6iy84foKXuT/Tvwkb3fwZobzN9aFGc8ChmcxcPvz
GwBX3ARfgGB4/e0ZLi7j5ueTGfJeYovwyrkrpER0THq5TPIUJRbnDfXXVLAr8cB1u8XAS2hqPMsV
zJBGEkmv0lGYk/VtILSkAOszOKyx+q+NElI7Cm2NhOK5O4eFLtALybJR6CDveJV3TeE54NEkAhto
XlxS/QLZSMRIqOqQrMMkaZm5lt5lu7oiJ5KqO4gzcKjKf7SHNFsMLa2WetbgN/c9o1BTrTi+GCE9
8Fv3f5jSheM3lOTTf9tylPI0q50Xjka3Qa2D7swG46Ef6BHpplg5cBU/iVrwqSLSHRer9Son4tfR
0LSLU3DSxjOhJHpAQGmLBib3yphvtkkWJkC2xphHW0tu/1egM2xtlygM4gBsEEdvbtvUA1fKSla0
go5hq+jPlYucwXwLrp2NrUfWiXBz/5O/qk7ic6lei+eWeRYcBKvkCermW4p626L4+FuwDAtcrdxP
tq1vTTYBCsJOZ6PU8turZqc4uyQ89ka3uWG9Ndnz3e9vtTPJ951ZVOZ7BbGnsdeTG2QZ+MNFPgOY
f4VxCLe7VdniaTz0PC8EjMLIH26EyDO6jgDYpoB08clGI1CT7/dlMzBS3Wk+E4O0B0z4meH7hoK1
o4j9s1P0z3X4WxDXMJNESzKvmXHJgQCQqx7q4IolMPYkD06ouIsowST+jLtaTsZ64uwR0oiqYRGA
HtHCjIFfwIaC4TrL/vp+GyioH6LvC42CYQlGG6CUOigm3zN8+vAKk9/+yHdba0o13/X0aRSoKATx
+9+j39K4+xg8TXgoORsGqXzWGYGg2JLd0Ry8qnVhEZCoV+EXw2MkL5f1NBpM6K456HCSPqtQDTpu
R6erIY2YRYjLluwds3CsLPb0/qvE+x+6e652hR0TNsTR33L7sVWguqjwt0PQkbtv31mT8yUKZCHT
KqSu/+anRGpOr8yTV8p1eL53irzSbAktx8ebN5TZu3jxbnFaUa6eGhmswUjNz/RFn2MpoUD4gawM
PuV3/cth38Yx5oW3ivrVwj1cpi7YI651/hR9S2BENExeYM99qHFgrUZpCC0/cdO+OVtxpxL4iA3s
vyB16CrsLh6knZiQA0lTrriIcZf9pYuP1STe8EPFjG11kkJYBR/TxHwVJlesW+fPd7m08o03bjst
xLh1CmLimQr9nmyy1JAonNwBLrkb/HK3KouXAufwczZZXnm0oCc/NnmVTtbtfEmeCGGJ1FAPIOo4
NAHF1G7ANoievM2cg4yh3U3gyUB4aKtVnkNdb5JlANvuqG7/iGnvXvmGn6aqnLwPpbXvCVggHYF4
X6UoQcWfijn/8CUOysJtIPkJ3K3HiC9EpICuLogMVik7ac+wyL/ePXfRWLULQhEaGeAhvhrleFLm
KKftadn896B6W0S5+hb8Ep5WMdP3ag9R0BRCb30a6FZvd/0qPhFgHOED9qi2boVbMNcUm0zbMNvO
B1r/t7atQhNSnGBn0HDhutAygVaRh8tjsMQTbAKXTjMYlIFiT4boQX+6Q0XbBJYh5Yss2ESbv60B
MUKkgZNVqU5yMZXCDGCP6zmB5Kx0B4Q/EAXV4bClFN+9IvwCVCLjQxEwEM3tFD/SbqDLFDo1kTc6
ukyOI85g1FrCS6rzp7Z/LyapTCMhF7l7Mq+8tN9nJ001y37+4WECfO2VzlLdTabJQIloqw7a7xnc
f1eMyEg/Ad+LttyY5EFx5OpdqJX0mW0o0g+Y8YK/wx+obETloVNBG8VONvaVW0WEXHAKVPZsGJV7
LLniXU4aznHPjxk/aoExhqTCk7XGkB/Z3Axz2p2gWlE5nqM3/A4y7G/PQ6y3o/1Jcr1+5Ay+xqL9
zMU1mf97SCXqlfbnkbgmp63q5ws8OOpLweAh/MDPJ5K5NkD74zemgADPC+rd1u08WICIFQOu/2AC
mIh6zPo6MG8Xgl0r178kIxdIGEXg/OG2XFHr6D7to2OMVBUoSCgQBcXNRGJlndSHpT1sA4Xhfgr5
MrAICIkv33RsmvFNvJLTJqBmbEktxM1sKwI/1kuEP30n/B/0vBXPxK/0arddW+/MzMXJLGSToM+p
JyKhlnuSsBUTe/UdMqySDqKwqmnQC+HyS5R8vJRXi4L0AchTZ723CGw/FpJg8hufbAfXx0+T0Yl8
NlGlP0Xwbss447F7JPHWeK6Bm5XBDHXuW7ReiQlA0/E8ma7/7b9+yJEAFSQkDu4npmqU9Ilgc/Ko
haFMlnN5OWqq3QgQ52TSDC1Gwq/k0VWd7liBPoWczW0EvKJ/h5VhrCMPb/6e0Pa7WwSgGSXb9saw
nETQpffbXHkYmwbBgRIYPA/2nsAJ38Tby67ho1RMbazc1w44qn99pWSqKJDte9gh71YMMcC0Ho15
W/twQGAuUB7LGK3UsMSdbia+9uR2gMmdTYHhetmZ/taRc9CUREPXCCyKQBgPahysy5XPdGxKEPAR
UUIthmH8T+2MwCwSDAzRuc8KpIgxYmi1qoU0Y3us2gGMyu8aW0Ke/e9ztfKR2QJZKN/7SP3LisXV
b6m8dmjRMxWrvDmukzrSOowYctfrvTQLjldYqYUqaEsNSLc/VGsQlTuNbLmYI5VL6gXd3zX3SzJJ
Ldyc7dQne+varDu/jEngRLuyhBgeP9h7D3K6LmpJnWYaN5aoESsKJB/AMdjyqjlTj2Wn6PaVLOUx
MlmCxRSrK2Tp+nIrkgM7WV/ySBnmR7oBRTReGjPQoDRZ3Co0BUUinujw71TW0A51Y+i/N5SyeM0C
3g03GQMUgboECVQWYlpVGUD5d0rBcC6cy+c3kWLrv0lR5BYDoIpQQ0nHYoewB+1b61/RSIZJT+9O
WLSNhH8Ns1wKhjKqbvloBauiziRfnK00kXZHHWiEhmxuBRipK51Ibe6NOe2+ey3h78p4FAsOzwPp
mIIRNJow0vwvSAsBUAC4G+MiW3oygd9pt0MOlbZeelTokBPgl1tKQflXtVTZhNgwQNYtz4JJka86
mti+OxiSCDki9uWfAf5+TVPQnx3J1g4Ew3gFbGRDH9Wy+JyXVPsAJVsvVlrIf2B383mslC/MxnhO
EmzuMdnIxYSxiQ4JdfAYrY79+87WKKRt8+2R/NGK+nikw9H1OHbVVxGdzqnHIlsQ2bbAG4YJndY5
oNB6XtJQcl/Mv64hhZ7VyL3uvNcCEIGAfDjyLRugInd+g6XmGLETBIbGzrpPc0vbE3SIE4ylGg0F
Sim1lfM99bAjWbOwvbAcu7l+fLEcpK6oBPHXAg7/j7opUCR3tiM+Exmf/K2wzjsi/b6v+sEJZXCy
yQZz0VykZSmfnHSewNdAwAeiuywDxGlMKYqgw0Dto7TWn36O3va2R3ChUqfPOiLkxKG3/2HXi2WE
gJaKDDt6CoWYZ8tESbfKioG+I3Yd+ySQizZlOubolTwiJvacuO688g0z/y8IWz/EqnhKGRzIPMjb
Nd/WTj4hnEOzjXagPGD7FPjGS7CPlz2eToG/qoGmoz/5/0Mh/udjr/OT89haY1jQbMy/5Gv0o5r4
BAdO/xQrcDRkKB+zUvsvQCweD5riUVbyh5ORSckgrbwQIH5boUM2ogvnVRBQqRvjYm9ON7UWJoLT
oYFtGp4AJLkMQbvSvCUE9xH0ymUo8MnqUam2e5oMKkFbFO+jP40ag0IgYHbJnsjO9MkdYA96hB2P
kAeCjcj2JhK5+VNCOpaHHVF/ht87g3wwgYAp05uhshKcrI5xtbFwDey11C9UqP6IFyfac7tgh/py
GqMQYv2tRrsTVToUpb0uESSXdjfrHWTpX85zOpGI0lAFf9SKy+lq8LxvtSn44c9nSvNBXCaQEIBf
iTijFuve9le/hbXMI5BLvi4woK4sV0C5jIVdVlArzpwe29XC7pmH2TGNjh3hti8LF8mAECqMad60
Tw5aMlHLsfCxLBuN3R6n2SpDklamy64v3xtlXdkYJ4JNgmD2XLKWB/pK9+rWDk/Ut2huT8eTamjI
4yP2swCfoossny2E8WBDljHgLBexDVGfnirLCXKSU9iKhhh3yKZ+vyy5gLDX/SfDXcpXbgtkXafL
japSDiqsSr0THAowF+sCVvKAmL38wEQzZpUwjjbdkHAlz0VwF2Y6ElABQtmc4312aV6Cr2W5Q7rz
yT/MW4+RwzHqmkr9kLVAVG7XdsqaRXcXOPThDKpR3awUC1b8FQQxomzMr21YjBLL3wr/d68GKuW4
+oHZA3arUykQ8onwyZZvSDdkB6v6ixNTIbd1mr+ALFZR5b6blFrsL3D5i8tosOGnHTOsMnOUSy/v
FbAbCS1tYpkwgMVBrStwHI+PFpmv5XgdXXPXsISQ5D2x1ncRahImmqjnOQbp6gY1gperwjk+YBUi
+c+2+l5eDhs6txiu5UUBt3HRQoOpkMrSc0CgzVfLNdaQfCLEdTBB12YW0mfcRD1X0Pq9BsSilp6D
/OdNdpUxk2GAHSDyex+LeUBRMwFaUEpe37bo7T9tYxlxU6/dpmRrVXlbwFeqlouTbng15ylQWfkC
0nJbMbOiJgOaljh218TGfk1ZSclkM7nS7D99cWbCzexKSgQ/UrO4bP4lVhqHm8xrBSZRHdd9m17f
RT30eOrXUn/GZz5ipxaFMRi1xSM/P40x5e8reYhbsUHujQPwFgZC4s8pBx1RrdoRxT9V/nkRXSQE
oXwEnXyS7cyQJmFjUNYU83z+36nbW0b1Ib2K0Qb23CgfC7yrvwSnGMSSTIs0ESE3CJFNoewWuQvy
hiJqmq0f4cdF9hl1LC3apj1wzFevlRd5aym6CC4iS07x16b5elmCJCsRN/V4P96pkgQfl3Mt3v0E
R4HiPOP2IykiBUDAniK0LQN0JT7ZGFf6K0TXVwvlSVLr4gMs5pxgJpUzpTEGzioBwAo09g1O+TLY
IxtUmgWypxQtIsx9pm/hpsbmgje85lmfUAAC4HrIFWfpdBWWlqRezMydnzq+4hUNe4vlR2dqlY6T
7SwKDR9KUgUgq0sucArP9vzsuwMgcJiti7Q+l93ZytXxE1ClZGm7NNn0rQMdjzq+Ktt0FZaOhJvI
pbGr3CfxAISGZjpisYwRFJrSkWYeuXfjk8O7iyZkYLfieH91IZWy4n7l+Wz5Q/rmG9g4Zhiv2xKI
2h2gBrvEyrE/TywZGrYD8JiX3RD5oXKtBpce7vjtwCxlmeyGjnQxzYPVBjrLWPaw1wDWpPVVMB+u
hwW9MLNjQA4eg1kYM9pjD2zfJSveJX/KHq4MTq4Zbv2yitQQNPak7/AuTuNL8iIMdL6JvRlegG8F
jHuC6KNLM5aJxxb2jY21PPBzjaOoUFbb4i2wR8eLo6pnEKF9dpMT33AGeocfIJcDUXkluK+Eu868
MLM+fs1nGltTymoBauRNeE3Qec+JUseHpuDVcz3KH71xvMHGQMsO1CF2QwnKDsfyBTYA5Nh9H5MR
AxcnBkerkFSzRJDyTIYQmlo3H1mASm5zpNfNA8vh/83g37Xv1j8fdrZtkQI+v8y4QAn/h4PEPwyB
0Diqgf3OoFdAb1tISOLZl64hC7J9qxQm7cn4tNinyGA1v6+trAb9tCtJLdU7XhXMKcpaXaFV4+Dm
WNuKJ5fKUPLD/9FqNkf+WKZqGHTVyPQVhYMBwHJvEsbWfocYtOxoJ3HZuCLPVQ7vqWHcZyBTeoum
hrPS3xib+W8h4o2DbPy6nwlJB/OR2vdJpuN3JnJ16CSyYYzXELOrPL0RG8PF9WkqUpmL3sKSz3NZ
g3L5dlWtj0WXvayoDV3TcvYHKA9KaLkt7lBeFmv9zTDZyqdRzV1ZcxpNxXLLXofdAT4FrC5IPHLK
fNqLwd5sDZO1egOZ7/wQupdrc6gXle9Ajjz0goEZBNYS2rEz2eXF+jov1Q3cVECCefNOjVMsx39B
8WFO2xUtpFSux+uVseRaotYPeOsZaPNABYmJfLdkk/6T5Sq8BiRBbRmhZj8vHrD+3OmNQ+YueZrA
t3zPaRnTadS7tmQvRxKs+lfzrWIcVcUJm5c9Ba+GLkgJ0qiiyQlN6kdY+CR7i7Jaz8HbKzp3C+X2
YEfWVPhnMggP2OQY8rzBDpNeQCUYj4IuKHw8JvIkiQM1mvXnCPFL3MxwMaWC5iKk1VFndVAyQ/q7
jAcB/DSYPz4Sr66OHJlfAH0L3aT1TquDYnClnMpN7ilapXoDmosGBzIDPSJiP+p2gBfJaF9qBrT8
HP+Wqo1/ok6iTQT0EBsh1YIEQRW0U3dfX2JY4cHV6nj9q0oIYFIK/Xq0IG7fArVyxW+D113d1FHw
u4WRSOS3YNIq9tkoztRjtrQlThfHqenZn7H9Zc2urgfNU2YhV52EXCuSFUL/f1F7RI0D/N7uxKW5
uKpTJyinM3uTJTMBBEbea4x5XF2/tW8ecvd7vBw4z0RgBAk9/DFfdxj1XnWLn4+DMyhFiNfgXZVX
OErfaxbi59rOxaYJNFXTUoILqZNEQZBOkp/AIdPkuB3SkcdVNgG29A9fsqehQutUqTLW2F45/AM9
XNBlaGYfRxsPltJ//Ep9xKg8kaoaY/hIAAs1DRbh1f04vlHqG1BEQihtMwXPn8N+1pvLSZJ+DFPR
DiO5LmDCcqizNWLhJN0hsuXlJms0awTDPQ+y6bfN78k9qNM4QeYxGpQZFzkCAvelpfWVy//sOFRN
qnOpbZp7zA7/34wHgcOW9r6lZlNfiFndc3c5700iI6LuB4i8m/RZ34OiG9bUAKRK05C/cKW/8FA6
RPtt8e02oUL4wjN5CwrvxFgz7l4XdlSXVlTXRBoRHtHc72JNjI6WR51iGbyTz999a5CI4z4Oy9g/
zGvUkeXjZfEcoMrZ9hgiABGeIw6UfY6Rq8OKadzIcXvgLpwfZ91w9zdMbdUelqLk+k1dmHJua6jt
pArxjWDFvVITZQgNjkactsofYHF1s8VD4qA2n65kxiUtAfmJKNU5WGoc552HZCUmLZQcA9oULL7q
b5MFSLyy5QkE8OozfFEZPGvr/txuMolgQnbuVZQfeJhI6Y9iVBfNyI5/alimGLatUGLU71TTPclu
ePmVYQA61Po3U74B3ilHYj05pbXw4INu1Z+bc4VrOyxGXnM4W/wtl508RUSP97a+lWrgl809zWTS
GjiuRSfYNt4j0+uk68K2nSft7NWsEppK8zJCNfovASJF8l38KKqjXv+kBpVqVAudbK+M/ye4weQu
WDJTKR8SuxsO73Sw/avQKzRhpy1PN9jwDN9Gaom9ORzB95FGICTR7veFj6pH2kwpEPFHIrwyKm9I
3kyGQFGnfqh/VHVzse1gWkO33JR/f9t1fGbPCyYu8uDwIDfhh5kTN3dkVmBpxRP/J4J39qVSdW2I
siPdgjDgJNDBKYR0H/zM8TKtgWcZWYTPcxJrOgZA6AfMwIqb+Z+WzmXc5oPJl6Ai6Irw68qR1KoD
zOs97meBAqOlbdccMgE+muh89OsMVL167hAoUxpH4J2kcvdAM7pAoKhEXATAj2cycwWajHkOhwJ9
K8oRBW2Bjvnys5g9OTcRzsou7Ci3eL2LdYVODNIHXJiOLsYnIsS7S6Jn32f2MHYYKskeO9xX6KuL
9XW732yZ7dlRGXh7pwRJRsVjoO9AvunsUBqVIG1EKGei62z/u31V5W9FZxQeXG0wCusJIq1KTD2c
XoLqS0lE8y9QDYjvmKbtsAxQQphIU6SMUFKTCdmNpIbiTtvmzw+nu7nW2jLFwkHcvfBkFnQQ8EOD
bukniCAlvXmBEEdpkbWDfxau9N6b5wbXkGs5BY5ULuqP5u03c1m5NlHL8wwgm//H9cvvFvFjIdAW
rZuK7rZ7xni+t/69qSRV7gilAlOU49HPSvL8GLXnh7dwPQADaQiSxLZdjaN2E+9c1zdJdxLC2vPF
WfcLNjsbbVqVTikPi/sn9XtEOHKeWggKc1UmrqQVifEbko944m2ixNwsfwWTsk3clc0V95LZ46ni
oEnhqtnIv7tq8//akHDnj05i7Fl88wMdutSBq22k2MsSkjn+yfk/Dvj4MrXGXUmgVAzcgZ6rmlgc
tGfzZBH2zv2DWbITt0JVz92Cyfp889HUCm73QHJI3j4ydgRwztu99symBlJieI2JxpguCxN1CgdZ
vN9SSJ2TvkxqKAR0cuyQ29ibIE7JUJjUJU7WoPxYYXtUH4hhAgqmKM7Z8T800HWRSiXWAW55n4C/
Hq8FvfC4+/TSniOwsb6w2h5IeNCuia1zy6rzldS8waCr7L+zUKXgSrRxe+O3jQuznuQmFuMnLxs8
2LqObPgxQuD06fY5Zcpg4amD7A83DLE0tB4fWYF22IPdfVf042/FgYqbbd5EjVcOefvNc8S2gTde
pkubbdJwJ1BqbDH6h2qihree7iv4cR7H5OMGdPraN/RQW/qQzmi0WIfqLzTdl22U7e6AHY70dcQh
YMPYOU2G/iC0+jyoqCKLrOcim7G0BasrBayQ8WgMmiu3Kic382CSOzSleeMqMR2IGXE8zlfzR/NM
jUHbcEKjuyrVWTfDb58ClcCjWAZ4R5T9WM1Q+nCGyANZ3tTOt+a2LRXGq9jfv7xGT0Q4wNKvnAYT
M204seC9qb7xETgkFlPStQJUhVi/OCNJetI60u8YBg0LWto9svOiQmVSyy6oxvK8Ji++mNY1UWMq
tVJD/n40Lx/xdvPt1kRUD3mKcTOASC8RIY2qVnXrl6r60z3p1QwizXsf4w8clZZEQ+UKFBgOcIkm
9DnqJjVrlInAwoDqQyYyPVqMe3BCaVprHj70BNCynyjerrR12RbXTlXJt2tP/RsMh123RT2l2Eck
OeOAYk/q3+8sBFBB8cGUTNjW5QKTxvqaMx/Fc27bsC8hf6MMaFu3vCqXTrq3DHmdkfBmQoakXseV
2R8SHKPQ4sfpSOhAq6RA2wTqqPHTbFutThDu/Z9xzzw6RxOyLGcMhnsy2vIFaORPiztba4OyTZQT
RG4hBszgeVwc+IiA8kjoEtvVpr4SAa+WbJjuorRbnYqXNnEk2V8qB9rpwl+Xkz1fJZeqrX1kCQEE
DAeLRR54vvHENA3wvJl3Of7zqV3X6aVydb7d4kv0jAIze2Pyy1cBwIyL/t3C9uekg310VbkMF6vx
BtIgbCa+rb8u7fKpLJcJzMg7c4mEl6/1AqMON3EPUsa09CjbOoYB3g565ZgjFBaVfuh+shUdAZ+e
m/z+RMnHgIVgkxs1zMdQ2RJugEjlsyJJ+I0903oKwMG7VnGhQNGiVMJCUjvSJMSjX91qE/qR8mR5
2oISGcdj1BIkRoIoELnsZSJUTuDEtEfeEoMqL0YSw7wQOuDPxKm9VexcDOn0MzodhvpXaBO2NMtt
iEQo7+DYPjknnOc2sYNYrXYzcmyD5rpwFK5sGHLfX17BokYjSjM7zDsGnylaiPF1DXAzyR545iUi
79dgWqhYY5WtijU6qnVOgRGv28TfmcZO7fiRCSC5OGcvYcAGsojZstvnbEfohPGd/FymQnF/69DX
E7Ra8m2GPCXcXmBZSsDrUeG+ZqsnAJQSZnGxVLUNR9l+v4g+S9I0+NQXJRM4gImg/hZ2yrVJgBwI
oD3EwKLfi1ZQcffN1Z4tdfWZBiFDNsopRueMDjpGhxtadLmMwChBlwyaJxTMkegKenMQB1mxcJnX
6O6JxE4XjiSahoGzs4qy7IuNK7OPJuYiCKsiaFsABUmwTLPn3jLTo4npsh4r39YsPG/Qy8WloIdz
SPHsWSAUV4JDwp6me7d+rW/xrALrTgmVsZMUUCOt9UYsv1kV8qUz0ECLaWdqBPRIJlbUABROKi73
OSqPPal+PNcs9KpI8WgSPH2B/kH7QwAToI1uriwRmxy4PnhvcWeCArjQvU/7QZeOD6oeEvNigZ/W
noU9oCRC+C1iNF7FfookJ3KZJS6+l+tZasIy7aOT15xBotYd6N5zLRbBS4mHXoBz4Lh75zijDck+
TG4OJ9S/a3D+M6z+MWmCf9E9oYdpei4YIvgrRM4lXbc3Ab5oTiBUQX0GmdELp5AKbBOBKN7kut+6
tNGzoMBl+y9wMOcwXKlcxLX0EF4LxLOf2lNliJN02byJGD17Rc3ftyiFI/bzXlG7pFAmoR59x9h2
6DFjtj37cfKYtlLbXKKQ/5z+0PBiVd1JO/oZsSkA51UQjYKFIn4fSYboduFQ4m4+1VNQabM+6anm
sW1kkqoa9YHePtUIEv6hxsIXKKxVR/m/rEY75LEhogHaxunH0s8FtGwsmxlACvM4A+i2X8LOhz1q
VWUbRYo43vXTcjDfEsScynwSSwd5Qz0k7dUGxxLaptm0r8w5qiVN2jzCddCJVO9Ei1A0nWRdsOyg
I9Mz/34LDVJIyBmUyfB94lRsK7IJLvmgM7WWiBVowrb77O2xQ2oiP5IZh2ZA+s8MiaRN9UETu48b
jyaENp63GMxKuZhgLFDBuoWWyvkDMswBA+3t+0tgvPQlwYAYRdMTFhfhavNkGjUyARRwXD+OCb5T
onRRxiQ2qbhGSRxXFOEyBR+RjVfeX7OhedAFTlqNxd4sMWUDJBgDG0JR7ZixX9SNoXlTtvPJzyDK
G6tQhc3vB3SFI6nJhqnRLPREqcvQB/6BFm6G6yx7103JA6egTpKw+ru4QT0eafeac+Y00iVZOqkK
su7AimrGVZflbFaVFrun07C9gwfI7m28cS3wstqmWuPxIKeRh9dQ41dq028Vtbk87TQLhe8wrOoU
LTBS6diyS/NRMenrvpccAnISXqxbuuzvrAHtkbMNZhOTX0up6X70opdRLoFALkyH3L1J4PhxEMC9
bfCZ/zJ8M3wVOxRgJ31VZ3ZjgpzIukOe0Rj7BOFzL/yXg3PexAjEQWJXcS9/SqisMhrSkKat1t+1
Rh9iBULC/DuuebiIw3cSfPn8gleycL+tS4fZpZQi8+UK0Yq2Uh9DqxfV+vDgxqrHNJ9KHnkFOK7O
zNpn0MfIcpCFXtrX2/mP2ThyiirSLR8d/xJlhzVM8jfJFtmWv+6ZKKPDbXwfNG12BgiJp7aRbzEI
AZYE3wwL18ofYO9yoT0/GyblGWV5TBDbdygmUulO1n/bf2qWPYkJdcEJLT0su444HyDB/4P9iOPq
4oGrLwmWhJlM+xXtLutMoS7NqE01YSjH089EtjY7EHP0wX69mIeJ4mXGHvK2Mmw88VQ/a4Eysda8
xSayXazK/vft+XWrTVGNnRDHAFFcPSkOQXwAmVIlbipIp/98yFF7nGrJXS8DhdSgPQdOfErfVdfj
V8gSQPTgkUY9+ES06+LiWYyL7ulSIEkWHrbgCbVgp7bmMvBSVAg5n2CSX///AyC7YCJ+qqLvdEwK
LKL/1toiOlup/eQqZkqYfiqBvLxHfWQIL9IYvOXkDCHiz2m/cTdHNVO2beXdt4IZL/OIvCWBt54G
u/DPvGPsUVQhEGPiQjx67alBwwt4W2ZpLDpDm7Iha8kHx7rB27iZjiIyeX80VKuUNUMqbg52PdVF
jUBvt/N8ga+clpWLQpWKuDhfw900RzI74HooO+kMlOJD22gjgN3ivQVdoyd7HDbc/KPSl+zkCqNj
yFbZNmjGH4/018MkMvawkoZZomax2IAxFa6lVNm15CHSGkn2nXQgA2YNRvXZC48bWkWt3ws1vFTa
Q27J9mpqXGDX79OUBOeQkAW4DF7M0QncV2au3W3lqgaV6ju8nZhW96d7codZZjetlp41VanKlW5B
+MISCJeAEb11yIUpOJOPXkAso+/KRkMZfu/JshszqvKST0bINxBUND4o1xQgW9XsAvkYRMid1AXA
tlUph8w/XhSmoHz0ZKjFxeABRkKZo5q4rOSuTxJvcDKJCDKuDvl3bHLh2EKXnUvpUCEOq8fcFmC0
D6tM2Izon5SU9hKkZRe7OrlZoWd0CaK1BPaPPSV1qQ4GW/XjNlXixnNT2es7RHKQIOSX/mOZAazh
PFBeb7QiZHhJnt2B7mY2kBxRq4lPNX4gzp2camkycCJAY6vlt1eLWQWxih9kpebBFwcs7Tcm+4fe
zB8KHMMmXMzqefuNecMJWgp/VKcSFphv5nT79qT5DRldM8oscomDfONra2lgekzd6Gsw2pG/uqi7
BeW64RAxyCz+z2+yCuP54sZqefLvnrgC8XHGac8XFh9rlZPw1MP3/zpHnJWZL7PLEotWjE9aHSpc
GpTuIbYuFfYZtsx2rGK1Lw93CNu6px0TPhtvWLaHjldcz+FF7MajAaim49UlUHewwH3xeMqqs6Ul
uJ0ynIW0ubRZMQRqD/GlgRcJoiOEbrIujvdaWzrmseqk2fi7jMJhuWFapJe7gBwGY3SltNmahJD7
/tuESwWaNFkkFNhUz4RuKOSRwxXDRdCGhSww++Iacu+XQmSeHRYpMTrtXNCbueYkbL3trTRWtwtN
pSfKQEAf1nia0mEc3VxqFt9MCPYi0GPlHKEjm3RY8taq9JNqp4B5w1Oxldd4LSZzPxjOv/+xCG+l
wG+1Vx3ZAqk/GhZWvGC2jp5TnH1K2oEqWVW7jGDf7o+PiXk579PqsssDtnfE2gRtS/OXrvmTMovd
7LJBzaNkr/i2qx2aZeR9brdMfAZOUPLCcTvWystTfPF3/AnNLLcitIe1jlx6/WnTzjXeeN+tC5ql
RR9CooWZ1BKySqmCx4bROhTfYBjWoTcCcFqXG5C1sHL32kGX1UTlZc7bDs3MXCdCFZzKEwZyelCg
UuzHQZl/b6OEV9pLDUuieUJBk8zkRLjRHmDR5DClp6IPnjUQ1oaAnHz5dbmlPu1oCpUb0zoXpF8/
uNhDFXqUUzB3qvSixws4XAw9I54TphE+E1GXyEEkhpdL2UqLoiKYVcccYJ5YwqOaBT5BSuauR4h2
MB62mar8u87ozEz2sz7mUZXVkKcLbE2Ia6nhQej/Rw4UmG60fH8m7HYX5JYzd66bMFTGPUsxoRvQ
UDC7t2fSzVwmMOXkLus4lpwt8GMspdb+9B2Syt/NL1Tz7i13fF36fYzb7ulklrJcF7aJrXVeDR0p
JdNNYZKdX3H166svx7vu0RRXNnFhFxDKVM/3Ple+8nCZihnSg5NDXTwSTynwYf1z/tpmce9nLwR0
6pninekuwcgyf5vDP4rGONsvahndRlY4ZXwL6Qb1Njb4z1gT7C5lQzworRq4T5Pl+ET7fX2T71SY
FnTTrMjpUvlAVF9nEo+4gDUcp1tgpNEnLUzCnmk4T7TAnqzY1kkE554LrDD6P1/uIqiARua5Nogy
PWGE0l1OzKXuXpLKHu0dHCidRPBmcK4mo2rhyyC7IX7sjj+Dyju/X7C4Hl8hgQYD3uxU6u6+7NcY
m1asTfIfIeTZx8MiDRyGHqB2ycJoWuKxEG2MZkhhUCYaU5WTfNbgiWMJ0MAArGKF3lzJbbJXYxvX
6lG+S8rT23cJzkUmii20I8S5algyxYQ5P1oTQlmRprxxdq9o2qrZoL0MdhJ+UF4WB2nmxZ6spQIt
No6OBE9V928jIMo9xNHV+YvwOHPXX1cK+Pvt1OcqiLqOVzmxk1aod1Bhcwwz6Fd5wdOLemyzy2oI
twhtEhGRJUglTLSNZjaf3reglNmGngkC2HzAkkhW9hltWdsDwTd+m+IS4O0K9bymcQa1x0HsKd/v
Tq7fFluTGC3TIWXa0Zgxunl6g7VHuaxxD/FESx1pYwq1yeR+OabZSjp6i+R80mc8DvJ1R6A9+Iaj
iaVUvBFhZReBP9XAxZCZBKoB/PPtWalGliuovuy1Sv5Iww2NIB1Qz1OHvEfKmTzPvC/h7nGUSc/2
ZBG1tb21HyeGlsEdUNH2sHNUrPsCxIQ6Y3ios/oOs/3rJmw5XyvAN9zQ/5C2ym/5bRXkFRE7MrWn
0zIpvLSxMxMsFLndVcwYbACf/GZm7KVgbhEDEzDs36/Gg26R36jznubgPYTFNu6H0izWOe0DdvQk
TgfZfj33sD+/QkZ4cEwd/nrzAvVnLzRRNrDOoV2iZWPkbQqeh8CKwFX80BmFca/WFkeaOYwV0LYG
HhWJKhiuqQ1uhILeBDsXcWZrvSCuzMU901nLqdqutcN1w3aWooedY6Agtw7GhjC2MULliYpQ3PT2
VQQx9nzJpn1xxymdP1/bf4DtGBRPfUATg69+yJZwsL85vIE2kjkQukyz47LgXgDCYauiwwuQ90RW
2jO7BubYrHOtXkrT7YDsdeJBHVlvrRnELOF6ej1KkWmEQOnIQTa5ZHa756sJvoQBOF00bembQYSz
Y8HUmgTyyctVtFDJy9v8S9q66FPjeXUxFuoKzfYooQJuBKFTdO60I4glQLGEmBPBCfEs5MwlyTNB
qHeJnv5y+CNK702f1DVd/NLpcbZZzzCtzSbaUN8VB8UNzOeHgePXjZPJR0MhkTLYKq8nq97Ezsb4
2rk9Pg6rU+CDh3J4+6ov4GeieMPxDQa2xVsLZsYNP77oXWyXFkDgEQiZV1K2KaFkqiMX5bR1AjJD
1LY0wgFGaP1UfokIy3tWTOxTX1NNoO4ynSwNatizkNDUSjBtQp/5A/h2QqdlqbLg6c7H2yaqb4ef
IASiBba0AiyLPkjUF3GG23QqJ14pBBuZPO/ANdGX4Ryv9iW+tH4VovzISuIhSoeNvwo6WqX5nflI
OLMUEu7mg/zDxndmeT+Zqx4Z7ZgqIQ/fdV6VNJDs8n+gaop2qmYW62jofoaJbaAlmZDqmwfoy3On
cgF/Qy9d6WKz7bUS9qNCyHww373N8hB6avbmMoCiae01aSbAjVo8wRMMzDVuRs3VSR7X0+0tdD76
FpiJP2Mn7iGt0mnVRIvUqeFe/DA2VCR4AdqzehdwfFX1PoiVSJ5cR4uzmOQokzAzJTxQs75yDUtM
DiVhnrvveYs1augPD/NOfG47o+DrODXk/lOkYKnIOZUt5/alAqvXr2tUowRAb13wHwLdXnRioEll
5gQCsg8mtVl3/0eX6K3u6K2UjxCv08XKv8mvEbZtKykEmUUaf4Snl8I8UkafhmW3ylSPUsGH7+p3
A7Ipe3kWZamqDIGx7g1gjOF3jWtWuSaYR+udWdxRAJ+NSaAyZIxZ5eXbby103OvtQEq73wPPuZ+C
aM9vLDoV99YKdoxJfgIPMQnKbEVEOZb9YrY7E7QTFugWtlOb9Kjo9Upk6a6XHNZMMlsyIiVrmwFh
A+SMXCCZ54TTYBd1RDdUKgRF45Xnd3Klq3jZ1hP2rJqpD0YOFW0ly8WsyKRZ9PgreXiZiIsOfm1D
eo8NTqlmSjcvW1pYJmW2RuyycfXBCtGW/Cuf2mnOj5cPRQUw9MTAFVZzR8YqoT8yUQaxpZgYgmSB
CaMGxh0ZxGJBpwY8eZb4jhQ/LMGlFJzp/DvHkXKos3oONTX1KPakUzd3Ti/CeHMeCK6neCSyZuOr
h/ayoxyQ0PF38pr0Bc9yp5RzM48xuzzSdVt6ljRWngI7fbmjs/aCKnAyd6STkhuR9k/N9UPOldWy
xX2HmJ2DB4zRThlsjer7yYNY8whFj7DkGSJgDloNlzgTddHZm6cf+RKSIgYVblDr71C6qVT1QWa0
bo8b2cAhFEv+uGlDfY9Mbm0WgukR/9BS6H9yu9ZmoB78j1w3GPUkLL0itpyUAUsuYIZp4EPNtjh/
Kn/XFGIea/sQeeugEM956HOupin6ywiC7Kt475oSVK5L6tgbt84sq7F26eBfMkdJA3zFPO51Liju
6cqSPa4LQc9Gtexc2Ksy07AgtOr+HAiJccEEjeoOBZMu4yiaBXq97CuMJg/KaLxNBFpat2EtIxIC
8LZ4sTXMfAYVCcwYoVcOkcbtkP0GC2NZuTvU43kgfY55fhKpKfVN66CPEP83L/i6W3O5y4BlfINW
Qg+pIEO1WEBYaGw6XF84HYrCiXK/gUdblKEc2bSGHEOoUbzeNBC9CXsK8tH48wQT7G6EQWuS08U9
TaHJg0JkMEDipW76lU9uXCQdln/yzixMUpYeNIuwRajDS6LHQHvJS1yHawUJ8PKePrmISUttAYST
k10jV5LcEA3B/0RA0tUPB3tHSaTjYBRuZR7ZRCReJuRx+vx+1UkzwtiH3W5x7JmDlVcFlregZ47J
kqlr5WS4N1ycmube+Oufx5OmiDPFwg7y4H9qMpVFpDhxewvzcVaeOcDbPC05zb7W0TcJbPlaHlUH
WU/f0f9Q/3bWBZfIRW5h89ltl/dZ/x52psuvEsagq+9vmcWk16glI2HIrqKw7taWdpRdCIW+u/HA
c88BsJmsVz9g2YvmlbldK9laK7NrBCppmUATzJSINr92aERzhR2h2k7Cta+CUpTikwb/ZVFjSO3A
6EMLEKR44/AVw0T7B8uoZe48/47g+p1XDcb4iwUTxut94fJieajtQIKRCUF6oN/lcoXMC2Pw7ccP
lNmQvJbqX1uwnssrAxkVqPoXGrFa7mkv2uBoLAMk4MCp5ieTwQUtmRjX7TWZbd9O4gYLONshQczG
y3NUqKU4YZhQ2krpGtZdyeziPCt8ELxSkRKZgoyihojchpe1jytdwgPtOSrAypzxkoLIGdkJUaAv
SLf252a3MDBTqEUnT8Xj6Mq9B0tUyqRr0OKwTL9UQtQwr+2Lha5okDFgaghtyvH5gFnO2GOhDD3n
8ovBUFQbFnrPZE4mvuMVwtIFi36Ploz9Xaabd21DdTp/s5ayxxo2oH0bGsKLZ9mWQgmToHfZvb0y
63VDRjN8LDBEkIBhyRGAcOHpjl2BcZveNG7usgAGeloWU+R9iS7sgW5OaUr/96HPUgEktZnhZe4x
PohgGjAWxUDh5qOfchrqeaPNZdZdGdtY/3im9GZHRwhDUxKChMP3gvqMAD29Zcj0RsoVbCmdgm9H
c3ngrClzb9zgwfuv0pHHJXb8doCU5zqJV76F13eTwGz6ysBG9bN3Kv6vKbVKQer+Qu8wfC8l+olr
7CtOYP4Am1tXqwpJSR+Pmj520skQ/aI+8RsCPdJ+o1DjDA4EwHniRvsrIFxB1kpAtYibembQiLLn
aw3NUXZ76+h5n1+LKKBMDIve+1UPmAxpT0db5r0pcPvtMG5YvsDTAs3mQbTSqAH4WOPJKNWAwF5V
XZOU6kgiViVIBX8g4Ctmr5DYhJWvi8jApwPHzrwkjzP0L+BLCgAkz/CUwg4qgJd670NiYOrfFZIC
kLRrWVzfmlh3/TGQN8x44n0n3EcHbdLJGdLICOJUId0HJybfDQMvvtVldr5Q9bgOXuamcD8m75dy
Jpgw+u+zG2OiOHQI+fnigw6l+822Gsef4egoW/mprvqIPr8KgjIVOjUUNhQ7U5SG13VXuJD7+iTD
hnty2S/ODMiVliwO3XsZoq7AqMVOlmyD+LR+xYXHqjTAk19/f+G+2m7sTN+T9sEGPLf9S2QeAZbk
lyCKPLUM2odZaKcWVdnMF63FaQ6XKb8pGAky0cycjGr8Px++ul/NZdfDapa/N+LiT3lL0xw2aJ3w
rSw/Y63syjbVCSkV2eDF0jiWz7jeQzeJKbk0cLF4zxa/PSAuYvaCYFNXukWb3fa/qWGfiLBrhN4j
fND2P6ktewmbN/qyhjUv3QWu5Q1pJv7/p5WqECNHseNduLrHxvtDIreCUuCFfuESqmqg9ly1WOjQ
OlkfkSHeCrPFxnKDhkfgZVJNZjAKTBm9kq1pjwfmcrkZDhlH1JvxrIddlDw+1746ahj69+v4+O7p
z8erFkHUAxoAujN7ORRinJQkGrJFel4wyDnPxRwHs60n5K+pjmtCWJEbhJ9CarhrKFqzExrYGlNg
tdoR3yNSV+9cAIcyxUyEVQ2X3U1j9OZSAoGBVQ5DQQPQqmNL8tuJ0nzNlHuX5gCte1qXCojr6FRa
OOuBKLTfYVncmb75/IMqjfp8WaplACJPf5fEQLATgoBHEeYNCoUtalU7NI4u3W3nGUekPxPp9V+l
LBmCOzz2ZFbSYY/J5H7JomGR+ufFof9TR0NaF2+txOFMWc5u+c0KRsQzyK2DvPMzNuF5sKQMO8iY
UuplnOuU8zZLWmdywTYleZ0cQtFcH9oPQmwMt8iLXruFgGt863DylfZ3jnrQdGvtt2VsTskLIIT+
UP4uirIGj9Pxir243g9TrtJirl7Xp2Hn9gP6fTTqm0pWznrGl/W9BSJ40N7ea0BerS/+Tz7wieKn
0I7JT0IU/b+U2WF0aqBU921L/xEtVNBSSI7/1EVZFNPlRDhUqoXMsTmN/IvXu4C/cgXbRt5CRtE4
fEJuAF8ESFpsazbGEcGxLrUXfc/W5VjVFggqBVb706zoQ+81jDIXKSMOlQrXD/MFXpoPGhdvF2/d
17LQz/T8B0usdoV82WUE9HfMXDWJTh4KkVANS176F5Cs1hYzncF7OiPQWcn8plC74VbiVvoipNdi
1XgVoXzy03L9eYnQB5v/lRv/FR04MATn/py7LRtoTSwOuseQXDGFyUpTnuv69xH8QqHO6k48yqF4
nM93VwDjk0ZSvwxsPfmxoMUR3pUHsj1Qt8JGEnICAgnP42P6eO9LCoStYT+bTm0vWy9HB1Sygt+z
8vH0I+s+w/bYB3SKKcSjCBGUxF9D4pyMnSnL/UJm6LRkV+G9Q3S2f/f1yoNT0tU4Q8VnoGjbu1Xv
lwjEjJUaK9myDaq+Ot26RgQ+jhmxzOBQvSAd+e27b12hKuHcwj/ahvmvUV2iFDvFkfKsbny7gWBP
L99843AiqsIuNz7WkbMcbOEWCLIT0br1PWJ3vU19D545EL9ZErfIMg+6Do6OfJPcbz7TgWne8VMd
9icePLDVcnGk/egVCGswP3J1yYgWFRHeEumQhaep8kmTYIU8EngwMObP1YYuKxNzOFVAg0JxPMIb
qexmlCgn00ub1thvW4OfDYyLb9Jnf8VQl9WyhrAI/Lq23HxhzmNEE85JrGsFYAlbzuSXLAyC1ucG
iz+ECyJ8RHcM9aRmyzNcWW5H/sWtqXAA35Vb8ANKfrpGwiYIgVpfz7UhU9EFdX06YxSbM4YgqCw6
U2XSHzhyj49E2ejUoOYc89c/G9CKY8fecwVThtKD/AYaLaYeP+pzzIixRy4VpCdks7L0pU0opnGE
adj7+NvPbTbVms+x3VXZ4+AWfXeuW1+eJ82R7qaSejSg57QRKAL7y7Dujy4Lzj3LG9IPCRSR1p0g
Ynk5mE2Ok54amhw8zzxgKpFjsUeItcvHaBUUE1jmPdVUKpuvLEW94oFWz+gLADiB33SoLMWfXZkt
rmmQNntOLfklF8Gcet9kNKIrLqRP/Rb6e4jWUSH8Uzdcj5WPD8H6bBsp8geji0WzZHMZqqCi08JF
Gen5dAC71Cxb/j1jtIk4QXRQbICZ79qIGhBfM0/UFdfLHZi20KLHgJtDPKdENc84ZeCmyg8VTB1z
v7VYdunjo02MDKl4UMGZuHSESMvgtV/IOUQtxZAoBYn1QrREM8gya7IE6ynqrfrGYHG2Nzgo0Ijc
X6oMrM3620EtuDgXMTYpSvOoTZoUG58grGKFWYhhyeLsxLfYBMflsrRlqCOCdTHUyOi5LeZxbna/
hGCD8OzETdYCrcHUg+2sSYixdicXlzJ33NJVUEaclVrxLrKWROZYIDtpPG2c7VLEMQ3dEinmj8La
qTxvX2uzeLWCfsBFvJ7wofcCndkd5FLVcs3db1YMWks8AFRtigyvnPxO9Z2cYxLWG+S5a1y09Tt7
jeBWeDvfToV9xoLd0Yl0kUmCAcsz82PmbXHOQ5sDV9fyQpexMnURGT2o/aWhiQU6JJUwh1tF3jPu
Rs4nTehW3cgaMXljcwMw7sRDj29C1w09/drQbjtj2F3PMJDFmamMgXkyfrqJDzuu8vP0V2Kpe7vz
j78zNrA7yN6grTW/0FVg/mty5ADYvPNfaLavPUkZ8K8jLA30NwBDsF25GqycrzG0xNBP15g88UPz
Z9TJy8CWuZpteM/fiZ/V338yejJAsB5vxK/ygepqTwLdgpcbmeoZYXXx26nOPiZ/XdOssKQhOnbG
Vk/n+BucKwvC5SN7v0ANOJWot/nZW80XfMpT0H3RjYp06gTKF8zIT5m/f26HSqvpg/uy+oKl7auk
rO15hBVQvQCZ42mwfy4KLV1EKlm32g7K6imwtTsjJV86dfq1bnD02uzIid7ngvVsI5Vfnqa9KpsD
qZoTtnwTYY5Vvt1TZwKr8PAXeOPcCQwO9rKzwA+Gb77y6WUVW7kKpsxiALKr+cfj6RegQU70rXzH
8GrhDDmhiMzed7HlHmRnj8odT8oonlbPeJrTxeKZUp96U5xXe54KPYGX1/ZMfySAAOOYLwifBj72
CDrjlEL+q2C/G/7EPc3WmvzxwiB1Q4vu+uw7fgUiD/vIxcKQD5Xm5cv2Tv44PiByM60uhLeqVxF4
c76yZb68OqKhZVcn+m+poXpIFCY0piRi7zpCvpjEVqye730jgSs6IwD2gY5ZNpf+FvnkojUPWpa5
3KJs1h8T9efk85Hnb6gkiFPJ7BoMLRKa+z+f+d9VOrdqyQZ18fuLTrk83t+ZJf4FuAQRZjNHfNN0
w3yDSmHw+a3ihMwcFNrtwMd4tWUSij3s9qev8S+QdZpnLzJj0IJ/7483lTBv+/mOS8C2gVE3cCeX
WCrHA01Qz+KGfN/MISVICbvAbLqrYyh0JAu95AtuTZMKOVk+7d9dASdh+NqtAhVnUJaX9p/Zk1dy
H1/oY+VanW59c2lidaGNo+uXMKaHrd2h90Y8qe45O5EhmjWkFc2c/bi9TAdo93gk7pkrzsqsyXdJ
ydIXOy5WOW78OxXA3Uvs6m97MCgW843u515Jwe28BcU5ZqfNR5BT7W0uGu04Xsd3KDZvPCF6US/D
TKpTWb8r9o3ItX3xVsWQPwOK2mPFhlS3scQbrqjAjKekHcCMNNM7gLD+sDUnukJ9PO1cpHWoQNUl
syCNwV5yTaSUoTcKKIr8QCD/zIotvKYDFfYDnAMWeVLNS4IeW3Ya9JVco3CoktMz8B9Ov6IZx3+g
3a9Ilk6WwYECEMMNsk3ojn4zbrOl0AtW47advMrwTHQK8l3sVRWI56QMN3OqZFkXQ4CC7iyY0mcK
X9dwmyW6t6aTOU87AOBqk/59p4j8bNSEytamo7kYtHexmo2ej81KTFcTxNK8mz4noDHtQTPdqiJz
5TsZNexWrhjyUWQOzZG4cAVag4HPGtUvKBbdadCsnWwpBr+VJLKih32+jBLKBZRtBAhxX71/hzgU
yiu6pwkyktn86Q8TWsgHYKoQ3mF+LG/qrAKWLzsozp5oixh577sCJouz2O0B9DC91euu6BfDX13m
U593lo5ZlZERhkfOuEON6nLPsiQTYXFRFIYl48l8EMgcnvC+k8HfYnHQsncowet+2sgdOeoridFF
/9hz/8c3pyYZaAEBII5NJ+y7aPn6DIc32Oq+mDXVchmRH7CRD7Vcr5lJgI87Js8C2Rbp+TJuyguf
hQ7Sv/cc4CehzW5SzZRHFTs//1nK6wwbs/PRALjBqqagfKoYPZAXZSToWFn97cpfvdtT6IbKXRJ0
fjTKAA5i90yQ1eRADNrlWarhNRVX6eSDv9Ki/5dnUeUAGRwVOgvTwZEC9eVYXeuJU7nDMTtcEo7l
ZUXuvlxMkkdctpVXMhrLBoKZmC4YijiXErtpUzB011Sp7RGiY3VKwXkKhReq00z+CCTEnQP7Hzm8
zynSOOXUpbHwG7IgPFHXPYngj7Xi6DPpeuIcOK5/VKKA/RO5cOVUqMXwf+pIlSqkfZpEXBEKGWdc
R+/u5j+VBMGDqPJhDdz8l9ZAD3esgb0Qf0Plni6CSGFAsWLlL4goQvdftNyuW9g4ELg3iqK/P4MJ
NOVJK8c51gYK7iLwph8cTfVOi4Y8Z2pAC92q1wYvq89SBuJ29/ylUOPHIWvSDRo5OkMQaNug487K
VOWziLW7HoT0f7Zc6CZk6NyCD7dy8m4eNCC00aGOChR4bPqFicyZRx9xIX/dVOVIk99ntVPnK/8F
d9AdpUiDYPKbRcRX9hWrNSVPxiBiNKXcX6HxpKDO/SgGgXKpnXUmTtBBcxFkz1MJClQJ8YtRJ99a
QNvuNME+s12VXojMFf9Zi7wGHfaaiF8EaRb/wj42Ylpub07b7K9HSeXhA/yk63+vi5EJkmrJ9y11
GGfLqTt5+BpYT5N4jmuOtDDRfOjIHZZUYcZLoJsDVCGhR33scLHfdjdY5ktPvHirdLqg9Cvm5WXI
0ggBQpdjUmsueJcErfmEjZx6KGj2D8bWynOiuU4AoXNo3nrkMfDOKFikzA3F18U0CTdKPyr05Epj
cPsYVUpvIOwksh/gUAjR3uzc5CPahoiQLu4SJToqkdjJumf6gjcuoOv5sIFb8C9QS1nfwUQrXE3e
OQh9xoi2QuEmyicxLkPg/26QQM6B/HWk8418r7GCTaXeDmfAPZ02RDhdRAOk1Q5vBTh2khucld8R
GJTKgB05BINIWZxq2ugHkKNiIn2ke06Gq0kw51V7YiK/rJWVZgRRcG1VLfj8cU+RmE1npDCpf/oa
xOKVFxpPWCXqa5Iw8Z/OOz9UIGbZwtd79lwBPztkHmIiSs1xinkGZ9WrickNviX7VyrHPh2ZroQJ
wDaj8DyMVcscF62t9kXNj0U5iLGPeSqnqK7A7ra+Yb+lHr6Geh0tfzfm9PSILh2pNcEHitvRbHQ4
pin6MbLgtv7NdJWluXz6/YcdZddLC5kXvdMjjLNYLDlDmyXid0YpHFrNcFs8PCuPVcJ34u2yCUa2
KaKjj5oP+baxBXg4z9gl6lTpZxfSsoJtLBHSQ9P6pkTVzlqZGuWcgYzgpnCviEPOpDZ3yz3nhRaf
MWsuV2EMbJNriIQku3X7R3Lt9wPsHRgzSXis2k4gkLWoJQMQwSXmYcD6QR2ypG6onpghLsAXTirg
7MFm1/y96dV9KbIQ/JKfxqRxpIjxADbAN6WocpvgkwBsftkPNTHYR6NMpiAG8QXxT99UAIe3O14W
FmLTFJbkf8CH3r4lJYP9prqiJ+yYBWNvkdVNN1eudBnF4gZuOHvxeJ9U+OtSR9vD2q0cZXwscieD
dP21MMIuf+570xgoLsPqIWReURl9VokBA2mxGZ09dIXLYJ/kR6SEtwUVimTpdizm0BOHSaaZ4EgR
uGGCRySk3oo2pjGkJFCL/N8CX3voi4MpVbXtq9DLBkDO4W44uH7nJmKi4Nuw8FvqAcxvP84E2sEP
3s5AQy7QETvv9reZV7YcjEvgczx/cUywujUXUMpknL6fI0fzQykL9PB4Jv+5ENO37EELR1CmOhio
kllA7RRLVdkzDNwyQjaiM3Wiyt72uFlkMAkjxjqb+9cY3GfTE31Ez+1bXJTzLEje9lmUKz9ReM49
2MvbquZTnskIux/hMoTBPAvz93grLHxwPnnaiXtjhrV7/DTDswN5YhXPcDUkd0ut+RYFrH9jaBij
MFvI3lQV8ehSy67Mc54vO66GcbcIcyPuQf/Kebjfv8olG3XIqK9mT8hJBdlSN7fxiYefovkVlQ7X
K1JdmSDweYSPuuHrcGOOQj6IofDlBqGkjGm9oPsqv/CbNr1oC9HHIBwC3KNheYxn9lg0ISTITxL3
jsi7w48Yn30B+iXsvU9KWU7kJsMKp6GRpTE9cDBysTpDijQEFUKxG2sytpKFsMq8li5lbtQbO1mC
wGgzbUil6/SAKrAKUzeCVRjhmUp2Ze5rZVuvrFe997dSjp199ddHe9u9Iu/gg7RlwJ8OoOTTNdSF
CVDIC6eROa8x3V5I9WedUTr50zZdJ5jbmwLYuKVFlonXO46Ng6F+CYU3jHmD/N+agalqre8Ysdmp
Kv+AOUy7YWbDl08PuS7+TNW3l9S54l6YtVvIgNSBG546S26dgUXuqhMWphmqNCRywxzdaIKMuYkr
Lv39P96To3w1OVqN2fxENQWxfQqp2DFs76SiXgfDGDfaxl0AF1UKUd4YotL/YgHdXF+geFBD3uuD
c+//kZpHjE+u1FmbRJGwc63sMgzHfdS8J1K/3TDSFdXEc9cKxoF9OmkcsZGhONoDTDrlIlagDs2q
0gbi2Divro5r53T8g0AOl5ZCVy5UMEPOLvaNfVZqB8bdvGm/GrNS2ausMnHS5CvuD2p7Mv+FBvAL
SkTCtpn/OWWcP9p6jX5ucaBrGLGcCqJ5ojE4uUbvQ6miUnoavSTiY1dqFza/ZWHa1YS/EB5+Wok0
CgeRIKY1H9C3QmPz7KuMLOPWRzxmoW2/WoZAj4rzgqmYcgCqAJeCgSWQ3lqH4d2jeCzllTRJUiDN
S5i1CUSDIdH+ctXQHK4V8km907OjaaviWxImf32hzxCrdwtaa+tHs53P8FGZOrKs63rNtMSHc/Uv
yD6wF4y7x/1J4Gg57nwZwPMJqpMJhrJkekaBDHXDU7oyPuzekNC7vRUztPGwMD2x3yf3YJYLxr+3
TefZya4QhH/A1E06Xk0WtHlh7GHyQ8MMBmVoZ+WM5eACy5lfTaV3Xg7vILB/pZ/PgISxJIWSntjJ
bnjpEs6d7YsUQBMMnNcrEaxE8KIxvIJ5qrn8E6HcMpTmpFAgpXq5DHaeZAWORyf1iZJPm+Xfa+OU
4OUtBlaTB+6bZlx1OS5M9MAmmXcNZ2DaEO2zXcxRnfgEA7jFoUQ5EgIzVmviy4i/td+AdPiWgWYI
rL/s8emmvrjcacvYMEkh7vmcBVS19cSIyO1kFoQAYVnvPaXk2Vhx9Pez1E2SsHsq+npdDy155WHc
ayIcXrPzUXCzSIsU3KU2LdGqTAnjt5o8mTuUyMBDyEoqVGqiUDng2aTAMQus838CM0+FbAn+SsAJ
seOGtl+2gjZituMR1U+QaZcKu1wRv3boKU4XFGAtVLNxuWChHQDUdnV/Oy1spv7/+7I9XDGk1SmR
wHZDEB9318WgtIOxmsH27czLCvPwzqH0QbgZEfz83mPUoPKA1xfyJreWwtNqyvGojyfSiRyfxl6x
l2lPZBKuxLzQDN6RChb+4e3NLJa4ZgOV60dyl/SG8a6TPFpMz+XybCqpaLhcGr0GBL9hahBSk7Vy
ZQfB5DT44Lf/nlrd5QNr0dc/pGuCBo0JS24KSMUUy2rtUk+C501ge/IwnE/FSGBzWhEpRvMfKEKo
X4ggPnMUaUGLC2Fi4WESJLoeFg6IGx3Fdo07QMUaF2zSm4biB4ygziifkcOP9T6vVb4rROmVHoQ6
fM1oyuU5npKXwJPS+r49/SgUBXjD2v2QlcGZPyhW7IwMEsbL4/S6cAugz5MLASCpw4Sz3k1jmekf
C3IPAMDo+BKIkxVPgr8eSkhUb81w+0yOXIqa+iYw8EtvkWhKnkUsKXM2RqRGhqySV3ZJwYrHgdix
DiyB2f8Ft2/x8u7ht+SvYNH5doKGB5pfQRV5xhEZO13vZprkoeDi4V/7PDba4ZlIW+Z9IQPzLj2R
6Qs1X7Vi3iHdwyE8S9HAtP4FPR5RbEQ28RVJ95Hgq6vjjbo5iF88k5WOyM/2pQfgSPl2ikpQDYLr
3e1tFcY2Dek4LH0exbikssuMGUkiWqubn1oelX8LerSeYKxndBjzIU+AWFnd6lFUsR1JBsqGarP9
sO7p8ntO+kq/KZbKoaK84QrO662otXcWb9sASfhiwStvpnmcLbe3mO1IjQKHY3zgcNr0clJEDk74
JQJ9Ax2WbUcw4RUfntdLjYiAcYQtbl5rZBqsBBXk7baf1R+Oqb0eOdhY2M9HRyX/P+YUA9NdBi/H
wPUfoPAqzzUQIsEWv6JdZ6F8b8vZ1wABp13j2BhjPWsxflJXWsCnqR/JLwawqts4vIkTifltnXUT
toWdUgj+UqZ0N0teT15qXzFwmepmyh+YmftksjuP8Y/m26U+WYWNdx1q0m+VtAJ3Tzu7UFth3UD0
DWaWlKqZVwBv4aB20fBDpB3/+IShBuhSQN53wdBebvTXY6CDYMM98X5dx1rJaxfF096f7w3Pgks5
DD6jVSgQy4w2+Ip5/0UQ1th5Prl0KfMJ18UqmKbAAEHQSu/OfhMH7WBbIPnrtBmCfoMVd4TLHvHv
YcpANxnp9tm63ZYP0nOWkacWCadOEaaf/L9oNGZTIbQdlJhSWlhs2p5E/zGQrgD0KHggeqricq54
caWTsT5U0eZYlui6aM9U5C7ZBMW7CVikvIXlgsin46PAxaxMjWfxnF/oCuQCnj5MqniI4yujiU+C
hgq67+9UzmKQIGGCEgKXlUzaVTqmsuEcXR+c/lXadd/PJzXtfKu1/nQj76YMDnFSuXjl0AfoK9ia
RubrqOCtu85AfowEsYrbSg+xJ2Ih2mdOqv6t0VJjZDACm0egx3+wMJ3XsYeO5Fxp6V/fEclt57Oc
sQ6LqqHWs1lqisVjveGBlXsZzFRMsNMPBJXY+VH5LzQRbXO3CtAjKXByf+IcbKFqFbUBCtEyM9iH
oIaE4lyjIltoEWSsebUEWMlDPmsH1j9ARALry1Z5lpIV5PwI2y6qNLlYwaHFmsgZz85Yx5rFPgTZ
A1QbTxx3FUTM+G3sm72JlFCqUcisw8934OgulsE7r817/YXHhE5cn9rO7SHponGIyS7wHWyhY417
rKN1Lx31xZ/ykDkJw9ja9dtTo3ipjCENRhYmgBfeDx7bPpBnRm0yaAQi3fUMVrPITYHLwkG+6DfD
o9cWZdJumh+ZTQYUzh819aBpYknHcznuT5u85JQaoHA6EkNJu3QJAX+7/3xGZBP+La3PkuIohnTn
TCwHxNDQDBFu2QKTe1Y7kSB2uCnWARGL0Ksn7mFTnxYUwSqOgyzEv/3ib4HBIu+u6tVGEbwBRA4u
0wDcVWUR5s+lXBPqK8HmkI6er1tC87et466nZb7IJFNASVrPFPlNcPzXFEQ66JYViudlKIEFT2hi
Zh5xRewfdnmTVDAUzFTvSnamRDUKUu7I6oVmE6e4uvtEeyYrB432/U/LZIoXd7tk2bSgBsX1fC3I
up0iRK6X2Jpbs9zerUWlaNKDbG/AUgopaeTmOsUXGju0Nlo5YT2BGpdXudEbc3asoeylTKWGxGOz
MfKKm5OhuNYPP4yoQ3XMhgHsqSFLNAw460EqAEOKRg6mTR90RZ7lZZLdWPC2WMt/UCOWo9pY0HUE
+hBFU/4NPjaL+A+GOBGUijP4lSB9wck9Tn5KaDgKPHyJfX2JQeMWf0SKcfLjxQ3cmyJMfENr3ga8
rvzoP+Y0DivGuaD6O9ofXXd1oCMr4xWQOGZgrNXTPkKQyQQlSf9ZnYI36aA3hT7jKwxddm33H6ho
OCae5UPCIfuJdS79Stq4IeBQGu7gVY9RX1X7NSnwvdBV2tGzfoI6/gB500b0ZuiyT7KzNA3GHGC2
QRXcGOSGOX1wYsMSRYgxjgQj9vgKWGYj4nRspiaW+rxuw2xtEz26XoziulNt6dZ3Nqtcc6pLqm/a
21p4YnoVsxitb3GxUvLdg6J9ym+QgJTL4IrXYb0R4MYJOrVU6Q0EU/TL4E5lAIGLpto7XLzKoeoY
E7R7SvkDKP+BoPiPZRLii86Lmju3cM5h64jHevpl0rYYOKeRbBTyrXsTFGYD7gK6kctlAYZZdGxi
FtaVzkiz8V1VNfnyjneL+2foIu20iTErx78AKg8zH8rnHNySnGhyvcfAmVBsHf21OEJF9IXm06eZ
6M9Oo+IJXIbC2J9uT00CVmtri2zIjjgYZRGNpQ/Cx89yUWCHjySoVy//GlicaTZvj8kBF9puTaQs
AspkVQz7rwTRUBPWReB2BubqIdsk0/A+U61kJWR4EzWVbu5pY8VDMSCpy7X52vSN/inqNm4K2ByI
nLo8A7bvTptJigM3pwljze6QuBDTZgv9AKhFxdzq30+dPfCrkU6CI4XZ9zQDZ+RrSlZIRiZBrMc7
wXHADe3zwcx4k0/YyIEZ/CJ40UWo6dFWzpzhkOfFK8tViPiFYE+o/HrraZAu0LTryFHam3zhJX1k
m8LRsfG3hn+Z5rTMxOF6A3EecIKfgM0bXHirsfO0MKgO7Ewyzn1AoTPgZMO8qgUfKoRyTJxs+fMQ
I5xZFkyHDN+WfCXdTYV8YWJeGCJAUWwoNUbuWjILGO0oxC0NzCtn2lSh9ShAwBT1H+eiwlvIr7kR
NctLQqRiiW2dHqzaStvfnMfktrVf9PGI+ramVtd9kDX0MIEWRZ6cgUPbebmWYS6nVD6iLLqqy2m/
Mb/SJDXyAhcYm3cJzgulEli7LjjDFPm5eyjt/aIc91X/KpnfKg4f/15D5AdGN9WyPXLsm6l/pHa+
8PV9ZDuexZSm+T9dTx6Ri/KsCzXAFXTCmKBPaVOnZTEEwY3kKuXb5HcvIJQgbsw/1Mg3XWePrHxO
L5DFZwRSBvB7Mj3+sFrJJsoYGuqrJ3SEjGzALekWswp06RP73i8qkByPpBpXgnKUOIlIAMyISPno
IlGpP6ji/e33GHND/RnUz+IvnbwGicLrLGe816VSltuMB1Q9Nj4FHTKKZBzrm2Lb34liaIjpk1XB
ZLjcBdQy/d2wa49MJf641tKMH7cM7LOqGpsdu9/j+qiAZgWc7Ya6qeugVwPq9AwU41btahD+kRa9
oxMNEnWK2N2UPZmFNJjV+bK5Gb5i9ZLDC7kr6iNHgGT/tuZIzII0LAL0JdOmfBbQoQqZ2VkzU0qY
VUocqoUcm2jgTSgkwziGz9gkOe9hgRp7NH6n4BrCWCvu79/NojMXY/iDXNwo2mnsBfXAAdBgoBUn
TPklr3WRNi66HWQUM3PTPqpLNY4L93y4XfNGfaO4U2i5EjmPgl7oTjwkimnBVNufcPGRuo3ZSMMm
PNbp0A3XcDJ5e5+0iY8+G/0lfT058OJJQI2QTlBDxRgZCY4Bnz1FPxtnEQYCX3h3hBEkDucAUYlb
NbPaA/JdPrVbuolko7/xyUU5lRKKAFZAQKbFgkd3RcxjpWRuzdekWB9ic9oQUCQDNP21RQ0V8yzs
EMaqvjBy4NP9DS40xoYAXTFz+G6vb6rCZ4eHgoKb2S8grjiCt3Q/3Xept+j3TMZuQxuoZZC5O9O3
U1hrTMGbl172+gD9n/+3oPQKmK9+fY/DKJRREyQy5kK47/D7OBJWo4NavS58iHza3fXbh/NgScV+
vgddhmVXgQBqrDvWXKfyNL+efRCl+rHRu75DXw8yknrkoK3GF2KPO2FkT7nE5bksY2g66kkBeSRh
Ib2g4kGOmHk74YOzPB9/Q1AajX+1uDAU5p9QLDnCGBPgmLfyZL9w2T1F1Zw8zxTMvvg15M/D/ybq
rt+ddGvDfVaHHc2fs0kV7AeAPZVpGK1p4xlgn/Z3jzt6yjmk6fw5zWk6SHwk6VbiRZrvmHgwaJaM
LX+1GRC21RkJcnejyXwUXsgtIWQTiyCUhu6nX6+KQIpnWFpmNMgRMKem1jFI1IKPq7Cw61H2A1mT
N500z5oxOjZSpDP1sWreXaOMKaR8IEliCKnT03LKPO84BuivFlKxrNQWjnllcmx5ueexdA4+KUP1
XOJxDGWVrubupvpgGHr9CDuSq/eeDFYhiTCy1gDfw8stq73idAP4eO5GILmGVFmuOYrQcpix5I4f
Lajd97FAzp7dyJczvWOj1GjZOpMq749LLDFqVpV8XVpVjGYNBuU8BadtiOrB3hDxk12G3PvtuKHr
tzJ4GJsMUNiWma1DGl9g3GkHkR8fmxfQWlV8oAPHAA7m10MdXr1MGrH5CdrEfIcVmW9EF+r3ZiUp
ehvSQz4aO8c/H55iA6lzY3WhxpLPpQ03G7WXrtpLtUi4ZqAG2lkdYdMs6Ht00mvIPlcpFkLOXbcc
0wos4LptfOtiRpgisPpZoZpLaT1HFZ7pNmKeLOPQX9V+zJUeSzWLqCOJw2TElRdKlFDIMsO+ngGa
iaqd86VItUQeg6m0sEm6E6lydIOB9cfdJI5ME0Mhg2gSOUGU0IS2kkMcBh6wiczig2603BJ+2ddV
Gv/ZwIq6GKss8A41AvJ9MrxTHSnR/UxLJ3ZjVJljNfSDQ4sz+Tu67dAXZjlv8zzhr8sOhB2PjJc+
WYmPyqC5TGLULBCl8iBhBfuPwe4dwFBffWXuPHFvX3o7lKPZGiUYbPMkGTH0n/PvODeZ5H9cih3X
LZuu9vevcKI8smbGuGxKohkUqRQ3xDBgwImwXNgktALDR0Ry0Zunf+EpJSBw4ki15Skrq+9NYTyi
Q+/d5l5ERxoTwBi56cWbgG+L9FX5MHCu3fcx+qOls7SlycpmEP2K26nioYdw+RUfUs3cWHX3GJ+/
SKVuIlkyHwBtASOgK0iDAll6KaTN71TO2QClRiP24Yc4HZwBivv3199V8eEQjBReFLHcsGppa9eX
bWB81C2DVej+EFUa+XOBC6n6lyz4ohnXAcaGsg0smhEAAT0ovFLm7UNzoDRP9hE0nebPYod7vwSV
AfeduTl541LRxibBeSj7oI93Kks2WX3Nl4duaTc/PPAZa28AAxlsXCzKBsxZ4gLILz1JZnZvmfYk
P0WoM7g2IMhJP+AcYWDe2eTYn02PmL4SKrMVSl1Xmh30SphGVrrlj5mI0EKk8QCEPoysiBe502JV
duuX8A4bkDHkyf/5Uw5SavdRh9XpdWoDdNUkxq6cVT2fxZ8LIMs9qJb6L2EdHpOwQaa4SbaTq9L4
J5s33ncfLMqZFFBZIr0+9HePXVbjD41gAW2QRzRnNPSO2BXxNBw/nnT1hx8RRaX41EHYujPEk5x/
hu8oCb1RVcX4wvTG4hPXn9L0OP2hyWs/lve4L+xRwhadRaOnFFSfUgJNoGN3MVCv/nF0pRvRKKpQ
i01nj8PvrfArC6AOGzmwP68vQ2fVzr9IFTx7GMhVpvpIkG9CCsqzPtaXkiqp98D0BnO2VtxGe6A6
++5qHu1PYWG0PkbXWLPgxXtSNS1mbB0jJZLfqYJoAPdnZ5Cf/rPDvtX58v5HrR3kADNknxFAK841
tQcNvf2cmZPlih2Umdp3WhpcNqjNHXiGXbxIfWw6KPxA3dWPImH0Af2UQwhKQacw9Eux010HvDJ5
BaJnN42M2nJ/pK4O0W1SZSxvI1on/oBM4P5LxKp0hpn4g1GJfh+gKRaHz0447ssQMRXyGw+xnUCJ
EfFjJlWMUwCSjELv2qC4l9ImtdZUekfCSZRXMxxPZGvzdkrJXaXNEBKnwA/q+FmZJJQyK6tH6/b4
7cA9QuwIrJZROTEep4AUTDCJfC6YOVl7J7hu1EYwPUGHDReL7rGYazKVLF8nFBz8VChBzpHKqohS
Zr2A7F2drm0LIeVH8lO5lmU9dE37DfHdmstfLDUBcpZU2MZ6IhhBGi5K3kl8B+RPscicymBDHvbJ
kzvu45G5SQiXcthBBAAMcEpW7U1CsBSLV6jurKuth9wfKAjFLmkgaBplcBz5dhjEFYAytqYBz0ea
zdmwlrVgwSOBH5Fo7+//7yY24BAbOOqeWKRcPtA7lkcgsqAcrrtYEPZRQyVBatQLsyZiqG5YX2t8
swGtBElXOLviYqT6NGRx/j9IalgG1Zs5u66NF0mv7yF8t/hX1qrVqIDaXOvjLGD5Rp8k5yTSTPF0
RjXwDdm9cQ6VpehGlH5SehWH6smARLJUGrtZ0mdWJ4ap00ZN9xsfkEW/5OnsAl2Hi90eKM+M979L
AIRnGsjVDQqYy8ucJl4xqiEg9R02dFQqgHfNJEj+qkm7QP7zngZZ4IRhGtyjkPgM/nRYQJTjPFIV
s2aDXbzptwQv7Ty3hMs+9gclANFxyro5RgCC0YZ6QQ9Yev7X1Hkis20V00smRERis+ideEvNt3es
AIQXs4kA7gzhsUxENNhhCUKji75hJZDYJGphtlp32/xzbO2R03QATEKUTSbg1xVKh8L4BJ+yke+v
5RC99ZCJ4oDMwlCaLBVKkeKnd78jbt02wvNWA7Gporb2pPrkLLZIvpQnhRfnB4e87y7BnBPeN8+B
aHrtE6MYSm9S/EJwMqwiISnR+jR8zY5B1HqkRjyE4AQFGywV7qQwss+pQQxLwTI8OTm0TigUVtFh
fL8lZHlmhBnPae+PGJTp/URjtz4jCGskq7amE+98Pl/Mc8gl2pVZ2q/je/mTcxunTYi3FUPRQnPg
nYNj5NCxlr/gztSnleeguSA40Xflfstyr23fEZCzpxLNLxyCDy+Qn83VUgOtzuFPJZfNEhm5IKWs
Sz1Yj9OEkjx5VazXg4nvT97F+d0Ktrdwmwyb6qOX3TacmgIZsMWMdAItaYypA6zyEsY+YitI+OE4
O5WojkFiHcrWc+LqHVjnX+7qEbo0F0LsdsgB94WPxUmR+Kvz4u8Rb6ciVllk8WMyDiuQz1iBkBF0
ZDm4vbki5ZQ8sj2StAbTb/C/zubhHAF8ajCQkJfTcxAF0ovPAuvbEN2ZfWRQsQIhqP2VW5kOYfvp
ZXkCaLg71shZRcLyAR2RnQ8ECfjYW4yW52hEhhS8JTlD1ymuppolZarIrU33j9g7sLRggrbePqPm
OEP+WiACQfUA1ScHyGTe51GMQ7ANO7FDQVfALHcbAPUuj92V0Cu15C7vFiDzcxQ33qKf2IzenGmZ
Acmpa1Ca11djcIW1YO6Fp14MRyn0DfTRKng5rk4cLuUKP3d/+pjZ0wuP6sX0SMFjCkPe+DVoSeD8
gPMzvUy0A/HEXiXLKZ4oQgDQrHIHbGc3SdR93q8yJsuk9GR4NmI9IgSCONwkHdoNrw0cpFkFzBGq
NAJfVWaq0Ijvf9WadnLbjB4mtcY0lc6hzkyWzH+Zi1WCtN+ZA8AsQNlK78kY2kTxPKnbWwrMT5e6
0DBxKhyA08KZVxBTRJo8Iocc5tdnATvDjurcg0IiIQ/Y5jbs5wq9P/hR53916IEL8Ep6H1ho4/6y
DIzOdhe7CGj68wfYfOj5ItUIB+VuRj5urX+yN9TYhkqj4twV832RdHOAchbbE5DTD2AblJjVUXj8
HHIJfDX/ysQLzwzb1gHuvEM7kMdiwTRvqEjdiE/tpJ5526+z6E11bLqOJeESXAC8Ov6Qw6sZkZHx
Ktbebqagw1q8yqfPJlfJgP2GNYKDq1SyGvDdOehLCWFXoZHWgEcKtxIZdY438VSUbiQ7MD8squrf
UmpGXTw+2MXDeEP9wtTZeD0PeRcvFAL+05WaMQIKwW8sA9cKNpU/RpL/N+JVh3k2hd34eSL9+aws
KFQJ0j7EUh/aur5rcoV17UeoKl1+C+2QsKqdz4ivdpG5ua3sxxBwRAuokvNI3sNNCFIFOv+/Jui1
znM09duURyKqjQKkLDXsC6FrYKo53se74KosnBgtbZn9t6OgJgYnym6D34r4IuyQCljZ/EAdZMUl
IoahN2S68gKoSkWhRPF8Hw8G7/obuRhhd9HJyTBF1brrlZn524YMtBna/ipfJL5SMMyMcoQnJWM1
JtmwIvEdQqjx9KkQOdGVsmdMtPUq5CfK1U8I7+euCIGq3rtNat3KWprbL5rxroMjI11Nb16bzlzP
meVx0ff7BE2CK/S7XTfdfjr8CKLiPI/NuceR1Ity7XjXH5qQyDM0gtZMpBCRHhPu001NGlnFpBbJ
AKyWyZUqi/HPAvsUbzFRdjcTiGJuqNutHIJBDQzp/nnoFpFRuaVjcFA9QnRmFlgLN7E1V3hsyhiD
GTI1B4JWqsS4LEYJrJ6H+g1I9IBuTFms9sHjvDadvfM6ehjlzbgxGTfyeno16wKxMJU/suYnz+0F
ya+n9oj05mccPt57BJpzNj+IBaQ1quQLWYif79oqmhXkb0Ge6di0WOaBHrvl/f8zwncicIP56Y1M
vombi16xcUeeTV14p45F2bpJQqPCMdjoNUQ8PXZ6T1ZxDYIT4u1Njp8PD7epCoUeZml+lgNxS0wf
MCEczxzCXR7w+5b9QPESFv7hBkbxLOjQrpdLyGX0hQeHZMQIoUHUq66Ho663lwjz25/86i8CkD3s
Eg9gFgRX3egoxaBf/gjevOQrLfeZDvWGzkh9eYWe6jXQezGBElEzYHiVQzJvi0+c37XH98/wYdZr
sElk7ak/PoPakiI+5Fgzuhy6QsXvh932/hI3oDjALXUTDqVmTyUmNGAUH6esh8L29gLiD8qE3/af
eLj/wSwERyOPn0VBArwHOLSc2X4nZ4NYHEaLFLMdk4l1r1X/cj1HN90CpYjOv+lYnLjdV2lJ158L
l4h9FolP9GvCGC5WL2CppPLWnQi4ZUT1X7WXVh1EHVe5Giq/eHLPT1cooSuW6HFlqGvl2/DIER3n
NLXqXf4oQVI6T5KGm3yLsjB2EPvQlBobheRxmCLJGnkutu1/wxYir9w/nCYgQIu7ffONiecte/Mp
+QoJiZMkkO6/s5Jg/y+cudp+nSpbfgIcfTRJnw4jozIfF974i67z3YQ3H2gQdMlnXvl+nM8lZApn
I0U+uBHRqs8Rwve18P3VnXgO3yKXrPWiWoF12KJbyknP9tU1avgmsyTtgq7MRWOd0D8b5Szg9Xpb
mrsowIAZNLxxgULmx2ovtVklc9AcCUwYJHHmHUwpylo/Zu+FdmDc3KPYF1lmwDdnk2DWJ/9ou7A4
PlX1GdrXXPl2ykDxRTCVmLcMME1xdgwRLvf2ao2xSxHLApmU9biT3ipkMGBva2kCTsKUJHE2F2xc
Bt6N1ikzYaOXZOHrT6GK4I3mC9Xv8NqjherN9RP+LVUrL1qJ+/qVkuQ8Q5MNs4AWChFIxZ/y+lMf
GB96APnrUJJu56JQ6DQaj7Pr5BHJUMEbjHzlFcDS91pCIcqXfsQyj/KY2+rgKnwRgirT/37w858T
ZVAeO9r0ochXNsnFtO+9/Kp/gSlTj/q4YWK06emDBk7b+htkyGeFKmMm2HxaQR30WMpL+V/MwY+4
RSJeb8iU6M6ZNqxN8q8agL95SiRHAYz885kgSWC/bonbX7WsWDSWL/k4BaiTAgrSbt8Z254qTnah
4qm8WbXF1jJYaFxqBrmKObsJp+W6XiJhrU08Wr05BULpG7P1Dxe69jzqjPDaviL91dp1h/CUqKF5
o6NAIL71Nb/TMUXX4Cp4riV3kolb9+30+GK5aoZGxD5Ahdq2h1jZjaPHP3NUeq5DB71V7/qfxTjS
nrtRzbY3IHjOJ4OGHYgyrNo1luScVD7M8biUvxrTY3VRGJJv8gM0QXI//tKeXPhZFJZmGnaKqCJs
s8LWeo2SmNG9HyJssgdU1odCvqWr26VmNVm9QaIEhY76OkNmuwW2zvJHXTwbV12m5vNeOm+N7r/L
L7k/WQiKUAbYqzOi1HgAFUFZnvZPVH0iJ84WjEERKr+8x+jS5vdZDbqiG8tyD1VL8hLhDqBL7EfY
K/hjbt3tI/wWIhZvfxpqz7JisqTT6hytSlg7jkLf6sn7xh/oB2PIDKP7m4ZwLC1MxANuVS1bNPw+
+cGtZAVkphHp9gxvHa+YZ/AZ1L7vNafm0NY+cZVXuDayK/whbQTz6igS1BxLiGQYT3SdPRYvFw/D
Asmk+rbkHIq+gMNvKkR1ql7o27YCjSzc8aKnFDOPV4Bj6OjvEJz65IFC6wd9RKAbs2DnI8x9LaHt
pUCbxauZzuOrjqll2eT3qO7lTUrf+VHM9oCkDvy5GtZyu0YN5kiuCyntgKXc3OZKyuRc83ZcwPd+
zw9P7pu1rjcnD04ZYu1xhMTPeIkMcFc/qDUD91zUrlRM9f6sdpai5KkHZi4mqppfGzXjwxqpaIYX
EjTNgTjCQ2zGxzqzLUZ/aaKjGrjPZjeXbvc0y9kz6LOPpSKj65naMWBKoMtsXx2P+bzyBiSzNXY0
sYihHFybIbODCtIvetkXQPK1YFUK0b3ZwYI10uOFS0QpfV6m0ZoVyJ/Zap0DDZB+5QSFf6QaBgY/
5sXDLdg/92LzU/kSRPc8BUck8n2iwzyfnwi/LDSBEZCfjYbUC1SX6x7+aUUNQ8FgkynokcZpBCE4
6UesN2sSy1PapwwOx6IDn2vHvwQ4hwnAqDA8UPTgb8cSAFAR1A5A+5IEgoj2dj35FMj3H+1IrS2R
MdJOGGEFLGtGy96oXZdYW3k0pi4tf+C8OdBWK8fqAuo3aq74oP7sdLGgdkY11D9c/6pjJUWUPfbL
AcxWNsKlL3TTaGs49WMra92R+GGDQ5vgg0m6zy0WvJXNZUtsuThErM2XcuFsNz2eu0z1n7+QThoL
tlic7zwE2c86tVQp8XVmigc6eFvoLszHjwm47TXADPtiJCOpFptSppGybGCxC3fUnbdQkR5AOnMo
84KFmVkeRWgS6izvi9S28zSEyJzfQj/4glDgGpDfNjjlUXhYAU6cjUolCAXRifyHEAxvMYrTHT6g
2qzW0Wl4swZXXdZIMiUKKlwvma8f6Pta5sBO9gQKKlBRNc9BpQmZ0LGgYki6ebLvINC7D3ElnvqI
s/xTLxYV+OAYlVKJF7imG4WPDCeKOb89GG5zNW5lFpljPPIpbaRsTJKiQUKPtmQM/g+sMVeEMrYt
87sI9DFDFtCmzFKR+Un7MVl8e2HS2YQrRGEKJd7WxtICf5dk98r4wlCxQinaFdvb8mXvDiKLCHCO
7QIVM7Krd/XQ4f34WmpWfL4mzc53EtFMRkXF4TP2kze2orVo2kJ5QmrzieikYikAbmAQrnK6iR/R
/tvF2Me0y8BUqmTJw2po9XvtZyv+f+2GwW42MeMSyJaI1NBws6Y0o0ex/1U9/sHdfO8NOF5bYU85
ifIrH1ZlWL4KmCbx/gzMfTNPiFR0OJkfzZJgIfdQ+YW56fHCS3Qj+g337pKemZDhef4grfdaJKN3
vO2pK1C/ZEZrFninD7oDzNg/ESU78UVXNEnHsex5o7FanZj3CtThmGDOvPef5NVJy7/jrW5zl1Jk
RadzH3rv0V2gha6yozdGCLpG/pM7TBSDdcC4GmDlIFRhj2JseH3xwwh85BRl8jLllYV6x/FJf26v
6NSnJxPRqzumqKJUXETh1cMZI2xbZ13uuOvkV8Sq3zqsWu0+GvZbUAK5VLepJGJY4vYilpEMewZC
L7GSGp4XICRHzUo5OJKIXXQ7SndSR61KOXBJ6i84I2t/dAxWDmx+tNotYaTs9Y6uxs64+rtm/123
hqxp8P7Mi+Xne6XY5OHBekXDS8WvKr8+jhQ7AHWkJWKIqqXJicyCjgYfwS/oqqTUYm1QJlHjCims
K4YzW+/dqPgtnQ+M8hfY1Da5KnC1ha7+z5Po5dEdcYfxOButC2eV2Lhpj6W67MCqExXwRGxo0wc6
KXoC89IHqqfBHDEsm5G+MQjb2wShsbXX6iQEkegVKL46QnN0jEVBfaV9NRabZRhx1wEt7bJAVadF
F/TAqKGHGt1qejmLxb9MJURFWYOe+q0AIB942lASUYGGxFVOuca+U5amE4lWBZqdKPbE7ZuHCaVS
Y2cEtmAtts0Q0REb2j5BXlkEH8oAtJBhDkpsyDK7SrgW3JfbHFfSUJE6bxRnR9vRW53xMyF3UErF
rlWNGiR9r4s0vOkmOn76nVGsyzW93EAO3GnFEG8GlbVRVOQCPG8G9TxWrl7MXtayRYoCDTM+N/+L
0I+KihkeCZit4eeMjP4h31CzPpcBtA0x+norRgZnTQmU5h0qZtZNhS//03eoMlEhGdODnXw7LIDT
G93c0AW0ZwD7QM4citCUkPq7bqbq4awNeE+xqVgC6IBjlySab7GlpnFyp56MecEbTlA5sviK4Ggc
rhm9BedcP71aomvtAVJt7oyNZ4RIX0I0MEQxbYoL0G40vI2yYidxYpmMSQt0/sWyMGTe2xVYcOYd
NgKRJQDIa3SIHpRIGFjyFMHyYYyyRC4jWOFsGKmOg601PF4ZCqgwcmv86LzrwetMTcUFkbAGyjTN
oiCOMELoHIY3mMZYsA55fnI+C//lHobm/ARy/KXNAUVlpE617KdXoxgyMs4eYcqVCtXF4zyUZZvS
92EGtFio8av3hglCDL8vw8AKZoNsXnXjT3za8EPf7/N8ne9hWyFE82DfvP4cIyVS5YvybJ4aAly5
XNCZyIZ1aj0qO+fzDoaMo7V/89xQ6ge02ZmrcfpZA1G9w29Oq3dxwLpglXaw2FQm7cXQh+Qsekd5
8VPzuZHluqljGZf2XQcGwJm0E+BBFuky/7BYFHbQBCKnSYuiDNgmDKjqnaV12FU03vFLz0gaKfDN
oVOP0lgPwDPvVgH4wakwWDQ0uuJz4nxxpw3IjPqIDeFGxb1KZU2/a7lL3uacw8TZhirnmFRxHml+
ojG0mgSz8PHM9idYjayI9ozAvp1UOm/9mcXaODrr7h/YqAHisNE/FunlqUuHBXXUPCUmwK4yDoIv
licuGBttXpn+Sjte1C3LbTBNk9OyED5/WZ19yR30pVDk3jQb3vqCkAP4uVFWmRenXJpKP2AS/SBQ
Oa6rfR49et3aeoyYYS8d/riWAMKsWxXE3PPvwR5ZC53AWUkIkmXuEXdxY1ceiOym4frnaPU9cmg/
WXIMvaOecILNvjEJUiGS57zTSumEf2P7ywjL51qWxHiKLfbDvQwNTROOdLq78WtF80voPi159UyJ
s5RiHbo60RfRa2JNOsRj2D6LF3Xls7TQwzsv3c1WnsX18NFZyDe972M/YdIJp7WjUlyvq9qWg/el
tDKyE8Zjxp/fS880CHjvJdC9bzUrnn3kYtiEHBJy1Dhh0EC7oBhcZlkv0Dq1cOlOtxvKfLCcXhYE
uBFFSImkUMoTORjbBWSSN+SgmWLAhk9dcNzVUx5d6O5NKcBorst+zuBIwWKPC+EADREfeDDtlww2
tUc6D/b4VwAw5PUipGbmVEYFuRc1M4ZBlxeJibfJ5LSGbg4w6Ipmhvr2uoKMvKFzTJEbg6rCBg6f
WJJKV6Yi3Mqtvxxo4P7BAWuQU4PVxaVdWixyYd5W9RSCgpg+rqQlrkiSOLc9X/h/fDPSXQRYV270
eNMzexB9OCCWdDxN083iXWEuQDN94WatO1PpOeHT8bE281swBMrjP3WnE0wAtmOFskpMtqmV5L5L
HKZvus6KCk93SnpigooyV9ZOcAVlIKgOoil0SEsHt9xyfgE+QKu8BPXTbkc2FGlqMkmLEEI05Ude
aWaOUU+Bol/ipxDFatF+vOzZERQlCH2f/WvPQwTGx12a7S/YAYlgK0QjR8KUwrpBFXd8YcEM/PsO
S+JUoBcMTFEj9uiL9CbA64/VtmX6TH8yPfZeyYfwe6Fvyc+q3FgeWsZFEA1PmaGjX7ltvEiQVQfx
h7iX4twguyhhnbelNhtC5+DhvTxDqYi1h6b/FX8Sw4z+1K81zidae0jQACe9q9YkB7QT2FGMvy1B
PfjF+7Qip8D7iFfA6bEZv1KniHRaZJjUopm5TGeh+uw+2n9vUXxWNjK6PThFLBw6iuAkM6/chouk
3ntuUMA7clGpNtxq+pnJuyBOTZcKaOUc6PHmiTxSGkn2KDew3l1B6Dz+zhJGz+EKjDH750lNS9c5
NnJoIx/5qJMud5fKe3tOo/tlPAsT8CG/SarpwQoazvvo+0m2l6eokap3TR5s3pRt+wY/5OP1onqC
84OpFU+9RGGeLnHh9C+sNQJKYS4AMFKsoPQQXfeUBRyW8hRX2pk+xZYtgTPY51XXOB5bAZ6qRS4k
bIIB8+S1XlsOcMBd7nUklYZgenyrOmtSKjY6D/qGOc8L84ptAVp1tz/ot+2gYYSLYTOvzrm7UdiM
Wu7GmFjEukWx9RYlB4SooyrcH6ou9Y9+X/X+6rL1QoxnuZ73FW5DU9q44/kHAa1WWjJOHSquxsIk
jGc3/h1mDTjlXBXBG8+ECRXwUwGAzVVNoMk3x9vq4ypNvEngWDZCIT9J99iAu5VH/Dqndodin9gm
M86CRjodYdqNNyPITQhIbstn2c6n7gk8TZHAJvuVcqn96MqKhpc0fB1do0fHD9cq/S0ydW8/9ghV
Np4IPrtJsCR5JRLAABj1JyoVdBTSvNPooE+TrWaAhheII/kk4nVp63t8629oP/khNE4omRmFIPle
/p0mfHx6aMVsDiyhTgxzeuNxo6p3YSF32EJxnl28XlUv0WAa/6IXOBIGPWE1aaP7sbUgj5a7TUHG
0Tz5WauqnYGckwms9bmrxaMYB6gDyCp2eYnkhmVG3/cMnvPVHMKzM+0OY10pLmoKAh54I+hk/2W5
wSPW5hfqxMlXybtxvfuevRaOMzlBGReSzDrRm+4b2o36KwRO4uEJ23P5ozMPuPgMAr42tLwTQ7l/
4Jf+CCECKxAElzuBtLgpmoL4LCqyQ1OBK8ddxrL2fj8isB1WUO109x5dutski0DNcEesD5dcRPlY
STGMhnf+F46s7f0DK0h81toz47Lq6xbIR8e38DFut7LdC42bKEl8dw6DFrIVciW2XuI0tK/uIh4C
+9n5G/9MAA9KT9Bdp1+aG2gkY2XpLdDTHpAxFrlqCTUst1puJ8raJ4AAihj9NTslZgbAzZKtjIZT
TasXYyQZADoryWDTZBtsg3fJU6/OTEqevKLt5/wRXZpYFhnEjHV65bPCVsTzgE2N4mLBfPX6qa6R
q2nh/Lrrq4zsRBWr6PiG40tv6UVRdlgULtCrobj4fPqm872DIzgERb5od6tcFYmbC1R+ij12CVJE
moOZ+1CU7GImsZCYGlfI6mUKdc2NhXtGvtmvmkO5ryvMpZFukeV5IQHUlxoCWfXMRPKGQO/tPKhA
7/+Khm8TJMz6cmBTxT6k3niQrxKmCi/XU5Row+jc2/MiZKPnfQURTBkAVECp+xXLcGr797fa+mlE
ZU8MoDp8Cai8fJSwQKj7dGQFcBkVI03MwHZFrncC0+TD38YM1EVfpEXEoh9XZineIDNfv92V16Z0
xB8hNQiQeIYIzuESnRisCstl74Y4rvDKn178Cc53WABARrKahPuQAzbk9UX0TYgf0vjjb+xBFuFV
PEzZYIJoizxPwKcyxIOgZDakYk0OpjGTHRy7Xqm1ENJEdlTzyCaF/MEiR3zpS/cNcIfg85rik9UT
6ob1CN9NPizEgWYig6nZKn+6rZUP+aDysLa/rWvRXomrT25d16vUW0/XPQPf+KVSw7QyhX8U7t+7
IEBm3l/O8tusyKFRDlXA4Fpp839wACmj6lTl6vMBI2/yBWZ1U04vUh40Wvel6OGta4bgvkbObi9n
1LHnPZ6j9FVRfqInqvoWRcoSl1YN+iSE0ANEiq0Ia1JR3hs1dmDHOWfHtl64rwV8v+sHvoIjvV19
Vgn6yBtAjXRrQQWAau+dl7YngMeXw/2ApwHk7i7vvZzVKVZ8BtWoxmXJq8G0b/Sjiq1eFw4vzEJz
9KRmvFB6nI87RDoBzg2EEljmkUzr9Z4l07tW5Y0x2Mc+T709cUzMf4b62mAx0O3ENFVfIu7S0nVa
8GCyKM7Gw9lPHj8qn2X5XV7O8UD2+Epbj89ygjbj1wUPvX1fbjCqYVPOA2U9rqAFKh6Rhb9KYFi0
XfIZ4PQITUZ1Bj5fYnLFNraeur/U3H66LI893lNj6PInoXGLc6Zg+e4B/Wlfbcip7j+P9swnwJCN
8iQoFEmxTbBT4nLHEZLBsXtxcRJJzgmOCr3nx2FoVRJYZ3q4ig3z3r37plKDpH0OtoiooTCj51pY
70x4DcSmO0xUa3Z6ivqssZg19e2Yo0wcy14X4Nd5eohSC2A5DECEB4bTVAB/nYLNRzyxdJOyajrA
m8ug5BVEbWi1w6vd+KyJFj620t7oTTYrWLnjwG579FAwxGUhxsb7GOFFoDmT4dNEWIVNdZZg26Oh
DFD5D+/GJqWs+vEip0yZNFMMzvDf/PHz3nKSwdZ8w5j9Mirt9kugI4Wm2CnwRywh4MLQQfdAKh7x
KAHjoqByFhgKg/q6i053DK9uyvdZYg6aKkdii3zDrHSsDJcdr6JFON/JA3eHDITJzvoDPvYTkOlB
cPPZ6TvN/XTip+Dt58lqxk16Zc0VfUnmue2UtKGD8Cx2Sxv8yKxDRLelkucQ5EkjdP71EhCSsXt1
KP4KYXM442Q20gVGGYB1szpkyY50OnCxlgQbxM0Ifb6DDwbY26B92OkugRYePPTOwifZPTMG9muf
71Xa50GvXLfM+58jvQDrpcNUXEHkXNMipDJwbwWCwMi+AkDgPLSyIw/rbRKjg0MEnLXtTnOT3m8r
1OzVtxs42i7Ihjrvf8RustfpGWGjbIgn4ARRuANK2EkC95GTYW9x/88RGp+QZkR0D6iKlhojTy0c
3ZuU2pGlRZ3gByDcfUjxJM7eqv/4xwiuZ4n3DanOFeP2xpmCdk4U9kHHgW85Fm7RJrYtI462sPOB
53qATz6dLYFEsHeFB2FA1w2CZx55TvxPDjU3VgaOByTX3RqiPBISU7HGfdFOSIuyM6Iux0FRzCo4
zWaUZZqTs/h1KUv+qmbKKL6hvHfnxBy7HmHMoKxsIj/z5zOVJqdUeQEJAjXhaj2c88kgzavfTUb3
1Oqs0QyHXfgiHoE/uOLzVNII7xl4tsgZsfqzh4yGwqRigzSeJGKkp2Qr9s9Gz2GSICThaYR8d6sc
d3rFDSZexEu0UYoD01Jy41FDAiOP6A/xM+4BhwZsIDMYeoBGq+WlD+m6kZMIZTETLc9IsKQhdRO+
mMJW/APQM6NZiAJe9xMiasY4RUu5DA9OusOmBPXkETlLOwGv6gZ3TK5115pHew2F+nAdgMnPHd2e
veG2k6f7vU9Udb2pgSmZCC+HAOflIOGHEmUluQlCVSfeP0y6KwYXE6uqfD4eszKITX/ys8ZcnxDS
oB5BkT6BEqhfPEmw2QJ+55JCyUuhLT87PIJR7qpC0Ob1IvVzx1LVRUyrMcsjm4hIBbLTPm1Vt+LV
Hp7LjKk0a3YzacuvAweOUSxtUjR2mfL32urTdQM0CbhtWgOKydIkoHV1TNFrcWBaQzxDTOP4a6xr
SApzqi3+X09vC9kuG7z9WXoS9a/IMP5i9/h7rNpPoAuZ93MmkvWhaP3lX7/TFF+Il11agl9rj2vJ
uzwg1YxKCCVxiTZhu3qb35cE7XnZYB9eBv22hRC2fn+KeWZRo3e1o76PKAiPuAm9ubk1YD7v2nxX
8IeRzxC2KaVEsCrES1WgFJs40f/aT/gOqnvmEcb6pDRmau1G2Opje58SQMSowSJ6Awnt48Eg23lC
V8V/xonjcYiX1SbUazwRU4pxyERGw2GNanrXvJVZ2KtUY3TvZe8sISnwW9jS5B7IqsGPuP/1fI2C
Cqs6x8wUbFrbReLGmMIq8K86dGsZOKqHxaKoNN3fNc2+e6GO90sBasuZl5t3jUDDZP4bUd6pwPJH
ph/d+b8Lutlm6AaN7NlGLxFeghU50f7/JCVzqwmbfjAsT26TpGPYJl8WJDtdsBIxY5F3taOXxvCY
RtTcZCB773IrneWLJjtgXH7LSmf/JTh/Cq2bdpe98dw4iwlJFsHZnOxvBZW9pxkPs+JFQ33Nf9oE
N/I5kiEYsKi5Wsnuu/Kv0vrwf5rIIV01xQ9FnqeddWh4oShZMJHkpucZUJGxvLX9ksbYpWMiyS3y
kHZebWQ/N+vqo8K5pphFW0ZJfhQZtft6v0OYAqIuW7X1s9qZMBEWtl1/y6PfwV5oLsXfHCcAmjxA
bbKxGII5OXw+jgUz8JdS7HMJyyUUfmFPA+yzG7Zu4APzICA7ClOsKz2GMfncQZBr+2vmggm5dYVA
lXWHi0EMyT3N1Ot5JIairUzA3sYEBQqNzIAZFX0YEd/g0GMF5Qlg7YzDD4yLiTQQ6JZl7Xn35dLG
Xtm6OkW2ELuhXo1Yt/yR5Xy+ErHwFwHRh6jbuej8EVQX9Co+TbpJ3Q7eN0Z86yDGlW3nuWoYPD20
+btl2aDRKSNUz3jNM0xH/YPRnKmz5Mu/YSmbCPNCKRBHD/r+sO/s+ZtkAUZTmkVVwVAAMZ/q+Th5
4N+xTQxV7aQkbbReh4D/UKY+j/fh2FqFwPy2Woao1wF4ihGHa+W1kR9OLAu7lES6jnH2aF6e6w/B
JJceukjzVtB3GRbGkmVAAGLnOTLGqKLgeXylJuj3E4unUdxTanS4z4j0WBUiGjULT7D4kx9fRuD8
p8675Y/DOIgNo0herb65FdTrNTzA0S87bhtoyU/tc8YY3/nMd09/ANCgnt1U2+r8gLb5M5g2CJPp
SX8tlqDBvDZVQ6lYjqom2FdnjYBDGXpe7GYnq4JyhOBifdh+hM5UBWuVNcME26NMaqH8Q+wjr/U9
1qY5TIxQTrM9Hq+gf0SqMhJL26iOItzDaNfgGCNYL+OWTiF+sMWsUEMrUJp9K3p1VU8gpKtaHQjW
dRWIisWpkpuXFE89Fmr/XSaBJSJI1L7m2wqrqFvUm0Y4/vAuyk9ah2wQsEN3yN6VbSV5WfWPaOts
rh/ta+QrxBQ+uStvde2sioN9UtRrlgaZ+JqjKvtcwasPqX/LhynEmRGEnORDLgVl/z2hDZDYAtce
3zRyypXLJYGw/NY8W/KsLdUngTmztrNVVXBe6ktJ4y1C7hbl4D2feRyoJfVLkjWO2XhnCmlV6Ryd
digZ+1RRPkKshrQ4G14PsFbXOP+sqhG7ablwxaHvtkOfOxAQQP4t3AkbzVfOXVJIaOeX+5NQnh9i
WInPR7ycVk78CYubfMyl5/oMC6fZJLspk2s/24DQYkQwQ2WlJqxom98ppEBlRmvU4vAAgpOsfy6Y
dgWF3jIP2CVVEZ+Uwnfgx91VBtEXFKV08nrRvhCNrxU0qmLMLn+aJq5Huef2TBVgVtNyRcJD2yTW
1Y8jNZ6GLsOQOX7L5JZlOy+oC57RUBPPg62f85gk7+DK9Po29w6Ybl6Ma+lUvs7B1RDuYCJB8obM
0JHWHRnIVqER3snWZDjHWEeB7+/TS5kuGf2k6Ygavb4ozZ4p1GSBaz4bkw3W4/BeILHT2dfFewjC
J4jyjxzHjVx+3yN3ze8Uhoc26tV+9eDjRyK4nNus39KqEkMsGYqAdMdjqGP1QClXkZR1rS/KX4rP
jgyfCoXiCwJVNAQzosKyruHp9cw/+3L09GEKDdZ85ADT78te9IcTgL4SJnPm8C2kmlkR5Mik3FCC
DNnReoXEM4na/TU1lxUEs4O7LSKkdzyWMFe78Yw9UTHdAMot37eAS1k6un1cIj4nFzoCK4nnaQP0
OIBD06Srbk2pjybRPyqzyxYQdx70k6PajqX2Va3BUX5RCwqwPN4GAkZGS8Iupi/FtE4dkzlACf/e
gl9kJCldiCLZ21M6r60AKTW3wqtOtrlnuJHxM6wnu71QmO6lE8M4IcRNQAHFM5+SL4NgzTodCB1s
3wCB1N9nmDpVY7zoK5wcbXEDU4TJOQGmQXQLySyF4g4wKb7l3ko3y0AATAQezcMHkO3dM/IDq1q0
3o14+m85FMkRUHyxmDlVjQU2Juc4rQgnD3e266RuLRNvTzmidvbkuM0Z/aMhezJUxQ2GV2uRkDQM
fuvqE48qotrtmjje2SVofl/GjPACnspee+1+foH+f4F6ozintST7XrrM9bE+Ox4HIxo6LbmDQ+kj
9ciUYbG1aFkoUzfU6toOShjPm4SPlg8lE5epOsUSDJJUkcj+Ut7L3cWhGdswpULO/aKk6N8q/QEE
RYZtwOYE+bdDl/iYn3YXM02E/253aHm2eOlqkSCcTsKVYVZ0jHxbTcDkrXUuBOxa1NsJ0T7AGRlY
FEhfeUrHt2qLSNe2CwNmz7SVTTWfLWh4TsTxB6/gbgGW+1A8yujM+MHVoVGfmz6LZE9fteDd8ww6
1jBcDFvPsjDwdicNOkxxPdO9R8Tgnj+yaCfRRHxWn6zpMAk5hXBuwgsqUlKyPji4X3WoIRt5P+Df
M7iK/O7lpkXQDABKVgRluRMCeEWg9VBFYOkE3fJzSpIjHIbbIbmvk3ee7HRkjPKDGNygyiXLCrn4
5hJsWd+sSkcsuAkLUDxmWcPgbV8mfKQbEkbDa49McXudtnyMu69UXSxV5TRHYdFzh5kfxDPTFjb/
JjnzTOQdvCJEajCLs4UQweY5yRQ8LJ0hJVC5AQOffT6YW8xlpNDtrizz9HtkoSK69uCe0nSaLT54
/edjwtk40hZ4+Y9XqsL0WYeMRzEk/eIuxk8YSOzUzZc+OQKeEqtvkSHnwNUDgAcaaA/TTRu1VFDx
Ir4W3GRJHb4o9wPlnd4XpEo4c6G0vtPs1S/vaENddzf/arfFtEEr5jdoYel+HQxSBJ4zNF7G10JE
I0ZVS+QxlHcbZyOfYZhgzSZv7VA0QF7tbcr6kARpfwzgdgrZtm0jSQ2vagQD8UxJ4JpDoaFCh+WK
lZLceY/JEUT6DFs9tEnuTCuAXmXA96JAsIs69R4v9hNfjWba24nerW80ZOBebFIvIzbwY2zn+1TC
yKLiN3+ImtlBI9PKtjCIpOcEhYOfk64OWtihwfOnvFn+MvA/92u+q7Zs5t5QqkzHGeQCzYC3cTr9
3pp6Hdu9B54aX7dZqoydA6cXKITf1VToQu+nvykU80j0G5Z0dtBHxI90U7gz1tZAGxe+3EwfpY4q
C4yDYbGuH768b16/o1fGy262ekYOwZJ0Dgppbxdy/3UgwP8o8uK1enl1aAPUwb4HiFxP1ryLY3pc
N4LwAMQ7DnonBXjkQUkzFGzmNzLHIbW39DaUKlblSkxKnxjPKaC/c8q67bVuBF/lGa2sy7orw/s0
f2ypDV0MNB4yGkNIzxDQq478YngzoYZfXX6zYyeNiDEUx3K5E0tTsnRBbVtCb3lNS5os/A/j5jJc
dQ9GhqMBI6MVINhtCclFFCRmhfJ3Bg/j2ttEwflFdaCL9R8brQt0QpbhcFxA1X6IMy1G8+zetHoS
1WDERMOXn8FRoGVz6lz+FOT8W4M4obv54AJ2cn2/ekfWfzaT2JJrpqp9cIUuzVphZ7WVXwedTscN
uGpEZc/xYoSuq8Cdifv/zPNwXlcBUj+bPjJT0tgxfCQOHng3gWOmQQaNZch0gG4Q+YVLh6wA2OyC
RueKtgpVbOiRcG187fzc6w0Bm5636E2N/+gpo2gMsXVBvu2IU91W1TDPsSw/fgQo3X3uGlVYRYsM
Ghi++PQp0PlG0ex8zsK4D6/j0nfPP5LznLgvxaWyrtXKTFkh5OefDnnOddQI2GTVgMuoSA3qHbZW
GkIyK2G5F7EmEjQQ4c3/CnO/b95b56GJQDrf51ZXDfKikym+7tiDyzjYGJDiEPl4tEZCjTZZkSap
yU/uPJ1sm+60G0cOPg26dKygmQvmq6/pvk1zyPBJoyYHYY026Y5tS3tV1X4K5KatSn+YLoGw1ZXN
Jdf8w7S6erkHN+4z5TJsCNfF09/Gmj0nU02g3FtlWWvW5Z7SHf2uF80OQgjhnNBomr0ZCK2E0pIx
HGSQCQ3b48YBcKY4tqE8tRJswE+BN8jfuGVJRvX6XrKv9H79uFapu1P2fw3LjUemhYeSMquXm99C
ROZvy6CovmXNLofzv1JfKiXf9ycDKRqhLVLmcJnQWnCf5u6YOhSK0iMRSlXNjiL348RKBbtrsDI1
wI2hA8bbe/cBM0C1q+zp9eWRGEh1EVPKhrwhLxNqCvVf9uDlF5TH4dcGKz1m5npt+bRi2OdrjVZ7
A8Sf/tDfxd+GFI6HPNWvn6lemXIoXf8Lq/2Jfy94LT0VPA+Zin5Sdtzrc5CB0RfLat7Jne7kupkX
unGkb/G+YjvMMJuFUdUn01GL290r41ytX7bgCZAMKbkub3wZux7K8FSBXZ3oTiBzDpkPVHtelwk5
sg1j3hAjEq/26z2FiKBYDeZkgCvL7q3vDomfDukEodwe9Ab+CdLKWDkOlEihBi2DWvSS61EgfWaD
vqVpYubR4LZJPTb6CPQ2t/nbd8w4TD4rCBdEAHk1k/+0X6++ay8e97KuQUL23y+FXQwUMTkgIYa7
UZh4YlhJu3k5z6oF4GQ4b4NSYIpyH65wGtXPn9KgOTs0PyOWJ0fkpA0P8zbTYNLtn1qVO1v7vrly
mIhHT1NuQnnBPtfmyxZG7QLSNgO2l1CjwPgBBQmyxazJtasf+s6cMBo7KOjIBXahuK5klksTW24k
zsbU4IbLH7LO/L0M0rAj8FYkVTDko1GPitUrQsadPGLzdiEPOkkJVeyx2skHxFqj5WUiBorEhaS6
JoBXqGGIRAk4UuZgj/BR0enf7VeM5kxQ8rBLTBCQ9y5KkPx4Cbb9J/FlvMzXa7GuWsWWpRJCfWtY
skH9exZkotyJvTGIcWMtxew2JWgVZ4eZiiyMrzr7ovmr+VzKo2DOY4zPxFukb+0JDcGRC4GKdSom
O6a9ZwtT9Jmk7kI+AwfOdpiIKmOTiIBOT5cdpj4laFE4eGAMGUHVVeeDMD21nRB0R4aiDZ7DKWWw
wK5soerGz1HFrvpbcXQKNqE1xvCQkQmyy8pThG2PNZP0zvnq/mF8I7/Ca6tm4++a4FPdapIMqL3j
51sRSz1BD8kQgIoVRitzoSVJgK05nJZxk+jk/YbpdFCTHpiD8vvi24PBzcsKLorvqHHQw7xxRJMR
yRg7CJtZmOUNINZuNLbn4MQ6qa3NfuS9o5ZkEwj+NBmlM7Oe+SXhjmaGANsZ0JDIucqsF7fObC8N
7qLF8EENB7Z0klW2VDFWCPC1za4XtKjraj8LlnK8b0kitAknBp3isojlyFv6JL5WNlQDzCVg4iHl
3SoanUgqPil/FJ3+RkihWn+p8Lc3qOCZfmQM5AmdovHa7xPd6UIy4BXXrcFlcVag7zFqL8ATpEvg
P/Iys9b5hUJ2n1OJXOuODnzoSPgfpFQ57KdWJb52cTFDPsc6ezHeRAZZzbSqqwFyveTiAEohv7vH
tJXHBUiZ4cYjVngtzk+ZX5vmsSHONVoqK7JdfUQVqEPv+/n5byBxgGYEBOJ70VbluktiOrWEe9lB
vzW7PFPzBTlrf63Jxgr3bQNXceOIxTz2vC4uvUg7Aby4cpKHbRbF0W43Twhia6F2gQPjhG5SNtPn
WszvVZW4yPry/sMpK3S9mXKwFVieDW+CzvseN5rqQSyi6HIIfo5WhTrj7x1WW0DxSEBCJtMSSZer
dSTkFP+6W90VvqtIfcBDtxp0RmUhKbgIkAuV9rdUUG9mDPAld+kqOtxTKf8vgaRKbygiJag8T8Kl
KK4YQDeNGbdZRZM35usiBYvzw79w31wKCWC1Zu+onOMiAU7W2mbydWMfXAnmTcbkJNuFBtLnuuma
olTO/moZJk/t/fLY1QNcjzNvSSudUVcDd2MHY4kn03OOElitx8aA/aCjveAZyifhcdQENY8BAdLT
IpjtBcQmL+bq9Ztl2EpMERSklzMBSyZUwndO5Eff+JXFoBT17Ad/I7YtSlY7Wowd3elqeEFtxVfh
EIM3gGvrkppj8zkV/DNejk4+xNIXB7fvWlwM1YmSJ9VEw5rwP5ZXgsARZkMg9BSqp1uiEkb+uddD
uZfEzsz88l0molME2pqkHrZVt4NSqQNE0cSG/jM/JwhLPXhBoB4trDIuCfmlLH52G7O9qzSkk2W9
Zek88+XvJkDsurfXpLVzzizB+5SfNve8fZJX4V/wCionnXdAA+wzbCQU9XRx65YdtHelfFGH4o3X
UA4j4CCHY/qbhHXUjskYBOFDBzNemNrArCG9+2Xfw+H7zABD63UI32ebTZwKSosKoMG/mI8EHinu
PHvZ7wal85JGS7YUtL3R4tehlBalx0XNTP5241+JYPNQVcpaQVzKj9Jc2jLd84Hl1bCgNbrKFEXf
TtxFod5VrSVm8ZubmtQ3/FzXkZ5Z8Lmu5Ntgyvnez7PQhzM8jh1/X53xykeDebghSfmsKX4LJM2q
SDMT+wktKXBGDvzLfZJnfd/2UgfA9/va4Tei3P95Cv+9dcneTlhJr/9St+wiShHsUPV6xCUcyT3j
0Kb9La8GW89AmOHYHWmh+AtGpaHBW1RXEhJ2O8qGY/Rq7m+Cw08liZk6MfzKM9QghZUL+tiIjTr3
VL6uS58sfqU6BoUcBNZHPybOQAvZfE4AGffN/rsHV9C1qktq6R/px99l9gDE4Inf56iaS9E+KbeY
lfu+GjVwRqxLg5nQp3tQan7qcrz84yAZmctYZ9rsOfURBdoSsfdGSfxuKKK+vk5A5ffIA5Fcfpl3
qNHNfpS9LjKecZ57bDB5cL6ovNHD367bqSRv2DwpWIi+VmZ56eCxP2HES2xQ55A+S7w+CSYjPs2P
H5ViFX4tja+8CA5WxF+ffAVvtlhehZtDegsHbYOAAODDzqp7WMiM0XC8zvBaXmSWb/6joh7OTotI
YQR/1FT/puFskWZblLunOoJfsawZMarfEz5QGKM/qcpP11DFfY3hGBqSVb0FlNa4LtiDBfAGGJ3Y
NgDQg2twwgdD0Fxz2tC7G1bGxn08Rrq0x+4EqkNq+iMD1KRFmwdkSTjneN68zCDbzGIjM+rHfot+
rGY48rUxvaXyEkfVkBw65tHVkfrGEb316oLtAVanp2btA+9NwhGjGQngV3k0eiit+VVakO+RudfM
BxkQqI2eu7XfgCC18f5NrrHI9/Tizpy/aBWthNeqEduXAP4/VChe0KNwL3UZIsS6VUYUNdMW9WZg
dN2d+ybgWVFQcoJb2ni/6wyzHucFzhii3ZOaD/xRbopoT+M44Zmnryl8D/HEPuoHHDvzB4Ar7Uvj
8lc7juYyM77rRfkMvqLjg0Zbze+AiZ6i3c5I98BWWquii9/1rPCUrpAvrJj5EsJ83X+ycOfbxPOj
JL1Sa/CsuOduzz66CMYUSKaCiwg/aqlEOp5/hwInEM8gMyZgPTDmYjfGIf0TaZLPcQTDMyy6fvzb
c/0CRvZXc5wx/lXCDrmpMwn5+Q2oIXz2HzPoVmYH1ef7g4lMFIgbLqku/fKISvg2TCfOYHx6Pfjt
BQquozHrCj2mDFdXI1hVG5RgB40Z4iyhcZ7jXdTGb7IgHI4uXOiDsy3hNY6Qfykr53SLhZsZ11Sz
iT/UXLztcigNGiZzuDlkquonmN9XAkTPMB/tEdcg+aA+Dx7/03HJPrNANJn8aiG62G08XJmD9E7f
/2W0hGmqMTN1TMf4KVdd0zWTdASple5fp+HFyzvYi7MVFbcgdFIQz5NMsvhjDqDtKtc055n2kB31
q+kxg8sfLkrJyscBaE2n+Nu9c4Bcm1U4gWsNX3+rUL1Vq+BCC+czOnUDvjeV/LAbDb6LcJoP4IHd
A+huWHH2scaxcPy+jiYJnqwvSdtYFb+BP4Gw7L5vWhRX6soeY+wQgIBfQ1seHvV4tOBGM8d3Zfwe
AsvutZji/mljDdlJI5y6lV969AdAKtgZLcxYIw6Kb7614hPkcsN+HvX/S5jlOLiYu8XLRzCFY5rB
6UocCL28apS+Niw+7roFxoj2072Ecf8YG7RnN3giaksY94tEFI8Nzaf4YK6R2JpwyS5DkSWFqeTS
fmLaTIVlT91JqPJe4mqZ92bBDoPUAAZVJcTsL4CMlbyK69rCFzwqCW9hKvgxDcwjpzdRbPUTQOVr
c3ACnucEZPiPsf5W7PL11cpRjnS/BGydLxY58bTbuBk/r5Bdgv3949XqMBFLYu9ZoOkOUTSccD7b
wjfdHMDvpSG0r1x5pYuajkFzNNie75Nli/9tEHG/XvqrShwDTxRbtzo+rdbJm7xcbGW67EAt1g/A
A+1fq2GEXsUF6tuQ5NJdMXSo0iFHUwXzExSb2BA7xoELF8PCyvx7r+D7OTNNRAkry/Bace8zjVkh
qLXeklpziAs3cVbR1l7aa1iMCV3GHb8GqAhm696GwINnevexWDNY/t7tbLq5cRZCehvPi4BdLkgC
gVUnye5olqZqwV0vkEBz9/EN6TDlQQ0vQfnYbdnw2fa7RwotP8I4+of+r1AXo/CWpN7Xfiqybs3q
zNDug/ztAXsPBOttYMroAjqTa9O3ymW0N2B2pbGGDcEwIMFVPVzGD88Neo88l6Y4+sSRVu1c6Rd3
1SY7SwyReDMeC3ZjGUjbz+g9eljD00gqB3y7ePUJ8dTnQgNEMFyX38OmXzPwoQv7KCxmmCQ+C1ka
Py/yX/ThdnbtmA4Pcv7lVUafQC6vp54KA5tqoBgh/0E0MlZUwt8txkT69AsQkqRMJvZwlcoHuDlJ
pmrgU+ObewyxU50xsaI+ouEv/1S28HZiO1YmdL7e/KlmjjCs/bAwVcQR9HvfkWBZ32KclmrlGWu0
JUcF4cOvIALLG2vcE2XdAQGJxLw5LzI9aMylbxs8L38tdbV0nSN2+ykcbF1dH9uSIewx0F92eYxb
0BgPXpBGGZHTv0pnHmGu2VUDwQYov9IEGE2jldv+NIYGoYzK2bYFcPQCkCnl+gPsBIyTxsNWz4JT
QyBpzwcKd8Rf5dGu6kfSvMCvC+Xr2uYEylO6pu+BbKTOiXNeGWrreJy883h3Vb9evcX4cnqix10C
0Q3HGifg8d1WHLWq6ezSgnIAc7yxMr777VtQrrwqXuWj3Yu5cOprv+VSejy5F82R0va4Hc1kKsFb
GNma4Mm1vVZYgIOa2/QuFtTfJgb+gFOhMiapfh8jEdI2WS/DAfK2vYy8JOWWMGrrPkbc1I8BIdJj
/1JEsPA3FVGSyy5nTNxurzfaZMD2geYKKkWWPtFyoOWLozw187MEdwpbMNrikzkYmAH0unVG5J3M
jD1eI8HORd8BgsnVkpvJoFwB+pmi8rBDpE0ZY2HK0QF9d7c43bjeb9Z882V/2US64rah6sqLUZ5a
H+zlzzyXPAaa7yZ9wFTYQ71FIox3iZHr4Ue4ZW+NyoRk61VLhWSjBIXMWQv9m4UnXw2aS33EIM+L
xUWET0B4uDHac1Nta2wQ0p7J6sFHeQbDJTZvOBMemmOJkHsvUTHLr3OA28xz6glAwW/PqSwH1FiL
y3rhNixmQroItL9IGJcVe4w5GsxhGFFkyDmnwZm1T2eSTj4ij6XyWaW3/QF8wCcUL4eZ5mMCXm1z
076Hd5mloA1MQagAaHi6LqNgGQ3yE0iNpp/nPTsdxO3+fUZlGN1bLooDFFBKtMEVwU3Ca1fntX34
m41mm69AhBh+yIvL56rJ2nfIxItUi6NofLvOeihR5CrRgpuY1yQbjIxbwK8Bgj3JJRwDe4Cm9vGz
uKdZubVucaWAvMbYUKYNMgvu9RTYGvLvRxe9A6joyV0TcDm9VfC0bCfaffhAZkWP29sf+kE1jq/z
7gy4FytH9T5msrvS2lGxsjvW0Ai+CLKrykIZe7M69/XTZGcj1xQxuUo8mWK+PeyQhtRqcV4AfRSB
p26AEKgcUQ602qH38nybwvsA2OBnBRpTfmqFUFCNCn2C2kpF7tiSiFsfDeLHCQZW4qHRhFbGEl5j
sy3jeljr2vUqMTQfQ/dut1SGAsEeb99udx+JbIhBF5vTWZv7D1uncIESRt4y0BBjJsvJZgIpFof+
Ehf1lheTgav8wDADYd3umsQ/iV8eE18PWlfWMGxr8DocOPHAsT4qe0zdjspob70v0WfPX3lHQJCi
AJ9ZSJCrOreWcObgSnZRVr2HS1vYkDaU3HCsMkg6lylBNq3ahE+KoG6LwgVcwoozI/FwNWuPDLHA
mFGG5WCm2jciWfE9BNhv0qw1fvNb7sCQYM0NB70gw2nd1UmeDPnNWFyRbWEgjHT+HKZ78FNjONYe
I0UK7XwdP8gjXMZ0v5bTWLNAfONskwQNMxSdSVhXrwMEK0s1K6dKWAy+jTje7gbxVXgp3Vt2BSza
smZHmTmEqmEOVSblULke2K0BOVVQJaU2Qr2Nv4ZkdkYy4gq5apZjPvv8Pn2UrQkE+MDDTxMn/PCZ
UjgI1qT9hD4PDhRXbBtW61NpEsyys7iMx7OAKHQ+nrTqj+SNevLuQ+yXDZYnaPID5rCQR6JHe5ed
5zMVNamwpuRy/NRoRJUaZF6LpQFIruAjIXnAs6G8Nd3XFr7cHGmnWVEUddfT/xtZYOUbQkP+wiWR
7ki64NVyJj8dwfug3WhjUAnj0nI/FBeztE5m2lOlndtwvvEMziKfwBit/702d+EpIPitdy80NCNn
LkUymnLEmyICZ/cde1JViazdAFqa/Zt9/jID+5nSMnJSZ6rL5coZesFYipDuSR5yRxhMfRMK5lU0
8tPWb/N/45gvWJU0JaMhTu77Genrbnut7+NWPo53kQ7pFtAeFBKsER93I/AGWcobkQ7APnnX4d9X
J2RsAdWrPzPFHdgRUxziU9IK/JHDFxfc9HtC0wVtW8ynkXaCyAnhWSiRnNWbL1SXbDxTs+xj+5G0
IMeTV5yJ6g+E/jlKSrrDbnK+tnH7ArC1XY/OamLFvso/XBCyjxhxpZr6jLdkdKUoABfqFE85eMGv
Tu2rhROFOeA5+SAfwZkAVuoVgB4dLgnbb0vDAz6IG4Swf2HzQbRMfEWxuXIE3QOaCxZbkV6JxsGN
vOgfKGv8l/gjHPWNVWci1KV3XKAfTl67zvklZBeqZDpIVgK8VN4IoD3XltIaFfQDrW5hpAlcSDOA
macARAFdkKafm1rw2Y7twEBu88UxbgCj8vCmmB5QzZw5TICnmVsjO+DT43ApolJUerNqlsd7w6/R
FP/M5C9DDsU8xHyY8/WjyjjEvTzDvoSYxsHejyDuLj75Ed04KrKFPDM4PuFVOkUJIpXJ3Ez3DkCq
LGillbQFn/lzrMVwfuIp3nNKAcXns/bn/cYG7YLSFLCN3XtqwzHqI9B+6Gcy7DSw46kdzGBqg68o
17A+op6tM5x1ZcSbn+XxIVTh0z1vveSCZpGimD15WZaipokufFjZkgeWhnldEsdA7srwLIbaXjTQ
1y9u9Uh5ULjATLYvh8stC39dHRGBpFc4OhWyU7De3/hJ4vNYpdmcSF0c7zEyOoU+Pe8dpPu8Zbhe
NCcd/cLRp20wjAB11ShrRKrMoW1ySue2D8LOXxIx3pYvRMcD5N5B7/S8W840qRjiS45cCCNutram
rlNpQkSvzzaeL5AkWqWnwq5+VbrYaALGRvR419hnJxz6QESrt6ifv2YcuaZIJcmlBE/lm3hcDFAh
9KMt3ZK4NBhvkEVQCB1uT08c5e2UDwHJ9dGmJxokYoE1hZcoZn8DmB/6IkRUL/8WXEc8XnfvUsPH
8aPh6Xvn4m1dG4vqpm5YCQ6a9YueHWCFJC9oP4ggUCIyKv89LtePfqOu/tufRkQaimgefT5cPe6L
Rt4Ju7Gk66nlGK76Q38BpvYd4EswegBjt4rdmBTUHrWfOk+/sryw/dax2QZ1r7/MGzxZ8fafU2A4
NJUoXejrefsDkPfDmCcGevmgm6YJjJ+tY9f8/4J5Z2BXBW3MQMucFZt+rSZOR0Qyafbd8YLQBVDg
Nz7oHevxtSAY4RsMz8npvnT0y5cU3HBpOJCRS7D1/C2w7XLHc56+aJB7ictN/O0aZt4WrEQijYPf
ZMCBcEtAkd7+FuKjr4pMCDC0xkuWYIstFi7M7RWRl+okMtd2mGPvV7/l0efixiVBGkuWg+xdhi7i
q/tJa2sBxSVz9ordniBKnf5y4NEEr55zaOSrmOYDLqiP4/dpRomFXTJB+bx7wEO99KcZBNl2AtcL
p+g5kWcBxLXE2uXIQc2xJXp5dGDypulftL3+qzIRRTDtt38Qk0IFNjc2nTz0pAjb/3J86+YU4oEt
n/DPq0n4tPMObwB20st6Zb2QoMJ/K7aK/DvMXA/NcNReesc251Xt1l+y0y5EhRccJISiHzBj+vQ7
0nvtex0cyUW873NBU7vRZbFiS2t21Je7jURSuz7Qvx3NugAUdOdnPcxyBEIU+aFIbyhOKGWXKjMN
jIhSsh7magYzZk25h/mJwhTmWN96LdDT+6kbyvBYvMI9ru9sDLvMoers4NfZEVS7o2ippILBIln+
Z5JEOVxouLcFhZCb+FLSjzoV03YJHX+WomoLQNrHRJnEAUQ+U3uvHtU17q1jJpFaB2AsQ8pt4JlF
Tv506q49ECIXrf3daJjcsONK/nuCvIl93sTC+Q5iUbrBsY1jRjmx3bbY8yUI3GzYjCUrdgI2hUoX
lXjXS/WoaTQEwE8IBysoBiBIieDLYXOjCI35YgJYB+dp0rSjXM18pUv1TEzWVQR08mZx48ds0MHu
cD/c6D/i/AzNtKnaWgWFSI7FQttUXUP+G4/ozPlC3fmhzafo4m8uKtE89RDlpIGSR2AqFVOSksnV
QxBINBEyoVk1Ok/lsF7kZbhnuALW2iIZMp9Avm9C6x1O1aPIombQk6q8RMyIgztZucSoI13T4FAg
rBP/JupGTXo9vEc4oHCq9BM4fkKzIAPKEP2qDEySrwb2plb3Jqktw33naO3YV5LxLfd7J5AHR+4B
bK1qRa/amKCQ3JGL2d69iYXMi2z+5ONNqvITcqYx30Rqt8gj46zt0nZn4FmPng+AYSVQaQ8djQs3
V9PO86hIJACPYi/9IHURip9kD8U0tuWhGmNhunxbATjy9uQ4Uliw3or65byJuxA8aIPg8NFrz9B/
johJxZ9iwHHh8YQ6xIbqvQs3Xcm1rTJqnkdannkP3jegIAnaalXgDpFNvsNZN9F/aGzrzhKx0DEb
6o+EpPRdbhYgz/MoDH4feEqqLoco6kd3a/1FEgYXg4hxoOV/G9f4e5WAE9akOC7A6i7gjfHnJo2a
VuPkYO9OzFidI7D2AelyFmJ0yE+/O6jEIJ8fUgA0y7lLuNTFzdvzsczJr77gsNjFBINFTRTjum4P
DnLQIN39VQN8PytC70U4g5B4rzmqKwq4+xcqT5ytdqCVbHrb96ucIbti12w25Fv4MjUsqobwSKtC
lmZwTeqikog+l3Sz+rcuHAYf10cT5/pxgmSeB0bkGaw6yDUW8TtCMezEMk78B+4+N2+ZYiqU5GVs
3WzhDcMwA5RPMICxH6lHaNtNe7mQtyw2aS0w5v0zEeMCBD4AAIQ4A5FWYc0Go9rvoa2oXA2FOmCE
KqreFaEL5sVZCf20i7NCkpiVBmmsxqO9eSklg+aSg+9G3I1315nC7e90g7n5em9qfCmbTPJPu9n1
6tnBc/OUTjw3BaPVyPHRSdTXGx89P0Azyft0q+EWhyKYdvx+2mOdwPy271agKIuVfBOTel5qLg9I
38DfLBWejknnhy1qpjcxgKQy74Lg2dMH4d1h2Kdf50A8pZGVTabpxIF1jZAKZMxc543DdH4JV3Lb
1W7DVMupSpyG37Rtr19DyuXWyQ0tphYYdNqtr9YaLT9yjUglfpglQZucgGuyjoWwM7OWjQMLdv6x
AytP/H+16hNI4BcI2AiQxUGBAvZvIAT/HGXIH3/+VFjgcx0Tj+/bOi+OvREPyZJ8BLvH3E4pGPcd
akC9fcm5hNFTM3MLjNquEdKZb71cHmZJR8gVoZnFmeFhN0tdeiJPfAo/5rcaNR6Gzpkxyb1PSD9d
kiv9RU8jupVotA7Y0WXdpaDKsc36jyCDxD85XQcSux75Iw48NsZKLKYvWUVWGJUYMJNAoM8xGaJz
PFguKcAzc2eDMV/SfqyHLjF89bJcwavd6OeGOuuRn8V4Dwrmp0eH/EvrBjxXkD1/F2ElzQzf8Q3V
PSAghYQ8xpMYsZJP4nqbyOr3DfjMZihSrgaikU94jZnq+T+5EL5HuxuRrMz+ukLR5+GtnMCTtF0G
+DuVz8iy3jdmiDqycHx/LsWbaHkygzZu1r4GknWE16fm58/0BVptLUnZdMBPTZbLWOmb/0UNU0NB
q6ssg0c+XiOUIp6gS3i4o1ihK3Zz+9ZgwgybSwcB7a9QeTbZb5OGfrN2MAtDtgKW5u6t4V/aqZRz
jkNlkAa9/e2DecxsvGTfjIVd22x8eVS7vXAOi3GQKzKEX0qFFTdzeo2+qnmbS2XvpIyAnLXpet4r
praFjCXUhJDBiadKLzOMtlpC0CUSPdpVBt4pdYThSxmhAPQIlZy8tojclBsItgCDETL5JB7ZTHg+
Z6NMnJK+3yM6CScx7kzd85PT/MHi3l26NYrGwQydu5zXeM+2oompkdJpl2vRKZdLMSvJkm2omArE
4zr126AfyfVKTTRkFoqlnFavZ7o6vEDiA09ud92SD3AKZ4N2f56TkuKnfBiaPbRit7r07+eL+VOb
w7Rbn7rv3M6VTeUKdeuwV5ISd/rI8twugRe9hMR3iGczLwkC2whvejtAfUeY2iMHPfEyeVnU+THa
ITosJEidNRKbCHjP83pD75IYAhm9Ls7yR7pibjkFcWMi9fqm3+ntrhFxWT00cReRgQZydSdrvJ2n
MzuQ1hiJcQmzJ2YUgeMd4ur2NYzopvA5WddVGKn0Lp+q6rTtnsyVRwM7rXO9n8XfNsZwEXr2MO0i
g11eDr8LllizChSW3Hs4GuDpc3z6hAKk4ENvm/HyUXGXV/C1BoCy6eITQxFSgO6miDa0A3LHc/H5
2uswGUvZu//yr5yJnC8SBkcZif/E17OqKxx2XvC0PHjCOsJ56HStvPMa1z7tXtAbWltQ4l5uii2l
vwt9zu8ehGU5isRKartKBECXumPyS0CTUsXor5kgg9O07LYZhqX02EDJTYJitWfy2zudF/4UpTDm
OapYxXiy5BWDcbw1T8AYnV+eD2uKnipntKpNlr/mrKTk5iGeJKGh3Nd3QPuey/BNd0hM6yO7Io29
YQW6yhzGZnYNMltQf7qL16juzy9wVFeO/WVnRnh0/oLIZQ5X7M3O1Qj/GyRLtYhzdyTkfhDRW3xv
dP5drxVLvs+P9cHyVSIyzlW/y1usff/800ZYF5TKSk0e3KOpzSf1R1g68Fr+TJrOjLH+YVULQ8Uw
6lvTbaoLER0EIV3TaAApojE5nrhPEZy27ktx/hjUtUdluzt9oWRofP7W08snlpi4HatsoLpSKrtx
uq7u5dg4wllGvy7h7yypk99IySG2bDvx/spfqZ6c0sJCoeEB6np0h0LJgYiWo80xixG8dLZmyMxJ
tRXYo0wByQINgPUMVNDv76aU/l8pZfW4OV3X2jCGNMues30pnkdHXAdnBYp+fyZ+GGcMXbgE4CTq
+65LDzkzAQ005BOBG0kNYTPwAaDnB8ecDXlWL1vg3urbCcRT8kt52YqVea/DNdKcuGoaAqAoitJ+
aaDQsonQNxHGDoBESR2SnGku2i/C+L1xT9Dxi3UdciFqDEa5ZBr/Mf+GpMCnnVb5dtsAG6qIjHnF
/GPs7q9Q9KbmXhkpgKHUsoP+ofT4qEdfRkTeRJ0ldRHuaWLkOY6dzQlrUAHFT9OWETl+1ivdPOYH
Ods+ofY24FyKG6Q9LRm1PoKXeVvZhI6/IiBQNDhNW2FZOygGEJYXROSly8IrBr+GMZWOw9z0LlEE
B7CGUeH1QzDkfgEknN+wX/RX/Nd//D8vuhH832vRwGDSDU5eboTymRkTAIgvFIK9JH93/NlIknLf
CN0YgGRZkEOxNx+wKmoAYhrjorMpAIZk8plNKFW67znjVnGUXaTnMkOH5ailgx4zEWc0X1TSB/pU
Y/PdW0VYgC5Hf09VCyVnPZM84vSKtxnX6Vr+OhiT9pdlMIz0XgSzLfX2WX/iPgkXsZP6dQvNO5J7
y8ToznGK7j/GgisdMdGBFqnS5gJrKHyPy5safWt9MLn1NXg5qyqeIgIVwp9sjCI1xIbY9yD/1SKE
JPL4iXMw7ANbQtkRKjg94Sr2ol6hQvGxwIAKUUbdSWaG4YmNMAlRyqodLnpRqzJiB0gQmD458yVP
I/XkfeSd3GQwWvzqurTZCMsiKTKL2Ybbkg6Ggnd/O/5WbFNcxd0fmQu+0R0SfHLT4vV1eJQ06CLE
O4LB+bzy1dx+Pteuwt7luF/M6dnGuwg7MZkLlaLizErBXxAB53LvTVpIF7vQtzPh7rMr/TRkkK2Z
Xr+gRxwHAfjMMZWX4967+IdeBS7awxus5Nmp33vSpdUHvqjOjXyBSoGIJ6jP4rhNQ7JA2D78dTaf
Bp2GhNqWMvEIf4bCSNjB146NU9G7N8bbwKP1ZRAartO6zN/sggJfjd6mdvFD1sdfJxWah8WxEj08
cLqei0Ho+BNsP1eNsW2Rehskeorta6mXuR1LmimvDY0iM7Er0MywPRuMX37mVYbdj+/8GjgQa2Kg
mjDnDIX/wvpqJt38fhZx61HowY9O1p7zXtDAjYaWsbmeMoKkQKbIVgeyVrrkgbANRE8Xjk7cbp50
Zg4MptSMlOf57TkwCixbTCNmWm3jYIs9mAtJLpOea091eQRSai8Pby9qAIWXqDqXxW3S1JunpZ4O
PO+aDY1NvEYuBpxJz5vHq0DE0pF3Hv5qWHaUf8M3liyvHpoV7ibDwBjVJlMnQivBDXukVgJFSnW5
hNpUOtRNpRYSN1xFfMNYLet64HGuHICcURXXQ81Vntu1FL0YR2VbCGSUqn/2p8/Uf3nu/2CjsTfj
Jcqx5T5hnHT5IsnhvGy4iPqzA5OqtAXYcS2jyhi8sRKHMYBxbdqnmfHqEEHr4N7AkbZcSeAB3HNF
zaSruWzaURZSInSWig4Z8QQ2YgmykP9xC0mm8Gi/e1e2bqNlaRoE6zgmM+XIN0SA0R1gTCHq5Aa2
VYKYMZEHb+L6bQqlRX6WNmnET1Cs4yC42WP6w8tHX257XKHs7kRY0Vw9oLasouHymba+gDo7TuBx
GQIIRzxP2Q2EuZInJ2Qad9uHdZsFEQo+Pt9EFMJtQgWFidTIU7fyVBcNaWNkEAwPL1GiguwqKN9l
2uWjeVeHHx++JFxEE5foRfCqFnTGhFHNXzLLN09myP2mAZORwVonNt7veai7+I/PcYDzJ9NJuz+e
grt9ULNWiLPmm0IXGbTIiIDuSqf19mbp9vSC8wxwDGbx99qeIipVCuq282LDvq7orcNkZKePSjtO
S8UQ9lxCPKg14URdW5kNKBogsFxC95iEEZr3I9rkfmG3oMbTVawyk4yiLDLPKoi1yoTkNnlieK1f
32+oTPH2QcwgxW6Ge9EAOCwiGkoANH6qYChuR4Z310hRQbjnmsnKElgLJZMmbUlD4DwlKHIHzJWE
nVOBuEgBydWcMOyMGnW9cjhxGt3LB9j8dE0yqPPr+0NHt3Aql4Cmu5wA+DDBKpB6XQ8raTvPz+e9
LEQv5FqCGimkkJGJvz2i418BgoOc4RTPyOiZ/MWnYgt/V9ExAx4hx1IW7G+/wIl2xDwuVslFkZqg
r0dqzyM2GSST3faTS+uZB0jhh+57Hkx6BTGMF3jc0t9IPprwF91hhbeZ8QQp17eVxanQBCZxNZpR
1vMFKdFRC+nhq+D5iva3dWT2vV+5qjJgiM+8GNBW6U/aHHL8Wu4XMGuucLK02PtO7TmV1ribKUhm
ckP/1Gse5EzXYaeuyVCQXKdJ7sJ1VPihkDbiaCfNu6GOGhJiM8TVGdRB+OszmZ2/G04f0WigRO1k
CinOagyBuHrB6qhkZkeQYLpt5fMDkZsPyrKgAi/jbWMbaYFlpRC+btua3FSNp882c0wwQBQ4rDdO
SGhVUoKGFFBYGTYljOG5885clFSuLXfdgHiK11JxpPT3ccEv8fXdBHpd4h/aRyw48eKVvVSzmDer
2FQzkT793cV0J6zvJyMIwc5MqnkSomdsc0H2XMLZoUpvIGTowdJPOYZIMq6pAbdYzVLUUXOE5mhL
IJXpxLg2TU/NBlMa/7/NhBzIemMijR7o2oRPdwS49wt6bR7eMzCyLlBk2ozvEpcAcEtoT7YKiZRw
J0UtZtMpx6C9RTLoElko0uI84pw2pxQpIEiJnjcDVoXmpDSvEI0mKTpc5BJrDPL7eUsDXUmHoFk0
ZqCm/7CBRTg2wTu3pSjauQAIXz184MwoIC0bn2d3q3VLDhdqxZbCrbI3K7MjehDC7W+xS78jCFKC
phLrZQV4gz7mPQhk6bWRZNd4vk0TofwbpWqi+dG8vO7Vu/3BtUrIN5ZyUE0qvhHgHLggZzzZsd9r
pYbfBPGJurRNgaWJ4IOHcKGR8Y8nRhooNV6ga8636+DcCatpbFK/LpJgIpftao/5ENZumRc9RZZR
Srq2PhOdVzsyIVMZtYvkmwByA9GRfeCpAs7SqMTacRHVpvCuTJQ/7W++53X67lx+pikz1caZruCA
44oPZRKM1MAtvRq601SxlzRx8ZTGRiMASyT/cT6HRgmcIPODIUm5COVVqkbnEJSBnTV+7cx+pk1D
X5mJrXcj/Sx9ENPVPQs/NsxZ1m+mdYqyJsQ7vZnNghjpAbzh/zcrEtH35Uv6Cra3C3oUpZC2kLgN
tDsGtr0GP6FbqjD1dYd0ueKzOn6zdf/kkYtd7MyychKHOHOguU5NGO9pGONpRvafOGfgeiGj4Nbj
RiiZFutHHcKNgQAsbdkscqQJSYReEa/qT5S5O4I+pTIHDZ54Qv0WqIhhKxdqsKrcQ+7ngdKjR2Ii
Ul7I2G7vkngOHzJ6ECX3I94+cZncDFSmmj+hJRO4iN+HRdEqRXiR2oa/kvai0VlT8T8aWr97B5tS
YfIjn/HAhA/NbTuBso+Ma+jwsRHP0jdr+LEFVICvjeDqdEDWHqGkhpndTEOWgX2I3/oVk5NRwIoS
mMCQrcEl93X8rHsfbGnq/2+9aIgAwwQoedwmG8ZIQHeAA6igKydUvOHOhKuBcsMnNHK3gG/HYpwd
REUVvrF/auWLNE0kHuMUImlinRPIvmwJMbNk/m10PcF2j8ss5CCelJBR/6cdSVW8WTD0CzgrfHB0
QzuL24y2fKueF4poEnXrgAddqiSLmAZnmDajuivDukJbwmlpVSvjCQSm8xTm8njG4eqvPiTsvTdR
0Zk4O0/19zbX7UkP6ktqVoLfYStbWe+5a9+6jdbAa5AwXp17VY67QmqE0m1owvoSg8syZDxhwarI
SitCLby7G5VqAJBTHIgQVBDbgZfJuvdbuKV2peXJuLTGpxqdsEBRG6t0vz9WW4GuYFZ8AJXZYrLF
Yw8eTy4rI0rdgrSciYnb1PB/BKrcIDvfTwyAZxt9+dMXzZhwrnxrq0idwx9qr4dpPU+c1adp2tOo
xLq5y1joB1RE58uj6g0mg7JRnSA990bvRhnXQ1P8gIl/zlh4cZG+ODa8/wiJ4vXPlfp+dz6JJ+pF
jDo3N3FQU7d8Ia2oYVMKgh8cF7WCpT+WuYd8DfLahOVJGIr+OKUKDhuzR4wprpzuCv/7qljak/b/
3K1jGIXHxMTaN37C6djX4OrosVYJ4t+oVg6I9EB8+XA2fp8CEzwGpHGeusZ7PI1OhpxY98wXsrty
IQ2Q5lN1esTqJf54HGJrozb8S540KOHuMkd/JNCk1b1HN8S9sNmuW7bwGm83l/k2mkSS0dFTn8Bd
YzVyff6xxgC39VikKWYore6nO/42BQmHahIjVqnTHrZQ185uY2Y1Xf6uw9HK7Ar7Ia1cgQ9ZOzTv
cU9UBrmqkYBvIEE+Lhp1ospjKgQdNdRW7tgrfu3jR98QjF9BeQ8DN7HiVka6pHuZzOELjYAFctO3
du105t4KY4Lyy9iYUKi5YcEYM8jEgaJ+aK7M8ZGpfRda+l/Idvk2fMMS9UZKqhdHSCpte7GKa7UR
QKcgkQa+rZFdmF6lcawHDQ8rOY5RXtv/3mngcwBRAdke3zWQkiX43y8RXhTGQnuWoMc9GHEMC2HJ
Gzc2sRfnApNCSbjRViE64Tn7eWFiBxWxSxwVe/7tyDFRaMoaJ7r5xlw5ySCYCtD9d2QIcwmkSFwU
4AbQwZOf2xdb0Ekbjk04350TByoDyZvuAktKuA0LUe5HG1wxCt8XAdtK3eUv7Sd6HqBPjZLmEFnT
bZnWY0rn+N9ZQC0s/rZCIWRL3hhcga8TZNjSix1YDHSdrMQTD1GgnaHBqYtU8qRwrpd+FFI/AITj
GGLzXoIe3CnPzqbDr5DrLaT44sDteVqEq2VGA+DeZ9/jj812nnoDun477Lw4Fb7qMEjhcQ0S6dk6
8KDrNE1DXnHI3QSgKzAlU/tDEWRWXC5bO2BeMGSNyQdUEf/V4bL3CEkmQnlBX/7goquRnFCEKIdX
da5zo9Mc4IlBMfDb2mj3b8ofqWK/W/SzPYz8C0H36Eikm8RZneLQ7vQ2C4CEBIzykTlS62jS6yGf
sbX40JihdGWoUFSv3HU8r0BY9ioqVeu25VF0OTgTSemZlsf/RpDKd5GP6wXVzooDKhXYzfJVSDkp
0RNLny8xXc8PyIlmtJlYLRYLGvCk76X/rm3nvZDCbknrUAjEkmXdC261+d+ATHS/uM9mLITeZleq
l+K4lu2XsgeSgiHiNWiBK+JD0hHz66qK1HFRcb07lqCZgOe3ksGGoS84PPikKod+wD+OQAVVMIwS
odB2pMSpQcV4qV7dN0NSh6hJSeK8Y+5avN8ylSTWKFOCVX3g3Pc8GENcp2IwanB9e1pg0fEcNRGo
w4/UW44Vf9dg/ncaJBMwqxBXNZpwx1gzEZDl1RfqtYkQ8149iPTIgt6J1zyU75ykdHGEwmvI7zic
bFifJtKOgBr1vHXFOXIXIVKSFaomNG/TdxsyrB/fxR0hf7XMV3HeEq4l3uv/94u/4YuEbXqV6F90
bwlwQq50KcnCjJZCp5FVuRoJOzfCQ+ImsBC+wHZwv8Pypwbmaj/PqQJEo4vPm06J/NYVBxFHth2Q
SSQRA/1PU4hi9Jdsv65gOPWO9Oq7QzuB/HXlmKKpPVkm8WFQ4+HyF7Dv2dSAtWI+M+RECcuqWIl8
oYAcsKqZBko6kCTdBUFk5puYHPlRZUr4SciRoipeFJnlEqFyRoEt/bYaS9Z/nWsuZx3mXBU3yc0W
QiFdrY5jP4mlxCGOW/o5vc1EdimoEVVVjQgnrI6C0j6i/iT8OzxORIjuN8t67aqDSZerfb1SilCH
mkhYqU8F7MC6jTqzI+N0+WxnsjYLxuu00tyIkUfWLIfmQD9a58tx69FctIJrM6J7AsLk5xK2Hnmb
l1KzYppsDftNnz0DajM8AHr/gYm0ZWgKifNaEw7gOdRIOPlk8W4MeJ7j89Z7m5HSYh0w2YOhyvAt
jaxM/evdwnLJfuuSpxFeWR1fhFjr0E8Qs1sEcDAzQHjSLBxA1BlkBPslJD07oHr/feVsKlvVKbpZ
jX4KLVQr6NVIUveQtEtkBuHDzS8GD9vkTWWM+Kmt0gztnfmBFQKyReuMOSVTJU077/rRnLO+2Ni0
mmXexdQkM1NBpfvap2E9IZizOLfGMrZXhRUBVsJoKVdtt6VXzGQtIKoM0mTjEOKgtrUJVbJv+Z9x
XIjZyuinkZukdbpFvu1OfQLrC3o65Xu5nw8WSxgx9ERpCLhaXHyMgvlG52cpkS6E+sJwwFotl85I
RW2OGoTNkfkP0ea21+ZTZHqb8OolooTvzBJNC4XnyJ9UsFghDvk+o3gWIsH3YrlizvGKXbUKrjfd
WZp9/8cX3BPO+XmIa31iBQ9ErK16uDFAJqPooHBQl0W/pRIcoyw0Mx4OQScgusP35fgjEuHkopFE
o325DG/o8fFbToJZG9H1FPjm5lzfn4mu21CPTao62QMGrGzlVKX5aGzz9eMkZi+02J9ac6byb8jS
Wj57VqltHygb68IT6QqvtBZYQXUr3SbCMuwJaoeUQ0rP4Zia+WCPuBnrxci0S0Gvw/gPk8gAsKWL
3T3wgodB8rREyK/giJ7N9YC7mHnXMx89P9pQX8/OBxII4LGN6tKsaqjWRHEjPwK4uAXIiBbxgLJM
ZXnicoIpYMYy1w1g9ftts4gNvYQhyQhJf1aZ5HAaHCN5Qcnr74i4jIrbUsDJSEwKblpHARp6DFub
SvplBbE8sP74Ph9M7bWG+Ef8IF7AYn4v5W82QIJPuv+vxUBe0Ashl+bTxIderkoiGcGKqrg6Bfaa
qMj15vY25YW6oSFNcY/Bj28RwfEJ3q3URCg0EZL0OpBEeC42/c4xrSZ2W41ZWAbj4BOrg+iirVVX
943d+TTJB731qTzxcDYxqrKA7NVfVJQCnY88HGAHlvre712T4Fejc22F9bDOvSIcHbDm/OlYMpsp
KnTqW74Y+XRoU+jR+vipM+EWrqEmleAxJv9fWLuXyRaNHnrQuF1dZzjNjTxhipbN1W3Ck/3WkUs8
p9XUw9ZzERBrkEdi4X0svQapOm3F3xYJBEGmEpEB+DaoOuzeVGf3UPWdbjp5PNyPn3le3zUa+kRE
+Zwhl+bzKebcVAcNF6KF4k/ilz5a2QQ9WWG659rFHTAtoCyyBv6tORyW2rB82/z33cVmjYBH6apD
WcVJbUsf0s+bC2yHznV22fB+jPMtTPBKTW7cx7IDfY1kFFdrVFvP2UKv0oPh8AakVJX0gHfUXiPD
0ixNkoySXy1rVuiDrb7RFCQnVhoO2Tp0PkEhW7ecUxBLozghd83Li+Qg/teFARERHru81aanHJWe
6ukNNAoiVDqyTAwIkuUEIPMkzCzJE0ScEy6RX02VmE2ZD72MI5TGeT2u9Y2ilcDfKSNvBPrJecMT
z25ziG/rxekFLf4ziO3RYNq9k4cPlWuZOUDXN/puMc7aVuHV7fr9k2CKaS4t/w/pTP/h7YJ8SLnR
VCJyO8M3JcpuZwGH5FuRCfS0PY13mmexu8G/t10evYokX9tr6m9czCzw3f6FvC0ZinI3RGOuL0oo
786Gr4Qz2yY/5CBsi74An0Z7NkmfUDBg+2RalMt9dxJtL2h6yZNc5Vpv15FKv9wP4IbuYKJDI9ab
BeNKJkYzCGw764IxyO9z89DFezDU7AJamIpY0OAqHLQlmsuL8yw6YduFXnCJp8nLeS/kU7ayZb+l
5FPUJC4NLNdk6qzOuAvYmyaL8a8qBSo67Xfo5r1N4xJh9uPQ0Z8i3ktlPCJPWziyo9eThcytl1BX
XGdscZenG3TunRYGpdKjWSo4r7pSAhxXLX3dNCmYah/I6mz/ZO8RipCOib2DqYhNMoTTuz2mcgmK
+9drk9npMPpbC1VWZFpvRUDlLjGN2smXdqq8esuWQ8RDb6C4FIvuUd2fgnzRPq15UrzMvpzNwztC
aBwbXUw0432IhTeyw+07EczopPepv7TGdqQdYNXbYKNHazFtNKRRV+aeZnUAVxf3AuRvtYKuPIbB
uAgfk5mpJJ2rsqIROSHCYFnNcZZjy4fCH8a0KHR4PC9hqExgQ1DZf2Q99YrGqSBUkoLgLkSefjCf
Rit9X2M7JKUELOtlsahUTBk4P+q5kibmGzIgBJKnRINj9Z6pfeva71P4AWUWClv8IFKYwKvkXH6R
74bzi16qF1EJjHBtPv0mVXjNM0KM9PDJDrlFEKa0Yb3RmofN4azPXOkqCqUu8j6LfcWzJ725aKfi
LwzlzAkAUSqywRFYSqJHC0NAciNcKBdAjfrGa7nhCKblPtxNGUmcCsyuvIOGXB/VgEw9eq1vTKgu
k0nU5yOSAMGyxyXYuTnqO3rAKXUYFKZpUqb+ljE2XVSVMAYnO2a+BLIUI4zYCaIXOpOAH6olGSDN
BO3emu6McLibR0S6BDn6XR5CuDcA22QYutraEnafIm6avUyBfuJBJ5sYWKer1M0BzeLJQkDdUrp6
PdhhjgYKajHz3DdkbFSybq2ZVg3XmiJ2sreLQpFJ1im6oza2BjYDztPDDwjyrMHOv9IEGfhZ3D1X
5WE1RDaVJ4O3Xb7cyVkbqwRveL0yHPNO3/tylT8D8Lw5dNK1ugSr+R4k5kzQRSsX51G63D96ac/m
U3z1Db1uWvVn3bUU1Dkz6oL3OO4HCR1CxkKB2EqnWDc4z34dsow8ic4CZumvtpEMZa11x9ZH4SLc
ufm8NClMebOEhkNP8e51GdfAUSp4zGqw3SvdTO42Bl87D6e9VMplD7rFcRbwVVNsMyGus0gQnzDh
/N6V1mSLft8o6tOz0ehPFVPQNWixgNor0ehiD+6QSfM7lcTAV3UidbgpKioN+dGEmUiIybFTrIZR
7SPzKuuI3f/JRQW/krsnFQzVsHnQhHXwpodj3Uq07pXP6soLtksRVcoW4qYm5qOd81C1WGnkI5im
LG8PV2RcmS5MMz+wtoQ07Hop3dixc+RhSUbe0Spwd1F38V7TKyZqGxnZrRKuOIwaxQyCjL2hwi9j
ORHGLlfUUVraai7Bma6FJPwuDfVLLimm6DP/AaFxTAG7sLcrP7rDb6IrhGhK3vBzv6plzvcYtxjr
rx8hYO/rhLshtcQqeEwTZCWB4x6kHAaCkAxfAuTMJfA3xMTbNiBVoTAKgJvuxuyzvJdIYRMtoCn3
zmx/6uQWsELKt1hJQtb3PDtKD3ZXgnpD+IkB4W79c7ZdtqFMwbBoIo7+/SnJ7dlP+pAnAmr3nseD
IAhzRskLbohCIqss9dbOc3YEatlqllp40CEDPzlWH8amM7oBpsWFy2qQxurEAfvrEivFSRpWRwvg
cAi5Dnmpj39NIEaeZqY2cMfl1jMfq+ERgGQuA1kmoietRMsYEGYPpTWYy4sS0DVMVvyGMSijgvEz
MCPmPWs7sXEpdjFIdMjvZa6MDoU/X/aGoKj2PQqokrVcdss9mziHYGTTyBsX3UXgKavfQHrVXGvO
92IM8q6sqzl+acZUMWJhxo4i5N+wOEzo+sflTQWAxFsts/5kQrVfY3epnIViOHD+aiN9JgRkDiwQ
XBkhFup4ZXctgKyuFWeEVbW4wRN53KZT5OUeiV2KAlWSnQFfTltTyxfYEGYFjIJcc/SvjcjdxitZ
GgxLUJCLkZwnzjVDyYnUeuLs+KkKiCyF/ZyGyP+yVq0lu43OwjFNUCnHspjea+dc8PE0t1R7sUno
BmzlrK7wbOrfWRhFvk2qyAEE3SQBh2lI2NcfdHqF9DqWXSfrBlc+mFlRdPi8iR16R/MzlFfT0dSA
kyOGgOhaOga7SxOzq5k7B/vx6k9e6u4D3JEykBNkBDvLcbORiP6k/rlYgOsBY7G2LVy000TxXx8t
ZefszptXjjmv+elb4AVWQuFVpXccGokB1YfsoazKR2Mo3Eh8Eto11kJKzue6gddTBfxuZM0GaZ6i
ezWrZX/PIpgJe+LKitX5+iNXZe5dy4S/hP9MXv59y8S3yITJInrcWSPNYT23pELysGmARxPZPqiq
WZWmTr63vNIramkBVp5wA8OgMbe1HBHIL3F98ZQ0lQYfjmg7NDr0tUxPmeG8zptXfE+UKPSYVmEG
M6p8oc/BPws0oIpIO0be3a3EVTRczxcH66YLSR/M8kESmyGvHbu7048LD+h+DpKCjHHwt8YzW6XA
2JJ2JD/dDB09YPWGFrkzPxXJBjQG4zPlrhkbTqkSQmIJdg0uLkyrkwkdFO3ggEpsFtBF3oBWuJ9h
8ZcI4aO9IM4be40hR1Mw3FAc21q/lla/c9Q1gk9MWx2Du5lbBt+2gl3BvCDZVXmA42nLTTaOXFvW
pj3Qd0RVKyHBlQqwtBNk255D+Ho/P7H4vTbsxmKDNH9IHwvAyRK6rCOH1t4oyDzk5qZsyj1f8XkD
EI1+/XOpwxTII/P0BIBrlUoWAMN/4tZpM3au9E+T9T+LEvkQgwV4EtHCbr7oYry/Kspn4TQ2WUk7
5OHQNUQhYh1qK/fTUgprmB8RIwdGAhu41eDfgpsEqRJYkb7gsTawKcPbhB9qEk4Lhoz40qUO/knh
DSiir8kR1Ifb/PBHfNfT0itgMv8+V5nWr9YgoZxWwbYILKNGdecA3nR8zH0LKJBlXRY7R6M4NuXb
Pdisp3jNz7C91LLIXacrkZgWgDemlG1z3IcjypHmM6tv+l1+qcudAGFTKiQVsB8dPYjqR43hCMaP
K+clLywaMNp73kvWS0S5nCva3zAbf8PHdVcACxcIRTFcM6GtjNhq2a1RAioezkCriGrrxIGILZ7V
DI5yonjkWoV/c7ghVOYaQnUXg8u1JY9IB/PZwtW30ksAmkrmvXowTbai4LYa73ZJWq6/1EBcb1Z6
pvio/M+oFx82VkbAiomI3cwBR2+Ft787yNfWROpPGjNILtSlF+VBopxEEKpBW0LZ5V2snKhjUKg1
h3D+sj8VByCMQCq6utltDUPz/3KyXI2vwKyS1ktQ0/2hY2CZFGU/aPiYm+CvTfTQOZHDlB2HlEhT
g/hVvoI4AIl2zwtS4sLdG6GtXnycr8Hl7X8qdyg+XCIZySZ4NSIWem07GIZWE8C2FLAtjVUIBuuI
8VkPDTCB++3D0O4Be7eJamCPscGhec4AsyZidt7Nz7VK/bsaC7WTCWc4GcVuao3t3xgROxdqA39B
qBjoY+7fhfLcuzCNY/MdIjQQ++W/YW8tMEsNcUdZxqauucYZ0EoH9zmY48SUB4BHKgbcaQp3S/91
NVQRyW9vnCQQ/c7/0ofT43MoXlG/dpRLna24bCE187P8SUTqQBRbUmS5g8FI81HQLWY8cCDLthSY
5irjH35UkirOw0cjnbfljsp4kBrRARN+J/NScRN5nhuM080kyVmxOp8//f4kjbVZpudaENFjTiTm
vAz6sFWK2cNfDY77/X7TfGsWrYUw+AvAFEkTCecjVJUkE+n1BHMwGtVZz5992aIq+49wMMktpCX6
5ftWokbTXoiZ5xylWySNY7NX/Ei1oH9QpJPIbOMAI/P5CywhU7pgyverZUIcv1xwqyGs4JJZ0+pw
RN/+WDlfXBng924NLMhV846OwlyBk/MHCqSR0Hz+U7ADBs7TEwJFeDO/29lsrjw4Hm56M5uROubF
7bKeU3ijT3XGAnv4apS+En+eHLW4N2qSx8nZ/0WyrkcYhoakVLtzC4gl6yJHhzt0PA0IU4vjCkGs
0xwKKi8VniAfTLbKtlGzdu7mu3ZEnkgtZRtED96SQlg1NYYqtKFMdLtkioIHNgotIl9VHNo4lJgo
H8OsqNyQeb/R/GIcPnGT0jBtiBj8QqIhIy+ecIlupMt4GK+UCqrA1/XUTWp3iViuUV+a5Gzi3Hdz
nR1kFV9YogMHB5ZPsdk4zHW2T9nXkMpmc/VpoTaSntua3/eRVJEXFQJk9LR4J/V6gis4qzOlKKIy
gRVtHVIOCKjQ4dCu6eaCFZMnMrCOBsEF2gIrDX5NmmOYQcABdg2KZE6uYE4JDgP72s93TFmJzTYt
0unBNs1p8jec70UCoP5S6givPnCkd+0HSc7xVaYUJ0wybgQcscdU7kal3Yz+AEYzt34S4xym2iZV
3KnttrL10Cwyy/V2Chz3Nf3dehsi0KNwPoZatQVN6yQcUgEkJq1WcGZxtGE0xuBCb2ihG602iz4f
pRhYBhnzU+UzSXoehvLykps3cN2lPpTmPrSvL1lF9PZ4nbMoNKfGbuzkIaFKntQbdCwGDnnzz8OG
iJ0PwN5DIvyMnvC5sszGszEc4+gJgkyx+E3heUOZYbdr/QOsBORHVOhQFmHTKWTypsHe/KJ61qn2
CJNmGjtebVyY4fcNZaW2S1ax8pH+mAGwrZdclkMnfpUN7YcPuiHiwmD+76fnZxb4JjRHoKEtJzuz
8bToIxM9pl4OljnUuzXxDDxu7i+8O6Fa88oOmW2Xk4JOpWpzg+91W67oUsOhft1noWKqR56KaifS
8B0dzrqWIumty5t9Irj0+JiXdl66Xo/n2qVPuey17druXYRej/7REVUVAcfZcEerCzxdjop5kxBW
2bw1oaP1TveMUAdqyKLFth9CSUjt6A0CV5OHBk5Vi5yEuCHmNsS6GzPNeuFbraVcdLljeZubDG0Y
R84USQPglxpLGxQboQVCWqM8Q+edHYHyIIMYxdaappp48J99P1d/Bj8d6gdOobS86vL+Fs4P8Ijs
3PPYz1A1iH/Q0652XuPcZLHOAz698dd626EUtzSWLtJRF+wXiZB3Xawjmu6E0h042lWq517r413J
ED4CyncjeEB90vfTUeuDsYF1VDGN+E0979qU6Dq9KiR4QNOUyQupIO0RoRjh+yayf6cdM1mZryz2
t540sVX/b0aN9pZ5sNu93ordHQbfsyqPiy3lzT1aKoLW+pHQYM5QMj7YDIRJZRimRYfirMtFh9qR
+ayUOfB1SWyN5yC2BjCk0nqwOpwbimFE/JiFZR31YOmnp03iPsHYij2KD10ZBheN+BHHGgWjkF/z
xGSH1qI1zbLjkQDGYcDf+4dDV8xXaMnUoZT1mnuv4dRAYyWp2sPr8LuAb33SuvqJANiVOnXEz3Rr
BT4i21qweuGuremT5frRU34WFU2618Xbr+P1DzQtTwDYP5Z+1RyOomyH2Zr4BSs0Ia2B6ivh1OYl
QAMP51I4x77z1HKRdZc3FBiOt2r4wtXr3Y1FZWRcvkC877+8hcHW3Xy5xUjPRKMyUeTjWwCMGAY4
Ia6IMPLPWm01RqDXZzRDluL+G7txNdG5FxXswGLPmOmkwfpgTQUOjhH1lZJYFpwQVGpPOKhI9moV
/RKAwUgPUIkJ6pX7WY7ujyWoIdJoang564XIM+9qqe6VdxEBDFUsR5sXrv/v9lnVBeRO2OtV3sDO
FL0JiZXR6t0enQYk+7GiUKJI7ki8OYM+10omTpfEtVt5SkNevG8lpMBG1LZF+qCupm2F2dv2nlrv
85FwehBRwtNwtxOHyV9Dc9oRBs2r5kfpDCPVfEBviWnLbgmpZnYZlQ1hadfTvCVZmHNk2O8pDx8a
427dHLs+RyjqzJCDEEo+Ay0Zibny1+6r38CT1CR853PSmLDqBT/SYF3qrrWZE2yR4kN9pF3fuaIE
yXEKor+mvBclKWkVDzibH6/XYWck6urrrukZGyoTHwMvl2kx8ui4pi7xXocxXRJgVVxAkPitwGRp
rIs0LbS230NnO2iTf6rlkRoGdNdrdxoY2dMNRNoLXgeJ5ztBPLJOAxOMvsyr/sKpJ5FvD0pkJcjq
s6S9VeSOfeb8tlKoxJZFrcpXRXb4OmXqQJNh7cmy7fcHWxslZTixp/db5iHQJ0tgXiPgGdAPCLjK
xkW5UjJ86kwrsH6KVXGbKgu0z75QmW4THa9hwOIP9bxflFa/1kFw5DFxv05I/ddIosE9VcM/Ju0c
g3FVm9O87Z2lutX68M6P9T1kFC9jo+SaKO36vsQUJrUKxUTUnHgZEEQoUhcO3WtTYGE44XIlRKMP
s82QB4vN0h6m7kOTFAai+lPjSwV3bUg8mLF5ISsW3oF7Jf3J89V8zTPgRcC1tWd43khP6zVuHsax
yTO+srw84cAn94+8V6UseKJwYzIOy7VOzM7V7rUOQAQcJhg/5xCyIG44Yeqp9l6bHqNXchG3ASQd
7YWz6z3ULjearb4kXTVTuvW0s6A99HtES1hh+20WQ1rDuvndYEAGPaEhNgyvIwNP09qOagNp0r49
FiSlgpy8UvbgrUL2SELDzd+2mJCqYEvI8iUGhFEco7kJhmD9byrlxkO6dc+9uVNQnRzKJgkwXFsh
/JsY01yp1I6auVk3ruMehaJ0XzZQo/EftLuM12FETTqYE+kn12UJmEaZ7nkzBm81U1x2oeMHXm4R
hG0jM2ah4/vJFKYcN0nyiEd1mwOlsRlBAf5Hlx7wkPONQZXJY7QuT9NTCrL+25FtyRig/kdmgh2B
gF6OmiWPBuoqW0j3mufB52eFzAwJhnSEQz0ZWPfTnkiQFFBp/zMXsfqZC26KaATn2S5/tUNF81fS
0ZOupGMgD5lEgEbQVxTh2rUqkKBOxweubQou/+pIVWw4dUSDLooI4tobQd1eFq8ah5ERYXAE5YtT
w+QDG7r4ELhNwteEbEEuh+4kySndZA2WoyVfsPJNMXog69VkOfuBJkYnb5yl8COP+bg3w4rOqwJw
+5GtgU07wauKKQ5KVN75bVVkApfNWJDUnRETCou0QUywqo/K7hh0cT7Z0q1ulMehX8TRl6H64aV0
HbFeJI+8ZFFAaI3amCdgFx1lidhcPxLBBS3ZsaWE3nKRnFI6KQ565wjf88ji6ahhraoWuTwCzElG
slX+ENtFIpxBTotwAW8cfU0YH6v7eXbYnstYkM2GOaYHjWDCpyw15GIGb/gsL24jJask3gq7BqC7
Pi7f1yZsHgn2/j5V+xVNYD6cRLDDEWSoIizw+jHx/rWSogqXPQFAVUAtYLi2f+cZFW+fVBnScDEP
kMvY4YGRuw0rnLtlBc8+4JaRKSyiwPYVihtfns6A1RoXze5dN8L4QQSL8zqW69NJ/a3m4ysaa/6d
QT3LemqX/c2KxhgQBggwEJItNoZfZvjjKHPoVBX5PL9iHZWYdn5H7zW05rrQnW978l5tDwxHl3FV
PXbtlPZ30y3XnhM85ym1l9ps7miHfZIr/yl0nNxUdt3+MOnutE/U+ybuIlCrFs8jZcehUB0tLU2r
3JfyMFrGkvh/1ON2V3m/qsntJ5k+vOxVLfz5ONziBUCisFXUhN3ZKl9SE221oz2crzbUPYrbAHs/
S+PyuF4s+6BT5yhRrAglohbYYMaRfEBaUFCkeX3+sZiriqL1aPqBwpoQQatZGw3UXe+7aIInnTgc
0xduOs/QsdhPoMSd59z+1j2hCiaNOrMJXS2jUe8YOEcUwg5A+NW8j7Qgop3vQk4bstgEMFqu0ZfZ
QmAGGR3rFwELBgzU0owJH04anq2M0NmcRiJZwQ8arWP890GUBVFPmpQP+WL7usgJb8Wu0aWy/3DT
QORS4W6JQiJglG4eWBnInX/GQnvZRLh8T0NhgkfmCBdzLNTaxQCioc+gxTNtgY/z+fnjEIgK4zEj
cSTD+Sg6u4BzmFSMC0z1HMiu8npD7T1fnNa5t6t/0leuzqSVVKlh5cNPzMOe0Jbq6QdpU3e/aHD4
es5F3I6ANq1fuZGOOrel7e9Xc3Y7M/SsY6Adtw0xk3e5hZKPsBSdkE/1cE/O5rztQEa9vp3hDPGO
i2OLH+k+IALdm6EsVPF5rFGV5kY65P+qTHeRn5y7uLEaBqZju8aPFxC3kAa6+i7N9O9IMze73e/8
CeCwHLgBZd6r2EX8xBEOVAjIDgtU1zw6HYYSaUJa+/2r/ebrV0JYfwWmnlVjVb+uzicJ2MIYK6pk
DTom70rAdQhmM++0jsLl633NfMsXlPZN7xnFIuxrcBG/p8QpcuztLuxDDzHvOXBgKwHBee7rc7Mr
O2WejHGD8kVtNAvKN+0tDsS0q6KBhWLYLbeX/3Bt8CTOqsAWgYjovYp3X7cA82wucmGcd5bg6Xiz
Je3Ui1TrM4dscpbcnIXBZiTpWyG+aT5vPwmp/e5bpWCvzGMwuvMyQ5PfMDzTFRp6sDLmWerpecUk
tA9ihPsG3/xustvbM46gATzv4ctl7Itl7sR5fWu2KE/f3FDYGsS38vQYjvqX+vXaXSLudKRvxHst
sN/K0lc35slSyVNLE2d7q5aelp03Q7UXDRIFXSras8gazqDv7AU5anR32QMpIS7lnj+jlyGbqfrO
U54xqGv4s/4Y9Pc+mrZclvxPFF/5Dd0hIJUF1aJ0GxmjQdYhyn/Uhs1ZbaAi4oNZoDrhdA29xmPJ
makuGJ6YUCtonSsWxIZaoRY4JAShwGvQWFBpCyFTVoIS17o2TgL6p51T+nUIc4ADoLCkBhY75qud
AG0sSDwQjH+fS82z5hpEcSRBs341j5Oal69DUbAInTDNtYBr95xUHksdiz+bfmLM+1bYPYFd0gW7
gPV00ZTtUlg2l5DskE/NSWuts3I4XtGNoBAQJX9lp4PwQWj4uh0zZOhCpb44NUaTnXUN4a/Z2O6V
Wmfji3sEi3OhEZwFzV9qI6PPake2bTcPdHGh6d74rFij7Qdf1v44daHiFwXoeltww53oHtuQpUpi
n62Z/6ybnM8ZInT7FNNBPGCfMo7LDQI6cX173Ks224noMPotP84SEw1nlMp+ZhRPHkSWrS6NKoOA
gtmbFAWM5S/GV3HnzXIrCyI4KFeORGxGqL0o84HyhB+Mb5C921FOtJBAJ+r8hEQeQWRq5eFIQAn1
IZWqQdawa9PsC6FrcFC8O+uWQKCZMdMpjmPCa0q6PMNV63GDCUe8ntVNQxOjM6PrklQo39G0gv5h
2qxDool+bJM7oSw8AmZA2u2eHSN+HpF6j+ax+oN6bHoNA8IFpZlX+SqUc9eV3FWH3oZgaQGenVb9
cjfMCWWItO9EGBglVJKinLtxQnpKfWGqB2+wjVv4znDGFtCbF6B7e5HF1ln9kynmKfSNAv20YCNY
1YCHe22Ok+azI7sZoMlOe2UnTcpmKle6HvIBcdoTgeCP5N3pEu7td2uZ8y+oXMlITIqS/jKaBJyj
cRXfdk/p+Zpf0w2JT4up7np0VjPRNq/hrLqmvPGW0oeDOxpSZnPo16CQkgGG6/LL79r9wu/kH0De
DhGA69fjt3C+F/1eD3Zb15YsSJ0SD98qu+25Ki1sLkNSnPXQj9fKrXehVRyl8cUTtTFT41I6bJsk
dhXglBTwU7kfuj/blfmwm1lIhdiwQBG7ktC/K7153wiYrK2RnEnBYbBPgjDTAvt2xs0iW7M7SrXS
vqPC0S3Wj/v76Wiidzp9XhJNTrI/p1exsYyz3lO9fdMLXamQrXNFVkPNA94cmSQEwDJrfoqGgDKs
S48qYDjopsHtWf4b0DRfk8uFEognorXDtBjxfpEQt1a5u9ocRvGTReq7rGqSikZ/xRJXL+dkjvs6
JSNB72WVT2VQqfok1Zfv49w+JMCMlS8HGnosLN8Mvo/JqkB7ATeNzfRq1xITvrrJdTcSqWAaaq7E
VMQzusAodNfwABq6CYXxDgfMBECUHc9FCR/puAtAJt/022rdRVGICSiixEl87lQf9ZJ59UCXIJZe
lDjjLasamPsUInOB9Ek1yKyHx/5vaL+POQ02YFSEsh7NTCWdJsPhI25ogZK8pdglV9s47j1yM5AH
q8JAT+gKrxgaEopJReN7qRNTNjyBnwGk85mNX7mgaHziTcgSAYEdUYsql8/lHfPU7ssubjlw8sEX
yWbSbHBPGjh7h+s4vesNY6uEyjywd2WR1ZTCQLgD37DWvM9Mc4rS8tIs+LT0pjiE+QXoCcfWjEDT
vLOhh6j9jtJcihJlZ0eGYtjZ3qVvDkiFSS9eY/uq/eFkxWD3M50RUhRy8HPxFGdSOfUpvE84Vlms
1CeXtPnd0EqRXBPA5YU+VnGzxfm7AkrOd9+1tlVajftJNEQK3xS5SXrqAbL1bbqAhxzr2abulXPj
KXbwD61Ro0hiaBHwVJVBdaSyuqNUPfi0dwCcsSJHBstg0yRPoOkL5Ak8TsB4l47xg7WD3+fTreSC
4GFnKmVh1aEqBo+4DC6dH/JuRAe7u6ONXouONcPpOUJ1MG23B0LcXaV5c4uFomGihZe+uOmfVP07
PD0wJ9TWMJDPJspEotyp47qO96uamEKOXoZ9YAzyruJmBz9fQm/l7jnkHz5MaPT/+FyyGerwsMg6
sZrtOMPOGRN9StIOAsQVQ7n9FjXVLNtb1vwlqJPRFsCSu/SjIncOyNJQEg3iRgMtfRVkac2g2Rcu
c6e+JsryXgRoxtgHO4Fs5z4R+sv+vHman5370Dq0Z9GZdmTkqFQBFBiwREJ3H03MrBYrfOQHw1Gu
G5J9s7k2/Lp2DACKeqQRs+IR0HACBHwfIKskaly3oi4kJ8rFAbvpUk8fNbQF+ZPpLbl9G6T1dzAD
X11Ck4DHnvIXI+SG0OhGJThY7M1UaLx0yZnOJ6fZHjvxIooaG1fVaZokSqqmgtAxgPZkgh7iJ7EA
RV3hHt44Ye241q6TkA7rJja/Dinj6chyah++Z1VI+32OyrdLKDOUyIgl9qmiUtcCrvKXi4UUiRRq
pGDtzu5qkoX9PuyDfzf2QS4nhoDvK+x8PxPuU3voNgGSwO69n/JjfFLprEMhqgLzagmyXcusH77V
m42QxTrOqDn39cH2714IB+XcxcG0vzyhFF5eTp+yOJR8I5e1Cbzd9/zLBoqDCkrS+yoA5WwcYBGi
9L+FPT/NX0m9+EHNy31M1IX4Q/QBcwNmPRM+9IALFeXlD7yW1l9PJQQ+OCuehgX85aj2aqiaufcJ
1JVWuO5McG7Yv8Y6wQNQzY/LU0DspxnyIrOzJNhwRrVGMgVRLPuqKlAZ1RWiLkS3Z3T3v2dXGfGz
r6WZf/RRSKnp4xtJIB60FHj+uf436ViN313FH/VNaJ4vH4YA1Z9xwV8hkvqfThwUuFedGtHyeTlj
zJ4dmrR8cXF1MZcy1njIgcQDSdkL/fiDR/HhGoUCJC5PnrZgzyYm2ieDKoulsP9vDESZwxL08VtA
slrFXXOeFWJ0s+koIACMm3RYCVCq0oIsfbsgEVLv1Q4Q01kX22jos6BFImv3H3ObH7bM5qSj1gNI
VckpISgbaqD5eon4viWqI3cA0Q2rGtauG0QXeJzhyqR1mhK7gu/QshHsy0vItyzEKe6Tj/Pi3PnE
Ht6S2B1I9lxEbLSakgBND2SuitygCKZKV0Odj8K4PrTyN/NgGxussL8t3YgSFMC59QX+rnhtB+06
+Dc16be4vF5gCil7yMlAnRzEmWutIDiaA0aKalKr/bhsQ6hXgCgrkqtl6ne+kn+N03Z/JcudD9Bh
JCjsDaOR0gBXc5XDII+UD65K16RxffcxdHR21dZIW4GxfDdfPWp1uXA1x07ejbkv+4zyrw03L+0I
dUGLZdHLV/mZduBGlXMU2XHGLTmyKTyTGhUSlsP1Zu9JEQ6uaQ9cS4zc3T0BLqiRm024umZF8roL
UfcAHkCilcbM4N06EOawqYJMP80SncjWFB3ZneGZW9aeuwTJ72+HI+lqT3yMm7j9CamerV+zwnxB
dnQQ4xZb9nHDG10HeNkVBqtTkahXnLTVK98suhLGkGOVNkJlAyXm2PQtf9cZdFCcqg4BLme91h1Y
Mg8rCgOxS+z4KFzAdJPuD299hjWIdfLsqLa0X2CSL45yBz4ada8bS7R4I6gZUSXmyJVRSHbgukdm
dwPkmT29D9jow4vDFHkB/sZIZl2Ve9MhT+fV2NJhnDA87XXXGV6lR4MQ7KwGO/qVIgLwVZwnBqyR
2SfZDTWXrT7SUMhqWCRQUUo6YzqxCF/Sj/kNsGFR0EgR5BeIBI66NAfW87OapvFsJ+DJQt9G6pLS
N06Q6la1D1YkGB9INH9xBlS7OS0Hk5r/arj5QjtSQS4N7ZTJn7+rIp4H9ZJLiRF5KH1CcVJyvmME
ai1wMbh0qrOeAWH3WSzhf1DmhY8FpDzljWp4jx2hMbE8rKKAxC99TZGvJZTauzNXHkAGDdisKjIo
zUHIsSXgazv+0dlAMkhcxroUZ8o/ZcYXmivmHIcIOPkCU53Lo0T6X5kyB9PL6Sx+jJz1OcmxJy8G
CzSVNetgjzQZoW6i2BwXJt4Zcv5nVe088M7xeYX2WVNob13rkwd3Niu9t0VZS4hDHfaSxtJv/OZL
Acu5eHFXQrWBdOnO+QEZJheoFhGyShEtLa2HDJmCIFxAzGIrRHUEfSpWVOF1RdBrogTo5U+X9goK
PMqJ+6NfDKR+jYow+sbknT7UNCu3oqiGIZn4XRjXrpCaLJp/B/Mt5v2AVJ+OAisaDHzqd28eBRfr
8JrpF80yrIDdv6e2469yYDCcKAo/AZ2ZmzHzULnpg59yL+BCK9VqifOGWF3s4srDIOs8MZaoepBu
XfSbDcR8TNNEjRctrD/fhweUgNIfZYHiX2BWZZ7IJfn98TOP/CGNITkqGvbF+6MbGXgxDzY47ueV
OExbF0B7CgX1SOhjeAyhc/dEVV/CSiunp3x6phkIrLNnlPRasAKlp9lsrpv7XOnc954yEATm7oR3
v0fMtZPXlKQ8z9jWbAaR+EYx7cUCMyNNA7OjplsTgDfCeSuB2gF5UGJfL3nJej0tPYwFvj0duLes
XhVLGKLkwVaDJDysQx3KY7O8sfuakfI+lCyi8+T411P5iQj1XE0pJ0WO4wALzK1EW2FEWrBAySRd
BBycGs2lu3NwccVnpBZ/O5xC/uGG1t7Nd8FY0dYtyGKxmNRERg15Dm3WOPlntV1RGHt1M3QFP9fq
2rGWDaiNNh4IDhnDtLCi1hHpDgwE0Eat67xL/YTjhF+iFdXrFD1GTbA1znI48J5z3QjFR+GxzBan
bQGDCkMDrnLWlpTvvD37xI4djavREWGGxDr1jjhKhZTclXUzvU3wqtEZWy2NS7ZlsFvwzkLXE+VW
xUWU4YQjJH/biXAbsrrhQrNEesCOZjtRXKYpF5yJFWB56eF+mnTBmgfcDpa1DCGrs3lGGgiZP4pL
4k3dwc32uIpN1UR/3LyZ6kcMpyIaNoBs4pRB8Y1qcttndJhlTrR3rZsGji2Zly7UR7IIcrCyV7+h
Pqk5mZWcUgbq02InwxpERDRdLxFkAm49o/Jq2vRQv2U9Y4fKtKsxfswkjmTSKo3f4LOyiACzbMPs
WpCTOq3GGhwIBiiVCZhRi25TqF7mLT73lnyWNeNbwhgKmAWuvXEQQXSF49HdQ//kgOHafwQiI8na
mFznjm4Rgi0aBfhPBifz8fEMEhq50JkZRymw1r4RhMJnlXK855dG6XVt9F+GXg5oEsgbQRXJzGNr
zBrjEsVdvAetci+u7rIhwyvHUyI3cg43YzvOxTbghomVCwi6ABT3uhQivVnwg+BJqbxV4Qpg1ptq
gADvRSMXSFYpW2iKbKHXmImPRlVpHqfGy573mxDhC0spH870d5p8It7mK56EllFR3l+vRsF2icZi
aL7sWWmY8yDjNU3Ze4Pdxibt8mnz+mMpqvG/CXRrkMrYleT8m7MKYYYbZlnGHouQbDZxXwqVylMK
6UbTc+wJd4t9w0t+Cjqu+fjBLFHDoz0VE/mlB6xhLTjdBBWFpRfRvnYMOxivSVU1VJI64vlRW1lj
8U8VhJT85G2bqD2bLgtfHFlOR+ZchD6MKDfpWgQI/ZNjPQ6pCXe8I1709WJPxaouH6qLaslg2NMQ
tH/zIX5Ej05G5JiwlnV2OnNZeStbUs/Wxa/IPFA0zer+3dlGlm2vhMmccjGfcEjQJxVPZsUBHPwG
/tHMKG/hzHy0p44hUsqGotOQlLtJbViUW0xeuBsfxn4+i+rJ0qOLwdatU1IhHnWAWvb74087ZLlW
5A6F7MID77yDF9lP63Q9LJxX2xYwQXHZ7JlIf5lnai2IKmHsDZTllzPAyy/KwJeWXstcyuIrC3+M
9+L75b2QC2M/vhtfC78jle4AJZu7J12Xs6xpmvWedMdbe0avYmhhXfUIcI3HJoYXxlf9OT3OOg4R
5AS9x3F4GDMJs+kUJgWOIMsoxya8uhwhpx1TajT7Dnb+zjcIutrqLUglmEequui+lOp+UdYz/zGQ
P658eBZsQrMROktjlWnDb5Sj0NeIdIX8V8eMZXSj3hAuMPrH1dr/l78j27chv9Ew21YpiMzTO1ta
rRkdKfuUDA1VjbMle0aaU5JUcTzCOGcQ1DF/NkzHvb5Krot5Cn/y2/iFmtfwr5vltdKR+3s51QOe
okGGRgJu6Wi7Ye6IvobxupM3ZykHj2Mq/UTnpIaULIlkMPNeircPI3QVA+43ppNkPbJUBfmI4Vlp
U2PGxybqdlorEwp+J73AOTvB6BrRe3RSpmw3Cjw5L7jNxtll8IHksjw2eC/yPJE6+uUZmSlDdH1w
Gvz2MoEaQ8tPGgG4qV2YSSwkfNtbdYWUB4g/5thXyUrp4bM7HrE/YdYaQ0c/duF8zgPbnUeOhSiH
jLVB1ObZqyQTAaZVnGe5VdCG4EYrUkWn6xH6eGfbEixRewcfzlU4x/LapT++xH396Q6ynm8RVR5g
hI2ENkq7ju4h2/AutXwRostvuwfHwuzG55J1GYYsygf0Vd9fPZh4FtwydWp2K3dDi+f8+PQgM8Mg
GnaLA77X//7RUPdC5wH3OVqURmEx7FFazv5qDAhujrDJJINmoi41yIo+qVGTfPa50zJgwNwMv9N/
X9owr7WwJXfiaBkQYqXy8ma9mM3h5WxvetJq9aHcoHZDJWPZJgiqrOiCd7VkmSu8ylRENf9gIkqI
K++cqqJo3nUE4BZXGu7EuRs3DotXp/rEDF1aird8He5P6fTtSIJbUDiochU5F3Biv2FnbNSHUXLz
/4KtJffY89KpbvM+OxzD1UQYi+HOTMFVWzI1DVw+Ek3nQlMek32MryH4++hgFAGaJCPG3qQEmvFo
//zu7VlgOtszOrWd48qbtHg7hc+ZWEIJyUKrN/FwREHSDgRAENGyDA351IZc+bQt4YFyYHmqp8m7
VnBGf/1SPDCEM8kx3H9UjwJmawqoJB9N9Movg2hILh1/M9pY+rSjF1S+Ax/K5WzUNEPzSG1Wmszn
dA42whS3efnK8OdSBlQW+QZBbjrF58jZFuY1SAYMuKeWMBcXvmUsXF5xv+0YR7kP5nAgZuVCMfm9
eKmbirEffWUIbIZa0bDbSFtj9HnCR7Jiy4a4JgKrNTZmOtDDYvrBqox9cMTYv2TwcflSGtKcEWx+
nbijYQeejPQSveGUjAkXzdR2RyJeGN914HouwkqED9HsvvdWfkm2Rz1TTnqMBxzveZsu5VkRZiS2
jc7TWwCqS1GYp/AE2HviYxvspyiABh5G63JDVpsYip53GVaS8L4ftKo35lVEQV8fMONJE+W93wbz
5C4ZmJVWH8EG072IwxFXhDMuQYfmaxJYv4NrnZXGBNE7gYwompj/K9B0okt3XuwGKOVLEaXgCIi4
4FLYpXnmDdZi4aeNfSm5w9W6/cRjIbvX/PJPuTf5+HfvVkDvfQvB0K77KQ7W6eES22AGe1+h23Gl
o20VsWO3nBeBG8C9uezT7bwIp7aXRNCdAuf2vE8JZzqLvDGF4OJnfEQJ1yEgTbVEOi4Ilyh71dFG
5xtkbuT1ukAQZ0Lq2bOVUobq7F0vjyf1SRYKdCZdLjmnatiQdfuIiR1ljtmZ6B9b8Ni9u8ny9yVo
gn5TUIHwiikFTBQlCqd3EdYvNVtDoIQc/yHBQ4Wduto0HZeHKcYUXFsVbtlJg4Mucco8YiLhNGLa
+HzmLst2wn+Ct5dsgbXClouuBYa/vMgGt/rhQrb38R5OWHwxaBVkVAR1yJVqLXKrdzktl0omXnFF
qDuNrewZbz9EEjQMjH2ixWvHgosXY1Uj4LJodlQYGjjwHtsZtV8lXsBU7Zlfq7l7rgki2Z2XpgAG
NeyB2gQPLVBfd7zbavaoQah+AydAbsKEhO86GFETbGxkmFwCCWISeZafImXRRdznsE7gNbMDsZys
tf619OSfod91PgvArX1TFQKSjTC6m8z+mOyvDIPPfky2YA/pPTxhnJgYsAj59WlJw4cVWEp+tTgZ
DKDgYAIBUoG399ON32NnYEKTtheRE8LjQUa/cBvJiyrnmC3WenOVIbewNUjmnMijd4b10Or4tBaw
cV12kaSLv3csxcVR9Ues0UwO7wJo7baKB84/wc7iNjvsfLaC3NHaQVcO4+CNe4OTDvR+7Kyo4mJ9
ZDwo1X5CBio8cRUlYBGyGWps6pj1yFtqbZ54ykMNkBj8XSnrlbfKDaurh5/n824Rug8gHnM4fpmj
OI6G5m8iCMYohzLji7vHHBtGmg3h2nDJe/KspAlOK5oHUTWpiOyIYZFZCcMyREbdMaNxhlaPa2SK
A6j4T7rlpc6ldpPU2mbVleMpB7DwTK3y6QZtXxtKMaiNT8x7fyMD3fywAq0K/SzFoujPHFP6qLz3
46ZneRxt6I7Tq/rDLlQ99FY65lqXCpnsA+IyVVMSs1DrVblVHmeb5D2P1JDz3N73qCtLR3memUHK
tQ9zU2yEIwv3pe1LWKvOfj7Lvt0wXDD7R5WNxw8dUC9Okc0BoEp1K3R8XOabJ1qu6omPdNv1VVzT
aBjKXNNW5MwZoNcpl6YmyeBaEUQVyP3ygm0FDLtcH1Bxr3DWDDH4UBwD1Vfh5pxfgIdGf5XfO4g2
vkfcWxpX1qc72spLcqXewhab7BS+qw8kyq/A25jgkJ1+loUpXdbWbKhz8jZDxzaCQWaWaniSwNeN
W1kGG5RIl4EzQRcXxUcQIAsiPBN7UgU+XNzVd0NB5Vd9oKFLW2/yxyEa2+VI2iDy07Nwf1YNspU+
/E+PRx7neP/Do10n9lwgX3zFQSo1imAF9xNTLWlP3BlePpFferVvndeGgJ3aexO2Ya9vCqs+umKp
ennpvO4hjb4VuMJPYTkCiwhxVl1jQNJV25DZGF0EBFJY2yzk3Of/Gz14E33fCr/Nx8Dsbs4KJ7AJ
78EYn1lQe4HiOMbrhGJc02U2LzZ0ac03n6sq43oZp3SLcnsRung7Xdp7CpdgK+I4whSiMoFjkroS
POLT/yIFnZj43KdqRQN648nbIHmGhHaitIoRQlCZGBEqBf4ChpainGfIyqKLNuUrFkZqfk7Q5Zgo
KAOtYSwE85iVzx8A+oxwCmuu9/Ee4ixunmuOJ9Z/aehsOJVxBjV0DLxNIhR2xqGphOtQfu1UOExM
1ATopjnuAY/oCMhpvkeSWw1x+7yADlaUj9Up0xLt90ttbMwMAw/RG7voCNpVmtNXEHdl+j3c8PMd
GovYRC8/pvSBIQOA/TLNEHkTEXILexwI5nm6Wajde+wWZxyK0l2NucKKhcNd3sKUAK+lK5VUAHOH
2uMKEuEtfaCQVqLVBN+SBBvIbXWUk8qkCB+Cn6apSjqJu/Hd/+/Adxu2P+ebgnszxvOva0gN//lR
MYRyQvrX+5bXFq6anVB4ZSwm6t66GqZ2jkLOkq4bZVkUk1fNAAcnVk2qeqUGM8Bm8o/uSRTbgSvJ
G/ajreBvt4KYO221r3z5wO0PFcMqgV5P6guL4s0gEX5CowOUzMgq69R0RWYJHzxoXvEAj+MRsIfu
DbRBd23xxk36Yx4OvzHqrmoCUlfec7L1EZvcmGGMcFkBs3o4ojCEkfa6bgefbI+Y6LDaUFJy31Y0
f/fI7PhbzwsZMMo7pws0nvOTDRMzAGwvRodns3CELWcV50z2QSujcmsgifXPweWCdZZBwSasMyaZ
TMut2rVQ3Vz4lY/y5F4QSMHDhDuFh76cQ6VkJz7XL1iyPspy/Ztlbf4xce2nHEpJ4UaBfv1hT81X
CJSEI3u7GgRqRt0EMRNSHqbs4QJTa9VUWOZr23nPQytfbY/prAQBmL3eTVDBuVONI39p/sn0qzzS
0HRzq25wMgNdXWenbpnLsiPYd7Hn3RND7zxF1gVKa9ZxRMYbtLadyDhXYeqBodV2Iati4HkoJuZO
0SGHGFBMWVjB8srMUX18Jjc877bLUMxpGxWIqsGhvkVkC6HzJbUODuudd66VAr2pa2/lGdbA9AnP
WQnF3lVPHKC1hH6SjDX631jq1IZZW2j1R+Up9skbOrW1ypOTn6kErf0bEncz+i6eguPlauWxD79n
jT4gTubCWGJ04GU1zL4cNEPaUIQc4v77JQWseNkSDk5D88F+WXfk/K9OiKNtIkF9XO5VObXkEBXB
hmdUUy4cWcZicf86PJFYB8iMROxJF3F7KEAvwzXY6uSuRu3ou37n+rqziRCJoZeUaVMbrnTbWMSr
jU5KfH75grKPmAsNmg9TybCdFnRVuzJvPEMuMW2N6Ht1u3AlU5KGjdhSrx7oPiF2N6o3jnTDWk+K
6VmSfblPZtVV0KxI7TR9x/uVp7zspARko86WTWj9D7rIgXGRMOxylBhKLpIpm7HLcMffZMgTG9N+
tARpeHgjD2en5n2h8Fbd+vf9KyIb0sZwRpeVitWICh4jECaooAnsu3jmg+ZqywQSBIdaozJn/qIL
CiUmEcYRDyHsAwUX7pfeJS1QGOM4SZOMC8o2GFrzvqKEZ4sSFba+dhH1+FFNc6VkEYwyR8Av8nR3
13gCmkMNthx3TnMAI2gXVRbYBW5ueoFplSO08en2VbVPNatx37fhm9lq8Sia89hsu6NxpWiW4xVy
TXKjSlqk8sqJLTJAREwLoLDSuGwFR1uX9DA/MyuyvdS3wtRTGol3t/LBSUw0KftnoM859lGE/OZp
oS7KqyxqXvlL4q4DGiOzAPjzVB6WGQCRt+OW6TexHuqVORiytN2gdEUHGTHeaGQS/YRhreBV9UEg
y51vNz/4/0AR+/+lBQwohezfGsaFYcy8WOwywVkyoBWo1zC+bcx8uLyHv6RkRNW8VMzIdrxb23Ec
S7BAwekuQQlphZ1wdtjwY3ytzEOvRxqf7ljaQS/OPA3D6j2AGGj+FVZSsZcYOl6ndZwVXJzwNVfb
Z0T7fEyXENQqZfcE+lscxkvHgtBfY3YbKsJkELxLFKIDGnTAg9oNOf21uLA3D53kbJO6KeNMgPDb
C9qU9yhw1ehwENdGGPK82r/np1H20B2uwaFb4uDOJtRiWu9QxrDYjOdxY5sfzCZtk+XB9mmAL7d1
XGUujF+Wt25IvfzL+NVcPPnywB3EpUtmxrcY8ctbgKZkM/OmcJdG5laiJdhs+e2+u2ckAXvSZXTS
sOyfOkqeB8+J6Lk8eTUGzh97s0pNhdvdHIRLrM5h0ybBsErFq44XDbloVxaE5OCqfOaiOdX5UCHt
xv3r5Hx49SWXNB65MNjg9RYBMUjtL69I6OwxKlD+NLCMbgD2i88d2K+8gb52WVZiJ+pTokjQKkKV
HcZBk2fx+KUue4fdlG4pD7RtS8xTMuFqzYTTVtTP5kskpP8fDGIaAg2PiqOvKeGArIrPOTPfNfPa
qdyq/N1W3VI1AJwCqF+nnazLzHy4MaFpye0kxtAAKNF89LpA7pOgI0CIExB4UezX8rvZwzKpAjEq
VbDqMi0kzK47JNHJl3lZUMp0+gacdFFEKGsQfoANNIR0C9XJRAHOYGhFLGDHkCfWMdBVGJr0PtHt
E+8s+qX2PAX4ZZ2PMk/H2O2E0aWt2CnO8l9nc/Lc+FCCzDv7tlO3kvMZbAiedJokOYoJyFh56zah
m02E9NIDuB8BDkav1qWQZIbQL1CmGID600vRVXMhDNQu1Vtv8qIV/WscB7iR9dAN8Pj9AvZpUYKF
YsMesOaOsbBI0SJamruX8tq+lMclhp4xhb88eQQ4hd9CfB3DhPSvAvPPXKgvef/GRts5dgmt7R28
kXJjlvdODcRy7mS8BNRzvFEKiazStp6irrY7a/OmqZUoWl1CaKZc6vyhTI15iuuaCbMJMpupSk66
B9y7uTj4JjNPDSb3WGhi3GiEMdJxctr14UYWXTCsUW6MRQhBcuxeKwm/xHZGjUcr+cG/fSmvfUwz
K+TFnMorJ9XATqB4pguGS8AhvJLIjEVZtosEaWNxC/SvAdB2ldh2pVh6kX0ME5mluzXQIcUC4OCf
zisvbuWLnHB5/C2y4mqykO4g86L+aZhIVe+IWMn5gsjezPp3b9PmpO5NTd2mUpYz1FZh/zPHTPw+
7Jcqkx/qrLpWq5NcvZpkOYlC+/ewxEgj8CdfPuumB2hGtV0tPPJJqmaaC1OxSNZKwARXUbLbir5n
iinhi1iP3uBtwjxL7o8JSLQMDmJ5ANTFBH9YUilEAOsLd9nzj9mtqvui/FnUvkmQnhhBiMJg1a+I
78120eXV2x1ryU75zdQjv4tTLRTGGFdIY8hnVJ7vVHer8asfdkl1JkqiMSAp0Sv2HqR2FYab8Yqs
QdjS1Bbuf/JfLMZX/G7eFIowmms9z+NkajY2oJDquN0amycowL0/u36sdVqwJrWsS2skBirtgicC
jZsqNP47mM8hFHY9P7bryVVJdBQi/HWOFF22kHhJ+Yyq4nzx8lszN9ETrol/Ym0Ove92gqSJ/a6w
6OBSJt4YgmZE1GOwXeGoJ4DC+P1YdWnmmCE6Y5oiGRxlHWR7NXk2RD4IryXS+6HuoXcRhhbvefjg
hUIfWscIYG5Ef0YEohtSRP2QxE4uSQ3rRb3skyxVbrdPZN8YyxsiCyQkZ7bk2KddSjDclMIC8WBY
xHIcygWNDan10TVJOjZt8CFRUaomWl/wXF40J0qEU3QPnWhSeJpvRGryCyxIp80x71LqgjuZq/aU
EMJ4uvnZ0siyyF6nIFCo7Z06o3e1aZG6Pyuq5+qSnzJI/NmVT7IWsXn/XeAqvtQPpdTYONRRWyDi
DNU4ic2cyyJt6fjIXac7M3mVd2gZB/hMQ2mXE5ZF7l6yirN/JBIFMVmB5n4gmplHr1LP3wHFehRL
/ApSaV96uiFQvtuSVg3SK6Pb8/d8xxIMvNDRGpqFFyv9xnkN4xCZ0sJM5ohxz/iQpUpbDsQcJ4bM
AxaEZ3G7L4vcjLeCAubpvxlJqh9h85kXqYb/2rGgdggYyDp5bvM2JksuBxSahQokUuqwqBakBQX5
Y8La9T5demf4PsngNGkVUY3d8URMb4T3Gw3E5EazNhm0E6bGdgM0x5/Oy31mHT8yGpWjxv04a95T
fEwZh4jDMYQpvSSEU4r8g18RvzHYBlSagf03slwQsnRTQseP2eswocrj06cPrZx4RNU1VSO7+m8A
H4DpDllmqlYWKD9X6o/T0cpZQ9/luqfSlTiQxd3iDkoP2OdT332rrxDFxN3y618nkkbCc0QR+vt5
ie2w2fCUA0mMR1Kk4cg69YyHTqj4lVYLxX79ax7PFSbSccldHCTYNVjkV1iWwCml2lBtaDKJz0Ls
bnqKg096RdVFw6j+4V4vQDTHna8PuJq5uDeoE7AtJE/xxVU7g3vetNetBrXBQ0dtAd9rzh8Ei/hB
HUgQ7IPYxTF9akyWlcb2l8d32ZJDCzhq9Smz+79B7HI1WPoQtfsUNX7VelCkTAkvOVk7Mv0YlX6u
QITsVLOf539RJ41Ef1nIj243o+9dSRYzeAPilUGhGuCkViVceXNvfCwmvGOs3DZ4QC70qUJMbjvP
alNRQEIkiKknz769VflH23v7IJV0meEC3C6v4JH2Pn5e/PjGR1gATvmOdcywOaAjc/U6mX2csYWQ
Ku4qgocwTLL5Uf3Fe6unkyWykMcr0NBocw48nmHwI6ACuAGbNYYAxrXzyMMaydVIQfCew1C7iExS
Yrg0P1wzCHflQr8JNc8fhjjh1Z+P5RiAfsOe3v+kTwgouZE4RR9LrG6OntV/4rMuftahbq+M/9r/
eSHIFuQhAR3sU5WYWk/6o227gb1SQKnM0d+PaCGNR9ONEgnLHrNbk7eqMXi98+9YoC7KUrEP9f48
aX96+720movWzB+axqz9Szu52Dbx9+CQ8nh06j0M776KIN8cfs3SAytznDdzsoDBlUYZL4PClFlZ
PCnEgtkLMa1lpanBcPn0GVS+cjnL5Fi0bHrCsoRU/tTQIvzr3UNhEB67YI88NCkirj58ili8+zkU
hx2H4ctO9qtGedlnYL7xJYo7kTdt3KFiGL/M9dxQoKc0EsQ3pBfXTW1KSAQQ1f0kAIDXgkizgdar
3QicKfWLDraA7EmMIXRu3lm/O0dOYwZISpbRhGwgqUtBqmBE9dPh9ptWwOHl7bTwJvVdmNTipaTi
gvYulolnZMFwYT24SMxWadiyyH6gvRyzRmqVAPxXfPIM9T1sTrziIBuO5YSMYRtSRWDnUW2ZtVWT
uPKaxl3xM/lgcsgkuU4GCqk5o0JRSyx+KVIarRmz70H0Z+CrdMTX60IWClhiWmUP2J6o8PwyM9E0
yIOSv8fQFL+XSXyJG1O57JR/lJt1pA6Oc9b1A1nRPdeZSISHbCQY5nwCU6qdkkW2V/9Kp1EBD0Qk
bdOK04vlVG3l9mXUbZxLbyn/Mgu77IZJJYxVfMQ+phfKrI/IZUciwB892/EBf8CD1UVsvGFlqHY2
RLL18hua/Wo9/I9Mt8RT+qIijF+3aewoXL0JI60MGbb9Z/mRfuBBkyYAgnQtsu1aQJCsQCdRzAvL
F9g7zjnn+UOZ6NRJYfiQ4rABdZB/uxWNDKUzy8Mjz8mdawU/xi+GOYRPi7y+Yw5IytCtokrCsPLN
+AJl14+2ZaTaD6z17ytN12ZoaCFBbFwANXB7qslEWZsKy1Hvag6eIXlaqXlQ0YPTKhPF8gSdy5VK
VtEEmz0vYexvzM/9RU0FB0P2UF/veiSqGtNynF7ERn30NPfwOVOLBPTwZpNop4JJPH6tTRMbfSFc
aRQ8PzgXD3610HUe7qztap31bVKMR3PQbIcVn/uFV4oR9vvicNuJty1p5idCj4j/xcKrcGavBcMu
ZJqngOUBcQeh9l0bo+9SNMQ6UgFjaFw2a7vOOrSwa1KIlsDEV8HUfA7+bRD9M0Hg/h6lSiPyi2UZ
iUAmkYoBnPo0lGcyeqasDg+kHTdp0+04xJ9fKHHkRVos8hlejuFuuSCfBUYGxBLkDfc7USIdYAYZ
ZJ4YOUTwMwSvI3oBmvwBMwJA9HOQ+NksnxgFEUSYxhidOmuORJ2U54czQJJOhCiLcvLfBxlS/qbp
lKUdMG6+kSYbyoGNFoDEwJb+UVFjEK9HB5WQpjAqCIevFt0IHejSb1qw7mOozNW7C6wkOgBdiGqT
SgjFLAgJKV74ZcasYCV47xaVaM6KSk9s0/EHRAUbFmJ/M+pLo6cifGC1mHQgD+1zOR9ejnIkpPeK
EYbCxPnLp+whZJcrbDxKtVqPY+0SWxXtQ+Uf+DlpOehmnvAMuuVbSfaQAZoH0CJTePNcQA5b22Qf
pnV4EZs2Ae43PS837RUvzfmrMahsrPx1xX+Ml5GRH+ocvITNd/iIaK7G/6Beq5rf6Oz+MT6hsAdi
MjN2EKgQMIrBuYEsDKWHKmiHYqTrQfnP5DQFH86J+DqbFn/7uca8HR677LJXFngq1F4NsmVG49hl
3MlXhrKbL7B1H7twTAbwWBcH8bcz8tgymFCju/4YxTLU0hixL56/Qe+SjBYB3tpRH7sK9DlzGeqL
rAlbanL63xZtxvB4uejkAKEqjScL9lRX5i24Ia5fq1x2rjMbaYN+SnFEnpyJIDx2rikR8y3hDQde
qipe1c09kwkuysF6fAZk8zGpcSOs1EpmVYDMxt5NnuCApY8OaR/w9mv/AaTL95GK0y9TwES/nsff
7srPnKtIEHQva9RrrXY3LZ6vDZcHFVMT3LpHvzOI4K/JoBLYhqNcYuPbbuRwOE8xqocBSMgrNcp+
KHHaHVi7xWz7S95bkdlD1i1TaETgeBOJ4gUqw8NJpqt2RM3CQHW04VUHULRB6xZEi7RN5eFaKm8E
0sot9p47NUsbNoPmiL9INVJvjbCo8JqtkVpAVdVBPElEwUCF9PDv0uOSKXAAVWjm5HYlv9yKeU7H
sVB9Ks7/+qXKTTvyERHxD6PQO9qk3ICw/rBSFnrSFV9iIQw7TPqB2MjYIbq8nIyzFid2ErbDA64s
ojmdul2N8b95G1vm1+sHBxi24cVOCLxSu8e1LEJ/Xc/YZkLr0CZjGJ4kpRKy2111Xly1YOvPevQC
puYSWz7I5OKotHNZg97RNB9CQt+r8AdJmdjHXMi9uuwhG99QrsaBosZCYgU7WSOaKFmYPCJdHkgi
llaY0Dql9nj9qwztqUOXNIKq5G4cPs1utcJt+tyduzMzuaJqgFljFPos2fze6GIe7nLyjMN/+T0N
URIJ/takfiNSjU+ApM9I9AHB63olSf5QnePMLKRRziayJi2iQ/JEJX9j+aa4Ukhl/7RPf4u6vcea
TSZ2bSkMOfwHBc2pYVaByDENxUySCP2gr7JqZY7OUY24I0V+BFwerjUbjRgqAlLqIdnwkvTEb3y8
YusnkYJaTqh/+umfp2VBjb1ZhS5ayubB3Rhp8lR3A3Io6KmYJPves/v+mOWxoB8Ix8vxO8xb2lWC
iWx4cexua7I+g0F7dVQXlERyOVb3MB6rv6ziqZlg09xGXwuCFaLtrsBxxh7sbbAaPyYc33ZBSFTC
x1zYObErywwA2r7V8TNtArl9fqPG61ZzibhaNOTzLcq3+yJ+JZ6YaC1aTWuTQVIodAI/koqsXMpU
AsOwog0z3LRvgCvxCj6I2Gua1QxLArqWjljQsNGgWG7h6Z9fLnvdhx/qAnsa8MJ+7cGa3AhlJU3x
KYTCdtISAb5gNBjXqSW7RfgJMkRW7diiD46w9qj7XwKrz3EECgwsVt6vLmubn9E8yfxVKPj/Dcwx
kaKFpT22Q5vF2mUncwHJsWp6ivKRmNYV2liQQedPz1wCc8D5Ju+S+cErCpmwLifMl40ga5zBd0pm
7QoeflV1iWBt5sNVyZui+2KPdWVLW49x8qpOvrE9gosVh4e4aJTFkGbQtBlcoKo88fCZRe83ukRu
3VwbVtDTKhxMKsFGIKlJm/VOD1cUnrgP/BsbTwN/KJj+otDPvco29FdukDb6VSdkZY/ufFptOKSH
XombQaU6HPnJztYZlXHmi7q6GTNqqKrtVZVnVky/WZKyjmsiu+NkK+Ul1Mw/7DaBYCsP9zCHibq8
KHkOZ1ePmMYOIVo+SQI0f8NVeo91WMSZBKTj5L/ODLBK9sb9lnHHEgkT919AcA0bTNpYujnp/KJp
Z+Qn+vZjoaSNk0DwZheZ+T/0O81gXenYYHehv1df/n9m1r1c5tMHmd3wT/ikQj4Dd5YLLBrsTBUB
mQg11QcQhFXvEgozt26fdT0qZ9DmgGuYFEVB3vk0RkO/s/HauHXmDG3W8FyV/HJ1mbqYYyCfxZ61
3h9zxcA8nWXdbDv+MroSfNhmenw3XUe71Oak1BxrUPU9M2ka7WfnqE6RpieVNSap074HMhyrjamF
ePMZiWHa0ek3ADyHn0bgxJZAuwcu90ZdOVq1wFeucH/EeO2qK4Vw0A3l0taIhJlK5qiYTVWrBaMu
3a9yyblcjUm7lyvT8mRFcS1DXU1bibusxtHO/tg5h9gKLRobMqktNSgEovttwuc3tF7l/oVtlwlR
1nNMNqBv2jeYZk0LOqaz/E+JUyivYOxByGT7a/CS2brhL2Ubzi6k8CfazGc8iM+kV9FIF6QKqhes
ZU9a06xM2RlKa6hlflHIWf02EIfYP1Y8g8Nf+mPr/T8IIKqUUmuZx08avrLJN+uF7aLxnPgv/uQO
AuHrreu1p7WGel/JK/n4njXfeMXzrAUd73OwsDjuf/+lqe0wY67n+ki3bs10/AGQSwChlHzd2Gdc
HsZK0kcorx7F9lgf8ixcDtBEYvEuONswdVHxQkCN81tgVM2z2z6b6MGexmDtdoj8p5QFLLiN7Hd/
J6mUXnw+grXTyIvBxHBtsjy3g15VDeVzMFa5gexDUlKUADSI5vuHgnydFAkv3D7KnqxlHS4fQauL
TdyASGE9j3wpdGoJomaqAQw+JuguKK/vkyrlAh4asneqXmU17np/9m534WcceISqGzPX2EPMzzg0
djYV52cDVRpkAOnbfBvkHryylJgCQT25V8vHq5KhdtZYYuvvdTw4oDgKozcZe/LKPBV5tj67wWQa
Jf/hWUlfKVRp5Qhpc9sboBwghlsyvPZ8skmhbO7MAt7UcvuKWgp5H9yM9q1hcFf/Z3n/+X1bxWuZ
8Q4bZku4M6riFWCobHhBtdhOXmvTYfYBDq3EUMcNbYRiIZn4C5AKGRCw/MtnjXs2+cwRQKbiFiGT
qirPEpfLy0mCVvpS4Soz+ZO8jqr+g7uCJ59pssD+LLC1jGPK9fiv8rJNXuV+YLqT3DCXySV8uaVw
VcrujzaltiuUR6x8pqUrMSHxkffVIxaevu7deHShdv4vzgmGcgpu0YFnqDi836YtPUL9sQDHyPzk
5MrG1T29afOjBGsoTWFGYlgehvAxQwrqILiu6Qno6DeqVMUBKkIlL4R18mXLBp1m/XnWwENMT7lS
DL+nfaTlFcvjSo+cavYFuQr4thtIxw0O0b8pqkfuLx4+bZSDO55PbjDnSidHpYOXq4U4PLmgwUTu
dHwd95OVTem45zDmCMQbx4I2rtcYsaOnGdec3eYHycbWu77vrc3Kyx/CiTktcSa3UWjSwEzk7WCC
RgzMcHEocZT8kESGbSVppg+tsROWqkKdjnQvy/n20Ud6wdLFhiDVvAkSeLZiOKtGqA1albq9QrMH
VQJ/r63AMy/SQUUqOfZRDQGJDJCiUQnrvXpdlKNxOTUAJedSrI7xC208Z4qH1dlzoIkJVEeRSuB+
ev0LDP8ZxsO9nDjEcgxqakm7oG1S7t7C0XzrieV5cgRnSc3qw5XTYBdoVtDGf4eaSUR4s09N0+0T
Q17kbMwAVkUISg+7j5jdw2XX6EPkRn86T+L6f9qun880n3f1nJtqy9pujmI3fNehxNK22J+asJx2
B6Stj8dNey1O5Ir0xkqaiO9ke1K7FZ4vWaOE3QAWIu4c0y1GoME4OJ8NU4SPaZzcQtYEglhHdSp1
D3+Tj/XG6IqQLjSzY4Iv2tPbXIpaCjEwva12bXCUwr454XmdCCjbsL0vJbZoZikCs/yBqc5CgRnV
17uAj/vSTt1YqqvUaB03vDiRyX6jC63xKmkKGmBLGv9y2Or0tOb3fQKTZHPUmNRksUAIbF34f85r
yMsOu+A9weGE4f1PQkP26R2tKCHnIwhov12lYQ03+m35n4eaBTYlKcmen81hAdq3cDVji/N+gpik
QykKN1nOJdpNlxLsDKK+0p3C9Qb7hGHZKTiI4WUI2VZTkB9x/5eWwsyL1vgd/jbwvJk2uWzglTkP
rivo7hchuYCbl/H6nNGR5vX6OBXny6OQTdodqMjS6NWPteykg6iqpT7Y9IOTrA4gj8F++7dBrn+O
9j2EO+EfkJxpIxo86Dnwfbk1IQ1KzZmFZJpUEByJMoi6Xju4o8NFcjAam1/fBErk7kJAs3EmsPv+
oXhqF9FHZrAsDlD+VmgMc4asdX7FOs5G8TNt55ox+Nm+QK6zvdosHBDbSAwzciKsQK5jbGCVViCc
GXoV++gGDJRQ49LMFsr8bAOgAQztE0XmX7vy5uontj55DkribcC4+nkeTbHQ0t++HPC9MkurYHjV
ZbokobB/S4RwwjdKA++V9dilOKb5Y7/5cnUHeUl+dZ9cKwD6ndg8DkU4/mfFoDdCGkyXKJmWunfu
6ZSHs+Lz0DAkB6FaffK2FK5amPaoH5k5OZ6dc6kHE/v0fABDpxDzlgYzioirCEh0CfSmTUOgEyrM
cAB49DRPxtKLWUAt0MRfHSatr/BjwAqRhVsKnUzpD5KBDnnndWRR6XvcqlTGYcQaCt09J/zLgiNf
7g0unJe0kftSLQIiaPr4thmKxZbOhKJvM0+QJRxSp52/aGdsXtZ0SpVBjij3/PY3RcTc5MJt3nLe
MIA1hqkna0flW14epwCz5Rl6wwvLUJvjYxHXPqdUMDhYlPEkp4yF+h7akGaRi+x5D20bPGFjaqHZ
DuAYMPC5vU78Socw1PVArCAolw5gWlg3h6o9v0Txk4Mpyws1tNpJHe1D/kDiKNB56u+pvroMlPp1
TA703SoWSwUBosevu/nrBWiQ08dN7KomQ2fRCTa7wtF9jeB+r4bQHc0WHnkvcgI/JsTGIutyyJ/t
R4Ir3114rL9E8dVlJddtARDYO4AGNIyF9pSDrRn2p8E99lmarNdztDlWyNrSNiorkEMxc5wHp7O2
bIyZJwjE3+JjL9jrznRkZehTIQ730E19yP0TftUqd7pD4v57dPjBwsGXQlKUHY98oPh730GZ7a+e
gFEZPNqivq7Osozyl7eo+Yd9tS7qT+v8O8OzBzfZaACjimMYG4Xo6fpk63AQ0eJQsvNFAvT0RwOx
WZKGcicV5C+3YGktP0teJLwJsb1ozG5hqCtrIzKsy6cPIz7eMrjJ+wGP2aJ9eVrGOwjfsufuaYos
pBQPUR/wQr6s82QQNU89OiPJvPj15b/iy2IVytBCDP0YIgkzM9vztQ11miP2DljUL4C3wDYM3Kyr
+2op5VixcY1dOIc0Ta+OvI8PYhy4xP7eTzRMmZ/TZXJISC44fs9alfkfIOQA3k8lBlAX3u11vRY0
ZAVkrQhstNzwiJMJb6VJOvuovN5XIahMDVqYiBTMZWaNql2HcE4xCsICik7zF9oL451EFh1YJIY0
A4qtj2iv73Ij9womwdU32JLKwV/9hRtb4XqNDAjhU+t6rjJ+qGb06hUuCfufKTvYcsbexhrwnAAH
Xgh/6qSgjAODp2QbITfSm4mQVBU0gVFoQ1iGXRtAtKvPky47L3QBCLrxUf1yFrHDP9CRuplgJMam
ROAjn4Z5H6y9WdCPuTDIQgIwhyTqFqqjB2aqNiWvVNcKWDJug3wsL54FAVnF9fMqomvydVbybX/B
7r9mAkIoh3ot7USCT0IjpnPxQqoK9Ieoxx0zKWDY963zL3Qs1lfvwIgdT+Lq/bT3YEr6QUMmRMlJ
pWRJL/opj+dUkBfD5GCW/HE9GlBWmnrIiJ48rjb3U5y68g1wWO3UFLnOyRXWfU6Che8i3xj98AfD
u10A9UoRs4xvXb4gYGiF+g3PTNGD0GtX1AqZWWAerMCtHaHNkbLhfQtAnOuJgmzAkL/BC5orYR+s
bRaE964S3DggMtkZsnRkSSjNPzLdfzeH/Bxs5tNtMsNfIy/Q0P/+yUQo3DU7QzPlez32Rbqgra9c
Dze5i7Lbe8gs2jDZPj9clMevQ+pLQ4h0pjBXZM/MT8ylZEnmo8TizELJ+IGeTR2Y02WFKSJQv90i
X914McTvOhEQ6ja1SreOrWa1Honlp9haioYnuobGt482GNpOi/VeEBJty+UvnXC5rOjEwgJYAxqm
/wyYId5+CBPTeqFav8pFZJqjv7Hhb653qjFJarYRy6t0E5dnF9zsnseREDIXFG4msKMMJ1uzWz3Y
CMnHmvy9qN3mlIYCzXI9sNfWo6eVXjo3BrZXL6XIqxl9F83ycDQI0rQO5OuFjamI15UKiCcvZWis
+rVPjiWcFsjEd0o5OHTm/CoWExEeUK3f7t/aD1qclAKPA8PrMGOJexHVOGfI2WbObf82aWt7xhir
Yvqx8hb8immIhkUkt+l/ptLjvA1BzlVllAW2P7l9fTfa+83VgB6gU4CLbJ1FZi1gWqbo7yzmmZRt
oxH/MGhxtd5E08uKswRcncgsW//g2pfqpVTM7HH3VaPzk8k+hImDsH+KoNoL8PJATbicfZMeAsVC
x3y04KA5ohcWPQE/u77mjVTNYlkZ6eJjwql6FdMSo7yro+sio2cSzEiBN9gii6Q4R8BKvOUSLpbu
/NiUMYA6SoEF1cj9H/SkCniscYBIDI1pwLiio8MeABLvZtb8TRN5PWX1KC8UnBWmAs5Zyk2Jw5GU
rDWnno4rbJZoroCapKYayAUSosFBt/thaXv2bpeCiXkCtYBHw4nVwiJd7KVTBLyB+LGX8xUJMgeM
+GchVLPAVx08/eQJJin5M1ojmFSp0gWqEMvcdKDGQ0vcDM3JcvIZIBCL9SNxqcZGlg42KfHQAPdk
6OsORT5++MmYD/EPB9v9GQQgXpgSEQRSomGANj3xeBPush3QL1hKhQoIg938p7uADVI26ZlYwcdJ
9is++xQkf1FTgpOFvhLmxUgRvCI/u6F/PUszsPwbFTVvsZpQMPetr0b/t0PdAnrugZsrQma4wvcX
YZ+GqX8Giz2apCZNfnjTNPAFZjV3oBHPougz8UclsSx9u5v4Qz4oElNTi65DTfd4XmLKA824K/N2
lpiRvE8z8cjPJ9HxXVNSr4QLGlXP1+ep6b5ItHZnxbHLtLk2eCT7qCLBQoit6WxwI0l266u+TBAy
zh371Toxr6IYqhdaZDaK7vqi4CeH9hVBktxVhe1KMnmpPXOCIsLlhTymllv9o9bp9kDVZjpVCjqM
dojXz8QhuaqLrIPcNt+giPjREZvVlMAYar9tw3e2ElRHZR98/7NbOODh5BEtvo2Y2AdlExlFDTB4
gmcMUzQKaYg03MI+9fN0EL/vxP2LuKp3VQJiOwsXGPT9eEWUSDHrBk2XGV/7LC9MDTJNAikRjjmp
+ZQEpTF1Hi3iFVJGgYtytgd2AT6A7QDGCm6Zi+lplmbdpGm7dva7pzOZMICKPjuDQ9SpVuaK3kv4
9vRBC210y/hI2QEB2J14P79puWrDKFGq93CZCGkbIM7MpYRxk9suM9P+vPlt/SrhJnJ8dVb4EB7k
ygDpul6+mxEy4Syp8tfn1Knxin1/1LMoLCQLLhWTrQfzJctTRlvCH66Uj3SFNgnWRP2/XtVAOEck
yu4er4s3dXSXtbahNzmXMMcIvmwNwLL6QCGH0Oqu+Bwt73AdPgWrQ6+08tB6Dnw9iAYRZWUSQWLY
1m3rCnLlEyn0kwPKb8JqcFOG+aRMqLCCkbptfdj9Te7sxTaNPFkT7QEoTXqJiUaagyB5eDIISxKo
mR4pqb5NaAZ/Zy6s1tWo6UZsXuTmNCLDZHx09qz8xLgX1sNGPYMSA0D1CnRRrY7qNWQOWlu08JlQ
2T/QTyLGHN1LvWJC23QDrXoqlygZn5JN5HP93ijaeCOUA8j3knUyW3GTlNZacgrBhWCf8PIzpGpf
2D1Gz3fpsi6NgBF1G+yN6DyqZL5CgXa8n6Ca98i+z0ySUD4CSViCJ7l3T5iTQqt0rAmlhvt5JPiN
2GCQCCTM2EdDG266cWFVNT86tLpfpUALuF26DFKJ2hb4FE90VCnB92kmm+BeaYLotIVYZ0dHDmu2
h10bUeptjYMlrih14E7SKBz0KVbPHcCZ01YVo8N1mPpSST0FXbNX19hg9NpuljL7VfTamP7uFzkk
ZdhNx0sIC0WJHUfg2hxxPBdxB1xJh2WvWjD6/thlHguQzYk1mXIWl3dr8lWasyqS9CXWYELWACYu
RSnZr+B2aADcgfTfR83JcCyr2hDH3cVsdOdd2iwHbuyNgm1rfDzsZ0ZbE2wxS/4q9FP6OsT5ZnZY
o0Km4HHok1zuF0e1KXykL9lyoT25Y5CbU3WqvGJNFHpFojVqnj0Tho8nSgLONZ8MZQnnRnV70lQ1
TLDjc7O8BMTvAVC025Xj4Z60y0JDFF4N1WknlsTgm6/XrTtgUJXD6obA9/E1phKpfmTrE8dmdIrS
7Gn1wXQq5MlwOgi0V6f0wCyoM4tJ+R2HkWNom7I2KD2hW9zjXV+5kxEBRGnhsxHukb7teRHvWffQ
We3314DNUdIz92/fNvZTFxtWvt3GFYt6y93wGrFEUWJbwG3vftq3pwiAYk8vOd/IVnM68P0e4899
/vaIqUFwqTD/d6ehf4qb5WCBQDv/VDG3Pbew9mXYWkzmUGkLN1/pAP8TqubwUXxkvCj8A14jcaUH
ICgZ4CRrCPt+x91f0d1cNGtyMmyJqPN61+Biz6nX+3A+OUGA571WEZl58CGViIiq9nG0PwzQAuYA
s0zXrpoCp3BMVWxacXN3PXKdZkJEsewioNKMNnaByK1OsHdUgzBHw2BxfhngePDS4IFqZYUatxKm
vf8zeCecBc5R0OjRp5Wwofqspg3NLElFPkyPxmMnUk3MIFwYsrYnMWrD/yY6mLe07tqqeTS0h08w
4y3sM4EfsdYqJKHL1ccc1FBiPx0V3j68B+IgVazlxZXDTVmcxTMcrE4MxikxbFNHdQS1Tj7NAOAH
5aioxQgvRuh2kubYPTK2b8pvXuDobsmt0/OOmLimGuxhzCOml7VC2nEYVeLqrVqWH9aFQS5dtXrR
qxyLwtJNwTJjTWhmeYRjMq2OaCfZmyoJhcgpcIX9LIHhxDVUwllS/7Q4f5EQOHIxIY41QsxR90IA
TkRxAtf/PVkPf6NIARNlF9DUFEgG3g7K0osXH14gIhUCK2zB8vmXMe8anUMUjZcQ4/gFzNe2OCiX
TL07O+hP7CnmtJRU5oEjWCI9jwkcDj1dbfXlgrqgLtlTnBuvhlsPSshbBegUg5roG5ogIAX0g1fn
RAfImJBFfcsYa3xwV+2qzR5iTSsBZw4Wc/Z4yYUhgZ6FqgB4PVjxis3KbX2nUpvRmm5/pFg4w7lK
IkC3EpSZ1MuaQRXNgTqjyqQfgqPJZPeKTHpLX3dXq3SM3Rafxna0OfUqXntCiHYpoT4cylcDCpyx
qGu3eTHL0iHmOFCRUlloTATmQk8vL8Rthl0MxSHLm6gjorztpgdtTPNuCwbIS6MrPyXmbbFu1knP
F1YzPiXmbO9j+hSJW577oEyjzRxXXoYbyfypGQ3CIoddDeLqdoSRSfFKCRzvOWvirXPBqYQD1Dq9
8NPhDZur2idQe/ikyWh0Wgn857ts3h9Ri0dDtnLMyOdjE/KhyWKvFTTl0a5MP2qzFNHscjjVms48
FMhrEV7E0Sv/Up45TBPF5nrHf/6hXUZUhaFAE8w/Z3/JleTorMopejsZpzYY6a5/Ae8nCrRetMb2
NRwqIAjl28dbd9TX70wg6ax8pvA29nTv66Oi2GRfY+7qi0DqVl1aFleThCq8rOhT90JWdJgFOjYp
rQduK/CY9FMOTp3IxJzgoPCDd3bPHOdqAsZpScFjYWgh7YR41F9W69Hplca/YImcU+DNSQSz9Ry0
bUndTa3zFQWcJ7t02vutb9Uy0ISALS+QzXgWTyBsnpxZyWA2QHk9fyGrDS9n8lmWreCkAxnody8R
SUMghw0M9VHq9yhucd2UNMhXqQqXmJQcYw3jWArw211YRSP8E+9snAAX0wPusOgMv5cNxSN73Y58
gaNIcUZIkOl+anU/B+E1dYxYKI7TMoyCRxqb2oP5l6mA3BaT8v+W4y+WALf/758kF8o2mKH8zjhB
Pbv9YWaGDMtauTDAxiwL9uJpRmvUAjYZ9XJVv22MrqaFUbV72cYo88+Gn7mKCR5+4aYjF5/JA1ab
QPnCV+T3ULIEJORt0aruDj0NTjo9PoIIswgJK8/iSeAl5NdWUbG0KEm8Mfa+cqxqnuR6rXjHSKP0
o6V6SwH75DFQcwGuMU8OyZpjh2z/6gvgzEOCyXzVVkZYIRnI9iKwGpiwxNJoPvjocr57WwBq0g4y
T8AJYF7mwxY+IHXHbG1fi8dWfpVY8PHKPH5o1KWlfuScjUfOdPgR8FEWYrgiAmdvHnCBxk8mp4Ma
dkHmJ88Pg6Ane5fyPr3qzCuiztC/FkezW4+pwdI6uzFthJgipz+HX1Ml3+Np1RQGyg3zjn75Wy4g
r2Xzw7U06bLr6DL4V3ekjeUv5qvjfYx6lEfvWloW+jviE7BSSI0xKgsmTesJttLzL9m58QGFn1yu
ksuZjZjLT1IO6WJUnaFCrkcIbqKAr6Z/+pnHlFN0SwkVgoYmj+ZObXahvRIkKVyHmVvzw1/gIQl9
G+ubJSahNFV1osPTIwROlrICGBwLcZ1TUxNljZnL8H2QP/Hv5tCE3WclwxvSfOSvScRPODzpF052
/xM2/ayqc0Fs7Kg+pAPgdlaft4biFJs8I+KBH3eR/cZ4s/k75GEcfQyZsDnn0MhZkDO773BYht5Q
NgzZd8+KMNpTruqTx6Gbew9BuihR5zoUh6joRAddgd3JooQ7RWyE3+rd68extG/ib/xW/E2Cgczm
S8PUm5q8DyjINHOwXJqgebF83Ep3yLqnQsGI+L8xh85Paoc7Pvj+reeSanTH8GGAAuRL6SkVUmJK
nvVbsarr1AhBvbLgvWYXBHVpi0p2IsW96k4D1MCcmF+CQKMfitN7j2QBhEGhPrIFs2HlXHTWM6LU
xeGHY7DLv8vRqmPeaTr6oSFZMXo/mHowqIpYFEhIKjho198BJDjLL/fHV8saMsrr+VaqU7vUNeOP
HlR9+pcuqWKWBrRqwXV5AURNq2nN0s3YLS4b2iubQVh6oVSFJP8jsHjHNCyASBKvYaA6tDPxkr7g
zqgMtE9tMNdDKdTK/V3xOB7Xqr5s0aWogsw483MXfDvIuVhS5gwZHcqiIYbZEmIrJjcs1GAlhudq
ydwACtUq8euBKRJ3r6SMzoLH6KVi3qKibRtR9ZDUkQs4kCD64zms0224tHH78Z6h7Y42vTxo0KUO
qDHBPIbKbjWwp1eFfJx5h/q+FdQD58hScHXamD/b3xsLMqPL6d1DZoQI/6LAXjIM3Mx1vMbKeuGX
BtoO9YoTnCCar0zWq8W4U1Sh8Is4sR+VeYtmO+J/AiBAILlxMWhcuSCX6xw0NLLX+fYIG0Cjihvp
v0QZx09b8KulVdkcGf0pbsBjtDCN58IEVN43YURQowUPtJsxIUE3zgtKD9KOlcByprDFwKmq46Xy
YiQwrP5qoHTZI/F9Lhd9QEsudK4m6kN1WFCWN1b1ycos1kny48ZnevXWH9bRMqm3G4Jz6A7Qnbsl
q06CzqBAqGXU402qMWH7kd4OQXhy8xRekupInKPKHTwt+zQUQOgBcJRlhvv5e5VOnYU58NgLPxZS
DVa2iTEUVUBaGs3hPnWsuiSNnZlr2qXSMV0w4chZd3PWMOJei0+NvLyzfAPQAHNVzWTP59iJX2zD
9sZSZTV3pYVt0r3ySDULOx3jOGHO/1QYRu1N416UhH/EyykuhZz+ZnpK+izo/bn6Uw2sucOyCUVe
6u2zWAN1t2OnyYgLiiGbnnyQp3/l4igXX36LEErlQILD54RfF38wVL/309lJ6qZg6K6aGyMHsQIO
nTwVfKhx4dpJ1xlW8AxRK+T36oKvWipg4bYMeT7T/ybU6ReMWmxQOJ00011zs3nastPgWSUyM+Bd
xyiV5xqXJDeQv8lj63m86y4/hXlf69LeV6BwrK9qUaijm/PFcd6fWAyQ7u1vrtB1QYEYxjnFwLVR
4l0VyyqFWdVlcM1l+nm6FMT2WGr9gTtGLukeYF4nAcOU/TU0KGd9HqlLHMiN7QErJ+uUZym8uhSh
WbImq/x1ldqsbNUEF1WcTU2E8zjz3l12q3XfXKNy4yezQ2Qt5eJg0+vGiTk/QZylAo4XtVAkZC+W
BHbJztm2d7H8bw1CwNx/qNpaEX9PFr2jnk4Un96bwS2chYpGl+Pa+XEGkXyHg/0PmzRPHR6XtrMo
SAx74wWboNVCdCf8n5x76cUzwDblHN0hspVEvZsrP2D7OjacMrKqa+kaLQNGMDu3sCmKZ0rKrZr3
RwVgVnU0VI4iAfRm0eseg1QGPWQ6oaWbKYRg0cvtyGZFd2xYTZG5TlkDMi3xfsn2bg6mn+wjY7IW
m4HdTlxN+OCNox+sjOxlygfVh0mdq0Kv3GMYqKMFJ5BaX1zJGvr9ngoV/NZe+GABUIVBGrePGt+1
wkO6CipRIJXqYGL1nbIQXkwLFnJdRltyrzPNbSjNH/tm1JUNQS9m1Pk2BnDVMrPHUCjPhQgDFqHb
o+PpNWzz8tUSxs+ShCgPT22SA6cs94kwPoEUHeRH9LtAZfQRXXLgpYy+aWyVrdGACXRLD88bNrK+
gVKXsTiDjJ5MJzfa8tyJEX/AHXcVJsb5HlLWrlEH3QUYY+fHA3cLrOpOc+dkCD/x8jS+46vUjwq8
kuu8uN7vN8KY4Iey84ti6gFvZTRpRUL+Gs+i1kybYwxWaprRupEoh+iVej9yL45bGXkJo9PMMi3Y
MOCdFDb6z/xy7+tCo1zLm9o+VG74E1V8GT9OUt9mpL1JeUUd4sAsKqUQ4DnC3KT/L3KeMfQVJjOy
wfeiig9kGTxY0VvPICX5nSbrIpD3Mh+CDmL9Hv/4RIKl2ZOodq7Sx6gVw3dLN6TaFKJ3AMRu4tw7
kMKAa+nly4cZeBJgMyO6w2D13UWYH6sL6Z1jd+yd8Or9C7CVM69fSXdEFkyI4hBKrjbwoIXluiAk
0OSiN2ENKkrJrs1G9kl91q0escvz81vYKpH7x3HiS3R0StfLLCm6OjAdjHB2yxUu3maSWcwyCWNP
e6bDdDm+P7EcqWikfrMqogYBUxWTab2FenEJoG0kH5UAxruCAPTplOYyBByBk9O/OuCC4aBPg3OG
15Gd6CHmMSdlFaWG5OwE6OAgkeT1uDSL2cY8PJnAch8YbCF/aByTIyGfs287hKxAyfdd9lCgQUBR
mJ8rl+hb9O5fI+P+rC2FCOaBFpiNtJZQ9iUriZGwGwndSqf1Osf91+NvTjabPf3cwjLba3TQVJLB
vfYz5eBV0Js6pAPK3E43I/AJWgcT/z7M1929BDGJGPIj8v2UHZKjYUuEdtMpZcucRU1AiFcFl9O9
G2DPhYiBgoWjmdUCJejI5QwpIuCwPrFI+pZlA2sMcM/B1qzMm/rsZO8A+NCLwFa/cisXQ4fy6YdD
1T00aVpKkijurJG1+sUD6/E8Nb6UvzKcdgcCM/PLwWuSe7/LX9uTPfYp7AGLILxkwn0t0rrGyL0Q
OaZUKHgMXpVyNQATPr3JMYF1U+7hfB1NseYHJp509BSh6PaW13T0Nnfmo/AZKlwXque4Nb2il0cg
LWL0IPk8lETRBR493rEpH/SfAT5+92VAPnghHwHtEXWJq71bOAsM6upLYN3aIE2dlwD7PbWtzrL6
Pcx0OqC8bIH7co5Xwp1jytpfNgpYk8fkV8vwx16XdjlYmyssLPVm4bVBv/SMQqfht8hsXwYlwwfm
+gtEZHDQ4vH7/QiH030APYzgmqRVpUHet+wrIbvcfn4pFNTq9wdBnk2t+lYoqg9D2FcIyXExuNEY
Raugr3zlFNOW7mX4q7/rHCkahrL3zc5P4bKpRRt1IVkLSgwjSw8TLLn/GdEygwmw1ntun7j4OwR6
7jdtZjoTQLSMjP/vcH+ffje9X+Nc+1OrpjrhdLGDDResCJ3+8Npedh24OJEPyxZ5Dd80b1OI+zoz
spvAC4+FuvSK5paXLZJSRp43Ub184MaG1WQT7bfLSnX89Bi6zQeUesyFxZWj9tIlYXbRHqeIgMqm
+dL84VVTn250/6PsJnrVE8wgU+tSmRv165K7/siCHNkpnYMdT/iXXcoUxbenDgGYKuQ202AFwwlu
Sni8k9SrltJ5tS6zMbACJiQVQXjeKswZGekc+aM6Ex/2r+MfoLwJRzzFNrhL4JgGvDoBYAA/rqjD
XTX+17C8NEWj1xoAQ5uVUKxcdN7d75u3XUxryUXRQxjdVba01KIREcnHeG898/jQUCHx6n7bOD9b
SK8STfbUG9ZZr2QIT4+arcEC9Tl+HHRJTsY1OeC7tbDX56zuWCX3xBdAzaE8i+uUWL8XdNZ+qF+Z
TASiaOvqHyJKjMEDU9WL3V0gmI5GnY+s+t4pA+Rci3gTgI7Ii0PVSEdlbP1U0ciQ8K4jM+dfmPpW
fS20g+SA73gzyZpxiQTQDeB+e1uLb18tKI20AWKn4Ptg7O6E/JIPAtFQl6XrCVTAnS+7MukTPD5u
/llszxbm/N3XVg96n1SWa0Do4QRhDJFecU92o1Stuz2U1Io4pTqQjTO8AvkTIvWj5lrbcP2tAuYx
xQuXJDfs6FzdsbVpBwNsuceTnEtQ/+x2XW+/x17Hm0jR8M0AXaIvQk9WvIeBwrVOegkZab7N2FAw
qBkd+gwk7nEZEVWDkpA19VzIRruzRd2jWZM16vaB9stWQsuG/Vgk9NxpeKi8WTISIh2SxnyRX3vI
oOPyQRJsNu0HeOyVVOZYEiCdO8VhL72RgHHbldr8URnUS8hlDQtit3xh/m/D1sw/41/AVBAoVn5x
KloHUsrhWjDn3a8r7hcEzisCu0KnHm21QWVAmPGxhINWRB/gRYE3eNxtuDdIpMvt7rxaEw7qXkAf
8go9Xg18CzyYdBynRNkBXQY6isEVZR61wqt8feRzAKvIId8MHnziq/GQ7yCpthlBT9TgLvFG4R/d
pDuE1EZj4AfRSfckToGy4Q/b49J5mWD+E478M83OTHJgnmHA0wSJX1C9TDyAJyXZsCidTCV+MjAi
lGpXHhJrZ1bSa7l0zj/5PaGu4kTpFcEp1QM2MxiLkAbKQrZQH82RisWKLRM3p4ktzRS0lhzP0Pf0
tMkRavfnoooLqrRLAqdgmK9d2MQ7Ths8/VSLypTGaBRLoDJz8nCONjd01fU3qCnW7pav/hVfeXUE
u1ujJPxyu2wZZe4H5rPlRh2SH5bcT5ZU+e0hG5kHTQvSGEEAhPNCrepTYxKU8908dJWWDhWDOFb6
kMMVHfDl7s2o6kwXNrzmpLU9QFgTTk3Awz46B8X7sWkWGQjc9O3mHShbk3Diuo+1HTxofBOtm8V2
MlgUgQqJ1Ugb/aYZXW5oUdYR4iCZ3w36JgjmT+6UPcJyTTLZJJs6OR9YFQTIp7hwaa1/Jm5lGz0g
SiRFDSyWul8lxohHg6TxGxQqLiTdr9V/Cfc8Jx/CQkdm88jWnRBYtbxsGL/BUDLzLs30fNmuTWDQ
+vFAEYVLBV1a8KqCdcW97VXpY8fAdpLNtCQUK8FbALmK7YeG/CwaX6Wg6HZ1rV594BclseF3E9Uj
xHzqZEKTFkhQSnFZ4A7zxHWfQiFS/tN8fy0fRtp/Yt9EM2tm85T5XYh8YU1yGIvYxcfr6tCOErzG
4WtQRkYaqxrNEhRImnQFnLkHPF+fqX2bm256IPTU+5RutnOgFbfgYl2BZczmxnLCehcd+fRNKVs+
dJ0vez9b1jrpxPHg8EmWByYWHK2vSCZUaRRAhyYE2/cdO0Hib6FDxKy69DPOCki8kuY9oyuFCrMp
js91huJfVsHA3PJ3elL1W/j0jR1Iz8nxvfX6i998FuCfRADMUBmrKNYEC4LjJzwgABJ67iMqh1qO
zQ/wpdTc8W6ygzqGHIXI+PMJDYZvgCd/9kC0OBj1K3F757j6GyZQo29LjeL5kcgWmCCtZzKFV3mF
BKg2wbwIVHa5qBaCi1gpo4AQgFaaIfVyMMzGfMmXAE+6XaAM6/UTYCmFNNj+c3Lzuu+8S+pNaJYV
nuddt/AbZuOiD8vHL0QFStRQAx2XKBBl+PGDp+AkbKvupyzjVe7jNMqNnZc4KPFWPxB3nj/KrK6C
vufeW0yyrEgvWap+dxtNuZyOaudJOepPRvms8ii/NF/97pYGRl9+RvkhYf8wJNIh8GLrxKPb863R
nkYd0nSF0/kIibOvhoGL0Vl3Gl7HYerolnGjMSfLqcFov6gkwB+7roNMlGk4hI1VIZAvsodFtkdN
41wbqwEUTk/UCMZ6VJyx5PNXSYlTBNUY6MjCC0f1s5zgbJlhdFujz26H6yF/xwnQ8bJqGtTtOUDU
psARRR6nkOKX8yhZgy44nqNS/asLhfHFFMTeeFRPlF06p/bB9lF3UpXFPl/xa2v8ci6pjy3vP64A
bDvRL0pEInOVB3CXFSsPXHKP0Wwa1tnH0AToIEIkBsd0Iiiwq97enNJWasZOr8fosqtVw7h57u+e
m/FheyqLSXNPnyctxJfldchc1Q4ktRiSCf/SyAxAzeFAmqYxn+jnTmduqPGrTXbBQmcISc5GAuKk
/UoNJKQ3Xn4vY9i49uG4OghszCJ9yJ0Mgw2nk4ynEQLXR7MFTiOGkF1zO3F8/PZXq6G4i1dXy4H1
wnoHBkHbsYQELgAsGU3Z8REKsNr769UlNP1yyYpyNkcif2ZciQpGJ/69HtEJdY7KXl0bzdPFnXkH
6uPNSWJPiA1tW9OAiJmW2y/WdTyo03x1a9cJwEfXwjNi6bVP6o8ouJDfSep/0j2L/T9NsgeaKtWk
j1VHlw5kbn45STBQFG0e7W49HDKKXGdOFiumeqhyzBDtb9oPnxpIRUoHtMVFV88yVY7C03vAwPdR
jDCFhARqa8NbvOrd40zlCpGRxsj8YTQfjVsg0Zob2FMzsMeqjkWX0yuD71nhx/ws4d3wP6C+QQIg
JzMbsRWnroZHcn2/lYZqk9BLAukLelN2GLvZ/SwJQ7Qb4iNvKERnznuksz+y/QBtsLWBqrQWzfLK
HXZSLqtbeROoE9GxYUrSYJbLmvojHWDUaubSsaTU0UL2VOQ+Qs7FBCF3H++prdzg6du7kXmBguTf
VB4yq5Yl197sW/RtjqSb179+PtzX8QKDdnAS5EjLyHY8aO7rUdYOGvpfDYSUJtG/Rgw28jFgvAVL
aMAknXLlcGtO8mbkESWcDUoygppSkHMzD5y8yYqJmbUSJTBavdwXXVIdUvqY5OakWeAJkLQ+5FsJ
YSNmkdsO60bhFf/g7GfDTKjsccccjyK7SDICUtRhFg7+CvlgC44JkymzgVtuPgx1xLVud5rQPASN
JuFHhWHD93dVPebSX+5MMgN41yLeVUWjloW2uSjzsPjFIIwNFbxmUlYZSQWL03XTMiL4n9jpnqVd
Hg4gMtJUK+JRTsqUhzO8Js3LurRZ33q7Z/XCSUV+uwEU/8+hcbVe8Uev/paB7KDL+1RhLEP+GE1Y
Ra6+5nWWAAN5hkAVyHcyL04XQfGAybfrLA9AK5smEHb/Ao5Mn+5MX4k5RCMZU4OVfobp6ilZMV93
n/0Rc5mSewysJLjo/j5q2xKn9UvDOPgl3t7wIgcCOS8APwuVM2wef254owhY84ylVz2APaOElnds
rF1n4Kj8T+qEVGrzdwhk05mYDDyU+yZ4x//Om3tSeKkD1NIdaHyxLE78WwiIc+kspXFqS288aaXO
uutyVOvuKwU8K8tF4rA2Wu3vhWe42l3EIyTcdSfjJR+9wcdCLWH2yZhcx9k5oUKkQL/j29GjVNgM
CqsXdhzs9dqBTAhdwJFPXxwrcQvvEIbAdg7Urm3P4ejjquFd3vWBVYwvDViaAPkahyJBVOSDfaI7
L9S4XiychQNAyfl+1AoudMAvpncyHJC8rDAADWYd52ekvjlIO97s8MX2nTPqm72iVYjfWO+civp0
2JngK9YHjzJBfu76u27ktz28P7GcmS0lpaj0E1bIsiqDA2wVkgI16hNPexfSBaZLhzHwieHcRALs
vgmh8DBZwfwURfT4yeGHsl1cKXbqawziD3osvWPZlY6Th9SRDu1vPyItBQxUkXaSRFixsDelGXcA
7PoKLSpCsKz/vpv5jjs8rs9ZAm3UciRKCJSSQ+MKqMqJzEHuZXm/aBCdkGe00m9Hbv+1CM0zdJyf
RNZRsVNbOAoNQfr8VDlJ8yUf1/I7iJIN+UZGToWY5oZkbBl1+GcU84kfypKpMZGDnifkiMnJbwxT
z0HcJvXlZG3TJnTYj/B1Y9ryhQPs1YYr6tlTlN6C7H0X7dxoq/uDsSp8ZC4qFFMOCCmZlGhT2i4M
slRb+rIWMYpqq6XndDLv1wsv86gPJeDKTYmJ0tqw0dqlvfszkYm0xFUTgnQwmDj+qgp6CWEzu1nN
UlKUVuIswZ9ktIJOGI34Q+Is/d+3+orXeKY+TsJyP1ynmv/OCOuTEH95rXz9783aoW8wvtGtMPDM
VLUG0mYhFCXwyz+uOdVLd1RObYhP6jL0cDmxy2WZFFRCgLSQAAvNCts1YyiFvnFAqJdl7QgteETp
Z+CQBIJBlHsFtSCSyVuejRJIuEekiJli0FIqdl/+kc5i45IHH5uns/bOlJYoYlInVdBZ6ITibCM9
qJnK/1ML/AtRXi+cKfyIPmvTP5MBHnNLMwZQGZVwS1GVB4rNl5n+ebRxlWovc436U9An5rH77QJk
qUDCZ5DG1dwYH6xWV1m912l+pNrYwj6SXfFQuuziLUCn/gjpJYFG9lnEuoE+TzE7WQJ1t9q6JcKl
g69au38XJw4WU3i9QuGfTJE9G6RLFz4jp0tusdWH+2fhbObwSxADe1ouk49aT6y+/evnMNMnqJ/P
FxI7xorsd8jEQSV15R4K5qxXcb8o+ivaNHC0wFXag8VpCHtrrCjUmvBPup45aVyoE7Mr3SnwAWNJ
sQujEZ/u1q8/cYJBvaR38AJPYYLjM/kBPkUjpNVbSNPG1BiXImBE2FvKJQXii4/rrQlPwfFQyItx
thpqbKknuC9nSSZWcMrFrdW2ximP+dNjXi/WzEt7O+eDbYBfUo2iBIaq9VoTEtl3AfT/DcENutmp
yZSNJhaoxol3S7FZMfmk8e5rc18J/VMz+V4LMn0B54+qUtL30HH/5/uz116Q1LW5b4Ntxbkm/LE6
Iq+1dRPYmGAKXtVYANmnfzwicxko828aTjKNNbRLJFPPFJVhbJfPfkY+hvEkMSfwvJR/iWMI1kMd
7UXLlC2Lyok3ob8er31crKSKloyPlFwO6jdaF1Ti4Tmvi3Bdu7TS/IDoh3ed+yXD25vSgg4UwPP5
kMRNqkt4qgBbJ5cO1DF5B54o6S5q0DnaYjij+I/xfrUeF25v/lG5d8ggRdVjUdsc6Mv7GL7e6WZV
svFI2fY9Nvs+YQf9eS3vFcfhap0xZrYGqq/QQimOI3QC4fUug7Yh8tXY2bxRsLzzS827DqBf+V7S
goZ0JVwyK86e6fFuSh8G4gXghIto7HRpQ07bmF2Of6F97EbLzFCGSI95TBdGD1aLp/+WkaiJd6sD
esOPEdR/77h1dNzvaTX9tbnxtzlgXtwPjNMyqnVG8EZuwYM2hBqRG5rb/AqpHYfLgtJQj58stM3m
otKfZMQbd1BMc8WtM01W5iraGGlEULgVzzYqZg/lLy+KmgRaP26eWa3jRaStWO4YI55y2YE4SvMp
/wVmjuj7KO5KTQBgBud48TYZxPBhflh07/LwtzkybsEdO2TjlObD3XEEeWN2XEY/tNMCS+WPCcHn
z80F/TQVzkB3QP9nKTgF4UnYm3OYpCg4/3wqErWH12teFkK9IyWaX+5yx/mNl/WURe/ZXSTDJJpG
M/uB7J2v9TGojGCW4Q30hP/5OlDEWsNBXe2FDNiaZS1cCQrr2+B39iJush9n3/29PHPB+ozEtO2A
LRuaTXGwAt+5uIlhiJDCDybgS5t6EZkbL+2eKho/4bkvdH3CVCsoeRTP0LfFe9kc2H5OJo+2VRHa
nTCfRp/JI9oDSB1LgZcYMCc/fI8hdCkRxVEhF79uTuZTxeq2dj4JUjNdbpXpoWF0XLFEGLX/GvKk
Hs9b/BsSW/GADuWDgMdvAH9vL/KajTh9li6VThHmvEy/SczM5T9WrCa5lwAOS07sS10l7Hhg+Lki
l9Tt5F1F4BmtVZT8AdLcAHBf29jumYSoWMcAUgdLw6CAqIE5RcRG5xi6GurE8HeHgrA+kP7WezIm
cERgDfAoPjxeqAn9svIWKiNSnrDirPvMhdcB/1wrTIFqXKuKmsHU504bx/6edtYPFXhpRZH1WyBv
PkwV/Li7YCy7L4gGqtHznAnt5F1lSU+Umab0P6RJs2CmmQLLpZBoLsn3XCH31p1DeR+9C9wQR+b8
v7XsMuNwwXEXk2WF1Y7bwapYJgS0V5JTwVk7TzCodjWPmqoP5WPC1gAAKE7JS0+D+Y9USmP9SWAQ
sIqjzQELWCbhYLzCcd4lYehhpY9030RBXKOWNxMde6wOOk0d9Nxt+dsUBaKWBeQ9vIfkU+IB3c96
ETsaq1paebL7iYiN8XmIRJq/FOH37dlHLLDwNIpV48LMRTdrZhYREA4ZboTImxLloD4TwX4QxWre
Eg+S6/aYD0oJyCagBwMj0z1lRQYWJDcijuQeg4wp5qSSfndP+GtLIZ+MCRM6HPzFTj6EKhPF/fXm
7FGpW3KasnDuaoMHOy4DEV3GJi/Uuy9evevRwpbYJioIqdSITxnrI2bpJtyFbPn0PHVoLnRZ5LT+
KhZ7nX6TU+ho15WwDibC3PB12vR/XBO/5IqPcLPBqOYxqC3rr1jFdLHRyeSy0m616VkFz5jUxQvx
R1GGfq7hwm1jbom4uKbZddfItrcrRyeFH3c6KMRlIkHNfGHwIS3EOjexLjSngQK+7omdigDD51Qb
w7BGxb5VamqGbOQxlvidcKSpmrV27Mjyt3E/zvt+PJ5ve5g+AigydF84hvGya9mWjB5Wlce8PVfg
X6AvbwVm9czPHE+1/rK5KASXPcxtHH0XdiDVu4D2SUmtDpD8Itg0v05e0z4jnySbRWh8abjJvXtc
HDApYECHfnNenIxHTPP1YcXzuShLg+YVPi/jF00H+a7x3kb21OaCDcTd9vzVvDCatlRsLBFVsUbi
dwX8lRIIOlgeDAd3+W0WcuTz0B8I6JwZoJu+xcFfvVkeizoGmp0SandyDs8rnFnMt2zdIXqTfkpR
Cv6UejBNDUSpe8nYimp249dyDsockKYWpT/7O6N6k1TUDlIYc4mLufxPFUQIVMO2LdniBGPAb6U8
uXuTXR6wrfw2WiP/NQXzPqZHdjaa8nSf4ls8Hn81zvUZ5X22ivKeUDYfzAqtEQ4hn1ceznsZcP5/
djswWsw9vIXUOIgOUzGxd/VehBd88GE81GNlGXDDHXcA3mY+SKGoRPzscJdWcqsJMtWIc7/VOOcv
DCyvZLnZy8ZfuR4KI1KZmEUYSf8FXFS5UZjv21Q/b9Ef8ldAW6NGJJbduRb2/MLc4JcoPXd05WjD
KT9187rIrLBs6Agoy3wu9xnriI6OK2NemRg8eo/slpm/6Nn3bO6fMl6nUp//NtO4+Oj5CogZZnGs
ip2Bs7xMvO5wM451HduVOpEUe+5bl5WU9ZwRogHHi7FBKRi8w7Zo6+PuW/fqci/O/dWkKBuy4cLh
uT5/grecuv1bxPZFwcc3elM+qsvYZlxJXXIwpA4oyRljrSBM+SWU64FuDIgXubPE8KFov5TixQWb
ay/QVqncyM7TMC5Uh2JLHjjGgvuzZazxTLAppK2gp8UV1Ok4feSMEziZOOsuQTov5Dv0+YIejllY
VC9eeGtBzQvoOgUdwlO3oUUQvSr2PRqDr3lM+CBpk2kUCHsJIQcRrmaf4o5iybsVfldXyx/ptkYm
01UoYXs7lrmPwrBp75mVigF5P4HgLFWzaI4yzBY+ImtqqdEIvKbs1pq1dvC06lYkt2RDzirRm1qC
H/yZVNm5/CJxlqlYW/22NSlOhxiyKK9ogseZ9XDn0XEgDQJV1CpxVAuYYLUQZ2mSJFmRO4eedcuX
neeunBPzSwNeSu1pM6dtw9HtcY8d6qdzWCvqpkPPBkMKd4Zl4OIrVpDMDYduv5y0IQ5r8jrzJzMQ
GmOuc0wIhlJumBiGG3Fsz+OD1+hyzIvSYBgOuFdvHF1LQH3TVwYc4UTQDXDcqwY8pmf+AizwIhyr
6Smkt220NNbtMPkCcrp1Iy6goAWpVR8jQcRNvSakci6Jf5efE4ZU36uulSwX1Gubiawdg/UOQaIn
JYMykL4QEKNui2zdwGAGupH5akYrNyf7l+kb4VwcA/mCTR6lsiFWQBPj2vhKE66pld+VELe/aBYf
drWBgkFBqqQ3cRXKPJOOMp8jEQocO6vOCNlG8sCw2jbGzyDg7XUWs2imDEEztIUfjnyymOXLzelO
WLwf7Vo9BC1kTmx2kqyteb+fBk4Ln23N4k7OzmnbuaPqI/Mv5JBUmgYpGP2b3Pfnrt/s8GXxFYAa
tmEHNaY99e40uvAiPEzUIbbv9DaeJPOmO8bT62HUJlu/PlvA986ZCkEiOgcyxxo0cxwWXDB8kN44
MGkyMzzmwM1qI30MmycGtVSMNFtmq8xZ3TDoZ9+i957T6Eb1gou4P2Urbw+Ow/vlNBmi0a8e21PN
JtW3/B/qYHHrBgpb3JhnhM29p98NGI5Vy5mQtmosQd+GOJTdO9ssVTnlUDltDu2I0040OZDPvPZ4
URxRg8SGxkxKZiyCWPAcTnADllWHJ/wPMNJ0q0WcfB18wE53arAFgiT4MLpEt3RCz4RHwuguFU6U
1lYDiKK0uljYgzLSpLXaaXrWOqcrECiSmLtl/3cNknW/J/DEfwPn+TENsni1jtAsuYAGR0b0+ifA
2ol6CkEtz3EOo7l4pFf98tqBB281v81tLFlvkynonUKu5CuW+UwfaA/J/zRy3m458eijemBB0xj/
OBho7QA09NKT5gWyaP7gw6PuTvYvaxqNOLKjFA/kfjiaqtw9iadIZcrK9PgF8Mq5My77YFgSmZ3p
TlMZYDH+ZQYV1mfnxINWxqdsaM1sjaHZM6l2PNVt5iWcDVpYLLIxkp/WbANdrZpJNj6YoIMmyngu
ALp/5jYl6ZTFaSwudeHLqnze9xiOqqvQWZKUs1KbJBl1nkfrdUyBwmvPjrA2RxexUCuVvTgJh1mC
KJGmMp2F9SW+POkiY64+KPQ0zxtx152a8cud7Dx5fiMkc4bax1wzVP3ItCZmqi6QTyC1MS40UPfK
Itc2R82zSrypPKSyUtH59nKeFRBBayYcLfUrVAsl8OJhyNTZEPzK3S1nDtKvTyfeV4vWQY1JHW1I
CcipO6YzBIKhGsxIeUkS42U9uYYBnS0fpQsY+NM8K4u0oBPgrk2kKWiZE81bkHjYRHIN3Ait//mY
8Lfz0fIPwAcClOyP0WlRJCR0R3Pfo8m5JAVW+pZtmYuaDz08ntIVry4Eh+8e/ORVjKUQLe5MOjXa
MD6cXDcjJnm3zfOr+m2hhr93NLuUz6R1q2hAWuvI663939Gn7nIlSBOGZebcKMSYpr1gDFvTLbQg
BrR+97FPMi/ScE00xVpuS3EMNg6Qx0tm/0fOCPQr52tHvqQ+EdCoPlMFeqHXe5PJ2zVlDboD5ply
hCg5GrnVfqwGgM+motP3QlPpPODbg+lHJGpcAvszD2cgpceiLnzkQsAq2KNY14/Ej8gbD4VdxK1J
sTnvNUM7GFm0uHNkKiJ3EwTRSbDgNKCZIZAyFbuTX+zXsiuZ6aXnfhJZn885Q9K2Gq9HBLBzlRdt
R8lSt+MnzPxSqXE+hkRmQZLEcBkg8BWjvwKkmXjXeshOVNQUVuj23uMfimNLydzZBY7GfQV08BbO
ORkor4fOUnH4+7BpUPV2dsfmbi3fQr6PRwlZvcOk3sBfSpo1+0SLgEUjlj0CNnwgkp6IlKKHmbso
QthJ0Z2Lg+scFCoSQ8ARdC8ko0ZZSns7/X/JVtrjCDRlZoyn5LRf0Y7eQPa28V4IyLlOyDi+W9zQ
6OFIqrlOUj/mLHYHc6Wg2c2xfgFUrLdjyCc4An+Ot+HgkJp/qhA9xUFxiexfmcwr1B44YSFPj4pi
TjkA4VV+oENNUBU5UQZPhAGX4oidt23t2MNP6WD7qbgm9GKA0BvAO1NBNUP1wXLq+HyKnwY4gMIO
f2zzAbQcxFJdaPSjqed5o/crou3+9sY5WmlxipjxHGfzasQtVufN+C/HDN/3rSEaHLNFAqt8XK7F
BvTtWauz7cKh9uHjaIjLqpfqcMrvstkyWh8PnIFOZ6RKS2hIpAtMViBp4udmnAUb+CzD4Lxv2c0d
NIzT32ak0hH2Y3JFZmNbfFBanR8p5zIAnnkEe50sNdn5ctploqj+jm4nz0l6UKcQLftCY3ope3l/
D0OlnRCKxBlzgdDl4KAxvJLzh2pmz0teP7LZifVhDHESWCoiST+OMEoDITZvhMXrdJjYOycuwjqq
RnQPExlDLUyP3ddUyADddRKfcJ07OWNjtGDKTXvEwxzFjGxYLBQLF2mON7H9kr13kuCMXwCF8o74
+zHOdZFKzDDHvc/AWznTrL6NhI87pC0GP4/IB1KVIjS1yWEIpW+/CMYpFdjDUfjmew08OaMaBGgV
IvCVFVsV9YyAwvWyWjjDoGei48YBWm14q5QADXg80N9TPkW+kys3Njxp3zqjwqxlA7avhseRFfVX
4/3CsAxsoil3icHZtVGG7EOusczo8GgFbJHuGmf4Fvq/TyZ0b1Gx911+uJSQT9FVouhdHY+eDncL
uWkiBpr6vE6szxLvGPad3NG2xfXSF+xPmbjBsOXH+dciN3oqf2qdQflKD0uKh9wN4+2ILUlsAHLQ
SijuHF6N2gyP5Yy28nNFUhlCZPjeEi5hC3CQWBAMXTHvqH3pV9voKflA/rxPmlrDVM17q8bVfy6l
kF9ezcfUQW77Nk7p4qhMoCkzkhMn8t090Z3IPpbp5VWkt4W+oFbRMp/QCe/9ee9BTedNehf/j83/
IgGYjIsV7c5HYs4gjMdgF2CoTYy1fVs7VpVioCRhYFIiGhnkbiiFriufbBYRaHosU7sCcTYCmiKy
Vf5Yn9F8tbbsGHGegoL3tX+CPXeFUBdIi9Otg/foQ0jJV3SjlSEpWeGwRMlc1AAlHRfBeGzXo67Y
0+Ct0EjbehMnYi9qPwH6NkJ86D0D7UCJMocfdHldXExHWCNg1NJzZxfYkwl81ijmXn4bzI8WcPr/
AOgiZ80IwQyfBAXs1OPbn0JxSwi+YFY7FHHBRKhdyN0qt4mP2SuKWbTuVtNV8NNXYkpZC4SBdbyh
VovZgu/zbg2N3XifcVPBVoqf3EbxxagDfn92rF9KE+ADgEz97XsWt3+crR0yST+v0umURQra9Ddp
4Rv2nZZzFl1IPm9rZw/4dNkaKucN+uBTGmNzSbYLLuCR6EVm2eXYvJhVbwblOHntIWFyjYQAGrG0
aW3UP4EVcw4OTzxNCbPjsH6OyK1Nzy9NRFA7fx+xEuL/3tBJtA5at7wdfYRaMNt6Iyg2IZXxMpR8
l+VIMR7LhODBYwRx2ue0fPhuogEtJKCcSZHmTxu3EyGZFLih3qnsaGEynjQ04PfLXBihbm5GwIV2
e4O8LMzLJeYYmhm3/esRM9y0Y6yHgMzQSohl0SrO1e5buV5Kji4xo1jb83p38BTTyMagmxs6wcrG
vuh8YjdZXF9yLIurIhTzeqrL/owljJD/pkoilx7qZbkzTzjlcI/+lOfVkCWZSvwBaMiq7VpwEt7d
xm7ifp3pE1a8VtmUni+kbuC2dnuexQVTnapgrU5IP/rlelv7eEk8O/iNSHIMx7WxLi6luD2vRMA6
n9FX8hc1PV4kqJZIC4tv54XSr3tuTNVfrNDXddzfXf7AqpRqvztqyRTh2vHeX37/3b6Vg7KqTQ7O
PQ8r+YqUN+O2rWr8v5aSJkzzr1EDQEvyFAXK6YnGq0iVCa0OSd9xRwsfueDD7C8/7cU0rqc0Fq/j
wF32bCNc3Z62DyOjwZBEy+RgNQY2+ZdA6fGV1BnTfClhfUn9So7/uojVj3mDrQZwM42Q2Cd0ft4s
ZBaPWWJjWD/YFaO5kNd8/Nlz1zK+DV1mM0vqhuLxUBuZSmlF91DA2MVFYfRySjZS4gouI0kZSxRq
0l7WB5PywXbz0zhOsWBsi6yUtdZXBbhi9GBMveyFiSzbKf0vO80aZJ3oB7sHBwJtjfJ7mKO10L8r
se2HKWb7cz3Oa2jJBYF2QIUWOvCK6mecrH9hEa0Vr1m8n3t9WHLBZ/oRXtJl49SnqxDSpGYHr8Wb
90o8XlLlZgUpIc8SdqgflOFxdjNa78LWiFaT+CD3enRNSW6oRMTzGpHATKIEBFk+c3Qtg9Ozkk8d
2dBjFb3i3aZE37lTH8eUqMh3QWWrNezsi0VuQ+ZWPBB96Y0JDGTnigeBoJ9HbZL0n55Trm5mNZYx
WQyV3APNyR+4dxrP1se4lCt3TfuGHEbmF0XHVYRrrI+8zM5YcMFV2mEuRvPx1PdXn+ARKQoCK/8L
4j3WLCjWlM8QZ+eShLKZG0aESXpy7BdcJJOBB7wzU65vWQ00iCJnf8/a0UrKpUskxYL/2T6eSz1T
nVH+HeqaR2YRun0FCJ0YZn7HoxLpbE/hekUZRq4Sq2xBCV+gY+37bZKRrrgizaGmRlSpCKXV5WKv
z5qtDYwKUnLfffRC74jap0OC6dEKMNYV1QeQ7vP128cCm3dAGdwF2rSJh0MbaRPIUM8j01KguTtY
tdAJ7KnJYVfep5AskW1uNbPiDXGaTDaIDxasikaDka3SWGrbmTSZELAnbuvVCJV/mSJWd0oqFqon
+Z5YU9nKxloZO9DDt7bfvhtz3DqMM4O9Ew0xyRNIebd8BOhm+rt7/MCuB8rPmNv97v/Sb6sPu4vw
A7jdyxqh8lprR5zQSlYlYRPYMdZrqowhkxkgAA1C2iSzxMrGGAfUgkHJYEwLy2TgOTNy9VcSt1e4
owUIdsO3LEwC536GSL1CrhN4oVmQ2N18qQqOEqlJ59k1u93bPR3x61q2r1bU6/cOMiZbXutsTkaf
RT2+LruVrRcIIqrTao0bm4sjXmFW3YXMQbh3QKgbwqnypniE3GEKGMF9PJ7UJNfOPmIgoqCTxJAr
Ckdi1de5f//gXg14KzOzHFdr4GIsB9XU/EGcWgfNJ/Lid6uj/A/xU/zpbjLkaqtkTW1i3R4jPFGU
K7I72NfojP5BvovZuLamJZmf83dXsupBPe2sDh19S0NvmmO+DECiYd5BFp+qiVY+yv5/Mf2Tj5NJ
XFj1fQLt/DBOEqtvgfzrFwWelZ0yf4c5LZXGxXxHEclKL8EOIZ5P3Eyj97QXSIHl6eGyd42Mv3hZ
51fqA/iilPwPguYrvJW0200F2AsbHxiCThbmXeBgVZQGlC8zKsEMIko5YzxoRJcKkYnTpj9HDjFj
i5rHpKqSlFovrJa3gF3ZSf8YQlN4wAXB8bS+imTsyZ1U5B5DKXN7kVUP8fZw1sJlQ+uMsEEwTT7R
1sTdMs8/OcmGngjWgr1+Y9ztcFtzUqlPFCCA3vX1DIT0vnupWtXSwy5l7daVbX31aG7aUYkJaExB
+2EI7WJGqRoC7Gvr2YfEouOvcAKNsoS8Git9uBs6l77a0sDU9AdOqIjMGUHVIkENYVLe46q2awvg
A3Ky3h1n6mhpFkjpIDfFA0ok3js8ca+5vjz0CZYgcEVguxvOmmHEHGCxBy7HoR+3wAG1GcmXTEiR
t3sO/nsVWew+389B5rOcGYW+9slc2b3vitcmZ9NNoJCvUi53oGAz8P9ANBq/yb1ZBA4bHs4q3sgy
CIHbxkxVn3WJsqvZJTv2oDqRlsvLf1KTel1LvVkZa1vCI4B455phv1UN4PkD49Jd1aOovS0n02T7
8lPFPcJ7y40FxX83diJ96tehncgwdti+VHdd6H2o26FwSzjtlBICZ3Qi8ykdFFVDzo1AW4yQyN61
Zy6X+d+A60nCpMsY8v7etmKC0DQs6W+F82tRfElOBzY0ChJxZ8q3Cf2JvJLdAJQ9pPSs9VnVsNd4
NXqtFrYDTPaAZBOCzH+9/VH/LVfzONJXOpiUioxqbAtZi5N6PfNIhxJ33tDUm3GSP30w7ZP/484u
i+b+kP2S5YjV6yk6pMmiUKajcrSFgwMwaBq4uJi0vsDOV9sTItUSMi1nteBYJaP4xYWPzc7Q5aBq
dkB6BnLvocqE/OaGPaxp6hnTng0i5d31kQMS3DVdmpmuWRO5PChqIMRbLjFmvEQZeiQtcCPDZS1+
GcOO1gN6HvGGxDlClY8pNUtln9AMpXVi/0xJGbkyJKhZSPtRhj4jJ+9G5U38h+MgMRdxoGjZwW2B
mwNwULl0cTOPzP+d4ftiAddbK2DheXKa6b0VVu2Rxuf7+cIjHLNDOtkRbvHZzRAJaYvoGf9aDKsS
T+9jW5M0WHGxVsNVUKfVtSjR+FagYMuGeJyFLegvFhgePwt3fv/OcI8KrLrLMZWGk1Cj69amgZiu
O7e1FnedrlxnOaV3ZtFOaW+3wpERIkaj2gWrJzHZiLU/ec7M7EmPqPNsuGE7es1E6zcZMyLyTozf
/1xaEk+12TTpsjzeplCMzNhUPQExdLITv4QDHxeaKNVaw3LNd+QV+lpRmwRMXOGPk8vb3w99hIf2
WJFNbz/qW6Q9PTv+FLnpO7VwLbjICKR3d3QLqpQ0QRqEkmyko+KR6Zqxpo9oV1ZcNSNCFh8wmAr7
+okkUVE2hl3lXf5AH5MLM5ndSHOdT+iI8qnTEjLV+OJofH3yyzpsRSURo24KFfwHzAOsIW7h1tmM
TMdRFKyH4vbiNTAkLIlFX/utPXNIop6ubtDxx+a0LFfmk/Q/TvDqtpqZHuc3rpRYAF33mgNi4AU3
md24dHUG7ECh5LPqdlHhPxXWzz1iOgfSt7/1Xuc5/Xfq9gb8ZpIriB2jaUxbSw9kduP8nZ0UjluG
jUnSMR1P0D0LV3o9VJgUqotn3VQAGs2n2FtJ4QYU6p7iO8pkWS1zDjM/sSycQErTYY34PLAZA6S3
CLfVS98a9IeQJNJkRBPieoR8MBxg+DgEDsN8cr66n8NFbcshEUwjkGUXH29P3xxQIMiK+1PNFC7c
ykdf2KE2swZoBILUE01G8bC69ZEoptvjkT07+joc0kUfVPhAcW4oQY9+7t7AzupfLNSQW0yZcqC2
xsUdBGggU2wflzTzi/GTivdBGooA/Z5S1uVJyl3SG4V7OHzvh9hcXWotHcFFb374YGZhTpgcllDH
mEANqXAlbCdEAslMVJRF/9pYdISLpADLprOK3wfAvwQYLJPmbOAAZOFESS2IlaQHRL2Bw5jmQfm1
D1TlICpWX669RAMUqpz9/plZhq3hDHvNUXTz0+lpPO1mFsloerxh2dTKn5pnsPf6CEm6sR7Uqk4u
TOH5xWD+0iNl/NxrJumGMAO5/ovu17Cdf2MqJcbgNUIN0dtsaYc9mg9dmrhf4BoqFuJNf4dOYRBp
p0tBdqeZMzSYcDCQ1kJ884+JBXLZrZ2m1f3z/YQYhfl8M4wK1djUqYYRzQN8bOTIjCll1LHDLAzN
vSgRWsufW8obC9AHk01sRD0WxkyFX/ZQq9FE66PoJ5s92pHoY2pAR9JDVEDe005hAaHQ/LHCYPsq
5IbhvAUqFdzEj05STTJtwIw0+CSV7+xaMktAeXCYaLYOTiQb4TU0O64cBZrs5QHWP2TANknytIlt
3BKIwVYe1A19EXzuliXtQcgu+xwtmtGbLry7o3VXqtD9JXZ2fWrJxmt6bGaWz5WltU+opa+oYUbV
mCclg6/wu8VvvnSniPuYsE/snKdxUZdr7lA51afns4BfTU1GpXiWeugxVRNAyXZkeSoJcUohGQ41
jPFuC3C92tO7t7zI/LFg4EUJJvyKGA3e6GG+N2l30spf0Q2T9nxBhnZ3lQ/zrP76rLPiTfRx+0It
R4vYq6kBKKLKth2DC8B0h75bwObjszBAHkXLl96iLxLBwtQ8GZ+1/IBeseT7CuOoUB0v0LI1KfyJ
4eeCQLRBn5aZxkygl6VXPuYtmbn1obq94VwEOeuzgVV4P7wYwNdMWCHL//d31dXDcIsQ/rOY5MOH
Hpi/sTr5VY0f+Aq4vUjnRBaX/139HRfvnwTKkpqpDGRO+RaO/J2+S0S9RnCiGvXnmfP7LXcqjMM3
Svihl14VCsafd+yVhBGon77oeTw9m08RFjZ/E0bdx288Agk2ZzMWSZAijupuq7EViYRbT6lGZkk/
6hOpKYd3ucZqeNKCGBAehRoWnyYskSSmqVa7H2vC5M/W0LihrgChVdznZULIFbaA0OyBsxYbyhxP
ddTIu2SHY+IAVrnfLCl4AuQC0daP+/TSNTF/YcCqL+5TexrhHnzPwBOyJnUzap8wJeGCo1g5sImO
S1yKWPHnrUgIvRVxsxfacAEZhS36lAtbbfTBxfxg8t3gHI8IIZCPL2WhaHKi4HMog0qXNZJujDMR
MNX46l+lF0X2CvxBVrcJ8T8lqISuLEQTJ8S99X46qP/x/MaixDxuH9PNuwfQUicWjh5IW2g3ZMtt
AHpoh1T9yu2CPAwVFnUyGOkC/D4TzNkUrHWZMpJijBDnssFFpozlHS5NIz4HIIog2zcAz6FtoyqZ
JYrTkBMeNIbLdRv9Q0IkxUo8bpRij04onpNNzbUrtlKjYZS5uSAxHN1tf8v4Zc3/autM/o0oqVRb
D3sF69M7P9WDN9XbCWV1tXO18uFU8aetqW8ue5e8xBQQWEUVO55CN34oHRUkaZRgG+WKHj8iiV6l
u0QDbwe9O3lm2HgTIyS1B72CNG+iUEfYK+pkD+21yFwy68JbvmBA+QosFMjdlrEURR/zjkT5IMaM
5jvqZHMJhddbySvHOJy74/1/NXq8vZBtgKT5trkjIxVEdPbTKJBbrrsT0bIRss5qKJmNGiF2zswc
ppn7JvQEqsPCuRZp4vEl7ujfYFWoxn6s47fEek65B4SThNLdmqO9FQS+kirKvgS79v2VY2RumQIO
oOlyFLl7MPRJi/2f+zczM9wvu6L6sJC/TxMTBsygnilWcZmZiCROp1AJn2Ajpccpdb+Utsf5RYQ4
kP231S7KUdYxJ39fPOWoK18i5CAR3/9ty2duF6bIj0L80DT/kiS/WKNSlcY4RKv6FMdvHWsDxVXh
G3U1BtOiJxCpgX8mKIZK+sX30yS385jue65hr7EOe+KUmZxvtq3btSL3MO9Ph+Qe5Ku9czYm9QDh
I7Ns+ve2vcrYU8V+y/cp0NmhH4jIJQPzv7NU57AkOf2BR7eMkeo6nqLodBLcpOgc53QSUtdsFbeu
q/WjzKsGt8SbSJZpMeBbINgua4Ha49ACXkIwE2xwyWxTQWl+XjgEpEJ6E2cY+YF/FQ9a5sZGiOxz
jgZV3A8TjEXfwLUouC2vMCz5QKfuJl18b8KjEA7Zx7puPg0fjI8PdA2zwavgSfUMGfyqn8rpZaa2
RJjPPg4Zw8KSeAqIcr4MGfE29GpXuqWVZuGEKalrSQmbXOyWfP3jyOQcUjOeYYeExdl/1pmdIohC
RQcxgvVRZ7+K4eGtpF9aFrWjwPA2Pr7eGfQAAl7Hj1e3nojXvFlSsH2KDLSG1/ZjeNzvD7ujHcNY
S1uWdTCwexZAvD94pYLQHmXJJ/2RrPIsbN64BA3N4qqzLfOMqwZKNP8a+Kdy53bi8bJSkPcNn37y
F9Rs1VAkyBpdDMce+F+M/8yIQcSXU7dhiwYNP0LIQfRW8nk1SViEl2cdJ43xDhrz69BxZOtw0bt3
MO0wC+NiXOm7/B9ucM/NftNEKscbF511P1bCe1e2vDe+FA/e+HW/jMGeFcfCpedgQ6+WSvdEaRFO
uU+VjU1xg6bk+1sctcBuqVi2itELwje5eDkB3fvn0l96ygUeoV1xnpsayoouqpPpSz0rI6qdP6sG
ZSVt5g3JEBfg/JrKdTuKekLu5SeN9A3EMsfTfEW8W7a1yvZvJGd7n43MAX1WmyGrooYyDc6lJmfK
b212dNcEh0tv3CqarZdtlJaxKarymSAAqCM/igcDOzsii0fkcrYYJgynkyYT4vas3sMQvwVcywhl
jFclZLwf5XOvvmRT7N0zcgR+3jMp12H5rhhrtMoN8UHGp3D2UKgOZCZOVgmopIWhFzxHn8wizJYW
uxc3GReRsOZShxC0ifuAfGkhvPCUeMMvOOF6Z+WblkMxsQof136TNN2PROM9lUk2mC0OVp/QrT03
Lu0K+JdUSdFk549uGFKwvnQWGDlxpF18SalHYeWA1g4oR96vRBuzagrdqLySUFZQgwcTTg/gLYdQ
3Y1qdrWoXWbivWuHcwJQk41eH4HD+L3c2hywvFKwPgkAaFdb+3cqGZ2Vv7RFWK9OHjXt3U96JpWw
UvQHzwWxGifIr0AbEV3Wlr1pObqm1qiq/mN/z2MQ9V7tmNRPbdeBjNjXX70uzHpF/Xe8N3zqctME
eu0E5vpMkWstDGgiDiCGNoYmuogb9viYZeaPBn50h7tAUS8d6WZf3EO9A/dVv0pU4IkdWysFiCSb
Q9OAYr9C8Ct12T9/+s5K9XsH/UXD5P7neREhc9dZ+MgqKIBat5+rc9SzgZV7KvJnnKw3h0mZlJ9T
WHsZk7Ehyex9pgtaNAMi25wSxnO96hQLurjEdS8tc0G39N4pIiOOkWc/Wc+MacyryGw4m5ULsrQd
ZKeTJ/gUXQwzY8uvxx7uOCKNPNgfhhl+3xd80/DmuqhWdT0GWim7iEx9CiiuO359WfIOyBFIuqhu
BpXGLbsURlPo8liIeuqhoZWt0MpTyTHEWQoPN/LzTREQBMRg/Z7Y24iCYPpHiHO/XdHV+X/QjPWa
yUjwnr0vuYs5RH2eOE1kOlqkj1CyWjHoV7beuC5yEdBUrBZbICaPQZZ5yRrDgwjPbrHbH/H1nqhz
lQk8GnQaSBt8EeXlnhkKQA0EJ29qHXA2JHEHjUa6W4yYTYnGh26XEknvV41u3VEy96VNKb/VfxJO
sUwsfbpMP944yTK7A2KuORj1E69ctRHvigjTJ05Gy2I1lW5B97VRshY0qbslqnW0Gx2YDaZj7JYM
uz+XBD+d5FjmQxqRAh8AbqPujfgRwxPocyorbVGq5XBEzJ40M6q6N11Z6dm78M619mkj6FVWmKDC
WX9UCRahIxc1+KvoOnyBIUmTNyGE3EmMU8srUqVyKU5pk7zVO9vSSCvpKoJogkJUfw4ivVKAIq7t
7kA33iuLtSPWUa3P5aLqApUAa0thHFU2mPf1L4MX/Sr1WWPRULRUCgybvpWZpm3+eIVlQfzs/4Ly
AkoGs8IaorJMqrAZDIEMKRRaceeJ8LUTAP+uhT19ZSGpZO//ES6gvX2PMDEuva5c6HnPuMF2hX0q
75enlaVH0OxnYxuOs7eohRZ6qkvJB6opu9RHUFkcNV46ZhcEWzF+croJaeiM1IaGhDTS603HJnj7
vALtR1o352bFlNg8f0LJ4IwbPg4hchd6OiI8V26zL8A+qpUFzB5dQ3EOZv76GFr0z32YS9VwUFdR
2cGAPSS2F8pgBt9+rQqZCU1hbXZq8n/98D6U1smFAiThjyyF59V1D9Jum976Z8p3JToqYH+e4Ka2
CZar4suFmb1ttPGsAoZUe4CTFbsXj669yyNnnTnTU5bkeGYNJzSAQCKCB6lt5ndHqLFlQN12MtEy
xhZhEpkOs9VToyo6qGFtf2T8ZBWUiwjeFu1QSEE7uQ8eosqcAaDbdy1Zdond3a+8wLewNgiqu7JR
EJodUmTbMXCQN1LJRpBgh5ErIl9UtLT14g8n7PyQSZ29PHWC4aBLVozGVBIXz7Ro90TRrBDfhNAr
zUtiIqyVTcauFedRjmzkXTPJal33EHt12bpm0939oAgObW4dViKUu9Ngpx+MNQnLg0J2hUF30FIi
99JeWK3FfwNjrdMwHakn1/j++AG5Ajte1iEyTBpQr43cSBcfIVFfz4Dd0gLl656ma50tMd6XrpfW
HkCTRaRzcjzoiGSWgjY5UGwTiUldNn6YiulYWfsn4BbFcz3X4kEykD8RYMa3Nk6zih9WZBUKBMQK
IsViT9Uj5LpQPByQ8Qj3S4dxTiIoLvScm/Ue5Y5dooEFYzDdEpdHbVr/02pqhQxP6jlVkbF02q3b
BOIngPAPAmmSHE0kIE+UoEHzF9O3fJkQpjrj8BZ0DtzvM4bpbbkPSaQBtw8SEsAwGVnUSGVYh061
gvyOvPhjanab1p00bj1SslwszgsddVVfa9sioT87A4agUXrsng2ucUQssp5pdoPGDowwztnJc6EP
EQnLHrH+8WCo4lXfx/o2hnsiyZFy4Asha0Hf/qFcJ6zmehRSJa3hS9BQQp1/q/qVoQpmFUjsXsam
BmVfL2sCrl/3if6jLB935H9C6eQvgNZYM4ZgijoMAcZsuMmI5GK9ly3Nrj/Qe72NzIIsafTEwP9L
V1KW49Vt6SW5UotMork6Lni0cckLDDyYBnh20Lv9XDqauUQCGXdFH1QPUSkVT6Vl9D21uHUJ2GwD
rdQQCMAvzx6k9WDlTKkmpXtT9rALqEzjDqrS7nolsV1Q/xwGuvn6gMCRzKuWy25sbAQRV6rSzYFd
o6S11bHtdP3S5kAtHyRcx1SFnTJI+8dnxyIX2GmeJiXiSUVc+3LnvuOK8tAFawrLL8awTtiusRTl
CJknkyW5RGWWM899vAz3xVJt2PnHrdh9SV6aVxOjvaeR63MCFjBDbT2pMwY1QV8rGKNCgYyd1r9/
nF8ppIBoeGpycj2AH2PlqkNe5hp2giPkVKp+hAwaRKx6OO1ZCFUXbvGGqwKQffbES7jSQTXRVDgJ
66gyH8ov053tIC0ejZlhs60i3nSnwKHJhoX86FzrYuL10CHq52T6OKNYqLD8ICDtxVtOYk9QDUlL
uqpWJDxJtmQ9YL42ESXFj6fBcsExte5qAhEFDaUOWfq/oa2pEhI7MZjUwnM1ahFoY0FaIppi/6qi
Ox3kUtHPrqrn3e1717W7+qC6Y2j/Qouqb0blR/vC1/o3pxp9UuFQ4c4iSleqJyR4hszv0KuQMR0v
e03iPDuQfZV3wELik7GsRwsXpPrfWERYlghrkWonxkBIURBimpzeVyu0c+J/1WQDOl92yc1xDkR0
qznOlWLLPSDtMyokM3qZg8pI4EvbB19fCf+wH8EmkufPaFZsX9Ja6lpSTddKdckS+XgUwuZp+N9L
qzJcIrJmZB4E8cPJMUeA2/1YkoFV6vy6e+BiNodYEJZFNUm9xOyYXOnRPPwmPhPHj0dZYvVJ/vFm
Qt/I6ReUVOjUzCVDt1CfrNcIcsEg8IEuXu24zzJaQ/qgxTEvpjf0nQu5kPfpL3b310rnTqV+zYIj
VbSxTDCeTiYb9/LYBAz3udS2F0og9xaFi8mGIVwAGX2PKuOiMt9ZuOCaCn/EPB0BoP5m7sSDGtyK
UtXOJ+SK+lf3Ym32ks/RUZCTcvrLhgCTLCQ5pmRkwU1nK4+jNN5+RQRxNQGiI9JDkHW1A971d+c4
qaD8Ibh1tQdUZFqKt4/fsb20hIQKXPxyO0KYTubCSy2W9qbQY/1xsou8ogCSxnorUwpkQBAibcNg
ePfHOyR5Kl3+dN73Yu7IzK8OeDlbaC/gpnKC7B2s+O6BCqKsqGjlF9GniNE+MJFRTE88HfV237sW
o1c6WQ6HKXpRgbI98pk0NsAdi1SfhUO6OuB7uLv58+1TNmm+5rcwVFle2P8rf2+mfS9xW8hNOmRs
L5XcUdeUWCBei91rOF+aSJd161gCJCnzyHMip7KQtR8VydmcSfx/ZgcHXeV6eTDvUNYHzSJpPPZd
W/kC8kTrdbsolf4ZajVsGDtLRng8T/lsK5JZ/6ltyFzuki8kCbbbukBCeSuyLgaDMFyDCDxXY52D
amVtDufwH/ifbbtTOcj/uhT6FECRMSopZpIsrO3QisoLPwGusr6NLKqodCZbZXcq2bH8cXeSWAQ2
8fA6SakC3l0pnBvqA62lHd7O9m+wrQ3v5o9WY6fgOJRxEEjPIHcwl/wyjzQxmtx7CQNYGcpn9FSH
qgXNekl2Ig6/WUyZiz464TVPMWj4zExoH+8qQ2Zxbnef6pN8r9iWS9Y4Skje5jv0DBjg0WBrTtvz
yidO7VIP+c39oOyb/V5rHuNPndgVHr8woB5Mi3xU4gkoyXfRwjjQxrWdVDBfxGBcuiumiZ5P85cI
Ul8GXxMRQldjXkjD7fwgdUVB5TE0OtcHfVvt1wbFM7fslUKjNZbVxsQQXLfDF9dx5FaVPCthw+vq
AEjv+MT1NPEZmCydjXuqFXZjxht/b8fKTUS+5DVKCM6ed5AtAKnwUNkRbNybpTYta7A2SGDu/B6J
RhLMJ0pcbKud5b4ezqUarlEE/eOmn7lfXmXVipQWZgD/Ag8DwSSyZEPPLZqIEGUKROVvCdrKi8+6
vhWDrk+cawY8sQ+uAQL2TeBHfcIyqQf+o2yuRQldN1XC01TB9gYQ2P8feKIZ/OgahQnnvSEhuO1m
W9e1hOcZBDfNG+hIr+ae0kzcoa2erR1XjLvevX9+Cj6Mf23+6nC52tP1kpbz/02VZ4moBCTwcXBT
h05rv+rk55Hai2oAywzM2XV6iHJt1mgtjyUaLGMiGyKDTVXVFvywNPAiUyPPTH1qHR4NFGxWYgTp
97Y0aQSJSvYc0TEjmT24Gf5izUbY8QuLMT5WwuQupBekbwE53NbAx2dJl+qC6xs5QQGBLHI1HMJT
bDYR8yMTfq01eqhgmlvLyh9HcCpIvODjqbBu7fimsMMn5wzkP/WiIZai3h80+q6AbjnBu+4r+AHx
N0DyGV6S1djZlpcOxZW9byUeLcysX2OKQkjK8WjkG3RjfgAk5Y0g6gExdvQEUhgTr/QCCJH2+blo
l1vfDzB4ITs1DQXp4YO63+g2LDu8wedSGvwXDFeAG3CwfZ173p+/TJoyYTSY5bt5ri7q7bwq6zkb
fIJQ9xJtKBXPd3tBlwDTKGVxH6Kysjk7F0PuudXjlTVBpB73Wrmp0oloESCXM5hYmjMRVTCAM1bJ
ebEcfV+nW/OMbuBfG9Gq3Ou8WTRnVsr29O8FoZy12ng++aERmRcrpO0DJNO+uCoSGZHd0wyVhjUB
Ch7jvQT9AZlmuxk7YXFvvxcX5V2Usb/CziAoK4QLiTEwKJdMQwTeYsOSEb6i8K0lDqOAaQHQ/PNe
YklkblNS2+9QkRoClboSEDnfR8egg3aS4x0322Tv//OOjY/K2ZP1n2Fp/468Hpaf2Wd+omEQe3CM
rhR809UNilBngtXyRdsAXpPj5DCVWf0+FWKfXd7JwYSQR6IFEo0x01nVHoW53LWVkC+GYDWfOyr6
pbKdTK0o4gOIo7RpznAGaH+P3Yrgm/PL6/cU0AJYuA9auw18nFbRQuaDipUvcVOeKMZZz8U1IBTC
quevMJvDjYtHcUfSvlr3YZEi6e+E4AIIsuH8j1CjSmdRfp/8SNDB0vmMsiN29Hpb+OshTiPllqYB
nMEVQFb3hi3dPg3L9C6ZpA0JcJmkhh998yd/fJ07R0cPCu0Oov+1urzrUDW9I0Ck5GfQ774JKwUM
EV2ay81W6I+uijv/tU9R0JiRJXjGaHf1s9eu/aA4oFe6QqMiGky1QiH7EHvbmmtLkhOrEXDvTK3j
H4daaS23OJvAF5nQl0f2SONWSMeByW5h2WvGSDzRi05UixsocUezV50uwYLI5H13jQfv4lRPzSsF
tLpnXCUTgFblGoDecwHiNo0O9KjVI/JyW2ixyUiLqjuLjj4qK4GUmSUlJJQcYDJBtvqYEls3J+TV
juGpotoWS/LTB1plyxxUOuXQUxuUqeM3Whr7DuKEoAqgDXOmISBXdiiHvp3eimOer0wms7uXWFuP
F1LlvZmF0AjhkIJ5i/ijWZFxP2BE1U0KlTZ1O6tXhVZkV1bqgjyeYyZg+PyEkNCdANxn+P/U9jFD
QOCc4xmtwSORekhNb7QaOMQcqGbZ2W/Xs64YBKq3LsOoXB+WQmlNAq2ZRDkoHpZm0wN2IKEmPiLP
u26HrRjUxdBXIx5iUdChBDqF8zhRadDfjklIL+lei2YCGM8fb6czFIPgcuMGI/qe7eqwNdEO2Jw3
oZL4ZWxiccqlaaWXLMm/n2xqeHtGV6or+UUsWZ/28DBPn20TegxKi1QPWt+LtnNXxavZXHdxghK2
O+JHbJMeW8Z9tNAPtiwtEF5hQVPcYWQzRLWZ3XTDvpFPH6+2LTeTGrMEyi2ZN/KLIR1N5UE9qdJM
ms+/wO2QpyPwbDeRwCfTuW6e51m+tsmrCgNJI5txfbkADTaCFmsDHxLRr8ug9QxCppkaHEFTMfFI
DdRE5aa4uZIAPZxrKuwrnV7p+XAphxbZgMkNB4JP4yQXyI8O4YYxmLYjEBwB1GQWIY/jiilC6aXu
hlyO3qHpnFFd+WRnQW1h/X1JediCkOzFHD3QSH68jPZXlMzW5g4NJ9OBUTkHE35Dv2Pskl3dDXtF
kEJkWNLNHOtU9uWXWUWA3YpVIc4quFX0UxMwRieYT7EFNQShsTL6Sd83oxLHXIaV0z9y+a7r+id4
r046nf6H0ykEQEgdTrX3DhY1sDv/appZvXwWwJf7g9cXxNqvyFeSPqKCE0wCki0rX4U5I+ZjSmT4
oS59HsorkCM9ENonvGO7Vi1xZwJwoRhVtx+MiUmV3f4iT7QIYCJW2xYP1Es4fNPj842vLQwbZjSp
6V+v+57h9BVZ5QTSt+xzIn5rB1u2VW71m1OmlkaU7kR5P8f0qiZSZ7L0jbkycoi6k/QVL8bIvNvX
PTMQDlFcW0GwldK7En0mOqQVYWswY8vDcfQFYUSqpygwQByMs2ng3EPLkj52z4OXyZLRoLK5Nplu
PVMTEhTJy1MM2KU+J4Jf7Mk7oSJ+1XNxYwbSmR3ptuPhymKiL9bKOgrcGJ71tEW1zyxuMfyWe+Xi
FRVCf+F+EdKHL02+1S1Mo51x8qZ3h6DOqnRiypOD9Q6Xn5h37IEqZE6viZvzfh2YgytuZS4nUN7U
y1IfFMcfUO7PWenPpQLYVKGjEKzElMCHIPQ3xn8LmQMyfW4HuLkSv/YIaI0jr3VsaUfzjzhPkshk
LQZ4S/o2Dc6Ve4lr/CYgCRslMP3fg0rJKoiSxHbBLBp7jpRf9d8h2pX4aYEYo1gpAKjhHynz/PEg
yoB3tgN4P5H9RCbmy8XXuwi5UIp2vlCMiFlan3I73la1do1fM6Rh8Lg1Gz7kRYDauhH8Cbo0eRiw
zMX0h2BPVvrzwKeUMLsyu51kEERqXfr3E7LKkoePr/J5RYnxi0uQxIuu72JoH7ldwTmQrjWYj/wN
tE74ngMJVDNb0fas2sl3NkWns7O0DwEay0mZ25IJYeas8TfHz//4ysbp6ooSu5vhoyfZBPwLK0dU
CntBy7Z0HUwZpL56j/DtgZleeOcuMQwOtCcQr1DuywTqyo19ASAcUNCXKYEL+LIQxxidqSi3x06K
0O383r9kKQSTNcWDzDDK/LyWhHfZo7DPY7bMMkQt9EMlEmPYVqQmLAxW94JTTO9TOZ8PF3rwgrCg
Ay/h34Tpy2D8OEFHS2zFZI9yk8lUOU2+bpyLFAqlVdoJA4T9lgWR7a2UkFZDZ1RkMASmFVBJR9DO
5OTSIbGzVdp4CHZYsEdpZndH9CI+iP2Boxal5NOOhvM/rYNao6dvXbvscEM0gPeCBlsha4LEjNQi
iAm978D26sKK0BckghzoMHv1Q6WV6E/6mrcDmPRKeg8509iAza/71mqffmECTSbCHg4xOBSc7RGX
fZY7W1vvhgvKbBbdcwysX7eYTqUJZkX4SIJplAplN5N6eNwGWq/BEfi950cig4YLcsyPE8rxN3AJ
kW+rZyqXfqgArE8AugDrEhE65gvGDOeH6PkrFWf1Z0oUuixQ0po7CZqwQKLGfLT6O2/27UEijc8j
DiaXkIrHQQzp4QNk6HBFHSf8Pr+NuLmZzzCogG30jG1zsDeynBRx8fAXlDXCjNeJCbvBhrgvaMIT
SFzuE7Eg9jejZrFUyfkmTAGZ6KOQwI7gZKLyQvsTlCXA4p99k3VhYzpSQawMHu4s8ii0DDYZzeiF
cWp9nQZpi32KeMbdiXitLcbOpZOUN+xIkHbvbBfexoUOfGPCaORBEc6C+XkvpM4VR4Jiv48niBVX
2M1tsUsdyoNagsd7BVc6xaRjhl9f2C3DxCIE0B7llxLVlCUF0bCe4Ai6ZGskQaiplAUXN4kWQSUJ
Xo/E+d7ZZbF383RDr+lK5rFjVzwJqJMHP0uy1VviEaf6LZ+tYQrqRtLdJ5LgmkUCLd8TMRl0dOwk
YrzRwm3xZnGiiQYfLOuWEIN6LAP1Ls3pHmmrL6UPkY+x0W0VOFJZQRMVeqQJko3NbDgho6NICDn4
0lathlqRVnNnXSro/oYz+CVF2cNjk3A5ect7ei99RH15Wdj2dzFFlBVuJUCNmODoKZocn4vjsBZz
krDEU0snpdQqai+dOyV295gptKdVD0kO1r5vs4cc57Xu2SgVAg9QoBtE9yexoh3N0xJa0ODmO72v
uXc37kTged/v5y35TMupog5tjRyud9AmONX95GnpS4YzXgN5ttaihJJoOKCGvy3D7XUFhsuWW1YY
EUCMD3jglyV035SQQSBdupjmphdvJRYJCNPu2xI+OlrrP+1jTwYSH+uDf+CMdiGR6WnQQ5dByulC
SOTQrFFjZwhGzm3U2tQfXLSdaeBYipwb1y8W4CGgBHId6sWmVF9Yyx+xVpA9f4m/VmXuJFztnpld
uY9zmU+iJ7dvX3rH+xgyPlENVKywpUFu0FEjAUHCkJl0otKY2pYEjL0OTk0qIzLXKYAuQ2s7fTGm
oWyzu55C2KexuUnZkz7WGqbF8UXVf5X1+EOPQqisikLVc8/2himcKXvSMBRzB46c9xgdW4L2T5mE
qPnYqzN2geR3e0eaDHdXlhDt37MCVsrRK2KpFhlpEwwr6yXSYQu0eyevYPJI38YAdvdKpbfOa7p0
ajdZ9a2GLn3qe1OXV8F2bHfJrHukkW4S54mK57wCtx4WbVAZlbl6HHmo36qxNA5nsnHmSsPEGU2U
3NmzQ5h8A3zBJbnJ5ueSEybdFnjdoLqZf9w8vwtCdSrWNLkNLjEFLEa5+VHr/1yc8j1nmNeJbg7c
s1MKS+oR+k6nbsy7oEguW7X0r3+7QichS1xr+pCSdwoGxempvL4k4pscAla5QAAuguSLI5fkF8ky
swodGCgX2Z5kEtX8OMvdQ4pZAL6Ll5of7KbwNH3LlBYtjqV9/b+/j63bFERI76uU5b+1jEud0T6k
8x1sU9/wbwZkNBr/4uBUEnr4IZWMBsnzQVcVnfqqY3L8X3tin6hBLW545oavcs+7ZEninMhp/tWA
qDomFPQKSEC99ub5oYId9Lnp8TfKPCAIAE8Z0psRKGO+m98K5nHNsgh0/UpoX7/ViX1yOo++a95O
xBFA42BBLx5YclmQeU020KSDoogZLyQa4Ymd8lOdIGUrjU/p7hv5C6ysq+/l0Sd2RY/GhZbNdxlx
70VvlRFGNrtuhslWq8koqsfsieebGT2Ugx6xWCq8l68X++4qRUdXR8v9Lq9K6Hpcb5E02fy7tFAF
PTDYGtBDU6L7qFcMdTlZSUbhlpCuzmw+w9pxzLdrXF1gEQVbb8UW9fHqkSmR5lVw8Sc7l9ltyqN/
r9/RfEzjXZpDGfYe8zyODAlrphakiwa4FIZkNWuJLjbUDWfHdb2xjYORd32xXt/Jhi1wDcaAreKv
nfggyqj7iR+YWylN9/nZlNYGvjyWgqtUZVxV3wSwAYRLYEYrmqwnPIyRxXsON1ATBduYL25grKiZ
GgV7IdljCOi62xY2kL/j7yG9K0OKvJFc7THfILV60oMEJFmjlEWJhueZsMj0ISte0vhjZqEfVCmi
49Fv90l+72ZphT5aq6fLTmf1FjEBlDxwGYHH8aU4+5lIQ4URNqYtwKvs1JLcXRKcZC1LsZwIcgSg
lcO/2rm5rKTxAqkg/zp/qaR7OwQt6K2CriitA+YhSdPBEs9wZl8pjxutCSa2IaeMQR5aRUfHk3GA
3qfoXDxUFr7SdrHSWYCzJXYt4C1Z8WP+dyasIlY3mSrWWJsUDLSjZxr7pJhbMaCrfs6UaYJ1vFMu
gyDJpB/JJEEvZpltydYg6yVCKwWKVFfbQpa4b55zFNevgrFfOipJgqyKDlNdSd20tbvmvagS/KGY
GwsHiNcl6LzRtB/Sy+HjQe0Wzz78umSY5HC+Sa0kCLWXYfBMk7miiBFUp10ItHuRQortAzQdiBgC
3ISzxXNPSaJrlBWpFpe7djnX17G12dKbCxTW7hsm9hx00JIDizmbHioh95F5MgSD7uElHD8j/QqD
H449V2+0Xzwvhzgem1NjEoox4RjZPUrvQtOtAWwKq2iw6ZNo8zAJXVlmOvq8JSogfCEHtcISnZqJ
49n3wva/oW4iJmGX+gtW5sbR8E/BoJ+lQ4lTLljkquZE0PQABM0CHJFwBOmvElxnYjDpov2j1+Ig
DguE1Vk95foV1IN9dSrjmX0Ao0k+BpXdkBZhVZIcV2eRCsBxN1hrlS5v6D75J/zJiV3Npz/QLe90
0P4eEs29jz5niRmOBj15nalc7y38ev+3RNREpS8IgbJU+41ZN1ND2YKSFMQ/3CCK2a1F1Ai3pT7G
tV9Vc6mh+zvEIzHC9UUhDKhNFqnUG3L1s4sZvZOgH47SlYGdvAHgO06AHehzsdrdYbScE394RSF+
Cjnuok55P6RloWiPqUk9Eb5pzEEoXxKntBIxAg+MMW1gL5DaRwp2kV3hoCVdx8QTabon2ukK/T4C
0i2qPaBfP+qEaKbCPWX3WcEIej1uBClD9Xt4LfC/LPvErPv7nIINv5B1xPJyL/HWu921VEK8/WGB
Enoiyc54zYAW6GcKH3yARVf0mW/6qu6sEzfodSl2rbp2ymOuw0VvfkTZK0mEGrdma5nepozv5pYk
JFBBpxYSOlas/Jh/bRYbvsykFdDW+qyLpGCB6aQD/GkDW4BNXLClSWyzX4/t+ske2BHma23gHF17
7xng1UsekNdHdbzVxKvwc50TNA46hXW/nuffYesl13e9X9NOB7Nn32FqPDvlWf5ooohnV3oL4PBN
EFjZGE/IJac5hONsBjf+DEiOEfCsyHd+pvop7HEUvxys+2nhmWywFa56sXZi///B/dNG8yc+O9dr
RPvFo9DsyWE5Xb3AFR3qq9dWRUKZcbc2MbhC0eAMZLc8AmC4SNpE8U/msnQzQU+VlzfzTTXaRR0P
sJdkr3SJsb1R9m27GdzipkebsQYqMSBdn/3znI/dRLJPG21gBZ3zwgcNrQmkr8BdI2jaU1Nj182m
9Zh3gOtDv9Qv9dLqkvj+rZrPfTL6UFhVDZP+mLXfWMOAcL5H7HtQa8fe0BTuDoQ6SdIcjvaWb+gv
tZZVD/fNXWRZkSaA/w72+uQurDzc8AYn9wYpnaKb3W6dtoUPqjyKg08kV3bt0i0ULOzu1D9XkmOU
shUrsrWRf6Ts1YnRIxoApDQNWCJABsCfnjt75a4FUyKV8cUzYa2pX9JLbKNR3RJy9SB1eAUfKxks
BFr1A5xhuku5IUTX52iPSwtdn7kinH6Jm3vtWX6LrBW6q4IAY5Je/c8I3z02AXpbWmgQl+FWCL0n
tuSy+m+wLBjlb9Yh9e5BYrXw3VjX+mlJWSr/u0sDAVC12B5uDyaE2PjXIVIQaOd102vCGxPxJuA8
aB3bw2NKft2b62It8lvYGuek59+P715dHcfF2I5Qgepc8JvuaCG+bYoe2BxE/sY8AIirCbPlNV8i
IMewTYdTQfmH6Udv+xvit0vUcUoRUQTvTavMKQudvwbzr1uzCSzNFPyjyRmCjj3v8ILY9AM8cA/7
5fbicE+h9OtduDIGqqU4kHm9YyhsGEk4M5ATRTEK+cOJlyAM0ez7KxarsTKMG68ZmSrorTZIMUms
c5sEMPvyV3f6lT1C62DklhL5dC2ElR33fD/SpRnLZyDC28KqzHrFNKk3qvJ2BFEtyuaeFx0PjvlG
KbUenESt4bhKqki+gRNotGnDkfVZLobZ6E83IFO1KZAQAhz07V93e6cBuOfQQ/6Nd96qZ2I6CY/Z
YDnhfOEYfSB8rS3G2HHAL+LNvoqq20EGKrqtTN1op2KduWOnFgXtNl8R8odH+N8Tk78oL7E8Phsg
ElpeJeHASOIrp/iQj1kBepJRmcccsavBsNM/SdZZmUIYY78/FyNbltqtl7VU57EzwA4QERNcN31L
iJa/ERUsJAoH3f9K1nDfkUB3kT8juPzF6UULh3alzruYtRGQ3LFtS5vgr8G2PBFMMQRH183NMXY/
x90ltfaKY3YXNxJi8sEFGr/RoXSeEgqq8YAIu5METEZVsKw2vMaJQnpwV6ByeS4vS2NKJTncoRMx
1QhUIMnu6N8ewwbPPHLBI2zlLe2rZxTqbCITwbthlxN8eO7oGVGWsDSIFQRwNBg79bIqVFUAhXDc
WBFtPNoL9NJZj7NtxauOqOi61h9HxZBFkeZRcf3kb/ULjDk77/UzQ85XJYpNqfIKg0gTTmNJ9eCy
hfJvqLtTkBXk1kQUhCC4s71T6YgEs01X3J4UQ/KRNug6w/eQdAKQXfi123VyR4T2KOQ4zNA4jQwJ
KukcX3Nh7IdgwdRm3HQURCnWd5WQhmeII3xyne+fP1bybEJnYIzr8ifwNUTCDB8ts0W80IC1lpRm
ouCSYnrkCj+eff2VW2fb60u5ClEhIfDk2N3hE0Dg3B2gF63HBYVQ9Oly0ie2bdl0JAOZpBA67SO4
LyzlBU2Qj4U5FrPt8ztXTluhgqzn3BmvUHDG2JDkCL02vg6yFN4PTWVRiPkvs+PSHMPNy5mMEMGa
nnyCcJFRfRLd9Pb0PB+51rqbrpndUipHXZhQr2q+JemrbQjfM5+HAlMNbbLXxXAxdDM7aFHeUGI3
ImGwhkJknD21nZNPbjKGBZqV/yv7UTTzXQNz7QWSONpVCGK0uuFmgSk9gNd+FHg59SZS/zO/G101
ZzOsi9i3UAIThsYY6q4afhrQuEK2BaOLKLQzgXTx7TlWMJ8G3Odj4cVeRqjAOVfLtA5iUmY3vITb
4rcRD06Cfapkr2k8StzjzA96AqaidYvBYbvuXYCgCmH5AjM4rka4+uk9dMMLRzYOdqAarw6rEZSl
j4clUHgn+cNRGAlcGF7JgOaEX94qMnLtGKFEy4R0P/QiPUiP2slsPG9qdRN3GmLPiq8yDIm++G2g
plPzHf203kEQBklFzuRbVKd/zQl7kc23trzdIFm5hG2A9DD2uCl+PTUnuSeQEg/bparttj3Gy2/V
SmxFGKD9khb1XhNHg/0hLEOwjg5GoPkAeUtJIPAEzHD3mr8M318Ggat8LFPjD3souxUdNOotzhEb
8mWzr8ki4uq0fFI6Vv/sdicIF3Q7qCE3zMi8bo3ik/nzuXB/4hd/Xh8PocGvfWF7l2pvcEpxvN20
T5MU48rQf6hwG0kQIvGEc4Nwq4f02KEsrUp2JBt9k5kVnT0zeBMa1yIT5aVYf3KvECaN3VhWVfak
jDzzDGeFUYhkAmJDbHxoNbSbj5NsFxvOIv1n3KPuwOREODSZkWjdrrYzAqKEhI+IF3Y1S7CADGCj
7wdn4Ak5KIazZ3RtvnC8aNGCqsujKNkabGcuKoYvjl6z5DqOaAkbFPwKojqLmZcCgKL5QAbinLm/
rO0hRCqf+R1lZGP8dEm574919++Y0DDbR1C3fnJfyoQAMkWRMZtPlSRd2dhRhxehlIBqzbRyZ0Fx
ABR0Pq3PyM3dSrS798CyCEKY7HSsGxOjB04TgJatRqmMWAF9Z6Qlv8ovu2yCnEnWZtUHTklmwnat
6ntdRr3fDKcWe5bzXB6VEgzU3kAL90ZvVjXFf6A8dmLz3Eo1z35EHdEAeGG/tHxgYyBZYLELka7T
rA1JNhBOkPl2g2B7dSJuh8r+JLFn7ZT/WZO8otFksECk/eUakFY1QpnvXD8a0pl9H5I7rNP6QiB6
oh0BBQ5lcRq5rkunSZ48ig0fHzZpXYXrU0T40m1aicNDp3CvxguHJbuRAY3LYPjxYWe+DFbjup0B
EhyLS9yDyQXizC3pY88WSE0auNe9YKXuJTqMKAsswS+I9BVECXWhpiEjI0lKKhU+3QwvIacezEyZ
qR+Sqj0s4MvpUJYUEx7CzKFli5qTe48nxShqlgdt+kB0VIjHzrnjdUeLlTKe4Lihs8kS0aLMqMDr
ObtmzCfEiMxf0JAhMZ+7+r8rF1Pz2P3cKFxYNTWeQ8TMSCPr8OPkFfuRbFcEk8j2+1yDoZP2bNwv
W6JNvNPqH/W8l+fiaktQ9cr9fPgNUYXbT/AoLiCnhgyIE0hUFZzak9rUjAMUPf5kdFAE2nzgMaJz
mPivLyAMG7JKB0c8Tc7AbFCPHJjCzK4o2U5PNPZZzRqJ1rOLHieykVxLQYvrF471XZS2NCPY6H/+
ZYnWRbxZTSqgsstL6qTVacGIuAJ2HeCLzB5r8Nzwk/HW0wtMPqtj6OdQ7UCXMHoP4tKAdrRRrA7a
nGt6KZK27sYkEZLCnQ9QbOIjLQBSB4+lkkta0d9bOU/tku+JLKCjamb/OBLgta4Vpu4VO1g1snB7
D1wWAwbguKS/klFxORePU/66vTE2ZKh1A82J9XJ4CZnKfEcwLHJNqrmJ31R+4D9Sd32VN8SmT/eM
e8CZAwKUpseSlopUnIkbd0wJeqNIBVYwYHZhOvd4GUwSUdTZt1XrCa2bTfqTIrd6xV9mgDGwqY5t
Qpe7kG+E0gV+SUC2xGvgYzPhXPJhm/37+nXs7CfAKV1crtnWO4wMay8fJBXZDs3PXGonJzJjQSDp
sobxh0KGK7XoOFHUPkxO9eJeCZLjIfnmkmNo2lJviINPbZjAtn6e2SdW7F4pnOS5K3zIqpjpcc2a
ZnQa/YBf4XY07uVtNQk4gC43GBTuqYyVgi0X0Ry0YJNTVIEXvwhbiIWtnaXZAEZLmorNL9k1zTo2
3qily9wxh1oKOg4pQPY3HgxAvRbIlryDd2RRsQBUBHEWj6coqjw8BtS9WdinleBfLfiWU6ZnUWeb
xRouFzPyDBaZtaK2bQ4U4Qg1VxS/CDxdmZWYeUYRQ9aYFA2SdhKnyqmbihGb2WQd8o3g38tx9CtI
wC3hSVaU2KZG/rAM0xht2jbflotOxdlOb02HdlzfvLN8UojCHDr5JAZN2sLu6NHsFZkzQPYb80zX
Kz7Oq71Ti3nQi620kWDE3U+dshbGI9ER9dUOoZxxNOxODh0KNiprUzsPrBgrcQxiKXfZthbMszoF
fiJAZEAx6+uOEu/zwqfIdnH+EMfCR/lkBduQE5TeoTTqFVQPZkYRHaCgWwgVJX+GLAI6I++EJ3fE
BPmL6au0hiKtqkf+Byv9wnI/Sgqvj4vqk5QCE6ScTcTlXVLbAcylC22RRMVRmp3ggOAHE5KIUJgc
fVLeeuktUX1bT9/sYjqk1Utfuz2AedSexrNYKntsxwvDuWbh2T/dbSoaEzjhtTEQxuIORRMWwWvN
ZxDHLse5xjAvfrLg9pprDNnjHlqv/cPE2QUlYuikDEGWDf3hpLXgmDYAkEBH6G3TNrRtHp1MbBPP
AwgDXBSxiFdZ8zXuNjWODgiFk4eZQvmeHfTmbqIDfyRovIl9qlj9EQh5mUmfMJii2DCo9UCX/9I0
foV0eaT2JertreV6rpO/7MwY07Ld6Y0rXPojB8bRQnAIZ4FiBypcdokPzdPHvH2jylORXCsETHJ+
tvlqf3Gbf+uvNZUDtgKK5WgLAVSAmwQ/OOw0pi+TOzsB11Z8gfnnwUJZbOvr/V5UbaL+DvZ9aKOF
Z3W03rZmUdABixCBZcPpk9hSzFlqBnRsCeYH4FrnsBHKRqc2poqYDX7SoHpT4yiJfo9jRX2oCOmq
/ePcPUwQYykb2WmLwUTctTDncSWtKxPfp8dP+sFTf/Uh41jEfEyh4JcgCgNGJu1UKff2/VXYRn/Z
Gs0vxTE8JsMYaNx8PCx4QW18wlMG3LRBDz6lCyDv4gSGgHm9AO5g72pVxA9LHEZGE+rOTwR508hr
Z2DnnDnkdCxUlcEpPTWCJG5tb5C5B+Yek/8B3/8NQ+D7v/3N5+plDs8GUx66V86rEay14dgFSI5S
CWyiyvTDl48QNbsA/T/iTRIhG3eI9dVeHnWjowLvrlKhKMdCxd5DrCIPzdpzDQ+h3w1rRfpzkME9
Y+IMyF1X4/OTz9RWhakNurekto+EgL22+r0osrjmD/mL3Q+xDALqD1Eeh6JOzUxTNdDZnEiabY6J
mfv2rf+x6cj40isHHUURv37NCcv2Hc9fdLet2EDK8TzwbkkYDv1q0SnmrbJWxC8yXehirOhLAfWC
wd+EWQJLaoqqp8E1IfwEqGpMtYXzjGtjR9UWOOqfLL2QktQWLcByJR5cMaRDt68T4NLJ4X+p8anu
fj35bMLLHdmetOF5zIudx+mFeEbniDwA9TtUv9HdyBL3hFNVoT9soPH263IBz14CgmMxj3H5j9Ml
piHIi7H5gIxe6Gtj9gLoMjPBH7Zb/CzTP3BE6BAnw6R1VgcLd75zqwTdhZIYvouq6jiec/+YmTSX
TdKBMMS1qgKQBajv9oe4WrCkkQYbH6c1nI5q4LoK0+Xh1nPBKuY532xqqzSYgeoIctjMMYrtLO2k
lg/YqiMuWrgyMVT2StW/39Xx48pbxXADGzvSospaUq6SLRiL8vT67Sv2IIXPIqxEWfLFsUsUZU9V
zXipS3kT+aG3aV9Df9neX/Cbq4eJw5nzG9Ui2dA/7xYOGaxwx5f8uFqwC7+Zbr+XuVtrPz0cqmwB
WfR4GlzWGo32EIwgGkEUTOYBW/cRBSs+FJ1q16sBYr2N1j16dB/+EoWj6G2IGDwRmo6PZ+XLkKK3
E7u+rXmnz7qAetXaKHT4fPXfcjXXYTX2GoIhVT0MjXOcHymyLjZFETiDcbN3OcqTGZQaBmwV9HYS
LALZUs027cXqWNT0koBkaoqj2dTgLBpAhXVdaR2ufbhgjBqZ/57oGhDOlaOmYd0biIaGhuTiLeNK
4wcD4EthWM2e8lFZ0aX9bZW2OL7H6j+6UtqrTpFYVSqpLdnRtDXeCr31HI1LCcPsf/122K1LG4BM
EqdLyMVlPPfO3I/JthkspTNH6BG73ANgZTRIS7E8CvH3ophuZpWq/xEmcWMnQ+K/a7VIPO3a6aDu
MudzCFCqPjrO4VFkOvprVS4gjfuFS7U3xB1ODZlAxywGdj1J4x9kx+r4lMarZNqGgnvI9Vvp6Xbk
/0Jimllp2z4Q4jrdZWBGlOVcOw/GGMcMjeffjxMVX/kR7rfDawF9qqQGzVSbJt6GY5qa1lMuH81H
912kAg11zl6vFSObYpCAREdyYbwfCvgkmYTMYmTM7gobhE/m2FxWlIgL9FYghR0WlbZ2R8kZ+EAj
TpfnPLrm1F4RtBGbLpE7JnG9QyhHHHIphDAfmo0r3eIZnziwmUwNW0+zTV6VHOvbZnrkvlW9vnz8
rjFNFBVTeCY9hyLV78yzyAf0w6B1eR+uEsLTidy+S3AwC7j+xwa4Uty5/5+Bvwfb1hUwH1dA1nOR
acP9D3Sri9QJNAyqY8hef5RqJNczHppF7RgnBjgRe3XHvb/XKUoluNLwZHSdy/00PcC1HRhcUyGN
aB3bKjb5zCJrDNObre6ahCmxrlGaGEeA8PMuxjWJYU3Y/j9GUNtnIwOZXaMgHITxv3qWHOs+Lsqt
W3vNP3wl5QIIrAnfin2sYq36sGqgSUzExlDWzgAQwCKhbtHKP/O6yUDwyMD2iuLgjWPHEKkfjmvt
nELxB5H/SxvZw//Zc1n6kybPOrsz3ht9+G2YUOTSZTOvq+lMZDoH+HvovvRN7PzO+0u0/akqAsWT
4H5QthBz137xJ0zFQFHD5IVjH2VkjFIGQllEcdhkokVxy0ofMJn8iRF/1/dG36IcPQoB/Ej3htde
5OOVfhHuYFJ2P77OLM8BH9mwCMXTgM+qG/jCcspLXLKspRH5azyJpKB5gIHGJh6/FqE4fc/DilTv
+lZMxYzP3NRQHZrejYj2FLGW7E/AnOcwTI9W4HVoQpyTpAJSx0PmzRSs3+4JV7ybWMA5PnMzSb0H
dqR2wNRWKHbVmJs5tXeKjy1WDey7e5Xz0ZeQcw5W8OWeENKYEobhIEOTqM26epJAzAkvG9wZc6a6
JXb983EOisxchX8CT/smrP2FuAZmP8KWf2tFXAoacy9Fk4upGVbn4ZC/dTIP0Tb7jSqNFYnAYJzN
q1Ty1N217zsoLNaE1Y5OduMkSJ8Rw4S6mbA0rtxfOFFWfTixLoXSZo43EdS3HWmdTRioL5fRQ2Li
4UUNAgX7ptFEP+haG2OcURwadT1x0R98wM2NYojQyZwBaBs5g66x7PsXwb4GenxFeAFiAKO98Mzv
ITUR5E4ZH5ZMbvgw9T6rk358aktDAETKrsdSC/xkONLUR3u1h/u2TZNH+cJbG8p8rzjANUeAm8m/
IK6tgTOBefPIaSBDjrTroUva2QPmDLvL95+rE95PTdrZcuLmwlmT3VTcQXdaWthbSx5h1wH4UuxK
RZw3CVlQXWE6zdNCQXOXiEFClm+bualP1nHbUNwe9pGGRgSxQx6P41H+tfYr1vupeq8hQfNwegKP
KVuC/vMtQoOMJzBBjuHaek/WLNjKN5idRCMQ7+f01sEenYZvIX5ZlWfHqAucPIGdIPESaK7go0jf
2Fdr6VVc22Hudyzsjlj9H0SfPKRot3MBRjLO4GXNM3ozfyX+sY10ZJPkKJaEPjshDv3pk9lJN3nl
EjSAUvu9E93Vua8xRE4pYkO4MIPIHpuh8BGiwowkC4f2BIMYtdXrBg+AjmvA+y5I6C1mSB5JE2Ld
y8eRrkZmHizs7IfXq8YD1dB+oMsid6Cb2bBOXcZSswwYXfxG/L6z6KzXEBC04UuErczAeTrrESNb
ozZXqX0sGWYrHNSNxc58alZuWLKN9HxA5PmgSnoD5Y56iFdV4dl0sal4jsBOshg9/LP3sTGGqDfI
kiiisxkMm/T1yKRAaY4m7H/0EChkElrswtO2ZC07oTXZCbB7++VTWQfYke6SnQm/hL7qTdw8gxOB
0P4LsVzc2BdAflDgxbPqcijbue5KQW9JhmbnkP64vmFy+GAk3h9/xaRKgEgatn6hSLeyymxlPemO
1tVO2n6Z71THYG5K6SGhKKrS0CXNWcE8saIitZd7bXGZNDaMpB7tFHfL+RF0wLv7zR4VFgSGU62L
DGNwI+OdQZ92dlieKXdh5r3cdUm7y+GmUUSz/sqfeTp1L8FV/dlsi3Hm7HtOR9qnEjGfey8Esnv2
gT5JPKyNN2z1FVdSfsx1MzQjoPtl+FpLTy2kXgioDJPAiPyFZbQX/oBHtDAokccitF81fo+uYK4Q
byufqFRX8V+6K2miIU4VgGhomcM2ZKtlCnhChueq2cvOMpiqpw/5Lr5LBu+r6AHGvJodIe0YCcUA
//hNa3KSNi4AAvFLDz4/yRdWX3f41orOpvC/vixASrxqNqYMIftnExEETwXVhxum5G3FMjGdlJsP
vq3w9C/LPr0vceoNZUxjRv1PSxVbypt8nV2X91DfXs99W4XwoUnxfJX6cAUw2W45qWpVJX14TjhV
b8Iyx6eKZa0PoL/CNME0lc32HoGZ3qRNAgDc55X3zbGAz9AKKgUTjFu6nqjb03Mb+IsA7v4Gg9Tt
pxm4985kMiqAAB82OUAyTwLtKvu+THNb38exNqgPlE5MPrWxJJQPy6s5W8tqsaLywdXDjacIddv4
/52oCJKFRmPPxyN6UIIOQHwTJMxmgZ0bM9yualWt/iHDpwkkLjVZJ2laSKPQH3p7woMy7xVRu/sw
eKf/FJNMMFTqjCFx/TESHbBV8ZJpSbq+m8vvcXgGBDGh/k02KEBJp5Rb6girYv3vhZNLWUjRva8b
2goFUg+zKipwLg42/0ObyqgD3wouzevanYHKj3MuCHoLZu4WwtdcpvV7R2Xi7rG4WxAP+C5JSagl
JNWkEdTOTGqj5m+u7Dr6CyM2yyribD6aYf7Jfp4l8nbkx1y31P63tP/yVJX1wC3QBldZDcVZuDMi
CPkmV4OdPPtb80zFDyrzpzkjR2d5NhE3B/2wY16RauVmQak3wujC3TiRa+2ScIgKQs6SMjLflLV5
qLuFE64LDelG+ZY0eRaaqqV9+VHqjE6NTTxWRgPHSRUbAECoeZGfGxosh2uyVSkuDNdjxA2ISaPD
Trmtx7bmVK1cjRZCwQojD+TxbUGq0aCHIi4fYELE9KBWQRCQ9TdAZVBVy0IwqysTTw7TAVIoo2JX
8UQhfSOBeMcT0RSX3UWmCa10mDa0gwmEz2zzxQzd6q9SFFxlqBgiZy2Yy8NX/sqYLIx0+s+kgznx
OQ6dw+JgCNIkM9am1R+r1DABduiJ3DcYlX2ftccdAP1aApNjl8QxOWm0cHmJhy+OfoCz+hhK3L4p
d+e7MNPhg/zbpQPV+S10hBg/5mYVmE956bs9Ynt6QAPc4+WuQLu8vqEdSPc9tbuRA3LLQUOQjzuR
09/U5cS3pO+wa+ZMQVdODgJJpghnd4lK17GkOrUsRtCoP+/0ffZwMH8wzgb2IMQK49BC84uvjWam
b6jD4cRKionWR3Visi9YSIKIe2gOtgCEV3iQs8KK01nNR4I/TyIJ7n0Cy28mLqr54eiUMd6wDfWg
FM0yfjAvLYO+wQujXP/VtmBOzIzspSLlW8dqu5mxBscKur44aj9n9lW+h6LQA7IuixhfKj4Lonm+
h5iDC/9RoL15Te5qnimi26hBk+J3zb1q6XssD2bq/KHVNGnmIkYPZxJEbMEF74AYSL829lHC0Ujk
T2MK40XwVtVllrUuewSlBb8Ne3/CSzC4Bfi3wAg4kwUjTLYtaXi+p9K1b8BYXM7HoIoi8p6uzhci
eG/sI4hDw8VjisBZw+uo+jnVD3Kh5cnVfC2g/OKu5Pv6pobu50Tru/EjTBulV3gLM/y5nR7s7wP5
kn2PIapbcu+GsgDNHLipzr+sBUUVqzl48MiM6tkoqYjShIvA9CcoLuQUeaTAsnNb39Wtn30Of0m3
lbo96oNOCltM1/jR6sc36c1E3a1VWS4JiKLJ1jFUZXvAh6WHcQQoYsQywAjbruGhQ6T7WtvNNB/1
9j0WsvRt1Fqgd8Y9ormzY+uG11ZrjPYx06zBjPDfxk4dpeVVkxEHZZ6g+D/D9sMreYarIGaVJJJH
DCZ2r78MISDayLxTphUVcFtAqxP3zy88nRq4bM7sMOsyk/I5avo+S7AvyHONqCPD+ViJYhMKz5nj
CyYYh9pXZl7EJd3lNg51sylp65r04nl21fu5RmX7739OahxpQW30UMGV333/QZT06sH2+/knA29V
SHPmE1/EWM5Pflc4zhpDuKteaFHeocFHIeOO/ckzmQKvhic0ILpXTCCswpryNBQQZi8FzTP3lLr4
9KPNJ1wKKgT0Hr4AHEc9suzIh8laAlvLOy+gjvQTduIYGIcsL+rHqp4ZFMPCdBN6vTKsurh0uiI7
Q/3Gg1T/IcpZGQlibyZ8YzUE4h4OovyY5DomtKur3tpmJuQzCWeR3fVNRjKu/rZ05LsCn8D9a8B5
FXki8Fd6EUFqCgjdHJknKo29oUR9X1N22y4Q9gFRgoFaELYfCsycmpRGy2vTQoCvizUfMw0h9/S/
X3FWmeWfURO+Magag3XvvKE+hQT238Cn6FLq2+Sr1KcitplE+Srf8bMPOSzfwpborP19X/+mbzC8
ePfC7dn+Ke6+JH0yhs9Q9l5X1Cv9iVVyRxiaeQJA/m3CArx1b70ShWFUkztOdp9viOPMBQeejL3j
ZZyYmdYEAVmujXmOHJf7u9jxS718m//3c32TzG7+YHoAqMs1YdXYJcITqodpFEzJklj6wLTaOeJA
tlu5bURK8ByfBbQUT7u90wDu3deJh95XSiW73/AySbKq6aash2JuCsVe7sJi6fxR/1fcCMttvHB4
OM0dM85+s+Y6tH2mlSz7Y+YzhLOXsJT/YwhYy3dLYGjtkQBjWdyUFc4B027Djx+DjmPXDw3JktBr
bt76mMRwqxqogNlJlepYsSRHqlqqMKh08cAu0UmILSu0+6IQlMHIGbx9/bv+KbWUzwK+m43IiEOX
sP8b8IoMOqGa5QQMyofNItGbFAsCYhs1a7N1zRhbNySe9nEF5QB/fyxXGt9HNSDTuwFYG7zMbKw1
cDY1I/X+VvK/ELTno4Xet9XFT2yL+FbU1tn2cQsirZ2kHV+ldHXm8vi2xyctUN79wZ3bT/Ez5WHZ
WmdSxwRF+tNmSmKIhh1pWywttfTedpF3yrSfJxJApSAwyBAU6Zr9zcyRx4S/mbH8iede/Zsl4451
uZD00/24ePzC7FLEp7pC2dWeCdw90wcbj11Acf4SyqAI3R2J6isLpuuXH3QkcVp3C8pvPKeJ4C9S
3LMhjSWZs+meRRu9qEk8gLTKSaW5BtEW6DX81FhA/8zTV0V0ON6cvINjMZmyznRbbxqAmgGMh8F1
37o05Kxg8OEzYs0e5gPCxaydYQVDaaMqSHMdjU9BLRvdvq8DV1AjQGak7DARP3aZVdHdQYUUokyP
ocRMcxlESswL4gwc7RHnogqBPdYX1LvVZ5m33CHhB15DrMbowftN6vIZfxgpNCuRVa+EgTrW4jnK
KTAN/+mbIEOBG2oBVNx8MV3G+wxwt17XlicBwYhOwqfYI7yAPhHEnSyI0ssPRXOl8DSsLJGZhQfL
BA/RfdxYzsI04bxGJD2R9z2ymP0CjxXjXnBnuQJEQiV5KQvJzgXTo8S3sn9Gdv0MziCh8xpO16sH
d7BfnNOwEvI7ZRFkKv/wIxcfh2393CbBcsssL2A7Q4RbM1jWL3QiPrJtN3jTRJPYDHXzdpQaiHLA
IRJf45ugA67+0aAR/O0i+GjIgF2R5Exm+6/U27aSgpnWHUe9FasqD33kOZhN/pln9X4XPtOuFgL/
tGGVLFWhw0cOJ82qFLZsyndh0cVuUlrpB8Y3/oN4SrYz0+Ry+u4sVSrUsli3jfPCLPRQ6PPKjlzF
usafV2qWbf9L4rK5uOiE9exFrILPsBmRwQp6d64EfsPoewGcT5aJ6bEQXb6R+hgeAaRatMyArvhm
caG79Sdqd1Az1qOJ2xtszW6/aGoMFRVdBAkNufPZr03MF5bBohrTMGYpHOaccels5TURd04KaK1s
haPzf2kLq7/W4LTEPlo9ZAtMZzb9DX3kN5abb3c+I7h1Yhndf201jXgxAxpD+hcuA1+id5jXdfXg
nTXQGHVHZZPIXmXFZyzIinrOz6AtHt35RtJ+18++LQyj9iNh4MSHe7XtuisJwiP5dBN1tOSI7kvY
qYgCF52q10uEKI7MBOpPZeHvbkpLawy/rUX5JRitcIq1Mg6g9YgDX79rfmxFjkknHUGbnrxe0dgk
W0LAb7rncywSbkJTdBEn85vHHJer8OpoaEJT7KYXvFTtU0Q8hwHz+ZhVIoR2EmMzUxWbEhI7UkMi
MLye/miwm455gQuItemv1ypRdxczcWYF44hCY+Lq0bZ6mgDalgaxpjIX8PnB+a1Wjgg7ctpSIryg
2hnxj/cN/MPFcmZCSn5xC77PYeOY5zPYQmoXmUKRBaChbxvdd3IRU0BlP8UCTJrBnvFs9NXxxe7y
FSZVxirJI0pjiKxydjHlXYPMgPU6zcu3+G9QZi3JeO1r5UB6K3LvS9J6CAAGKVZZiOT6FtE/KXIV
lNmoBQMHyJ7RadfjGgiA+vtBJCxLQ4Rsx5UHO2po77BWbnkZQyFfrw5hfpRprxKegTMj1eF8R6GF
Ix3uT8tC+9rc3kPe6AAH7gLJ/013LYOIRqFxVtxpfDvVJvdFiLkU/vKLh1eALD8vL6wFMeFv5cEB
XPQxjCSJToHlYVjT4HxaQme7kNxxGcRIkrMBZQnh5A8BvNS8EBS2bs7AmyaClKtold6nbn6T02aW
6zJ6l3y0PKFrOUGDXHj0PsTcntJvw+8XOBATxTzZqCfuZn7CCyr8PFvEOahbLCCF9cH6ZI6dttIv
plx3Fq9L0jJld8bi3zdERNW23k/bmkrLBqis85s5GS3VqX4ghO5r+kSbzTqfFEnpSu5ftI3K6TQb
PQPrAEuzMiaRmCP3WykYmF9U/JrCc7jlR3PGBAydyjOjPLLtLj620MQrBFtMYv/0xnsdhp4Asrv8
/uGb3gcw91HsCpEZ94yLcqGwpSyPAb8FxjidRHtKrxDXumfOATDT1CSOsXACF94n9ZABD6lmakU2
liXrwhjcw/TmmCUZKgm/6K493eovYoQRd7oDKpYebJS/svmAcdLLgeyXDlvlMw+po50Ybq74r9Sw
IlOhrxM2E7O/f8HI6AvSVT17dGAYyIY2pMJW4XJrZW65wp7RvRKyUoiUXnA+xks9SYChYYh9SYH/
x8ZUQ/5TPWhKHNBja5wWWRONSyBStQjHpu0thLq7LpYE5XK/YY703yAfloRQQOu+rqVOGtaq0GOr
HTXgEXrrZceuJ14UIS5Q1SaRoFkYsqNo0WwUASlZ3v/0bkdRoyGoBO8TgyFpsfQ6tRN1vdn/S7p2
G4pOfUYsPtNXX0cE7R/YEq7uZk8sq9A1KvmXR5OBGLm52wsweT0jA/W6j5/S8JYSgOIenyr7HB0A
4y4dl2vs/pxOYfk6/tx8gg76dyqBcg4TVT0sKFxDR+r7j5edg8HCP4eIdFcJ+EnOsN3Ju5rEU+0I
oc8EX6pEsxuYV7BGpg/SnqefHXwa6qIFYb/Zce6gOLsBYwYERhbCd2A67VDBLhVI19JDo5AAmEc7
Nyp5O3+7/vvTC8STn1cp2eJ+Skf6tD3m/WfF1+tasiswAJe+oAmi++ffd4RRtW40F6dIDFoN6VWP
K2POG6m7NfNDqEc3h0LUEf3DMq1yCGorw2S2vrd6/cf5im2LM2/VAdq9CB59enwn9rMM6wtkKkYM
uwquW/tHzmajLiVnO36Nmnt3Tfm1JnwtKY+MXUqBgKHqZtHAqaw3nsnJflk56tcUjx2XIaqO9uZ4
j6n0Cx2EgLpxRl9FAjzVWaNMzarBbZPQBU9Po5beQj3CziZQzXCfkVaVKhSfxt99u4L41AgWDjqa
QObBeL4Pn64mHR1+1Wz1cQXIdItfwAxZykhaMeOadQutJ0GKQHlrSYBX5ADS3AlxJ5ua/inVM091
iwbz0rSXqLsqlfBciuUaWCZ6MYYBOILOFJUSABqogokHtpOPJaS9ZlNCmcSv/PzT/J5CkrFKj6aS
HpcSv6hRLVjltUruyed0rwUnBkBSg0kUXvGfpe3MGJqqRG6JVv+4UXVC5lqdNEdv2XsA3GD/cqE0
lmRjVFZc1pO7rauO5ZeDaMqbaCP3lihoSku/vZcJiEVXgfS9oRIzbbThws6oQcF9+rF0Btkakozb
jCzuxjZLfo+kbS5FGBOrmMD7pzXoUF8hxqjIE/xQwzljSqddksGIDjloyluaw5kQ01OOHjTdn24c
vIwLIlP9ug9l3mzuYrrRfFK2K14MfKhbI/FXX/izdUSSEgm0yNcrE9FPOJVb5cQehVnb9rr/buOD
QVzRFSOkLBBbc2WuhdIjioWKYsHGb/FykACavt+4kU5SYsxy0/XW9TcPdeP95oYhv7sMrLUmgxd+
yUtZYsPcZaZ71sIJPsasLADbnDWbRpxoABoBRKA7/z4K9VEMsKRgM95F2xE0haglnx9UM/cOF3X4
1UVwGrzCTR9KgisnbteJ/ktFyomNZTmqzov5cDG1fKvb3ejnqtecuPJY4+o/QE2wBZUDIw3QwD3U
W6HgeipsWbkYe7JgQAqa2TfV5U3HOyNeG6wdmC05n07EtNqubJ7+95yS7xJPS8XJGN6kkulOZvk7
nupr7GFsa4ta53Du/p2zsECXlzAKtcuvQ0rB0I94RDbN06Cn767t66yFO3owJVboCZiys72jRjom
QbxlkTKU4TDypw9aiNVd1h0p1jl0O9qXXg361SJv+dByTzAwPqOG98OHDB8oY0TDvTH15nVZDpzW
JTYYTCJl5I/ioGIP5fp4Gmhh2EhI67pLcYIKxX8PXTwob9nmkBJpqMZGVU21ZeJeBYd+8NSXpdFH
IsuYWnG2JvY9oJZp+7eqLjMLCZC1jBj8rvILEFwNTqcCGR4MTQo56oMEtcXCi+9VvE/GIMTeN2xX
PhRqYE+1bLbAvANZAU6wALV78+NW3Gpt9APBin5+FmIhEyQJNvXj/QLO1CsFTDK8H5BsPKsxniZ7
w6i21VDzW8RnmI2zbkcHZR6JNCckdn51sAqiBx2zUm1FjAuJLZAtTjp8J079kblVyWINsPevKovx
fb+Y4TRi7OMCtv44ybEBaVNPBb2AksVQ6uZSMCxyyGV1TWRJzZ2Uza8QXkENx4SaV0L9yC9F4iCK
JVTAL7fRSSikSaegBdaOlkBmtT4cKWXOEcf/BfLFS0OvmbszEaMa76m0e1AqyTPcS/mCe7h4C9sr
GJRACXtEbi7gg9Np99kW9PecrMxG/Z5c/F4xNYFVo9YiRJuXhlYHwUvPzttXCBiCk+SP/+n4kF+B
6Ls6YV2+A8uOCOKvbpd7BLLJI90PtvpvfvSDJABZw+YluegEDi+GQ3vogtJYi5Ve/G6Q3v2gn8x5
B0pml6HSU6SlaVvS2FeLnmt5j7nyTXByh5KmW/9ZTow5TZu3QXL3Vcsi4WNuf/Bmg4y4OxFYdT6M
lSoZ9+EdZnMZWN4Zn55ZhGg4och/wBUl7PARxIHEPGG+R8kIJ+t8ds3PYDR+SbD2LmyWCk3nK/zO
Om1LTx1dDtvOzsW+L4MreAVnxJQ0illUFDenWS9aJ9i4lGVvi8q2QJAl9iNa2ry38u6XsVpGbjb3
G4OTbOaByl2O4SA+S/BqJv8zqPaTdBWf38xmL2/TQyekvufCMTPkaVx9aEEEH9gMfEY7n2/9uNAA
e2xHAlKl84IRLo/iu+OIaG9oZDDSrt9lVAp0+dDNR5pdAT3I7bcHWSdfkl2jRN8/gLwNkqbJmyq8
F4MAuBNSIQYpq6yMV8LwY2l54ArH1Ny8rmMNJHLg3zbAoVD6ExycMGjEfpbZ/XvJmJBk+kYMqqcJ
heP5lkqLzzUIng02hPFocjPmWr7kuch1Htb5ezQHLTbTkGsQmERtuoD1pI/mvxCbuUQcgjYEOnLl
mb2oK9feTAsEqQZBLLTiKc0Hx7uzle88COHqN7W2t3gjeLC2Pg9xiMELEfPu3e175gFxTER79BId
ud2mqugQYfC8y10yV+P+vEpJ1zznEgIS97Zc2JckFO0HWmAMbw+8rQPfBBtFmz5wUMNGEhZP79vQ
imKb7St64uCseAaqJJeRQjo6Hg7+roWqNNWujx294xo934bbVzJMJEsSW4OIeDtmN4ymIdnY4IVM
g6wvBMEqoBHpUDx4LiEvHoNis0ACy8NiYWxxUc8Oq/eaa2GmRp578uYBTfKOjxWcisgq5SC1p3/o
6ZVLYENPHlXt4H1z7DlTS2i1WBkKwVqCW76fehC5dOQC+iaBJyh7JxbkuVwlb1Ja7xQ5Aci4fHnf
nT2wZLUgpXrwgvWPdz0tUxGwlVE+O6wS37ADfmmh7BmkrEtRi4nCYRLFDXgAM/KOxl9a5JoBLdkv
8B1w1/P35MdAIcWwGw7I/RFIH7Bx2c8XLI0SmuCe/WXjcBRIaoC3jsw8t4ZZf2QseJhQTW0tez4p
Qy4q3701iSpi2+vyYKtTuI8oube2/Sv+4A5KqhjcX8afxe9kvEv4HBrt6dkBw+jVt4/if0zWoTeM
FMTVR2npbtKIWVQ0pEXDNQHnGOn3RgHZZ3Aw95nDG037l14BEsaVNKPMs/tfmwMgfVO9heKl7N+6
7juW7g1QkWYPBZK0dHBxOHITbx7/b8egtEUvxuSmXPcBinQ7twzMp79QeMDNEijxb4Usn6hILDgk
B2SuAelD6hFZ8pAWV0Lpp4A3mdN34rI+xUoLaQ5u/2/rA5qxF0pQH5+WDKIbkrYQKQ9qv7dW+nIh
AiRiZg0tHQWoTGCGIa4NxS48mWP3rtnFzhp14ghYi3ZBIT5hH3sck2pmGSo6jVRpJxx0FpwHlDea
M/Cn229NC2yqEiHl+q9/BLUSucPouRhx23T/MzONOz5plF/WOIPNoOa30N+WewNHotgBVXW0YIBR
Ug5UMxgPt0Grpuy1A6+jHF7KLYZM3cFykLUYZIgkd6qcZmRFUrD2bMWMvpYaaGK+YiRuWwSYWLCR
0vkbhB0lddJ6A98cpiVU6opr4ioOM4ZbvMLnLZLY2jniGaizXsXeUSXSWDhVJWD7dolwWbuPNAfo
8aYpbnjytrS/QU5F8w6t+22FQDgT1/ziTfGJ/I6AX4C1oocbDCrYIYeTLMh1BugP3aVxUoTsGriC
kOkqNpHm/vKXAgAd4hN1o/sA/jVt2PXSNtNr0FCsWR+vvG0ntLc3fLskeZixq9PPrf0tXBoPWmDY
dvzJPN2VfGsIoxgo/Pf/D1+SBJBM2OUdb1rxT8YQsYjsSsVyE5vIefwc81XItTJzRJuxyG4GMLvA
O08jbIs9YllpV92sYHUbsHQosACv2DFiLq2C4ev9MXLYcMZh3Tb9oqwMDFZOdSS6/POCWt/6T5v0
tidHhh5NEmoHf7rJOvfg5mYr2ijTg4GbyNyU/oaO25nGjS9gdJjetTifIb7LfVmVrBZyysh8dg+Z
iMbP6PT4S/0bYPclY178Al9kcMc3tDQedW+IrOP84TnBlXHXJtyh6jPGNo0lHmvgvsNZKsN8285r
SLDnMYjX+ej5A/+5d+SzYCqAMBsDb57VNorK+6ChYP/bOQrfHj0n2umRvEqJRzMk33sWN6AQhuNi
R6+yzAfg45ry6vxE08KMMLf6S1dwFPpuePJP3dgJM91QDnyvkiclXblvYkdulgEz4WroeIgwDs/E
+OEMu8TvJZ0mdTE2Rg0ng7C2dxkp8+1w7M1m76dfEeZuCU6fLD6J07nIMT239GQZn7SxgStxKXkE
y/IeebCJQZsXAix52+rT+wwof+owwhGyQZhBYT7VcRwpXvGvt/8IrjHsfXaC3WKdc6OzkZi+KL35
lK0KiPJV8cuoFrQ9s2LUjXncuzaogyq45a/qq5NsgOJ1CuQirN3KC5KxOH6bz9S2vUO0H1ngjCQc
DfUlzsGmadkkzAQMcC2EHdHDsVHlyOpyupBSGJ5jfaOzAKnpZWpbNNcN5DYwH722YClhbxbTw5aI
y9GdhJx3HTmYMhKxj+/Gp0hSx08k3qZslYpzYcQrTQNADAj8IqzLQa973vAKzAIdxRP4xazI+9h8
TUHdRuFYYN6R9/SBx778Gmj1Np6VZcRsk4eB3ZtZEmlPU5+eV84ERGPj0XW01zOwH4HS2rtzJJhd
TRb/u/ccnMA20Gv2GQKmGPYNAYuh4UL8Imaz4ol/GF+igFVpMr94x+dPd3k5alNLEdDK6RHk0Eey
I2bbTwZ6t81uIrxPokFu4aEfwC9sN/g+whcFKmU6Lgwz85IH6BO1Q5xiWPDHuvKV2aYCMmEZ/K3T
0Z1IUjiUv5M6sJUEObDf9eBh7hWOGI88cShOxTrjlX5plY7YcbK4Kax+fPqSaikesPkFRfMk177S
3RVd0IbRU0TQON48v7pX1SaXaSMmWHPNZJbfH5837HkK4Cof3v0A9txieHneirJNaItR3rfYDYeJ
CBw3J/c6EohhpUf3vF0ByvpJAGQcmAmcgUjAA39/6Vdazm5ekdAPeanBFanZ+gs9anOUlm5YHVXk
BqBxbNhtxBkwfWtJwLiDJxMxGFw96jSUFXjwY7ifI5XKFkdSFrg7LNkqcnKJRePHAobzgDevRBDb
0yhB7oUA2gqGvQl9ARVgBrVJHBEN/upbVnftQYhMLqHE5HJTjYTLdZe8VQmgGVKLDrHhSwAv4LH0
4bOFZ0eziwUWNMi6vt0FHskfoBAuiSSGLoTAvkR210zoH+74uMyQhOr8eBQaQyRj+tfUcOL3lXLg
IS80L+GhwuO0smpPTraMlhQVc7abMBLp6WVuwaPxEy4+rck4N5RmUZCe1WJYkG7h9NhYTBJq86DA
DERfA/mlcSXu6jtEgSgkCPpwqfxYezwrH+ZnEtnTM01blhSbwxC5qekDE6nkRY+laCnVPEFj+Apd
6v8VZw7uqjUTbmM5uBo9/vKc84z9UwX2XQloFfMs0y5SVRuYaKp9zYwZMf+h/4kotdYqv0tYTtUr
dnuDperU0gk4RcJQVcSg8fJEF2r9SH0ds6V0bu9Z2ryeSm516BbPebUhjLCobqKJZI5DBbOQbZ1g
seL3lINC8+bz71t+IWTgqi+xmcPXmccbMdkAkqqBHRb49nLk4cX4f/tG3KrnKLqCzK6VkHotMi+z
7FTYCFqsly5nR4AMRpFUfE3VQA35uHxA74G9it2x6KBBSO0DHZfvzlJ1R3FDHoQEvXGWONhrk80G
JsxPK2kCfQ8lcCk6yP448t7ABELneldifhhvwbwCI3NtVN6/cqPJoSryafRU+8e8/iIcZmiNZzJG
FZ2uc8PtE9UjwjRXh8XjYYgpyp9w+fEdr3ixhXgX1RLo91CYuGKmGG4FYRf6x6e7vYjfyiCgM/AO
T99Wn09YhETUSP70ZGrVfF9X1f3CJ++emss3uQ6tnW65lmjMfziQpcApuxXtxLh/0LBT9JAhkmYQ
nDKqAliNmtVry4+WUjEhmqA2Z3Maw11mBtRzk2OYiChTADj7WjUHHTbiVTyehFSZpwcNgMF4hryJ
hJa2LT+yXnH2HYelsYIGfNn+Q7P/Qs9oq5Z24YwZh1NzI52qJBh5swOoiTRIhgFQxF8wnPsECY68
PccQJiKI3sKZkqd7qU1FdRdKsW34oS97uARMVrWSvWA3CIAbCACyHYzGyBsfDKByuFE4AJSclfiw
pSPim9HFgsobTqXhJcGBn8WxT7pSmtTFpanqWAwnY4odR1NdFl3sNV/z4/b4N3xiltlOoJDeeUXk
LFGBj6H23GriQuSul2x3P9c3fOEnytORrqyNtZiPjw3lxyL3765/JBKGewSrBCFAkREz8K+jMMfm
GFouLs7s2tJ84lM/xbfFc4d87KaWHwPm2ruGmd+9Bf7JKbHsjnHZ/9VfYSICi3Wg3yRK2W+AsuLg
jTv2fkcw2DzQxIy/MOblHN7GKFj5RRsr9WJj9O8kcOCGfa3EgDTeXs4gkCTzAMpzy7WHO+oXzAty
QgE0Sme4Wcu5dDo4m39M3rtnaFKDlgKdg8Y5wWIN6eYtobRug9QDr7H+fbLxTyfXfVPPu445ecPM
tmSSyF4BaB7lhi9t73pvCnnGgxN2pd+tfNgzg9/vR8m/IPa5q6lf57A/dP8O0wWv6eP5Yt48yBK+
vtdaqq9hLEIgPIu6vOL6awdRmac1gwgMBujiAIHmZYwxKPMFtigRb/hnKkOSQlCcYZGZb5yjhMbc
Txh9oHgmh51HL4e9qTFAxPYhL+JRp85HPCNOfO8aVgmsRwpXE2erO+DzbEI04Kc5ruZfstk+oJMt
UBVCbdHLNLbqIqw4p1O0KzvSdJZuCtQ2c4T/Dy4h3Yj87xRd18dNHLt+zn43Fagx9jcrZJC1leZg
oJdKTzQBu2f4p+HF2vI5+2an+i9FDq7zxb0gD77CvMAljRkjsfNZVdaFrWzHbfN3cmuCn0JNfGpt
0wupD1Gf9sHyUDjFf5dBPTC3zIbhAHMVkXLnQpEwxuS7R8Pk/NgJejoAq4r273ZdAr+Yvb3+Qv+q
iAC1IhDAS4WIOFAbnh/7rsnxs+96puFZ78QPO3nCTeTVdAws/MF66VlPZBJCcsMRyuqwU2R8eDkl
x3/INJ8Df9R+MBKtS2Q6jI//ON0RwSjWpTVgdtC/B/og+mDxtYbdMPy6pzdbMEhdu7RuqNGOoeOx
5Svgg0z7lUx0t4my0nDO/YTkDxHLHUlsjA5TgvcmIBqWQbyG83woZRE//s53zZVP8M0/tc6FnNK8
tVSyLr28CxDVCIncttnAIeZKxUDlbRlq7khIFHACnw4l+SM5MdOeMD3//lT8kaSbFrPZuYA+Giin
yEH2D49l4bhUfctEzZgM1eaoPnSEqfQwlapFuqKgJZ+SZUgRbozmycDHO9yiMMKb+Zvdp8s0FZIn
33s2R6nEx96IH/vihVw01TGZQlDZXUYbHIYHnO4nnWInwVoLtTWudr1fbfZ1GG3eUzZg0xoNBVEJ
eIdoNr7lr7MKfKYx1/4vENZqgRSiiFNfBHOWXptPXlXFQqYGvMH8B8Sj90dOC1hswt4ucrDPfBDI
QSWiSw1OkoaPyxe7IDZx5X5RZZRQk2kps42EALxCgwdhLsgsElgDz05tjnULSBww69JSWhuGuTok
rooM4l7daTKiFjTiBOmMvuC7TZop8pTbrgpfDQNYVF6PqsEiceLOAYk1c/C0VucNMtfYnCaxPbsa
W7OQwrJ8BFajil5t7p7Bl/Y3jDJlO+DLjuHyGpUX/29nkhxRzqA5gVgQA1xbh/EdfnhV99AtjRRq
G/krgQVto38NkvXcJokjav7puDPaxvJ9iYNwlcx/zC3o9KEWvA4Dy48ASFqlx89YM1V4aygBIPAk
XOlHPyVFZyhrb9w5NVX0wzZ028/d1ZVe5BBp20tCXoT2bJ2uqDNAx8LznkwEH7jAF6dPTmPzRAdn
hflVloICzAUbNMZ54otS3eqTiLgz9fYfq6dytVCPrijgYDW7nY0FNiPsBapYIAew4FoJG0VpqHWr
+FbjDKmKrig7D/LAN8agCkmPcK6s7XxwpLxZZwyxcPz7Zr/nwLSYwADls1B9GjKrMKTRdRvAy/Uq
LDIx4e9jPuZjEPtMRjt4WX0/ImOBPAMJWDYs2NwTT46ptYUMUbFUiJl/29kSkjF4p2fCXiBtqR1o
o4I+IHX6ipps6SekOqgqRhSaGvGwiAHFK6b1pMGqpvBEGCLoogccC3rfxCD9Ou8z2/bjYSVm3Gsw
6vm6oIvbegI4N/eWxYqh32tAHZMhL7L3ALaTGir4V/Dszs3A8XoY+zOpHz5UTqXWzsjcE1el4fV6
dtlV//kSGN/pCIf90SFuQot2HRousOMov3UrkPgxKZ7uPYHUj/2EDAyfm5KylYhaoV5PDpHY1ied
kvmIU1z4aoJggxtx4s1VvfNSx+zZKUA73nX9ksmcFmmjP+4mKOTBO2Gees7ZOOuc6o1/8qTWyhGs
KchFg88C9UN4oqqbTqTzj07lLp7A5yEFZgqbciB2mcSlgH7FzjFxnBb+wuW6vq9nWWCYnYkJWK4W
3+SIYdKkQ+0UEDOBq7TjmT+HuIzQqUaMlmaSyGXaoQ/cznkp8E1yyG4BMB5/nHUYcXUH1tTuoACc
cReS6d77b8DYSKhWqAEUKAmaxipiyWSyBiEiURwuYqP4R7zyy9uO2R2yuFQV3/yKeg8C+vyokrfa
6h5IRBerLy/OmpKUh/BpO83MsFiMGU3R0zraVfzICR+K0v7T19wlXjNbeBd2kdGAxHKgu/EAiJJm
ICh821EoU8Tn9K7VGgF3l9JC9kn8HBABd8zuZLZ+G3sMh/5+t1tZDK+7J91HPQz4ZhJOppYMDXcp
gW0xuRePWUUzCviFPtY4CxvBTaJ4k4s87K9c5bCoQROPnZQLtZ9FHH9+IububviOy/i8YP8vCxuY
SUBwprr2TeJxuVDiktGDp3hgeHm4FdrtiklOZ6e1l3j9X0qRo+p8kwt8yFJsddUc73Ncl78c7uXS
NzKlxaSbQ2Iwi1mP3htVuYSZvWhFSmVkMQCq6AW7h+0tct1Qw203SFUCbYFb2U0tOYbgaMpjFl/L
K6G/BQkS5YGCLuEyv7DBE2H55e8/iH+LviYNJWUczEnG4n4le3LRdBokDh/mFq3VlAyc5qNTyjDn
8RIDLY+YJhIyzU0/LoFcepJzvFFbN0HWeh3KjIeDZD7k80TRQVuWqWyECMG4Bs0LGjIyxHRKhWaZ
mkWV61jxOZ8C/N9A9A/e1BNTZq1yNZCWJ/9fdD7LccnwUCO8NpcRMtPKQWqzBQiYDTleAmFNurKk
bA1pUHZHKsO2uNLcYNtXyfkbKEis9L2cbV19HjP5AvBlNFR0aiJ+7u7NUwAhzboV1hZHKj+JFh9q
0SmlexwrjMYimn4zQQJATonzI3oiG4oU06yPQ2ePXYjH9atmZsz2JuX/mBabfW753ielIyc30Pmu
VJZTgvhGkm3YVuF+RN1H/SbLycUD/bi3r4eClojJlIl/GpPJw2pBO/+lyu7ot+wOCyETAgi4++hL
yAo4Hj2NaJA0EuUZQh5cglk5V1UI8SeHM0zWMjdAb5YRj27Ndv/+3e+g2+TuE0VwHkU3DIgKDwGh
Ci2d/7Co18+Lw0R9yAuSSwM3uYvN0qgbQzYU4b59hKstMNGw8n/DHAsFtTpheLJZPh+fF26exW2/
QpJgdPqiFa64oJvCpQ1LJIKha4FSGhsHBtelQsgFm+xODRGNHXVDJSx9AF+um51pWtPCGrPmQkb+
/w6yvKXet+s4eKNZzCF3pOod9hlJFUEY8HOeJAICBYEKI0mp0mCZwrdgEuDikmu2YULNQHc3mRcY
vot3PSApgHfvTiAK08vPwZcZTl/TEfSYBHt4QKp+4orsOrex4i+cEHVXbYUWKzc3svFi4I08s34x
WchXrH1hR5yjNX8BXCL5iSVmMy5E18NfwKC9OiN2senVJF3nBEh37JyCKjK97VkkJNG7wWBYf4Rm
PpPu+rZWHGtJNVU0r5r73/E0LYSbGnFTTHtT3OLg9OlJDKp0QlNtkgGWd7h3ajlf+2ul37++iVz7
L/kjSz5y1sDLg+Ns8InFm+/tPOjCpJWpg5X2EnJNU4tfjHMLMVQMIxx14FbxCp9VkwxOHKgtSU/v
HDY3/7pcOKjfKCEiLvf9AIwap3dBEi3wMPOKOFqGnQbh2GAYzf0NnP4ogY7QmBH5C69BRQ8FC8Gq
K3pjYaxsZYxpZbr1/wYuNuNjQ9Ttoc2Aev6GD94HnTEiS++aH8U20eW1hN3SmunnNDHrJQmoG+mF
xTrFGwnp7T0JRBBjF4dGs50wh4W9nRL8FWm9CCxGOl3+1v4s5T2joT719hqCVt3XVyeZNPgsJfa1
VGx4iC66hMR0xd2jvxQIS4lYAsrpxK9MeubzOQbFqUYHimNUqTOoWR3lUhvSQwe/2DTmQ3b9q2ji
s1NgPO42LuFYzbzogMYLt9zUSlY6X5DE56QOT/4Mbenu79VAfdEuNM4V3BHjOe+iW14Y34909KXw
qTbrh3pGQlde1DJ+B1YlGaEMnQzNztKZjvFP+G2NiMB8KA5xw+XQePNfGrXjMxlzHt48I8Cjk/PR
4SeZugGbxOUg10sY28QtGeppq7SfBgngqOvhTyiIUQRJCRahHrHC7aHwi4aa19m5j65um6Kpi0fJ
k6qdpjkkF9zxj7zlvQeTr+gdUq5fgztvMGrdYMU1sIiKZM+pVeMPT31l6l6wssfehxteT/gejcOF
9t6+zntlwJnLTqNq8dIXcw3B5WfHVNElk3jIvOfm3GzvqVmUCeYj9eYg5t6ZPG7XBzfhlCCdFHOo
w4dUWxOCDc9eawwQ+ib/yr8ydFif8LPu6/zjnkJg8E+zafP2fjLaThvHZc/k8M0SdwYTOpFzkuzd
IEf7/R+S8P2+4G6LMmVTJ+Tjf60vGwplHcrzHcZtO1DMZ4i2E/8s5kk2ArOR39W29fj0J64BW5J5
6kgv8GdtIrfuUAe9qpAzSzeBxrkupJ0T+/rKAfTXK6KJ7EpR0hmjeN+jIj9IC0Al56inv/u1/X7O
t2tG6deyy4GbAHNjNLtjE1ZnUNLfOkyFkrkKX1tEupRMISj1ugYNFIfip+bzQg+qtoS39jBCKLvA
d/qrviZQ7QXmWbfwZT7McAe07LWaXgw0jS5GudOBlBJ3Zh9apiPaJBn33U8P8nlzdOSuzMPcbJ50
U5p30azuDdeLAvPna0kZpmEQk1cc3GHxmV3ZvN6Q/CITOErANuiHldJNTpsIviwmiAtH++aNOizc
aaLWhV3PFXXIASK/lmcfAqAxvxf/Heru08r7hoPj49YUEKAraTwlwgaDeYyy6tJTf6ciNHwOe5Ug
A6FQEVyGUVwTB4gpiKuQy3U+aYB1I1WbevZYNlaU47l15CoRSUUVRWSsOQjk9/e2/4mLWhsyphHj
BYR3uh1HgPD/k7ugFB+jtLH7LFBA3RrratXELXGCpc1whaHpmnPN5kg8ySAgK3fnc6nM9w7kfedB
kC9+3GY0aLoegUMNdR/k/ZqZwexjo34zf6FfOtZ5dhjwqiSjPIk859xe2VxeekrsEDv4VS2kUdNQ
0dd72j0okLiUCVIn2+1dfgxaSeqcmalf+vQu1jZW0oshfBS6rZUuw0N4tk+rw9r7IfRLy1Rubhuu
eTBBQ4B48xjJZkx+kekltpOTpX1e+Vv0/3haXaFNqw3Zv8//A+nper51z4r1/ALCeiHScjONBwUW
8L/G7+m2AnGj0K9mAhVM0ZWB18DIu3nWVfujF/kZk4yH9JMuQKApqQaLC2aEFi8KQkv+1+SgsyD6
0ltFWj/H1FcGcR6WwKVaG40EMzR45qYocRonUE2aK2UGegHIOzel17CsKqSnsJh95w5yJKg+dO6s
w0G5naDpjWm4oZShdnIRL+Gmg871fw4dsJamBXcBJOMDqjha1MsSl853Zwh+hxONmk5fSWy2y4zy
gPNpjlL7QUopXlO5Rh+eu4V8G0fnSLLN1u3Fm0yJ7+UpfWnxnaxKpo20HKT/C9Fi6I7os6BUKk1i
hehqpo6QqvwN3z/A2wC5X3tK2VXjOQthbVmoX8nzwaR6AZJrMR4d1O2lgj8jpXR19zNe7ylQdGIE
xoeyu1dHVAFl44795Gg8AttTCDw9BJ8Txa88cm7P2QjzYLDHt1sOt+ZirXzc2vKjX2EcuG7Sc2PA
ANvQSRqz1nyQtrPgl9ZelU5IHqnSOUiVldRwwC4AY4aKeaEmDtt9qzDQ8OV0zmtleNBRurEd2rfx
vz+a2YFd38MGsKvO+HDtlCNnL+XCaoyR28Tb89Ih934PQHz8dniio9eLwMHnIGvzTEitLeSbqQOE
AFrSFJDjQby+U7xd85NmWi7Ur53WuuniDe+y+GnqpT+KJ3k1m9V5iXnzMPWH6vHmpzcyePU8IxPt
gzdoW+7b1vqc1lnUF5Ya1K39ei7Fw+55dPRA+iKZg6mtLbwhh1Try+fNSJT1bmxCy/lUj0Q1kPVX
+tBHN8+M4jZxL9t2NfaG3vrUQee2EYObpmQ9oNaNkpzyhBcvbv7TY2b8En6R1gaKxSewapGqZyH5
khmp3IyDzmbormoD+O+RcXUSERoMnz8V9YB4EuT/H2LPRFhmEF/jMsCrkHFuF4MrgoogjfBT5tQp
TBwXiSjJaXFYHXGXD1MoxjpPQPiOPB5eHoEWOgDnznl+ewaEsbw5LBCDxzQxVTWtj8EnWzDKsq53
mPx551fh47Q23DpEoF+x/rQk62BqE6l8A+NMNel09s/AEHJpytGGRCaHv3mChCUv3+At7NcrDXwK
ngbZIteiHDsQrCpZQekO0rWqbhI0M0p7MbN3WQbw8vm+BE4K5lHBL5gxMAp2PxC6KijPnD6PSGHe
lIxFKkNvoDL4308kjJEld0qDTbGeDAlDUs9UcuSw1j7EM5GrM8pmcR9kdglHJtQZRH9ku7mYekGi
tafuEs6tzf+UoGqVrvsANR2q5gm6gF9wcoll/4zlssESXKLFv9TH6NFtcsjGqOlHCyo+bbebsgMW
UIPhB7IKQXKHS9bmTmBKCSvODSD9BjIcUt/4qsjeJ8QVPi+hx2EQ/83Ns3boa5KFqnFDD3LbfcRo
g+C0O2RXlGukdijnzMtiN2TmdLtr9CpD+7YqUQHKbwXpTZopj7xHs9fxI/93zCC2PGWOtSiihr5g
2xoXH16/6qn/XzHPVZJVXok9inGp61nhm+praDLfsZyrTMDgZMrV24GzNa7AKdOnzT2DXfY466vT
xVW2KevNU+Vka8+fgSuMqxbS9FMjGRWipQMEIuwmjq/KwfjZcG+/1rFd33USWkcWH3YtWHU4TOIE
5jOYJkOWAK0nQOAUf4RCGPBYpmYHSihj1MZPohrbMK7A/3rtGJK3HNJIZE587vDnbYj+XwetBD8d
RFDOLsqe3EfFZh9sgDZgnf/nM29gb8H+9VDnS7vVJgyOA6xMk9odmDAix+wp+7jcUXKLZxGJkQ0f
/82Q4cx9/QavM8m3H24tozckEcW4DvAYuTapeZWPMLwfnUBqZ5/2xtoP9vua267bGBCdXora1D+x
SwMXr9RxiaAUlyalbvRJ/R36/T/1+lJJJn3iKcnrsbu8kSZ89xz3JRlq8chTV+koL8PA8wYB9eNF
osR+Y4URA0pgDgvGWg0ahxZIa9dPSwrzNLUlzK5XXNBsSRKSwzL9kMNXLUN7IrsHnE9iAkNRYQL/
jHJxqkD8xSUAYF+gW7hJBPwKCnTL4WAruOwNd1dP9YT7f/6YdaeTQZQ6xUbS8rLvFNTC+8/o+gpf
GzLFKAmCIKydMK5Imfr9zZNE70L7Mw3LeDzlIGobIGEmi032s06chGtjpcUr9Wu1eFQpAr7t9zhg
Ud+udnnUCdgeLisUZRDLqiKNF2OohMFWTZ4G5h756eqdYdBcOmCgo/5wbArVG8Jlb+Lp8gGDlRGh
2YyK8oXseJhfXynvlSw0gymiMOV20CxXhT3rWiiUdtRPJe70ipLbjOBa9GWPul3LzG+x4yQYJ+Vo
kD0OC9Ry1zJDg/HjLU05xJRIP9hui9rzmzFQOMvcrYqqJKXQaaqx4TuKnBOXX1tQuVAmy6O40nq+
8rjajdxmEeYggzNzy3lVwWmPVvktwHNa4WhSXQeeWRc6qhYhIBR4kT6+i6UdP2CKCU7ADplWB/s3
CkC5Eyek5OhkZa4Jx6E43R8IzSpUCi1f3ems4ocDbXzn1wEsyWowtM1COhxnLnLvYoKnUQCkP65C
0ZHDi2y2pLTrJJtMPFzn2qgSgJZ1EJKLZcf4eW8uRmOy6WhsucBtByShfcbSquCMn9D12YclAIf8
hlSLkA5HbD0gp7MrhTPk2wJveNxX19lCNsU9CEeeRWr3at1J60Dv+QIdpnM1F+egnyd8CVkbTV+k
Dtf1MCGLd4vN9CZqw7wY/p/ydcjnThiqPT4ZuGRueZNgy+NgIE62KynHu6n0oj6FSfsKAaLppGbx
JKgD9YpUYQAKZH4jjiSKCWxH/qq7DpLpCcPKkeivtKvetNok+5+kHDzIDNoUPRvAo4axGvIfjj2G
SKIVkxqD4XUhEoUzWbrLfrq8i38yPyXrMlPxGlIZkniQ7Q9+ab497chSZFk91u5jFw62ani37aX1
aKvOs+oCdPxKIQtEXpS7z6U6Vc79wIxr7MkyW79zMatKWnybe+ZvkWz18osWPNXOMaVMC1IQp/VS
wGgKE3JgS7bAIh5EsX4FuoU+jKCXFaHcg4+XvpwFzcAAPdBF8+Bqx6zWXznFXV6wwI8xbugO9KUB
2Pl1WuQZAJ3RbrwQaakk0ZwZVw39W1Zj8EMntVMea8x1elnFiEL4W+ZAXBGeW+rVI+Xf3W1MnOIx
us/ng5ypygFnpjOrZtnzZTNiWdpJ/+xQOvUWp0fTtjtzXD6X4bK4Iz0853D3+o4I7hCillnVtjjt
ssZRoDt8MhP9qu8iEvxUGVJ9In20Pvyo0xipDe9JrDyIgFnNS09KP8IO/sqbgTrhxionofK9kZ0P
LGbKjPFCiGn2o9/xAVsu1mTuZ0rm2LahfIAYAP7ajeA8e19rCzVmrVTQuargGpZjJ4v2xI0V9JnP
pJGNdLHZByWniP1dxJJdfVZ9eKGIaLEuXBpVovHdhSHk/tsgqBWwdoHYSCi3pj67kslj+el0PPsb
PdwhD+mgcwEf00gGFSZzbmZBH923vDdUFnboGiCrlq6qo+2xjzMA12KQNHebs5ua36MxtpVEFFF7
5J+kSD/XEYl36sFE8JyeQTrAA9wU/lVDXU0rQqIJ7NBeWI3qr8Hcl/LTIzkUuncovdBHepItSozp
puLC4jcG+Yw1TobV83uPodJ+oLcWdbr2eNMAP0ma38g23DH/HlOs/vql2662PFTvKuiWowOMuYJe
2WsvtZQjuBZeTdtkAxqbGanBug7Q1TNDlZPMBXLkJ0AWNTBlRmd50mPaazomVV/rDZGx5Bzu2TPM
J1rLDeAkgfWod5saDiJOkFDGwde1w+6btTYjPa/zrWzbmjrw9iWXsUlTiJimWBvlH9mLFnzCtHgE
qq1F5+Pv7++PG9HHRdk+PhDNan5jbnqu9Np2YM3vneLnaLpLnX0e8j0crxz9Jkd9l04P+3AXsPyK
u95bcJK+XYmaZsjO/v97IOuBko+VHJOGMJaYedbe7lERlxFbZEMS/GZ0NTz7RX0NmUUEY/ENBrQA
+dcVvbC/ATK6vvAetUrkiSIfJR6bJD6UPdRXhEHnoi0SjYxSd8utthhSXVrriJMIY2i2WWV+BuaN
f73Fw+6nDKl0JPUe3OhA34L2UCGqFjP+BZnEZRGQjo/rIxEFtMNf88cgAZbOS6IokTTtSDNsVm+W
fvE37kscsLIRoVcSPfCciM8YiZVtgyHw9IbGRJbNnUBTUiX0Fmm+1qt2lEZBwdptjWsAs9ZmwSGw
DXfKczuScRgPmh7LRhmSalALm0kVe9moLzNrJWRq8x7vh0xd7ZRlveRces9LtOXEcb000V2jM7pD
SYbaf8IA+Cwj55L2RQpWRn+0jB3rY2mu1Nimnd7eADOxhbT07Q2le4j1JNbLBcArdR9EyJ7I2dEC
UJUFVba7gGHZuoLFdseiS/lxKgQeOTSl64w1m+E5SW/rfJqTZwGHUagHOQj9Xt0G3B5kQWbLmkLg
POiBiPHhbwEMS9OEqfTPxkHEukEai6rFtZWPvT8F+4Fek9VnL0zIpjVc7PCsob9hNhQEr3jxb3m2
XBjhPmqlhjebT/VQA1eFR7MCYuhX1BAaEhqISKy3gSErSqzWBEvw3HrmL6pGZNzRnmOcqGc3E9nJ
6rfdNdD5uzGUG3M3tjeF2gyExy/e1Umyrd1YskANbOC2xB6R0nN2ZU8znbzJoZxQ78Aalzwa9Ctm
3ZoxAro1RCALG9+ogtdDiSg/JsCm10MwB4Cp3+MlA9/MLO2WA8vWJiLwOxwftEpOyRhPqIuUxlfG
LSOtfNB6qaDJGqxfLKjJHL50s/LMxB60NExpAHu77mY5+6n9B0CssKyaj074AASMKZwMfU9Pjh0r
1tFRopp4Ud0p/kXRHy9k/dCpnootVWHOiFFqCH6CMIdNQyg7Hu9hYbYQlHIPEFwx8FA2iNtQY7wC
lvUJR5DknibNdOTFaf4e7OoLE1sqiccZMlfEuTRxyeDgWxdjHmcTIsAeT9DSnYgrkyrJC0AfrJvX
YkUKKSB7gmn+WCYAa7RCaDGPNLp7dnnO5uCxLYMR76VTf+ACLqHa1i0gKlcpm6CJCghNj0n+K5HC
ytGR15jPRaXKFVxhl4TrdT/VHFgSSW0UiGdCMvnnFP2kdopJKGKqPBl8rrDtstWUSJgJedHedooB
fUaf398NYWXYzbMnpoSKjsrMb0Cza9JsAdXa8+7OB0n3vzz9EonnOJwwu4YzXlqhsvHiklgOgUMt
TnMAhhC/Ig+j4jNcKP/KCf2tUsHMExW4piRq94NAKUHiqd+hbjZIeN3myCVMgzbai2uvaeeWE3yy
PE+rel1P/p4GWMp0w6KDGclwBDZA3NmycVKsiQXnTGk6f+OfRNfIJcXVJOPWWSBQ7Xo2RcL+W3zH
DjjtyOc5iu8y2keAIY8OJkyEYsNXaEyd6IWhtpDexBwUDLgzxcaS59YWlVzTxYB3wreGcayqlgHB
pgsKHwHHLYnsNCwKLngYwnjGI+Btt5KriuV+nDDYhi8f5kOOl2Vcl5eizGW/LizAlwgxeMZnbY+v
K68cikxnm+LpfR6lTsRqjEWxxcMQtfmkIQiRWfQJ1Ycstny6gX6BuNP77XkRJ8IE+Vjeqau9jTuA
nmWcua8FyxJnqq4BDga//ZemhEdajMxq+NzKs8P5bh5w/R/ap5Imn/o44TR7jEBFMaqmtD6k2FSf
MP6V4scOaqGzIj4J1IImXPHUBNQReGiU+VGnewOgfVAc9aZaqxu9rHCmc1mGOiPFv+RwR6xOBjkk
LvCxvlxrT0NqWj5Digm1rN0p6VZvu+d1hsdeE5nT9xXWZPk///D3bDJV8LfmSezPpFwjZD5K5KV4
taZdI1/ndHlE2kMNmDH/BMzYm1zfOC89rB/BMPXfWcBNsTQGqz24+6aIO5j5cQGU1pL87X1PqcbB
/c6XFZqKRyOUe1D67GI1K/+hma1CtxU4EEJStoQtDMGjvuqmmfV+HsqMu0XSDVC7wpeCwmlpzg0W
pXExksYm/l/PW/Vk2p4LQeBmh0r5rZLcSRy1KY6jOLMnJCPh+mugF/bcJPza6VzbAT2VhKVs0L3H
m2hv5JhKz5Zy50+DCbA81Md9/h/viRCjs1e9AmIZbz0sVu8OuQ3xfoLSqEKZ5j54Icj8dSzGWF1u
xCmjeqI5d9gd72VH7lijtanoFdtf1j5bwiWsS1weZOyr+86PYtUSx63XoWkOgR0tFhe1qfslqVfo
rShqsQofyI9oAHdYW+L6Tgy3bvbi3FHfJDiPKcojwCwVK7gEkWWfYvtD8K0PZ34+yLtfi6SEkeeG
R/8c7yGXS2CVioh9xc+cR+Stv5x3FQfaAc9d8KCMfP/gtfJX4hmGqALTqy2I5ntiUJbwXd9IDaDD
2KvAinlecP3MRLzz6vJZpHB7Ap+EYlCE7tZPJTjAjqIQeq25hwNCSsZDmxM7VJvIfZAzq3yY1olV
NLuxgggV6e5tGM3Ex3pfVGgrLxVjb60iuQY7O20PyBKKJTD1PJUUi504WbwxySnGURZRhf5SkJNC
45viizJMeyibQhTtZAfCz5jFBgf3kLtHcxrl4be5IKn3JmiK3d3RkSS3mAxyvCtreLGnApOXXpBW
Kfl/fSCK0MZsuAhLCP+VfcK3L+fTkhE4a+1Srh65ZZRNlVKdrKkVf3Ae4TvmRvS1a+WHtmjZmpZ2
TdbsX8s6rG66L203ryV3gmPhmfa6uNSggPJcHxpJ6FuS3NYddyOVsbkJRRKsbVX63kNgEapblpgx
U/CO0LkUNqyeaSL6+u0SB55rkO0KliWaXO98/pXo5FBoizdnb296VHP2qwQHM+EB4ITmH2wgP2pl
zv3XaWF22RA3xbofMjGc7d9xU3OnfRkfYp0qqY5FowYcFUup/xfk7yWDzrIVg7IIbBAE6KAwczRR
hQTvIINMJ2X2V+sMuNkphxMB7YiElSKXm7az4I1q4WF3Iggh24gySVnYi7R4a5onhu1v4WiLMarb
mFusDgk/Knzy83wNgp6u66DFSyifRQYcDtfPcKjOBg9rUdEH82+vrWHm44w42MtINtKOmqPRroFD
qMZWZcsDwUdFBcgxi51QFCw/PAZPnN4gbXsCTQ+c7dsFUqsnDX3mmOJTKqba+/xzyyig89cnH7uM
zILVFKUxawjVlEQzUDRIDZqnCBdgV/7kDbY+xf2VjNBkl5SO2wyBj0B6aLDlkzIqUFh/v7oeKnNw
kFmPEC6PaGnER1k3RJ8nDC5MVvKs9VYtZitjcfKHwBmxKRhVXgnnJAW58JHtiPifQQvh5B00LX7J
u2aMnUP2tZYgIBCMp934QNuyGMydIraND3gboSjft2Er84t9mKke4ijuKIshLHCs5tZGtjGHdCGY
nCgAfyACOATn0wtgliwPA5jXlbh5s00gs9eSEMYM71sJmHRKU82OCaa3QZW8QT7QbPDmJkLh2AJz
oV8JUQreM2OzKV0BxIBUzc4mWRNUR+o14xO4e8X8gidtU5UUjBTsmm5Z5Md/TR+0VIZQEGnm+rI7
7g6AGfYsbV1bPl624VqO8AF3iFdQ3iRtf6KYiLoIrTM+S9pftUs9Nl3pTjmg/4AxgYKW2Giq9F2y
cvzWjnZZtn6fk84K8HwEdjit/YkaFNahVhSeXa1UDzn2oOBSLfH1YpajCZVtwYmH+E1eGh8zbunn
Ytqovf2+dIkaf1fJ8NeesUCGyT8L+oQKk2+WowqtDiKad/2DvoWCim8j4+9p/+1gKkofGuZemW6d
ke6B2H+rCYBtCXw8498xgjInE2CC+tkgCsWiZQNDgyv/Eu8ynjc7JfI3vp6H4JMec5Bhifg/hrE7
IESvJevJsyicH2cqPVuGdaDOz9k8qV4/LGHJpTeWLj3egB32wVpodHl51KNNcTDdcHsDa1voz3zo
y6aXZud/5FLhrMDzjj1lxPI65rBW9p4BLgorbsNK1TZfENe2xyNk1kgv/tINx5e8u2FCio4dA6Io
E51LXaWpKKy2RMsBhC1eOMR2+jIFLn08kvgiMDMtA24PEGXUlK3Fr6Wnq6RBuAVYgnIHHA8F5e7L
Jz634kQm2Au+6bACApNuHHEaYOzfU/myNBjzY1o53v8h9DEnUkT5Qk28PiCFhitV0X6wf9+AF/D2
KyWbjj7mfyYEr/z0vsf9D05LunV+17pqCqgAwDu3JzGAoAMR5di4iQ4X8KXlpABrY52SB06D3hX9
gYKxVedCyg9ZPTRDzswcE5hvf3UfTto14VSTmnWfhlNDOyiiUL30gFqE9OWAuZG4c+FjkDeV1swO
14UO4QSBwJmMk3C65uGlm/4TXzyEb2/6I4QBf9Yh0DFhAIiHd2DR8u97K72P+nzQlyzMzLY/GXxL
Aob1wEgsc7DyZ4xagao/X2IOfhkK1gRo89aRw883Q4TYmqZu5R3OwkQKdSrBwgfjtuO1LcstWemq
sKaWD8kXieHch4Gm63OEIDbZ9K8p6oKNhQ7mpnNLETMfJvsdI0K++1xPxoJzxCXglWe0eFs9Gbf2
RUBrBH0ARI0rSqwp9E/t7rxQ4k0m9lDQXV7xQN6jdOaCb7w+jYcqILHvhB/WWOiRomBNlspQhnUl
8FUwhoRn84EkIA+RCEhFZSdALW75A5cX4JiGF58jF2lM0wducJz/65+IAHAby34ekb6aB5ulrAvO
4xvAq7hLhhT1GdTGCqh6ZVVM4BfZRNFGCQUMNj3lw54TQIt1gl/aJLrEjZFLA4CkS7wbQK8SWU1R
AO1EtZxZyZoWMRoBq2kjJx3prIYJd5Q12ENl3Xv3zrCgHayZWLfAWQ/SbkmrFmn7yoV9LkCiHmmz
dU/di95Z//y1gNyulK67/7graaawa41ScQ2+P2wTHiDI+l+Io5Ll526huCSl9J5m8Im3eiV98pUi
P6sfMQOW679E75kR5+yMcWMGR/pyLHB0s3j3aSoQwry9EPb1s1nZ0cXrGwrVnPZHgld7dVKUthRZ
s0fU9kjto1klwWNCDV9a3A8B8ANv6jcrVu7YFD78mVQC+ZlFcZTy/J5lE0cBtf1SuZWl9IsuFrZ4
CKHnWyejIfltWLfPmf/4XyaTjlUENLVGCdy8tX+19lLtZWZ5OHKpJDOxJLYKyBvHW/9NdxxhLpCu
AKO+vyc/4AeCQmVJVFwzorehe6SK77GRgpn/72EvkKs4HRg/Uu/6HgJ19duKua2qwD82mqm5W2zY
BTE4YJcIsc7O/VzqXiHUZkLBtizrwW95hSj9lr6mfjBTJpBl9gitGwJMkETlkyxKdcSs6x+Q/4zu
OalQ6v8JO24sEKz9MwfY27gSnqFlc5ZyEshXc4bjJ/O0AeigSu0BD7fzfMfP4W2BdUEYdp4K3DZH
b7uPm0oUqQ+5OzTQSERySbVAttX+0NHnJVG3ISiJcDJ+2ocIEZY2s67qwBfXb+UW3z8l4t7IGPh3
0XgCmUUcMyWwsmEtLy4h7w4+AQBeunIHR7haA5lMCIVVM/UH7mIA/YcSU/ftF0PZ0SYcF0mTZhQR
ULdCBaYXq4YLUVNWhd28YglmMY4Nl33LDv/3eK8dY7WEKDWxfCyWhtW+IZIhkoKMXGC5i0TL0rmm
tMtTc0MWK8TpeN4Iyvt7m3L148en7ySDynyfvycBP7KblFLLksKdKWz2DGRaMzM1Dzv7XQH8HEwm
+lMHKa1/8E8kgmTgoU+xngELviZW+eV7Fk/OsTX6ScNDxXqdZtIdqEbF6qC9ZOyhSLjbjw65XBSU
Xp4u7f0VlaxhX7a8NAjvy1VjQ95D40+omM+3T0Qkw0/9dkS6xREt3dagflVm/1XPaQz0jWTvbAZM
G+0Ivom2fmBqd9eEqYod1tKw5hPDhgSaXAvM008e2vsM+QuSc8ozSc79v5/FtWzJHqDz7gdwGtwf
xYmpXSngJNnwL9PAjdEuBdnP1dHMC06YlSQQZJeNHlWeJS7riKbti0cgBg0KsO/ZHpsOVagpsolg
hc762VsoPC53okesFh23sYI/pQClyn4+W67Usom3oEAY7Gh9d2EODaElJcrAX+KY2S0tgfOwmh6o
0pRFqhsqVnx3vuCafrkjtFjsAD5nuSLO7g542wai76VAMqfvbElxwrfP+vNbBkTAj4r/aYke7TWR
kvDpAq9yOkLdSRzPaHT5mL8C1ys37PB6Q/hIuWtur38lWBlN0u5rtTBf+WuKe6W8TxcnekVBI3xn
z1rAenouEU8PxVYoQNDffPQM+8iIGk1mQXM1tpPW1EwITvQznAQQUXWslD3KJ1GC9mnp4qW2k5tP
BE/w3hB5PwuGwCQtEQz9iX2MRTt7L0EFXV66JLeYjOSEJgbI1sVkdB/pf+kD8u49L+JLCNJPWR0h
zsym8LlMFUpWvLLopLfKau72OTRO2+Z9e7+zi+c9mQ6ET/t2rVd9t5nUt5weFJEdiaOxUfjI4+w4
GCa2zptdym4lQ2noPGHG6tVrTMIPl9pwYb/F5ZLosEhlbRuOWMzrJg3Z9V7XD4EqxGjMrJYuBcvI
O7my2yYCWVlCKm3bryfSCeAg8lZejilbte0+SB/V6DR+fdl6Gmj91QsnGy8oX0+mGzBTjoUzZQQr
LcoovJO6rq3GG5DQhkrpcLM3/pJXXPmO300gvkF2XZr8S1/y/f27qa29NpKvkl91Q+AhzmK3640n
FigRLGIXyg89z5a+tq2KLV8RH6AuvSJLpV6F3JuY1QgCU1ODWfApLF1A1BJ7ro6upFJrd834+4wE
nkhyop5tNO6SFvLVrg7M2y9FdpAmA/fCYjd11r6M0j31W1t0478HZjvq5kDThQdgZEQ3rTU3rSlC
uFd+S5IVIP9AVZn1L9HFqFsywytkKHtV2OEZFdGzaLyPDBHt5nxv02W9MvTjqMDpQVY9k4iCyLuV
d3UfaUw9K2KNW+39pFh5XiE9WToIt3p4USUx9KT7r1d2COdRZ4tHZF5WzKKjMfeNOA9s/71ga69R
hXz49O7SKU7oiZJIKLuxy21pgwIgJzQgJ0ld4dp21ZT8rxPBsqArgasS7UECAkkFdg1rfk99ewdp
WERWaJRGU6BfgivcQ+WaFIqLfxv9HeVx2t9ibb0K/YyRni70gfr/4DgTBb6ZiwJj8KQPEDAc6X9h
a29hCLrftw7xJ15unMQghCzHyrAaCgBGz7gFQc23Jufe+Jff+MZm39f5iNHysz+q7lyuUISrXiag
m40mh3VaIDe2d+bN1nv5Z5Wyqw7C3V9LGNt4KGv7kprY0Q5nQUe8p9Tp6x2+W6a06HJ6umpjSOFR
I3Q0yog5YcriKcu8RivVLI7qB8otqAv3jbrlIJyrm4sKBba44+w1KNhdmhrrJKXxjT5JS6jQ7X1+
GsV7JvGx8Y29GXHOopzbVOIFc4BMzfJB5yW6hMB0WnNJjmnmP5I2Ix/HL8iluIUgHcuWFn9N7a9n
7tbgFBBkjwrvSMw9jgRR99ix8v8UpGo2kJkNNeubDLcKTUnjLIxZhfTs8sPopLBA0DU5ULz7fNTh
5N/CYWFsCtZjm8VND5P+iu1qRdRC2WpA2Ur+pmRwZq5Jj1ulkGyfJ2LKDPUbJ/PyYou4tdNhXTPZ
egwWF7ETrXRnCRuSQnbbpIOS1Yoer3mjTTFHPXzM67Xz6qvzeq6QeIe9lU5Ba7F8oC4CiyIJ12ai
rjuFjhnIB+71cstNS88+FGEUVrWWtSFu0PaCFzMh9upz9nYK9itOPj1WARN0FpEWQNFN3zShtkue
6y1XLgi432CJ8EiWjepqWLuuo0kku8H45SQNd8JlY/9OsiyZun45vg9tBReXOU6rg9v1T3uHtpxQ
i3IAvYUcp9a4ltGzMhVccW1LYNxOa6UE67piATTfud4EbNAUo0F1oZS2baNC5EwTnEV076zZNZe+
GdpoRsEU9lU+XEId4yfZJnwg30fuzCIt37Y6RNvyDOmnP+EQjF1AylannSPUZ1miAd7vAi9C8Ixt
c5fX0muhS9MC2oFJgLYlEIuiDoohUH2/rQBJBVtGpIh3UgSJNJJ2OZh9IDdQbDq+6TJdvfIc3/iu
q3o5jNjHVtuHUU0VZ7ZcTBgIePYY4I+Y3UinO5znY2q5bEjZJkeq+IbHpSxzaC24t3JQ41EFK9Y5
XDUuv34gmcKkhwcqnmGRg52kqbb/rI0u8hDcHH/oiK71tq2T9MmonUXAdE82KCM/WGSt1zmK1ClP
XAMVpuYmrrHoy8c9glBHyG6/okRtuga3XiOAUXs29Sqi5EzcALZfx7PGH8PQZnmfTWmhSw/UNysb
AhqvvUnyUoU7fSm64qG9Al5yU91e09hCbcKokwu/8iDYyDjbz7QQheuBJjPlSK3c0IUy5cdcHQzr
5WUuQm89GZkdxhN6n/Zs4dFnuK9wKgEayStK90N4e4JF/kHx3//zBp9nq9Fefuci05SNtFpzkH/s
NcVQlrM4xFBh9T0udQHpNX6ThRcNbj0cbRMug5hRa83ODrp+xRjXOTkGpSsevyRwKes4+h48Z4of
4pnSGJXkt5nmeTa2uoqYgzrqdOP7dbSH2HizHL0LQ64LBNW5njwVJiLcS8VCsxnmw+rUHiG/6vnL
4g32jP0mEVGwfQi4w2gPIwkgsHxRUI0WtoHGulsrleb2/nefkdB+IWlYDeTROb4YM212PLIzCO5h
MaK/mxXKorAjKyfbKhap2KGgQlx0EKx/d0YuVsz4wYmK7FVgAoVgGi6oBnYF4Ib0GU6kqle26ZtQ
fEBiiaVIKOexATDKgQY3kpApdjkbYv7Y8X/jX6STvyFXdrLTJfCMDLSCHGKUpLsx4ylE2hpIl4tL
VWIrL/nag3yUJjfzcKkrb7fmXlziyTrffZbez3C/ef/tlW2gQYCr2YAzl+QUaVP56gwowwxl4A8I
O1zQ3TeJF1zwVOV7/XwjC/pRx1WBT41uFlqXeonrjAf8auSkUbcojnxPurET9n+M44wZxYgtlYAW
tsAH5U8ITpCGEmFtpBC/E7OF01OGkGvlxt4scKAGpcHRYSpyvKTLypF/CAzprBb3+8HKObFpNzsY
oNzqZfDwn1N4gcj+XqfHoqJ7b04TD5VYcOnGJIbYJzgBCnpssKiO2HeZFfA4LCsd+v3r9RyHJ9C5
bNTcefMRIbx2XugnKjzOKdy/uCjW2O+Dv0ieVLnIZZ4K6oG/BCcVVJxGbHS0ZOMZu491zeRnTZ4u
yCHEhokpg9Ow9SHYceDuZ13AOfHXjHlHcYUfPiMYbx5zAgZrt66IRMIeunt623IVX+dP1EPnoYP6
aKE7gW041T+XTU7IKjkPPiaTI045++A/h5dRjh7Tgc+zVqdsQmI0LHM8NFk4VtwN93owuU/q7YkU
OxFYLwUYGRnw4/oO5fn+22y/A67zxOtMVJQl4MGFFfmMJxDVmMi77mSPKfZALZhlaCB9HTk3RkJv
+1yIkwVn7/p25hDbhwtTod0G5LNJzfkGISZmieX14hjY3qdcVR5UZUltdeaW/BZRU7kc4GeNOCv8
Y63E/3QRmL4Efnzyv2K1MVvf+LnWVf+nOXpGMQbpnC/EW3/WVRYIeh88zk1l890LhC0Nt4E9HuZG
V+g2y+8EyAoT0POuAe5ArSpi8YRt9J3pYeHnilgjJOfYrjRctVIG9GRyu1CId3/ZIKn5IiX6/PY5
CcEX8tdYhSEY8ECLG5dZ1dU5bU2+rFISoWwD/eDjmxfRhS1Y7rzfVSsD9hXlLHWO+yBOrIHbxP8N
HEDsi1dMZTxbf9lUwciWkP1uKEI8zh03k5fka3N/iRjxfcBN9K+yp3GxjR4MSl42isYh0uDZVqQd
jABP78Rnv9fIB6JOWXuz8s/xVtWS6nuLXNAj2LgKocMy15iv+Qj9L/CX2tbMAFvPuqzlHZ9xCyoL
ZDjjavQjMQvlQiNNuwvTtoxh+vlgXE43mBzB5eVzfZUjymjfPlQf+FRnIqSSF11flspJfFAkICcF
Uu8tpwiGWgrfHg5wNtC9rzF1S0zWFfXv8zKTRfAkB663ragHs/SPE2QciCWxSsImgL1cZ8VzkuUF
ziyJasMd5OhM1N+o5ijaOpOIYaTVXJdJSsHb19yGm6+lLA0nwd126ZoJS8hziZJDsmxN5b8pg6mK
3HYNrgwmrp/xKfa6p0imMIcJKoWsFWn5+LjixXCjJC0cqDR1PteB3DqIszk6eNZ1L88vyCjminJm
dL0DG/r+XrMT2ZPsNdYgzsXhf+XGnqw7vWHCkAXTVcR0W8xNdTdNHjgt8/mGLrInzRY/Y2uBiOko
QN+6aALo8vxCT3mqd6e3Cl+48La4995cP8TEehSNg/rDxFbG6Pa/0rzydqcJRykeEkppNJkFmPAM
fS2fhLv/PxREvOSTzlHmD/OV7zNdlrsuazaZKb6JKSjEulgzqbgicNv5f2guGsyyPZioJlYkEWW+
qTqaMNMMAvZ1XD4qfwdM82OuQlJ4Lam6WDwaOXNzpU+UiwT/DS+PmNUY/7wEWXTOmIYqBXSA1rVu
GSE3G+d8zbXiPBL1e4j1O4O73tPpiWs+OA2IJrOgnZuBPp/t7GPqffB5rP5f20lHlP7RuK1/jzj8
1xvSrFbUC1NHIQ9W62PobSwIju3Mq4jVQVHe8Sy18/s+O1iMmcxxRQsnnEEm7MrTsKrg2JPXPmA2
RPb9Zs2dBXEJRsBPUJmaEU/Nk4/O1JpJ5IVVUCKsWzAcyVYlsfiL1MDNIsdRA7tZfn+g0QbJ7wxQ
5cDVipIG+px6GMLV4NmKAkaMWVQiSfoeDKn11Fgv0aYpayHHRylJbi20CLznksiLsgBnBdJDZOEu
Fs8zRM349KqNVYCHDpjrE6IZqDn6pIQuMuc0iV+n0u2IQ6q29JYpovIKGd6nNadm16IX/du7gO1w
cLefu7lSO6o3MZByyUHY03CsBM+PPwPsXlPpzYF2nEMObveghI53r9w18S7PBdzzF+8VK3h0mflC
CNav2SdrSvBJwtCXhsdAE/2nG37j6mI5WwSLiB4HpGm8t8d8ROCX6oSZBeCGRnuWvqg8jLhI8zzG
abyfysyMQIhXx9uddxRsW79mkemo88KqCsha0j/fvghom31BJPl/NMWg55PDpKoFJkewKFBj9iLb
3PjS8KiLvFUFy+ufd1q6qvUAOtnHNp0sDmUl/bnbHV5dJHmowin2Plti1t0ERUavYwMgI+AS8Neo
x/74WPPODTPcHi3cm4QpBNZJwnSLxVyK2ta5F0vFpLTn9oC14fEmZ8mjZcSxHP/DanyZlKRlkWEu
C1SF+VnUeyxzN3lamDZ3Hz+zJTqTznzFFvSrxy5JJY4CsqqAMZ135W+JOESBztrJCTFyAKqCD8u8
qNpnbHKNEMqSzhYlNXkjlC0i+mWIAqabOt6CA3QdRbqvvicvgblh210aQoqw+NHty2JP9tU+3zqD
MHTqiD0YpRW60Xem0/FaJuZHFVISq2mOM+zTI7U+zwi2GDEBxUtB7dJA+lhvtnqVxUdkn9goAmml
9YfNaG6EnOSKtWGUaIUKt1Cs5o3g6rHuJXCHnER4/JxEoFZu0rOW6YmcHf5PMxonq+sB+WioM+CM
cB8FkqGWFa7E9YkSGfuk/+a0itsZDT021ok9CWEVwW298jzBGYUvkldL5UxuKyz/KjOOifF2ZPRH
Zvmo9NnOE1+RBGFNGb9LRSWu1Lyo5fTrpMnub2S/Vi7v/H9RdU9RnjwbL4+5+ivvRD6ogzUNydD0
gJBo8va13MyjGtXEICxJFt+Ayvl4RxF/GhTEhoAkF4yunr+ubc0+U0ov9iTBoG6E9NTWpOcIMIDs
kH0rpwXqVAZBCpdjsGFDx1u+FlfZAJjBJsKt8EIoDAKmpmcLDRagswoKYBP4KyQZteIxyInMvO35
B2cW+9+z5h7gt7tAFkZUm136wupsbCZfB5d+ga8utjlH+GKp2h8I/d6Igk3K46+/a0Fh5521Kg4+
f9JUKUHUarsao1pySAuOaSqribSWJk/f5l5Ty0k31msXLxLJeQn2ACqQdPgWx115KQX7heL3gXkL
rs6Jj8YfMvPdDTfeG1D2GfEOXa23NAPA5nGlZp3MY+lMpHPVlfusqidVezj8ggTfKfWp8o7Ex2yu
1LrPyDIt2Ex9TUCY3Ndfih83Ns4WD8bonwxvtEWHRxpcf5iBPUoqT6+yrfldUncee1lERDoSyM53
8ptBSDBmbDzBF8Wbfd5I+U1OicwITVKLpeP9Bew1t8kQhj1arE4qsR5w72latr7HK07BfOvJaFvk
TUS2UYK0idDHI+mtMKGuWxh9llBaWQLf+9gEu2qGos0BC/o4jD9XrR0atbLhKsbQTXpKUx2FhsBq
tp1OyTM+ppJFID+glL/7o4peI9+gFojxZkIYZ3Dth/Er7/wmSSzzy7+4hXW6JsfN6PdaCgr4PWKi
y9TUGgnyvXKBeI+A1it8lpVCc1a1HQVN/VMf/XgHDprxR6K4Gc8l3dVB7zSnm8x9hCbLqYXnl9DO
QNN1Qi2rRFIx5ObSeXDA9vtn99FtvU2bMgle/tsDDsby4xomXbCuWt3p9y+HfgFMwAdi1hEcIyct
cZMATzd5j3Du91/j4qUIgWC1tPj5aTBPujhBdjZnOcx0guon0KM3LFgemftg9/NuIkMXMLGfEB/Q
BrRm+RP0XsgjM6zltdlx9Y1f+6onDNVBUxY3m5RT/SNUhsOzT01BFdLDxA/7kQZNzh7c23NUnCqA
ADc1+S9eIldNWXPitEDbLazEaUg5R5GOhLQ3vrjo5Y2+yKfA7uvpxR/GlHzVMpq/NUSdHYVNl6ey
T4vOUqXFvisvPsTD6YNICziN8+6q4dk+CEnIzDcwEAwSCVXxmb6Nybdt/uwezBuLRokxcnE3hYmk
2dY0R6+OWAdOVATANhfKlQ/z44eeffqxkvIKkOL3ICefd+pfDAL0rLO80B9GNZ5WvEyuPVENf49Y
LNN25H51KpGyF4NGW9nMPHN+ii2u8ldplxE0EI9mStgHD0dteSdhhjTP7SWwUz340jYc3Rkgb77L
RKNdP5fZ6ewMRgW7+buHAeBfxz4f2/r7VHYcBaw+ixMXKbyuMgglooiAxL5gdkm5akYXHTXDaXwp
aESx+Oy/vYcw7n5CSX7F0Z9AtjXbzCKyDjGf/yTzg8QaU4ix09zxmQeXpbZMWGycPvRCAdsA32w+
ZHc9YNa0V2fP2zghS5r+Ryo3ui5w7KiFCe4u0wyPnKJJshMoSw2dray2w0jMO2N0xmX8KyKy8fpa
uG597x1KNcR8CrtyBJQ7Rv5w40xsIdgb141XVGdsrV/030CMdhRUTTHXOLxuVQ6xb0q2Z6Wz3OcR
MJ2Gq5fUCUAKPAYoTn01tvgz2djh+lgmIcgZJx34RVbPD7uc+YSz27pVYxIsnNwtuZAt2KyHdq7/
UXJ+VJFj+GA5cEzLj4d7k2iD4QBqRTJDWT0GFvAK0gdu347RDhIMLVThNUl3TpBeqp/bLfhhflN0
giLMktXBAqVRMfmFbu+fy+BCXcXzfpilpHAkBQsK670e2yhJBhfBfhEew3G+gWNISlWl1Z1Qu1k0
8K8il0F7LTxTonOVTMEi+tfe0wEwFW06l+6upV3XTfXL8guJvVI4jfZ9Co7MhfTCmtd7qyy6QR1E
tdgJv/7Iqoo6nKjGVpuiWHRz6sL/rtfeoMZw5MTBrCsZTziWTRQUCoxc4xtbG/098Dyc8nb8eeVo
pgR7mSHXwSToqOLFnGbCAUS+q2GASi/2fjfdQLvkisIPVaCwZ+Xvxv7soRwZG0HuUgU6MRLjmXkP
dVGLtIT3vHZoc6VfHYHHvNx1Fv+Hvg/EryI0wH6FoTd8NFp7qQpdfWJtu/Y+KLokLaufo6HOYz+A
+yFHMsUNLXUExJv49U8xt5eoKNw1btbO6Gid66P/AgM7DvVtDic+xScDHBEOtNsx7Pkv+lRJ54vu
RvBEavhZE7WPmP2JQmrDS61sxqLhAyYQusc8xeJZTAO2KWePJ+y9udPJ/rsHfOPCQjFLwtSX6O3I
yrKc4v820OpvqRtNZOuuMc4ss7qb5VrQxrWN3AsLM6Urzedy8d7tw2T81i0X4pSI2D6fp4JaKnKt
+wLGW+WbYao5zt+igLjqwZ7FkX/62Rk01vlFifZ9mEMTcCdU20lTqi/NeGG2lbDjgpI5jNjGWzm2
U+nySEOQqP5Ng+xJmc3Gw1/fsOfgwn5aESjVZg4zl4F2fNegaWJRTDQQgbcp/MYLHboOEhvBssvN
fXCRohyaHxbHKLRxa3CYHiuAWwG7v0RnMWiC5Dinb3TkQT1qS49sxrpHXyhNrYqqYlKnReKzlvYx
aA1WTduxZ7mdFuQdwQdvW9gx86p2Dch1OUKMkr+TWvMBjNPNcW6q5x/IYJcp97Y2ecik83E4jkeE
Lpuo1KB9l03tu0BMTPLk1DoJP094YBrNvbz2b2EddlDo4O+TMbX3rALL2Br88mtiy7EbdZDYCoun
xbs7njJ64SMD6B2Zms7tefFIfQfuOGiQIvQZlqAXo5XrKDYGwQcCOIFgaZsSbpPUw+ygrrXv/os+
/rp+8y60df6k5QBNst05FBBR39/rAnAD9OuYUy7b/L8WA04+nUqIhuosPxR8AougN7CTuwqsDYaK
MpXEZ13s9ltq7emh/e4T56aVi9YIJScz46NDLdZBdymAYlLUrxpKq2nSiNFzUFRtPEW6URJSGAgF
UfDZ+/wv8YaesqIi84zl/PZ2DhR5Ec9MjsuqfZrty/udPV9o1rYqELgg/VUmRAkOerkr4fCJLXfI
uTciGfcwu7znU+ccUcW2poX3gG87Uto0cZGOPPdpAHNvwR8ulzM060zRzFAUYrp1h1ngx131p537
NHsmK6RPiWC0dtAV6OXNzma81Tqo5Udr+FN1NmU95ajIQ1qlu7svOJXa/mWeh+DtGAVcl+VrR9YP
d/BNiFTjCtmugU/Jpw7QYwAAcfGv5rscdixNMs/Apk5GJtl2jciillzpug/vQ5RJFI/wcbMNLakw
8jWQd7AnJxfK+sIVqj8I3NildDaMAUpTJbUyo5LAN91AZyAsFigNqtQO2Nrhw7J0ei/W6dGvRYz/
nIA0THkbI9XrYhoKFxoEWQme6sN4m7g6OsiXSrzdhuhDyOAJyj+6BUeNrn/Fvsj+VboSM7n3q4p3
kxPvuyxLFlPydgNCh8NxXiUnRjZq3EsSGUTQ4d9biFOfGIUzp95q9zm5Oam/PprmRBZ2SVLZG0zz
HhjhBpFpnknlEF9RE1zZnGtJIqxkzMFNIPgNlg41z0iqAXhvCI5nl4t1iz26AtWk4O8enlLEmtEB
v1qw2Y28U91ZjZVG+WUwcP0CwS5lA4pToet4jejPBFgc+Ik5amusx6/NUiB7/SWMojYbViWwuxr3
8qIQS5RoNLvZvEqEa5e2YgHvb4Q3vJYDQvTNlXe6LdrKsHAzBnAdODx2p5d4ZxSCrtPBjISifU67
c033N9OfNuaGbCXcFq4sqtePGMFfGn69HMKd72PWlYMi0wHBx3s3vbBBhirMKzWIwT3L5wCSyYuz
JaW4wHqhOrybJ+38yNq2Iga/Yh5wd1WSfc6lJfcpijTvhJjenCvrRRiCqmNive8QMTjYepcSQlPF
DBIjH50JEYa1DaYVZtxAxJTZjA0bOfRb+WIPH3hExsVO9h5lW38EY38ErS/P9IfMSfp/sNOc+Sr2
PpQKKxWOJakFWqkhGuNajljgjvb3SVLVpdypGRhrKGrUULxofxXTsIjhtC7oPAEdjJCxZBPCzm04
bz7hZw7+n/Ns4+77tRAqYi5EDwL9pH/SKdXwh1xFZOzj/BYY02Z3oklg5jOv2pL80dimdPnsSF5l
E7LEl9sY/RANV0Kf/XBrDO9BBrHa9vz3vX+LpV/2EMmMyrbTaxJVz1Lb6FNMS1dtrqN4bnJFpN6n
ifQm22rswjpcRdMbwENruSxHhVyuOn1RelOJiKMwIEBpt49PqNfVRT9ysrPS4l/c7joAnkIpbSNE
puaaHSQnN8eDH8rpEspsiSKhdHkXljNUh0NltQr1Xuh+A/iGTIJU7cT58ypS2QxmckESMF15Untd
j855sK9HmqZZyRRCGb7jQjZ8gLYCnL61LLHoDosZGomEjgGjhMLZhcQ7LsI3Spi0vQGpVhQjE9Nj
L7DHgwTiPq8OWovN27WdEcrljHmvhx8nUfjaeto9WHF8W8GlCGCW8GrUtUCRZ4gMdP0YViFRedDl
5MGher+hVViil/vB7Eqs794PuqpVe3PrJs1jqR27ddgetDtnnEnrKsivY1oPNMi5i2uE8IxfPAG4
t4/7Z17qFAIu0GrZXSZ+gd8Vt21AI8o2frYhpQVUGzykG4bKF5bCrdE8cgTGUDZgzxB+42m0FaNq
2zihUraeTzPizHcgCT5k5G08yFMSfCI20hP+4wMLtSQdgqkU34P2tvVbyFCuSkK6lLBx/ZeFqAxp
L/WYuzi+l9KEWtrGMem5DGy6sFoo1OKI8bN2AFnsZou9OLHMZcjSTGG55FwMZ0OVfJG56FdK4D9K
692pC+djF8MlDqlYMrbSM7UyMSI4KqCAAhtc0sjEzs6SKFlzi5HdLMrYhUzjmvVDNkyouhI9t+cm
fvszPl+xwa8agUiCFQ9zoRIfHS90R0YZnAa7j32X8Pq0kxvDNZnfsvBcfRMhfyYKLaciecIYSPZd
2cYiLwG3cRP4zF9ihLW2UvzPlEfV17Br78ni3olmlUvs64Gd/SlL732jreXJ+L5hJpvDETGiVRmt
RbJpvCgI5/9Aliqh5qTnIRMek7xKCZSLKlEXWNgrS6HjKZQsuAN7h52hCG9xMKTCOy4oCo4dmx3S
VUxKL8J2KgCXgn8sDEMSj5MpBQIqtOb0UUOVAcMMTs3iUjqjEIdCTeYobNcjneYukMf7x6fTyi4y
gOoq4zJQmjoBQarQilkIymECkuvRUqgndn0ePOuOu7Rqvs7aYwUE3zCTr+stOoJr88NfkLY3hO2E
22Ci7Ko9ixVgJ646Pd9TMvCh18G1lhoStcY8JQdGMTvIiExWolFRSEmFbS5TgtD58lZ++8nFXEk7
q4W395h4X//ybTGzgpJ6F7BaIB789pGiBZ8xyOgWR0QQXSgz6a1iApvwJcHUUIc6d/Ck+OIiT2wn
6n0kTnRdbOyfWoVu3pbODam0MrFCt7DqqNKBxLpLPoycyhF3yXvE24W0CW81JizC7wnhBrDTKzTt
8ntrL9tP94TRD5tal3wSR2DrmZ2ioUaLvdM2UtXy/JHX1IZRyJRkgrLQ0q5vER+gi0BkvWAaUoxS
4Spo05LjDqoqYIhZuBUqQzIDUS+YzBjS/leC2crNNC/80XX9ts1xwOfifmd3I+mf/6d0k/PKThTf
aSTkoFLBrZp/rV6GKSutwYk7KeyISCiIxusAEeaf8229Kw89el39smXlAC4c3HFXj5lCniiveVaJ
5CiwtUfeNWEG/wFY64dF6rVyoEdqsU2z1AkD1NJheZ5NqKWMyQhUMIHs9JJIQGGcGPgVBLpBG1Am
WxjjSLLJUq9wUvqWivNoOeXln2niQq57z3YgITovEIXOKIN6ufRxFYVWWqf0xsp8/XsEjr20i15v
LBCRvT3Fq/cB6sHApP71JFjuQQuSLHUONMlqcWUMMMzjgZHfbqAaakx+cQs1lqGpn1XUyLpKAcEm
VEwjtv1Kw94KE8JRAv+JcuaSIWptKFsFIX3SMH5/xuiybGPd17D9mtLBG4wkcpWgQ2fjoT76FEgg
VP9FmvyxKLrPKuLC6YZCn+7nnSnGuUY5X5oIEFh2e3gjTKD6dnjoNpyU9fvyE/Qdd5ReGgtOARk3
Dz+0PY7BAW+9SkVDiOYm71tPHL5P0/lYfPVNHGYY23lIt6WeCBLA9jhwmCYc2M4fVo8Eunpd370I
Z/HhGCA3uWFbwZca28aICDTZSh2FGqAVKP7uWnxLCTwPAHqgimvIHF3rCtL7pnzBstQqrSszZeJg
7o/SfkpYy03NhEV5smxZveeykqDRX2qKZUwgTAxjrF5YW48Ye22AbBlUTUEqwJmReGgtPe2pY1VH
B/pWQFkyPZ18pcVnvcqup2w4/sVldH5f18Cz/iiI8prqTjisBD0SURwCQlK9LLyLEaKbEMN5+YPe
KXG710VyvEOeND5VWz0sUNz/sDAR2loh/DPWIzXZ6OKpaeef0WGpseO1kT7bciCIa3kwcqaeMd8G
TXObLm/hnQEbTwjjpkL7+5fzfKVniZmlDpG5iC/U4sSQvAACJ6Zl+au9sMwrfN0gcf7c+XB5ybCi
flKV3mMzEOdgNIJfSXaum4KE9746Rybywb68PljxfIDDWUYbnH/ejFBDbxmRtoIF91wJE/dWggx7
OmXveOYweEs9XHRh56odrRjQOd/uJCAHpXFJdLSIZYAhBWJUCF98JXjV10WgdPYyiRk/xFVoJxe4
/Ff2mUzbr35ACa3UhUgrxlU0xOK2MKPBzoDSH5MDqLKw5d/nPaskjXmzcH/im8SH8h93Ry9Aiy4g
asbS8qPBfwBlkh/tVt4a5o995RoF8AVYMn+UzJ3nOv39XGqNawlXcihm3pOZZo8SdTOKO0hHozUl
+G2BxOZlBjLfnK1vC/hpPUa666IvoL5Vm9gNsDzJw5v/IRdwPDiDnh3sEN/pBHG6c/LYWGuTb9Cj
Y0BQ5nJjSFV7AgqYKo8yuUwT5Iqu3PmjjenSs5H6l1MxR1hwAVaZEYWMy/AX6UOLFEefCmSv5Cc5
HZf6/uB/elENoA08nLbY8g8aUgtmResDPNagBOA75tzOlNesjdoKSyMPA2vGAvNqu+RUkFoiNJlW
tFLh25aeBBqBnxQesmt/vFdlgvgYroIUDcv6Nyv6fYN8Ph3I1IPivpJixLSkYz5kE9CbX/BaTG4O
y04QwwYbGvTXoOLnt7vCvF2HjN6oFLkppnHzf6ZJkKlUgbc4Xx/lN3f9/NkX6+kBR+eWrDyXXlAD
pM75KkQOYA/qnq9ng9Mjy7lz34LJSsZa4cPk5pIAH8AKg5MdPin+lvLIMiP7at5YW8thKnhz43P2
PdxVt07c2UIUAqFcDM/ObbXlTsPsB6lpcEraqPmDMBfv5o8GEAg4XaSVIVuqqnAcLXT4vA39ZwfK
LEudZyojGxClhepkLEbzdOHy4WodJ0UFXHVLfl8PGjjKLxa2glYiJpPWsQnj1+WblxokmgHGDjfL
rmzqJYDwF9Ec4IYJrlZDzsBMszHHkZ/WapMoBDoIovAb0C3FD+hvFWqjUn1E61tBXA/G0Otz4+xS
f0TMnOEteC7c6smEEiVRn7APnrQWo5j0qumV6IGrzd6wUVdfx6VLngtc6siuBPz8gts8k/d4U+wq
P3yWeNaE6Es7y/uNJlaCRduE/L8yK6aiahigmhZ5CMkYsO6ZSE9t7cftFX0FFzVhQtG16h1onRVG
VO1d8/aWIQ2daSf7MRLrgi26MSQqn/rZvn0SDWgo67lP9bprxbDYvjkgAdDgCqYraJzal0B7AJse
oOe+33c5LMundONAQQmuf3b5FsEC0M3PI7yhW4zaMcFeifvkr5xNrBtJVTduNm4UErrNAh2KH9L3
UzuBSLOef1qidx0KxXDvbpbo6OTB2HGv8ZWv1C6Y0ycHIeZ2QaH9LLMePyQpYgaDun+2WXaVSVBc
lY4NhEE4UuokMDLKtuewhlwTSRQvJWPFlL+mCrjyOdVnJVMxGT98fKYyaRrXfi4fFsWr+NphwNo6
fDAgMbonN3fm8vQGLBWd4dsdTuaA754ZiihPFF6FdMSsAptK+4GNjWUZHdUvAJjnID0g0QLtTq2v
55Z8I9V8m4zhIM9fbOPXgF0G9+5kGDQMxRE58O8a4CrxJnbMvL0EMSGgmA9fu2fX/MdeJShKt6g2
3XC92myH8qbLN/IisFEdfBM78aPCUm/MjWCc4KkVuffOwgJCxCI9Yvn7+i6uzaU8cfn1frdvpWup
JHY7uF2oLs/Di+BeInvSQLsh3MPRQSEHmr30XRsCKUo5Bp6glB77/sDCAaXP90KA62+5nWY/w8mi
VPkQZ1DL03jpTizrXPfWgPkpCiMpk4WxUUPDXuifCyj/n+6M7wGbvTquFSO+TyKErX/SjdjT3R5r
48r+2rPSGbeJGj29uSyZhSKxRponBtREBUxqmIsITjzSCPb8PngX2c+/vxQChkrp5tck/z/zNXY6
UvWQH4Wgq0S+wtJMUskKPLviEqLPJoIquK+w2BCjlDOPgg6UBHkXH8jhr65uHjkxtZz08hCRsVhi
Mux6l/mUPhx7AntIwa7dNSHTr8R6RKHrisoygb5CfOSY6EwEtdeWA3qmzjVNMMf5h4y/F20Nz+jr
XY74VJtDToxWKItPHWoW6LpnbqxWYRRfx/MGx53+eue89MQkM2N+CsddxGUy1mA+8d/aWIUv7ah9
H/Jc3bfxgyMWg0gyQhnVz2aF1W2wh88C8CoUQd2XhPj0tnzS0mM+v7SAWgaHk3/gHhIyUlNe/Dr5
62OnmLT+AWMjtuCkJV0os3xQoqN/3uWddjkyUgYSQTa4/jARpKHlMV16dXsImuhF993dPsFAys2L
EZy7JrkEYjH4q02eKpZVYYWdEw7y0SPjhsyhH8OjeZLE2WhHaBhpbKGEdi9pf5E9oO9wSKXArtY6
laN4PmuAuqSv89xm3PHSR5uTR/tPqfz7jP1vSx+iuARfWW24oE8gzQucLX0jL6PkgVAEKuiS9+Ba
rzfVXeM4uQujbAARC6HgPOlHWoksP2SrfbFiimLCP9liceEVQcvCqs+V8iWNiURsmChC2WouysqG
SL4N2h0T2k1ZF2YA/YeFAo2gN1u/dIFMucg2fvik6JuGeMPKfImW8KZrZxqGUGjbkkKBgqzG+7Go
2Ozm7kb12BEsWwG9RmI11Qn4R7EaS8v7AioPxYvJRTUneZAhUPBlPMxck3lOrgdN3ypglsqlr2LV
m+tXvBUvUoZSRUSpgP9ONZV0Sof7jDabcLSPGRO45A5sUntJSEojBL8MkCLlAVJg3ttf8gYGotz1
R/RXgSHcNKIbTBQobtcS4D81jgo96Dep+v+69xMe850CeJhdo0PKB1gSI4EryK1q2efgNOw+bfFH
vf+5+m/YmcRSMSQ0p8vaXFr8Wz73pQhlfUFOSgjsDqbibCGYKpv8V4UQYhm3sO/Kok6/cYfdmRxI
3pRqYm2YRmzu97970n/rHMvzo+FkdFmqPp2uTQJBFtfvPzRwGWagrE8zzV6RhzBAIQGQaTGT69ZH
rBJGgnmzRKC97YydW988ASP+yljh7pGSf6PDNyogk3HivQmn0cBZ3dYx+Di+nvYts79bvkQeOsey
83YYivgXu36U7RXT8mSg6XOkTO6NgCtGQNVTXiwrXR2G3f4r4wP0idSltYOE3Ul9gaRZAHeBRvVQ
49kUV8SGfvPkE4CwlsjFOKZ3JjQ4tcCvwQXbIywtS5D1eDtgUA2rvkwWlDvofXfjO8bFd6NLmt7o
Es9sdsOmA133CXuTtmb8OgRuRIFtASz9V/f3I8srRzRdxSHmCuD68NoIgrolO48+n3+FvQYbQq8R
2zevabat9fvpp4N6mevOksWNJxmKuRGUe266tQI9S2GmLTSNofOmSt+caLbrQq/J1xYLZ1KYs+3D
PJ8u+HZ/+G+05S7l/65SvjzJvvIaYLhtkLDpqc5EpMvoMUWdgh2LUMCJ/xK38mURxNGGpj2qQq3V
WB1ldscqtwUH+DDlgmBxSepqMGJYKBXkxapc//p8YH/WLRcZDGJzV8JTyhvOAlu5/Vqo65avTvAv
ZFH9oeHfffu3GJUQfmZ0sujcfhZp2PZTqAFJKKYMPHySyWYBjDCS3mX2S7Azhag7Pi/kW6yWIluk
pV7p7nb6qfkpQqLk8KaXzQMNN4R/hC0k9+7LJdoGIbU9Xi0lSUQalcg9/EoguXdsZ4jbOBqurKjW
vewfOqmtbVUOASjlBr48CmbN2PZ/5jp9Q/bYe8LEh9H19+s2Ouuig7UQ6zk72htb/sMyqHQ0oO5C
0k3KTJFi2XdDOX1vKwi0L9XufLQEwFophsC2g1mUiSJuhwe54P6muyRHHpfLINBQHoCo/JQGXEEG
DVM19hnL6NrxqSXmwRGh+LMBiCq2o6Eyrf8y89mQrpWMDMiQ/xWDpcnouRh/SIxIXiVQYY0/4jz+
LfhTBnV1PztTmHXBg3eh2dkl6QBwRGsPufW7FgMKoyFPZd2WcjAlEEcScJJ4SvN/L9Bbs/yRfg2S
SMneymDgkg/hOyNH/adWfmzjEb01e1Tkcvx+1v/VmPQcCNyJOc7xsPfsBLLcUaToF0W6C2aSuRhD
O5kV+FtsvFVZ5VsceewpPE1Gpq3BZIM1rNG/gv3iWICqNvWou/igT3q7JjxIS7NcyDgg4ruRs476
OQBuEwPUkxNGTRTcUcPBSVLEwdSBW24wbIRUaBcySZfTrfQBG7XvB+NCJMcu8OeAQ7f4vlb9bqjY
yC35mFnbEp/oxXVDZkO/VLfWGXrnjjthiVotcv111SA0coxMuYFCXVQu2vLYzADpX0bljX/6sEUz
QbCnugVuJbBFFeyJ1uDli+sZHcZWbxJ0wsh/tyS23+WLSe3icX6wnbO/Lie/IfqJ4M2/Z05gBe8s
1qGHIIX3DugFHm/hHdC5lI+o0hTnEkIMLXr6/F9fj32pW2CLrLQ4ygkRtb0LJ049OKsQHfvCKjPE
gVqAxFiCwjZ+viTqjXedOM5vE6uMeR0fmdkQcdtQE9W4W7SwoY4C4SH82SYGSe96RWju46klc1z4
3A78H7qKYYr9Gq4BTbTABQaf/v2a55VHAtkqQTEkUy8jYfw8ll/c4YXoNOBrDQdNH+CmlhEtHiCp
5YYQpp5lzJKkwlRa4zG2/apdGtFnDKh6iBLsT7gkxNkX1MMTZcRxoVGRjgfXl8qgjeMwFxEgepeI
I48HW4r8hnZVqHO4cOx5CX8204ZlmekL1UQfLDjHfq73FMFVsv9wUrzY+FeYsvpCbltmwvpbnuv2
xZCg4cSiJmbWpVAJbEZC4r42oEZ51O4MxFzpGp+tlN//HKTVKqDsnUNpFMXp0cwW0KjtcnEwi7RR
mwoBn8f/I4LdnTItfzXiTMWE6ZFRq+OwS93+XZpQ3tkGOJbhjRnoGk5wGQugoyN2/QtOD/RhJMfd
+LbN2lQwHWO5pQD/85j+izSEqz/2vdSiimiG1/OHzRROzRGfTb4AvMoOAuIlhcYiGqwAKopgasI4
vsSwOA3VX2QQrB7pk4qd0rHPs+4+MvahvXYPjL0nGPHMagM3RA4ToE3JvfMOYfbIQ5B+vup6Z9rp
QVtpBMlcPqdEWC5WtJOydYUI+8N3Mh/VLEp75Tgc8mETiN2d5odfLZP53ZtnIcLHKqiQqkF502OE
ATszl7rr7jxVfuKU8zes1UxS3nQF4O2CIAJB2ifrYtkejy8kj2torGu61HLL1i/4lW7ICa1KxBHG
ORTPgEfBs41uIWK5Vpr7zrqd0C5W53tfHKluNKNggrQO9CGRelPuGzX/9ud1ruMgVNFjHSejP5PY
7JQJKNuCASrz8fXlJF0VRp/ekfKxbgenVqrkdxzBImFDzT5ZOh/guIHbfxHOxbClwv0Jm6yaoIbb
oLaZkplR0utQYWSjr5cQCeaVV8A9sYSK191bUykhe8wwWY78XZbctoh5Ma/mbE8VD+TUELNTC94O
0vinEehPwqRv8aC0dafsFJ90i4RdprPdwsjHvH0D7IH4WF0FzTGGWYxVFfFCjW8yHz1ZpLFxzGqK
tZOXnLfFQCTq2w1i1YWgLtUXnw5+Q0j3dhlSW+l7pYRlk+h2Q1sZbzTtIVu33wOZ40pm+MkKb/X6
evCW2B1kGiNFYdVesrvwhVwfHJ+DqPVFzQXh0jYL4HeEWsq5Rjs+6jdQnjxxm6OLgE/6PGAhOinN
Rv1NKOjdebLMDMOi7kPo0jrDUqjxDOiPvc2nX60gk6a4BnNk0T9aiGXApnaRS7dKG25l8vTk9IDZ
BlZl3xdWw2Utt+Q3CsG2/tWZeC1nT38DZrypUJsk+sh723MG61uunOGpklzPZ5iMucVKrH4RB2WW
ZmjqFl9RMUBvbaBHfFXigBHMB4qktuhxC/u2WE6CVgb4XWxAMcMX6/V48CTMK+1G88IKBMwiWjIj
FLqmcJVztBzImziYrVD/qAlRSvxtPCJvfPGVmw3jVVUpHAsi59ni1PHdPojB3mV+OD/hA/borLEK
xjCthTyqzjEbBh0ZF/5/4oEXrWsbPzgonz+v/2GW8HEVrOoxXlTDW3daK0Q+HSBzM4UIKG488xhw
iqkFGmwHQkjD0uqkwYxR4oG8gAEMxIY5RupkPSUSdZ7nmHu78OGG/hvKauRXWJeVKgA0UU5oFFYy
jcxO2uJOVdtrYl+iekZfE3Do08wWkknHT2q1lz0BTnTtJcBU75NhashUpQnRXPKu0BcfwsTrUUXe
/QyGoEaZyCcw12vrw232dJ130NgZS3H9REGFz/6fDq8ycXscvXg9ncBUcY/ndhNKnxf0jEUIFrgi
G4uv5LXpNmMejadwj3/HjmhCVU5qiX2QF3HGkn6EHkCBwti/Ke5ysd+wbDiUve6Wpq/DHBaVCAGh
AFIFDarwsGtlcDvOE8obaGDu3Ol3cJFtLyZKHCYojvceMmruMqOiJPSr78Ac48Bx1jNtv25KPnhI
UG3tfzNMuqOynBD27nlPN+fhBx65/v7Qf5FUd3F7of0uPKiBsmz+0LDEJTDtLPdQOFcD9kOHxSR0
nGImEz/fbj/zkNYJZqCQ9Ol7fksJmXHbSGYQP8zomDgkboy9Xx7TACcpR+jlVf193mBHlhEVMtJM
VAH9XECLeaSaN4lsKWFF7jVRldCz+wP4keNp9VbxZRUsCH2bm3DCiSTjoR+i+PJDaansq7NyaQn5
ZNQ/PptFYEX9FEx0o7K3zGICY2ODIGp62fuwCVh2hgymTSIOLCAsEkQ9P5yyceklz27mh+SSuJE8
pf8USNoy/fo+o7aGd2Os++SjQWc8hxBoZ39NrQL5ArE/aV1dDLCEIGmfx/31odUlb+40vlQfXJ7s
CRg8TmEEwJ5Fe5phxLskq6OwPY0tqkSFDaTFtwaVCj3xt93ITs1AkbI8wibvjtHwkc59aXgN29hy
R+hrm9ZElI+OnhA7E2HOcSGOra/UXDG9kaxprkuzK0Zan8ng24rKMzwQlZd8LIQBDUrVlNZQHkCf
lil/th0H+XUHqw00bv/ZwjOZRvSXguWzzK/mOo0q2PiODlcg19oK+BXIvDaaasQ6E+QroRwc/5S4
VanXMAmWStUwXcfZcpjmH3bxl0ti6AIIYA0UcjRbkuCYJPg724y/7VkiBdvfaW55i3sdF6c2FIcQ
nDPhF4ss+6Yfqlz6+kKcGtpFy9+/yM8EnkjrNXM/2KRfKMkXcFhnvj7a42Lv/Fw9wIXYS4PMdok6
bQfC2rBD9NKkfBKw4TX1wX5X0j83CgPOYv72FHDxLahFfaEmC7FAghDupQAiyapl4b82Q6KSVwOO
CRgWlRKT3F1aItOxCIdCizEjNJpFN142yTMScRzDA12/snqp3D8AJlFJETJcjyckN6yVDR5DlX8O
/9mBHylADA1RVBXtV7v2p2X459+z4tdIsk+zi69EJ1V6WYzn9jOkwoKMR3shG+IzxE8HGh/S2LXz
IbDiM8eXzUAQyw+nArniobwBaib3ceMYHG7IotnA2/CmIld88fKDmcx07+LXq5wvCtKbxigm7j8w
qA8dfAx72MBT44oOa0Lkbegz8T45vj+aeraYJL57Az9MeDqGt9L0JWvexwpnH4CUtF2ADpuz/Ulg
01xDGCIDQP7N3hm/z4u2hVNejm/IUHreLUP4S9EG7rWEAiumWl7UjP3bBSJPmAtTl2PukPBe1384
LmZlRPdoXNZ0sVqERZ13IFVZXLT4AIjUlOPW61/3JPou9ZzVPr6jiHFnskcKen9rfpfSCXC5NO7b
odWNIZJ5P+tLxBQAMn/pcljsRisb3ogSvOPWU70KFlVanKB2RL0/cckIoOt92fQiX0xeBpA8147b
DvbWucHZAeAeCnu3lM852DtMxYkpigngb4ccICyaxhO7hMT6p6WfvUTCtJ5HW3CCJg5k/lapS6KT
TC9cMyz898wi69A787ZKN0tZbh5yw3v6lb+h9s7rCyGv27Rh2mwqL69P3HdD84a4S81zxMHWrM5S
fXIdY4qWECGjeEAZ7gHY4NbmIlP0FkSpG7FYPJRtW7Jqdicjf1gbEutXevFXYvyPMSWZjuYCG4A1
v6qKngFj1HcD7OlmSv38PDbcV4gNVwAsz4HWGuY1kt9vHoI81JH0MwUSHdk5ldD5HiLMR4RVSdbJ
j4kfvfxN7AXmGdNMD85q5LU1kxzqhcCTmn2zgfx7ryOoskmgzZA+E/AanEae2rsC0IE/Fr90PCxT
0S21dkDJAsfNinFU54/CzKdKavKhToCYkWmpeEYPCJMgw/2bHJDx3XYTpw4iTgtNyehbQ+AYgfo7
QKwGZUJk/8zlQm88mSxZKHRaRFmfX7tx581YKtVWIUqVPwH/4OMzsN2ZnE5V+zMcLTrfPFxuM97B
3mTUEfaUzUStOmT18L1V/cPqbJz6XRmdzWPdPBJvgqLUlTGQD0tRXztziFqA7F0ZH0E+c/lNNbZH
3/xnnKh4eJTgAlZrnPS8YFMMs0rgWPWoXQkDqtHRUkSLckE75jwiygqqtGPM1LfydEtX0EOWnvq2
fK0Ft4rq1jJPffIsQJmZ/YzGOEw+qw+mPfGmp/SEQlz1qBbApgJ7S9VilgYwNrzPP+8bML3ubZId
1H1BOp0O371X8VzAbBczmxHY2nZGHEiTznI/c3flMuX4wdc5lVucj8WWfKVo+5u59i869yL8gHv+
v2g1DhJ7FjvIqWuNQhImMGGOlOuQFh/Zml6rzLqdM0JVvaYmtO1b0WUyo7mL2PqODOa3Aq2k7lL8
2ebUkEABBIffDGP2gqc33+DZzth2V86XfU7g42J0R6o37cAsZ4nT5Jt0dDve5hd2V2j/gaEqj9At
ixS4DmrxfQ/JAylsZy+3vBMQPZwRXwnHKU1tmkKwWdwiLNvR7IcBulRssokMTHae8BD3EUbrOfAE
iE4pRLvFPfwYMgS53JKSSxvEye/zym8SqIIvkRAOZGAB7uKuWhXYmzcWqmdg4dp8CNXmdjhKTHuc
1ud1Go2ch3rZJo9al5RnkxssOfYsOaziMHMwNNIMei+7XsmLOezLKokqHecKhOdBZKpk0M4mxI81
zh3PGoLJbg4BpwPtPXxmxxCnMvKwfJcDx6NFlpVDURYTggQGqpy8IE3NiJZuZseU2UbVLsP/35q3
soK6Xkp9g+bq575/Kbfvfw61qHzw3LHG6Kx3hlBZ07/IQ81iiZhHvfFQstyZGFrOTfKJ619PVNQd
k/roaePxZNd69afjMy53L/cM2EzmtHtRGHcXjfkZbHcvnxDT55V0rcuAX+LcH3yrmZzidyK/P8fq
dknXQ/soX4NBZG6tCMLAv6xQPwpJpmaSFnFOtqUf2prPLcBnNKMBIPL7G9Igb9OJVcC8jrRwbrEF
JZpPTX/rKcjfVvRfDvBH5ZAiNVjhVRI597Z6x6kqe97VAP4akKf/Atzplch7iZZHtm7GjgmHv7WD
3YFmZSEh3gTiiRIfwhnzWGvv3uHi8ugVVQJhpsXUws9a9Qf5TSdazxe5h+pxOtamIuLcpPW8nRnd
AddWwyq6bsDr8pXDX0K2wEuw/2uKtJHVAgZt7OD5y2+J/DNaNxG7pkNAKKbO28xobN7JPM9wqTx/
aPtcdpZWRvAM6XoJh3G1Fs01nHM7AX3V43IjEHwG1ggKTou2GGNhPNywE11sSm0reOY3RosinOLi
ctipc1hjzWfU1K0W+QaueU5V8+rnoj4OgG0vqPoksGyF8AF0f80Xw76GYw13gLopptfBVKyFJsvg
MlKTkq5G/j/c5tgBoYoumchKTuiI6wXYeYZKUKKaFWsFzCLo8SKqrl5QLhLiewS07acXcKjazbKP
58vjYAJwnvTTintsb863AqUKljNLwpZO+/7tZqPQciJwVLikF14TsgLaYIHpvC5VWTmpB0ndH3cv
CXOfg8GabsIlZprcMHUWyv3I+vhepIWFnxNTOKJsh2HfGhT0zl59E+46vhD0FqzdG2SM86is5Kgn
C771OnZ4sm14O9/9eqkf+2hMIt0hs6KyQIbj3mXk+KXg8UlnIDAHIIm65/XS9Kl0A153DHeJhTGc
4r2KL5mVHdUxzt9xclCjC4F723NOXtRezj/GwfqDPmLSNXV+R7l5iJ+e/mNJfAYuwdJrsymf+AAC
L+nu08cvcKi4kuZDnQ+/vzH3piEIwI4Rc3UeSUDAJMtGkBar2RawdykY8yrqnas/YfkWP/ueWib0
aB+njT/4slJ6KeUoHeoQ9YF7EBTD+kaidwEOkxyXxHjHqtxhyozeaRKEkOTgpdo0ksTmetpcMI5i
yGPk5qxSl+ZWlQfJIYSHObRtDWHiGAgqq2+gBGooJnlJhA6Q4IJZiKYIoB35uDCpkwfY/xkXhl5g
NskMIpRW1fyWGrbws1hf1mDxt5fwmJAc1E059ph6CWLaFlbAseO3s7nxF3wP3J1TTRbrm04lKZ95
kq3FJ2cJU4Pm46fMhvfyODnTxA3JNg16Jvyq/gs4RJrB1TMVI1J0YfLRmIsmuUmy3BJyxs/40oLC
hC4p6fht5EiP/o3Qv0OgvyjUjtW/FvnfDoyiUbloP1DgExVam2DvrA1xp+jVHWLy3uunfNQ3AoGW
agdLW/tXfEligaqC6Gr7BClpf3zrieU9+bCHGr+tVzAazrTGrddHB4J1ia7hy9ho4SU4qyzpv2wy
BEafUEw9c4jDPMl63Of9/5rh+LGC3BOWN+Hgz4ZoLkeRcaAfaKbrzPzDni4wYuHNyghYXF44hMEJ
j0Iiyfn/C2t7UShz9+D0rnS+gtR8DDJdm5RM5x1+pUwBib0VOkjzLuxfCoGsk8zbbMrXMVdXBvtc
aR16NPDdyJxhH/l0tvsI1K7JyB0MicsUgmuuMcPFs4Ex3y3R/Ve3YMPwVdoES6kRowTiJUjff5xL
+UfDkVBY19g5GWtyAbwQgZmaFSKtT+qEVvrmcTfEHzkNY9ZFKRRqYIEnU/uQ1oVRIfSmKc5I536/
OD5ylotozIXZMIfzO6SbTcNqqyOFdYILoFQLFi8kNUdfS7Vp3tQbM9lxN1Nq0JxPdlQaU9TPEfCY
Hu1+MYdL+kH1NXWjXn1JIH6Ku+2yYmk+o5Ym1ubrlidUt+Op9Q6Ue/fNawfJA/mxPgGEt2Sz13qt
YJlqckWss0OqaUd7PyofWR7BNjrnemeXjVTX3Nl/NCSn4tPsdTatFmGLRFKCGBdnfYDOmFwEI4II
8HNlaxIN8xi6IjGEBTWkNdbURWOfPsqFbtgt9bZDMSGqL3wUmwwmaXPh9YO56xeVwlp4rBZSURDr
OMhx3OdIW5zmbopgISIdxBZUshezTfS8Ki3hqNSmQMQ8KG47tPefK6wqQuziaKiLfTns4TkVs/CQ
UBJ+RsFifrLZzFHDKpXwVpu6ZNajI2ZzUcQRqXD58exuFHCfnSsmdW4HTG2kkRWI5hweL/xhYVSA
h+voRXcTLe3H+/996d0E83WW32/qJCvTfNMt8UWRMoB/2PBIbUCu9NzQA6yiqrLagPZelsugKaid
gnONoeOMef5IkqmrPRWa4zu4UWIx/ET8WpEdlv5MzIPGs1timH9aFpeuH5gua0j7KoTmykvUg0Zo
hLE6uZwcA6yL2MPu2CaltvT4YClNEV8gwOZ5jsMZAPh9/mbrXAHJEtF/sKinWnzlWnxE4gk1Qs6L
+Z4PVypk775dgu9x3rolXgn/pbDfakBopRh+ZGL+O5yF6PUGdfgpUNsOx+ib3jLwLCvtC04eXWV+
inWlekMIbneIHYKvqMJtGb/zQ5Wn+QukGwDSgBWs5jvse4HeS3MVzUDB9NXqlmr4fpFBVbLKZJtr
5frQquq+t47Ms4gJ9cSS0ZJwOF6gNJAAoS2DPfCxZGWp+nnxFoyuOlWoUvAuhynwBUZIgAdBC19w
JBCpDTE7/wqyzJAT02hK3bFL+qlIvyZw8BcGut8o/767+r88uY+rpMJv6uAk6TGONc02RlmwUX66
5qILKhrB8liz5xeKbcBOmUEp0i/nYN+gcDkboPrCCTQ8qC7EfJdblggh12fqOcjav3fC8TJkD3DL
G92Ma2HNhqqHDGVbC2eFe1IVFb1ogAxxvws5felBYIkBMpBUsqITtFpHLH0zX67YGniEKH3eDlW3
R8naIbbnM3H0+cSpf1+BVNNIuXp5BjijD/XU+vf2P6QHbqJBjRnbRY5IJXlWfFHi8Y4MmkyXrWnj
Y3TaCluJK5P6ntV/twv5qncNGwRq47X0nhyiemUUAlZGPDyqWFlvm32AYBh+fU7aJfn4RVwVKm3a
7O4Lt6ftOCzOFMD2uxPvhyIOjcZElONrlfxKLus9b9gJU0M5jErujyFbt8GwDQDq+IBcJibhasly
DJF7/nA61IHpCaohy8S6zbV2K5q8A+nryhZk9cZjlrFcKY0Xlp0IeLDhSMEC5Mzy23TuPctbfkGZ
KRRdJR1VPBEN9vc5s5UpYtZTd6zypBAWRNyAhL55R/rl6sqUDNAs91jFnI+nD28QiVdkjyEbVsYW
pwulX6Vw/vRS/IAnKuQD+oOyTxx48f8Z5MNkbqASdvbYSHAPbs2/FgSBs57CX4uJUgQdBFzBKxMz
0f0ayjlpGcLxTnfhVSc/us9vIg4HGmJsawJ9hzzcBi5wQR2IeGYi83M/kZOQ4hryP7XGsTcOD4hD
KyLOxUe/zYcOCjPK5NxlLyM7LObMNu3ZaYuTG46BjXuclrX/oh8ox4UG5p2PcFrzZYRZaL1TM7uq
7aUXTg9r7E9KOAF0AumimLfRijLa/WPlLg/YANrHsPfAYevnF+1ejS8eL2GuPJSPUxeGSaoBAsj9
rUbsDi5G0rQjMPxwdOh6iC7Cp3FVVaAV4oE0ET7v0bKZOMKGZQ2g+g1HFgQ45huaQzzMhxceILYg
FBX4muKzWkc1zsEHO4wmzC2pfwbRj4ptpBYsMRY6Z23oaLLOJA3jr+yN6z8gAbYo87q2yaLe4OQE
XITChc8jftuTM8hvnRfoenqvFmr1cHGbPOru9DfR8UuB4uR4OGZF+O8lTPEdQK8yZBZ16D0mGxRY
A2lSeVpvrTQTkWE2mpBOP7xked3use5X7y80biGCi9hpZ/aV1fnFhO/xutngMIsxnn2r4XkWuxdj
2Jx8JwqT4YeIMLWEnhvCY2ra8XMnGPtr39bbmghvZEr2I3BKv/qxRVvaKxMUjgsP2Adtbb6uWh0y
OL9PohmKkhBg8Ek2Gzj5LStZGcbRmRrzFt4sZysWWdwmxUm6wKJQCOyG8B6fbD33HX++jMvNEAb3
+Jei784AiKaBQgdZ4TmLfID1Zb6IrqUbT2avGaKxb2UrBqha8CT3hy+OC1RIuwQ3x9FMiE1MFyYc
PPW//CMxOoyVHGMosrGGFJUCoHno8FrlD4C+0t04Msk52PzcNcCv2R48EqObTjqWiq/15/RCaqlv
oGkbaBxzxxYEULXIrfNnxsqoq3A/7IPLWYEarVy5aTLiBaM+IDkt1OahiwA2jCvwuRCMV9mhcwWM
hjl3s4Klclg2729j83wj165vOfIoE/Hyl6EZ/jkHkY55SNHJfr81pw2UNTed13oMwCrJ4yJC44+m
YAJgKKwMUprJifS3b1evIDwjk0wDkZNwZUHySfucaFIwUCvuhcEboej6nctjE7R0+cJ+PbYGhgyT
Zgn0f0D2FMC6ggswnKjdRTqF9yH4EdoaBG6d7JJ9lrwOcheF9C2iqcdPyiaQfNKf4oWxv10SNTRh
n4zwiAKZc0D5aVK0khXwR8aPNReTZs5sQmvIT+NDaiUMNlr4QkT9JXuIg6brtIJLOPGKACgkV5ug
vbnI2/6dfEk2UfIfZDlqv+PKHeAm0LevpwYq21jesx1KBT96In1EwVRC1RXICoHCvkXlgHmIL9ST
qik9CbzMrEoIs1f2u6p18mLTVUKoVvwMy6eb85ucxrkLMVC46htYdLIjgrG8fv6BDaI8JyqgEhKQ
As6S/nlZvt17NojgasVuElG75NOyzf59ADYO/auQFloLgYuZSdT9pRiChhDP3RGxhPW2yFujLHdn
RkB6/1DT1hfH0Nzu9VURlmZk4HCAOw/HrOnjxd6nSEoQB9t7O5GIuKsPPXdW1sL2j6L3KQJX6lnA
F0981V5VVmGaN0FObMIG6GObLegigdu6tjeSGz7XQhSym5xD5nh4DhOMSbLdYGjukVh5SDaywtQz
iISYDTZEkXzq856K+0/rrWU7UQmR4y7cZG3qljLXoxPfFArBXVZGRvmLJHcJPv+1T7hsbEBEdwrD
FaEVs0QbunwYGIgVOptfIThDrE4R6oVAJR2N53Z8yM2b/6N75XpyERHU1ajgXjiWLlzyFPquxf8M
l4ViHW9s5YHYrIqJm3mCwW0ONmgGbodC8HD7OClCHGl+3+03TAS1/egJ5p9PpymSrQhlUxT+6HBw
P+jQ4fbF21uzGv3b8PWxRBJKMxRZrl+Xasq6MBe62zQ4FMAg/dRe/1BgBXa0inAWOIlVeiQl951B
i0M3Fa4RCXjKiDrzkGcFOqcBVc1ZAPkbiyKLFip/Hld8LyWmA6gRE8Jb8B4DdfFVdP9Z7r0sGXxc
Zio+/12XF5lOAYh5/S0EeVpkuxGXPMPnxwXp/9KzX0SDXm+7lFOs03DGW5qo4kbJX6nCmsqfeecT
A+WGsZtHMyTV7Ji1CRdsEdFMBqc9Tj7WmNuCj4+7ywco+iHX5ZlmuIbAV3Qk2CCv2TZSfRQGjWb7
xYu5Ie4KbwnSpAn71SlVgMg5zJtTyrMUrB2Rksh96cr7/JN/NSfFEvaTfjnijfYbRAv+I9zN24yZ
g2WvCJ+IYkhdRG2qdtjthWks8UGcJYrOguTqJFTBr8fGlR1mmmgJya4ECQcFz64mrISdD8n48DjS
3C/u4m4YdcIL0ugoujgVa7hRb0Sp/1h7bkpHYj4edcd0KfNW29JzToUflfFBRNkMNdSGFoPgFuUq
Vth2xCq2HZFrQVuYViBiYZmt88DWvoXEgRWEQ8jRm9ZpydyYFDcaKJgnVb9K2FW0vrOy2H+h7cW+
+ICaCEuqntE+bXPX3GWxgAmVwOpymyWcTsgydggUr6ZxiIvdCFeogRjIS/o1aTa6y9YPsaTw2xsc
Ar0E0tEC7xCMrYKRUPcyPUXAHQW29MsHQNZt9rFkJnvFzszpuCCB0SZhpTlZgHDAq5C+o2DDsvGP
Ad8erVNFloWCJNAeskgP9MLN/H8dXWgwVzyPlEClyrsFZI597e1BvS5jT/5rduSNpoRqZhz1ygpk
gak6aP+eEfdsVmSIABIeEyIfjgwu3mpm+1LyFKepeHISFHEgYtTdqP8ZUDuX+jhw7dZ17iN9vAOH
6eLQHdx+4bPCEKoEDEsRKwyEJl69uNIq6qdOF/BHsza16rt4z4yPVAupgB0Y/4Y/jCx9AJXQbiC5
d95xzI1HyWu5pKXogEDIpwyO66cWXTOA0qD8k7VupFAqwWXUJlHa2sv9SAjqR/vf8PqAcCZJ8g6D
31aqEKm0wlcbJrBGFPO28d1GyeRjYI3kuE7muNs7JbdvZ/Q67OQVEzfp1BrzH6bZAMJTt3sgY92I
xei8cNgnWKyEVjSOdT3+1CTj5ucAoUjoF/uK0OX4xo8K8yZHIsbUYXBGvUJEqwq8TpqDodEvOPG/
sHTna8niuQf2LyPLT5R1Y6PuuTuxkB5IV+vuiOdYdQxnMEeeC0tPt8ANOqa/klpo0YKEtO8C4gpE
GLKQgw/Hcg254ZZeUd8kjQyhJv5I7pJcFbZH9RUMb+NN0TKfi1+IXKya3whUsJAaheDBoZBdwSIz
Ta5ZyIGY6Er7pNGGHI1WxQ+loGlhNuV2Xff47LFVdQmidRlyUymcsgkcAM93AP5s+rY1RrP31pNW
mSX2MC3WlcH40HYcOsEjlLhLfqKaFuQtUEh87EjnWEuxwTDF5zRbrHrhu3QK12lI/KgSMeEfIBoR
5BSya1CtduYKdhCVY51rVP17ks/2UF5Ye6Ah392rwTLHImx53jcBgzMluclKjUExOCLiaXlTTBXv
0zmOR2Lq0qe4y1fV+E4D27I/HAJC+3Gm4HwLc58RA1228+xx9OwcGO6m4JFY11mvc+JCTsdJkNo6
KzS6zHySz0Iqo11QalgugLV3lZbsviKdU+hJ+nJrvQ3F4usQQRip6kJa2xUiW75SD3V3fMyxBrCU
vI2I3dewxmD2zXeKxByEvlbX/ilwOgkR6U2+RiCwoYt9NcoAcFDWwcJAnWVmHZQoew5S4s+dQv9J
RCXsV5AUu1Q/4WpHOlRQMElbQp28QrCQdMaM8ngS0M+9GCfM8IjTG4dpB3NDnFmyVzosYKSJZFPd
kIas9JDiUql8Hi4DBow4K2POSY9ZwT8cFGRmksvw5wqJvtGON7kJB0Os1sNC/UO4SElaG7whMf8b
0DlBnepXU0jG/rok2R5xHGteTmq9NkC8ma07TySnxprzDSNAh+f6VEnYfynbIuTLZ96UeNvrw2EO
7o9YFjqHJ6OcglpsI/clqEEyujyWoSsepfsSMWTmHCNUviab43+rFOoejiW9WsKZ8Y//nmp7/rjE
JB5qFU5XWsfztf4Nnmwofe1b1i/9rDuEKsYyuIleFyz39pc3Cl+srBj8zt7bXocxPnd3MtbYklk7
CBvCc3ChDtgQmHBYh/vc5fc6SU/2e4BVfLXEUiP5Rkp+z5XA9eaM/I16SbzEG+svqJfcFb0B1bA2
K4JMNUesosb9JMi7srTwfXdgEF9s8lNPEAQXnRpHnFnTgrbQR+R8qTTHR8fhBhqSPEfVQucFAduH
SnsBjUmdRLkujk4kOrJQ96UXFXJsZHs+357o5MB3PISjS8/REzMV9GiHI1byuCXg1y3Y7CKSQqZq
qL19OxY+er2hqLbj7vq+Dkp7Pe1l5ImYg7PDV2spHTI1f0QgcPlCwUamSKre5KE/nUOIVp/a9gwK
K+KGtzTxpP6y5qUUKhodCQjlpTH4X27f9jO0LQywPYaLFWMyg1XojdAMhp62woDICcTcxYh4Si+3
yfXyqYcN5H+WXl4vJi9+n77MOURVPvjebfi0IU5TycjS37tVF072Gm2CsIZ0zMo0WGg7Cpc8knUi
l+Pr0bYRFFSnscU5ARVcHnMraSvQIDd5aAteGSza8ukWSuJSCbC9MElTOlB99XGvkaXVihRNR8Oh
1zBjoHSjQNcf6YAazMHB0pw+Dh7V4NygbiJOxGFHCUyJWlGyIqDnQOm1dmp1ikhh5lx6nfZyDbF5
/rDYRLUqeNMDVg0Oi7PskB1rLO0BQpeYJpM+IyeVGS9COCOjeL9vrci2oAIarpUPyEvnbpqEqq2d
7bBDIvNF0/NbcIIzSCbAwhPGaJSgcKIaJIxD4o68j9JL39aX9vykjAobIoVCbnGy204TV244hi8i
fLFlNxplqyz0ZrKFo0ptJOSBFbUMD0/SJhtDTmRhnuEb6J45OAIBUzOeqe2mlrbcA9BtiWKEWs1m
z/hi02VioV2diiTNclh5ATEACqLxRGVRXMePNrbOS8lTVNZRjBTQvmgBvPWdFoLi3hFUVIQ5QV4U
Muy+KLhyjgi2JgXetbRHlxjobsdJmQ5XlGZdChJIjkAgu0XehEMKtiaeyVBGj+JOi19hJf9bDVLz
fzC1kigJIzuMyDgcqs6bjgWgpOCNXyy4JcXwL7qPwchK7HUpg+zF04mKckxbiAZmNBajWDUAaUMF
xxdos+6voKrCfl6aip78QmEZ104zCEe3T//WqyOL0MLT0Z/shrdtl3JCHSVgKbNdvb40JSG896i+
ew9RsCCv4+kQ5o6PiLtAPotwNzlkYB50qRjCFixWrcuH3XRcrBGHccZddduivumaqiZqUD80fl+C
g8kImTbySkVKXtEWHGeykK0job7CooxJMGL0DFNHq9ng5IA/gpOamwOi/QHHUbhoi29NnQ39Z369
noLiF2QVhIYBpX+p6lPlJ24TQI8Z4aiL1d5FI1ZGjhgMG9H/P11JLfmi+SlrocEajb2IxMiQc4K+
81ggxcfA5uS/e0IJ7fZxWc2KLz6vTK6nQKDOvuAN/2Q4xKf+10SQcrGMeUJAtyFggEzLOSNKmWc+
eTHcR5qWMGCdnxwcgi8SzFAStDLOUomUPj4uWPoweI5JrQC3k/GFog/8fCk4x35LVyM2bNdtioZ/
s0R4PrnIqi2FWAgDhMoJZm3ZGZGO+GmaBx/bmkQGlOtk3Cuj85LT0huZkJzXEQpKoPjuR7K4/uzC
ZqrI9SogE43WU4Q35lwrTXvzbi/dikEbqc+ZcLnoSekmwyCNUh7Z7QOKtGvtEAkhvLQ/OAtOd7Ez
1mXp99jMDk472kiV/j9jDdejzYpj6842XuMjdx090PvMtaq6Vzipl+Fx7JJBGGgV8ql7WVpZIdT4
XOmjRitbCnTa5toJxckGoiaL4ff2Ko1EbFgiMo3Ymd7htXU7/JV123sv/cl+HD4a/ef4w+lz7Hn7
VoPjRnpPsXxaAR0uJCe2DwCPwhTDlGyukV9KGY6N2b01omvWGaKozVr9LSheKzA5N4JVD1l7bNdF
X4t2jXQXYpPiyUjTnpLYmub2K9U6ZlKpvICyyTJHlyJ6t+bjgtaSsILkecUYUb3snDbuBwD3aVeU
fRmVVVqWz2zXUiGrqALP4/BjXMgpjOBrrJX9JgkE4mTr8PpyH84EvTtBOnNZO0rskCWPfcdnQrr5
U51mBHbsOJHzb23wYyF5yTKxzUWTBDgBuyvGNdEytOEwXxLmdOxhHAUmYARQPNRkXUageQRSFlGk
U328QZb5jGscK0YxXHEgPvfoavtAJaokQoMvC8pR5m8eIqXSGYM5ougjv4dHBnhZrAc69ZpwOIBu
n36eQx4z9zkINVrRlbFXJnyeYS3H3GrmpfPNFjiyCv3yigyTOGUGqQX3wDRxa6umvM3C+/A+ChME
hO87SFl21vm8ZJJyCLtqkFoV87xnRzfJ5DaYWwDlw0YLAAmh2g0tj41MxOJtTGZIZsvJ8DUBByHh
wbDjRYAn59hqhYDPuNiHPl5h8jBylPDSec28ku0WQ4ddlpsraKneyrg5S/9sAoqimc39gGzaAEPK
GxJUOjsMn2dsYsULwV4642ZrLdSkbSobhfFuo50qb7Puq7G7ylaeU5FhmAHTPo88psXnKtYRz018
PYZ6rAZYyZiAL1IYZuqA1+/zYKz83NslvasVnuIZ3tmzT7h+eFA+4R7iJs/kpRny6iLWZmHJikhd
PfX2Qbbvlpt7EVMAkkFKTxkvdchofYhuTXCir1YVfHdp629UtnuW223YTpCwXJypcuPSJDB1wnKg
THDPRrXzG6T3TmZFtYK/PszP0JHTl7yAqrRJfpTRnmNAvjdvJaVzPIAvssHCvgBj9hhcs3ivfP2w
dGUoXP8db6FV7+SOu/T3QZ5SczWGNZYdZZlPlLS8sitt/qOVjZ4UGbTtuijMK0uBdbl4V1EmhyJB
74hj4BYwZHDvrf9uzYeBtMSr5+BB9hwsurkil/OpHn9Nz9IOiJlmQ3P+7PkylgIMBm+w2AWUCyMV
rHVlTzwSO4TS9OKD0CZO79JnZEREDDZ5waz2F0KW3SbYx94cWH71+L/6H9oI8HXvziDB/lf8ZqQF
J599qCHG4GgY5hqvIubRXKIv3O2aM/AeOvsRGGPMBExhdLB74WhZK/Fi9kS7QzcRC/uEKxJ84bKL
H4ElrRqdV/e9z7a7nEhA8kpKb0kGaWlJ+yKkqQ6BceNIdVjRN2jC31r2dmkuU80Uk6j2W/hhbxvx
sTwCbRduPjwDt1g1vXHYdJOyT4iRETyvJ69bIRf+oAuxvsg6ERS+ZTW9sNsD7XBCyy66fFOwOtW5
y9pASq2BJNL4sVX7f4O8ym6gCXuQx47tAP1Jnn9/o2a8N0BuXz++ll3F0xLg4TQI7Q2XNV087ZNI
QRZS6y0uWKtcSwEPs4JbI0fK6vqX1OJVdw9LE8LSZxjg7GDO4qxfGJo5FZA5gOJVfiAv3F1miJG+
c8VUyTS0lfgstx1oHhsqHQHZQjV6XbVphaY0/DEOQ+csB0+TbwrefT2Adjvv9JYkX2vXP2Iudes9
cJ6mAN1YnAI0Z2lkDFv34K3LuKjWJ+CmundyQTIfgBeTwG/OjmE+rswOufz8mU5Bp33QdFUwwQjK
uh/Yc3jZA+YpTVeelgHlap2cSm3s5SUfB/m6fBllXj8q11wtkAPVNhRMXh0BD49ks2rj/PAY7DvV
70BmnMGSS5oZB0kNOdriiHw0+eiT+W3J4oYQSuWK7whO4ciuYKx+e9wPWESNZVY5oZ/stptL/dZL
zS5Kzx+GOiEuRx7E26fKXV+GoU/O9DBu24Me+YluWD47gfRGqgQos/nUYm/gKoW2Ns9u+acnwNVo
2h/bHrtjsdfcwFwoJhmduIJJmNui7ce2jExptUHAGN54nfti1TlCh4ld7P/jgAlxKlSxqPxVVnbS
jufGFyFYQ2J4QQgCpc2vf4nqdxtvlgG5Kf4rkiT4D6T3OjIM5D15EtvOnaInz5JticaW8dNS6PBJ
UmEKzgjPjSV+Hi3uTuDSYGnbLLA4XmRxvIYZfDT1nGCiWdiTPMmaUWCItNxnbp/toDGqqPpNqb6N
9rWvddp/Ud/ZWLRfHVV7XgVYP11uKTU1eWogBoMxC4rQtsfLsKEHMb8agSfDk1CHK8SJI931uArj
MUsKnWjhs+Z2sPaxkv5DmeyOpX07qdjOYqz8g17wxrCSH28qCdG881drrVbjki5oPcf5UAwTJktl
zub+K4s/HAjx6h56+VLAxW3KlWPsOBq6bAx8N+hLzJz88jwWYABNG4pYzwUMxPTeLMYtRGDk7/6C
tkAtzVMup1vR2ZnJWOZYJMyi8IJoz7eiO08IoO/kVL7h0hVO826anx1sbtQVQAvFi1jsGkx93rzP
hmtn8022jiy1fxuDQCEqh2yol7rpIShbCasEZTOTsuQhIVVcB2MU7W77RyLAhCynY/ZIqBFYKvdr
wpW2HZ2C6ZPhYNOl/yJkw+Kz/APO17zIzTAAFFk8LxTOPnCHezQI6SF8ULHTQdgaaYCmyUaRa4RO
3hNlMm5AZCCvKcfHhERnl0qwCH5WcAxXPdREyi+Ws/OuK1WUk5l11a32K2xdHlrkeFgZqTfqiuzQ
agXFo4g9LI7XV4uTTtD6U6BLG0th7kFWZ+/kXE7dGxHotF7Whb1m+eFpiUtw0Xyrncv1qchF4lex
lKVe24bSx6Xk/bvnVEkHQzv1vEzbUlLjeBqUtZ9cQAVm4Vv/jOo/IqF3a4dV3C+0JTh4TbYXMgo0
qVcXCzITmRMbWaO8oNbF7cYbt8PIHphFVYbOwsQg+QkoAgn6Vbhqxg3V29cltfZaB3/2oGRKIf95
8Q1VM31+eVlb2zelAQToDLTt0ztwJinO799m3f/ec/Na/QPFakiUF+ewB/1SkVTEyVDxTbiIolW/
FQE81OtZBJ5NlcmJjP3pPEURDkOOCUCxI5Ia3jwfoA4Ddo6uSvHrdeuNEpaqrodJL1Yf7qzKIon+
5+HGJE8b6z096Jw3HnxwnHrULhnkWsHJicARjkTQfjj1kGHHNLtMXqHr01XJtlSQI5FaV1PZgYRD
xAbIeU4DNK8dzW9OFyaLV7HoQGjVF+5ZT1wNvzjx5l6bwNxPha9IHVYIaWnTk+1v++bCb4uTeBjv
mdYqCnaa5U+w//staCPewCnuCOqpQFIYwftSjXGDH9IjXAA+zFiHVQoCNK7/iQ8xVkc1LfITLL7d
gxomaQVra2SwtTTEMimWrgdjSd4KFdSFYf053oxDSan12Qs+eHhmCc1dqmws0r0qshyxGN+5lzJ1
npWEF8mfFIdMCO+cLakJtEGgcpqCWiFd2vooRZc5YbLxh+BbUYcjMSPd7avVgzivVemiFHgq9zVT
Jc4nm1IhrqGS7MysWIxOpRXFZ8Q1uBr2C7M6HVd+c2ODUflc9auOsW9AJXskcV9Aq2lRsD3mkVSc
lBJ2rnompRaKfghI4KFNBSIE7+1A43YF3uwqsbsL1L9T7mp2QbtLLGXFfhRwBHhSt/DYk7sq3ARq
oUPa9LGXqeIAUsE34d2uYKTGIHHye5BuC8n5CPZsjdqN7kp4HdHEGkeqIwR2Cp7smFgN/CzNc6l/
DyOQJUtaTHO/8ng1z8gg7BOhK+OWlv/4rM+D1NS26bE49IuZuGDwD34Og9hWGG1qzLhwj2+ysofu
M15HjmZBzT4k5laOfKOOcgqWu50z9xtHQBhmXw8T0msR0xmRP21kIfWd8apE/30TzKgOqRaJl6MB
/g6sg/THzUQxWQiicrK4NbcbohYyd584CY8wtmSYdU84N0BTjJ6pYCh0S2fiLtIJ6O2AU9qPRLpA
NtQgFE9XTEN+yk72mOssqRuNNed7u7JvZLD6yWII9gin1kXzaDFriKyfkhWurNreCxtl2r9MQEvm
1pgNduXrMiJNfl6w44Cc2UrLHs584JIeXKWdaxoB2Icv8U36X1IVnygTmDA2ULmvaKkW3JJY/QNF
ZoQyiXgBSrBC87roGKT+snC6va2JU9KbDxMVeWyhsq1ZBxSWSvry4saZyArUnbpyQu2RRrZtUWKX
re6XLCjMuAegnULaAzeiPg6jLXQl3dTGyfXyy1H3Fdy6d6PbHVXMjR772B6e49B/dwIJyoO0Vo61
KIYTnfAMGEPIuWAH6K757+IQ3AiaL2cn03A22uclEaCKnLFeZghf0hgjSgJvumXM1PaM8ol5jcLA
iqEsdhSXAFJiYni5BiYYlj+VDWcRUNvZNSNgNXfmxXnjoE2PIRZuOnR0dePpdSTa14cHV21NaBgR
INh7h4g7ymHaGOQ70SI6hepWx+85lo+V10ehrBuk6y6sl+Bxspe5n+m+iEKWIJ7y8m3uCeGUlYUl
orLNUkksmTHV6sQBX+MZQModD/EY+Hrja1LtVbz4cjlIiKAcL3T32aPaBTtizHy+A8jtJ686p3qg
hr72Ki+tzZQcF+onXlbRSTOAo9YgFwAjZBTZFBOsw2kd91M5vt0xcBJdYzo1eQwPU/T2Bm5oeBWW
pTfs0YSCxfPcXRqFlSkm82aTiitKQROChNNoQw5jawDLOZINjFFWcxKgQH1JKOv9aB3YpjzXQ+DD
W1u2GZ2QvR76BuCcX3TDNnFrvphAjDbOURvKQxh2Z0z6rnF2qLE+kyYDCuZ5Wa9RIy5rUriiuADG
ktumnAExQ5mwYYirhWzTymLwa2e4fKwlyEXxW4Q0qNPLT4HKXK1tDDFkNziTdwR7b1xfFbTUYMsc
G4nlXzGf2Zb6KVs6r4ceP4r0wexjdRn3cYIgD15gPTM4luPqHxAqJDgF825FeLd8IrbOKLMM0bX4
PCxmvazgjJJQV3XqWQt1BQZxcgC6mxPXe8T0ND3TCsTYDBZ4x97uYCvZlgIP4v4Tj6bZeL2Bhmh0
y0ZVSIU9n8tG9s2ATh+Dfwi3NUFpsFYdEoEvKfReZuzz/tTciarAJGtkmfRLjTFMJ0LG6OLcNp4s
moC/GYZrOkJG2cxKXwVEeCRnqCPalIus020OJAGxP6aeduqKWuQtXea0DT3XiBWiKk1vWDT0PFph
E0Kz/Fb7A26gBWaFJsw+aGohoJRJLSONBic3/M/iiYHCfOgfLeavv/jiwKctnvBgzIbQacFz2uz0
TLKdOKmuvfxeicHYZsSf6VmgHu+k1/Lfa103JWOrMe7vH33EmgRHBXdpo5VTLv+rMyXfJiWnr1Iu
d5hgTZL64NAhjTiOrbl+YpIxGr0OvR8+caXaLuLoFndTSJrEezgNRLc3zv8Xm2rG6veS+1am/K/i
mE/V0v17itYzYgOkUnk5A4ceQYDEiew2MCluFsY5Pcj1tnAD2HWxPngrBEeG6hzDoDOeVxF5q7l3
H2AFNOVBDyMBKT+UvUFfd48oefSxnSZncjLMJW0TZhT3XHeM859YJAebvK14x63Cs1KoUrUCdITR
kMQqtHNz7ACkXCCH7ntUzMgyIuFzoC0dswkPwSBHo6TIPxHZ8l0SBKdqFimzmjv3+CDFWZ9xEZlW
x488L/bY2T164EUEqiWlSP7AOKnPD1ZzgM/bCJKMEaz4dIAl9jtu55mnv3+6Jlel2J0rS9vhwdqz
yhna2VqOu6c2TcuN5bXeLJAE7ADhJoVg3w+5x9VuhN2g7tZY6KXqXFBI688E49VkUnWeetpThR6B
mIFemhBEnXyjdYS+BK9TfQj6nEjQsnSXcl4s5pWZY0+MANn2lN9F2nD4b5p4KvA3ggJriCSF1jhZ
nr0BpLHj6MpDyXaoXuWsyxAFUkrRe2L+6RUU9p4ei8qjftyE9QtyPsNL7wyrvCLqXIoQd9eZE1dn
C2WlXrEvLrBZdQxFX63zcKXDIYrpjzkKdcKtfSb0oo7eeFNbTjdfDOiA4agLME1QaZnhrJcM5A8E
PU+l7oWdM+E2tdRtujyWAcS24v2mMBhWngOhYPtadtjZa+8zeyNMUgYiv9omlUazSvkt/hTVOIaQ
7hO6dkdmpZwpmEPRkCkYJGJCSjfwFFxdrSNBwcf8uZZXqlhu/aCbTMuI+e4yXf4xwHOD3Pe8OmPq
G/3IZ1qelivMlxCQi2FUuj/OhCJTyUkGM0zD6qdqxDZ4Sl/QkZZ6C2PM6ir5Oq/42TQnlz+zsq7F
OKIRlmtFMDaNOaxaYpaip5t7JVro3SgUXcLu/sMhX423y5eolH/78Zbu+az3CJbNTHWn/dY3iqzQ
3xwg2CTriUPHCiU4pw4HA4HxYxn8ujG94n3PazRNhlLGo+TVyf6VNlUNe2n5MtqrmLKRsWFd+ASW
FdCHyrAoqUjIV3bOKnGgrxuelNAv0vmlg+1mfog1H9aycutqRab+TwdNLLytQiqfckxXRTmvRHb0
UMH2JK03bJE9ouFdXqjmr7c38nqwVK6CHf4CK5yY0Oj9Wlvyl6qD/2FKRnUKMh6m/YQJWZP8xsrj
n0KQ+S7PeOmPqLts+4Iz4mXwNlQwbRJwlasjky/772mEsBhwws6AtDiGk/YktLhbsbUj8T5Xrcmc
gLztritHvtGJopMOPOLjHq29sDVbb55QTV0Lhw7w2g0F5Ln1S5eBv0h2TvV13QX2jHtGulpAYTHf
A8a6ezEjTO4uWImeDpaEvX1qkBGBHOoUQ86o1Yu8HpZ+ZiRf3MeziNZFnPyrEVoy2P8OuXSFIqgc
MgKCqhNKjOrgS5ik5y/SYMN6mConyf6SWQXqA8EL55wx/Bk5derJqo4qwPavOJucd7KkNDJZrr8D
stVQihM5Ode5cS+0+eZBqmu0tCcKxjbzzfnwKWYQzEoB6S6xR4iIkG2jborD/i2hP7e5ug4KNl/g
tQLAJl12xpiOH3fnM4Vgy0AkWy7uDjYBwF19FMIdNwioCR6jyVFezzGbGAMqLcd9NgmCis2L9IAA
/GzXLcla9qZYxmgZ+qxwgfgR5nfwlSbCrgyAbGgGcNCMPBLxu9pbVBcnSTHnvDHfQjJt9DKCng3H
aBR9wSmez77zHPd/zSh/t1BzwVYpxBLEQENX0wLmtscJA0y32aRkgEOAkAg5IT5+aQZKZxepzLck
tM+JgFR2pAF3Ob7tUdXBt/M/1vNh/HhOLr/2VkKDCP+5ppZOfrr1VFYn/niKT0YUonbWRZIRb0XN
p33p3h5EvL4k291Zsc/YAnPLR78EsZXnAonD3Qnv0DaEKE++kLKeWNbWEZWRZGfxOckowpYm7SGb
KqG8qePngHq7dKrfDimQwf8W0zZd+6AxJA8nKsbyiTyl3H4oO1hYh5kX+YK1D4RJPv6AC9wNqh8W
Xsz3FiI2PKZ0WRbbO70mhFYSX4U/HJSyNyr615RP3jqFsCFMZUubtdYXSKZa310Ba1B0Vy+Y+l6k
jP61cQ9XeBDGDzjdRo8TZLiUF8nA0fEbuvN0k++2bXIghF4mR/jj4BC/GC5drsGi/aVAYqMsWcc/
HZigq1sWYQy7/xbUym9JEdvkl9dYplT3R2F35f5P6fPjvvQeYbuKTWpd3nIvpwnuwLWutFB96X0R
+KX/EBp85Fl5W7R0Ki9fgq0Qp1MM7a+N2klVCGq7NQAIatMx/jt9X4/WgBNs4FWia4fmGoWtZYa/
Dn0Rl+hmhH/ABVuFacx8TYj/9NqPQaDgIlDAsK9rdh9Gq/uxV4mqR43za9LrvNZEI4DR1qUGpK8B
rMMre7TxNwhCXCd14yHCa+wqS+QDmsz840zUbdtwN7A+b0/pMzDjxJf/1ZNkRu/X7dRgRGh1Yoty
fRWRNSkrv59hHWrM41LtCziMbUAqxlEWoQUs9wBG2cbOKBlZHFoL+7L9EpHTljyomtKV/mOHBDoH
stutIxlnEftKWo8uIcmvNqxlsJQ8r4I1gfAyx7FAcsYhbqcbYa4CR9C5khOVOevMWYnf8mrlUCWX
W/ylB8lHvoZdQr38wGJk3zWhAWXtXNAMvjTP0IdE9PRXKJytsLWSBiRR2a4f4jY1xvib18hx/2b8
6vkGXCan4LHOXgyMW7LvRCJC+4sS6PXMfwuQiWCyqxuCTjzknQFkHOz2fUP0J+5drH+Pi5x9u4nr
hfE2SbohlTiRsPqQLcKWXs51tyKtcCsZMBgBqEY3ONZSQPHn5V9AthO20+Fp3sj9g7IbaK77pLVx
lwbBXd2NYilDGK0uJl1duvsJ7tfZdVWNJTnsBIYx8mqRiheEzwHnHfP38Fr3nRbQIioMLiYu7xH0
TpncEYcETkM1VIxcN7kxkKV+E2MNytbjzx4RHWkWvum9C8zMgDDPT5vnbFn31WJhYmBk11tLbrlJ
laIHL2oAm6R6MQT8WBte7+a6mDNW9TKG9ac6kI3ob2Tb/V1E9iJtBjNRTmC3X5nmIv/giqhxkl3z
yXYBn37tMznqWUlwtdVpB0pUgtYu3OFRMYmL/nKt0oSf/LGkiLfwbjgo8pylMS9PnA6VYhlW6A7y
gjfMLRcvpW348Xxo9CZ8l6ygkHMufCwyXIkz6ovmnk0SsBTt4Ula8IQrcdM864SVirDHF7oRceAM
DhIg+qTiud7PcC/tNQBZ9Fqbnug0411jwxnlCNo0lxIYQN+ZnXex/alsXYfv+F1Zi+QPFVBT+V4B
Li39OFUG+U3krCOURv1bFM9hbluSMgpn2JidNQTKJ17C+QfIqyaKaKYlA1mEvX8sJs2N+teECi3K
s8OGh+bvW9P+sAKW/+/ZLNb3WzzIXM3AYkjeV12LWKYcdSQ5uybVgkfrUsdjWtGOJLIalEHAf1gk
VCC11VVkvyyn1mfqMWNHm5hh2qM5DK/YLg4cGdUHJ5TKzAvNDWNUtUhNPXEQixxJJl3eB9Steg6M
22OeDObtxkwvEpXuzMq9u4tuqIBX5SUQNO2gLQxlVrcHWpBg7qg2Yi0huUrZms8IEloXZ3smc8eq
iFfKVYHnCyzSlWCXcjIlNoFwb5M6MtriqCX7S24EX+j5gQVUHK4758l/H7+SQUSFd3uLU/P2ExTO
pEGHurEsEpML7FVCfEEGEg2ktD7j6u6j7+RZ/as/LQojxEtxRCUjLtSoxTC1ZtXXSZHShq15TxCQ
/wLSwuerW8WB3AL6dbRGeuxtphfI5qU++x13PgdvF1r1j16ci9U5HBPho3Vyrsl/gCrj6Al4+JGS
C8kGe1UPe956aO8yYbA865XIAQ7xbk/v83oUOsicED1/hNq2PAv+VLgFqQjqH7q4HoXx52Iu5ceO
N8bQlXkYeKq13ElQGTkw1XM3JAZ1gkc5tOlJ/nSdowoQzJ5KpsWl7FrKt3qPQzdKltnYaMzyxfNJ
SxzOrviTkSOmDQUyEL7RCkbTMV0S0VeObTokrE9TIaMlveBvc35GrkFdX4o7Fft4T62YuDF08DBs
nxYeAB6hpJNNgrPiJfI9Ert6ae5iZaAXgUOeK2w2AewJj5ufHGexCgG3mLgPMRj/+JZWp1ESVIpZ
hu2BvorilssnWms1fNcJoYg4exfc96/g7xWH1aS4ha6ExxsrRCYb2uh7JG1XinyZ3oHk4Dm7aOYO
yAZF/U5EzBIqoq+DDibqyeX/J8EpSTZgG5fQ93+YtyvbfmxhyIHhN1dFYFX1OgYBia46IZsb5Wqc
f0hRjFddCaIvQNlvnwF51/TfJT+MmGVgSjwzWoOw067fzU/U3B64UrF9j8bJggkLu4tcg/58siVX
2nb8B4mlQR/JWecA71dfD2MgNwpk4JSLkc84bxR/cCkrDAK8lAQI4BX4zTRggXaD0Nomznvje+0o
jRcvIIBfR2BKWfatcSe0yHL4E/vyQZHkrsJnc+MyynAW2Jt/xMGsBDfcB+s0NrPZufRFJ9/ZsGM8
Z2Nz7oMW1v8Zf3kM2IkQsznEpZnqlVaudnXPvAQL5ie/FxBALaJY+Gl6VnNMoPnOxm7Rm6TAEW2l
fG1VzDsX+AHdrbzQOoJWaQTm48NsLQA5IEXg/DcLb43roGtGuoOv8rpD+ks2EMLra2veEG573liW
/OjOT1UtTWRIlmv9Qeahbd59HbbqQosUjhbTlp7QOypCx2OPpH1rUx7v1Lt9Sc2LH/HmsXe0isJZ
q4lysZYTB9CqxmK4jT9TzHc5doG8BvnEelHZz/UxCH0lxUYZMVEfGxWYNreS0wFYgHaAvYunRLAl
ZQJYq7BA0jM+v0XD8/u42Gogi+vyWKTSNHo5YxrLc7A2zAwEriHjg6oRDP2BzxaE6iTNiuBODW6W
ZjEytQNi8jydAUK3EcyNHKFvL3tphjWkMobmkQLDMseDYU5MfjzaNGJ9RbbLM8rnUI6Iyt2o5tfB
zvHkVgY1dt4gN6IAD+Cgr5MIJrszM19FQpQ+4Wp3Aumckd17mAk9ixz2rhO3Yu8kRi38Uqsej6aj
4dk2jhUgxYCmi4R7yDX6OJ21jw9iyJlsMC4WxufjFe/6E4vZNqvjiFlnk637i+CpMwTRZ/yK1Pos
JYEoLh07A6PsJU/I56vznQgUX72AeQZNFYCOZJIWpZdgzosnynV+nitXgZ/5xyMCE4xC4fPTXeIv
0nM9NvHtRgZBcJHG8spt47OWLzgI9oZJBOkntdlkEpoqCCK9+O6bPYR93QfK3wORjJ1UBG+ewycO
QSs29gBD0WLlgb+ocJQicAqubTGcApSJxgPoN+xWQoSZtJRf934MoHuVMV3pqqtho5TJ2jlev1Tk
PbXrDkuPHP6X2Y5I2sU6LCFwD2W7cgG0KbVjlydwo+cGYmcqvm/EOl7TCiadq6dvAg7rt8afy1uv
R/HvEGHAuzikctXczefI9XlRHwZ39/5ZhpYAr9z2j/cftc72ldwkQh9ONfuZWt7s9dDk6/VzmIyQ
er9g0/cckH4CiNTLsh6Ji6ddNXcH+PqeWZojL2LRRKz3jMkesNgyVEfQstet1PTTCjypKcK6if2G
l2rBWCYcdHJvha4Pks6dr+ugOBrMn1Sv4RqhSGWbe4DerlYLp0HKtsqaUMGB2RkTutGABXnV3yFJ
wlQwLFazOdSBvB3Xi8BfOM5wnFfQYeGDDMYTR5M82W/y9L5Zm6q7RiATYt0akvBFqJ9uHMVKbrW2
tOWyv0G72sjc1Or657FYJeJgBZf1+11Pyt619gTYI6Z/UHSj4hUh0uc0Q6FhV2ixQV7bEtKo2gkX
EPd0Cn6KjPvB8vh0aYHrzqQpjxuRM4r3o95aC2TnvZhJY1X0XOgSOrq46Kz5guhCuK9IFmBY5isK
sz72Ayk6Hg9lfgZ3z3OxspFGopYR9W22kNEd3RMfBcYKGMVCeC8v3uCOAbFJqvCHASp/+dwTIVhd
rRY0jrvV9EUzTwZKxndot+vMQDpT4SrQ6cbWTknJgE9RagIOtHDhsETkd/SD8wV+FieusC5j02nr
WolxdvSaShk7wpzyZ5+X90wf8enRy7zafCvFFTXRE/pfW9tAy8aVyO4ydk3TgITHFKLbq75M5pKZ
FNdMoxv8mX3ezDNjS8f29y5owK/Il6zMBkq7ISDjFKEAfMtL2/nqB2teK6AwtszE//ntARPJNSPk
qN2J8RrqNDjZcTRxb4SB+Yq9Dcfb9FC2Q9d/mKE5cpsB3G7klTkdfttMgTrZPp8uM6G/m+IUeYox
Qz/HxJApo+kmAYZdUku3uk2JPXcvuDxa27I4Jp5nDIiKpVTGtkwNUt2/skb+BcunMMS4JQW4H9qp
FJ6K7NESlGEUxdvdU4LIN4UMn5I0Q/sXksIK2VXbaMIo1h6Nk+KBLPktjj3/jXn5L6Ez1LQxcxEl
q644Kpfa9IqYnf6lt90GrO/gLBv6X2Op0KILl5mbVtNtYbnOAComGDeOA2PzsLXI1nswQ7J5owwA
u9vGFkTN/8KJJbd6VwJ3vpt1FTRDMSv2uYn/RhbdMfkC5ufexEjTCyfd/xn7HQ85gCJXxdxz3GX9
M1hXp0SL6+fKxxpPQywPfvYX5n5bI5+4A0BdBEi0nS5BTb/Pvb6kDZH4Rc+wXQuSFuEbHgZVVLH0
COBKorAo2x9qyzl1dnZppzm5jqlJIIFCWTFy/7pzaGZSkwpXPo3HQ1olOvtHcbc+Nt+Qx5O2zhly
cfM/oOUNcwLPGyGLJxKGm82qb7z2K7Tf16SPIGh/3splcVC9kH4FcRwm4D1FQLKHuT/7ATEfq49r
O9dvFeVyN9QDowZPfb9p0ZV1l5Ma8Mvjmy2HS29KbPNCUUxT2STziLaIJK59/qryxjiTc2VjyoBa
liu+bFV/C6Grjbc34mUSqayDYn9gZ43MBTbyN73C3gQzdBNrzvXTe5G5KHzdiNnZpvM3whpQ/Rx2
zVAbm6jJA0tmYGqMXf51kOulcMdCWtt9rpuGmmamz5rCajOMZs292xwNfzwSVv3EXQ9fo1+Wvf63
VNL1eYzbpxbBszUMjjv5Z1hsswYBmRpbKq4hQBFfzDeGa+X1vlYPjXpzxoQw+AHzNTunCrQNqFC0
HiATWQb6EhKECfID3iGuk4KoBkXp12+Gtx/KKY/Ft514x8gE31RsLSDcwV+VmrxG4dUb1j5etMQW
TGqUWnpBj4YMujuUbO12WnZPYFikt4yvzYUMQtG42bCOQKKupNVDq4Qxkjiinc6qFaq3F9NFrzfY
oniH3YxU0L8d4BigKVvr8AoCqPYesVsaWnjJku1I7C8zHbIbQtbnVrnjh11Zx3FbH1kI6Ua0B8PB
l9bielQOCJcbsviunrTJp+XHwk4d0XS9AwVntRm+3PFaPKzJHE5shLBE6671TqodXKQAzOB+T5+7
8SR0R3a/IATBAH3+tMVAPD6BsKW+IUcHnRJqJDhclk8ZTrYwkrGZVyEzta79wY8f2R5CYHcsgVOS
lANB5bD03YS4lgne14x55zIgvGY7E5gGIa423m8EuCodupmPuvdLmQiPKs4SEOhMpDXZjipvPIYC
GYuzVj/7EP3u+hSXMwYl9lLixuaxzYECxFV9RJ9Si7YppPlo2ZLs+xUHU/D5D4YIHtWswz2TS+3z
lOfUoppf+kZ0nHW0S1LXy+i6ZmuqZQ88L20h0Dh9qTHf4+mQt/dbiYg4f9V3lZ38nsGcEZ9p8byj
cWFc9rbUh0AFxuh9J8Krhah0q2pSRxe2/qLLIBjWVrAS6WzCbBrIXc6P7ZT/fuNUcHHVwnUphpEl
EXhm+3oV79jGNWaWpIxwdapma6h5SCr4rn3dNZmg5TosiEYwxPehXaGS8ICxhdomfGs5U8FbtYPf
WwOugN7q+C0z7lHCR9gnIvRzQaYaIRfJR80rC1XRIYxuyHyj4io/q2Wom8Au+uoINeuNSq0YrWxa
+qc4Y7uQ3NkKt9Wq3u77XOPVpxSbKA5KuUr5UMSOa4p+Fqfetid6sX4sC0iBT+/aM6lTeiDSNcDQ
N5trJPVwAerX7Mxa2Ek6S3gjMegbvJR2BJh0m2vORE3kLNclESss6oQG9I1M71+sWGzg4VXiV1mu
9b1xFs+ag9CpFfb0oJVbSdnVOtyDjwLVYob2ZOl0Iph3qowAJwic3M5aZpGm44EQNxT+d3Mn4b/H
Tq6lSJIrHhqvXX75W4vOiNoaNScFW1df5FxcD78v2Z1wybQz7jXNdf6c9Lm4M/Y7QUHkj8nz5Usq
j4/JZp26Z1y8kd4S9ZDMGSBlBb+Ud+c1JHicUgGgUc9XTaiq/mEctaRMZMPWSt0ppwE0kEwxR4ho
FrsnMVouzvyx0ufK8qhlCUQeuOQC0JhUSH7x0AtXq2Xui07UbwRpwwf+Hl7z161vjvH24kYeB3XV
e3DAOKqUg0eR18w2+pUfN0O8MyS/ju3DxzPNwtgVfmDIcwNDqAMh7cBgFXsT8DJz/LRvVIDfpBYD
5F7fz3+0DoD0Oke5NDaZ33BlctfT1EjngzIcmNFayLi6jM5Kusq495WZVaLKK4pTYlxzwa6ep7vA
BrZz1Qrw86hakcTOtzADW/joEs5UvftrBS/MDZG8f2lHTDE6ilcWptva6IeLbFXCRyKh/tbbI5h+
nLh2EnZVY7pcridTdiPjzgAQU4grbBN0fd9HFKIMeS6Zch/m0VRNM4MBcVlts0yuj3NZFO6X1WTC
Eojpzto62DlxiA14p1eBueVfGYvtCN0qJ+kdVKrXuC4P+WO3kyYRTEVxL92y6kmEDNu3LaGKxulV
q368GZYjJQVQvNveuMBU6Zrtcfsde5DyCjU8wDMps81ysMYewZHuJZlNSbzOvhVdx5/AfWGptyt/
TALl9EzlMU/jAI/aEbo4XgfLC0xNrDc1P9r6H+ENnOfqFajk+tkxUHBpySIM/9wm9oQv15YuzefZ
6y5LidUH0F5OhSO8PduDPUEE3ItWVYPdPPST5S7a2js+iCZcAlY/gixTGwgUqLZ6CA6h0D0XhZIC
MBB1axzykCZEeiN6f9SZWSQbE9rLTJ1sYBLjmvGMZLojsnVa4qiAZmpZqVzgmR1gZyCmNJVf8Qh8
Jqmc9fVAx3dz7Q/P/bghhjVNfB2l4FqJk8vY/s7fIDQcMBjQtfB3jXOyKBjb4ndlFxRlMCzZoktf
Ysa6u27FTY4IP+zBQbpzHH/45JL4o+FPCMSDLzlL+8HEMHeylkSRQICF7YLFH0LKrBnXH7pcScSe
nw7pk3Ye+cpDLUvWkokR303xgTkBvSSXGQfCAoMGYgr5Pc3enZUHskxFf7YBmftKcU/LQC2dAXG/
tjNcIPFTJ/7sK1aPvSCWj5pcGd/RtjRi44I9iBEVnXbIu0LYTxyC3wvI89mdvk2XdLc68r4Ibl5l
JCgGP1gRjqlhMbkj+Fp0pXq02mq0PTAceo1S2SF68bnANOJRdgtFVU4ob6QfDMxYqzxCy7EXpd43
j1Ttn7wmJk88aOf1ZHPvFvRJd1HsZ2ivY2k5yU6hK1GxxTjbgY1+PXTv2ERcA0wTBYe9t9uK2UGS
RObuFFnA3BhQE3eoqd3vWyEERQ8EkSiYuaIgtWgsjtITJvuKM8pi3HOvaw1OicF+ISWf2ue4Y3Db
/6y6Rd9Yo30mR0PwC11ko2kaEqut5qfWdb4AaQdz0dnNSRlm322ng4ktqDUUN1TP26+Fih01F61r
4OZ5BCplCpDlLX/l2EXJRykVrm1qDS1EBXyzsSQE/d+z4w3fS0wm7yrxfOdf8yOi7PeCwsZbQdoP
/nLIQ6Fp5KvwkzNjWCi1EDWKmKOlFD6BvgUr7gsSiy6aNkP9WXWuOh9eOz8evTDmcVAmZOhLJmQv
kAnuA1eYGBV0RD1LD5fjX6M30rhd7H1ZpenVPgQsVUFvhrYiX9O2frRttHQJ6pQFBP8lym2WvFRr
yNDk1ECGGtFxOGlxjOaLmBRpa/lpKVHk4fPK+gBU3oat1nFIufJ5KckjMUJaWSHXvFADqe83GMiC
CZTbClehrP/Hh1Y66GVrT24IACMYV5pHGZk0bmB1F5FlfibC0A+tPAzgEGDGamapBzWJIWoCGbCi
6WQ1mWEVpG71GPpG77KMNCvvPZiYaGMqq8NFZG0JLb54SbD/GOznvKlW7rpmuElgMMDAdNDlZ5iB
zAr9g+7x1toVAyyDQ2liI9zBcdMl692GoGfdLBN6ajmmuJb7CrAdc/NwH5VEbA2DpehlAee5wWwT
wvA+M3h83XRZLJWOnhCX2Tudh3uultUBap75vIhcs4NKf3PBnj7MRrAEezWCiebYtYj3u11IOW5G
I+LagQqtEusRv47q91lx0wO3z0ZJni7U5Vg/bjMIhwEqm52RCItqYLPN7lfcFnVj8v2b3lSJWju+
2IoYBBKphM1/VsUmBv3QAfn0aX9lh03xUVE5Moc5rZGg19sGCE96cBw6L+g8KKE5x6SukBQXW1jO
weCfkq5qNIan74Smp1RwekHRgZ3JHwFTdImJVQg3N3TDdCkxqFL3r3qdHoQAVeb/WubJY91slnSy
qycfHZ19rmQLQRNapY9Cxjx+gOIviI/WED4IGt8NjzPqVN3XWWAOfRC2bpvxnC22U7V8Cfn7qQIW
B60hzpg4xcslBiCZnzYZZz2f+yDk0zIxQ6sfOqj5LbpMzvnqcarIXDVG4Qq4xC3ZFI2hKleV2t1t
sM4Jr5BSZrm9etywGp2QWl4Tcy/9F6hSRW/Ua+lq/ne5zSlq0eC2YWp313iD3rmeiWQS0fmuiQqZ
UoHV7KMslbCflOhEN2nKKuyamHJvNK7Kh7dYWcTXpfXpgzr/K3M4y8LQna3/6/sShi7RAHp3dvgi
AC9MvUANxVophOQlnEwQM3kOOsgS+BlGQj2w/+lQmRRa+gInRqhOeL1IH1Xa01G6FjPYm9y6HUqa
bJBtLgE5oAmOERYrP5y7vr4mG1fSCOMzdpsr9cAsglDvDhoF/XucZmfIWtsCXv+M+1hBCu3bQ52s
kiu3t2XyQP9QCI/mkbC59i1XOxctFWgzD4KkG5npj89UqX+u+Hnrx1xLDOrvTCGWv6goze4x2uVW
figPkiMs5MoPeKwYrMjwBc7JkEJ3bqEX9qq5OmP/Sr7YzjhRJ6D1fuuDZxpuxIXhtN80d35pEWXs
l9xip9+aAryXrNvga91VR4nXoqpxwWHYqCsJJ8+jPtpAbDSahaf6+PvpY7vVNqgNRKXwpaT6bBsc
lSf1z4MloPkWBDBYGFm8ehKy1w3nS4A0TNJAs2zYDs0LrAnTYcxC66vNm2fC+ZEhbqfg9EupyDjd
BjBFsYYSIux57a5SLdkfhHUapHTZ+dquLwqW+XuFb+G1AoWahQhVIeHLzq+KvMk1/Xz1U/G82ixd
0qiBANqgq0dWIy1G7HPXbTurzI9uxCRO5azZxN7+UPnUvFmHUdZT+Dkr4OIYUiCgFdMlnswmI79u
TaDRSiVbh313KkMDVajRBKHtgXb6zkzBLZSzgN9q8tVGq0pojnPdwr53bKIZJ1kZfuqq7ECMoMgC
lXDnJy2YX93IpNSzairZ38FG21Ob2E9qUhiPWoqPND4upGwcJVw5j1JCbMgGjr5gZ0V03btJ49m9
r9FqEW0yOdC8yaQ/ZviBXhxgEhZ37t4Zzs7G8n+kHP/JXzaFXN2A29W4QygV9LoQxSr2zloIwSvl
FUVGKcNcEnj+ucrdrZZSw0LUWEQUPDxH4KG8TfmjW1SK6B6luA8S9i4o/vdrGvsNmf0sG5i1454U
my6SLorl5mpa1uTBrDESRj0S1Dc6zKaydpgmyx4YOiR0fV5DgcMEkQNfX/rM/dczNnE0oBhR+H4g
SA0b5hzJ2FAk8IyCTcvEOkzjGbqGmyGUmagbTwcmf60ushT19XIAqdcGRF/tjQ3R5WovlCYrnxKw
p2PtaJ+lKDNBflUJcabIkpLsep4UUNa2kMdUtUj3h92FDcVD1/cf+IggCmrWkXIDJWKL1qdTg78j
6ABKSpvxz603h75R+TuhZKj6vgkPT9zv27Uvp9Qrh86myEKfmxqxxPSvz9FgrWrXrjZqsytH1+DC
gV78q4DND/IIA3/ybZ3GcUpPLdjL9ilHHdV5GFLmzBp21fADIRrpSQ1IhQfzFNBLosUdYr8Klm9P
VaTkasXtd4Lw1kyLI+8yE5S/DCiSRu5eKcSdKuMYFZPSQP5zZaWxYmhTHTY4FlaCFkqNcuhwxvxS
/UQMRP86XYtdX91czDUU6f66XTMFYORB8hfLFdVeSdc8xUZJ593ItiKu+p4OVEIIB4pm4LP6GRmY
D/qOm4y6r+FeZs2psC5WMBoYsCqYgZMn8sQhPk7EM4iFfDYf3aOhZpuPfDVvMb8/Q36WIrAzD438
qgWMUNAIBdGwwC4ipOZMZtFVmhiGjDoR7hAN02R2XTPK2hDr654vP0KuIp6C1c47sYPNcP3NE9k9
8EYxwlwsrP6AXSGMSpbMOGJg11Fzu9x+fwumV1DBqZ0kzBBuv/muzXionM3HZP2i7M5tD0yO5z09
mwrzWE7TeoAGSjdYdavskdjtMtQN1KD+U2r4tHQErd4FmfeEPpa7lG49qgcIV96711/d8CzUr+e8
JFJZXdxzYJk9M4s8UqBVKNH7uUc++284oOi82qV5QxJePKEEnEuqM8C80qNIx/2jNFy94BmlxW8g
Sx/12xFnFXhFiuPdR2DwC/eWpuME5NY/4ZzT62NW7KEn+uW9PBoQse2yUUpRMga09DEMWUez690y
Z0GlSTyObEgEQRz21a+Fdy+tl6EQboh2KmRtmAX3cERK03c6W5bgmD33ix+Ibz7hfTxK7nI95sEc
EhsbR6mJaUbKK/ti+XFsloFDNfcGytEfWN3Rgug85rzTQzTQT/yrXIVJvahGymqT0vk1PD3zl6V1
OdTzzxgwT7Z+tp0j+yYOuJXKwfaFzjtsuNVL9GC40OsfkSQS85MnWpCpCOoItSkKqGKsQscUfzvH
mz5FOj0x1ugl+4rXe2bV6tyvCaaXMfGpZnmXF+rIaxP3fhdOXVjCkHBgaS2QrjiEminc9NEqy2pW
hdg8pyvMtdcO5Q5WDJlof7TD/7TPy/cokFr9iqf+ag3rHgkEtG1VJWxkOTzpGthWsR3IGfqOpx6E
7yraJBolwhZBMNKkNXX3gNOmbCxs9bvKxy1wNJiyc2ywpOHf5Vkxi9+AIsBKpN2zI4+xfcCSHeTN
DNXF+iwCuJq68wqEHMFTTMdms2Lu6EAzuOx8ju/rD+jnp5x7i7IIXTDfaUXG0wMdnxUT5yB/P0bK
/utdlQMVnbwG90t9TCgok4PG7z6us6Wi/OLwey3CPyivH1dME3/fwZ78TkEu9r/CEs7YAMwF3Nff
fKDsEL0/kwcrM6RTRfP25m0DgGPOyFDX5kp2aTPDKMrhG5HjhWvx9iQyUR6E/4W1K3TtwSIMEXSR
tZr74K38aPHQ+nhtOgYeLwMguouQ6WwZKmut0tud9scEQ9suWAfL/udmAKsNXq0fOnNVGEn0m5oW
CQTKJ1YT8kZM6Taor5x8yz+IJW811t/zbsw/oDOn82o9MIAwqr1tm/Zxy3QY5Dm4o6SCbwUtNotg
InMsQU6YoTnHcYtorZbrIIFOKkeR2fbfQoPxp4DTOwQVn9rsOQiZFP2mCT1f/XBh0JrRK+yfPzFt
iajiyC1C8gKIX9sF4JMGYxwHlZ2UXHZAExypyEgLNI751/g/CCN7BYXIHg8w8ROgrS8K9d7QGYWq
7Oyyy+5tTiKtWeRQrbx9uIOWnaF03e53RExw/Uk7129tqwbbmb7Q27QIJ5pCckiPO7+b542nqtqm
2esmEScIg3NewPwxwtBhsOoeIsoqJr1Bexx6fKaD8wHWM76doze6mrmSPFxbB7kN1HWUaxaYTjgC
v54e8bIuAn+hCMYF2D3SECvfOnFElclh5gHj5c6jmXj+uIcK9QRwB7NDXMSscSo9bG8sIVIIK1es
rlzF1Cyv2C7ZssMcaZMnyAq0u5XgEKy2vfxEeksAnqIRm0Cch59Wtf16ZT8zwSh4dmOIYoTOtRgQ
G7yCvcLRHG3YO1rAROxUzI44yRFmd7RNRVYAc8BRUiv8WWNNm7WvFJDAKyU8X/D38x9xXKm7+xsm
GDuD7OzZ+uce3Ip1J/W5S55DfNdz3nM2Wa3ezhpMZV0WuqA0l/g1FAb7zakloFLoIGqRQXVc5DFE
HOXzXoYwzns98o4u3MRJkkcCu+lS9/5Hr58GX4agHWmOwicRykBVH5L26tFeGDalck3MjOhMPWyZ
M44pLRysuq0ONcowGJ/9sO+A1muTpfpqbVobS3gdOjLd7/Fou/ZTX4FcnV5T4RhfELLRzgSm4G9m
MJm4qv5UjCmSvFz+XF9kTh9AmEPORusFpgkODLQqgnYPSADgIVzPgJCoF46T9fxL7gixz91riy0U
4fv/YOCotn464vilUlVRPFsZ8a0p7BVZFKQ4EYqFqLwhZzRLYkCqo3ADJp2RhDVjUFkm+l7MlX8c
Cxb5pnf+ISV3XMh9maft/sUvbf4Ifj3G1YRd1iOY7wQVWIuHDHX66xF+FwkfTT9Uj1ScaH+jfeGv
fa94aXT7pojZ6ACk2t2qYOGniIWzAHt3vFkQgbMhwiz9ms7A2ekWdFEl6p7PLrWK0C1DOL1a8o2t
Q3dRhDCG8uipML5KZoEsss3GJJqj0kotIeKIyQmDeqEVg4L1LPslKknKM0Rdelion3wwfjKgNJFH
ar/VOf7dDfPFVEE48Ney3KHOr47gmAcacbD6L4N0NhuJN3It/p4ysMKwhWamiGreVWH8JZmja7Wk
h0wZaRzZZVp7yfoFKEB0YfvC0vDljff3AQXi2XIPiRs+h2/eV5wKdoMuaP0UiGHHbFsokBBYlNzh
a5dbmXVub7e/bPYAEL1BIYRdUODMh/+6+gDpGi4pGEAndpYbdqOsVHccugUHKLvgYQt7YdQeUcvf
NpD1lkEdN6KauUDq/HTW29+L4+trxhY5d/MS1azsPCjRs9z5OPsvQLXh1+Ne/+4LDQtuKzQr0LKQ
t8HjZAVG/65qS8a1I1mFFDnvaX/jepLy+gXNz3R65fYFjo9vAVPJS0RMLSUE3k7q1GFiWmRRBtp+
Gp2o7GybtM4HWrPpiBUZb2CCK5rZj8Zc9ApZU2f/IhzrolGLLRFeW860ZV2A/EipTBuxZ37tzzW+
rdRakqOwkq9zo08HEu3BNhWanHrZZqNf9PioQAAKNCQ5GZwhx396blFKoXS4E1AyfrY0SQ3+/xo8
bJNrlFcws/h3bg9CGFcTgXIxuRl9axyDPYgqDOfgczPe2u3q5DhI1LjvgsVO0OmYhcH4PuRIA0WS
opiVXshDdb1+cAhIT6Kcvj6luwFeibA8zY7e/3Q7Mq1MGu6TYbKgjCZdQcTXFXqw670hW7d5bsPa
rn32MGkbYtX2ozjOtFBTZpu8s/Z/S+1nsrQuH/uXhK+MH9Dezjgb2qEU3YJpoMSPw1YeYRZrUR72
JZ3Dc3K7D1cADYai9m77UGYgdO0/B0bHJNEZ6KsDADl4WMCYSFerf0jfv/u+bNKZ/H3Ln28C/9rN
/TfMQgM42JeBZyPfmeRQcbOQRuuWnfiMXQEEir/J7+C5qm2RZdoXRclIirHwjtFHfboVhLAsAK8Z
d3voJcPCn/7R1SubNApwoHh0fhdMjuwhFpgJOqoJwqitl9CINJm04SEJu5R5SDQaVMi1mh11qGqp
pYBvn//iyvm2a9jnJzLT7WBERIxWOWmpKlzWMk+vpP4CUHtfSOFE6kC9qFenKCCbDV4c3z5sVsto
xe+oJSNaWP3iPzxXPJIZko/UuaCrlVWq5SpT2tM8b9pB07wbNQIpsrwtQLt3v75mGO+x5lUuzU56
yXJRIZbvjZ5NsLjxYuySjAu+FnMLABtUKjc7Czb/uwIByIz1sxe4RFfkEjD8XfRHbRsSYSWEYk+N
FzzI4xTW8zYJAmkHI2VgRj2c5bdm4qlW0bKcIgyB5J/iZDLUln4hxETa5QpVDSJ+yi/CpcF0I1JK
n78IAoQ0cj0qAN48iaQ13eLOYW4EPxZzYlf7LpCcD47cteRb4I9H9K8GaCt1HcaAB/3sE7WU1+Iy
R7l+Ytd3IlICc24iWoFnjMy0GY59XL2ps9wlD3Gah/PeJeLE3MtcQsJRUxKZVQpDN0SYIFWdGrDN
fts+RNxMtfx5Sl9+tByGg877KtBE0iZAmNXvDUwQGmMBi9UxvOE19tq5iHMuoctxs09P8cheW/PO
sqerAwbRz8L9anP+Va3w7mrqZSvXEKnoF0ajdTyNZGejKXOnb68rsBEySj3woAMoCdKRScS6wllE
9RxtqGcQ5d8OYgiRiqSeNZsWBKxf3YGxrV2dP5dRPyBHYiAl4LECM7Nvjbvu6uZGGEXvYwSTys9h
z4wpTdSfpfSOpyqXOjvuXrDkhTZ1nAq5wQuyCZlSBdIg2fyGFpqXQwoBMBsV5lrjrkT5JwxdB/Pc
82znJwa7UgsT6674x4cMvZ9b5lkdHmVZrS8yRJkIqpEYHmYGcUMLk1CNwbhIFvC/i5nd85cucOlA
Z9Da2MGRrkl9/zkSu0WsB8geDbFZno8WVdUEZXodFNlgIBS7n5MHFLnHr33cHREgHn6iitnsIPgN
/9bq57dHgVbKiY13NNDr4//pNG+S906Opv2mhRDfAgvLQliEE3w1qMOK5dDSC+worbf/CaxzKc7I
XZCkBmiFKXabrpR46E1P/63qrIVseTqpYyZvCLgz4oRQyHxOASASHtygpYa+HWO1aV9CL+Jfsqjv
iEXGtzsn/VMGOmk224Riah7TF0p0x78TCa6nWfNdWHph7TSDRQYpikpuYF4k/oSynqrfNwVWpEPM
2WXC6KGgE5oBWpZa5P9OF4XwNkzE55/+Y7BzCiKBMBRUTNxkZ+ClzlgGz8sfNMtOVzNkCTs/pAVB
FWiFLgZ/zchuEtc4duM3a0kZY5XA6EvYWHXn+eRcCMkE4+k03kLGOPF+I1VtC2zHIICpLTShHC3i
2fc4vykzdYpgfFgHXJzKEvBOWBQSvtVeIgWkVJPzRa/cHBhMs2sArnQ+41/P9sBgz/NcL20w9Eve
7Lb2YsKqwyFwKLi+QFmu+PLw2c7w1bOsV3lL8TiNnUnIz6NLTl0Vbol8mRROGIZ0o+FkWWmSSopd
qUZAjsBNgSZdtHhTQuXW8pzwYDtHNEdW800oWgI0Yvmo4ORSci8HXZR6BHD6zohqcKr17ZAXIJ0+
k6umnsEGXWI+2HkOF6s2BQO1LQm/UD4J1jWpryW3nvHiL2qTCiueab6wrRCCVYF6y+xEJODI911G
9SVkmNaAOguBQgatFlfzLWyRWhmVU5Cp3qZ0pwWPydm7+cNs/8ue1QpYZm5PAx96/474mTkX31au
M4XEHZ0CZg8hn7DssrMv7STJEwdN77po5kynwcq5HLXd3qezEPm2oGL76a2n2tOFkzQJ3zQuisDj
CuCcQ5iLs41TAQrrUCXl41mnj+0p7YmazfpERO/l7RfSgnkpmDznehi377UGScmGFUjK/BWRWMDn
Qr4paMobboy0IFGh6bXoO4dWRJ7OLOHQ/MnppqjgAhxSxxh0qRUK9vjzIUPBEX7DP5Qs6jpiJC0v
7/TIkGalVaUXf4SoWwfnpYCXg+gFDNC0HiXKZYdkvSuxQdS+hG1ihYDYz9yvkfBl6jD9ANfwmqbS
xCCcAPoNY5mqjXIYd7uuYJm92wFApxGjPMDkB1v9MAu/n2HR8iTT09/JQs01b5Zp4UK6d2MpjHXa
13ztKFw9ILi5H3pm1bio1Uz2wlMLB4Cfc8tW9YrmKwJqnbtQnV+vTzirvTY1pImXCDyE2PafexeA
Ifq7Zmnnx/MFeJla064fIOU5QjSyl1yMCqCWpDGpjFgHK9UV0dYWXKtxAdiZVm+VvHXP+XxDU7bE
SUHKPD2SNcgRqEJAxMN08f6Ozfcgq3p/Fs8hhHsff7SvNZzvKPF+a6whjC14g3qRnzIKAN1Y0A8G
SOr1eTvnoenuHbx4MdswkmsaCjAOP9us5jdow/9i+C7YujyV9yHFfvwUdrJdxdNI2gOMGnt2xKEG
Z/HyqfAspW9ilnTrqF2kZwrN1/SmULZ89qWF3ccqkre+FeEnBssdGtEWbAf5ZqmqfQuJYnLMM1jt
zXCP3OYlccykoE9tw6ZW5ibmojYqFkGUW7lmhry7LnxejnI5J567Aj61TrZsh8X+URy+g6uFis0E
M5n6dN1TFIRV/7ZkgsyQCBbpdyC7sE0awiF5xABjqH8yrBTQGXB0odnE5edB99DXINh8pj0hlkg8
G9Coo/5obNv4wG+8u+WU9oXwk6U0wd2tE6Fqms4nKXWzSXyUqHfQ6CJvxYc/wfXFz6BrkK2XX6j2
BmxqrVFZdq/hYDruABnf9sDlrKkw4LSOHAQB+qAxWt0WVughI2+EuF/C90ftNqfwOqHq1ilqG0pc
EjgyjpmWrF/IcWDMikNe4hoJAd6age44UpkC4am4trlnYf382R3feibTvzPcNLzLgPQlsEDaQ0vd
l5QLQ/4/r1HUbm6Mbf4E4bHAbRAMvvth3Yxm0h+swV1uCTf0XldQj+rzqag8dWsJMwxx8obOsnXJ
gCW9iZVy1P6L20GYrdFGNTwvkzlP+/G37lTCcOSL66ycEfl+A6zNhhhDu+3VZRa0XZbnk9jzhStJ
/2kA1aAi6EAqmxrsjdy0vk/gNJS+PeGst4P+xY1nssa4S9fJCGDx2HrH826q69ZEValHXXZulQFq
gQ035B3ja6zRYQ2RH+fbkvBcD2XJKSlMQhgnVwtZiL8vOSzaQNdE32q+jm0nG/9FDDAZIlPOCBQx
HuhEoO23ab9BRZpnhMsi8KT+pB6rKt+nl6QTr1LZmSPCBiAx3WyiETUDN4AoUfNNU8IqUh1sMvil
6vWyHYcCWtFNpC9kG7ugzdF+bj5836yxx+hxfC8Tm38y2p6d2Kr1XUCugtBb0HDS4ccU720BaYfs
Bj8qiK86r2hnOAZSFsI+fTAIxTOyz3N+LxjxHwZSElxTdJVDC5hZ/a0/iFgGBjqOrjD4zZujwnKD
3rWW33vfmfpchBsAUWVCFRW7oRhcGRjh7ky9ZIpCJvN2D8ybY6TXYg9sPfCcyQ85blmvGFY51/NZ
8PNmlG8uDbxC9nbY/MYL9Jy9Mncn/OjvT+nyMSdSaWrZoWfmGHifBJSt8jhRZIfpC4wQKfcHS7/o
NfFvjty5uCPkB+4W4uJDRjWhEWURYuLgAiIX0LdcEklORMC1nsxiwieNFU0HomVlWlxNte5BG4Q7
t7xck2iWejFfE+fd8M3lGlqPx+dsUf39x1OfYK2zVCuU+gvII4M/irSICEcp/hgMtwXVV4XTwxct
HRMTvqwDI5rT+nSog6Li/X1s5DGA14IRShem5FckKos1lJok8AN29nQIc52ol0X40jtmtcLscpzJ
Auj+b4+abdLJ5VVMaLiZmW5AQpGD1ndzVrNhmr2AEP1kV0Xl1W76Ur85MfzCCusIxXlkPL5m5W51
RAtyzN8NaLyT0qXXqnWjW5eZby0+W1rdZcdiOQSA706QDSR6/eEBvmDYh91Y2+r3tU94iJ/OSKAL
ndiWF19Euw79PQiSlK4haUIshupGCgO2pUW4MjdaopqTUYEP5dYcynDp+O4itxUmGrbpFhDLVf8u
IrhlJm3Ms0dI2eJARfmTcOueljSh7bVlmgfEAWjRGr2/IZSSD7Vo/J5tWXbW2c5umg+0bWxlKax/
DTyA1+Z8jZ6dQU14pjN0tv2wgvm4DdwJBYmNziYDMDq5EmioE5J/dO0/9EllaTFli5pEsw7AbgAK
D1Z7/lYhTeuiNZWebLE10aQ2+Ah0USf7eAwFZnzh0DAIJFYhOa2DhJ9tz8eXPr/IMrkLpLyIEGFW
qTaJlncfLJ+pCnS2pllEX6v0XCHiGKwFlEprfhv5gXptagXP1NTqoCkZVEHWqeCorIdt75f8m71Q
Dq9y4lYuNGYPpJ+pzPA2KYIo0w8/bpFG4wRm/Ly2j+dlBEfx3mz5fwUmbDO/bGVttTB61lB6F656
flBwzkTDKk3cvitTctgPr6yITIMJgnxu3Vj+N1lpmbnGQxCmVSqwAn/d+MmFdHUh2OqNCAvMyI07
+ROtrZBIMIgK6EcppB9K/qmnou4dERm9DJ+TpviJ8mrQ4wU5doXFkUPzPYpOn1BCyV6D4P+/ShS8
ErkrqTkIdOSStiF/W6a/MycktJl16jNwZpUdnPC9auKIdqiUl8K3h9eun4jQI5V0NCQ8LHOyt2+X
x1FDdKMWR9sZr7GZjeGpilVqX3EOULolSX1x5zizLyvHQwiCKO9ySKkAhWDd3/MaViDrGMyEIfz+
9KPK8KrqCaWtdUnoN+Sz4sFHjXHz6WRnaAqSKYepUQ/YLMpX6wYdrxtT/6SFvAZYo/lfm4IRG++2
Jl6etTw5QOglFQWXcp9N+xDkjPEWj6Kb1HOHfUXHeqSZTJfA2DrZ+2uGPPTFDd9Y9F0HjxS/NMXb
qiu4aLshoYhRhza0hpdTmmrw5ohMUMSFzH50yOvV3bOtPBvHGRLqGA0VxsOqTMCgVMgXykgFhUGh
UaJ/v7n4eSW43fGsa1ErVmKeZUt8/b+uaiagrvThRuNJvqW7sA2msJUuQTLLnMPgWgD1kKZGuq8K
Ud/jZebtKZdAjuCT87dEKi8VohyImOLQfrtOYTipQWozvR1rGnJ/3UTTK30mhKTOpO4A3oOVqod8
/2CP8Rwc7FqavjyTunypqh+lLboal8edxu72mLyijNtxh6J6SCVSXAwk2VJRONkNw5IAN9cN1u0P
O8ccBLdJYohSeLjqu2baokh5GbzSsuTcw9ge/ees/kyN3NYVjt3a8He1xfK0fDZWARrkKEh92TaB
1aBx2jijva9ZZjFZSSYiTyyMc5jxi2FZ+MWASAu4rUZ5Gi+c4CoK3xruzUoUL/kqb8mugN5yDmtL
L5qBsowbBmuMjncPmTxMylYd4DJD0R8viv3yzoW/XVjXWPe8Z7f0+FimxOqTF+ogpxwwBkg8K2nP
faP8ZSO5vWIVhH2QE6PNteFODWx+8ZV0aYiXRyfsb9/J56is9PAVXWk7zLSJGw3ljYqg2/w0u6VJ
4TRGLuOcSY2HiaNgN9QCEowOGK12+FDjrouepzsVVKpIxCYVuVAFXUSO6UH3IUcDBb3cQhHR2021
xpwgze0XLfKAHUjvtFOuvqlwY4rWcnt6YbYd2ULv7RBIrONtaYfZLQDR3VNtU5KnzRTOaLR3jLBO
h7uNMCrk7ITRL6CbXDzYGgBMF26r4sD/i7lVnm2ffZ0t2W6UOjmLidfzgAn3VSpi5d/bthsDl+g1
fRkIiIDmJMqOqoTL5OdOKwdrrWq8URCucAkEGBb9TSqwMFUBlt2th6JAo9hV3LcOG76Sd2toXx7p
zIFdlHv9mU3EpppP8cc3OEiOwDEphWkestYpnDpaz2E2YqJRe3YWbGnrXl6t0o3+/rAhCfy8+Ym9
vylFQATkhceF/fkJJzvtqpi3TE+jGGY+NEHmhT5u4CglHbSj84VA/8EAQVS/6nricfxd3oJhlkMr
S44L+4dqzVFrHgdNkEfqk+dKA2GBoI2vri5q6eXvStq6e11EAIbU/T3xMt8BYFfeBWJYVT7T8Xxl
p7LNLAa7KieXO1fWM8SjTf70kQ5TqJLDREivJomvBjIsMCGm+wsUqpqPS5qQkslpQxhay9zEcPPJ
J9eV5FSs/ivuh3eZHo8i9tXDaVNELMT37dk2SLY0OrIUL2RnE+rs+cJ+dTMsH6BnYXkNYAm71sLJ
WLRl9NvYYlin0tEC7NycjdTfUo60jI405af/8f5vk1dIoCQY6WA47hin0hhIs/M6f8/ZFHmPLyff
4DONtWZmsc1JzXQ+vA+66est0wKKkWi0MstYqPyHvHtXOulK1IpLDiUnu59Qsp4GQzZkgQeD3yhU
pJHVhhrkilYhwmCmlC9WeJUkzOE96BeUhVMyOUaPf+5JgZAvJRPG9gKyUy1m4q0v6IoDv3co59xR
BrkfFTFa24xl4lzqWyEb+3EeR4csoUFNOVK9wiKIsLw1ij4iiohhLe+vCun4LPALe6gYprwUPOGK
uIU2GMgFeNbgAQIqZAGwgUpJh6yOj4Z1SH0vcvFj6Eh5PJ0/gPn6MtTg78zkjHLlYn+lfh5IEuah
gOro7qiV0sk/cwJL+pKxH6i3Qi4XPV9E2u+roV+QDIFGAHYC343dtln25DmAmeMDQ7LRoH88zFME
EuGNu8YyyznkRyw2XtoFnaLs4gStcmIM1klkFxa0t/nfZH3DANBhWZEjGEM0dpPsv3vCTPA0CW6o
9BmZ54QnIugUzwzCccYJBTvv+T+Xtvpeigv8dEf0hBrnu/exyyNQDFpTDSVBvuIpZ9mdfJCRljMD
4ZoX6YbBLpshg3B3ShjZXvE8alNjPXjkXzTR1mTqScXQS/QwKpDdUeT0+Aq0se4e6lBrRRSfiFgi
T+d2sAW/ynnkjsHmGVsEJw6rz7EUAnptE5nLi/Crwesp/u8ay56xC8AYI6SgfQWEZzGi4dC+Vata
VmuadMIIk3vqrHz87n+xNw3AFsdpMyY8WzxwPGOAqMW/K8WXvk4fdKwZZLM3RFtSLGr3M0y6v+9e
4BuhsmGvLcJh0WxEIl++RURA10oK2kaI+a8o12KrZfyKHpsoduRIL6eCHHXUv0II1hXjoWzCP9Kt
OgDqrnhNXYiNWLc0maxr17PmKGLWVZoV/BoBBCXGGQJR4byQHLVsftJDPIorZOxcpUY/2Q7GgWe/
Y8lOL1wwKQgIVCwpzjhXI3J5oxWtr+5PszHnBmXoZNC305fC5qCV4Mw+k+qkqUKr+nt+hxCw7RQf
AuscGhtT3Kk0yqN75+t6OC8YLX6lL1CQr5A4eUzyjI6Oru8wUbw+uHV02r2n+EdxsuGBAGSlMGg4
lUqBjfxezh0ioTYddcfJsEf2E4d2reiL+Wa7WmWaNvUMIh/FmD76LZxhLBoTvTRpfQSkWrV7KW6v
uG2JdLnv96hdbwJdFSuw19dSrbO1OeWB1pGGovNDD3sCPOLgmbQN97O+NkJdjTdtzXkLHs79YPZE
LhjlyawP3V+t2cW5iJWauo8XRMGVpqeZQHqMJ6bbjYQ7j8OMCz0oUmxmn0QAK/fv0Re4vxNZV0CO
IgomSfwCYx/dyCK/lJCXB0B30xLRaMuMg3ZCcEhvnlRUwHrBIvxw3J4t+A2BqVNeeqveAY5sNwOr
1UitCD2ppsvFfxl1ddLebPpOBzcZ0tyAK5zstftKsnXXO9BzidLYus/SK2RLPizz/q3hjaNKsJ5f
xHUNvECCC0yFglGPOIHGWnZZ/G9s0JslqnQBY/Bn/iBLSUCtcCBLdb6VC0Xa30ye1uy30KX3/8O5
xQ6ZpNrUL8dXf+/rlGbIKvikiWniNhGEdf1bhouI9VQpsNwZB5+9s8l3JsF83jeYZmpjkuaw71Xq
WhahiKsoYg6EhHWs9LjbLwz36Tb/2wMOjkHDvzCiUGwwMdL2VlzKzeFul4e6QRH2vd+qG6yQ0ZVL
DOOLE6lA2LEroS9kEK6Bh4VMG/SRy4DAH70K2ltITrK1wpx1xYAOnJiAzHpXXKg6m0lphS8z/tcn
JtVUb5a33rE7nwHsCWQQ2PntUUTRLuvFoF31H3trAgvUbBhizBLsftsTJXG+bVSpdeHR/hDThCba
Zvd/kkagMJLpXcgdRResLJ5gyBzP5X7d5EFl5yGtkMD3Ih9H95dKqT+hs+nfqGyNxS/vWoh6mTZv
CeGiTg904Imn/wdELgilssBSMltWuL4sfc7VOg3aXI2PEvXgUPQG2G2WfoH7tiy72oOfobd1ptdQ
6IaeCJNqwRXUBD3aOfXwzOEfVcE0wRS5LNCKwAl6/8wQcvApQpiOZda2H1SD7f0k3m3vv6L/h3nR
6YKPTJeQkL4HAaQcNF0HZw455xNion2ARXH9WXKLOz2WYJ2TTSzQnOEXWzaPOkabSaCt3gmmBtPY
pTqtQsMl/xjsBx+xIep+GRukXlPzjcY0bkIpRImVfYb2OknSwS9s51f9L9fvuf1ud/jYcYauGUjm
R8IoGNmwpkIY52P9MXeYsxyq+EDHEtmN7F4Cn9f68YUI0N/OA8mvNReY/boVYqAIMSA3H8IEgbAq
QBp9EPgnlYbFTt1pb3miu3f6Y0FDQ1ESoh2B6lqPN2XahVweg+NFtiVn+Ox/rzAVHhbb0hRaTPDs
Nbrd6XaKZpH23ja5b/xPJUzP5T+o4E7NBphDkUNmMHDgKFU1pIYOpCX37ZaFUdlYbXFfIjIOnhlT
dUuDkcld1jnCeeSn67eqVncqaZ+V7faiSrrJrjxmtJ+ysAJMDOvaQPRqWPjzCkoeIlluWb0rUGOA
QkfBxeKWLi2WiauP6yHKkRz6B/jfJ0ySTybYC7SmzuoB06RroH1uJdc2kYuL/P7SZunVdJpwnfMW
t4mvIyABphxntxL0xR/cV2whVUK+rzZmvxhRTvuZbBmXD+2TEVtZB5i+QvqaYnilS+HCxnDFLNGz
FbFI/mZ4qeSdBb/plXVlZTKa/JQ6ASyC2AsCoKG2i5XdGSjYFy7lDD1JkqEHdtxxbPGVtzjyBlR5
XTr3ggFcPmsB4guYoyGEUk17GFQjpCgrT5ni1We0S2LvHcg04OH0Kvy2+8bdzq82C8JKF1JZ96Mg
H03JThE/KARrfzrewwg6elVqBt2qzwwJPWeEibtRxkiw02226Y6w7KC1io8i9CFmBXSrwyAC9oUt
U5Q0H1QjZ53xxoiCIvDQ9Fv535dpX9PC/mHXxiciPNrflWbnwTRdR7sXjbiLNYpnv4Ue/fyQWdXN
FWHjFoa0HJmeAucbukcMJ+JIRBpRt+k6xank6yKi3Wc5KM/2K6wNPvkRFVA1ihszMq9l6ghUTiZp
aY3GVh0IWHtDF5jaYCIauSPx97C8QNirhjaf6pEMA9a1eGbKmRaX7iV/TMPm+alVbfh0gU0nHdI9
701ykNyplsVQ4pQ9n4XtrebAkwGskeFU7Kn4uYQR+46eo0kJHTcXHkZHLDmTb1Wga4R6SUlE56v6
L0dsyXCXKWShCdk9ZurehhrAPVIaeX9Nv/PzEj7kzv6AAHXfq14eJVbHVfulehr7b+RLpwNbNmmm
+aHN74IF/n5gXkfBK20BOe4skTV5sG8doSW940BfKSqv+0rB19Pxt1NbNZF5sdUM0gsSRuc+3V4W
eWJ5QWE7iUeDlqyeFhmYL8TysHShppZA+tCBVq7z72gu68V7IaxXpm+1EqCpiRVDQnkn2VJE0hzB
wMrkC+25rcejQZkGiElmnijCFxgZytk9twjKAEQKE6kziew66gPrdMygTjnnGATV5plxSQLhDoZy
h8eFbVZIMXLuZ47HNNkab9gjPOgsZhkmsNMrv8NtkakoqfxD7HwltruoA2oD6oRfdQYF6F5kuhyB
RPJXiKGk2al3ntDUIMA3R7f2c+AUJav/oyFuiNvyJOy8/ausANb6vpcYLIO9sMV+AGil8ky4zXos
KUQPpl6rROBsvuTe/lRY8br2CpwhpsXty/e9qTxCM1yxGRfsQ5VfSsIGiboUh0Pu5FvHEBEav1mw
8mufYeRzy3qGgbqslB8IIKmZ2fkjR7eeOGa92JIfsQvYW3xkbJivy3s51LAVKpD6hWpScx9D8VYh
VqrbtJ6cCyFeREKUhVJI7qBRv+5fESL2+oE99ugBdEQqNg9LoxV6BMnIVSpLdwIA/gDqRsE3UMqW
8Z1BuN2Ix7Omg70eP40wHdCbVrWRLK9OwN3PuJyXAcyp+mTYS0RfMaiCWJc3nDVpHaFGRG0wh8qS
7HMeDx9vs9X+lFC7wB8NQzICNetgOBFHy602bAn7rP+Hb0J3gbdjPoYKg+1E7gNqkUXYGy04tnEd
UzVuNLWDYR5RGbFvYXLX1RLqvrtewkTiiVvDtLWbL12PHKDQVsXSXafOZeXzIW949aKXV5G4txaq
HPAEGP7AgSYZ6gYC3JHoSc5wSc72atgKy5nzb524ANWGAHAHwxBPZcAnYXH+yMR4j/eDFe8TzhNU
6VDi4RxAVxTthPunVPSy2trCq+Wk/yayyac1gV0u5PnkbOEdDgMFytuC2vNmLf4T2wJaapL/0YP/
DYuhUcNPYoGQiUJe1UjK929MivMQ+Vosl4ihRN5qYAy+O+JZcAOafIIJqvLlpnDg1KhOa2QLuLvr
sKEJJ1wBBu+rwryScbA2GtvUlGdsodyB+t585pW0/73w6pSRaJ9BCi6fwZc1kJUAMtZZr+a9DoNw
WfeZy2Z+H1oPgzm7Py20z9Z5TSB649P4wZ53z9mgAbt13Z9rPOEJ9lhkQ0HFkmJ15/RoiaSHonu5
FUiSQhTToroqcQai3bK8l/NgfrrfQ4YlVZHPQqcfr3GLlUC/WmtMgDgaLmEqJJs4ClFPu3RWDEPq
pHbyqBfFWSFR+ajAITVdWVCwASUq/4Gqxqu1Th4a29Y1i4vhjWiQ3C/eShoncV/+0qD1lYceJNFX
qD4tqRt+fCRCJClLpCk54IjbErSyOOI46KPecXo+i6uPkI4IErYJUpoMVFzEDzcWwAAfdyh7JowP
edK46j+JuXtQCW+7qC9X2XvL01zD5vwJ82tq/V0NVWdi6unZBCVGQf3LEUC1vP6QXE7o7d6ao5m0
uj5K5I/6WGrZmrndWqcviTFVy+nJtfg14VyGRVjOpAdiLyytIf3sBDaV85Yim32pm+RbgjSyztlx
+MCFyRKBSylmOypMI1KnKmFcsMMd7/f+X8cGOKZNx47QD9YW9wqkbI6189q7AjrLOtTneNZ20ZTb
gPe0a7HxZn7x0Cnx/bmL/KrYuZsSuI8tQYb4qcYvBXgCPQ4ug2UdO+pZ19VW4DncFanXsApdZF8D
kHWl/5QcDZaEPZj7uipjPRYaMNGMqHTNdQYh0hkFuCMLCYJkKr2hj5yxOMHyAkrPzhxrc6/qqoUI
UPc5hSVIfmnunWrVmSx4iJgWSATdVhENUR6kyXmQDaUFXKqLPh/LQRAIVRpUGLUO0+WCUioJ+/jj
SCDWAxdGKGKjKI149I7Wka6ku/Kf3z/Js1+n/LtjzKNaMJV1Fv32GPmcG/IXFDQvMp6wv92kyiDA
GFRBOPqRSwRsj2WmblpgRQ5f2p9VA3vjZuPPmNCIbt1NzFAePhJuNGpEWpfxZhJj4ZyL+NAirnlp
pcaa2bthrFpsQs52bXDybcZHPA2I9zkNUV2XoYZoPcc/YFBQXAFCdoHYfvUlu7Pz5DwPp43mqWPF
jQiXZ3L1xVl0YpyELC9Hiras+S6sA3dH6iCX2bgNzL0/eZj53MFo/SgJ+V2dWgnR7RrfuBRqmupq
NIemxgEOMPfk7oNGQToyRKvZ6u2ODk23yc9oPr6rbDK3UQhZ9JcGLR+aSgBP1yoG9fNjeIc4R8TF
IXVfuqnIZJzyTVG5rjyim1mkMoZ5i5bUQlsEE3UmYuox/UEe60mhO5qO1n7bZLr0Oz5yIhgjdK5S
EJJD7ENwPlP8ysqlI/fbRYre9GLN+aKZpUZQWbIx3iXfNFlwcgwwfX0Et80lRPahvKbFaKlZUDeA
56PIwPBjC27uoF1VHvNUKONiJixMs2OZzh2FadIBa4ygQh+sNT2MYEA/l7PP1X0vtkOlnYMdBHqC
d0WtYrcJ9WvQPQ8kQAtHXCdTyr/ARspBMkCsTkWVzPjLr810kM0+jRgebAhUeJo/B/hbmhpHQuUh
O2JdowhJDR4xY4A+2pWii9xuMo68ovshD3jeDqrEWXyHnSFhtIy8GTlpbz6lGofJja8vHBXnJB6o
g4+eS0cUHf3JEBJokpRNnI/qx+RDHc4ksOK6zUkTlLhYpA9a1eigO73/GYWpXKptmks3StiIZDmH
wN3lKZX/OabguWfEshYzJLyytbvESGlc8T+XARUDpgroOilAxVllgIx0EDhYs/Ki51b6qiF0YwDJ
o80k+/r9RyaQClTEek/gHMsgHxsctaAlb8BaRBUFgordvfdYb4jDo81w1nECBbKDp9dG3xZCkNS4
h8SBI48TTmCMtjQfzpByqg0YqoyGHfAtmKh0Kp9kSbrSwmdqaDcPxiS7tpIwBtSRCH8Fm02wsOvm
aXHjKG+p9K7Zry8lsmpHuU8htk8Ba/yzpSNZAFrmN2P0P1YDUZ3KWyCj7nX/OGIA4GND6pQ68Q0N
2v8MHyPK1vBQBN3z5BAwaY85uL2QdSNpWRAVGp5quzU4mJhC+d4S+14+Mi2+fc7C8r6Ty9zyD4yx
ql79O513xBIOl+VqvaNAFQRAPkcSv1X0EIVBo27IJs3QZMnNruVwV215NGoFOnR62VoWRxCnPk4V
OxWz7opCIeWjhWN/oEDsyxa2SuHmz3awbXCJe1gCgZB+DDKZsk4i2ljfBPSNS/aME30CLEfw25D1
jU00vFa5FN1Qt91uZAroePdLEMvEaj8X37ZJHGGbdNyqIC/1AGudmoC+b8TV2IuCpIV34Eq3bGOP
VZwnJESnHTUb8T1gXxoThYB+k/zXq/EaIV7EHalfZfUzmbv2npQcCXUG0lIjaEdOcv3JwaR5g3vM
Ew4hHs4mRPAZSY9CNBxyoM3Ks8Mc2Dqqk9AUNBEA67GgGW8aDdd9J8OgMdGIG2xl/Yvj6wPqfPcf
xlKzGP3zanqrXGQTEgPWTVDdvqGEsjhgvueqainotsJ1Rr+rqLSA8TIVBYViOYo63gKqyJXhe/P/
a9/zH1k+AtGMaHKaEEU8ZRMFPlS0KPAG4oZIhJx4kjDK79JMRpdAgSyQ6Q/PYS5YO95SoR81Ifyk
A0zHM1B34p4Jd5bwrmQrDCBIWqorkxp9M7aUhdoThZg7MFQo6Ic63taVjTlbqmBHKW0Dyl/znigW
tA4YSYgqpsqv+Xc16lg69WugWMJwB7l0aeLKY9RRox5ot6S2R16uWl7IWXn3JQEMAinbedYlLgqO
8zYNYh5TcSOo0a4hCxXX4hhHO/AZdIZ3AfpvAdjVPdgWoUm4f6Kvs7t9q8L0Firm5ITUZkQRaQ2+
MWmEapuqXWhQxWA5OIpZApTFCwTNUkpTNpPsjfLCn8xC60Z349FF9lxCm0qgZWeM4pXTrfIOttG7
DKiVyjoIdIJ3bD+vrMfnxDW49EPHIcbRJDf7ipyPgjazhz+1OhYi8+YTDm6NUSKwNJsE8dPrnDBl
PaVLc7j1b7n7orRYafMO3WN8bMUIM/WrI46AIm15mtFtuNtFfFhpFhonQKIhbk5aKpLR8aGAuY+J
OOqwl9xGhSxSQ17QiR5F63vBwpGakpf0e40EPj2E2VQeWUnqSk4kpMg2n4nHgddqJ4RonG76lkxA
FW6zahO1SfgUo5tbhd2ipT3ShWM7vbrLUCpjo3vF2gLfbi77D6e0mhQMWgq+lVX9CPIdilC0qoJr
ZSzbEFfYkQpfV2dKUIUiMJ+nlnUX2A59cluoYcZxh15cbf+9KWrKwJaTyM4f4xMpr9T1nUu7M36I
gVYiZgexpjpWdi5TWnG/x0hcMwGWqDJBKlk3cDmAojKbBdbhjaCNzMDGJlpiKIPcejZ/2ylpQ+cx
KZ8EV7G87MIq25PnxRYeWxboKkkt3Q8oWhQLHyLXu083CY/NyjYlsT+dM6ymgpYGtcmL+YJixE+d
4JEexdTjCU/oeDXev31rSrVM1RIYSnOkVQ6/W9eObyhULi+InVqNkTVRKl3r0VTKMgyehxucMj7J
DuQplt50qMcob5y+p2nznH9cvq8WA72ZmUS2WrUPNyx2Eg/m/jhaHicnyb0aD4AYCF0RK/9/HcqY
YnPdL5f7pxTal/ESdOPrCaZqDokTvIkehzKxpJ99RcDATgYbq8welCaHn165i9kOd9RKdGfLc2Hs
iGFFrUe7Umyc1+YLUR1NGTKGLquu2K9zRlboVBmU2tZL6sSU83nd++QM0+gHfdsFeVminW3SDmeJ
SZ1FThTf0uf2pmtEFnZdf8qPt7svfwGpgMmJZhCEZW1A+9Iwa0KytGvXdoqCamoGjgGWCUEuCGwc
ml04uD49GbVsg4rsRjKErWoqibmk+LqF9WkBay/R70duA6pUxtTa7wBd0CRxnvHEHfO8RP6nMcs3
voHOioblw3ug+KYAmdmF+EVbeG7R5aTwXPe2H7eMfw1Tux4YQmltn2IpVNnSZzCGaLjt2pywrJQT
hTVBt/CBDgeKMVjpxLqcCDqq4ipxuCaubKjb/XMyarfyrIG7muGft4B9x4pJQP7r8T+v+9ajtYz1
ZpghpFd3u+u8wfWsOwUo0GjKOmTKP3bzaMnTHVrUflGRNOjQGnDaH3UlK394XkEJbvod1sRYIzvp
mGExwBkdmZd44YNDiazerGLQ4Pgat+lgshioJcN2lxkl6wLPR9q0LTSIm5h/cNp7Ogs1jmFXxu+G
rQ5ZLwD+WJzRztltaM0a3gtHE8EtEWzLPYzwgd/qM4t4ct2o/AG5bD+kfClgi+TukjaMGeacj0TS
ztrDtKjIBXjkaWjPFL0Mwc+IL1q0GVJ2OZDlRjVlVHAtPivpTMjC9Psxt7bZ6ZwQ6N0gyDwctOga
vzrx2vmGDjAMOFUDbgg10U6nfO+KlcwJcBXT9a0ffYkwIS4iqYmjScd5WHlpwlj3MEPNnwyP+20w
LZWmGyAObB+hrJolyR5i1iugdvt0n/NZuPVbnfo1a+j53pwAM2rjgbxAf+SfQ46los8BFeYbYsOk
hXpI0x+8l6mIWVHiYyQgSjjZetpHCNVJxbsQOkUQNcpx3kgQAGM2EzMY3DdlT9uLfrMQzvcF8HY+
JRx624YC9n0/9L5N/EZtKErEhyxvmHBJbR8fhem7ks92fbinlia4TiL62FTkox+G8icBtQQXJxiA
HeDTETJc7+skFHE2KJpXLXagWlksdltYfyL6geN7lvzJl0VW+KgGdgRG6DMH4BkK/TbNWfd3KVwW
dEQxOzgKAMYFj61drjJtcEEseZWyrByYlIuAmv0i7caB3koIP0GaThWPG4yYw8MJgpbjwlkOjJ6m
oRPNs6OaY7E8zPVbPnL3bIeUPZoFUMDj/ejRAWgU1lcMzW7c40JrJDmvVB0XvR9goP2fJSIdi+vu
NaS5FV/v07YpF7huO1Mgf0gyAsBmxCJ7/fPfo+8kmcl5oiEdOZFfI+tSwVmkBU4qFSzYzka3zJLs
sLKJrDD0Mz9A+qZrjrDZ2l4tT+rUuAXcy0VN6pRrov0lViSnUgVYsVaECZYl1PnU2cZlEpgnP5yB
EFGX9CL9POwNfdvzPDw9LZ43DQJ2PLb9okd5YI0vBei4CuTkhK7+wivO4vlUeECfjKk6/LyF7vSp
+2fouM3mYxUpmrfJL4eWfjr8KQ6QxAqEyxCtz4inMx7KoIejl/r4iNVxqT42RS/PEKBBL+s55Bll
2+q6oEVVp4X67ioFdBeTcCyT+HHUixqpD6nQc0OxnaoC2q/rhT0RjbvRCEwfhX68KqQsqi5phJ/g
nebNmDT6xrZJohqvnHC65O/y4bM0YlDJE96yLLwGh3KNhDy28G15b6DDCqPAtYTOnmEjTrxlX/82
+VA7nabbnEAF3aQpOuTlFiib3EDcU56Jihw1MNbBnohFUXItGooLJP1pk3GtcE/D4+twQVQ3qn56
YvgCIpUHYl4XhDIH1dCLdm9IQVBq2U+eEMBBD6vTY5ykHPz2oDzqrpeU4r0+TPGhxXeajMH1UfDO
VmMRipaIut6sXA9okyCoQcih4LdlTeoQkeuwafRreLAba98wjMeXYr1u+gUX0rbvXEyIOWgNeof8
6lzt8I4Zkl7xxjkyDPM9JWEfIYK9+mGBsgzZHAdoLdL/r9evd9ADMSbtnBGW0AdKNVvmn1RZnQtp
WF2l6PGAhbwKIOXL5wCZV69N0xdcvKQaUhlSDE29gIsySisya6MxEudZrNhYCs6zVdxVlFxithfg
/YSBYDlO3l2LDX24rqZPSKmzeiRwTAf+VxFNCsmrWk+/Ll0RJzJP+7xeOqgtMA+1kzqje/SFQ0oz
KVX1imU93LJK5H+8FVzZIFCb0XupV1U3Y0uT6P9hMiEdANwLEo11bPL/FjHql9ITiOV0AMpukmrD
XTDLkR9KzofpOWHy2ZJ6lLBjIMWA0t64VErPWxgaPTfYpC4szzcOdwIJl2Bmxqgd3cOkCVJijT1h
TbnSv4PPVe07Qa9I0iavwFw2JS8IHSAFLwHnar+tBzFk97SKy0davbScO0dDctblzwq1CNl4YAc2
y71c9LhZ7vUj9OmoiF4avijyqMBOLYyRm2ris9M28feztlBxYm87ZOYCZPdmw/kMRyWERD1RM+cJ
jZxuMATxspWLBp9wn1cyvR55f1NJwY8sH/iCoxi3Aix8VxDsXpJXZd1P3AgNcON9E3Aw2Zn6NrWE
sRMPeOcZePa0+saHq4KgoC+cmZ8dyQxQDe3KTrfHGksjBd9STcpST3NujTbwsIAk0gIAtiVWZXzr
kNQ05YK/UKP+q76djQFFccNQELum2y06EnhdiTz4Jk6c6qjSSiRaG3p4p3htkH+IbI765Pw0fChN
rvo/zXoNSjMefJP+XzAQeqA+CH/v0bNcB3+kGEiW37Kx7xyupXD/OPW+OKdzhZc3i+TlvWUUwF6p
SCK5tlDm1DbwlfPbCih9ktzAGLuzWesWarPVc43nphS8Qv5K4tt+VR87FemW1/uWHhldlyWdjQOS
nQqIVAz/J8mkJyHltE3T2zDJ1D+FBRy23MpDlf3rZoh9fxQvl0M+XlorYI874bZ8O1KFZY+BEjcn
MT7vsCOvP+rlvI4G1/oVOG+nvc/anzp1CBg12FLGCcZ7O7TUVMBeLbo2MfvUzvZ0WgaaqFQWTXuf
RsZfkyzxFUvfuPQfGSqCiYSMVvvcMNFPnJpcLRV8m8xd/XD9OsyFLdyk9kO7P6wVyjeH4rdL40DJ
5/i+oVLNd/T2acOe0AHx6Z4wVfF56QfHzg67JergbDaCO46SwFkw4y+/1kzs826jVXk18pdKTtpO
+BGAqpkxbJIMG09SX4TMEbOrdL5wlGs2wIkc8rrSSW6pCCkqRyc44rAmtJrcjOmkvlKLTDyM512+
pSstsAWOwxX7+P6bSX/l84kZ6JndN81gkdKSnclfdzHNRYjR7AbK4jRkJ56OhC0EB/xe8jUc253W
T3VMW/6sZSxvl/kZkyku3nnARsa5u3JRq6Qk0gEzcjwqfFEz0hFP/vg6rQMcY6SrVeCGgMAzfhwR
DoPp233g8fZNCEL2TQlFs1/EEUdtRC60vIGM3hQCdgTanAWAU3FyPYBx2TrPbKFxZVeYSKba3SAB
isLtuX4eckBth9uS3nk/l9uL0mzgncVCdVVHCPZeOlmrdKAPoD+V/hBvmTQkxzlrSOJvgUbn41EM
q3l+GQlxeXIirKHk9noEqL71O2C07u/JBBlAd4jVoXvoaeuH7Mo1ILn6sxo/lGthdlurteBCDlOS
twAVV223RFgVSFqfhsmmEUBClKGI47hR3rTl4PH8VGT3RouQ58kuj54nHrAWIzIGbwSAEvzNwkpB
jVCIwu0Nvv+IOQCeT+f6qVYnNXXZg12jMTXl2z6Q6K81M0xdNzWjiV1R9CVAgOyZSlc9C+Bj1Duh
7QNOernd7uvG3S5cbH9B9j1fPcZYbEuVNXhLtWqW/htlNZQbV6upAj0xfKt95ieBh9pm4tPhJvDw
QHgmPgD+iSI5rbwtvlt7haU9eYeGq5PbkP2cvRxmlFDpRiQaJd2L33pvNxVNNfbxstDaisxlFX1K
HgAkwGuWBBQLZikA9kiEQIoOjEqpG7mWo7mx4UOHyUUm8Gd3Y+bnkUQYCKhO5ut4ZvsKlDyKMKT/
Zqq+DNQhMoRVeKCgEDanIZVWL7AaVcsM6fvzPnebw04FzaCdSXW8Uw7MwF79L7temKhjqxU7qhY7
qeK8m31lkmyf7Is2c595qNgc2zrFa4ukuxQCioukRjTjvcp+kri0mO94QdzUNJtnQnxvUW2EYKSh
Jo/WIjadPTIphTZIRl3YZV7qGpBrsr1eeaZRTQPSZUyGzTziNJFj8kksKmbYG3a+JelgwfOqwAgH
bNFXj6PacwJ3Te83hexDUvtlOxLf0zYdYRq1duTdeFuVJZ5npfCa3ufssRHQYzzGWpd2BlKSp+5X
UdUpbgwWk68bm5jeRicdlkaQZpa5ZceIpE2u07WwhHljgGJhedB6UPzWZkzJHmVFB81WQwhjLIxD
tr3QmHIJTE6V0gJI9ptnDL74eih0rXNjTTnWiD8YLaeCV9xbGqJHpuwLncnzXOPYk7mI4zR8UZkm
+VwuDy2nOY3CVMvrjVIH68ZLPCzgEwkvVhfaANwTu/f7QYqlq8okR/1NGINFJWkYcyf3sKfCT3ps
YnSCDDFREKOYcwMtaqazb6+6RTyxOIhtOwXQgn7fSSleGASmSoymIIx58VTHgbGqpIiyDSjCYErT
jhQUAY3ebjIjDahS9SMfA481frtCXUMQZ8aT1pDS8fbOrXHT2AjzVPvq6HX+AbKyuPptY9ll15yg
397dHVcbYltoYl+u6JxWLIJlD1fQRatD4u0zLRUd+9YTNHtdwB8w3gWWXSDi21Zi5xCGGLBhQtbw
GzWS3YEHU9B335qNTqDRaxyinK+YYtcvMZgPkPIafG16v1iNSiK30879uDe+VX/w0YwVaVRHX/y6
G0hTCsElC6kI1xM44LpCF8T0dIJllzw3Jg8V+ft0Es2ZHrPO8YnwbHPOZuYjKfLF9+2NAKIYeCxA
tLcbKIGC84w2rI5potC8TF48Dy3pN9T4h7NKgWjfp37Z3LxPTmdC8vRteOM/GIR0G6vJd3IwgtgN
Hy8B2DNkzToRZACYEHNbqeBawC9eK54V2sBArO3L0WGZjoxyG4P+rYs50SRZUK5fiky1DUtveSDN
zqMcacSEY/Old9Wio8yC4XZQAVQWohHgwMjmPv4lQqzJM14JAoTrYQz5IKx0SZo0h3fG58nN3nvq
gRXoMoHMvI+w295QzRm5X4uwc1cd39Oi1xKj+8fpiBWdbwGee2QXbobsfSa/whhuA1lmWwykIh4+
PNZ/eVTRU0s1xf57Ib4MB9+CgrYufGBYkE8agHRizuqcg8/nt84N6r/XI5L/X2PkrpYjFxuYFF4f
nAJogOreJbdjjEQk53oqLZelKcI6FwHaPLENtKRjOJe4JDf0zg0GmNOVmPgSRO7n5uvXxKPd0gqI
RY/F01vHvJfr2Ds5LBAnb+CmMId6d+9f9wv/RPWWxG9yuv4r3SA5LAj0aZeT4m+x6jdka3eqeqCh
XqUSLLeEImSHrJwZHS1Q9sdwIch2b62DrgwUqd2czgRxEYjveD7g9iTjUjfTsbYOYnUcwjDmOKsI
mIic92gcUTRZoZJBs9Emb7yIHOYeNAasfdyK2XEmglyJVhULEBDlk1E+qjJ+bX6LEy1QAp2TbdOz
TbZV7AfSTv96h7WQawi5F88YWlZOiKtsn+fLn3aAckYkv5f4krpfY9jpuZA8QEH8GLuFDia/EjRS
2P8qvKwsBkM5SlWv33MquuitWquou3JazIOU6upi0XhkuVdO1zkuFbREyAOns2x13xHVbpRurzxr
/b/yM3usnipc5Z5AHFK39BkjkJk4gR/1lwj46wX+fg9A0av+dAO8ugVHH+TXrHqFQRNbv8tcJZ0A
K/jZkLdG88U0tYDsEG6+ZtBoa4ep6iAwZs0bLFSY9WnNB1vw59p6u2XVIdEnWy0VWs/QNzhpFTZr
VX2H99kYlxsOX06nr4HlJryNIgR6q/MUU8HDrfllO1y7g0LCUkexsDBveFE263wdyEUKtwjY6M5P
TqF7XhcWUl/17YVIeqg62I8+QfAO0YmsL/E90rGGZYJWBMKg9owlVR30TP0OBMdG8rActgJXElE4
YYihjK2kleu82hO6uiQ6elYZ7rXeT9sInubAfHZ7rQA4Gc9lvBxwyKfYxoz5jfALI7bHBKjxJcds
weBPGauFJ7x9DGz9SZ2e18XqlZwl/ZKaYA1hPF5kjRI0b8HNJ+CqoYwnh4xVfsUpsqbWXMyW+Jyh
m0NBisyuh+v5TTI/UjBn0T7RWUwCez+yg0iGgK7lHWUdZHrOhkGRZLTEFhWRBGUuNrqI7MXJHexI
kkw01qxlaT4INxqsU+cpKC8vWRh2HDNLYv62Ghsx2Lx+7B8Gjx2SI0SGf8l7bH0ophzL1BiJufjs
UaxQCEosGF94urJg7dWSIGdpNpk4XHUvCImJ4r5QVrnFRuYyXfjJJnqGPEsl50kpQsT2E8wBqBT6
F14uCZqg4ipowRGG/54vFAKjo1l7STNFgNw7YFbYKiETk0bY7AdB974Uv2t14D56iGHmUSXR1VMW
RHHevPImqpx+3JjW5e9LYzQH7yxYVCM6aqSyNLfwbQz7McdcPjPti1q/GLV45npZZNiSuG9IYLNK
/VhYGC78L3Efnacb+wnYrM0OlFgaUTzZ/IFQ/P5RwZqkgBjgwpOmTPeLAvDZqoXIRWj904p+B5yh
p+TlyYvtqG1mu/yaQNhVCpLCdBGQEMSG9Zc0irrGqx9ye7n/S0U9UBdU03YmTIJTr2vxFyLwtBtk
wAWyLpDl07GqXOOwjIfoZ7rceLDXAOULb2ilhJIexFxqrpcMQaf30mB8m9ngJMVJKVKFMjGukNp0
mpJzpwH0pCpK6u3DNSGzXScychhHDRfEFtgpU00dOksHCOFwxm4M+hp4HyLjCsgalLBx7Pb1o6Xl
1XMGNrPYLF7irF0HlNpc+s5WZiFTUSnHkYRMKmZKDY848US/CIPlThRHLOY7J9Qpfu3UDyZcgD3S
oSvYX+dK6w7/CutopID/4Vdvl0tJ94+JdeOEe0AnhniXiGBgBYMd1gsdDtvL03H+Z7wYlbD0bMV9
efcXoWoPlSwIoGk8niHTwtVz6+/djw5CTG9ON2ZRGpKchARMavJ6Xx8IEKl+5n249qn+R6Q+uroa
e0zA0aw4fW4bJgV+EBFTV3pyf5rXD4BC8RB+va0PYs4Nb3Qx4ktCpPWnULc6gVhYPxjY+SuZVKGk
M8blRAf+iRcXDik5HUd0GwMguM26t7/KAXOvXnNe9SCX/iKNdTxf1QMNKlSG+rG/yDFGJaMF2yN/
jVmZx4EFBM0opnvEKD87FoWZ3C9Jni+o0SJkoPw4goIa+H6t6Ht4ULVSDr/7In9wwzkABpvBay6V
0KLSVSkN+a5oD0VPzxchU7YHP6ciJX6PDXBrbAHqYRqImhhomhGGgUGYDQSSS61A2DiKwBVlf1dT
m9uDlBa0Cn20YNcS6+BlNw+Tk9iMvEdwdzLwwFWot/3lyasXErrBQnh3e7QxBWPmJE7KWzPcH3l4
hlCoEmK1U8cEO6p3fXB6pqr/AYvqOpwisOQjhL4zENLZXt+n6Imknw0QIX2CXP83jLb55c0TAJJc
iqdtM8rxMXHL9WN4mLwHu9VnCT6qoEGiilkv9g9YgxA+mi7D6Qw9aWLFjr9u0PopJhEFiSH6kvaF
PpC+kaENVFAYm+kwSFDrDMEB8x3Eu9IQs0HWpSH4tjWT6KRREXcY/tPTlrDuIoq1TADx12jxh8hS
FNsmdwxJ6OQbHb/Ho5dRQ79wKz85s5MpZ6Irfk5ywBlA2HKtYbdRCBNnroSdC5EED1MSHjIfwzd6
nfsPWXjXIk8I3jNqfzB+8Jkcl92qw4sRDH0uXzP1KILGmW2Ut7zT4uIq45uq6j5UAwgHcKSVU10h
+DLADX7g+jAFGvUjDaHrcdJojFSrIEsIRmPdzWzusxexwCymJUgAx3Ory/zkc0C5PSeOtrZQKkv6
tf+a2W9Q6DjwkCY5IkY9bb0Lvd9T+MB+nlQYuvdxdSHLo3muqNbYI8wDjQjReA1gZXOk9h6WWcuo
1lDV0KWSw3t9MI3T7ssN3yYe4yOc8K+yEalV/dsA6SG2FGU8zUWVSUZ851I6s4h3odMDBeXAPgN7
rkkC+bs/L+yr6laGP0PnN2ZMwcMbvOgwvrBUjH3inp4CZVGKJQ6ljgIS/eUELhCvaqHXesIzXteU
sbgKAJ2W83mV31QRCBSMoYud85D45LiJczzs98dla4bi/QKHBLPwEw1y2pFr1+TcmEhETQcnSQvq
UQdFPPJQSv0ky5OFIPbd+jqOnJc25fPi7xneGbYmtwDSZj0k+tQAnFhyzIruT17NuSMc2j5W+ZZG
H6PtRFGGXTDmS/gD93E1B2oIt1Q+1TS4iSgQSm23BfQWu9bvXv99i9HdYk6BdPO88CXT7uPp8fgz
ziLybzlLloBi4+mNxzaNCgrzglX3j9cb/8WykK/NMxMEvO8YbQDc1f8YPFQSVZt0OC4HI5doTfE6
ZkxxXqwehHaDlkS2oGuca6sqA480zIe35wdjiPyQGJk0X/us5QyoiBo9JE2F6k6ukH4oiMDoFFly
e+UQLVvxLbfixpC971OBB0jkX3+vZXtmT40OXBuYPj+WIAiN5EM4wk/+bhfgzi2MB6788ac+GC2E
iQeLRCjMLPyIZYlENeA6TdXacBOkEFpSwvG70MQSJQc2y3fYa9ATgprb8xCoxd0Jo/2PsCs5Claj
7/DXDDh1kPAGdB9HqgIg23cWoVygRsPfaNs5nF0/kkqV2AJCDLzWyTNgE5RxAHA0/cvVqj/Py4jL
JCkXYfw2TSSxQlkPU+qdGviZy3ZUikVX5zyAIQj3ydR2ZBkVNJ6cBTgCVyaTi1SpEUXyhBo/L1xU
QrHSKYZVbE26GYU03rLhjHWuUnFnQHYimUAuGXhA0FRkZIZsIiAYHQTDTxJTR0WS6LharcEC+zt8
fAwgrKVjDT8Wn3qhZ2BZLunMC+cjrSMC1CS01ENSn4MmMnbpdOOdBjQeb/riFFFq36L6ljRDlxvH
DI/ysXm5EtQw/h2c9F//sqt21lf47S0eycP6eZ+9jchIQV2uTPBm6HTtTE1+q7b01yv58KBIsEvt
oruXOmBcoADEC4R454r6w/uHuPpUHUfEhuyUP4mjMj4LGhCB2nEGozLEVa+AC0WJugvuFZI7CNX9
+Jkj/IG5HhpeugKll1T2EtToDs45w4EtGFDm0DLrTYUiCZNfiA/h5WVLNRNngERDnSAUVLk1YQ5I
nYIDjtcFznRbEctQN8hYzl7alOR0AXxWIChYYH0gK4P/0lK7jyKOIcNYfFjIEGzN5BxOfRtwHaLz
xsKzkhfz8eNUiSqh3QekRYJ0b6UxtQiDhq93RzcsJoaiG6EKQDGXDeMfxLp8Kbvd9McVskZlYWgQ
N7JJlY2NZ7gW/h7rY3F/LHTUbPCDMACPut3tovGsgbPcomcbmBx1vLIBXm+1EWeKxx1VZ4Br6gzT
o433o4wQ8A6uu/ft4isjXgMA9FruPJBKS1ievm/wSkvLm4VMUaezoKcu/km92BZ3XA5dB9w1sslP
HV9ydNapIWstJfibgJOp8LLBXFLl1pSwDXgwoLA1OC45NQjakzucJBi3mYJT+ctvAfE0ILh4Pjb+
6LC4AmFSPik/IqYUtVrcoxmHFrL2lUTlm2hnDozepvUw7r9uOOEatLkdP7/O6cachpvMD4zI4OFn
jYjpwBGMlTQY4Gb7BUCHzh3Li9qnJigm4QCcqhvqd2Qg718Qe24kXRZMHmrBJkyHRz1L6N/wEd1v
WCXyzDnhfjVHbQYib3q070JJxP40xWOV30qMAbZAeQpDx42n17iwIfcUbCtmCYSRlnYGVBycZIte
nQaJpbpjQD9nqxupq7A2P/iH1uKfe96cBIVQxUz8lpXfB/PcMB3JmFPXT6G8wiqqDIgzoymFKfil
HhCJoDTCitRcUcjVN8uTZTeX28gD67UnWR4XH3CR9tzneQ30qHW7itdjed9TBNsnjttuurV1NNLu
oKViPSoZaoXKDJJSvzHENA7LgIEdroXlzixXSpWGdRXn1mpQBGlsyGBgnDxWk+2bU1YsI69CltbH
oPM3NXlSMOJpqU4Z3C4Mpxw4bXlT0Nu3BQSnhJWoQSdgUMtJHbLYXB6M/BZfVbVEtPBcwuy0AfPd
xijDlr0hkLPnaBBJ5PkeXjfXJvsIvTQVviW42CVzTePwXCyYDru3nTodUe0/ADbrkI+MOA4sC9Vh
3J5qKWFsdkXRRMWuRmR45IwH0B0K8oE9S5n0va6iFShZ4VPyxvDiv8YxxZqPtFfIAtNxBH8Y+2zg
43AHXkgnB4+JX6O57yW7/uC0Gn/YTNZibHr5x30LrIQlU1qRDuAMVWv5naNOU1OfxbSd/a5IH2mL
2XsscEMsIAMUrBaI30R7Tt1uJBmgcxPSQzJRu4Su+BTkOey3xau+1IlCI+W97pnglqdvsled7VQs
yCZ2YZz5FSPuB+tZsXsZ77gZNM9tFLS2pcs9d76/0h2JwxvYXmliCwFVgsKU+R/ggjVWVAbDqdd7
89a+SHzkXsbUeUwf61wcTGUNKGJER/n4wKJHhrsG+PHGZdW535ai/lklfo7SX/9mXQZHi9WopNIr
fnqtDIMbgUILdxl0YvqpsvoCcGyx0DlYcpLch9tDcoTrLluAYKnEb57ES70KlcfrBud47R/zJZTf
Yu7NONVGdPVBvqFuMB8s4Muuh+zNaCigjFjrT8oJ/rG1LTvGuYXrnVmEr+GM06dWZ7tfdoVIJa41
S9+w4hKpMI6mrgfYSqvrZN2zKWjuguP2cYPzpFeclLsYRGW0tRvJadfpydqwOLgdaVwLYyV0LoGZ
AIvvXWuAHh/Vpyq7LnHqS1EWb5u0f4Aec7GklhwE8gF7cV+y1/4VB7ya8nfueQMWNQ8XTypkhhgh
FyIY40GHt25dQsKAGXPQK75oSUSJQpb2O9nTUYPU2mOiFHRkPwrZexc33u32Ufqay0TK7NPwC3GJ
6BingLyQO/3ZC4i/Be7mjPQnbdkqot1yRyGzUnFO5boNpQaZxwdt9NJEoVgIorMu80+9KfWxOO02
cXke1p8MzJnN7RDbkruAnJ9KUIfpJWTSCZyAVgFC8PI1QfnVJQR5RyVdQYA6nCOeKEyaTsd8wLCU
xflsUWsjwls9a+6kxVbWJ02lowKf6kgutWkIZDwx8a2MP/ISSV0vaXMrMfcBpv+Q7lsbMAN3Lsfq
TRjBgxGcOMv1pX0F3KsJJQR3nX1xhtCf6QfI1DLNGSFzO4k6tNHSvehbrutHpzKbirRh2TwrgoP9
vnIHKpFCCbvnyog6tcwpxIt6sQ1tTapob+QcpzSeCVz9NptKWnVd+Adv1HRfiSy5gBxt1xR8KI+6
LP5rPPQukvVIME6aUYn1Hj0pX1jPltmqgqNcmvHR8joGQEYcU1oe4NszoqUp28qYc/0ydfvoy7qj
87vmXTKu5dlQhr+k57tp6np4EOFPcJgzXTy8NPaVLcPsShMvYtzVBBEM9zFrlKWbN7DA/xV63zBK
lUrFGDNRiqKP4NSc0/rDihQqKDsVxvh0twyU8tO/gmxIl1jzGcG6nwWBbxX0q2flntgvLDYznB4E
LN3Qv8Ya2NHKgcx3kRHIuCIyeiPQash4yi1sscg2cQDclIXD7LVEtZg31pG+aItT/5CPb4oSbayJ
tgy7mgQbhL+S59cuATtq9yLDI7vKf67wa7Ogsl6801ofZBHdbcx9fRSX73v+32zOtsQtUeiDFqGz
W+U3XclVKsxIV785TgYS+j/BjJjT71pL14g9QfzAGjUFPnWSdkoK72giOMTtZszPQOExQOMscXoA
i+gaYphcw7P83lQpOV0Dn2/S6wS6bO8tGXBwkcOLoccFzBZtxmvF/LlIZbTBJoByamzrRSEHk9eV
Qc3qJsz2ejbYzQOcuG6UpGnNeg/rlSTOe48AeagZenH7RcAXpkGQCfvtrA4vThCpG6iuQN4z/8PD
Bf7X8L2EUvj/uXJnOXHk+VvRyABp9DRjiP3ZiiWUA8VV1I9yeau7cMgxcT+HdWGoe08jZL+PnxtQ
RHt+PNmPZ/tzj1Xr1R4QTebHztXA7PyVIGnP0K7Opyd+AmDbsp1Fafhc7aGCPT+xgP5m9ocpqWdm
RV7DUajliS7+CJhqbrumGZb+xz7kD4JSInFPdiaHdG2tY9e+4/lDGVPyolD0pW+m7acUDUJ7K3sS
da4mgYUytoAXB/BTbPJkoHMPROpzXMMurYCY+IOEFcZibYWWU6OdiduN3Ax19He5cEfbutMMMB2c
Jgd9h5j5QbEE1n3H6qXhSr56LRFApECiklfeFa85RHWbbdpiQUd+bGdHusodAN0pnPZ8TaJRMSWz
YZjhj3pySwE62EjizefGIWYravBPxiYoaB3ndmHPJRVVfhGFoA45Fruyn7u0jUQlkaqSKxaQEK01
wyROaHSD7jxGyTVY8dUcrZyu9N6dOrPJUBcYBw4bZVtHK7riN+FJcXSLw0tM+Fu5Qyu6Y5ASeID/
X0qIM1pjjuV+BawNcIjwvGMHdn+PUbPm6PO8VMVAXQMyyASrea+E1oexNKPFzZTt6YKdHwEW2O8E
/BRLDcNZJsjwNcy5lzZtu+goDAn69V1WCVBJg/uNxa3foof/VsGKtDNp/QSQ1fpBQF+JyqJv7MGs
TQWPBs4mM5LU9XLQCioQrtGccczLwMeWPJTiHIwpfI1JrHG1uUC5xCr7Rb7ELeFkTfsjlbquzI90
GpMrzi4iI3628zrmI/gTNQyBRzQbpmaywSLUQgyjIU6XUaqVyW8ugCMiIIhaWcbMWRTpIJgzoe/i
4VB6gWSbI+HAUHGbNSxJzBmBkBZb4rU6PVYCu9FKMmwbfDK3WI9HfogHq7m9Lb4AW89kLJ8A1p0Q
tY/4FQApkV8Imgp0gXlzzqMHSGl4paa7k/anuZGMbnEKii5TVMnU3+QkZ3qeXjwKV1Q6VHpyiDgq
FAYvxR1VPJE9YXxb+ZwZ5cCGgm1tgJ5Ku590KzezDXVgklCEp3I27aSdRbLzNeIB2JLFNNc6+Rbo
0H27I1sDG6uXsw2WIz3QI4mGm9YTLgz+xgEeGmFm/0AvcRc0J5AbuNL0x+I/Q5WafvqhG8BzOLRY
Mp2MAbR93qhSkuc9YBTWGsrkudsN2/6LZ9dheE+pWKyw8tctKzLgvtRPWq/y+3f8jQDJr+upfHqc
+dan5/tZmxzcCursf+yQg5bmUSTLNR043/gNxc0D0uBVDRzfZrHt/h6ZMCL5O2QKsp47+4pz0Ytn
RcavbnG1GgF7qDwyKfu2DXf4jX/l8s/sZuuBFfW/l2WO+9dspkKaAtfoiumRcL1LZazPvnnOp4sP
Fel2dFWk9koL6aoJSSfOygfh6o1UxW+7OwnnlLf31lThzIGOCzWvFfFbYvBf1blp7mnKARZ3iDn7
vL1R7t1BiGyMr3kDGAlX77AY6rxN+IZjyJkineTFstB6CeI72z59L7wG3bRDOLrN8COhnefpGicn
i+BMdlW1PYheimdYwgZKMpTnq4WdALtmqCGlmAl1K/BvaohVrkYh/PNAqAWabvlzI/mf4t760cV0
1gyYxPXF+csRXDMHWN3PuK5/wWGbP+C6yb7/DueqmoecyGItMdEG3qFGC6RHLhizkMVzToYNc8DZ
kzr7xqfcBJBzLTOIFejy9KGzN5TGazQf51KqThEW2nCy7apQwtXViPRZZ0+89r6pbRm/93h2W3dT
y2tuajI7rdUanoeGvYA7hulW7xM0p7VI3MlwJcIKEt4TvF2/X6940x9WBXZ/57XsbAdGtYoGprxX
jILX1DnFpqJL3BNhoJ65DGwtpd8e6mGmR58Ekj6JkD3H7wEOIUumziK4DKqVs/pVnO2SpsL6+mYe
aoJXbr2+hP6r87z3wBdpaMXFfyQRdjiGQcQQJELo1u0O8tNNAvbHSx6IpH6jSmgpUgYKGo9QqEpz
k9QZwa22tkIfD3euGT+sLqymuY1NBInCZymJURG7QC2nSqrTuO+K2y5UvLSQSqGJaWp/BYd8+K4l
SAPWyvgrYfVdzhXDterzdwwelaWs4q6LAVIhf/c0j0cY7anFaj09dHYiRq7MX5p6N4fGrDZEvymA
XntqecWRZPmNhQ1V44x254z2ocbhGkdVF4MfUlFMQfd7NB2gWaw5DXXLNmT+/u4iFjQ2fcCIWmPe
c91EMZCMlv1QxUoBgYhgFaM31zfcvR2TfatgY9zPdE6GZ389YXnT326JXBV+Z886d4oM+lBAHCKg
bAMdKqz7yRCo9r+OB9nsh6lGIaTDV4+49s5+Vynheom6pU1rSdS2Evt6l1KhhduNp/ecu6vsq/q0
O6cVIdvQIhlYYvjHm80Bwswu9ihKLKh6rzjLDselt4T/f9mX2FfvpZn4mfsay6EjJQMfTrXytHgD
cQWjPBRetZz3zXpBl9hm2o79IxxQt0Yvr/yYAj1ZEXXYR0t042UpvAKTR/nkwKtSnZgXaksMJu7Q
D9leo5ETU4/CiZH+VYpI21eVsmrXi2wrWj2uE/vOo2bs8wFX+vmIOMEDvuu0MM/UhQjQ4f1nEomC
FdAUaHrRVJryP3lqMare3WBZlynEj/SvoCYiepj193D8mLOFTj9C9egmIpjBqTv0VbsReHJC2iR2
edrkKhcHswYZ/J9fy3ALA2TwBHMvLSgZmspNSoPf3+imEd1NUGNconMGQf4LcaArF2RoKsDNAxq9
VqUeEuR9NcnXamsX1ZVUYzBWGSDT1DqH6e/H86/rq58S5xQK/7zbpGbpHy/yfjgPr/e6MyE/JwFd
gmKryjyiRyl9khjPvU5c/wgEfk4Uoeq+mJd84UCtz9f8Ms8SRY+I2DbgkCyb8+Njc7xWfO63Rdk3
leZCxQ9QiOLXmSby/oBmYdjsOZZg5ikaUx62HzfeZNnrnlUei4f91zyON229njzj6VtWV2rQaxUq
Kr6QrrdwmOGz848zlw2X53IlwohC0DEyz2dNG11jUt0S9mKt4tbdvOzW0UY/TwuWXCtEy7w5dsSb
DKrXPOP8mUoWT04kr0fZ8rBZuhYPFyUSSiLlt0cKrx+TNNCeVq4+qIfMGWIUbtTViAxeUFlPadAv
mXkSQiVyAKOidvXmSZnr4JhJdKtzKu5WOz28D3QQyYRlg34B+tPJTNA9mOV6XgD6abMSHOLAxfOA
YVbCWBXE/C5OnbTMqzPr3RjqEd7APD9OgGWeu9x9moMwqD+avntxm9beZ3XZAAtsB/TC18Et5Bw2
mWQVxWh5u34s71pEKPFFd+4WGodLG4WM3SdrLAdF8iSK+vvM1yj7W/0oLy5IGwdQDQOt2uj46tXj
Dth4UYcDBXuFaNgMBsEvAjdJDwBg3++3i298abF1qnlS2nJ5slNJT+opSMNUVfI178tcPCwgMl94
wvZksA8ySLmnVZP7e/gALKRF+WvCSxRfBaM3Ax6K9qnQ+ZPGMspwPUC0Fbp0dZdgSqt7BlOamUuc
VPxkqXMlt/ipvYaxM/d3qKvOjacILZ3p9Hfe7uS0CmqC7vq0Rv9VduS0udQgaIb1t90LUYuShQID
HtUzyr2JUs2IoJ8UeVARdLvVp9kAcb8X3nqBOgomfAc6avJsCoi9GE+egqPRSkbnY31E09YdXADq
6w5KU2k/mnO2o5GtF1ufyv4PJ2kXl7aI4ojYBXQZvCv8NYWkpXX97tf/lZAJH5qTTq4JWXdTUulb
YYRSXHESDVfYfnkKAMqUBnm9hHr0Dhf4UEexclUr58Pn3brvDJyOkLKLMtInP8HUIeeU/VjQs8lE
AfeIe8zwJw2iXXYaAfiRWiCfCz1v1qN1d27Bacd2jFrtFBXrWCGBy5kk5XTW25DkIQAK04wYAGZg
G292bWdPolYbtb4msCQI6koWjwVLgKRCC8fCA9wvZVh2NhFCHk8Jp4sJTWQnTs8q2/Zk4QuqY1z+
G8P0/Dd2pJLSFgAquMAAam8Ad2TU6y8Jc2lzoMwQBlWZ9JXXk1CVVbUakoYISDSmR0lWocp4AA6U
+ju60PIEfieOMXAmZ33j+XrbteaEgUdyok7khgvm6HQv+b+WTDKml1bxsJuEAX/Ba3cRaDTz6hyy
oRKRqdJM7aszVgaHJEu+Z05b3hXQjw+hvpvlDXHo0knx9tfp7Oym/Y6oY0WAOaTgBRwBVDCrNnZA
B9D/sikqxe8iOrfNNXnb0Ryhve52qzTke8pYNrfT/xBSIuz56By0Av5UtIKXv3niz+Z2IYPn11Wq
fNLB7HEAbnwhlaROxxrp1S48XY6/nu1HWqX8YHD0MujKfl5NZIgHTqwGR+nB5ZM89U1rH2AkiZvO
71prkWxtFFa/QZApQaLoYfdwHp782Bb83l8pE8Upka0kAhqEbbnyaW0V1p3M/qcY73u5iHEsCXUH
668jE6U9IbFoo8QvEy6tekHTghYA1cvXGB8vRkFv4VLVMUn5ZRAaWQPJ07QTeg6mLlkudn5PvbyP
1zfMH+X4BPpGA5Mvb3aBxxFLkvPRGMRoXNi2Nhx/ABYJWbYdQrm+d6uWVGYgbSbjXSH1DwEbZJ17
1b+iBYviJm7YooZA2NVHaiFMwONH+mdBTUA/gkSD58YkFTdCksChvC3PYRDDVeGpBMMIvN6ahCQB
D2WBzh7Gchuj05a4e7no/PcRUpSvW1FC0IiBuIz85Fk3gZwD8NuqKep/LLqOAWxbXRoHegQF++wx
Qau4EENTNX1rbmR5GRitPODEnUXWQr2Yi1FhjM9MOE20DFMw1o+jk76PTxj3qKgGt4TYtm/w5BSE
0NM7Bx9XKdYm5XjHC12ovjgM3nXVFRMsl2gI5uUKhYJ0YYoBmT0/UtvIu3k5+BLDXdqn6rpLXM/V
KyF0yKUkR/ZFNstdMpkb59yQRTdD9Ba1KUfVi95ulTmXfTWN4IgNjrlOXOvfbU2o4alBkVUgkiW5
yHp3AoSr4ytlX48Jjteh7N8+9g2/L3n6Btsog1cK66ei3WZjP2c820Y4a4mqzVal0raDYgSgzJtV
R7okWu4iw9bNFRb+l36MY1jJ1GOpSYAOilYRywpUPDiKrqHrWFbpldF0khCHoUGMHBcoO4jiBb/d
moRIh0HmfNKRRBca1V226jgTX4TXblpEpxxdfLxgyf1dGBJov9KtPPKNNR/lmp2jb7F9SFBSPtYf
c3G3YjxjzbLJf0pIm0kNvMsHJU2Tf22h4fwiWpOxL8span1MNYsk+WR7I7RWJJJl00mogPLkqh/X
6KSVqy5FtGU+gX2Wg9tUM8u+GSCgDWfPAEmo2aa4m3le25e2mntPmmQrUVBiSUB/Q0lh9r6a7S/Y
iaZDsa46vIqMUd8KaLBIB1S7B+R97391W3JoenY5YbhEeQn3vMupM2xvfwGTEVrsvvzARWm8BJBp
9sWnxwpT5x0q1SL4e9O2XcCWHOlCY6cKWs9yUDzaH3rPkGQo4MAnBfQSTMNO5rE5BVE8152TUyuU
yiAkYUlCalPbpd1Acnr29C7ItQeBOl5AOdLjI4XuOxlu7bOe7/ZugzGQcAWY3XdQqsFmBZt28BM7
UvqdZiG2n6W1cRjXIQfSmLURYJ8qaEsJETUS4SHPmn8lx+w7t5Wy0fjfxpMoEYAxqfp8+ODRsr7M
g1wSBbNVYDOkUzP9/kyEEEKm5NNIFA8Ho72HqW/n5ATPUtpJ4s+DL1IiRSTDURtwLa863apmd3x5
1NfDPhpH2Ft1JKtmkgIvUW6LdRn7tvBDQrJEXkAZnJLuW8QjLUbliMd5mHZlqJPWNLr7CHcJ2Usr
2v84MOFE2uJ/aA/oJk+nFCWpZc9oFJs1ttWIqTTINnc2i77yk+p3PREuMNWpc3RO3+mt8+Xt0scJ
umfvE4Ot1At8Zbd796MbvWeIn7eQ8aTq8R3GzXlNFJ9ZvsDFfYYkWpw5mgV8xn851XmuPvx8i0QN
m9sSHqKd+8FDW+ieqjhx6TxedFSuXKn9hlx5lKNcQc/v5IyMFp0Z0V2EeBziDi/PZ/062ErjKMTg
3DUpOOcGDNRDMguZP+VG3KUUOWVS3UpZV7zimXQuIuCvT01krnFgfVfCGiHgoTbgnb2g8hhpLXJh
PmS+d1nGxxMpd/4yrltV4nMQ/07X14DASMx4psYpw5HxyRfkTRgbA6PwpmpPP0Ou21vCtmlTK1cR
TjDRWpwQiO6A7STcQLjc4eLvvZ/HurwjLEOXxOAN5W5Og1/eynGxif5zQuBNv+nLmiRpmoEOBViw
0T2Rtz7tGVr8/utFWg4L4Sb9hWvNAHK2KL3W55DXshJgHLbbGZs2kOl7ERcOB6POqBFAYi4dLveQ
FVd5aKbBrkui7ajj6skSQY495Wur179WFMDw7LgyX5bJa+xUhrA06/E9tczPPCKScHW65AslUswI
u3Sr8p4CP7ahmlPaP59xri/D87LOoMy9aoHS+V2kT9JLE2YQ1ItF0jNMisdtJ4bD8CV1YosAbNRw
q0lnH8zLAnFlx+WQ88JBXsPlKgM7bsNZh7TQRgXuc8QWZDjHaQZIF/1DXO5opVsla2czZNs75lnb
CqMXlDJlmtwL9G1lLhCHCoNTC92G81/K32gWEUuKdDgLIsyUNCOQv0exNclZCLzeToTr5hV86+2H
FKvyC1HkSoYZ0xQOIe+8r5oHvj8GoM1dCtYwh+WwGBwBrkfNjyv26sXz4GrnqcRA5PqVte3MQ8fn
HeezXrt5Swo0EtPeX7xhnKyRoN3jDW7a78xf20PMi/zYN7tavh0ABJLsU6RzkktmGE6w+/GP08Mj
lWx3OuqTHFC7X8eoZfGJfhM1GNuwZ0P/FI7IxCTgc1kZZXEmgzBwUEry/wYaH/MyKJP+yxCrC5+8
6fYnM6REySE2yNTK31MgR6mS2D7NUB49knl+dOJjec3afjHt2zNEmJMg3fAcBXactOf/J/LYYVxf
nKNsDZOkORTYrQG+R07AooZCHpvYkmP1GcKfHZN+Jx1MvPNjUFVAwTq61gHqFCKxITYeesm6ngrK
HFrxGLF3bun7mX9jVAiP9eaHG15+MV8VAVZDLkUAMJB13DA9Kyl4jeVv8Qne3PH2DYnyK87DcC0c
qHF0JQ2KCXSKd74lv+UCf21Ss/1V4uX5zu16Su5Ycdc2nmaUgYOkZriPajuNb3525QL992l0mhuO
U2AJ66IglFnQ7wRZgwL2gqLt+9sJRQgWSdVOhG3/j6lCFrDgZhr4AbbqmG3AHSBUsoIVLY37NREr
lPpE7xsWHmjcZU+YNZlMo7/jfuisSmLCC+D91BY4mzEmOPBiiVVnBftc4JuzjhqLXD6gW7IMQ2+U
HfX8OaEUyKGl72OAkyZYI0RzE/IK2thK2cSWzgDIPXk8S/8Z1mvh0VQ/ulanpnTe0rGPY+k30yx7
aV8P00BihK/0JAaxrf0r9zhwKwFG7LYUkqmrLilCwaYsBZGsSsrSM+iTuCDYXXSiF8FGSiY9reBO
kvTco64h555jsdepKTHOML5wrSQqMixxXzQgfGjxDxV3INZZB1l3wDN9cR8JzH9JD48O+dQsi+7y
kWALxRF7fjkMlhZczuoq2FN50y4M75mOSo0DTA0Ox6DLRs8unu30t6+TY4ptDrRh6fXJzqQdg2AE
0v2rolvQpizaeg8rMD5RfeGbyUZm2xD4Djlfka7Df8HK1vSgeVr79oXzbduSCZXYuKVpmIbiQdxV
dEkF5hO0FgVmyB19DpRGldqSRrlvtdL8L1VwdVHwuMrCdW8N/F00SiA4U5xk251A3H+XZnFDsJTP
LlLoOibsgtH+eLTcefkkMoJvWIMJjpAhjSSBUooU/odasrVVUTq473W260cXRXCv2/DmQMmmsC3l
G+OpN+fyJejIpLe/vjQ60D8hs/zXxgMdENLbZNHXA51o+xsIkPltO91Dc/K3z2GO0X5YxnSrRbp9
deuWkxucsUr1PFWqIpL0P4E90Zy1Y8c0h9uQxqb+fWJujgUkGQSAc/uwzYv+DFEDcEWJUbOoHdhJ
fLpEpHkcMfLJ4cpHEwimqUPJaKgQsZAslZRjd6Z/eGuhc/bJOtZvTe9o1ASat8lwbIFXKLlIWktc
/DVBTG/qSM6LFptOtG5CHJbeDRuNioTJDCmV65GS+aaXU4/7e9xn5y3rdzDCSuZp9SFO20uozyeC
u0iRbUHGq7XGCmwf1ElDOPUmEG4olF0MEFpNUuM/c0YsM5HQ3/iCfno/oY3QspLZhvXtnbVa6rH/
EGn0ujn/LZdAIHkpDs0Mm01+9rSQpSnPL+jV50A9v9IIqzbpV5UdzZFmerPQK07H1tC6uX1C0MHW
T2RHk58ZRGhE8oZqNSw1b2g6Y3jzap7rkkkMALCkJog0GUFMDtp0MOckM9hTYek7lEMrkmMDSHV+
NhY78upqr/lr4iTqyqVqlL5SKWCVMIDgqM3kL8ejr/iyh1a7hRU+qm4vL7L67gHES2aC8UaKQ+2w
nT2/EtDuE4yy9VkyA/nYbL27NKAszYzQVcEnzNrY6gxT4O5+mkv1yN3+PRHuZVIIbZUk//wIyd0S
rcqaQZ0uGys1qIeQc/VFsfWuDpKupgqmTqCGsFN1eFBYv9wkpaBxvnkz3GXnLocK8HigLQQfffLG
su5FbbvKTjLTPtFS9pcXJ1FW2jaXFo1wwyB5Mp5CO0su6/fWyJVXTQ1BDWmBsMIybUgPj930tBXs
1Y260+gijhF22oERgfZleQGrEOrcDachCG2sa/gQFhrFMhTewGJxwM7F83KjXyLeGVm7UmAduwEw
RaAJhEgEjzan+sj1GqS6r7y6QVSQUr8fBEdDFrQlvBPWrVVwjKUto8U7qoeaFP09STGpGCRGaRQ1
ll1d83V9pyPyDsi8GVHVKOFmzAkrIO4QnomQalt2y0nH5ktITvxF24wLJA8h0TiUCftZakmtUhco
aEuitcHWFtGoSp1C1RljwGUcDoVim2aKv/gSXJWhNm5QEIpSDw/2CQ4kNVycrx3yYazTc0v7+5/Y
W+2AdW4qcton+LTLee2PYyQ+ZfVyEjHKYKMu4GphuE7YULiJNKtefkxkPdRrBtQTZVsd/J02k5c9
a6j/G63JtwutuZbcTrWpQxkakgt82ffS368slYn56Am92UVjsWrl8oJLfz4CscdD8Xxo2VHyPZpF
l9BK/gt1IcWvvJ+RNT8dwy5UStUBXzkmxOlYpTmHwhm0sdm7UDZaUitJpOM8+W4/wYRM0cqB+XlF
TeVdxACTsPQ7wj+atmVgV7869jN61zKmuvTf55N7OkeVvE5JwuJ9kgDA6/CN65OZk0MzbjFS8LCi
ARfVpkn2iZbBy5/0EbJ86jHf9uaTxljNEJkumAhXSRLpPtuBLlZwtM1JFi8oX22hPE6yXAlVpeAU
YvYJBTJRR/bkrlmmBRE9c2Jkm1YOUvLiIXsEfcdJD4Oq7VkIFJRBqXXmFWum0ag0M2mhVUII3se4
7F42wMMpTrj3T5T7wp2yiRueaP49XmfqJ80Yj8wjPj3ThnHnt4a2w6D5hS5vlJ2XVOxZb9a2W3wo
ErYAJtUFeAe8m1e6PIJs9HbsZ2Pkagfl4a7RowLp6gLRB0SfGd0zRSpbe8WGh80oztQ8iqe5HAiY
1HmsYW2Kzq1a9TpFUMCGuwDXLAkK97gDoD9c0R6zFtMqkXZsVXoLYr7GC5QsmSDj5t11sIsizzVG
FMgGv+jAJ1lTuEgPJnaeLlH6PAogZWS0J+ENPCDPQXgE34i2FHsCIjjon8FWHYt9JCM6GNGA7RLu
1LSa1ErYzR1ATuboFmQtGBl3M7Qdty6RfRdO1Rj8gGCLMvtDcVKQjundiKsThPknPC6DuA7UAOuX
ZG7wks2JIjaVhTkGN1NLg2ULW7PlMYciF2iO9Wq15LzFLVXFsARi2+eOz/GgDh5y9v+FwomaVuZK
fUOoIZX4cn74U+wtLeoU5QKaSXTKr/k9of6zgu8KeAFv0Jv/mSv/Bsx1c0euX/zhoI9XSxqTXaC1
R56MRwW+UoRW0bxGhQF9vwGT0N7lSHjcsnlB1K3imrPUESDsZeQo5pQHuw8vrFQdZ8DI+kCAhlWB
0PsGIMDOFc/E847NIREy22vMGlVaBf+ItxSGdQJZy/VM0Md6BOflp5c9gKRzlUHRFdHJDQLY4BAs
U2wZGvbhbiw/yffoLwdybIctY+fPE9qB9d/87zObfwk/RjMUny5Bbx4SIEcaWirv9AddrW0Hec1b
qd03hMsKyta24ZxLVOluv4Be79a7esUiEQV/YXN2EeTrj2/o0uv/vkUVRDAPcZxGggs54FqA/l5h
v1ZGdM056bY5FQUXmTpUcDRP23yuK53hIhsjp4KpG9m/v3NquQ9UlkrJ/WUTp0sgCSB1xX0hLPQV
413j2GLTuSeGmxNSyeRI1UE6Q6y/3fjDGd0abS6fp9k0wbJxxO7kqmB6dOgONJZZcetoZh4qqpah
tuzPUONzeNXrbjfdBaxAOzRsN/m/SvyYmZPk1vi7zI26KNZksD5oJRcOeqRvCJpZiRNhRUvXspaI
yS8I1hL+0MgH6crbeY/mOu5XR0aiFDpvMO5iHuTFAcmSxeB8Uu+pVPw/KplEoljlyDGfC+waqdIB
5nWIDWVCqQ7visPczDsyWdGN9VNzGPeLXAF5L36cw+Xtks0kf6tpczoy31drW2ZnGBpAx+MyP1P0
jdLZHdxVdLJcA3Q6NfvX8EpR6vXAhUYI4PtxT69BXS+44PfYiRD4KHnoKxUiZLTkvnmj6wn/jvIp
yzchCj1CnE0Q8wXZgIyc/u3k1wopJjlP/UlAAwbzb2J9xBOQ2VzC/tfjpsHBLVemyPtopMzSBv9l
SfQCkCdCob9wH6Tw8SU3RyhMMyaIsAVZQmO8+Noc9yjS9H+xo8+HSu6rjXouqyfYkJp42/L8XHz0
LlEdDgoFdcX8Byjq7WgJwV8/BhL2vtdUe7jSNSPN2koQBO+daic0EtTRVyvgr6hfXE4DGrnI7Ihu
SYItDLh8X4JINWt3fORCkdjDDGqLZ/1rXDubXCaEpB6FtvOt02RePk+XYto80zKVWCWzU1bjC4SC
37RKz9JI8REpFrW52s12I9EUbZrViuT/uQCeqe7GGPmWIXauU/wsVnaxUnSg4qBoVTO+Lmx4GmTR
6qFKMRomoYy+2+Vl1jqk3eRpHC2U9NFGBZmNG7+yoS2G35sZOIa9YAZQpE1Mx9hAK+mHZ5tdJ8by
tkVwDhSr/VjBY2Vghj/erNpNGbdzwpacfjls5nsX4xQ90+uXmEMijv/DDrTdksD8swthPQwuU4fU
unqVKfos3ZcewTegSe7us7FkdFypVVQ1jTfyTiOLTVMpeeBDiMbOiVXseNxjAQIRFGRRDl3+2KAd
1+p36KJFfXjcxM5M1yMtpSa7VXkg/cFei9G+g7f4K1U2uBrxoZNFeWoOn8tqKGq1kLvlNVyo5FRA
DlIoR39LvwKL3emB8IfnreblAmf89fNVv1w9OH3f7uJSqNoBrHhUYfR5McUVvQwtEGpswFElT0YK
28xiukDQmMgcAb2Y/QAf54jTK3ongm1OfC9vAh8c6LPrzCLY+EfBAg1WO4tXDdrKNhvZUcbSVt6Y
wFEGpVK3hCNRDDw06NZbRJpVbJ2rlEgpFIBUUsPfyk/EzFOtjW8qsc+ix7tpnQswt4v6verMkzOl
pxiwTWPU8YHfQwik3GwZFSmy3nyhpKjFPVp01PonNq6AWsf7wUlIV8YNWHXnE/2eOWqGLr2E2NzX
KcDu+z1n1lAzPIE761b95sOd7qR0OBcGClHKtxfOqNGA/52SRQlzZu5poP5g9vyChtnp/lMKNfRG
Rkho8td8W6bM9wGvAz2ripf0Ny2et32zCwMJDwEhjiWXGtL1WXVDFO5Cn6SM5DwCWoyYCu4BQknV
KrVN/9r9mh8XCdMKd21R7s2k3rgsIeaqvnqjJdmpufwsUUK/ih/oUHQWM4DUhXXzahYltmIMuiKc
pul3rXQdXqTI1pNMeAhiYEeWtkgM5Crn4VtH7E+9Dh4khRVydCTqXMxgl6xG8VmybXf/Y+fZLfPn
vZiM/0o8gWE68wIDZwYL0UCqzeR0mVEZize1PIPdcwLWyybIYcGJAs1BgcM5MWCtleqnHtpU0lPM
oTfbskWI7mj4psPsDKiQgVMzz6Myi/ZADfi4j1rywJTG/SkW+qvzR6XdzBRlazPJdXVYuQrLDhCM
NkucE1ki5TZxLXZnrzzFO1aiTxfVnEVIaYSmmSprRMOkzZw0FW3ESsXorPyGoQ+B0QlYNaAMp9j0
OfHZH5uyWYEGDRqnaN+zN73VemzBB1+K1KFr/FHArJ/ueiF8YKvE+qhbiQWKtTVw+OUurNABvKkt
hPXAVLVloYpyyX+i81fbfLBLs6R3Kyene8acHY/xuWSFh+imy1HvjRk2A9tWEaBPvmaWZMaI0JRT
+4ydpq/X3APzIMyqLslYFPwWHyJZP0ZGb/ovsBB8OXwjmVeBkECb8IuUT0HGNfEcUk5kRShOsL0V
jowSpgl0sfORo0h3xkuiwVvHeEHmFPTdEuGPPghcMmYaGm/HgmF/PJ2IUqoELD4sp4ENRMAHguXz
L159T4kNoda+74AbR5l5LdluNIMFaOKKHNc7vcdH4/hmWcCCPNYXazbuMW1V4W9+hUCFmR4qKVTU
aNwv7uZAMlIAvjEEY6+t5POBZ4b+3YzOIUCA2+mUOWZ9buZe753XJ3NutDh4le2wvdmiRrx/9Iux
/Hld/LQoTbr5pz3+KW0MP4vj4AdKkeoOODuay54TWj9tuAPA60cwvRrsyydja3nccN8Y7YFTNi0u
KY4H1sbfw9PifzNl90OcY2lO5wWrCp8fiOnw/8MxXBcG4vHU2CWBWC+GxMImQ/C7FlFBPN6Tomei
mZI5jqS/xIrP93QDDQEYf/ickY4s8UBlkX/Djsigca+eyY+GRTYU4lzOvY+KBp/o559ZGEZkwFVT
Oohd32a1BSmAA396nTTkzGpL3yXwCOuwfaPPZ0wkvOSfPTd1H7xl2vZrnlCbneMcP0WZupKyq8oF
gHz88SRWJsDdqfJZdGjoGPgS2CXKc3YCsPdEeRnVuzFCNzKd5gW+6ZT3lOwW0mvNHPWzXsSjPm4w
p4CM/WpVzY70jSW+V7qyk85M9RFuE5MxIeWtCSH5fRrJ3DRQShpuaYZ67lIiB345Ky+O8JZuQ7EL
FYCenwA8LFLy7OjXbae2kkfdArszh9YGhBMm75Mo+Rxm7lRz4BG5q3//Wpa45mASxnUH7P2mvtuA
xchybJjt7OhvpijYRj4ryuzDqPXGDN1OF381GR7hyAOTQDDeOu4uLgjNCMn6OEJVBK9490hkFSMT
8Lb+aFZiks8leqV67twfDbkGlrPTU26k8yabwxWGh3bW96tmJoAR08NEdTto0M0pY1UL9FiJOeRP
VccvETtRFuE4sZGw2K7fEi0+5WP7IQ20ciFQPP54pDYceUKK6ZfIQ3/fQOwzQPEYxoqORdZ1azAX
rzEQKQNH412kmKwYeaHQPoYg5UEY8sypUwQO8199IfadlW3WIsZCtq/IdlhhtmBP/3bYXzoFQKcp
4BF0lw7RKcyKWevbta/mFbqd1yQggbslJ+HvozfgFuuYcAkqu5EPaosnptfHGhesz9/X47s8WFuE
nP/v622eV0JMR102c2MDZaCSTxvwVYH/BQfazUqSkei68c97fZ88WFVjKVYvYUOFKq3sZtnoTGsf
0wrscdzCNkS9IDtuDx46SQK4ffinJkNyguier2c4Cq1lnkG38HZ6ZmWX+G+xv1Wx8Wj6r4q7+SbS
ENiKOzt4fDxYp9gii1B+vP3nfy2gk3e4HyzXJ9RSOvjc/n9jyKtqmA3QyxxNE8BWJLTWqGViGKyn
6cupGlAwNRglqpX2bWDmdgNJvfEaw96GO1naqdH+oKjnrkCc/furrc8VnNpylUt2bMl1z2++O+la
F0MxHzoorR5hgRyLR3pXtMahLg2Qn60ygweahhvQbpJTOpgcjKJbXSGRxTW8facJNw4BekFBrkDi
8YwLu2Qddd004kxgQa4Ci914V2YVfY/5g11+fJtp2nLzj06HaC7GHp3Y69u8wiIoWmG5UC+XsEad
OYlKQ8s8rZ1LUM8UFizlAGmRPwOUE+1YbmS9QJjchedYoURhP9Bk0uB7evsFCWh6CqpMcE+wi0+v
xkFy/NCkPKrlxdiC4DrH+r6jw4Fs1mJSENenT0FP7fIVAYL912Xyck677SRj2hE68QfCGqLiwVPk
Je1VKWQTEPjh6H5RwvBC2QjQDTu6q4OXZv1PG4qRfcEHbmFaKJjkOnHW8mlG6pROhVXOrnii9dE9
MlsjTyx8Qh2kL51Bb/kpHSPeEWOZD3CZRdgv6LzAxuDglTKoW6eigylVeI0pMCZs5ZCb6Lw5glyj
jAnfWL2T3Dr/v/Zu9pJwRdE2xyckoFk1hVUV30Bw8+JEb9X3gm86Mn2Tvo1t1jPD37cHA/FYLpWz
9uRKHNkVBatt0/r5qN7V79OSuhc21IRpBkyZnNOzBDgAgPQeZQig1ET5Y0iW8MH7pf15IsVen7Be
kcmJKOha6kUOp5JKzsXmdeodvsISBn9kI1ZHU/WugCvRaVRlAdH9dTwvk/Rt0rsFBh2jzmdHiVBP
pFIH+AY0Yp/3VcmkKLBNFvK+XglLXZ3WsMm7DP442eNevIY/MR9gv6WM0lL4CqoOK81cBtIEFPNf
CSHgrkhl3pVSloZWAYd6b+jkGE8nUAIllSD2eCVYAP2lodkiBoaLSX9uk0oRFAExqFC5pcLMlhqL
UMZ/HDEljkBUpbTHTM5Zq5r8NrfEERSR/jmsNQSZh9Q5LSw5Nnc9GYtQXBYdpfAQltHB/Bv+jmUE
DWvZq7oxcNTlxO01yeUwaXGrrvzeJ8i1KMI9dMg5cqz1pTp+iwVuLfjR5MOf9dhmU75qdt8/aKH6
BUCNCRkL+I00qFavwhxG5FOCiwhxOb7GBnulq/7ruzK16+RATCT5BewoIThlvCAmVVLy2tOMm/BQ
/FduyYmIsdNDNBn6Lckta6GsLiVcsWi8kXOdnDh1zUsmyjY8H62z8KV+klGAwhG6YWm7TqdZ3ffe
/SIg06L03yEN0Va537F/qmhjfFWrCfYW4mPZNyLgTpohtyYbSpmjg1i5IxD4N1Lvgo5dd5drIrNb
268HQyDjTRnKId++zxAXmDgDLBC4zwzy//rn0a2cqA2jkj7brCNOHy72aAZyrhAUoor1QvVCwRH7
b6seoSWm9V0DQXRU5YnW81UnoTxjOgYTGK4ixJmfkk4l92VuA5NkRc0LR7c1F2b4eQl2hk9Lg3i5
1fU8KC91npB9+KrwSxNhiqyq00X+gmP++YEGhDjInZZzkOT07o3tWWYY/Hk9YulmZ0aVe1DgiqhT
jwxClTK/6t2bElfb1Zk2l6o5jPK6EO00NZiunUCpU2U6z6M0hZS/HhOIne4rZvYMZ2MyPBQHufjQ
XMGfFE1BxH/nvxUov/iplBLZz0i31Gwttqe5j5gSQGYywYj9cMQ1jY6zqLlw0QMLeD87IPfZNuqb
UOkJdVMvBIl9Oq8tD0by1sQIDP6IRah5GkGhpzY7oRNiuzZp7l0gTK87zFjdsS57RQ9pemnGNzz7
3yFPWTspJTFsvhsqQiTAwPdXkmujSgN6rjHqyNM4FFpk9Tj/D+hRIiy+ZGmvChQQmEhxRnIDMi2E
fIH9qBxiMy+0iJPUrIGo1tHidC+mTqIh4JeVZnG9BEVzxHGDIyeknUXiArcd71n3t9AOpKUX8GyA
aQiIBJylHsNBCYeyS9ydtr6OGo/v8yW4I1Oi6lqa3+rjOxpGHG6W3thgtruuHk31rApny/eJEYWU
oQLtCkUrIxi0+IAmXigCGcziqpDrgFlgf6RaAfTDcDWXN7HYFFo3IHhFLIBM1o2DmcrBmzSDWLTQ
foTqOab6QtBAHFuFNrr890/E/yEHva0BFbliiHwEGYtK2efj6wJ60ARLB5/BG91N2yapT+E+Dmwn
wv1wA7F/GnK+iUHlIf2TL1iALbtja3AFbNleah5oTA21yCoxaO3XMw8KsdQmkfGgi+CBoLd3UgYG
of9sI12hhxseB6ZNc6SewmpsLg7vYNcOcIOlICgFSyto8bDlqcSm+UdIM9/0dTBpgzHJ/Td3LGT8
lqtyra1BV7A18WjZugWnQ+0Fm8JIskoTR9ajBhglXr6frOdmxz5trEpHL3Vk+rlIM/NrdXjKRqjT
MzEWQv8Av5dJ8BQoRgtViOvwY85BWFg+edY8km/IXk9lCZ4slOKZYrC6BQuyxIK3K/OycQXjXC5Q
aLavcf6ntY/8gA8foRDTlc3w2hkx9ADjOzm1Rxwab3tLiM/qC6xy+ScnYm4MxVmA9QwW2eNpun0O
AS7Y/p5TvRJhtHZ7DuUwDmPLEzgSZDWDDI+gOOzWcfny91woujyKR6FMUbsUauZRVfYMfGp5RcC1
fSl749m30o3MCWUTmHEiIQDZ0uwyBKHrQcscHy8PEqKvYsXN/qQjPMao3ST0gnt11by7c1fkaL9i
v+1GK73bqT4u7j/I8FDnRM3LZNsTGUaxUdZxrlFXWHH78EdVUi0T4lxW1dXdFFaUKe5aUSyndeyJ
PTQm8w0CGVYrlMxWa96eweTUsmU3CXtzlHLkrucUrXA8ec4ONJPnJCVez/2KtRugEvkMJtsSs7Mh
MIM94vDx5nsPu0I6064iB8BC6uD63JyHrkogF/ntNWPWQWtIRQzn+7tpYDQS+J7pPhq6aPWb2S4w
j3MMsgD1UosPLF/sdPpgn2GMB/5qDAjEXH/BQxrlgypShAekD7vRuVRZwKBWLMcpkb9b9qNVf1Vy
nrGa+gl6CLGN0eFI8XA3GGEEoA6upddpq3TI65v+r68LV0mKAkX2fa2eLG6SOcC+fP+sgqO9Yxex
XB1DL0HRK2pZFAMGajQuVr7OTnaZN/DCSyiYkNv/ZJVtrQwx+RNxG+ls5Y/hPIqOYnIIeCuiTEQ4
0vEGQjKzFN0qCwz5PCKqgyg4M1SQ4QvbeKN4cH7KGzR6O3MjcAzUdD2u6UYpN8ofPDkJH66DvzQA
/bEvb1yIHXTcDhLUK/Fkcz4ZaHVpCkUXZ9pZsH/+cTa5CEJobJoDHB0OiUetSR2yrRBA6akL/UR5
hkZWe3Q2vacToJ4l/4U058D4l7oS4C3E39BAq3nWkRLrVUb+0ekp991gMdJv5YKWOMzSwTnCFEZ0
+fkboRw5nY629vEAePEfYtFo+gCRWpB/Jit+yULgXaXKrjnT/s+4xjzIiQ6vPpUmL8IvXZEJBpe0
2nt9hG7jOLOvBLu5KbeOPfF8M0LPQ/X0xWtIMfOPrvGTVtvD4W1uWGAW5YOnAwxsVXYh1fXHI6us
L62DxJcHgSZvNI+AccI6YcJnz0xmMId0u+F7i82A30v8Tv4/Jm19BGVHChnbSvP7NQ3gsp6WFPby
1+SBk8iXYdD0lJFDEmdAMBZtMEyUwdje00sSK/qtbhE+NSnGsopp9yevXbmVUb+BFvkQfQOp9s1M
dRC7rTiRYTxczFd2quVuNp0bILAcWm/NdVPTsZOLRPu972czl9BqxaIlSvpus2Lx8Ia2lfyE4lT6
BMpfkeSjsgOVZSXe0smqFOAxQ1EiFZfdwJYhmmc6Fkcq2lHiKsngAE5CggDm97Vt6M2qgMYU4tN4
w08UgIXrZkPyJuD8UQhnPiEa9wEdLZwipDXbm4K3KzIWbD23h4dDJBX0HDqtnWmxVMwzjGhIK1Lr
TxJ8der+L3dQ7FjfLVrQfG0IFm8TVaSbOMwKohdnhoPStOBKaefgV9+5jDPGKMutN96dRap6AfqF
K+ui6Eq1KVjv7VwYDR6aTDYHMurzsN0s1+VQtRUmt3BtlXymXMcWNEwEMVoeijEuxvjkpuA0WJIp
fCZODmD3DU2owdgA4EGrjtkVa5io3ezRTz+vwbqwBbrVPAmBVtf6UC31Z4Ws+FYPh61up/hsAre2
+XuSLJbeQ8AUKYlK1S3Rho+nP8suR6+mw3nbkkxlcUJ4SeZmKTodg/1UqLW2F5qO1SwmEwF/Qpmb
4uA2WI0LKBg6GKx4A3JJpKpkhMJyYWlVpDe0oRY6X9qb3KfIvw3i8VBdexhzEu0RmfEsadj1Ja8J
oP5zRvbd3/7trw5dFZbZZ4HL10w3wCO7tbmQhGjowTUj2m9+WW1mv35Z+4ZBq6FBiRt5erSg4O8e
DAzEjBv16KtgBEtMaNM2kdHkOUCCQ/zecRufVN0YUuJDYKNM7ScqW2mBE2HXKskpStys1tRvx1Hq
V2LRSUvxVfz3Ifj8vEl7OHe8D0NeWaTqps6QeEpk4yBuNLcWYT2Y2dMza6OhskgY2eYV34eFvu/y
8pb7h3cdB9ORvkPEvbJSaxTRocjGPfyFh04icdtcIh3Gyt/gnTtgjC+fP3EEW0zs8rIOGyvD2XxM
nhxE/sscTCENmrua33nuOwzTDR+2Awmf+e003vU+/UlNIsefkn7i+Z3f/i4dyqCyrDontryo0Y/f
45sTNg/vyoB7lDBaka1fdJYbtrBqPghv5cI1tLzbjABPP+Arn6706S+wkiHCCa0CChqNONr4yehX
vywFF3tg6WkcQSUtErEokfrpYJSeHHp8TeP0nI92zsDC6VzALsIPkNkSGkBg0SjRZ1gM1b7vesgB
LZA03LGlgCAgZKMH5Zt0V/fc+adVOqYm0eVg1mv6Mvl3A0FJHEnB7r65Hg5ul55Od0oacQySfwKJ
QovxEducyEsz38WvDCui0yKLHAojnsLgz+wbD8T+tBoL9YDRMi3Z7EdII4lS10nwXm2UT4czst7G
mMwKBbMqWUSLgZXS19G9CnlTKbRYRiWkOwC+Ee6H0cRGvCrcOBl1DZo40t4dWQsCW82y1iHM1DAb
Sx8Q3o0C6ozlhbKNSyF3DLkXnjk/ANKZNK57IiFzPtLDCkzmJFw3RYEHYZ1m4cgYN+G940MggZcT
n7LZnzqs0kBXODzsSWJIn0yX3CKd3NDu0vrouLo0f3UcJJvGIjIFAkwfkEuckKQwXmsa5DPtfAUT
sXEM7uPvZC6o78v/hZmMw7mHU6AaKz6R3A3LGeLCdvdfiSiD3ZNTV4Mq6JR9kN3zaHxlrgGQkp30
sTEpZ3Quiz8dIGo8gRHZeGPK8I4KkFpQXLE8+Aorr3mG35v6ty/JSrQsym/FpTKixzGVF+sGY/GC
zhWlOvq1K8mxouUHEoezWvF4TTlmmpJdTzCfWiRRpf+U4+h66bT81vNbvi+MSznbLYvyiShKIFLH
iOayBzhB0fx3F66bqz9sSTmVt8SFf5p0elusaEHP3l6YdTggyqKbURrpKOSBiWhVm/zuU5SjxASF
Cscygh2ZUnepyB8vO8CeFIz06axwO0Im21IgW998zfw4s6ByVuuMd40UpgZ9wGuckjT1GplGJinF
NR9xq7xHa/XJ7mEWvLONDLc+Hnqv9DNYLG5nZ28wus6oL5tv88Vy9qrSmlqdtK/aEiw5vLINAbA2
Q2fQout+c79jmuTL1S2DpATFYNvyyRihOtf7e0Aks8kakHRIPREcuftVM7Kdr6lcIAWMsHCQJ+LQ
A259tf96EJyqtpIWEzwT8oHLapMpltYZnuxCBeHjVrylN5oPJHBoEmJ1UXXyfgfjL0cEzQx7z3iU
WOxxJUBV4sVNavQFL3U81WHtOmyB3kRVa8afNoKb6FjBs/5l/8qULwRCNPrg+EvW+dHhDHjrYSp7
vm8K7wLegjRJrii95dYlhP3dtuK38yWh3+v00q/Yqdc1iw5qdMX6uKUclIIoVGhVPmylipuiUBfy
vyp+Q7njRxr1euP6sGwofuMKnzATmkpI0OkbyG7f35XI4g+E83FWI++1N8Q7C8Cob6ZIagU9ToMW
vURMEwh1TTnmdfsT3Rm0Whx/gd80SxnItz85NdYdv4oWbxc7s0otFBF/bJs+ONJ4ZCagX2EbNu2G
hWK9tEus6YSQ7m7qaCscm2cpb466vOFTd36E/xjV4W53Qx6mLzEJ8OJOvFv8Z9Jspk7+VPr3r59p
AdJriSDILbin530BHSDSGLyV8q44Uwxr8kXTB5owtwrsBvjVs8W9x7E38hnLY69rnLZtrTGfpBoF
3aOmKyCPzeOU6+8xvZmWkjT8SjtecfNZuWbxqBj1VLyNzutKx5Iex7BseCmpMA7+6t+qyIjbyZeR
2NxGvDFsvqgvRUNh/pzOkrsGxWh4nR66W9upp/aUqT2yydNPkPi1EPruixo4Bzf/xtbkUF4OaGUj
07D8t4c7VNHbCDAgJeK+3nycSSjKg0MqpJOolxEPu1iHfy/GQ8GVioYph3sqvtyOrNlKIdAajYox
vFYarW7v9CIGJsotjPBqdmHP44mXWHWrcIUgW9DPh7lnmzSpnQ+ikPCDhXx5cpW3tpW0wdnyoEjS
Kv0Jwl9q7TvM9gIgaVEaK3XdeyzpV0YuHOfSwj5MbomzkK2iGOmNGn19NEagqGDk+cvvXwQNuFrz
pgbLRgh5I4jV5PSkl5RZL2jHTJUocCRYNpjwv0JIjjR1q/MRJTk2BkcWT0TfIe4iC6Q8dAmEdjl3
yWDlzwtD7BEdtDTeVzdfpuJ3f88Sqvza+nCEmF/G5Bx9k+JoWnru+Vyz4FkS7JfrgA2HTNaTfi9J
7p9erSc5+l/RnBzyk6O9cNPoDvBhXuaWNomHCRxbPvNVEcpgslQof9/27LJm4VAwAi3EjlV0cueQ
YLNiI+rm/fZF9ND5YcWUJ16/dO0CxPQ/9a54AghUCeo5bYyhdVocEHjS/3CTz1E2tGt/+phSf3V3
WqqlK/tEXSvexq7VP4GD8z+P2E3bUq0hTNBGzmgOrlV2+6Haby2abN0yncN6y78z5WphJmOQ/8pw
mO4TkR35/Hl9Zczm9JVobBLnrM6yn2ilBjxljwHFC17TOZy+mbOE+9u9rz5K7/QXvfX1yrrqdAbg
zR3oSfEmpREi0Ek1A14GHUqAYf8kwJEalE/FbfV4vUrlagMybGLRyeDT/j9N5beIQr2Y6pMaf1o+
pgmRS9wmycnL1roZFrMJ+LBOYAsKR7B1Roy6S8bcnkzT52J+iXFWD8Zaq0c9NCyXtYx0TJP55Uq3
WKhPhLLF/KiZwzmIkiXsZts00aVL5Q8hTHV5v6dGGNH/FbDuZKGyFHU7WM9MOzpE7kf9TPVnO6Ih
gLrkhuAM1xzJd8J864nvW43PggTO1U2PEdt7HBPQCNXu5tWxVQZFd3NFY30VH58/wF80wbeIkeJz
o1JqQ75ZizlkLt8F2XOEN0S+fqt5nCdC11xJHJPGo6klZRPVQRf5gqlgfJrOnj3HmlwVIs61KZKG
06YcZVixL5fermv6xFyKfHvVsVjThbOSu8bHKf0jAVWww0pSTfZ4uf0R7yUvOexVG9Nrcr4F6Raa
33fcT5Hh/dQozhhoZjil3bYUmQUrwuKH7Z4qAJpd5s2vLnXBluhgg/rKgbaSGifsaXblT+THfDU8
5VZ/R0zwB3zDHCpsyZEpqXWE0yYv+rg2rZlkeRkj+9NX7i5+YbIJraFA3Xvy6p9ZaqCOlcfayjfM
D6z4WkJBmV4kUfdhUY/qPUZGe3YxKKl0MRaVG9S/cuyNiUL5p96dwipvoq5rYwGgjwW0JY97MPVZ
TmnSPea/uTBFVh4VeEqG9EfYi2UPxaIgyKtLBy4qENTBrXz+cm7VpORkIbAC9FvnkOZYjT1v2H6/
qQNi6Was0AFsHN0SLZ+ubfToHRYxGM+J9LjNBBJkHgASBdg3/Q0LEf0u3EEn68efDxHD/xMMSH+M
bPup0pCh6ZN5mj/jV3WCqMXDiGU36aomi0deW1Je66DEeVEXN9i7u3OGtfzT0qVnZVXIPOXMrSxT
GFGS+4ldwOIPh8O6wo5M9umWGm2bpkWiDUGSjvusGa17FNb0LklOBGGI88Nk9s+XnO41f+GC9zgq
YSnNfnom2yw59UFqETRwHcXodDzYhcnwvcdEhvVXW9SSEn2CA6if8Qv8m3lfO2IDG6gYqMjv1zEQ
5GC8RCi0zfT/wUjx0WONy32jsmfHiWIaZT2iG7xl3W/kMjBarqGTXaeBq/pOl9HHHEyECfRnuw9p
QeSiyT5gbp3deXAM1ZcsxxDtBvcApvX1TPWUoHjC9s1EAF18DjRrfAb081eeBYo+/rc33Pzl3Mq7
9RPWLHnP7Xz1skRBYDh2EBKAmkD+MJuV4ByY+7xcPDpuMGXgYFFtbzEx7QAmOlXqvcd9+xMerr+o
z4BtdDDeLh13K28VXU24qUygbjMzq9y8GYr7WgcEGR+umd5CQe9/hXToTZa+nXxQT322N4rz6Nva
Ni2W7s/JIruVG0f2agrpiIj0lGquZJd/68eMOKunRcr8/P8tmjwxOpOnNr9QilqUzxEi1lIokd4b
IualQVM38ponmiz934Czgrhw65Ob7QAsnEK23OvS9owG28Djc1iZfcPsqAOoV4R87y8c815ngGZ8
Y0K9iuYm/ctnCXQz/4vbvCSL39tFZpqpzHEEJNs+d4UpEs662TaeQM6ce2qZclOpvbUfhACuqmrh
WDJ4mIha8QMDc3uulN13edzxN7DJSBW76vBoIv8lrB2426Tle74TQZbRKFQDWzD2SDAEGpBeYL7q
dGB1wF8f3Dwynsn0v7RZuGRIQdb9DQjopJ8hKWF8gmDdG+rpRtKGD0lFenwWTaTtcdtqETSR3rj4
JVnr7uMHP94bUpfHRNSy5aexTfqzPqfQa5ekJ5Kge0dvr+jjf8DwiAHOtmG7hOKReYnTEBnoDXmv
nFrgWOdmwQ0Ua0rk3nxJ6A+d0HxL4tB76nDCG0DxoGR9moLsH1JswxaK/N01LmxnvBbdD6heuHGF
9Ebb3h2DqQfJ0meaku+3toDBdObN33j0WlsEfXTnO/BLWpA+yrGluSeBwtCcmpYvOsX+XvSjioHh
W3tYUYRr0U7zPhDIWUbLfABk/yVpzM/b5dLeV/P+CScVOUy7gtAWxW+h1STbZdCoyMih9eVW2uSG
ZNXGGMwI5Liwko8js7Jq6XaKZyPALrJYWWFGd50rMNhSq86hqxmpU4XebiWIbAPTvuTuvg/59gMU
hQNpZvqW4AqHtFe3BB3OCzGTSswekeBg4Y2FmkiiY+R0MW1dT383Msb1fyf3byhjr+Q2dgeXY9I3
eVl8nx2IFTbD8M51u/egzgZsLbO70967BTnHF1Y/ipjs95NsON+XKgX9L5jrhgi/z1psa8IVZdwP
KwCacSc71pvCkKggNDFIMJ96TCB+11BTf237fA3MkQoZCzqqiGwq9rjNoQ/7jLwH/Dlu674O1V33
6aIPlqLgC7/y2TAEJ3OgWk1g5ljMaRBqouL4aMW+73UVvta3URrj0wKpnUcfieakLhXkzu+H3HMl
lRHVx+dNRnU233DZPaj1hcrJzU2LJOaETCbNogiMa9vkiFCLEvjps8wdX5ZKQIkUqTu1+oCDPZiJ
1lhRNA8Oyzw/7e0Ds4Ge/RDzsSMDh3JJbGrn1NfJXUYSYfBukMhC5ARYh+VIN4z0E+LeYDZ+a2Nc
6c6X7SdIsiOfGGMT8gCJ1vyK+HgJGFhfQY35Km9qfzZIUz728Pfm1sCk4bYg90CfuNUQGZTS1Msz
7FvPpO3/vxDuNY1Mi3uAL2K176SXEOlDuuQJifZ4SsPXlJQvChKBiFoybMYFwE1ixNg0OH3HAkx1
u2JBVh5pEzKXZGTNHWvL19lIpGIR0jSJ5I3+NCeLU1u2VwozzQAq93jFoFfHfHx86ROLZQsz2pNG
qbru/bzn7YJ+Vb9CaeVzIN2jI44ghQhe6IB/3NCesgvheIUoxTlRlVhDOSDkmYSItBNUSWekk88t
cDSXM2fu1A55/CBZ8j1bXi8B4l5ERCSzFgBh6zDkH+oUy2f+PSmKYso6yYSsibA6MsuP5hkcaK3x
mpxuENiv8CDqtP0MgjkjDPtaLuPIy6i9d8j8C1TrOTHp+o2FGa0BDti6vEgWXQ57mdGOLYPqrhxa
FW8bxoJtojhAAyoj92RwtUl2Zi+KhbDHoFLmQnxkO9yyXojwzaGjE6y1mIhmJSO+DRRWL26QdZph
dxe5cyHX8ldhqhYrstA66zGZsRLOsqAvvGnV8ZPuXIvbIkzcj370DGmIN7Ylv2+vsCUKIBgNv4qM
XBGLZeytOm6+eBvrpoA4lKVrF8Uwq3HfZe9mrrXephNWe+AUdqQjvH2+bpZO8HJWKRcUiENdjElB
l5JRkbJQCk0ev/SP0+epZaT5kunQGPmxyMKL9iVhhN1iN0KYIE4G/4psYoUwMIRbOMLKdDZtxteQ
D+iuTDjTUPF4SOWdAz+hhEX+DIRK9tCnoMCuVr6S5Tvt923DeZnZ39FPMEXH/gu5kMBKHLQyf2E5
uytN8EysOR8c+n5kkjWa3+E9dHy0+8ly7dK+fTElF3cg2uPsxZCDwPn01TE/84QH1TfguBBpTVGf
4HvG9LwZ+IkX8H2bRXuis1DlVSdcPLBrrieezWhP2pVjUHfWDvXuG85C+kBMTf26hQIoYovQHiTI
NlR+3Qz6wrxZgfGZyfh2Z9Z1Btglufu1RE75snVpF6m9+fFebMjmt/MqJ2jugOFUN7/hc7/AkSLw
OjeTBCQRfxG12HbV2abA70T3j5L18j4EOlEeqpG9EifuSOiwAcdRHbVBqkT2QRC8tnREwKiL8eQ/
YUzJrWiM+S7DAUknG5SouOkTplyxwxLrdjzH21Ir8Y0M6JqdxoVkHW8MP/A0kylChE7nun4SUSyQ
bwPaLqkrn0Sq8xaHPAMlaCKoub2BmnxOO98v0irLrpipq+P5WzOEs61oP3OeZjQ+E5KFTWoNN3MB
fywS7i689IjwU7W42umCufu4p5Y78Y8V0/DuGAXwjzEm/fD7VrsB8sjqfOFQjrlJHFkEUVlv+zXI
eNAfAie1zhVxGYls4t8/s+YaxpB3Jx/lb5cQ4mjlpy8eDFJSeyvankBlZHQ2QYOt5yWyC6nKdKl6
mKIp+jndHT+wwGP6WM95ggAIA8vtBuYAQhGCX0GeYXKVZFSlvhl7Gg/+c2eoAir9tA8fhMvoTtZg
VwEEaz3RqZKoWVs73m1dAi/MzWDCeiW5NJTata3kF6Ln+h4v0zSynH+n+Q5p+KLn3iB2re16UAO2
BLagA3smBuoYF4vAKp5UpsUg6QM8ZnsHJuR2LMJPACpk17Wzfq+2MgWUI+85g9ZneOhB9lt7I2ph
7k3UC0DMyt1pFIj+xic2iiR41Z+D93frEj0hH2SvtPO0WdkxDtM0lywrzEuujusPo+oIN/tJIoi5
9guvFn3Rdls4TL3LsS+2abXDRNxo14pZRQaYIGHumwJoWpPeCDJYLIgX66ZbtfO/WRXGdYbIksOR
o1tweLQdSjwXjY6evpUVfrw5izykZHJRB1qIBbouFh9JdU+zI1iN47TK6u9uAuhrGD4H7ZdZtLLP
QGDgPAcQc7uDOI8A1vdLGVwt5IO0QrXKIiZb/y7R3Ujg1qqT32FKGv1sHMm9v8Fqh8w+kfSnVjJ9
/ws9ctYz4WBpSBvHAygl3B5pGygft71jT0GRHm/v+J8IuzVt6CigcN2/9tG+I1oTn1ZdaHUM6GGf
gsILd4Re2kYUGss2gTiM2JuCXCbGvKS9rfPU05y1sqWGFBTaYQYtuPRrCGQtkzkemTsNvbTEf0IV
sOKxwhwU+yNCLxeFFPdOeJpctqtJ5DMOuNtV89/KFnidANHisJUFWS/AalDnKMa7JXogCwZgCwaP
SwvGlsQqgOnvuj8mx2bF4Hqw+Xq7jNIHikkvF9RFtFw+2426zQYmXXdwM/A1YO81EraTSU11KR8F
i+xdPFbWOFroIwwR/9r7dqmjHSpI5O5a3ctFlstmfxS5l/OVsBpkcHaUnFIhRkSKxHO9Pjd0r74y
GwImykK4+YzvYqfOZstSSL2EZmZm4wYAhtMo1BcbycHoK0Bx5+t/Erij2lMiq46NQOFh24Mt+UHX
+bP3e1vOdpkxHxbcZVFrGlsV+o7FUDNHtvPepS/HTbhVPrzbX4hfXCXH0CbEV+ZzkCFoeFXxAHGF
0TIa+Vs8QcsEmupm8RakGmuUJ5KxkNobdHJE4tTvy4t8Z89z8qmWJMXSOc2+Q+AHOR1aecmDY+8o
x5edV1ZFe5GaPL1j+CgU4iH+wjNoouR49JCqeHL8KjSv7JQDSDnHcaMqXS2fBMqgAt9qbhlXWK88
7d1f11ZTEPaLHltr97ED59ZBbfDj+1SPzHBWvBFhlDe7AXMzaFX66UWM3GfgTHjEElYkoC+7lE3M
ZKcQvcHooP/nVockpUDFHNF6c9kU+m4UXWbXJrLDzn+cg9OFYPnDmwubLUYl8IzFCC+TFg6ppbKz
dXsZm68SOv2qnk7k25/UsZ5ctL6arEWEajmjXBr9EBSljEE0uhkJ2rVgXOxLbDUhbSoSdgUmMeS7
ikuy3FVanW1/ISsUcuLqdVZgTuOxcQmokuIlvTvdM7smBHefLKiOzKleTR2dMXWP9pRlpRhxcs5i
2l8z7RFCOqoKiR7yxlfIgjJUhNMp1pA5jRbnt+J9mJW8nK7A7pTTtz7TFthyu3VzrJEr58G37Odm
6IRsptuZSVZKN4OlPoOJiuOUFElLfRT4Gtkl2Z1VTtJcR47te8SYVNZsYMNPBmtoxgI+Gzg6HTwb
VdTRgE03fhVWP+HO/4zEDbU6eofgtIPzQWY23ievTzgvPb3ipKYlcGIanXi6Jr17HGvsT/w28OpK
FvdjSfZe+xU6gnRGx5qzj7cRRe1qRD2u897VbXDItSvzlB9FBBJU8yYJLJEoLnkPaYX8DD6Rk9rE
g8KuwSpmLzB3SDt+EBGNQvwL4aYJeYnxztUSCxumSGiEilPoE+/agal1IL8CxLXib6B/l73qv9gE
Xq2ArO/nwfJC7lcSCxjNnyOsBZn4bXR18IfVCKi/Txe1nKPTdXTCYlO/mwGvDLgiXxS3HVCEVXPC
fSUXVRHBQQ9KSlQY9B2c0lHv/JBf7n1HQBiMsmfi6uksJpXK20eaeu9CXa8SSAeWYFlr8DZQvc+A
GtVAzKiVHvDIp4bFiRevkdxpI6KGdax2p+Kt4zi5hObu6uOMsv0sTJCIGU4ehgWCQXqY3TY4TgXc
uyhirKhq+am/CWVEI31q4tMkajlLGdMkqOWZVjGJFKHOJoUWAm6xGujU+zUau7WsiPY34EqsAeFe
rj3R3r6icOxKQve86YU6UUBks3smZFn+UnCk4GYWh10AP7XuLL4H+MmDJ0BNNBorQrza0Juiq2vq
78zhHKvtU4x1QLNvuVPGrJA2oQbwVHO2+EV4Hsq0luC7yeB0caEIZfuKy9gVSG3k3kxI0sn2G1Lr
ujVIrwq+GzreqYWkYlQvASKCJfqA1jSskB8Lo1zwDc/95EHHRLF2eH8m/Uca/+BC/hdaDvMBUjd8
5/DglAZEzJKnEFgffFWA3ZCe2+iEStYdSdcO1lU3bmbxofBnU0z2kto8JFATUIgTR9i+NgoIalls
ysQSEv8BRjgYYJMjeZkyL5uXzR5Lq72f/jg8J4doOcYv4irUxSiAXEbSf+7CnnVitwKE7B2A2cKF
VtEMxDvrJC1ZcDjebmnbI+d58+n/PNlvEhovizjbLiBmCAhZEkDpbyjt7mxIkTHLu+Qk0kLXnVad
96yQOR/ae2RQZn5EK12gAXDj5pxZ8wo5EYjJzFQjnvoCy+cQfrFGQwB6sbjXfzitKMJM1JmXvI0s
EvuwBve/lS9rigcg9oA0GH8qMNNeF/UzzKOiGYkhHNfXTJieVD3CJBZ1s89PJc3CHEuHgctY4xVN
y5XiMVoAw24FVuGCGto3xsX2Ap1sVImeHtfCIgHWr1CP2n6RrKP1ChBBmc3RPgOll8vL4Abz9QeS
12n+Yn01uSVd2PD3LorWvH+n35OpDlUrA1W9yTsLc9GmAkbRgLO60AZvAggVzTfu3KtbCYQMiCEF
64RnWRw7O2RLi+AwTv6diCwTvlgaf9Qi387CMCcSvyrXd+CfG4qjIbK2MvnK/meexWEa+D6l6iCt
JGuiL9bga2zrlJGNZpOv25rcxscO5h6v4tGAUAeLWPZ02W4Y/uXuLtZDbLZvK9HQb0uonUiAJmAx
hQuo8W1tzWWNABIYi1ls9GU6dgryWhv9yYnQgmRzNNzMilMciTsbAYFYeUejNHR9+ARRHrijvkdZ
uFb00uNTRuis56lcrScpHeJxaJsj53B7WTRwm1wNcsABAOgbRPHgEXwgdsKeJsrv5PvPclWhXz9L
XxSwD1N9K7OJzdkApd61GG4n/5gKSFoyx2h+5eicfNMEOjLEtj/96af6+YtbZG52JxRM2K8fxHC7
5tN08k6qFXKKvnCd9FXLSNQ06V7bMivJI6t/t5f4hKHp1gvJepYLtls7rGaGt7CddoFwj5HjPBYy
L8H9Td2gvkDR65c5r3U+n3oj2eheM3oguwydpbDM4ltzHeOVYiRe6hFnkEPQAMAxc+CYl5jkeTYg
hHwglL3e6+oPut4Q2/WvSiji63w6Qifn5z7RBlO4pVfiJA96BmQqUCo7pXFLISPpplwvUY2xQ/zr
8vR8QzunETalHS2Kr5uREDGU9YJX813Ngv+LfoCTXOVI2hsZQ4EGUT40M19YR+ZZgRbiNm/A1PXT
k8VS2+ziAOOo3tiA8s41KeRTYLU3QiYDSwFi+Co378BxULx4rCVmo+o8GmzhLfhDwSx1+EIiTMHD
fTygQMUgzxF0yzw2e20CgNQtkjtJhVB5daFS19LEYqlNJ2uuGPb/fOl60BE0FBwaLKlML0DUkDmN
fqyLvt/GuqVHUlbIjr68yyrMMsOs1T8attdrNcBp9GhYXsJU6m0+DoflEdANv+SCOttQ7ms9pRt8
Vq8m2mDXeocUyowHqo6l8SWmcg+SzF/VmXuIv1FEQ54nj/YNc9BDz3wxEbNruLqeEENrxivN+Fv6
v6Xs8+SGK+CAM02PF0Ed2dy5BIZzWA9GwbEcOzCnfVubwmZBxFGJ2s4+UKI5rsJchq885+7wuXBZ
7yjqQGyj4Xy0ZOkjnM9wbFNvXiRxGy23d5Z8S5b3QNOkNpARwXn26AGhR0CQNzhb7hsKVOnVuVQt
EtH2wbFcQlQ8zwQMbJKF83+luOihvW3d6oXe0LLbM12IZJU97Xif75DcEOo7JxTkkrcZ1Egb1fMb
ilGMAlxUJWGD2ldqEJOKRXiK25QrePoS2zt7EAIt1Vcry0HMywow7yG/cy6MQNvEWF25+OotKQQE
NQdGE0v+ApxIYNPBz+etAtZiC7RlibQtqhYkHS8gXlOVNokednb3uaeLXv5I4qr4zDFBDQFNP1Nc
P2vXxDFCSORLgOHyOe3CfjxwMhuN4AUxdOz4Km+zUot2VISa6CuOqeLQjKM7Oi+XMInXXm7/Df92
K8f0Y62yrDyow4seOrcAFTO8r6YWYLFhd9bVe4onEry4Yce1uz94V/uBdZ0A9PeLYaYU9UCFin7c
SAla4rSs1J/rYaB9lkxWRgQQzSictFe6IKdb/AyVesCOkC2h+MjfcBcesID8macvh1tlm0cAkPIQ
2h5ZIqr0+VQYgOq++xWD7/hwTiwsnwcFReoGXwtOqUZAmeDqhSLxN9PA09jg9pq2t6p+XjmyiTls
jej0xluP7C7nQbXYVniCuDIKzb8eZ38VNFta19nXQqyNX+3tTsvtyzGoDHsCbG3ngE9/RgKOLtG0
JF28bS10tcHQdsUlykdzdyujfWpZ7dRLlujhKuNuJXKauruY5NZ3Po3Ivge8BCNC339ae5pluHBB
UHgLqHmGNAAUpwsEDFy6bo8N0remiBgKHaYN9V2LVpWZMHR/wMMWHzvaAwvYuxCE3VjjZ2tfDk97
MTXu0DGvYHxm1Xqll3NnWQUTagfcLGFCV2PSOro8WyCu3Sut03bN7QOnm+Ye/3gJ1b5Pco/MMj2u
ovQGMaigYaDlGAwXukGMs5MndaIH2QMGUNHiZDtpvY4zuOXE0gDTNKsW1/fGHyjO60Qw6Sp2MKKX
ZwA00IOF7rHg61cPK6Rz5NdygUgIWF2PlRsYrdtzPhseETsVkVqsoB/ISjWdh1mDoSeE1YSCifI0
YSSbpiIsBEFhi35/LCWshU9pDVmnVnSzGpk7n71RdVSdWQx1T+zHZ5XglQMolDU5s46osxvQRPn+
o3Zuqgz7t8RVJCZIjMmGydZ7/vxCGpW2Lpsgtlrfd9t/HBn4GHIlSlfbg0RIK0BEGjUvfb3Ww2uz
mDYtqN0b60uL5yFpwsqGFJEV6NKuCJP75/ET8av4oihXzwRGZ1gCHh2W1LLZJjV6/qq9NFyKN92A
WnOLNWgMNxdoxiSse6u0hyYhvXeFaIVt6xeFQfVsHXirABJ3KFoM0bclh6weF1/Q2iBnzUEIzkmu
10b5zgVM96/nwnKyugiGcKCw0VEJm5AAsVOs9nHHl5ub5v/Md36ISxwkW7nuTsEpPj8nlF5d+Qi+
1J4m2qRAUIKBbOZV7aHxa6L3r1fbuHke/+hNSbVoNTdQ+TuKsNklmaT+ZF02msG/j8GMORFn+5+m
y3JYywFCa21RK0me64X9de8B2/7z5puKts8D6MsoIM8zewXFsffaYrf+2BXht8FkVkSIZ3TChPsP
X5XfGP2BkPxgwTW7qr6eb4kWNaBl0pCT8hV3FCdi/YKYJOTxI966me24CsNJTeAlFB5K69FWUwJ1
ongJ2gZ5ZWz8NczYpJPo8HMZyPsk9+SGT6F4wRwhNXzQzXfwY1uOWPvD6tVgrGowyZeVdqcQCJE2
ahoYk+HGsj1FASkfB9dPIJuJIEx7YIoBO/LmpYp0lFpkTXSWi1xIdsocLWvKK42eGC+57yiwhnC1
fIx+nxAMUxcLslQ9JlLGlwQQbVHlwXJ+b4jUenkz8Jq0xpT/kF7FkTX7QDKTJb9T57HvDzvVVHUJ
uVA0AVBfp9MZl87Iupm1Drjtc5o99sjMk/DWWAzhdgabA4OIB3EZGQ8Bcf9t42VGLwhQl5/MU4rs
92ohP9l6tIKv1TFqsjL+klHZ9otq/6ckCdCc/CDFgg8Ie3aS8B0tNrvgDgAU3SHcoZF0k5coXrYM
OTD2FHvgVrwNZZI0T5fIKxZ6Nt+TdRAjKnbP8WguJFBT9YHqBWvP/4ZxXrG7SJz/PaCmMjyFHUGT
/WSEiVmq70ZraWxa7GGaNP1bX57aZB6ZMcgxVTntx6wvlMpLXFS80c24kctKUkszeLvjD8YIGkS9
XE4Z4/9u6XOj3HZIuZJ2EhRBl3QIiD16nkiubkzxvpFfBtxLjotfxCjy7pcp/33SbueNezTF2Q/n
gDL6X5fIyexc4a2XkoXU/WPdFUy3jH9zcQiE/gIjblT0dE7l1/1WUoq6Cna4XUyXzXw78TrQKcru
uixaM0AnWv9weQd2EZzMqtAYvu0UU9UbWeXJ/W78ny4zSy8p/eFhjReNm7hBfCit+quxFsrIk8q8
y7xC2aHrGB9HNHHgcRAO2yaBwFaxwzvjVBmmwGmISivCcBU14sR27sleJUTqRSHiXV7hy4HXdBuW
eKBrXoM6pKvj5ibT3BGqTJcZrKZwCjn9Qrc+ETVnLPA89HCdj07k2nvbCk1eBPLrR/PpFvgBzGxt
xt5vWaq1MAZiTUYaFOQsgw/TceeW1sLkkVsWJpguD7LVxFFL5ie6qLRVx/Vxoe7OQeWToPhjRxrk
t9Tzof5MKpsh7YQ1d1xSmbh06MmHAvteQNw1wgxRAcQIjMX53wWpV5lYGuLNGri9pNmD6KG8Zhhd
t28bwSi+KCcbFHJXKUl/5SyUFr/b12EkgsdRRGxZbiu9ZUxTjFgZw67UOZvpniaoBypL8wEgIbEX
NTxiz42hmRW5ZFs1Y0GMZF9cb8H+srrN6J7UOYOs9rDgjsj18E858f5wYtdo5eajKwViEiq+w/sl
EaoDiStzL7VKfwTBviZdOCbLklG10lEHlQlDKr/QNrrCRANRS+8C3+GqTkMIWUN2BCI8sZS4trX/
Y+dt4Cf8QX5bH2KXY0+KLCER6Qq1LF+TunKsNM3+YjrPjmyzXr+C5UNzD5WJYD8EkuLUFeS1zgzd
ndGYaVoB6LOhF8t2ngCc/QkUMV2FvcPcmhMlVoyFKrhzTy+Y3WLT0Xc+cTDokttYHTkAjtyH3tTI
jREAleUxTfOBscsiTKXBM4A9HebKgfFGEaGNfa0BUJ4u+0cyK2W4UH6d7PP+PB8zlqYOC89YKAMn
TJUemMV2r3t756E3M31I3nlljTX6NyUf7L/iY6ueUme4zDsE7ouFfao4iSaxhIBwvu+wof4Af7hZ
MsAKeE6mCnFx9eJ7EVoEkE9a6qizT/N/mzweyvJwEbRc5pAdyRu6H+OSnWiMX3XXSq+wtVsDhF4U
3vWhNHVT5azFniOwK1kJp1GVjFwtMJ/pdmlGUwDegk4gdigiHS3syKPHvmLWZMQfG9ubDOZXcOYE
hUAZIY0W1jhSejR59+ZTO02QsDTDlN/lZOdL02WhCD5qiBv7kmnA3rLdJOrHNu324FL/8CpD8W7h
Jlv5vb/+Au4S28aCzHPwO360f0+2nYHC8rvIO8qRaKt1qC29UyeAxlYOfFiUnzlfCGQuUXxrP8Dr
bw9q9RZVnTZmd9mFR2sfuFjr/8XOODpQKZJBwf6Fsz1Sj90U/nq2cG9vWMrPW/wOrgHTNVCBdePc
98dYDhawSHwoRkOMHoJ9eAVNjAcfnEaumn3qc17wH6Frs9KyPpZeOK780wqBC7FdNTt1MqIOSuWe
oMzMdhk7EuoLJtLxKtTGhZ6VThyH3ueOw3K26he3bwj9rpt+JVUJuE5eV+CS267snHWwzLvQ8GUB
b/ucKZI9ebUiEq9bm4phqXrJ4D9gQrSIax6NE+J9+tNypTDOXFKUcxaMwZi9FGVnYMpJsNxKi8GE
5CoFxjy4dZxkIvBbn5jvZZ86t47wFO8kELoXQmHM3kn9jtxNeAtAUV+cJQ3Uyqm4giQghkl5LW7q
PWoTM7cvZSYvovhwouGFdNwUvMOZIoQYH9Cw+BznKep1JaiwYImAM8rHSAHz06Qc+IUGazYyusco
bvR57ORq4exwJyBOZVrBBs1EWS7pj/2KJVt4GOF4ceq7dwTegKVP8OZeP5VrsPpL6aTksPIgRP0Y
ksAMMKhiI5NxPnTiiqYtJUN01XthjRksAFmG2bWuN85S37Fn1PER87ooK1E8ucUmYKm8Hsl9lQWH
FTCaHKGcnmxceM7aC0mrVNb2Ib8E6sJxvWx3Yp4AYM6bg/v6qKWvqrlTntyF7qw+swkjKZ+L5o4k
r1wXn2fGMYJEwACkOcOR8MPK3HqcZwblTkdN3EbR2WAjxT6JOYQ5MuyidlW9744W3BEt7a4sOm/8
WeoBNcxxtqTaNqE62F5F6POn6NftcVghA7CGA7pKCYbMXnYOvmjszZGWerrC58tgDw+MoYI3Bd9o
xWTNM0nNSoa33dEIh51PlbRyM7l52KlTb+kAO8Gn5QUdO0bLctalbDEHKGRBokF2WVjmouZU0G+P
o9L1/imyF7rJf5bUtagIy6YewE/gimzOW0baj3WuXyu5V94YBfT7wncQvJi7UYk5eqav3UlqGRV1
LnBv/y/W3LZUttTbrRp0zxhp4w0JqNEoxvhkI8b7/fM5plDC2HAR8jKIVJZyToJgEqumV5+KgfEY
H5+jP5j3WNqrbuEqP2bJKj6Tv8qvsk4h5HBV99TIYYXsDgohFeon4l2rGSrfA/d7XsEhHUkuc9pS
SWmX8UYFGfaCkeVHRrAwQKLM02StCj4NxeMUsdngg5no7vBJNZPjNF4lJMBHSe9yNqWU/QjT9WGL
r9hJC/QGy+MZUI36nXnUaF8I+xESjNAtngi+4+zw1qNFN5tEVwOgPZTeQKeaII8bFuy5ezGYlqxU
g41m+PD2t4cswLHvsljAa32zi2FBtQuVtN7sISUnbbJRWbW4ZbjCddSEf3TDTLFfNmmCsWy8WsR8
0qP+I19R3mSnCrauR5aKvp5i13dTSalR42Hhzyzz4DkK2/5zy6CQb1mk2eHpIFM6aD73qLYwD8py
MwrcUajdrqF3EAN7Z0BM/31yg/0kyZ9r51J3YlMFKh+t1WxyUGHLaXPYftd1wD5VdafBY3To+qH7
Wsc78UxhP7yq2n8x7yij0Bw2EokL0e2zUNleryp+ttfrqeRZ56KxMGqlOh8xGZlyX3umcvvppce9
OWZZM0eVYYKD4jUFb7WrLbETYbjlFOGVvgsyXWUy3Xg8bKlaB9eFwDWieZOe6OSqOzuNRUwgXZ3H
HJapeIAtS5pKl/7k6p8Xgzh/FDsYlDL2N/wLH1RuHCsk/37e6v0gaGPQIwFva/G9pEhwWqaeDBzC
sPhWQuXgCW61k6Xbl8Hbi2C0C04b6UF/5+rsnz6I5RkpqOXotMgG5KeXzixic9FqCtGrmmpRhmXD
nmo91CS9LgzXAwkAReECiVp6XUO7pNBrE5mCyZerWOBECVIpVFo6bw5PTsAKxNIrwqw8fKmNbdKt
2aDqG1AhKvtOncq6V009fchphtR04Ti09kfrzpXiSQOv01qAZup+v+Cg15QW5zFLOOYE13JL0nnz
7s/8AWXsQQ3mLa0KpUcan8E2hP7UmY7TBCLDwBjLyvZW4hOfKjXQsZz/Ud2xOjQA4YKPrKYxZt35
To/T3D0gb7vKC131PBvv4ND8uvCji2PxlMUMEm1DWVbpi3Bx2msW+LEL4ZJ+mkh7hlSUSxf/u30W
MeXK/iA1//PBjMokzcxZy0mKynZ4vNc8BQya9cT9pdEpxqGJimzAVzNLthMNiUW/kX1CQZod92kH
EawQA70iUVrPb0OQjD3i6sL4n8u78jNW95KCLg8/ELJlfv86+eDmZnONW2uydkj0z+UToidPAXMv
7Z6E1bLDUXsUvEJzyH2mn/JviCR5BMbtbWxkfQBtFjJF8r5DN3YLN3B+Q2RlzJVka5alvIJ5DC4r
RGm097t1ZZPXIRuj9u++URdqp1jFzRNz2ldlmC0GUZeQglOO6x8M/OLzq87Q6gvnl6dTAK2D7iU+
TVjGDH5fakOP3h94crnP0ZNFkTuS3QqVWd5N9Xg161SAjTYfC8sIjgLc4baABjQ6xzXDFGBrG4Oe
oVRjIOu8Y5N5S2huYA5xSBn+vERPEu405PWZO9qVGtBWsW/+yc0nQJ+8EKJ9kn/U75h1sEMH2INK
OXHNNSCdPDj4Tg6Y6cP19XbcsKh1ZUw4mNaH7nvdpIWOVi/hdk3DuwVPNkD7JwK5ImzfLIVzvgMK
6BoEsUdg0drAzSpmwIUHL+cWqQDZ0+e825GIxbWod07DBNTrX2MngVCcjlTvTD/8cEoDEzyVYApI
v821whlSZjGlh9a7HoSUClB7pnCm9evagYcZLb5fPKi8njUxowpWegAZzD1yvyrf1JHb0FP7ImIz
0RNULLOlIS6X5xuWFMmcZWmaUJ0Gx/sDzSzNzB0p+61XGQLueKEXmQkdwTcmaFLXgaK6e9bbqoBR
xgEk9F2ujkbWc5nid1SRsyur/esfPRTuV+/LMJcYm20X161/SvW0Lev793J6SOJ2LJHuPTogHXMq
VCfYJYbF9ekcroYJoQyvMG8RPL79zqeLUbpqtUBbGF2DlRieYKnO//FfwMKCq6uZ47D/Nyqolimm
iyMVd1TMNzjle1vadHeuwGUefSdW7S3NN4ktL3nEleHkoP8TykAfy2ffNs5iQwWlQv2Z/xa6sXgl
+FZH7BeBXv2mMoHnr9Exbfsdk+EleNBELWoqx1SnLA80KKvcYiGY/yap9V8Uw40aPHyA4PkguhJG
JJJQ49RrulUohj8AnVJNwiVSRx21aArbP6fRZfZkKJudWcm3W48tcl6Xnv91iPD8GHpPoTyKmo0q
Xff+BJ+TCathYdGDO8sj1AE4+94q0QV8h3U3h6T/saDFdPiLy4HSc5EK4coT/mSSAOz2WuuH6phL
JQ4rGyLjT4X5kgQDxeg947HPe39kggu/O61yKzCr5KnRnn8JQ8sPpq6WcO6roR2xOKN1Cr4IS2qN
DdmEBDxt/y9PNcFyjwBXREcjG7OtPRUC8u/khzjOgxur62ayIO0VPrezXyl9OazlXH9CORh1UQp1
n7t6JtbUoal3mM5EeS6J1Cl1ThV8bUim232SvpuhZ8ozLv/4SlOkNn5JkoEqVkcw8LiI/xF2b8X9
8kVGkz3R+naxReX1LWFFUcsDlZLZrC1L6Uye5D2ugJMuRix7oFg3MvSPTM3dslM3uwu+Mn0+wOIE
ldZQ2n9Dqhv8LD47yUqzMb48z6bEAVdeN1pHNPiHZ77kxf8dvC3mmNxk32MEMjDcICdma9COGzjx
mC4A2Pek04/TXIzehXBBgrHhgtirSbaBuMwb+BX/Z0loK9SZ6rzRA9cEvgeJxDLtWuhNCE/wiQA4
TW+AsLZfW/ADk0Jd6lMQRQh2kc9prWDTYyyYdV6fDMQFiQSVaKARieH1U7H4JHnfAv97hoIXf/tY
P0L6Hem+Mjj81sqTMfdDbCw7oEXouFFW87sh1PDhhi84813zlAsAoZckRL0HIv1Yc99+D4nAZE+M
U8nNbFvantrThPAZfhb+nO1Zi7OrcCiZtW/M4++2cw9f/Oe3oDBAqy5DKhCDQO9TGjwO0Ed49RIp
BvELPB/Fwf+iQnYYu5vuKgY45SNDYP0vpkwhfWFkHAhg56DARyZ9poXqAGXGY9jHu5PdTHQYGqph
bqmLswKLQXQFv8TkhhIDOHR3GllcxMfKjlixzPLd6H++Cj9+FRdzk9BVPiPqLGBdF2M3xN3FbCA6
+2t0QRJQiEDdAvnXN7EF9XIdK7AGi+wVapsZKBVJ5EaZBC+/LgtV6Mm6+fjJgoJNFeHzH3Uh3PTr
FZWqtBjZBr+E1dnIqxqK/kdYtRlvETPvmHyH2RguuhEx8U9VXs1QZaHPaYuvwVoAZK15CDz5BsBE
PWqTJjn+aW2GOI11P0rGwsmGSijcfgLwrPRryNZCjl/94S/Ik8xamsLsJyNryNdV7gI3Fb3rQFWh
+Jh6c/jgsqnVmCeSPE8WN1hD6eURW8m34L+jU2s+33txcnmw54R2l1TD4lOvEfVoSG/w4MVVX3Mt
4Q5nt61Z/jeBCdZKAWgJXQAzAWfXgc8rNwzp2ACjishQ+5HXnCRzl1hVkiUEAAgW6Si/utxbqG4P
8RWvv/xp7oaCZF+yF/NG4YggxgzUtS7I59xcAUqU55yMD5o0LDDWmdjJjQpH1AqbJ/Pu0brxe4Vt
u4EHbLllwM17b+7UNUZQ+G+MZOSp3fGwCCOnM/M4Y/7Ty+wLUQZ7qzcfEae/bQ1MH+CPZ2lMIbH6
ArebCrLS6sgehcLWcdEMKDl/riA3r8zzkTRl27Rpo7TRmVX53ioZuTKIKmUxV8hNmayfYLdCfFI+
Ro9adIMtLII0ln02ZYh7e1xWpERJzGaXJW9k8lO2VJob8nyzZv0czdcGkbAGa4BXD1opKG1F2kKu
bhL3jiMquZVsa9S+mMU5MCVkHEGyh1U7tg/0+yoGRN95e2F+l4er6e8cLf5drxBFz+BBOyU9ufWB
M9rr15JNEeoxffviZESs+13X3KIgr3TSk+H4PTYC+CBVjPifnV6TFUO0kmBbgJVDeGysosTyLYVG
I55hXD7VPknHjeZ4qMJ104uqaZFP3WM14riC1qTEEEpfrdv//gjIKjDNa06mszOQF21jGrHzjlD9
u4KoBkASkxWmiQ0ViAgW4Z2Dxe5Kd1Ko9zeZgvGn+ZpbAQ50h6zfqimXqhp/7zH9ZLK+L5DtC38t
GibxoMXyk5Rgr3Mu7KWweIMbChmYHCDiV6sPhkg49SIjjgtRf5Ic6CMdnTtdUo1d/b+tCNzGDa9y
l0CakCGprcIKbSa/7XS7t3Khu/5keXn/6p9truf+/TPmI0PkLh45LDd8kKbg1aF5i2pg3hAikWNY
3yGUQ4nxIYyl2C5AQFvteyls2Rs4IMQbcxRSlZ40iIoNXcj+c95wZn2UZNYChABoXJ1pX83bc4aX
RXkY87vdM3j/+uVOfF2Nn3/qaokUxovVCguILQU3S6PrV71YJiezANK9xPiRo5Qxnt7Zf3Wr01J0
OLIYoIKc9PZxRtLhNJijTNfBI6h/ad3Yxurn3FhZcNp1lmd0EH19PGrV0CcZeVN6sNtiZ6DEsHXx
89K9wj8vVlWXV6kBtuwq8SzZupASJHhR4+BWgouyKNk4NoLRZsjOm+VY/e1fAOaB9WtXVOIZI7na
I0QQVxR+cyZEHYvOkeXZA06P2W9fW21NyEcYvA4GEzpH/Pbk3P92Db2GdgZOK/Bu2LiQFIfX84IM
nn5px4NuC1hdIywnrCTRcgchVy1q3dKPB/JMhoLnoKLi473Cv+vsf96LAy1F4ctlJ4EvyBMpU+Ux
fVfH4D1mxzNkxbxP+5MdzYn9LSiNTk/BnTQ//s1F1gkKVObIiN/0/7BwfTNAP/y6JLxMSV6jAcoQ
6LmBuZ24QExhXqt9fkPKeo4x2zTJVvo9UynqYGa0dUS9Zj60MptPhHjwwaHkH8RqRbox/ag3QZiE
yCuG6k6elnVoJ08ZTspF6WWFjA9pz2QvUsN//PRcY1vX4dibXTKvJ8CUqX7+vS/rlFHFlRRTF85u
1Z4dIVtGwlqEk2ECPxndViYqZqYQfAuQw5nm62BEMTgqzMMYT2uzRpGAC1PBr2n1AjZcbRBv00Z7
elh1cOLU9CmJW+QI8KGW1QFOv06zBCIADHDGMyDulh6zWIKHaZzy3TikWYnTVoBMUcDMkpVfnDZd
e3Eu32dWKXyuRE8KBk3ZnPRhrt3/reXW/yWm3rUkuJPYf01DEY+ONbdbnoox2tKRHUh0pJwwKJXy
+CNIAD6ZC/xKDKTxfdfq9HOgTBGpj6GOpWHRNWLhlwwTDbRDeuCXzSz0cc8DuCkGM5i6p7ybSOUx
ihjDuqvB2wnV8eqMsq8TSTdP3SdzkZZf5RQRY11W9ETbK4jb1H6IMnDJPbwFAAAhDMRmjYlOlSxO
DBtlscRk7J1HsFNBBAolQsbl7LYfeT2HpbHLxV+Z36vaWLyZURaPWplKY/mBZ8FCGYb600rskI2A
CzYkn3r1PIswVOmaChKGkW53YsmzPjMHMai+JNXNXriGqiJL6I0PEstDu1/JQSM66Frlwlqt4uvR
kwzz+7J6ZA42y/LhF3Iuzw68LhtqMwBLs3VlOSY2I3oqGNmqr2YcM7F72okW4C5z8mf19wp94416
eOAahIijYC2aKP0cxPfD9GAQglaJB4TJgt4N1A6YbJrpm+AYEDCIbgoXsVp5wzHBlalScbwkZOhB
xFCRfiKqTJaQPGbAsfTQJTwjpYimaaq29frLUjPhC437qeZPKQm1sgGXs4/EVXKpqsCokDQZlM6t
6S3F0D0KrTJy/U00UzJ7f+pwrbCwsZDqDKU2TZ84fl3lT+/I0tfdSYJ+hTd3XQbJMrSlVlrDold7
4gw72L4JHI75pHZ4MP8WJOFuH6vjJxMQfz/BHuGsimP5R3vE0SnoC5eVpvEcZ1plv5vDerkcIMRP
Ae4kj4nlQKxevcbTCYzdPzwJuw9PfEkU6dJgjVRTBvTczQugrGRh9X6xqtfimKmpj7R2LVPg6/4D
ItqTA/d7+SitucQ/384LSDu1qUFUmIN0M+mTFOg9263o8xzzQKYDuljPWIWl9vil4tFvPToskEBn
MVRNL/NBANyOjq5+Tof687ZhUtJKTKmKoIjfNs6Gybf0Vz3LDz8tXBeszPA5X+OHT09bmrxc05af
PYwm9F4lqK3r8SAtVFeFs/sVZGRwbfOPm/zBrotx3N60cH2uaNHYtkM8QsLW8y4TABpPnO9rbMid
ZgEgcsNyWVQbLr2+EpN0fg9MCfwaG/vT3wYoLQAAe0K4RVrfNGUfDSNK5pywbYujktwLPzHMZHOe
+Bpsr20PbxSkUALGeSGLQQwlYWotL8Tp2ekFM8pZT/mv4dFDZYl1p57Dm7eMK72+K8ybBVutkTfe
wYv2MwulpTZTA0nxDNC2e5/JcSiBAH/zr9j57/S2rSpPuP80iryZWo/KsJ5IBkgUlcV0a1+YXe9E
lkHKKEK7YNsIC5JunadAdBtiYIOgDJ2QENJlSf1yBgNVX9z9naEMQoAkliD9EjN18cL24P+Nobj/
lTxgfWnZVkkG0P4/eUZVcG0i5muhRp1fsXMg/jPz9Bn3TYJ44vROfaBcxQ+nzrLznWZukehir1KM
7DCHseN3FEfhXMfiruzD3h5818Jt5WK5K01H8zfhnAQvmb6x7sW09fTl3w3cTRDKco5n27Z0V9ad
CaPhXtVZJYRw67NljqHElG9POYdyQJ4Pmzmbq4ipW+ULELlsRGCi/FzRonYXJuIGf+8rtJLfNRou
4ziAwgJxnuB6Bi8iwkEbN59m8p5/Cpsj1+FkWLI1cspNaHQ/HJ4h4THxLnCt6OpWfOUJk+rfcXN1
Ww4WD/dMYeCM+tgPgdVDh+yQVg6QeQb5U1Ej5nua/MTyGKHMX3MsqYYFrkdQMIsz+xE/ovCQtuoA
KjiUOB+hxEtMo54T8jm/geqxSIn9JMNu1aiaNMueveU0M/WH3PdzOdgV5A7ss2LRJKv/uvl7Womq
rChmuMlfkhymiiOn9sST/X4OTcc0SlPkrcnika4zKO4x+Ft1HLVRdCkK6EElTe6yQ691kA6bQFEO
TEEbwZRwQ//NlIm2obdcwaSQAkjQbiKLxMSbwQ5oqyxL3y2/nOToz4FD3PV0WXkG6AITm6+Cxlmp
0D3q+xJBWNVz1ROOR8k6A1+PLcAXRjLbBTtp8s9+yTR0LeI+QVZxwqXi3sNF396mXi+osrW4Nuqq
L+Jf8q6AHEXyFs1OoAhzSrc220uTYuQDVGelh/VdF1qbSFqz7YyWqdB/VVPC6YIXSreXoCNn1rat
7jA7TLzgDODYLPdVHpdRj6VVA0IrmxGHVyj3yZE+y6K25IUEbksPIcIi7OJJkMudtifIfLpQZRsX
cJvD5Ekzn+LBwTv8B4hP5BevQdLvoirSbN6XLtLvwCDwb1ZstdJDnVMVOS4h3XtVWiNsnPaYUHV+
agANmYFhFco0EKFmjSAJ5KKaIuJkiHcGrqzQz6Pk4aFUg6PbCsQPbUZvQD/o5O6GAUJjQ7Ec9UkK
/7oJScOYWQBPGb/1E9AYXvRHXm89PuW8euBFhRCq+ASNjAQncfdHlc/T4sMZ1JcFB/zl4RjL8QCU
ywto0GXAWI2mg0RwqTIjuAeeOApgbTJoBOWmqOXRB2sH9dOxaptf+bUlJNzwqA+NMox0V2LgjVVR
H/1RrrbN3ShwdRchPd/4E+AlQ2ntLUB27F59oNL9WkG31Zf5x/dD/0u8wgZTW8rKHWyAWKIBzxkZ
xKPWTIBbxtN7W+icX2CG5B9I1WMi4Gr/5cCRT1uqU9ZBgJvYTJldqG1HrKsEV5qVM5kCqRQ89pmV
aaVfnMEbflq03U8mBly+ndj2hLyIvbtx+ESWbF/0sJzO1G82fywD3bdpQm4EVZZoeWh9OT54L7pi
M8HNVnUyDOW6f8DyoegFoZYhTl40+mD+S1SWK3pHf0VAnbpUE8+Kh1yMrphMifI/xBOOcT8AgQ85
XzX5W60XaHQHgmlVPNo72Jxilo1s83nKB/YJrrn3a7sJrcIQN3BLWXktztfVjkAelp2q/jtHs7Gk
UQ3yDevToDmUxfrgvxTuRn2kt0qwzZk7vZGi4bqNZSHWVxgsSCSTZHSden1HBAzRDPWm1kydWO3u
ZChnQt6zG9FOErKK4V28mdppyuX3KB680x5LfRZJSStJhojymf2dB9wa+HRKUNiLBbL3BrDXJkcV
oPGSfTTs0Ga9PpDdTJ5UBkkPYQvR2sKPLJhGL8yUf4g3b0fjmDV0+ggigRnsMoCkGxdigfawWv5K
g9fiL4sDKk2U6RwwxW7aiMmw6qKR+xVe2Fb8EiLqJ7gCpZG+XDzEz2S6r4vKx5eAysNGOJGrqNsm
ekiYl63QI6bcLPPo9vNKEqOdnIlPqhH/w5CnXIhb5XvyqRzHRvVErqZBuhzhGvtPi3bT0i0stzAq
w/KEOpKSYyoN/IuU8ahhF3PqpdemKBsskQUBIMD5AKDafmUwrjqd8tFACmqHnucqIv58jTQf2HIh
KxKnHV1HzBRImTLKghdpc1Tj1p3pcerrZVel+ozMoCaQff4VycfaGDhayTNym3ZlNVPaXkqpp+Z4
qvJQIW7pbiyueUTGj99JH0JBga99O8iUZkNrvgW6tsu2Eg5tSzqS9SGnrqwqTy58ptfaZhpG5dEY
9fe85cK76OtANqLBlbVZFlwQkl87K1Bq+UwRJrFuTDxOYvxo9rDMULH565zse6xx+VCHA/LbjVWZ
eXATx2jdhspriuY/GqsxvIZT2JNBTRerOcuO7RVWoQXpyoB/TsoEKj3i53vU9bolXTZc/Kn+2X5N
7Tp/lQmRYCFIbRmJHVJWT6Xo5uVjUJMsuJXaOBWkx+Hoyi3PfR0s2pn2S4s+eQfL1xQdN+LiU4SJ
ehas4NQQI1jScV0VW8tadd1qKjAyqFRCtr7QOE+n703izCxPMpir//aLgZNUTc6SLjam+ENnybMo
PI++olgxVbQWUauzSqDNfFl6VPRVIvYNDDNKLbgRB0E6CwjTTv49QBFsrRVKJRRDnPhT85rgWEZS
aj7bVEB13GlAI9vqmciH21SnDePjc+lef97OYbjsvhoZ+FkHSQ7QX9srlxAR7kcNj4Dj1N/VTRa8
AARTok+ZTnOtujs6w+unKBuztUCzRojYUpDL1fXFs9ncfaf7Lvav+Fqn26EkWxuAC7/ct4jN0b4x
1UNrpngTyh7FLmPSI6qEad3phnj+TaqHg7pgoae+bwdIeuJFqZ4Bk6ErtSk3hKUe5U2jV/G26qF6
ibLTR/3UZvmr0EA2qAyyIc6oPhJO97H/lPON3/AEx7OhU8iNnhTUEPAOtVv1n4PKIIBPHIdYXI1Q
3QtxI78ojAMdsr8c1+Nte/JhLM1+A+L5WY5ZwrwOMgmFq+On6md+Wvz6CBNPfvlRe62cgtoFqwMD
5bKao9PTUyyrQfnDin891/1lIj1RdycNoAeVCR8Zf4SkpnsouPeV7Q6Ssfkz4j0w9KZyKhaOuDkc
nKv/2AEYhsvz9aOkkXOtN5EeHwcPuyg9UwZPWydtZ9rppxPPlidEDFrireI/G5b5rjSt6NnX86Oa
8qY1+rm//elAy96X0Uej4CFfKooYWshnsV04VBAT5ccN1V2E6oc6sj8q5udQkWaLWMz3tLHiwnh+
y77S00TPLqlIQjMB+H6MxNOK3ULqXJdVdCB3D3ru/zMBncYwuuqcUSm8hxu821OMZ6HYVTbL+iUe
zcT54Acuwr0aYmwuocbJB87sbQhvMZ7ijnBm4acjWWVlXjG8F8MPeGqAyK5uHYHQztyMBVoUB21h
jV8rkwIqh924V/13wMp9ag1QhIWqTLc3izFOSvLZY7xriZvUUAkRvMcfLchVT6n9wEnKj4ASsikH
BiYOrWAHIH+GT1/ScIgN6T/psxN0Q+/PYjHM8WTc99S5APn1sSR4IOek8P5nWWaiZPrgSJXat+5K
Ev3EaIvKezJ6yUfNRk9ewt8lzUBlAlBhLDlk6UtCSM7kSdYehyAGQvPtwrWe9woylAGB1D6zsIVP
qBq2wVNcXjeUMK793dLin0f4hCVBWAiX5OoYSdHTYX0n0CxsyQAjs4yuwdYUZa+PcWZHDo1Uz+Nk
MtF31FIBHCbHDfk6tUHEvMzq9uociTFdtu4822qvG1xFWXfkEPye2zLHLDz76zwgO5MYFNMKlti2
TAM7u9bjOXvsPntnrbJDqfE3RXuy3jQNnNpHeSxHVABXKt7+lkkz/DBB1dQYtH6VpATCBul4jXKN
amu+t324zGLtoOyAQ9BQTqwyXCLkVz54CC/Lzb745mdy0VtCeMFjpn/UtFwKG51VI3bQ7/QbykH2
zpBeqo6UgGpT9OfVjtn2MDTna/5OO412V3wBBpEkBMVGIl5yKl/s2zonZDMVX4CadylpcFjl5eT4
qBNcKi/dlPN+eO5e4jXeLbhIOFWd30sQggEgJIJ5MW0RSilO7CY087dsfcQkrTwIRgnp92PoHkdc
zYaOr1nmVtQ8x8exB6oWxUK2f0wDRmtuzVqZ+/obutao5i15sohKjPyZG8DU8sEGV4umypvMZhKS
BMue97CwQu73THucPv6gQwIflbh+ESEcZPepEu4ppB2H+rPKrC4KRZBhoA9BWT3KUxBXxaG3F2OX
uruuMvg4sn9olJaqxUQjw9Owj5DHcxlr6l9POwJ2qYBwn9/bMGZx5XEfy3UfW4sFk/bMFnQI3gFC
HZQN4H48eAKW8KipjY0sicuPK9I11xyhSal07LRkGRPrsuPkVQOxxEQ9pOpRD7xBukQpCLW9DAo0
kXaGzuEuRcAUiqj8YdovY/4gwhFSYG1L2Y4JXTWebhKgukYw+j/cUIuK14xMkOgF62Bo+XWR4sbq
8HrfvoZdWbPRs07cCSyqMQLeKg/l1L0cPkasQdtSSWJt7y+jkMN65YKFWq9N+HMbDU6O0NsO4wsR
1TcvbKo7k1sqHUj6hW2j/77FaF2bJcO5nedCsUZtHZmXCUXQLHhKmkRcr5YD/cj8OVrJjLFaR3/7
9UsWVWZ37svMvDwsP3mAWwK2XfCuDfCmGFEOyD/dkY2sJY/pbzkesx6X7uw3j5KpKqkiqgrd6C1N
St4ZgLZOw5CFadtEHHGVFwU+wqAZrxEnmGI4fkGSKM3T6PcUJwz1rnld3gBdD/sVCBZRdBcMQVhr
fusir9IaQs9QIh5hlp04HdN6J6Mg0oGPWBB95PCYV2hPXX5+0/xmz/cjFEM/ZAvS/X83BJo9qV2/
i/tvVZPJQD8OMPRCBECJNcZR6gWYOqkQruf/2/XGGNBTBd/QJFKN9NY++Zk1yA3erC1xlZarTCJl
fifhWzOWVK2d5sj4kT6pVon0RuUMPSskZnefosyo/vK9qVD0alerDAOQ4TDKeQ1sS4iN+0wurTUl
xzVt3iird6y4zayCJ4iaREg4U8tvEyyXqO5FMG34zbJEZIfeOXDaSJnpWcgF684zbkiepxY/vj3j
OvI2jaYYzdU5e2aSbBUhq2fuIPrVqU62qpJB1YVKyYdxivX0dnOpLKNG+9YMsxzKfctmrVmrBvbG
DUN1O15Kda9i5+92MjvQjNWiao38i//hm20B69s2QMorCOfxvcvYBhagmW9gPCXvXSGCXgdv0gZg
VdXE5AD0unDwKaP26Fv4o1CNt/2WAtrLY0uKv5r/3G+gsawrEtM63rMUeZiZgUr/eAbh7sZbuZOA
OxMdXBG+FHO7UYPY8Afi2OGSVDBOuH/zL9e8g6810PlJUvLIbS7M6DE0Y0pU/iHhZrm+tWSvAuNz
Z7Xn1q+QnmYhMSjZJcuIjQ6emRNrvuvMiDfTrFMCdrrg6Pvce1PUbr4l29wJs05wunAL6aoyMUIu
XnyTDzwQ+2LZ6bh3ZSU/Ux4LRTfkP+CqC/RdByP51eZdl4qfuR1/1BJZf88XOXFj/eZJt9+wygFW
bkWeCZ2Pty+6dM/QM8Ynva+c8KqIi+UewBDrKSpnf043fdEH3My1mErGbfNKkDTrU8U/ufGjjVaT
upyFmG/WFjh4FJj6sIYJA+JVhjUOQiMkoZmOY5OP9PXAHnUA9N8GCy/mL/wBdwjztW0/Dc0q0gdB
gE5wpvyIxvGZWDzfnw+21+R207BIotny/OhAgizLlwdB1og5nTjClAmPXD3Gq/mMWKKUf2hDkfr2
RYb5eaPnPgce8YY2cO30ztu/E2eyQ4qZtQ4Kb3gR/8QitbN0fTiwN3vEapYhrmyv0MTG4dhONTmA
aAGXZ8JvsYxLHkbHbcIfvTGg1HeliX7x56rx7AOcnjSSTEMttiDALUlJAkhJw/2z1j7ZWNMoIoBK
kFxIeDVIvc/B0IMrjjyDsf5rsOh2p9zgqfR6n5iqtatCTFK6TxddmAe2Z+nlM0xI/aJ11ShF5euQ
tcBUG7tO1iHLFcEkQIS/stP1Dykl6//4aXX4lXK2adtl4NthFOsG1DQ3wESWQCU2InvTfjldNHCC
K6XD6jV4Q++CE487SN55XW5/C32e0E1lyajj1ZTm0fw1SeILdwbfmsO8V+ir9xWA9QrhXMErWG/P
zWszw8claU7fXOCaIX26u1VSZR0VBXujdY2nNlLkzuX9dNle4uFcE13ReYhqAjDLeuNeYF3NNpd2
CONpyQoMH4lBSQ5yprhOeJ+34HaQQU4q7mKdVb+QdZATKwG6sAWeA43kIevnfARm9DdKtDflCuyG
jfYxuUOJ2MPf28eejXxwnBPzIZIxDaSpUwF/vP1RRRaYSEm+j+UHmAC5pHvXbjp/OOavZSH/R8JT
V1DzAZsQbCUiyYeVSaPq5W/Bx2lJ5L23HColbV45wU3MM0upLaAqaM/iUem47csMVcpR3rDp04Tz
CgVtNFZiP8sIUTgUeA3B7JhAPWEoNclVqWEtOQcqTIR0FaeiGhMAnEUZLzKC6hYSgTi1aTvzhMDU
LYZElF1FiAEzM0q06+g+pEe14uD9ZAUFrOYwnYrtNXUCThEkXKY7MdeM0v2ZNsmffI3LJ0jzrYwZ
sx7J6aclbLjWGjIHZYpdAdOZzvjrZcT/TmSIk8YrPms8mLdXCG9S+qVIEukoc3xKyJoLENNikAam
b72OWNaVkzvi5Lipc0sPtmZRN1ylF8FziwRtR0widR7klpcLy/wSdTfbbFm5BsKzVw5Ok4Z0MsTx
/37n+6mA2ZfK3FO6sQLlqwW8pi4dHr8U6GHw0fZaWgkfodwebqiCO1y29JU2fU5no9cgbM/nHdxa
tWiiwrPW7YSEX4Kw2m1ozaOTQ/iOM2jlz1p0vcwkMKmJF/WxO2H8mv+6KNKt1xZyho3Sum7DYyJz
61C1vn68EB0DzIT85gMLpVjOY7CFO1CF6GhOHlEkYkFHvDGGQ+/WGaOBBdmJ7QfmdkKAdpsWrA6E
+nvQ7AyginhvPCCEjvlWt/l9wWfeT9HxV9KNkyOvOVw3bxkmYFFGwWPW5ApmJ37G0hT0S3de94eK
eNKAcboG4I68y9KAnVfjRqOGzBJUGXXo+jF6v/bd5+Gc/zPIrvptZmVTfGSBbiFEYJdgZ5p7PPDX
E5LJjKGpLaW5GqVWaGoIOcO+wKj+ChH/HaCkFJPq649CKP7ZuGf9dqj6GJ/ncLCxx05MCFMhxjiH
268GffjCJtcyDDIfJpCJWikNZP3pF8PS1lHH0SQ29iVxVgwknNiMw4kE452toZmbOk3aapNc8ZVX
vkocLf2oqTwE5gSnIBPzafUXsrcoh2oXqLgs89lgYmAvDPYhB3Ps0414mOSfdvXkPdVchz0OdvcV
v+LSda4Uyvi/fkOLSPF5SJhpMK6ibzojHtMgTVofKQ4NXx3GDflEp7rmTttKjclaMghAFx3wTofx
RRi5yCM1xRCgTq0kx7xxTkkSmhS3BlM70gKVtPsKHrd/PMMcDhzpozYt4nMjLBtoXVJGYODhOpFk
jIMpkdj0z2aHJdSqZ7WltaIG62jhPO6yl8iz20kC78YRY5XrITwrR25s3uC4c17j8tRYxsguv2Ij
W39U4JxSB4LNe2eEAKU9YT6gguqyLwq+tr5BtD7XWP5E47kK6S/pVSnP3asHJvo//m5pK5IRO9zk
+D6YMYh2rITv1SwEcrT4Np5WLAEZkOF/3A1EaRjlhDcSO5X2P8ADZkoDHTuQujlAHaD0xx/uucl5
zf59RLctbDJhpfovKcPLGONjvusSsPKaQsVL2oZ+palgWVmoWFGCYVmPGCPeSRpBIPK9zx5sSL/5
pmxIUvLRcYGVmvLDyj8gW/vsW9kL06BwwB5tY/HAr/CkP/o5vTVyx2RdBYwLB4VXpqomLfoL+2ZK
URkretrTd1rVem9SUWPh6PnR2rImJX1Qsu0Lo9qXIbZC37wC8zpZwDEE64fo/9uTKHlGRmcmFl4+
t0tqZd75k+bWr5AROHlr6IKuGskdc60WsAzI2eema7QsdAzIVI4GN855ZO6KHzt5HLHVKGNkWYNu
fH1WAXPgKVxYHsc4mi9ffO2CS1zcNJBYPPydg82Mmo8xIHl7h8UuSrZdjIJvJan/4ZXUCv/+fhgK
AfRm34r/Zr2cSnK2iz4VqQ+Z+sF6zTZDQQvkVvtpu/01QQSP+COXUlbKxjaNZnGI5c1tamC2ViN0
d5hevnq9WrtMvTVuwbHno5EZ3YQOaljxmONbFES+8u3oec1Th2S1q8VslSQPCVV4PGru3g0Vkspp
UAjpMKu0iAYUSuMBqSR2aoxqaNoeNOB/Hw7B2inqo71rJ6YuAtbaHPwUW52zPzSxdyffUHEhPlG5
swMwAaRAhwWf+OKUWbyBrZpgVh7jhLsEJEcwgmOfP1GBobPYaKyceTmiuOjeR8dB4UP1SyY1tTPc
dq87GCdI6WcoM2ZqfB1yQ5z25lc0yag0B65/vClsaQTZJPsY5Med15vpwJYffCKfiOHixKPEuZij
84lPQTPyOd0eNYIjj6NQsNDUNxSqmByiGn7MALzl5oMXdNmhlJA10ErChPaTub65iSfHbEr+/d8a
Mmm9aX+M267KAJJvTi9LYekKWlQN6iWYrEGV4+cVUMxhUZdsp5UIL5zqn++9wO7jDNQIvqoqdnua
GwvqNPOwHJItAiX4INMe5nvAbPK7HRo0eq13GREuhF5JTXbK+kU+bHZok4F+soWWqA3er6SQ4wFH
0P3fhug/wTPkIAaezM6cmJQPQXCX/G8VfJatAnrbcy8JSjHi79/0Z/L4RPRRr64rW6E57uVDyQ6B
AkW+O2ZemN7IdMDCwILdowANJ9UyxiR6QHWYL3x2OE1F0t3mfdFMteLeg+YOUXpGQuVfQya9SyJ5
1aW6J/aKjuTANaQbmMbpbR/NLrAR32GGokxHdeANci7+vwKjkMI2i1z14lLJu4FQkW2CiitlaYbM
ptG3zAVeUjTXQBS5p7UFhv2+88o0Ly65XoQ1uqf15PCCRpjMHmmfqht10J2n3OjNKRfjT9R3pari
/R8AEZUoF1F9oDfOiEn1euwt4JDsTblOWy/oJVv7Fakd+J4WPHU+WQyA+iSvXrOSa4mUsafU8rib
G9Ua1iZOJuLrPBkW25NCMcAgYeBWxVPqrHe/qpomcXsmmZEan2GlIPcu8936JXyZgw8pUqHV+BKR
jIq2BTzjUjMZdPI6wwsX+IEowQAB6TCEhASchPJtO0Q9XX5Xz1ie+L5xYvItjD55Bh6ajObz3o6K
q2jSQYEB1ViSN1IJRaO5/ErVt9p8XVJj727vhRQSpUGQW3QF6UkbQcioBRolfFoa+f8vOoXeWgRR
KCx31IKmGVATcBUY1J8op0YHxWkVFZ2qyrKi4qXku+nQmY33fyuSJfuLChclFx5Joj/hqluLw14K
1Dut/ML3NBL3g+ebqD9lZ2IkaPwadiZ6bNgAdJnpKTJrk1QhAq/DDUyX7i77tisrJI57rS/69nJN
+j3LmTIQWDQmNlJxVEx5Zff6n+qJodRmTSp8qBHu20ogDXj9mw5AoydPPxzEdXNaRrRoMNUK9GML
BhxinW8z8PJSDJDIWBP4DBvtN+tekc3paiIQwZLSJBHmnRIQUqKDOxCtB3VU7y74UgWdYvvIU/T6
VaB2xx2Tv5D+/190IVvSCfSCTatv5mSwsF/MpXRd8i1suXBh8vvtlqGafVxh8JMhwjq/divuYsps
oqwTVHd1fMx1IstP0YawcQAFPp6G9xxOnBcpSwooNOfjY6erWKon5IIFHcsFs/93ickmGy2LYPKl
uObz/KMOoRfi4OC9KuBOcvZYav17L7QFs8q/JElMt+YC+xZKKUuOAq8EIcYGQDakeHMNY0jDcE7k
NSWCsW8J08ASUpeos2/ofjLcCZF55jg8vpAVPUFrbug+OB1fEA3z/MgSlszUtbo9aiZuTA3gyNwR
E/+ol5xC/QHSnAWarLP5SE3NhAt75xl9MyJX/p6mHmOcGkCh23XjGmH67GzEbK1agrMoXO0bz9nl
UvTUA3M2WQpRjNQBTsz7djMOYceKBFR1Uz8UFpMp2kYkrpla8mGuDqLWPI/euJLTmupSaBlCYFbm
Bncmtq8cy5rELqZE2yBQdRHMpqaN6MHc0/G7WQ/KwPiLcjlLt5bSMfJ3cGdfUglVkvieO4V2fxj+
g9pwYGseer7unqqdOLuqovNIifSARU/61Y6MEzmSrwyIjxNEltDlwVy7meOwjrkTd93oD5RpY2rR
t+ckfD13wled22/5+bcaWzUbp/dy2Khiigppks7zfPf+7/6d+Lix9XgZxSSkRGdYunRE7xTiqi44
AKT4jZW87VeuPa32Xk9Cr2hm8t313MDzeblCoDlEClru90SFGQxGA6K/lY1gLp4deZYiVGlc6VA/
aUzSH8fbU/HhLyvnD6nv41kzAh7wu8cZT5+RKbwuPONJtbiweqEYy+wKfv164Q0Pq6sW8VjWNfSV
TVvUSqkjbUhc4m7DWOXTbB0CWR5dozsmOdUBqBNs+OqGouYUuLzahmjsTLZD8crq46iTBwckw3Pl
Pd23zQVBJtLotmJjn2lo78AOMTg0GE6bgvKbCvUYVvuKjx1/yP/QE/HvqgNw5w7WRj03W/0ybhN0
DWyUMLejf2hLqdbhmxozng6SwYQnUunRIgUCc6SMkLixZ9jTvJhL+FHOue8aWn3lpPIHBO+VVRSI
EQ/wt8vL/ZPx/p4tlNEjz2I/9Yea7RuZUP6ghK4f9tbBZReV65SKT9VNJCPE+lSJigfcNz+JkC9D
H8+JJoZd36QXITAh8QD/KVnuIcasRRDjJOakLLim+4dq4aNTOJujfs7OhWvwCOUxjYtk8NcDeLj/
/OUTXVPr5+9Nge0TGN9jfL+CtYi8XFJbpTnKCMvzry69WRmLWuqNdaF0kRdO/pI8RxhG2KA4kLpC
64DtNDJ/llNGKid1z91pnKfatfc6iv8LPVfSwVy3FUnHevbRpzJsVQmq7gHZhhANgUamXMO+WAT2
dU8uON8IpA4ctkkLGu1+cPu1siaeBfxflgm44ZG0Vo6oB354B6K1Blt4hp4BVSvJ0gREBM9ZAI+m
H1n25fN5jRPNeGa8Ngf57UcCBalBdMXtCl6TuPrjwwGLr5aBZdDiJ64J6Eq4oJomkIBZKPsn8RU9
hPFm/ErPtOtSBdtsZFemswxeopgtcoHpku9PTdGOROHowT8RV3RP5jRx/Ok9nkd6VbCQXD/nkxIU
0GjU8OTD1EessFGPu7PxjC5luZ5R7ElioeE1Ey923kRxuV8OsmYwsH7OMUifQSVJQwcwTUS7JWHB
7GXiXmXaMDazws3zdG23l+GGBCMAJbGDJU3kYasyZOvJuGNS7qcz4gb8Hsn+sRy7r5WJ5UWgD3Yn
gPGFpZmkdp23eQGWSpvWtgD5BEAUdN9CIUhf+XK7IcJyWdiZafkYMaIevOEShPL1s5Kg5MhnI9qW
m54itB/cYOwZM7ShSbSMI1VzYp6awQ6rg8vPSG/LdQoph31iuBnX4D8RAYjMBJetzoCOJ1SK/NvO
30RoeYGlPuUj4+PNnC19+k+bbjY2S6KK/rVGidiVeNgn6L1bNqSkv/cfrol0o+5/sDb3f/9GS/yq
h87S4dulF/DUGnpmF6CKzidF2+Pykb4azK9cWrUrxJXeE2dnDMYrgA31tmIMZTgiks4rZh7PrDXH
77O/+0b1U6Rvf9gXwekgJQqyjKot/S9UGyj4CVpzR+CDiyEBRF4y/Yu1Kx301CNnNbuF/rJEMfCi
bpt072k01IrpqGRDfKBDisZLzvfcQO2s8FGn0pzR6I0JEXSgT2pCJ8XgdIvquM/iMGJz8totAiiU
E9BSjWogxd2EyJx4Vgh00IIVcaTiDX/7ZlN0J0XTrzKTCYC0zXYJtYZ7nIm2pUy9yY8ZE11qr2z4
Rt4DJz0x46AnPU4Q8woejknNo4toDC56eyZsmbMAy/bTrd0tPi7Tjao798wK+e8/Vk46vZmPMzAo
sZbLk5ycoEZW0n0BulgZyuu91i+90nqqjQ9yOW3Tbj8e733YaTivXbUFJo6Qo5xd4dMx6DZ5mtGf
2nMyoJNCluVkDtkvwdMKQvmpwWhswDjMWFl4s3bf7WS7NhR9JfhZ6agtwqaHTARU2Rpsi9VGKyBL
xBVQfgpk8vrgiYRfW4MSIuo8p/7LjcuVijxqQb/Y9FpDzl4v8ri+FiHbRj4OiABf3tWJv8+9e6DA
3AdrJyMTE+Re4HVrid2wvJGTWVGNpYInjqh11UshOgJETe9KgRwxCjaPHtUNNLtyQiX3FCDXZ7f7
ffmTHYong4WxjVXRvzi6dqQipXVwSg5ec22qZFj8OIAXO8px9/VH23ky6Dnwt9igqzRc04gdO/bs
QE0I8lGaVVkzCXYB5wcprrpJKovX6qe1hs+SOMEYGbNArY1tP1BbIGxyypqVekec15vfsw9p7Qhe
QS1yYmg+fTO3NWwDdrbN15BXMvZ+5OYu0mcixZ+tTOei93y0eEvt4D/2kVHHC2ExQ4UHEIYndhgw
iLtlN906g9UD78TmAYy7JmNDkGM599THVv+ouOOF6vYJHN7IwsJtPJdXT+qBDmhsG6CbYLOe1dt2
LzSFUcROuDvp78LwmmzygCpzAWee4ZyWKvg6IMVNhvOiSwSMWIVEtgP3SlA7BR2LZF1qd8maqJcG
qvU8rGt78NdcXSTXymvJ8/PZmlN9KTM6Vth2IeVeRkRtMe8S2v5bQuVmW44eX5T8Mnc0zhvhdoih
Qhlj5G/FF8tNcWuWtgmYNcbhtKQgacjh5I8zfVGxoK9f0zv8ooy6d6C6cnrAA6P5xqzKlzIephWr
Yr0h8QGRqh/n3pdWw/JvR1A85t0KeTdzGz+WRzDrRZY8lH/ykBMLIxtOsIEqwjteONJG9T922ZeT
8mV6b+dPgQhzzl1Tf/+wPxJkoF0gX6tdgmSZuQD+rKDtNv2lZzyy0J8i/buSPy1dt4y3ny/GC2QZ
9VCvWmTntQbOEC51bxKzdNH1JwBW36NnZeNemHueWyCqgny+jJ6w17kCB48Uk8WPPFiqmc4p8m5M
m9cULlSiNQq4UVLahsLoeEPduhqnSPAq0NyaqWs7CAyeB2Y5QDwIWtCHx4vfaJnoV+Xu3VY+CA3K
z0XbnTgYwrdE9BQVNOAyyzNatqgh2MGtOtOdqGMsDrLhDvO6YO+jGUwT6GipywJScjRU/gxuKFuw
L/OiMiFw1e4ncg+YkyLBDYaUHhXftES17AbGoF5rLOgtXuXGZNCHsbEJ3Z+u2TLNUFM4yvpu02yv
esSWs7MVHDBETLAbmnAMyOPBd8IKq1PXcq8mzAQAWhx3MSQ4GVW6FiRhRr4jeRwfKfArwMeQ/RkH
RLQRYHNAO8v3StcwvVhxXzY/Cw3RN40mBM+7snS99CbjMRdtikU4E5pHwMOM3Rl9atnmWKpVlVxi
pyvVhtjkxKgljiGQIc+s5JPRuvJYwK/WiSrQtA53UM///b7hlucTVqTB0jD9baupV+Kizbx/OfEY
Kw2a9IoT++EPVF1k7nHuCpV92YBP05ldgNdEgBRuG7Kt8pudlFNcWa26EbK0x/Vdwh0Qf7dekrbh
NbxhqaP5BhuNc+dY2JlqqTi2diy1zEbUFLRgUxHhwt/WQFzwyofyq/r2xZggm5l1mFP2OdsU+x7m
md3/duTthICRzGkdmN+CxBx8eaHz6OAABjmhgmfSoF+YqNl1TEZEqAqtQmP8fE6yVtCLGcSus0cF
bm+ptTfXYPh6WZiq5M/oLTfMb0L86q94Qa0iQZHd79GCQjQwbhzoW/toYxx+QSLTTZVX+GglzwoL
y2M1/GfW0dCy9rbwfG40n+O4dqg1u7jKNrbqx5EQTSwgihDpGWqxzRVTr2sNcWo26KvIZlrTf31M
UD3GGeNw5bruSBXWkLxnunhudNQS/Gg6qi9K6vfnwiBEwWZh93SehO7XvN6pTj0k71enrNHZ9d9I
HJYz/rhUyLpyjCNZN5HqKUqoxmT9KNjTyfO0Fy92LKdjpW5MUVP7icfRqYgLTrO+js+aDxMSwnDj
rGic7+xgC+vEdEg0NBwtGLZvQ4RT33odpByCIGn+VJUQD2NyC86V6dtuOGm+0BE46h52a8Hdw+v0
gBT1t/VwTWIoUxuXBajyF7k+2vXWahpB3HchzHwwfXXb+fbqcrDoxi2yzgOdczPSi4UU9icde3XB
cr6Og7Fl5LNqO8I52l2QEj8is1IzGH0pyYZVJXACzOJFbwN1uWFqluIR8vtYiq62MsyKnauz84zu
69B3tZspZvMtVbi+co6yE2JwnzVXV2qPiXutzVwMxc4GPTYms4rtIAlvxihinlc7ESn+MjPzK1U7
caJGVE2ozTTaqbacG2/BXMfoLE5x/4kX7jwhW2W6YTwgdJYR0Fd7dj71x+TYc6GBAwMUVT6llgul
0hQBBb299vXvF2ZjxoTvd7yRC+nsV9vPv+WjUgjAiepBWZELz4/2GXmN7VovY+yVdSIYWBn24P8x
ZaBm0S2HuzCVSJlaiC5oa5H0c/tLIPfuQz0AmRd9Rm7xWFCZ9MCnGU3qoYPBEc0FRVAWycaljGes
p6qdtzOnIzNK3AmfBhf9L4WGNGnigwfsW6XLA8+p2l/7LL55UGm3zRXJ4BchMtqlODXD8AD6khux
TvROUSfLnQqpjLpCMlgM8DZ8rwIB/Cq992f1vWu++lJS0iH6uIcHTlJeB5qZ7IMtWMFnZALeTO72
sYKWh49yxZrUsX6joPhN3oNSPmRqTZkNbW3VJmVUA7foK3gBIiZrua0iXE2/mLnG5Nqo39SR8WyN
rQKuA1kp6OtdySn6vfsVWoPNP1j7fKNJsPmppgIdzweYy4bvETIoGFSnGJ5YfSDFO4nHCAyZppOg
pUeEKFdek8l7/3i564AxYPfSRWGl49GWRXzKVVugNVZVFQJL1jM6OtKIoc49A37AI3KBxq/SpTwk
uqGGPzhDsV27mohF8ngQxstlqOXoH109dDrBbLhVVZr1dX8dYrE3rt2+Jbns9Ih38evBnLWwNubb
hFpzUQVDxy1GQXVGRIo3IX4jHDupLDzuXovJzACaszVIK5r+nqyNf5aOK6aF86IkADSAxUo1l2cB
z2mMHxK62AH9BiCjieP/ARbr6yMcu64gaISJpqUC868XrDWIs/cs0N6BymXge1kvEfpmcmvQLEOB
yGScecalAt1X0UrXNPQ21Yj3r08i0/mk63KuInbSt5vZH3Jtn5nViHGmZPGyllZcFBA7IcCOEbm1
uAkFOgVkpTFFOv+567PAvv7vZt6TB/SoWfASN7KlPjH9cpMEezfyBk77gvgRjOxmSrvq4qi0fBbD
hyhD1udhYQanbwd57YoBTmf3IG3hWKaB18K2uotzbHKlqmR73oRmz2oeJGWhP4VmhKO2vG5QtCyV
BZ+gxLYbepo697Iz19xXDvV0JxBt/4arwM9Vk3Y/LI8ccst/E46ewIfCDV8GZPS6cQVtnUZI1HOD
yW3ZFaky31XTSv4kHILJedOSNfRa+tmsJXZkz4Lm3rsKqXZayMHuq8WowhRcfigGqfLFkeD2kVEp
pRWXMwE91UjQO0zUrSE5hRDTuYcrH/l/PIzALiKm4xE7+p/1eGZCvTulIuFDGhV/cQ+B80mo0CDe
1jrM7ViJdMbkswCiVSzLSOTmFXZDZ/jvMefqYk8qL2penaa3QEyDO9JLQviR8O9+EIlZ13cjQjKR
MhQtVqw/wtelKp1rX5Iqb08VGzvdAJG6M1dBVbQrOTxO78nrqk7vXIELcg6/HVXzQxoZhpS2Dn6G
sMxHbiDLBeM0uQ4cdFDXTA5tTPWkxExPJH8Ncyv5reuN2+56Lv3qZDTnkUnYq+00NSYhI6Q5Y3u5
643vFipPKzGqOC7NpfrPI7Fqedes1oQqI49LEsflIk0aM0y7K5hUW95bw3/YkFcHMZSFhcxG4bsg
cwmbdj57cEykHVYxldO8mL+AKxW1OSB1yhcF4tSgORVPU8t09tUrFvNT7Mo/RZbBYRipMZFoKuCf
MozcoNv4dp69OE4Z2JIxzymSF56UfzSjGmkRPJO2V5Vl/wlIByUDYuz+x3Z5+ZYe3LhPGUzF9Dyx
FLsEteSgwZpMbUEp8lsmMtqvnxJe2CAPE78uUUCS3nclRdZVfynZwOgWIBeP0XsljLgAjuXGlFaH
UXR4vnZuWWgzb0IeRG0HXCLlSG661foVAr70qVU3lbOWjAhB9mwVLpkhcPIPmg5Z95dapUUFeOL5
OoX1kTEnC1eSTnoiaxtfg9Fw1rnvTvzI87LiDK19nFTAiVk1dx5uT2lYlca9OJHBt2/JeWvOdb03
6J5tovV3VzMXmEB55FfkdUtD1EVOx0RByLE3Vqi2emHdCNIYPlamghqnXkBOfogevjPPnGu0Xcab
hxr5mkRVumYk5OO2rsdw1ii4tECbRfZjXZl8bU4kwYUW8RjU2Jzpeztk6OTw2z/edgLtYXSLldeG
YrGRRNonxs9Ltr3JOlbORhkEX112fUm2S2IdJNHmRJpeHBgxvH0hJ40u2afK0MzDne99KFqHfLlL
gplsQebXxSSIos1fUdQOkqNsIwZOyfV5dTU/azHpFfIby7HMP7p4kblYwtuBPimvWj2PYON+fTn/
Pg4K6vlmn7oy+AyShvVowTVZQ55WoThrb85NOwIcOj08mWMlKv7vjnoQe7k6m5FhM8yOv3z/G3l/
Qr0ATYyyZKvSfn9tJnENliD+K7VkmSYZxX2NvRJl8Lywr/77Tfe4OT0Vv0mTueaVgRwv9+EtFaWC
TV1M3Yu4khnIODsK7Lwlj1CelPBDMbPGST4ze2sAz38kKNxOFfPRzX64m/IKIs+76GXBf1Un9NC2
bGda3AaOlVGNdGIDbI94ZvmCNiy6DaF6mot8W6ONWyhyZGHogN47ti64yWwQoqtvkN13CnAiiUBi
j8k74BCW6+AuRzEsGZFRYEa5baXDhfYkLY/CwR+lE0ZDBp0ZCsHUaXboWiFtUBylKgmfdP90H/H5
IHhxRdNyp3/x5o9xS06PjTY9WC2yoRchJPVWGx1uZIpslfXk77MZ1r9+Hyf+HTvkjcERLFXvS4ts
ZO3xJLCdXYchG0oce4HCysKtx7TEABi6b326A7SNaAyAzmoIvK18L6fV1JjLaJJRzr8XGyzR38dU
jVSoMLU/FJficmhMEW3q5stO+jLmLK/UlfzPO89GS10C+4ciBjyaBsFExnqjexA6RETbOz/MDmE/
QFnPRkPBWRxCykxmvmwaY/1mwOuSNJ5vMaT6Qdgwex1VOMHcou7V9kfUCWYpaRpsJPq/A79do+HC
6YoO8JjYT2DkgMNXu+kZ2gjgualYdDWwgwIUZORoOlRQZ9BkFrRhVvqlJMBkvOQtCd4Oux75DKWW
LkFRThbDLahY6jWw3OecX6lwLRe/OY3YYoaFFCOwgEDCsLTS4/mhnnYKRzvp7OMAv8wYuiX1QiIW
IAj9wVbxW+KiFp5nhoCtdvVR3iFgw968c/0XCoB7MmSiYaT2dNs50H4/AaKf32VOm9hI9q7aJeVo
0hVttXCM2vrGVxoqfW/p7EgHY/LD/Oj3aLD38w8LRHAZNZHY6NsXssjScY/H6AIb7vQuuUsvhD3N
VONzUNeMGPobA+tKyAOtp6H4mBkIwCeWPVL55ifTzJZTcQG5J0imGDMsZDupwWOl8omcqdr0wREt
/PIYx6nKAEtYco/hTxIXDIgCTf8jhUcJ+kNdQTbBlAZN61zoxjTJUokqW+d6VNSIIIE1EDEQE2f9
PgtpTKhWwNww5htQPNxaBalMcDPcyHmG2KNnkDZQ3Fn+2kF41itAiv8mSciY446QXhr5NU9RVI7i
LqiaJO88/w/aTqH64tRsY49z2RbEAo+udq1ZX1DuoVksbbB+3scqZbBDKGuK0n4IgVBp+pRu0sLm
q3s9bd2T1W4If/7oL+Tv1bXK+t966wtZ/8bw9YMI96zpMnGiR2yOEseMV8gdM7NZ9MdcIF9j4Dmq
Re/jNlCjZfEKYv2ZhqYdfuhZRCE4pNeiSL/BW0LiRtzVDWA63WbOaRiDdvN/rj83/Ex740HkURY5
hFobWQiBJ6RWyIJN+RYz3nafOby7F20x5332LvgXqx6q5OACGjJ9QSfpWH53hvB9VuW9uNq7PGHQ
fkLCm3N6TQ1NqjTL+SVIvN3h323cM8gfPRj8dYW9ZKPywmk4OjG86IZN2S+sM/fa2LBqheiyCfNv
bFunhvwOw2zE4VKmjyk2Xj1GDoaZ2YPsT2P+1dGRBeOj7496CahuGK1mz+uBoIm6Ja+RgW68ERD/
O0halhpiNiQ6HAVOT66yeGMYEezUDVHbt225G7xzPs5sJjDfR6Q/Ldix5amZlkARHV3xW8mZlb8W
hY/t7rhjV2Gqup3A6UDY9zJUT30i8p++V6aNZMTVv0MkU6G/YWax8HE3zdpblo5AjqX9NRdJpkQ0
12rCAEg1hS+/lUcvEGCqk4qHhlsz9ey9wKH+pDGVV5bINifFoPhlnHSc/6buRKWhEllb07QEqJWw
ekymqk+nOtld6dCN1uslGRUfnPvBNpBOs2r7CTgdUrG9d+nKZQEp3yrtkkYCNnGikAtbwPi2fes1
CgZA3slLG7tSWFtD4+Opn+68+6FyFvYky0jkOj5xON2qinOhC7OWeYv94rspzajMbAEi1WGrREQ9
41WOoZE+KTTsR3B+OTuwGCRP4v2sd8KMCjUycWtBUOlFOrrKfM1eClN5t097b72SpSWj2nphz+et
T81nLwa1+sVexy+HgPPr+zq+blacPKotMywWt1yZ7xDGjsNwamQp1ysf17b5KgrV/IPXDaL9kyQh
aHYd3fMLT/OXRAVxS9W/kllNi76LKqD9nbCjZ3Kng5Tc9jpzE1Ww2Eh4cm61wEP8HuQa6GCcjEoQ
wJ0CPSgTPfmc4a4DBgfXPw3B/GeoV6v6ckXpW5Lnhi1oD4HjYjcFth1hv0d3GPTAseAzyzxmjG8p
RGX68oWPnUN0edRdUTE+L69xVeiA6ckDIwskLuvOLhyYRnMt+/kiB1LVGWBt/KLlSY+aSBjsoHpj
87UOeBxNg9hglN/BI2MdwxXmMRN0FS8zJILpzU2Pk3RonO2bLDlC9ajlzcGYAso0OsJSCYjUPTtq
r5JuuAvCYBDEMOYxvmxTVCzEtkLR7kNDSUXwH4xwcJztw10Ue44zaRIWJzSbzOE9yRhepr59gthT
u+38I5dUq0wazU/caArOo3ASVE9SL2PvkGNJSeFSIMzqj8UJdC9DO2Z3AeXRuQQHqLnOoYQdsfDV
6iucDJZBcQSReAlBcFWo043OkrwnfvM6YJb1NXB9xxXai2oEagF5PL0cUHuX/lJHsmw+fpwMqqtz
0KQ9jUIm8kj+A+kUv0mzaN37YT2UmgnenousQy/7QUBovvsDaE2cE9JVB+grMvQQ+Vc8eKvNHE92
8MsHP+asFQ9wxSME87icJaypv52ntQA7Jvr0aOD/Tf33vawveBCJFSpgpDAHyv94+mM1m3QJfeyt
btlEd3Ea3Bdj1hzTUnacJFYBX9vzsmVgdbSJLOf/RZA2/HMFsCWGPhDPhh8FVod/LUVY1xhcFZEq
105zlYxoJ8nt7dvKbFu+TXtGQdQx9XfHztAeZRYSeAfBLOKcwhaM6oWt1QLgm3Gm6Uy8V/D9gcH0
i0DBqu9cojn3t9Xl8f9zm2PJ+FWOebHrpbKZrihCPvDqiU5uRSJmn2c9lXAl/PzAgJbk86ttfWvB
uz22Fq/FpZkvjEsbAp+M0z5ATK354122BX8Mwxd1MzpNz5S1dHWhRSjHaYzpTUnePbvihjyJ+Xtg
5qG7nFKqyplxlqh6FyExR3d+9JNYzZj+Lj+XQrI2Svh50ps2UNhJUrvGvzelh5xQUmNt+ub0vgfu
iFm5jkgSCGia8R2AUDhnyQ4XuCObFeP5pxSm18UiAQ7EvauRTdPEXG4Ncas0IaDritHlSvS15Q94
qMmFS7EGS2qo+NLH1jVejVMTTwVMJrWoGfN759TDRpEhPriF3dVWVqefBszzKOqzTf81g19gQdg7
E+L7wsHpODKVssy71NqxCxpQ9IkBMeMbFwz9iQ3RtWWYoDUBCo+kVotkc2jOOln/VJSxFRQLcChY
XJ2U9eoC6t8q4+M9v6P9LveG7ZF+48U7YZQiROeJUFdhse1mhwc+zIEovGStHJW1pe/6icYxcNDm
FTlpCDzyHgA+k+YNMTWIDlbrCd1s7uzxuRGLItwYUK2VZUAj+vkMuC3zXgu8T95QGvWu1M88H0Ys
SNRr9wqWFEPs0y6m0smNAly1dRKuXKrEUJuZT0e2tMrMujN8d6sTQQOgjb/J5R9BVMNfQL/Dg00F
RFIG8fBGv4d4VoIUmYW/CsARFkY0efeS28KvhRqKEU/0No1JQjhk1pw9zh5aPFGd/p11ghz8PvX8
wn7Ow/2ECHAZAf7kj/Nf3Xg66kjYZsyQJ2cXYM8YnREJxMXzflbLKLb4z2ahxu8t5xWFnW37/hq1
SwjOIFdU0dGcXZKy66zfNVSs7Nlxc2EBfBWlYfDce+I3M7Y2vEwVzOFHp1YyR9ulBpUl7O2agIvV
u8uOBjZ/05tg31JpxkjMH5ldNnvyJuNi5vAzcuxz09FA3GrwgXi/4TlTv/ty6ppXD9MCnKHLF3jE
8/MHdlD9CxsZg54xkedK5vF9nm12+hlkzFpIWJtMc4CfokpOzgqQldC6X9bq8/rSj8b1a8B3BBnM
d266Ec+ovv6715l7JWVwNxSuwdMjsKi3f0F72dZrtLiAl52L4d8qYv7bAIh4sMkAaTHatYQowyKy
1wqoJUj8L4oyCZcErcykAc8jnZ1lL0ISbcxapjuEk5CGVHXVALjeB+IFXCYcekAmbc+R7anyZtkP
ahfZNfxWq3TLQ9hZzux09vnLZz0EZsvU5uLREotJg9G5zkwe1YvVMkxqqJvVoKufk6w68yzxnK8j
NZI7FfJP1waNFF0DdLQyZSf6ZRPGXCnLBG2NQAMeR3CviKB0nsIgbmgFI9eoHn6EYRWV1wpTBIb0
2LyCXHAxO9UbdXzFGPKFnNAZA+r3DcJ1Y3W+lXRvDyhlpb4tFkoGlkN5YFhQ7Gl2dE+J0vUQR3Ie
+mFZ2jfdcfCtxVylfAzny2uE6eipiSV4LkykMhb5vufb0UR0n420RcjM9xr4SILhhwLTIfdF9z3R
SQy/uwXTU9UMODcCj4EINuWpv0XYphWU7Fcd7yFgKWtYA/A1e6OQQMzycB19xLF35zOeMV7kP3GZ
/2NFRjcnsrH7rZU+Br98MMCq9MKCIWe47iNMYmOqWvDGx/iGVpO9XJi/KkHlVEqUepuNj+CYUUhR
YdX1zQhOqc5C/NKoeVfnj74UVPhvogpdD5+wh8yDuwcGhBH1Z4oZnOhJnw69iJbFMPgDRXh7iKBO
UDz4w/cVus8hn6UefrCmJTggxdPs4KG4rHNaNCgYbJbnuvyC5Yqcn4pZxWv3f6CHIgiWKJlL80rl
2QnPLxpFC+JXMOM8HjbYtP3E0ubjTGKvYdkxlvObUT/O8YSx3+mhP7U1pmorKkyUPbzWV+lC1xzh
cn9ndswAgRIIIn54/wnYI0jQYcrTAKj70UTAdjlapuX2u/5cEqy3dXB1X2cf73HZ7JcH5HQoRn+W
DbwquRIrFMAf6YOXMZcDU9ldkCbGOow4wmUmjec6+3ONQRm6/VNVSLwqmKYwhgDn5hlD5qlDbLpu
RGUMQHfZMCvloiwpH8ajhbBXbQlGlFGH0savHBZ+/scESgzQ7/Tw51kXY9DfgYum+vC4A1ZyzTSR
uwo3OxS3kDeWw62ypD3ydEGqgS1UiU5Y9s+AueJWUutOHtcFDDeQOEDZjFHTbShXMFoetL5ci06E
BqWohC7k1jGE4f9erPOJ2HK6oo5b9vQ25eOYKYW9RARA1AeKDm2uzjbNU85OeuiEoU6Ato8Cfh0k
ZURzXEz51NU/d2twCx7JsN1tuoVP2o4a7ylOaXJuGDBDw0fqD5nGRSvgs7h8XQDYSWDJseqgdA1I
YdzzU24n3UksEI2UdpLEhmcc8msYvQNBPRnOR3TOP2TsNjkaWZQ2ztvEb+dSQN7PjzjRjYMXF8EQ
TdMDK5XEfP5NLFQKzkHbfwctT0rGSIRCDDoXKFoX7qQoIeLfQS1VVxYX+v+jR3k6uPQBOqa5YWR7
40jwp/GsX/gmQmrcGpELeOU2NHG+XKIrgrR+sgypSFDU9PfRraqVrwac3mXE5uf/8KV2cgs+XvWq
wJO9np91ly9CfgsTp2lrnHDvnQd8pHNw7TIuszf3CGieTluHQdt7XGK2zpH2k0u1iW4O/PaqHS1K
Lpmpsw4DJfG1eYDTdIv6Z0Xg4sgr/1ftMdywhu8hAp4WAdj2TFzh11bVNvsGmJ5KxS2cMlk38tpc
eROFQncoFwZcys2M9+cRqdWoyrb7O4y9WD8XfuLzXNd+5jd+gAVQ4jsjITjWB+XxNUcvrPvG6vqP
jWJYXbJ+5tQr2voJplcCtD3LOHPxoGZva30lxJplG2p2DZLmWYHyIa3cSVeqqdIlyI+wcYYOBZ0h
bBmx4SaXBTNSVZubQeolXYG65tUrDfpXAZ3qIaoV7+wzJ4BT4tc4xt9Adiif99sJ2TTBOOiLeE8A
ZDGw1vBMiZLxMJd49fTO8BnZAm1Gylp/o09E1wc3LwCYvduL1kpkbpi+gO6a1bIAA2mfA/N91JNF
Ve1tVNbHFG2wjDWaF19tLata6X4rKO4YCBsf5JNPgHM2KU+6tr5FV0RaFLCUjPzPNXHHYm42GA23
z7yHuP7ba0+gKGLuL+huEUecB70FTHpZpmF0IAjraAc13mSCG5m7kqvlUjCSeRQ+pFG5octklP67
FON3yVPXPkNXCb30lzCRrRwuqYpbU7/YBlkxUGId7QZN3Ht05xLxZ4dYaiJZpDvlcMOhjr79Y0bb
SusIFt7kVKFtIV7/+6xlm2Fb25AsygwNyCFUf3huH4Gt5Y66C65PI1eT+zAP8mHAuQPf9OTP1b70
ySlQlxTDcQDudR1lI1/Xbze+5qjeNr2Yb/J9JKaFBmIiEeqMBDjiLWgHCfJ9HFnRZAaRc/G/Fc2t
OHzL47vRP+QvGW9f2YC3Ms7spIUv7VmL/urSCuUfovbDLqcPUCVgxa6vEGdwmdNIPuKc43Lo/MvK
cFq0MyR4kybYTiCm6ax+fLomWBpdmkipX6/Z6HV2ly2/UZHyyMmDC2b9kZb7gdVPDns5GI2vlGh3
uFqSl2NNNzhenL3HPXXHGO91sKK1Kk6VHIv3wKo9REvJGjRSPHiJv+RDOogEH7T77+SDBg9W+UXa
oIUJxnXHE/3qmUQ+Ai7jUyhcwPdsv36+145jolY4b9yL3uijxewATIWQDG5Bv/J6jWNJQ3+GxB/E
NXREa+PPXhRq3HFbUuTX8Cjf8IGWGW56gqKTwniZmyRyT90VgTIPE9Qzt1x09nz7Oti/H2ceCWtV
br/Fg2jeMhuwnji7aSiWvlBzgQ56W7WX6Mm+0zlgi8hdhYM38VQA5lz/IMXqfuECJw83xyfwDLLV
wof3frxhzGWl7qXo6D2IYBTIArRo7YSDPOTdpdNnDp1FZmCWfeMgI/0c4L8BZXue9yLprGCp74O1
r6HHK8q0+WhsBGVatIv6AGDpoxK+SPA8M25wqufG1cFRUci++o1gxem9Szhn8PTkovtHHSOLRun1
4CnKdCPBiFLarjgkPO3QCJsKbOzPRxCij4vGz/Cre6P/6EgGKOBRQMiTvLA+rkeCRbx/SS7iJ5Hp
95Q2C6mAPYovp1qvmfWOv6C6yf686dcdXmwZA9UY3K6xKS0V+xD1a21MXOmz3qz0uB60uMYTSoC8
6NZgKzLnLw3O440aOJEHVaQ8aoQOCDG+wb/PjRnIWnlVBZRJIMzFal2DX4fKy8kIVjOKSMnAVQA5
vz/QdOEZKKZRoiSfqUoX9Gr44vEwbFPczivgvqcQXvk8CdV39hvgmLW0ivq52hi2XEqTm/G1y73L
N6rbIljJoFdri02Ip7Kx8xO03XwS8kEzOWQU/NUIb04HQfzQ/ox05f3VDy0wcaHaSIq2lE12OEsQ
2POUjAue8gu4fKAkEEFyAfNqsfa54rCteyxB3OwQoTq43R6XyrAFKHc429hEBxuFnwRfdqpS8zd5
7LBLjAYYJ7ARGZqKIDSnE3P4+Ue6dd+d8bbYBiBbJeByHLg7AEwKt7ZKLcUmDGxulrFxqaApkdRe
J87RqgYLbFedzhConByo51kdkELYAPZ4fw4p1HChkBsGKUr8SHEu27s6LXAQZO34zXp3pckzDcG6
4BvzpndWOgBKuArtdncgSQWtBjxrfAe+THRuSW1/U9HLQWkcLX030+SUSsdV3g8AuE0r53EBMNkW
GCcxOZp11e8hwvJhTXJEqErOps+gXTwLh7mAKPHikKFnu+mcyD5jbVFJ8tWbESbeUifkxMJb3RzS
5DvaiYvZ4O+3jJwgqAC3koTZZNzLD6kJDYzaqBFflPKZAS/v2Nc6TdQKfCrF47Tqd1YQtENRvsp4
/XxUL4XuSSghKjs0tJCE59y5fR8pPuXge8O18bA0sMd3lBWW8ZTAO+pFPwCb3vYkM0/ylVXfTiYn
P/JNVtsHBMRPw5qxrKnoVXraKBHBcX5KyxBrUlJccAZqKEuxysfPLhAE8hPcbcTYq2tIKmq2aOpr
qHvdT4IPVfExrBYVotzVGFwAog2UyjlyUkUEnWV7bZOyBrc1wDb5de02ZIt0cr0RfQOpwuOMklXA
5JA3zRrYE3t9Eu//EniHcKZzvYaL7o7gSMY6ELpq/7b27/urqzX132mwIm4y4XZMn0GwCx7d79NV
JLWrH2gDqHY7P//HPaxNDWRoHo0EIOu9Vse864TkNtQKJx+oY2YEUkiCOaNOEvJc2QhOPzU0yhbh
/497ml2v0wCwHYbud9rRXCJxl+jn9eKx+z78twZ25ZuvhROjt4n4iRV4CEOlcRyWo+X6cagGzOdV
QgQsczKKlF59okfQqgYgZOf6MyCnYyeNRVmGJLYwNHjFMjLLfTsZCjCdLgijW5jK/jchddckX2Zm
z01Rx6rgbjKECcuE5bjzfhUhg1/8VpLdl/Lbsbp9Ti712mLUc3T37QJeNQ/L5RsyQTrArf8pOYXJ
ZteOhw3dafCcNk/UALLP17eWFh/t7K7gvvunik4saWu0CQbinxJZTbrk1jzgXvnVVtIrnsFF1StA
bsR1WedmQo/GIl4ukijcyI2hnE63GiZj/f3Bsgwcz8KpKXf9bEmbdZ80GUITz9+jrtq4K2t7zE0C
tqKE84yfLNB8vLCZZ7oLBEr9Mng1gc8rpUdVUV7G6GKivwBIv3+Hrjm66aM8Qu/nUBXPRWYwRYSD
O8KkBrvqZKxm9uv2JqmvvCdmHoMyhw4k6lVOYMsUK5lXhBwB30ZtWMWDV5BY/sLnBWH2p6e6IyrL
47x5xOogIxJ8oB+pkq7CBOUW5PEshHjKaU0h2fup2fCXxDwIxlRI3HCm2c9Xx5FmRMU01bGDR0ZZ
LgJcxxZOwcUUtgstlO77Fy6YV2kp3Vad2oAE027SytxamgKquNvlFdhdhc+LJ/4sHYZOYz4zfCqx
z95V8B1f3voU5+sXb3FCIb7XmxdJB4VSAsqXg6ZVfR8Vg+srvMMpwLJYytt9ExWPFMDjcLUu0nKH
ipRHuTlZWbeUd+c0vPZr0xE7e7wJiOl/8FZUB9KzIkDhCDTdMKkTiIj0F0t9qxFLG6jNKeEnPXrY
r77LUhsil9WnCqvZ7Dpa2jhvcT0bEafq+BTXRsNAYg+QshPgHYmqxc8nnw53HaDJPNinAKy7BKBo
5+FnqDvxf918doae9iXtgjjwMPoNGlo4PWSmA8cReGIZsOQ/P7P/ytiiCP6+iVIN1TNgrdZbi1Q0
Jej/8hY0ffyqiSwCj8opEGLDjF0cVUCd31srZggRSXPw/9diQiYhlSbfa5Z0i6VS4d+cJLle6XpJ
OpUB5PWbHZ3DirAVuMavPPlbnu8FDm2Jdwqb12UNjjfEvf+I87ON8JhCAXLHw6x2Kb6vh0ikOrI5
m7pI9w0ZPeaQjxLr76r/0BIMOlsVmkr0riOjNvA4mN4yNyHKELEEQA7C1W/6/GDuDioSl4CJA29Z
/wexJBd1xynBht5iJFq9n8L8R0MA90xfujFCMxBk8lcmablkoF1GeVrFnjBWFNk6HOoxmhbmMiv1
+A8ZAZ7Eydngz/QapqiN4N1vuMMGSlONaNboucHeBL6R+LX704oToLicHzXAd+k47c1x/cv2Ni/9
J5OriSWJ5K5zMTI+c6UYYOT8GFjAUXIbNSQ1nq2Nm5hT/nX9Br+1Hh60O7fXcfiDKyuot3QQM3TI
NUPomhhh+kUonfxkzV+tXyWpxszF63XQ7bCFqf3DBKW9jBqE1YI6T/R5XiWrN9nt7f+csqdGLx/t
/6q70qTSZ0fXpWzpxoLmwmcX17DA796kDWm/ncAU2rfKB9ByKo26jsiSkaIuTBzsJSvth89acM7I
FZoRSKZWyKcIy+eTvH/fUjbVIfhjjj3VLwgXjbt4y5xAtBJiv7RkBDdS7eE6oMhFxXu7SY6Q9nXE
OPM0DxpotRWXPUBDAt9wHSP5ZFjaf14iGMObojUrNDr90jzWstdJ4yyRiHXqByDY+Q6/E5QaHXIB
FxDCNwqefSubQH957mFBlb3Pc/pG0eautvkSC1ELkHzdeZVyaApiqbpCMlWEV7o9mwsGocVgiD9j
uUoyuPdxJnBQMzLZqWKj7Fs7h/HHcrSXXVS+Eqqhjn7wcV9cx+yYb0KEn7tJaelhaoNhzgfP62ey
HzXFdVi/G9IFiNkoioTfc513HfjTh5+fqKIxzpD5aqVOQQzN374mdvB7/62VA5Lmhp4J3x0euwGe
xcb9iyzGCk6OXcxIwbwnYTLXeVpV6mnUYdRPN4n7fDXfc7QSO0wLE7AMJ9fNLktAurKG6/9shBEz
DmppRd5USau3lsMsxNzIUGqBpDKu/UBgioyzK2JcvBuaFweYO4WTKVIQAc7lNDB826B7bGY/e2Hx
e18dYMj3+KpQ+EyTSgwdCp7PQWLB89Kudcws7+xqfWvCqPfdrJ1OCCgF2mL8lv4QtDEj5Fi61pFS
jzjwN6tPiUo5yaOG/yep9Upa3wVvLDF5P/TlGB7TPcv3NQUe/dwcyVA9QKQ1Jydl/nVH4TJANGGU
kVe947FzwrfWWbstye1pL7BAI7UpsVFYK9Jr86zIcsM+ICKxWbn24nKqhmjAMiBWMlXQe6/cV7uv
YtBy5FSt1W5NoQSvbXFTXcCvTu3iV5X2kyH+lDqbemJeI0UKOyiVe9qNKuf9WODZp+sIBZQJwX/z
6FtHZ5zbrWvZ5rlidCYTeHDoB1IMPvaIt/pJ3l+1gB5psBbV2DlwNdDIYlxT/ogFkkay7BkRl3f3
0n9uMSsnmF5sBR3pHnzHfG0b9GxDpU0JTtlj5q7VE5n7jzAd7J2RUCfaacGxaXpdcFhs8xk/4tWF
/gzaWRrKrXGpvqJtf0gIsfX3JvziSh9FJwkbTpgknSL7lj+JUnSWp2VA584wsjJiprtwIB8Px3vB
XlxEsbl08k096s2uhp7GTXJsZsV8z9EDr4p77Lk4odX/tVkmOLORBMgGYOLgsLDuT273nf50goTU
aEjA+fKVC2oJZ7JDupLvFJj6GzCt+ExN5YUy6N4NIVcMV0hnbjFVZTc/swxfGee3kK0g0c2StfDE
ToVoyJX39lcPETj4udDINOHDP9k0c7/h9vFyKQGeuRa2+iM12+3Xz9PRhzeNGzfsrBATeRQVxLjK
AqYVdgriSD6p2UxCw3p6QEQoflk8DIWC9z1EbjvdmaBo3nCxrhMdBqtBmThGsOZmfKdb9AUcsZsN
YcbQzfipozbGhja6nt6FMhRma9Wi1L2dB99Ogcv6n9ksykZFtGhr98FN8MW9Sz76apkRm3pBPUVY
sY/O7PiyOSehjqkBY3JN6PmjU40f9oUyAKfpIcxqA4TCsYGhL2N+uSATtHWf9xB+R+o51DO5GlnJ
+JykR7KECd9Hl2D/9aDyoooneFcZ66+XL72+TDCHfDevVBPYg13I+DKZpMvpiG5l9Mmd4XMJcJGS
919jeQdC3kaNopDyDF92CBcO6c60I8TDkiFIuVNxPQSs+tm09ad8HGCzrr22eUb3Hxgqb8l2H6KM
HO71foKRMYDD/tC6GCjg6/amb3zAlSeEKqxF6EpvKYM+IMWOLopFusL0owtsD9PfbP/f9/vTWkZb
4468ogDL57Req1Ad6ILv7G6dcToOdFAatu4gj9Bc7xqvODHxIvVnJNDXKfjDEx3eaNAR6EBg32oA
wTl7p43DRWBuk5hCW5X9olEsTYT96h3EhlTAX8akDHv4MzGF+fGglgkmNy13LwZzONrqqyPSXRlB
zcZJDqGxrxIJQvmgUCX/JGKQpUnkZ7egJ2PXvkNi80OfD58KDgy2q9oLdIbXaMkYcQ8L8ETisz/T
YhQclFXbbRQxfmSHMBBzHHwiPXpM0ZFEBy8eqX6L9e+r5mZqlgc9ZuGj5l0veraao+SGSWfmK3vj
JGpGCjdfO5ioQddzodOvZQu6d+6BRYXGo5fP63yKDvaXA4IrjrHSZ/Sj4VcpnwLAI2em+giZMhJM
7PpmjvBtpmf4n5uO6+yhL7Ta2/+D99JxnN6EjONSXHRQcfGY8Sffvz9YYC9lxdYWgnH+zZ0NQGfJ
7jRI9fDV4ivm+3cr0OZg719pJdBEzZpRepuuC8kzuakryRxvxpG5Zj5uB0Bz19O5Kuxzgo6S2VJF
W66Wi7BYt1iHjpvriDGnxCWHDQEbfORWknV58xxwsNBmwksrJ32ie2k4dbElos6hDJ63vvxDbytZ
08mvPV0y2xC2VMyITekJUAzJyZvgh+8vMwLRliDmAXkP4ufVLvysmylKNn0v56r5eXV0B3q0Ng4v
HKQVJHRPNlTqQG/IquFGbD9G2fLQsAEL1eG220T+j0U29z0RsoksAnua1HGi/lQlNeVRGO/V9nwE
upBiVLz7b53JURenxdbmRix8ftbo6Fe9HaspmBqUrKBKBqmL45KGhUhNgIN0Rfic5IfwJ3fOrCZH
HQCOAm84JosECjSCDglr25GOYMRSVYelTz7sSxTz+OO4nfRaVBrvFaKo1Iyix2AnlZ3uT9GYDQkP
pG9ciZdYy9uhqhdoANytPEWsrwspBR1utNfbP9t5EK0fu8jImNzzEzq044Xi7yqbM22HBa36McLp
xiTEHYxo+qlguumcxUmaKAoW2v9Bt+EgMVBDE1/kMpTIkLOBfr6Iv0UAn0FKoieSvKewwjU+qPHi
Wr/E0fkvDvFzQ/eb2i4nCKeGKgy9urUEhH4bsELnMQwazotzP2wD7VxmR/144Xt/PF+r4b/zLJ6z
A80eQEvXcKbU07MI/uovXCwCKRri7AWysFkNFJQQUss6YXZHfyNzFF4m61WIBRG8K+Rx03ntd5kh
zY5EPiDLMIfs4vSB8vxhnpeC60nqvjs2jkDTdPxNoVx9/NOtm50x1yQSimF1tn7Q2vSgE04+FZ8g
Za04zKMYG9aiUhpDHIByl9XKDSNsHIDgqXTSVaGgca4tbRRsfECveHNcVxN/FcUYtHBWYyvAe3rl
Nbpvk8x1OBs25oika3bL/JV1P/7iUnJEqdDn6VRLbvOg9yn0n62VTuYhHfNBnjPq13+GC5qEiNo1
IOtpZxoYuUIg0fsxU5eNdLte+ix3WqOCOqeJq6SC24NMU+c6gmQI1k28P9CL8MAuQ21ye/XZNjr4
00Ay3VbZdMPdpmQirgwbtbhonf38SXF3iqvpHgDRnw6TBEpkcKV4me06ZcM+omEf9PEWJSUO/NDr
7QuRQOqqAssVVPZm04x6JDju3y+1688hLiFIS/qQpYa81ngfJ17QsWci+Wiioukpn5N6uNM876A2
6pv+r/YpLm+RLnQvwVfGXzKsoy1KMZ7CeA8Eeh16AUXyXehFZGESQTE3dXXK+6xOUCw1E1oeFl4B
WZaGxXsnUTgFzHn1KIUoAxrie4pvhAXssXIBix1fnOVRkTYykWJ/dYUi+6PpAxKnWNj+rDAEjnEV
gPkfDop+/5+ijmccrO0b6PEEvgUqCzWQk6ENNRRSMMxetM4KBYZhc9w4BMEzBEY6vux/4h+2eAu4
GtSDVDqHtDVHbl8+EWqwh6zCZbaOpWi1vjjBAl7oLNuTxi5/uce2rKfKo8VTpr1HL/P7i0ew65MO
E3JfxkxxGcRsnimUVg799hhj+rFsm5YTNp28G7BDQgPw1gnrgcD2YQdAzXYyRGQa+LIrakeg9OgV
vDOHkgXDL+45q7sEtGVlFwYGwApDX7GOgi5Z2i/EXThy5KoiVhBI0abs3a9HayJL5LjiuY9l7NLm
6fEPXN3I5kaDquTSXko6E+IMH7D+ovSG6XkiHj9K5FHDmwI7pwtUOjV9rl9mghSHam/nXKwguqfv
mH+w3wOgBHYJ9N1RJo0YG6F5D7921t4FYvZiyhodXQ+j3WCVuJR/xKMmm9XkxnBWftgknZl97sHR
VJYm0dIY+Fl27xCh2svEHuigZqVXiOjXpY0qusDlu/3VswS0SMy0VM6html+f92dRcfwZW0xXm9e
ccMd7ilpPjdvSIhBBU1SUe984hWiQ7If9j1RqM4YvBDUuhowy8xQzGPLSFjqHTK2QbV13JEUY48v
6+kHUUzpOzoEghO8Sm380cEoseCVVjnuAlKD3HsVUO6wOhHSS+WoTKtT2enCsvuEG28+/6flj00B
9IXM3iflX3zisFjXCnCuSRhZd8ClRS/Rcnzqt+zzZ1z7xgs93pkmWKuVDEtKWXSu3E3bQjV9CA1N
bt4Ozh9YBv0OqPJ6QKFhZvEgax60SX6CTlz4fuSeNlVgSkdFbgnNz92FescpfDSXDTvs7AAm2pBG
4X2XlFYuYvxZrnQaKqb0KFyOkRrXk7zbMMqLqW1mhY8+GkZlmg/3SEIb+geRBN8qF/Rqbc5TUlib
ZMvBIka6ZiCbmY6F/uw30TQYujIEcn8vGEZt8TOK/E1EaPPGrAdabCnkrjWbZF0v2fs114XSPTuw
QEdFnQ5vjGLHkoUdgTrs/ZT+F6vG5M0F9zGiE0Ntvf7BPl/8v30AK3Y64ysHY2zutaN+PulgwksC
sMX8PZMBtL9fDDLL3yGwmi5XpsFNbyn9fCWWRbrNcgo7jOx0NYd8mHhoIdKJ+GV1p7kaVHTYVLLT
9lk6BAn5OR2GCLQCxTRmGGLLwc36GDFcjHJZBFVLYxXhVP7j556u2R40IepisHJBeKWbCmOqmpz8
z+l2aGPubpXfYHC4YRnx52VbE4ft1bQ01JYXr5C+oxp4utNc1E62MzVie9qoVy0vfdM+JgJbscqP
eSse0wg/wdbG4Ztl6xJhKZEwLpqOoe723g7JJxvav9vk/2kfVejxYgK150USh8QhA6wtWjb3k3aS
K/bRT38SMGh3X+mKhkgsMDpP/z70xTQF4fNT8eAIZx80QiV1jyO+FSK2uezVYHIAtH9UyaBFYn7n
+9lmqbrw2sr2++eMZrNxeIfVJ6rTxXBx1RXtUG9JdKMKeju5FkM7g/zyU1UPkBIVGssDvwlTDhMk
jdy94/dVNknuMfmfgUpBgoBFEDP5zFstj1vCUQlCPdYfOZ+wZtnndQbUEgXDD4x6STyP2YCSMLeh
+mczLlDbPmvsr5rssGHd283Q5ZZOjxj4PJa3jncCSFKxdIuTDrS6qrVN6rX0Eb5qwTgbZGgte3qb
TTewI0WhlEqJ1GL1zOtw0eJQFLYale1cYaDFn+ZC0ELYCqmMY56dN4DVj9Aj1muY0MZK6qqluD4k
gXLh2ndKkeLfXZZAjapUcTQEwQZsqFk4D7YFOG6xNSVXoJniITT9FLP/MQx5F5F+X6NrOiRJdIpB
O5IseTrY4pNH7E7M/VhOqx9jxYG7X7+mwGEMKE8e/39y60QpIiLbDDmDs+PtirL61BoPP094m1GW
PD7FmG295xccwqHfhuTPmXrtZhrWZcPwV7cr5Qzn7KsD7hKETtG1NYZPSuD3KEj3R4uO9SqAoQoe
iVbWa7dhXzqW4dmBJEH3ms3gsLHiCT3E7Yx8j6J1Oj8pzb8flIJInIpVaYoj3d7YgTj33myhKL3s
Xo3+iCrh17907bY/RplQY+2D5p5NuY4wujUd7Rv+EmhtEEhAMns1/NAE6PUaSvSkJXktIY472qBq
DpG93eIt028herwZks57Tzpy5f0bUXjV3TvMkilqLN5yzKtmciNFx7jhIaphnin1DW7rWGLeupMk
Ca1CwrsRJ2UUhCoykFVMyT8f6ijzaTykwKeXPPsj8Rq7D0uO3HYREpHgm2PYKvSConTj3ceiClYB
hStvt1IyD8MF53/3EqjKzlPt6FIR4cTzsyWCH0FZcj5tKlub60bbMRSNxd0YgBf/8WxWUtOUxcpY
UhCc8Vo1N/bjrKVwrf1Yq3OtyyIzsofr5wZMGdDE35sKjncqLsx6Ct6F/15QGrjLpX3s4PXBVo1F
CTLeVhLZRWn9ib7W+J4Brn0aIzkDbKh6Ky5vtL/upwYMMvKM89h1fOYWYkr56+GMe91ymzwuZIpM
4YXveMAgTdXFldpWhfBZyMHGiHFux78v/qit/gkAZOnQi7EWyYIOAlNLVuwNy8SaBMKqXuDweBoG
5YgmWqmfAWCX0TBNnVslr3VZzfyJIqJfvKMM/gx4FJ0f+i/HqSt/qOVFU/kGkRrBD1y6JXhtrQz6
J66e6k9WCeH+RKX/quWU3Lv5xHZ7d2vaoYMKpGsv5e1xqXSIrx26Six9gQYdgM86Ul6tP2STn2CB
/3Y2DPrVTEyAR2vWC0m4dAAGBw2g5jQTJMqPoN5ZV8xcsQha5AKnpUKBIjFgfKRsWNghwpz9WVqu
s+JGKbGozyE/1O9txR1RIR6IP5yujGVAkIQe1XmzmOzAVvkJg48P0poCPFXON4he6/Id+hskWSdC
rtbFQ4+cj2LWng64//+mDxYA9im49ZPZ33aCimpiFEUpch8HgYGXtgKheUuKa1/+dFEogAZxyvJH
yoLfcMmy+9XBTHxc/Xq1/Vsbb1dCmVTMD009Nu2yCeMy+8wmgYMt0/+Qu9zwYhfaH4PTmuSE2oUa
RtwIuWjsEz0pthur23sjEJep1HsZ82hPYUhs6CrGbynN7X/qnglq3crawTkBql8dXXLIgXxRGUgl
3+bu+Y7VdTtwVG8UV4K+/5zmR2Mx4/vDu8oDXVvcvliSE7EUGlHmA1g5NBMnqJJQdPDbq+ImHP87
Rui8/A37Si2z3Q0JeQtTr310HpvLTIEs118PRhvXVMFrmE+HZBRGDn2sASph1kvTjwC/tDtBnOCj
ztsASs0kJsnmyRpdvwwfMCC/YTtE+/xpIPi3nQ6lMXlA0HGENJxWfRknREokiNXeNQuDv26aQkaN
XEzTXSCRepKLXFrfs6t9s8c3VZL4r84BgBKMUXJTnwRWiIX3N0qsMD61n/psrgJw46VQhQzLYE2L
9QL6LXdI99SxGLMcVenDSHboVWJtqzPeo0p7xubmh2YZoH0kfoqaKObGMFh2HnXyQs/so9jzDF6L
6Bi15J3Al0cU0e2Lvs4+QUKlaGRUG78qZcxf0Kehi1Z3Q8TlyoQKjaCcYoZdCMPISKozD9U5cQy5
8i3XxGZW02L0tvRIcwTOFdNZdQqjD3MQ6RNZ+WRYmvjbNyA+x6m9G7R9nEO+SAZolTGcLM3I5gC4
qIF6QFzlgP3g1cIDcx3/O+W7tqCv0sboimMO3uuUiQwED2rijcOYmxwDCaQIAA/rAORAaXuli4ES
x81avAs80aFlJ1FX7AjApDP2KkctvQgHT55CI/8b7hxVYfxilo47NavDyn6TatyohRl2f/lYtNPk
EDNmHQrt6k0d2kYoG65C/km4f2grG/ebQi+jswg6DqVI6Oe/T3C93TFnGBHsJdBbkoLsD98dM3tk
MzakdC8BtOCmp4KLCu/Ir2G1834NXgfLUMMNziLTf3pcdHg75tNCvkc3n2+YIuqB8sG0AAj39zh5
IF7dELhIP2S8CUhpDzTrFv1/HN7EBbwPkiWk3BgOA1vIFfKhWxLE2kXnZvfPz5QZfNkMQr/YS2Au
u0VIxlimL5nHVvuKm2Fi3Dgdqi4itUf18H/8R9Sd8dRBjKr7LKfhhyHcT9BdPCZVZ8AIUidcKkaE
r8qAtJZ0hRYWqsxr6cMXw0TYCAW8FLDJ1ocTSxQu62VFAIMuzuJRIOQbK6XPG5Kj5GGfUAcM7ZqP
9Mh1LIm5G8PMbonC1eaVyil0HUWyNVm5rkxv/+tAThvn2FmGyox2c2tv3h8RYHbplUczugTwZqoO
boJMWxAvKEZLoQDVLkJYVFlZFoEGljk8qmoYizve6HoIUDz4ws1KCh490cSVPcoFnBtLtZFrG0CG
v5Dled+bRj5ovtgrXW3USmU628NnFeXASLdjsuG1JobyPrrI4OFrVl243yL27hA31txkSfrsYchk
09n+fj7k8zkdUmgyUUik5XCNfpygvUzfJXaeBgHe3e4g0latw4qW2Opv2O9Xles7qVzPXoZ5Qtr8
Gd/3Urp3vfVxOqxsCu7WPFF2UrkJhbzthYkY6/T7zShmyFx/NgTrwYyDe8/Vcpk+dvBDOfnfMQFU
OjcWEJFR1P8+YhUlO0ma4S71YZBxyS8ngirZ9ZcBcyLx5OSsEkvRpd36//jOSQrdEU7M25t7eenf
GuDi09UTmi+l3EDeISzXCJfhyUKNF7hjk4AMc6ODn/2Dw7iRMNI6veDAA8R7tO6IYi8Ay/LFBykZ
KJrYYDIDBj8LOrRF9b1SQ7o6M021Yj7xj1n92EPnEz4o6nowZitStDwoF20v1g98QPYthGUqvJAC
UgZAxsSiPu00NE61rZE0aX0IBG0iwASV9UG3ALhSGVPgHpWJ3rc4xWMlL8STKOAswUin6kwjaFPJ
UA6z1XecowDDTiu8Qigt4WT4TqsXbJNE2sywQGKe5Vo8uOPZvTfuEwRbHiwG0FRscEk+Jz3hPdkU
hlb/TDWPC/D0mLmNl/PdatlDEV5A/Eu4Pt3dfjKLLRaZMAV//DgCBX1cY19oBTVq9XELjzzG1dsL
J2qqj8j/jcXZVYvaGYrLbt/Y0qjl4Ey2rbx9sMVHEQUFJtuHCpiQjMa9ihPEYB0NRz5z1/mzmh1t
pN9KsyKFayzQO6kE7msw71+0V/T2NfBrV4bwLWFbs3fn9qS6cCG7qwle/dFzPl8sOHdWwwn3c5u9
3iUeFWXlpvE+q0XWe5H6IRI+ZtjeTOVLj+Qvvjosi1Cy8ztsquO3VIob/eWDOWCDPRJBkwV+JXh3
oyyxLd5ZQDpsCwitRclZsTeHNIqZsklw+4D0deraKRLD/bSq2qZ06U7YNu5KURvR3HaMb36mRvZA
eypphKGNIDVCA9qWY7drtvblGQqNcEl7lnx7w3HdwzjU2PSRc+wYF/nqw6Kkne1idWMl3iAoZcLA
igzpc/YL77nMyTpkTEZk5PZmctLPnIWlMsOa2SScS9BxYERi3XHr9ItrTstiMdOhMJTaPtNFHlNP
aaHMg0FBx1C9zsQerXxhwA/BPxM96iyDwKumExEkp8h4eomtvMHQWKIZLlQxCGc7WzMqKFwIT0nJ
G3gFh0NzIpGJ6suoC7RGX3fmP6SXrywKYF1/IMbt4mU4I7KyaD3G1Lpkd2kw/qBAKLR8tTSprGVM
4Yex9BmKV3Ug7mcbtEc3KbHsiwwQtu2+Ojscl/11g+O2u//dQG3MSgJIpdR4aDGdrrVfsNL2Ni/c
o32lX3UtTIxXUQ8STugb2Pu4pEvdXO6edU7FSEal5B1CetORjSItNrj0TlxCvyixpuSdErfWd5fn
jxhMKhR17/gHZvrWyZ8/4d82S5plY7vkRk2vEDXT45BFrjNI6vVGbk5vno+qNGYl+4zDNe8XKQ2c
ixpjjFsR7BE3xE7+E5Mq3Aj2MAgOf1PgjwIwlQLflsP+gOom16hN3/81akIhrxp+9yteVYEzIowP
0LfUyAou+Y3RzPOGGXI1OjbMghbWKIIf9g4ztk2lTsoMJOXStRrKIO4P0LsIeI0ZPtPp+g7GkHfQ
mtq0aMciyoGNq1wPagWSmNz3w2GmuZI1d/XV+iwsjsthFURSHvpnaG8P63sIVVNkfUVJO3+OmNrL
5ysuWjy0ADhSZdOyPp6nUnvgYoW79igvcXYgAp0vy3PGt5RbWG0afLjtt0zBk/4zeMQBmEZ0QuVn
Fsab9+pBTyzj5Tt/ckDXJGa9h2Mn6XTxZiIjHCWHONuxftjeXkIzv1SL+Gk8P3+Sfal5qH2hQbj0
pYuHSGFvSohrk8NitCWH7UZzmWSmkeBt3PfTDIUR4tCdDDxP7hlyGmXqyGgUBaCyHK4zXLRgSzwl
ALRAEYRNw2Hgi/5vwBmqrUT9vso/lZSqnggyYfb7/Q/qSJ8uwGiljRnV27HMOHM6ElHiJZfZnwzN
OdCn8my+OFIe5PQVw7ngQ9vsCyQPRMIPndC0ELlxFFr3wrbm325R+3r/JzRlQo8o2ZGiFM7S706Q
LNaXuZ8CPnqPqSXOd/A6YA0tDZpktjcFeDXSxWErMUZh07hkQYzHhPawitBG3AB8ntp8C5awANeJ
x6p1HqAayf9ITkGWll5yGUezhHJvtT5QH2ziNtfQ0llU3rdfiU3/WDmLiDsbpqQZiSeVB8QnE0O4
QaREZv/+psSrKFQCUII5aJjnO/22fyn0VvIKSyoYRzd/jlFrMWj144fGSHjTHL0TtP1YVX94TUdt
kJYc3bVbR3X0ymC9Sfq6Kz2VIoWArbpxwDfISn4FlGamMa09bk02OK9Y2CmyzBNXhp4sqAyjIxjO
Oh/+Jr8WvYQULFOug7LxGWkTvZWR+zSpCpLQhgbQC40DevGVRPak8oU7hZsmI0T2j5DsVGoP88PW
67oOOG641h75YAI49ICkZDUoXEldBsQWVq644/N70vri4x0RNSkne9sJLs5fLyz/VqWgBsXy4QmE
lRo+cedSdzrrBAaXHvZTbWJKRHDxujGxclqxjNopytKVABw2TWFoYK7GHs3YIo4/XFhX4KwZ1UsY
88euR8z0CXJlFtejwnXQ2WZGtJdU4+mm4ApkMo04IXIdFD5o5V78sejBZknqRJNUN43XTYHShzEO
lub5LHLU2GCpmvLKc/16JLt5JbYd8/SXo5ZByogwBW3vkQbW2G9ERZJMVU/S2x4ZYrvMSxxdt3nX
u94FbKz79GTB3P9pvNC3397r7DrEP7iszPh1LzpJIPczwZoRodU1M74LJZm5rvudyVcIm1tcqC50
XbQt6MXW10EUJLbT/HuIc3Fqp5I23dSdpSoBwy/odQylkTZVXUvHmF2mBxYTUV1OMWCj6WylBlAt
p2+cXu9yZnuPXd82OwXB9axkj1lb9XK+tXH5GfbAG8VKUqCQtFb6YNRDpf6p8yRcEsP1oNywWzaB
n9tWpDvu1PkAXjHtamIYmIAxTQ4oB79rcuU3ob1BbRutUgLdiB6PxCxHn58vb1qpWTaH8Tb6wh6U
HpTkn/ir1eV2PqzKVn8BGqu7mMGQUpCkkCC0ajXqSy8KWzFaWj79DXl/Z+GGPFYuyKAVqHNHh05e
UeQoch+2eJfMDaLYXMZ3dWxRpr/0e3/jlhZYc8zx1LKgecj1BFx6bxg7FblrwMRRSDvg4mTpxrdR
VIZgJa0uSPLFz18EVHFf6InxV+SYwVT6TfCoCvIVAXiv4f80qkxRS8dx6e51+6AK9bSMdV6si+lW
UzaU9Kz4M5Mc4QkGP8Pe13UIJ/2dSeyhzMQMlo77+u4qPKb5vsz81Q1g2qqrIyfSbTXS3kcyogeL
1Xz/8DvZnzTY5TK+qOkcG1WBuPAa6hwqk2SgU2TOAZpgZrJVNr6w22xnHVoXPlt6on1ZfaBobiDV
bqbCsJ2ks8bIPP4j7UQWQUOlOuj7dXJvZfvd61INUfhL/FCgP2ERXblZqCqoQUL/znkHMXKpiuE/
Zmr5KA2DrEmY+5x77Bm5A7inhAghipUakEKeKN+436LZk6NIQaIFyhXjcH4kxltuu3WvLuc7hTgS
EMxyCF3rCAkdi6zYu3ULYx4sEVHprv5Qu/l80f4IVIIZXa7WmMpkimKtmSNjPplH7ihQEnenZphB
e95/Z/KwX0f0TmXc/ou9VY6BdwUdXt1ezjoJvBQN2IipFEZSmDa02a3UgVwwuH9XSkTP4//QdKC6
dIvqLSk6ZhxfitKUZ2oD6R8FAuhjzRrgyxBwxQ7scHTt1ynRRin27G+tbxf6SDra6QCCW+aG+jR1
5/mJcMevf8s31Sc4YBO7o02VPlvIPx5/9eD7Y8yyvgQdCl7ZDxr7VoPBH/X5jKASVp8vA/ec160d
rfvKVg8MpvMNNMuadDcJHXlt0eh7+0+2UUU7nwxnCDvk2YMUvB2okZ/C+UvZoIfCKA+P5wghVjd1
pKDouDI0c5S3fYJ6Fs0THPK+ayk1TAZC+fEKrJltyL5q+HAT5R0FT3BIVFYIbBrvAREB+sl6Q4ao
Gw/qjLzDPYytZZjlVxwCutDc44KT+/LB7aHRAJ1lL9E+iV/4+LqeW6eN4fGSAx4LAWc2bHTRxTRp
4vNOahWXidl2k/eFIyfT4pF5BbUTO3EDw7JF/ashnF/zi498TRaQzUHPYk/Tw/w+PV/Egld5Zs2F
HjdvvYPwKd3r244wklVZzc4DJNdG0ziebAR3nAVAb68IOwsap/y07+yTs9ejcUY6kvrS5l0F5JC0
ITR72EIvHqg4K3tKVAKjgEsQBSe0axj/bqhmnEAuuaWbU6k6KOljSdPfDMxkcvPbS46b3YQcWSux
CdaWI+46Ria+VFRKuxyYyxHI1Qr0DbgFGbHXfaAK7j5tG1L8p9BOZm2Qf/FE+CX6pq2AlY3CMlM+
yMhBpZ3/McRS/NjPKtr9SUU71ZTEkuDz5xY64PIoFN4+I4O9QEsnu1qAljFE85nJ26Vqp9UzohOM
Z+rS0tIiIUhV/dFpWcUCI6rOeE9FEOaUoKP6E+7HdM2kzFykPOXXLBDErGPkJZIw/YPAGLS0QZ0o
6r+OQkm+8cOOgX3QkyDNNEwEVNIuGUQz+D3tRvvci65if8gFyMX8PwemLTlXOC1pgBCqaYK8Z+WZ
4BOuTm9JFtmiZF3ygJb3xlvH6M/JSq6cF21T5b1mRP8yPrrbCMym8CXnk4DYb6Fgezcoa0Lrl2Wn
tYH4SLz9Xi6qLZtCU6dYdDHRPPjG0qpHMI9HvcMTee4QV/ych1UxE6Ga+BpT/DMe34r+wGY4s5+u
ZGNudaQP+sB1lT5BS5u8z+yrN1kCP6DtciYlDlkRgUkJN6dPQ57+Iq/7NzjOCOIKBVQ67WyxWWxV
4nICcHjzJLlwyiA8jwFHddFnf0l1WugBVqHkDS8OOF74ZUH6TPlMe+Q2X9ZE9JLrw0Yrot5t1QZB
tuM7HaPJl7eqj+9rm5QEdsSPPjA8Vtwum8Z1RsyOZtKFjY+uhd4j7E4QFWs+D8rE+4vO+GHSxTMs
gqM7n+CgYID3mhXkyWNXkFDRepVzGobfPEsXPGL5nkV0STC++GYL+RrS6uKQxKDVugMVuI1wKGV4
qOSzGZMPuM3K3rR5gaxVG9rSJmaYDF8CGXVN7tyfeWPfWA5E0JLHRuOjJLyvuNX5eAXGqf9TLY2C
fiPithHFTdgGbaid3l3xqhT0x6sD0pFkxCITGltKPOPvBCy1clFhK999EcFwGubKiqYzxrw2ZBH4
lY0m5HcXQKUuENpB/R03d96IzNsr9Hn501h977kh6yjW1SGUMJN5cWvE1vb8OIkqZHU0bDJ5g/QX
z7I0GCOGsVHYnPkJVxy1+3i1AOxgYuH/dJVyu43VJfFR9m3Q7QFeFYfBbjcs4CtcsM2DuQRnqRBu
Ktp+loe1la+GkF9H8okbcbs/40bIwKuv0wPQ6THOn1DREuS9GijufMjMGmsTe2GjO6nlmAubgPu0
kRAXd9MS+0scLrZlnzeeDMzvnx8A8NU3eTqL872q7qPhLnDWo1jZqDimukibGLbhtsNpDqjtErtM
Np9xwiP3dWviJuQc0Yd27eA35sZv3vkHfiMG1CghsLUepoUsfEC4xnCJC0UY8xJMwJtZ3/zG/yWk
UgJRDfPsroN1KPgexm4nhcgEltN8YpTCWxADQ1bvtv2B9pilXYPM1YyC73+nbfCecdV3d5zI+aN4
zVKih/aK+vHbZ6WWuj8KGgjNPy03FmgdoZLrj8CeKM7gzKdK67DDCvBjJae/vvHYfLC7o+DEob/B
DzR2v5XWDhqvSrJyaN72f5N5mVu6xLJgq5OHWcSRvP/tgsytJ0AqdxwTtt3FeBOqIEmZy57A56aN
hXznm++k8eUn5tWG58BJ0JOIZisSsoTVhfpisNVmrDkQk23T2b9Odil6J4Ek8UdfexCLcOaPhtx0
hlFh180wLyq9207bo7TvSXWnIez909WwEuV0QvVUbJ621TotcOQO7DZPivW1ekkVtJUP/Ry2lzv7
lK86bkRAlaVL3zVUKrApe/XL4H50j0nkFng70pCbYAMCKw3B+u3w4bKA3+RbPNRqSP2SuL8MvhVb
j+f9wusbfPB7aCeAU3fNc7gYzjfLnGUWTNnfy0EpSg397tKLjYg4AXkmsFsixRajlEKpo+Us9IXp
nXp6Oy4EQDidzzh13ZR6hC7k9fwnan5X0XHjT0wq8twtUiQWU+R4dKXi6FlF2PrPbmuIMTxGP6/g
+Us7qV2xda+G+bRVn3VB3fpd+3OMAgFopdqCs4EA+vy0nTKqTtzh6NR3ado/mB0cK+H0sd5g+gUe
Ho+jRX1ZLB9adH49IPdCNA+soGU/nY4FPv8Jute/vi20bk78HEOmCXmZKUxi7KbwEOePsWwZR7bw
1XljzFe2j/hZHUw/cU03+hwGkuU3TMIhht6vNnvfkXG4bDJ1CqxaFeSodnaEy1WFiGDl/t8vAAf5
7COAIwHYBgymxRHJw7Ev2+U2V+q15iBKILNYYnhA0CbZQmM77EZk+4EyguUKldxmBMem3JNhgnxp
0wiRSuFsbjZt7do+/pIlNEv2QM0YpAuSx1BfX+J5NbIqAs2BierCYalyITTuQ89PElrDnMAVvhiH
XpNXN05GbgNfPX3BspbBbcje04TRmUCb1A+gh/ieD/D/44s5TyBna7mU9ijzQ9L/CQWVjtBW7ha0
Lc/yujcqt722RmMFfgjeavMLjvdO51Qt3+TyilP1aIEq6ehayi3dbtInP37hS5k2S4utYB6GTGpj
DA72Nr2pE4I4TMz+jqCagmBvs3limLjl5D70ecR9Cwcr+agfTVe2Wa/QQ+u5awY8qrkU/xOGlfEK
Gbuyfm0y/rG08Nm8k9Y+0F82/1YYG+PfNNJJBPCp8rcxdeFIqQ+cRrQHkVaWNeb931XmT+Yb/fQ3
9la3tpBT4bWYLYe5mqW4xSimP2V50JcQ9p6hJuRlun14JQZqHhiUejk/wBOGYaFVOO+Ulg0Uzhen
u2OgB/8HVmRLRJqYMyGsgwHBBOOdP2iMb6jCM/sTVIpbexQzxbL1uspdUOpVajOaCmsbVAwQjcs6
m5c/ryzxxH6MRF2ZvKyH6h85dW3mcIVqcFWw4BHcEnG64//cBziPTfP2md+kNzrGgmzWoSdsAriQ
Kv/VEyt6351ZFW93+lTmXNbybXjD5XWcwU6bx9/2OoQP6cXiP3DruFPBtLHs0L4YyN5qKmESDOqZ
2aj50tkIS3VbpTOM0rdpLX0XuB4QeviXjDe4UuootcpElIQKJZ1d20c4FSOQFEXjNDUt27Iwcarr
M9AHvTnkju5GLPTwrNU5+S6OOMO7gKrRmouvQA7rYJlwFcp/fhAU07VYrDz/S8Rg5t47rMHjZ/wm
BzsduOt8iZu1argln5IxTOHt3Q6WcmiM0E32wNGO3qq9ROxALB6zdPrsdXzKNrRno/OoQFC4aDHZ
C3SiqTkU1r2t8Gff5jxetiPCVzHPChYzEBwwnfa8f8wz1moD0OV+a1ZJvuCo50t3b48VqoTLESvv
CjbwlBZ/6UbXlzuSmYD3r9r5eTO7wQOL9v+kLln+pmjLHnLwBcguLyO9QwnGA2l8moBLtp7EAmw6
G3cbPra1pqd8RXCmsmott1JSLR6pN45CE+vp6fSG5o1UXp9AwqdUpBgLzE+jGnT89NI/Eyy7TIQc
mlkpiSzQ4rNV+tfqyG2IixpIkN1F+Al4z7T930imOqupcVIpI0u6L9FN39m5LWkKpANXZ+3DiMRG
mgMwVCLaucKwdPNwTGTTF8ZhOkQNYQxLTSWX3A4DgBrYQtJGfE6lOZNdAeHrzQkv6nEIDeOWVScV
kxify6upWaolLMuga/3iAwv/5gTjwlMBmpEipbJsUs1ByC4tX05c3oi4PFTya68kCVKpCVshgGU8
BtkrxXegYJ44XD1BEa8sPIoELM1nzxYzfbuj+FhxUke3W70qe4mbrRzPGHhj9d2VrCOvE3mq7JvR
hXDlKT1Uvwxkqmgms6nzEpjeYSOtjcxUnEJk5bX6uR+4P6Las9iT/fXEdCP12kJk104JCiMBfBEE
lbWjWN9bTV0IJ8H/h2lw6C4osCwxLnE8jtYoL85n0+bybhfVcP6h3N0Sfxco8QJQrokJhQZqmXp6
B0kp53Kw8SB0yLz8WJynaSK6zkxR2+G1B/jZI56lEExFvg/gkvwH4RZ7Z8KvOUwaQTjBdJPbVZuH
XJLrGlQtvTA02azOqqLwOoD8tDGRCDAFWw46KwKuUgKQMqnBNF+jWTShFkUVn6g1aFmlsJG6pieP
y4piROulSR6WWhdGudDiOzDvEOTzQCFqKPF0Bc4/z+AUO46kNn/7yA9FWQYfvR1uviKp0KQXBdBp
vc+UEVCHNMRPz4zO10HhNIUxBhdlAFLbtaM8G2buARVAmVwAZnSWvQ+1FCK9p31H0Lzj2Hih3DmG
1JoBw/Hb8goGgDM3dqtBwUbVveF3ECwCWGgJzEaznsLXSwX4navTK2ZQTOzwo9aMgpDPF+IJcvRB
EguUkCZbf/vaKptb3W+ECWeJjf8D2IjxUPw7d+7AZWFjm4NIPPtx5BdU65WRD2cWGwCI7jeAJ/ap
Kl++SugI1DDUVyaL2acZuGs3IONOlmCYDsVW9DQTovL/pgcdjx5XRWlE2cQgy+E7MWYEtMYu/wn4
pkdul9hdcT4pRU+MY/kc0JxcIkq7bP4qdJtTgj7q5tfVBwnakVNro7It8IuZ4DwZKfczh6uaPSy/
x55jVIhsOpWEKLkT1H8WfCP1InLCYdanpEN2JJbxcQjB9DAJjw+z71LDDpMnTczKnsDho+6XegIg
efBrd7CHlT86r6z2ms0xeTpkVfWrHni3yxA0JbtpK8Atby7QcqQ/uy6Wz+h37KuTs1P369oKe7Z0
5iv+IvxMhyoSKRpwLsvUwjUTsEMtH7oPaugRxEZ5NiM2yp6F51v3a1xUI/freL+MzCY1cxfWfamx
oqQsbyKn+66oN0SB5MonS3q4iTrLboPUVf88mIn5kSx31BPKcUWbaAuy9/0VDTprsOCX+ishbst1
J/0wWYMByro73LY/M5VmK+ej/UK8LeJ0xwDXG7cvz7xMEVwsnvjkokONr1GmnpBkDhRTs9LaMs2W
Xsv2TVyIhr8Usw0Suuyzi+YU9fMcLaCgHnLuD3ihc9j18hlqeTEnKAUNBS3WoXyNykcGyqsttilF
fl1iKEMwpcaYmT2+OnLE4sUnvz0Qzd4z6S6ueUcNyHV3svNeIb4hEKXv6DQugd07j/Fuioe1S+NG
+JsGDuCLz1UcvtLMQfcvWPxjjvCUt7vsWMOhZHPRW/kih1KusLtEiCilIWUmwr/07b1mfCCSo3jh
gI3h9VTkHyJB3PtdRmFFECSa3EZb4+T6uVLaE8/kSdMAsdtaM2OAbrJKgMjubqDAh1PZgfzNQ7f0
ZkJ2nNOaYnK1aCodxH7JDIW+uPe52ZXGo8F11MxJf7C+gmn1p33B4+U4jekDRZEr7YlW+hJ+EJW3
JYXmLOeWEEzWx0zmaDt4rPycwMMapcYaSp8If6w6iEjyZHYL7sPQ3V7sXgYJ9BFgot327h385VM6
cV9KaQCWdyJoPGWqUeXl2aJb2QqNOYCUtkM19q4RUHoyktKRqo0XAFzQ5C2xPY0R8jkzkOaz+Z3C
gzV9rxxpxADSV8Ndw4DEYe4iRQBt+Gpz/4QidneKc5LSaoLOcFm6nGA0h6b0EK8NJmRpQq+t6O1M
Z+p11F+BEaBn+4QwCwot81+uoCCoFm9QjMTAakweKpbu28WiFVuRqlL07EdZS+7XzGGpO1na5p08
1zC/t+0AXP8iNINrRajXvToL8BvLcwhUVs87snfGQPCQto0Ffpon1YDncZ0fUVcjoITePu5LBDWc
5XMMMQiXw8IDeHdNRHpZjVNUWfToy5rrNFjZ+f+X2RihJOMDzqpJsGS4+7ZwtfHdW8UqYz2BrGri
bLR5USwbHwtG0zDRPRArjgwkj4YvHaGc8iUCAxqpUtvh3g5/9w08vgOMmWPgsG4pScu6DNLVd5Jk
77uU9QIvJDN6rj8CC3p5etVy20WlnPA/J4WXYp18AzW9srP+N/6P/VovGBYh1KqAVAI1jKYT/xAG
lgPLpom3QnH1Z9lLw/mWcoC+hxa0eozXV5wK7lSSmJQMGUCY1vngfawL155ABziW6ARtEf7H7xZZ
YhpaROu6A41XOLSklmJQJWnyDD31xuucBNWvjzzgNHcehMcvFlyuyd3JOqSzqxCP1TzEPFPxHH2f
zRB6NJVgJeQ9b+RxgOPwHjXxcNP1u83TUR/sRTA+C0Ic11hqHpFpFUdCxtO7OxECbmRjG8BiGtRF
gyYilPqLqsWwEzgte/JFSdO+UScp8LG3aL/4ExHMU0H+2g0dRQXCPsAYirMIwBuBcr7yff61ND1H
ijhaRN+AOkQ+40Si+HP+o3BVe0yVrJ3oklyGISYWd7YvJIBKBDlhcnjJfyqWqsFljgSlz2JbXLqP
TQy88WEFwn+TDv05sCzW3NdK/oEp16xF4q9ylyo+/5uJoPqIxbBFS8hkktaLuUE4UFu5LkxOu/J9
wPXTtv29Z03NiMO5ifIdC6gaG0bJ8BtEoC7f2LWfjQPOfU/7T3QCtRE4Lh1Xe+r2g7wZvRfKWCqM
lPrhm2hPP7F3baDHvD4doe6m526Qz1rIN6jb6tw10bdnxWs036cYpinc5NXTgO77qZSmL1PycnZ5
/ctEtC9Z1Uzh1MWR9WQQptnVd0ZqazSbHv6BLx15kCKV95MVf0gz4JmY0AUS9ddgs1vruiOXN8gx
lGSRmofWrHA3Oi/1J9lgeoZZrAHPd4qS4bfa7YocOAh1pXfYk40wRXK431PqQUrbfVLE+v7xjM71
a/yji2JYC7Qnj/4BZ3BR4FI1facM6Q1XoiILUg1gFhcMMlTfcXQ8i2wuZgLsluVCkVaUfozRHhVB
itNwaZhDfUI+rhPOjluZmj0ouK5nmOu3h6o4BCjwhEKkJAoFKQYW8tZggC+4UfqLEELtQpTYzrVG
rhKKsmFKPIOUPvIz2n0DvJwFA0Vq1UZUZQY9KTfSIX2zmGC9xRSMrOd03uHCpC2wbAh+EUv/+On5
ak/OBCbWmFQoUFsIBpU73PwBlYY0R8FpDCMQiRmeXwQTw5uuSMT/8ULeDusZywYQAc63HOPbv+6Y
7aax4D7UFih8HW05G6gelRskNdTa9dtVaKUhB+aQhyxIjbd91VXVMdcjX5rJwNPZax7Lqrhq7x0x
DGTNBACOk/TYAGLzrG00wO+e70o9OOT0VFSktbQGXutcUbVZp+Y+1vHEuPwuf79Ygk065xGUQzma
Zi6n81XFh1ERhRAzZffCWWhodjUVuFqKC5BXTLA0gqeWcLFT6jpJLqiB0GDLTjAPpT4wVx0Z/z/U
sOjq16JAwpJxxVPKOzezVkGv0dZ6x+DN1BZWxP6kCMxRZzfPZlRZzjilDaneUpTpe9vLbs/HCA6O
icHrUi2kBCEUy+/d+SzYAKSRK0Tfcf+DO95MeveUtFonzZ0Oho74PEPWtqutxJ/oWAsXcPePakeP
z2JtMbpkZvFE7ccE32TTyWaLRyDALeWdPfCS87WBb8B0PwbPI0AYZKGkgM2wInpzORl14xEXmk1V
zxlumV/JyQkTUj9iGKHn1eLbeyU32rNAhnAJN2XG475E7rc1/NgLZ/80BvCm8mO13cwb5Y8wKfxB
FTeBUz+52huFnEMTarVfkbX/1DRdmoj6N2i6/9EFIMGnov/hi38FFymDaSu6CX+rRBV/z7K4Gn3p
zv4IqWxzig9vktazGSKzCS4vMjNSYarDYxi+XmpsmA+M2iuLw16JgCdluDisIKYRYxHR++DUn8Ii
mq7rUhYw3pGI9gJlDzz4xhBJGyp+uxf+WVj+kEUlEj5cm8OT8BiPvp30a8vgul1pcmY4vMzsC2/5
CAV/qAVMaMAVVFZdozTHzDNxWRbIQvY7GWNwkN27/9bR4vreniddpMtwhdd6Wn7tq0YJ6/qU/2Yf
4ht3g9/rdbD7ejYGInBn0uSiR6PJR+Z0XcGpFA8JNkPOhp8MAmk7njaEhUaVPuXV3ZNSCLl2uXCZ
Izy/VJKAeHApPhk2hlsdaDHPMqTZoPTNc1nMq1UkVEqqj9g6cqZ3M9KDbsFHQcTdfwSiGNAcU7er
wciu4KKDTC127QEjzkCR3kOBZ8puZbjsj+5VaQ6MwKcPSONU760CUAt+F15hk1MoXtPeKzhixk+K
lYp8OVI1nJPO7y4wuJITT120+1j+ndQtQxglsAv10BVeYjIhBi0m0XA4emqCExrL14v63DWIskKy
3KWaJ9oulXf969htmzFOm1BZFfax+RmsKCEYzK2J9NiI2MyjMCOjz1aa1gWRRu3cQeHi9bDvQ6Ry
OnNAeglHKyW5DaQMVuOvQeD5/yHTCKm+XNSFItoOX9w1cxgRblpSRVAy0aM39YgaQMyvtXSSA9oy
kX0nd4pN6zOkrJ5ZyH5M+aUIf7DiLcpIc+6oq8vcyA3kMJT/t2RBT7IHcgZy5fuM43tE0l62ZVUg
cN2QiIxSN2XDAAIfHVbZlpL1++dCgN+0P6o6Q4nC/gVtlsFfwHhO7l3kJy9/w71/Kk6k012B3kGQ
/JdjymtM/WhUbVyMwYddV3dyx6pxVqOxEi/QGoRZFXf45nscsLQgDOZOmK+VNl2LDelliu3W4EKk
FlUrIQuG+0fEDvkjAnTzuoHVIW1Xwr8nbNNIYAQ1QVfiyL+zsCZe8j0lazUqaw99MbgpGXLQHf0y
qgD+7e+j+y6Xe4f7WnmTYBtExzyFDucZ6wlBjX1Hpq5Gu+uyi6kRlCSEokuNNk5lyWRdoqOBzHPK
cJt4Uw2UBGLaz/fsD72uhbSO48yHCvConpQG/MLmxkGvurc2MeZIFAj/Gfb3h0mpw1fdqH6/Y4P9
Gje3e3DQPpFttc1fV23c7u2C/E8RImn3IMF07f1UrMp1zTo68dEM36vjyyLO9wZrcxCKfItaiI7y
V8Fc1PxVocZqTulSRMqoa6sg26au7SiRiBoG2hvE0zzB4HrfvaxEssqMYoFp6al8rB1HwuM+vw9z
ubb/us+c2iE0czUltr5aVGmNnLiI1gfUlU9/BgZXKztfNbr0Olc+j3ha+TLbRxF/nTx7+uywXXaW
iqwwBCEsSlq2uyWkKq+7UO5eB6T1hU3dZrpQ/FN97Bk0fI21GDuposyga+87QVBQDgEN/fbi08GT
YJTXmB+sbJF1J8V6dFvSMtq9QI2uEn5x59vH6p+CtMq6K35vruv9TevEm5Gx3sy+J3UcH7akDuFg
WzeEV+KucMjxOdZwLHbsjzZtynLUP1Dp0yM3HNRgnv/rGBhxmCzAEViyFrmUeLWq90vYUpMgZ8Cf
ltSSnWSZjRvKfOcbVdp1/MxZ3aoPpCdiz8pyBCRuxpR71ItXZbJ2NvjAc7ep4dMgBHnYCLFZTXWh
Gs1oAhDGVIqNQfEz2suzy6I0l9oWyv0yWWsbo6WjOgoMaJZYNIh9EAY1b8hkvmxHc/fQLy6kkj8/
TMlpBCkzxnb+KyT+UxoE47KD1SHIDs19dwCZ+iMnxggNlhEWaS75/F6SDCqpIRtWFDIy8Yvyo8WI
lnTTktMFPzvefI94yiG3U5TvRtjXsbokWrYM0hvLBHxOXKmDZiu0HO8xYPNB7O9X/qpeBeHDuq8y
4+lrhVRGfQ0wD/1JGc/Hl77/a9FouFyn6O5N27HvABQNZh917/8N6IB94DrfbRypCmZxBHJCZHLv
UYmIEIlkednsmE8H18I0FIF4KWXzoW0qOO5XueoZ8rX3k9nA1UeKhFs6hqIwwXEd2PkPYZcOlvQr
6a9MxrM21o7+ug8/qBHOCn7lu3qaCjXD8x6Vh78Uux0APnoR3i+EfV3KkDuspVgB//djpLyyKKGj
eZeSGyjONiymXTjZRPg5SRIOYoMT95WZXzw8zzNCgnv4R3SdWjSeipjenb3xdCa1Ty2/L5tg/I2u
Cws42jf/J2+OKAI7js3STCAg5i3z5no+QZjhbqPCNrw8Tu7U4KahWTmeA9Iem++NOUpQdiiRyuhR
kU7i5RYa2zKuiN2F7WajMtI3PLiZ0O5f1qoqB/d6+7akDJxA0jPjfTjHhKX9TMHTC1ZWVfyfB0Xa
9pJ/HY/E4hv69W+6BNvSODd9EupXwIFYoQUo2SCjrXqI7u4mvJMhhxZXikr1V8Hoejdm+8uuKOug
d4ZgM9MMZbDvDLIWMbCpQX60frtW4JacxYm2khPWEWyCtdZqlFYLvWKW8gwJNXyCJnRd/xUvXEj4
0qzleEwmoBOB1Y8iMNQs5Lb0bfOLVkeL6RUS+0W2qXTSl3ntCrOTx8E+jY0uzgP18WBGTPq7CGOX
gZrjeIjQCumSZoxoWyX7JUUad29XdoKTnKi0UD0OTS4BVll4wWFdbvsCfgVO70+XlDqwZNEJh/SO
tIYvs4aticJZxIDs/8B6YZd0HjMYqTJjXgN2DadZ3JRWKZMlzCFlhnxTc7Ys9o1zWoNTGaCW9MJX
oHHPHsDJVTNe6t2wcqyFB9vvbbTSuUjqoebo/1sJFNxC1aA25Qv8bTBG2+gg1dUHHcavleB2QXeV
je9ANBXseuFPaX+XlifcOL81SByDSUL6EVM9uIHOm5ADxqMnn+W31tUNREYimxZ8p8pN1n14wTiI
EwfdLxyTMgHW25UtrcEZiC3mqOx6XzNzw7ZgDuLZQNpza0y7X2Hi0BkI+wLR4uXhd4pTjuWvGGrp
rUJbmbXp6FVBmCEwBqeCmno8lAcOXBYUz6OY/B0mB4z5FqC1y9ysAAVk7R8FKc007fOnI2k/nDaY
ocw8qdXBoHnG1KV0XwcYHOT5WzTbXZq1v0oCYNRUAy5Ue/xgINqqwUj57d9o9t0fuClZWxBo+HIk
Uzt/FiBJHGkJ/K9rbg2ekiEskDbYdpEOG2nWxIKnCQg8MFzgzkCZyoHOsVHo9dRaqo68nVZNkWHk
kZL0bgzSRopKVQtDQciRG80SAe/ajPcpuPLCsAqbDqEuZ3gA0FZj2dwp23X/pnmEoJySrsB2KCaK
9Ic8zp78AqhMRRxqCquFAOjkph/pWO4PASEFevagsmmCwrKYXUUfk1VaHwhW9NEqbgzgX/GTWqXw
zXgj7lbQ6V8J3GYCVoh1xnFe1fT8KWg64qz7ffwg5gwPPqlMN4kD/f5E+eMJLGiqcfdHvv3F52u6
EYa1PGlsZ3eS7AjMt5IKAm42nEcfsnjmpTNvd5inG1JKccVNQDem+XOt4hvfjy9PQYbCbHb+uYz2
o5CDQ0bU3Rie4AvEm/3jt1BBIrKoFvMUuMQNW4l/BGu4/S4r0XfQVkKAASlE7sh9eRUMtgqfmJ52
ym7cd/dmr5eIAFF7fpaDOI3iqxXhlsoq7dKa0xfpsc8aauxHKJYN6B0d6CzTVYvM7QYAcc39mJTU
N0EIDkeftz4ZgOub4zvunrdALLF8Vb63F0w1hjwoRKEDg1mhV+mxgHeNBgLC02v0vB7elmRhKskF
/rSgdladQyFG+uXuOSvUPgzGnTWYoCK4KMtTT3KxR1BonpuYwJIvgPB3umrOq3ph6tc9owNZ+HEt
bOqcvzsFAxp5zVy0gHRUQU3CM7g6rR341YoI5md1IpVubgGWl9Z39dIavFwH6vp5YrmsJSgZUlvK
XNnLHx3h9/UmK4/hUhfbsttrZIo0yll9r/Hq/+YQB3AVf3rVeDKpxo+f2Ix2BdJBDM3W7fXMaw/7
JDlumEfY/+ZaEIEO64GFGmyFrZIS13EumvYecxOz3MnaPYxMlKvewt7Efp8lOA6chEu8yRdpzMEE
JQAQPpuIveD06o2K20/kNr0RMSRXd26tPOeFtIXTvwhxPaWvREGqromlFoQpztMMMxGOigDsaO64
Tg6LV9ZDswV4x8crk1ZgNDNpFrt/nNssCI7ENwMnMVqIIhV3oxz5KnYRmFu2Lo0TcpN90QAPhW3O
z8svqDRqdnBi2e028GA1VoL+1Y8zQ58YSy22bLdZoTbx6en0VZhJl5DCwX1cDqVhSfPTkwUKlsyD
7sLsEhkRJ6ROngCNF0qw7Ksyb33OvnrxF5Vp0BcQvp2KxSMpUqVCPsXDivR3VcKToibKf0wi3ItJ
pCQN5bVf7q/L6z9No0Dk8y+Mzur6HYGc6xUuefP4SksWRWwRXuEvwVZNTEzS+HhkZRIYr28jL3bD
bTn1XoDe98jbPC5o2Bw7I4jw9E5bzXtc4qmiymbq4L6AZ1SVD0D2us5PkuAyi/CsQEVCiLcDoazY
LIwQlvHKzKuK58UYaynMgEn2/rZYv3YOPgXsyVrxbgZwBTlC3xcmROx7yh0yIPYKZVONyImKIjEL
GZSKBwWof/JX70bUsYVBTMkps+O2/nAfIpcUL2+GCiwwt0SitQnJJJ0dgDNRIWA0dfV9bdlFT9FW
efUOS1+V7rcLwTEbF8/UZUGyepBugZIVg17rLXr2X9JqulEgJlvlD1Y27AIO9teL0mhvJprmq+8t
1pkHQADO5faPnUIa0STLpRBCmRV4+j07DZN6dYGIlH7ag4CyfxjyrqdZ2fb/4T/MNGWrMXIjur3G
3uxKvGhTn6dDmDQifFQtRQK7vGj/+X+d1cLSit7a5XeeQ7XgvbPIdUnw+IQBT1HpOg051AJtZLZg
hMiO0o0o99F8znOZNavS+oww79GDurdDUfQm2RsYPyL5G4CiheXlr5zPXtswmhWf3ctmGWm/w9lJ
WzZoHrvjiQ1ZFIZAe4fReOldc8kzGF2rq8P2bPn/K5QpjKkWgpFNsIB9aHteGKydklIAEtqLjKDC
ozXozDTlvUZW8M+CaG9/EhySW3kcWrutRAMIdmIewOlwtax0OND+JqlGtIxfCztqEHc4p9OMhqSg
t0xgACtQ5ip6uNgQiLo7QEyF6gF1e1yC6B2/NdLptnGI2KJjwpgDteQPlzqz3qnCAkNBrkzCVKn/
yA1j0rA8h8XoKdjroCdK4mmOBTwHEiq/SgriBDeUt8XnZ0hXs3v8MCGKeRFbgq35BSGyXH4xJDNX
jcW2E/MyP1Sfxkb50Xp5p83lw4ZYahtcFC49nG8IyEpVxTmTH4BEiEeEPKBquPgzWuyEd2iwpaWB
ECruhOi0Ab//9ms16NZm83C/OOXZFldzdlIQMyU2PRACk95xEVCNpFX7k/vf2QYzbLjjz7kOFFxq
1l8QYNIyGdNhHXSDA0VCc7ajOTa1eWRWBDZM/VK4dKgfjVU4X5xIKTgtZV6vAOMfcJw7MtZDsZ6+
cWJ3i9mlk34gFecG/gnJYvoLJpM4vGdjM0fI/Fjrl3dmr6Rp+ZBK2Z3u5sfjVhmBqxlvB9SXEarC
7Otute0Zqifm+O73hlf0E2h39wmnR4bJmdgj48RedpGpApLWq17EfTJVXbi/KHLODAo2g9cVQnaA
PidyOUlIX1huJ73v2HKo2fWd51SrlMd3tZUfczYVOh9vrb2VXTn26xdssJB+vldRXUW/ASgRNvlO
Ll8PKuowVC2cW4P/QRGdgnLW9LTXdeYu+VeIj5zfGcrXFJHLytZwrppWc21h8l6efvJGnBt+NG2q
GHvX0lbk+wfSi48NaFu+aZKUdgKov0JxZvqlZ0HVH3IZdGxv+ssipuMXDj84XFUHLEv7mhecauPX
oOeO1lI6QeAv8N1B9zE26+2MtOhi1iaOgL0o1WiNfTazE80bmcNHHrWNnGDBINmEkmWf5kUb6onX
pvjB5QusZ54oTEwLL0Ew3gyeuTBsYE/+i2OKxPUJAPGVFCOqpIkn8ONc2AxfGU+piqxY5SKHKapM
Ye1cP5swFQZm+ixeWrEVRqkl7s5pwi4L+nNx1rvgI35WOzzr4Xo+9ES/r73wnN35Zr+agTmo4BCs
B/SqGnzcVCSEZqCFZEWX5no+EO0jGyAwaIA32TSWW4UlB7go4quyR7jBOwrZE51sp9GtPLS1dl6t
77hEozNKVrkEeIcv9lgeLmm3NT3OrdsAAW8x5QYFCy4gUoZTsWI0FB6+vRR3IjePDHxii4poRnAr
hlKYpuyHXVRiTAWWPS11nbKY+qSy61aMZIqHz84dsCtezdUIplR5gKxPX1RRvUlMVckNQ4Fl/GDk
WO5pR7L1+J37tvP+fdupbfLLAHQjz9QWYXe9odb0kCntmYh0+9S/vtQmzvnYj5Tni/3WkpXTdB58
ifxFnueSVRv6nlA/YrLaZWTC8N4X5AbCmSnx4UmBbizGZDP/7BEP8XBnAHh5FCPzeiy6QuZGXaog
52daEj8OrqKogtdh+jjcCuH+7jg5bDp+rHptjLE+hawwp6TnjPDs2g8J6HqNZa7NPqpkWhLd2cjg
RDlNKgAfHNXbK5CyrRjn/A7TyROVzcxFunnMfZNlR9n2IDxC+REtukqdg+i1AcXEMaXVKwtjpoBz
x+UQPK6cwZoTAtMkQd2U/hv1Os077Ux3PanDyHpN6rdgySdeFRaQecox/w8W00wY2YeUuaP9Tts8
aHvwaG2ZhgocKsPMIIObw6Ua6t8MI5hvQIKt3EK8V7ClOl5xODp1WnJ5Hk70lHPjaH0e+OWaYC4b
EE5ujbhVZR3L0W7kod0gfT7CWslz6bxvBhdefLreb5Oda1Le1ElqkiKM5OfoxUEKbXHrUEWbGypH
+Q84f5NS6ma4Uq1RddQfR4kOzzqLcFsEC63o4MFyONPwT8UgRsHz0K2qwxzFJg/nT6r8kQaZ2pFT
H46Hbh7+KwxQ0wWwDgc2ytVRrHPY89qSXbAewVBlWVC2Jedv8pCa0/W0xnaFOjhXedRYwNooibQF
EX5AvxbOmi6gIuarcaxN40Xc4izTmAeGNHCWi2H18vdOxL6pxYPq0cs6dF/Uo3D+qv/3yMMQDQdC
CsbmlQBgd8WE7PXfTX7cPachYz2g/J+qQ23C4d7ujRHVd+kGLc/PJ2vFbYRVK7EIXVDG7Xs7H0sT
eNFFZtVzydiPQ2Hg5+unUpm2qagRysMqwKTcP/WyCN02P+z2+0ag+Nv9Da7oTws93cAP8x1tETEO
PxNLaR3EcK6V1d631wO6a1b/KXRF3mXxhxRKoA9KTymZtmCZd3S6ZJP5DZG8vlrCY3Jgg/Obb6Zk
C9HQRLhR9ZHtw0FtbEtsJ1A8AKq1R6i0kcBnep1xVNdgPrvAclkUajB1qYSo8xUDnacNKoHxG46q
WEJsOFYIpxYX8DyHUsgNBJdrUiNlD1+tTuqU4zf5mE8CsaozcAGyk4AzSNP8KU4JRMS7If8uiHxL
JEIfl1OsbQz0rTwBY2r0dmO3bIMO7b3Fw1mztDDEzLG+w9C+ZjDo+i5qGlCnCxLB9rxrJfZqcIr5
tl7gWDLMjh77TChwJagISIuBRB5Cdmw9Qn5oxMgYexPYCTVrD2UFV9AKneQctaaxLdZ0bi7WmllN
uYnutmHdZM9y+gZLjv2qg8tq8x0RnyPJiM7rIovWDfHVZo9LTx1uUyWujYajkTInIjIThn+Lsid5
sDlLT56YqyhW3gELbYMmRQdd7AqfNyk/OnG8bZ3qcduM9fyqSjOhlHVamZg7DJs8t+C3q/l50mG9
SGam6FLi8Z3FDBLrhZH5G2qp11NfQFruAgif/p/e3c+/j8f7DWRxmNIjeXb22T8SK0z+edhECePk
EQ/GXvYVTr91fdOI9/yLGX8sKEGWtJPzx0jEiNzdCbI7frAJKs9agKWrDcGLFsjI/aPnmjZSKnmd
lRgJ+ChZ+A43uJEQK66VaiyexRk22rJLko3nK/617NM6pYmxkjun3U1PZtbihbcOh5wfk5m5Y3MN
NSMDY1JdofCpEwkJ0zZLCBno5HZyASnnk9G8hFLfvH8LhXkgRQyhnBlBA1cDhznw/uPKY+gmPrsk
JX6DfvFNXiiPAb36v/Y5oT56nnrGGUuly9L5f04RhDM8nLNXaCYMVaGXjTWbnvpKDAywj9t7u+Z7
Ln7tHrr7jf00XXTTy/4qSkWkm/2qElYACo8t9o9dwEEVuVplUomc8+K0KMn6R+gPilHJ6TEaDcm4
U0esnobp7IiMrJqk7JYMhkQiu3ZsrG5G58SQg44ivnUCM1ttW6iVIb8Ys1zHeBfLMGrQp3uap1Uk
t4H+jbhGlAxne7sXMkIL6+2/fevcxXuuLw6QcvCbZ+bCIsCbJRH2YL2UWHjmLqktmGciT9Kp5ZUV
/MzoGnYIT3Cbjh36nGfWuX+JSyT48o9q46E6uuZNJDsIsCtYHMWjmfGFZxqPzb4Un21wcl3fznak
dNiRScwTK1u612R44DuVuo17dLRnKyEYuZGDhLrtWa+wvtsqXYJCn2CDLJOqE4jMUFQDuKV2cwJH
Lahzwn/u8blVHky9GF5K7jyPnSwy0V9UI8WJYw3f006TNfgHhte1Rz6GLkyQ3efCoVcCu/Rcae/c
JeuBBaj+ng0yblQBJ22ThCWHgekTvQVSjQwvAJHaESKo2pB07Ol7h2FSi3zlsqZh7/0+HAhE/HaL
/vK/1iV6IA8w14lsfEhb3sWIpqWnO8b65YuVfHzRJwQtBF9NjOfTpq2FnaEfFbsBi5mRpq9dBegK
hetvA1N6c3e6kPtF3y27Xs8+7dspcLp+lc9D6VPIysx/TNKPHbUvRfSOTUHZxzcPqczt9d59vTBG
U+mC1oFDcAVSLiq2swehYPYNgaMGu6Ill/O1yD0yLPPdX599sKf/50nGArGpzpHMfKKaG9WJfq0p
bHpmTtgw6hjqlehADYKv+aMtJMuqTXYmDwJvPfelfB2Mqv9bbW4RDtxnZAOStk4JgyHCzQNLt7tS
hM9qHvIbvA7QAaLfJrV+WdS89ai/+xtPKTYVUp3wBf9ka8jAAdRytUY5wZS1X0l0D/S8ZSB6iyIm
1qPI6ghvovNL64qVhg99jXemXyH8JQkyJ8ANrOjdqeNL1zDG/3cOyh0CXUYJ/+jvLMXCEYLHaeJw
b8sWarOGH0pQMJtUc91f6y8c3YV76SBEyqKJ5NWagjJsv5LTuhAmd6DaSR0GVBNqyuV98W2RRAyF
t96Taex8LBA43D0J8MCddBZX+IoYFPM8qJBQ4CvvQskWt1u2UnSQJ9mEsZZfDwlz7oBpazgubETq
6RKs3vI6COV3hfXuwggD3Zgiybme1Ah8K65eXJDKVrarJR19KIgL4wNeqz8NldxC6QLW0jyJ215i
eUU40FOSdXmJMgmi+Q8g2LFNGKnZb3C0GL6lp8vcVSUyKx++puXwDIHOtfOSnOp7wuGB/PyqrXpQ
5ONWX8EcOLmoLs0z2njQbSGiRa695suI7Bmh2Kw9K0Bzd11Xfx3qw0bAcldX3mErG4xbNKaKmRjf
7mMLBSot20qpSkIWLLOjjEOMsW857WWQ/9QupCNvgFIA57BSvnK2FSpXg9Dklfp3VXV+Zam6OuzM
agHJ4jvQBOpgEankGBHzV/esNsadGzemDnCI5NFuQQUZ+n4gLG0xyPZST76/amxQT11JGfrlgmzW
sO9X3RrCDmIjbN8a118oi2sLXhBp5BNZW1YF6z2/qv2rozB5+0zIspGlZJu3Gc6oNwCIfHSL8xZW
V3MbvI6L6p99YfU3Cx1s7CrJrYpOrOD6I8iIcUjB7HSIPvLYlkZB2VPvoKtBUroXn3Hoaoilu8IF
U+T0/M9fYHdkPoKwY2dYHV5nugbqxWIJhU1P0YxFFHV3EvsZ39N/QbFVc2LNbGBex3cnw8wMP6DE
Ok0h2GT/8un3zmTAkoaNDUK/7ls1V1AEleBzAXLDdRpc4uAa81GKtoj/p+ldkmksGMcqYdwr/hX/
1QSLnb5Pv9gR0LqedTbpdb81Y+fxYnMon+/PKSI4PHgVi7/ZiPhdv7kma7W/utxYmHVw5F+/MuA/
BFauGgNRHyaLcFp8mZLOuUc5cM7280hbSDwXIUPnTs+Z4O0wh17davjm1Hoya0FT1+G7mOx1WSA2
tfT6TxQrsSUHWGO54x0lHqfNrgnywgkZLxFi9APghuBx6opof/wTa7iEdO93LRBzmfbVbUKMwzct
LDZlcQblMiH/g4Os0F/+W/j9gHkbtQLg34L/YNP6sOEEcVuRvM3WsF5orNwGZTgwnoW4klAiBzP7
CwOgsumq0N6eL6QA1NTC+88gheQGA6KQvNqxoG8tcLij2zxgPjCE1QkmycMxfuhmYFqQvr2dbZcZ
/BVC83/xZFoyYOTVz0clvSmoUEEaicgF02ECAKrLI5lqSXl8TXnMqQNRfhJ/aY7Hw8vmZ351ZCYk
cIurS7Cwpgh30ahwNpOe44o7jnTSV9fdJ58hhAm6UVqTSoN3SNQ/V9TsdIu56MJnqja4cao4Uien
LLqznkTKU2/dIaGmfa1eqcgrsZLocZzb4ZhKUHoYJZcc5uWGRVqjIY6IIBcGucfwivX2MLwsnA/x
sORG0HSv6IOtY5X0rSAl8dCTHuRCATt/bxiRT6cGEUEVPKNetWtthfjn4lRKI3eRRHz2d32t0+Nv
qKSYn+hTn0lirQiwnNlISd2/XgAwV9LDlMLYOj5fdjoHnRzqG0qlCoYMSL9O++ulLI+RyGaRc6P7
Gfx6hTqLMLNuE4sd/+J3vHAArFLykxWu68FZhddM0Vcppio1/thPFYbfPpMLFfuBNZofp0VZ7pX8
XcCXvm+u5w7HOyky2avcCEs/XvT4bziuILL0FF00OdqZiqB7DpBYJx8mJKN5sBctSU2y6jpo6MjH
Y/ioL6UxZ9VTjF56DFTIcJeLXipc7fisoNroCevJclIpd+arUz3e0Z3GdrFb3cXgvpLEAoaty4+Q
rgicQxeHra3k0J8TrxhyFDgRmAljA5/EZUiOhOa3nWt8X4KuHxWDkziJyKAT+wrw6jcoA4/WwjMG
33F+03+sqcIpU0I+cXv301qfAMq5YuWIaqwZAbBI41hVvd+g4c6sfzPxUDqzARisvaMTvbp311jU
gpRp7EkCmOICYo90MC6+CuBqemTYbyysul0a0cv0Xz2QRNILDztng5GTCwvCd9eu+RTeaA/SICuE
M/a+h0nth9a5BSOrqFoyo2oR4DSO33DCwU6VfFLzruXSi9KncFTfDnU16OVPkYiiM/cmrOw4pB5n
cGaY7yr0ddneuWJzJEF1o9uL02fnx/mXFgUIp7rmAamoBs75wb16IaohLbjbTZaaaDXhbmfR8AP/
YJC8SBc/7t/KyR25VMkgTdy4oSeaBgp/U1cHg/lcYkEmLVmMsnzZlSojjUl+ofDbRoHjFWWPP737
ix3+IAsLY2LT4WnllafcSIxAxehwOTbfq4MXT4HQ9wmOX0NxkXaUlvaReLAmQnpclR/X+ArUDAMp
qwlhMlHGpKgq8WOIvnMuDlB2L9OYI8y+tWXIPJK5DKVIDAn8SeXxccEDEH0r09999PI0sXeXYA4F
MEZATtH0mJpUXr9G+FELV1+u8xRK+JRgT8qEaPIrHd1t9aVc4ohuAu3WKgD0B2VWJ1xPhEay7sPL
3x9gxRMp6PhzOeu4pLfi0J1XMX7HpJf1INPaldl/TweFXg1JRjaZgmhdsawttqYCcWjB8stf4qbN
xGxdVuOGMhntp4RgvTOktaguEwZmNw5zoykF5W5+oIyiD0WOfspcPIVmYbqiv/to9dh3m3fC+kEM
DhWtHHq129QtfxOcRAdqtmo8UwG/S3B52G3dOJ9KmWumrNITHVWevE3J6X1biAK+xz5re5O9EdMC
ideap18ACphFiGD4s5DOGywOujRnry3LMYeEB/+OE6qK1mS61pFAHrim0tXzPjLRhJZxPgp4vfFW
6iJ5/A5jaYIsicxxc4jXEaOJ20MuQihoIfqed5eEExJTbAivv6tQu2OPqlfmmsSnm8BKIfB7Qinv
diwoYwr/zPe4T5bpWxPgwdkL7rw7RkYEQaOU9tsCwZvU4d66xz05siHL9oeOoEX0qkMtd97WwGvF
Jz/D97lQhd/lNUS918G/NAY3aYb2SsNXTynFFAjuj27AfkRhRJehh5/9ZB8vaU2v7HpSPd3VLtvn
y2U/ZtAn5vQPGChiWdloQ+lnYrOlefsYb5vDC/QkxWO06iV6TstQIdBOkqW9PTFakd71kZpovoSG
eIOxWfn/iRwqtc0lJ7MYk6SCbimtAtvQ6FcIYXxYFqUy+dL5RJoyR83dkH67AgzN0swyyxBXxBsB
DEWuZuDO/Nz8C1QEuy8cUF825fTdYMAKF2wDFC0I5MWCuE7OcQTGNHTmogHLi0IutgtwA95yKncS
xNIuqo+niIc27zpU3gmqfQdwPFwayAQLTv1kZu0hKHf2+82WVicLgVuFKkdb4hANIUMGH6lGsDG6
wM7+ZzRFarWP80ANeM85dGDC5tgbl7p0tOWEeR4TiLgd+MmrADa+dQjIIXItErNDYGR/fcJKFvS1
Nok+CH35JxvUeuR7m9/4dhGEZDUo7bh56SIM1pmzFxg4ZLuEC2pHJwS8Zt6I5WKNGp9ZxvCRQNfb
ZR7l5HAeH7PvxNqsZtrb1D3e9nJP6CEiKXFHMWxpKNjNibGFzzNKJEVq55iYYpTWUwJ8rJuKW/ip
HHyO2CFCzhZ/ZDXo61Gvot4h0DqOzZ1ZpyVliby1ERMLrQdtpbJFoQH0RJm41wZJZjPysgK2u/tb
4R13q/NtB8hoM3+05/wwQNnCBMvJOKRXa3FU8cOzoQ9EXfk7DMyph8PuqH1ulplUQYgjiCNZ0vf/
+7t++cvftUZiQaSxWxO+FuqWDZ9sEO3moGDjSYgohCzjPHl+CFkQSeADvRoDFoXo2j6wD938CzJm
TIFJUTv9B0ZuENVsnScG/jiFPw4U0uAeedqRKNwv+bw5ZQccgwbo2fVr4arGxLnYRP+1BA/p1MRR
p5GxmHJgtzutEgzppWrCBeyC7nFg4Lwlh1mDkIljI9f1h6MOYsZPsZQLmOFgQaNISi/wWiwp/r3i
tL3+8cJ53Zy2mPz65U60Cgiq70OFSZYmyXHMRuPzaKfD3QYl1kZa1J8FUV7bjhX3acoCJ2tHCEyN
zcAKqMw2Wo55uYfEjF+rjhj9VI8jiBR5kyJZ0n7UWJBxFfd+GzY/gifRDFFzyI9Sb1LYBeYEGnhY
drnR//cNfMfeY/0ENW2ognogIg8MzKeHiXIdnSM0Iwb8fDgDD8DFq1eaoBR/17mF97CpQCQA3Pr+
oWcoORsmY4yhxwcUbCkPMjv1dThv5iqxb6J0g85uiOX5P/rQIbI+CUNiq2wKMNNCGRQ6UCt6b9AW
8WtjWZMETZCIjO+rjXVtcHtnhppFkcf4mRHm73AF170Wi3WN9I8aViTEjn/g3HagMg3XReH0gFU2
Z3ojcvX6yBjhb+H3CzfTWi+7uUKfEv/CKwsazdnFyP/OWIXr8bUd9EBU+k5Ux0G8plZPI+3z57sz
QM4wzabYg86gPVf7gCPDtT5PtIqDv9yjkjbYSr2z1DKpth50knhrNYVrk1fYMBHzfSRIRuKEOi72
Gz7xUwMWSL/ehxmBnbWatwJM3UPR+SV0713fubs9iAt+Q35p3oh2xFqTvH5/DJH/DZ089zKkl4fG
BAUJxkN17xMFnauejE343zGVaYkFkRlZAiPK0Z0vajosO81kc2Neo48edRJAXruK+OJbjZcFDFX/
MhcqsQGay0UWDrk0SSZFcVTjxRk5OaJ7xNZNEw4Z2gG7ePCcjTf6GBKrQPo3gvGwsvotMdb1Tbev
y1kp2Tbk0WHjnvtmyPVxhWKnjtrnvOE4Op7YXjzKsH5hO9XiSf595LJUxQ/oRF+Mpay8sB5SqlCg
bYJ4M50lFhaWMNjilpFGtKqkxm+8Y5qykUaSgguyv6VRidhXDGnuK/rtHH/5vvvUp1Kjx65/7w31
ADhspLl/ANIAVRgE/mhPtgCDzuTTFn1L6bCWY9zq3MO+2SH9lCE3BxJElCurD2v/s8FNBGf5klCx
DXUCrc8plAXFEfs5IVBxDTMvMXCTnz54a071YKx3JocJj7Zm5+URrFqnrFtmWfci3w8hLdHgCCGJ
h4WWuc4H7mve27RLiNjTXM1Ywrc+yaKJdOR2tRkpiD9vIzSuoUsZG3nDI+sT4mW/NA+TSb/fOzCQ
4vZgNBC39JE+VhSMd9BySiT64a7CkoYqV8QImi/UTKSjKTouPp0xVxSEgYyoaGgtJCbjAVVpifba
3Gk6jitQChB38npXr3zDcdzLRZQFVpSNz2JL36728/G2d5pzemH+Paa6TsxwAa2DgpJVs1OHXC/s
S1DPJMPAFMgfhcBPGTaZutXi7FVlEjBT9Mv4u7qblCbE87uGOVlBAsxgL68keZrFx0VFyppZ4V+Y
7K2Buatq8LVL1rsTBHH4Pv9h1rvOyqIUBD/f/LXPY2OA5N6j2bmzi41548u3JXyDm3SSrAtidOVI
BsOrdnOPHDo1+yWgPXB5aNXbuQsWNoCBKkFBCBK06ZcXzCCV0QTnzs+iT+bjFpQdIemWdv1UwnUv
uOsk5Zzh8RGpGE1Fucl1hlJTnJTQ0b5bGamBBHIMr8R6ddOHzAEVPdNOS8lwD+mOhO3OEWflf3Tl
hOWMwqTrk/CO5n6qr+CvdN224jSPEe2+EdsGB74HwA3oySzRX82ntHAEZziM+OLZXTGyVxKicKQD
Dmfys/jGHeS88pY6p/S7YQfNT3z1Agi6bLhQBu4nhKvxjWd3KJrEwQ7DnhS7306JtDwMhjosBCdg
Ja6In29uWpEwa08EU5/0ZGm0N6Gte+g7VFwTnqBmtEu4mV+dcX1Jk36w6mDdqWDKqsIRssyUPYMJ
OglZa0Yq+J2lx8RlX/ST5NEnSJao2yjRv5Erdj4GNFdxVZvP1/vlCr6fr4QLd8NG9Q7VBYZyYlN5
tW6+DGgT6AjE+/Ygrin2MAnLfhJTcnNtECI2C6Imw7wieTe01F47cRLTujdhh+xVcZPHntqOVvh3
TvsHuClxeEHNtlvrTcaIWZYg4P9SRjOC7Elram3N+DjxED5nOlrVAYWI4UZ9yzsKQAixWcbMZSWI
8bFn2uQjhuQ34LDzFxBHUjkUJzInpkR6LLXNK6UiY0IgZchXbU6qXaVOcCtuwTzKi51/vlz+JxL2
VcPn8COX1RRPtAPLOQ7yZMs5bfC9eUwLXBit/CpzfS7JibhjanAYwoRNqcvu+lj8c26NUQ/efqRS
aZsGfQ6IfirlxWW8ED0XQUmE5PnVLqIa9waBT/+UO0LhxEbnWZNLwBhSLgo/Qx/CgJrzqfP+9DrU
KindLOqzQ2sUf6YsZkbjjgLrv4xu7KRXppizyu8SlzW1TlRwNeASQj9VBcjUgKrAE5YPKgXC5CvU
QTfseTSnjToEXUIF2gqsyR8X4CMpgzK3lQ5VgSb5EPx/9HPucMZFC4BBoKBRPclEIn1QqWGkHYr/
2+WZIBTKpugYb9fEPmmkQ0mrs3ppF4np+KzjZQLHZgE6NyKPZyznJQYG5U4Z8eEhLzTaBIHMttNL
ZmfyAirbAE8iwo8wk3/peD480jgynG4y0GhozNLZnYqrE22lNo3yJ8PtWnyt6/DMUU1MlqkuAqNR
kPAYvaHt+aMDC3dtbXUnTBTwMmxhIb10OnTDsty1up1rRXDVlFDTN2VvQiWF3FY+cAlcL80kPZZb
1uEbkZBn9JNA3SMXiBPlkkMFmKqtLHmz7ZsJNDCSDGTS+RBazmcTNdnoRiN8gpmdElvmCmRRd5op
Q6w0C3qILrNRhb93L2Ek924x6KtT/Eg1xkpRilgsPkRhDDmi8KBOVa+sv+AbDLiKGK0moASxQ16T
U4eb0+e+ncO8gSOvv1HEbuqR8krfnotLi9RABygTyMw70GLXVRW7zom5GWNtRBv6cDSFCFf2RP3X
WVE436gNR847PA6dLt7eNHvtZl57kRmvOC5t8urCiBvOWk8f8GStqJPpJ8WZzPYCWO31dJhkUrsh
9DuzPik009BME8vLJBdKI6m81HKhS0E11aAntHGmS4Oo7oxwz1FYWIKUvSckoI0ow1XF8Hr8USIL
jsr7WmrmjJ92NiB4UwQsprvY5mFF6o1t7apT6tEGwGuLUrXmR4QnKlxxDj+1MM7ZgSVYBbUZ23lR
7XvBgyhkVcfkd7XUyUACK8hTFv98cLLRGqbDTpJutYyog0XFMMmemQebB/EC34cVrvLgQNjlnd5/
iW7Beq8KSUGUSQHPUPLdnQ/HjKIuCMIZUKiiLpxW9xqeudtpZ373x+hE3LatlZw99z4aD1Q1rD53
4SsfXStHYhEWx1XPCPMcbdwS65hVDEK6vwZVusHqrJ1Rnth4snW0aJEW96uY2DgqzXya67Hrqme6
lIymiNHlD2ZDCqg/sAVjm2fsjXUoUYx0Nw9d9eBxhohgx9mAqOxHOG2izZ22t5JGOpL0tN6qQ8sA
oZ/z483JE44x4SwXdhP8S5xeLhE01l6//TrgQx6CxbHZY+YYu+IJQqZ4lKmtL9OXqvh2l+/wNHBS
Nbd2n7xd2JslAZoAKpvPJrZL4rqaUfdP77vbjZkt3InA8K9j0tE/Vi+Z4Hji9izSRUtWbGW/ETKG
+Jx4hm+kSXdekGPyPFZzwqHOWOI3lxZyd0bq91XYSbW8//8mWNHS2JI6YGbBB0sJROZIYPqa3bKM
ihVRPI4AeFl+1rKf9IOzdr3YYYPFrGAw35ab4Rw4QxLQn5e/ZKSAAxrYGsLIQea1UPAIFsEH8xsf
ffRINaeM5b2YeXTLh3z7oDqoR5f2hZzlsvJBJZQ4EtDbHZef4rX5iPMqT3LSmRZe3xPf7Sapk4cS
H4S6EKC7SftgtsCeFKoaSyz3GMrorNCJ52IG1PmiMXwupcXISkOzzIzXkoMjRcHL2pZBxmDAd5GB
5L6eB/W97OLGhgBft/DMjvXujVtLI6QY4H97I+OaDXisA9MY2gvAZFqj8dwprNcQNp7Fjab54ocd
IuItPtV2AnnUeByO8NPRqmvQIUIGt4Ym5q2ldr2fPcLVCugLijBLpC7KyNJcJpyfd35XOh7vwhRF
FGAzemQ+fJhd+Bd6M5qPJ4NRuXCiebG3TUGX1rug0vNVzXG9OyoLHZmgyrWIKatjlvRDYIy/irSV
T48Bq3rDLXnxSPcJBZauO0Xij+hfh01pSJyWS+8UMG1/TAOJx9Xhr+7BilzSobgd5YexFx0QQZiq
DYP+LB+IOPt0ydkYOFP9EXxCF6OyAkIn05uxyDjgDTqBU3W3BD3wqIaQs1WFMYTPUb148/1mijza
XuIUA8DwNA+xVLX/xevLRfVfyJYyzK/KREncdpMTAdcY6Cc03lnH6ljkC1vFlEizLExxTdEYcPK8
XcZ4FphJr1QZ0+aSXiFt88SSu7tcKzRVLT1sBiTGgS9fXnuGKoDv7wTWBeuxK9MNQjJ5Mi7d1N12
oKpPScOp9Y7zSVTpi80umR8lWKRkpvqEMLlFZev3rNhPcqASx8OrydATuKy/e3qn324C/vesY4on
89gw20pvEF3ntQX/EVBwNKq9v2P4XXqoV03bB8yXEuuyLc5/wVjjONcW6RO+ukDTG1LGOZJQiukZ
qrPGLrQo79on4nK/RDhVZW3StDR/lGlDGBxeOBvKfj5A3B082eSfB5He+h6PfZnCZdGoWS1Ha/Im
oC+VPTs/eRTzeLdtcHQXRZVrEfcurQClK0oowfECzFK975QIKHu54Nr2snSdPauA+d/y0cZyADiz
1ilmzKqijCqOdQOxR7DgW2ohICQWiW/mxVMhUbEwZUSSnllNEXtdceBrSfNK6jrXDYTyNBXT6PMB
eeMfMQtqy7990ykgem5+5M2H2TEpN0aSUg4d578uu76BKMNRH7rec+SXWyZ/fnI+3R+IwOON2vPF
7CNcFkezXw5JM2adTSScOJPko+H/DkDYoIxR94kPXEGgSiVEXJOJ+bBJ18dK2alVUaVfxRqWCoah
sIdN2LN4DhsF8vbrtR3wTAr1tY++s/DmBvqEC91ERnsMDQjsSaGvApjxFN6H1VxXPac/0O3KQX6V
K7STz2DN1EHH21v5iohUa2+oyoGyu5mSqbVSn2nIL/woA837GRsGxFQ2FtycGsyc1BhXG9FuxSb1
E61QRJZsS0sS8Gv+q2S/N/QovxdQg3RZlYSjtgJoGCha2R5uAj8uSTdtbjXQ+e+g8an0iL4YQKIK
7yA51bDarIaKY/C/Wzr6s0JkBP99AhAvPL/cra4gkhfWKKGmEWbpajH2FdvbLLoyBu83URS5/wRU
RVURXHgd3J3RJYtEJUJdireAYufVQq6N1L80lw5a/QvdhkoKu3mr9Oh5JDBcJafcCgACprMnNPze
zvVGNh10SmN8LTJXQlLAUxNHb0JzxJ8ae3xVly4hA8edRhhEMlhiPatu9Zmv05xUZTjT6oo7FOuu
3VAQ3W4k0RWnNKWrNVUWuHvvfQsTXkFTsvfkVojjfkMiV1NeAiyE8Smx5YJSxFYDqpLsEaqJTyCG
OACbV1qROdCS7tqTz/S10UBoiNXMeL1SllorZpA/Xl8Cgz4F/XmKOThnuOU/7Azqrpmh6eUUhYKB
lg8U5hyF5ab+BAUpBLot+2/gOGHT4u8+RzYoxZgRD4MBk9dlsBhcgHBRl3ySM085rS4VgU/dpyax
6ESSvTJj6z7lCZIoT3TExY3b7BkGbjRLUfA8Uh4bq+Z5khHGjnamcQO8ny1dynniUHd8p7CAp7ku
36mE0lHJEVdB32LfdwutW9Q+Z0TBQ9Hx8ertMLsLuUuanFvdMpiGqGSH6SOPCnmiJs5KgfL5ZfjI
rKW2s8f0SWssr2f0aERAZQ2zQNq/csx9W4zQ22hyFkzdB8gIen77BCrwsMbGJqO2S69QhqBEOfNV
f/QZf2RligyVZS+NLjQCZTFCA9Bjoj1/koQDyjTdtzpSM9QJd94qio0PFi5o/YTzt/hRAiyaXSAG
46LOUZecfaTm4SuEG0il4YHkpUOROBno88fxVZqgW1QF36BGMznYc/BdQMhufWq2kgXP4xcbGT9s
/98B7UcY/FriHZF3oeuOCqpyzPG6pK98d7t90KzIq8jMEq347rszraP/XBRzKXSOgh1ixeQjfuTm
foQr4YT4If4zAQ++fhouwrndynqSRnMsvkf+o4FQkl2Sypad7PojOM99OrNCC/yqp9meLR3yYa7T
KyEz7FCJu1wj7pF1FvnVL9M9teNxZH87TmOaNB9c9PZ5TbijP859E8X+l/m81RShLWdt32SlNcub
Mg1Py+msAOPTxFllk9OLd2NnrVqLZoUzBTJT6ZG0ey0lUZEp8UiuA2h5R+ftdmVnELdhOthVZwmU
w5lahgXmCykc/U8pyqjI06tppM3MeNvXfycTNej6i6bC0+TdLq+i6T7YzJjZYa4/KPNN0AT4faB7
BqwyEv7YeYJLZQMUbOnD0Xhq0y+nMJeYym0cCrJ+yJyTiIPbtzH9c2z3eCGfi5o28SerGyLAwvTS
ujJ9qYpJ3pmy95UVv2GMWypXZ968pfWftnP3dXq1CVfDIcDGw6ioyfjBAgvHqemlmUjigCZPL/Zq
IO/PzaLHMgdS5GNetLK0TqSDEMbPV7qEBfvxlExIdoEeIBQjBTKWkjcT5YhJCQw+N00hv3q95/5W
wNma0y0NJVLxzeLxCvxsonwwzlboJS1BqzX/LDmSX+Q4vW1e/kHuL8ly79TR1TR+4lVLvG7t8Res
zDWbTCvjnT+PecctR+ife0bHi7Wt6Dr5k96mXw7TIod43Nzo1wWGbGYZnxTRiHF4TCXgKWqR+Xni
Uv8i3QLyBBHvKMtZO8vuzd006W4bSph+vV8T7fIp0FYo9NNcfGS5IMc19DNjHZUxzPNNyYbDjcin
FI7E6/GSBlYqqyYOZHeSqaHiFo4Vp6H7spTtPqsrpdM5npSK21Qua1UB9Q9FjYjLUHK+y3xvObDV
riyw98yz9bD14mwfvix2kDFiJesBsE80t0fmLLllOAAB4Xd9UHu9U72e/c5ED3ry1tW07J2XcaQO
+JSuWqvxK4MWnjP12DKNXoIht3fLMimj/HRxBDikj2SosoN4dGMpEjhMbPslEfahrZJE0Hj6drRa
Bo+rGiLTgXR+B2GzKLOqav4DlD5m09pEQ/nnE6mtvcIVihwBf6geCBEBfqthOtWceCl/CzaVlGxf
y6hT02uRFalox6/nnZ1opGN9YFRb0iOpZSuCs5E0t5W8uVxH79wSLzb5zviEJa0jlpv4fOzrScmG
chWqJL9qAq38ktXCla/gaJgH+1Uu22g1Le05V9ikRyH6bgOfSi8VFzbLaXaKNTMJTNKFa01Pd6HK
MMd3uozrfS/1DY3QKV5g94P03qUoLs9zz++R20E+zwMNRDuDKY9kOwpXqgPi2H46CYAWt2VifuL4
TZUjcM+xqsXtizlrO9d2oHkltgg52ip41x2LgioOr8X95yZBdvv1GkHfPWjDVfWWnIQ2M+ClCEyd
dGNS28wIGaWgwHyeEDONLZo8vKUn2ssK9v99kr2vBG8M8kJcZW31fe4qIvQpLqXf0OyltCPxRNiU
FZxjPWIXTo7F1I6u9K+tqWOhjwG/iLQBLV3TN4KFjJ+UjjOq3ZJCgQoQmnWN3LYbfM4JN1sk+/Dj
aOovVsuUXF+YwIQBpcevAn6nrGn/dfRxLyapTuPRzZyoEdcM2GojmQj9vN36Ne3I143Xo911mZRD
9vr7IEyNALH/lMttmTmlRxeL/NlSKVsm7rq+rRYzEd4HZHlNi9vYYlKrzTUFkF/HvFB7MQTHcZrh
OX/RDtTD2WZ3TKkMMMTN5d+5zV/pezW7GH/GjfEk/S2rZTG2x98r4MMsPIWO9kboWN+jgI23AV11
mUUEoWtA6SBZT2EUBiSHvDMxCERRVPQjGjvmppygCXimF1z9iRSwVO0RdxLhfu/pcIm3qXgOdP6j
4jKbSDQbX1LdhHc+HZhMjiXqbr5ph6vbxcb6QmAo1eCrNgyMmzKpABFD+a3XLgggPgGWttUtznrK
F95JEJLr7gqAC/k2H51QBDMLmp82UpRWBgGIacRIYI20JEWvOtKUyrds4dve3WgPlBCb+DhVh5je
3LvpHmukSLCANFNIybvi28dViKRe1mMDpkhyhGGc9D3K5fna3lWtmDG3opSz63QDeOAzbMBhv7b5
LKMnfaugjQMXpbvCOgzqH1zxECu1gIVcT7qkyOX65c3BeINUH2ds7WmnqBIhVlTdHt9GXAV70HKP
bg2ievH7q3DeN0F3S3Ty92cB/+98wQqB2e0tkyRI7fBU2RP9IJo1bDSfzWs5Iv9/+Gb+ZDIXzTrs
aSk5l/LAx5ohEqqzrkMH7Jki/bZGmDWoo7hBS04QI3/2IbqmGwO8kVe0ysxNDy4B+RTpR3xvqRHF
gc/EPJ3nh2D9UV9KXmsh8P/5nEvEdv4dMG+f+zVCrn5tFf+W0bmiHqeLWO0fJclr4NrKDR90hPL9
9tWWdvQxoCNC7VyF699/XboxyfvcIOujR7Et1BFkfxG63k1005doroqbITxblLw9OE517zULmtfk
U77a3JJSzNDDlc+kBI+nQXJyYhDBkq+vK71xQFSwfu1sdffam7eVhfM+mqGYgfHOaJHHjBNyGFg8
qDOU1o3s3i2q1v52tj9nrtSnVwl1tBuG+sF0EO3/XQezzLBNpujbXMg4b+RHUFrJFwmICODVU0uS
VnZQZmew1aYgp5OyHQXOSdeKSouIdyi4qz1vMretNxBE67h2SKgzPXeJj7hxIcvKwConcXUPMgFO
1gzQUWJ8lIlBTCMM4Nm2gBAHB9nVLm/K/TfdA6Y9LKCaCsgASZuL1ENXe/bgSXLTJsNZoh8XTmg9
Q/Vuv+OWrL1pxYQDxc0Jwww0+nqxAOpacKijsACDjIWvh0VOyasXG82krEsAcJ+6gZxXrB+ZDdyj
wkYOJVEwGL0S4V694nKICHDuqK+dDxDds8UacStYvlur1VoLce5gvpbnrxlL22aPRrsQXM/tipTC
78lQw3A8roh5rhwpLphV4qxeEpWGyJEbgcyTv5IYsw3FU5jEEPeFE5uL8jST0WmC1jX16goKopgY
ZpMbcWeurA8PGaKET3KRkWSiMy1/Q6xv/sEsXaGjGP9OO1K9uhIPGqdfp97I/XvXd4NL4JhBum0k
y5bHzmy29uAP3VPToC479Ay1+bOwHin0N3Xg9nC9XiSW9xjwXmy4u1+oX7v4ANerM28zZBbD1FNV
px+b549r7ZmbOkc3NiKSM0y3HdpSG44rJ46gJkkXPvVDRrZdOHVSOFtSfSl0nwvKYENep7pYk+4O
7imDuocKdNWfHdeSg+kkcQD2pphXO///eFqtl882KMc6M53fNy2VYpcCruE1ZJD0vpgqAJykxTg6
uTQSPsUhe+aoVVpUvKXtDdNssZK7/mO2wpEhnlL88xgI6OGLB1Aq+xW79o9rhWq7u5dcLhsoWVK9
jbSpNls1vz/uIm4Q5K4JYpjTxHhJDQCCEb7MLlUxXinI0iO7JDCgWtt7YlqNPkHeTp6D2iBAT03m
7dndfvQdgp2o0w6eADt+BOYt4RtXOTXcg9Va4E7YwVntX/kLir+oOtznP1Is6rcuXFMVB1U1g8zW
3mCL7+lJjyQSCDz3YaMavsU4TDDS7SioQigvWNzc+lLCPFXocY0tDbFHFWqe8acImPfPPQztBysO
Wkh4eAFDCTMOrFFt9wonk1sorbVS6fBqsvOyLEpj+w+w+PPy2Qq0bWJnvM2+6roCCAxSM42ypUHc
ZFNkuZQ4hmHE1rP/Hm+kT4L3j9KA2PaYhBERBKnTOsZ2/RJfbnY9rkmlhZBpCW5A2utGium959Gt
6GwUslMHyVSeElPBazWX6Mo7OOizW2dIw0s9tg0kh15b5GM4PHcAkhgTFrzuWC4C0yBctydDcOT4
WAl5F6iWey2CPqsa45Mj1Czmm5WdKhuRD7lwO4HqaZiDzuAdHM/fMkCwOK65mslu6TugxuzrY2kd
lPD+X/+0t6s8zWo1ZjysEnu2SRge5IVnkCQCFkbNJ/7IIuQm96Xma+QUk/iYPfFEfjtD6QeX9eIY
j9Bkm5Jyzp4E/RUWil1Y84Vds3h83nBW2bNHnv14HrnVJZHzHhWIOirDkAnGq5DH/u2ag3J/VzVQ
39l+1UV8Th4jI0zo1TVHf1Oz664o7WbnZfjLqjsTwSLFbJhX22Q3BHBAUuC5d1yo2Ca+DRTryca/
uqvg7mB9ZmHSMd0Kt6VFVLXiUHtSbDRUFsU6yzYd8iDT4LgB2/hTk4ceNWt+gmOHT7/lstx4+LOF
6+HMtcJBAzbh+vKz6q8F+xW/w5EBar8ubHgnVRn2bAiSrHl4cKGozRlaVQfuXXphw+p9qRBKPG8h
qVqgkREjveERZ3MWnqDgTwZ9syvkcA/qQwnktg0fYZB/+aQRDq3AABQOIfLf8HrhrajK448YE8YN
a6TINkpT2YEzL0XvPWJATri59twLaFy9wZhWXOVqDMQ/5E3iXr4KYLT2ROY3hFcdVPcTAg+tKi2L
nDCNKqLqYiGhiDQXpGDcHwYobDvEi4wLBl234epoQAKHbyp9loS/m9k3FXuE/WQAM6eJjKMtLB03
RdSUfVKEUET+x1A2YW3/kxt8tCVT2RMaeV5Qfa0JxaevtkLepS6EAfww7Xk/anZXj9r56GOdG6Y6
uZZp5OAX9e/AomQZlZAvieCxSX5NkTljEUHK1+fIjoBPLbRq6SbnyknqlwUM7gmPR5ULEqtJrsnD
+HA/qD2voK/jnhUeIpXrxFLNeAtsUm99BsQdbS+6SFksNueBOTWfOMLxnjGSKf2M5dvyed3I0nEM
Y87l3swkLptTvD88hS/YTb/Evpl1qWIwDh4FtB+CbcxQ1XuYM3vEUr9iW4LgYOymiVR2pGzsM5aY
0VdCBL8k+LOm5A8wHy//aFwlgp5kAGGF1izAmt4RQw35CWhwDgH8tmDpN4ctHUZnl0/nTMifJSe/
WY1AZxY6y17avs3zCK+j7SsXuH74Ho38qpBfN1mu3honYqo1VMUnuzc9SDqx6MlfJikxNCSXuGt5
Rft9TWgjSGnS6CNXb2DkjoEOEoP8G0dmWT9eAaKSQo05r3u0XznQfeFqVUm5cSTAv82lnWB/gNZD
9s2Fxn0yKL/n+DfWr7dbE6K5E1oGbI65KuHqCF9nGJBaW/8V2fQxdCtUBi9926WK2Zkwv4dYXU2+
vLq/XBWnbpwafD0N868blYM1bEkvK0CagA7djS74E48q7cQsCEYO6UkV/cxjpds3hl19ULQOpbOW
AsNZaqqbOfdjf/Q92YM3ObM699JNlfrq8bJeD17hoCUAkYo7JvLS7o8keBab0jMaGdvdOSdhfB3a
f/iHfPIOHioztP6Ltb847iv51oCNjV85t30V5s9VtehQI1Un17R9STcZyWNKFMvwb4rKM9zkCrzU
A43l/5Jz61YEZqfIonwc8NybrnGseOFXybGambwpQdFmdsBVD9Rr4I2SXG8H01NOcDIuaoJkAIkA
s1wB7ZE68SpdjmMPSDUhe6dVFuhn5hPDDpR1ddhL1l6/8kssTgP6ACfcz+bEr+B5vru96Ak3HQsV
f81NhBCW20mVwyLRE+LLFrwNu9qxt1jpJvNqd1IANiNp6vtea14uIGElifOEfsSszzwZWZWAGj97
JmMVEa0760f/tj8vBnEDH0jVzPJeKA04M76y7CvSizs96URPOKEYv+H2Ugx6uJPr/b57cue7B6Zz
iDA+Ljr/vWWdpd/INRMde8Q2ZAy88uEN/r6Lb15Th7Xx8FkGHEBV+e9a2Y/BP/fDiulT3Si610K6
PzEp7JG5fc61fmbqam6dD1vK8pqAHI91gJtBOE7x+xeAgOJJ9r8IIlQA+I7+uMoBcRbei7l8s1J7
CXZgtbQA7+y1bF1RU/YkUeW9CVShXtFxZlHsLg5NGOBTm3hXn5M+IM4NP4ysLopr/P+qSejB0aOe
S6fcgRAvcKOVEBFveeC+tiiip9dHm38f+qDPPH7EW+/iBZMdGE8tI/3SXGQP4/E2jMQFqyQRyj6/
uzMAwozpt+ZboY4WeHCdJ8Oao2lg186AcmpDKvfUty8VWQEPc/GKAs4PdoRLpDf0eAffnKNXAo0/
+rcUoQQ/NEZhLYFWvAmJmb4jWuMI4fprGbxp9Wq4pUB9BIU587pzIrlY1RkKCCPtGzkv3u0uNqBu
J3VUa8q8Fqp/3xfbIGfajZCUck1IoDsl6e19j4PHQgTGcyO3POksVCKb/4brdOYmuv1aga3yVRLR
VdGk53qKb+1v1nxa/xC5IAc+2EgaXGRnxaLnl2NPt0IpjlzuEOI7qFVBI8khRrlMBjELnClDFETx
3Lvvq1IFxhG33l9EhCckEMwSDJMZJG4mLqHih8YwvqJYy5cPlVSuERJqnI9bSmw2w6i5tS/xgVnC
dv7YJeDXpyuQW9lV5KQlkKj5+S7zYex33Suy7DThpJHejf+4bpnMwS7Zs0yVqxA/IV/gbgxpFiQA
p8dyVuQCbOMkLLGR3FBA3GVnxQon31wXOfeaeE8GudFwpEHLfM7q50O7id23Ecfryp9BcfUJTO+o
vFk9b6oxsbKQ31DVJInjPFOQDSwD94mdNU2U5Jman7l3Z3RrWUsVyIRKP2RolfhVWJSgWupYiI+6
jpvjh5d06XmD1BYGUH+JZ4/rlYabw48jxidoOfcwwzVKUf8WfEyDeUIqLi/UGipDT1p2Ub3+s0bA
6lCCeUpwVWNM+PnLFOV5lcHQN+fh27gKryS5KTRZms8mgKW03WjPDMK2DnbhWU00asY/6/NpFQ4k
N9OZ1mQTPy20ckIfhSqOsvMf15PlrjZJdJdkvjPXnjQNHG6gumU5YXSS65Tz4nbbPWsnxECCOAOz
i8wvt+AyM5A5ZX0zyH7ECgkGFqJf67UzoBUE6/FygFxuHB/SO4EwmG4OXgCBengS4qq7bjJhjN1H
ViT3ayRRRGuJvKoLyQYcMKkfeUryY2tVrSAdOSsfT9H5KCKu6tUtGqB8JVQX862rnR0dPPfacslm
jM34LOmMmfYcthZk/F9KnwFT1Ssq7kKVXP0NfBJ/o0HsyVuQ2v76yjKeBX/NoA+FOFcf9i+loiCQ
8FCg6dKuo40W+1CXmx+c8UXbPmWGsQKMpdSoWElRKQVaH6oQ9pOyI8tNCEl+sEKEuV6Z1l3hwW7s
AwswJn315+w1uGTdE0xYrfjHBWJjPUuRXhbrwtgoEacdlXbDOaaCimSmRslaY3r5Oc/mLmYyWwqM
tWN122UbisBKUw76eaawzNhEnvjoi2mvy5Sl6XsHyBmWuGaBlItXIXilUZiI5YLiA/Oh+ROR0XlS
ru5l27vEN8M6JJaqibEV3mb/iCok82GgcUQZVnCJsh3PPeFmuzn4IsOBc2pSswDE6CsX7tQnxdLW
eMEJCer6HMgCN+zDxPlrfLwmEVqrcGM3z29zE4m8mazY/yBBlBd+US8zP5B/E1Zwq6ZwJ/i/Jx+M
R39aXnb2BPnPQcDLhI5KJVJZ0WylkHGHz2hmMtZeVeS9hWf16mrFKetpMyxxNPmA6WjjadJL/S9x
gFzZsVqA0G0IMGbhi7DYqLxawOnFx5QqoROoW688kCrITcVhFOA8AZPcX5ytHWa2OSOFOzKH256+
FQ+DS0BF4nZ1HVDAfWAoOHKkYWcGhEkd39Z53URWJrWLD91uc3uw8X0anNDpnCdGe4FCGFS4enAi
HRs5ws/QdUF53fwfnNpD+cbRe2NfwTebwOkmU3O1mYHyHzmoc+RdidnCd507Kq2xANEfGI5NIqBo
7Q0G6pj5SqfcsxdTq9d4bPhyP2ifThnyJ38hJKIWCia8fZGYUbaeyJrhOqnODQWUyVSH6fHiwRto
OFSHJH4bJ6qJTcBA/61ZjwRO0Ewb2JVJyKNjaTpB0pXVtXge0YeXPXknfsU/TusZ9dZGdO+iTgMb
cprFQLIg/tn2AOdW5uIWV7URFpSSb81QHh9sjRkcuERz1+Izr2/JQ35pIsDDW3kLssNC9IngEX0l
rsswYS4a+neb8z8GmZdzbj4GHsr1BqvIE1DCrO5NJE7jvicAghRoGSQtl8cELxDCMuKhFS2Cj6ON
IT1EFUDdgQj28iVCGJiWKjDV297FUcAzbZFWimhE17X1vQlkKlpNz4dvYOkpWbfWEcE1y2r/wplx
oefUvR4YXyGR1Xxmz9gEWccMkI+uRZ3QiLCH6/Sb4g1RkSj5qVu2cE3J6luC0jhi/Rg9KZfaFOsM
YxgwTMfWEm3KDyoz+ncEW834X5YSfwJycm4QbqgtQMmrPpfy4Wbk3QdpoDjA48fD+WxilyNfQQM4
kuXh7qZueENR1HVGEYCE8fTnSUQg3XRzrr1OwpAVqr8ASoU+CEL/FY3H7hcNui+KOllLzXVK3nDQ
2cY5IRcpLo7HIR10IKb5eJPwzIHFCkz78/15TvEeyLJK4+HpQqj3xr4RWa0hs07lp5YiA+wiVV3t
1kcYcJd4yJEulSGfFtOl43l8CKZMzu7+Vfd1fHV/U4ttKnZR/zZuphsu0M7cLHr1b6K7cXvkWNie
E1tDcj+NDHcTK/HSvXb/gRkxwVki2gdzla0+KGw8m/Dwi7qQ0qxYHx6mAD3gh4TU+eappdZYJQji
EzUyGTNtbTrHIyO4ehFStKfw+1L6IinePNzKLinKw80vixuQIxlEfvzmhIVaeJJjU1pebkqUdzEB
4Ps+3HO/0RMv0SbL1RV8T1i8gOyCyEstfmrjf9lmU1BKwIIUWf5O6Suanids9v1hEayCek6R1UCG
clFmbJcoAi+uHNhGU90d1j+trW5JzvcpmE4QqU58fKPjJP6ZvYl6u1QjXZszjYSU7g9wO9swk1Eg
g+zciEGjuGUqrcNXo2pRcA7DAsMDnrOSUQqVHTdPeinKTEiswv0NUmPG+RkO4EjigQT8qb70qpRr
RVAydaetGsY/kotDS8O7ZeyVrjV5lCXDYx4TlvskESa6vA1UHwfceiap18CQG1QshYMdeXla2dfO
sJrSrbMIy5lePNfL7E50zINIfSzC+cNe2r4jwLOBu0ioiv9NrhmzpGRjf6/1d6YkEvvZVIrBZTFJ
/p6uzuyNY2eS36Id2/adNGNKj9l6dphc+BjhigJplKzcYYmpKA5R0XPQZRKq1ougUR1ip3dajLNu
bxGvtG9Ta+/qgrGtKkY9hg9AXXzFT+8MVz+82IZ25xFJxoVyfxuYKE2fJXXiztNHE0rXquAGA3DS
txQb9bV3VsHgbCdGiHdunpi3C+MiYsW3GeXXYV4PdusbD+3MEW8T+kwgpOCP/XwXd87MObuttXlk
BWiAJfF3O/VhQe4MBJqjv0FWVWgeMLnDidFnHammVimqhhFRM5p9XDR9yFHwjYEiOmCUlUG7WT+V
TnoPZ0lFlxA0v6qqoRdoKvxF1L+kf21l+aePX8jScj8ZLKhqZBD1zHelJGYElzC/yvGQp4dEqc9f
3bO/ficKPmf0FX/Ndve0Rc8530fGU/xRpmsw7AOqFsAHfzPJ2TKjK94RGAp8RkfZL34FDbQ8SDX/
ggK7nfv7hsaVF6DNPvTG01xkfZINGNxv/wNWRnDlq8xLaD8K/uTzQNLogJlH8Qcx0H2YAkzrSfdC
PCqoW/rSToQmUyz+uiUIeOwLN3vqos8Bjw1O+VSvrdFi2iC4neFmAnmpuQEkQlq6ZSD+i4cY6mZ6
eIg2W61Qk7mSHxt4QBVgxXhXRYBDXySWKaUq+XjRcuDgx7fwDSY5YAFy/RNJKOUTqxBk1Bv1zxgX
Qe0pE4QCnOis1bC8hFMQ9mBGbI1mkRdj27OecFAvaGMf5fmWIkuCvPbvSJQtTc7cLNJkroDxu0fv
Qb85f5jGOv0UyDznJbrsrLg9m4jXuUYtyyS+R26PqmkQmHsWFZydtqMEVD3b9YpXJH6fKD8WIt0D
dBgEN54jODe0XgkmAbJol5cq/0BOEO1iyRkaw0mcaBRWRXcZ2gO/K0fUvJ9HhpSOMBT2CPLqpmGB
EIqYjb2SbnLEMFk6UpHAVg2Wfl1kFH/2LfarE0tqN4kr67uYsV/NlsgXZgctEsjn7lZH/69sLMTr
1/TzjTpwNIeF3N2ITQeCXEAw9Kbrp7pBvHZ+cAykG/maS6ejK4VeJSNDkd8iXFZQJyv1unQPqiIL
f17i6xbmG8JH7VYMpmGpkaV2LWUVjDs+kjZ6WyevtwGmSgWqINoyMSVBe73EWVnPFuGsqIbbyn6i
ZOs/6eJO/3YwpxNWicZAF0VRt1lAfmswZye/iGl1RSJTGAxgCOUe+WpBZ9p5Mq9iWwJALD1va7XW
4zvM5ZjKZSGzD2dePxIVN3bFhQcp4WG3yiSXqnATbtnSW01YDXFyrBqDYlLgt2XASriiSbtbFPDM
wNqTrtUtxhWEn4LZ4n8iZhR6jhsZ42F5GUvErQtTZLubOu032/hoSTGHP7PP0qy2a1Sb7OFeRxEs
rCrM5QSQK9qZiS7niLcrLCXBWpAT+JfmKx+KFM47zupY6SDnR44JGgA0R43PjWeV7nGP1CIhXz7u
u606pIKbAyRf7MXXpfai+JL2Ue7F8D6BuJ/VU25MSjqdTArdSQ/wxaOy5hgzErJ9ZJeoNTrTMoV9
6WyLuMPOX53mS++qyfxLOYGsZ4JrCx4y7KCFiwCkgfAXVVwMhvGyb+a44GKUwi0OOJr+78uTkhaL
kuIdG4d8w06n256Npz0X5W1qID0JjcWb7KDqZB0eOieP9fybxnulM5ncyeaeC9WBU5D7vkaXZaVJ
IGa3y623IC0Tlzpm0xJIkYt+rq8gEEV850Bhy2bvtyERIHwUu4Fx/66nYDTBk2Zd9nE9C7A0s171
ner1sE/VaE4XROtGgAxWwzykOxwrjFDzB77Ol7tsYe5f/XlpOFiddrO8NUOgMGUI8ZkWIyl1KuMQ
+OiX2IOZWoFsqhC8nbbIAUJrtdKvPlB5oPwfMv4VcjEgNgj7ORItJMylYkAwpzadqOduCshxqNJL
5YEMwAJ3XGxnfFvtiDdfuqrdRQ5GdKsI+s9QCRwyfdyBo+j1mELhw29rAmzvM3ROxOaXFlXmXQlm
CRBoB1aQ0zk0fSpf06nsbIcNaWxoAE7JlC1KBzzYZXMhyWpAD3Wsb0nW/CxF9UGjPSoJzSWSqh/k
uAlR8xrhDatSvcUacyn4PgiaxKNRE3/8RL1mBreZ6biUUvU+DajTgdhxIKhSBYLZ2OZhndRSmaAS
c4knTR8uMER7xWJrKuDGMmAidF8wHyqxMBLPu7S39DeMUbFR7b3RFxEGbFtRQ6tUKWR3QOdDA5L5
Qnb8dF+BgsLLu9D44niwDk8qvzCazftPtzjFRlLNfNZlO14rPBojC0dB8ew4DoF4yYBuj7QsbHXE
0RSe5JRle89iCLaV9kHwyiGoy/U67Gc9x/n0jPqjJrkpfWg17YINoQyDEqt3pIvd8CvReeULEZ3c
kZvrVdZ/x+XCWNB5Q5Mxhs6zOhb4zlb5LJS+wCSyM+kF2gcSfa9r3lkvtBXZQwQYbol8phJRGF9d
9nFq1ALovcX3ItmL7MxEIb94O1xpGOde0wPueXwB4+2GolO9ZoYLD8Dj5SG5+OnGqYxMsCU6sf+V
TTAdTZAJmIoes+seYv9WYpkB8hC8R0IUozbR0o1SrHcWSBfeUrrVE7padEQcwGbdUnAo/KRqnM+G
91mEJEk5bINjvxdiPOu2a6RPC5i8OsrIj9xtFzub9d3zO6dZD0jZe5UEQTs36P3dbT1KoXfisKTc
6WtSGxTAro2PSjYNgD4mI3lJhRoeMv4yYHQ8nuWf1OGqzK9JpPKjSSvF+uEOo18iJQiB93itjCmf
ueGFQRyQyogkxbj7YY/T3OzyLBT2U4nRJqU3ST8nw5k86j8Euzw0r5C+ihd/fDvJ89CvbuPFYxX9
blohMOF8U0H/sXxyhGbC5mE+BFOOLkEYZEh6wzLwaSv+c+lh8luWhW+Vgtw+f2QjS6NoncfTIzM6
F7JfRsgxvfK7oTRHfJt3VVnMYUzxCK/CxqXZWkbRxwtr0S2dDdx7D0p0ePw5gXBOinb8PL1wIyU/
YrjWrDoNCGMwr5YdJvvxDki0xB5Wo5rw1+cGGesW7Aw78JkiCN9WPp7N1UhbUnD8+mmgk2JKe2tQ
BFJ2uaxZGIGP5ivDRpk0ufafuMMCehRncZ8jQ6n8jGk9c1Jzm4mTaVskKucPp/+yc7q0VWGWfw9n
5Do/6HW11QQz4my8M4InOf6qbKGsZFVm+57SxKKl3ih20vQtu8qyk0rZHyBNhvBD4yWyjqZU0SBd
oQGo6qqiMDrofZUFzSEpKFv+R56JwzQhTpkIpxbUX/84Yn0/yVjMdQX9M7vVHnSK0t6CYlSGCsME
qg0JGaJniD+aBJC5slP4gVmW/uJsb+garZJD/LUVb1Q/37N5scSpgaoJxA+9XIW1ZTdfpZ23kOGM
e6TLWs8AullhH6hL9wW61x18a3A9NafSwUBNlCQFxGxIh7QJcHENiEMQFPrYw58kq22j4a4eybba
xhJ1Mzk4nBgQUTvNMBrTLovUGJPKDOga7/c7MdlYhy/fNfMlcN2Hx/5cOakYJgQQUWS1DhHCyGun
4wB9mc268u7n2OBas2c9dfVlJEH2Yab05vqU0uSrF4td+W3n46hsNy9Q/tKs7S67UsIXdauKGixZ
iUnM/yz+Znzw9ZCUrGP+FQoTrLBf6Y/m9yZpKb5AqrB0t46eWbxXd3okBRPjRkLun/H/TIKgQiiX
lnHCvRyaoTduZ3WnUQYAzG1sX7nssoYC5AOUglBnaQittKmuDj2i8k/PEMEd2bq0ntpHjcTgwbkU
h13nYeG18dr3Js1H2UCUWFrt3A1YUu8f4wLUumUTH9Lz5brviaWzkmuEht70Sna6eL9gZQkz/jY6
/0U4B2THiai9r46bwVThUfZ/CLN6eDOem2sD5KV5EBdzc5UuAn9vdE0Z5ruVFQuN8Kb12KVdqL5U
8rTL0PwtV5Xpw7tzQiCSofY8gpiM5K4pKuA9jPEYgq/tZanY3ayclQfnUtt8ZAo70WqqKO3BmYwg
KIw+fTQaG7hJ/fM/gNjbZaBQQvmgMy6Cm1qcYcdmrZxe5L6Jl+3y3GUOX/MuoFk6o+HCOULqpdJg
IW6lQi0t1wHH/ZgHfpOY+q9x45Z1C0orzxObvycYjXesY9KMTm9A2Y50IdZMDM0DlIJcN+jK/1xe
dRvp7s+uWqNv2lcu0XFQ4icxwG/YHJdJ4/xyBAM5WCD+oXn6NYTnBbz34oKBmszGzrPmqRCF4wGt
lXE1wXqC8tXpRfJjkYTwCC3bPghPz6Y6TfvgXzNEEgQ9t7XW4rcYce876AmbrK1mYvjsQ9S22TXG
jtORMnwXwaT9mf5iCPjfwA4rpmieFS75HwIj4O+EHUpM4HTR0VWs0McGXiAbIF2MzPJSqrfHLVvB
D9G2s2C2ejVHN2OF96L4qWxKtsVthFoKx9wDN7qGgP3CLuGwd01XW6muoBQrKvGrAGZK3e1lu6g8
J5KjZOM1XzemRLJ87bS/CFq7FPCJPd7CQ10ukb7MnVkOeOElg/1It87ucelTFwPA3gLGh8lg+Fym
WpPg+thk4wgXQyKR3VGp3VYXHbdBt0sDSd/KWuZbu14fPpuIJsvX08KjJHAc7aw+OjEA16Ozz36T
FB4cRsw19JqL3EDVfYU3MIvCdDeImhjWTsRfy7z0ZUoz1Bz/bJ3Wwip13YCtU6b4NxEzINLf8WSv
YdQ2is2zgC7sxaihSF4fiGB8WEKPBMb8NQW+Gu21cW5+fRiXvOuJxQvRITstoUpWOLPARjmyOpCo
IcEr/CoVNTqXX251lJV7QglX+bqs6W1nDJ7UHiVtCDk13mCnJCHvql6yHg4qAJpNzDXo94QmfjjR
Mvp/dYtAQP0DbAfuZbnFDF1glyWxRpW0TDenO90gT0MD9TmZpT8/3+mOxiMekiWmcZ/PNK2oeAWm
7QOU/IswDU7fFwnBDLP3/VikwUZsOCeqoBzsntGuNvE8bIseexetTgEvb7D3GnmpPtX8By2E9mT4
B56YNDlF308l5BQcsrT0nI4RoWB19S4rrDY/mcUxMBczafXjJ6N1K4TjXQyOlUtPuj8n1bJ/4KAf
GzVzZmo7zvCrXGcRySGCxSZfM0pltdrMdywbdU2KfkyBzmkQR72WjqAEDSA2TmNJ0DHs/Rn7FF5N
51RM4u/NhV9farK7jnjpvz7LbcwD3l3On+y/llvEiQ1TNqlalFT7PilTIt03Ui09giSPXomNya/h
YxUrprOuLfT/I/Mu6y9FjrBv3c76URXAi682uLT1N4Lm9yxH7/bNSMtlprChr4wn89qRncK0IfXR
LPV3pKhVzcUTB+DNtx4AfGHElOpvN3r770rqPx4VFbiwQFVEkgobG4CzC+MwHCOyIozh4CuKfDSB
SfXcuWDvN6pU0Mna6pqkkvjc3YDqMvTWJGQnOEcUjnoI1f2NzITt46xvbmTZ7Blr1J/n0Fuv0GfR
fsdvHnmHDktzPFqhneQurCBDSL7QjpefmOK1KoARaUOnfAOlvG2TMR6AneWq4eNT70k4sqwsWpZ2
44NAOaoredxTToIzeT9g+doaXcH5h5ZivjAr+SRteOfb2aHKj2g0KL7VUQ07TdvB+MGhfqR06SC2
yV7VYIS9FOnsjw5cy0RyCSgkfOKcw4LBUwaVDKXsIBdc9Ple2i6Xz+XBMRDzRhyVBNOGSs8fYXnd
W9yMMU7fuXqYSFOKpyBYcYezAlIJHuje0jtJfysjzlj8tCNP7zVFODRrXjTIOrb6rSB3/Ei+zCEY
Sfcc19ZoYoxFA6w+snncpk2ImIJFqZkl2Moetvay0zlr+MGHVsU3TPAfxAsA3ge54CCgZv4iiM4w
Z0Eq9IToM0UFguFKd/IK9bQ+oQWzxl1lWRj0+kK59+QiVbO5Hgb8gYLcsj/Qk65T5YhtKA3L2SRN
wd/ugFb7W9FAc7/OxZ0zRDytitwI9NxlMchCeJ8Tyvm8nYTzifxMThzB9eg4QVq2UOvT1KPesJS9
9bfj7PVL5a83wMbyL942joVfUHvx23fZ1aeLZC2pHT+kp3Ahl+Tl4d+rIQYk0G5FnEgq5H2EjM9D
PeIJ4ReO6GV/Uw/aO+sq2HBa3OmxJgAmOee5md8EiZ+h0VLjvM3+0oTiAbM0+SJD1tWcd4C9mQIW
V7y/Rl//iK0ETI/u2f37a8fmcsvkZ6uN6liGijP99ePBYEUKqF22XQd7G0ojbmIwqMy6IysG7ifv
fjKVMquJWd8koDul58YPDf/rpVFKbG1eeK04johS51cUun+MHbzilAdbowCSyuOQx6xu28dmoNTr
bkwrBn9yCe0js8hA1F9x5ejQCdYnEtfp539IsfV4zqzb6Do5kb2E9IvvHKxr9O/KXpoITVbK1qny
sYoDetCWmLroKLi1+E6E1x/bwwbEl/NDaccooiV5ZzJsgXqvB5FBAyoF/rLXpXVqp/1GUvUzNBXC
Kmk4a49e7BLMgy0pr18Zd/OQlEHUwYMjAa0RU3JlRuirH5dEUwe1n6GjdftuoX2gNXvUSvEbiqIc
9g4Ru0LN5uxDCcGirRO8KU68U2UjS2AmSUCfSgnyYI9br06pq9N0o5uxyRx91ehOkr8fqywvLxN0
hYp+u6n6x3RHiIO1ZgSu3+DNxvRk8zD9JYMcTrWsiY0al+2SC3bNrxI+IXD5BfW6X8RzyuWMyBU6
7MuZooAf7uAf2tUv8N2xhAqYSyP7nzXhEo5fptFNJIGnUZyIm5YXvVsEevuzm2LVqMffA4Yk4++P
iSLBnohuWUlWCg92MRgLn1dNZICb1n6txWr1Ty+3BrzzNHEObU612Uh6q8PlwYBbRtaxGi0if83U
YO9+Uy0L77rdPVET5TqfLPguzz4oO3T+7D0uaCRAbPno/6ii1JyNQyeu4FVNJDN3Yqlg7017o/ij
547MLEODsz5Jb/+HVQwBVCs1Wm/wQ3RmYWamCvtv5y2pvkpa86gVi43OmIQIpTueapWvOY3T0BBX
ZTM/tKmQ1C+UnTdHvDRCK5CEen/AXEoAv9uSCnqOP9xuPTwoJyQf4xiJRg7jUeLG5jOVTfsRdGW4
Ew6tscxz486A8zhH0vJdZdS0sgp9n2duLtrollbWWjIGGxeQxyXwMKy13CLn/B27vF4a9iugGKSx
hLXeeFnFUTl4aQPucWjkL8gYJ2MAJ+jhQUzBCLMsy6LAA2WQpHozM5c1+tTzqYuruEfpVpVLLzn1
Xc7JBoWCsNHQ9LiIsaZ8ZK6PLMlzEsWWQAbsawqgGjqKV8/W3fhpgjedjGaFPH+7Mul15Bo7qy2f
lfHR/66kTd0UwupREUMNkVSaGTsRingykd6+Qeddn0mZfIyU/oOQmz9YE/W9KcS90qyzZ44MXF51
DFUA272hDX/62QDZOpW5AGO0ez3oXwbDIwVEGSEgJahkljSpzzDrpi/21A0c8pGu2MSD/ppybA8n
V9I3MvkKzKtekPb3G4CnzxH/kRCpheLVaLmzLQRbzq2zRRnXvzYmMPliZd/HlLLfheex7PsEicb8
CqSD6TDXHqiV6Y3o+NGCAAioNx93EvlDzf4zCI0+Ref5CWTQUqu+q0i3q4X6rKBsJBDoHeez+XSD
y1JYlrhTtPbrG3KUvunKEsATCYq5kiYreJKTzN9+h3PZQhm7byRfEB9KrPt/Xi0J2qe/gFzegCn5
6u4ld1zv86OK3tH4AeGMgqhtbm/0geR00CYH+9CQQ2uGnMqAyXC8Y7Y49EuOVvYt6IA9KSeLF7ns
ZOCexi7q5lL+1e6i96KCRE8yrSDeARYssGRdrRi3foUPyP7TvWBRc0SxzsPWzRu5GdBE8CtE6rkg
SJvI43E484O++kyR7RbKFtYp1wQ6Lh3kKpXagCeNviEo462oL35mmMoR1/f4JDZxqIvEHDlLn5bA
dJD3a0aLorKgzX1SReQNpOjwc3q69qzYeZOrFZBclooU2GnEW7vIw+3U6tGgiOgxP9fNXc1b92H7
iUFug+FTD2xvUFS1glIPPNw5PRnnEFaENdjLL+0pqqdaYbXzy97FaznAD0WkbRGkkAY7Dc8AM1cT
Qx/oiCCKxk1n2qnwid/dWtR6MK3/8FxKSSOpWJIixyC0RKEmcNqWEGiuh5Rqp1lsdEKgirqYL+Dp
5Zfm36MBa1rMmAUMEhktaGISooll8ArUtf1TbVksH7mX4i4/xnh0xjRjF+cgThlTuSAUTYSpyGQ/
UEuK+NpETGnfb/5QABbNZD9bqKCAes+yUpc74Y9AuWjmM3JHu4jgdOjpcua1/8UG7p6ANnnewTs1
grPNTqsnw8BmnYXeCIcGALQQCoYOPQju0xYsoN2OnJkG/bXp6LamQ6hiC4b2ja0SKDEUDQsfErDd
4eDN/VbvCt+JtS966V9DnnCWk1lSaOy4NGiW5bXMSBF+s8ceK0G7rBSpJ4b1LLwjy4WN7IswpMh9
5lFlNmkVy3V319KOvBzixmBZB8iMCZRHDEqmNKY3ixHHJoIHdbpKBHv9Blq3ZAXrkfrxJ+2Mx5ee
IPZVpFZczpsw9fXZVd6SQd3uZaIwLWisQHuUrGB4gLN0oxS+YbyTD2L2YpJ8JMBJ516g0yVaCWot
3rlV3r62j1mOIY3Ij2Iof3CuV3nmKZwPcebAZzdifwXst3/t9mPJ4VSqFQgnbnNGBcxZBQZIYgK6
Y/YXlkWGu96NA17m5NF/v0GHa7QZsx5ohmRSx9a35fTroyoc9X+jXdvpIobQGPeADOXBP/qCzAjM
WJVjCO+jHTnayWoWfZfb6+9b4G3NqFVF9M8wSUlUM8keDjoXZSBhwYH1sMcAalsfW1CG2xotkxtE
3gid6HTS2ZRrvoMFf1ll5zPGkWxZHby82PWR9Ys/sIUwRCIjp9XAw5P99QT33E9kB6Tw8Kw4T3NZ
rN1ObfE0WXMx2VB3D6ndnaQxAGRTua2alafVDH1VlThZZTnFypu+8t0uRg2Av5hhf8I/r/oynvao
5c/tUZFRaH9U8aOeHYN35T2AjN8RCSC20nVmEF0wz1Yta1PJpJ1+B224gpJ1+IJZkWVL7C8SSSgA
oYXHU8pIJULcxVJv/P/J+viBtqx6g8vKw7dXyMZi6/Ek05MchQwkQEGWCw8Hfoj94nzyiJF8bks4
XFaSZ6fhzfttI1ZKWJEqFkh/XjG7un4GBwAEf0ysF2xukMD4oUfwXQ37qhyGwSQ7YYETL9eDmSDs
aC5JTUQGyaV8eyYU1qjy9EG2SE5f4OaEKv81exL+6AtNQx6W5i1WyeHgNz4cZ+27lhdTVzF1v9Fo
VtRIpZwLPxFtNg/PtW+GBxJEo1SEoyV23g4zs87Fn54kCaNWXogCxp6ZWnmCwN+16bAr9oN3iq7r
hLhixJVmb2DlzkbInKomPITCItAZuO03/1UrmO+rRgm1D3XUHzKXco0lUTnY31j2Yc9NK/VAp7hp
aWr0tkVShopxDLutyrAEmLKlHQfBCwz9aVPK8QQJiuG6xllOfVsBg88lKH9+2XEDB8MomTrW2o3F
9GNXFusNn3hEsL6bcZ0Zreb7iKYe+QcWbRPh1gsSMxvFmElSBLHQDWx2VcIP7An2P8sg0p0gwcr8
wEpJvKCdESvNtpbF5jHdvg77HIWei0ZF9IhaJyLBVo89x5qZ1tbYtj4zKldtQMq8wyw+B8VnsrGj
8TGEDJCYUawJnEQ1Xb4xYeEq7QwUK+WNGDs9vXGJNz7PPdzMJHuXJ+AB9R/+e+a31UDvHpxl/4Yo
lzED+Z2dnPm8qoWKhhakzVzGg2WLnZj+rNNuF8gPenOcfCXrpuxX/JygKI4mMB20kVf/qk3pFLNg
tcN2kJIfEEltP6ULmBgMnFyoHRNt3Q423RywVSnrx9PKPqiTE+qPNowRSLWjkOf5NhCRUiAMvcvi
w6LbIsaNs7b2GmgoLFJf4DIxtBhAAp3C6k/nppshBuhxZ1FOw6lfDVwELVOALxup64z1HfKMpfub
osjKNyWMMqSjzlxOJvXypmqAWVN/NU8JctzX+TiA+TluZfz5p6dlJqeF5+z9koI95Yqm4zh3CB1w
IF2DFv0oArOpYXsyfDruUKFKkSbZcMbk6+AyTDvkj2m7ufcpLrflMACBReaRoJY9fcM1SyEgtVI0
roktxJ8LqV7QxOt73AD1pDT0R/sX2BpgK2YUHKYLK8SGvMaCZazOxhd0s5mlurAwBr5pybTr4Fue
95nbjLwydSH0/04QRMY/oSw9kjT1jmHcWbRyZHg21+BC9GKzhZVESZpREfBMVKQTXDyxBN4L5bV2
JgPHhNV7Rk2KL8O4uXDog9VPMJAxGP6tQsWvoHdRQInYN76hwp/CHvUTYmQ8F/V3/Py+MRcEo9uQ
rEGbKIMrgj9XCs+TC2Sqr7smBCTxvJUfZIsmUXcrlgWFNKPixQhTnsNgaZ9ITrCQeCaGXxmx8/bm
Eruu5COYODZw4hJn41p9trxNiLpN8nsOLo58fKgRxUmMqfL1pWu64HvIAwNn8i6PuUkGxvVmrMvm
t59yg4BxqaVcP7n4jaoaNuHsS+8IHCWFrKG0WJeidk9/yTpFyPJDX61ZOz3TuMCOvZWdIJKv4ecw
X9Esh1GK1SbWFvIpPWN1k86+iSsBwrsraWcEgCc4Oz0m/tZ5ZaQb0PL9bu1pGClogkpIdmzFqrnk
bg5cSywYHZvxu+kMqe86WhCn6Cne+5fy7zQvjOa7idFK9NpXDDJEJQ/MmI6YF33JfgyqSMQgBd9t
aaVeRIGBmo+ZlmdoXVpPfWVQd4PeREnh47MT3SuaI3IkmsEKEyMfp190mE3afeH81MhO234oY3NX
1ssruxtcCctNE1KFdZPXZoqcbGxpFBPtZ1HCyn5IOl+UkvvvjQy/rRnORJwHF1S9qgC5/DjQpqrj
dMwBTGVoYHRmr8LHD4hQ+zHwwQXHU9M8iSc8JZt9T9r1AMof7f0njpkF/fTGMU4CIQF+OZK9QCqO
3rbHvGeB67CAgN9xhJsuY+Os4bp+AL6u4VtjFSZMFLh+oMIYSB3aO02Bi3iPAH2is4cgSdL9QzOE
oX6H9MjyrsF1KOc4jbaQAiwpfaY+IeJZ6YJTZBcW2dHRLqupe77iF6pjD5dW78UwOxaSLtvlsdSp
vlUr54v/IczzbQuPqhxBGkgwESwk0/FNc/1nazLtD4nsAkG7IUzv+qzgIXekFILxyCvUtUmDZMOK
GiAptnCnzK7HvaME3UwWby8kHmXMl43o3I4ihYshmfRoJgsarVbzbbzjQZFt7tt1S0tg79v5aqHV
7HaKEzZO7XSahN1Qyex0GT43T7o7B9VRbHpyQd77TZNi+63RZeEFFw2Dkzw+qcOzBJ8vbzcylseB
acsPcDce2cgNubf7QDGDlyoovPA7mfz/own6QajEbVDhdNwIBxp/EkXBeG/mDwyOe9ekH3f3PbFQ
kDQrNIOkWpOa1ppGqcK9x56dgv/wV6Tu0gzVfwzJ67ai2Dm9/8U5YfTj/B+GaLwT13j3rn5dMVa0
AhhUUG1F3seUO7XaAQ6ES1e09M36eJQx1+Tv1A3Ba7/VYfGkNwkOI9g5OS0OLgN+apYfEGYaTDfd
oNz4vlMrxj/XPf4VhtmOV6eTVs8gSqghQ3YOndl/HHdUAmplmJoisvQw4PUTLgNZiR1MU2YkrdgS
D1iMHZZ0b0lwKFhkTcGz4JNXAeiop01z7KOy74ZJZUQoMx01N0oo7zLEoBLI/eaLn4IbIhKmEeDB
dTYxbkfUhAT0KQsp0MVf+yci3EIPV8n/O33gYA3XNKcVDRotrWlockvom5V/wa57D1rhJ6RSLUBb
bBqCAlarOuGvRkEONrLFUPntc3TwW0susxohidDshQMig8IgUskBrReSRtbB+oFPf/lrYxknvTJ2
tNiGpwqtF0dE4xT8OBo53qX0DSDxoJUbpuX2TPEd9T1oMH9DuozMgnTbBpA2X9pLD5Tf5x6jNEQS
bFbzIFaDOX/R+e+Fz7lZZgV4DIqGMkG4rajwkjVnlKRPV9VUu5vWIyWG2zQ62F2q8oWRsXyvrqaV
Jw1Hj1NsGFEjgPglHfIjcK7sMsl8fkCF9Np6dhOYkhfbSWUYq9UiAFUUKH55Vc27t5/j1+Oq83M4
SLmAkfv+R+zul53uGlaP6sksPyTuTq0/hicNSN+7ieUrI5vHapvDEwisSfihRIZYtgFX/Sc8wIRM
Lpiym07RYRJiDM9u4X188V25pfVndkg3px0pRfr48HdCtbdtf0ULoj1NkzzsIHpujn3Ngs/mTdM5
6C/5B3NvEjl21bZckBLpMJiwS23ieApPWQUeXB15osWVcSlHkpwD8xXG51YHEO2fZ4wN0NXEDVQP
8FpGmkQBCccYK3l+NfuyU2xWHo36Tq1Ojm4SNSQZX6vKXHihKVcOht8wLykOW7D5Pj5S6qpqJlTp
FxatvMpigiLK4rwgl8ZjebdVHuxmP95+ZkF52j7mMgTIqbO0+AuuiCWnpfbaw5exTbcQ5tK0bTic
CvSuR+egrdJClGeGGpvh37zw/DMAi2zuQ3LTMuTbsP9tGEam1mQgzDUJgUexKEbqLA91JJyrU8KK
rL/69bdpwW5YihEhHpDFOJfxVUB7TQsEf21he4tXTxj4vLERoiKwc5PJOze7wA002LJHd4WUI4wb
ullyP14iyCMn9vRVjzE39Or6RdapCFS2VHXlWxTmZAiRPbeUGmhA6wdTpl9fD7X7M2WHsJ7p8pxQ
yEJJkInBdZo5Zwna7zv8HCV361oUK38EI+ezXn+7E+hHlmbmERwBaX9uNPZkrDvrJJS3kx4NY6+w
812FtJlZXx9imHcRstzijSdNaUBECKui+MrcKvOf9P1XavhbIlYF6uLvaK0jmxJM+HftOl0hpvKX
MXhw/k2Dz1fnH4UCbtzjZnb1NWxU5BYtyOaoYVL62vk9JZ7JleH6TfptpaHJMFCgsdZGIniOfKK9
GG3jzuFZMag5O1sIwfCJMnTHNkbe/EDtEZVV5T0B+g9UVRuAma9skDz8LDVq+NxsUaosOAhDSwXd
htcF+TaliKZet+ZT9ir/KSegv3ppJBlmjkHTa6hFjyHhLAIsZgNczQzatTvLsvqm8P9+vZI8LdWq
2vZPHK3KVDCYZIXRSTdm8TH2AD5T4W57gGbKwQXqOHW/iQrYTSfI8zFh2EXtdXNzHMe1wzyiykzF
46dWK4Dn4CmmtKvMfuyZ0Uqb7HKI7NgSdYKVs4woPwal6lG+IYuLRxPXFnHRo37DsSoeREC/PICg
U3wnwLz0zeMzVsCQmRKyYhM5WvtlOMvvgmWxlSZGpsD1bQfE0pBWrgEGbS6TeQU9o4cpn6AG1Z/4
U03pqu+qtmuVKr5D9ksZmCcpNAbPDehtBAVYHpkpIqyrSjRZFU7kRHiOKZxqskCv7diHBN9IL4JM
854OLEPP3Wdtyj3vmZOqnxg4ejfvrp4bt1GHv1mT3T1TmtS0IMMPnNzoyd+YYkzR1BbEcaeVtQuf
jasttnL9Kbu3xsP8w48ED77FX1ocCASy6A4La3hb4OrvAzPXfyqRodIIaCdEuIppfTB18NXqeZS/
yduLfb/lh+xf/hrxwn5rbGzHdN7eUyzP42M7OoRZ0NYrqYewRcHFEmLNAw7AYU2RdITUjwq+tIYD
NtXDGgF+MBmzf00Zvcya2lpHyRuUAbc40mdXbU+wA5311XwhNOixDQLga60Z9X+xYqB3rBWXW8ME
hKlN0Y2v/mrQqcg6WxREJBUjYhLuZs6pTXSow+DlnFpKwjMopNErPWggSiETPr0E4/zxfdJo3fVr
n3CD4S1bqrGZ0V84SBLRXBfop80GCEy9i+2KQfhgpDVXCFwTJXbRtRvpL52KyINMCa1J75a7eyhN
P6XyT3ucAlzacQLOucT9afHtczHt0LcZZ7UqtQXxODvNfEVnMRQO973jPEDD0ai4Cp0R14JNGtK5
YIVcPVhuL/jyxKT0oslUVVf1yl6UzsZ+IMGDzFLZiFUIHB1B15+lAxVgrx83uUpxGGe59ax9KOn+
PIq7HGRBcCl63ErZmnFlx2SUwAcDIo8NqnPYoooYtAYmNC0EiBFHVV8AJH0RE/HIME8jaKtHZYqc
cQpjg+9R/aAYqL2fx/QKbdtCKWtfgm/GcwfeNylsZ43n8mdRU6JV5h3PO0PkmFEdP2fayp3kSS0D
Q2LiuqdCMQ6yk1LLQT15WGopmQL3xGE5XJqXauSaGWXfY/+Z+HhYREcoDu/D1/x8dRxY/GyioiVD
bTrRRRP8Ozo+i//Rr8jsO3yC09dD3vJ3V5sfHnJTo3n69Xm8Zb5dMZ481Xi0f4v0/FyhxYMycAq7
Nvtgnb0c21yLpdMbJ6JF5yIsgHd2sqdJ2B2QxeUxK3C+RRaVNm2taRx5ZfyfVsk5MCIKhcwjCh0A
eX8WxccA+A7eGiGPOVQSh6gd2CbeoQzYK/Ez3eU11Z4bZQ/fsf5z2X0OwgagnfZanp51+k9CKXMl
Rd6z4vfE1S56509I5qAjWmasU9ckAZ/nUA7ANWcC7QNW2O+YaurYmRE7Tx5rSM9wL35OJBySvzjv
23GgeWhKx51kB0CT6TEi6CjY0HSKGXpyddHSqJRdEa8/MPnNc7V2RUmZ0aN+cGYxG3TkpjrtDJfG
G9AdCLMq/VBpQd34/cd6whuC+aZ5JnSEf1Ar+l11iEtZ87HLkzI44ZZj4as65ZzGTwWYD5Bepnac
iU45BDvLalLfWVWIJrhMDMqnKR4d7ZfYij2kbWvgSu+/NgylySucBj1sRyumUobBFCavyM7v7W5+
WATIl7dLavU8f0vK7gFu4vKQEWVxjU7iz20Jo/OLmm0s+I6ztAO/4ahwGWS5YW39JajQExEGIPyZ
B8f/i9OCXrlLul6qN1qF78j0fZpqvNkJVwIPo4HxZo+bIiG0J5KlSIvg/P0relRZcSoJC00tfRol
bRWVMGycnajE7afxXscjMkhnBCMvNnfFwpI05pn9/CDcfDxB8Sb7Ip0fIymCwpVCguVMqwLtl2L2
m8Bgx813bOtLNUQRu0q5V/a5hHIKAdWGVz2o/cWrOpL9K5n+oZbY12xWrpZkthi6+k+Y93z+zbmh
tcbsulPY8fowIs3DLw2Dg48Cd6UDCUk2Lp8+YCCf5vJ4XvPtnMYxXazxGUeBjXV88eOiW5Rn9YKq
GZcVv5CXDhbO9Yv3cOZK58xwUJKdDG/rMgr0XzDiXRs4WDm/EIDJZc3iWxgT9rbsPteNtOwCnUoZ
lkFXhaHVtaLuYdAbhDb8dAmyFEVas68PtzPrvXKHX8m9GyZQQG1qoZpUlFGmpaNhiKxr5abCwnk2
lTi82uGV/epI+nFWWb27xupKET6xFpui1FDQ7FJnGa/2i9M/JYayTm0xmiTgaZ+9dhAOB5EwrxoF
4/GPHuJ+t3Y0VjdUru93eyG5etVEyNIlTHv2ytNEprKlFIXgtEdOjR7/aHBZWM2ZFYK7mXMEOf2z
QSCnCeSYdEEAsHgqpPXt3eQG4lHAYCdsv9vc+oo1vAMeFM9QCbQYHkrZM5tsxnjbjivFtjzJcQ+D
A1YgPBoYKzbmC0hIlzQKtaRoeAlijNLsSH+kK3KBe/2dH7p3REPNmtEmFNrxXFDA7PaB7ZJjRAdQ
Qf6ycusLinbmGmmYPOjVKIN3XhchlUMLrTCxEwyLT7VK32XfxUPz3+B9yDihh6Zb/VbmKIpow/HA
BIfSAoOkkie8LJAptySAst0W+fzcCMyMWGyMWEvY8MY+jR5LwfxdMCV52WKG3/y/qDYrlKgy9fh6
KN6ylPGMCep2ItMvN5OT5EI/7HVOz2B4zGmOTPVQsk60woS2LURYGLZepya7qqoc7CSXboLL2lX7
ochUx2VcEpljtfHZ+yfHrXSAX+PE+pOuy+9bjQjkfSHrArmPgOYIqe0d60AydpUjE7bZnJ9Fhg4O
Zz75DSqBBIOPMBG5ohu3J+VzoF2obYucxKMNkqsGgh/GbdkryIZW/0RKTJvX9Frmyn5tgQVTeglF
GJ/5kMKfQYzE4Bk0xEFHgcOFHRBd0nBq2VYsgY2x3Fv8tx4Ff0NZMTtVyW7/9icDkG4X8OofxJhC
e8QnZDKR3IlSZB6tU5/0joh4nMwf1+b4J59ElFlQrUJtkTLpeJIaCOkJzV2fqrBdON8zMcHNuJOq
Njxkdez6BqgHAttxGvi50H9KGeA+8MevE43iEu9e6rxoXGrpBQDZeP1Xrm4FJI8KBL/YEOwdeVHn
am1wNYk/AS8C3dFCV4izYRyqGv/H0Gl70FjCpDl9UxMCkJ+PoFO3y99NxzNgCtvQF0m1KkLxaj4m
iygY6UxUw3QMJ6bfH1CHygGXqzCT/ofbOCPRVoCbAFCrcokzc2229CDfpfJzokl+v8CZnRP9cQPH
GpV3mneDxpjQhVqCagTbc1vZ4mcZGV1C1AZxJMytO+LLI5m1bkYrZL+/jPsLD+5yYB74KhGxBQ9F
jeFSpCIif34cwHV9uO4VNCjH7W+8sGtnynkARJn5At+Er5TdppxismAfpTxLi1r8Lrp7LK9Z75i3
YjdV1nPWSDCci/Dg6ech4qDSLygjRTuz3KCi86R12++WTBUW4IjQ9D5diKSxjqkdJsd9v3FfSUAW
rpfAwnTKO/En8GPq/MuVwvSJAi2xjrzRElByk7K/SYTv61DH0B21KXcZ9JB6h2Y8hDxQ/cFlBu3h
tUk10TJr6yYyravYfCesBFo00/4BtwaC166rYLdYB3nY1b99OLrrLVqJ15/Yz0/5SlKrVSywFLxK
PbUYmJBAZIlRdYq9vXw6nkf32/2AsOG4rcTbOSpHaixhSYLAjAJhd44jq/IDatWGQW2sEJhMymsT
A4OxHXF6SOctWgzPkJGwcmko3+MZl7F8fwaEt/i3g6KXSV3vCVrO/eEiBRlBw+14a3psbsxXI/bL
SonX/8S/ED6o06CjEdbrnjPRolodcWb1ACC7ZzFNzBwqk0Fe5YMv+oQhTG0DNduJf5aCdFa6PRMq
vy9Tkv4XTwL5ibDY6SAmi7Xi7H0RO+S49VjT7GXP4CkeSkr4ixCfpkkTpwI4gAxwp8+QgUkm5ML8
AM0bXilqz04VuRjideaJbK1ibQjqt95B/izXik3GXvw+NH2rfUDN5NqzaAgz2apTrseeNdEGWP4J
BENMACigCK7cvK29zxxdb94OFkg1ok/z9r4SAS1AUQBvrNUvMRum9g/xt6qe8/EcR9Hd8MTNuPMw
dVJWaFAg6/fgENKFT8HGPmCA9gkc+7FyBe7u2bNuBj4LUu7PB282gJBzHY8mnQxIor/HtQtLhhdb
FsNafqIgKyyHg0JJRAp5Xl5nDINaAbOt2Sx4uvmiG16U6sx+hzAZvsy+aNmhB5Vr0Td8KMMOsg54
Lmi6eW9xZTUASfeyGKMsN+nSw5Z5+Q5uZ0YPbtmfQmcPg1h7SPYGE7p9+P4B3viVPOrhZKHF/i98
StpoQNtpu/VqGhRUPuEo7LikfoH9Pob5PDD9qu7/Kkxk2ev6Zcc1l6lRFMUrByg+KV2WrIkXZ8tn
rBDrlDftRFETjmyx/1ntOd3ATkuuQXuKV8u8w4zzKDfgfyWsxzjpL+vD+kUXjnLfDt6a9cXtpPHL
x3xdShzDZ9ezFJOvr0Nwu9ihTNWTMOSlWhhWPkBTKZET+mLZTlFYai9SgPen1zCaneMJEXYo+Q2J
T+cHIXMgAsbgV1VbJ0h3DgbJT4kZm9QtQRYrhvbZBsnmcV+q1Zw1Co0ktXI6haDRoOKBmTtR/XQa
bvxx43ySz0Ti2leVtUt0DP05xcd0Xosns4Va0eRdKBJjInfcfkjhkl0EOsTwPmVBPSk73zHF47Yw
Rui1m0bWEcozv7UQk7mMNw7jyqBIrT39ymlHUSHua0Ym+aRea+xk7up4KB6uqlx3RNGf0GJ1+5HY
AZDXjc09CAyOZo+aiLyL70LrTtwUeiEzfOq6LonfVb1SZD910tiunsw7K9ONQdJlcTa/0qArHA40
e8/qq+teYRZj1rw/hpG0S6uWq/ZlVneXUPNSvRxGizmQrfj1fynCe9ztCePbR4oyWk3ej0f9WQXi
64dbVny4EnJ8T2tGkkZXwJqlOZlx1r/40wV4KpPkqCVHD/t7TGq9jtlWh8cv998y35zm3O1ijfag
HE8C2be5r/xTK4/NaF6mqc9SF6hJ4ZO8Lg0me/ubNrloqo65v4pI82Ui0EWK4oRjbRlhB3lL6d7Z
HmW//cj9MU2xrGhu3QALRZsdxn7BHv8kS1AfAqjgp8AnLjr06QXXTYxWCRnj5g9MPlg0WhD/tlmT
JauTCDomh5qiki0pUb8U+770gffcMmy976oraPWnhyvaSznXyj4eZtlJAZrtfb/zyDtfXxr/iEjN
HFoo1UjZ9i2UolBw8zG0wxskkszqwoFFfj+85MDR8Uo7CKr9nifjrFJWAJWtGYzIQdRyzfgVTqu2
KqqgKXobMLGSTgllV/iVvMDh56/8nnMlOUW+93U+ZoEgnbSFmyyhznQmMZCYCRE0eHVSkJv1Dnny
xnkcqcGVjrVfKVpeibB82ow79XeMq6oqQNRh/kUtPAZ7NxdCbI1V7MPsL/aLEx8+LS+cJnDPmtZi
eGggCL5Nu16mvqqs/ocvIb0Mg+EWbcqqe1buTbZNQHd1O0jg9GkoIKglGiqjV9rDIWLI6o2pCyZZ
ScQ8ky/4OQxDHDz1PH3LVtXtvrJUr8mlXQGTfBINQ+nOPqT2tn87hVvKTlV+vpJi4sh+TIi+JTEE
N5DEB1QEJL47SoXT4L9uOD9JUt0BAbbbnoqm0ehJNsAYVdlen6Kt6q8gDClF1XYu+dllEGoNu+7C
sYh6CCEWtYm5u1di4f0gYTQ0lYCV4XsCDV2KykwP7hAmY88ToRNaxjEweHFOVSzjntE/dBqhO2Rn
EEORwBXms/dd0+r6KBbpIybiDs3OKTMo2wcD1vvKNNjQo9iinBas2PZii3dtIITkMvkhovqs56VW
eeV8uAegwJIkFH603KeqttM2eSowqA6g12KFGTnFT/D/BoZAfmyiKTy85wJbb5FFdzsYAMnB7RfK
04tMe9vgXbGMILlSLkhCm1UBZaUQg1NNyWEQI5+zrnqgn6mUl5TO/8j3Nh3fEnxSH4WBmLCxj/qW
P4Mo4AHyeFpFtws7f6AAjV7EkMJ2vQMsRo/TxDKun92faAHgbjsIx5Zlda4Gb+UeKXWJMbk5Pq4m
h5wgOVLA7UXUzKsyViI5CsjrYs6IVjKU1EMF7G4cbN59+omMQk70/0LvZ1x1NS5smVW3VDZMkh0w
VCxDYKMAW6XI0SJhcqUOZ/hXni6i3qh5gZ5A5MYvXeAWq77Oi9BzJKsC0Uug9VN/sOEkdPXditpr
eNA59wRdy5LWC1ZK3KHK5iC48DNpuSBCOoYHdaqFGerDYhoW1SP627ONtsaECtr1L1tgpAyrGWXb
sXV62NdAx8RAfl83r/8E6fv3CX2p/ShWyqS/JZcRmNzjpnQ/10RuvGbSt3xFhwAUjr1TWp8botMz
w+nOYHtd0IFlpVxt96larzHzNpC0DSHSy9m/VDtrxeL4/vYUw1eIFS/IuHvT1/zP5js+qOLNSQqh
KnaAWJkWizIoqT0C8lvaOunjLNFuoBQpc9SDjmGVW8DLcN9gD6N9h2hllNHickxUeKN0KRPvY4y8
3XpI9BZzwW5aCTyrAYJVua+AYjr71UJ60f2enfJGpP0NDCOoGn2zXNjNiiq26EQbJ5JhrJFNyQyN
Jbzl4AGyfFyx9etXlvAqiqthUP69rBGqY0CPIkIz2Lu6Qevz+yr8HJDFMfVOXi0q+QpkG/9HL0i3
/zF2tr2VfK/tBGkkrI9zbXcEQiQZA1WD2j7uJgllJ8ZCKXeIuCdjtOvq+cEF+XGsvZB1lf6JojB6
wRFoFD3quar15W8IiHHQNfOvXv2Nx+rFtzkRFB6seMlpDRG+lcRNm0HI48ooY4vTXwm68i2VP1cU
VsmuVC+jfcpatOvmCRoqNdI5db3QhsqCiZWt6qhQdcO78tQP7BhK0nUrFTAERa92kMqo2LNj6r4K
oWEKKsJvtnCWMjIOaEqnU6BL9PV9ZvZEdCb0rafMPG1WY4Di/YSktawiYMyuAn4htw0ciUEY2FKV
ixsxmGN46ReNFRsea9i25F3PoeCTWpVb1PEBWvOLpPVNEy3lDhyPgoKmH2u59vNFOxrbrvRTa72Q
Ia4cf+447dhoHO5Esnc6WAIRPbyQZzD+SxLKOQNVz2lU42f4BGGGD9IV+DENYefmtxrgnyMXXX+n
bJbpO3CbAP+acWyW5PHWAw5Vj04JYT6ouFGGLJ+psE2YOCiGWRLxhfAAWyvmllaQPoF2KkgQWJUb
N/Ei1/GC2fxCUBnz+QsuYiSYKw9LwV6etPHTj3JKlXbWTQdpgk57D3gf65Zwf3B1z/bPW6UqKiqj
YLmGzgO+JFddXUHGGEMhiLDmP9c5WK7RVRx4DVoM1SAcSjYwWvndQXnRVLLmy6jHAXAT4YEiNlk6
QUiTm9fqyazoVn6AERoVOppwXLp6eCAzTWkY8pDBKRqNG6wct7cYW0yzx4/hdVh3jg+uddtm5bUV
9bSzuHRyfaHnBQuPuCkTMJgKUHoIYE1IUtpi6zOqm3RS1ScNCsnj32TYBwJrBKLmU9+IF7dsZGr9
3AhLzMMV205hG1T2PmDgIJWp54+nuBPWNN22q/IgAEAT/XckeHQA7AvNpd0QENY6MnB9AVJGzL3A
xHzs/YFiJQa5gz8cU2/513WX3PG5RbgwNs6hvhy5FC1xpwsJta3CsJ6yKNL5o2x81Z6MYmhbvzuo
oroGRKqU98tNeVtKtdBYtXc+2kOnmxmM/R6aksYQI7tGNvbgJUXwnpQNEhJ8XbyXjz8EwSkW1ztX
bCs7CanFVpcqiK+GCafUI0ipQ9kLP7f6vIAdCtt3ErFmd7veQFFGaHPhubzt8uVyOO0dGl42a11G
Z4DITaEgm8hBNCR0e93Cdy4mJfDFamB+w+YHM80Fko3E3MPY/EqXxYp6oOx9pAWxGN28r2Iu5N2l
B7BrGFSCYM4/NcxItTCBNfURpzU8c6gjni0j5Hea2jPdgb2q1ZSKQKGvr/hnk1a7ukL+9gfr6i5K
7OO0JnIol5nkiJRGnaZyHPBSq1q7+XCGVfoeh7Cquvg01T21sCIVkJDugJj/WB9IolmrZnkVxjZt
yW1rWwKCB/NISQ3asjkdAQGFcv4pfVk8Lhgeotj5LL9dyGQphlcJlqIQ3JeJRLtM+QJ19WFpN1DQ
yP9DZA7+RlIr2v8R/yRl62sFuzea1R5AOjyUA1rITAYVxoRlsm3XappVJyWEzh7+ZAwkIZhXjTaE
mm6HJd186kM1M/NAcawuf0rlwILxaaIcIcDdFOLzdjMXnAI9h3ZfOQVyBDg4h2BTPGbor/E6nmEc
6gS4NZLVIeSvR/FLQYTOcUtg8LbJ0kL028b0M1I3PpzbIiec2W45ZqzT1cu3IgWGz2agQL6XjwqW
e7Tzmu2DWfpFUtPp/q6qfCM343VYw8oN1zFa6a6jqX3QUlwvR4TKJhI11dGTAOzGrvEzHQrDnjcI
XtOtkgAg2dLQmw0T5K5t46tsWuNtCaV4ed93MBbFw+UQTCEo9X/T7mG3EsKIIODEfNPhbw46W1kS
281WfQvv74A+dTxWvGf0Ji5R4iej4oV1qrYEGfsFaYwQALdYskZxlINyT7m3BpOewXVZaFd2FQL8
rYpskYSgWoMAwbMjjMx7lCblIvFVYYU0C4VsbUVD+FV5CAnz2Nv6XLaHE/YVBWnA8zcojN5nei+p
cJGH7R6GH+x4AHXv3++LoFwTn3AQLup5AjzJqQchzfFyyTazzPFY5m9m/61mNx8r1oYkuSJg6+gi
z5ykaXmgIJgB+vpdUfAPpVJ5038ivdes8wIKKXkI7sfmj9qtCk7ip0kafrJn/r3eoCPSV/4cN46v
1x9qo+UGYGMkJI9BdVFjoVbzT+jph3PKjY3SvDTsp4n9juJ+np5h5YVwiyBnNkx5Sf8Q8R+i4vnO
cp88SwqXrLKgIgei0pWc3+dDVi4ZRJl3oPDLaxXku3BQSHMs3KtKyUaDlJLfTpTkTSzqfWr9LX26
QfkkbAuAfrwknv4GX8KkGMLCjmk77nl82ovLrb8Dj+3qgtXgfEySbWQSIZSPrA9yQY6icLOd45L2
k6Aj5qdhFkcA9FvTAKVs+9riAjQ1SwNg/1t+297jraZRBCJs+nYrE7dlxYDDfgGVqNrc+SbK5+2i
cU9cagI8PxAxozwvqShQVTLdC6Cw+p7iEZlND68fd/p767uDRksqUagF7Eb1Gi4H4yfsreTO3/qC
DbUo1T4upmxBoyp606OETNnf3Mqb7uPUx907X4GhVCftBhGUSKWsuk2U7G0Y7b3q3CTijaHSumBa
R6qDxuuebAWftvIBII2Qxmb1/geLFD+B8fJboKL6H0ppRIR59EGvnyajiHzphUMBbAi3XYRiq3Rx
ah/oNiLWVGRGJIfv+l4A/O7CBM5rJRPeyr0+NZ5JSO5mgnRJP79BAPNxQnEVRpgxiQ2Ul34gkW9g
qs1CjDONLXIJZV7krkVVKRCMSzp75PnmW2M9XZNSc6Rtl1DiMQMRXjr2tcRfEDtZZwVQ392oiQz2
olvyNRi6PShq0kuybsUYFGgc4GneXyUM5vE1mMF5tU/iaR73fVVSzSgcjThoSqLXjNkXE4pML0xw
VsgDmIFcUo+eENC81Ee3n9LCtdHGY0q6149s7p8SluUO623r5FxGS8V/+wwfL6QSxWYEJNV4ghIG
81yteJEeMyGf6pNw0/iEkgQ+vPsNpUb1Fvvwn0WQnUiE63kVFDSosbDArigE2fFbvpenCDibSWVf
71NIr4d7YEy3Bh2DkqDa2GSpFw231mFv+7TqRuKBJxsvozjzlJRwdofF/ob63YVxXxfn+wZhuGi5
kJf9ron1EelL4rm+r4xwSvu7sXBBQdsKldF13zLK4mRxseqiI031Nu0u4GBz3evs8kBawyfTPLUP
3Mgk1p63P2Ie6LzyZXYEoEsRnQ6ZQ1v7gi/rBGPzQxq5NnfQ/tolYalP+7hotUSPEBkkwsQ8M4h+
azBb+J97js7iD/+chBsTsjU1+Xm3f4trYda6WX/qJnFYGoOLXYDkNuCtUNn3ers4SpciTwLfPohN
AAtE8oA1JC43DqBXJY4J85Mw0drXsYhWzWU3YSWYggZElGmHf8CmbMmxt9DqO7AS+PpZtvAngfPr
zAZRqRachliRIKkRD1j/7B2lzmZOSicYqwFiUmaoo51hCv02tTOcS+hRWtUDx7E/gB+lF5ojI9sE
iic7/hPORgbBt4OSTLUIX8eK7TBLrtuUFyhWzSJGzX7wh6nyk1gm8pS8kKZpfrFrMWITmvYnyzDB
KkXb4x/UJnhSVDSiwBPeePbC9iaRHM5AY7k0K2ahEKLh9bitcoEEmBRO7y2SQ5sjk0edxA3V5GnR
+3sEMQzwyjc4/MngWLZVfDlQVV4h27ExZU2XQlUb5p3Pk5ufUy2Qk6z4Q+rLeVIfK23NVDUkt4VG
o7JEafZrNJRpKTT8LGCuL+5eVyctYqLKXre9RWsZucwfy4/l0Ktjvln9SR9hBWRJw4p2YY1NkblE
dteHYjwTUlQ4R45k1kO25RjxUvspDo9ilXlHOZiKwyOTGoCg2n84KkfyvUCY4oRc5Rxk24wF0YJ/
4UcPY7520ujmwyQZaEw7zh7ZQaJLxGrAgDOMjLPN9R4DWAzxGBN+Npf2XF5O+bI1GMUEn7fUbZeQ
6JG3lLX+tmFt2+z8vO2ENNBNa4WZRvKq+LjBmWcSMrpPiqo2xm+suOLMt9vvyPb57JseVPv2AyK/
LifWLQs8rx06KoXkNGX93Jq9/RbZ0gPKYigvcvlGorrQnNLnhRFEn3lRUThDg/67M6koTWIBwBy9
QFweHw9PnPaaH5XgTf/GQ9xz9NcqpF0zVtNjAygkpG2DHXEEK0eL8G8phqYYe6KByUkRRi3uN1KN
Iay9LQ1I6o93He3Nv/8BMYhz8291j31Afms/o0DsN8DcH5wzHIdXnzjNsmG2mEkhIcIV3YLqjeA9
CGVw53KFN3PyC49VU6NOz2ZlI17ywoitGSrv05HmQDTSvK8FEmMVqTmk3QymgwbO3js4/LVfGNJo
FwEr/hWxX90sJCz8ZAyQWb2LiUSCItGhTEl+p6NYKH71Bqt1mfRpwrr0db4ZIOZ//0lGhKCqVedY
ak5JxV4PrG0yJn5f3OAPCBPBUlh2bMzwoVL2LyS9ICtAnwFmSvSNXZL9dmJbCpnVyZKCcNxoHPVd
UliOxb9vrDH4bbJfPaI+ixiFcNBcaKl1mA6XPYEPcsoGoysDnonYqb3ckAURBGVUOM3NaSgC4klr
mgXdr9waqgTEAK6fXQB9QSc242OLGkpacua7XKBpo6w9x4iBo/vodL+EbepA4UBjkYxuUDWu0st7
s+e1xXn/fxsrml7DZToh2piE1fwmFMQ+YtoeRDcMhOwB3sUxFxGFb+7m5Krz0gnxHCPyx/shmUEZ
BRvnsGl0KWed+0nCVqzmEavCzuZ2djdZ2e6LKm84uE1dKDYW0Nlw7I31m4PyMsgJ7KPvFxcSACWS
P4lUif/QCPBeftxQ6ip+Q2omq1/HMGZdpsdhdpxOgn+j3F1IGj8ik+6dNCS/MpiOSML1dHEZkMDC
hdNc2nIP7CkUW/OIbxnmrFwIZE/3XEqmPVWIIuVLST79PaD+/EyUsPBlZRODzqJiUK06r3OoM8cW
WV+t6HYLPApyMilUpx2C1g0fw7Hii4qJncvkGM5md+KQFFl4E63OjySaRUe+ZWW7d+AwIfBd1Bq+
MXdWoKqvFwSTrxIYyD6AH9/uqMyOQiylflXuM30DXO0p6Ms4Q27+oCM/VJ4eAYwTUbOxS9B6oJ48
+46Oay/ubjcwTwqqVg8qIOQbhYYhPO8V+RgreFaiNEXq+S0nV4TJRy49RCHfuhaITBZMj+d7eZjT
vBIvjptiYHfnZzAh9AH3p+2EQbq0rVy1+qcLu9/fd7Cc3bsGVUOlb1cvwWAvLi/1df2AsyyIJjc/
U3ISLzUM43LOXF+UgHw/t4LUrLZ8zRu2ta7vGsoZFRTNqh5+l0sn4ZPFMq8Vl1bwTH/oh0lntWb3
uHtRoDMLLuSFYbwxkmCY+fJGKcjGq5IkNOprBWZ+QobholwXjMz3A5+Emp+hQaZlN0XCB169q6yg
k04gXj4qTLfETLdTeZ9c5rSawC/4Edbkr3yzWzxuMLxl3m2kak17Cp69MuZHBIfz9qsMcH0j4N22
57AuXo2ySqCOk4Ipb76wyaWehNRlBtwn7Zh+lWEZtoS1aW06IGptmosMcw134dPiWFIuF9E49/a3
HKYF7oyyTT95dMrHJKwlbnadHS5kFMvmXirirZJkzYmKzp2ufyWVf2qvl0NGupxCsLAyfBdFJNT7
G6Dr2beV9EM1syKcO6Rdp3SNZCvSqQ1Gc6bL5z1hdgHiAqV4w0t4LtLX3VRSYGYvL8kZRdHBtJCJ
jAjJOuVgSvFCcxtzzG/gSQTIRpDfEICwUwvahTg40YJRQ5gTZ9yoYT8wVP03n8jteCsXY7EyVuho
Q2gKVbGCQj4HKAwV5iXJs7bglhVQVzgnzAfa6rURt1+ZlGfk1Qk69WwCHnd3HHPEqqAnUnSezYDa
yLE1iTz0GI9PpZN7nLnFp9sOkX/Eiq4TWLT0KAjaMBxzAnto6kB8D7GzCULQvGPSFg5HHDNIC7Z2
UtNf8R0LVAy6xLtgcW+DgH3Q+s1DDolhOP+d/h6zFvcQstlXoP9NZoX4k8wUCNxc7iWqxTr6/dnw
q9/T9QK8s6zw0WW6aPZU3W3ka8jnUqfoezVS6N4F3+QUhhKZge7JNohJE0MYH4cudi+iNAfC/0Y7
3KeG6DmaybAT/kyC60PtoKfexzGWKedfOdKn5WstrHFYIfNg1CnWUXVR7CSdUdr6YgrPgGNJOzMB
ebf3dM+3GajXwK0mUr1JOVsCMTug7zjTAcp7KnwO6fhJ2F5iGMbX7QwFKUt+l/cfOVwDnWCLdk3S
vU7EgviM6QAGhdqGgcinvLnJRHTqFp0/Koumfgi1GB+ZhRyN5YRc8qJcICoDv+AUKpwD7cxLfBBK
siLBn4sXm9q+q5+8crWs2MdpOY9DX+wlU7+2SHfFCEEVoY4dDz7E2ZHEw7hpcrwwfsytYBEqrdod
RvnVwwDd6yaIUr0jjZ30PF6P3G8+dwK5nZe3Ze/NeXdDwwfCFe20nsu0sM4DSMCgsx4dXJJ2QgMx
DtPGslG1Z81N8XzWrNZPHAIK10AxnvsdfZHPag/bnEj5m214dy+098Q8icRwV7uoYQCjF8Dxf8rT
T2qev/2nye43Tge5WqvGckT74DDHi1Ohin6o5yKGncbRYu/pWdKtZR6QZVy9RjhpXJVI6z2quoT3
FdiV6a+esyB1hhS0BPaDNLRmjSWT9SPTsoBFQeFHwwd/RA86WgpK6mRAQVLMWLUTFJYdUSoTjkjH
LytVGj0UuK5tuXJoKa4InCxpHNDfmc8FHRIjPRuErp/X1SZUrXyPoBi7ctsDIjsCK+zQQ9Y6Jl0D
AenUAofH09dNPgr9DUEzNfi3HrLwzykKAJnd6R8nnaGf2Y0TZnx1fnn/9rcI3Q/Cp7oN35tGku0l
N1qxtRE9I4G3hjgYPU+wvDxvgHmxUDAkR53xy0+heuBZbepJi6UVReSxnThowW9Fc/F29NiQSYCl
VrUAK8e75lZPKty8jdtppMF1UUfejc3f6mTXM9mskifclUg7jiuzrTumPVgWBGrFKRqnNv9415B8
PIk7JtOjhefu0f0Xnsb5yJo3BUJab6ExZGKm9QHpTP0cO9RIY9zGiMVkBTJtXVJkm6wZdTfZur5y
EEKyT7sKxhJRonteMUWpGx8j080+4wa4VKlzlRf3aFM+88WyPfVPXhGWfF1AhWQYtDOM/wd7JqD6
ferod/g6UpFVwcxn+Vk0MEkISX8Av8ohrSitSHgYZZeQybg9SIi0q9cN/st+vAGez4plecYcdwC3
FQI33wGdNxsbGkPKpHIz7/zUVNyVcWPg9P8o9aCHTBvf6uFAxZkMvE/KgawtSPBJ9+kxR5Zj34G0
dpFx4iJABrHbnbvbTijSPGCE5/UKMuEWBWD78jxlq0rTJkJ1h2XP7zVAZL1UO5OME8rpzWiOpQrZ
uTkD2Z4eeve1R5CVYHXV81YNDj+3K2txbRE4LVf4Ohi1kcDrW3G8Je4ypGPMnCibgFy3Bdz1KRYK
KiwPeDG9tDFWCFAZq7Cygj2LXIfNWZLTTAXgzVfprQH0VeEtUx1fd8xMnxXVwL3e20e4O4H6d4TU
0vmWM1J945DosLwvk+HHwSSFZLdXYeKd3A7FIjXnkEfe0OKOfksKMQVm8fRFLCEKxRFC5nlTfgbx
eKMt+BkNjzHvGJTAWfyE8/8HIR+cc2Yok1Cs0W/sxgTc0R/lQfB3eL+DupTvBzHI4uZ1vqNHT6V3
GPjLskagEEz2sZ78w6al4qa3mLVJ3vnRxIzHGpGED0rpNknf2rCK7/w++lEyexqgsNpW3pX3N3m9
pWFdeGvpskN0+f2seWC4cuU1GyK5g78d6dcgF3FOe0Gjk6RRCaaNQMaAniAQrPAQntw77a8BqUWH
E0kK+blysNbw6d8smDHIOkGO/LOyaFzA/Ul84echpVHito92jkFOvCAVaQOYN43Jn0bH8KAET8t9
Q/HzGh6pWuOZbnlvisq4/eGSBdeiyRsc4Fz1L7LD2/a5aHi1FSga2ZMk0bzwwXQwi0YmcC7CPKFc
Ot5+bUpyIwzPWmWY8nimMtHnKTYWmPMDUXH7hAX7XKdkLQKujEwT2w9kChuby/fpoMLol3zL6Hff
drIFRZ0BISKeEH138CCuhY/DhfoDCTVIS8mR9LV9k2y7gz+2/WUtO3nFtR/B7k3X3YsSa+o4dl+3
u7BAvP4oVcloZkyqSYr1ImmKSbs9EMiO0ycGtJEl2zUIxcclqqu8J2zbTpHLMK7LKWodND68PV4P
krbGJiHUnKGQ0wS4i9ywXM3/5JuZ/OuLtBY4hffoXEpnvZ4+5HYZatRprvS9Vu0DdXwhyHRbWkKl
cDD+zWh92e1zxmF7KV4leSUAMAxrzrBinZVTVcPzL8q0lfLeRQqUSy3iH6Whr5gZSJyzCzJ2hxgW
4jqwbG6Nc4Ebp0UGrw0a8lrLNUtyqwLicnJ0psWMJoby54r3ObuI0v39GZ95AOQ+KpzkW6b410Dn
WEjXx71WXaOgA/wJqrf6NW3TjYZHBjERojzx1Ou934scX/+NrIXoxHjdXE/lKleRTzU7GAId2Xrv
XMj67VithNLA8IfL+otFqzRZ7CniA9mXfwnwicdNAsBu+BzLI2tfDVHsq+DVIJ7MzAwhd2sEBsrb
LsLvz3COlhKvmxFj+CnjvbXkeuwzpDJc88gR5UAkIknDRu+qGf6dOLaRpgS+Vuj1Ax6rFlw7/8Nc
gL13e7cEruX484loEe+/18oLeR+/5btVooenDjGBaSLhb3skqwPD+g6ecDdYbUCPLtTQKXPHlWP0
q8LoOpLWzaE2ktAqFWje06y5nnSnl5dvxHDEqhNxEMfIhmu2ZsWZDe0sl0+uBMOVbVcmso8LqHTr
qICWYb/h3jlBzTp4tEwsiYNwErm66G3we78Jdk6pEUNE7VRWWEKSC/uzA2z/4xc2/fKKy85on1qi
39xcUWdkJVw9MvWBtkd9sIZ7W83vJdAIUOQ1DE4m+xJfN5vWNtUEGizeZZXji/0m6jC4BgoTilgI
uC0tSGazF6d+us/YWNHMNAk83aUsen56mJErEcF1yomBWKUwJqiA0Tec97p51i2sF5dZQybFlkLc
Qpdrzs9CnkumqS26wXv75zKXHDViPVXGCVIVx5IuqMyfmhvxC3vq403RE9K1XObQPMjznGMVtemG
PLal2wUJ8e5ciAf4w+XOLDenBpvWsk859TchKg+kRPiUzM7vm3uYcoMYDazPAhu2w/cIi4GswIcX
Sprdvxfa21hHC4JuyFpO1VWPwGN9rmVREf+niwkvJsUOzVacubtv6OkVS2MtyAW5orvFP5NYpMje
T5dLUVhe2grlU5eHLY2R0m1iu7vnRe85+yXPPktNcdW4QyhM5u/2HGkK2EMRrUtO4j7GVFihELzJ
Bc5h2Lq/A966yUioPXIst9/VmLPqu6d3ZxnU7Wu0w2+6qEIO1jr3Qt6QfE2E4Rmo/RbuUKyMAK/j
CbVyzPaggIlEeRf5Cc8DrYewyvrkpN6sxor6b7RgOk/D1qMnzm53e4bluG3XWflnt2bbUS4soRiF
tTUrJOfj02pYA2Jops8rZeIFQ5Y8QJwUUaBDZrJlf4mx2nb+5tXZmGCM9U3ffTUwAO/8AE1A1QYd
yN2rnSRgka+ZWEr+dOQGZcHVaeoxUEtR06+ryJfyY2yhOxrJDlc0i2DN2sPs+p3VUJj3gkyCBdXi
lEEjkBdWzXA827nomOTlPNmFSGn7kk9RyPUtIlsafPUiNWBIz9G2UNMSlTR8oO60H/JN3AAPlrHl
nL3UNF3VvRiiXAID4DbHa/E9XqoRCP7ugFXdGqj3gSQrqrsQot+hYF/ZQbf/WjGpdvo+CnrtZStR
MmVVUX67l74P/0+Zpg3WhtDz7+QLWRtXzjMB4M32oisjXlbcyZaMoNABQyB1IKyPrxREdmkSiyUF
3PLLvwfeGI5aIKtbaRjCfmBdBkDjN527BKtzWNAP/XxwCaLUep7QYgBqq8s8TNtt/mgbc00qIs95
2F0xW5bzb1EOz0pbzulyOynNOr1v4tAiI8Jz74b1NF24+8nItIGWO6+p2CSFWRbWv1FbwJqwz8UY
kKaX0rQR1RQoT2uQGZOxRmqI2miJ+F6+Q2NWdL2+QAFjUIqxT1Sa89jRTdWdV47LzNYk80rbw3H8
xzdGHKhNw+6piBPNfEA1AUlbX1BietDOT8tUhuZrQ+PjFH8+QVQFVhIaMWygjvNLHPz5ktWuUo+y
swQSpRta/p9b/rD0UTiURgIuIFfIZsDBxVs8abF8sn5m9UF7BhNNb2ORUF7TVEuChYBS3tbQUWqo
GLIcMYPYOUVCdhmw1cE2KLUN/qAkVoDIXdl63+ZyV0sKaHjuRUo9r3OQMAAQQ9Tltsyi5J3W8jVR
OzmnLb/3CWbELSJ99NPWuD4N6JT1FGLwVne8qHFpEPjLavM9LRaUYGsWY4wSCWByj1WgXMQi2pVw
tqRRQIY3JgBjO3IpCNm4nTR7CM7/3StSORFDCV6Q5T66r+szc+f7Fkcr0iSgyFUQynm+1ex+36fd
adyoUpfIgxthDMhAbqK8DtKRNfRHoz+tKNefe0i9tjcw1sbYbdB+QzS0xpg64gYlzieqYw9KQPRe
aHcsh++krBvlFqADHTmE9yRYYcgBFlT43wVS4YR9PgEHG2VazvNr/rAvCx61iVcjEY/6OWsGDba4
V15TM42MIQtZFJov9aoBHpfz2+MRDeGO6Qn3zf52vOcCCFVlN0+8o3WtqhAJtoBZeusERB1it31f
70KE2vrKrDiRglK+aaE5h8+BoGO4ekFjrVtkor9AAZJHDYN2F4pCC79qheiDb2QCMabEr1YxuuJL
sNxiUG8daL6WeU3zyXj+yWlqpx1CJKQrXaVMEvhrppnZL1nbiP1pfjk8iQO6o9WrI1HsqMYUuLUD
6Sc9Qt5v82Ns0K9yB8mzBOJFq6O/tfLoI3DND0lURZYIPGTUVLTJ05leryIeqg1k2F0u0dXhQUOT
/bigg7a02ME0+QiEv0CiITMo1XCajEP0e2P2UI22S+j68fhYCGP6mBOeTGcZj2HMf2+iPQEznL6s
UwW/H/93gopwKkcOHL6QLXyUCkrPISDcDy+o+ZZG3xY/W/XTBd5uBHvkdnatvXAjnfOdsLoIBGXQ
pd3L/0DHqwwYIcZHVMZeZRBb9EWNHezhVeUdk+rsAhhr5eWe+9wWVTDxoY/ZgCkAZBJ8p24v3k8H
MPKJzWV4wisIlUOs6n6SFEfiZPmCrFM3SMljpypoydC0oMyB8+Js/Sy8hOjw/gzNXfoN2pQwOxbl
CRR905isK7mxrmoPDU6FLDPxw/NXQkgTMblmgkWyiffiG4CvXJ25p9oKaC3X4gDqV2GBou7n+DIX
hCkhkGsdT57oVnbZ4bZmtk4RYnGriKQjEVYfVmEwEprcZOws8+Udtx3xdDtjg97ImZqw7vdHZZsF
5j09cIYBHrP9HncmwZvbZ1f5BXLPor9Kgw4jlwa8Ha5a3THu+2y6FHCuweOwijmZeMHhxHiZyzVl
2ERhi4dGWpKRTAPXsB2fdLQBrSM91UePHmFFustF8CR73O3cvksd/yi698lZT8vwVnaLrYcN08V+
kvUZIamJzBEPDhrW1k/U0NePrvTuhv39hsBggdGZY792TaonT9S7IuI5gPK35o9vPfathsW7aPB5
P7uNLyiEr14waeS4H+HFx8Izo7o/bOeJZ/3KgfUvKpDHxZECdLlkoqdxwHsa4NiG4UDtWvOFAPL7
Voe7lBMt2xIC4PnMqkEjTdJNLipsHgOuU7L5bjSS43EJ54lMJw+sE9ANOUX7ScFmavT9I3B6JR60
CHUF6GOcE4y6xxskL54ZvAU9jrWL9Uz4hSrbv6INf1umdnZ9q+UruyH3MUeBbQmC9axv0QdJzGLL
aNfvqr+OeQPc7I3iThp05gSHqOMwDsJh5+IZBCPCCTqmtvmmG58B/wgujnb3XqCugMWZMgjBASHA
z3vzaLdEZcnc3ueI7CwWw4zizPjxS5nK4Dvb6FHHZ3giDJKl+0UU6Hctlt0gZ7gaUCISLj98ZnlJ
1DUkhrvUU4NjW+HbFz2McAYFwUYBOr6dA8qkcB7FTVCNmyUt45vb7QMPJcXlQG5QZRs+KtsJ9kiZ
DaZxU+XYni2Sd/eJcvMh9PjmVFvDiI/uvPcaYLLiEmDflzlUwOIoNpDFwn4nr1ENTRXCzz0S9o9o
dq8LnnBBHLimoBo4SVsbz/NPuImAei2rPDmuQaXd8xUtSNp/Ma4x1Ypaa7AvQcUa9USOsUCoz2qL
ryq6HjwjWX4YTxLyV6Lku3t7T2mz6d412pIdQSF0odOOMTaut7yGjAqTWA+YD4OlSVd4G0/zqUax
htQ7kXeCbEPVIE0xjS/QKFimjqN1aF0pqK8He0iOHYbDag3PnvJM++EgisoEAcRgLMkVM6/9MsZw
sRsZ+szaTq/C4Z8T6LWb2UUj+/hUZlUMEeJn4MoWtOq1xG/CU0h6BceN6486VnTtCc4VpGZFTEnu
K+MR/Gun76/wHsIJjkob8SU1F/Hk1SiTqaqR5oZI81rpsElSUyoe2gBBG2X5nXNIYkAg11/hvDW4
2CqYR611RhIc7fiuaGjQOIB24ywaR24QD/QpZ7y9QPGjgWsEQtjOv+S4xVnm+7K1Ih0oJqBaTK5s
9TSIbomBFnBkQfxmg/pqUNb/GkdVTa9hC7BSw5qBFzsUSzF6cZXNc5Xoyn8HaWYZIZ88ZnGchk4x
TObJnDUlioaS4UuKy3XxmFpgdXn5zY+f4wCkXoMSnvJ4WJB+MXZEGadcq01Cnn6zOuxPuSdQ/u6l
Vo02bWK2XH3KVTIbAuKAaqcvvFl26R1fpsgKPR3ypl0BaxwlBbFTuEwvybD9KvgI3/MpxkTQpJDh
BN5bUzOHQjs3ADOAuxhojfNwMBEottA5A/MLHSOJ3iQ3B1q2F/x8KeLZtdm/MoQnvuyHNg7bGrJa
8HskfFI2GDEEEu/Dy0VV2oFM9rCHrHFD37KtP3ekJS8TZ75hcCYoUjlEJoCBrkLx05v1hyIr9zgF
Ae8de5afDiKyAkbzlW/PBaXiGxCsEP/IC2HX0O/kEQnO0bdEqnf9IJjUAb6zP/+ZAAoO1BJf+sIF
DGL8IEqJCG7ROjfLnXYgdyZgSnd+TEGzYMi7/eB5eRP/KRld5Rr6IrXfvI+gueiJVUDj6fTPHV0e
4rGY26WzGyxxlIimtJUyKAEYb1lwO27IEYi/26SZlLJL4dUU4+1Wt0PPTLQbn/aWuWlQXXaK3kCz
+1h+epxAGUgIAwVHfAKR3pNvXKoMR52PZmbtXlNf/Ol+omzlSlKx0Ecso0HcBh0/8KV7jqCH4ZQM
3Z1GtL2pztnEmbAvHddjH56Mk4X3+w9/OYXm2rexcVl4tfwxpPXmfqLX0kcm7aj7AvLSKSkiYZVM
4gXiWUnQXxdyuitQFLsvezBaHk8w5vPoavS6rS6nhjj2ugKXr4NBGOagMnjrDRwHpuyGaGNf0T0a
C8aP6d+pmkBgRyaseDlsuf5YPjMwwHhMCH6LQvwoxeH/LTYYFJEQAjZFxtyC++/PcN+EN9gFwCZl
J3erUJ8iF+rytqQe6wLymfhu1ZAgOXVevpgqLmwl/DGknpAS+gPCDiCHQpt4JyCQ4Y7jHv3Bqh07
a6t5iQGvhhU2kzRZsjJhsRfNPIJ2m9BDklzdK2Iq4GbDrx/OUmZiob/gkeqLqt1Nrr9zRbsMZjiQ
oZUM54IfvV5s7U1yTQ0YxyOWrFE3XMadx8dCMD97fNvuFRputOnVQmL6uDReeslQmTCs4F9b4AcR
Aj3e/884kfHDPJIH1SLM172GFJJvQ0DaFKqbP4jIxMbJTlh8fwy+MN16XTbnLmvrxiVSdncb1Fu3
SNFDVxTFlkUR1f/rviX1A2PQzhtS57S8aqdnuYTdyWh5gLvsJT0w9K9Ghw8RLQqwwqdHp29KhU9a
cTqY7aN86kW/g6FZxHKXEitwwMa6x7qpZGuQULNvNIQmLVuzVNsanbgR+M9+dPUrSnnn0JNuAiX+
GSr1z4GExzbsTqpVssagdBeY6d9QkmTaP57VCJJy9c8TFgGux/st1vVS08+AKTuL7gZOYskrJh+d
NEkyZSzqdAUldMUuJMo0KxADvQH5PTwaGS8gYDcvWl0jJfq+ByGSLAoQrXOlKtZxbxbfBoSU9zQw
1IzbuZsVBFINkeAB+ugZOsTGY0kzCAZwC7qjGi/VtVF40cZ+gHde03urkyyjXmShiyiSc+vHJncJ
8zKLuuvzwuNBf5mUy5/KgWdOMh0eHu8wQDIXjbwAsnHMefKGw2ZRS1uubPl8CLONhXIaI90m87oO
NbO+b2bqGaMeXD9+oFwofCZXL2nbKByXE8xKXkAJKeIjOUqmPUjuU+/dO0tSxl79cDUFmodVdsyi
BO8FhkjNNffVa2WhmbZ1R7WiYzSce4dx/AJdA62DNA29zU6basR+n1NxZ/Xeg/u+1sRfsA4+CTzZ
wOQEBcZxQM9/eUgi1Buigjf17+QIPgHEqaV50MIpUU4tSeX9BP9/sVUo9Pqb6xfWK6ApGOUbwhBK
xoum9Zp5Rct4VhpMhJ1/Z/Ede2KjeCRwTY443bEtsqdeygMBEcjMI+fGh/Bj/9vLQfrFJt1k2MIG
LweB5M377NbGeqzFUsLTZ1okUpcUN6ywB1tLHGv82otFoA4YSoambx7EoY/43YUwrIbuelpLoevj
cQJck38Foculh0/pL8nekxd47xSJjLJaojyGpWo0C28tb8KK4EcL1RmsAmxogeLXtrPKF8DlSoiy
zxXhXKGbeFVOyMkzxOGSBR5UhaKPpz/rma60RyuCykoTfjGTWysOKjnf4b743yJXjApS7RXEV7Lm
QFU4BF37LphFFT6PXbN0Ra/PXIwCgBR+B/SkAZAmGF83XeXLS04naXEGswUyShSh593BRDxwYOSL
B90cdD1ln3XSPyMkTiukqaR5uvFY38mTk0zC6K9YKtZrLTyBhaYDIbs9e2Xn+TW/zmTAXVNm09vz
ub7cjkBDebw1WSUDVtXAMq7sbplWdtPBE5RrVflHX/0kqyo+XLVrI1O+vxioVyzQIxqn8nObw8wD
jjlIKKjoKaivZ6tGB4P6DCqr1f5dPFKesaG1ev42dJGJNtRr/kVoaFVwlNyR1pZ9z73vfZTmg32u
vePD8rU6XRhlvqsriC7AssKHD2boNGB10N789dPTURjr4oFedrlHoL4jm+yqdaoP1nn1jyJYm3BO
PC7NcWgoe7vUWTvJANU+w09C3RzV+LtqWl3jh7GBEwRfYXoP9AkziuSwClQlSzTdOGsiQhqyklMU
B3fkwtZlvOnVhN4eOguVTXxh4E+YEPYALemlPyUEQB8zBS9bfxiCLfcSfy5aoOmgp+k7pAWuqOLa
3dIGoszv4IbH1YSdW54duGqgj9sltBpcbFmE36L1vcmtq6c2d2KsjiUiYuJ5wL/mfMOCWr/yYUTm
wP5QGF9H79f7csYEeGz8cvR1HdXICgBpUa6lFMR+p7kfjSnBBTreL2QW1f4B5u+tJ+dn4SNgT74O
Vm+u4nf4O+K9BA/QRRXPbXN4/y93Xl1rgGURFzh7XUhGnrOrBJiNyEdk8EU9boOdEK4hNJTDjXGR
ux3SROaoPMGUTdoreCjRuVb6EUG2hxcfgALSvSncRkpGuUrzQuWh8lEd19HsGWPfio1ROyTgM4X1
J6csbi17dmOLFICIkbvwfWTuVwlw1+c//ciMS3cgX/7HcrfXYOpavDszGo7avQb69c92IoAZvdt3
spxRIQXSS7vSpxeopO8qeHmwYalABcUoFcOelSD70HP6N2WrxtZT7/CsMuZraPV6HM5x1h9RR1V+
XAggXvCDGTeiw58dBZ9pqGSySPjZrtMSE/1U2g3kl/vhyh9a1XthOSRa/l2y3gmfPN95cbm0XxOD
LTi78Q2igDcItme5bEKhRadeCEsxcPioHlqi6iH/lliPrgNvqwNxXJR+tFxh+5YUHH3oio1+ySgZ
SmB3DLuU19eUYnNHfKka77/Wk7BDHQhWRg5Sd4oE6hOs0Zltr9wEUzv1TiWgmWo7YCGvZdNWtXpr
ezlj40IyY7PBCntI1ueLSa8YGgkL3kjIe03+w8f0L7bkkBo79RrcUeU6Gnhz5YtQetzRnBt6dkdB
aDdYayl5BgG2HSABRziY/IGHiMpPYM+dD/zLHnt41Q4MkvIYCQhNThik2ZQYmIBcM8leQ0EYD25J
TVpNMW5twqUlAPxpwflO3S2vUU9ha34gu2NmhZSVuPXehuatvUn/OP27GvwiXFRSSQHpmbjh4X3Y
ImtjOxZpWLxJwVu3eQn2Um28G5GXAlTG8nrkYEMGN71RPjfD2jIIcdVbykMYiaumHR4YJpVNHJxb
a5Nr0wMBhoiR8Rvn1F0LJYoiNAhGdp/aux1tNxaswEgIWudHHC6d0uHbTokXzVbjlXOusUSwklfE
BNwWLLEeNu5eh0wMmjPTpkFevlMGovDI+2VvxCMi1SIqO6vwGgkZoxQXUuMpvBYV4saSxrOtB9Y0
asnSGmsn7PskqHyr6VjfJJssv07HWGJ/kgTYlLrPtHEKwS635Uz3O7MJpXFz4ThalcB3bBS4dAy8
n6UyjLUNoD8IZ3tMCnjpOFrJ5k6FLn8t3/EhGeovgtsuKavOeKrKmPIxZHWB0hlr1tsfMG27SaV2
XbWHHCH/l5GSRD73Vf5kCDQyIVVB29Eh13sBoK6Laexj5jR0PHIWpsnaXDLzq38S8xU2ZxuFJAQ/
qKO3YjkqAQ17ASSxvK6Uz17qJnPLhWCovOnhzSVGroXX8KCyHWp7AbMo03BMMQGsdcEbPDMBBtip
Q4bmqG9yiCmTT/Y2WBqwwcWjuMMrvowrBALkl/nQO2Rx0ZWPIfAsZEx9Ls5y6CXrqwt0NkYRu8Cf
USSr79sg9AU4uNwvmoNucKpiLlCFK8UGi43vRywT5lOFkQQWVUZDogvKgqJAckXUe0GwYVwnHcZB
N53K7ajX4EEfbUyGL/p6cpMJTX+RSpE93cLloWsRsdzjcikh6xSmLlkivGLueiIt3zIRS7UDxKN1
LVuRI3PpFh5OQ9mr2OoFWoH0a9gmoRV5i/YR5gnUv27EUsaLyPX6YTL2snP9+k6MERbIlf24y/7f
yjo0cwv0g1e+1KKiMRmOf2eBwlx7TkmEdCxLOEeokcEo5rpmdWPrlkOOach+qxwh+WhWtqg5b2r3
Tf1loq53G+fAibvzQ3lTXpnSPJlubMxpP7w5BLbG+7WhMlEPc0RWVuuJFNzOU8zXhM1+H8GGKjsm
kYo3mu41FS0O15m0vEuMe42Jy97RscXZmqnTLSWzKP9wVtOGkwXyG2dn/bMPozV0RYlohCzua+tD
CgoztiQYxsFpXng/tuuGC6Mc+5ATsB8gYpnCLywRF0r5y8eTCJ3Ti1d3KzgpYyWHWVYJWa5at+0i
A+Ss+9vqHZlxFVGuipu5E2FTabz2wGCGq2uLp8LWRqXE67t1WEr+meCN44Mw3b1Ce/Y0tBLcSzHm
l3Nvh9YimfNQeUfzzcO16LCCiTs0AtFHiBs5aJ4R6HnMEdGY0oTFoLG7F2cLgIWw2Kh5q96TlI7t
AUbIsBogD5AZp4derU3Vwhsv1o8mDGkQf3KUaiH1Ckb05N1zdo2CWgn86S53x2eZqTUHUeZTC6dk
AhcSIZfAQP+IO+Q4nl+7V/oq+yeOmPyPMB4MZpzshZYtA+F2DaYFbJbIHoaACh6Wi6GuWSyIocC5
4MxWnrREt5FZ+5Ict1SJlO1r8zaLi4j0Ll0SDjKm4bJdl2aJSM7s7aNFBOeFacMMolSLf93Wncea
UJD4fvRa9F6bUaYv8TzW7/EFSriDbLEdbOm9QeQopKGxw4RhFKeUtPQMpJMnJQxgOR4vTDKvI5np
sRu/m9fmLb7EQwYtC6K1Zv6QZzD9LFlTQvKSNqz6o2mm33kUMo6F+Nt+iQpXrUnA1lVuQUPvD7mP
r/2L0ohY5rY9TziFq6aINryPThQhd+3+NkdUe0kZ9ncPZKNJb/BmCSyaN6b3Qwpd75yU80wAswQK
noRxytzftGkQz1S8/tiwqMHtjAWe8PWpXO1J5PRW6jG6Xq5Br1o4EN9D3VpGqrERZNFZ1uzFDVzY
web7dUzjCen2ALXKrch4Z/Uhyzy2E6rbyj2Fel4b3RioO8IVUrzZFXMEFE5DEwFgdA2qe4NbDz2J
QHwMcrRwCouQexH2NdGkvUoPJgHvcIXopnd1PSfxH+S/WGwEBZ0u6a5ypQd3G9elvlp3g1oFLcQP
diiXzRKzTOigaTgBw1dA1dRbpQkXmjASCk5PJatmYfF23I/a1jFsoRejAm29XJqeToGEkWIJ6vuv
0lkc3xqiatYYVlQgNz63Cu+koaByZebpPd21ak+FNk5PNbodTcdNCzLH3/eT0AWKd9I26U3H01QS
OJYFOtZvndo5kVI7ITcer/IllNJMGUrI8n56lTcpbCZcNksszx/O1qugTMEgLXJGxtiOB6irYZuC
z4WCgPaPIe/ORcWSZWDfFowOZ0iQdSzRl5BkAgS4XOqBX2uBbzE4gMtYxR0NlSgDUKys3/4xJCp/
Co0ivMcRjMXkXSsBbmJbM0eecAreQWUwGkxfFv/HZXZ18onlU9Ksomg/RxVnetBB4jfRCjskvLxr
96JJC3Mw/KNcVoLYMchmC6RoxBtMNxOF+O1iYDX7W/4hFHbvtGRLwezvzuYV3J0hy/dqKosvZyeJ
QK6BTy/dXEbfpYvSxZQwzEg0lO9viLo8o7o9/X3/4A/8JD3+yubHjLgfgWEEnyVSoznn9mIO8TF/
6o7Q00ihzNsb0Q1ONRMje/IUPiwiu6QngNo99idVBQnc2jt3F+Res4x673Mn68s/R8YEyn222cFE
5aBYtKlzxIbX006BVu3Oq/W/vHceLG5FNtrDDqy7PNcB4R6Hgh1SH6J9ypmorb1GeJpjPM94GpoL
RUO3BqOVMH0EyCsostNWNvQzyEgtBt6oHBAdjtbuHLsEDglOQhT3TpDVmTIypytyNV+X4PECxrZR
KScK8Rsow42YBnS7hSwl9UJxZmQh6g5VebYjFOLgoMBMRBJYltntRHLkRLKM6SuAFV6qvb4GCd/d
c9Z/b/VBwxgM4axb/gdc1nMeNXZSPDCmQZO/iPLczzyi4tUv8dsHmkk4Nip6mKWU13MLv1yeRgw2
RdroOZ9BAlucn3CFswnh8xzluTkbeISdhWdR1u8bCRsxPZ5HX7Sf/broOPOXdbcFVdioJPCwXM1g
hXrRV3/t/ZeWFiCpUzTidMVytjA61g0Qh8zZBptKhRrW61hbMRhPUXBICZ9AFyvtpgsc1030K7aE
GjUHdVAQZhIi3ybfkzyIppNhPg0xf9fMZmT4z578SudZZbcnhAbW7gORzSVSqDDVCZ7amChi2uOg
cHMwQa8rGDNjlYSMkAZy1MfCEgSWggopicVsgyga0NlVYOFlgfj24ZEFTkOcCFC0jVzyvDCHZuJL
3p9seh36I/Gv5gNS7wHI6aV20s1cIPfKQlC/+qr/c5bp0bYcd7rkhARFV6xOcSCitxOcheoT73Sv
ZLVd+LRtn3ry7wReH6bwaMZX6Fp3V8bmRmUvA1jLGnd745yxHLVgZjG3EznUngVOS0NanWsZmCpw
HW2FshzFtg6QPycXtklLJpa60aIplcRDB7gPuFTKpw0xvfgE01rBj7loObv+brsaNZdX/wxwuKVt
cRvb0Ywp7EBWVGzDtPK96gHYfH1w2u58zRAS/5sxTLAlmYzM23q2h2iQuCm9378NPPlNf/t5Ub0n
bzxKfXPvsvgY4gm91bTl671nxc7NvdZaBhKCnku4Q0LN7lAJBvT5WRkD76XgJ5w25w3vzxIRIcvZ
/BdQAkXulBT4YGsPcvWTRapV6uDiOIHwN9A7MQgTPTTeL71dINHB7Zol2Z1saH0wCGmRDBNHp/+l
DRx/gZvOWtmRof9JTvr6SoG2L0Ig1KevkBn+Smg6HarsDgGfJQph/sGVE9/H6EHIKpIj4vGusNmo
ROwy4mg2oIIgY6BwOCAz4qR+rIDvlm0MekinsLZmaDCzc5uwwTuWwAwzXAWqDccaPasIXP/9R3xP
iQbpImKq8VyLviFxTzlW8ps+A/HqhQO4d+z3HGK0QmLQdiz4PvE7ON+GAEx7uHBqdylYWhkkazGQ
CFVJw22m/7C3GiL3rzTQbpRxiPrvrUuUKdMfIghy1lFBAxs4uTDajyqrb+JN7RjW01aw4S1Zta71
5VZLerODCDOYM525dINHi2wUSq9qzQqfE+7SNeecZLU5m4RqZ8uXclTIengYGognLVkv9rMiVWbt
RT61BDXa34tkgveTurPYBaFesWqrtLBkvWiwL+7orxrgucLbwcIpMARUJt46RLPz0uuiRUw639tv
E3DZihXgQe4jsYT+0iKETB1oduMhX8JiKdrsMP2x4GgVffK1SE/4d0LYVZU+UKNrysEmQ8xVLGwa
oD5FfFgwGkZaE1sTpgoIQ7ewavHcIiIDj+7UiQOLaeVYaFNrSIQPynhB9mp+SXtzupsEBfkJyVTp
VMMR3whHC7/19wR/HHgOQ8VdI1rNetmBGi01grPsM9E/+EgZrpySi1udXo1IE5QLCUG409RhF+ZW
Hwa2wtUb/xV+oI9xkT7m0pokXFu+AFtSC2Gr1QTfNbbzx3mKI8EZrvT3wy5MWtNtU2XfWMXMCJAI
tqFJN1tkB6xLFhruLwT1rJv46++X+IJu3CDwXcAPq0l+YiBJse1PqumZXOnuGg21EQbco0nWNYbE
clymIcgbwxa6FlhHHGLWcyPvt1p5OsSLMUii2Ebz+pAoonL4SpcerCvtoX3BHqVWv9KIqMwD0Gyc
YI/jTVYy89GnFo98/09r755x7nc5rmNt64EOsvbZg/o6lnoOt8HK2++tgtT13BWa7wYwb3m4e0y3
MBkooxPE3RQb4O3ITvc/oxFzAcwD1xXxwm+GHEt6wi3w/0RBuEApqym9rmqhfNykww7lJpK3qe/D
WrvMvaqhu1q084Wr9hfc0V4BPrQf1hAJq0OQTUoh34K27m0ftcpINIimHB2qBalcWhX/AbK50+ZH
MwaUzhO+1k1fZ8K2RNvlbrqorxJRV0zSrBbDu652ew3MhJY4GGHxMbnbefq9QmnhMvbpBGFe8w5h
RWCWuvYCOUxquKfbVsUHlCFqhnYBFThsSircQskGFbEtfL6OVT0EPlFkvl3yUZi7zILou+Q17uil
3whgM78a3Xs6YW8aIj/CROpQ6uNCzCl8iBq055A84FTLRuH972qcaAFegtfmseCTshfn6ETdDXBp
TIqtIjkzNCUW9HaO+Dj1IxSYr2aadRkEOU1xcEeHksuCqqZHjmjAs2CMn7I7W5dYlcG/HUJJ4tS7
boWwuYSDr8PQ/RyGPpAfnXJ5UyNTFFvN7qCKU1vOdxeLnQ9FRtZICvq7LmtCvIuzZ6yhy6wL15lx
TAseHgj6jaj4GGNihf96DWVgr408LeLzFHH1EFIz2nBX2TnbGeSKBQoUq1UZQ+NecyQ+UWUzBFYe
3G1qszFaomhr2YYSW4uvW+AJ8uPVQmmg/zkCuigeP5625UV2eZz1RvYbP3oKQqXh+qdwZxzBJabI
iS4HS2281NpNpfOiiNokZKdFeOhFPxEDb47T53ijyuIx6gbqtfH2r1VUofyNiH/kaeW1v0oUTd7c
y0RZIVN0XmCf63oW8NL9s96AJtlsB0DKKH7Htc5F2pw2/8PM5lEeMlDgNwSVIgKUiFiYaoYgVtZy
rcGrP63p/x1S4AM82V7QXJbX0mKgXUzdDhIJSt6blGtO2rlWzVfkM/5AuSo2ouz8TPFLsM5maylh
8cfCTh7Nx/xZEQmEeaa0diSuVbR8DcayPA4dPTOjBSB/W+CIGRUZSnTNZJYOTR3LNzitSPw6LcHb
QD4gewRwnzDoD3cKI7RzuG1CORCh0ck5hLO3WUFdrNnQX00pqB2INbXkEMUrf7ADwCCv6AIEKEbN
9KJTUW56nFw1RB3LQZz5zi1kjgY5NrpLdcJy2Fql5XasrhviVwNEbh8ODQBDdKdUeqYOYjHCtWIr
M2ge1MCYs+NGx/QAsXi3lwyzRRQ4BJq/bFZk1xd/kSFuR8iN/AJ6mykBHNCO31nVQ57yH4O+7+u2
3KQQjfh3AkbifUNIHzjwDhtcprK7xGtdJzEihwAOTqt57Co+n6m7YGHhfdHbmQf9xU7owNhObRHg
cZeHLuhkpzKFSA6+Pt9uVWpl4HwZOfVxOOX7AJxWWur5msnbEo9sQ7lDjO0kZy/tr06tk+5bi7l/
9zx7uFDltzf+rJ5smQFZ4U1tsLYdTlErSjGC7bzYOIv6OPuCriinOkRf5RIJmOgv1DT225tWd/zv
Z/CNhKFj4UeCVnYVx+rvzCPsuFvpseRV0JZbQZh08saM/XJcVHfIFm3r63l/EmJd2xe+X+oVwjgi
c9GLud+8iTcLKbP/zOOTjozrJtwLEkMCOUO3U3wmEHlbmzx9dm5Fz8VJhVjxL0GUuX2JxqsXEWUT
C1lWznME1kzqnlP1TLpRp6THNnj/aNtZbue0EkuUQLJgxs26SY6fj578ydfBAHIoMCsnPod/R445
ElLp/hChZUUxF2v9i6r327+fFK/zZfiop+2BfXCk367xkukdGffOlSqUzUf/5S6MGHcn3i/OnLJn
AjUGEyCIbASnqk10aDv3Ka7gnQTfDlYe9idZRV32+Oi2vXerM/RtjhnvsoUtBsPAJms6xEXtUz4e
k+t9CPfWrVpiTU9CpDS9yL6zcNr79lMgMJNOUJErlwMndYOGAohei905ua2NskJWy444ankhY12f
eB9hFUX+afGyoDGLu5Uq2NBBpg5z6Rp+WnVEsNZylA6HfwSniTnnVrN5GiSnohfx4HhfZCWVx3Q1
2nckhhhRIiYi2qDoUmLsaGCHsbJRChGW2m60BdMPfT60mGJMt0bNxkldsZTH7EtjaUDpb9FvySPt
364EMRzTJz3YHi3bIW7c8VLpR2MeQ7nDrrMU7aicZeS+cxQ7sh5EziuzDtPwiktsX5wJnYJJ9bTT
nqRRTzd7fEzO6OE73foukKJ8eD/7rpABk4ZlrO3juZLwn+JIySLlZtJFyvR+E4lplDN1inOpoG7M
DkVFEK02gkf9gUlvszbk6FRLRCiLGZGiL7WmT6g4Jt+4vSmC0n+PWHiXHjfBvBEYnc3qz74OTdSB
bQrwtghmeAXjrGI4WN/SxhXF4BrZAa2I5vd58CGGpZz0s3OlkWbzR+RGfZY263rYg+sDeSSZ60cy
gcXfmKTxcdFT97wo6g0fbKk1HB18VO65iXRa9MYoMim/B58goC6YlFMcqpT1WgY0GgzAKfAPW862
0/Luiw0OxuxW5ttCYIz9WQPsxTUv88IG9OnudLYgfVng161I0ZXzWV1CEre4lMfyi4eIUH+eSrdm
rUcSJJmOSZjY60tVs5ID8VxViAE/l/3idxUc2Sedzy0L5hOkNmjavh8/ZeQCMycOwfKA4OwLXM0T
yYsP4P6OP5MOj/xwadIO2l/RzIsXvV4YrxkeiFQrvVYyw4Bn2yNvvpOOnTatp36BCoiVluQcw6eO
fVkgiCIYDWIqzIqJi/MOjfq6hUDyggrORuCfvv+f+fGYXm/lNSgN9S2BpjqGuLensQk9wpXYN5JH
fd74xWq/qwbbAIgSOhxUef3p4ZwpGj7mub77CaBuZ5YVEl8MzRJ4zFo1eosZszkNtTzQkAfR3OA7
2IiCRr+2eT4E3XYeQ5vwygbJpObRVwbDKeOJJ3BmhNBlMS4ZLIK9t2i+XlGh/qB0JzkIuTl8ze1z
34Smjbuo/3TULi/M7LBkNUSIKVZrvFfJ95oVWGAsYo5d3x7vVK2FdUbsAq0GL9qOw79df060nvgJ
/DWNdoTire3s4T16DgKi7ClQLgZG/Lu25aegVDTMbZD8kgIckONqiGsQhSOJ0wI7uXtZ7JRBXZUD
zUfYvfcGkS/qMTeybVWzmsFduXp4Q6+Z3espiIfKrz0pFapfx21uOaLwwfUiDazJKaRbxHGoqaLJ
g4UMcvNGzAoikoROIrPXmu5L/PbR7vK6IgWSr/Y/58ca/L/8ImPfSdPS/A3FC5SWOJfHwz76oCFe
AKqMtqdFCEqgLCErBKZCFrDKRO4Vs0j2+qytHbAxIaBloL56AZsZVC5NiJrFPK98y3x41M76qmH5
CdnGf3YjGkOell+B8YJznL6yo+I+CcDCB/qdJMUn4Bz4ttjI0o0j/vlBZ3hm0EdetbWn6WvUIYtT
+Nhvdx5nBauiYz53dbI+OaJ5tTMkmlssqaWfRmyjNwrFoJZsV0XUWYgeLduI2j7ad7BqT8KVvnPF
tmxUaMh9JZ1lwooSDMTUPTP0ZoFb/RdJ5SK0GqMj3ty/n8Lr9O6zOdmQZp28+RezwMbLPbKdavHn
1DFiUqzcyckS/zoLClzjUOsWvF7KgnD5pahwXBh+tn83sVALc3LhSDhwjMZFU+dJs5qMXtxzWdWn
yCJP20cN7iFqDJOvXNQS4ITqaEXJ5jAzZy8cZy2oh4E8eTQJGOFAkYbHaWUZ71vRsSh7QkAIPU+F
Oq7cgG9Q//bOQl3kUC69H3NEa4YY4Q2Me78uDGWfXto7ohTCZ3ywVr8WnB4qsf83skjNE0JJX3el
2pT6KXhfFAKh4euckQvWTTY1zGkLWA9+MAR4BFBgYddmHDj69k1lp/wsrPSVVpMiNYGP+2CvXdf3
O7akITji0zYoCSrXrnUpFE0dsQkZ9+W+SCAMj+cE7QOHSWS3gGK53fFEoGOTrzLB9cPBJ+EDVyBv
zXYvhKAWVQSFg/48fWFNpkXCWcmMBFVaUZzdiIEAGXqAG0PNnBLoMWZW0fSQlSUAgf+/wjXATZDF
JjEbrjfM5D+37cV2+/JC4egIpicbsBI6leGsF3goQhfRd8bYbPNrQdw92MQ53QnN8FJXPcHpg3oB
OuRP1yOnbxRJpanD1d2dWsIWGducttvoXUK6uq9zLKUQvF8aEgEwac18B3AsIbDzakqj2LCz3M0P
wgEJGloCzduI6kSRYC53jBWge1LhAgCrmZQ/G2uW6SYjPyg1PDXPLfhlbDG7v+tjv+mu3TIyk2W6
bFWn6wsh6kGXxsaf4zley3VUQvspL7WemMIr9o9geXifHSzwKP8t2rZ7Rh5FB4PoutX7jHYcuJtl
9xmN0QswZ0ZFyGHfzbb7idkTrej+MC3/kQBvbt4y6myu9BAbwWPDCTE1WPOIhWhyMh+8ro8+wCFh
kLe5e8IYAnU+DU4ByDatlsDuG/1SeGmrFzgMDcQpobjnjWFpg8T7Gk3cJXYbENIaNLmkZ1pvZ1+b
JYFZIuzidckSRh13NeSjqhmCwZSLFS4vemeLNoxo/Jl7pKb9esFPsAVO4ncz7ejuehtEhCwq/zcD
tH4cHHMQTV1u6DOur/u9qKHk3NIwHBwQwsYeK50R6AFb117wCP+tV1TYohroaC+Xq50/+619gqn0
jWx44IzPgXYVxDYxQnyGW/gmP7oq2KL3dZWXiXPeTh5ES2nUv6nREf0CMXMkxKEbG//MztKW6R/s
L9O2Qfx5xWzPXcLhshus5ZLggRm6vQA6EHXgornB8JBxqCU+ulZpIinxR5J74oxfUqACZLY4IE0m
0jvDq8jhxmEl2XaNbyDIGEZ3iCCfm9hSL2b11SdUGHQgj9xujsMEuyQHdS3PZj453aGIH0MEZGnB
B+xftO7lb7o07VFX6h3/tK0fL8jY7UhAT0VOIl9O5kVcbv7j+antuliLGrYYa0nYKCTpfcpxjG/h
RvUsNj7mpel/hLqBMD8ntrcXw4HB+STXyOAwLZwcmRncvEDZ0HcQj+t4fcgcaYOwkW3ZiS66yRpZ
vfPZOKmDEU4FLQke8HcLdPE6NzuvDRrUx1WfGHYl+vojwftooG+2uFdHrBLqf9Xieu7dSSSp94L6
mDe4L5E0v8yL8Ix05Bdy23QAL5CYJh2eysMWxqKJIc9T8E4/sNkJAne/AI3mm8ySHj1oW2NTDXmf
khVzDtXJ6yXqbS/FHqoPUz9d3T8fR1xYdt6TbW/omANY1A+QkbdjHXQzBBHf4k4uLvmgIQKx7Fl+
yV3v8tKWSmSGNkLpWshpn52i6U7XCBm4ILVo762omujAM3qZpPpDeXFZs6GqB4MWj4q6ctOeB8Dt
UqN72xhnfd6qPZtrJy5PEz0H0Ep3wTC0o/aoCR+2oL8W5sO1K5yQYCTbQ7FeyU7qPXXd7lVR7C4B
BAEpUCYc+t9Uzuv+IfwNxP5NNmi+eiUmbSZJn8J74rcLx4/7vqPkK+dmbOpxqJgB0UbfXE+Uhz/u
bNm/Q/G4tN2B9vy9mlVjAmL78qMWm7Ls1xBER7UPHU+ao1F9VmugCEgh9AdYv6yu78BiaJGTSn1D
/DC6+FbENoSJGbnug4rN6/l9zF95EpGVvILIRmxfM3g6Q0s9M2RZV+u4iemllnOZJzDA7Pz0tu6U
uqbDTyzA2wEAGgdszJWs6ZzyFziijI3k8KHHWFp3jFfWnr9zspBVPCDn6NpkHY4Bj11vxQ9KqAR6
bYgoSEAIaVOmY8kF2CFcP4y6HuPBDffxh85g9VehlqDmgrlIBUfpn/vHw7Zj5cu0q+Ht58E5RZWw
H+wn5RjwaRYrRlhakNDRuCREgqt9jmd+o00WLNvcVgW0QfgjZb8lNysBgN7MNk/Ot1kgHYD3wDdW
EZsItfQnbQ7fM9jRv9vvL6N4sMQwxeaLZNBw2q3PgO6I+eAlRZ9klJ/NsRU9K0WQbXLvEd6wt7f/
M2UJaLZq1039QO2vVtqtBRW8IoO7+KUGmx0mUC/TuhOn53CmZvqYwpjEGc9+pULINdPfLHdBMa2O
SvnCUkQoHAa45OjWaWW+uHY+yxx1j0/JIsQ99Mz79gFsl9x0j5aVxXWc2f0ec0xUj31x6u9YXlbG
R0zh0e2nUBvBx2DUU96VLCR+0EOJt8Q5967mRElsukwvJbMv7vFeu8dZBr04qxn9HiZyYwBXKEV+
Z/DuTppcBwn0nUukcRLCNF9mTwKZzyvpQY16jy7AL1/kxSPOLXQqNsPCJMma+0NmoWn0IXwQ0QuA
6Ejyh4huvSJWKIBFyGdCH+dg6Bz5JTPm5tMyepA7Ze9BX//8f6wxXfGzANQwRdI+RGDvFdyP0yLL
4+aM1prtVfopGP7G1aRbLFl4YkC3I4k6XFgHt9ro7f+DNFT54LNaBwli4VLCWUI4239RFPW2wLE6
oUge3FNlvbTPSq1mW3bIdy4jbQiPd5igRAg5LFnaeFeiTfNbZHmxflJMI/C+jNZwrkSeBisPcMw2
QsygbAZ/3MV00HhBA8S0+rAu12WBXmnfvTwm3lVwJQxMj7eNzrh7IRvi3g3xCFKlh+RdDIF1I4L0
WEJjhZjknhZSiBz3HS91JGJ0OmlJLLbXIs87Pswb78t/ekG3p4+KGoPd/N36GGPjxaqe8McfXpC6
F7eQk77YRIeZYIk8X006zCh9hn6RNEkigHQu5nt2Y5G4RjWUvtpbAO04V29HANCZbrTLxzyHaN/d
PAovIxwEKGQAuIEywKQIA6l/3IaGA72/VNjANd16KHXgSbB7XVvDhKUINN6tR9wuDz+hlZsyorHF
y+/6Lwr1xImpKQzvVBrnpjAQgheUxmncRjAjLj1tTrlCbvfUeR3SBSaz0oh6Gc1fT3OrLMf5ayi5
qPZ0Al6wonle3LVLOtVaIvUULmuWr31I0Nh7QcCav9X8i/8lQ3rPt3Yy/cH3gTPQq90edYuKowTk
7V7a58Qe0J2ECZKJ5fDDBasFzWJWMKGPsCodXwk3+ZOSOJwgVv4+lEXTigMf8n0F6p9RgMR/6Ofw
PLGmvCkepff8l8mvVoytI2O2fHbSmXDWR8fU6vpVIlnSjgEB6haCY7V14rfLnhoBFCqYq7LB+t+2
vKc/cEmM/AsLb9ERkEEaPlB6ynJsOUaVk+LCC8Bdn5kAThtrfHjFYbL1rNL/FGvFZY5cOX408SWT
6CwBLuL9auIHKHTmAJtjr4Lr0vTU1nyFTROir9eGiKp5AT9WEBMIJ0VHLIXBuqiEN4FqziEaIhsT
cjyc/7JvOwExNMoKSj6y0+kmkQ9Shsau3N8Q/pwg2CZfYe/L8hKTXXMwwiUBjXfyMmz/6B7Pj7nY
k4g3oVNDvRTo/D87vhVuJdeUXt+NYTvvxWqpSAHJ3JnhKD/Vu23WE8bLDIzkXxNoIH30f1V8KE8d
lIXtmgXC41JV9NsLa1gBWh2KNqMHdi6TBAF7Rr3nkIHaCclVXlamxkLp26Bq/2eiDQ9kiK8KAQv/
lgvIYfiOMiIET9Pqvod7jZDvW93tKLdmdIM5+KQYw6uLlZH6ABllme90MhV/ZnY26z/9pTkbJ7Kk
TafhJbMy1cEyBdE3LtJf0yLb/TE+Wbeph6ggghT06FmW4FaHOVdEf1WyhYf06JuHTCkvbhM2HqNX
0T7DSDUN51y4+8q0tbBBOz+eqBdIgUwZfbVp16qVdYNhXWg88+/Y0RcFhG0ZDHQ9GoQ2wsyTwlvM
7MvnfoYVyfcG9L4m9Wdh1kiRXDWJgeea4ih0CjMy2lw7yGRk6W+h6ixswp5DoN3AaHze5HveiC5V
CdO8WcbK3SgKDcQlLTneus4Gho7OzuqoZyGgcXzaTlIKF+FKHt9RIAmwiWPkMCWurwFb3cE2XgYb
uZjaeR3T4QHLI8WH+eprcNx5GS6qIJ4dEwbjdxwBMzUTxIPv4g/PrMvdNidIifiTMbvxwShixqGW
PiVWLBTQhruEYxrzI8mLCCE5EjjqGsDrwy8xZ4rOsH9/mcw1iB3NTaFeavYZ6RQFvvaSAIgm8Oco
mFfgZqg5ZWvl99ol2kDFS5F47rr/Aaq4NctYs/0+xtUPXBIx9UNz4BTl7oChf8/GuNpQISzjK28m
oWxAZOTkKHAGgTjaE69/CVdqhn2OaQYPYsidNqpcdJyn+S4I6LTdJjwF1BceRUjCbK9+NAnyA8ll
43bDEkFQ7S++yts0D6zl6Yt4VN5eotVQstcVVsWbLxann9AIzfcih5Q2yPqfzVyvAqnuIKPSjvNM
ZOl868c66ktobtV5XoC4kHYYh3c7rV1kvmSyQfBGrqsm9CCBFg/tvhMBxlosO31JOsbdsoJ1fBbi
6Iw2+IOjw2JxO3ns0o5T/7ZNuNnuDqOHwYoXeTu3yLsHUQRYmmdtFy1K9yzbmxgav94hkm95QzIg
zq3i1lGB/GIf5dUCsugxGYWLNv4Eli39lroeOzthUXDnvPmY8fcTbaLF53SWP70uzrmw0mR1G5wS
AqBZ6goTDCrnUoKMJljXVT4MzcOe8arjSbhgOjy+IDuGWNEdoEDnZpkAxILqvWsnsFCgHpo1kbih
ZrzAW5BO9d2P1AkIhNPz9yP9KX3lLey4mE0SR/Theus6iEWWLymwVCtXjCph12ZS8p/mUym3o8r/
Z+FI3dOdr32cN1niO2V/9AWAHIHB02ml/ECVfmoHXNFg/u88RoxR0QA2SX9ClxTBfWSxONmQv57W
PjfnfnAwSL02S69FYbWveqOl2JAcvYfAmIDoWe1pAfgxpGEcfFkWtyFmEwvn0EkrXNtRnkUOqrzs
uGreQ8Iiemu5cwgjsdl3x/NvrqVOGpXJ8qNLwHwT/+f0YBD/xBS80edvJOlLo/qk0luChV32qAY9
+wNt+HgdXVS0G76UCL6P/C+5d5ErIO7GoMjPREQBB8dydrdRMLK3gppu9SLZbM31SAfKxJ9TnMYf
kfMUk97Rm5Uai93i6VvuEVTQAgxHE/XL4UezezHQ4pZutBUbWv6HTRsA1vlUwG1h+r4t9s7jfg/w
j05ewnF8wd7/1NDkblR+dKiQsJBro3PKNrA9UpD+5foxJxN9SnZ05eYDyhLq61D3OBduQZ1NtU2D
V0cB6qxIZuOuLX1owm69aMe09DjygDAEieyJG8ddUURHy7NJdr0MK1GHDHmwj3Z1U+/UG9gM+RwK
Pq22Lp4YBM3PLwWuWLfjhMibS8h07H8apNdyyJhBjoLGQQurl1TMtHk6M+lwDMeW+81lMJpy/EOO
kHEB6J87IqbWJfIurNKA0CI3NhaYm0jwHr2XkV9YIW/dS4j5gz4kqbzEVDEzFgixqUgd7vt3LUwn
sVtxwt5g5Y2UBYeC4pYo5YIyV21Jv+iGgpY6j70bnTfPZTt6pSVgwZWwC4LXUIZdRt1L8Y/tkKMM
zFFD2YNcMep77KDdRmovCEbi1F9Xc8eqb8+vOW2KLqOdkvC62ar0+toCyOh/UFC8ZXvrBqLVeQdd
4WAPb0kLbJQ+skFJ3rHU7Aj3ej7f8D5gyDht+zJJGOMroh6J5sU+mmEaAcd+hRDkRIxnP7/48ojn
VO7Shd4Xe6nO5kHQRyxxDECtwWRZRnY4EIPvff/aS7gw2sX/GjQfMkvKY+h54OqR0DL+0a72PYZ4
35nqXnsgE0AXYUP6Xq/hI5Ug09tUkjzjDKzQyEaFC2faylJ30FMaVuLXnowP2s+sF+20N6OL4z/z
kt6WVZNR/mBo7evwxXLfOPbSvA/e3besY7mx3tiN9T5/xNjkusQBZNm/NccJ1JuI6Q9hoGKZx1tM
RgYT7+hKvWh33SaQe20VBZdfpt6TYGpuN7sPNjmFNYbGV4QjkP9SsgUjCc5PifW06JD62LXfSrMp
EOA9wqYMdyUmkx93SN6cV/THzpR6Uu4fqUoYQS9oDhUq4pbyp/f2OURFaXXxiWbm0lp7NKpAgZTf
sHbUSI+tNWUxGJn1aq2aJya5p2g7qjFAU8+rWuGpevxy4M6cfuUP/SjPxJZlfZsQS2cgdmElLar6
UB8W9CoPVI5IitwvT5lvmlsU7hcKWgmqMAJoJELeFHNLy6Ic/kMNttnB65CHMuklQMLpkIBr9/iw
T6TjdSHUYkxfddzl494O7m6AEPPKv4GZEaHdLa4Ob9ksDKcRURBc9X6I3FDPSWPecws239XMjwpe
ZZu3pMshOsaQyf/U1VqMe9PZT9HZ2HmCSNjCKCf3OnOzqjrEpAuonh0KAmRBTXOAVkp7ch7WMUKh
CBLYM8cvP3CgMitvFuvYxl+9qQvfpaPWIL2xkXN84V1AkZrOpBkBeHToDB4phP7EDTX2Fb5jEpIU
am7/kc5fGrBGfgDhYalCiLpAA427rytHhotZmxX2IgBZU0EQKO5d1HcYd6FKf6lwlVrKiba0kBGU
z4QKJJ4Y5p4NIPl50hW8nReoxAlWJ7fDyKoIODRvNlZdj9vte94tyceOjCLhe1Dmi1EY48n1aais
M5KWOSdlgc36Y52B1erZ4cT8GiIFtKR9/VSNd5z3AALg7fUvu4wjMJOWZZqsEGbSpINrxd+VgQsn
cKojpcgTItF67jN0QZNLpbR0ioF7Wfj2sIQGr19SajCayEf8vIbvUot/LTGPRWhAW/uHliFLuzOj
XW3SlppbCLJqAj/t3RcsBp8nyvK3gBWu7eStka2zlgpNnIVSi7rgYFwDth/E9XgCZkL5DYuEk1d2
I6WUmFGoayqfBkjhg1zcG79p+EeqkQ0FneZ64qrMKgAupuV3yTWvks36n2qHNd3+lNC4Gm8gf4SY
7x20wOf1tRZOnF1RLHU45854Eg7tvTs/9J7hB1RhW/hK+s+rIa1+D3a0FeAJpsxpKnP6QqtIojk3
XDW7py2prIVgJb0dkPCU+tm2F3yIoTbPwCFZ29BcznxKJLZ3YWJguFj8r783OesIPxERkEPBEQWo
OxDLnClXepld0y2wiETIncXEz1nqo66g1dC55fPnAOfE/DJjBlr9643NehyqyeuTwLpT1khJtSa9
wztI7hp8a2YE+VmhWTlDiLp42JALxHmP7Zfa200Aky6OSoyfAWZIRpEfkpbFgfxPwnqT3PlolPpc
5BYFpaoXyX33lBTbKOUOzC6uciZ5XhykUad7aXaKwYZITtb9/qBRPQVQEKGYT02pqbxMh10a1Kgy
ulSryfzGVmXe8pghrR5wjGbhxA5XLmqDCALtgTaJ+bscXIOuJydQYXl2VXSMNOgL1lORq7EPWpNl
Y4ELtnwCjEMP9lNWKq7s0E/u/wqWekGOdGZEdgyJp3ZRDLlUCDgfaM4sZn6UGa/pDFiiRMJxh9iL
5o/FMAqzB2JgZO5DdCmUQVSjltmGnoo4gDphK2+Wztz7/2HU/5Cf/bS8YBs4T2c44WbEeSmN0afo
reVKo99Kb1ha+6gaqZnVmReDlhrNoMDa9QIilOVcTC+iGPN63nPSmIlB+spb7r4FAMD2pHe92VCz
vsyozyY24Ff1haclN08rTeiPSpbO3nOidloKKEnKmVZaZnS/zpmOMF7bOg43tfSjzw0vAHuyWgpD
klyg/rykZw0sedHKDeAeOS0gNiGHF7D5Y5YZIR8HtCXCCww/yo4+f66tojCC9H5/JaFdmALX82CH
StHz+Z0BjNSCxyFtvc8cy/fH3a99u7HGjVh9MssZTygn7vykjcVmVRM5EZGy/IXm1Pnq7d/Q+TnZ
3i7A7dBcj2j6LygTteeUu+qgy5CL+wCJJcx9DkpgZMaJFJha6KSATGcXjNXvVb04VwFYAboNOw2q
oeYhUhkoXvcuMu8zdCAVyrC4oNe/WhfL8enoMYjMZ2wUnkGUVwOq9hHOGE23aJtf7qfEuf+6t5GA
n8Nt9aKgGLZEsKSySTqvzsjSS0baxiV2L/SYDRNuePns4HvHC8Xi5hwWMEgLmuRjxWZAf8jktbaU
nEBoC6KPS/luvltoasrRPyXzKEvEyF2D5Z2D6S1G/7X6SKkck7QxApNDW+e9yuMqYdmG3I6LAEvp
vz+hdGiDbpgblBSoH73qysOx8jO/5u/WijMXWfH6DEwSqCIcoOmg+5LdZB9BCBuyHIFmIKhhLRbW
jDM7aiVIuT5RW1Y0LWMEg5qexeoq/lSCYC2v5ftopP1At4stFNps/Ls+IPWPZQVXkZp9XL8vKa/S
G27nBeHMYU3H/nlvsVt58Z0tn4HqdPmu5nw0WfS/HYcD58yrjeYfj03h98jNY/vAFaY8+y7ivz8j
GVFlzt02PEq0BgSwB1J6LOTM2Id06AAAlhLnwPQVeGWoWcxbbdi7RJ/ULkqw8NfMFVMKSODM+e5f
Ze7rRveU6+yv85j40JmZRWw0uqw/rTIDJIl8+G5UFw569IJo1PEAJhHBtxzOXgDD6LN0P+SLC3Jm
YKIB4FqzKM2lS37O27KYFAdHRfo1JuSYqtnvrH29mWRuGVAISuuh/3kgCH9SO+wfRNSmZ7AMeVOu
eL8RJkyOcbsVzTrcNupz01fdeJkXYOw6O/ON5i3rovRcHKiy8xxG0z+F/2eTxCPA3Q8/48UhpsSi
6/zR1Ml3Q7VUZzJbvDDIBH4xLngirglAWxoUsZOhK0TDexJQ2qdNUvyOMK20HS7eFmBp1n28i4vZ
KpkfEJ6FaawXiO4Nn5iPd8BX5nun3C4W5DrxjZvEXv3+2a4aoz9/sVTXB7y/j2ZDBJs2DURIcM22
HXrKekUZua7XBxClowZvBXQa5oo9vuKrJ9/DKc315/ffjQcfdZVIMbwa+flPEj5a9TMjkVrnNbW3
7ZjGW2FrmX4CVzjBNyOoYTEgOvmjVbuneiz3h15J3idRl9f6ps/wrOTAUjSty1CX1YkccLX8yMCc
gdrZ9ePcNWj9xISn/CtGz8D5MvwkFXRqbYWQ2dEih2UMaTVKCY99l3YGbvnJJZH6mxiPzq/vD9R9
HLH63IeGuxkbDAkio4dE9wcGGhzBS2fZG0N/+Ev0JjHwR0saxuKF0b2mHBRuYxapLcjvB9kpeTWW
LryBz6KvUNJTgTzHyebaTlzcrHpbKuTYs3hawZ2GHvWSLRAAH8xnx8bdFDz2JHqhdpV1rwDI80u2
cr3bmS8xL5REDSo6kaeF2j0xuh4JU7RrSBmyghKoL/2UlpiLjEWnpp7HteJ2tzRz4vJdGM06w0AV
PhjjYtK+NdX/8SVlfDz3cph3qCtXqohx//NbiUp5ltw9hCpdkOaViQFiwf2kvGqP68KxxMMAHixV
+pUBXtCgvW7sZAqTHzR00uovI3je0hlHttCMY00BFYM3JY7NuYh+uhi6aaueEGdIHVL6h4oVakmZ
kT5X5HtljRF8yawP4VUasuolSEMRPkLBCOhKKXQCorVZU51ht2bk997qRB5qY44IdOEzo74W/L7A
4J0Np8/LcFgpyXlea3EPNVPX6+LmE2cwAD31VU6wV6GWxzN9pHjEbb2jexKRpHSD2mpbENjmqKSk
Uh7vgsIkjUo0DXXtCB1/oC3Cux+ShCqAlgHR9P0M4mEXsdBesyZqg59YsYoAkDzdqVETiYQbG1+C
WyBcmr1kwXENIBqWUA6VTUUH8lHgKMb3CqjaGaLQdL9zVr2adZIKDtSmaPMGDK/Bm7IgqIV/D0l4
SDJyLr4z75e0awzd1lzfCqO7W7T0kK6g7QeecL/C8zVzG3dPhCw9XVNCEZQPB4xapMjhaueJ4KjL
VMDy6V9sSG9iIZ/13ikLiM24Br62IDjXcfMqVba1u8ndVTi0FuJFdSKgNC1p7d4xK96Y7zXSYz/q
8YQ2T4EKc5pvLvfLn+1lrILty2IN9QbId0blcHMsbuGzglbnJiEYs2+ZBy/MbrHODHsx4q2RbSmw
cFR/SZrFXdB7qI6a3MKgOlMEU5PCYktC0TG/OQKGu/JhPbC3kmhj8B617+iiwRfxWsl9JFg8qEPI
TAk0IaYk1LKlZKFkOlfkqhS2hYFSxm0yqN7pbIbdJCFWJzyFMAvRpjuZqodpnjTPzw8/pUK923dJ
/5cSb04d8XYGBoEd5k9vfMfOECc1piG20f7QA+SwOopHvdUyHqQtUjyln8PGUPwjd3yBNu6jgwGC
IEXd+4emqhoJGqNVO9SGGuI4L/Wr9a90xW/ypGGyHskLZB0dlJtD1hWO8VqAJ52jX9+8ebr0F4/Q
uK/VmdPNnC691tZZFwIncQdgy+DEkUQXjfJJkpt8PpdoSunzhz6SOmQ0btGgv1s1ZJ2jH+unZMTv
IJaZ/WAlPBJlsvq54WQ+Icudmtzd3ygShNJM2Ss9brQHJ7wNPHN4taoMwY4dKp5/hhVO+wOMe3D6
z4XqHvXUMDhSTvaWa2Z2LQPxfpai5jFaKb3arjZ9r58mgVaGRu3mm5o/KKTQscW0sbeNKKedzo/A
rVEQt9ilvkybMj+u0obL8cefNZpq8dU4nlNBVxjQXvzsfygqhVJyz5t9MDR/JwZv2XrwTGFbkvJD
bviHEkjHOOT9QP1T+tFVWV6KAE0vjv3WA+OF3l/Rkd4TJ87P45ZQGbtPLZyF6AuDF5pV92YD93B5
x/v7D+MIw6ICtmKSzCPEvuXP9mejk5oCxin3UAJksnmrt2mgHQmYL9il7zx7xF2ohospghlC5gwo
tdYjhx91mrLEt56kLbMKooR8+qp/4sZCHIQdwLXIXhPwRfPWEYZvAn8iRQTWAMSmiMk19UUlygW8
5ZjHy0XJ3sEYjYuA5bBO4Lxu3H3P5/GhileKZjt4T8MfoZl1y2UjpIQyVUuX5K6tbhdRFBw1GumC
Itio6GAgpFGVuXudRgvVfzr+DnWspre10+6CoR9UvTFORYh8sn6am960JnUmgpvBR8SwL5Ucok9R
Fl7EAOmbSROViR/8ks4fzey10FbRc77VTn8gUGguE2K3RsM+K8+b6hsx6veNv4ZyUdkS08A0vP0d
L2cx/rgBXvkYcvkYEfV0Fyn4/IXkabYwIH6acicrK535wH11DN68SA3u0cililnpgrUsANhyy+NV
EWB3E0Rl/ElDjkEEmQ/9IEToTYW6emhIwf7eZmx0GJkDLl2Fj/EKOWAgozYOJ7bmD8p0HRUnepgG
2etEV+oNQkt9Xv1usQe7bZY3pRYn0OA66U06/S79Z4Vs6bQe+NnEKFw4EjCEXu5buajWjBO3mTfG
6QuMuE/olcWAaOWLvOobPA89bib6oDS9OIzAB/2znBhkYiLn0gySCpGsk9SvP9oJfieQZ3M0CQCa
gVQdwQTRS37JpAXxeXwnfsC98I912mMeyUO9nPafsS/KmSJCawQ4rO2GxK0vSrp+3+NFFx6AY9/6
BAWL8gwUzPfCZhv3oxoqudzWNmX6ZOFPfy83SqhnFt78WWF+SPiswjQ9kcBm+KbA7eB4viC90YTM
JQRbThhalQ3gTwahgcAQCEc6p1lhs1ke7BLKu2yWWtniM5yjyxSG3/KZ7r4/SaHucZXfZQpat0xW
7JCseo9YimYXMq7VH99RU7LvI7iqwQaPLclTvCuS2nTWK6nSHf+zqRXuY/vugrm6UPp8AOejtTiX
jitMTGTwFrnsVr7Koctu6SD5UUrI2scyWgaJryw930ca3grDkufskszulZvQ7rjWcq4mhZiKGpCy
96uzQmuSuwXzJNyXvH4ZlNnr2lE3wPk1bJE+9Nl0oyjlPanr2ZB517OYW+a7UoNjCE06N9b6fv2s
4EcSIjkFWUZiGrEJNN/Bubi0/xVKMt1PtWHi7U2EYFEujrZmuTV5L1S7JB1K8T3Z3mtJs8BApUjl
Lsj/9yRJHJyXMOOtNytBt/TmTrn2avfMIY8eHd5eyxZ3VvLI2jwQoolgoe7I2Xw0NQ9e58aXxLAC
lnUfczjUvLF0C0hxsMGRwkYkAcVQ7aFbX6wncBrjOasjGfXa7a84s4/UadPX7FyheoEc08q1tSu4
VuUbzHyOggfQK+AQ5iTXw7EarplO8jLouyceNXAfeChglWgnvN4J0JMyuYuwXH+/QWs1iTegtjDv
w93mZHjICABeA3Tk5WpzRBjVVvJ/nsjKIAt5fhxm5souSapC8/x7a/wz+hQQmvL4gRBcZjOjuar8
aaX7drimHtX2pDSH0XsalxIhtN1OQtpX9ECWqhzkWmdXDhEYIo0zyKGrX++48RnSemg+fhXr2ZQ5
z3hNoiskYN+PS+8LtIBbIa26OGxz6EseKoMu2WET0zI7hbwoY0axccdbiPAUNgjKCvMM4+kOF/uc
UU+BnG+7lqnUQi9Sgo3ifZKbvXSd53Qz4JODKtxsK4xs5cvWhRKDsCZ9X/OvLJiN5OLQ5N6L662D
SOFIUMvSc3kxqENjmSfwrdj8z7FBUM447FxJQhbi5JLyOJH3fhfuQCaFHE5tKCnhKYS6ZxLFyeTR
u3vx/J9opHNE75vf/vh3+t3OlSMdD5YTtD1IgQuL8pJVPyF7tpD3WTD0H9lEZurSAmou19CGNOns
hnNfmDdB6mIUfo23J3qfeUaCwcgmU77RM7RubXc4xwi8r6fRVgnz+Q2vZE/C815fCTxiM8j2Ss7f
2Ii/8D7YqlKEtoe2JbolCw5BNzkX9MsGEHJjrcgZGnmfYohzQL5kWA34CFKIxbO9qsFlhlfUo57W
CF0Ozs/wxYW7S+St7eHmHjQXaBBag/CFCnvJUdry/Ihavl6e+kIKNOFGAlAci5udxSc0AAVL37GK
t5aQ5Qh4I7q8l7E490XLc14UAYAGukLcZUjmguE5T2rNUXl/XaWekgHQxgYqtS79vftlqI9fFi7J
9NrpgKm4XwW6tAiHSi7RlpeHeTRDUyjwmrfwzHGkeqXlPd48XKOlEKgsYz7ABglEHvUzba4PSsLE
PWiN/8SVPmgZQKYeL02htcyDemZzElOqh83WhlESLaXM1ssSoYC1u43KgEc5Ova3OHCHrBUmrHm/
GCgZAfdxwAaLeNBIXphZpQTqjPLTkTYQZ7+ettsi6FoxfNYwUxb5Swzpy4AqfjHIN2Z6dbf41w4w
10I1nF+IznM8lUioMmAXydb2sISeji9Iqz3Z6jEz6xXsmhk9G0xcFu3NKIlSyKEQ4UqG4DoKQn5n
34xPgZDBrDIOriseUc1a9tD/HvF49vB78Le7O+xZw3AdM7a+2vAjzjdGHg8MJWuy2gXYogG4I5c5
sBu3p7+N7avTbG3TN9idFzu3vy5IuA13KOIkoOdA2Bpn4QNhkRodftsUq1Rfs3+ys1/3y64S8KCH
eZQaE5V22eRVHVl0/hMM/zCuOznR6kvuplzTl1D8bRtju2FtkHEf1gD5/wjrgzs5JrfZaBCM+1wv
70Sx3DC2vFuUQ6wlWRrCYFlAR4k+S1+Sdsbu0aYSnab81b3ww3vdbG51OzshFtbKjG4TIUy/5eRq
upnT69BO5PA7h5lzeivwE9RKEvojM4L4HPSL079tybBnC3KfE7nlPKnVhut1ny4ZMnOo1SrMgFxy
Y6EOyL+QqyO4t9QLcW5SCDB3iQF97JOfT0usxjLwnI/6OuB/SIwDdpnW7SbBCkRcN8OulIlbZ2Wn
MBmMEccaFkDrHgss3ibKIHne4DvBoyEMo4gCVZ2herDtxHB617XsktJOz3i3Cu9YcwN2XBskhRVw
9U68mxyXyvUqLOeLtmiYiOXaERht+Ceev2sbu6Gi5djQ0jzLWFQFpWtxpRPDDIzlGiayD2OgEEQT
EJJblkFDuFaQv6/NkMF96uDLZfqzuDQVcI7YXR4PbR4ft4gXZWZx+024lY5mtbRQpJkM2cDlfMTO
Bkth54Mj8eay6yMfZhj5aKI/ungm8dV5+i3+3Dwbzcj7YtDlBfVTlFwKJtglCf4gZALQW+rh2Soz
+PLKGXSPhM6qABBBnk1niHZ7YBgcW98fvJTEupojSaZmv5g1rMszSLc0HK/Knfhn1H30LqbETeYY
4cqdftpAU3qXxxjLt0gslWLE7igO+nOLHrgy4OBlGoyuq8ZAA265wq8nh6arTuuF61wdpEvNAzEB
BXoNTvW7S0iieZ4xf9VJMMftwYvlajk9AKcfGpKxBGE/1v+odMz9gNqU64WEF1q5hXUXbe1OH5vE
wgvXzR1hJadzv5B4ZcWIxKgsa6+pNJ+YN9FesA8zIZ21fC9oy//3qwOg2EsX3jJICnvGZgfbkTmE
ssG9JgG9v5aY2aWPFczu74xn5LlBfutA7klegobNA7SJ1VyvHKCQHWDrETmRkenGMajMLmAWEoP7
8KzuuzPP3EZIRqALPF3meoPvA8RIwj0uLwZ6jQtCW1ugby9lLYITwEEVf5eVL3oh8fMO9ZeTGaJX
WyDnrLk2ijro7p0bkZrcx5KToaMFczQcS8/jbJpdNiniX4DJlRK+RXwGgpR7Q4BH+Wfa/R/kxRZf
FG0+NQ3XHurH++7RX0yrmUzLGViWGSBn+kMDpNR9H/+b3XHjZqi0xYQWh0s6BCxVXgeOe8aNihO/
l3bWoWIdyRDT7/cyKFDQU0vwajVqn6IkRlCJ8PE+U1SxWVFurWUZdphINyXZdVo/O0WzKlBKuf0x
ESEc3OnLOP8tCpSricP8BOazD50BZSteud5OkzU3S49pw97vsbkJEjNfN25Y8E/BE+0sEytznoH2
kF4v77nASiIpXf+QkjjYfkpsrB1nd2IyRPt0u+CtVaqy8BLOFRL20DTKxG1r/ZiLHXcwbep7SeQu
3/DJa4Xu/BeN8q7Nbx0uUf6rggvq8TUBEFVAZrXb9QJtSopl7WVk1eWUI83mclqtewsK3NLxiOCg
8/5fpbslOjHmNGMYZvcM0YgzF8/sgFf8rUq7e8xBjT4jRkwg238ep1kLnKPyo2h/USTXLDZFGhbf
6aPBbbbAoaFw7+ChxYTn3wldQEIwrZMdFQrpmK/5GU6Xd5Pm68IVkfyVpq4af9LuJx7uV8Dc/TWn
Vke+N29teqB80/ILJW447mOMoPB1iqEioCo4AoA/L5VJ7FrW+TiLTD+/5TQxz/6cIVGFj78lOpgN
GiOdAr/769XDL7OahA15CMQSmVueYgd9gDfYDHaHTzDUBEmTmndBK6/zWkMUMfNJy78iq3wvfZus
urJ7uYV8qshR0D8/Zf1lvbTYzVIDsKaHQUGTugThv8bu2J/8Urc/vikdU9uypeSD0XGCcF1bNVqj
HdB2BDZOse4KMlJZMTqEdwliz9BovCmP2CFD6l1NaiRMhNilszK27KxUL9u7b2LnSeXGFDn3F0Dt
PK9DJ12lLRcJDl5A/AtsncOiDQLjhmzWbGcU5hPv8NCV9xOcksqJov4++ypb1NvdDcZ1ta0n6zDy
jTzbvpdWqoO8x5d2kIDtPCvLMIqLlVPLWRyzU1xIt2Z4XwLX+WbpQGBK3YJnFFkvD2UizPhJsDJO
DZ7fc+k9dWP643V43yZUe6HemTRD5fc/V+NxZUNAIlQdxJHzPdT8GNeMvc3JRn9Uyqd4dS1eyas9
oZsrvYlVHvwtYfgp1zTkMxaN7PPlDceKI4kto+NDd2kkdvFAINj9ETzT2EF510Nu9p74Zi0IgT0g
nBOkVkuu0UFcgT8Ohr8gW62BwpvAazFer2YawwrnEUy1y7HSwHbxaWQltUselKZ9w3BqKiLDfZce
Pt6dZQChrzE8I1Y0XxWwOj1XNpajf9HHTY3gHzS6LLJGgmOj201nDis8bei5nTNTUeZbeL8mg1Ym
z6PdO/ikB++2RqMYGfXWruhLd6sGwIajGY1GMQNEkUacX5rsBeB1syWORHPDqlKMSMpv+PjJHR9z
sS6wcmVhRS1REvkAV8J4HWduOgcHFN5dwhIHBM+f8LvJD2RYxLvQ8KQpXcPTkuzH/xZLhsWSwfVn
znRomWmp+7E/tkH3lh4Wu0mfkSiTihwhmfpG7XmeaNq/MGpywvHdjvy0MTslc/B9xfHqcarXyLo6
sMRAoJt9FywezHvGSxVhF+NbN+7pXuTPmIKD322YZlFevwDS8gTRp88tx5FmHeZcSctPYXA6qd4Z
BFFxDVALMdv9a8Ki74P6t+9HTGw0xTvGfl3L09BYDxY4du9kR3eGVtvhdVFjfGrdJmHS126ZN1p6
wfH7njvYAzi/gEkxKpze/7MizDT9xORKjHn0cHJPrUh+LQGNXx7fxP1aKnWzL+6Mb2C9oVm1CYK+
b7Qrq/C7M4g8EGZBtQ2MKncqamrKZKZ3cg0DPZYoeKtqyp6C5/JDTHRbal40S5+e27Im18PKE7xC
K2ZPmx8fC+2JFkw5VXi53vlEbQjUJpVKmlbxZWt7ReLL8ybeDeuS0UgHWVkYDzlOjT7e9d68S9ld
Pvz/8XK7RANBoAr5lzTc/EbH3DxVYC4ZYJfBZoCN5DJ2Z9AktEsKfnqRaEs9btRhulPX3FXp4AW4
bu1fltjvUYN+HJ5Z9cBZpQYv8Bk5Urh1EFkoBBfCXpwzliiJEnyIF+nqgSkNkuQQFTV/YWBlGK8F
mPJ7P3a2t0EkNc8mrq2H+8bRYE+PUEYm66EuoGtS2h4XUbHkMTyML+xUDifkwK0OOV58lF5wSdsi
UOETGxsM9wBsV+957eZ2E5QQrO90U1GadWW+qxt2HKy2s/EMr7Xh70UTQAR+cfSKVTzwyJgQABiU
oh07jFYxJHKEHL3f79CKmHCBi0JWLVxCkLmXGpImSQPBGVbQ5ml19xRt2Me7EdjcyXfAV7jiCMpC
yWAfxNdVOwisdKOmspW5k0zbmmKcmUOlJxs5FMz6FgwLPIiwGTYJrlMJy4C0HwbF1jz3k17QrL9E
K1f+m/BN37MdDgKDl6Xi6BvWz9CgDYVBe+gik6SNYr7QW0RZ8H3ZOyd1LV7tLHgETYe5Gwj4nFod
8ezknuyYOwtPxAISbyieqBj5MeRAHCYsLYumO2qyX1FdWEMO6CbB+ZWNH/F1ZjuREeZeXFaae3XD
egp2UPkTTx69FTKS1WWO5u6HKD4q8HkUFzPT5eX4Lvx9OWRvrD0hmpsIIT1sesrIDudzON+44LM6
xRvpHBOWM9RBrsYDQ1l3eLArTR9HvOJxUxvwOoERJqDlylji7vXgT5uw8Zimc971hfz1qJ/UpmGh
K2RVZaNEWX5RwUmxLXJwQo+MeaUHiHChNjcfCg1YczFsCbvx//PLSSXK+N5lQgjHnquj8If1BJQX
oEZywwf7iiUNOVoQkQd4iP14lJ+Lf/IceiumqePqfaHF+co07LtaMhB0j0HkmrjEoaUP7s2/kKwG
hYXcOik/x2tC2V3UtHK+p1sA9q7603fB5U4/uQTA/FAG5L2oDr9NH6tI3MWA8guWTbLWYR1I0Gks
8BxdwOrw0cNpFLCdMu7dyNnCnJN0CEFQcO2v/oITm/mL7aoL/DN/+WRbIwrXkN/Vr6Fr13ed2bqL
+b7s6LYcsv0Gk3vyiBxX1M6AiyROnnVQkfa/szT5hOjejfltriaqVD/+9ySMCr5ZnOYYJwvUFYIA
Eail0BdhDQg1ATjNt1usCxtQNW4MhVEL7v65BGCaJvPVKWwtyF/xbvAaz2dAp09awdXNFFlaJe0p
pCt6aw/Hu8vHU+UlMwwy9I2qt9oPqQDmCmf/7u7rGtw+2vXnoIESyYc3jmJKzvynR/5/5Aun+BEU
j7Aql5igNvBzprmryhKAv1oX8ltDmpCpB6zsz7P3ShO27LOV1fuemmysCazhRZL56vT8rNm3wrUe
zLWq1g1s/VAZ2jJo7l9kydrx036Ioj9rNRC+Ukrv+LGWySPHL0mrU7ugJGLgzcL64CopLoJJOXWN
erD+/XhyOJ/ehZpweWU5O9xjeGom/RRfhIiAOZl/nFl+ja0C2kTbNKgryAUU4E1jcU7C9NkJpaWL
XJE1iXfC7MvwetZ11MEXxApCBx/bc6WYgE40NyR+E15Zl1T5UKbwxRgoGUYtIxoKt+PSh0yY6l7g
GtgXypIb6rzhQ0OtfcLijExuu87ZNLOSvsC21qh+PFMlk2S5knOBqu+mWQiOaOvwVXTHfCUatcQ3
N6fJk+gIYZnfVdL7CuukuKSFrG8qLpzHExnLds8ayM1bY/Ci+zSLDtT9rkh17kB2W3hQ17sT4nj9
x8kmOlAQx0hqY+gyFiqhb3Pg6xYMf3Jw0tfidPb5OvfpZhq7OSo6YzQfyIoazHyPgVd//6sji9EL
0miPnj9kscDmezrFOfh56BK+BqwCEAj/Wr2YjKV3Dw0cui2rqBuPnApf8Sf613dxQymr79RDrgja
/Oiw//uTrWw+a5mmNeWy6ZU8ELX1ZLSp9x+XOYkGePlMvKZlgYs2aRYxar+OMMq0kMcNppZKIBeT
G9Tc7XvN0OF2Ms6oR1AZHx9FORn80YSAznt6AjoLhoyNPM3MjwuANda9J6SouaRfF4NgJEvnZitv
I4B4Riornn6C3LMnXA+v9959w1yuZudLMgYN0C5EFd9eyd5QuxoI3wf6VPMZWnSEUElSgQAikbNO
U4QBy9L1cCWn2y5tEZ7se1rVhcyeaHmKRriO3iEsFrbiI0RucOdzyxCP5f/D8q0CrobRJCw7DzZD
tvm58YGHjNf3OaESI62jE4HoiVUHHMfC5FNt1xDBQzuQlwZ1MVxidJm20bw/m01iOTvvKk91cRBA
POsZ+bVDIbjynRactTI2qlsLZjjPHlxiTWUUWuOfY7FWpSkFbi9XQf/BEEUR8/o55Mo8VohwTa4d
6QkZHZF6ZIti8aB+ysKu/pCyEpuZ78zC4gb7GALoK3jV0g4Quee3LiVFYLuwWgd5ssBxpBfdoHqe
8kp7yCa8Nvb0PrxEKsOHiDtpCRayTvs4/Jlm0lItGE9gORYsuT4ZSXYO8SGtgh6NRt/Pb2B/szOo
wX4oDJg7USVAIhVHku/Yu4SmhQvpEbRw5njBTjUhMduZD1uKoexZdJYoZWP0SKH8bZVLnG3wi/6n
JBqyz3Ah9aeeVAIR0q7sHHCA1+4MAEGbTva4m2qyuslKc/zQBQNxDsJGDMnZjoAyU5JMWecS7ji3
w6mFNdbyy66n94VCROY2hMi9/mSaHsIEXgzTE8Y03Vt1flQ8V3uzMHKLGZMRwyy+tARcXfg1aDkV
KM974rElmQg8ePCHJCz9PdKXUW6f724Fu/K/hGX9Yg4IX5CDFJHGgq0ft5W1Dp8N7rqm4jI3tDl/
CDpdesQcOwt98g5w/NQH/o02uz779J3Yqkam2QEqrOuLXTYwUW2kAWyw/9z9eS3PFm57u/cOcsDi
7mSR8DrnLRndp56Wi946j9hRnS6W/haL67MlFGgQzpnKLtbDAFZ8Ox5+wRBdDNs7MMF0ozOw+KDk
04W6RCJ7L4KirbgWcVZIx5Xm1mQRwHAIXLkQ46dUqGufJpRglpQJBP6q1grWAQCnTs+ffYdzKcw/
7ZPuvKMT9eQIdFRmrtzvWftzz3ajWz67Qlxh+Egk6BxZckyWrD3uIpND4IWE5lw0+mnokcqZ2lfC
SCkBa5ZFFhlNN7Du69LGcdGwuhZbT70knxp89ZhzwSwukZ7IYyogPcGaG94HJYKlNUOXk/AsHC4Z
bTAfcSbZaanc4MivrkEb76/Twu2rE9PDxQaIOjqnf3VhQgdtwLTvtg59MsQcl+0tYQWYd3JcLYee
teC7cO4yNz9mL6+enzdxksiH8bBP1l+9zZO8silOXji6F1PfjTe4dtzjeNk2jYjtp87f7geK4Z1A
Ha3UdPSJ5en43TkiLtoYXtmVwOKrI1bKdzYeKtHMU9+MnkFU19ZQYZjHvOFygOrWsrowXpONIMOn
cjepQJKHFbaC7EAU1iBhgof/Y10eR6v7ZMbewh+mRzf/PyaLlV7JZqnRpdu4pPjIoMmOpKhypIch
t7bx+2115m+lRY4wSfS902EfpaJKyfDdv5DiVOAo+nzI6bfFsaQOg4aYyHmPLi38QsBdILhdayli
KsbhM0IAQp7c14NiKfPKeUI14Q5d+35gX330NSBTUqDCXIQNWFs0HZ4dUVhbK/9LcUGGsE3PvzrL
RXjp53XpnlihW1tSE5wWcfEF0cqwVwmpbAY1rxeRqiG0A6uT2laDfBlRzPDDHnTqFGpzshpHXX3X
i/bjvP5xbnv/WfnMsJnRikndNgK3yI/xENpxEf9oLHnOnK5Im/IB0MAEJ2/Zpnofx+0HrfvRAjdt
zkfV8BiGfmko4Zv+ZNKyCieVTCihJWzDvUUKpVfYvZUMIlFvji0Syuc/VhzjUznqaKahw5JIZ4wk
Jr+ovUxgdiw7uQD9h4qENLwtgIzTpS1inj/wKr+82Axe1fiRRUxf1T0OxmzMG3C3OUlpbOR5DvZJ
TAh/1Og2yjOsJJnqHF6WaNF9+QA3hf2CPhnJ+t0NxXl0qqjtmBqeT1sIu1GnJ/UtZE6EMmW17kXQ
wZVfD6h+gZYqxEVwYTASPUhgue6cVnW+qOVHJPfXfY1sAivKADWI9h8LA1MBF3lf2a5ZtIFfSxfj
WHS2ylaqqHjz/KZJXXt1Jt37nYGuhLIU+HLkDoLTe5VVrbEc6gHyGx2g1TjtlaMPolCoZ2RFwMAu
Ej0R4HSxpffxU6bisqjVaPTIKV7wOiwUfVhvoT1BrK1/JwZ7i8b35BtM/DOowF4sfO5stlP/p+iG
zhqGYHjL08Idu4N6nk6FuYLG8DY2Kbb0JWQqABxAuctFa50wonvDRIET/YqQwrUKHmf/ySvPZ2y9
wYv6GkHAWZIBIHwpNPl4Dx/ja4HWAaQRFz/hRWVIgylkGdbLz50oYsL7Xxq/YGVNlhOuu2TKI8hS
D8UvWORrVJ+mCK2J4k6BzifhsY9mYAkeeTev4YaQMhInF0VGzkiH94PKsoiiBQUcM21vIMAPjWNm
9ZYEpXw5aazCN2vtJvqQCzQkdztopHsBuAZMPClYb4VupKKr73uSDXPNc09sn5kWJDchJFeNdo7e
61zbO0Dyf6a4jVbsIrchM09funu3re4gRsFw105yipdhnuyx1NnMBlNYJSKNV+ZpuBZWK4iiLM8S
zK6AkblJDWBPleWijxuV28YruyL6J7Jf1HQuuPCX2p6vrgqImABOXMlsnGlYvtK3hAoDbBvq1bBk
i5r6PS04T9OXc19wHVxcxdBvXPdcWVBZAdAnlY/S8KrWnycFSW7HF6oBrd/uM8jqqwKb6gJrIisb
ouIK+fhXYsxjc7tgXRqHN4L9h3IIV2s45t9sqBtqh6Onh8oOOwdR+BLjMH677FJSPmNyiSRXpoxi
9Jq4sh5rpDrkqrfp57N7NRfct4fULJKv85S5Y+4U85cFkSxzjehsW1NTy59zjFVs4WN0QK4Lwy71
fLDtRty6NRrF8qTGJmaPJ4WW6sR5c+ivZbAn8yG2sxm5n/bwHZU0Sf334D0OAUxnTH3apLYmHWUL
P8kI958OvRQ9hyUFdmhgg+3Lk+cv9Su2CiS4Qqc6eJ1z5wYL0/BQ+KPwQHu4RdmPTiVFh+k0+OaW
P/IAay6lB2Jbi9EISI2VRLSVS7rBcxzdxPJesu29zIzVmvAOsVFmiY9d5nfaZTrmZ4ZMSk9IBgzo
3wXQs6QspajWSXVtU60y4RIkpjmPgxSRAcodYizUyzxAJNTvwMyrv90flfYZUK1d89u6kKeH6TSq
dKK8UmRRA4eqXPNoNYNgOclx75bYXfCm3lbT7RB/T6HEB0VfG5Qz1tMFyTlaanSZYaMlFDThno6T
PSybSWBPdkLyEal42t/xWOO39FMOlWRo379fOOFYIlWKI/HEdM7Tygaai9OJGbGJKVZqGa+Y1XuG
eE5IWa6goJiNH0wgG+0lND6pKwEmu0TQrP65tKu+OXOXRDJSBIW+6C/dCGG70/+FmJROXh7ACb81
zdZ5s15LJDUP9aH0EaiCFpARyYKLh10EH11yWiIOOQfB4VyIgTyJjRFm5IzsovjuUnwGIYqCa6JJ
rYOA5vdend5M691bkMzpiSodmV02cLOyaFTERBrmNZOnKbdyHvRC3alby8UQymSaR10+B3PbPsWj
fqo0TjnLDXyS3P6aJYTHN6WFacxatXjfrhRCu10RnB1+uxdyTudHgCOhxOD1EXg9ZVaTLGeemfDa
2Q/yW2THA+wtez7Y8IFWqT5vekscXldkUhdU0Y2eOYTyFVogyFBHtrRVCN1LM9h5TqNQZCDO/7TG
HwV/uJT4BdvsVC3cAUXPUR3dk5Qen64EOFiqNL0p7BKDYe7/4FM0BpV9ev4p+/CEUDOx7Jrs9VGN
hf6hJfuyE7sj9BWxVWqn6sGCwP/OHJkAxkkudlOJCWNqWT3L6/h60LhKIaMrIExsEZj7D96OFATn
UZw0vTsUJLaZ8SfVZ+BCMvkBuqsgkVHg4elnqinESt5FJeyvwjPVnn771d902t/Ta/DfARdtQC1B
7+2iEjZqLu+3ZhAloZ7Wqg9lvM5FHfxJyL/10z/XE94MjQIO0bRePGWyekQG5ZYal/Q71al2OXG/
BegstowdasHFEZ24pYICBwhCR3evCKgmbJsFLNEUPCOxqqhUp7/SO7hxjCaUTPJJRV9WWR7nvUgR
WKh12AHj2sdaqCJtUVupNDq7HLbjSIXliRH69RcsNtKlANRhL8e2ly90Pd918Cr4SNzr4nNtonYr
DBKkCC6LTQb2D6aGvh6vucIBXVHD7iBWAlj56umv6Q1RXCI6j12OQIkaa8ZVslxDgIRxY0QPv/fd
zCU1hFnK8LZsmJdup7jZhDd32vEWlTkKX7eaY+3rHhgPAAjcm8kAA1NTwk4OblfHyNmom4iJnpHo
r1/UjaBKFGoAzJ6G3OJDmWjTl5YA6xhawptDlluaDUd/8lthG89OqMORwa9TVXJHYi76oTLwhK7A
k9xj2DWSakQQ/Z8qnmKypd3Qe1FxEP2w032bw9ME8BC2i1IkATsPII1zH2P6YVkqQw+e4DWScMqH
y4jnVLlOpQO1CrNDIxncItuHlTJgXpBq3PTkJxXpO1z5eS6d3oN4y9go7zIk3cbOcsMCZYuVptFM
zYVIV0HomhoAcaWiU6vgUvllFdwVsObXB/xeH4f7dZCpIFDlXqQrJYE9NLKpwgNyWYTlrj6thqkC
B7SU0cNIcyLpH1YGcY2oWL6ogBbWxENlEWWbhk8YVTzchLSTSd2IvtJVJkOn3sTYJZd4z2S10QBe
py6cP5MW+REvy5+ev8vlzqnB+NDLwpYhL3eAiQ5u0qX7XiJHcjfGREAOvuW45YXemwx552uHeaNm
p2xB6S/SGmvhJi7w7QY8J//wbfbIDyLkW8bKteSD9Wba5YaT5FXz3HSzLh+qj341U3sXyW8UuWd4
65zKGLq3TFEKE1ltPisCFQTLe7OV3v35yiuQ0T7upkN7WCBSrBiEa6S43O6EaMlNjGArQNRZseyK
v0EgPazy+CGMIShO/FKu0S3yM4JWGC2ndwSbtNgr66rQU4l/sboViUISZdKf1vTerTf6MdjFod74
P6+SuRjoLToCbO67hUXPK02Q8gNJhj0lHQlZ96gf03B+gHlblzslHZISxfcjpYZEqma2+wBFVRAe
fT/VfpVRCfuMCeWDCTsRFUrHXZneU67IWrOsaVOIt1qe7oS7VIq0Rf8S8N19joExLxpNEDE7Q9kT
pQTQhj8slIibne0ZBfESjvc4U9Ja4NFD7VqcRsVPN70ug9UKipAJ4otwii8+UAhoRODkcSEo3R1W
Bm6EpRgjKsPWpb+V2plyMv6pkbucTFBYbC4FBnln4F9GAywqVtuES1PEKRES0ergv7/5XDL8olV1
II1oOpZfpvt6PaNNpzqOUSolJgwGyF4jiHJ72qicNrfIMvFX7lAzr9vmABEuYC7DywcyRc+myOqB
Ve/ZXXcOESBD/VeWxMpuXqqsw/RfsIXP3RaW/asEIVrqp0E4it8q1eX/cJXa+2jAasa+HriCRy5k
IBNviaQKNiy8goE7Za9JsWfRbmAoCl4ixFYcB8KP9Z4JmfDBipN2W5JzO/AjXDUjyRu11o8AP0A4
z4K+4UVMk9TyMt2lU3p4UpN76Wa3SKgztcPZpkNRHatIEbRXGvl0SLngPwhPNm3GNRbowQNUNYGt
JZ6KZkLolGNuqPQdsrRtKHtUMBJe0XL6VM+Ie/0ZFkidnhsw1DGI0M5zwhPttm+pncJ/BaP3ADoC
4EQ7GX4S3Y7cCEkWMpS7nrxWzmPYhU3++mxkAxZ/TgJKmp1LIfIM66Qr3r7aSSR6hCum4Yqp3Bmf
0OqikGZiYzp7jrydQk76N4ukcvHmTwx1+a45PuuIgY6PtXL/UZBIG17KZm0HrMBDpPZQ3CqDaKlb
jPphBXLhmG08Gg/fGNcabwbY1Uj2GRzQKEa16XBxbCbjfgZNwusjcy5ubhy0hxjv4kxRaqu6EcwF
7JrNFZ6wKdlbgRoMmiIxuG/eAMwwfDitpUoJTzOmU99m/X9PdRYQjGAJbyhsuiY1iG0Sw1EM9NnR
J3g21fHOZDq0t+qQrA9EbGdbFvJmsue9IBhggy8tTEAOjM/TCVzXyhhsqFAygiZQfxdds8Ky3r99
wanhc1RvmxHEILM8znAQly48RtPDQsCJH0x/XbBOqryxrX0d4863JvodgpQvgWovi5BqD8BD4m21
ipwmGLHUWhiGG4lS/2Y7YR7Adw+Nbe6NoNjvXWl9yKAH2a3bq+V/Lun/qE2znlikjgpymEiRQOPp
7Ft8GIdJ32eff50734nxOoCIC3Q0TzmDDasSR3Td1W1WT5MAX6HyyYuCpku8pFf7cMWP7T0lruuX
/DmLrThooYG8jYp92flqfbIVbCtkPkz9snTctW5YFf2Hl8TxgsynYhoDXnnKU4Fc7/+59SiLDpp0
vWto/B1pwJoQO2BRRQ9W8sFE7+gwjRhY/ZdJRqQdGW2KzOhdu4CPYYutyw88ULOfmfJWzTqKZgS9
78GxBfuLVXSqdWc9uGAu4QTMkvCMkc6cxxXfhSqVhknf+s3xN2ezu2hg4s/t+egGDI/QH1Rkcrce
CNd1+KhMGqg9alPleyK0UOb02j+eRxuHe9+QdlgJw3i0e5H74XteSttO9EpgB9RcexC0Pta8r2Zy
xnPcnvZd5oPTsmqnv1gULUgC8DT7jYk+Is2rICNooPmr/ttGZ89w1lhZRY2XF1sB7cIFZ05YLT0h
6w8UOWb8bCeRHVFtd0oBmgWhuzxvBOXLEE6AZ2PezwIJotf3bcL64r5bC1e6gIvHfzlLmNeVFaZu
8KE8sqBvfATxwmm/8yD2x8phu/0oKRnbXVGVJM/yhVpegm5vu2knzwRUdSPXajGQTfpPMmvUnsM0
9sMcdaQz0jI6b5TtVYEYttXe1+N62CTCE34RipGxCdylXExDh+1kRHCyZ7IpDhqOeZuIDrbJSrNF
+BE5WazQDyvUIpV41hHWj6gi6im7Ig937YV0qTvRwJR4ylm3Ecck5X10jmfE1e1zMjp8WZ2awTNS
qzvIWN3o0j7lvyoQ3ce5wu0nUR6gLHk9/aAo22u6QZoFILG5Wq94Aul/rl319JrPfps+m3otbGCs
rUEhsU1Mw7ctUVlZ5NLw/ZTRM3CAMBJzG1+PtEeQ5MNiSnBMTAk6qBTGl1oAoNOIypO28xqafNvk
e0InSbeiN03miamd2ClGIGveyagT2ZSJjAzx+mOy13KUleeMSRbBfDmXS/oMGTPM7HnMOMH6i994
hjg9i9X2oOeemDgIlDZniysrci45BHcL8KjTkQ7SWfnH0xzSo+gdaJDEr8m91Axvb/nEUB4wIFKV
7swuvkkiHhnFKALNCoALF/7ULoTXGunMl0HgIze2ekfY2pkwTKhpRlJmXgzZHE4Nk8BzcgS38gTN
KXtmLdBYevJEbSW+GGD31cZyX3KOmYTbDRiAHsvdX9nG4El+FK1UxvXqyVfesAsI9YaOb8PFvnSe
u9sDa7wVic9eq6iadcTtYwXqltamZiESrKxR1YxevT7h9Bf5U0Lcb/VRlixxG3tMTmsFwQD3SJM4
p7bot9ygzCW04rMSyglM6ZSI75USV+opk2nOJVtWhpAIM+YUKrYB0Ax7l8nS4BWARmsQVBJXVrHc
esOKWdlhCnxEDYPSV4WjOY7QqjeL4GYakylSmRD50nrcUJpl4ZkBM+vswbmaN2QxMsboMl5tWZcE
EJYtxWrwbLIQLvuQTiLDw4IVHk/tn3UOtNyXaFirETmq9hJjW5ZjnEKHJTMlBDISEqUgIXnhCmT7
eE8imeoXYOTgPkOmFKAIB/4BYRU3hr83wUCcT56RjDHKy4fKjDtmQf+9Z7fL6WwQ3uKd8aAtRCov
f6mGUttbOAxfBDxvSgF3STNPN3oSh2k+IBx5uQuJBf7NLqJHtmng9YMQAnCtjVFuXEACc3osRxUB
RCtCvpbYdEYv1mIXHZkqYTfWYkFrTL6CbB3IZEGVgQKHBvtkZ9aLXJ0iyVi4/m7hvLAaNfnpEeWJ
JCYEdrp5fejhcmclSHTw5zfaKEPTWWTEHMREsCmS8wI+fCG+kanj5mr4Au90IvM6Rup8KrtnIwds
G6PAdISaktNTFhebYD0Zw4kzru7gHVsqiPN3o2pUUF4LKM5zfpJHQHVoiGWbmB8N3XNByIqN+i+X
iRbwEqCB+P3u+FIsJoUDvpJk9G8yYz/bW/tBA7kb4q8KhNXBNT1Xcp1M/+vhWFybeif9PiF6sKB9
JVI2nduUe1Riw4b8Ffioc2PZ3Ioe2UF8aWH/tCDDHPo4WDkO2E9pKM5tNUhd9i3sIaqmJLOSrxeJ
tX9tei7npTfgY3aTZEgNR7mzPB50+LqAmmVEe7IQZF+Wiwb+Hx9taGFjwxl5iGu3BIfR1xgcRZBa
0fepHECJ91jHsbYM6ZCxBfwvgE50FvLQkh+WrRJNA8iB5syD8u+p/cp+s69ki5RxaI2EjEXEG0a2
grrxr9Pg2BtpmbZyyqRmJhqtJVbmAdbXi1ZKeZMWMWq6xfU1YF3NWZ3JHTWWVN7tpFus2FJ/eZu+
9Tlp1yo3AVhrwO/KnfuZP5W7itTKGMQlNLtmtS1zRa6/ReniuiPb0RSquL0QOxCcorLSBeqyMhoU
z7yHKjoASz2GFDtAm1V65aCP4nZNe0IHkBBVDaI5atebQnaspNdIyLCP2zrRpvwKMwZzAOIlVwiL
icA2cPTcJnQPNg1oW3OuHCejWHFO2HVE2ddujbFIKhZFe+ymG8C+y/unedDFGurQRbhhTu0vGOFG
T7qJP/1aXRU+JA1xU5w0CEG9q0ymRnFjmMj/YQQEQDXFDqddsO5egm+KMZR6i8n1C0UhO+FlRZ4w
04ImprSTUHTBCpVgwC9fy863U4ZP4gJp2IajNNoDtvL1mtcJrMYVUWDMzQLQam7ll6lgBsrjGQas
kwgeO4HRtG7nqqmXHmebaj1vnEFhuiyuP3watj9zOfwjepwE3aeXaE7bl6rcLxST9hkGhAuREXbH
rsu7X8t9knlJGHLVz6yHuvzj+7QECAKvhKop9SyRx/FB04m8UJvYsNQ0a5hr//dXTen7yPmXtCX1
StoGfE52R0bX8mfxAzlZ/3j7g2M+1hQmzUXze7t7GbX3AM/2M9hDwoRBYZtsKRlbtBvUnyFvsVat
EY2hpYAHfn7H3rrSj4FmfZpemrVp5pnJT6Xu4QHl55VENUtggMCWmcaiDgwGBruoU0ih2wpB2bSH
c4RuKsPd7BTac/xLWzimJNm4TZVjykd96ZOeAjc79sDJ2QXDTv8nk+CNxprMdbGFaKYc9MKAMLaW
Leh482q56bHqCawDbTNJIbn2x52ve9ATyKE33e401ygDoTIVyuW00lMq461mLWL5rOTJ3Lryn7M0
W1f5u1g2OJBy10SiOarHqE3oGgOIavV1cUKeU4QfIKLSiESaZfYE49Fae4PbjrH8gcrmvdtrTqMx
5zPPD2dKsjuXyYVV79Hiw2JkqUKfr/Tc7XDaXgzqedf2C2Mz23Lqrw5r/VH47TCqLNCsedfIHRSN
46Q5r3QBf8hM2hNjmM3jiuz7u6IngiWC78Z8pNRM16ViUmsuwKhV6yo6o9p8Grlmimci+PVPfDXv
LqGpDKk4Z2v7UqigaZzIEpgz3zyjgnJRUIeOliqA3jDDPSxcbaizXdW+lQUdysvPQGvXNkuy+ZQB
OsD0yFyI4tGVSPrce2oUswSIMrNL60OebEzuCXspeimX14BoxnGF/hKdQswmcoj6KNXanOA5V2Fx
n6LrfA6IXt6+H0dboNh0oV+3xlqn5BzVwRdmXH+qTTHNmp0llW4w4h2kQCU0ZL7t9AwPuJadUgsO
DHTH+QS2Ht9X1jFbrgHaTFlVjSThba+G+qK/jaPyxzxRGUvid5JtJuMhZrYq+PA3QtLbKs2BAiu6
l/7c4YO3PvF93GGA8a+GvC2Zz5Y0ja0adWG6PZEPlNk48Y/esLoBMmV9FNmsvNd9DISwdfsIYpYC
yMRQK2DQe3eZmhDYPlDESRGIJLo+mS6M4j46jF4d42UvPYHrtdir9nNUqsS4HzMJ8wN2412jvp3t
xVaYzoPtKQVBFpsPhqs0U3nOYQqRzXF7bgDiKfO+pxhFFO63Q1jQuqw/SaZHO7wVUnR2A1peu0Ds
rid6lvJs1pFq8u5Vr73ybBfZZ9FPNXeHjbGHcy8Hlg4d7UAHMaQT28vp6H7i9keKEG26kbBW/rGM
NbqVAi0o9Wr5HVkyNhuo0yyaumGVqoxCbg7CFFUhE2iFhW2Ikf6c6OKI0z2JytazfAjdJ11EhIbJ
2CqkR9N4x83MSn62Ujut7jJFin81BoKdo8vFCtPuioKWFJE4kArAeOtlSDionE3YD1qu2vLLR1OS
ORZTok7s+1AVHZ5dq7oYB6cqYTPRbIY417oqdFyD5V0OFknGPhlEPzdhsO9TzhoBoFIunKHKOLxD
sStOGnHUk3TSuaYaeeInQEY62gkbqVYtr0bQ6IKWvGiaWhuwFgqYTwLWcn9q2tBx2ujVwpnpbM/M
M7XAPoIEiw2D137tSNk2VrZwMdxLOsxiKsmziwSW9ss1v+19TopeRnCNvRvOOzLN4VhlCuR3qlo5
bp1veFY8lVUdAU2XVShl7lHUeiwi/tPYBkTsIUMOl3AGpp6+JE4kjn5yOx998OgBQgxuhUxEdiF4
h+WEV4LJov9KHMCvZdilcC0EgNTYm6u+9FdlIrxJr70SFS2MNDbdJ086Rmynb+kY648Fs2ZeIB13
V5HyPTwY9QOaECgEbpKi+D32iMb+rALTCq09+ErhTuiY2zrYN5/A3gK0tJa4T/ER5oRsQhp3cNuj
BXBJM680KXJhjvu1S6CsM6V4HJRoa4Fh+GCf3tR/fkPObTRWgOgAIphWkdakQ1oVaIjltg4zREuh
WqInDT2RU5zF9iE+MXAOGc/SAGjT+YUGXPmoqW1hPHBMA6nHK/tEBLY7qvtXRVse4FrZ/FCvzshA
evADpgmfczCkQ9d7L+OB+Zgw13xN1Zo+0Mn8Ao1F4OHQ1cEIt+Pu6LcSuAc8IKM0N3s65NdsBGy6
MkfG5lXnBgKgo0+hR25w+Oew72fn4Cd5Z5PQt+gZJ1IHfDdJ9WtwWuJ/HQFkG729SmEg4x6++lOM
tyHucF+58WrrrdZbn+bPod7tAq19ZuCJ4x8a42PO8JaRIoVSi5YxbNZS3rUIOnYRlTHi5RlxAKX9
Y0nAN4UhNUDZBqu33laDEIsHB146/r+jWjZaWFLUN1qRstkJJhdfblHunPOhxg+SVCpE21LY6lgG
fnnVtYC6ACzclwzLc1LDLlzeoaf9fVEkltl176TDHhwi85lpv9Pg2XPm1p+ZdUMDMowIFD8bAPti
ImhENCYf/diYjbRAabVPUP1fQ0Eysi81jtcXjrWAqT8rFiRriUivGmyPE3aQM8opZukylw03EcA4
W1vHOcYCSz4Y49ckF7IGGFcC6lZu5vIV9zyIHwPVp4KiH63uG3imHQgG1yVPC7XA/SpG3FaXcKQk
2bwPhislX/ZZVtBuACW5M1vLMOaTmc1SoiuuyGFZBWP/Z3AsML9BLPUQXSQGfym5lcIuKa50ks7f
jpj0ai3MaZ/QouR5zQZd7hFOOzdfHtSUD7yos+STI86KWYyUhQYGJvmJSCVFluEMZkaJE5qYq9w4
IY3pj4zgsN0YSZ5hJcDv0+/S1oU1qa9qmZh93G+WV+lhRWUVldz12w1oGcHaUnMqcQxuJd0DLPrD
ydsFxXwxEleKPGL1LCuQljOkqmZEFPxSy6a6eIS+DYXBPe3CFITDy0b8YNoPAx6bIUcVgV70nx/T
hO6EfnWjIX5v2MCIB88VxBqA/qbPoCepRVuJhYYHGzchADfeSOtyZI7PWl4WMwaefH8G6eg865Vq
ZLkdFQagqB8Q7JPXMbZ4a5Df8g8Q69rSIWknDiJ9EzzcofBliSR/lOSp9Ste95VP0Amc9dYWfTAh
acItiqVMu+ROdhLfU5pUQXuAKwJgYhSSaP2+UwfE5tdlVvbV5EfMZ/92bTa6zNE72mFffruX+B27
ALFgBpRCN18SfkYppHl2m9owIRa9qYiSDBrGXscmgO2aSgOAruYbS0ZEfcIAiPhwHBHi3UKLw1TP
npZmy70hj9THk6az5OQOpbDA3oUU8v8qUh5hPfMCqiW14xDRpBjoH76fY8qmOUG9DCGGoVD/4rCF
va4hxdhRLZ/q8GMD1drZWd7swZsq6g3eqvi/+Uv4XADjZ6CYtHhJrou78qzELtK/DpUI4MxvE18p
91VQ7RimBS7GiKWRzRVw5XKJK+9UQ+BUyPYgBcJG6F4BZZy+RgDO3pDLghPfQPcSxUaj/R9q9JFn
SIXwkmvZZArl2RC0IHywfG99jfXVFeBz5xEziy0scKHj4FtJcG7LPerghs9+Sas4kWSTh9QZNgkP
YnlPWUyhQFzfFlSseDRHjgK/T6wQY+5h26T5V/YIdGurvnGnj9YGBOeKRsZlcz9NRbQuZzYePc08
feSr7ue5dFytqG7VO1GN+DG3CpeRTy2qETx4a5zPuR1B3sdPibTcPBqoB4290RVmQFuuFLIVrymb
4Is6zrzDn22n0ts1DCSuuNQzHTd4EzPTPe0MlQFFRz//r4ZWs49XGDDn1pFNHmNTw9bDaQJWvcZP
V4LVpy6HOCYexHx7jkd0YCAOMDaq+bNPABf8f1/dZkoCw8xVVqVjJcOwmiuUwbDgXZQidi5sRXMy
lcc5fYrqVpURrddBpvQ18oCEThPZox3ERpsNIsmGekGCktkCB7c1HOafQtdqAQxYensmlytFqxpj
1va1O+miYQr8iDqxcKC8TuUYQ5lhlPkfndM1A+1B8Lao3Ose80xWc+CFaLibYldAy3ZLfIJV68No
ZfDjxVlDrEhr3KN5NZz4x+4grDMSWNn7CHPODi1NAHfNG3ST71ArTaC09vB3wQMOvv97yXO+LARM
/1UtAoXv7y0PnjO3lbRKQdIWQiTN/ZhaZuiRdaeEynSoSY+xEFFT1kkCf1uYvf7eGFOA3dzk27Vt
Dv++6HHC9HhV4aAcyrssSmjPVOecUDrjn2ynK/Y5Kof5cGF8TwJgmbyx7M42TlEZujMxWszBRn2v
s3TcYZLG7EygMDHRIW94uMYJWvxVePTe45c6qnFN0bSgdoaJLlEzlT3Zjz7eaWjjuDFdeDXOHWaD
uAXjCJqskO/lkK08gx/bXaAQFE7bwiNqnbH07YvUhIS2Z+PTvjjx170y+83eKOGu/MAUqaRM7+Pg
FPWlPmy0pfyXRVziiSwNObMtZLaVMhF5tAwbJ5U0/keN0QxU0J7dr0aF3g19D7jinuD9V2eewHbK
mvPOeJxey17oLtCrtJlB0vXqDMdIU2HjD8btAA9BCeevCmjkrjzg5z56atfQvjdpHq1+vR3o1Bf+
pyIGME8MkBlFifHffF7ax06gH33BWdmKQ1XXbAlGzOGXta5lRDygFCYj3m/s6Y+AcGBvCWuJ0jG6
GIX5fQa5uPeforFG23wH53D2cNzuLcUmNb04GPkjfyAcu+q4yRo4TEU6f25yJ+AjRVEosRFNi8nr
xfdl56/reDyonJD57tgDTnql5sZUNJPRo2fwO7DscKtf2XG8oauW/rGCmIBaY3bMNlQ5nXOdMWyU
AtEoNklum1Gu4dsuD5AgkwuL3VJNIdjzqwbp2SCOGKsOvHUf1UUX52//S9tpRZ4cFn+1yNiSAqVN
0emuJzZVr2lDlDSkE6zQzeuMMJMUb++YMuTPj9KV9lPzEbSd2EMwc04aDt5g461PLPjRVyPibH6N
32Z2v678LpMICFryRBf/Ambi2/GFfh6F6XxbqDC3mpxOGSLP42hW6AER0PuuRxBsuPudti5Zcmxq
1VRLqQH5hiPwLMQmDx3UW3vnBDuH48mU/j+pepxkUbDhSPkngx37bmg3FNbOH18j12A3P2bsE7VC
ewxd9Vnn3ObAvz8/1wSpL1Axgvyhe9m5cu6mRVDg1LBfxCCTZH9dhSRRv8A4Q1S6qKMvf+mDocZf
6oBngiCOeJurLaKlDyNUzxkByf9188q10CnbGwiZGvePKoyUTss7HXtFQRp5W2dD29+1BiWufexy
KzsqYhXbIEIqKJfC+CN/No+ioELN8kSi2WcoOD5RjigrycWOPaCw+ws9NrQRU+B2KkyQ2hCsjH0b
LCzQ45iZz8JDQSXwY4AFAdjaLDYNKA5nnBL5RW6tZu4ufjacQNtu8E9E06jmjdcJcHb/NhRNxj42
lI2J+gyS6EQTaqJVMJj47Vovm8fKhZExMjk1JEC10lN/wDTU6OXB6y2IhkSJ6+fn73eNqMUTFMcd
VNNbDeHZ2icXQMxFIhGXAU0ijlro2U3nVuB/BOrdNxvVoSdWBuvTtoHrbzR9pNt2wDK73iNxeFz6
qLLKaOM/gqLXkzXWq7Vsiz6ez8SUjUn+p7ptUtbrpleyobCrMRl9GeEv6qrySSeODbwoH9V6+duc
sKk4ooK0zPZGXS/KnfZQCeRIGWOuHRpW3e7/ZPeQvIViBasR+zskmKJLB3CQMA6ScbZCwF3qs/t3
5jAm5MyZHOWx5hHSlbda4wwve2IKdg7slVZ9+Kkce1r3atwN7YCwk84rFwSfTIVl1lecHE+cUXWt
uSUQvL6BHmYwAmRD1jzOQk7nNbjDpHdSlk6/gGyB/583y81J6N8TbLMNvekmSR0ehUfRT9qGDHlD
AckRRqht2tKdZhIoBv+k1asJjsYZOWrPocZ4K4KTAFA/YYq6opQPDAhntEJoEfYWU8UxQK3JH4hN
bYMmNpfy/s4oiwK900d7mFfKONowJr1fOdezTMiJpIsNmI3fwUF+wv2Ocgl/0zaKKIQb0kVOXHRs
MhfPaiEuowWFsqhWMoA9YGWtxg9aKP1AVUMnGLB66RZmVzz5e/mdCmiXAPFnOA08HwL8AwdDz3kS
IKn4cK90QiLEaL9udjUITj75FDez+7CxoBZw+pk2iIxSFLnJn8m0YB31GleTLqxwFfpdeffeFr09
gBC7Xv0WjzFinRecQssE2FYQnjeVvG0ec/1G/CzX8f1yQr2jayBIrPgFNnSe+QC5VR7qjTL/HizI
WCRKyRyCHoEcrMZTDjQSiSMAf9MbGDLBgcvYbE3DMjq+3zkpoTGvOlQaQdXGmonpLh+2ZA/+zr28
LEHX7vDC+vHd4s2KkBuvAArJoitTvWo+Gxb91qP45xappKxyAKzyR8mVwU99eJGTHG0tShe+Bv1z
YUrsnlXudqMCfai6MPAuSkRjrVDg45/zQ4I3M433QYo/uizCrR5SGebX9bysyRjb5GmIgIsfo4a8
9eoMSi8MiNkAFa1Vt+sFmdHjUKgGx2SlDM/G765i9RCiLmBQwXMKZzUArblF/VZlAjgkvraTNebO
aYWSolTKTyKs3jSLteejkfY1Dl3+CIfL4EKBpQP0ryahirkUu56KevOlSkH7vJ14uJI6srOIKaVp
Kpt41hu3/YV0IuAxqJhscCCsctOP8g035PJWJOcQuSLQAN/gD6/U2qywCXFJ3pANfuk58DA6xUMa
23DQeQpJLJqumxJ59d4Sl7TKrYbI6Uccjf47aFTtS35f2FXJzAWEtQyAk/RHzXpBL9U79QT6F4JH
goUwdXERy2jGs5A7qCSvOSye9Xi5VZkDxAWzrrGqw9Ra3n9/IVttwO1L8UOwXO6CEM6KS1Fj4NNX
PU9/q8yK7ByaqA7ePV+dC9s5L8daIDuyDWPw8DgH644wcpcatg5BXcCoiaLTpbb1IRhRWJLXbC9n
uXyKFY+HNFqg/qF0+Fyo7DBEG+LoF1akLGEfIxFQnuHPgmsVw/g8vIdKkkQfi69MWYy/8d9p7FXM
53i6pPh9/niFmLqo7wKmoGNpf//U2+W2t/hAlnuZOUA796QZm2WLOfoVlFSX0YHZOOY/DokD5qB9
lAU1UHRMvBAJblktQQMh+7H7I/IVIvlqguaDjfbMpLYw3PUjbXtVCb4o7zsFebbHgOYgCKEGuSQq
3tkpDpRKD3k6fGfXgl6b7YvmBQxRCnK5v6FCw6VOZBrfA8JiPbWvfFb39i1C0wBmBY0KsmTmU242
BNX7QPMJfzqqTO+duIrzQxGq5zMkOkX8UwGmbKUB4i97h7shbRDj7gY660FY09s5oPNE7yFs/5u+
LdAqXQFUMXLnhV5Lt+d47CsCMkssrxxzfLY4Oehf6swvNEufKb4Nb43nz+hYIJAoH+NAasko6h68
vJdItzKKQ0ac6uX/ahoDwxMDCtKwFmyJ/pDK/1iiZyvfca4Rf4AMKCom4AuPOYUayyyGEiOOyLcF
/47V2JeUSwp4S/63EB7c8f4ZY9WoTeMVPEZqlDe2IdijQYWdXWCOwAU8+LUQexcEvLGt0zHqJ92/
Cd+TCEjYeNNOO6c6VCFrK+LpvPTK3z12VUVybxxRqmDsOMEl/2gcnxS9qN90AAk7wFlF4L8VX6uz
4Ds1ASJB9aVYdqQuchB2vx9glGPbDC8Sfl1Z0xAQMpnSAnvf6J0a8K3wDa1Mr+SepVAFDnIFepVs
DsSuo3UqXOi3UDm4r59VgAfIGWzjN3OmS2QzMUFCX+Ap9fUY+VIfMXA9JtUOCNaOHhMF12KZxO2j
ot2ncDJ+cWYoWzdwNZpnDOGXxTM/wQsc/7pfmDxgaRfDfnCJPgdgeyfBWKNIh2EQTQZQ/f6PXrUV
PdHPjju4uwdKOCR44t4k36l4C/NJ1GeZUaiHWuUFKX+d4zZciHwIPG19XLY2Y6URn7WD/XtzjQxZ
3tAjlS1AVNAfgQlrkAH2ce18u3tjN4h8JAbAGAC7m1BZJwI6OMHEa49j+7/PLqHyiXfsgMWf1CYn
8CrFGJoNgAOoJjRqsurALq87fvXX6Z8uSrJW+bPwXcXXAmQOwT/ThJT3LlCxxQi7Rh5QDTi/VOcV
SZdkoOordAQiyLj3LW1OnUaaY5aQHuAe+QT4VczfuLlgVN2kj77h+jxRnwlCChyOUm5abpmr9jqD
6J9KK9bOtowLXGWLozS7NdZzK+/QfOCzBVNc78G+nMvuLsBNrD2Ag0JY5JGz9i4ThHnOggyINLPm
NtfIR09mSeuS7xx2hylMp997Yg6KwZr1gbMH8+7YB0dJcFfb9OZukusuVoCAvM6LK1LBDBUq4RSp
ors12yffXHKfOLoo7E4ewyU02w+YDJgdyg/EE9Jf9Dn1aO0Q8VZPXruVRUU/rR9yPf+lFRx/NlV1
grsXo2iw2oydrwKTkgKAa3CrId+Pt9SP60fe+HrtliAoNC/gb9DB9v04SJL6flVoC0hEvHmYW33s
SPy9CLrRaE7neN0IPTsNqF/CSbFLY6pN6amj8AoFnIgsxrXQG9gYIrk+FHsu10ARH3cMM0sQR9rE
s3JXbKUbT3d7Cm8xTy1ajtFMriu60XawHG3ceXlagD7b/SzQBOYvjADuJZYQfUgQ7R2joUAeWnvl
7Mzwjn9RPvIQNr0jQa8csU7uitq4+AAR0pxIaeFylEaAeHId9nlmmzedSG1RFwKoxkoSEWN9ZU8g
/7e3mpjKhNdX8TA3OlqXwr7hk/pMg8xlJKAw1fKRLqtuw9X38+YKczyORZEt2z6cip+fbwHeUU/h
NBMTqwun8tnYSLJTZD4XZWg+Vhz3GC3Bl8JppjEz6g9EA2SOxDCaYMwrUCmn3o0plkJ527WnBSg+
QwM1MdzUsIBstaBLPvYtjr4A5kvnVyneO9VOBmXZiSm6t3X8c8ymsUURvgJBbZCJEiEcAaKPYbZa
T2/dOYmqvqYlbhsvma2P/uWEnAxpIdp74vdw6pgYmMj63Vi1v/zyIJotzLYr+T37cIxUjOPwLZTK
wgirBv2dcOuIO0a0SdGf6Z4fbapAmg0fdroSmmpaAdInoaJBnaOLi49EqJkAxEkIrd/Y4EVTlV1b
WOQbOqNjpScmk6Gt7MdL+aK832Nh0qq0LVWiXuJuJhQrc9H7PQi3HRn5PqazXeOAmPiSSBw98sfx
j2S0+65ucugK4oiTC1tUa3S+PYDRShKJZ5KBJn62HDtclAI0Zburp6ov4nBn0OeJGmqTNcaRJjv3
MC8PR5YyBEQPXVGwNRr5tbPxbUl0em41vjffOn+s1qTLpsq0zlp32KCtLJT0/SuGCqrqVFaQfTFw
QvVMO/pBm8oaVEoRqw3FxlSv+goIq5C4BEfRK82SDgypUVftK5rIAaxzqpjCHK5kUvihD/nH6fZ9
+D94PDwyUrTqd95CWFhjgnBDdRkHMYbCXv/viu8pn4JPSBK25glaiaw2G1igivsaaN4WitZdrtRx
ueb5AiRjreBSLnQT+SuhFZoUprkq4SseIYA8ht4TbZ5S2zEnQRvgymkCCLWblC4DImPm3jXlzQoH
2Ob7ei8gn/l2ZeorlcSlZiPjaFX4MwVxvp7W53dNSQpp3/xjU0j8wr8WO7Zl4t4EnN2tOlkPKaSL
YXJk/FIMaVF0fLJ3rkRRKhy8t1e+JtZZ3RwMH1SCLp2xcBIK2o2NI4CmhVGkMyIRGWZnqZQzKl1P
m4Ttea/SDWsUn/KMf8Nroa3kzNZ+FeZiFm40EqiVhEeNF/iZbCYB+7Y05l2RZ+x4o+nmMj3uDUku
anJUg0KdQf16n31n+RwDillxne9w5dRwIGzqC9NeUd47tE93ElN7PMDLJZKXnMtxh2LvobN4elm0
Z6Z1grvd/UZwOYtU7d+f4yxxrri/LjeoCwW1RKtDUXvjkiCKPLsbKFlf9PrqjFHHHmOZGNt8oXMg
OjpAoQCqnxXPEXGGXwU52w5+Hcjpztm4cvjo1NqylHyEWkW36I8trLlgOR7OwqkmxlbVNPl0BznM
DWjYaKwy8VEqULy3dnjdDUjr5pMqH8e3RuQQx64+ZJUdWz6UxOiNV71lS2ss7rz++tKoj0AShLv3
3p6JFwYyrcs+rkEN3+TwdusKSc5YophR60Ojcs3/iH3z4mSUwaNfAR8KvERyag4GD38wVoOzUwH5
XGLHajMcg9WKfP0VLafrH2waAjBvLALH0Qj+Gs2ErTOLQMs8PlJ2vnRKuzf33+RLlofbzoiXSQSn
HFoFVHiLpYJKuXYpIQJj407GpmbdQnoT9OBN+RKIB7DzMEFVLcqlgmuJ+YKfJGglUiW/xcdvG2i0
5MYA+E6qSoPgZ1g+ukoPXdHWl5+oReETuKE84gDyziho3rVQJyE+e4ag4jZGtEgUxXKxzpO+Eltv
xZeVTxi5n2GBLZeqUJSxRwQ56eO5pcU0F9IEtgWtiUggPMQjdJO4oHoTZJbhV57DfngnhBvMZWrO
b1m2J5Q0g2zE1j4otJJmF2qfAhymbd6UxUhpEnzjnpYnEQ3rTZEGUVOWqdeoYOT0WC5iJMNltT9K
nKT5zSzAjxDK0Pr/TqGaWAgvnut5ncVaIQ/KKmftE9SlAN23xQgjHQMvGlZUEyjUbdokrSv23gkH
TmJ5eBak2fvUaoaq2hLx7tdYaOTpuFYt/CoYWGp42P3FecPkN5MXmRND0IQ5tPRIxXC1NhugOExZ
MnRFoyPmuxcqFeGalRL9cpfeiu2vb0Of/2bcMEoTmYmW7txJSsMzU6Tdsu+jezoOvCNbXFXLFrTJ
V3Hbn7NNDFBBTyoMOjZ8O+tPxiBWyZEastojGALJ1EwsWe7L2kCVlTZkWKk3OQSPAwJ4zweEuzyD
/CmqHOFMVTmFE+Yov6GUphvDrFmnwCjyvGr8vn+8EeCyr5FCvdIkWLrkUKfUjHwcSVy9VFAy/u9N
1jXTT5atjdNh/s9v4cQPAQB8E65PctGkPEAAd8rF5kcl+HSAqNM0PnXn1ho9ftvcV8M5i4YN+SRy
yvPtHDEhEl5v6IrkkJH/iQ7VvF/1zacuPrmTqO2GnL5B8c/kPUbmu/B4JEcgzYhtvxPOGElEADoD
dOblH0766eP0V/A0JNrRyGBvIkYdOzcWiP+C7+dzcbEPLDsxV+aIMIhmWe9MKKGJ4F16sRQx3GpS
cv9xH0HaDWBhO/fQbbtjVeIBaoKGX3APknb3sX5YflLgDSu1ogdCXU69buUh2CGeKRb3Zex+GAGe
XvwPJZqrdTmXPRV+OsSBQIF0qnCJdlKxKNALQvTA9+cf/y54HpqVjaDfJV+KOe/zWsWw8YbXdccg
WWZiOFqTtlm2fx40LXS8ewY3H1MzQv2ncAZ07lriz4LtfNbV5w+45MbTkxObvF55kEnGqRPMQHOE
DDiN6gX5X78Z5HX1TLTZ2rsoWTQUuylt8l2u5EcFCDxNyK4zHKaNS1/njqw1Yo/aAvRZijRarRnw
agrTQ64MIKOL2TzXC0chDZFQpWrzT6PIcpC41eEVpSGDcpWl10gFTjT+zflF2cTxz8WLBjfMdw0K
fmlcmjeS4486teLCnyljRXeVHn5QWOmBVGeApF0lrV/vew+DwQfitaGJDdPlhwMRYKrnNoXDo1NZ
sPX9D6dDu+tYROZlSfWqmbVpFhKOKdaNxFskAyf2YlXgNqeqVEViO8EeYWBsPkaOftSdyNhW+/CB
pSf0FmucfdVFdSjzv+icRBteItSKebCvt5NBUPFbkrig8BjNaEi+suFmTuQCgiiCxxEWF9cLGXDe
K0akAwyPsC5rj9QFwNOYkEYn6YQ52Evw3/mrft+kLQeBqRDjo9QymLtYeDcJfSD+fqcp2P6w3GC6
cJLIGeHVJ6WnCmZRfE0QKCmcnrfnBCDW072rE1W0alKePd126B8r6AbFxi+hsb+ZS/X0zF34xmcS
FtraYbQZNMZGoKJ1MNRN4PcMh+gHaIrVVRlblUqSONumhotzYB70WMSJip0X8+vRuHeOM6DGXIJN
5933o6t841dbi73DxawT9iV38Mihmko8l97TXmcup9A3Htazui68SvIVv/uMa59TPj7hsHqv+lL/
D+LZ/juSiJBo0wJr3I1zD7FwpH2eim+qx3MBr3sYKZEcLJZcAuJlpgmyvzX9ydBDVQMxq6RgUm/3
8GotbjVCrNUg2MF6ceD7Q1cifgBnuhOW4k7+CVct0vZSANvCQuvlYowpoeDfeDo4KQFFCrgMv2Ez
FOBRKQUfWw357EA7a2yF8tMiMBOYS52AKynYN6l9pJvM/LCH4p8Z85qTS/zaQ+RewNvbpY8Tr+wp
Lupspgl0DGjkieKSoKYuTDLw+TIuZWorT06EJaQMcX/enCgx1PvEoiWr//Am/l8HX+3FUjAwMGK4
/pMxSjHQWtWubCJcUFJ0dsD6HRfDuskfnf5y0kTpLeq6mvFl7dniWRycn1SCygisMkhxVv7fYGeA
eisQ1STRG5d3lhc2i/nrHHMGcsP1bsqOOxkm7KHrdofppWIJ9HdBbI8rBg5U983GEq4Qkr58KP8S
C4hElq/8siTqhAwPPxJx1VoqBLcmSAk+wxHmK58ijPqAeNDFb8DNuSerH0i5eGWVI9Asl39UiqRx
b+FFBPd8Q2+ocl1K83PQMkdvoRuQxWuWIRqb/MjJv5j/BAsQHEl9eYo9jWXZ7k9NLK1I2Pmujzcl
5Yo5SmSK91yMqzZqydX5gL6FMl2W22H/Z4MIfqNJgskfD/gFjSV2VgAnCzVtZR4akJ7+6W0HTGRN
++cvEgnRViTAX8RIv1L2o5expmin5fASkGuiVwuE9bEinLsSJd/9e8tLaud5LB0ukexZqiGVNChw
cXe1Vga6GXytvn9+bPK3sTPbRz9LZNLPoQwQdugJx5wI9m0TaR4Xov+4oGPcxeFpiAuj4jdgv52U
HEWozijFSpAs2o20DHKP3o43cibGGLA/ObqEBT8QOGAyKqZuovtqLrP+ozYwdEUcbV/scx4Flpg+
IeXSbT+3p8JoMZ92Ju8Nhd250flECoZrLWzk00Pk9BCvxINvjfU33Dfn7F3T/eXGny44yt/d7TP+
P68YDa3OWEbxK6PgN/Bqqn9gGMiP15M2HzayWcl7t7QVRdTwq6J5Jv0JBpLYgR11NBIgsKigi0vV
ka9ksC+xBMuGyhcmDZalutBcsGuRQqu+5N1h2JiwNkzK0WSCGNjHuM+j4hu44e52P2Zrn/gUTHsu
8XVcPXGTWslEt2dLTQYAUHl1N4QSiEhb7wzraQ3/wbERcEt2E6jKXS5bKEiz+/CbLKFB5v6x49qe
i3KMTuiqDqVxebJIMjEPb5To3TQpPH1sJnjLu7irXP3zakngtQgntZRmHIKvWWMTbjkaCG06CtFh
k3VDVXOV1pGrcxeXzgXOyswvtyAF+Jppj7MSxfKqUtvFX/bXL2q+/3X4YOFbKC5B8AHqFOEsBwZc
yRFuxcYLyWYW6gvqdOY04wqhEr7U1pE/bbDnmcJVLJADvFLMqsEokKfv3JDU1T7PuYI+38UjJCG/
5GbWtofiFGZ6BA5EMSyAQVOvwuTKzFRasTw4MvQfWrDsTPUfHBqIyIWklbkQOUQvF1n/vtnq0Rmd
E3lmyLJuSz/x/UYjktUhwOlZGJP9C4JraKvh977zbgA75Ekj56ZYGvYGwqBhOdWg9oQA+c79A8db
Zq5lpp0zxjNIrCH+X7Fj6r8CMg1CH5nRuyKSPzkrUO+ML0ctoL4TIkZbrP4EaGYXP2rVT8ZMWPgO
hp6YNt1quKm3ZGOryNOZpiIVlWPyAwEglQ7MdZ4Ut0TTN3k/TFIASnh47AU4CZ+fmvhU4L56NI4g
hVAxjzMhwV3rwwr0iT67N0tlcmrnZZW4zO+bersriCdERnSkP8ZroNhCpxGPtRPR9RZuwH3s0oUh
zddB+8geVwAz7xLOzbQKRUoKyrNFKiHZWTHcLDKH8cuQpfeqDMBCO2qa4L5l9y9pXyvAiR0gRbPt
7/hys5LJ9x4TkPITIpfAQMJwqdwGpWVcMu0K4ebU6LOW4FDcmWM/M436W5hJDYMAQDtSsIVHzwXi
H+S8npLJh7MpXRQ0pYrlEOfEukD6VlVhIB3EFO63qXf1zz249KClfQymyMRcDzte6btBDn2uXItP
5BfpD8i7bb2dpnQs0K6OPeuesQPEVYopSW0A/hmdFUwWgJDH0uhIroSGDXxpVHuXstqs+ullfbsl
gDrIQmOJnpYvkGLvYPKZaFGSb7cWUDfLo/XeuDMkh0ZEbBlk0/z33r8V+KEhCnNeiTUyYJsyahL0
P4/XET07E3737Ero+YL4lQYSgs64DQz+yL3rScXiW1G6/4WxgfM7rnSH5JhNDpn4z7TaFTizLOiH
bmeA1waQySxJuMLsFDw0uFWn7B1vqOSPHBaCJL2xusFpFNH3qI7jkaJ1qVCLAUGwFeMVNyw6cX8g
HK8Nq6LYvuXnFlxDAy/Bi7IVVG+C97v1wUwghM04MfkRro1Pl1/nraIbFWRiTzxhLqiv7ygiKI2q
wNr4esyT+Bv8XsIULTs8QtYIa05uK5A7MAegOeQntnOZrXJOoIyqrsmrbE3KIcnNMWpvvahZGU4o
ZwWv3Yc1fOnghHrBcT1ARniV9msXWVCv52Ej0O4+WXaC1kdbXp11dc9ikYmstwDFzgbuxneIbjTn
4iVwkLzoH4WTK88lmnhLePftxEuTCEanOsSRSH+Io+impeH4ds6NPSiP+0bL7r1fSDjfWd2PpWTa
Sul5GS8xzeIb3F5KOdXpwq8bFFodaaUqEXMZhYUaOoWTrzEx7yWc+BGO/wFeWd89aSVdeUJE6p2z
p6QBJPMxTSvD2ZbZr/5U8189JAROfMl82MYiCsi49t2QdmFEP5Swipick81i3vRWgg0fRPjnwXZS
X+8Aj8QTFc08bEQuEZ6T5tSLZE7g+Vq7reHzQO8NKd+SnAWSzcFFcHJEkvnRjY3+Q34K334hz65/
+Mp/yMtbRzrS74lH5nyawJGIYO5NZT8mzWsKCq7p9glUBHC/0+f824hRMwJ4mabEP4LHN126wXLh
j5fGlmX5zKpH89gACH1sJtXtuhabpwO14V+hA5lZKtO+eGxBuL4VEYfnTcTnFeKNr5gPryInq2PW
4uKExuHPGKdYiqZ5aDoc5T9LefZZtXr3+YUb9a81YSEldsZJNP27CxMZG0PYB3Vz4kyqLA996I/l
KGb68Oss5uP1Zn16RM+DbTwqx5Xs+DhpuLds14s0a+I57WMNG05cgYxcv8jkZfYGCSwZJmDPN3Rm
La+IzzXa/+ogDoMmT5GDLc5dwNJdhXmugL66Jnd0B4QEvfNE5IVBwI/56SaWktSY8ka2Dn2pl2rY
kGeIeQxbdCckbyuyvNx/nYM+fRDTjK6xR2dhk6WPovwr50YiQw3I6qGtgUTzZfqzjId/NZAn/odw
FkPBnj7hWef/ugzHmSQW5qma9ogJqigMdRYf3eJHsLu5qhjMBXIfNKHgJbr3jEEKPofAOZ7Xlw+N
jYH2vOUG4sGSZ5Zd8c7D5e8paUU8gA4yx68LsCFW97cuBmSYL5WpBDVC/LfHroE3AHcnVcrtf9Bn
Dd7b5uEl5z6XtKF+Y8tX7TIPNbHCGnUJGvasMyixJq+LpgKodIWT93AiILKPSSR1u2kEgvybW0Uf
zDObDSzAlM4PLVwrTJBll7SBGMt+VX69buDHaThrltoFflDRkfHLPUHJ4h597yKf50oIZm9GZQs6
nujc7orhKdAiNJwcJvq7rVuGYj/xaArEEP7MkKWuvARHv8sBMpzbvuVCmLk/5iINP6rd72stlMqj
iXlidjYiQzNglOBFk8keNal1uCxPCsvmYbNrc6f28P/PYk/LcgZXSsOXe0iPkiJyUMsZQvTy8jbz
9kCQruECN1D1YlxD80NLgnbUGKVY6xtWW3UhOqL8xKbwm05zDXMVSA6KppP4OZx3jya6jROgBv1L
fvC9psjZ3PIS0YCZO4YxqNhI9WxdwPPxkLPQjPH2QuLWqjXFQVIA/ryrIfzA01o0ec8hv21Sou1+
CmqTFPN/HlPf4+LAqlv1Eilb9ms/CWlNHRJ4pdKyj/CcgYTErRTtHHJPdl/E86/gY6SuJgunc4Gj
LJ00MbUazlC2Igqnc3jQ5bH8L39Ue+tyA0aV2Ffm7ApVW8CZqj4NzxonnfVXqBp8kFti3/YK9w9t
Mo4NepJikKXUSZuk49u/tLto1KqVRdSvgFxAVZbUvAcCzLf84GH+47pLuGMdmGs1fSTri159/ikq
V6qPStCwfsKMcQ8rEruR1y5i41E4elt+KF9SlilcijcGGA4FmkVF+9Pb2mllI4Wf32PynDwAiLL6
KcLlXjDEHFMmUrVLjQ/p/evcE1nbCoHZDgfmXhkAXDxhH92iJ2iZq/PumL4pUVT25wNy7Dm1tTE8
BbAqf9J2IzTMDizlBaXPygyygfk368jybJN0EIqTwowxtJfv4KHHtqGJB5IjIqDWLViXFFpN+4Sf
gzu0iOZFDElTd9WViKhvJJs1f3ljuEdpFJmxHBm21xZ+H/wGy0wYHoX5zV+V7+GS3H7evuV2nDez
JaMKk2QUQHIFlDtb2nN516TDGN8VcDBsGyS2pkrISzTNdlnxrg7PDvpUzRtButSbcJPjJK0+dY5A
VOx5EhHzw4b+Y12kDz1b+lU9KmuHtAQLsbaHGmfGlm4tPG3LyB6FW3jp3jh/GHVsIJYqRwmeBiDU
DsVUr19wjyO6NqqXhsgXuHFveG9aMY/OzSiGHO9aYCzHSZ4eGUlIrscNMGesHS4Yc6UbGEsUtOic
A3Zsh1YPt8p3VUJsNPvDzIsME0rjir0FcDEhTqlI6mndbp9US42zIYItSksi48LTqkxCtPk7sgHd
ti0DIdzC9c61SlxGidweOm+xiLFW8atU5j/85bY3SQiZVjiRVYFWY6iPT4MoD5f6VyO/UYfx2Y+k
01u1G/n6G7aeGUqqL4OZzAQIveINgik9ukmx39YlJWswWQzsCO1Wxl4eicpLkBkNte828P1lOmYq
L2sHhOi8PUTmY3JvcVEqpAFKRwK52/vcxVWeBubzABayf5733kTxJ/ZY2+Ylybc+hXTNqE6jfQBq
abXpFfQ/JF9pEwMbjH9OFAZ2H70eyXscvZT8Aaiw2lRENqZZu8sVFsSMdtdL0Lhda//mWXeTxCYb
3H4Oe5mhxoFr+KhUuOaLVeO4O6OfH0tz/bCMTDNgGwwNrHNruhYLrAapTudRq+WArugN1Hfdwwd0
mOODq9miDXpG3xp5UgzIKP3ZS597Dfz86RSIY3tyCBhiTChaXwMQLjcaO5Qfptzp1wF2UdJY0eUX
irp02pzNAAGFWUC/wEBiYGJ4ySZ4g+fXZBRZtNbY1GkvcyX+dFaNgDawQIgDgonYsCxyhnRsgq0e
QyOnYMkE1ehswrKde00QoveFFiSriwdDXPrEp6GKSXgqILncgjmXrQ9VntTz54FyeId8wCNg7csq
z4aFfZ/u7mfbje6OOFYMAwPb3MzOikCbMr3tgYpEObo50K1SgB3QP7sPBbD8e8JaF4wCR0OKU3wS
7uciZ3FwRko4zlE8KAu7c+4GVGjnoPGMnFmPqGW3MEUUdZhV8jqz8q+8LFuQi/NT4sMWV7D72OfD
fzn0GQjOasQ4mnTZijLeozZ+7Nmo3qOtjSpN9U3puFYJtYNVD7rjO8SeOpMoSzIXUQBbtEhjt8DL
W3KvgAWDHdK2BHzEu9dTm+Z20Wl9MaAh/3PPmhbjG5/P/G6KHPmhLJGFMDjao/2LasUDc539+tne
TVzqgTL8PBl1UCF3y70YmOKTE7qhPksrXhQ1loaKCuqFY6fKe79tDZRQXYS8qVVPab0hoPqJwLPD
qcnlV1s56BaxXy5cxBIKcLSyfuZf0PzDwceh7EUQPda2a7JmE4ipNdw4TvfgUw61R5SYQ8nn3mHu
pxD9KFdPZncnOluvzwaovbRDiNZAj0Ry0Ewkr7ULlLKiqeGbw0xcb8WbO8jdMFWDjVuseZ7mbGqp
cYPGTomCMBIbwioay+k2Iuxl2NMufKB/w5MzY9U0VeL2bm8Vg/G+FN5lSap38yFhqWIIjLVqz6R6
o0yJOLeH2oGOyBZqNKuhZlz+DA7e2TEqd4JZOD8qRyplTDWKnCT7gPh03Zi/Y28EgFkXVXYKjhkf
GqgMvT3YOR9QiVzmfIdkSLfUSKsv1tlFWqmY5HlFSfj7qmCfATKvCYPXOI8L5857naYSmPBrEcBL
pIJBMFIrbyBbiJEJ7HBLDVbDYoaOBGzNHSkHn5LnKPZM1qRBDBGKy0W2pf7xWndb5BY+n7q+WtDa
Nvna9voDIWbaTezVDM+ZpgbTgSdlv/f95o3MTSPN0oiL6tH+1gE9iyhAJSjny76+010iy1UTRAX6
ogSFApJ81sdd+ziD6pMkn0z3NcEAUvzgpK7uG6NMJzJfdTnyGwn60DZ8+lvDVDCPI66eeRM2m/fx
kN55domBpHqLGdS6d7R3Ihio0f6eKplPlK2l5jB90vJJNPwlaAiJRZGgFLyoYXeqEblP4UdgHui/
dFyT10j0d03RpTK9hsreYZtvJXab9rfW5iZmhd7M5n5bULO5dV8w6z3gMzaCwabBokiEfqvhJITk
RpuTQwdRB+WeINRiyV0SrItLdLaUgShTaKapQNkA0UvI6gzt2JnHt52XcmZ1+ZBMbHzBKEEu0wXG
kzAceHU/+bhdDlPfRiBhB6GehPMhJBoaXUyZ9VScnyZ7EoaXv1mpkrocoLe9H+oKO4XqRV7F0UjS
TFZc9QCDg6WzFapDH0Hejj3yzHE3/EoMUcPI1aqIMANkzdt3Ic5YlamBEnpg5Q/wAW4zSmIfTPd/
P1qFslioZKtNIk30n7zlb27fqGJxijkMfsBEIXMwZavDuUcKNl87Y+LBNBSFmbzyWZbvovyoS3eO
7Iir3atLa1YG1e0ZXyx6YWZ2PORNIRxFCom6JT7wvJERyYa96kEvm4CpRa1qASV+5BbF++nWG0lO
NfqlvaKCByRatZELQLZvS2CMpz92lyly6vEFKYIiuRYhPS66IrYzB1jGfRzmhnvOeEPa9vViqwZL
YrM5Dcx4ZszFKmStoC3bFBJ1j1lKz8A3qgrsM45QVct7TRARrTOT5QwMXXVP7XFICp5+EHnBXIdq
Pr6kn9ypBvqGWKBxSUXc5A/KxZDjDEIJPzR0939HQBODH0+h4M4/v9KOQiji+TMe9a+Y1XLnhuc6
VXSsjLxITHgwYiBS62za7gHf+KRB0NdOQvOVoF0QkHxW3gBPaUzLx58D3YFM3uXP6B6K+M0DkKHD
XYljHhSF2gAMEUZtsZWsLgic6+uhrnK4KGardg8ZUUSIUf5hpbRA6WjgG5S69USp3f5P/a6FzlaT
atb6yWlIsCVq0i6GteCQ8na6mzfhzRp4SlaiWSn+kYfEHW+/HGWn4TC+ozTYjfLF1AcWlElI/FmI
hFqNWX+ssXHNnRn8rupjuco/+kRNjzHggONDF5NLBqcORREPZfO4YgqqAUw40g5r6eKMZtc/4g7v
Q9qPn53NCdXsegsYDr+v+SpVyIW/yDhE9Q8kUvMOlxpRddIgipycHwcsAODJHBxMbyQlQtdzxTlt
hfeqYT6pHDfvbSp3bTO5l8PVfAJk2y+FXYIGZ9+QsOTEPJDWVM1tRh7MrmBZ1keBEyvVRUj+Iq05
AegCjHTV7ZUZU86I/DrMwQ9n0Oik+QuEcuboxf83q+G7HWvChPR5B4PXdleQ/k9gqNlBb/1/8dvA
VPXL+yR7f34avOimWVf4Eh0J5Lt0wt/SxLiUQk5tlSzi9/jOfZJYjLCbKgLAOTekJ7Yqv7ZAOWEN
u8EXgfVxQtHqP+ysx1GFvgv14/eCVKTxMa+Le09xKLdUyItiuoLwEvN/NBTQQ4JfMzMUa7swPgqr
78xCE5ctHIIKgSus3f5QJ138okPfeBbowcUifdPhVC1yALd5O0snh2LSavxaW7pilaEPd8ns9JWF
U4LxqpH/FOa31d+j42EGR8RCWjZBupAEH0n/HYBB+36mif9UHQY6I16f7Ihxl1rz6fggTyeQo+Ei
VEd3xmbiUPJuSQTIOGpG2v5EY03RAoUoVOjV2b29MZ3r+8vcbPUKop08WWl6gR9KCsfZoei+qkbr
/KmAXNdMRo6sQn2U1/fFtknZ2ppRlk2UA4Npx0mUxZuaE7Y4j1JKU67XYPASM6YplE9HU+xzBiLV
l+/2OSPg06Xt95TzRcXLxW+gqG7rro3bmLBsz/Fjt4I2Aa/FjA1bgcG01yEzU+KqTVgkTgdkLU/0
ruZTJmU+OSukzVDDDyZNqmNli+wWXf0sCSqVSyYMUs2HI5lyxUKOfZ+s7rERfdy99iYV7W5fZOUR
9+vnJopqzLvvBzmNQkzjbZdleHTp6QoYVJk2LExYC2/Ptw9VjSwe1T1GnuE1PgKTHkyZh9KP7M7i
Kf6A4Cz0wRo2rYutWfgk1OOXfAfxc/4100HPPxf5KRwv9WlVbwpXOlzJxKWB1OAjQhfU13QRgQ+c
wTTdeHIxIUW/rpaPVdd2jDheJosB8w01PwFOmblGVItyEMW5iqnBQ0eKOD34zHL2idy4Y5Hb2XmF
Ks9kLuCR6rq40esWRfro4PnlstbEhDL9y1A1Xn+xOa+/csUHq/eomE63if/rlcK6PKoQ1HAWGBLV
RzmpJF+T6Wvvv3cdcpDXtjvQWYuBxnzWt5FkWZVpwsQcHcbhPtLsZkdLdgvX/d9KFogMVghLHJlI
26l2WkLBueSFilCpWWJWVivNTl20L63JfWW0qpt3DTkBnHUgHgTbj+ERjlyrevNLqbGlKNz/M656
8HYbnG77LWatVyBZ8orAcl9bLV1+ZI+DMGvOflOw4phys0NFhQKNpUdF1e/DYsHHAEFfcpgV6yxK
Dwpd2pRl7V234wqaRpa7VVxhMOT2ReFjsFFE7JTqTkN3nJYEhtSo5f9pZxEhgI+Tpja0Dj68blBl
kysEZQDhStQ5dptQSSKvTnq5UdzrmpZT6NNGfVyust3EmOqWGOvi3rQfEA7iW6Stvms4Pl4Vk6hS
vHfGfPUc6FibE0TRJeUv0FB0lr1hvbS1ao4HJwNxCGGE8QYsRc3k8+ZOxET9FUyIakGnIQT9SZrt
E/j2pjfl66OVGNEyohRlAuY9xV4BIfpLc34QhisWGll3ugAGKjTdniNeQC7gm7LCxSyWgKgtauJS
eRTmWAt/XXnYCbWIyXiTq7XpxnCAgnIh206hKLuW7RhVq1TzqOUzkJTJ3NrBJNXedqhoNDjZoIWC
U86jHIkjZnxM4liv+8lbSmjrs8avqcjT1C5X+jyDciW7BXQUwqacVa1L2bSIImle0HqM+O8DGQB+
/5rEBbGP/v9akwxFOT4GuKsVgb3LvTa98O/bnlVuK9wAuIJGlPxxOP3TMYCA96B5cIFrT8+XXtZr
Ly5kAXUlk4fdOtIlWDypD7qzPX89TuJmRsE/TT2wm2PtZXSgNRnf79WeDa4rIXR0Jm37mnwSEdjs
b+6Qp4+izmIsEhwp0QDkt/iOBUBL7JwN2ktNxXlUrtfJJUYBeUU+CnpCnJHreHe59BfIzRbfeOrI
4BzqSxGBEta7rZyxMmX91WTWA7FJgN9npZbS+fXlhQUJU0ezS03FBBSf6cAoFnZPfMiDHld+G3la
oAFmeimnNSqHjH2gDRdjStTBDa5LEwLAqEPAXWuO5DPpnt3j8l5LBWV0ZeUYBWoOr1/OX/IJsaCW
7QBes18ZQmWAAprHsetMSJKxcjDj1f7LZdYWQE9kDh5awGKg4nAH81gTLAociLNlGJDz+ScOAhJ8
l3v372jP7e2Jk2XfKUedanIldBbwQOTsMyPC0l/Gogj2SJfyAsNa9WtEpTbSuKjArYTdn8AZnXmD
1qbegREjBkcgOjDFUjB/tHboQl7A0xeke6Rssk1RuneZjseSGe3khg7hBNzKsV1r0Q0IP8K3Bfh0
/OHy+msEAVbevHv1GUFzJ3q3JCe2H4adwUdsOAISnEQQZYBRUj8mvPUotQKahJnkUEfHMs1vsdnr
bNAtx2cgrVqu4/zu7oPxWriCWZLmXi6vUSntrkHg+95cc/aSMDh2lUkLnxvCCQxXoe0dvlJKDcm6
T1+d7VPWW2EU888jRNag6b0IPISNHDrrWI0/IRVEsjTsIrwx03fTJc0V9GMhBb4uGrfndnMZ9EJd
AwB0kWaz6R38QVJ0CkEukmHTEjC3uZPkBj2uWzMIzD8KMfID0CnFYDpmRPHz4bCYfcO4Ky4rmZfS
l/WDYuWXUArEXFLnb4sbcQwZxNvtIXi1sYDXVfXqU+DbHFbEf73VZEe/UeCTLqjmBC70ABudHMqv
cK5rW5KDXga0470sChnB6zvfilj5N2ga1zwkBfpK8tiO/ixpl9mt+cJlgYRkeRLYBLk23ZK3EN7W
9K6YJD72+pxgYQckXLhnkmTzhH5lTxKLnc3G48wnh2BIefJHMQS6NWXn83+5CUNLt/695+NOuIN5
D69JcpNfzf9IFJbGj4sqikDJKWceWdGKGvBWcLjDBucnjkxXR986pLK/JhhJiPgz2K7ZqKx5Lbsn
CAXXsJ2706xpSnpA/BTehOw7VjIHwSWqd2pob8Rbef3hM722+FS1y7WKq6sl9+QBA/xwHPN2cZn4
wb+aXRKPbetm5UCzITnevqaVAe+VAA9+J428aM0w+e0zVrxkaECi0SJWcTiArIGvnnvyxel0WgTy
7AFRh3+PlxReArQyzIb4iKU4Gg4ALCJ4zVlgfEnaRO3DmNIzm3FZkcooE07N5NcQ73ISlQr4zvzZ
rMRru4MjFghqcl2gczuBsxYxX0NdUguFY8cMpqeEUCDFrr1pxiatuFtl+fGkEXkvXMdXUDpYaXk4
Xpm72iERdGEezb6fLclyhDOMwwDGJDgEgioE7dDdYPhz2LEVHSvupxVg8Fqx8cjTz0GAebYqPEeb
5cUcupr/fkyTEleAbIicOxFw8uJfXZJNpk527WolMokKNciCMA3RjaosSC9bozyofAOydqTQ5CzA
nsyWAii2OZZji3IMVNaxXGXR8w3j8hxlCZygJKGHJV0OFOyjaYzKBAG7ojAYUUq2pQb/r/4dw2IT
mr5nOyHJ9hklt0N7cjF4m13UVSnplu12Kt3PVTaf8Ok9c5Ufle6d7GwZBUCYpUdp0W0cBZk3LQ7n
rC+3ypcvZ73kcAmt/hC5d4LYIX4eSjNU0hyjs74Ni52DKvHJS+F5gIbHW8cetY1ljSe5rFUpq+uK
7SqePMUkMXjJ9tRyf1OgDRP8WE9FbiFjmvcKmlQuydijVgEDmYJRny0d6th1NmnsOPErNlvGgTsj
vgtIhxFzKNNNdxS4dAgJhwEEXD/lg5USoiu9+6a9S4x4yFUBcO+EGjTu2ZywR54PIxbnVf9kuCbA
jHhxwz2WYUJryaSHUYdpuWLSl1z1JgpgI5c0PXP+euMOFcRWjg0IpanWCGkopkFxiqyGTR9ztx2s
WHWTxW/nBiLdhXihG6Xhkzrdy4+wdWPrI5leK+z4U5SM6Or73PTmQhC65s9xIRJ26efR7ss7GH0U
tseX6q7IEKlvjiiQp0nnc9LnEROezwSd6q8Hw6byIiH/yaDy82acL2msZZldcirUScp+doOGtwFm
ldSWoAI+oVW/oj3Fk9gqrOCjIiuEG2gB8SSJVCmS/+86cpBD2HTo2yCwQ6YvVsFHqdVFP/CSK+tE
7ezzCR7Iv4oxMk0U0CWGqA2hFraWzaYkXsf2DVebbgB59mstGmw6DPgfUl3f8rXPQokAjo1ChdgG
sylE2tSyknfQ0u8P8pA8+C1NMfVvT8gkJlHpl7R0NcJ4BPRI87lbhJaQhbrTKvp33JHPhUUZaZlo
+2UrE2QckgzHbBoNcBZfurFnSMiTS6tKTXz+v9WS16Q7UfUvwb6p8xuuTLdM/yEKodYuzqW06JzR
sVHH124hPRfG/uURcaCt6JMVsg8bLQgXa1knudSyQFPEYYtDQNehOPEgeyvHjnTZy/kipWn/Z+jd
ZYDX0hgQFV1B4A7G9hhX/rWPcfPk5FdCLHDWYInKW1Q+FmaeILyspDSXqaVUsrEeJ8NPgzJOLqnQ
r6k5Y3BAkGLsx91NWBKuGv28GTR8p9Nkk0VvPVzL9suqykG/Da9Y6G28zyhIm1hh8CCUzOOA2DHm
+4aXckkY40RGgw53dsaUoiN/Y1E5i89OkW3Xag66oUanBUaE/fOpw+NbwGvNjbMYztyoIfFDD5Ce
/AsyyXBhcskBtpzshAbo928SDUZ3KvGGdzM7py95c2ia+FQieS1LrbeD41/PNe7xyrjeEBUfpU4H
D/XUd3nbATtzdSn6MRBM4KmRi+tORkEUTu7IyWzfaWq33elstyzUJEv1meHKA4D6/twnSFCzZTYX
2DNWA724mDKMNOC426LvoinypUX7YbvW7cle85W9SItDlxYMO3b9RJCV8/EJ3udG/0zuMSJmDqFk
oEjd3Joaug2AB33LAfETdJgqg3Vzu92wNWLmlhiK+i2uQ2a86M9pDniessUgkqklpmX85WeDszVp
O2VshtX1NXQUzTwMrxxHBj3vhrvFtTdHZZUlJv5ConCZpAiXCGPdfdXcElk5iB/lBboQDXq5/5wC
+R+TRiEsJJWiZoOI1a3gVoOlrmbZ95R8cFieO7C9i/Rzl0MD2mKkHzvvbEq0pcoJni0hEhfabBTy
wwCt8oV9ia/5cdTLSqZ0ruA+MN4L83iye+C/MjOrSzf9Fhv9Da3HB7KowUgOEBJMvAGCOLy4pvnT
3Qmdeo6Grxov7k5+qgV84eYvmn9+peiR2+i9x1pQ5zAGS8X3pINWjPkAVrloLyIs0yTDLy28N2O+
vGywsyx3wCX+Z6TzpEuFBcieI9Zxb1S0kYBbnM6WnT7ul7bmQs66Yohct7D7ls+5Mb/Xw5/eI27g
dQ79jvWLtgUbeeJj286h19ewLxysTu+5D4vg+Bzm21aQEza06/b7FuhpDanxJt58qtxsm249ruwD
VZmlkzpBEYzOv9sxoCKyZYGU1Jl67S3OfflWyc6nBkaqf2MoayVLw7WDaPPhDvYEUrvbhEfugW/R
KUneQOlXgdgoX7Huo4MAoG3Gwq2snHWb3JJpsnsHCyYAmSMLq6Df9g1k3MDhZMi6APetqWNRBU0z
D0rOs3hDqptRk55fcdYN7fUO0B2OVJXLpcuswEQKkxR6MO+36nQW97a2tqJbo6opSKuA0LHK/Xyx
mi2147PaEPzulI1/KKT8QcuhwxbMfCwyp1jfmocIlx670qpT/MtT7WrTNncOCBl8wljkMOJqNW0R
c+pwSsCz8pGXIf4rJnGt9gmqJRhJxZtD1guBnDA1cxKgLPi1wqqOsUnFfYEkOSLlzcFnZotDIZh5
GM/7627HEqQXiuJmVX/Mu0sufNFhVYiqaZl7RD7ibuGmhOMR/hXPfrBu+4gpPw7v5fiZjKHsUJm+
sPvPKhUIZCnjdhul+oGBcAUTThhUlW/UQAwRHRxUj1nzepcJYBI6n7QmKxSrfJSdnp2VX2L94AIO
jgm8jiRbJjhdsCQP/79IX2QVB/WbA+Rk7mzi21yhLhCN676EmoGxzi89MF11IIPV8q6rchjQxuZN
OWascS5Qg0fjyyCpK8FpeRCPbQLlXXS6rgKPDxnA6E7t9iFQWBy56rilv94EhViip8pgyUE1KjR+
jstEJgq6NWWeJlyF+kjIWj/T7kPDc8VG0/VwGPB+5u9hJSan3ys6by0wry/D+iY8+6MdLsOmJdkf
Cqp/upp4MZwGpgdBoKmpstVLw5m+z6ZO3VfIS8JMMWEETdJUV/bDq+ybPmSYrPv5Y/jrW2QqqS8D
XyUwkbeoGbFBSLoDBCQtilvLfR777rN1j1rh2rb//Qcwr5HqVVyusYc2iQteV9akwS55l00lpX87
X9ksSYZTZBSawM7TvNCfT7jJgL1fNBOxA5TGjfY45ipIpEdXhg5LkI/kjc4e08ve5ax6StlBguEb
rVOP6VQDu2ePGl3sRYiTcGC+9epzfqt/WjCDbW5Qoi0juE4N+N0IWmHfzVuiO5OtqkId5jg7pHcB
8qL7A315JcO0OzIj9iRt01WszH9Ky4z2wZmNGCrDYMm1mo99NO8Nvw6hV3U9GNrjjdM2xslmSE9O
UGZTFC8Tg9b+tohx5FY4kfIyNb6aDhFelChhJO8c5oit+89smeZLnBtaos3nA+S0C+7ex6XwzGFR
B/b7Ks+8zGr2Wdhc54KWGFawVzrSim0v7x1hajyeaKeRCb5tDQfg6fU7TtfiaGrJSV3Dfu2WM4Zg
2SdS37Dkoi2NWjLIZVXkDqir4HxtMy4MGlXaRiqNCxgqHRE58J/miZLdm9Xv0uiXv2uv3aW1bviK
V5+mskqODCr/PcuceiGtn3AFDqMl5dJKqokHZ/mfy3gfNnbHD+hJyPFR5566SQqeiFrrfC8EE9ET
RkIWI/wYSeFCpQzSSbX643z0BI31R+TWcN54OFmRsSGro/FxW99nRaHtu/KLY8r4NCVAc5Vcy7iR
RXo9dGsxzD9UnyqipR1lK6+0apS4gUi8IoGZkzhmCFaUmXmk29jI11QHyIebFCLbwLzFw+cQyyj3
+d1SwOspycQOtQYRkIET+W1uJjebgKJJCUhD1mPMyRAvO6YM3DkimJTcmcvLoFrl4s9fvIdhXh9U
0qilGBz9YzqJN+ZsrQjvJ21dmh5h7NyKTPE1sn9ryCkKaYSpfCLGAEX3C7D6o/jaBO1Jkom4/4Ak
nSrTKbx5hOvODa21zGDCRAqvtyYAJdB6OYnZZz4BQSZ7HqXTvCk1HXhDw8MrBJfYo+Nru/FxxxsE
oNrLxNzzpAKWks+NK4+Jn3czXq7VAOW84B752Z0HvKIqV54xLq8WiohrMNh0BSTywtugMuLs7QAw
XlE5FJ8vvem71rSOhA/9EnLSSg7IfIXjEdlKsZpGnTlbsjiqAbv2O6i3Ep5hDqLbNEGmR4/G+voC
hJICJmoNKLiyWoxNZi8I+pp7i50UWQLFDdy5aMCr0WKrVXnKfUcER+tUNTbrwZWllR2nu82d8ynU
r/PW+TLgvREjHYPQ1QTn5zKmsXQVRMEmbDuIFDhBOjqG0CWKJu8Q/HeEeogS2Ad7021Lj/qEb/1/
f0Ld66Z6lLyDuSdNJnXYHs3TrZ+MLHGX0tyJO/nIH2Ici03vOQGJmVRlmiwY54agn1BNxh6jGWr5
1Xls5wBTQDj2xGGI0khmpzYmoAAn8EP49QdGAu1VoL+fYRaxQLJKYLE/vfyT54TvjMXmgKO28klp
pSJUeC+zXO5FTeWofpxTZO9j80GB5I7HZ047FWBOTlvhUNEuzjTuU5XWfLP2OSDvQJD2Ztgm3JIt
CUtkzPODq9MHFXAlvWk5Sk7EHCEVzLhpXNn1YptnVkQFbTrr4vyJxFZW/PLOuOW1by/6FiGOiZo2
jjEPO+4ym/D/i7cQJavalHrBC/AL7HB6wgw03q2FDAm1E2Pek9W0C0bs3XUekqwa6vobNrtyW2XT
AqlXxEKZSpqPTHB03OmxX0oMEk9DgksQEZzDYxy8myTzUNmlEVeig/6pEmEZr9r2PXNhxKA9qbpT
eNtGa1aTh+koA5fCoaakudJIQahdZZ7tCPi1qnXLeYhSEjcuZsL3XigzGm2Dslc+COtPXDpPLlaz
+gF1M8rJpPnWVBoeJNY/Q6Ew2SDAG9XBRMHBTVX09SmaDWlxiA+QtGcxYVq2jiMSfggk+qCDhp26
DxRGMkV8EnUxHqPQbC0IxaLwzey5gsrky1d9y/WTDUQ1h6HmXVAYacWrK8F1JQqGH4DaiepqStmc
H4LPKkYYOWyqGjdTtPRJ7C6hrGBGFA3Dqzwu5jDlCkNpnynOFvTr4gLwDZ9yGNhteJUeg6FShblp
MUD+fMNSY27SWH3/BD0gP/XG7vLRmDrVFKGc8voE4hsA6kAukiU4/SuBghOasATvtBcjbeLcXoNH
eKtT4yFq5A+/QQ2I1lgG4NPdfZYu4UqVwfnvRkqiXf7hTG/pu76QzsUmLymLfEPYkmRitZDkTnab
IpAWyQT6zAhYaS/U3DiiflR83OY6MX+ClzE5DgjC4Rxp/vRPLJ+JFnFWavvI4pUpIWRKJufIBuAn
tOHuMkBm14acHZQ6rTvgLBYMMeE6Tq56hDWZUzNRpj/1g09YPPSnC4vTd103hmmIZ2bQgicq5az5
TX0ZfVDoQ3a2vOUR9Mrm3ZbUDsSvv3IZCi1aI2yFjBNkHVpriSfO2aV4X9snbHTk1lOzI3NNiafN
5eTKdq7pbP7WN+67xWdJfAqwDEEEYQx/V+rrCeSDNs2BhMf63CUJthBqyLP0LTMgVddlkjxcbhYa
Vc6Ll/qyq9HdWMkvLixlCnXX/Se4jJNLe7jDGEw95O4PnROeCii3+GEoSq3/bFYDuFe/2F++35RB
ELP7og+olADHXBaqXdLqw+Bf+tikzNaK1nOiSFKC+8pJ4QnXIg/FCyD83GQ5/6ljmePFM944L7HW
oxlvNmFvbaCmgYPepaXErJ13SeuQbP9oZQQyit0L3rmVcqwXpSLiA0oHYDm34zzy1Qnh1D/2yXaZ
vnpFep4ZbsS6EsT3B22W/iiNQj9aRbay6RrDsxBViXQFlpK2OpDToQ8owLu9ZXZHlzGRYrQHoE6X
XZLA8d4SboDTrDEVbpBEVDWdsvO8OyGSElYF/qRuN+VkjHt+5dDK0m2tusxfcnQe23buJ9AYfF40
3btExt/V6bLJ9EGjI1CGUlFdOksJQ4I/9ATlO/1c3t2N/CGj+mavdDlkroZZUx+UL1NfkDH0ganz
IYpb0q2gtp+wdAS59oY1CqZhs23guDEc59UWPJRO665R9IGTYrl17+vA7gn98Mkj5sZh1fPtZh4w
SCgX17a037Q4MqNdAnI5k9nYKyM4+Qodk0UwAMaMU/Chv1LoPAHjqBLZRTpirHk0Xqr7qUwMdskM
1HJTW5GxuiNk7k1YTcb9w2j89z1rnQSIh9tV2Luanj39sKfM21a3HPZO3TXyzl8abq7cvxN5J4bw
KEGIdwgHCnIuTLKiDTbgrTF4dgSLtY19kVfu9+XXevYoXJnrprfbbIVdk2Cc8tvt/zZ2Qvpz/UJu
hgBviYSImsf+jlJ6aHadMIa6RsllLjAdI5MmghclAMYV/xZ9g0buboEQISvxrTjNKXf1yqA+ubhA
7XdVkG/9/RaAHPU9kWJ4vbEUuCdiEl58RsB4lavMUt3grvG8imcEeamw1WSGX25Xm78GOEO0+UQb
AvJbUgW3IhA9iBftQZAHT925Raiclp2y1H5xTjJ8U2owFmuA/LvBwBXhTpwjuuSesdoCohovx4fE
IJNJuVLSTg2Ss+xIMKZ9il664JffqJeQdX5Xmr9yGCkCyWGQNCPJMEXTDeKPZRiKjNgRwK9hEdmt
0ynaDfJ/cUs2gZuopZ1CAXjr4cyOZPHUxYPAMkTIv3ynH8kloTXBlsLTuc+eLz0Gbs/kUuxpyJwn
Bsh/Zn5c3dz+5Yv63ooeFkluM6LGN1gki/b3U3aTUOGR5e3aYnWbYytkFJJRNpdizy0qF+hIW8Qv
RZr4W5E1BwvvjQ3qzwTcXo9wlw2e74K0et1kp3DxnVvFdwBf1R5O+PquN1WNh8Bc8lChkHFubuvV
Plv5iV2J5l8mtYtUtTScXdIpLFPraZNyNiCa7hXSz2pGIvOFYquG5G1gnO3U1ANb2gq16wy9AsbF
iBymUyKvUN5Qup3Yu+cJzi5NlFm2hauT8hke0FAyIEqhc6lx2VHfPhJ+u4wqlK4TZKUa1qy6r+RI
0bJPJTeCpG6mp50hIk3z53Am28VN84EZvkxJ2XC2R9zCwScw/srJVA9IPS64OKBMNWtZXUo1ZCiX
PMmMLT5J55Cy7Rmhwa0JGlpg/wRxTI8HY+jA3uKfiRTqRBIq1mSCk6ua0XCJw/oYR4jg3j1Qp9fJ
Pggr9QPayAOVID31qKl4qdwa/ot8KcOfjv9Wglbr+dwhbhaOlkL86f4pSqlQ0BB0lf0iMMHYu8+m
IsRN3Ycq14Xcu4v+aBz9qKV0moPPcr7aMd7NzGO8s9l8dKquc2S7Gfw/1ct0GrTuFbEYdPxigJI7
jhe8ebYAGaN27fmEJ9l+M/6jnaMxcXvIHE50LGZXJ7M9PFJBSqwuorudZ4TO+TXUFAYUH0Tjnv/t
uFkPfhbRmJSrBKzEWoB5fE3Vtvz/iVcHWuGJd9oOq1tUA47Jwj6dQEd9Mu5L6tLCr1PbpO6BBKO3
zQe7zhVd6l0cMS5bn5ivL0YPIHnNzxLjUMQGzhz8SGTaL3rppYC0pD1D4f6KqEBHVi/EK26haJRI
FuGSaUaXQroQ181qvVhHLM7fY1S855dN5+lBmjFA322E0B7Uymog9mOMFnQPrLgAeZjOZ0s695E7
20TirRpGrf8+txN83h1zQwbCxOzZzrzLA198Ips/ADeIfvz+szM7YbUZDgRwp13vUItlRMOUg3LI
C4NSKZxSTk8oy7epmga+Al0DyKvNG2TfsoDdFEZPx0Y9bbmsOayO2xBYGaKVOxYuX/0Nn7sR6V6S
sdnzto8A5vPvBLoMDYBb0DrC/U1qg+5GxvykUwuurk/71+atvuSwoC7ZBEbTvE5kvThKGi0NXO60
gMFdn0z1Ls7H6vK4t2QBTm/YVonWAHmlnTEXlvAIdtVL3ZRA/3v9hctajPwqbrpUvQOLOwi3+ocn
AunpKKlEFq0miGV66ENlVhMPGQhe4D4HwylMjkSjU2WM1WUPR2DQ1HxpVwY6W/l0Or4TgFm/Opxk
8s8YtYuM58qAcCAPgF7vXhsmgkCg6evDSqXWcEISKPmestWDEpU8y224J+hQhOBwU4pN0is9q9+2
0xOzLlnObdLEEtxKfQRCKjisb5wn3nZhmvv0iIeSiOgSpPYYnXA7t3kGkoiEumk5e0BljvHDbQOQ
92aV0m1fx+ZjhR2zPL8C9fBxJ1FKNb7j2SMeEPOm77yHSWMxzeTSEcAhKPC2sLi+JrveTkBT0LNC
wLKcO7KlzZP04rSeLu3VPOt0Lqen4RwKiwmhNaWdf1U7CcsvYN5K9yaLYFNHNNqC9xGHI6gRp7Nh
KPSJyoIDape50ZBSnSc20/ncEmKx7oYU5xk7GBCZ7edk4s1ISGOFQBAMbjTpu3y/jwKyXbyl2Ih2
dQkSQuuch6aIPohsdLMiowV6LCZDtUAfeOrmMk4sq1Nc8UGcuqFHSSG2zjBHA1axoJwpVIOAvliO
MlkF/wRpMbc0fOzSh2TbFYFg7yCIq0S6q2jMz2q9gxNmjZSSPpJZzS8vYJ5+429qHALH1EHxEQ0X
+rRU+vFPgAQRG3U1pyZZeSLjy+uIkSnwBh00C54YWCQpyukoh6oXfiw0ZwpajYoG0rm88JhwpJbH
hpGLtj8H6PWZPBZqG0ap1pya6EHPQyHhti6ttGT6koD1R7pIJbVEf0Jhcp0Xk07K+fIzzlf7K83y
1g/6A0Rrv1jspq2RBqrq46O31xvZZyzKJkBNy4WX5YNO1OGdmJzyMIIdxviy5WDRZO4Q3ObotMVG
9OypbpmjSz/HY0tbsarj6O5uBjTZ13AQAMh+E/bttt42XvdivadxCI+EIh51nQrlvRfQZEiEjf9J
7XdlgngAASdyzDPlBtHuExK+4jpZbYbjAVg697rYxap1Btpwuo/IHe1W5IZXL/YBV34oNDnilYBh
D4Sahld5jx1EmWKrl/5PBcMEd2hTnXStcjH4vJjDOsiFyS0ht9yBC/vQoPCzIxjQZEDw/6Fc0UE+
QO2zsbqgWBmNzMI5t7sDrmSxsCgqK8MF8niSjj4YxEGdltJ4ByD8O4jE8vcsLRC8+wiFC3vLAFEw
/kyMJbR8dLYDoWG814s12feYT3Li8pYLdBP8kLVq306lyaBFrmEbACvtsWk6DqFiedZ5OfpfMJhR
tZ9bO1EbOsPPJrAgfbjm+oRkbC8pLUp7zR2Iwgk46/eU4QCkuuapBIsdS4wx/0Hk4BjNAHz9Fnra
BxH4IE6TMUapib6EfIvQeePPQctJ6BpyQz3Ov1fKOVE/3zZE3Bg8LytZ6fbY4z9QbynD0aP2HTMM
8n/Tt4aMe/w4mFMJyDGOVzflbgXqEhBB3sk9xJBWCz4gWNPHsulRa+ZH/thqRmKwEbK5AqHj/0GN
bybNWpCNOQZTdi6NFPD/ben3bCTMYKLJxMpn8/GAMmNKrKsloh2DFEla53NLmM/KF7LaPdX8m2+R
utiO8f1tqxvcdeTR/igbSBG89ZEDzgMtvVvOHBplKEyl13c/dTqKI5EIoGPhuUWD44C8eX88B+2C
WemDzmSluy3irVNdk2tOsgPEdBwkqdhIt+AOgv9hEEOU5CYB0YJjcGlMpAOPVfd2Ix8ye+wCUCA8
kInzP48dGRThNTHqo02gAsg+O0ipF8v82jMOkbQVlPmbwnlvQ/xuwsVsAdRDrbsXLEppVsh/NrQc
QGjrTViTx7YrCtQj2qgD5CDv699x97vPZPxZyTHKfyZE3K+rxZ0S9U/lK/QA2u+Fu+V2h9EXSpxK
r9vfkxtc/6HdKO1Te05r/mpQg139rrXOB5LOlZLfN+4dD6MPPlv7QE9NSiXNTVnaQaXI78r/21uG
jk/mmwRgvmvmuxlIhKhCMe3I+cxUkQyLN8rNh5k90GUN5ts5JJ6ByZPEVOezrRevuq4Jra2jsOA8
mbyFjyulRjFU416jXDM1ZmwgL3lUJJHK/UJ1toae6mARK0jsrwD4w0ZmXWV7Ffnn2yyUdMTUufCM
uz/Rly5aQhfdME4cZ61BF1gUApPnnN82ChPJo72hcXNmmotOVWD75C4mtYyCFIenmpxSGWi49sP4
KhamPwTWKum3xV6vno1imqG4E6hm655oX0hZ5QhyO0EiTxzse7L3XgHSDXRg5ivgFOGa5dm/vtWm
dppGBlLRWABKxZWzWc1CR7SkL8Y86uXKa94ndrM+aRxc980Zw9O02VqNmdwvuzpXxs/w601/rvN3
UiHNxH1re2s2ddlls3xaxVL/W3wWvBVlK58tTLU9CwTv4pgbxzYiKgehHW2PKSIZ1WLfC2FGxxMK
lz6rg/dSs5FYgxZpa6IJyAfbIcN4wMNWaBI3TEoOYvAEfkuVgeS8nl4jPwRkztxrf3eaJe4irb0O
q84uJ2IzDc515x6JOIxIdW1AVecTWOtEWwIC9T3q9tN0MNMvlac10LocMu6xi3j28JPQrqJE5ueR
tgQrRrcx+uRIEUsjzGKGNm0QpNyHHtd+b/dQ877f0ZeVgaWX9rgF5nza9oVvMEhexH54R+8M2mx6
JB/mkCvHjGFmi9eOIIPEfPrhG+4PUQ5rYdzF0PrFYKYtv+wa8931AE/5r4OYmiT4RjfOSYXNqNFl
wIPJhIOI6v4UR2W9jNuLoPrm80r+eDStasz/5cTpzmQFF8pD+Y1MMQsZAr7v+B/cnaxdK5qt3FaU
Pk4+vnvcIGxLZNNV3WIzPUcMoFdqC+VDOZ0uQLF5biL2ctXOhGD9Nibf4V11lKdrQPm5WS4aYABh
bwB7wf0V18q/ASaat1R+erFyb0rfZQJ1+joJS1Ut3lglLyYainbFaUqAVBzLxfsqQRahOS4QzMk7
17dPj2jMNGyQKANS3FPJ5sVmOrMLIdBfOv2h4Hn4HFGedUBJgdGsCujRx+rypbtfsd4KE6QE0luC
X5BUNfu/GzFU5h051azrs+pzKUdy4dcPIeAg4/yXtLEmxLnrUvj7YetQrz0t+bRlE3Qa6VAmqvO5
iSmRNGueqHuC+j4V7Bp1qNSAIUUzP8XJ54Tg+O5Oz+jB1QgHqohw7Mo4kR6Vx2AjXLJj7Ixv7Hxx
11qGY+7k9wdilny14M+AKWKTnmQ8uHlvR5zuTncjKGyP7GCK9oH55wk2c4lBIdr/+p79HzZ+fJfS
xyffzc44zBfSMTl2DudxuRVmipFrtOPcpKeGHAT01NcnomgEuYyLYuW/yRgVceC9+E6sxVqOjnSU
sIVHlTtwRkzuy9hHFMSdMvCRB3wkMhwPuCDB/iCfs7cx/QfmzoSlZzXaRjCgbWlIP4GJiuYQBTHN
KzLSd9RHYAoJBoBn2xRemtb36Yk7Kg6y7dHOiMK1MEDFrZlXbrySzNuVYfYBT6m42Vkps3to6thk
T3I/GpsefqXqigtRkIVAimv7B9SrNbXzdjr7dF0yK6UBP8ISs6H1Eg/IVkN2v/wRbEuceNfOS/w+
qfhhfwz+z9TulvE1cEB5meNreGYGFFyuiKObYqFy2Mp8X9UQtN7EnwWbJ0WEWM3D+KewOtddCAeh
bVlpK8omXH92QV0JwRzZsp9VDbtHE0Bs/sA8OVx9aDbZgnIWxr9Pn4fPyrUYzLx+fm2DXMPs2CmT
fXD+lJlVov/usPT6PGgD4c59QDZJLixS/C2hX5sj9jekO/KAWe6E6SrtwBhjeUu746OXjA+U3K4E
j/ThIVRh22D8tVgWBQ79zIKz5N41OerkIQFnGI14heIHam6e9+RzxxxGRO8sCInUAuCI+u0fyxg8
PsbluzRcrNbrc/QqM8VE8z4tEpZskJmM8xVqF3JkkwizEqFj39iNd6wJpksQVJ48cPZgnAIIsW9h
ZuPVgzhvbfk4vWKW+B184dtuim49t83LHsFu8Yk0Jtuxl1yMyYjeJbxCMgPRl2k+bnXBEk7NfBDD
px3NsT8BJHYfeZhf1XqPO75626N9GlhDgrF/Q0rdgS3zZYWRbg8XqY+x5v9TDFeSrn5wIY/KTABF
LJ1W2tQOZRMe5qfy3C8vj9DC7Zrn9RPHrIt6OT2HHjZfItj6tlIN5zCGBkXXaqFpZuamA6GhZ8nx
gX2Iru2W+o3wc7F27KJhdJveiCJYXSeHMBGVYdraUwkQywvB8zGvapqhX6rC5lZDsvb7nZzG6NJZ
Vt8Wcijnx6RIS/99mzyZxmJW3y24GVsX9/ox22w3pLlEiUO93bnSdCYk5/SLRxV9CcHgm1jqDhMN
+o1hGxIZP/sM1isBHCuvCD28tZnWPsKmgRw+fX4/5YSMpfOeHyycqII+mLS7oWVMMSlkQo3Ktx3A
mWC21s67/ng2RS3qxW/5LZwWfRG5sR58BaM+TNdXTqNt+5T3fyb2Lbg3iVq2nPXJFbqStbK+dIfO
J3B89RIqvJGTpVtOYjJVS8gT+vyQz21MgD4xJzoIi6X9NRDgoT9/Kiv1HGJelDBtpuL8eCvBtZmK
GGY/yACC8tnJxMxKBdQVkBR+iMTy8xrIfoUY2mwD8I8rS0uwFynWLZMvmoi6ZBo6eL5TPfaqS32f
a2NrVcuJfca+/j1Z+le68qd6aT/oHFkyWaFUtTWMgE+bZzvXPK2L5o/24T9V1Rg46sSY2W+T9aar
YKqFcRqnolI5t5kE8dpixFcnTESUA6k2wTx1oZ1Zn2hC4pmVzv62QQU+VqjeMVkpEYurUlQaCsWs
SbCR4qhU5iZ45blEqoSGin05s6J2QLsuXgJ1s2KjnhPeGQByJ5k7naLfLIiB6DcYWII/hp5NqYet
BxxiffN6GzK4txPt+ghilcoHGThYxbeKX50B+oHw7Ze1QUrTbdky8j554MOrn7VBgsGcCctrhL7x
J6zpZtg8J4u8k1rbEfcpV0FBHIRkAYXYc7lckZMAhvAtrBg36pMFNbYmgH4jRZ8llz3V04cT10Qr
WJ3Tetx5HA4syzaVbj5obZDC6DFna5Rg/86ATq58vhhHJNhfj9PtgUfQ/UzznSAWx0w6U/aCX0rZ
hy32esPGaY7NIYfN92tkmodZbkgoUwVLm0l1Wt3JMiqs2XsLWJmuG99D9EbdjeWROdKAoB6SwLus
LTyvO5u5tMP2gf/2m23NCCHBQnAtNVSfXqfKtLLG6vy65g6dKyD9+8wDnqqWaVJbPvVCQArElYnz
1SlsjG7cU01xaNqIX8a1N8LEt5rD8To5USkIVoV0rwaLiF9UClBltsrHV+PmLqVgsnhiErtceQTy
gUKSufYHseSr9ryBqmfSNpquRodgO24IUCQCYuiwqTBf0URuEfHpushOf2l6WGWgsZ/Y7oNfxG4a
jqxna0XYG9PjGs8Ej80GrdQFMR0yZOOmT13jVi6/46/UNKMiZNVSEGE/7/ihuefuPi7ejM9Cz+eq
dWsvSEIB9clBKO5BnCU5bal0qHGafXg2wn+HSBKawvBUK4SjxF/w/x3OXRkTaShQRmbdDm45+dpY
CGwzhiQZPD4Kbp4HFyb8PYZ9YDIHDf62PA1SiqVKMjp8uZOIMQlUxMitMgZSQ/YrXN4mSFGu7lpg
5jWcNyQmvlmzfH0HckDvrkbats2cfcgFaYXM08Ljle+VnfZ5TQcuizmZf5fPTBjT2RReK56m3Pxb
DI2YAE7K4i5H+YVhmL+zsJzLms7/urDbdOp8zcGNTb9v5+J6a/xVsQ98b+9FznyhNUIjK/TC4WMP
UHtP1yB9j4dZiMOT8fkdOSzJnSmGHhopEJ7/Abe6Tpuq+t4xtf4LAxeNKnF2fVCgwfX63rEyc5HD
EEimtgPCFHTEmoLhH3zlAF27AKkrY6xJsxWDoDquwel+eRjFdDz6fKTgm+VtJrGWnIRZ/nEWUhNF
vYZWjUZnvJWqXI1sw7pT0hFoRWHgDB4E0q1LvA6aZyotNlDAAXYOIp1VgFsXoSmkyJhW9HytoNo6
NlT7tJ8qnqt8qSVA7XVFSnNcegr/HqjmBurmRKVmesX5w72C1gFrANpM6UNr0DWMmLdgIbwczYpy
Hg5PSACLu/hLSIqT/PnOHqE6EfSyPO70CLFN1DIRwKB/RrXt1fKlYeLraevZFVvJhO7lAsi2duz9
0hZyHtfiaG/yLxPn2JrS8kwol8MWB2iS5MIT59sUs4LriItDO2AMDdo/wRGiGtz6jt48FeQR1OBd
EggtjvO2eNGeFW/xEo2rh+eKxi+Eq+B7tKCAmzHPV4OZfAGYwIGEMFuXktd4lBQw/yvvYDf8GM+/
mndG3lZNMA+Dj4s/VDhNkVUeaYDbqD/J+k5+RqfhW2d3gQ1ukHd04o8gKdqTd5MfRdFDKPqDzQQp
SGXM5MWU6C8K8dbhsIsPcuw0kHkr6eix249lyj9EQYaTMe17MGm9xWJfmkt5A10mx0lq+3H4F/SB
5bSlq/q8fcUqQj7tmCW1SopoTt0YvfwEw2g1bYI02KMdgDGY72BqmOTPb2Lb6cpGSHEaJyQtQ4ff
SIu0A4ebPlzF8aXKUttpV7wWxRS75c+VBPndvD1VRdWHK+lAgo/Cm94r5kcXIuEMnv+vlUp4N4cR
MFZbUcBjZMXsa2ld5ooXhSD7x9EJtDKq87nl2pXYnn+04cHtlzgea8Uzl1gVlYGKDrqtOyhJyYe7
TMNvpCheqaOf7wVrqCvMzBC/GYe/ULHFTy9dgXm42J5lMt9iRXi3PGFV9CnrQcbxoQVdMVK6pFA0
KF/W3lAvBEkIQii4xMsE6xocoNlAoJ22KmGRQphD2QQ73vDW7T4K+13YJyBVJk+XHQl8y14uw58c
cXNJkMAU5xC+kk4icycrBRMAXkHaqMxjehBVFcG/EfUCc6SJ1AY3SpSDVVhgY4PuqyczRculPXFw
JoBmHGwkaB0ZbNuRfImKjhTKhiEI5p5WpHL7ad7i9iTVgQLb5ul7J26ly5VVG2ep7sDp/n2JXpl+
P9PvZPL6/SZq88VThLUEdirByhrBQZZHgA1K1eYPm+4l7xaQ0YQwg4nCfUQ+BZ6CUbjqc7E/SNU5
9bis+iTtuQAb4MMvAS44VvHyjW6sZTladtSzzWnlU5IFf2gsMeQ4r2MXR9h/BuI6dHqzpns8zv08
cVzC0JbLSdEZ5TJ9KPvTocNs3H83KU2pP9ncBZp9EPoF7tFHjhrGG15l1TmOzk3Igvrv3mOWwQcP
doZC0ZTnCe1is2Od9tZAMJ1MzE9/+tNkxBbaJOGi9ui612KA1vPvyeVuzzcHs7PdeWOxc2Dc/jVC
4w+Iw59rNGUiI/FsGSX8PZORcbcgBSsSA4bkj1Jleh2pYihxIndGj53elWbYCK0sO0nsLFkU6lj1
WujaCWnUGzGehI+nzzjJTCEQcCDpFCyOc8OyuHFkOKEPk+/Y8nVB3qm+l+X2hoqDUjqFTZMP/NEK
6j6NW22UK0fdnORTqk09HVSl9rNO3UCotDIHXdmz8IVCty2c36cVO8fWKhAWSM9xDaizElu0XNgJ
HIMBUrPoSLlbzzcR67eCdSxRVvsPMgLQmA9D/ZSpCprxNZzCp189B3/1FnD2wMeA7T1WiGH8LdEe
fUN1VElGPFWrH1PR/4I3dJe8fkAq4qgwnsUf1Gc08m7gOKQKZXPupQaD7PqkMpboZ+Q7QgAE5qFf
FguEuJWNFtQ4WwmHNnDftp1DI70EfgT4/G2ubaw8TLWO1sbqYcs3Edn9Q52oTrpSOT5HB0CsSCpy
oFVsKVKnBfQQTzJxRrkDa5YBqWCyF2h8jga4o5PougdYkwg/5qeJQVoI40p+m9yi2A25X/tOa5N4
lNHxdjSe3PYpZCHiAYxMOlfeNAipaFHtvZEgVzEMsA99dHl4kPdXrcF7eIqaT0Fpc7bm06N57Gf4
LuhS6Hl+8CR2/Syvs+GqvqjkNU7eh/+r3skisri9X/t8H+1vr7KIPsH1E8crV6n9yCHFCTMwXynr
3/x6hTCng82dOol2grrWtNFwCzU+RzEHdhuvF/S+eQGF+KBJ/ANf7MWM22J58hQ7H4Ja2xEUf3/G
4kxG8aj2QtFsY7D98RiveyiU/zGNrwmQaTqjK8RgzPDxZWqKuN3IbgprzzeTC3u9t6ePkZw+6BdZ
0Rt8ACsmGk6iX+WJJwzhxIhWKHFq7gEaVZWHAwNgFyL8IMMlmFoJ2EUV/LO7L27dVOLi5RTyJwFN
62NelQ4Z4w1+mIDXXEGqzvyW0ohnzZlLZHdTVEXw09WjbepiEfVXIiaDFKeKNl/RtJBP7vBChJoQ
0gatuODta5jnqxIBZWJ9vtgscbiBzBxUJzjV0oiA0k+oQEVzhd+E0cXVZsUammbGGzo1/uKnRzWS
Jn1QQsT3FZDOr5WWZcbhFXfUA7vwCrjV8S1BgjqtrFkWMot4/vwk9iuhiJfK+EF1thxddsvDi28U
5k8S8uBzppMEKpR1N6qcjr3vwnNPGFIUZAnXhxUbODGXVY99KiWE2xwClcWQlpwtwrouXDvn8OEA
N1BLd1Cs5GEFtp8ywkkDhNeBbMX6lMwyazFtLUCQ/nqW49Uy0Rv+bMlT9AfyCtyd+T/p2qZscW8+
1yR6ZoBps5neZK7yU5skH6HYpp/ylx1pyuUusCoMexK6IDxuDHDr5sAQZ5sMUiuURv1cDkWVuWEn
+mSTNdlrtZnO2XUKs8EeZHdiYUhFO4pRnksL1gEwYKnbqxYN+5DYmXBIw6Olr8zr+2WltVsn77bV
4b+ZYv3+DgFFyM+11Fl1oXepqg1ML1QvY5kZsSbdM8Iczihf2MA//j0ua32yMTvGyybZ2/27X3oA
NOesuKwlf+P5nrXey+UkC6t1RJhd22tgAGR4KBOxpig30XkXKjAVx5OWlFrD0BxMCtK8yDew+HCX
EMEs+ZmecFkjLLf5e5nmQdA1fwBU/MGhXvUkA+TBmvR7i1ojyudtU65B9yEi3cTH+TYgDqqt9CAl
+B6ASs8q30ZW3eErEbm6nCYyTy1ncV4Fn6OEf1wSnth/y3EsJZTcxkVoNEKgZNh5J+I3yhWeI5vc
JfCgrGbmx+T7u0btgniJa6RomrOSTbEhAwVmdpXI6WYME50GJrM5pLrmay5xs21vMfT8y3CeUkR+
A5y5hoMXXGDSlSttE80+QnsRvPXgC1GQp2ZKs4FDEPhG8c3J8Nry1pZ4Z+IYosQXuT9urwOLhjL6
0EdaS9165WGPgALajgjgjmMwj/XwzFiBFqySKvX4JTLavrhGfEiC3TWfinRkVIcmotLBq08sWyAH
dH0Rkck8MNX3SF4gMPebbU7MTH5+/suHTwLmEwOMqjdhbGx81lXdBI6SkkZ+OjeLQPWy5TulHxq8
ucZ39iKHu30owQESOVmMVZRrgtAeex3xFHS03udFL+7/MAG0YC426SKwN3swwS3ZxxhBxZq+8DcX
R7VTOxDBZD9P8IftNQCHKFnUuSSuqXhW3rxJFqHUBC/irVa3DdYdeTYC6JHVpVa1v6yVZt/y5BcS
+wUBg00wDZUdM5YzOZ3++IksVlTfWRzTpIiAazwIv68IVt7d4zyGLPiTMzvWLF1X3Xw+a2VKdKST
h0YfFgYUhQ2KZEwG/9ZY3fxp25DheyYy5DWIipwWUtMomP/bSJWSiayM3I1frZq0+ygMK34qOO3W
gKdsDZmxji5I9VgYVQprfpRW8iYA0MEe4ixE6Gqq5OnDXjQnmkB0a4tX+tB278aIXGC9TLkJ/X+e
2KfP+xR24KC6zLMA2gEUa1GAkgSlFf0a21FxmadEkIHJ7mZaGDjNBMCSwqXxrRg7LF6Ca9ER46Ye
PluSXHZ0FYB1Y71JFOeA2hpUK+mJihcSDILq1LryL7c1tdWjbMLlEOVJJsi6QjWTMsF0X7hYveL6
NHRC6PbFckQEOJ6dp/4UJEneS+696h4xdLG7KNxtxlC1CZQBNL2ofUonsgXrmvp89rROawjUcdZa
Akd4qDrnf+EhAJoq9a2OS2nKFVb1e7MppSFYcQri8OcSpS8cmIDZ4oTh6LBBQkhTrfWnfIWZqPxv
xT4bsJ+9+I2uTAOoQqCBfz9UctIPN19SzE38RmtASDUHhAJdEe/60E0xZExTf0R0xpIKkMGhxJjR
wasl+rmGrWM/m1c+SmGRCJaOx2fjvYxX75WNMo5O+rw8Pmdy5USmPC/5iywOPn+6PB12ouWJhhrY
t9QxWNXT994wREXlaxOY8XCDIaLpfpp21s0AZpHwF3HctDaf/uYTuQYQdWR30olkSYyNAiRwoCeO
OJJmjKwxM4dC1sBf0nNsrx1ZfhrSBxz1yxGY8SLBh8ttAwLRYfqi3yjXSZtSZ90GqvJ28WSz1+87
VEo/zoaPZn6CAY5L2rDcqd6Gae+VWqcDeA+2lRcttn97z+6gxOxGLQZ1L7UdPKNjw8PfKAzVA1vW
rma69K0fKtqvCfQlD/C25SfdGr0bpqhnWFlDARlf551t+BMMZAul4GCyFYROGFCBP9GMEFrl24AQ
qQEzk131dsZY2gU3XfKOeovKrIt1kFHPmuS5tweYTkQ7hXAvH8+JQVcHWHWRAA1g1zPze4QHbS0z
EWtPdEu0CrwQ3kchmQ7zZKevxqnZFn1Vh6l14HjqmkrM9EjsMDp5oxTyo1rDBh60PYp2SjyDgshq
tL08pm2+jrBs7LLuNoSFh+41YKf1KaLeW9CL3wL/BRQwwQnCLMRwhAA8q/LsAybHok/GjuNuJdhv
JLmMURcH+OXnZxarKe+vUMkOEWvB4zQpIoQa8D9VcYsjp8f1iYqYDez4AKCCMwLekORCpMAlTkDV
sI3njTII2PXj9UTqtYIUgu+sfV9xhIzus+8KG0/wuLGByrUmICiVaKZu2PaULfpcwlyWtc1x0wXC
exH4Iz9+4/ttN4Thp67hChoDrU2psXJcTqBc0mNLh9JzKDKJiToQKrqZgeLdPxZF+yXqKBQpDNyC
c39KR+YVR3+NffELv2ySDbJbovFPkW5N0DBRK9rqO5g8YzP4eaKhlo/aGVAjaK8v0L9FcYKqXVIT
hsFe78oPL1/1lP0ulDj901FLw+XcYvRi7KuOA9m5GnUacSzLG3R4Zb2/qmci3I7jwSK/pVvbCrpN
IuZW0Mtk1EhMFHomA3O70AKFkAasZCEoMtp+R4aNfbcpEDsTwy3t1CCk/WhNrcGn3clBQNMBKZg4
5h0C32Ahk8YVqPJzduZLZv4/rwIIAJa+vUnWPHs8MjiRjhtBAcaGEFpVpvtHEBxCSntKfg1e7jhB
Y1lxqW/2CBaEnAq4MmS811kkOi7Nc6RbSsOiH0LpvmxplDKLoqoJ0gEJRUXyMpmUkwsZk2z8U2VP
MhBKqEFeWYj2DugeVnO1blwdrcqGkbNP4uNxy6QdgPao+T5/337oh0XqUxK2sY672b3O720xkaUt
2cpXY20+DmL+alPfMJUxJleET3mte7nym3Im/h5e+uymnjmp3t5etvaCddhimkbONakQxeVWeY82
dKiJTain90Pm86AKXYtOflfRSggUy+rKRhdF7iuoOfuNUDvadknGSUGn4KU2Ddfp7VRk/j/0Xtwt
Mxw6i2ZPgTHe/O5w1BpZb40PSqaSYeX0ywdCtq161vggnNHwcih7f3ooI/hpdZmWRwo2/enpkg+8
fFHOwT9cySdx8S5OpnRY5Lr21/rIYRZBVRIcwF0oRBltpOnB342sydqeR0Geqp+fTJSs9JEAM2Ut
X5veHllAwQjaoEA2qO4fiWlXcnLUEjIbcQxwZYgQVEE1d0RlbulBk0OEEdQBxiirbJU+uNtbNULU
vmz0kgdGa4q7OuxVpqL9nIZUV7N1lpxvKLAGXBORPD0KJUGeOFoqwi8bh7OTg3bBHWUqhfQXbIKw
fCdawYP1TXF/KfhnlzFcFyAFFPtzsK4bqko9kymVvPTF0OD6DXPxta2995nxmK6+sc/cqe5DM2Li
vBONFGEuJIhFbgbocs2y1Pm1pZbwWy9sjNoXpp2pyBjB/ClomCiHTsQAxYmbNwdkZgNWyYdjWvVd
BCW9WSe2YLqr8Ii2uUkgP9oOfzQImldmtoneKN+Oltz9gHpqz7J1XYrAmSsHujJ0JTBjxYVZ29h9
0YaKjLPqyHPeKOxVVTE9zwcD88rDjTKgV/dTXa/DKDBdCurpxMDaKQHDDgiLmy4Qd2r2ajGflAy/
7hryuh4Lr4Xm3FWCESqG2ZwrYcj8NgBFQR94ouTTxbTO4MiFvcNtOz7f6JatwycGkkGK4KtVhr5i
EJu5xokljTOMvadGJdmYZZ4TAcY4Ik3Qxn65MGtJX4guxFpxJTwIuqza+kkTeq289b+avLshRi8H
ys9Mq1RX+DQCPJYdZ/U7q4e4g1IYBGwXrvWRqOb589dIJnvOiELl42Fcj0arHxsGA4PGA7J96IXJ
Cgy5apoFDTgMhSmCg3nle1Gvu5gm+2Ooh8APLRo1vE+VaR+ZyG0xqj0UUhyiuxrpblK3y9Wmxg9R
DaZrmj79myvy3YFY5JQ/vU6S1OyKYIMD1qMLdCazEnfipuD4TLo1CoimPUkbtu3Gu2kF7/Lv9gtn
jKLo4of+xE6WDqnVjIXJefqNkCQoUWztHO6RmRvqOVvnxSSX8QELnx94bGvPdCupsItTUQJqNMiV
W+hjn15HU/fv8hLGuKOJ87NDMK3zO0u2Qkv4aYAhFVnVfQWmcvV/3bKyDUIJ+3ZrY/nY3xmxXMjr
QQxg1cyfKdHUM/Wm0E721kUgiDsYyrK1ITIq2xePl2qFYmq6vRTi8cS/nMOoDem/pPKqdgKyyuvE
SbRyOcrTgUD3rgqOZ/j2PGrBaeANGFcMRwgjypAYNJpxwYNrJ817Gsj1CMjqmpvEVeZ3u2RppWgd
YLExcrQ5CAkZTRVxhk/tGQzpkw3O9/DiTMFvSAY42C7xqcYIulAgz0xPsM+YQujdcsKX0Lb7uFbv
MvlF8DP5xRD31I+dKvAjn1uriv5VAIhzKWUbF+Szh3Dx5a7yNbw+N/BRfDbjfWigXheKDbWhK96p
C0T4dy4ocKKVggROfBh5491GhCJ9m7gP4wULQaBnYmgGmR2nj7Qa4H7VGmse9gcZwrsniXUclZHL
Fbsr0ewsi+mhDM7qXtqGySa3parAPgF2RKWlyxHznkcOh04Y9+UsO02T9nOgWHR61Pxw/fuzkrP6
gmiNM52kOqyFa9rzLfeBUuNyGVE3UEzHvFCfv2V05vYZKFZKDTT13pXMCfOODDt7tGN0bFwMUGXW
2HiiEvsIfKOjzc45G2DDlplBzmXlYKLPSO8BEwSbfZevbuXOJnsFafVKwfoDxHlrYVSVgs2xMVJK
WkzJnZ7lZNMx/vCrowu2PVugS6+R13541lhHUpWeGj210XWdOVWFg82XXMO79LmmPzAAKmzvIcMU
wrEoqAjSivBEHoFu7Vrw843ucCAjj9mqCzoituebE79EeDrUUeXYIfMGiSYodrPaX+issxa98Q14
rVglXCVgaohQLWajC8oVPe4+Z3AmxDWlgtuNgHZGTTvspPSnXDbVIfcxjZRKOfaLM6HKhFfmqEq7
MnAD0wglBIAUKBU71+zZc62BwTLMF3z8IGwbLvcAy2QFChLhAN4IQYcuUHXqHCRSgTwXw7wv+Qht
SnMcs0TL/z+CNPONnWCJeoVEGI+FHrqf16g+r3g7sDkFHO7VmoKNCzVATVYusJspgkWBl2PNyl8E
/8hMreWxIPU5I/qarn0mjxSyQ42icQ+cBdS1RHIbqKoPD8JWrtCZB8xc8N+skREFTkZpKSUBr2EV
7CWokX5tatDXTZ3N0EPnth44De9pf63XQ/4UpNCsmYj1xXNtQ0tZXUyIFZyFh0C+r9eYi7BM0x3M
Olc5JQjE/rLh8KgGONCmFA7Hu+7kQmlTUfxyGAqKw5QCixSlLfpKIFvMNqpOMr622i9JE9/uvN2b
Wb3gsT666ffFVSFDCFdZm2ymRLuDcR8jZmUQq2SrJ4MYrS52j3VP7u0tdWo9msegK4UVpMjorZrS
EHPIDyfaB5oEy2t4kK25tkwOme5iACvFSHVWvPTdu8JZoxl2cLA2lLG3+uL7GA+jICzsvMlktKY8
wtXYKmfczBDEwB+8DJZXsebd8dhYDD3gyKKD0EwGOg5PCzkXBB2EfopMWxTnefBelWWN85h+IG7Q
cBXUX9U0kIQJrlFeyBKiHNMEUfdJBnvl3ezWdPYUDu9hgFsY+hSJ6zpZYwW5kWsmVfwjbXgaoImX
zsGTvQrjQWuF8usxrBTRtHHwtSvo2gVIAQFSy2WEPgSmySB7eAYSkIiX8UulBQnHYmsxIEYe+x/w
oEs0ZnzBbQD9BmnQ24GwKZF2S8rOxQW/BG3Je5/mo6NofF+PlcBQJNDsbCmr+yXO0shW1ukaTvL5
LU4g8vmr8C1nRdnmWF6ndKbX2pL94ifZUaKytGmcpN0jlZQA94idTGlKcvJH2abbUg7up5lvwZMm
VNYPRzQEQ5/4AumjkY8O+fOyoWg64B6k8JB6en4pZzHVMlxtRJMEG9vJUTgqCUOb6BuE0WcHxDXC
SWgnBuvq3+gfkUUbvYKG7uXo/SoaBnSakbLzDjfryAfiB2rxTV2vppAUbqXJUPc+DmwvED/jJL+C
m01I4yBAGJ9LhMKDGuHwwv9yvHPRleqICZNJfZhMXcUjPOrkMdpg1ItvzVzq1vP6AgNuyi6SEkwR
QRNyN6vhSGFcx4Y61eYu7VaMvq5+dYYU82xMH9k5k3Wsz53VwZUojJrxkkfr6JJfDFHGKSpY55Sq
vRfVucD1dYvWH7A4lPxMctpWdufgEjNE7UmAlhrYKZUuU9NvqHefWoU9pEBzPeoFvfami0T6RYWB
n6U8wFM+YOMGbL4KxTSZ3zYMF7963AOdnw5UgMhovuJpmRZeYI0KIlBzMJZqDyov/pbjKD4LhzT1
TkiETAYLXOyv48l5X8ilSDmaDoRdo1qteJ+1f9EjdG9nu1QUecCuHmGFLW+Ri3qEt4XHyGvkgRe8
IFV7neH+Ox79iGC0/HIbIqF1uCful2wCFzWpqN84vNtnOv9lSlzVzivAet6h+UN5sQnEeeYrXIoG
XOylUlqo+nLpLrmUJaslI/1hqcNCK24UM+0V2Iifi10Y6EK54HwEepbtASdGsw79eBGQiPlzGwL7
EHxyjZ339jdYkRzYBkfX0+nFso6CkZTJ64y8UBItZzZEQ2RxldzKzXwCYbD4Opn+OreEBltFpl5L
O/xo2fKZpVQl3LX/IMzrmiclQYRSZLU1KMVlZtPcVJxu3L8gypzz/ePPO1lsZan9M1e2gF/7syVh
YqOUY46rpCSIs8b9PRqPXwjc1MNhdXgCUR+2ymLbeZ3FgGyyUK+2UVQQCS25lvyKv2xN3PEQhKFo
sBOjyzNgi7gmIlg8emNAzUnbc+r03gNJMLMAeHdpiXa+rhscX5Z+sgFwY0oZ8IdvAqBBp54SbYQI
18yO/zwx3RKmkmmfPAs9aM5Py8EOQmnLup2ANqs5G/MMW92RhsadUK8qPf6BNPeHxyJgd6JqPXTy
fZO7eW89NBgDrBpojhYPsQLvYCzJOQEQHkbbI44+OYsepEU/TeMaVyxvtuvBqY39CHwmXRpXQ4O6
p4nFGYZfxtohgtB3TWTrEUKHWyEucjkKI10FY5h+uYAUQQ98Px3Y8UOlt/RD7aZMcC57hpjiGYhy
0Ilf5wtsC1cNvk5WyKPJTRW73YBErcg6q5+HRLOJzd91oElM2bO4Etv5OjuK/Zc3CUf8CIhHsJ2k
JRXyXlSQxgUFx7jiXZ+wXy7t3C50vU5QabHrCUnVl4Eij2hEuUdw6wpZmCSVvmvGVMYfgzLBBm27
4RVo50xLUMumOZIxFnM7G5za9fKjWxEC6gmQlj7tFLdY27OIFCtmrgUwLNlySvNjvdmvUUsi5vSN
5eipbKCKclL+hbnLw/jH1o79G/mVhZ79m4IIPkQmA7okHIBKiJ4OlQrXoOCiFZ4i6WpGQ/z+Otuc
jiJsGuiGsfCvmhpIqDXyiDPua0RM/8pIUmfYwaj5kDiVlgGgs036m8zp5gCzKJVyDS6XPeJ67KT1
7oCdjKRF4dkPysuyQR/1bAX1U9HpAUi4boPAfhdneoYO30p8KAwDBF9roafUj2tOs7tpoj3TP3uu
dt/Dp8TVjO8PgO9mFLhalmDEOia4oFX3NNw4B+P2iT74RfJOJD+O7AJBYJlIAf3SM9CZ5YLfhT4q
SXm9T0j3VvK2qPPF1DH6WMo3qLDclSYL3/7Gc4axmLvpzUrdooUR0Gow1MdY/JB/IMrrC8x8cZLI
X5kWOLsYLHFiCFguREq9ZQ0YYEW1iqFNpmL2KyGsFi1VnfbXJxqfJF9ChJvYDqvgGSgNgGheKJ4X
Z3RKu1PrE3N49oTRnhjW1LIEcSnmmjBJ79oyJXVXm9+WvxWUNxt/duOnDPshiNuBeB1Ks6m3AfFq
ipIKfDC+loxDV1wujn0hizMBAvWBW/5WAPSpRGjXtx58bBSm5S2/7cARrKjvZEuuu1N8Th39AqKB
LRMjvbNfTHfOHZFelpYecKiihnzbcJ8XCZg6ET/B2IeqpXPBVW572Pe08dA1lR/tfPpwT/W1x8nF
zs3uam4IiDFzFnLYKv1PIvRLkRO8WgdPO5BP4DPlDkJ0sDVblCIDHkl+kTw/eK0E7Xe2WSgK9WgL
jR5hKCKReDnWCXSjy4ciWmzg59oVpTuJJ5WbFCgA3dtfaRS1LmbpYzMMhFsDeEJd8Z6czpP5z8Ia
KoBf41cGEDECWJ+GAxv2c7qEaQix4f2yc9OtzUBU8szoSvpr5B2puQhFBcldEDCehGqu5EgtGVGV
D5MrtU9QcbBZf/kY9tCUYv9oHMoK1gTTUr6cZ4d5W54tfptFzMGskL5HIKo1RjyOXHln1abneCEo
IxDie6jneceL6exhh0OZRZQtwqzJub4N1UhH7UYuTTRQPe0qh73pjBXSukxSXWuks5lFDBloGSsm
V6b1g3KQqMRlKPduYhacMhmAtjaLo3XTIlfwPgC+7K1/0mMkIMJO7M+bnp//KPAfwj55X7wRUXzm
roDHL0nne0IE8DUwNzbfDK6JAwKhLG0XCT0mnkJtWDISIpjZYYZKE5P3g6fTJFUROTjkmNKy50M4
DPcV5kAp5rXuuZ9b1T1hc54Do0itob24tnJ6deLSebHgyP1DI151QKrJ+V4fZpKN98MJ1MkPYLGV
r/bt7eFhBHDN6TKxMcJsBloi4Tf3sUw+dFSaflsZP08yf29rNK/HEkDqhBWanpasQevth2gFFBhx
UKEt/aL4ilp1BCgrmqE253wNIgabMkVV304Js230JEbF9ZllL4x8qiRDrHz1h/QbpsmGFnT1hDVn
AYtTzy7n9vw8igvM9H2TSnM4hPJaRyqRFgHpnVcu+IJFmW+Dlk722suYVEDvPyG4Jl28FZUS5L7h
MJvRKueBTyfYaT1W+/u5HTl8ncCziHIP+gaXxig0T05Q9a8Sk950xzr8WomZMbcd9tQsqdH5LGyz
q1SVlz1F3nJIeaXdKcYv8L2OaPnu8TPfblFrENQOtJExElGzg1EWn1XdflZVlT2ZI1LigIFylvzI
AgbzCltPpLjXpiC+UpRFjwVtMj03xVV/CQGwPL8cy4x9IUmXYHuzj2FaAx2rWN4LFcfKG8QiWF4b
R90TSFph9Wqb/1WDGMUpCpaipEVnnA7FA5zLKnxRVNHq5TwGR2z2DxVrF98O43t6NbfVdrKdFQ7u
G6rD4qTVY1vvReaVoTuXOxa5MY0syqWgnZm9JgqI/u88+YMNQ758y16EtYeckOQw2UJkwEY8PgYl
lCz1L/tKtbSEsc82mkfzevMKQkqEK08H/oYjQjkfG7YdIHTuIQp/0DNLjJV2TgfK+NJUyij18J3z
VqLczhKw5H5ct0rl2Y4XMR6IpXtR34nVJAq/H0gbJgv2DbBM9weAfcfgSITEVUiwQcKoQ7ATL4G6
RG2eU6NeE/W87MJe0R0uO6cN//sMfbAa6qw1SsRBwfpblydE+5Nc2ThvVexPUexq0hN6Y5eDAQKj
n2Q8tVF3mCpgJVBAtZZ4J307xjoFEgzc9V7E/1zF0MUw4drsH8tv79RglF5AFmWefjOy5ka9cyc7
82P8ytz86py5pXpHhpebWkZAR3IzXNBgt7mmth8+KKptfu2CvNZODgDtuH8qcmGKqR2sbTMYvHhN
UjXRpfE9gZqhM972KD9stXUORhDINy10brsmwP3TK/vW+JP4rB8dwSJxVAubTEh2kO2/r9SzoeMM
Ci27+mhs4fOUzoYgWX0bFK0qzB7AS3eQz6C8CoBAzDEpxAPTrMGebPLYmErxBRR0Vx8SdyxtrQCx
EosXoXM529tphIpcH+08xwfwMvpUNthDJMuLWn1ZASzpAL+zJvK92ZTzwy0HJXwAKcbasmZQjWAo
PiAn09qBkf0YQsxa2T/X2eKtkSSm7iYMn4iR4JVuf9ZfFlA5CRhUfbqCP9zEaZjpWbDNVtubgzHE
WMzNApF4ITUsLzAZIehNU6HLXJikmlW/1yYd+oIxm+MJbhOglHnj2btqeSNdmQA4c1Ep/mOk2fFh
1n1fJOaAxQNuHv8Sy3RGV/+B3n2e2kPYdx8pAxED//YOpzJcbwEVl1BMyonYY3SBw9oRIIfg4IDW
b0E3etD3v4CsseEd1B6XINv7xFST0xQq1ELb7zGqrDIm6uT981pudEoz+9fy5QB0m4q0oz5fbGtQ
U4Uggvo34KzkQLcFo41eoMP8w+F1X0OtSyLg9ZB7WKD+gUe3PJU8IwBq/uT77ClJ0xIyyNNcaft9
YcA1nN83zq8kkaKckf9b3MU59BjM6EJlleLtpIAh8FA4CMhYnm2HAiR1VA2Uu8oacNNGFtG9BJay
CbszUOAVCG4MPpnPAWIixiI8sJfgssPq3fKPRaxavbCNvCKwRQhv4vtaKERMhKo94nE5MmPTwUNI
jU44IBMFaANGeA8hG+/dZetO9zM7NYOXQD0c4IRdrt1xqzcf95ovn74kGloWaHG7Ca5VzFyl/g2L
7YSd7f1XvZrCacTd3MH2/6B5JnKijwqOThCkj55fCaOYSTkhEv/bl/s2cDp6IbRmPXvIdvfK1fqD
RTpidf+S76ZlJ7tfUROS7PlMZ7zlUSkpOXfFDtMH88BmQ5ygjNY7opGvyjhnfMaWVaOvf5mapUSB
9oy4sHkeHo3xHokhMXakItzfKsZhPaXIxsPBSUu/zPgj//TZbnUvsxYn6XOD0rn3xr5LGwlf90I/
OXAS8f527Oo4ti01edT6KkX6AieYSbNnImP4TQN3p+4CBnwCRVA7f/jsJ/Ha1vNVWsk+6nuUqv4X
sBIj8n+GL8DzxMu+TZgE4foF9qIOaNvHZqEXUvDowahmcrVc55MinuDNYRcDdpJFVi1ovZASFkDs
8ThWaRFnCox4Cqpiumjd1mzmupE505lGq15/9+ALY8ixteovl8nRgXWo+LOhU3PqB0Lv350TzeIj
2G8Qp6CWSdo2wgaqEYmh1wqkBH9wUIJxxwQpt17ckr361Gl72EhTG7E5leonj10oiGanz8a2HvW2
zSFNim9SrOxQyMAKwVB5RQRCeEGycosHC4m8IbNmomxf6I6STxFZLnVYxS3CRvV0K/f2sAoJMZte
ORFg5U+ERKxRtLRi57B/v3BI35XogNavpzFEcwenHaU4GxkoK/LarDWPe9m9gaYqmTqjYN6kl9Lw
4zYgqY6OhOxNQ6AM+h8vMXzCh1E5E5gSvLFu8ePNiIC7RS426yuQam+aYUwC1uFUZPt/TU6TcpPa
+JZ1u3UIrwLH0HSGvAmeFDEw7Cd/Dtn2tbUKoVgSRmj26I9a14E52ZbM1c5hJRyXvWbQ1L3bVLCJ
PhY5SJnOCqWyrLc2WUIPb1mT8ud70o6fTKjTOmvBey+eVj5sfNlCUbq1hM8oRpj1R7tSNjCuQAnK
A6YveSoLBy3nRKB4QDK2oL+0vrA6rjQgKdXz7BJef5eBdxlpfqOMgf4h2uXclsVinL7Lg8URGGWc
nMKYSB5S7GvuehvrVHdHkyC5UjNqISqD5v22uggLpsyqaBTUfTxysh9MaWDLYjxavbbjtr330Jr+
FHJhiJDDfPdoMbTA2SsXDFvoOmk+vi+VuKjr8WYjutitZv2ZJbh25CLt01chARhTSuf+1KjEmAkR
9B8ahn6Z9kIflVpLPzqgx3nTpDG9BQGWidzMEeEUhIs21z49U5AwOU8UVZftTpkAqiGVSH8j3HBb
4znoCAHIPzJv+l7yH79syNNvns03MoMhwBhaFbStvll+VArF0r2Qs1zVnCo8LCaC0HHLG88EsMRD
iWcPJJVr+fG4KsVYwPlDugGPdiiN+EEHbCQ/tCNzUXdqZIHzxoTDct3PreL5Iv2mnfkTkNiDXmzf
q2wXeHHfCTxO0TmK44jipzIHpTnOrMuMLp/Wx19nSSqL3gdTc4Sw7COy/4NzCmDkDJUw+FoOIdou
1V9n8RNrb2dSCarOTfInyu2kjGS3fpVN5T3a5Zj0v0WBeUdMAtsEbTgd4SVNwOuy/NcGM7Dl/C87
RfWnqJGj65sGMPaoC11HuQ15ubOcVIv+Obc2oFk2FHutpbPtyLiBF4Oh2rMK4VkpuurXoqqGJqN4
+3Qn0SE9+6AOUs2It3uvi65pAZw8/HCxn7ZcQ973U8C1ggbrtecQIOsWHNIwZcewY2WkvWSV10fi
0ZCJiWUiseFMIl+LfcJdkhRQanGXTvIHbb8SBfiqEEIckWePr0drw3TpbzdxD8R1IO5gYZ+xS2aF
WTJwgm6R3r1t5dKTFNn9p8MbrM/m3Do5m/xp3LVdWixSQE9KHPCHxdimg6gux6GIbBvdi3HLGttq
JlXA80pD+1SV9I2zXuLt+dL7LHnxLXRleQEutThDmUGLzUn5ja8BVdCFt/hj8eQ9R123KFE6rzhs
OSzV8jsamzQf+jvbwbr2qF6vg8/AJg8yrT5HD3dIuMmApsh4jewjSgEVCbDWGshziyUpQCRcNRTx
eSP0XYIOQIscEbMvE3v8pGKUeuAKciyMALUMJxCnTPC6TEvh0vMvByY+yTlr6o/KoXniqnG6EyjU
WE6eVoc7HULP5fdDBc5e83BDI/xn7IzggBdoeyi8sNaBF/GSVufQQTRjL0KXTq3iREWWdsjkppXa
iAbghF+HleJBGqBowqaEsbuBfbEoTK6l2jpuo3nFkEZu1AJ8I0zkMFgeqSRrBtegggTI8u4cnhrk
YssuPcYY2EVCHjl9KpFS84qJYPyhtrPLP2rkSCbjRgWqI5VRHolNx3S5IzglbF7sV/+dpmFi4ahm
FLtixXXsyubs3r24xjVRVgJVaIWMo+gKfdsp3NaKDnTTmnikqUKPWEWPbU7tA47L3iLdhgvO5gSf
bdu8IlMwR7ClHB2Ma+BChmfkFaWXWJU5S7H+36Jq0XEhdPllQw+jKeABB18J+ng6PQfLO9C26QMh
lULCHUg6aan7tjIz67JadhEeSa60EG4fO+k5Hb7aKFboXai02xPiz5d3c/8ztp98I5P3xQfGNTGh
/OOSi643EV3uJKQS7qEWemWmo3AbMczEspMhJSsM4Fl0QR6k8yI7Oc051wx/WkT1HCpvxGsqwoCq
3LnAPhIJe29hdgxWJTnmGk1dvVoQf/Ae/CeiZXm1v9MjmubTvyoqdHmMMe5GOqEq/j6VRaIs7QhN
VYSvyEjV4DNkEXmRBe1OndjjKiGv9ljvMfOn+DlEv0sVgPnZITodRsVbpUb3L4VBsG1PJX8rXdUp
8Ra9SBg+7wpwnTs1El3hvamSMzD24+1fW9clliH/Ru/2ZVyZaGJgvUvN4gMYT8eMV2hBYpN7vJOI
kV2slRRbALjglpCHUt3rE0Q7YE96vKt05zoEowFCAiUPV9goYjCWwdZAbsp3HgFvR4uJfJTVjEB7
xvII0l8vd4UsMLVg91lRPGO/j4ykU8rIhusydg1vgBRtKEXMef8BtL+QJSNswRgZCe9gQoY4stAW
iCGWmVqwHP6PlFrH/VFTEB1DdimsuQVg+oa1+M+OTd/u6LjfFzay1sG/rdh5qtx6p1zme7LB6t1d
1EmC9WiBxZGSdaex58GfwF8D9gUYfY/vtnHd9BoHhzdj6uD6RGwXQpuIyfTWYI2rRhSVXgGFlNWc
KXxYyylLCL/w5ONO9X14pPYmah9FpNmx3p+DPfr996YU+TrzZojAuZ2WJzAJwGjg2iWagbvhWLiv
dDxubRynOLiXx15qrvgbrmLNtRsUS08tYUNqXqaWjXBHICjcrlgtfMExrTcxBH+54k6hTW+TGMfW
sY8WatTP3CSyfMG+xl37fOKSv1pHmxWl7Tl74UX5buSG7Vtsjk1HUGqQGPKGT7xRO82zRnrkwI6C
TUUH/CLnKtQ67ReAVNb390+oncRsBu9b/QHXn5GHjIxWNvIEO6dWyrLJlge5KOf/88puUrtgAquN
JzN8J+EQL2/zSRT2Sd0z3FGwmWFSXhIGwbPZ57DWfE3uA1cJkajG6WDUP5INP7UB2hV6RM/0QOhB
ThGZRaT1ehk5Ay1XwWtyzDKH/mSsTGF2f1Vo0u9+A/OKhezknIp77nDq0LNGnvpg5auEIjzpi4QM
+Vlhu/JsrUGF7wrOzz5XL9zBsbSvY+mFrfeausZdz5TtPEk90r3/8pBZslYSzV+GYJFSqWElTl9n
4bHEGBggePVnvmooyabYg+rTcdnvLtVYlI6Sx7Wt7XZWXLhEK/SidJL2y6Ms/NTNQD+qZ1iORQoY
oiifo1FHcaa9LgN+XJlpeYLr0Y916nPPKDrxbUO0aa7pqtcguRwPSDMplXz8BfKkDw9m4rt9prpm
za+Q7Zt3goBIR4cYAsQ9NzZJfU8gBCevrB1TtIgULVVxdKg1Q7H7pGhn175rpbyflyXWtOspVl6z
D8hmYZT/A93GmTIw7dKV6sG32QjqOUlrT7BDs5+zZy/CaVru68L8qn8LAcW0lAoBkbcK/+IqRA6G
Q2a1LhmauazlAQGjAGeJ9ipctO/t3Gz74UZWBdJMvKWUg/PoPUInD0rXxtQlFDpFTSPLDT48DPlZ
01mj94eMMACiISdRs+7CHgBtG4d6mRgr+mIfsnQWDXw1AMjOACyim0qrDuc0A5/q9X7gjwguXJsN
mOdly7xXRBU5aq712jUAhhd7g6zHph37IdJCPWS2d/ba4rUgzAIlqS39jHfMEyYMsGTfjPO6Y5Kr
V9ckngaIzjz7kc9vtTu13qFr8BNpoHjVdeqEaTZDhID+GHiBYsHhAFvm0xkxNNNAWW9D9h9IYDPL
LwVR2IMctiDSIizo2oNQzMI50g+ratT/prdk3cFUJLI8RIIXrDIQDl5T6ZDISfP5p5nEKHF+aD4w
McL4rnDdpODu/G6zrHxsWaINrs5fSRhmvo0krFHA9tiMT0Hjaf64KzKx9aPHUrRJw+DkVVOkjvqL
Ood6mr3yOWaNbOFQMUPrzTiHITzFh3rbPiMmVO4rWbiv+xXZ/lkGkZbIRIvE2wYK1au7SaznDAo3
SDHfjop17IX6ztpPXXQfVsje6cPuQUc11ChBHZkHaMxhMPxhzgPGh6xcWozsIUVP+vAs4M4tE97Y
dySgLtcY/02mBzCcQLREy1yAaIhe45w441/E8xiuBZFfAfkUtU/1sTxnsPPi7ZD1iAhn5bjKBPKO
UoMIfduBl1mSIm+A79etMYK/h8iEnisiggXW7hEG1+1aRtz9Ah9wTQCzzpzmdX8PP4/GY9HI5cFV
Oox5w2Kw3YoskMHDBoaAEiz3I9BXCJDedPad2GZWuxbLNUuu9+R6aROjNg0Njsofi0e5bno61ylO
ck//l9f35uVnkOrGz+1WJjT5i3tloEo/tI6lidGdN6mbZqVIwH3chrrPdThdnQL2AVSP8/4ietgc
cbZPkImdMFuLguXOVUMXgYIb92meq52j0q5LhF/c4rD9YGcU2BSxc8sz81XOfrbleSilNxCjT8ee
+UDLi6Sapwj63THbEE/g7uCiZzlZksjRb2/XuVR3wzS+/0xNLSSdRzDI4kcLlRHOr1eksPWv5CJU
DqmzSJa3XSLqDfmShrWLGCJdRacNgMrfMEfsgcb0pdrvSi2hAppdjEr4R/Nb5swYjd5tfd92BscM
vjt+W1UIlw8fmZul1NSP38qEUAB5RYxA1DDzEGEKwvlD+X3kpUvUmc/cGgUQrfKeMahl+BWXturE
2wc1Hi57vWIU/mx3lZtFSaOeSz45N61bu2dV+CNv1uLPzTpztGgnNexDoHmFQE7egcHy34s06Yoi
33OZXegPDQOlP79lI0Pc+Td5hUHX7/BJBIb//QwuGobuRzoGnzzjcO4LNTIMVkWWGUWRsq0lqOB9
7boEL7ZitAOxifFpjIECJ6IKsiC3DRDkyH5DCO0fOP2lOg6mmZZBg294yreOt3Nv/M+si8pO2STP
DfAQ58/8qsid5cKm31yA4ACp3f4v5d6TrHKct96IEukoSmFLhjS+lt+Pd0WINwdVq9Jxg/cKdmRl
VCX8WfYlFP04sByBP5FQAl028Z9nFbO3b6UYUuQ+sRuTHErtEdD4758ZxFYA9+zR0PGn7WnWP/oh
RrMi6C82Juej9VFPO1cDAD6gmEVwAevTXz1jvoV5nslL5OCbCmMZjgNqWHfjnw2fhD9Ui9XEJOhJ
QKsW194fTBBLrldVJHqVSFbPb/NUCP5uoVl7uZMlOUpmDYlfysf4BOdNHpzvLERwqKtZBxJOIGQZ
HTKlJzZX0JWK1w9ktJWoOKxXvpX6EUS/XNe7vmWIpDxhUUctpjKUI+1GX2KXerpj6AUYTCmrvrnV
LfeQDYD+6p05/muCmzZdyTZjb1bwRVBWXKBnTYItwxbdI66DfmNpwu0RSNT2m2cyt+CQIU3wTT+3
8tiVm03+vbz2EEwnQh99sT8TplH9CT91db4rFkAhXxOPI6klAosxo0i49NPk43ILvq2i5ToftzCS
dDcIRKGW5MFWhg9dND4mrF4UYDZIYcU0OJRUMj9Q3cECdet2Fo+3gQOoD/JAfauFlwNk4AbnD8EH
WhmwvskkfVasTEPkVLeEt5BL2pdnilDHQp7+zYAJelhjxTyHGEZPeZz3yvaF9lt5FoFIoQqI01Dw
JCnMyhkpR8nPHkC6du82IDZasAGHnqvOND264D+bWuDXYPDimFC7H0WJjgtnk9AQ+fsMUk/7d+qH
7LKuzM/Ats+ZgCi3CH31fwVJEqp74wMkKcQyAhn/6cJe0y1DvAlH05NFcmIwQsAgkNB8zusVoBr+
Lnl2FD6uXYElTpVyqwXjeehcdDhbU23SOoAl/amwJoueHZJbf3APaTe63f32RFKD1RFzFrB8pYIQ
0GgvB/ukx4qi1A/vCXGu7OG010lf+hhJsdIzMqfmMlAmDDzSyGAYE5BmDaMPXbWs3p70kH5hE3ch
9nE952RG6YepEY3cC9TMyp7fCoTL+xY+Cw240UrLdHFBqouZtCEeo5z3ISd2hXZceJQrwDFxf9by
UhudecgwZJYloDnBE5xldsJjGdYw8ptpLKH2xtzT8PiRzYu7i+o3nGS7kKMWNBYXpba3QQxqVewd
rE3ynWwO6BAdCPtHKR0IH3+2G+8k8ykveCCRh7iL8Lu+xlEQ5bamZrSVBrYo1eMO4t2Hh80pNRAg
3+bH+Qt8QAJjPYJZWTRlimkSpa7jBLC2vijVw9rh0DKND/InOLwwXpQN5aKeu16LPlx5VXwJVmHf
y13i2st7aR/hFVYBmIQHR/Xmyz5HT6zeO2iut9a+oy6Sb6dFz8zmjUa1UsOAoix942421RNJmt1E
FtKIakKEDlBb5x5GyRYa3aG5Cu2ycGBr1kJRkFmYJ/g0dYg8FE2aZmqe0hOEI1DrddDxkjmLKhQY
b+sUPFKni47x4wc9DoeYiTXCTrCz6CVaJxoq4WIGVtKQeVAOb0YRsHnvKvJi1oNw57xZpxM5c1Ez
pHBFGtm5uuYRrYmG5wtb0adx7ZlIYC2o7E+NRvWp/f51XjFm0DA5ZfgM0++0MUopXKVZiC7H8qts
WPfj16jLji23OQbxwInSNwXR94Ojv8zK8F80qsQmfCic40CKMhx1Je7VLLt+RAv0TrbvAjN6OK5C
HrlHZkdFb4YkDBCNt4P8JDC9S4vpMHvumjDCw9HBpKntdW4nv16ZDiuabCUz/sWyRTBBJJBtkTbW
SbSiwK/wvZgzzgl66cRUr8dy4H7yEArAwKmIqoVvV3ReD4HqWUH3K6DTKRRHl24dWiA6sgZ3Fubv
urkbFKHcgZxwJteT9SihExs9QGmYixobjKTnQEAlrCYk5IjL6T3JZW1vCQA+wRS9XWCAl7fW2iKj
/UwcwnAf/XOCziKOOv2MuEELiEGE/TWh1tQokkWpuiw8eSjvkmOObjts3mlZPM8RGTikXyot/RML
/oZk9O2ey4OYil4mgTBDZ2pwjInr0KbP5rM2tAMMNeSu/x/xRIOgt3OCAqX55YBt2SZ6Dfv6ye+e
HD1Emt8DgOSOEHUKyhySPp7G4Xo5zsWjBa15pDJ/4B1/PojmfO4WNIxSRaBToojdV4aasBiJJbmt
sOjfqYFWdKH78IuBmPILfY0TQsComDLj2Af4R58mDiaAHt8DzwTuiP5BV3iiW0k4RtRGUqOMrrJK
ARwCm0I8d3IhJpB4Txf4cX/idGTUzIIm9lcS8YHe8e2V2SAvzyEabFNytrGcK2oZFv5YDXA4au1Z
SRZNz8lQvfMGxAQAa83taprxAzYX4qJJ2L1ajGHUVcOGD/D0OzZq0vPQCG+nI+61F6/DFoUynBuY
Ewqh+6EBq+/nQNQtYtAU8fctHwUtn0UA3cocp2VqhvYzhsY5juCE+xuSo+9v0nlZn4051zhMYfY6
gG7Qqsgwtdo9AQ++39OQdLE+uLwcu3lSwWaDRem4SUWoxQjitsQryiF3YbdSsKLgdN+PTUS0rQdt
m+L5Oe2wH4TuYy2CZAjuyjl2kBk6qDI6r94XqxQu5ZSKTzBKHEjtf9G2hQQZKQnLZkofG42gTloL
UQoqqTBbCPvEfltypmb8mYHnmmnYE9U9wSte3eCoJPOlnixPytLik6buD5znKCRPKlcEDWAmO27c
QcIbSkOk9IP2e5kouyjMHVy2jkoaoBgUgQSnIZ9celnLmul1jePxkDmkvLc0sNRDJelJBqzk/HU8
8UiJbaidYJonm9T9tUP8u2pDRozJCI2HnKTwgz4rX6xNE4dCUrkdKmv4eTh6Rss8TIJDZOu9/oZm
whVUIJT65Cfd2fVZ06e6J0SHSGZ4nlpKOxVBUdagAkpk5hKxwhsBvp7PL3++iTs5U6SVT5E2C3NY
eLfqXU1vnD5VRoxZRFn6ReVAM/JvlhM+4V8WNA8C05nvVdVgYEBwD34s3/+XiGrP0Y1QOFWfOpDD
VMJur1jETcAmqXmhNWIaVVd7K8/7biHCdxXPJo/D9hKxj6FWO1Z7KBl7LIalWe7bfnEE1hWQWMzP
aUyue6yyLokV3Zs8uiDPs2kjZOertIVIjYrHsi3qkg+O5NFMpQBrPzPCw8AQpAzW6uZBENjLUjdz
aWwoahstSR17Cmf0Jb+zvD4q6BILMpKEdFbrz2p/LbXzPXsF58pNbZZv0QX2TmfCml4KHa32HJhD
mgTF+vaFL7E4O9hzFnWByAGEuFsFGO0XH263gB3Idi8aZkxkA157hf+kawkUSPxntR3z1WLu+Q1W
Ipr4HvRja3b15uaFTbmpOXQ1Ez1pjPI4/69mKJQa/4q3szC+L2IGgPh6vUHKmixTySwVrvAM2pug
L0WBmbTMZbQ94c31SbofLXcK5rXAD5KHb2MqfDfBOkMiat0CNBMFK0y1fiFKZZXewfznCzxuBAtI
9do6bfke8u9LvTHIMl33kYgDLFjjbpyK27inwchyIBtuxl69XijCU4ZkviPWzQnPaGUEPYIbZmJZ
DHKKiUhayI2r+iRSV/5Qf/KPd/+nqcmWRH22nJgATE+a6LfgkIHM6HXYxDxtLTJ3M9xX5jvgoaCm
mpPxQ0zwq2yka7LRyYv+32t4CI7qSiRXNUkFo35urgIG4srZlSHamWSnDSz5hbY+CVIx5692w/l4
loLHGlHtfDaLkrsovcyqnMb8L6dHDhsoTHaE+Sp/3vT+4KsWtiLEPzW9x+gwcDjfbjWujsiFxiMz
3V9QwnMUo8a48iVa3GzoMXVMutq33YSlAP2x62utWTsfRVTO+2wqsThbo4kRvGuKNHBzLP4rsb1+
ySwbfc/JYHnQi9Lhm5VJM6qoeVjW1cecBC8CKDWwjlNiQCvJMjv1/YHUCxfBA4p2uOuv1scK+tSK
l7ASrVeyHYZWsGbYMerbjuyu6KMtRqYW7/jumPjMx65VmWgJ8Au6bQz5cWHbZkj6oXVjE0u+WyAr
4Rd41H7rT9XL5uInEoRflPEcrHpJt5USR2vJQMPRmCiyt+rUabfc8EiT4JJHUdihrxc0UHmFHSDG
wiP9exHBhsvVpWy4Jhx3ydBMyhFljO3Bohz0Mt1UqCQ+PaVyeRrwHo/FccmlvG37MnsKXMK9KORe
+fNM0M9NPB/jBFSqs+WTba1NpINK/NekVea7iPXKrRQBzR5rBUXZYAjCIx5kp9GDKxiZDC/xpy7N
WSQjdZ8nkqzVVXI3WofrV75r5FKcG8rf28uolWkclc7dp5mxjgAW2JZKJqQz2qlCDtqmfEU91ta0
kxyc1ihthKzJ92bs6Jkx2hKQEKV0I+XJWP17aLITw9LbvF1TC44Q3sPp6TVb9XFiD/l8GgDE8Jol
YwbxUzRSbIlTTtGI7HuDWdm9VgImJlfyzUxBo+WLx5KcU/r0YCYDFXDDRLwlR1J2BTVKlNf0ST+K
R3s3Mfc1GivFhMQWTsoQQRVvNxK72LvV25TvgKNSKX7SH+2qYgw97NLvAXZGODMTriQcV/9m1po5
ck5tsnBVRPr75+aE5uBCN9qxTjRTjFxYQqOn6r6lwp2WYCo1czO7fF27vEUPEOVVmX7+RiaPZkTe
bTkxBfRohbP5OEQAbUooAmgzzC3NdhrEgc5gQ9sw4VPPTbucrqSDEj+eKkDnGDeNqOxyCQEX7C0u
XteEzXXwn6nmBYcy9M1rgeB8UlWgg/9IqTPLbh4jMMhMIATDUfqm7/Jg2FLX39FNFN4SG9WHv2ty
X+GocsxU8VF+CPA2EwlQ1ckY40vBguLqgR8Ehvinbka//w/LwCn1fbdblVM8cA42toOVX7GoJvss
dhbmKg18qoIlN2Dav81ywMqNTCL7kypCdIwJBcCMUJbchlJVhabyr3mo4A82LYRfUnGVcXY4cbyO
v2/n5BI4MWjpoAqBXnVwNmoCHNfSYTnXkXvBUciy5btMeehCIu3ryaZdJLDt1FM12p2y52T6I7pB
DKaFhIBeQT0qiwP6Zqxc2z5Acbt4MZXWa6LgfMvkftIkcM/0nsFWg53R3LFD/iwVyyWXT7LA+GbX
wxUk1K57c3kDc+bT2GX6OCm9g18eZsWflbhzKfdEF1c3ZxnZzlPntx/7iXpQ23Go0JReCuw4/lhF
xu3RCMAYqembl/49VTFReXUTOKXgx130i4o9pjoLkwETCD1iIZ4W6mqWjvySbP+7tSh2T2PM/0BW
bK4ryw18665L/r54+3prX+xrpdvJ9/3GxWr8cHPvmSxB+EfjWUAXwenxq4HQdVV8AMCEKXIFssLv
nBG6/dw6iWOCMqkXT19mKLLk4DfJeyCbu7Zft8RDmEbBENTC2TMN0MyltpVeqxTmNSxvf4dNwcC1
tQXcD1cjNRaaSyItMikUdzPlpuyuzZGtfXkGT6iREdRRpYbjEidgouVedjZGfavKnVa0HIYQrE5W
hmf+Kz8NbjNbdwIntKszVLRXVnz4qBYSN1uD1MhajMLFtqnTm2M2bQ7XswMV/FjsT20RuXyPqVFI
V30jrgy3FUX3CfjeM1r1MsSRTA9a5J9Z9GbxwRBZxX7ReSJczSNsgZw9XmhzIgeIDsaVmOaJGBLB
JzytXf6GoC8dJz5u1jbuvbMKTvhEX2LpKlHqPmpmFR8PnWDlkvhudybRFrJSwDkpSrqMW8z7Ay8e
tUS6l7FOJF0VrSCe3svLgxDteIx+kjXa4W+dErebEdGjnqY7wok7HtrlWysH31j+CeilQhbyrDpy
30/vfw3eP5Dp5YcGEl8RHcWgtB7qad9USAjPechxnG7V9Qi5ko+VQR8iBILT6k7v2w0pmt5dzxtR
8Bwl3WGxnSQQBRxUPOorZis5Qx7tATDkwNqyMZFqBJ8guJENHouqyBgtm5VKrTNn3cLYDgV7x2Tm
s9R1nKvHzMyKaaOiL+bJEsVdsQsRFZlmByupd7dF0Pupbgu+Lx481vkfHC+d9mAu9Qgzb/OwpW/A
H7lIvZXyW08jMZYu2CpoT45SDcbYFFTv5yKefJ41Ov+eX1bpw7ek18JYpElJMqq3oF67o+Kyfi1m
GeqeLNkigP/BGNbAot3UrQYQSG4+JCwocurgtLVP0/2XN4fLJzkpbttQZzFlQyxU9erFE4+XSzC8
AUjeuUbDA33PK+GHq6EelhAvcp/UyikfGcvZJYGunHjY1sCbL2LnVjq1aAMPfA57KjrIAn410ZP3
5q/RVVZNUj1wph/UXOq7/B4LYlL6+NQEr0OZQNHDXVY6E7IR+FuQ+HQv/SRHwq/mHAvxpxvxLpLP
CjOFJw3weEvQB+u4U3KadyAcgRUxOBU+sa/D2c8fSKnF67d6+AImWQWOR6EQSP8Q45Z2SI/G5PPQ
O6tpHlf7QFXwI6mSUelw58vKTLAavTHnk6uX/bikCU9fvzmTuRQKUu93a6c1dSjzySZG4xABk5Cw
bKnFhs4wIPM+aCz03HYV7of9N0FmXVJhmqybuaZbcR2n8hpoKDvj9Ro51Zn5T0Au6ofgIoqWoIWg
O6z0er3srru7NknwVDHnaCt0hpXilX1h7VydTuv+VNqry040Nq7tOvoQNphX/CFGTgnpRTs8A3bc
YIxK3baWUywrUwo2226rDEUWYgN/voTAJN0i923oLQADbRUMcyaIUWaqC2ahWpg6vnRXt+K8K5Fd
7vPJujJyx4U/HR3JHoEhgV2h/H9EGpd2kigZS7g9gKBelR2kx5vOp2M2knPkq444VaV1kjNHWp97
JuJBo11PF2hTLqpDgWbZcy+6pGpQtmceL7Sv5XNwZQIwf7dZt9+pdLOLkyzFqQVaXgSNlchTJa4Y
e/MAvaBK/eWAXBtt/PlPr8LhlaHYcVFw5hQeGsu03ZcYAoU45Y2fQJBYZwsA5VJIC8a+ECPrn8pt
bkdkgBGOmK/8y0kHpDzQvO+nhw/UG7qTebXELpEzBBr6H0AQX+0Ta0dTFKs6Z6WGfXdWCUdwVguz
BBfiYWYZoQ3xZqo4YWuUehYq5jEkUfigA4T19REL7U2/z+pJZf84mDWSvAiYHL677v3DRr3CDTl6
1SXsNVy0HDykxjcj3+ofC9S/RObNBQg7dclV2384tlYQ8IQn8iPk9dHKK4boiIUnISy6/SJqCn6d
ZFyjGcNB/jZgC5k5nhBl+uvmH3H3n36WzDfHINh6uoRNpTLf/Hk4ddrINkhUFD94VdFVr2w2uN2A
VtR+3nbxLrP7c/yZL4xUNj339Vpao9d86jFZPlSROldpyOcH7/VC7Fnv+1Ld6T/5ku6BmOmfA3iE
gQeVCsOsvGF8tUnH5fjND7DU3qOQDSQJivUyyMsd97LLa3Zi7pH2cP0xgfCyVeazKfEa78hzlYaW
BbiE0Tj/LhtIFJ63aoJR1luvaC/wlZ8FosYqc0NgTNcEfBi8UaycQFNKcY6bjiFtdCkOXgDDoBZb
R9oc70DwUoH5P5v5ibpncRO0PLX5eYuRgmeOTwQ56DzznXQoq8eCxNSDd1nkdTjypBLKboDIAuvV
9O2bcDXWIC4javgnwchrLC72isdk7ye2VeIj7XNzJ1KGU/aZHsiPveqhZXXihxYKgKBygTa1OwjH
Vh6y9jH5WPne3X9p9Z+XBmtwvf+qmGVYgRfO8SnnApGnhM46wRla+TrGn1wugvPuGAWuX/uN6J63
OCuwos2WQFXj7QVa3vbyqj57dUIoZlwnlfsvmqHfMFacEJMNxW8IkZTwtf2kKXfC+/ekdRc/OFTz
VKi3M/oB4/A69ouj1D0rx2O0rpVcNXAkwbScIzR9pkM5lIczXvkBRiGP+IfZMCQfmYF6dKKi/A4O
8bW5sKyku2uGK7ZmZJrcE2hsoAQSOBwSGza3nqJcXCg9fVxfv6RTf5MsMslr2lDtOh+SWRbm8gy1
TUcj2ycRYuSw/SbD+1Yz2IwukS7BKLUHokCJZ0d91jCmOvV3l2Zepp9e5zMO2KXPb6iW4WwvhLGk
9T1jtSjgPA2Hd9w63aQFflW/fq8Tg2tFHnKWjNH9mhYlXo0eE6fAK3TlLbwBKmxyuxIoW1Ie3a/z
u01yctTaq2dHvLwDQGulqCidzgd5ZvJNhiS9m2QRHqTR6+fevTU4MfPePLCp/9OmJbfQirNPXiRq
Y3YcBME93e2YHet3Jw/zW2kbUFYLq8J9DqHrLPSF+a57IokGszQZnauY713wHXeHDXu3hin22qyC
ihwRCTlgH+QDs719xSaLba1eAJIzscJCQT4B5HpyaXPOW+zBVIbCcbGGMtFhHZ6JPL3/UFtr29i0
CK+1hTSdcFpuXKMz3WQ7V9dS1rzqj0NTexQ00yCS3EpiBWhpSTadig0NSSHYCb5NkRi53/A417j7
PbLOtS4qKvalGGjpeeFXV/FVz1bqqm6TWNNTYrHckopbyzvO+r5IqRsJz172+H9T3Ny0UZyqcVde
YUiIqQBp+O0V5Z9N2ZoKIbujiv3MyvZsRxacsxOLc5OiwFI3XS1UcXQrTCh07ItIAa15PB9BvPAN
sKhFQI4LO5vX+PRDB+6o5VVIoZfzMMcn888EmDFD1LbxveoKnno9fTsyvuvDS3oxMe2j/7v24p+6
9/jqwmtAa932FM3wZuGmWH9GqTFMbrEJ04cZOumGFSeFWY/rfpx+vHS0JqwzE56DMOPGzYe1BoLK
7kGpHmZg6saIHXHag6MQ/0Klh6DP3E0FtVIkYzJ7x7/3xqT+M3JzwfZECWfY407t6GZz2IyJ7sd3
5sL+32KQpksxcVd68VzA194rsCkKS8l/KsDslUKrbw3QYHlopD0kkNY/aQu5/nhAvuKI6gsBQ92L
KIE46tarvf5rhGx5UMPwC20TZjni7z8Fg85khbpC8J4cMAQz9m0STQ+IaLD5Qv2PlrV8q3KfsAOd
6QCh5MmOxm2w+4Tdfcj+NhC7LJbOGB1piOQr8EnDyM/qQFpCrzbZ8f6AcywcMY2cSmBYbj2rZg16
rCvUU9yY1Mgs14DMu3jo4+dyS/H1p+oI1Chr4bS/Sg4hnedJb4c+S3SBZOLHEUxEbJenff8bIT7t
M84hSRb7MTz0kCCN5wEgTMBka17zKFQe7wv//301eLDfUX4RJnL9FI7l/hsqgBZ5mOEXyOtqGS77
NQJfqWdU0QodSwpqT+iHRJrGiRPNSmr/KGVDTJmWSeSoGr29+C2fYQXQRX2LRL0wFTjRNMGaM7pW
+l+KI5tbFj/7yTHYHVTXoYbjZyBtBS8H0i+aOFQWIvZGgGQx5Mv9GKxc+B6muiZjsNX6Je3evips
g6z7hXuzeyU1G4OP0ZUvSwIrr8Hv2dgJ/cCAIkCdtwxeChIDsqclP0uYDJrTLj+X0Uq/FfLCEwiy
Tar4Ndqs9yKL72/Ob5yJSnkbMYvwFGs55VVnjGDqA+pvKcM61JJR4Gd1Sg8QtdO3neqtoXgIvj2B
WhL1ms9cmHr/Qv8PwsQgg74FpEZ9aRVpwvaYK340visvqp30eCAglH0fql3GTt4bJEGu+Z3u+xcw
mVJydqJpHx8798FiHJaJCwrr/PhOyDdPyFOi7FphjvFRoKLTzwXc+ow9udPUGSNKUohcyhy+QgBp
lpqQ5hlagmhM18JBo2aFJvyqpnsAxvf/6RWi1JN52hRplm6MfLEf16KpsfqTAZ45oo0T1psHBYgo
ag6/uYLZcf8UDA2fytRdEsWST+z/IsUkthBT9HjfsZ4O/lSDrMDA9Cl40OFbX3QTgjdR9XHaaAiU
N9rArufwaz8HsCIvaZ82jkxpDXqBTqKuPVV0gi8AxiJ87F2aDJGIA+PPZUmqptwEOyETv+Ag8Uas
8bldH3hN/wktlSFXQKNpnNDAxwYo7lUCD8coYcHoVzbfog5DCvFQPlKhZH19kA1w1WH2hokOM0QT
VpWsEpauLhrkyher/dyEiyUd+LC6GZLfjIO1/uWMSKVzpdt4GcKIOIx7WierbL0S0W3FNTP3kC9n
iJzCSQ/v27RvbGzdo1+CODgBcf2LMkOOWVxorgZuHH+xZh/eUt6c/BZ7su6sRtNAdALhuDA1JXSu
HV7bLgrC9GYd24YTSQFIlnM1C+nGwL+6HfGh7oTVTmP4zVjTYyM9HyaZcEksB5nMq2Vcr2YpYE9U
LBBBuFdJc+1XBy9uS5MEv2KL3jbw22ecssLZVr4IsbSJTX5plksqwLsS7dZaLZ9mL4VdC7p4gW0t
cw36HXGKg5RUrkGoSPsd1NAcEE9HWLIOxBMFBG3SGlAi2yGReBuyktPQNDQomhcwoJmFCtIKii1/
0mSId9TePGV+3GNitHAHyhIqNI0jBiIc7/iaH4cq07gi6Utz5Wmq2JVpO5p4EITqjthYOr6UoA+1
FUeHJD5HsJW2yXpRApIeHuRD6qs/iqMV/KofhgX/qlpBBAGLk64RK66VnjIS3KiMrz+OPHZoqFUJ
F8H6WTp1uSOx4bDoTxJ0Shwx9XjuQ6DWa5QVxqM6FqhZSfwUA7QTyYzq2sESuUcBD/V6QMYUoOz+
psL8WvcPY0LTr2Iw45XWki73DTDdg3kFx/ygWNLB3H0VSbZmQoghW7WZkKCPEATa/9aEebSJakb7
n8wxld0m5WrFIvN6AmO21hFrLgzZYtsrFwZTKb3fxuCE9ecFS4l3Bp3GJarlsc2cO1hRnD3MVWkO
mkfLnWiADi506/D6cjzOK1t6smfdtphUDcgzkxENxySMRIVOVjQyQ3/O4s/h3v0MnmkWDaYL0zow
MSFr3eTZKEzx6y2253nCa52TDQIZ6vVRCLSclCYDTsiuD2Q/BNZyGl3QdDk1eytr28GtUKjafkOF
Ks8CBQh9P7f1R3YfHrRUDyi01WtbZsg9cM/TtpfhXdtf42LThEPcHwqhW7ozyqpBOrGHdC2QXrmr
8JiAyRukrqI2M3+qawPVnLxFMCwbR+F5fp5qX5xU/2xjM8vZ91Arw8FYoAsEIwkgNIDGXwjibc3s
frmdCaCuC8LpMhVOD7UwDyNPBRFTWgWCUwaaBkAWDtE1hjSwNmgVRjVpQZ5rvYvAZetrdPiPXb5q
ScKagOW+qQndMcsuXqBnDRDQlF+Lo1+2wRWSqYKPE7iFpRRYC9pJKAkIV8WMcGdFb9SpxKouA+l2
feeeMDaToCEZ+kLoDVfYAJPd9aHk1Cr/uPGYlDX772tc8r06lfFiY7C5vhTFvqJVTS/loOGNIay5
ljelN6PGf4GN5ubqD6zG3IYdJ6ZKYtKKBtGwB+0GLXs0sJS9FykI8cYYVBimTeBCZWVzpIPzyl83
kXGRKa0U/vvq9ZKQY33yUfP0XQv8F11rujTSpD0R/TRKGH4ht8I8D5QqhjgcTZ0tjwPXerkVXubA
sSOVRSyLwNGCzjBM/ObNIvwjXJ3f9vPtKszkzn5A3TkTdmyr1AcRGIINv3U+guKuvPEMrR0zimOU
jfMn196VnmqEUhV1wHMF1iKl2/+DWFXclky0ZZceLQ0u/TuB8r2dmye0zpOUowfz10bG3LAab0bO
H6sKI579USYafxX8SM6JbMvQ5GA+0sU/uUH5tINGmQFEcV82+venr3kUZxM8S+QNZJOU81qEVo9p
Og/lkgsJPgK4bbjaCGCSUijXv+bkT/q8MzMq5Swfk1DDo+u9ygje0fVe0y9vfULfj8+CCQZTmUNY
4M3ILcM9IQDQ1YM65VolRzH+dMuPmNHyY3OysyIVnq1OANIyZNrPjDBPN7yCFg0/EPGSmTUtS8kl
vY9FRNnJFcTamHZngs6tTQ+dovJAFk0Pal96IlhfvHkefK8unro3SVkjYhccp7ZnptMtLe0HKRET
t3yWHaRuDEqTlOASV8CqRCahlj9wQemx76mDlKZTIqQL0AA4CYvB2HELLO3CfqNHpuEA1ObPip8q
8RuMUpulri+Rcnte8BRUrSaRk8DH3L/d/uLIdXJgZO0UcRNf5WnoWnYSbqb2G9k6svv2NahFV/Da
5igEqXq8JhSoweB17VqMDfa2m79SUTKJEMhGFzUnc8AsvMQhvSB9JF8L2ope5/OMLTYkzVsUd29B
PNs/0OTaE7KCpPfLWT0pdVHEaUAzAvz0cgw7Or38XCUWMc1fG5D7oRPWy1XRdJumfZ80ZDNG1I1x
lKQGZctisBPGMwECBEsZCXvKBa53ZaXPQJ5EHXtt/rmQ+nfXNvXIgxou89anZ/eJZyAfsYnEhRNM
JB3jBUel4znytsM2jpoZFtfWH120097pkLMC5+2DveRJL6MIDPJFTvf2Y45Fe3eoz5akI79T601m
FzGRDVznxwcvu/QoFJOEUb0l5gABMeZ4WoItzHWMu9AIoLq0lvvnujwmxpVcjFaDcW6/g2YtgrJ7
cF0rsVQgklvZvTaWoJ7OCVRXSyvLgoP37ixHMsphiiX76Sim/tvq0w8EiuM3FJpdyAQFIyo+rH1x
9k18i2p6CswryH9RYx5ixAJJKnsGKjKU8lCuqYTzQdJD0xasDsA12vRMuXNoZmIRG7LiHjarzHIk
9bXCTa/wfif7bnYCk53oZM92GOoA0/E/ifLzz5+wT0pWmUl8LLe2KiE2lXs8hJjw6uCt9BAKO4mg
0w366CO0evbwC6BbXGfNSBB4zaD9h3mIKF6orcvLhDT9lKlGuzZrV3qIamkMwk1YsDUpD6sQJ5cF
6YyvOXGtXD8ERDzH2HDmPrdHoxFKNROJ27vQgtWSfJohsyKzEokGyehu+UIyn4qR32tJoo3Tt/pN
ff9TbCpmOE4+NpmAzZRStyIBoGN4daCawWbGaCGaVTTLNbalPgZIYySLBamIxz3+R/ORfpc8hMsI
Wq4qpkOGhspC72IXBemU3P1fCJzVCnzt4zFKQ3RdvdlxT/o4f1n8YURqkVaijtbBPYOm/M20sG+n
Z21zczgPMTGk/JvQzmzt11JJtcGa5t3ElK5er8yNosRyZiflzhX1+QPtrxrkpnJNtPN2+onRV7P7
cw28c5zb16mpGOH70qriTGsy2Nt5oKGx50G4cSi9g5MOZ6FSfTMDmeiQ75PtmkF7ryrEPA8R7ldd
Y3ZabhBhC0UZUKext9JaSqea5Sxdcki6vFYRbX+qJo6SSRBA76rDAVs0UhzSNhPPe7zQLI7FJcwz
uV3G8X+aT3elPYJ1xXR1MHqrEL6dfyoP4jU3xdqjrNiURTL7HRf+b4zLx+OnkkZ4WjFcR2OOZTsY
i9jYSWSi03zAgpwFEV+muCirBVTyURQyS3dTzVnBhbeTFUgzebW1jZdts7znpmHW5f1hO8bxseiC
P2x4PnFWc/fxFlxMHXQTG0u2QAhTRFMG7roHoCDWiso0pQ/9RixuWi61dIz4dexmLfFH+TXsSKLF
FZqNxr8JiA5H7pKSIqfaw6zR5yLmpWZ2X584T7prEf17Rv+UH374/EP8tiEOXabgCayNzoAYqEKq
8HyUA7xAXto5tqvpAjjlpOFhXxXTfIFOx/igAgySu33ZpfbzVUca6EFUaHepElPCbEgARBAiqd+5
bZ/JW5KqLMwdKicVcFNN8prSi1nI0AkBBs0LSGkdiuyExAYNARIuzoDITklQjBBj6ts9fYVaPQHw
v6uBZLfKB0l8c0tNQiws8vmddk6zm1yz2yaVvL5QrMhQ9hoUDlFSbjijwzvmO81kYZqshyztCsck
ZMT3AG+xdPXzfxbIBr/3767tTf+dGE6XShXbdm9Sp+nKhUA3V6yK0ehNLD1GZaNj6hFUuoh6FqZh
nTRSLQ6BxbufLEyFhMsnWmLjoExvlYeZaphBzFDNDdn4wLzKc3mNYwt5q2AeTggGRYgQkpNc0cjJ
Oi3brg2HUIo9Yltal2Z7Ytwp6qWa+jdWAIK/AF/TGGMaAFOtakM63ddqQjyQdptUjE64bW6kvYmt
v4+jLu8g5joUnEwkCsdgVJAdXm4+ycXCfJlVP5Hd6KZSj/+907VV2mVoIMhmR0PzogefoKzgPflQ
BRXK2TrvJDEtUcJ7Qh/bw1EOGQ/3cIeQ9+GDF1FWG6/XEuhfaG1oHP23J7FMZAuLUoVYEGg4cVmU
iKTh3zsQ2SQGCUI7U+lkBgx6AfsjK9svgbdbjzABtWn22fqvPwPhGNNR4zK2seUJStKoRlXxsWl1
rp4Ponuwyf6njviyDE/8vFzexkgy9Y9CQXPFr8WndEcKgFHCVLMV8rFBAaRuCRUcJS0QuU4dBzQs
Ik8Sf/pN4xBRLbVw5HomaahjYXlv+fqxjZgAI1Hypt3rdeja5Xf9cR8sH5nY7fkV3IjM1XamSLxB
mU4wT6RCfbe5s5mB1E/03/Ry5A0DZj+Y8ppEwnTqT41z4VDnetTUrkZXQRycAmg6T1pw33IgYYvD
HyVUSUoWqgBOP4fbTib0z8Gv0wIrFt8nJdqdxTQaQCF9N3YJzdCtf8mqOAYn6+wzHp4ZFJbYEJ8X
A3XI9Cfst+sGW5ta5gbnXY3Vq5XTlf1D5s635zrPqr/dWzn4bI4JI1gtYWQwBsyxe6JacYb60XbQ
wag7lbFqTk0D3OeHs7bKeiso2VH/YJrmEJNroBm2jlfd6Ye3eTpDZkQRP+5g0G1FkYDcWvCBigoG
dElZ8ATgglHIWgd33l8N8S678a/Hqzm0+pMMDcNbCtEAf6uPb+81htUrP+zdKLP1OWvPU6Ailevw
FySFg6cW1O/iF42IPov2wNsGF4wth3GCm1aX5H/DdZyTV0wQ8xIGqLBCoy0hzOVVe0siu/RvKdJZ
7+RadCGtxjVDz5/3R4f4v6pCsTjPG35fNkgOpa5NBY7FIS11iCDMlBZIuNlvFON53NsPZnv6vrah
30CEOZRhkel4pzl+RnjZqrOW0LxtIvkQFtnAUFDOJFxna+Vg415dqMp8G5O7OHU+eNkv/zviyCBC
FzMCdTL5LuPE0yXEyLBbJfyKdS5MzconGIwaoS46U6JQ8/7y0Zt8sEpxg6jQbcF/gDbbCFOMzkT9
9VdjuVUdSufvsu7n69eztTz1DXtqtsXJjgiGJpRzcETc/6B1Wks9DEJHF9Osb2oH34pylNc7+GqM
jEjsI/qOXaa6KYqKsldJCeykU3mXnrVSusO35anl7pTt5rEGwkxaCqUfTzOaoLxc2+z0nb4XAR0X
zfwBa4Q/bTuh20rGquhxxJDLRoO0SQ+UB7Iy9vyQeNjE6ENCMqUWd8LMluW9WjSrww0zaoqUxmdR
3+sCmlqZxjg/hoBu2t2NXGD+0Otuc0+AhhdK43B3iXd9AObNi0ZFJLnM1BFqScRdUAstoB96rkld
reXV3RHJY5wEO1qpFWFs9rCoVDVGx0xSfAnEpFgcPkXHSH/Wp3af04vqIHPS7DcCrMsCSISSIw6t
kqQFibA92DZYTRMnG/obIuFeG/znIYOJt6lMYInYOZWN8BLPuFAoH/06GFKo8/1quT7JyiD1V4lj
3rDTi5wgG5pzzsXWlTgBIeG+jH78sKnt7bbqzQ0pCXtzrVx9vowg//hknu+9PL4RdRdrBSiMapuS
pAZRXoVFTBNPIsKGDceno3J3oviVZwSjoihmDbYI0LI9cfHRk1lS85G/guXJVieh9vC/KNUo66Vb
K47v6ta2MBAsnhrAudVTlXEoKrtkehg7MhK9kp3uSvwVvFG+DerQtGft47KRORthnoQ0H4qyVj4T
/rbTZlzw9D3ATlsrb7PrqLBR0QKu4SWi/GUoLn0FuckIIJPjMMqvGvjk77pNE8l6DCjob0gl6pfv
zbmJWpm04+t15HWacCGJxso/OxmUJuvg42R93KYGLCUo57ZRqJ80zsq+ubDpQBfLaTmh16JIZJ3O
XERHte4HcyILgr1bMGL4uq48yzRf7nwFinBq2t0lqkqfFQmGZXwnYp/b9/1JxEWojZg/M/lky9rd
yykdMRYnH31okvtJgznXkZvrAEcWbkay1VpAxmR3XfG2YpAx/aPL1OEIEL/uGZqbNHZcczWkxPLE
kqcfo4ht+dOH7yHItPmwdCtIjyAYFGVu/Nmcgx+Os6v3noqUeN/4d8gn7NYqH2euvyUcRcIow5WL
SGiuRfnOrj/i1VQhZHsAC1KBOR2aLyMrJdtDIvBS6nCmWbMt1cuYOcv/WTjJF4SPSOsRgu8DtIww
GljtQw6sYxVWO1twmDYUB4KFPpPfMRfrJpHCgeVfWs/TOpaCsFWBp5fdOPM8egKgLz5HbbirR7pW
hCEPJzysPjDvaGAyrXlkIYC5cyr9X///GYD3UUt00mg7g+2PdRBVrY6xtbzlG+EpuGd/g5GJrTjv
3/iSmAeJn3zdYDdxsmMzjaf/NofOx7/qNUvQJRyrcvxG789C7zk1Jsraf0FjZmntx4/3CQgvxXp6
EaCIhvunbX6hZwBGcapWScKVqfQ5+B1pkBwprYCrBO0bsTA3rJB0kOvREv08yJvtxhfgftsrr6dI
EbgovnFZzv8LMD9I9h5umdsdGolLKRKJnZmMSGAp3Ycqpf+7SbDQVGBzEjy0XdHgRyeX+nh6vCNe
J2bvhfxK5AuMYU6fxdiZ9qSBfpGAczVH7svhka/TGB3cQP7VEZ/DoX3q2wOPOsWWIFABxei82EKy
r3uUpTkQ1hlLNjR7OSfwAwI3cPwK9jKhYrQjACyHyTetpT0I165iXE5+4DrXXtwx2nAvkvjcF7cU
NmmDb4R87yvw5FpvY9PIcBMqQ/hfIji+xXwnkQnMR1B2wAhY3uOpf9qWxQ/zjEqygUxeyVaAC+rU
7MBPVBWYIbjMCN5eGw0Cg01TdwGebtQ98eXkJBcozaFM1kSNflbqPvI+ESQRDxjOji8BOfbKMeiw
iBBRJ5xwF3QZZUtwMvWreeMO9UWTlM+fx8hkDa7g17ESbaNhTMOk5Vh7f2vv40b8KblhuR063o9u
GLs8AFq4VKHBFmM077V+ZlUj0O9BJuWt114YCXFSeqlUte/JOwJWYVZqV5Ndm4vZuuudap/KlyXD
GzNIr+9c9qVyiEv4173jtPxNDtF6HfiXPR+3FErRewtsP6PhFEYFyu1BtN3c+/8Nz63r3kZUiWEu
KPjNGagZG+eGyzydw6EL/0eyvFSqFVVg566r4n/mrdc31CjijTe82VWWMHu+Ce92HAnk5zV0N2jr
l0BZwMfW74Eb5FvySjYFpm75MamKpVHr8dNAc1wlMuio9aklb3RnfgpV0tQAZo0KoHF08LbfQTDi
zbJPD903L9sz/rF3Mgt/npxTKVIhnx+C6XPN+MBAc33fb3OUAluE2cfMZZh2ymDf4uJ/nFHOOLd3
HSrjnUgwDrDZktBwO7OhrF/ICbIXJP0XB2FeUbPxurxJhWVoQAKqOZzWajh6PKHW1XakxKJy+IZ1
ZufSoIzlsL845qNR5K6Quz+z+WVkQEk22w1uSmTsabdzQERkCg1iXvgBk6KP5nKPvBWkRKsW91V+
L7SPdwmItQoTdvvICoJd2JQT2/Nanf3UwVptYSBYRF73th1AwOLJRAgatsHCPjOlnvnNaOzpwwZI
WDa8e5w1lkR4y2stQRn4TB82ulZcr+iuZmfoEpL9Q9b9bz50V2Bi33VCgRjrnx54zT4wS4qHg9cJ
mDvrmLDhuBx/3Y/besakG118M+lQYRMyXAd6MdLHPacr/qvJchJwzILnSMcroZXq1l+YhWYWfebv
nVQBVc61yqYoe+/XL1aa4u6ChJafYGuoSkLFHSiAF8S6OEk+6bKQj2a8hfpXLedOHbmq5OUGT1Jx
25iiQp/1dFApRj/b+m0vakOqpXdAJnJaRHfD/mFuVPl13YdwJEM6MNv0myCM0DjT13sYZZ0yql/B
muX/IxKtSoNsGf5FhxE/L8Y9zYwwQwhuc9yqVbFB6gS/j/HNLOEy1yTqVRMKRQwHLVDrdv3mbhsO
6RqJiK1WUwV7Ou/Hzv3u8+Ncju5uznzvMPF/1ruLn2wURn3t074MdHrlLVDNDdsmr8yik4uOJyEC
TXmbTW8FE3PWAleGCZujkata0LWEFAmtl2MyWuKjX/OBY0gqPZNqMqU2bCM9/+Fdd82xrmqxEkIw
YM3iLCGUTp0tzyb9wVkPVjE52RsSUwCqqiw2wCuZxGEr3V3ypnk3XAJ0SvXlSJ4+PCLysX2RnfUP
Jd/pixcbTaZasr4EMGMXilnkD+CbZauF/bcmMPSzUhOwr7R7L1RkTMb9kMLU3l0L0EeaOkKLk5CX
qO4qzDa7pRSPsM0zslHWibQDsUn+5Xmg+TT8Y/VtOJqS4JEuI/Ed5WbDBbZvmVchwOr9oG8Nf5Wq
WbV3ZDMSs04B1U46MzbnEpF2h88yCK9F75x5N1cGwDglqIdtja84QGpqtr4w3HwZsoggtwPLMXTR
8IUzRI2miG9SftdITlvEOshuztIC3VtKD7T6dhcwo/FgvJDv+8WNr1IV1dkDGa8t2sux8+xMpOGv
3VKoLDmnZcf9ac6p6G7SjdOCD8CKkQKV0WevIiIx9UV14EdhR2YH564cG5pJJZO2upKIFV086dSs
imgPtNyIhmj2bneuWjAuLVFmv9CVaW64ncI+8SSDBZi5zD7J9UPQOtUiHL4LXnQue5XdxeSPkzY1
i/kjDK/lXgHhXy96H53E0kjMk/6bJLkn+/eTU4oxE5ginnuPKuE6cJpiFglfZb5tW5BDkOCqM70H
jAOWzEXJ7m7ATo64kk69jQnWUVJvLrOuv7lDhut5dAL5JdIes6cNGiznS/0n2wzmrwRF7fVPEUni
JlLzFzuhqXTUVRAUkAyy2WLLNqwkeYAX5PrcNxDpp6ZO4eTtmO6F27hwzqoEBTVcKQ6WFiACB5zD
Z6uivOzxAA++WXMUlkzA56XHfG5R9L9/FL94Ju9HA/2Ov1pL9YzAnZnsq875+0Pen/rxtvoHid+W
2kEw8RlWnnkp2ySVaIwjpFzPUemL4WuXdFySczizMwU0uBDsxBOLhvm9O5tJQwA1WSw293rS2mPW
jc3wn62p3R6O2wygbvKOiprTjs5IQNDjyDxBg1B7WRY970UbAWIe56KdWgIvq2xSy5LyfaJZBtsr
0kLZyu22fIEqyCxAovjWG67dL6BaiAgcBUx/uvRSdjr9aFtcuAJQeFDio/7x8H/KxtiXkIwJADv0
WAFzxrdDJkyptdn3PGbZTwrImscELQy2Rdu17GF8xHPKHfu8AeUV9pIG1yzexhia9IhnwRMMlz+d
eArMNIVEvrTiU78tWmNT3H5uIvy0JRN+g02LpPkRxpHViGwtuF0gQfEnInCu2PPrM5jvFFyIANtA
ngO8WQI1qr24V1Bthc7GRh22SwHKue8L1pukDfT9qvEDc8yqtoCQXwheU11seWzAlom70bYcbzvw
63VVvwGlnHGF/ThC2CnlmJkK8WNlt+TNYOd7wR2q1UgS6lP7Eo/8EvxnubTH+4UO5Agmzt/SsHAK
XDcnglbUGzMDUYNFrK/Io55fiP6n1UFcuysqAhUQ7o2fm5ps3HXbVofvNuhDqqCj+X8bV9M8yhde
aW2rZgJjfRjgOE6xwmO1wBbzbGVSx/QV6RPS+5ZE7xshztlKCBEAuBdUVQ4l/A+jdC702rxomrDE
ez4n1YOmhFxd8U/IgX4wYyVwRZXzM0nW9h6UCKPEsl+rxnRbVGhswofN3NoVQdR7HOUib+mO5u4r
upNNpaSPxzR8Fzsurv/9U4Q8TkDdP5x+bYNC16X0MmCzUw2fS1/lkAI8Evz5SQwCRbyuqU6sZHKp
uUMSkMoQU0hLcivHwsvtt6eZALR4LlT3HRUUl8R1GtXCsFk4Ta5GKfOgeJrODvtuTRabOVJ8r2KI
6yVpNxJzwWn1SnbqkPj5FQTclphEbfh8vzL5A4fQQ22wvSiY0FLH9w6+BtW0So55alFs2cl9l8vM
1luzLxG41ejtcRvTvd58LpjXMsdPoX4vmJeYHBiLZG2TsvrjePYIxPYTvFG1972fd2uppC76hwzR
fefQsWA6nyhhjlhCQZBhhGR6IYBBwW8basNbr+RZfzPq5P20VnuzQhm9cgo4FVWVXqJ9lJ4GOQmt
yQngC7CBEknhLE466aDvzSk7Pi5O06EMaUKsw4swr4LlXcAiSGYJ8dzLm8MuQ5VGKzFcy0pdSKXS
qHxAb9aC4WqGBKknPmZu+VkSVfnuw3M1mjMYAuWpmEXt53RFfnpJ9TfQy4Uwat97crwHNnWjIzKF
TgPG1ZGrye/zejT0fMoDzz/vR6hjAWzUd62dSJymHduyYK7AxMIMSBBJrepM4FjNIshE8HnKuVct
KwiV72fzkBldRTXsZvP7hSpCde/4GzwdTODEkaQnUfs6YLAtxUsErau24f4GWag5GVRX5hCoJY9H
kL45SR4VZwQlyZv7g869j7hTTS8/dCwf56tQtCkZGfHIq3eKESxf/l2eCosg1lsRLWx3kDrhSHJ4
2I/tZa7pJRtyjHSpWkr3ED1EP0gRG8K5I6KYAEzrajlxf3iu49rvz+G95JJUwOCSSZYpYVi/5gFh
nBWXhfNRIXbw9ZxonDuoN9gic1ORZ9FPxGY5TtFLj+nkB7CI9lwQwTjVm6gW/2alNGXxLhaBhbEu
7R2BjOzqdmOnFJ3jz1MQSVEsqwJA7RnLoHZDWvJZz4+W17VOZvHUSOhZo1QN9/q41e8hpcSSkj//
aNtrhyOT0EisCYZXanKnvV5WAyVi0BpuseHyVgVnHvgM9nbppX+6XxEq0n9BqtWKjUrhp6GAZSy2
Uvh/MnqTfHYKgrLOZ6yJbmthAzaNtPVC8tTI0dManUl5OlxX/eILnQ/r/UJCt/V5EEKrjDEyf1KP
riT/yxntphFxN5YjvDIVt5iRnV5sLCkaRixdlwQgJwS2RDxHv+8QS0smrjr2FplQJ8yq0z+uwKSS
7zVX025gHkSMM+hmgshIU34h8RVE6b2cJfghcGw3HRU9DB65SFVuk93f2niW6w9i6wvZoX7djPun
xHGO/AsZv5mgBQPKL2kEOjZh2hYYOe8zm7KenX/slHo/3C+knpTXU54eFlcQl2Ur8xKcM7qN/TDV
ce/3yyK2SdDtiXj5QeQVosP6NnwBMeAQP9B5qfrko/HGPbfYYF2ZLo5FxV4n566fkLJE1xGK1YZJ
GLgI2bT3CEbzu1D5puSpJQFJ3pGirlTZgQh1dIkbUnKIO9hUJVqmDykXFMCUkbauQoH2JLX0EOtE
GkLktdcrNBUZ9gjuGmd5M+c5+6EN/ueMYvvdOUOFw+KMvga5mnTcSycDWxzSRTjVeUPz6+mI5AA3
m8ZGgo3GJ2Q83vDooCK1r/LTD3ZehdEc1jKzd/0NgQXkjd25LTrwUm1N+UrVp1prbARlvQnVlUnl
hdVZBmpFpyhFL+oNiBN+Zt75FLaNLK1oYhwdLHzglOJBKsVS38ZP4MpGoe84Yjpe7/7yOh53w27b
ju49/CxJD3Ryhz32/gaxGCsx2nhJsk9zIgT/23+6A3yrQRvFp0ggOo8gZTK0spsuGYVTgikXY66v
zCEXfHecFdemrt9oH0emFKGD0OzPAwwR0aXO18XzUzLPNLFv4cM2j/sAOgG35vUMUmCOvzmm6r+y
133qIht7ovvitTxncpIvkGUwQrueAl0gfRfLjVqUlxX6mDixfr/M8XSvS864yaUoC5fD5XNqTMoI
JBTDzs/StLw1nHmk4CwbK4hroAVXYuAPGQHhRER10N4bPUdFG1lQ3uqGS7Sv9DPzCMyctiF4h6zU
WDVX0FFnwGc0nh6RUl9PHJ4pvG3bYyzrZ7u+u5L+FZXbF+3o5f3w0CSweCxOm3C285Cj/rR8HSdO
qASzrRIIG59zefYX7LPHq+Eyzg/E/M6SOfv421Ckw+AxTF4gGljzx+Hc2yph6VFcbVXcXlp3f9La
xzvmBbkKdLl4ycVUxDaXxzLoilkKVevYEalhI/pV0bw+4q4jwjQeisdvA066p1eogd646s4rLIOM
PtTnslz7EogrzkOCbCGUclHXLEDlMynQVlno9rwOCyZpyItedXZvgKkstbqoY5wZnmoHhUJ4rupJ
TJv6ay14prcqfTHuC96DwDAwFhkr/VAS0PIGcWxTj2hGdWWc3+ocJttG/prPKrNQYAmPMzGS4xji
NErM5TrxBEI9gnO+NJPtXencUbdfqMXRRNOqhfnpk9T9mbQ5lQabRapLwglnX3iLs72F8gpH11Bs
rNmPEVXYkjT34Ju2mBj/n4a22gejklLhAn1v+yHulnnA6AHoSsC73mFtYQXaHRm7xXharkdgcPVa
8kgOqmozIXgsY5btfElDKh72h6ZQbJkrh8djyds9jsG/UR/Pec/hDve0EHTO7fYDf6QgbeITIaqG
EnUX+OYkDGj7vic1snWFL7YwDaL8S2G9AQpT7E59mI3OG78QKLA8luPHYTLqZqYPRf5g98w8Z4eY
3jnwzx7qfCMdv1I5G9dWDww2KUsbKO+lRkV2ePdXv+onNyzCxfk2RVfPk63loivbEu7amhvQuI+I
3nAr5/hdyGMs17mWHrMxlRl9sIWk+UbTKcKN+mnJYHuCg7X/M1hVuq8lmPxBmS9/DOTI80n/HGV1
Uk+q/Rc4wjYcHxDqkvS6UCkYhaBxQFbfpckdUjcQKVYDNIW1pMkD7MKiTLzRSANNiDEIW1pATaXr
e9sYSfEIQe9oKySWHYyO/JmIPs6ZxEd7nnRG9GuP5jEq9mhfcLyIMr7iCWDpAgTjuz/wY618V9Z3
r7+aqcS3464H2EzPujRvx6+55BYGSspIis/e7WQZdiEDW4ICsqEPnllmNk5RECxz3URX9rZ/XjFz
U6Lr8PQW9Cosq/qzmkrF9gbm1ypC95ktMqHJGDDzbhgZC6x10ldhATQEo9hBmarJTEapkafOvPNi
L3aWRQeNOB39HGv0Xxr+NMyCSYYXMZdayqZ+8MSTLvrarO2amYXpCqHVyh6/O74rkGOsGxCpScJl
3xjtX5DOJF5zE9mfwGUCO1n+8UYV0KDcYi5ShXhO5K3dv+DDScO97qJJcAnRmaKYvN//TmQvwV5R
U3uyFNhGv3R7/dbUEzVn+ZVt7lWTrdM9HpgOZh+eiHigBePb2D0Fn5kp6mVkUY6PupkNI/+OcCfs
PAqjxPETh4Ws0GZ1V1vvt5mWa6mMiWzRH6flqp1MSOg+iejQH72O/pveAyqNXjrRu/qV/JqF4UM8
ArbPlNURZUUgKEzc0726LemZwEkd/BEi6IDyH0dTHCCGMuL4OVdCpz8lMRIi+iixpUvtxnkzQ/Rq
OGTfnPBuPpqbLNIgUez+rd/gZOuzWbmBmGnvQlaYXPXExAazC3PrUqBrX19NUPMg+x7JxrJhnmhe
Q4QsQCsy9GeLr7XmrVGirdvdSpMbCTWIX02MpYbb4lKaUtQvuqgYate3mHMPFgfzdtGHgUkWrnRl
78ZxsQxxxJVc63Ze0kaaXX3Dg9St34HlcaGS0zTFunJ4AiJwII8wsW2Zuy2lEvPf2zNCz3HSyTEN
VwocrMHTf2gAQoh6iwOGCnaRfagrqPCUVHUEkN56gbYnUZ94ClizFiHPDea4U0cAw7itY7bZJSFg
m6TKYV9MSOxicZEHs392tPIVJPW3aWKbrOk9dAEHLYK9smx4waRRMwd+ka0PAJp8jcfuqWVTYawn
JrDMRHEm+FTEg3g4ru7LZg094wIMZ2Ok5ovjuqWGUkOn9asaXMD4GhrLlm8zRO1FYaLd+AaZjV6O
rWoQ8uqbeEkWVqDYiyCfkOFNu+UH4qIGZKhaOs9c7RKtm8W97qKNjqbHzNnNM77h+u1n7Met+Ybn
uYdMwSVenxQGLUYWUoGmtCZ6EX/Kk0pIRCtrO2iHyxb+ue6tbZ1o57GsUICPCpJjS4fAMRijYMip
/yMSWWKb92ECs5dGbLvCykcR7gblEbwoXLlNTqjvoPMaZqQxoJo4DV5plMoyiFL8RqyUlmQuIWnb
iw1wE9UnH8aNfbTTduxwuHywmEU2xpkgST8nukntj4+ocgiKjXa+Cv1Rxo7RreOJ6yc2Y33TQr6C
OIksdtEt6tAk9Q8o0eMYzb/pVu1zbtVmdb0D3NidGQNEa4bC7UjGHqvO8VhExLmi7k9qCweAYJ7r
VE9+4NatG3mucc/AxR8Cd3K6q4qwywUE8i0GUkOEJMpE3F4HCuWDGtp92i3Ksr8ntU1+PYBHQ42m
wQLU4FZ1HlUZgqeI4/CM5Ud8H1iqdN5FaBynosesTU/xbDevf5fo3yCJj7JdmQLORWeiS2wcjA9b
NumzmKp5cqFWIaMeuldRfk3tsOjkZzcH5WC+84Io791S77p4Mqes1EW4do0ZDca8Sy+W9u+bDIG3
KogHpt3R6gHPEXvgDqnk8u7oid9toXmCh+3dBd0c+oOXZldxFhVTYpGTwrGFG2hGMQyunv1Ol53x
LIAy2yzPuijvQnZsW8ZGUeGXp6wJMbhaa7SRolViwcfg33Ty2NIHscGmZ7fTn07c39Yewidkxpeh
6nM7etDvVQ+PQd6Qh+r30DzL003PjROMMmhbNB9Ls9MY1bCMUB4UrBjuKyv2emWFtCuuS7QXV+OY
UcUrUinYD7YD31wds3pfW8Okx5dx/2GB3qRmTke7h33pZrRnaFlnRSMGxC6k/vRKffgg3yb+WWI2
KsgyT9NzDANECzjpLIzKv0cf+jfMEzg85j/iUSenOT5wTOvkCIsAi/2n9xvUy/HUOmD04WoR4+Zh
hJ9BBwuGp1jrsynlDd0B3U6jsV9JHN+ZKkPkAn3pjfyyhYVFzreoZSisZIrctDtJMWDsnsJrSqr4
rEadWcIbwUBrpFeHsXZY6dXf0VD0UyzctOEeb44PtVhV+CJUEgCHCIwIq7D2bSzX6d/bcyGdq2sh
yndQMZYqe4RDpMCvTnpkbSRuNXsGEIhOdkk/mTDFAHYemv5aNbqL80HkWH/kQutRU0Ef95KsEyID
NeKUQVc7L8X8Sk4PsU475LEhLXZ/FFxL9REB6b7TigaNVCAxJboYW6Rk3PHX/V/9KD6aodCGmbJP
VnTa3HpD6da/lJlj4TXZqhPWVjDUlZwGl1DbVD3zP2C1ccj8Unep3QpI4Cyy7CutEPkHxWa9hVEL
BNkLIWfzoP4MvgysfRV6lK2UN2DkqePObeGwDn3Qqo0vedCkVCkDvU7UA0TO/HpcLtQwfVa+XYoT
h8qtoZUnJ8GpM5m1gpgbGrDK1zuEiZYLsPULvflSTiz1Oy05YYFEOf4PcuqGCH/Qmp6hdaLceyTm
FuzyZUdLOS4tm599IDjjLN8wXs46xxIVXQpM/YqX9bLq7bxNCZoT39gyTWr7YgUaj7M8MQrpVCm4
jSYqMxmNQ+J+gNtAL5gSNtednn6gpCMfbA+ASou02Zqfqf63p/6NPdNI5cG+Omta6s8QtDSZWzA0
NoGOZ0Q0F3rhCoYQ1UnIgkmzl5EY+3zu0eHV2mseLK/p6tdrrY/8W2YofMtKpzOxDJ99wiO7O1XJ
dNpTP+NHU3jxjbQaiFjTjv14uoUoYlXqvBLcbSnpums4lugTqPHyuCRWr5NLLcBEcX8pnKL8R5Z2
Ig9xfpb4ZK1X4Uob3RNYSeR8b74QSnkZho8VEYdi5JG3nvchJ15AAHgYS7zCAe3rWsaL4bSS3CsV
Db7kDbx/6Rmy2PbeM3oI0v34EJYy66RdNxt7DTndElTknqLPvi4HSg5lKVHsrUiBla6I7GGAxSfW
pO9s1o5dO6zMn96ruEKLLLj3gt5+dCmGl4uv8gYq1WSOGxM3eCN41rVrbGdEYNXprf94QTNzCqQQ
ZuTYYoZ3ReZHGJefXy2TJWaQu9Q9ySAHjBfKnNaOASUp+7VHX+v3FORBbZZ5+LK+8cIQ6z0O6TML
Ml1TMm1Z4DdoYUtS3kPMnS1WCd6JZoFJ8+PrDkWmOpuZbR+CK3TfXcKObCeCmZKxAtDTg7W/Ov/G
feaudoKdj0yUWFZs73fMA+nnuEtMyOVxZSHkKRYE805WKPKfJqQWVi+TB4DC+kuuv1MFVxSFMolF
gp9U5CX2wuVV6zEGl6eyLQJ8AZwolol44m7/dTcDeNd9eVuUwKqm+Qs+G4w27oyD1l3oYE3o+IS1
dlln1vcyWnO5gnwO8tujC0RT5sqshjH+sxFVTJdYLzhrJgVbXql4mlYk3m0B3GHfirMIGY5RoPYa
+v5X0axrg2/0LuKrdXtYy/zBm90Hr9Pp13LGon9cGCEa5rYmXRUu67MiXKL9TDAt5Um7pQrPJM8k
YdYuc3P2IjDhLb/CPA8vRRB+jI3PxRku4sX7/uv2qwY5aLZw7bA9k0HSH+pv/PrCRz/EevvcYvXN
TJ1Uq54uS/+VBGySeXlX5r8SVQb/ZBWiXsG3sqdK/jZRS5y89rF2EMSmyzpE7/YyjpIqMSk2QFhH
6gGs9Ko3tJE7breCI//r97N0u4COm1EvtB1PCAlwJ8Bc4b9R+r1ehwtiiNWfnbEP76PX4oVqu98u
iBzn1CpdGKtmAi0f7vgz3ZvP4vKh3cTIaw7LxnUTXdAovQxDGv8tInuHNWTHnoGtDYl5ZJXtQ9mi
fsPnPBvB5i1WUItmwjxxNtAEcK8cy8vu0O4v0vdX9i5p/6I+FLjaSqqHcTTSfB37KjbgmjYR6caX
xgaNpNf7diWN+jOyTHaCRFPchIO91j+8Q+AefBum7gjgVI5xmc/JY6y0gy4YaM90lpZB16yNY2pQ
F1/nwp3VZADg/2XcPEu5l8Hkxnk9bc4FjYkVA95IlzT2y9eVZG4HjDoEM2p1o8Pb65rUPvBKFDrQ
hSiKyppNDHh05jX+KVWsF71ZL2QR8EcQ+yid5OOqgfk/SF3QPlzuXgCkHMejRYSu7QEZIbbtFG8M
7EqUTwhbLjpaBeNmC+zEKCAiN9IznZubMcPJg2V6ZGQEmA2WUedyZMXee/3yDLbNCkKpGJA74Jci
UVfVtPP2K54d7J08yFIAJq2TP2P9EitXzlOCbk9FQojHb6bmqVhssBaKg4mKpj8AGLJUKee3UwG2
QIygpWghT7ybjFy+zC/MpPvJNJ//1p1PtK9H2qf6Qy5K9O1mPlofi9QPAFUdzN2kICfN6bSpN5h2
dvCisY/j0k/kujr4pXcwswVjmNXSYUczU6YV9gQDdo6QbLe5IwdYKGnqH3x8Hu4+LNLTfKR5gxJv
9Jt8BbfSo54faLuclSc7JVSbFBDS61FcC72kFhm0D4j+ULqBe9s+2NlBolMLh7djTQxgyYKm+Z2w
iFw2ozNUYdZxFBHwxxT6fC/pmUNN05ArqXjf48Hr4S9T+isagH98N2rxS9KiKAH/+8mMdOye1JDj
rD0SxtOQaAxxlXbaN/NOyHTNQG/Jv2BH43F3Q0iG60Sjghb8Hy93k0yDuUGnB5xEXjSi4ic1vWJb
9CdRn0giuLmNpFFa0LW7TfZt2t8NTZZCFvt93eog+lqilKOKkuSIAXZ8BO0PSfI9rKHPghHlyEs5
SPoxqnIxI75sieyI2rfwm45NY2pyP2LrrgfZlhuZJWHzsXiYxk/nz/rCzk7OSvrkIqdKjT60gIRv
n3+aLrJ26uDORCtruzhGMp6fvRMZfEos9mdEXjj/g1Lo7BDCl6cQdSgjVz8ZnCcFf5WVHuhqZVDO
E7cTsVufyALWCWI6eXUq11DqpwFKpeA/cKdQ5wDZCJ4iU9rq1dE6Dp8R27QfWnvfdiqsH+JAfEJI
xZhhynm5KRILPQw3z1ent7XR25D7CtZNcpeqVaTqGV6h7iRR4TAR0eBLunobKIDEkpuEb4qlyr/s
YcHaL3E/O5Th+B8g0/rj5AC8zY38qjaS2CbRSSyX54/38hfpjJFJRz3XCKxuRSDqoZdakQe9g269
G8YgZh6TTs7jSbD7apOeDg4hfRhfII9sg0QHdpfGRYgW/546kRHh7KEpQkKWO9Z1PFeOukpNcFMO
AGoObTr3nQCEflZswrtWG/ae4LO2FIeHPNSe67ODO3N0qdfjb0V2AiNSgH/1AYvCjkUuTmGbPAq5
3glEPdktFhfTrvkx6QReYMgZEMv11BYo4/RJh9Udldmp//vOgkcT6n2kyspxDdhAhvu/QoAoxwCl
OXnY+CJEeOqdGRtyNQBXg/yHq5VqmMiGtVs9L5M5Ppu4+D0OZIi0qq8kHn9BkHnuuAcYOd+OvE/7
hYWSDUWVJyqD119MK1iYFb/t4mxzo9K5bAioY0Xiv7rfqcbDK9095/D5RCJP+i2LV5MI9trnAayA
VWbvPVHjMZ8iXKPhpWYDznUz9C++p4mWNRg7I/RYUfRbg5eyjc93gP4ICZsnNKtGcs7Lf1G/bGrb
5HkyzKYHuauq8671RtuXxqKvEX53nMQXkF04/XWTPjHubnk/Rzdv1C/XPmhJ0Cvrf5nBuIs/9Lic
1gPIhm7GxYih5/qhe6xOytlV1vjTu6szqZvVyxLBGgEGBNbinmP6cEHzZzn5OZjWUlSz2vyd89Go
NmvLh1I9lkq9+sJUxwiOGMZAGJ/XYcHV7wg960zLHedO74B5Rsg3wwQpVt4sa1EgsE8ZD6tiKyjJ
t6yplixwRmqKZRkPDK1lS5Iw3auZYWBSKZ9KecCRjjCZtbX6lxgJOD92y+RSi8BYv4uulV+583+/
VmmYdQDHWQF1Rhza2rwKZouL0I+A1Iwj/LuoMmxsHjHsjJs3MW9/PiU4rhWCzW0pZnug3/7xyeJp
CTFeN0pvotwhzBk/KUQKs4aX9Pb/kzr1m+fCEltmp7DYpsCv3kZVLou3qxENWLrgUjQjDUt9DDc8
0glnn7QWb9fqgHhwt6S81L44VBPGAEFMHE0npSs3kj2Srdaf3qbAyzUgXmfOXplfEM/ezowDDjHw
kwi3ELfr/6AVY8T5JQb98eJu0EtqnY2W6wI9OYX4U5sJe9thSwgt7I72E98zdVF4St/eOBexU6bA
rDf+LZE8qqIw3OPy9Mp7fTGj+eDCT3WT35RcIA9UHgmN7nKUxQJquxqKKmseij62VWVD4fl6OwCB
jhuvNtrDxbRNuFlDJVqnZLkmO0tkf1eM2J3qkual7EQ4toHi81NgSGkj4NdyQ5r0I1sI/FZ2Ubye
vbv2wmQEwkcW5LjJtIVOX5e0rzH+2waZPt1MTUnamCgMvMefpHd31e5s1+xFaZQfpFmU/7/8AXAn
eT29qEYtROj4a7hs7VQ9/yG6OrAWQdUoMRJmnCwByaEC95I0mDE3cW99sCvHbHoumbmOZ9zM2LbA
1WVz8mrbQlWZG1wyklr43FB+Lhy3p21N6ayScbN0cjocIMwlS1/Z7cukbt0cV17035Cl/f0gGH+X
8WGJ0yi25Y1BLAYWMU8IFG394IW3UuNHMeON/dLPfIAowyWc6jxOzc8WwCy0MwrC23XoyPh2eA9L
DT0+vXs544lwJtb20cxtYk9T2bBVrmGx4lMh7yipc/GH9dmwr/GVXtm99z3Hk4Ht+UgDcA3JFOPY
K/5mPcNZmb8Ds+StMmu/QFP9k05P6uhLMLiXQkreMlX7YQJqBtO3r3VJRXjmGupvfQGM/oN1P66N
Qkedfq2tHj6wYQ36G262bb8zv055mpX0/3F0YZWakD9yVhPRjCBYY3SJkoYI9wujZ3aGX/ObQTBw
rmDohM4v/uOBW05iVWfWRc/Blt0Z1l+0coQovkBqKs1x31qL5/YlqizhzOLYNHaPQ/qWLT/E6FlL
YPtE+8xhWNvc5AMbof5LkWh9tbRj2FUEIFFR0fI+15hVhCEt55n+yXUfC09Y7oPXDmhBdGG9jiFN
ds3EortHDjyJHZq3QrtQUEdJERwv3kwsNeeR3R+s6ofWmZac+GHtK0+6CU7a5UmYUucXKieJ0IDI
WcKkoCrR2EO2K1oAzx/TIURaTSGYGN4lEO3xq8bg7/UajgIjwjzlKozcoOkJfdqVP0TfYgnz7Eoc
EKkeeVlgdF3Hxs0sVnxCpT/jk1EsbYLEaTOmgfP7ltRO6ecVbdZDwZjfEFXcXh3N67N9RVFQFbno
t76v+kFIqSQRVTGw486xOpmd8bV+Noq3SoDMT0DwRrLg29D6mgC9uSNqYOanr/MwXV8UANr3rLW6
s/XudVZUgcu/CeBRtdJfWVqnKLO9viOKptxWbBjizsi0rRsSnuG54D1zckem1jx7mjrZ4XpC19ix
rJTR53uCri+DE2OWul8E3UmM4+ttAP43J4wU6H82leKJhaObQU4bL7uaJ3wV4N46Q5OyVy1qCQ2Q
Q3qZM3tYYtSbsKD39OlCQCZTD8ldFz3x5b6Aru9QXxhAZtoG9Ylnxr72UwS4mMrFPnGtm0W8vApQ
pHpI7v/O3MCgIbyOqBzc+dxWu6onNWcsO+8xwDrX+0cpKaTcgG5JC0rZ0FPNT18HvSUxBrEaLQKu
Y1XdsugalGYYjeyo6Ax7l+yV5SX2LL2KXFZi4bNDa686UU/cgqNr08yQMJhNk4+6VoaA8W47HXUH
VKZ7N0ijdAfto80F7zvOZQ3V5ZqLgU+ohFrkuLVN7/4b2KuYL5KpQtYZThbzIIn7A2etM4mN7U5i
7oL4cLtXbLJSa0/TYf5EqbzNvCbUZLcgJyli09h172od+Bpd9wSBgpNqv2PAVznPT3Uw1rwtm8tp
hh74of5y/+eUC/ZVMNyBc4LwJKlU/el5md5sg2sId1qsPlEJFOqcvLviawE8fp4xKy4ZYbOmuuj/
Uaq5Ff2sRcdMLKlx16f7ZbggLEjR1FGaTzawQLDoZv9cNw5O7FGRfBWFKMTCgjkb7AC/OCWphOVH
Ztl2upXW06e06mwZGJ3uZ/kjZjRB8Y7hhzXReAqGUFcvxiC2G6rJcXQBH6NIMN6ZjYEYfmXcsM4M
9qB4KTXZ0u0R4Atbei0+7CJhEbgA2rIm6liexbb7eii3GgZMm1tN2KyJgbhwRKLZNEs6KrG2ZOU+
NZtrGGvP59D/OchD/oYWvC4+d0xkyRGdel0RXC+rG8+YI5rvCO7XYXgE+z1uteBywF5YW6g2yGQE
tlb5Yk5YPOKas9Ox1kt1eY98Ic+9+0BgIfm77DsEdYTGZO+VyT8JqaPDS/7QhKVvnj3z38f1/Y1t
2fRKWCUQ5pCo89kwGF2tUdKSByc6DIHpx8R3A/JxPsqXgEtxTFNCkv6vhYcRvrZlBuwaWmvuLbCK
Bga7oNl57MHUnFlOg2VUm7iWH8LdOm6Q7/B37WBqgJ6L/jlx4KOoZc3KVRpOWG8yiOSF3uZmzWKY
LLoGRNCwV4g21+HibUL5IkF0BFjaWIvRYgi4I/MrvlXVts+6R+Nh3lYSaCBKP94sn+ciJI0Ay++E
ftktllIWdY1ar+KcakP09DhTgfzXb0Y7yrd0Kw9o5OddaH5Kgp5u9k1dGH/Jws3lbMR+nHtlyMNa
dN7eFFiHq6AGcp6SFKGEmVnUFbh6CgZJruILafQpDgGFETPZzz7DRZ56im472xq1TKJk42EUj3ab
fc8q/wDIuK9AhZszjfMfAqDRHSzwkFJ1tz66VbPyS3f6fZZ/DbaahXi/nEurMQ/J9dUWx4q+XjHe
GcOPA6DDYIJJC4dHs9OPL2lHHsSw1aZpN940bSHliI4kyfunBcjYrHpDqFAHygaqMSKXAJJMDX/e
FOEXqZtUV3roW15zqvZkV0dAEFzLtV9n7EV2UVwAshfhZZKLeqtWxFuvPl796FWujzovVIy/aP8d
pRdge7TVmPyZgWOxoWKhB21bm+KwKWoermkcRL43vw0Fa9/GZcFqNQnpOWAX3xSUgoHTJxzXVMqO
11mSYfBBT1aWYD3yEFrYweydRY4baHV6CZr86NCeyNFMLXFEzO0sx2iML5QxPccICF8hHKU8mgT+
9H7e2Q3+IUh4JDNUKJaBnz+CFK2FdhqKuKemElOYyVV7axqDFRfYyXHuJ3xeB2/oU4S07Rorrshj
4fzIfxap2NCWeec5yzViJZkHwZTF0n+7S5dTcsZfZAsyXSG3Qmped54lLr38Be3ooisyYQkOO6mm
WPUnSDiCcJ3ib6b6e8bDTkvw/ziiV/2JWt1re7q/GL74wF015jFitq8tIW4BpffU8pGjeJ+vrWI+
IqchRwx6stvDvRJ22k9KFviP0mGcndT0tIbC5EjKoDZOZs+sycV46mkvfDDLLyPvuguOD58w6fdc
oxJqz8E+71VyvyCH9cM3iybv8tVF/6Vdwij6M3izUyl524j0Vg42aS2kio90oMuIy3pNSibANVsS
IBU6DDBkPDowgtSf/D+O3UEomfflRckgsV34PMT+PujKnJW1I8PW8eftcsCaSXvnxpzIJfl0whtl
YcOd+qzTQWx0x4R1PJvu2oXw2FJc9c1LY4pnEQk0xsOXjj2LNUhkn+GSj3e72ynt3HyQAs8z/HOb
o1UWD1tqThKJ6U012Dq7hhsOi8fT/Na1CZXHB2cixfqBaNMVebG2AJH1Zq5CGLWQJksMC/zTzn07
MBjXh4kL3waJjTzM6AW8LesK2xsUz0TXzzlAWHXQEgG5wgPzt+EXpG4o9veuMnlGG604qvslRNn8
pIS8OUMuqfSjndtYPYedq7OF65HD3e+Eb8Obm26aUB7JqqwCMg8IV6zdMNjptlnCo0NQNq57bf/G
B+Bj8AaI+QLmmaowGGTaCy5sa6QLmyqjVQmE9EMVsNSolnahF4/qW53cEHmCN7tfslRztrw0n4Ec
DeKdaHLa3pZ8l4JWUx8C9Hi604Ayp21BX89ZLXsEnea0o9vMPKZ043fMc4tepte0pYEl6cmZ2TDk
/Lwsw9CqJFO5XjkqujoUFel5g13UX2EB7yU9erTkG+w4nV1zW65t/ssyqs9hMo14h5vB/zBj28eI
JztlBoxIsylwqsQrNgL2A9nMwL4zuAvCKVxGqYqTNIVz4JpN7+fPY3DQNInL10hJXqMC+PVqAZLh
ZjQr9ipuB+JyJqY5Jf/nuO8EiAYwRiZFrwPY8+zqwCnJHpG4+PJp3MEx9pL8wxUm1mJzjEx61d3Q
w668QqQLcTvXWr2gE3SJFD71DCTF9jWAYiDD3i8d79z0eVeDIOvzJ2/X+aZbp8Xu+6P7s3G7LRzE
kn6ljkSOb9C2SYD49tSdiene9Y6021MpKeriupUq2mGnbGkVIj449UpLt+H+FFLK1TrJtLbydKnE
9c+RQqifsn7TgbxHd1bT83j51gZfL4ke1VRb8Rtsh2SaSmSzraBZsVsp/6eQWD96YcnE3X7JFGL/
VzE9CQW1olJWKBgdcBKLf2xqHJ+96Qc4vGgBHnJvDZ3gacQLp+VSomMnNOiCQwh/eaDmFjzWqytC
9bximq00pZeZ6JwCvvp7j5K9+NkUMjBq21c1Kjg+dEnvoZJZH4n/XSmGT+e54eACHJ3U0dIhFxzc
bmxYasX/rX200c6dDX7bej4u34Dxyfu0stYIUn94jNOlUMlmurUSEJ6uMuGhDZW/CpmLOWL2YuVL
Xbsl6fa0QVmVB986/cEJa0/6PZuYFeMjp56WbW2b2NGnMHvsU2rdPQ7IZFsRXgznbFxHhm6B77ag
70ue479om5293atZmLsGawIdh//36wBTSRhXS8TIvCP/u0BDBtabueLV/X/vehbPS8SupcH9sfoS
iA/pLq657T2WxjWPKOeLszLsRGeXR4M2pJw8A4EjvdGMKb8T5cVZJTcqzCIAHfa4GOM6frx7PCk1
GeGbECSB+pADGFNHZfeNFvSHFdZbcIMLY0naMi9GeAd86T50+j3k4bdv7vGGgqzoMbCUszWgqCFW
Rs+TftozhnPuyDgp3thgYWwaAK2Uhcq99xrBGukBJtTq90twb03+cYcuk7b0SQpqIeW2mTarjExa
sRk7Z0kf9dmGCT0rvxRFfXcKUHskUOyFewNp2YROWtJO3qSD8v8j3H4FOQ7iQFHbh7JclylsEydX
Itx8Ximk+jGqw1OjeMjz/7olEVA93PswW7cXdufx3aBkCKZ3gUgNsxDuj6G8ZdkxzOS/uDsIy2F+
rtapwOSbdS2GS6lRi03YafLYZNQ8B/yE3L0izLImbzJMNR12R/9wJ2phr4pT3792Y//qbSYqvSps
dNCaLi9iTH/+J6qA4tWBoxTI/26g8ft3IX+HI4ixQWa1meRH+4SsytZUbNQ4bWtu1cW7RwhZlvbs
bJUAZbGghAghXJm+obUSrn+qWHwddDbgIu60EufaIjnR+aGdCSalhYjMNBO5uVTD9Rssec2RI782
np5LYC+9XxKtSxFoMasm6I8EPMy23P+DLaKKpm3zNdPBQJnnFbz21F5LjhHaI1kG8gsOpUMfmOaK
TkTjMRfwAO5nLBd2/RfkPFPlZbetpCEqaoQ3WDbbD/ee9LnXLEyhnqa/enFPAxN1yR2fGa5dnOjI
uDOmQls2jFYuaT6yjJeTKGLczDaXihh71B15Pbi3xrCJh2fxDdIv/UYgoy5H0vlMyNFRttQhQGFG
K8PcDXePgXQhMsrEnRTFYplvSXf2zFCv7uNcRfWwyY1Swb/oZ67BGXKNFHPqTQLZxDcaI9Y63gye
JCTUFguq+7ZThKOX9TH/wKxwel8ksh0dsmMGREtQzldZ+HGMxf5Ttg8U03snC2VcQlgtrg/wNwPy
nf5BNZDD5lZJ2Vyj8VJXQDagRVX7j+MhFgM1Ffo0+KO1CK4gsj2fQp7F/kbc4LfbJb7EC0Y1TY0I
k4Ff1Gllts8FJb1exM3K+HlAch6gaZYTMZtxhzG0w28ZJWLmyzKc5MQ60YGvbFmkuRESQNLZz0VF
vsbcStVMvYhVJWwUGW3e238PyOg9gGviiJgryp5hqH9WGUrl5YIbgaq+fr+6P7NcuWUMZh2gR+M5
7uXwR0PDzOKnoye80MzKQIaNelQ3BJgB8aH3kqoOq+HrzppmTG4gD6NbQTvS2yzEMf6fmVCbMQLT
a0jsC/XVKkYJl9HuEWuGNTW4r8x6quzhw7m0bnJy6knagPiCHXV8zN2xGm49xoLSQzeJheTNAIIK
i0LIou3UsnY7Lk6KdEQ+iUuldE/hizBmSCjcgZLphm8PFN70INbe2J11I3rziSOOSO1qvmYRdJ1e
XFA1JpaBQss5FSrbKsRjIQDFJBiJWsSmXxacBa41EYVb1lbSyfuK5CQG51Q+Jc18HO0qcSjsxury
/zXQYkolyoi9MrxqoTKeI2MC/chORZTrYYgJDaArOEdyAljKM3E327eJW98EhiOtvH9QbVUdqo5G
xB3PWWudQIeA7/46PtlCbvJNRVu6LIOxCO+pFRe+b/gSdFgAVlQsvOHgHNixoo5VAr2NR8BaB1kJ
AoRRzy10R3JL3F3ppblpNvDpUmx+IsqWF5e9lJq+6b0utxtaHp7VMuM1vfrL6fNkhkeUrdsmXaTE
iK2DQ85hHlXHO9/YdghiTUzsEEQH/JV3N3vdMhfDLxqNadyDf61KWMppuwHI8ocSPQ1HOHjkgVO6
Awl5mJEb/9l87GFDQnUBzAKcQhzFe566PtXiFFwcnqSu/6MdoXFoMHgJ6QqIighnml75/3TeBRWq
gy8MlIoS5xEXIqxqEon9qwlkoMf/qK71YOsCTojZnp9HutP79fseGUr1Axm+Cr1BZ98IsTzdkab2
zfRqnR64er/q7dAGZ5fYv/m9inRDgRHZI2aauVfHnBh6YaJm5JiWYnZWrkEivGZ18jYjRJoNGhqn
rx1GyjVYQXMwIj/zXZ/AAix8Q4p3Vu08yBmx5XNv9h/06Dnn8v1CUZcH4AQZ2BNDP5UmwZ/NGxvu
8/+qixjBTu/OCYpGKTs5it3jwSlgXX4I7JfnEdSXnpJO1hj7kGvo5+iX8DkXVWHetTKH7FOrODCf
zyFZYB7EueSRW5GyCtxXh+stymBzIetXfYLknY4zDWafBdgIAVY6Q0vBe+OhD0GdjqR4P8v+vFPe
9k9HvVnvIQpt/D8BhWjK+NkLycOfEAVA4ZK+c3XVHe1Wy0rlrCGWmuFW7FBid4p1mJlvzzSxWiF1
4DnbLUFtvFxKbHSJsmQyJc/40a83jynm4YH2SaRrV0go4UDESiAJF/gtuko4ulRtgnG/3U4O6uZJ
pKmCKm6I+64hbuwWa4F4bj2GGxCYAc8pp54cyo81nSc1WpmDUz77S0plBmyDr2TEqgg92evqnMQ9
FqPGQBjChkckrGfHW2X6sWe4s1sGgicH5LEyXqFlk+6pcQx+jLaR7enkfaLXqGwypvfzK0bpejsk
Cwctc59cxJCqVvHfutg8jKFAeJSNebjhngqhk4X1heT1L9ZkXJpW/GYg0ioZOu2YTTRVFhLagdTM
+z98xCQpADyAk/Fg9wWE3FYUgr3aPvfrTejf0s3mpZ6AeA+pzccceamXtsgkzhB3bwy1OcK7CY8c
tl9TcEcNQZlZe2cMp1Jln+UTa1sM0TYfFWC9ZuZL2bhcAl0Sht1vKlg4dYpvvWbmBPEHVn4hiE5r
OU2Bog4VkJBMmeK7NqfEO+6RD6viGkh//tX58B6lvPKT7q4p/Ixh9p2aSkDLVYHuJn7Pnk9HBcLt
Swhux3T2ntnvVyzPNcrNM3Khfl5rubAkP2NNcpm80icDmoAcEwvvuO1eFZ6n0ex6n/sRWmIhJast
jgYyGl4YmoUEcQbTjdZPnlJnQ6P13XQUQV3r8IUJUXMOkoWETGenRhGCNddlCDDzRmv7561nAkur
qj+Bk+Zg+jPy3yOYdia3OwZ7n1M2gcwW64aHBwLRYXMBKpueqcCknd/BzXBGX7LdCcu7ZTGm3WGo
9xbFyafAX8Za0RI8kQcL0KSDxjltIPxn/gG7v25+LtNJEekKUnf9HZiFuIRWf7O8xBSgkFL3A1Zr
LBTr4pkKXuTN9bqZxybAMthkSjvkGKNw6xS1KQmrujIqjAzq2xv4rtpLW7k+W1ZZ88agsx8CqXc9
SP++lwwdEkMHC/f1krGPZQmSzpqeNI+Hbo0LwRTSUcT1amZcjiBCb63jUarfiVaQPaTwDtw/Io5U
j+ZxMBCnZq1Z5g2zLXYggb19LGtqYet5UkCm4eM8HqWj9dE+EladHECcNiit9FYHlIvvamw/VP+Y
V95ufjv6ZqheMWzVEaT0pGUfkFYJjYoDYXjSRCg3DyV8KR3Itowo8z9fbGyaOH5JsR7AMG4lxXMs
zkSRf27In6ZQqhSXtdUhW2dVl/gxUIRM9LQF1LcE4eiRL4zWJonnYkURUNp7VcVvjH7vHJAE0mhm
1w+ibvQtb9qYlXD/9dYPyZPFMTwAoeIxdiWqYgLo4195uPDqyTZ3V4ZuKlM7jx0n+gzewHf3v9ny
jin8FCTlaYt9AG+Bv+iwWahNarKc866OjPkwGA0YBWCHe7V4gmJG0nAEKYJHr+rREB8TxIybaqx2
wBqjSPveG5ki1/kHloWpyHtV414p726fxlhEE0y4YeE7+bm2lQrimQVCI8HY33QYePFl/YF3222U
0ZDhwqj/5ERDEH54LEUz0OO3rfZPuNFiyP5jZbTVnUzC3l7P7rciAQV0yoR6iY6E1JGjPYreKYTW
mXTxIXVtQEJxYZD+OJ64GeVBWaMemeA7bLA30Zl5E4HA69cN4aL3oavTGo3KYI0+TH3KzOwalFl8
bsy8iG1aKFOCMWZPGdLW/yZ4UcytQtKcJt9BDjZm0IPtdUjqV6WVkFvsC1+aE1SldMiMbnhPG4DA
HNrWuppqxPS0aDH5+BNkC3cbzkrnHVK4MbRPt2sIwRkQ3AMf6q1ZIlrQsdBQWpb2EIRhqxx/ytRj
yW/N4EmgrLVZ4UN6HNxR4hNa6RFhv4h5gytoCO85UsYBYqC5hke0r1HCfRsCd2V6yNTei4QrB5TR
XsJfuloCu5kYVhThCeSsOHWMetPeD/nJGLqSmpcwX4ekfA9CIO0A0Nz82yJXDVjlurMWJo0z1N7b
ztSo58virYlIH+dEbuxdqF/LoYmCPyW9gtbFaagvKzkEYtVgb/gIpMDDPGi9ytk5xS5Dge+lecTj
xh1Q2aNpe5Jv4CMwZM/tJulSXi0lwlszCe2nI5FliWGBlOzSl/yk9uSP3I5aVvLPTgRM6fQQAQoK
mEdL4WTAmn4LINmqjc8QFGIoqohFe8hBzcq4wrYPH5EbixS6VLXgbAIgrCans+7LT+CM9OGmvt8o
hHPU+JfkSXJ9xRV2A4wKygOYQab3BLqwcIjgn5witjxS0nWhSlBplESEWADQVjjSN5qu0vKQY0UQ
CWV8xhyXW2ixZedOzMtn25wXFW4y4PQI2w5CW58CgoW5A1vwrx2UZg1mpzlJO63vdMPWL7VVfjrT
LuwVovmFPojHiZr4rN6GcpwU2KAgZ9Uie+lBEltkd0yJAfEim3XF8Fn64FWSN/+hHEoHpA1OAxcx
HdbilKw9TR34D2nkk+E/S+5wbP3ZyUdJO9HpgAtLQVYj3QUd6dzDwa6fuGMRJVY6AIdJcfGOIcHS
A+Y2A/cHOVl5Hp8LgbFHyLepckpy3A+Qj1F5AnVsA0m0SbfmdvP4/XHlxtbaZxRl1gvKjCBvxuf2
aXwty6Lh2ZcfP6LZ+2BUqqIkiyZ2Ympj2xVtLvh46BQpHbKx5vpVH3jDlbxQ0k3Yby6jwdQKVw/o
CTwLLYUN3xXkIYZk+C+YCS8sp0XoQTELKAWAYBn2vS1hA8CGYXJR1XdYYtTU/h9Mh7fIVMs/TxF0
/gjyOeIRlXxRPxQJ2Mbn1woOCgVPmyCmBzKI/0NODcUYeK99JhX6Z0pjE7FTrHbSVku5QLWSM1Jx
pAQ4M22cVDp2A/JeHG6Jn4XTx3alIhBfy+7XyJZgR9Y3+n9p7D0mRNCoXzPJFroh8O7AV756KxGn
UyKI7451Po4RDlVpLd9NzsWjphVuCbHZ+JVUf6y2GiVMnX10rJnlr8lKkhpkdubjTvnxIPRfLZFZ
tgggh57yjoiUdXxuK9pjNckwGJAKzqJnZ4O1R+E6rBzgtX+IFYwU+11+Q1uFcbz25C6ikItX9Vmo
siubx1qreungQMBDDu22Z31cH3heWu9KW9E46DVRUPs/RQwdMTpS26aZe/n0vnlp5KwPoKc5ZvCZ
EcOVlskOKIMMNVVyIRpnKY0El9g1Fyj9xCm5zxz9gxtNVyM19Uap3a4hUO3cdnrOU+qWbgI7NJL1
Q4w02vpGPJJV+f3zc6X4Yqzqqo7jdehav/2zw18pXd8UC+JP32upe8PneCmpV2FZLwjn71KS/aYS
7hhggFvIn3IqBGvLN2/ZRmF1p+6nCfDEIuFqieCRM7pAV4GkvVCcxgh6j7/YBqujOPNjTC+7jalY
kRNa4/fE2Lu0uk8HUVz7VFnQXOGqVzXeToJ0GZVRbLMhn2MSCl7ULd2kQAh7T2FgdvuMWYklWnxi
3VX2Gns3lxszrE8bkgMxBDtkENk3gdIHV4scNYABV0cDEcJNQ5x+g5iJTJcPUBnhTDEm4yH3OSah
3MvpeFXztjA+nHOZHZp+yTLwcvc17B7XStMIDnFfbzLhszumaGtPU/81Qm//x5zvAIGCEFgODfa8
nU/XKGnxS+VSCLqkNRydoXReDFix2MR/iwfElX3DjgiDZfxkyQNLEKfgBGFnnxnBweHYFZmxc9QI
CC4i851ZBdvT3hApUzFzLhaRyGjYQxRcXI4pn3aDz24V6n+xXk0bCJQfciIrS3mlDvRu5Xp3tm/n
WoGfB0b65KHCIwleHSwza+H1HZJTbJdgs972eb/CD+HT0HVh0JcKZWE8jl1uaakCPH9RqSUGz7Hv
iBDyYRV9N+MTuUPxsjHu32kDrqe37MNcAT3Elyh16jnbKEuwC0jtuP29tVJXQPm83aSrLVXHGHl3
6+uNgdo1ZFYyZKBs7PsYZjsVGYOz18qRL0omyPJb6Q7bY7YYx0NCXxM6ExBv/EH+cWfwjWgQ8ycH
YJz5mebrDP++lqdr9wrE0Smgke6SDZNogAPy4mYl9N4K8F8Sl1vb4+L7cd8hL0eD/WkCAw45l5He
tYOdQ3h6pv0TSi9g1DLhIasGv5dSxL2b/I2KAVUMU+SOSwp/aLkP2pncdzjZHfXj0yL9moFRG02j
KVeZCBCpc0temUBhuOogo0sl0REkvMy3kyx75mg47Pprn4k0OmWLvJV4AGQG8cVCV4tb/loTDOIR
rvnLRhGu5EWGfNzjH9/KM+P84VDmezF1tVIuoK/a+P63HUG/Jjt7jhcMZnnp5MhfVD//lRQGRBy7
TqewAJZgxuDJamICRJMqHXKoJmw88tR2aRduCIHYQLHWxOClVulkR+roxTLxMAAOWygdBDvvolTI
Xv+I9l0in3n5sfCOWzVgEtRCeyz5KqGeIUJzfo3Dri+B1VpLrkWDN6I289djg4m5pPkhKJ1kFox6
/rg7rpQRcDBfVl7e9N20THALMSMG/b7k+AnZ6LOWruBA2Wzdnq/N/eFXE0xH5OGsVpWQqJyDxujW
QbsqrkNoc0QS2Nse0BBB38mWeLanrQL6H/wFqBF63ZQQmTuAJ09ZZ9R+oJsl7KCbhVGZQeGVoGH/
PDFYtfWe6W4bToTf+KntPsqcN3tBJHBhYB5nk4k0p/mAZpTAqhPDbnAq+jOi7PpAhPqAasiR/IRX
NVKGk7sVcUuq3Hqgv70yDpY3rWsHUKIrOXeR5rWD6tqeoImDIo+6voxFA/fvrDAPVkKjFt4IepIZ
vcBDiqqaguBK/cUW3reHP5UleVkA2HX8KGR0FPIWkaIPYFHFuBSrW/hZXAqC3T3HX162W974pnRg
8B/VjmWusb2gyJghoN07SZrWy/3BqRGFwIu5/l/yc2nqnTiiN3lTisgLXwjpcRUBg1ismM58jPTe
ghKuYwtNsSLvgvZUy7xML08fdAJSw5EW6hRSe14N2Ij0gJpxJM8opZfNJAMAtB4h4uZN3QIV7F9b
+gqX2TKQIt5azu/7Dkh5tMbxbqMDHDQ4slPMZ0ovBw5OPgfUt41peH4bi/8J86hgxjXJHX4M4pku
OOYMHgd0NUj4MCkTd0QoBTQPOBzOLU6djrEyBPQjXIqJlbNd9LNuq5XeOv9NPUjgyWnQMe8PDqgp
jcYV6wsUIxOnnm0K5lzACzxPfSAG8T484CQ2C0SY4vonp/2TB2yLbDJ05I64ykrYlbHMaMUgGMTV
9QKhR1wCWq46Ys1/PYz0GG/vcclkzsezdXURR9kS32j33zyQA6SlrvtdTgVMJSnLeiRLlfAhkETm
hse/LHLXNzPFw6Th9NxBiA9R+hbzxhLOJyvd+KIsEx2L1csD9FdhrjJop9vNUWXrFUv/FtlvjEn6
YFptTT35G93NpbV2Z+iBBb/rZjXuB22kAkEjzsw0Sic3DpXC/JxZs96R/RYs5Yq5E3q/jzKl78ga
3yWtl6JfoNeb3ZI5iYKUxG4NJgGfaiPm4Vzl4YfJJsXozafxuOVuaxTgk3ubz6lBibe3WLtiKvrB
HkEl/qWtuw67GWZzaf62ZEgetnHGV+YMPTgAjCNC6I6jM7GtfDMSqZIMlt8XCb9R+limuPL1Nv3F
lmpaHJvz7Z71HeIwIHj8Q9nhxBDzO5qlK1e8HtSKdZgUDYNv6+LokeQ51aVXGWntInhhQXtyYe8C
6XFEeAkyrxdZL5JvbWTbSvVa/vI36x+Qod4Il5CSIBznPaUnVCvXxHCt/dewo8M0sUH2rGaj9dtU
iwKj93R027BKeJHV8kZh180EuJ8Irr2NhTArQKptJ4fSLEx5FzaW9gWX6GYsG97Myrp5hifNefrD
GjT3Q75DQRmAvjFHsqBaQY7nM3wP6JNe2uWXjFfOd0/f4/U7voc8o3ow5f6c3YqIV8H9BHMIf6mU
8vJy2H1ivDK7d5vhuHIO5zBQml87LD3KlfYFgAREPSkY/peKCA0VAljRr4Ll23oQfdz1H1AU7FU7
tq7Z00TaeGZYt/2KlyIXSXi9YAcPLc3n6umTCIp4qRseP4jF1VsZMNOPXM/5GQ4WhVXbLexKPy8F
wrjS6eHopij2YBBC+z0rlmmuIQYsuxDfugqejoDhihX7u2RUiKzBrG9wzX52o6vwPnHwFQVfCqop
QwWT4f23xKWxzh5heLrw8XbaMxgmP2IsrCo8vFb8Fk6ngemlqsx+nppmUksqEPnHWJhSZPvJbyIO
KJrb/Vj/5aWd2BXswXzfJWuQQZDEkSfN+WEv4NJO0r/DilfmmIUJWefmV7EQcQiLavtin/oPlUj3
ZRplyq0wbIGHdf3eyYzTKgWPp4iro2x73DoREC6FtbHZhuA0LoYZCGPTCouVIy9urkcKHnytyM+P
6NLz2Cn790O+rS1KCGRi4Kni/XmAUKeTSvchrd7Ue6z7TMloyFn3Ftjw8tgTjtN88/DFsJhOUFUu
Yo4cZY9Nzvl7gzQw6XIO/avUOBcGmJZGb5yTqNBzKwQ6XKRacI/kGJufsdJ9KTCE3xu+a+fOdjRP
8s2nngy/6Dp3j75Gm04Nm3TbzdrB2LzxOOdm1VEwm8Xq6ZF8mqYM3ogpfhLHF6dQkvJJURJAxnGW
1d+9nbleLTYFZ0T6k5jkfZ8CYBLSKY3naiTx2mYSuSbNS5c9nFacfqpSDo98jD2ZjlScSymU+ibg
IgXVmPbJfOssp6Hu9ZJdRFnJA/XKMOYjZzhkK35hlwrZKwy1CNiBqwpaMOJfKyWyWWi4YIWib2i/
4AYFf+X/sJpwp/OP1tG3kUBFPrVXtlydLdgHArcxsutR2ue6MmrZGq9eqYLw1wzYDEVcmp9B4yJY
MsIJuCxIpBKOXRG5P1LNgnRxZ+2qFSs2M4lsOyxKH9pl3Z3Pv9FOaERTeK0nHBIDNWZflfOJ73Zp
zKUwe8rOW87srXGAQlp52xRG++8i9HEY4b4pbmkkUzl/Nn1QAZBPx/uhXxz+jh5Iq2gxlTPY5Ixv
wkJdhdNL3cvtNDPxljLvLm/94GUm8hDwvDIVtESbq/9q4LEQLD7S5yZB5NRRP63XdiyJTyWSqtdV
tjQP2FKzUgfFv5pskJ0aEThpfsDRehW80RRuv4fsnzjdxpKvSXWdPOdP1bPXti/btaQpWPL9XYA6
T6RUrwNKHQy9Xw61vkensPLtvJT8mMILh8de8PYBROGg4UhA8r0OGvq3GJO6CgGAW8dMLvW5KLpY
CPmjH3yzZ5qbbJyPLCWrvAEvbeGRNahbLYYi0GjGYpjkN2Nwhp8T/e/WLHZ/mBky1YfiOvxZNKN6
YjSX8O+Oy+/eeSP8Bc9PIzEssnvr8sXc4Af/z5QcgPi/mdFJ3t/v91mQ0y2+47fNAO/pUWP6WK8R
K/hSJYydLGbfR4Y+jyp/rKg46Vdn1Que0CWt4GNm7a1QYrbkPWyEDdHrbt73h7s+wzaBNVfFr37R
cDy9i0QWzqFzNW/JgNq2kMCmbWS1qU359v8dlXE+PLgGO8yJHFrE/wOGI9kWKVMK8Rd4tfmQyQZX
a1PfTQQhL2K2fWEotKYWFjKltJQ0sef73ZjuOv6i36lpevmEw8bLELIccETMF0CkUwb4ebtEUgyt
ubWXHKAFx/nIlnsM+qEmOK8ElJPeUASD+GQwNZJ6XybYHQnPMyslEVTwYIsI7gdcCZZZwShoPr4+
8jSvxFCw3KFF27M+ADvHzQbXZ3CuM5gS/uKErhSn0LCZgT3KTL+NJ3JzHa4+8JAYU6XkVIABSqpn
jWPlhUu+RQkSyqHxF1X4+MYxjaRPI+QCkwWs0fjtBXvwZResKmCwdI4auSh4qETQwqZbJoysyOBj
uLtxOPzlbHh1yVOgpXh/Kw1/WjNplUFgGFRJRsCu0txFBhupnRUKSu609/cx+d8BYpHBv6lqJNpd
CJ7DvTaau8oZKOA5OqxOZ2Tc4pofF8OT4purAXrCyWo+f86S6Q/2+O4pEgPhuOB7RfB3qK3mjPFC
NOU/WopisWdU5bpFTLc+b7rf5WfNLy+mWOC+j8dSHzeEwVcLougpDgwaTbJk3S2Z0nOuNgEba0Bf
u23gxxNzPXFOylze2i2XRp3aDxvTZDfop8/iG/Eu/eIF0NxbZe48I+W62CJVRUWCbEfNvoPPEN/T
K5R06OZ6rkc9qs0w0yLa/RxwgWz9HPgT+kako42FfnijkuzyBKZysblPu5CoZeDmO/ld+d4M/vNm
hOidq8elEtypcFs7qO0HaLs8OphMaYSYn2b9mHA00Jx5uGrYeXmLZTjWxOMa7ZyUzYdPXr8PfSOT
gPK1PR6GPiHkMp6HbhV1KUMEsCDqLaIHCEM+ssUHS94UryvUwJScSF8EzjV2hYoEYZGsJn5OD73Z
Oz8dKQ1wECfRSYkIdukKDjaQ0Y4fzIN+JxqSUVSlnxoKGq7tJLBUn4rGni4kxlhfXsuMdDAezVt+
Oo1UDLLHJLeWgegg8afDbXgUIwRxhV313edBG2NTd7swnerYGG/NVWICxGb9C/EU9v+hxFnaSY16
uEktVj0CZ6U4ShtD0fwySswN45WAbC7uibd7q5Ab8BwAgQzt70/xYLF6dB5a8j0YOymuB0P4AqhU
Sq57cSn8O4KBT5bG0+HG7z8d2lSPRFwuvpNStQ5nOR75gRxXr2V7w9bxMJgZ7bwLeA3j0pKmhML1
3OHst+gIp04SL2Yy4YAw7hBGobghNBfteL+onTNX3lIcW7yYEtLK/vrA8eRSelS3dKVXmZVo3UW/
E3C4oyRqfVNi+a4SY3LZNHEyHCHC+o/vBFbiLKfG0UkoLPn7LPqHjf2vWBu2oqMzfPxQaqqYH2vR
3GjLLstNFhvUBS93UVznkseBM6h8PRWbfTOkcbAZYl+JSiJK8u17WLKCQNXa5cYorzS1T6tsIwZ8
lEvou5UAfNL/KdDaezXMxR9k2o21c1ElhAK/JOwJ2V/+Xw2BGe9+u3rTEb/BIbgo3Mc89wMZRqiJ
EASfsnYWzlgR4a0Q3caz71oIh3YHsXOFE4JEoreZosbckV9BWuuI+J+BazQ44KGn83hUHbZErHiF
nOdzHgR/7gYkKYgv/xy662rYhgXyU5ViL+nRFMorDfYa1EPI6B7590+MYJiXKL9ut/LVPlwua0BG
PqnXNg2QSbbitZYxXWd1qOoXADMIxRkACG/8xDCNlpG6qT1JeZa/vdHE33+fY59Mrf6HkTuLJAGZ
FQVILNx+KJ8fCoBmgeAKaOvML55TerhAAkabZVH8LfebKqULbIB+UwLPLsztfA7D3PZcKu9tQvfT
gIC1td0GoZAEhUfBJoms8FT/UMGGdZ7GusItji29mx3zSd1Kduwc7UChfavDEfvvGnMNXiAjTq67
g6MUAqyKJJf/58aoqxlpIGTTpiAHVTkO6e+AZtevSmY+YxvaOPO45+sO/8ufvLhjMegOom9UhuGR
X8+xmSHOKFzPLCwJCZpRm78aGNtve9vTMQe7Rit8KiPpy2lZTDGj5CtnxJZ5FjY2EfeoGhR+D/en
Fw1TGZ+a3foRbYvVJuzYR+wtmP6uKF/OMNPfQRK1QXZF+xsD/bf+Ys+diAXKzij6a0EEYDzFflNC
F3+mspjSCtmIEkEFmZXEZUoJZPyCk6HvkDcyh0EqZcDaTkitASHtM9I7tsS4/tAOZ659owm6RDqh
bdAQDDwNUQzCV7KSFoy8b6unu2g90fjorWKTqi9OeKg64QdavADm5wLGExClehxnSOiD1eqXMcUv
dkxa5vZ9YLoUGW2mauABwTJa+DZV2S4MC6Eqjmy1tOcX4boRjUEhm6+h8jn2hscONIhL7hN50lV8
oaHiofVfsvPppjTYTWJ272rEbaFsClFtzdP8ImuwZbrgbCs/aebvvyWfNkwS+nTmslazG2rBTuBt
SIaCzB51Q2PJhA+xjZsZ18V60BfTVBTzD7QqOdESdMdClAtUQb8AjbChCS1ff5iU4+B5Qk0lr93X
ubq+uGqqy/1llNnSKqlRvQ38FePzsH5XAgYh+E3DV5SKD0e0EHPhnUA9wnaDmYv5DONKWnPwUjmJ
iPJpSP6BJw7tbfisD+KWuPLj9XcQkKKyJABh6mQdKTPAcecJKu81c0m+ZLHSvkbsWZ2uOgFLkjit
8YGl8MbEwMDLt0Ydo8DXt9CcZELf0BTSbHxQ004sK+qT3nt5y0aAFe7AcxfmeH1CaOu68E05PAP+
4J69F4pGwFl0trIO9mXo9D2gl/uA8bj0Bpu6RBZ6T29fGoEHCBxN7zdIeGFHvtNFXmL3A2LJO75U
6NmxT0QYsJH1YUnj204h1c+z5ZCCIqGZknzxHoH36OaRp6JGASdWg3SUxm4Ae04DVI2HsTZhYNC7
E5JhFnAC1ByRsmJl3qG+Tz6GjuvMYPPWwmgxIqB7pyZRK1hfuM3oFj2FcPCl7zm/Lw0un4Aa7qOV
BsjT3EES1S/qYH3EdpgoKFJRTlsvqzvWhF5BkfyUIriCQkYw40LAPd7mH4VsOXJpm7wbZM+zUKLk
MSXOWhfBRm27xjk++hMAS076va3bUJQH6E2n6jRpvuDCq93s2qi8WHud1xszjqK5//PS5sET5koC
5l+eteZDC5QQuIG+ST9L332KRlJD3oXWGQv63gOqwANj2HUu3zaB5a7N5K0qhPncHx6P1pXGAWXq
C9kJFTdwWto2KhlKNiqdkaXYU39BFxK7Je3Duj+ejwUK+prcRGxpOUCpwL9l0wSJLdz3XTU+fsk7
2WyAA+pKNIzc2Bs1Gtsg1ujSkNjwwWI7OjhSx08vGDThKpxVAMIc+xbK/DceS5bHvBH/mIcgRNRi
uQht3701XPTzvjckAiZ6K3DZDMJHHDgbOHxF0b14o5ncvsZKqpCOsVJcbKqO6uVrvXMMdIaTS6bl
JT78RTz1AhEd+cuSWuzzMbFzWp4RZqbKocI7bHYQ8iksfy1rYhm+DZ7TnrbN18J30pgEvUN7LpAq
96TKIHn28TDvr1Jd53sLt9elJXlQjuMM0LcGV7geRvQ8Ak6InJr3jp4KwQO4SLp1FTgMMMyF+lji
g3sRVGHpemQzZraA5Yp96L2C2Ph3gqA3/cGvSAzYTNSsIwKCroYjzPVfTYldDZ0gUct6WhBlFTVW
Jc4xi6gGnZhISiKJoZzOnFAXVOC/MwynVrbB+TR5un38Nn669M+AAmHNTA3bUe1Bcuv19El/nQMk
PGiQboDfeiU35aX+Z23GpFFyEPf/maH03owC1epRTwZ7FO2Rk3f1NRZ4XsyzyEmqMiUiqUWaGR+b
ISO3+tnD9bDZrisD1ueD/wENij9WeZp6j9x/uT3dSnSC2Do5ng5A1N5ctIQIDhK3zgwFkUGTds/2
dUFmibRGcuJq4BNMLphH/Ix75X5cqEINmINEq0tGJT++c+KR1A+tPC9qsBzy+EjuhW0S9B9/rLzJ
GDa0lCPG6amGNEwACcPVWsIA0r0BguipJJnZv6H9lQjDBori3b62YBA0OCON136A3q1cnvFrW67a
Kuz9f5dGXbE42pULq/JaW/ZvG4MIBzSUnqYpZ0hTYocEcZ1NrITj1/Hnzc42jHQW+teYr6EC/aRp
/E1scBx7ANZ6XD5BhuNh4L8pWMkzJtNb0PnZ2bvVEVrsfmm4yzAV5Isp2N1CNXTkOlDbYE02bAhA
voNgv/f8ZcxZp68D3I6egWzS6p8fr6/VgX614ZnvpfB3TymUrMuV91E6YwwxwHP5AgLmFlhhwcu8
dCAfmdj8J5wThM58DsHXIM8WqX1qKhYcKJdU+W4awhcFzIiEjC7AajyEhshQ2q20cppnulvDZs8e
k/7rCltNsZrJnq4sEVOoceKBZfjXInU6o/G0w3JDA0g71w4OoLQmn8xnI8EooCBEFU0j13uvuYWN
ZC9oq9bqntDMxl6uLZPSZna2P6+VWtQI7Gol+kK8hzNg15FB4bbHNIkQvnARdM1eQ/pQhPxn60iw
WEGVFFaHtIoKZxZWJkR79Tj2ENJqEnQGYn+u0NtQQw1IfkybezCVKK6rFp15kV15qyoncBGXGFMD
IoPreaghDssqy04Y2nlfZ6PMQ65KGSTy/2C2KZnTClz4q+JvCs8ECwM5q7hTvMuowwl5MAozWfLa
fXhQULRazHFPzYbmqzmmzUIHJrKwdQ4vi06MjsP0p3O/HwvCd07Vds5f5pR0GtcnutdDk04I4VUI
2vTMYUUL7RQpD92jgSpWWFgayx2sS2ezv4vKzAi3E0LPEH/2cpicygj5SbUbSUNvp8doDdjq5dPp
A8o0Ei3IJV9hxMZeJ5m41od7RvafZlvMNNoSvc9KJl2ZM60nzIpLQW3ZE9eEJrNz/YkPKc2FxPta
1nTiGKi/ayI/0qwVXdMJj/85QfeObPUGp+JEi5RPHoF6J0oc2AjJ6mr4utvwh8lUGTyN+6Efcu9r
87eozyI1cUfujLrY+cezoW9jvcFq5Ctm9koF2nkkPn+9boNsfxt+Eie78GSMifV2GjCqfog/yGWY
vw70mCyRjsGvPasummycSPvnu+ph+xKEDYiNCRBNzs8SWFHbfE7Ts7O1h1RWPEfWwaIA0eMnWc4V
xaeN5ujfYDr9dmpiRMJJa3GQNqpZT81YDLQ2VWwdGyTN1cndz3llvT/NxZBHIwFrnazjHbSfXdkn
4D5T17Gge19vTQcSHwtfFNVxwa60JzegX8mAxTP0ls2U6zrElRZn23Z76O6t55zbw35OnMFYCzfY
Yk3LOXlGmCxpSFeyj+Edit/t+e5ZW+/eHNl2JkZ+DDixP/zP+XnS4MhQk2SZiNjLtfriEiN+bHg6
ZSWuTuKvWsh6Eo/nWbudHdtHwzWaZV+3OFJmNvvWxgy7RYYPvQBakte1/sw0yek+VUulGrLX+QI9
VBbrBllK/iOa4jHPswmnBQrXZV965FppIZlNPkpnJAS2qasAeQ6ypVHTnEBfkGyp6zVKDQGLRAJT
7g4zCEbzc88Jq7A4O0PzlJG0ouSGCwuZjXd2FyPjacROlKT2pu4rl0/N/xJaEJHHYWTNMLgCmHxT
9oYXO0d1c7jrZJninHX6CqeGto0xxS+9QiUoPfltY4d2V6NKZcPzC+1lV0DzC9Z14+Xh63KNU5N0
AJmdxli+Iu8RB0SW7fpX4JVVW+bJU82Xx/ZzPatJZRPQuDJQGwXn+48wKGiRhRPO1UhDX8Bmo6NH
AgEaaFUBm2F5yDJx+quBvZ/wkks90qi0AdVo1QZYJou/U/gYodErmcw+5cX78NAotPfdc1dr6LbI
uRruMWrFohiLCTDKkanmcLhU9vGNVuW/mTSbg+I/TDTv1xCujxbZk0vndecut7iwGiiwhlyQFij4
h2nQ1XQb69jF5Rwh2PcvSlja1tgN6dXcGlLHO9sgPbVUl+lhOThsOJx/+cOsvLwLL9QIaX1T1WtW
9KiAMWvohFZ/w3qlU3/dsc6Eu34FTGtF8645W6Vf/Mruk+d47/yoESeish0vEXROBsZruXgfaWRO
gOoZuA215I0ARf08dhTppfBCqh12nndKmP0svyD+/jvI3WkPs4fP2x+J9tlIwBGezxX5lh7BdY+0
iS0a4txqSa4BexUunvdom7aun9eEEthx5aw3QQW5Uu9cIGmaawlASgaLHc1lXOh1KuzoTG1jt/VX
lO11BB4VT+Rvqx+6aBhwd6i3QbqC7hXus4RTWJdVUCo1dRI0JXlfV+Rh9eYQFWCR113IEcddL9L1
dhBC+YkV+/TmvrTAQ9iVBvXBdR8/nRKEWuwFwX1cQZvNvLT9u8xfWmgsDQ8hgvZXLeB1mdSyt+wy
LXvEMXIYNFJXK4MZerhzzKpdA01vYbwIVVSjA6TIT/AU29fxlX32DyYMmHxhXB7gPz35UHNtCQxb
M1cA/31hDl9tu7W7ZIvdaAk5/zHxuRCrOYL3zOEewCHiiPqYe+1WJzfWAq0e5mCAOe+LtZ+0ePNM
p/znum3grENktS28MS6JLPSvV8j5AZiMKVEEAyqpconQW1kmTU52XfC8xP+ixR6TeAVaWFN6L/6l
08LL0+vYt3QZGlE32Vd1ghtFJoFXJwBUTClslzU5wmajJH5AO+NEDF8YCUk3IX55wppWrGrH3B22
jUFyUn8sqskT2FbtIrvifDTPvHkhuZCq22LtL6kKKUCmaCRMJ1J4JY1/nVpxIIK9Jo1oNpIzReVk
bhlY2iUUt7V9sRHGK8wEb7oxZlDVrIfpjewML07OYqSM/lZiBv8QLjmXth2BJSTdrnLe9A/3zFV2
B6wXnr1Tntow3vzLbZ1TkU4BHiHi/7PWr+YglsLR6ZgEhqLhVTo4bNBPaXID8tR3Gugai0c51PWW
Eznr93t3sOuEJvnZ8EAVvoCeJPGJ7+opjcd3Gy95JQmFeIs0CIxLnZFtSYvyYWOut4puMRW/yjQS
N0Aq1SZjPShJXQFP4sl1G41AwB2S8HMsC1NmQjRBZNnc49Kpc4yV4QUGtv/YQL5jqZQ2HfygiRha
p7YNEyn5kBOnsLEJaWea/JgrUjrVCKu7iQfsRcFB4R2r/MGzcWR/2ThoCB1f5K0TnxejgELvqiPC
IdqEsVTQOmVKgkQihPrzCObXV3MM9nqfXSLPMp3+WjhmQl9pWZBYNsSzASxkcpZU14qeBWzJlFRI
v3sTDyh5QcL/IxU4/CoKqryTyaeNHu5Nm50R9K/y+BhkV4LFWcaXfJcWBQ/62+81Jj8F0L+T5l+5
UazsMOd2MB47qGLXf4nGUFgRKQIW0n37IK5TzLJgwCEXgbVAAq6tLDVHvo5xGoeZjSZaSDInNj6T
9eAdy+I+wliZUj5FblWmIKTEqLDn7PQxHbST1b2+ZBDOLECim43QjQJ3ygm9GssxmhqEkjTJG8gM
iN4fgoS+IgGoxSxolrI/tip96mKch93BsAgbXHnV7kb1T6bYrw6n5WuikCYMXvFvArkjzscRiItH
av4Z/JlklXTHU95R6XYdTTck0wmyKieSF42sejOpPQm54nI9Gji8U6rsIJghFwbt99ByfH0zVliw
p2QZT7Sjg5WVzMo0GWt1sU/ijEUbLYe8tjpxoKybEtAZwhOeMgSfROk1cUbVcYRnb8FB5MpVrZT0
308FUj6wrOA3cJ9lvMqBgcWNmP0GTUmD/9fqGrzHFreJE3raJmx85mjbkV70TjgFEtfkfuLR1Lgs
RmUnYwYHTwsqto9AdTv6gc0frFKMDh6p5M9s6qvoZl/5Yr4246O3MWarJHn25Gy+AXrlDEGhCgOR
tV5KoJeR4hI19O1ii5H6Xpjda/7rd9p81m+tL1s14ALmkmHuMFqnVqJdSU29Lhk//fETTZwPBYTP
oQZULispBbjhWDCwzF0q3qfWLETyukayGxSuoZtvocF5uaYOMRislzMI5nopxWi+NnSeeC1SZu78
b607t6yNNJ6puC7aYdPGUCjEu06o3Znu29AJNieijLJsORJwpeJav9BZ/rl9A2gbjIMuTphTBdPD
rga9jK7J2rTr3C4iFbE/MaXYBH4TYVRsLDh++CTtJbQT9tSB5nGsdwpBbI2LEdI4fiepZnGJ9nC9
dA8zHbxevSIFtvStVmYdSOjBiGGg+xlQSc96bolMfctITnJ6XlqgKuEDwH6dulZgI3mBMx1MhymQ
JIYGVZoGVLB3cbVAC2qiOvrxatRAz6tPDaAksVS32oPBt7LhSWpWfcISSFhZGKfkGrnL28gOZC4b
G6SI6k5j+z6F+yUL4yTmzoaEXolb8wX8LBX8KnuGE/t7RgLYJM9q6F9GvWu+7FkbmGpEFVWWhJjY
bwGIu62BqQi1QXlDs9yf7r2jT1wOMbLrd81FnR8JgyPrXoSEv2X6vgqnEfMR3bwQTLr+K+pPsf7x
SiLeBQvDsUEE/KQuhjxucB7fVNkeo3m2YFzyX3qCoccw0VdJ87I6ch3EQ4GxB0bQolsj9VlJTcnj
ocaGSfE1EgzDi3WKplYb1A+OYNCzmyuv56Fowe+9G8dPvn1wB5YMsT1Wv96QtZci8IfffOaZSMBQ
IHcffADIDxdOQH0TvhRlf1XCDR0a2wXo+wvpiBiadoSBAS/Sg3k+8CWd8VJHsQJaEkTQybguFJg9
6yQQ8ZUpShcTwWbshl6FauBsFtD/njgIirBj6OMpJiTgqBV7uSY1VAz/e7Zu3gtQ5Q49lOyjxjgI
X2O+w39ZJWD6+2RcymuY4FynwrgyIBL+3mRqAPtgVgt2oAcgHZ569IrhMT3/dp4F5RlyT2gpJDrz
qFPqZ25GnXBQX8bfon4e1C1x/TbP9KN1VJiMPq3wKMp7nalg9GRmuvYmgkgiC+j4+62/xYflBnSU
8OzYbkLTjaVkuzY/Kx22da20Pfvy3qYlYbNANaWrJlci8l5CcrZd3pnisrKppH9ntYFH4bvIPDQp
KFnEd3iBBeIdjMeCQy7SP/SkPNFZTFO+gecMnVCUW6xeLd2B9X8CB2JlmN2JGUeutHa9I6f7KDzl
fJ1Dly272bTPiw4gvoYnmX4hGF5WvFJ4p4e76p4osp1plMmszCSFPwcimxtOwPqEXXf8h4zW7sKs
jrV0HLPj7a7DyJqpSG4Ae7yM/dRHj7VuMdGGKwW/g3pLNkRK3R0UG8NBzbfelNVNobTO0jmx5cNn
CGGfO8+h3SMejA+wnnUoRHFvaZ15YX/CGREaynYmYzxujv8Zqkf057W4Y6pvFc2pAwDvpGdcr9u5
bnlZOx7da02RyXRrCKPJi0TsoaT8gYdP3QJ29UIGLEMKjnpmBD9Q9ScerfJiH/wc73+0eVbSnaMI
6wS7ZmrK6I7JTR4RpxWBrlK4t0u6vCyrZwr0Y9wzOVSW1ug6/WsXOQ23H6aR+ZtprZBqcSgyNJwb
KrXDZ7rgaYgoEnLFOPmOSuFjs6ISGv6xIn5HzszCmmBMMuS98Cs5eIlSG+DaJrVLTjxAI7ePATXW
YvUeMEcfdb13Arrsku0MQqvIa6oOM+zC2+0IlH2k9w7LZqfGcun8OS3NV7r6zXSK7uNKMZSv7Po8
LwFUmj5bfAS1b8TBx9/2VCq3qMy2vQREGd5H3O6qco72Aa7jllZTmHwjGTBoScoSvSvtn1l2sg0L
B0ntZiZiHdrzRW41rf9eDBcLbZgSEckAwaXm9UgwAwjrlT3rfMLb2k0+QDWR6HMVHP1H9rwUdWcm
zE84Rk9Kh40PpJqxiCQuT3BEmOx9sCq0qCjfloAVc2N+IrSIQ9IVH8Vff8rqXZH9lgD5LAWffXhF
BaAmlDscmHxXY/1cMW8Pf6o6PfHHJ4vnb0Bf/slHMYM9HQ5XFaorUduX87WaArB7cQ81SbDPbna6
GSVsSwp3QRVAbIUno4ab+tcir8hvFxZVpqLqlQQh9f4SNawRV+LIU10lgrzCEfFRGiH8aBKJP6Wk
Ze7WGgePWUgbi8bpoQFk520u7UDODYk35dLlJGHBLmUwSZsXpqwhIAEHJlUrTzKy/d7exrTso5EM
6IPLJR2KQI9epySxTak9ufa9CFJsF09hkGo0hmqqfyD8LAIwcUaz7jOdVECKyi8S4Vrxv0cUXnhg
VIt7d0D9InLOuEHqa9cz+deyNSV9/2xIq9PJqK3mNZMRtKOE7KDQzveaUAZjcxqAocPqPv9dVi8o
h8sqKc34lFAPSTKca0SbcqEn6QBjVMwPNbD2ZfU0QVVbUZVjClV0g88JFonqbJoohyEWrnbAzb0X
5Ifxo78ReXgeeExndPGg6rpRg375I9tTsHQRmr2NarDpEmW0f9vRr6svNyLD6xV3dodf4VcuzqTO
N0hNuMQeHC2aTWBN+8bCQj3l7U3gSsG5147R1Kj/f+Q2qJk/yMzFpIC1V9BnfDNoIISJE2jTHhmV
aGJ8yejwXEbwKv2sExpMtcyy4+52XAuXXpRNUR/HKYcIoEXHdWaEpsgXHgowdDc5AGZwztzrbS1u
TQCxF9v5ZePv7VfqIKoe7KTafV5x2s4XspiyjySN9uyhMet32OdfaPsDFuuEeXJsZWJD6l8W+wOj
KbR+EoslCd1qDabUSTRW+M3RZpMhvW1b/DgCLl+QyGK07b5eN7RHnpLHZ0sPEP6y4IurAxvA6rlj
d5Mlr9JtDH8dhkBED5f4QUl3RjMM8VXyqL85FKPwUDGYYZKvGj30b/a5WdQTL4ZxOosnKlmYfqUi
5wO8dZtvfutZ7+auXMISiJxXI0JJNfaDQAR7JHkZg0MYdge1cQJTBvMJOrY+yCjo2xq+sJs9be5Y
Er9Ed1QuOapb7M7bm2A6Z5dfMEpUvY/Gruw8CpzCSQPvVKvFkkWYlMrreKSFeXxuF+WQufpXIShd
9nrFf4er+V6+wVtvubmYaZMfRyuYE2GN89jBgHw7rlomnx0KH9+V29o/trrKXpYZoIK5gCZ27qWh
scBCSj8awaIytj5lE9Rybsed33J11DgYQUGNewA/rJuG2wABkRLk033t5C9Ztncb4+ueSUmOVaX0
L404k9DyoVyO1VwCKizoqNUBg+UYtcYAtPB8OrvqQ9PqyaP1ucjOrL3f13HGqR6EaQP7gURFGwOu
64dwN97FoPAjlLSREtDtxnXeJ159b69HhmIPm7RZ7AV5Hk+p0uJ1WHd7xm+N8HnG4xPN2P+fskMS
i42cZBjN767GE6gXT9J+Tg9AIJ/4k/xWllAL8Po8qNpbHsAHU82nDQlAheJZ38jes2efIM/SyC7A
X5AOpva/hMGXt2LpL5ndMFZFR5UG0T80LiDhTHG0vWL5RZ9zvkzBVlJR53w3T8LIeg8jl4si4ru6
uU2omvMyN7400ntabanJXofH9FF90QKjrT9RVtJ2xUqfoTq+bhytNy5XMFMhKY5g5tUC1zLZ9l46
c/Ddp8a37fXZP85jdNKDsUvsm05+3cUR+T7XenOAK9aTS5KUpO3qCjB2ij4cu44O/vgfOzL0Ze7e
YGXVWTXdc+4YPs7aVZCcpGky9SsfKQMEQa7/IZMkGEm8VabCM8s4qhxwa/T+vi+hY8R3IWtSQjxn
70U7ztX/YsfFeKCY7zzosE6C0BFA4uCKOM2N6Yy7NhG+up+fgoo2Q1md1232uqpKGQzSyx7N5Ijx
xnH9ggUcvVygTt5gp2MQx+07/yRWEKl5AD7NrkUTl/at/C7Oxa3zdfGqPHZEnDPmv1pCDXccATUh
kqpM7sOpwJK3HY3sodQJ6sKHqNnC6yq7obYeIbv48+TddmAaOeA7lDyjCCm0T0pkB31L9DGEZfHc
GOiwFXezF5xQNrAnKa0NW7CxnuH3aVejcrtC74ihCDLzGM4yL+X9a06WM9KMv9jhruJm5UZieKd6
HDFEHOTJIBA6kBDPeWkgunWhy5/ixbC2+ldFn/0PMU31BKP4bNpqRwIYTjxQh3Lup7Ryd3Cx0dM2
3XMzT4ZX+q2a17BNiIPIHj9L2dl2krXaBfgUbsy8+kTeswxhR4VdxwATw6SrSysM3XtUrRKZnVbQ
lFChdywEnKZ0PQx0BiliMuHfqTtSkDxIVabSIjsqVoREcaBo6U8GhLGagCor43SISaeIarPYi1nD
Q4frXTUsjq9u9BLhvFj3fGP8SSwl56y2v57T25LYHPlx1ieen4cuEyvMWLLrUGDb62AIcAYVVNsH
PiSblTclwpscfwtJ1HRl9mYbfgvHvtrTeF/9lgMukWf15aWPI9wZ97a6c103hB6EJ1jpp2sBn7AR
bABgkC6uuI1nCXcz+J6F/fftkm7OQrnCmp9ekOwCBbN8Kab01UlEWa8tzDNMwqAKfDp0emPTbHEF
3krW6JWYBQJkvdS8LNn5Z9JLfMxRuj9hw/OQ8LNFPGSYj5e2UxlLdMBIN0pSb2NZrjLYr9QnfR9N
mr885vgMgmadk+xMFSXhyzCewYWZo23E3A4DQjM/pLHIfmuycieBFYBjNY9IP6V/udy2Qepj1tvI
yDWWn3B4IDfjfjH4WNVCRPfhYPpC45JnMbiJY01V5x5R0R7s4VhsGI7jtRnE8qW6rXmbo21FGEP/
tZDNI0gWg9e0vWIEAjzmiMdZJi/pfAqBhi+e2LheTDbNmMO8bz/5YQTBhPAGxPw3jVCWBFb+CfFG
1qs3GuZBHhtRy9ZY3q2ExjluSINmmlGeLQ71DRDNyntOV0UcadhDRMUNUmxj3WcXVCjmBbcMi+jF
NAUk6pLDFKSQkB+fQ2bFv7MUfAKQ0bpnIa7aP5Aw0k6usm6HnIl6JLxkdR+klOCUvAIfd8Msx54X
ncszsTe0blVTiis4Rj6+6B04qZw37eXDGacgv4gfzC5uWk6yDVXckC4kfIswZjzbCvjqsdOZFHMV
UQOcnPDZz+uGz2AkANwHByl4PrPtXKEoHLAG3YR1F9Nh7wKjiTdkbelou5k+WXQWIdMq9PeOSEGt
vVy5j74f3jrACS3kIfoY+pu1zA01B33xuBJBAnVBaIJGM9PulcXdh75IyK1I6TUZMcWDkqNdbS3o
/ZgwJUYjNkEwgiNewQrCU60eZ+acUtqakz1W4QCWyZnpBymynJLhs5gv7Rk4DU4Gjs6iAQ/iehdC
0qtR75lB0ZppwhU50/6tVRWJwOyQra+1SalwWWTSqZ8TbdNSRVkx6oovV/w66JfFtAi+h+X7yHA2
DIONPi6W45wZ2bit5MCTJnClkPVjUIhFgQeG3VFY8tqax+u0z2WkQ2w5FgJOU1py+BsEX2o+uZW6
XfCATioiPXygdGCz89qLOHoDcQQzyz2xi263dmM0fvvJcLA4PMyGXDrSpkfoSDKLjryNMVQBRQ+P
DWYxmX6pb8wP6hjMY1l0MidyWMhE5Kn+iEgA1DmB5GUmwrVcP0DDO3LiPRycOU1Rc/egT6LykOPP
5lAq3aGq4SUjA+bBDFkAQRSHWlQRKlH6Pt21h9GXTurmj7zUnJpB8+jWOizGkSsoXMFhbGI1o5zO
cafhQK7a5GTMY+f+gEqoeWc5xew4QiINTLXMncTsvRwcGYDJ6ZWNRqahTBMroVbJ+tuHKrXTp4SV
e46KMdtfF2vl14k9Envq5PdAmRpkGevh1S7EmUOhK7b+JY/0lpEwvy7FPCQYqVhBinxddgGa8F4Q
jeiXfirAeSS/qPVVElyTV9Cq0hvtbkjRW1nLUaoXFc/oYjDeTvcHbtos8I0jswDrCZTjl1YzMJWc
BBpj5WzbBLrnntwozHy5v/2Kd8BiX5n4BSQ1M898WbScIHN09xQW0VzSkV0JphQhd+CFEAXVjnVX
tLtUGTqHJj9sNIsVdzJdrRpwFnvGOzvXLWUnObVHRSGJZojkS9onBj6GMaDqZYCeA83TJvMd8dUQ
M8mInMV3+6/vK+7mgl+he3QGRrH4ygoMMROtldD3onhOW7ztrkMcJ2E1afb/nCOk7uG0MkUNTdEr
PgiFlU5Yb1VPAVgnkjFB32lyo+6pPNt7OP5BFi1CVPnpc12kY9dUXvvfEwRrE9giMYD2DHJtjZOo
/KCFafHOKYLzzy7B8maEj468xp9rffbERXuiFQ2CeX8huQEdzqwA01KODLVjs863/wdjGxCay/+G
tw9/ch516jj7HVcj2AHc+W7IHmvgajyddieKTMo/z744nM+d4bYSdkdfkshJnBO1ZJRmiSd4D42U
3jqnKE98loy3h/ayeKKPTC/elB4sW1SqYxQWD/HCcD6SBwquuP99qp9D8FRHkgRQnimmIYlVKAOV
anpwN8NgIGh6vIpBMe/3HlXr03SmFD3UWtIalnqtZ33G4LSCjrr+6TqSZKQ0NY54nvJC6qgoms+V
XHdGtFyX1si3m8inmGfUFifX8AiY3mHbDA07yP+Cc6HzRvKSSWQAOpiYVqoWJEEA8rOwz7QqdFaV
PchmM0477Eilk/dYad5yR3TYC7sd3WaDANbdlmM3yY/8aQjpVwegDYxXT5RSi9IOITRPB7236Zp8
uf5N0ZctnEGUTCD/Vp1uNCbA2N8Y8xdnhmPForTwspIXs9Q31ZzO8OSRgGMWeOhmDSH+S1Qf0jiS
iGgVMBPCogkIcgi8h9WDXRlNU1CNblmmZMOD2qOhgrVqCdQ1RMy2l4lG1f0kAyWsjdjx60+a0QGI
gcWzy0iQ2KvQhmB/mdMWSQx/0DASjh5FtZzIVzjI4+nUoKnZtRa3YkKhBUwi29P7NaPU40xlZNkU
NUyCWkhUoOrp+4uixK2Mkt/xJ26y/Ta1+fsCbd+cp2004Eiai+fH6ezJjcg9w1YPKON8OQ//i5go
5ir+9jjPg0uUI4tBOfPukqrVmqALRiM9uRYPpeJ1+MeoD2pVvT9kSHXk4mp3SsEMaun7sV+4Wxb3
6OstVfzEbXcoDLkmvHIBPICjLmHaO+tY+0S5vuPKjDOGPPUqhWrRk4yoU0GYk9mEXOwcM22i5D2y
d4ClYHfCnbyQr3keu2S0ZU2Zh3HePb9+Jw33LDdNCzUaHaE/t6UTlCj2JGnAaBnL3YJbZj3Ji/eo
kIcecPAXuoRpNq+rpBjjOz15ZUgpmcWVVlMe3LqGzROaT1n+L21EKCuGCkukaVdNT0EjlcRGXRG1
tIP5miTxjQ4t6LWXyQ2QatytR9XF0+APcLyD0fOZuA3V5LYr0LBP9Euc6qAMDqVktTkKbep9OuLC
51ayyqnaePYQoKKscIP6DYtLqyLCw+yeMPd8NHhdkeWhrfnyKdvA1u9cMS9njwL66jMb/LUrfeze
QHB1lYeZKrvlrFt71tE9lU1cg8QDGiMYty6LNpsVRwfeM7TERmyzmGI8LPJtp8+f03xGjiEHdu5u
KlyVe/n49HsUVcDmGNaOWgxZEzOLvd+16pUWlTuXjXrRll75HENpXTsUbbrk7RkbjeOo6ZEm3MDK
rl3wB1mDBodQr4CRmlZIXALTwaBB8uWjBprxV/DoMBT3riybAGP30qujAPhZt+OI+7Md5ED5gA1Z
ZfUd92btKHoRPRSaSEad46gdSFAOzvINH/I1U/MMT0RdZXAza1YflFVTBxY3WnvgYE64OxQDJVLJ
KYOM6Ab/brHRAal2oY0hJ22seAUof/bkGF9RfArm8xD6SSkGW9YhxuvyH0lQp30zy+G/cBWFdLx9
bZOmdM2wf3NQDKpGtlZls0pXeOkRtVbPVj/H3u17NkrQaXFIgbiUYA1y5LMel/+awhxujKqJODjr
u1n8ITfsgXQOrLRZowSqLcPCSWgB70nTsWzCKRr8uc+z9/GTUKGYoXJOBZ0N6J7oO41y2z3mXTUk
/jquRcxBVEiczgeIkOtNErBradySZm7KaAZPjw/1BRsfkw/pRS4Sl/yT7O1De9/AW9k+nw9c1abl
NQkvMzX0AmUgC/UBCTx4f1zmxP4+ojhSyqxFWaOiuSQMCFdDwU1sWcnNJX/m22V2sgssfW5nW0nS
72LaVi9olPXkw+3Bc1OSRtrqDYzmZ2QBtVDmb4x9KjRosmkUWVJOvH/inW3Mff7Ywq5z3etNCXEK
k9URFmDJt691Oa4EFZUAeUeiZe9r70v9x6UBuQqY6uXAya98MCRrsbF1BH+Krpu3mk+OKaU7/qQN
NcxH2Ixnh2ovD0TN4hVCA/b2BI+4LPV9Wy6VLuXGpbq87uOPDHBET4qxNEy5sb076aD+Kp9YGGtt
RO18m36Sa/0CLi+KWCLDGctHNZvCp+GKk3WTDaRDg5aQ6UoT1HYWARW/9fhlza9skHfM/KUFqls+
r3uISkVoaelUAhMT+KSEnndwapwwEevDSXinIo6Cm7FUx/PV+s6177VjPw6XbCVwhGw/4R099YrN
npnWWZ2dwiE8mv0z4yvI0fjR1R9hlRYotVYLrZRou4AzGDj8CzBkhXOc9o6ebSd39cy+2shl8pn/
WjARoZA2nF3fh4SE9qAXMUy0HNDmzRdcOP6hYPQ4cPc9vwxZ25LSN662sGCOSffKdilQi60j2Jol
zJ62Ww25m3fTyFHnNjwWCvglo/nVOPF5U5voSyNu9iWZuBWSgeQZJ4JBBP1wfJmJF5HHRW0NoR4B
RZKxRqjJdfyUX+PuliJ3M64exSQThNF8ocTRQ6qyzC/oq18MSx3Pif8QftFxiIBrN5io67bwLRD7
C1c6pWANwNI4qyZY9yv+dIbQy9uLbfQhRysO7aKJqbIaPGkfZ+jlwdtnfBQHiaoTQ96qVjoQuHF7
G8H7vDIAGs8s+jx7LpoWpcgg63YUzBmYIDm38gNaccWs/DjwPZiQqtdW3EgnHv0lvsdR8eKGPlXJ
eW5xZARPiXTNB5ML3NKGbDZXduggzzzfaNzaWFuinaphY3mHbD/2XuyAMK8c3KfJVqjeEF+uZBqS
NyAYX4C3rMHnPtN3dVPwO6DTWPzVgeFpvKah7gJ7mjPwGVPsnTONK30sX9Ozt9in9HlMxFgl5fdD
M2kXmPPU3BRk2nkZejdhEQUZZyQ2zuzXGZ/5W+hq2Gn/wGBx+RJb/0SHVLdYSTzqwT2CR3RdZEdr
har+U0V7yWVHyXVzSIuo1s9O9+D/KzTEAkr+RWYcF5wLd6IutEmH2lcaIWLGrswJrm2ovfulpZLq
1SXmjYi7eTnl2fCXzkxsp4SFfObuGN+yn/1S+BBJM+7BAo53w7KgfVGcTODsJttcENtZNggiNqbd
HwSiy1HS2l4OhpKTGtutjEvkRDAnQEnVrqmvBGwFNQ3Y9Dy+ZkMwwLAfkhaFU69+oWnFbBvVWBsm
UEn9pVCq9Fhkv3UGp1DVu98kGIfB3YGbQNIlngsRpK2bydAKJzuuXanmR5fYLHYdPBqYEa0de4vw
WfXbxw0TuinHhCiuZ6QFXfYgn5JAg1fakskRG1doWm8/jVom6wq8nsJgcfk3C3JWh3R6nhZvH23N
eZZlkOGIEGBa5T6UjwrzoYmLvr3zS51xK1nNEnWoDJmU0zW0i2Jl2mlYDwX5HX4XjKRwPCZF327W
sHujrwEiU0Vy6mQsq5AjXGJ66HZtkcKw+dctn1ZTHwMWCqjvSUjp7bqmeBvs1OHVkfMBBafiynx5
opSAPVYJV6apCvpoYV9s9vUiJEjcj1gMqreJJRwlF+5jyRAlbsLFOD+aW3DgcQ0+G42sqbDfyV/q
ItycXim3xRiUhcCK19KMhoakeomuZs0pUysKnp4pbJ566K7V5vui/s4giAzMLOVOuAxgEYWB3KTK
EM72ZK0rhf4n8+3iLvCrC3s3XLWwsK7s3wZXo1fQaQRdml8xYqBFiXJJ3zLnqz6Q8WxO/Mvt5/GO
286vwouAmjdzgvaEIPltzgAT1nEHTAJl6/qqxInb0jjPSiSZ4Gcmby9x+CD6WSnbVs2lTeviSXOb
m6nPilTXewI4RDkRTwwY02PyTKhjra9nJBt4NXi92UBAZIckRZbgvfVMOAW1SBL25ip0G4YxXGN3
nOReDrFc9Tmy+rEeGGZtUz5pryFWfEnFq0AWSiIHfNtqSunQ99t0MVM/51Xxmlcz55mSosex8Ee+
55TXsUyNT0qk/aH1WeUDn6ZLpyvTKgZel31uas54oFuPx2BSJeJXMI8DBl51OG103M+4cx1z/h/u
EbmMh4ifMI6LzRmIV623tFOGTmzyVJ6VRWIelyb7LKe1Fx0WjVl4V+H/9+vzbZT6iGUq55UiiMjy
/hj6sXqfAGLqZyXxQ2NLIO6OvWjXU2W3HqBCPlwK9kBHQQ90969fOLjYniL7BsVDMhzyLdsL6qdx
WLgekHIzjYIeilSOU9t9QN4hc3eXTN5BHcES21S+rFVkJKaN3DX62zfG1Z6eUnpn9hVVloJ0WnLb
KPiI8gs4qbgiG/u8t1GWVzf4DSbxrJdCmjlUyQy+kz6CnviERzQ1VhMp3eWEfn7b/yUptnGzVixI
Us1k2Z1G+cwAJizbemqM0xPapyXIGkoP799bLbFXwNZTEVUo2xKXFtL0jR9kGTjoF8t36gyLZzDB
NEzdeHHVKAWblRSlGmYvNRIF2UFxnizTz63K0tqgSvY7Fxoq03JBopogWh7iQ8bYiinL3FUigf+v
vldMfnHbm0fTklFGSykwrk7z5tZnmdL2UPpXpgf6pAKINgeu6LQv5pKoTP4oyPKT0lXJX/LdfHho
XMSnC870jI8QtfccPqz4Q+pk1n6vYZk3wcNUlyV8BzLkaUckVbNoSwv0GhohoVHcRXBVrZaFyDv5
tO3y5JZPOksxr/XNd7AZ0Lua4yIC1E/PY3UDkuNKNwIpokFnWSyhX1KYpkMzzUHXD5mQAGTc2ZPL
/VWtir9pKLnXWEgilY5hWkHZmEP35RxaLyWxvTT9ZXMGbDGjspioiMEAcY1YAnh3HOvl1E91O1WL
J7rw5dnHBKlocqbrkAbB8TrwtMHQPLjBxy23ukdbZSyq4FycYPQwKepmnuAe/2LllNTwmrFoSP0V
qMkFZfbRIBnLuG/Nbmls6rpdyLHnDgXZfQfS8UBzQR2oLzPaYkADyHqOzMLCMaE+XwQ7f1RW4sfS
KEYYq7w5kptN/U5RKJSE7/Q6qi1CEfbXLwipIZQV/+SPR6b382ARrF6Cb5vmQlTNP1eo0P5b7/0+
GFE4oEbtD6O6Y0VFanhqZ+d2DlTzbWO1c68TlWotms6J+z4iqLIrA/I53bNRF2V2Owadw17P0150
sG3IcFPX2JvQ34Vr4Hv59wEh7jC9tfpmkbl7BOYntn4/9Z0KnaO07G0kpRRz0mGmT5FQSFL5Mo2y
zsLMfk5L/rIHe3X2fcpFTmPZSltJmtJnif2PRte1G5rqI1eKDtGVEGV+lsJWODbDpPHczRswdTAT
YkallfkDHbffobSTVoph+GwYwoB37Pbl3Np1eCSZl83mY/o+vNqpYPR8ScISCQebVYjGPtztqfMn
Xiv/MNusNy0joQ1mAznxqrWrPIXomY8RWYoJmMiKDMNLPLKC17BuSv0+W9iVcyfyPA1RiyFr6tIa
3RoJlaw7kIasVMaBpOsJjFK+u2xwiwutGrKD9EtS/FU3lV1o3oOeDySietUyIad/EomEyU0rurbB
4j+hzuyPZahjONG1SRTHvCotcWH5PHxRbrsnF57z1PXGjLihhz8Q4XQbHGeO7paR3HUPwEmVAc8n
eVWfNtIsCgjHJCkPw0Zv8BvWFtvOCJN2lfra9Gm7Iu7ORSYnvBN6eOI/kqi3uvTp/WW4OC0fnvOP
E8Hk9x0yTiYCimRTNlJ+5HD1FYNKFsT0HlhnqVqIuFv87vRRUXHgTB0AR0kfktE9C6WcNhb4cjC4
Uw2zjlIaLaSWqZXDjHXmZ30KGfm5NnGxjSNGXkUHEdaEUENnEUYm/tv0tB8QUSw5GQ9BbqZE9zVq
eeqhaeUxu6S4/bxBIh4u9yC15rB/cCEZ1arSlSv3mij3b7vyV3foZRgveNNw2hN5w/5eaz5VMo8N
ovicO/vbT0aD+z22oG/tcF7cGjDyau9YvJLaK3Ef4DvHiQ1nvla9e4vbI7koTHCDanPzkib2PixN
ST2mJxEZJkvIDDlNyr3csU5v5qcLCzJ/2A+x6IQPub7gdjPngm267Z80n7q0LSFl91t7HEO6lyTu
oqKhk6cvn3Jj3HVx2yRPB6smVC5Bj7o7PwMikumDLuBJLLYwvOdaiOEw2XZ/M/jGbpdLubZHxN6l
+bm3IDDtpz7bbXH2dmbOPI23NhTIfteDGXCR/P1mbaXEeBeUax5h6DGMz92puUPR8IYWlkPzd0A3
YAyxHAQFcn9vAZaIySfqo60IYVGW/KTd1Qc+Lg7VjV2AE+knECgxfs3ZgE4roPJ1cLxO0Ti/F7bO
XIuyJ5tq2tMF1coeP1r0JEjirw5tKg/5dZIcDXqHRoLFZd2BkTtCk9C2t1h9Lpr4LlbdalCrAyvI
u0TGEH9IubGoup8oWIgXP/pO5l3oNIhTz41RWPcM4aPHLYJ6Vnz7ZdsLQbrX0f1BN2ABp1hBo584
2pLF5O1mbaGo6mcBG2CH99q7a2PAYX+ILM/ly2vv8Mg697bGUPlz9gMuBDvHGPZzANPqFhshGU9R
9hRRZQl1k6oYaf9fF0+duM5hkBey3FckDZGUmj5nw/daNgXQnMx/Ij4mEhRUkBRRRVk0pC/LEQWV
8LYZhtOGBTfP3EM5tEjGTvO0q6KQgDA2Rl39/4P4ZABgqfxqsBCtV+AbXWKNPd9/5isXs6hSgFE8
HPA4zguOSO6e8CEFoB5Ts7IyKzgfOLZyj+DCkDsiSgYo4rq+OxVhoVocTNkOz4VSyu/4Ys+jfxBB
iZOiU4sbVv0XHz6WLqXnyFHTD/arGLLYfFdgy3kdQpOaQEg4FJj8xeYgANrVtrY4uZpa59LrNhSI
1ThHsvVZDTVhX5dW0ScIWhkCpWHJcDitjiGoz6fDBQFmdn8sl+SX49+Otq8DgfPFd2Q3Znkts6BD
QGRCj8MNhRWnBGTrUZtZ5ECNtwqDKb4kDLRToqCfNKUaSkBBbTP75V7+wHZMFPwKLKDgEHwjYPSC
S28+922txV6iQt5rTxAx6Dm4l8t87KeVbOccdXh0ca2j4UdYLL+M/HOU2QBri1Xw2j9TkZQtINzm
Aohl6UXRyrz6r4cmwUyRRhjVZqTsLq1oRGvL/ayFbedlqgCC3xDGBrAgnKV3EI4D7FoNWKTxFyOk
OApAS7IJ3EmLxYPHV0ohuwg3Zqv8EpW9/Em5zYWBNl4pAuUBvNRKVv77gyszd9LdJEduz5e4ZcD2
sA67ASt8jrt/F74u42EuV4RsWYHvoa31RUo8m0WAOns/VQsaumjvDpr0OnI9Hr5ii1EWmRfVMFsH
5/i5cm72pZpri0BZ8nZ45/0yLCyTAKMdBScdBaVjlMIYkA8BZq7wQODw/AEkAbVhjK48vpFvl+rB
K2J7/3aehXj5QQSWfmLCR/P/sqjBi1qrl3LD39Aie1odjNSdxNp2H1Q1j4cco/Ke5h/3ufBPN8gn
F9Z0aHbtOK1opci4K5jbD6IQn60M/HRfKvpwxNhCB/UrYlCzlK5Pknjn7JQlkWmsUnzuiAGpRSw6
LKUCAHlukiWxp8CX3vnDEUmFfGc+1OzLUJbTUkArI29dzgXvIIaCkA2w9l9IZezGda4bsJQ4+ZcU
4NvxOofDjeOZA++/BK4maPG/FFXtkx5HMP156ugRia8rRtSIBlRXEKlT7ZVkSBgwZNAClJ09ftQw
2efweL6CIF0X//iie9wyJS+nj0y4mD9FAn52NVKJ6Eh9vp0sUrDYVTYTd22uyi06MKR+/6Wh4GyX
pcWPgV9oN0/3F2A8j2H9GPa7jkWYA5UuXdv7WY7ZQNqPTcIR5wW4fqm2nfuxYQGLTL3OTL6VXeeN
va3I3ziWv409Hy4LQRnly/uOO5xoetsbmAxFzJwUIuqhYZ9ztQIas4VdtLBn9FrCC/cuHYP5VYMq
qabD1JEZ5XX2lRcC93mtI0tFsEr5m/cIWqfimKeXeAK3faA/isGZ5ZFYMkdmGgdQRWIbOzfDL886
AvOuayH8hy89rSNK8VuGDzsAlasGlmR4HU01AyDM1365/CYSEoRZnADrO0jKWoTDKJCtssoq4c8I
kDnoZKjlg/eZAeuO5jyeuMmSgjXhqIGARSmhk13lEQ9dwdt2cidgFjpJ8uFwEVWz8x9hhCmzPeRp
RbK2b2TtA0YKTOzbbj8fsxltlhzoC48UmuPbjy6pMDPkVFDzy27dJqn2RbmIMq2PiER4w28Tz5L+
VA6uYde1UtV6/TGda0lGZm5ojyJBBOzyQbJ0z5YmdfJXfR/0IePlSwqa3cOoFOXVBkj9xI7tkzMd
Pk+7HivwjwCCfFTku4NdXGGHwAHPeEOpKLXe8dAg3PBtP1cJKlBDQaGqVwy+fMbD43VYiHlbX8JG
wBkrmphiRO54VSxqRNr9EFCxUAp9+v7PzeTkfLU+yspGasMun4wDhdqFYJ3cQv1WKmLiGdcKH01t
OkfJ+ktJf0WbO8hwrg6ef7w0dTjsezfLHjm1a4pGbQzwzjjgShfkmcjCXmsA4w5FBHLf05Iss8zx
Z5aTLj5Qrf8si+h93kUY1z+hETjIQlDLV5YDMyMGYTAZIergl3Td7tuQoik8WdavPF8TowhWZhe9
x2ypW/Qs4iJKPDr0dPR64hbImIw6x+luNDddGLzaL87qSSabFCE1Eqnjo6fmJzyBBO+/TtKCrJSs
xncc2Z8e2mDtXXScGXO0ex1WuO51jBvDmX+FsUGYs8whdOyUS/K2yNrMSQO4Ziyyi1N4vd9sC65h
m0n10TdCPuAZY/latn+ZPLnumhRZqmD9VtLKWbzp5DmrUElF36STwnijC4LwftC2VsbMKJH9zZTE
ARo3jxzAqRcWIpO3m62DM/gGoux30LiGk7us7FWZyou4aPYL8fMvMrcD1EBRy6bLGYWsQ29VIc09
cXtPkrB+XbwyIgFkykcEivMExK4P6fsKCnr1IS2pSnwogkCVreamNlZW7tpWnEsZnzQslQJutu0/
Hjaha3HD99VBoddbtcWsYIBGasTJJJgOitC/xIE69DJ47BqeTlBIUY8hVpOCxhkqzYncBIhtuMpi
a7wUd66M8qNkFPEo+QE9X1QFz4sI5cnavLvtpKb1O3qZL+fkfz/X5pGCBexSg1FO72voc8/hnavO
FdCJ5PP1OlB+asdfN0jmKbtpaHQWwTkPouRXlKHFiujUCmPXT1U22sj0sqPPWl/ljK0Pm2uxkEPp
AIm0i8QhyReaQqJ7d8U3gj5sGLxSKl1RYlXalk/5tHgwkT2nifM9zaUqX5ha2f8N/jQ3y+lqSn5x
2KL9uMnAxaBtJ0iO+3IB0thMtinPP4PkgJ8LUGfbdonGys/OGQBGoKJtyP7F7QYTu7g58djNB5jU
qP0IlpcWgeVmVwg5GlVdO1aQmkkjL+DNoHwImHgcbIkxnJSGRLHk945EDvRceJc6hR5qoJtlXUUi
Dhrxnd1FSRyo3hJcEj9XsEhIy5m28yewyOtYyG2xJtqvfJOMOiqjLmqam2mpuTk7Ajh/i/H4BxEc
0ur1XwjosWo6yJMfniBHxwV1hgA+ccg2oEiL9xTOlNd9F644V6Q+rpB+EvcU8bEzHhWaFySUgNYo
nJbx6uMeRHcOVNWsWEMjMYHvpMW8OVXUStUK0TKunrFWX0wRyJdcKZJcLPYwc7dqNMW3/CeHZfQp
j9mZV3001xdcwLsQaqW+u/cSAT1clGe1zHIMmRUhGo0eYpBAEe05rWp2KPY5f3jsDWkbZRUgCunx
1tnkq1R7icAWvSFnlaFGrQw8nA+jBcZWBqE9SHHYZhicVurwrc3RMxAvVN/HltQrnpLvkmEdeKbV
+tKba3bLA57Ja6F2/uaoSlhLRIDqAAto9YpaR7qtkEaAUWGmFxIfdwNC9vqEubTa7tbNLSbtWFP3
0XUj7YwdfdBT1IkBer/2XqOoKMnJqJtkwOmSgN369sjIdS/aF0PhKXdVrT5t9UePWS9Z7TPask0O
nvxKW44a4dgSBQF/5tDWpccBqCGboDW+4qo/+Y1Qfr9IebvQDYc+ZA1o7cMzAi9UbN4NGbutRjm3
Lzuh4Dk4UnZhfQhqjsvA2tMXjpP6XQ+p4iSPLN9XWeIrcXzSHN5pjnAxMQbvUutAcqVaFX2tU14r
tm9gKbVe/joTF2QAPKUmQwsRB7O+mLX3hmi9l0DSl7jt1WUDBDWgCCYwD8D+qmayuHolgbwca7wQ
PMc6ggAyfXmUJCWgu+3be2VF9SZ1SOJCuqLWMqhn9vwbN7BJPpYbe5quZOsK41VCEw7ktLvzGgvA
4DdlzdnJZXV/Z1wUnshAJJBozFB6T2ID4ji2Mi7bMTzJSYClIPI3dYj08CNkbIOX7KGafYvEuK12
My4b7zIPlXGWWtDRrZI/mAvk6D4NSmEa8OGa0EKmWaBoP6vsUQocdLORECHODacRyks9YsDO0fJK
g+SJpt4x5FF9ZWiCvX9beAHXlztXNTJ6OzRJDl3hmFjsznfzLXik2C/7LsAZkxPQbCLnyIJ4myow
aaTS6W4EKx1LqHrNcJZe5qGf40r0logctrGGw9wUkdjtD/nUIVWJ7ytaSKu4fAenIwcZff+wpsU3
bH7M5Od0mLALukLhWLAdBv8CEfND5j7DXXdorMYFhLMYKgHeCOi0fNJ8n98TXkB/lBBwQPMHsnIu
Trqhj1a+OG0Ds+SLDHLsW+WWg2CGK5epsvNHBFH/1Kqmiw3xRMFVWFriJZosijRk7LcVHmMiPgmQ
qToyVqvgkFO488j1NRF5W/WxlBfXdqMkKbZYOo/15xkeGnkF3raMqEnDCzSg+ajPQUTDfBC9DhkM
RdJtE6ZBG/kXZEsWgKti0ZqeMgZwiNNTbys0eumZwOTJjBnrGmnTPAQ9xk05SPaCid/mwWkbE8+j
xpflcKpiPN+vHzG/XK3Dl0AaDoTUG7qUcntDVedLhqEtNGwuqYQM1eKnBLyVkYiEBwLPO1+ZY5X/
Tizia/6FVvnIk+3RUWdsvQ4DdLQjKCpuJYXT+I0ql0DxTCqepNgpC+yxmu5TBxLkvcIa8oyC3dLS
NYBEMtOeBUsNu2qrx8taIFydfd5JZ2v3nrfWBSD8xYNqkqAV1InDkEhr5Rja7wgrOEkuK4S2oSnG
TpZkLB6MHHpKQHo24PDUV+M0EriWP91RtwvIAR/TSE8CxbSF04ANItmOkMc52vWXOonfONF1ZUog
OWc37wbsp3IMsHg532wqWm5bMd5o3khjFRQabzmciafj4UFCnhBlfGTpdgDLqloctW9KMmjv2ud2
ME8ERdUKxNc6qfYcWt/o+Vj2YPVgeXRYZKG65k50QAYLJoEvd5Y2Y03jHOAjOGdFPtZcTifEAosF
MYRcVD2FGHd78BtEYmFar2s2bvw0ATY/xrAG6GaJdeG8kaq7OPsskHUebuMcJciFY7pXXOGQW/6A
bjJf7KlcYYG7Yx7cJWBAGuCgF1v0/WeYey5yR8XAKNQg6oG6fm8l3+hEbFXUC/cYsDtC5qNEeSK5
Y+orV3A5wse86A1l4RpmI8ueqZk9yaRFu9x1kAybyWhSA6l+mN8XtQvyfyuMmKEdy/O5+WSaLGlD
7FjfbBuKN3kR07SkwjBUazTiWC4KDZJhjHY/7itIqgb1SkI9ZAcHP9kf9S63IQ+dBKuNXQ1Op/Bf
ntstR7gbPhIXd9qJWvtWXElhLik/5um+yJKBAwPiqSTMxWTWY6jmY06LRImG1124y5GAT4wQqcMY
xfD4qaLMzImu2WYzZR8tIZSjHAhUW+KypUH7h8bzWVs/2juWqXgDV18NAOwD0VcO7AurHA7aIRnv
dtXu6tn1hHu0caQAAgZtpL7S3bY+DiuZR62hfvCLxMMDfCXJYj0j9aJvVE/za+BhveI94px6pO4R
n7BdKb3WwF+KSnIkPbkYyHH2OoVhZnvr+M2f2PWSB6MxkkrAy2ld5k5Molaoh+f33ST0CBtZCZdb
0V4vM6UwjyUdiez/IRBxk0MadOHX+EsBUyklPaG9DTLyi4hJzLCpl5zzV0DPzNH/WrWhumUD4KXT
G/vmWtb0talGPk4eESA0iAMjspbVwR/I/hVJzn5YRbpFyRZLUOck67LwJRvNipYYw065/q962hQK
Vy9rdsTTQYW2ERnrspVhS9biZclJvHbXvdvMFfzGIX8/N2RH245STDS2kXPFQRqhILVpbVKkrE/M
nl5vh6fkbYGhRlYY4IEEr5WGKIcNo1umJ/mQSr6lHgyu6Ta/jwzM3djW/E0sbdhurriIG/omqGiF
fzPMJmHW19naN5ehKHNnBSvTBvn/ofYW4ddp9Wyu5TvnjCPFVOqCT6qF0oPtVzVasJTw+0MWaWCK
Rtm9ORY2hhVKGiZk8o3sz3n4DcxofXtn5BVEy89gODkDZ5A8jIIASOS3P/lF5tEdxc/92E0XnSXd
yAmJvuDZAQOnPualTMPkmEFWAdq6xFCt4+tNe6Jz2xWmzeaFl9q2WQX5s/xQ58Y9vkqwdDG8RTfO
ou8XGM81qIaKPbOFo2T2BD/chbHqadroeHXHvcDJeCd7uObIpBtLh0Srgf+F2B37XoSd0MzW8e9s
YXJ/GuLQiLGS84Kc+Nj4qbAFLgBjiWBuKm6IKnarKcSMGZHXG80fnidjR32Czo2C08rY0uVAQXci
mzQkmlZjJmasvS3II5NSnyfycdSpG8ZERjqnXtSEbpQWJIisqQdC0NMkyA3wj8fztfvWALaf0lBB
vr/PlsMEJ9WH7+5fblUQgiunSgi70xMS6sKO1gMzWNPIGjDoX3OxJ/Y5ByVzl32ZRJJy07rFYa4m
OyAbqFeXdE8m880IZUKD8GlHTCGIan9ZRpNvT0FsLZFcJ+la/ToFqJ7AlxbvCDVZQCM1XntIrSX7
xD4Ci7vLuKmXbm5I+Xn1hAOjMBstBlU59nTbIS2tqtM3cV3O29gt2szhvURTGmC0SgNI9FTksWt9
T5Y/861yYL33vTMGlUPiXkcK2Q2iA6zSiXPRc0qLUn1Rwd8zrpa4vkYfMCcCrXWQ5UKR7yuvg7Tc
OU1ch7FeVEChGZNEw+KLPlbtNBlcEUEECbX7kBjz19JnLieSqaqb/B+wJm0GYpBivPYWpG7zDh+m
ZyF56Bthaf/dbtk8dnGcU93Bze5zJTgFThK7DvOdrb7tpTx8lAilKJgSAqJNcHMEKrHS6S8SrK9X
IW1wGVbGa0MwctTAVMXj3awBb+V3iQqfViE7l7d7wA5Hcm5hn8q1uW2i42bm3NbU+BwQshRLInK6
s675oLXSwfA9ln38oljMGoAuLH38+aQzF5ekIigx7sgLXAbZBry8b5pdixa3ADDpyy2/HwGGtcjX
MsMmVCGLVx/lXBR21vG0ocpl/J01RercrO3nw5abd1M1CTDkuv0lWHyCR5LugUgl9EktGagNcD0Q
wlagfsanADV8rNlD4hnCWgreP155MRwLaSCHkDWsqTEAZraSRgTWyZ7tPa8eGbpOd7OrgBtyrfdx
tf3y3FoBrM5216MvDNU8IoS9MtorM+DJ1eUmZr6xJqyIFkMndGrC88QGHJvy7PlwY/ghBWfGKRJc
LOvi+MqjhexMQjEFm/nSXyIbXx1JrxpINLn05GXf53+wHKjOA3teX8HF9lz31O1zSjEgTcvzwuFC
FpfH2s7H26J8/vDC/+RNafupdrckansRiMCvlMgDx9PUP/GzWWx+rKH84d7Thhl2atDZGOBGdZIz
YQv2S0qCmloMSYgPtDVPXmeuPuSappV/VcIVVlNplaDp40Se8j9xhIkRTxFo35o2t7s5QUL0D4B0
yt8WzdQQ8JhK1VbKnheqYFGa9tOEdycTzf6jR5dvVNpK2FfXf0rLZ/6EQsyqA4P1j4zk84vekEV3
kFPHnvcK+pgxmMyENm0AEZMQbrySzfp4OMBefbrtqGYKKlHF3GPl1UzgfK0063c+Qc6evdcUNyUs
2Efyj8ML43LYudkr5UsYaeOtMyAKq3Z4FgacsprJbOti2mfSFMW+zR810gl0W5zq6Gz/vYQLczPn
SaVBz3e2XMMXAcxpDjGPMU3O3yGZJCR/jSdV2dOtUVIs8fwcNQ+ExLTX0rhidGh+7ODCtfNlvyUW
WPuaKKbpOyPileNa9fTfqWY2Kwkh691jiuDDtGJDAeegiQ2ay6P6OkRYyOx0et9DfQpgwD+GxRvR
XoQeRqaaYJ3I7RSQl/EzcZvJdF8TwFTVA51ANYVR7SKxDjtohIt4XYKqYsYl/e0iU0WpP0ah6JbE
m/QZ4f4o+npNyS2mZ1l9lEzr8hzIQ7Yw+//s4sCM8nNu1GjvcV+GFA3ETsv4lXxNKAjQO/rpGbx1
SCfwTitQiYwDDk530cfBqY7IqA9XnKVfCnI0aR+aft/izrRLJ28nFMpSGwB1r2JSSArCSQIdPk+B
mhJUrXcqf0e1kRMhMdJty2LXcvM8cvIHeNnPhMj4V+Db237TrhexUNJCzoQXyal+EhaT0BCJeN6r
d/VCyYyS/XllflPAvHCFU46zPKRX5M6FB7bJVbYRt1EFE5DIf88XElPoQPF1TLL/5Ba2B6VXDhUq
7+wwoWp0izebSdBVl2huoA8lOif2o57HFldLG175zLAOjF6xx/u/z6exTi0+DoVST/7iw+KLsui9
v1HtzPI6Gk1Xr1MyL5COpPJu6cXtJBUEgtSicgX2Ryj57vIx7jxlZOpg8RQTmBBBfO1swrc53zc8
SdrU1H2yLJn5co3RpIMsalVn/9WAShvbsmdGrgUp5b7/tPqvjflJV23Yz/iSAW4h4TNRosxbvciy
H8E9eQ7VKD88/6F/6DOgxuQ6eeM96fi1Nfp/sJdbBLxNZbWqu0nKcxkI0rSN1b7iHb1RZuELnB6B
viCZvN0mBJEyt6fiqxp1Wuio58wKrXx0vDYN7FmDGTFbAsWZml/qIeGVt4+h/HeCdMwjnDTfGcFO
UjxU7arGB8AjlQGm6hV1sXBQ+p14lbdo1AmuF+gYW+UTItCmOo8cJaoUgNzfqYVLSwv0C1oSvJuC
lFesENh1nGmU9aI6lYMhKxvMx8KsfCHMG6gi2d37J52NXrA5AW2BykFqpoEs2dZFcRUx5bKjT1Vl
DoRpRMc1vmT/QWlIl+/r47QxFkINxEu3Tw1tE8SUzqBdLyge/InFffbi8zpci3b4591tUyAuy4D9
bphjs5TU9+IkdKfBZE/IvIMbf+PFk2v4SiuZkt1T8UwNACUAQIhkGvHahfe28S8vrGMuC2npF9DW
Z2sptnOavY2pbQ46pAp1KwA4MkQ2Ugccxn+5EQE9Dg3vRW5JOYlnrKq0aoZrPeJjYk10E+vQTazE
4QgGyXXc0BFNMgjDgQuqY9YVvinIfpmFvSSw1qJ4KftrULxwJKpkxcfZdDU4vKpdwme40xNHKW5b
VYyHCbWrsfv+rZPEYJTe6LyWOKPx/UK6noag6YXw7tPZrLreZ8KbxjVq/VwreseKnFA93ZArBEnQ
DclQkIZ3/UnyPUbmD6JKSE08DLySW3Z4EXICyMUY2tuhyHaveBInb/MrIRQ/HB0Vsmjg34/gxUFm
A9W0sRjT7N1E0vLGVukECARDi+a9OwUu4reDCapevICOe9crlIf1yfNMcErTQAR+XNAFhH3LxTub
7kLKVGQKWpnL3fRUK6rxfOo8BPXkbdCX4dgf8EKvO6MBLD+im9ZleQlhbJ8bo6O//ujPb8oNYYW5
u7dqOz0OajbKYiP7orHbaxKxVgI6b9Cxup5KYoKe/uBhWMCX5h2KcVSAWLNW/rY8na7u/LERfcwT
pRNUxyV25GqfY18VvJI4w1Qx3OtOkEBTq05DI+P1W/DCB2Q/XhuTvGBNh/6UZBYblgzfYFvrIKXR
TNSIfuavQ5wxBZC5RKhvWhF+hbvwlLcxqSbaol/JbZwxu1AxjW3bsEuppUlS32jU7AELisy+OIXM
BzQfy2GCT9IoYjdeFj0TeBH4pjrZk0BatRiNoZbvb56Nn3qb1JGM0Rt9zYE5O1ICq0cqfaKybXAw
ZhfnupG7PN4qPDMnd2PxD1yZQQ3b94dSAVDsxV2aJUFLIoPUEceorzv2Ytc0q0sI0qBXWM6sz0eL
ZdwnKVN9tBKKYMhGjCPQcbgvvOqT+bL/dagRUf7TRfiMKQGRSbWUIbIWve48KPMgYvif2kb6MjjB
r/fxSW6W0KIIdq6T18amgaaakcaWjnY48q65Hk4+75GQHwrKLVjsQzH7D0VFwZOFwVtshqKfrDtf
s/1Fwug+AbnUTepQ5Y+xj+bc2TvvTgqlq5Dk/i4dBekG5BqrOpiIELuf5Gzoaj62yaS1YFePJedz
rLw7RgdfDnCgTfgyWMOpVmD20huSrv9UAA+gjD9RZatCJPj1H3S4IQuJlgltVwZkD9G+uyrUxjMX
LDitUtihhy1nbGiwg55I/BJH/Fxt6FsEJ6M8golFYFXfRD8JMYEWflWw7YeuiaSAVAaA1NAzpuzu
RJiMKYim6lbFfAYdEgD2CIZktJZ+nh9UDsnb2hDf539CkT5ecPT/cYPoLaK8vDWmnapQa6vOVqbL
nQf2EbdnjkVrSkWbard9antd0kPUAcSdTBVy9/9+q486UPNYYBHQWj1rIWR1rCzruqdLEaTkKBK8
8YdS7mtGxanvkiTQFjd8pVDtVSViPsch/I7PyNcTOuZVmaBX0FKip27jYDzBrcG19Iez0JxR9RZc
xGVLmkPMen2pue6TZ9Hscgu7cxWqsgBmplJ8xiQUe7TiFitZApXjl+1i1jViPhuAcSL4oNrNjbsE
B0Hwbh9sjOn7xcK4J0bSBjhQjvhy9wgbXvYZTLtgSFFe5BbrBclVjk67VCskIokvVCIFHK2xwlGu
M/e8KnowS6MEJ2zDu5PFQS4IAGO7A285jRQaRgC1ADbe1lbzfYH+gdC6I/ZUYKvTpkFC5t6DVtxU
qD+OQkjRHsXTKnfN64s3OYKIKs94iSp+ljKvUOus0RZuxHe3461Ct5QNzw8QSV6itQvegNeghvGI
fHvc3m0c69qrhgtcorInCXsrMhLnUv3FLkfSwk8sXS5D/YgpQ0pimmakbYnUZJqPc1Td0dbkxjqA
WKAPeR+FbzcofteedpMZdz+MzWaTi2bqGk9YA/VShSfc6034TZ/jfFTxJ43gv92pkNlx8XGZsdQg
BRAR/4iannBTyLJGR0hvU/VXggtSjK28S1pjrXiaH6VgkqpuOP8/iTUguU+sJfegitwrPJMJuyzE
hMmxacTSbffLrTxmuC3a2QxxXBVDWoFF3aEQGkMYAHo2KgfKymZstttzWCkih4fmxJjdGZGjofZG
YZTlSm6xBwk53OAdm9rImaDuxSCuccxKWbRTzESFUIxlP2md5hZVhAKYl0lRw93Z3Utp6gRx78fj
Pw2ONus9TjlDAzTJ+3vnJQfihcdg5u0xnHtcHD9Gso4l8q+uYYfnpKmjcWvgqE20oAHGlqr6T60l
y7T68G1PmMb0YyAFWa0r+GC7feP/lXGAgFPjRqfTE9p72gjhufOkrT+OSAq2zcpjHjo4a4nTZjCJ
8rmTTvGnuMeE9Y3fohl+Q2ewiqwgfLBl0yokQXSL9g3jXezMMWS56xGzCYtCDsdxhskpP5a17/X0
iF8LFMIYpz4dWyWgYc9m1rGYYXn4ZEe69jOLGCI0rpWuxjLXBsn+4uEvOgAw1TWKn4xeAumKkDRi
HLO//5cMsWf5h3kCP+ZwqZAS2k4gQWEPOn8w0fNTwIJK9XSmOf1IkKWBAwKbk6qyYT70jIHdKaHb
mb9vsj49aCOKgErGfbcWBSKL6pzKRUbinEmEb/ANEv68QdVUoSmI978YZW6jzJJe30/AQz98kaiA
r2cd/99NaJV2X/3sj/cAeq4HuxO+eaxKYLCQcj8BB+2/vU7FOanfI/R2uNcxu/DRjtplAFtAb/zG
0e3yU1Q8dNbmRE4tG9tHPbQLUV3gBxIaMp8uKF+NSp6JnFCVmf5kwuwvMOEgpvH8V/cHzeF5QvsL
v0I6xVwhOdfzEgU1BP7GeZlAvNzx4pZEpxtaukdifRRerhBKoriK9etVa6OTsub7EuY3+Rx6mZ0z
7AALDCGmb/HDBMaJ1Gp9U4GWiz/zYqTFzOv6BNQL/eSgMcPzdbmG0yXeVHY8CMxz5BqCkcfte4nl
jp2B2mtioAttC4PWLGA+cd6HUsoU52AVBIFAazXLXM8h09DQl4UYjGpSH3H3HSDPFEomZFXqq8c6
CKbEC7G+Q8jLHcX4WR6PPp+tQoHCq0dkH+9mKk74w2ozFuDqcRroq2fswORi4fH2+oasb5+8rW/K
f/yMGlbdyW865fx437zxQZIJE/49N1hvluL39AWAUA76G8sMxp6FQUv59/FprgAK6DRESTthn21m
Vr/wzejXaFxKDo/Qcm5xHATAIhWHvO3n1kRa6fUiO7D+oZSvjJZpj4bbYclOM1uV6RYFMH6Pl+WB
IGwq8vslzirxKeXvtU3wTAvUCGzhWkQnQh28RDQTslUGU7g9FTEPMUw8DAMRKu89ATTSAeeAL0or
SSoT4YY91yOCg/eIv7TiorkmZbPAXZigk19DuYhbMc5HwLXZT28JLvJz0wXEdZFgN56/OwFjrUOW
54JZ2gBU8hXWUqnQBJ2K/uXbpflhNznENdzPgjA/TI3VVFrtLeBOXKGZXk48HD5csnKdqUpUYl9Y
PzvlGwB5bTMdC+dGnGPrlrmxRhBVAA+k+KZkhd15xUJ44wxYmp0J8vGf/gVu6pRxmvQridKMbPaB
B2+bZgd3/oUexlASwaPMkDSUsaCL+lzNhbuluvj/gub9UDQE6xYLu4GQfdl7yE3iltA4ExBjjMqQ
35sYl/yIjnCSd58T/7pTRl8D72Olz3zCztK1n5xqJezoiyyo+3JuF5MGIdnvlYbFmJaD/ul2rfu7
JJYYNSg0KZlPeMYepLPrXFC1YXBXWe7mWiBOPGrIM7++xeLM45VERAXlkTd637xUmEuIm6qyU3py
Gpi6pQw6/zUrqHWnGC2nse3SpKLBRrDeZ/AMXovjG1HPOf3iKV+ZNVvWAGFTboisfjgMV3s/G35V
z+vZJyPH0s+MxU85btCVA68Qs58nIMr0FiQwEh+D1PpYi+ocCNIZQuig2taZCSzAu395GyRNmxWC
Btc1veIusNQR4NXcVfW2g7RvOtTjpItGl5iqnYo6NQxqwNWqVirDFrSvkQn+0MfEgkZFS1XqYldm
Ev1I4+Y8bTmuZtrGXKOU5rAyWbWBLjCpVLy+UITIV7o7pS9zN0HkltISygA5kfVY47GUuuSelpk7
hPcxrPPqXMYFxLNk9QJVnNuoiTR6ctMyYmJ8iSHnUxRUGYfcE4FhkXi//B23jko73H0m1UbBEOUf
q3rm84VNnwvctHLtnmmZ7F/w85dvpnrdcSlmEUNyvcluqgtgWwlNsVsSjeq0vnvp202A4oCjRr4I
z3MUli1mE+OwvrIE8GoE0SU9c8mYk4rTQKirNbuxNOWMu62PyL15vup9Kb+tHI1GY6Ot2WnOabhi
ybcznFk6JPa9k62E3KClcXwjimrlMLcRa5v7ai1p5UhGWe0pVxnrvCrD0GA0hrWLUpzxTs0uIqil
l4MtY4iLDQdPLDlKR6FP5H8Hb7A05X+xDPWrySpvxd6atUaFecFxLvBEXsZM8Obk7NOEjWH2a0xR
YgAODbEaaE4fPtqMxjXuIvmlOYhXsBwdTK+RHupnAkvOX9xMpaGXhF9v2jOYhP4k+xRP+tpdSwVk
aiM+yYJArcggXMyhfGjcplupM7JtG3lFFyhzhIJANm62GU/JEioTNvqQAghjB46TT4r4UQd31ayo
nbybmeUA51j5OypE72ffPqgTf/GsEe8rArIoV/qe9JmzWu4qhvXtDe46Il3Ppp266tmutrnK4yIT
3gPLLgnQR8A6T60lBwZwfTzksOD7akai6ibjV28gsHYdajPr6cDTLOCs0xN68OOxJgLm8ZrKrUN/
toSfIKQaWkcBNAftbkmLbe/3WmK9xAiWqbYnS7tjM0naN0PbhJeEveFIit6bg0Kme7gaMPR3mSwU
93gYZYLwdEdMG3bwkW5XMZz33t5Nn2LdQgSMi3I0+gco4YdjDlf06E1OAxkDjKnqZQ7KGdk9rPih
05ZCo1HPewzqa0zVGHxXO/Faa9of+6e2sUxvFVTBv9/yjqB7q6sm5xefJ3G+ZtRoRrEMPleEb2Mf
X9nyly2fHMhjAvHKf9oZbXV/LxKW23+i4kmlEwjz+oLy35ECOQYavmh/htMwlrE5AK4B0QTpe7FB
gwU7Ljc+doQZ40y0z4ORxqJN4wdU1kvV8GLfPwrXz0HYMBQjTIRh3T2iOI23Fch/yGiXg63vKa57
ytF1tUxXqhGW0/CYS9RnQOrDZwXeOiXsrSthvs4ib2z2E7ei3BEQerp4ZcF3rv+mNXtAo2GtXN5W
0LSENJCduln8qa5ewo5uHov/FIy/v3sK+b8pYoUxcjFI468w0nA7LN/AXpBHxis6glJIGC/cgVX7
wPbfIQfQZ5R2eKZd8CG8KozopX272pCEjz7cPSsPE7r21JpuEwr7ZRAZ4USIlam98XtNJHS6s5RK
skT4ElN+AuAjhvrwqsI6tPXVSn6Ai4Howvwgz0/Y3M4eBCMKAcxitk7jpsQwUCgXjqjd7dC/nRx9
KnuEBqFCrFCWxhqpim7aUllTJQetzW6zIl4U/L75HmIim6qA82SWzhoyveORpC7MfEJRIT17eFa+
sENKKiTbPAceDIJ0mUq77uuAjLBbA3PU57YTnYc0apGO/rv6MpK6qvttHt8QKI0CIu8jOO5yci7A
tewmYEspbgs4ejVRuizwynuf1i/a3FpwmdKMRfYRGeYePP0nz6hkqmZJsaURmexMbmdFM2wokAds
nU5UThiIU0xs836MPtbAISYRdA0QGt7Z1YRAxYIIsrYVyl2qhNB/vXmerKWzpz4oeSDQ62MaAwgb
92oUhgxBD4B6Z1OCrVKUbHOaDJKm8J8U7CVP2dhC5iot0ane7XOhjE43GnOz/jYB5yjyTqIWrFUO
2cEXVAtD9Ub5oTcmOIGd9Ge4eYfMOEkltWSWTwJ05NrfgpWsJQb+RXdQddw5zYVDMNLMxRKri8jW
oEJtKDaI19lLeaahnyGXEjeS219wUVjFexxtIfD7wVSWC9Qtv9s1eS4KS+b0xZX9fEXC3V37F8WU
9E3BplaARFKL22A5f9TxdUn4zPCvP8oug47tKfSNp8hYuwLkYCaOy9ue7IcQJvRV+q+FwrK5p7IW
nt6vxwAMfb7bESFa0Oh4Ex9fPcUU31uH8lD+tEZZfMuZw9jlzFOkrY2ei+0WAHrdfhEph+7OlX2I
DcBrb/feK1UFg4gnxtttyr1hlnZYTHM1/1xxOrxmeOSVf4yYaaIEgjgFZXToACRIQICauvo9Rp/l
CvTqeYWJ4rETEeCWPkRJX7g/IPDCdGzAV7+siwkc+7a5EthQa7kSmnO749CsH0/0BCHngaR/jIqT
UQuqYp0tYevEnUH4wchEHYAib5GLSBkQYO60Kk/b1Xlzq3U8TvIgDDB1+j9jxX4uMySp1VvbNKsB
8HmcJYwaGi+Nz8hy/9VSfic3ga3tWrhO3RQr/iM/Ce8nj28L30PMuUjOro/5H24lZoc8h6iT3Q7l
PWajbFHwKVEy1zNos0/mjv1uferUNVLzGbNAyFQmBMIKl194X8h8dV9YUY65zco9eb8nA2qD+HmO
3SEUX8QGRdzvN+g3VRFZXtrSr0u1/A93u0KbaQr49vE0fS6R9QODoAjrBXmIpvWbUx7ZUkM6lvOt
sKbn3JSFaeB28LKQEThv+FolNtAzJUe5KNWle2Gx79WfwXCqq5gCEcUpE9HfGqcu29gxDkezNtti
erF94FMLJs83BC2C/Y8G9sUSMNSlvGuoA22/WCHaJ9JfhJbyt50VfT2y0CvIJDdxys5P95sV+6tI
C+vvPGRf/90BbvFXGTTB2lAW9+UOsut+xSKhr0ySwme3ZI5lGmRnOGhOo7i54SOI/lVyjSBxWKCB
bAfwTGsG690infKjrhO7k5HNSr/X4d9rHiomuNT+LR7/BAFhlvw2NAQ2qp0KHesOzrCUL0SEMQJT
RNqL+FZnjsmkMYzaws4gexrofV3v27wD2kehyKosCx9xbS3HNT4BEj8QKIQ72MWIcqXKebwJ2pEv
EJFfHVReVebtlQzziyP8ZKQpnPxR4ZqbU7+e8uyhCXDTQheJFAkwKhZNFzKEvPXKhBJXR2Q0q60Y
1/AovbjP7Vgu8Oj/BqF+CotrlbUjgpscIGcUvmR4iGmKjsl+CTUC6c1kzrEwW0h9bXekgDtT+tZi
tjNDk7/uGkN+yKvokbzTwOuCSfe0HuIxpYIu2p1Ca3s0ZaafEK9eudCu9kaFasNyB98TNAkBYc4Q
Tiaj4yeNLe+HdhW8/B3xxi62d1yXtV2P37h3bhsIQXt/sTy7rBkxy04zrkqEhODrkTH1suytLk6A
/iJeNI0WQpy8v7e4xGIgbk7t+M6HmgLTOZebt4mcrd+hi0V/SAdd3xKoi1V9f+PEcUms2Dl3wwKu
immhlsBsTYH6p0eRaFQM5klzUgF4dEqU1Pf/9tsavyhRZC4b3aD9J1H1iUWZtQdA6mknu+eFSJ9O
0VDrKZQdIHpYzwA8MW+82WcAhG7uLLPHw0/DGzvPE+ufGwmf3wUoObHjjsIJo3uB1oLpeFQLFS0M
v+AzzXEGNFVWVvEM/O6ZR+9cRoHVcb9PEXbjQXp+4ISkVQgOkP+j9qjXf0hIR3d83K4NlnQleUUM
CupkmHQUEhXLu4FXADqBm1sWuhpQDAZTyHbMWoe3ds/dy+LdVlVGJGxiVKoxuA/lbIJsWqkr3wve
1ksIZVWq4v3YwlZS23Moi41G8IdVmbd2y41ycWQB6BF3DTQLnIaiiNwi8yFR6UCiwteqxs7gSytf
ctNgVIXsuk8fOIrz/H+bgr8i3WuAlf5FK/N8xhqRwT5VD7M56RMuqkxycVuWxn2hrQ9XQ0tA6lQd
kln+ydVIW7CorVABCXhvKu10P4uL45E/BQcWbvaoAsbBz4vr+T4Ld+9DCQbJzuPtS8ASbiKyX087
hdy+a/j3slHOo4uD0e8yBHmgd4bcG7+rOcPEumEroWjp3OG1TSgNyi4vS9XIlMfy+89OPW8fyC1U
CauGMgZv8aJNSp0NzvjV+jqV1D1/yqfbCDKCHLm6rJAouwmzpIJy/EXTrutqfR0g1QgnS0qBXAhw
WfKLIfKOMDpLHQkPR1Y3CMP1pMlGblTB5kmKRZSPgcSwdsEIVOf93jXDPt8CTPblI20NtdTRkdl8
/d+tVhz6pqeX0VLip5yhSsifwfsVV+RxJ/I3ksgq/h4aBsetdyRy1n44q+MG0AtwKBvo2Dscv/iH
XjuCktAjT5mFsyu7Wrzic16/w9aiLLkQIDoHw9wNj7ac3hRBuDxQ5u+8WgQuR8HjbHPMxMFmI2WC
wiGGpTEY9u9GgbpIQPUZz1guwy55tdegxr9WtxdJ1Ahj6r0AGQYyL8R0TJUEoB3/ylof8kZvsbEG
xXSlsdpDDt3BziUAgWrsxxu7dgA4O22tvOgwqx+ApKTVNwcvv7xYcnL2jBpDJnrcOqZ4KtadPEXG
HhkHpXMjnNbleIZ7GQDEEbwEhwAXJvqehC5untB8f0szEZvE+siNuB4a37El0VSEmckMl81qCMh/
I18iJSJJzZN6EvlQ0ZrlQxT3hX/zluGEq3ZMtwTwHlVaTCOtZwXyzGDmWvRfHKczUNjGDw2ZGSf1
xJA/FpZaxNXY28yMFEbSVVpWHl8yLYYBe5jE9YCbl2VRNvuNGUuAhKCGs6usZawkJBHsVCopZ5kx
cHrNrf/DxxQfY0BSuac/KqqIDRpmqknCsimczB+/KS8p79ZGjH66PhXFLUGN2XGtoo9+pQ5gP5OU
Vk6TLhk9xVdaGbECwY+EGI5fbyt2iFa6kBVCy/1HcctNgjQ3nGIi6GXgUQF4MOYD87eL2sp2Vzsj
84MEHil7iPi5CLJVW8klYhdFDcVo6OAavT4yDz8Ffka/pedc6bSZNRR3Lkhk/eJRVw588fT4Dr98
Ovx2lhqz0zBaamh9Tvf0dmw5bcg5R9PHyVc0CT9w1RMYa+kHBo6beH/BZjajNsrlKffhKMCrvCNT
7Or3YCZs9+ROA1piOcSKKH0tooO/te1SrJJ86bj32hZoJ6dWEBgP8gmeJc/4lBopJfWZRZup4qCE
r54kzXBVnBpkw8MCvwQD/FskyK/Hbc5X7Y7S9Ur3lx1Dp0pHkCyj0d8iyzNneEQQSBETBxDdqLhr
98zgtlQWp0OHtYxFylDcdPxuK72TJE+o4G7r7Sw2IN7GDE0o1hZd54HIJaUdOqzqWxXexWA4aWVm
8+VghiU6cUOyB4oZgesadK+No+A7zTBDiSFRm/HSJ5yyT+TT+b6aRF8lU8LXKarH2NecqPZWCQHj
mYc0cMe6jPRa4Chn6b8qqDyoPgmEobIG7Weq5ao2DGjcZcgs8FkIEEL6uYl9q7oozHJic0Thb0bq
9grA02QppbhbC2cxEHIQOno8d59/dbakRDBBls9FRXGWcLCatn+T6Rth1wrDkLnkmVGYbitd27Wd
DFY0c3ELD5I+axKy+FdmquqFa6SY4MU5Pt0ys+N2daW18wlktaoCodB7hW1YEZcmAt25xORAuoAB
duPoSmd+hyWqkJxV4/3p6E/bziLAJ+FOp4xeKqoCfJfr81iQOeok6D4PnyZBW379SKY0qgDKWjwy
/HmFzcaPuWiM5QGt9+SH07g7acLFwu5MqlTx/tZNZCzBHTdpqY0GfWBv+eDoB+1Mv/eNAAKdkPMn
FJSGW/p1Ps4uaSavur7Vz7EVmfGGNjTWhKR2+MiokuT1ciiXEuI47OhdroLg1ikb+Q4WG1xYMDKZ
7xE2Dw5xkaRRjJSbRfVtIvs9oT06CzlsaiPAbtrrucGRrI5oDyV5Czhg4FJ89dm50StybzcxPrJx
nPW81ZSfc2MAsOi7+qRfgIylBFDQvWAJDVhPP9moc856iohshnGAxijN5X5e4KDSrlPC2JgklM7E
pvZL6H57kiFcRC1HtoBjOL/jjgB3ZsuciByGjFqJJhWCpu456VxX/mxOgcIzh/kon/QCRqMD1sIf
wx/1Ut2b3bJ21WEWdA9Iou+v+apQqtAs+Ih/12eYhhZKhIir4yk/+CNxGUJjZ2tOM7wU2as7NXx6
D46H+P485KBGUsitb/Iyv4E5aksj8rk2UUR/6ie6HlYU15xidzlrnlIHo0Cxxck9RgJfpl6F4wac
GoVrkB8plMgfgISF78Xw/DFo9kURMEKi5eMmAzXdmVdYsJcUW+awA4aGPg3SR1jdRJCD4jAR0JtR
f/xQqjcK/dLlB3PWX7QrTe5dMMpHEHgIwpvFUANVwdHfeQljVvqsTEy5KQ7K2/5GojHnlxHbUV4y
/6uGuF38err+h/RfKg1lG0A81Oy+O1kHm4/qClhxuKXQAzOw5T0ht7Z6X9cUUQQ0fHTA0NGIXuh8
jaFLc6C+D3O33X3qbF+BGQq5je2ISkwjYXJ/741LqG0peIkOGsjGIVTcErxgKKl40UUn9lNx8Prc
DzgHhRie1GCK+2lakWr3GrJzTAjlnmvIcbLwrnnj89rWwBwRv4mXvmfTmkvhGm73nbQhrDKhkoIf
rWzJuHbG2azIuXxJlfsw6nE8Zl9PFaBBl8vRQf2cEo6z9XJIuCdQXs5Pe4SM2eegdY9+Vt8BHye8
qEHnxiPIA0m4lYc/dg4p8XTnHkTiivZacM/Y50PsFIvMENUDvFpRiJWEwy1GKvWCEGl7f/vW959o
FRORZwurmeaeuaNuS/PU4aOTlYYfGWVqhd0K+9ILlzqQEOHiEZa97i1SlqGwK4aik34uy2pxvftX
WLNJuLngbcMzk2sXTUi9rcswpUPMoTLcF0lDxJqkAo6NGT38RAI4PONHy6WfocbnsKb+E7ezINvv
c1vLscRs4azji8CbTO/I3Iged6AeA4yotGqkK0iEhE8xYcYx6c5nlkHOZv16/PeUWloTt6hUPaB1
rSh2pnHPcp8x4cXY+0sfrl8jw63s1s8k+buXiMJ99WpNvLlK1j3fO0bm+C58GxH1NdeGbpN1MRBy
FzoYAxVO2xuDW316D9yADOPbA3A4FjQI0LnYw6W8/zXDAVq9gmf+s3Ft2rXb5Kp1UEJKoy1v7gCc
YZ5PTTjJU4mNpim0m1DF92PotLcUXPFi+73LQZ7GkIA996Pc4FMfqCRChJ/sWEPlK95xG/Gmxhsf
lGVLN74JyRQ+Z45m3tFMimk8RYPRhmzKJIMZBTGTUXf8ET1K/5oPyaVzXh3njJqIuDT4Jj5MEK6H
mwqBTgQvKMesAXW2WokPH878TtPTP7NauSw0Qnk1jWiNHyKUYvN1p8uVbTMtv6JjK9HOo+TQbIGk
WyMH2snxgFT64Ct0FlzQKng3VkLO2h6myiEJqp/8lxjaZ0oFC6gegTgAvc3WKsljWEVeYCCLMDp2
oJE+iChKhOiadq8EsKESAoi6UjSbY7mzLgV8coUQunpZyDfeqXaVW2TRKjR16TByZdTMWP9ac0cH
GM7naDtYGZXWdytQvCHGJxpA/gY6xNzZTMHSYyp2mKyhLE2i0ltIwpDohlMD2OvgDoTBzo8hJynm
DPcNfbz73zkw2bxNdOtTQFn/WRmzJKEb3vq6XiC/iuQqY+ShY+gvl1+w7JMznDgAyZqmWQXKVFH6
IeHUHn84gx7Tswu7W42xv+Qf5dx4KTaxhUHL1KJ7gkbLBn1pVREuOYmrsO2bZcOCXAVVun/BfItb
dWHgj1Pj4phECJw+OZsqUl+nmdOSIqkR5mJbcpI9phBsWzS97oSF4iAHy/+UBvXC6JdiIuYCIfzh
UbHM+1FbqTCoKCc5Kq/ecja5yel5VjXJiCORFshnBgy/lv5g5Lv3/K2YkMhVj9auDmg6lYcFTc4n
90TyTWIDl5WCQr3opTeUSVcDGD81CYukxDsJojjjNDBFE93paTkVM7A7C56gX5yHQstJfJdvhXuM
QA6XTsg+iZ5Dp6lzyihM5NmC4rEpwu9yYwObhU/aCoUygk2ZbJ685RPZr5vpEpc/1vwyNug9X+7y
ncinRZaAoJQo/HAtRG6pSzR5hHMnhOS9EimppCcpxUV3HU4rsEqwIEoqptCtSToHMi8R4ACpvMnB
OMgCohlQlc+oI1wqB3vxT/Fx2uuUe6WVIhtVNOX+6yICnET9VvTTDi8YODiVJWLUg8auj/9EBHtp
Nj/H3N+066LcpaSuoCTP3MqkVFP+X9OTz2H0r5i8MyuFc0fFQFYO3QIXUKT+ytbihVwblEBwWM/P
E76OdlsnNNidNow6yfECifueTR8H2Yl7u+IRfsuMZN9IL6zL1+o8cg4llFEMc6DZSvHl5lcgKXKo
ienod9+mF5ZS6cEt2LVBqBooXg/Nr02/l/QS+r/kGrkMUTgzsufH8xrpqQrgfXyukGb0i7oqVRO2
67RjiS4CZFMahITHSOSu6awbSo9CxUgmfaSDIiZwwP0+XE2vKTKsezy4TMKzR6abNKWawDhWCUpZ
fAud68qxbVUZ1CJoqOnlarfP5mi5Lvn21PiMoTN/PfNs3t7X7U1B86Wt8u4g/JvKNBe6vwZEdSo5
Cjyv3L6VNdsMeVg94808jtAudt9LQlhk9bIT76p7IFmGuPkI825K8YpUICjMkwPgXX2+LGIZyP28
qqgu2WIovPmHOhJtMrzSelMijMPSOaX4h8Zgn6GHoK3Ro+CTbzkw7gdKq50Pz4u6u4ESr/Kfw7yn
4EfUn51VzBZyZ1l8JDqns16qkOdl09cLiR4urhWRzfaWtKRW7XgDWV8Zdy5SKDkcBqqhG/pJxzho
7e8BQICcaXd5A+Y+W4Zh/56emf3yGdRZPyLiqzbDDRyoS6UnTOmAbVTe49/YW9J2FQrjB2Ehb5F6
3JvdhSgkJZgKxylhZsRegejT6udp7mt3guYBI0zdw4Ex7jJkE8qPpIxEhXZ2ghIJHV1/AECq+UDJ
VTtZ3PpO1Lvmplzua0OlBCVHCMOxqmlMxvMbVg6hR0LFFzNl809J55c2cKgMkdn782XKaYrMtxRn
EwvkYjsQxpbA9q9cY91EAMCKZr0r5jJfFX5m3LgaDHUaje+GNYOjkpBgO+qDOxIXM7LI9YQBf3rn
QL9XTBvNcNPCC/Zz4RBBjVD7IUxBbXTFotV9OUqw8hgCH8tnlsphroQY2jseK8JbxC4bxLF8JyBK
brTaUC3LwyHFAaiqFWql5hS942Xe1//dCLQSek71qhUXApbbjS3HMADFtue/b9mdZlGT0I6k+1hh
CvUXHzp8xesLkyMFyaZwDeHksJz5AfQaf+ENV9D4YZz2A7Mptp9kNJALTAaPRcQuTXCX5lR3rJDv
WilTN6qBPjswCg+lfeB3fSQAiQhwcTbdCwJLtf7ZItufUH9qxEHAT/a5wq3Y374u9/VcR9D9K/52
+qYtMOrDsw+cnN+vDUBLqo3BydTwbvR+kyo0Jlsd77RR040xzp1FylxK3rxrcMgKswjyddLdFePv
eDCWVT9YNrN29wDhRofgZ4WWUieiAFICOgowDBfJtvDityooz0F/xC8zMeuDjU0rSK0lrpoTrM7c
0ALjavqpPOfzgGxOJUA3AvGSMhkIKz5ffxdS7Z3LXnmAEUDDM39h6XUQMjWNAjxTwPurYHr6o+ZU
B/1dktAmu7Ijk0WsNHRBNScyQ8bF01VBAKt0v0jLSqPxAYnJHiHbmZkOvn4zht44cqABszMiL6EE
DHV3V0RBE6HJb/Geq/V4PfLA/4r6l4aqFnGaUjKCnpAvEBLer21DL/daBWys2ZrzkO+177I9QXlK
SKO7L8wyPdGxXi8CwTEN2wsq4nzJX6flfRLmGA+D1/6Mo8f46aPanAKaHbqzDhtt82nfdJDlTaPP
LJoeOwqu2vVclLhwLselgw9PxWaXdq41lyJxupQhezeRC3MLoP7L+16gro1xHrV6MwXeh16INODY
4laXD/7chsKpaGXgkaproM0lwixxb8CCYBk3v7el7Q7hiXb5BK04SkZ8eSqNBp1kWgEbSaVYTea/
j4/6lE+wVrlSmVNepeCRlUyPqnEbusmHMGvANNx6fp2rKr0exG03RGcrfI7OErUgUQX+fNm0pMGY
5k4RS4Y1OzdtAr+lLI8/h6610f8+brsXwO7Z3yrdyUf0S6w/a/IY/eF4DurAd0JN0PjWGY+yJwZM
xDY3bdjIN5krWdWoWM1tnmKzBgcMyPuOdD2mfVTcJJH71FTVvr4hLUSS41nz8DJKRfVfitXWUKRm
2f2K1KGmyE62pKO7vupUAcBbWYc6UmqFnjJ3vas4xcyVsbATZfvnTM3WrTZVmHyphylxW/iuK113
UECgIBAPdzhq98KENXyCAagW3t1uB/paPfQZ2gOjtvWwVKK7banb9bgA75lyfAzlECnMub53BA8K
o7782WRWuVCiRMB4dFp2FhR4leLk5Go+v6Md7oWlP/ggvYHXO5Uw19DS2icJRHzPirTNyqUMDX1O
7RnONUA6sw1BFfnnWmqfVxD1bSBAtIyAeUpnyEkZQhAOLksV+KRmKfD5vZB+dcbJD/nN6IshNTob
p8YhtN+K5cfDDfq/Q3balCHLi3PJXH1oOPqN0xtVvH5ZpxFhua+kJwT/VwXpIkq6su2fRBeT3B0/
LlEadfVQkVQdFtnAxF1Z6gFUuncPzd4K62k49RhgwKwaBYHzfQ0AipmEKJxOIt0RXLP3+S3WcN95
72WvTyMPBTtZY7v30cGjPY6PmeNvs7JNvkm6TNWj23jyvim66MhdyCOsTFynJ1nYSbBXbx1rUbSG
rSJAjQCFDTUkHWwz+cZXBt0Q9roFHIHoZf2TrCxO58bSXCVamLx+M74YKClAyUuhH9KYp1sBmV/r
kwt036draKKtRN8AtfchA8otZ99GgEnA7kdsGTPI1zKy8VVR9ScAxF3psZVOhi3Fyl9F+WFgTPzu
1jDkTmd0PGliBtU16y4G9qBrz8pyPcXvn68p5HL8fH/tJnMgTV3WyteIWKnr30PZnQE4EkfbdN7F
pIdF3apdM6++YAiTMvjVeUEJMkLOEUYIG9rukK5E7ypsloFRCEPw2oZikimJl9DJRvqh6KbcEUsQ
fRSFHFKLo6LT9rKLi3qwswLahikDgyp9yhQB5AWM+C/PUgC7Cd8lVBbXl3ToirwU5r88gKqSixu+
zDq/wg05TAUDv7Om3xJ9bkcwh6yI6Me4FY/KPI9DGx4kl46xNCP4SJJIVCYa1ZFjikSXQNJ8A7Le
Fn532InEuwST8l4GgXybcVQlB/hNIt9yDYH/6/iMyb+4J21kx6HKVk6lr4k8EmON7ybVx0eiBHtL
E857Sl4bVb8IcbtjdCDN4iOpD4/uCv0mdMEW1P6iEsGMqcALV3cZVqUcBkwWTpoWpbjYIATGy4h3
PxO8mMVGPMzAY3PnR1fwmpxM4h2KKN6QNYia8mhvYD74k976jfHu+Oa6K2rgGQYC4D6qfZCDTNe9
vgqRmqBjM6WIUphJsapAbDiP29q/SElBRFq9/hRKwC64Ji9E2U5w9KTubvNRUGjQGDq3xNkry7iA
5FW+Q1TNBYeqZsNwAYFcnqzVT6id3lxsvukbL4ZUuxNI/YUipSm9FkBZ9ZMcP+NIsh9gT3mk0V7g
7C2iCceg2I5OnHZ4J1Wkdb6GxmQt0Z5tSm81j3h5IoQHbHCAfpsDDPZu1Fxp11ML4JKOFm/JgSqe
K/00I3y96kgYrwjVmX/dVgWmfVrrcQkj0LvBmzNgymK5D9xwyzl+eV9rRMabJetB7+HF+l3+i4CF
1Kmud/8qh/Q8lkCoaouTZo1+wcZASYPx0ux46b9n+4duw3Ntl+gVRFf7abAGsj4Qpucl9D3XmkNl
cFEJtr+xpyvKtnodWjKNCtdxkaNNLnGEtXNg6rfjD5J1CBOQpm1e4Cba2g3wcTmQHB5pUZykV4p+
zosGWBPsjaZUiRbpXWWJilL1zYt2Zp/NUCvcAfe6uWVrJ+DYLr4vdqQnIZtHghVmcvzEM5RZE0rs
QLmnIBEI5sV8GM8rOIYyN5MP8zot/NWAsnvRQqp4UR6oglqefZctTtNmdBkvisZhq+d8GVkL+/M2
NDupwg2COLpfL67H05PRIi+x0/0FmiOZEPWWPDKxK2ASRVP6w8yD1DWiNCC4d5rT6vqhu/P4TraH
AM9aHXSR0SrFaGgQBXSYgOiOA6w3t8iMyH/Q8ihtWW0ZyFqYsSl+yMH1XC/6reKxVR32OCObzl8D
yJOApGNBJHf6fe4u0cHzEttSQoOen3IhsGYmYp7kFPMIYyX5D2GHEl3N2j5FkEPrFRiebM8gxcuS
LsPIIPPF4FjE7b1Q/ZuGhTOy1kMaaWpE5kDgJDvJAntwGqFIe9uxaDPtdXWszAQZDByrfwId/qaD
Gwzd83zTXcRRjpTEfmDxzLKCAve29C9IpnZ4pe9Pqe81H0LBPFraiHvEqLes83UFsOY55qp//GJm
Hn5CfDHbNXGIUZ191QM7YkeiJgzZZJA/eNTgQ3M5CPQqu7GqBJjTD27+yxwwx6o2kFmPWeYdPC/1
3kmIQSMMRiMa2s7DkuHm60nvpA+768MhI9WobS22XukyTZUDM4Edk6BUkZnf8VKxcryfLnpWSyM6
x6rSm+eL9LC1NFzFGXzp8KrzwmGhjIuCrIyb88DyEBrNJ1ioTjHrIndx52CUjSfUy/j/WUPLa34B
d97ZeenFDd4bDWQeOB7c2pqliJr5hc2Y7L3NLO3CSmC3tg+rvxDuFNTgtbax5fVtP00iJveuxLrq
IEdhRGhgHR080A5mpNgIKp3XQtXqK2gm4PaC8MIXRPpXFHl0gt6T2SC9LOasUNK7UradsV40YMLX
cFx44PCl08Vn0pO7CAeSdfQ2OD/l5wzyop9HeJdERkGFmDv097LCbqxVZFsiS+KiJ+931XWBbRvr
9a5nzKoFNRRe+oBbM+umnd3isDaJDyQ9fI3VLL9TyqZ3mhqcMpqMXYjniheF77Y16ku1ytwZxuKE
ebWc5k1AbNFJxHHb2htUaKafkfDUd1PacyYxHnbIFVGnEskYiLo3gMYmj4fj556P+apaAIle1acN
DlDjU6tQH9PpBVmliP2hBJ+3jDrhbzdv5YkI/zy4OWmvI0xXbvVyKRVfsW+yGIKjdoKcLazZCBNI
Kx3oe7fy0G1eIB8pOgZFHSsThWDMElzAA34Oc5Dq/NYfFPS5Ev0WuiDV9bUv4hf6JO+QQMD3FOnG
2/jQAbjW4RhaaCKs/uLK1CAqKCwFvEF6oS567LkxEgJEVpoAPON+6HG38VPS4hoobUapc+BZF9mb
5gdh5KBzdWu/PrE2IOcDlS5EW2avhZKNPaFLmrsik48H41rT3JVTeiYDqKwkQz0caxnDrxPJmn+u
nyqg47p5wCakp25T+QEf+A64G55BljqYA20lGpa/6RMpCMqEC7GZpAdVwp1FxMDVu9uK8VUK/lVA
s9dJ9xf++mVxHRV8lNPvYymMchk+zx7UE4DaxDf7Ku4wSZWklhjWJXhG5v9ZU6h81y55GG4bzGpz
46LGS20Jy7FrUVG5lO2/XdL4NIoeA+k9kukOzLbQ0tC6WxPIMgZ2OKqrwlEnyg35Vcul51J3X7h9
gg9AToz+7fOtVpr6luAm2jS9bzUbxX2Yw4OpPjEP4HtOR/4TB0sAbFRClexfEfSRk9d+hEwRaRja
HepyKEMjWByOxxpmpZAMglCAxThofhUgQQCSTiuXBmw1M2hkDaDE+nv8ciHhYHDljkRepHWATU2u
JLkE+pH2WTrt/5dHJsJ6IoY3gNoK/5721I0Fyxyv4ByM70qTMVsJ4L7Ml0j2AK1YgTieQEx4TmQf
AUM+mKaJ16ahFl6xCNDdXZKRC+nWUL8bJ7Yj00hUjyHIApcZM8e4Q/2RN/IfAHYLvle2X8flE0nr
izEy/oaAPuamamjKGkvog+s9xYqnHhyhcnFQoqGaQA5KQe/kStgVpdVdyDxZNl+ArlJ98wNLGO0y
Yx684F5AbHd2o1dj0MlL4QoFCeHNAHN6cQkfDyaCmyp8DG4ejlb3f9RvjxoYKNhgmqoeuYOrnlYn
K5Fg+Fn1GTGrRnCe6CuUjI3O64Qa3HEcIEGNTHQaugISfx7Y+KTRT+GICQrXC3Uy9zjod9dKv1nW
qvQ9hbx02PPPNUr+LZ5Hufq4VcWzE7P6qkR1GKY0RumZHKbDedZxtcrk4QMIR7P+56ibNNK6qAIb
riPiN0sFl1G7l2Q6WelrBKk1klXY7h/BDv4ZBEiCXXi1t+TrQl6Z6+hslh4gsKBQY+u9LukTCeTN
tB6B0nLqReiBHkyuFpXaf3RbxPRSleCeHam29lwnJGB7k9tq0Cad2gyuYVaWSckHCsnAraW1WrUP
/sPcWscntKabUI3FPOvB0643i4cJjG72yI3bM2rha3UVW0K5B6wRX+fUekCdx/apSVfs84JrfSlq
PtygVWXIGfP8JxKT2ATz3AMknc7/olOIk62iS8IWwlaGNhyhpm2pd1dcNitLUPxo4ti6j3bKLCZW
ZvlduNFUA+Mp6NCn7+mQr3Ut9gV5/ahKnCHCgo9/5x46wvSGEaqqceO8M2Jnk/9YbVE/ucW+hiSv
NMlL4oVCHj+XBB+Tygeu8f0lFsaPYitHAw7AJrL5i+uT8+TwmBWpMqDa2hkPANCeDdoHTL4Dm0b8
VgpqMrOTIGfchUWVAKpLqFibSeg0I+T4zg/2T7INV/HDeMkAglxkxim9rVtP5wJQ07hAvGX5n5AY
cub1nL4BjcVweS5aPtuk9Ew3jQC50C7GW/agcPRjKsVM59EjJ5479uSXlnCdAl+4FtCUijcE46th
IwCsslQo2vmHbMguSmhGwPgTce9HmgzK1eTeT1WzkqFBtUDLO6QR3kfEgL0iG4jxfevqJfkzkMwU
MTxDy/XF6DZAVXWSHTHIIR6xIsqdus3csxyO2fS+tqYXMVcYw7pSM815amA/vaJE0VUKZAHcpE31
WT9Jj575vT8BduuvCATW+wUp4nfLPSf0tKNyKdCshKd6cX6G21DhA1ySMU2m8WAZ4zqowIwuchrD
RfRZNqpit5bQOcoPsRoU93ULoz8U/1Wna0bPzIHQDVhxLDU0YTtku88JshooU6lqVCT/hRzbsUTh
YcLQJ9CPu8LiWm3gz70Jpshx8gXmpnVIIWkn0jcjmTv5RdFSoL+k2Mz1fDVKdzfCjuVMclkiazqZ
KLf8y0dQ0c7BCsz3OZhpUZTKhtmx3XAHeiJb1yycNWKqqqSmEDSX1deojAk2WvKgd2qQdyP08Z3F
1s/50bgOB2v4PytJkyK87arn1GW7DWNWGHfgQpd563nuPYguPqwaRzff0tGX474gg2whphUAd3Ws
4VhRJOYwqe1ZCXBSZobwd6YxsnaCMHg0FirMWCDCl6mzjSKu3M/WV7nKVsDyPMpN+t924O2iHAYl
G4npXjdwi23lOtQH6RVzJGYj9/Tyv5hD9MVVDqBsibAX3Z/LnpcoL9BF4Mrh8XQvgtO4JkYDvNsj
b5Qk/c//yUvtvEz/PMMKN8l98XP2yhz6/aiAI3/s8QdFpxg1MPDrq1uq8v79Eq8povT2AnN1Zudy
D3ORjKyWNQMS69fIwQFRdd3xM3k5Z5Kl6TuU8j+qgqgUvS8sqL4S1MPWvSKMJ6Un4K1Zp4CP/4iL
GdAm7tVwCajkgKNhox0IP8qADck2gAMxdypmLPEH7zb3ftl13i4OOn7dqCHBH3eOjg5TVlQeEFuY
UM51lUWc3mACUJ0kGeC4CgHNPASqzWQYS18nh4ZxuWMxiycom0Nj22wLK2nJWdGmOUBQNF1N1Dff
ym60fAwEj0GyvCnKBHdWhMsOCdqqj7EgkKhilWilKcveQY8YkQCAzknqSRazNhTg4lSSqLyJgR4I
uIiilZDpEi9ODtlxBRYczqTB1PuEmp+RYsNf/X5IDk1nU4NPAIXCok4OoQYhwSBPWHKNeci228iU
EXDvpauTFhKpZT5Q57zCs0XK8GQaHAIYHHgaGHHOAnuS6XqB7BdtUoa6c7JdNi6SBnxUVEminOB6
43QSe2xWpHFFZkegeqU2WJJoc4gvQbEAEJZRaC8xrA3neMuGG+rosKzGuHdPvHkopxO5b/Pj5sF+
OO0eM7o7k4VteUw50wnVyC45BM+rI773U8859EUNFPwVheSvdusYZVDr1Whiq+WUw6kRFf+lWXNW
fl5Vcq43SdvYTZxHRzofV1D1zvePYHta0E9VvaKpwAvTqRz1Lcd/Q3L226fLDq8ZeNMl5uNiG6tD
e1iv1QKAfFORZ2XcfDimh6yPa7xonGMUCN+0+TkYLk2KWn2qp072ZXC39stmxIJqphZSCibxt5lV
2jjxpPZL8dKLstYUuKA7KXkzByh4latza8SgM2SCCbxp5+iybOOSjX00Nw08qRwO+WuDA//n8AqA
FvTV6wvNtNviymuGnpabgm/QX+TVKO6G2PmERWlVorWZ4Rk15y9wmjsBZq/W4DzfL784uFE2r5Ct
VX7h9G5nOByr+jMbaEvTSN0CwWWAxlpbfu0xb4XWUUH2d7HSamG4jyZE0h92RtE55PvlngMtDdTh
/VVFb78tejc+hzdOk+53XK3S70ZemeG39P9oCFFtuVHudKAPLnM2ze6X3dk2Hgs2aFSPiPSXHNgs
xXBxu7+TiFc550FOOxNW4OX2P8lJjRyI4yZKarnCX+OddUha5TAx31vjWkTMXx4yOrtq+wlttUJ9
P8XaWv78raO00TdjhroaGFoN8BbM2oDleTmukHcnqKn8z2sEp7fMT0Ao7xO6JdKWEJi/kaQ22mxS
XjrE9YMmEAn7LvgnYEWsjwyn0SfJnUavLVSPwAeM4fCvgyGdglYu9dhuB0cHTLY/9Fpc9zC5BEFu
eAxlWz6wOPCGtb8GvwLuigeL4rPcrz3FE1jK2D6VtuppsPDXQkcARvkFh/6RWe3FQ6Pdh961EHZW
Fsbe/h/TD+ARJfCdemJBd8hLWCsVHDK2WE/svAjQPJ+I49Q9ijYFkppBiHqkYSk2zp0QSfeBrTb1
CCpazgqUFROhq/2stHR7q9ASvhfRxPpFhCAgtI3StRj5CwQ+3mE+aFPAmE7t9tjVY3iH5DQErL5Y
OUEFpbtKFD6znO++WI/9+6dfToEwFVpb8sFbb5N023e2JIxjcXAHyAJax1CyiOQbXmiJrVx3pr2N
B+A7RcGy7cqys7owBinX1lFF9E2ItH2fnHnmi2VnID+z41HHh3/dRtOAo9Hcavxk0KK7gVVHtZw2
MubjWlYGYcuqQNhyG04bOXiyFJp3w8dhwBEa/jQEoUdZc5I2rI8g00Etzjqp0uqU0X/YFmcCPbnY
b+Dzo7dl9GjzQ/zjT4WyBPgDEdY0cjt57tnpJ4zxx/zomOArydrV7mXzGEZvferCxUVg6Wc8SHkN
Jp2xzmFMLS+9bhkWxQjMFzVUdy1wRiSQgrbThIrumqVwcGgFvEKOFSa6rZXU6MCOsamqakAl8fz8
fN79pNp4bZTTANgY2b7JjCxc9uNTG8wucJIn8i693rMImZT/V8ei1kQfTxAMaOzK80XGdUshhsGB
4wpKdXyfc+57v693miJ8iATmHl2l50S3d4MNuK0wTeHcI3HRdPmmf+XhX7MmUgRD03ikCaXGU4yc
t53+85vluN4uOXAAuGZoxZo63P8ItmRrbbnPsMmCyFqwc85s1Nr1UAIWGDNuK6NJAjj7gFU3hG1h
vOlp6uylLvMrJuWT7RAHHipLTFYdMnA3itwRflqTInjAuV56lr+Yg3gKjKCrkdFimHuDGBWWIXko
rP9u9MZ0pPMrPEvLTp3jOkbAqfm3ROcVnRDKxIc7qN92yznabk2j5IwDLimIzzu4sh0dIHpfF/sh
SZobfNWzS9k6DxH1gFyIKe6Ko0kHmQo0tlmpw9CFzVDtrOmnT2DlcnKsAVGxDf8hF9yuKRrqCYXn
Yj/5Ip9GO9f5rLgMqa+rj5ir2B6WLVTLKrPq3fVJq2cWJNBTA36RzLzcnuoirRn9nKq4IV12oMU3
c92ykCCVOCy04qfKGx2oCLFUwA2uki2XgxKupBlhDtOEauEjjlBrBbuSyr0+JS69ux/HV7a7LHn5
87GYtvhBncHj1zer4RV9X0k1u3W6mfa83Yp7+ake1kJ5CTGG7ldQfrRs60SoTtRtbGPhSN0jovUj
5KDbR8WFQpfcrBMnS8qoRCacaDe6hu/NVNl7HBwDtz5KoWBsI/k1tBy6dYMDUm0cf0/kqfyuv/wO
rQk0atWjhsVoJGRTfEir9JSjg1lHLvSTJhwiOJScf6kd3MkpKYK72Fu8iPyy+Ax0PNrwwdwcu3pF
yAvR6lDjBQzuHLLrWgJOUF70tAPbKigOsuXHvrYE6Vaff9I4V00V9k1qn/CwAuUbkbjOncVuQ1DQ
Lb85O/0lc5jkQKRBBhK0s6qlUgHUCetZs1lmNLjIh+MCpRLyNVckOTwBkb6BUFWAt7EPHGSl4GGH
9posRVd818XFVyS47yFWUASfsX65Qrc2YNS48PDHagRubgzFs8+HTc/Qc7cESsO7+3eAAaKL+g3J
a9b8hQWiiKJekTQn+TT8cZpArvtwlAng0nolfoBfPEBrp5xrvnTsmaCz4QlPd7qBShw+QH9R6lRS
+uXMzm13HgNQZ8BGNhVw3B0ORpDuMPVjuAwsxCaNV7EILXhGfkgVQDHrZzFL8tpfO9KKyMM4d2CQ
fqE5Z1dh9JRye7GVu/pA+Ja5Zei7K0X8J7x/fmovoo/fYvi8YXfhqMrkzUoqG61NpLJZTkxK39Z1
RSrQ2pmaWZmaMqsI4lfxCp/lNoW4aSeaDe2ZYnqHZO1wyTIpu1EeZVi+pJY+37DrEAaJb/S/Ukxu
0uQBC77OkkO6a6cd5H1u2T4ADHg8vbig1yk9y5a/1G8Z0mQ0fVjk7mbic0bvjl0Xa/GOujYwjbbC
tHQlVNYR1HNGcrkq1Jzow4stcWKt2N95n6Vl/BG0yx7bVhOvUaWnAhnkVllgLgPFQi/nILGLrnML
5cj5+loswvV9H65gQacOTJmcCrXBNf/MlhQkYLcCtQowDGMTTi8PHT2LeBc3gXHzx4gy7/aAWpVt
V1lKtWXhLMTrgWZoynBB4qNNTjsWszb1HubKMCj/VNlgakxXgdmomBlz1pDppXTTHeBS7bfenfSA
KB9kOiqdOc0Zn6Eyo45gtsBHaeH8QRqpIDAFGmTRkyYG67HPNSgUq7CdqAXeqih7R/xjcdf2gdmH
CjYW/4LB3LOp5gOnM4qIvqKeKmOdSWw9Qpj718wj4lgMnSWi4cKtttvxV1YulYR6gEfksGswhAz2
TK+N8doHzrCKdBUbp+Iw847iUFIFVth+OCJEfYpp3mNkuOrKacMyuzRnmrDfudczz8uJ+F6OhekV
rUcl2aDI8GjV4a+U7V1GLVL6wQkp831jU3vtbJFTLeytOpkibpZ2uVOD2qil0FRjPLneSYAvWudl
11jZ0JP0piCl8THN2bCCwWXa2V89zKSrZEhOrCmEYwMmSuiXalF/dEmvL+hiahs/fi5PeScqonrD
C+F5eCwsr17Pm3gP1PfVqmF5UxGOgVaLJsyuFwCY39pnf3629igw4aNvWOzpf8Em5SAnkWTp1EH5
/G3V55cEgmO0PCfkBNSZqrz9AxLgbk0tRDOu3hHJ0tyFhfP3tLPFEGPTVpxZTYnl88kj42Uevi66
xrMvvtqJvNCQn0GtG9mo0H0QhdiBNzN8VX8wObMDeT7FRINj4CqkuABpSrj8sznt159+ZCjV8gN6
i0SZo17WZE1DRUogokelQRak9mZrl19nUMs6NDvaBN7fgIMEK9zf+gV012wkGe2QZnqfAfej9+R7
7jJDohNnbx0CSTDVdELozsUaidvfn+BV5cbIp57EAbJg48uj80BH+TAyKVynKFRAfab1AQ5Q3QYd
5tUK+zXU1iVJLJoNVtc3CRc12Yov/ZduN4bNQOhhD0yxoIHLk5Gp/Fgm2Ih/fuQDt70/TcXzTKo0
AyHq4aAsJEOm3btDt/Fg1dCWbd4tpjWv/g4K7b9mYl+cmsBk+6MxtJ9KWsMeeZIry97EPI6HmPL+
/bMJ2cKqGndFTbgbXmplBhgoUOWlOGEfLJBObMVvUnwd+oDkbtbKk/IIy4F+Cb70wQqCNzsWNTpF
HH4Go2DwXXcDgdZYbLvXOu6Y0nIeh4+O6JIQKge9ropDDFteWz/VuUpuWuVQ6ebk2sCS5bPHTE4u
2mDekc/Hl1wb9jBWaDMP7w/FMS7lBhgletVro9TFH/TYDjklpXinYtKf+hExRBGUYi2l3yXkRXtd
S61Pyy3Wd7/mgrTgno0PndqmrC17plnv4/baK6oUuIfMMCgrVPwzdfFuMK0M1StUUVp4Grzk7i7S
VMdC7sf7Y2n29cc0GnTXz7bk3wnzSychJmP4RJDb/dic9qmtAc9aJBoyuwnDcpalQttbOOm/8r0W
Bpzz1Q1/fdUeVwXoIXvg6Y0cU3qX+MI4KvRz2ESxbuyQG5sccBTaBW63W9rR98MhYhKmKmezP3L5
H3q+Rmik5oD5S3n1H0V1W77TTCuJr+cfOxM5hqOkGEWL4tIuxMYMazc3+6fmM3oSeiSSIZDTnqql
tSXra5hywY4pGR5WiD8ZFjBwSMG0VQE6cKfT9o64dTtxgnSN6B88pZuteBIINADkpcD54/QXmeTc
7YdG4XoN4iCXNmNH8HKkITHsR72muhQnJ2ySlYSDxrt58sxCMT6HJQgligjIPKudg5wmgAvxv5If
bYBhBu8gq25PKCyW3B75ItS9diPqkCAjdawVNOfMlaJzFal2/6S0RaRMn38XDZxPmgsPBn3oFQ4Z
eks/EY3RLmHuvshIaNbcInQR3VsHXyyFh3jTiLiOK7YvDBTzFVQwC6amBoXD80AVzuNsKIkvXx5B
DDdEj7WwFe7PLSVZLce8AVD4UjNnUm7gx3qpvxxPzUnrNM6gP37UpF2+2LtvnAqBy33pmrzgL6QU
h5WDxX27bVoVwwp50AAMZFr3KzlMKIrcXmFowqUMC2Fkgikr1tsjBGBYHU7ra2gK/JtPzIELgkZ6
qpNJNcxXzbtZp7Dkky/Fxp4iDogdTjRWGQwBNekO6EwIemjqKL2z2oKv8BoccTFS5Mt2wEYUmy0U
08x6if3zknUsFKBQ+qJMloScCjYfiXiPJ+d7Osh6uObqtqpyqHjGcilSz9yoVDrTIE5fTXKDztL1
sYyZX5o0/oMavykQDODvQtewHVZJBTrFvPtCNPj1WLqgqrs9PIUXViN3E9CYiBZKqXvl4Ld6mGJz
wtwgTQt9uOsUR8UN3IkqpFU0rA+TY88wveBanV8D1N+X4mfEMfixq/X9kVrGNCoIs0XiBumgo4GI
fewhRDo8UI0oOPJX7l7QhJ5IwWefY5bwdsvw5/ubgoylEO4uWRcGZqW+x+fQgxUj9J3qbLROYlh0
MElAbFftn1U9fNVURzxRfOif6FvQylxMv/eXQ2Dkwd40Xp5J6o5IQSwnTODSW1O7gqfV5Tk9DtnU
fe/qzaQiMRJ6IiucCO35RVgAInEekp04V3BxNlcGm9t5np1KS98KVjxN5PPHWNHGz4VcHXWhUFu/
4CwUXkAXyXr1/y+Lw+gOe0AmhTpxgAdGxMthGUu86GEoUxJCMYqlgiN4clrpZWgJFjwywQRGccgR
vdQHWUCODtL0LnIS1mCcYr0GM0R4zAFbwfz8y5PX6SMQYPw+7Alle5qC5eRmbXxra8TpCDIIV3p2
UqgXbsAa75z3tGmTFwi5T6pfxDXR/AWbjE6q2dbv6VDiADxxHVnXEsCTVsTLIez1vHoJIHoA4xWc
eHUPSijDM3ekX/cDfFW4VCeQwvCuPHUMzJ+JPkI7lD/OgIWyvCrYHIo+in6pflso1sdUFTYX66pP
c3ckzKGl2y9WHVp+RU7Apgkykf0QGgDggQaQ+vT3GlxjgtnCN9VVNsSFQn78r+/sTgfAhnXrVsBV
xo6BMb7udOvjSFkKw/qQ5S+v0uGIbRoCwTDmTZoOMNhJIRh6ozXewroZzydtyCbju7zk4CzCT8as
5IF+QvqOsrPL28NT0/x2Qkz/tMXU6Wu6ngIXuAOIqf4XljNvnYmYL1XO3yZQUPYeslZDZmZhot01
q83i8K7FjTEnJyoD+wJnER6A+1G8lFCkE6z5a3+pJlh4NLsGjrWZOvzz17vTin8ke58cwe6qS2D1
wCKply0zPGvdmwqaLAwrVt79B6ifEkz1xxHe2A8RZeSV+TtqjqysS32trm47Bjl1yFd6dd92+nka
vMrW7xotN6fQtcgnsikJUG+SOiyoQgauE3K4bjR7dMPSA5dJ1NgMx0kcgCcfYb57UNtH+EgavAAD
BXdGMqk8JhPwHeIXEGfgM6PyD//++tJtZXdTgLY6RsaTK2OzuhDhrc74NEgigY1FT2D8QrDbRpEq
9cFjPM5/9lZ1YXGYrGebO0OSopP4/JIR6Usau7IXfIDs0TJD13O/koDkRelxufD2s8gCc3a1LCbx
qjrgilB4ocf3H/a/8SUeQYM5Snjia0JaNnnH2dqG/gKRp31LzMLOeUBUJCt0XWXWwKFxeJxbbEPX
QOk9RAt0WSJbUgHhuxGESoy9DjgNLgxBjFjBuJ0kHoJoFvYinS0A1o7oXMNfoEWsX+RJkLOhZ4n6
mxDMTNJ9JZ4+wxzRH8FC5vxMcvfBKn/SsgHyAvD8chpocvg4EVMThurt282RHTKPB2lGq+qvYzhb
P5hyXAqwFKuweofqawXT/cMKcdhKlUdgNLQDTVzI+Bwofnfw8Hf4ogaN+uzMuX6SZAyFCVA3BHYz
3t3+ZY7dh3Ht1BarqCryCiaTv0+ZhhZ96DMqeezxyoyPzA2xu0q4os/dgFQES5vrny4C4L3Jx/ui
LvbnLKcPnDHelYAiPHRO04lIf7qfNEsuoggtECubSpLUIG9ZtsorYGzDh7yRvv4giJqjdRkiZrEO
I6PzmiMNVfHZUiyMRTuqQ+XDB0DlGJBmOc551dAct9CbMgyz6CVv7Fi4XgZ6+3ouAroCATXa2l8d
jB6bz5URgvVXCrfg/4zZPAC30hnaOzUJrMH00Rb4+nCG9Cmgm8RPjqBabC5JaF/a6S7XW9NaaqoO
D9XYwk5xkB2bxWclzCo9OKY7AkEgUQFP/zIVTBlRvlILLUiVmhelcNfdgf5d/DNZrkmo0biG2xBo
nRJA1rUcyWmniy5VAfwecU+TBfV6rqKkigsknAlWFnaGY4nVafXGe4NLf3ZjDV90o2UB5STwFIu7
vF512Uosj0AKNLpNhuS/e69AhYi4kwsoomP4Qj1AZOOaW63K3qKJOBMwWUV7uFOdwuc3X8CQSmcn
Gx6GT3+GDW0sm+QeqvmpbX4YuRW37EmNX/7U7bEPaOfZjZsshCTXZK9MWrZPbb8sAYY5cxAUQ1j5
suxVEzDoywqop3LBhs07EsyzCKtFtRilvRCLOoBZ018g8E+J6oITAENCOQAMo2MYqwO5GFVuoi+H
MBEW3/cnZG5Z7TPtgLcAHNjxF4AsHiz8DbODs8tKmTmTuvK8H8rqZzgfW+wC4MDthq3TQ3H57i82
xY09wiREMBeJA08f9yL1vrjcfuRAfekr7EtqtuVHjwH4QmQMfx574sGKuhfxjvSjPyWh+aPwWLSU
fu0b3ceUHY8B4UbQcLr2LXaej9XKbJjuNmJp+1KZFBGOaOaRdvQt6P1afZcKdlFrDu1eGHKbjeZR
ikLcIvqgsp7GU/MX49v/XksStXRPL/GSl6RyC8EfnWDpMHYDpc6Ug15Zy/k+Q1n6Z3w7eF4VaPML
EBKZ7dmwQ70zH/bX55Vdst76AfPhAQyrfhKCTOuwPoFkCSvRQDAESxtjDDitvtPH/9ax824yh/1E
OA2uugKPJA9/CTZlj0J7M7rz02qJ/dASkiVZ+Xn/1l29psyoODJvyehshP4MUnYv/KSp/KeA6dPx
ye/HYAXRe6nx53kY4FgviZGAX2vcGkkipsXZ+ISD0zH4E/nXCw0Zd+09lD5l1nf113ok8yrcSFFh
lo+VQnKKOvnY9TMlFEKEl9nPxrhpoUOaEe/h/puxGaZOsHJP6ifd1iBvssGQujQCKYZka8VtvQi8
0xHGeodKEsYwgkRjbjY2Nex6GeJlpvnodWiRoGSazCgV3oNCLqZ/LkvDivtLm/78V0DsE5xjL0Nk
xVnJZC+E9e73LyFeph8XaUekrWTqWeUvpD1bJ5dkbpoKpNF8t9frC4G7wHmMW/WT/ypUc83bymbl
a7EJvtJOR1IFzePAyhkmW3mknN03K1IqRCxKRRP3HTzPD0OG3lKKATwKgpasBDaXsGb0EV25CqS4
TPNvD3Vzhme0mxmfycizDuh0FUIUwrOwzRfOSmfULKgxHKlOZbIvJMR1k1iC1tAFKUZI9eqvNphX
4QIyNM1kufQUHO58J/f3F4Yt582grJpxw/dy0lXQGegsp9jAu/67r+MsZFwdtO2PTsxVrdjvX8x/
LR7R7Vpp4O0g4+R/kqy2QFUR0Vj2eg51/+PrKjjgvt1+oStur9RrZl56BsHiXp4XkmsrsaBd2i2E
KkND/CoDWt3EF5vQwNdGhl6ZUFjrTP6QFhzipjcQmyZDeJjJgso7rlaWWtiSjpxCwT0RazfbxVvn
/GMMtS0n8qlGV4T+c4HnmuWeqlkt+I0UjpLPbgPevxAmiZsUcrDsLxEu6bNd0vJ6RYfCd5ac9Abk
tNyrj+O52b6rYeMVtOeWaZB024ODWFHmLUey6Omcuuz15+/Bpj3RzLyvQ5PgtuQbepBKVu4xnRy4
7/czWbzL/fE7fCSFM7JPCJoGgLSH2STY4u7I8acYBjY7Zjo6fpSjnlucxp9JEqO51GNDvZ4YuhPB
iVVPIEss2eRu2diE1599OaHxhUtc1xdT2l0Of+X6Wz126KifSfoarshCnVOmlKDCowvGaciXeGSm
R0R4AdkOnjVyfUGGV9bQplbJ8VqVssQw9LWJ0oSfG4D969/MWknWZQor3DbcWGqyBYeZzH3r+KGO
bIzsElJv/Fyu7GXVfSjBEUo4paDUZkUI5BjDC4CmWDk7sgYhkyDdZI1/pw1Z/u+3qdbcPIb0P24p
9MDC9eQCTkROBQG5fMSc5V+a4VArDgyJsixMl79qVSjB3mD/qD1yitjaflA3h0RllA58aDw2OR3T
/oIIMIiDFV8j7qDKzdp9cPBfhvyT+7vcCtro9dWr2C2W1h/ElrLhfmbYrmG3PiZ4h0mh2G3UCY2V
ssyTP7Rp3ZBE+qVJ7tavw3wQ7BYBXKEdYhETs+KcVwEqrKC0yinsSHEcErDn8L4V2rklFmpK9OGl
sp4yxbSAbCxbeI0UYxPeaf/iTEwkGrub7Mbir625sb3sNMlpGMw9yuQFa9tfgwByznsTr0EUEkAQ
7d5TAJIgCIhUWhZdlQEjmFKvwPJbMVlrX4FNH4jUepjgKMIY1Vrzw2apgw5Rs4WmqQsQeI8GsL6u
36pDA7Vja1CDn4ycF48puwnSPR1SDfbEehH8M5uFznivRx5rG8nPLBfBNd4tLOd00KWXi1hWo0t0
5vGUTaiElwTO4IIJp6fNYcnGnsk/pWiXWlSjtQDqaLJGFUZk/StadYhVypV4htX9Q4jtW37gpru4
8tXurF+oc0OrE/EoSZhlAdwz7wp6BaYZkOdS5cRNcegKmjBA6brDWnTH0FxYNJVO2RR50vCkquYu
wV4tksAGzTDf+9cgSrbySoIVpPiXugDy0Yd0QWygKVFbkahQ6alwFZ5TzeDvhjWEvvbadxhOmVOv
RnGVPFXDVU2sO6WQ4mzdPqHBe+DDThyxvQCnsVwFujEnV8TfYWe5ebONowJLLq4hMStXJPvs2GQL
FfqDVNXjU/MksK/6In7Qh1z9pikp0JZhqb4sW/VTXVrlsv4EbWTs3AA5TufWt/naCihCbZA45tY/
jaHQqGes3s0NFg6LSuK/QIDwWhlQjrT7ZeDfKnIc9vju9xHm8P1hdA3K7KPJJqlWz14/wR7mYgsc
d8f9QnCqbPHWUc0NPWMA13HnyO398ixn6bruyqFHMD0AP7WngUnX8Rr3Nq5ZuzQtP0l8BN+M/W6v
g5g4FBdgIElTzmt/6H/iOB405WGES940ZasSNTbM8IE/rWXXFqQS96jYqyCJESJibXfgof8ZwKnW
NAsDXXbMWURKX3D1KSpHLy3PYJpedCAx7pvsRIJatAdPwgUXRRx/ING0mf9MmT1FCjCAWx+E1ck8
UwuvZUiXB6kBWjNs1ef4ZlzO4mTk3lyOtzmdPPeFyROkP0jWT6Tl0ze2CSssMwYFfWRBS/FoxbcN
8Jf8VoHKTYE9SC7DLDYGVQR+uJHjDqbPWCnkMzBt9YRZqnPbhdlS34J82m1BZmnqAMysj41WTSZO
xTEdGJ+T258oYJIhj3I6dJZc1HwH+T+2RBEi+8/yL+15ltg9B9r4INtF3fH5NPwjLAOU+aIGpaVT
iIrmAlEm2uQp8u0V82ZzPSYODeki8ZDmRhVt0+Tl+boHq5xhFH9+GnAN5o3ADcnI/sgX5S+nDitA
eYnvd3FhZ+q08YMyljphObK7g/6SUFBsg39tU/IjrNCtN79RMlT1bIzT9XPqNqKyiUvly+z9P7Ke
q7xNcfYTpefHeoRHAwHQRJij++gHF2euc7K8O8lPiwImKgyMVbhPxi8kKPxDeJrMWxVklt88LfEF
mzFV307c2zeIiI9CCgQYD23gweFJ2QC5sjRIyW6qhH4EEeT5LnulwnrBktlEyw12XvNifvKjxJsT
AYF0ehJcSTdBFVyl8QPt8pfWfHahFeiYXFustJ8BAXpAxxfFswD6aSiWgL78bvVp33yNyuPDeuuJ
8SNRNDZFgRDfyhzTzq1GvOiFcqdPbxfGw0eoJ6q1KGtSQV7MlsFUgDjwnbNE6T1LxxrUXJiNN3Kc
4hP9jFBlhmVivLS6/Zjhgdb9s/MyUbImQGsb3+xNU+GMGe/dHtCoxiqK/uuSFIbECdclFd/94BSP
RP9mPnoKX3pOwCslzcPI8EWv17fL3csSgKNMlMwjUJ4w+52sBEa2uVwChqVFuY7bK0uJOuRc6WKE
d0w4EcPBdcdA6GDQu5a+BBoO47Xw3qFj+XzzQbnYh3X5RIF6IrLbQ/dkIWllgNJvXSoY26fYnve7
HUNPqpGaSBEerNJt7lrNFAe3jDD8O9uL4bSWDiBLVQgjJXECyxmM+kRGcXMfKOjzUN3edoKm7aYH
igzjx0SlBNPm3euMoUq4mAhnyBq2zA7K4qAe+FlSz5GAr9Qqusmh+2mVwcjg6qclSuXFB5vYGGIZ
zkiGGzToPpQc9y0RDiv0xAX1M5moRK45q8PDXbMMBP6ng3456DAaVi3cFXAWfDWtA7xWtdfjOYED
oLwx6DuDuKOzrr4+detJk3gCI6XMkRYixCmF6exvuXeqqgFKuTbPI5G6DRhXdDbTlk7/iiFmX4l4
dfB3ZORU6zw2YNg9KOOX7chpR/+lOaBwRiW53yAmW70FmnKaPTotvyy8ix0SxyRj4VKjqt+QLdwg
029Om4PuEuuI07gHxaybMKpvlPNKiIR970pAWCY9iN59LeRvuuPoXCCtITCxhXOgaAD5lGpQNqwF
VLWHjBu9WnrVcB9fVmfxlalFcy8izoL2UjHiSiIsEHNVLjnpI0VKe3eeNSsK5OOeeAjwCGpeK+0T
qUAfrh1TObESuuEG2pQhExCZCIEaWAQf3bLAXUKG2Ruin4S0QdMAY+bQ9FWdXREeTqNe6FNSj+cn
2j/3OBrkaBJd1KOK6nrmAjzUgewSxZ954o+FtXGwE5m5igm8tYF2SQGmfkCehK4RXlqY3U3SaFKd
G6KdQG5ktEqhcc87nx21ZwLPpSqMwSVLAfZzsXwkC6jnTv9/8BtYOteeleuFmpRmoZZZOj6aKWXx
phvLeBMmByDBHE43tC7wGumJj8gJj2v2oG4R45vEjkaK5sdE7IHBc8+AzBy7ATbu0SdBIyWu24ME
G4BnXOXqDWp5904tAuMt6bFOwpQ5kzttgNjDwEg4dKyXxv6OXn/RZwlltDCi7UA6cYb11FAN2Oax
SotMY21qQqzV2Vhvj9kPeJ89ZnPUWNWt4hMDXDHHZnnqj5KA8dAV0tPiwaqqiSrgA5fBjd7FXByN
TyD5AHWou5vCGsO3ru109ZaHQ6bgECkpZKtZaVnlUUYcJ8wqGhCy54ADmAoDI6/UAlusleVr1cqi
oK2W1Ounc/GS3oZCAm2XCAneg4c7xnHuxbrCww/vzn9VGQlEtOwLqWupaFlskrKUuvXBkLgDJBw3
bNgctd5pPvUBWrUw3abe8sK2RCbeICqdViNFD351ChudCk7gu1eQFed7J4LyHxi0HAfGb2dewVUd
mJBRXdN5QKkSLAZTkAWR3oM9HHbPZ/r6aU5ao8KUyuiMnVKMKNVugRAvCvUd3aZLKhYEQWZgvlQe
JS1eOJ6eUN4hGdepS13tMHIPcehla2Bdqh05v4O0iHMXd/p2y1ysKGg2A8jfC5sKOUSuH6kYC8kS
FxBvkEPBsYbpUajF2r2xCX1htZMs4wLgT/+tUKzO94y9ErevaBb2ym7VYzCSJRg2lZqRuiaXAe/L
HSI2/l15clY5sVLzowTWcVdDVuYJxKHt4bUZ435cyKRmoHuVUbJ8etIZRDBPBvDG5RQQR5SxuYm0
uh7itoItYHgzMrsOXFG0nPkA+OGRa8kiXgdXgh/GfJJohH1I++SzrCbKWOtAjnayyOlLgo1gECWs
Eof3t2HUF/UO3kLgotTc2kR/Y3G0yUK7zFAwwQtykwAfZlrXBpLMD699yIvnN3Ys5/A/NaIp0nI8
we/9NLpKRtHq+WtqnjcqJe0eErOHP07twmumuomQvsWocCS7OGjYqix5J+gvpTnNkemFvMa/Bq4i
0tOM5ZX/YVQDcCMa01FrPABc7cjiBzhN2gBiebrhT0f8C9LViTaVHAFBC1O+2JIJLdvJRNULGN74
JEO6iK7HWl5geNfYRuEwi5ipe06/xzoJqUyKlFNmwHoooXIvJFIeDpYUuvZeeoIH7nsPpMpakC4L
nfosagrp/pN3HthHiv0IHNzHiCVmertYGNbmMVwjfJRt9hI/JEso6Skuaqz3WWTB85cfVTvnfe8z
q1r7hJQxM0vELw/xkbGaFP0N/bpTIwHWQ9KtJaFQO7Nn2Xm6PIQ+sApfrgRkyORW4ZXBrSTGh6vO
LcbcvG8Xy4CkiY4HwZgnfS37IzjuYN/bI8wmB41ULbEznkvr8//v7XpoY8rffsLulBtr9SIn8GPI
BZTdOHR6InzIjqSdbXmdGmqvAP1/Hiy1LlgYinkigO0UoZvLVQGB1/Cw8oQRBSsDBOeLxMYehR3d
lTzvYXjqYUWt/zFsJqtaiFdGspqA/Ymvv4YIGoHV71Dnw9Tbfeu0NeEwq+MZFX8cFlVLNztdeBA0
wAVnkGzB3LvSeMIOvgagu10c2uHgpXAzxxohMG8ME3nQMldu228Zg99cN6EsKb6sWSJ3iGyVetiS
D/r/Eon+tRFFhlgnLt1tHVeVa75chrPQlyXMJzqn37L5dyoNv03Um602g5ZfNX3H2e0Lv7tJIpng
WUJ1+Ij0smrmhDtFFQpePp4cfJcSX6BteyzPveKBfUqJF1KVVYoEXysr9scUMs147RlHRZ0Wkzja
ORb0aQS7xk3BPOPzEGaPEeu0nkfxVzhh4AaMJ2GO1sVQXnAs4b+NJKikH15X05/IvMPmSBnj4HFB
g6KjsAdHpZoNd7dWl3pfm78cOQH+ZYVMezfA1vzQPhfzCL8PeTc8Yf84Fr+RlcJFJVkNSfGALWZR
8FqveNi9U3Ppt1lXuThvQegEHxsg1Dyy5khDVIw5cAOVDENa+UZfCiqcE9AAL6E4tKVt0t6QatUb
7raxzIpAGsx7PAQ/bBXPoMVTra7ADQKJORZfbhoIJljMGpR2jVvvIUlaZwSsyXOfQ1GQ49ws5eJS
RNUrJXVyf8Uwmic4zTimDJbYff3R9RgaXrWlkGbS52h9pn5yyQSEcDmfX55aw9V0P/7iLS4ZXtRG
vhLc+Vxl/OAPlYQf9ks/MKtW7AAXkh/nXXBpgRoZOHWav/pZFWsY31oXZsC1lKHIitANUKfbHbUX
OJczIkuMYbEqgm44jpWxygpQNvjyscJDXKwsxfgmcajuaEKzCah+m02ovCkB70/jdzMbcp6YQ4ku
i9O05dGL6LZwEVwVqeL51OWh+yD7oLrNRP9S3BuGF/nqYQPu1ArR8EZgrSQtSkUCXP4aE+XZYZy9
sKZG81MeO36dwj34yF6h4ygLUsc78su8OtPpc69u0XPoBMObyU96s5tWiBq+sXRFzaiiyUGp69YY
I48jnRgyd/aMwqTjCXSd0JUrafHniEF8A75EJU4x62AKk90ssVXWvurLYiqgKYf0P/gYHpoWblrX
Di1C4yiokOC9vTiv95LBAJ1qqyCMzne+e9jZEqYDMTskH/7r9Ic+uGMU5u1Iy8aRW9Ai9D/Lzycy
YMgB21+G+r+ab/NzUKhgI4m8WwXa5ZAE7hVnp7rUbZZZd4ozqaqlhDgmzTCoOJFvxakF3oklPLse
VLtdCY+kh3ucf9kg/jDlIzQS0t2KSLzv0foemFNmzaaClsxVrteLgOwz9cgUQ2AGMz9WDGN17uNc
DGvGd7xAGWh5oXzz+EeXNKmkmvslnVd7Dw/+nYCdV/7tel8iUkQKCbEVIEDfNA+lKBotBEgBtnX1
ItduXlOqe6tujYFLyd7qDGWU1W9MFYsPKey+pFCmMuGZtB7cMK2vJ6UTDeEQxGOIzCSTW9Jwq87Q
IyU0fXYe0E0hdV3hoxdKMGWjXB45O2VzuoZbkx+PKKAY4RTVHynkk8ae3x+s/6HEpi1IWNqHsOXF
56YFlDy1rq8pxu9O4QmykxHJQWo+DKzNMs6swj3msbcH5S0a2mtOausXNaw8P+7chJaLAobWzExX
srq0E+1AirDxxFEgfdd1C9pQAsuY4UOXgkKQZ8fR6qFP0TH/t3KkssOQZMiGgks9vjjxbRhcrEfx
Uoaz68VGAfppl7ccwk60nqiLFux3wysAz4QmX75DQGuqHVFJw8BlwDM5lesCbwTO5gcPnGz06uMm
FSYQ0eSH8s2qetYmmUsY8nGEAJvJ2l0Rmv3qoCfPDNSYcukp/YLMAcui/smK6hUB2LwJTq84vaiq
7CfS0eXYhgfl1BL3RP2omAj4s2Wx/0OomxMd7x/rTbEMyIzsD2d037P10KxX+aopAab5Sbj4d2xg
NwfoFLVoGYh6vkxlzSkUZFnrOi0bwwuEjCnL5VNl+T1LgwKhpOR58Il3GW9dsVpMbX3hz16qVkQA
KBeojLOycCSqjFSkddGkTXUK7tbJeQio/xxnynuBjTumOoisW+j67wnhEFluGZ3CFd71d5fMUfHj
8ggjmLmuxAyofixHa8cLnQYrFTOnEkxf+ctSgCkEZCse1s/HrjlCjMDG5DEMwZWlXnAkNsZechzK
vYtB7kBW7jEaxlAsrEXpMUT4rQkfF/ZIpiFyrSuFk5D/f16LqoaNeBSC1EJmW84Bsprv5aUAkudZ
Nsj5j5eiI6oJ9SkLqOZWQx4O1qz9GEa41r3KsYd04J5DT+WfpeO/+kPDFP2pce5X9xwISnp6o0eG
pi7L4SWiFC8UqnORBzXy8FVnJAI9Meb6fVPTAQetvLjvDgD8E6/HAEhNAh0TJs+22FEtzrI2IdRz
aqmPAzQkf8NFwXwszKnR8SZeTQ1luKFRQ2d/7jIk9tmiyGEFeuvWiJSKSXkKiSQt6wW8FKgTAGjf
PnVVAIW2pedQ2VP8H6RqFkiIUVLJsXOE/RlDm+lPlWQw8gLtgT5xKkK+bnNMuBC6JCm8+vxEL9zN
rTm/fwLeVTncLg4Xqm5A6ZdAx28NP0tFdL837wiiYNcZdw5HEcAyRCCToySdtkJ+noz4TF/ubVqg
d0S62NTeRsHxR6cwfleElUOaXautQHRQ0SZb14ObbnyMsF0paMbJh60cK5TViYZT6RmmBwHfjLvK
Tzi5ohDDoydt3ORDxjxGEgl1/U8OU9akv1xkCtF87lOR1hn4h1s6b+8sl3/f8TQtioa1quJgMS8W
Xzi8DD2Uf1P77dbc3V9+G8iYT5XRTmxnDdxtT//Fp0i/bXQmzVaxm4YgEXQMrclvcDrBmJs5xjr4
l/q/mtWFmSauxBUphN0HGZDS01L5BuHObO8/AiIrH3zmZlb2GcwsIi6UxfnjlTIei8aKkEVg8BXe
UkUU39EHWBQEFoAAa0qJ2oyC2IQiwUTfZrY8onCPJMqgUQFr3l4qtCy29HlsaiQLu5REFb+A/h9+
GdmPXAgEshk57PDmDBdLij4tuRqhFf0kBdHldKVUaq3HHskPxYdORAHpHzad4XYBJT/zvkOUYYv8
OFPR0jfr8KdtHYLHIU7FSKJzsAeab3MfZvgtoD0HZ05vdT8X/1alq9RrhGWkcz0/9LMyzujdR6pL
Da2d09anos75JbXDyJ+8zkOJoZUbQgTtDrVqpcshY/E89zZ7CM3r8Sw4j+Y4fWq+VtncZ3UbpLlf
y5Whu0z6r43k0qN2n60uiqqW+QCQ0N75qYVPwql/MK3zOxCqC/hqZHOsR0ruUuC3FYH0Pt1/ZVir
7ZZW0ndKzZQYoiaWQNnZM9sQ9LzxXegAlo1cOBn4QGlEeBCy9hWAqrilY8WcV9h1RuIwwYZPLXkx
dcJ4NtLMQgwl8TYTuaZKI7VvguYEES57FS+i2QzSE8Es9Taf1PxtVqvB3a089wgFANmPJb/wvQNp
upg6K5k8Y9u/CZGQE17hSOKPU4u1SgVt/UPxN0dbq2qE6sCdl1uzEaUz0+qs/ssUjMPIKkyL5ptr
ph4dMjmOd91TIOk2BdAkaGd46wFugHaa2b+pBPSLicaDJE/lxX/CUniQHCcP5KMaWJHJg6PXf6JU
IuBl5yzbRReW2v+nVljl3JIN6pitpN5V6nUVGt1DKJcdI3d4iPM4/A9MX+aTvheBa5lvJx+KmeU1
6QsyNqMPL8LmvcKNLfRuFvC2i0b8E69+1hbwl2omfNGzBFciIj803B6WLBMEQU9RNl2ZJucXv8QL
LoZzUz33Ed3rFbZp/3RTC4I16gS4PK+dfbywEB1nAgvqkCiB+5f+YeKID4yWeBX2q3JN4BuHloat
rd4CrbqEHsmmBV+yFXgSDMUadyGCHQfE/dj2mrOoDCjCxS0EjBauMv/c3JAb5/uomoh2l02QzeCE
fTkEFqAgoDycJtYh5VxgTHmOMGwNv2TRgzHnRquMJPiDB4UB72JKk1JGQfK8x821+p5i+25xjioa
fjxibO6a8dGIENM0qbTr4hsnmz8rKyc2DufFLOCS7INiVyynPPZz+B9AD0LlYg8bkHNcwKmpjO3E
wVUuisBiqwKdX0oI3iO6zgP2/6fzWBBv6thnZ9w2iArqMOrnyh/HiHPaICtYPmQ91iKm44DP7u8p
4mCG2kfTXVHmfNqdb86XFKf452O2j7CjiCKCGOO4z+0R5dyIACqkgFEVjPvX6f4ALSbtb0j6sLa5
LKaGk1uuy/47f7mY9gJuZPD54bBheAOKIBgYRnGmvwmenWzyiBjxdo1tnTtsL9PZMXrXlKm/ogux
oNy1CctZHXXUx9yZzTX7uMe/db74sdabHATqUI0FVHlEUYJhAmBDpaEVOZq+NSadBeQet43zknT4
g9DtxwcrX4XILL+3IdpJW1bw/TN6x+tOpOTGYoEpcNuqqVcCFWIVTGfK7rpSU4xm1gUyD5qcdsKa
aTAwTlkTbyvy97AaUy789LBt12+2MxkN4yjrD32imST8hPqjPvTcI1SeEgJJ7dssFMBR/ohyr1ED
WTGkFfrY30ZZ1va85fh8An72Eo9kB5skxmlC16iYv/KeRDYpOXB3hUIKvmYX98U5BkPm2ls31HP4
y/rVQjEHokBWYSMTzxOKDyKYBBzDWJJ3TSMFoppzkbXT5smlPwN290XDATRNqy33IRONIunisULK
3cnu4JkT2NUIccGOHJDc6I+q2ne+xf5O4VgVh96VEfCkiz5HP8ip+lG5QqZqJYTzsDRcPwusTtPx
6VgqARgn3VLnwRdIqgw/zK/Qb8ilhU68h656JYUJoUYmamrsXqjPeTztvSioC1it0gKAIKES/ner
fN03yf4WNQTGXd2LkKx9PTei7WsNPNortdJWzGt4NETBAkJzeK8HYi/49FDdRER+ixJW8WD1BaXL
qbQIAyvhOYf7RVPhSJ5wABiuSoyp0giLyG+akQYTulFy8Cqi4Ue0QFiP0iJKS//I9h9yce1A01+p
Nc1JEFylcea+vZ5E7qK+4K7EQU/Z1R+voG+65KImh3sGyYzpmpaGWo1XLaQxCgZHKuRjKKShSnYF
jpMeluFkQGDpHwqKJaVE80t8nrVseCklXC7yW6MKfxQGJ8WT+CTCFKxh/foeR6ZMQtVrOhfT+EAi
KrnjNRL4Uuo/b9enbLPM8l9kHSDHfWxwVKXKUktBGdM6gsFxjAbtJYd/SkBR9tyLhMJcpRYKZcHe
sS4sdtuZopeur5E2dPc7QOXrW9Y5BszoDW4AqoF8tA07Bny3r538nIWpjVMxr7hQArVjD90HYseM
OmPRKlbp0QQnbXmLXzCFX1UX6rd63qvy3BUoXMMNCPMd73T6BiAKDrbMpAHK3mlZ4ZlvRqBlAuT+
0XkzgHLmy3PdyL6wCuu1juadOKqo8nTqZ+XuGhmyxkYrRmArXUoLXvHccXfHsd1+Lm1u194oF8pU
VUCjd/T0EIz2oUwJIO82E0Xd9HjcknqHZiddrkM+mdc+74lXU24uI1IbWcak3AWIJBpiF9vLuKlI
1010KrWxkSASnsrtcGLG8s5Te7J7A/kfOBBfIM0pMvwmDQuv+KNi/4PHCzEcm9VGIDaGPBeYZ7UB
iRo0akKwIV6oFfY/6cEMtnYt9hEQbnRdnbEUlRCb7LYySsjxllDueI7U5fqgClGbBPqmg8cIFmkF
KJaeiN2k1XuzL/G0qrjBWqLStalphiwpVgq3HRfUUOpxH5uiu8CoayEbChMhB2VCk/1BO6KPCat9
FV5pJe/gkSyCHWpMLxO12mJ+pDavwHhCK26vHwTNKxKFn9ol4ju2U5GpVIy2AS7L/rNBtsCNKPeO
KUAQ5XJ0IPMR/RD4i/KYSM/WBfUw6E1NxZSMkDUcYdhCIuajJLuy0riODfHKl9aK5mIFmCyBZzRY
/JOObvHfHS93S7Bq38ThsSHOrxE2XjSnELlwBcokzwHBcc6pnB5KnjrhMiNSdQbCtTAQvu1UJO1Y
coYnPx9iBuYPcsmo9EUz/M4/p5NRzTrOWvltONYozIi8aYuq1/GhkPy2RcbIPCfyqB9eZD2u4Fh5
UuDMfqWE3yey1nSXGu4iSJnwmRNp8VuR3klKKmN+u8ZLhgspBhm3jK/7xNVWHHJNvAs4rE4yMaxk
8PaNpxgLv9dDHAod9kYNT77fiE+79p7g88xP95WCWSIJmB2c2DIJM6G0Sqm+iuviNI/w2XDF1tk1
SVg0R7GhJqBPldg5EgG6ym+qNvYLIa4DRgHZo0HxlS5Q5CqnCPVl+40wBi2ZHMlhaZNHjZiPlYtm
DvbwgqKiQPLgAHU9UcX71LHNRU5S6821cF8CqVuzPHHTdIAcbBP9b4bVAybhWNVaOckhUYirOWNC
rsNiAqFMtwohNPFWAPivGIGYwJ8Ha6EL3p6ChHZLx+hXVp7Ka4aYjZXp7St4RfB/8Dycodw9ryvn
Umsx7Ffg6AdxWzjQr6xngihnNMfeOc0AKACEMzUMibrp+mytOCGZkUUa5EDqlFB7noeg6YyX20e3
ndA3w+2pt7qxK//0jHCOHEvTxNG1e1Db2Wai5AI0G39Yr0m/HBZhGm6fBbt8dzn/aEeNXDRzk5E1
0rQCTzoJ0Dkm92k4Z3IRwxvYKB481Lmck8OlFUMGigSSFq2+hTAUhNXlZ+pVnCf5m16WSo3c5IyM
l1dvyPIF6LSIzWSKHl9Qw9Lz7uAHOa/Kyyo3wb8vtIhkQRgwkst/Wys4swkuE/APEcsmr7/l8kwD
KY2jjma/RhrXlx7Y3pUgU142A0ypHJTYvZHXF1EM82sBhWosl3UrDx0GceLlCjJJAdhMHohPr1la
nmmMHDrrA/eNh5BATJ540totWvy4I4YWW2V52Vwbw/YbytTXhKIokE91PgUO5za2hqLRDkM1ywI0
cDAu2+XecwgcALzPlLILRK+T2v648vdAgq4J1AQzjzmuR3PjZW7h5yKAtPYnkWVs84kIzZ8pje2A
Yw4sMpqYStve3Ksh6rRe96GqExEMuqv2wK8GFiarhUyascqnG5aBgcFjeDNdquz/iXqAnmJg2mIX
Y4m/Yv1qfDbrJyUNkvUlSe1u0+rZHYSwOc5KCN176ImdXOuzIJCHp8gr37KDW5QfeEcZ/LeDX7qS
uNkvm3PlbIoC3cMr4AEJNFdUzspsdCCEYbWf4A5jrZOZw8Chg8pH9gygw1ttCxTa0R5XWXHxHYFb
Ue8ZKZN8NXe1Tzp/tmW6A1x5pJ4oZe5SgvBA7thQjrDoDTX/hk/SGLahBUQuk8jwXM+YJ26fWojq
DMwfAUmzF60fnxpTYz7S31mdnO763yHfDkCM1+FqzBH3RH0790d4uOPjJSQdHbBB6HhYiDgOeKWA
BW5mWyLOZNKSV/cTQWEP/bPEtTNPTVrVSMJmTTmZ3mbpLYx6yOmXq8X6s0fmNMIDRqyqJuTp4cgw
cwIEdPGtlNKpCgTrPFY0Lgb+Ri9w3MDq9f6NJ/cwwZ8hug8BXmslyeTaogTauCAZbf0iu7fAK2n6
k5+ABrQRJFsIAZIt4VnQG4fA7hOlUFFNEh3c5cvTz6M3/Nzt2fWl8hFmJy6x0p10iNG/sQ3ICs7f
IX+/jMtA+Feg/7OsKyTa7u1yPgrSBTnq2E8YtK92lVTqg1KlRH3pT8T0Xov9dxJsniR3GStx8sOb
2TWEw4brdFHD2wiU8CTRWmW7YpOdjtqZkmb5Az8X0MhrvjCt8Vft45Q/Xny3D0pdNZcLRP6uXLxW
7zxQx0y+bxCBV5dL5DGeP0oRYAdFxntyzQwUqZ13Sd7WA7fRepAcALh5MP3IbEF0JV9aXXCQycFY
uCNhNfIHzpLCJoUmVhuoiBctUzLrrSBa5IPuYt84zGO8Pr/Lf+SkkbBWVjLdKv09ry20bbkrJ2Bm
Oh61F5g/Dxobsg/YBGf3qYp6AJ2pryQKqzxwuH9ESMFWJNwmqpMjq6HoxthBsuWIaZUBzNTGtj6C
/w0z/6UItCumBXSp4tXJ/pRncN2JFxwIM8D6UJKrDsMU7597oQ26+pn1q8aiXvkOUliqRY7Dga9i
OcfOvOUlh9xNgJ+dpXjuQRV4kcIwBgZyP3Og4ugJrry6x3OJgA08y/OtUXGZ2LjcXyaYRKNO5UDT
BOQ5r4K/NNADM54LgHq69w5ae/kxw8N182a6laSH4RNr52+1wjsCzv7jp+g0pEa2VljYD1cTvYA5
r6UTqjE6YXXYf2epB7CgscHGXNPkYbRRns9ND1S8P7bg+C++1PnISub9DGrY9B/7bt/6A8gkWgFc
vgE+dxFMNEUDgOIGAOiW4kl/8msDvcxvYKcjUlNZw+o5dWxfWyb/ongs6jIGma0Li8rAz02QvRZ1
yNi9QeC5TpMc/xGT6jAaeC/0bdTb6ahnGvUTAwzj9RfwRzDrcDIawDluwDANcX59cii/AnumSUR6
mPZnSxRWUQ978AmwDss3ca8PtzGJtACkSvO9SUJrqcInpidMRG9yZMlVmhW24HKmtwuS/iv64wbZ
J9rcmhJLu9Dt6riJ9kEvACQtmqbGq/LdXMEDQCX2+qruVoPbSLGPvgNysqGvJWyRXbkbbqe5kNAt
7aZvsO6DIcsTyYTvuxROWhz1YUmsVBIvYRNZXTkX1Bo2wcapqVmbLFXFMAPPy21o266Eo56wEbLw
o0YB5dE54M37MKvoOsRA6yk9cKQ0FkTa3DQ+0y4qPGOVSFX9WurQ5gfGgP3PbMOg3Ayv+0i8EgAV
YX+8xdasGERiMFsx1dGSvT7p6RtiDVKkoAEqyDugHy8auN1HF/NsdFj6iHr7xwOMQJh5Zbj85pyJ
4wUgl7/T1OgyioXG2vc0BdYraSEXtjWDip54MZw3d8uG/0zv10bME+30qO5p2QLGZgR+xNSV2z/p
+FO5cKMYtRuTvkvqTN1XtlkOnru72gNrNIu2fboQHyBuyzn5akmEmcBCOFp0xTnwm5k+q3SoYDbD
1NhvhcBjZR12U4+PRoDD/Iwis4iYDj1/AO/rcSeWKAQZCgY53nZwXZfnKBf223/kqMx+VKNwOJaT
nq+I7F/QJ6mcGszuqgddpYjPUrWHbtqaYjIasXp+Kd7oI1sbTWnO/WbLXZEO4TQIqRK7B5VIS6yB
txlw8RN73fNr5l2CMZX0NhQU/ll0UYZ4s8a+WYeB/p4GkQZdwH7DjZ7xqoaZ+s5Jhzoun+/21VyX
5B7LK0Mi5IQKw32s7JRld0Bc3GLEwdaOWca1vqXBPI/sRkFUeSPmbcFS5yZ22boa+pvYUQ6w4Ojh
xLYVKz4nsZW/2eQUC4BviWgGhdnDZ5zvCV73C3teXM/e2JPqs2jY1nt2qt4jlm2QZbXF9Ee5Cu35
45yXzz9+8LAdoRTHjIgatXpDJTv6QHCytj6MtHjfuaGvWgJyQiDZ7Y3wCftuMGE5QB2D6a34USOK
VAMzGYK8p4Yhj7z59U3mY4riET+WhJsk5ggDepIW2baqp1UPlGV/9RvbsEhvfz5gpfru1RzTWi15
pFe4e8z45R04uXQI05HA+qu8NJ8KJwsTt9NivGi257iQXfCDMdOufmegk01IZt5GrnszE6bFlDkD
7fp6d4v1NF/bihzGuMJfSvdcQ0A36ko+9Id46hZsDNVFfVXoFEtz1hknlphntArGww5mJg8NSwLX
ioQ6BFiamHRYwsYo/U7p3ieeUGesCZOV7TuO7451tQMF1vReHyaMxkaYhml12fPKrUswbNZTHoMT
aJ2PyvZWLTnlsVpvQ0Z8asrWcf3wBuY5OljA+MqcImmgQN/QtgNgBZk/QXfhB6/jO8gl5oK5d3vB
69QjIMfFqbT0frQb34xbDXUGKDIA8qX/u3VE0LR52PVDAxBPQaWOJcqLVa7A+vi5M7Lc0MdoliBb
mTtOtQ1EOGhphawPjmQ6HWvWYvCNVY6WsFjzH3LtMIQ+iV52DF7opnRbT6t4fPRJKE23en4/BMXj
pEzT7ObFzEIW9jVVPWV12EX17DkmNqB6n2NIga3s+b5M0cctPvKfSLecv9cXDdP0wq9t2NEES7fY
/Vn+ZzD19pmu/uLQmdR88IoCX7SLY24lyTtIN0nviECvWEPG6xHHAYo1l4tNXqhnD/ZWYP1/I5IE
5UIJbiUV6CrtZWH1jmm2XwN7bFE3HrmcN6yF2YElNa/aOYa6tJIw7ZHrpqjs0LYu+9ij01lGgAPU
dSDkqFXlbJZCb0jtT+KyF00ZdLO/yOgVNqjlGVQ2CRnN7VbI9Ul0Mu/+TkOlpBkOxc6ZcV4BMhoZ
BEC6bWOiswqdQ2xYb8iN2hgFIPLatYEKTaq0+WYPg+P9pbiaGqVIxcqgXd15gLpcTmJaO0zNo+L+
083tKc5ojgq5V4eX033wukWL1f2iRHJPdhraKuKLfJHj9j7+ki1QWTzHWxKR4epdmNWRrDQjArto
JiLnTRikDpmhLFHCujwk9fo2THMxlRZmuhVWue8VecKP/gQLMf+mGIToT3H9CDUb6ZNpSibeg3Eq
I38gS6h6MrK4sLV1BeXjSiav+wsI8JlVgZFC75sBtA34P9AKR7LaQZBSBk1rf6UIGmNAQmrlZ8ID
Pw9CRdDmc4qmkLOIlM2L3Kz+DpbsSdfE6h8X7FLav5a1dk6fTUgoypE5uZD9pQjOZ6d4n+fIc3jE
YFxGEVVGwMaqudtvXcLEaZBmI8CuDExSBv+bP2YRcFR0g4x3NbhvV8AC3b0ZJ1yKFfZ79Tj8Cpgr
TNDxD7ws1yuJAr3+1YOaERGjGIw4+42rHRQT9eDO45HaZkGZHBKdUBaxeEPH1aBWfZK7GXO8sqph
06f6uVn8cgEbuNXfJbznV14StZHCNS5sca6I5GOQULiQUVUivz8mKynukvlYyMbaBMzpE0e4N6u7
dT/UhhZ57iW69pocG+FbpHdfGjNo8oZ9e2tk5MavWy/1iu/aTLvPZRD01LzZevvf4pdQJvSHWmZw
zySz8EONyd0fOfhY+IK1K6+FUgRl7kHk+oorHis9mw9s9GCBl/rnbHkM4L4gC8HTvF/UFHLq2nED
4QPTbRsPbY8iefmJaArkYthxbP1rDlA39eCWpoBplRC6sK8Q/p4UntttVYo6C8G7JMNweXcV+bHg
u4Vo0ccno2U4FP1FrDFkEwHXgna4fu1wcKnAefjfnrRlPQ3wBD7phJzjO/9bsFEIRAFqeSrAzSvG
MVFEyP/2K0qsdc9U+bU+CdelfArON1JADnGKc8ViiHwCBvIozMc6Z4dWTqDRabKDuJipOmNHuB/k
UWcHwGVx20LxV83u2dkDYjKjtyDdDrmLIquhr7gQ3E2L3Eht+kDo6WQ0QEFVHto2VteJ2/j0WNxA
WaBJFKjNTaU/FeHpxIS+C4H7+9Bn2MXKNpYcQNIvrflPXrAULqs6EuwfAUZqb8pWTEJf9l19UQRu
3pP7790ANkW7nEdzjcMVd3MubeyL2vsyM93oTqXYrVLLYrdCTs1H8s/s95xfS5xxcGGmWakeMOKJ
7d60zcniWgEnFKIMSBZtrtCGfNlLhq15L2KO4NnUCCstzus4ZRBfWVCCCeRtYNzbLvksz28Hy5i2
Mv+XAlh1nbDeUPXGrHvxBcZ2miFEzhFraQAKjx+NZEUHBfPbuDgbZN31j/LMsKmi925ZbtZUIkWM
7xNdtc3k42AzbqFMIDaFaQ2CfRGVdrM1Hr974ALewXdSQz+oYXa/xv0S8X+tj/j3WluCXB+CsAaG
kzg8z8xgWMDS+izGTSJ1WfYCFCnFGjIRMKmLkO11LqbC+3LitLU4ZkSRFPhNlsXpbRxliluxNli7
0g3v8P0y6aWJEUSwUtn1t4gkum1JB128YLfRdzGyohpqEjbChzVvDctl+ggcMBc0OgtIX5zmZAta
NSNNZPR8H1n0KagTvMc+4dqdKVfnezO9AMmvducRqtdiVpoBnnTpbAo/QhooEF/EAx/nmyj0abJA
CHXMyT4HUVLrqtQtzBr6gw0SD7p0+5HmNfNkVBt6wb2wF9xig4LPtU9Pzgy+IHBmgiFpAntTsMf2
TJy8+ygAA6Q+KO93/lqD2Z+6ElOijm2k/0WjozzMKxX6oLerO5VHlt+qmV4R4swQau5B9Q68bang
PSF1LLcxhLql6DW1R7VLVH5Ja48t+hfTUewNMEzo4ye1Qk5U+WMCK0BxDlAS6c2s3BtJpvQY5E86
RiQzfok+6eHsgUs7FO1NhJSCLetksRe/mtBtb51CL8zBx1w1J4ymI47rvnfGR953ZUS/l5+0Hzrk
w+bYZX0ms4p0Z92lI6dsD49j3Gv6c/H89HddyDfG/MUgpv27baZs97LIXCrSPAB3QM/i083M9Ojn
mK3ATM1il1tkPelIJtjI/5esXW0wT1rZd2BES3CYjcPmH/+uzD0et6GMiFGMv4pys+Ja+EaSnoQt
Ac7wFscrqevfDhGH51M8e41J4AIckuUYjhFoc+amDcC8STXRgw9kkB6wwBSm2ijRGrqYY7rBvV5L
PuS3WH035Nl2Fa5lw5RJE7ETtpiLllt1w1WNESnSWcf9opurM9Lae9iKn2ic2OShXoWKQdhS85k+
wttrCqPyMmu6QivgOm4eV3jhSVBoriZSxKEjs2s84j6K2aPZYWspgRbza0sD7p3g+SZI0OaSyMjN
enhr+5UtO5w5bZRWbU8TCmkbK6vj9rjex8AnR2OKX5r6PC1D1KycSLcq8EEU2K7ZsOOtzph+AOAz
8HaqguFFxPFqtk+P3oOPd9bdj/10ppusk1ueLdK5+F48szchS+o1hhMcea5Totu/aJFCpr/rzx44
7+Z1PpRRS7udVyzWUx+QQkLQAtLyB8vL2AKiF2TZ9PtmRUQDSD9jNX7tHIFY7ZxAMyTLH+3bPjw8
x8kGs7SXDMCbr6ASV/MlOTgjnE+7JKALfzcpQoRPaBf8S1ZzqGuUn6C7Rl8znuKJUeBzIJu0xCT1
06d2GTI0gZBLQ5Rd7NzoYH1h886cMPc26Zi4J5C/evDG4wW9hqYGhtM5IHdcquegCF8AiY7i5jSD
R7WiEGBfhfViioLvQj3Q1rMj+YSlpghUWkt5nSKG8XSgVjBaNZJW5+ZMVq4V+Z+bPM/UPylPPvU9
2jo0Ew1TtxyDjyu9NNI6beWm5gaUj569qWE2Crua5fWM1nw73dNNM835WSYSkDGqBIjtC5bs9qT3
7+LpiymWNJ3tHzZjp7+kiyFhsExyZbhtMeal0lkFVpO8Kf/txmf0l92pQO4W19KiLphkKKnj4CAs
XCUNdQLk0Z9ST7iOUUMxq4WdhJvE9iZeJY/3z9hBUtWxYz3182ROIue5LDQ1R+2I3cwFKDexu35r
4tyaRlR9CQ4I6qCvFNBZW7t8CwHG91Z5x/o9TTxpDSEXxG9IB2HJ66xmzuiUdmw7Mto+XdZa1zMk
0Zu1Jf9PM3Uhh5Ntye1e4MSx4DGXkrSPVrBHeJwXitziVG7B0HbTIMsLatdpSo+6y+Yg7qlixZsp
H8YoRSivFXBvfxFthOTTA/X1toBInh1PwUVb3X4q911B0YAUwU3AfqQLhaeYpF2VpEOE8RpzjIhy
1pm4sFdH9hxZ5rJ7p3k0uuih2ru/u7nsSqHpIwoRoetUpPJ9ikoVEB+r9DIlacgi4I0GS8wcYk0d
KZ56EAmbKCpfUcBltxZ2gA83ANEVDnShjwmbUTshV0fjoJf1AJ7TUh6Jk4tGjfqMj52+KAcyta3h
Tv73ohdnDDJcYFPNMLLD4/WWR/cfiWVjXppvAEF+7QZZK3YGUtMyEB7S1ncjEQ8F6IjU4FlQjr7a
aNqfprB4+oGbhL6Jzf4u2eNZK2e1hTZDIs5LaXItRkIowFzt9YorVPkjBpayzpeKrmNl254A29/h
Sk4KS5Q0PMFQ/11+rzqq/VkXCreUeVP7AsvqovEcFBF9mpWamShol5hTvpJzrLvItEWlaywMk6We
aOmjtWqvkZUHL2D/J/mwf4KEZq8Y0ydY+dQXuDA0oMT//Wr41ZRZei7rFjOJVdyFgL6sxdvzYuBc
YZslIBndhdQnuCsoa9Z7vWGL8YdBdN5XDm++i7Wf87OPuotNcM+/gh3UPZaNSpf5GQhkJOBj8ohw
/sBhZ26bP2Nr3ZvneW4JnzWJtUaQWj0AyvMQOFlCvwe8rXX3Nja+0TCWyZ6o/CVOkVDxwIqS2QDG
10/VjlZFSWFUr3+JwUh8Op9dbkgc6j/lrTcX3UMFX9+Bw8VnSCA2P+SnGyY84Zjb9Bxmaj+qxXG2
qU6bszlH01nWB8mdGrutTpS9wkGEZ+I5OpfnEP9/8n8ojq8gybs5mHWgtsANX6BbDUDIxYbsCnCT
RqhyRtwlGWDk8F1foKkey3gKvrwFOOs4+RB63ajOAZEOIfup6VtZkm6+SKbRqhEKnwU91UmRg0WS
WqtsLUb5hXWq62yC9ap71o4RZAm90txujoJQTK9sfJzgpKkzbkKqvErS0chUx0xSAp9pOXCShkPX
jIu2SCMUzUez3gr51ccK2TzLQEedZfcH4E+EVE8XbCikOGJjyNF3HKUn7ZmXaSrfTL75Ojf1XfxI
coeoxc/VtEFX5ejK9gCPsBsyzzwj+7AqYQUq//jYiJ5EVDR5As0U6BiIV1iQPzkWVWol4Aeg+VB6
ZSAl4NqqjtxYJWgj1n+DzC4KOhskb/kyFd4TqxzqpLj8J1766XqH26pzejRwQvONQA0w/oWolkg4
H8eZVjX59wAXL8DABVebrNDkuL/8Fb0rklBstDx1TH7IDkstlrRLOKEYNx1bcjfEd2egzOztJO/O
DSO38hh3/CG8EBQo39Rr0gF2NfKmyLwqyGOqHtZr1e3PCucLOSjcXW6w7m8pxWVkCwVuTtQhWbBj
7E/Nz5xqJqz44zJdjRL2VJOuiJEK2NeV+wUfMaYfzV48dQS743YsZYK3IqMc7ufV3lJZcUBje9Ov
6B3i/+9Eroye0iVMDVf4t1lutTNUUQF9rmI1k9aECCtnrOcg9s55C6Aec3I8Orklsq6TQGbc/rxi
oTGyTSAt6UFdwRVuSn4edAX6FH9u3wFF0WfLpmC+zeCpPtQl8ImT9z+/60JgrhfZYChowyUxRQAI
MaDQHJz+qMGu/N7mt7xiWVSokVSbdD/ev16EQ3gqTavNpWd9nAs4zOxVdQozHetJM344Dt/aAjKu
5GT0pcQSpxrnukFQfhlhFCj076WKFsD3nbQmIhys/QkaTTqmpTfBXBR7B/DQouegeA11YNQezYg5
hRcpsx7Ym97mAsSu2LO0h0elBHvPk01cGSl3tHEC54q9midh7VM5u5MNxVCI11eYzO89LHMa8rYz
nWtdc7ZLfDKDmgtQv9Rud91SW8UZHrdrR5+rmlOvKGLuFjEM9Jc92H21W+1X7uvcsAKwU+8mfT+G
wyLvRiU8YrJ+v74x2JCAqjnGvXmfSevOhP3bKGLZil0ObMQbQExj8+RlISbmChH9a9hi56154uO/
DTIw4BCaikizm0yu+ArnbfxDbSEVUp1Zy4D8rIeSDB2CfO0ROS8MwAJoCa+xLZxYPS97PFZPd0Em
ZyGCbF9e8jsevFrtm7cl2u7UniGcnVeUNqdPHRL+XAppn0rfO/a28Q9T/trBcTrofcduyy8lg+X4
uMvlPGaxMNfgYH/OLZoNgqbJkK34jLGjJ7oxYf8RXbWSzH3sJDpBhnccGQNbwquXBIfqF9vScSUJ
iGnAqhrhn6ALKZ02jYn+7ZsmUo9vHGwUc1ge99w/LuIsaCQukI4oakHdwN5A0C2ifpODXjmoIME1
hPeK15CZbLznLHYp3MFNm3cN8OCH8Y5+hfnVq3efZVRRICgCOf3dhzauvTnqV3saNo9zxDDCXnKg
TRYt4NHslaDa0iv00AEqgjY9vWjps+LO+d9XLYXEehDH4BQeahSQjB/DXwb21jsz8mWpAM8r5Y+H
UbjoGUels1rAa6UdKB/2mSHVbfK0y7drp8U2/senuabGS3Yx8TtJfLzFON6QrXIba1POnHeoSfLQ
yPsf2Mcfv+iYB/+o1absLob/OIDwO7lG/6o3vp8Im9wKvxpcY9hbYm+LDabOD6ePa4epb+k0Tw+Q
CDCGaPhsLosIhJlEO7F8v+TMUjfmxk259VNSjqtR7l3DDkml1h2CVBp0Rxgu+x/dIbtlrL39s6i8
2VzW0nFbNXTnsFTOAfM8MS1Dvf2mMQM6LXzl/5LcZYhiNdiEIZCI0PQImuESNlNt7VwGXWlcqpS3
z6XsIj7/rz6fTHutUMIAt//4pdJLID558try5EMy9PxKbyk7ZmpH6tr6DJqRRkho83H2nNbK6D0T
NNBgJ3hin2cJwjafKFVi+6flZksBwQC6DaC52D2Ip3rPuGLKzpckpDuN40gc0iznPPc2JcAL/uxc
R88uHpcsHm3CKJi39hjE3JeP2DsBmSCYPb7wYz8LSwxWIbo53ToTYrZVEzKIJfUq38gevvuYB4jE
lh5+y//sjZ8N4ncU+bUnoxaMX07BqZ5QpOK6vgt/EEH33kWST2oPcBwWbqu4AG2yNa/RRJxcGdJc
ATjbbU8qtshL9xO1HnlMXuAkg7vX72UagtAJ5Cqp0d/XWApatTSS/ZTAnaATP1HyWHo2MYRera99
97kZHoLbw1YWRcqwCABu5I8DKYWxDWU24frMgt2Cmb4ZeMPOzJsYtxFst0FuR+m7VznyTPkwwKPX
Sd1VxnIGKlzt9kgCMPz8Vh5ChmXpTxitH451mOmNJq7MzNsQI6pI5yrOUmLiCY15tuT2plrv+xeA
yxk3EaTqdNA+OuHrW8CL7Ox/94jD4QFKn1/DPxBt2k7Jnej2kInihuoaU15OKCzB1DspcxG6HCj2
9DRGDkDrt4Jfc/LtOYRrip+S8ZJJuavtuH2za0er+vnwiaSOi/MlLdbtsLijG2JainFXT88JtqdD
QWXXseVmHoMj/p1kpZCjXzmZYthUhGEgDnFuhKdwnF2BBZc2aVzKp/Bpv9Ez5QPcr7OuJ9ekwp25
/0hfPvZLGUtYiNLxm5D3VxyuyqJhcn2cj6YDFNME+712G+EA9MtpA5sTtY4RkhxUkilSOIvsHn59
CK4w8iBf9NuXR1pj60cG0KDE4/LGiYXgxxNQ9+TprU6OJgYVooHUbNpYe4pdBsWJ/IThqT/zKlKA
RcJdStTV8+Wd6oifMeDzbbB4kE2HEFF4Ov0mj0/CxrB4esurX/K7bSByXm+/NNb+pQfeQpLRjAVU
y6DmQr8+ZMoCra1FZpBiMLNsp3cgEamYZbDKJEcrcvUuf6DmzEkB88pe+uOTzyVhsW7B9UkZ+htg
2m537vFyPCcAxeTp9Nr36qaWMFDZwZ25EitRcLJBVNBPiEQY/834WVHY+eRus4GjH8tDNo6lKIXT
iGSo5rm8nMS9cn2JyELwpOJz2IrW4320FP30Hj1hJOXFQZz+j8mJfYKNZvPmjIvzhRnQQvNgV4yP
da8BPv7BJGuZcmxEdeQa0E8Pgbg1KrVYlZMgkQX5ulcLL0b56k32acDN7qS05PRjqFttzQQD3j7W
WoBxueHKX10erIYyLEXMFwW3t6eTIz/b+Zdmgrd4ZTBBWY6Unuo2qsnDlpdRnNk/JCyecTntB1NB
SYqwk5TK3xjjp+wZs6neGac0FAxRgsVDMsqEgXynKz1c8ATJZy3skd3YLwMMBVg8IBvY7HKFnPCL
57rHrtCJEfrwKcv3eoNjf+1Os0bYSYaCQtskXDW/2j1fgsDxVidRZcB49/ti7TqGkzPxuPogcC9L
ssinPVP0qugpnaeRVsNohBIv81UbttjvY3e7LRjub7XzK28nW9+Mxcq1+mFlbmXGHVk3/jbAJU+s
coBrtC3HjME7xhyvGgTp4h7mxqGaIwdHtykwCq3U0TLgg9k/kOJvkkswkfquil+9oYgCSld1kYje
JeFY+jyv5YCLKgHcXF9xBGXahDdQYZYobY2/VfHm6IlkSL7thseEMiU6Rhvl7Lvcqcpwy2gIH4gl
nAi5cfsBMJ30jMFGEdghLpIIj/ghJRK7iX5SHpC+AoHLsR7rxMV0pxWhC7zdLIM3ugbX85I5Nbnq
fEOoL0s0UNb/k2cRifT+jETb5TBZTj4VVXhpg+cHBvEBs2jFdxfbBD1jJxWO1PisOcgzb47Zvbpw
tTZckd2OfOxu2tt4jIAHbel+nbCbR43Ur37N8H+fXrDth0tAzD8Ok0g6ImGcu34fwzU36NFZVues
SH18B5t+lg1skpBz+d1brvmGW/8ZD1h9REdTwv2iYVUx6PNQskAsAUxSpS9Ywsr0yDpRZIWq36L5
Q4c3r574y03ogD7ISBs6M2yOYrdmcXklrblVk62spju9ycRcmtng+u9qHaAxFYdqYKGIlCEJX7cC
AgaVs5QlWw+cQNovlU0rZdKEHKNJjT/VkD3+gjOEDi7RtmWWepc8MlPTMQsM2ln4qzTz3mCIgKIS
ITvBXOv3v5CzxOC2kzg+civMSGitJsIWjLXX/7VYdD9GrXHcKqFZ264rPhbT9UJ03IP2KFkOdKet
yjhVnScOJPXAUvhRiryP6cXW2ygJjplGvbTTJARiPQWL4jTW+7wHFYIcl9TDR3J6MV5n5DWq+kue
nTtIzUHAvvBfxLi4U97+rrjqc1uYbOnhSyUMDvSVwO3gTbQMWtASvUI4TTun+rrGVy7hbPbXQ9RK
RntC5NXSVJw9/Sc3//UARcL8P9d1Bv49YDfjBbHBTwSUERT2XPyTYhJbEYAcA3F3l5wQMigGR4ZI
C1PtCWQamCD2Ybq9nRpn64J52Yy6GBRdgqIA2D1i2fAcMnc26hOUMhcif+X+VlXcU3+7Dv/Uqm4z
PCuwSdM24nhZ6kwyXU9JbZ1TpjNIqXIH3h6+RguzzH7sRbvFInyDkKdhGSc+4f94F7k1tVMCMezu
TojFxydy3xCAaLFA/fg4CKDQn0Luyi+3R53ipOFkmX4EzbUMSy9r37XlKpHCmL2tQGj5oWi0C5RG
OUAPzkZxOxC4fymvbDheapy60+ixWBt0r3p42LLOENh65OjUiGvYmNwX0e6AFMsK8gEFTGmPetYK
zujnEjSWETAjAQncoSeLDUsBUsH8U5rlJ2z0gOlYtuWnnE6rGN4Hhk4IgL0fCFVZ08Gqovd/Fh9F
JDC/CTTL8euFPQ7FMIbouQz0GjCpsvH4gs7UVUfonHtKmQwZYsBM7GxocuS6LS5nF6ShUIEA6P9h
H982rX2bYaI55PW0PWKgEgzF1oExG9aIUH5BwGmw3jIwmz6KQspqKOuJalhB3w6PhQxVzqN9PJjc
1CUWPSVcRDCLK1gi4r0H4p+osBixQhQFLRLdlhl2YEKrhKsZvGwktxb9GxvdilTZSOvUyoi9e4ke
MZAVVBKNOsYg2jNhmzP17yY0v+Ff3+TW2tDHAkH9mjoSwjQPbImtpcLMOWJatyMkUCraHHnlzB8R
UyQhr7WxEenNmez4BMH8HG6cHXGXe/LjvTy7h4HAmNDc+YiNuf6D8QDlJzZ39PllcJ/aF3M00PsJ
kLjM2wZPrBwjZFIcSHax/FMuw+LRnH3VUhmIG2o7XMhiZRIIuZMI8qBh6drlLsmVH8o6I1H4rpo4
D8lpWndICKyVG9MR3OZPtSvoce13bfPA5GezYRJ9lE9OoMc+36PCPFjLWZftQfMqotZtDO50WLU7
M0L596sX9jxq69jYpj95iSJyY/T6xOabssVXSOHWXAlyrwgmMBHKedNUzlnhkDdRRa1Y4v//ACHT
PUa7RL6GpD9+noXgKEb3EqBjuwU7NzV9VoOm2dYUy5HJZhprhTIGVcfftWMYUaRK6osOoNcuODgQ
c8Oh1xLVx5/MSzAchAUo3sIyoICVGrweCiukm1HGuhiZxQ9qnmGqC/5+bLlxhWzJcd8RwBwNN9Ta
QyxI25saNTmKoNUScQmODOYTJnfEx73F9JW96KfifaRgvPO3ow4rAnGS726u3UgPN/WMtXhjJAmL
ghvoFRhTP7R9swftTkX1mQx/XmuBTinF4NnUOxdqzweYjPojcwEuNeTLQurXB7brXtgqqOKSTCsc
mq8wTNEJiojP7Ef402UyYvviEK4bu+ldDsr7TMAG3UVYvwO7doVIJjARe9PulLCnHMrNIiJ+pYe1
v3OZuPv/Cey6UKPHjI8KO09jlWVs7Mh3e4u6F4VWt2jYzSXeaMcscJyjJePSJz9B/Fu1NNBjTGdD
3eCfEx7gyJs02pp6UW5NyeGYGXzH88u1lce0pl+hHcpwnrGYEOaUbvqmR9df2/vUvO2l0W2rZvLj
zzrKjK7WjpdZM3MeHkRBTLKNY5KlHdCCecPtcWOVWJjp4Q5xaW1M/PmB8pXuiaWDU1Y00YTeRtZs
kHfljBYclYEuRlkNNHXHYU/vF3tmIxVs5ePK5t54t/Xa++sv3P5nZRG99toLoNRJp9rLOtCUkjqT
DVGk6iIciOk1hxMdR5AbsCjCdJaX19sz/uF5b/eagJOhJOHrC1Jh+HyS01b1lOSRX8vba1KU7OEX
mTUOkKU2FI4v1FROLQTjPqlLa/iWgTbOC2G0I0Z4M4+ZSg9j2YVGl7YfTnFf2aU5pru5KtmV399V
V0pDxXQ4f4/ZGCzaZHLlgX2d3CkQOZXxd1lDpoSH9apFCevhSCEbZ6me7v4T+y0cpeEvsvXAE1MF
+NQ0MVVn9JJDWwtBx+9Ilt/ssE4zXRtErD9ygzai5mSZb7hf4mK7TrLFDmGS8tBQDM4ZmVnYzSVY
NJoDxUx5CnsKJ3dh8jQtKuKoTIWoFlDEUubFeigBcVBnMaYZGXYTktxhsukFBGUkSc1oeF9PCk1a
zvj9XQNEWLeYq56ekZqc6te5stsqU1URDo1OCncIOXMRPL8lSD0DfHf6zyUkrTWyjIenH1Wetrla
2VbYRDz88QGruAC124InvfaC/p0lnIVsB6LNZ5pdVmDSg+rom84wKLaHoui/CrjRgWMH9twkeDWQ
e9nnzQ42NFeNUeCBKTXjb0WIKFw98LcbVXmDdr9csPV08CSxga8RiWDEQRuKwc2g977n9EU81evS
Sd+Qbrp2qbFh3Lkd3kxDUn6Ty+PpjWczsAHQOc9rh0HEa0Kvg6l6aBBN5AMniHGUUL7bbyfeBnAa
D0MQzuvO3Unvj/p4WhcOGC1aTUpGOCHneRTDpLTom7LryV8SXQ+CH/VOk1Ft22qby5+IzVWeMyQi
orbXNg6ybVthV6haG+WxNic+cP+tEGw32q5U62cluyC99OQXSfDJV8Y0hYwNcNB+MSQxCpcK1bSJ
c7SNnNtgPG+nWAqCuWixCfZu6+NLA8PqLUAvcdEtfHdkvV+oBRM6BP3fv9oMFBSSRXjmWg7yJKKZ
XzBSQhRvYUlY+G3T4l5z8MjqF8KF+fwLN/otG+P8yCchbzgcn0yaPt1pUQn8OFdCmzKJiR3mU0is
cTNFP84bLOzMGGP61iPTsB4CS11efQVZ234hKPovZr8tqH2Gq25PZh+8Dp696yceh7SkQu1gBV/c
gNdQP7zOECHCle3EObDlrzPseoJMKPG70i9m3+sCWO1dBas/VXhHxmJ1pZi+7wp3Og4h+Qt5sr1I
F+AltgFuQjy0vb39Im3NAfP8xPKC1yAALunVMR3B/rxBJe5UpmMuilwbbYA/do5Aarq5GKAawa9R
9T+8zFoQun8uZ5ewFYXwnh/eoPIjIb8/Ixtm0sIzQau37KrEdmK48lDOJCpCpZIZs6Jv8oREKWzn
xJ6Xw0YJGoLmKwclUmCxOt7KwA+aLYXlHZMczocpobIXrXqcpdu60K+ghecT1V5G+AkmmCH+QGZ1
JGboi55z13egec62gihE/yOrKv9Co2o9OUljlrOLOmPAaWAVf3gFtbskHW6cCJtO/ISNGuTfQWPN
gsxO/DZ/lxLZMCVtjPis1TMr5pfLLGnJwzVkz5MkUOnDQyfi5FuYKL7F5usqLkWHP09BFC42IA0x
838XIOZkB6uAFkUTt8zsIa067csxxG1itrqJ5n8YLZE2Qew+tqwqh7pf5IVA83Fi08v0FXx49gR+
8MGTMAQrvO91D8zpB3m/sMYi/BQGh1z4TKMj278pkJq/FOSTmQmInA4MNC0Am04TMED8XVcUpmBy
P29aNbGkikGAw/lj9zRSOHwvRQSC2icr3E/ZxNpBHK8J+wxHXg0xe3DLqLcIL0HhOW6Z+EvRvLnQ
gni5GP6IxF57LIChqq/DU7tmwM36d2kbaTCz5LpxnkQrebjiYre98+VDF979Dt/G/vDkRa9wUH8T
pWOidmqAuG9Moj8sDsjaCQF/vGLhgwZCFIhuSgTITF2VeDRof6RlexaWLMk4+WrUG67WKb1YD4Bb
tayDNZFOXzetTKNtCHYYzyVaiskAdcR7YjpCyGJY5FSQiwYeTMCI18SVi3YEEglANEPr/71jQGkL
RvNS0stgpn7BmMFejDdIln956PxCvm4XKi3mRd7dAXaEMPNgjrQg/VXhfitISey8Prd1LYCJpTy6
pJHc0qnueTLGmVtmzzKN/uBsTGpMPF0Rhg/xGR2mDzw+7AmOgNqqcvt1YMwFX1LGVSqVS0bUUKtq
lm2sI5N+xDTuzkgAJ5+BEy/fl2IihEPlVzU7kqhS0N/7SaQIkb94/frfQ9LEgOk4iphwnjh3Z0y7
AowoU4UqOsM4+XcaXIZNUJ31I1C86cPVs794+cCRUuNWUAIFDpod6i+82rr6qkCM9syIYQUJ+aLp
pL5BOimK9lPq+mZqet+ZY752B/1HKAUgx760SnHtZ4Y+6RfvAr4XGmqYSpUpAFFXzGVeCYCOSadm
InS4++wJSfU8XZQPR1HNqqFs1fWCbCAp22dNm8nhu020TOMy3yUarp0vtpMb62PFl5ALrQSMqzJF
XH9scZFBcaYp0MQ8VKXm/CSPP8Y9/364rmCWvFPRDy9twprIvXlTFRAvUqeFwN1Gz8BNM5e01ype
URNP8xS2T9NaqZP8MDuzZMlM6FczFbSwBJx+hmmBYTjKqi2WYRRQFnp691FpS1tGh4gl3C83O7ha
yAfBxyJSfUOA2bhxiyGZbW11rTjZG2a5JxUKNQNjxjVe/IkRTP9Q8IrLbDqOMgLCAlLcDkOtuo49
r97RkCouM9T6xGGdmH+w+Y+kESUXSCM8Y4L5xN45nmQY6H1ijjDbF2kQ8NuchWF3Eg1L4IUJTe43
CmU3uBO2Xw0kNZdFvnDPQ0Le05uBMqJh0qMDxxn98PrGfIFh9igFQE8qx2Hq/iXGTLKgGax0Nh2X
YHlkl4zIqnHCBAinFcuRF0M7jewTqlR3DzBsCk4sV+6c188sRkzZIl6GbFqwhK+6DZW8S1Mc88Ts
VN2XML5HDsyv2zWQ6RC9SzW7FNpDNtPfD97vpjh7Pmt3grUonJi5y8Aik9r6bKQeuO/ILsoK9HYv
AT60Ye5TYAPCebE55s1vozaWua/r6FXO+YNncrL6k9UTniX69ilxLCnSxjuafWGuTKAWkosnR5U6
lwiCJSUFZ+Q8bBRGSMq5x1pMEUvwo5D/iJbOv3KEQqDljrzPrm7HsKv5oDnGFnxDIKGPZfe+K7Ym
SpP14ZLTBReUdpcrhGxn3eDScOjPTuwYJy3GhwjDtMYqRrdWzh7xNf6x9c6msXnJnF7RAl0sGV2q
uXtllRc+Gi/x6K+pqs3Nxa62KuMhF0vnu3a4BvejaFbG9x33bNuKa1nwzuU0tEdUdbxYG8L+EQgD
srUJW0sB7t+X7GYabimGTE5VxuEogT1msHk9NJoCxDC+HM7vtEPrFp3T1422//djWotyLeSoQrfb
ebSX+eNPmZK4Xvma9v9Yj8fYzDmop0t0KwaiCcsUZenQuIQoHIZVxXOwS/NnQrZvJ6WghEmhS+e5
HqPPHtn/WnV6BzzVdIAnvm0n2tEdCxKzLkk9JZ2/lqPPYvRuEJO3S95X/Zug4sa1CQK4xBfWOHX8
s0o7OH+1M0sIul8q6jXyv5IwTp8uA0SDSH37rt1s2QRrAHtevLoOOstRyX99ESkdzkjtedznWJAx
3ANzaxJYWjs1XKOCQ/CqHWSHHOG5soSdXsDpgMtX1pxzR0XiNMC3qL2jj2iRYZkgeoAHBTtOy6jS
tvsoKl6bIdadcwDrn+99zKPUdQOS33QadFE4+XkbwHjV1Qin89EHo+eeTDEPIXuHjhS8IKjTge69
VuJjUlZYSpCEcLZxKZY2wAOfhcSeB79vK0Sz8EXr0J/Rdl7eIRjzdDbz7quMslXsZAQ52X8GosEP
XCDm+0w2JqzC21vw+6+BqBb2envevrtg15mJ4FgV3+a86GfxsUQiYTU3pIh2SFwGWvzNM9T5ytoA
vcw4q8otMONHG6/MsqLaY+6Sjkl3r1Wn5GO1Mepr6+lgA8ODy395AzNpcnmgDTtzumFNYP26OIwy
xZjWqrsVRTeGFY7ssW1gO2DTQsXu3SxeWl3iNtt7+CeXJRpbIIpZ/YBw0wOTQHTiTJw8pmebPiRq
4tIISt+rT2bU1xbI5D7mHEmIYo+5nmjo1smWBZlKJdDr2LEUv8bLjrG+PTSl+RxqO0IGAEg8F6ni
XwUrk/rGq9T6Bw3RmYOHZVqiTS1xBeEf99eiUXp432EqCUUemr0mxhQTMEogp+U7HdD+h2+mgo3l
a01UtV2i6lXWBiIv81BssnT6UqRgcTP8Wqi/R7CUWnaD8IgRKCmORnXVI6HvWPhezxBB5BtRHJ86
oo/XZqZpP2TlUuhPQTsg7bf+Xh1CxDH5IT9maHRU/L9HqyJzi9EECRQNxgipQn1B7a9e26kl/+38
x9wtWD8fcnoumVFjKIwzpMmtb+TzwEk9ZWgFbWaDFzU7DaIRO8iup+zl5ZAbGs6kfR56FlGnBiVE
r2z7r1O8R/71rZe+2u8OTQyHlPgHJmU7xbDLbwoTJ8VRm4lUH6XUbxl6d1B2oLtVHizu2nhbJypF
HqIlP4cOaOMr5ApRW+pAIeBy+dZUSSI5l71LlBifAFimuursOj+senThJdDzIv3E0krMhDNOri8s
JSjfyCrQS5PRfZjuRrHRX1S5sY6I3yTYDIEXVM3O1n1IBHlJpbYtu6XASZZ6xoiPvJElVVyBczVq
7hLC/SwRlqUjqzJ1rIP1rjFU7aWVKblRdVCnhRySTHfk6SrJHZYzVZYDVq+b9o5sO5+7EgTSV87m
oWLQHwc6ZFD4U6PmgkeKdMs37xo0neDzpDHiMvXLeT6thHZCL+0cMF16DwsVoGxJJlzd/ty7T9BR
8U5MnlkvL4N5TOVl7Nm1ipptgUKysZ0RJ7a3bJoXPGyFPnD1prGZQcxq2ega5r00GNSnx/igIf34
sBoh9+eFrneFRTV32D/jFE8MoUeFdjTP2Tx1g2jLlL6Xr7KVDSXSWfpZN7y53U9wRoRzqpY94txE
yrMoTMrckkNo0FNK62HPRApM2vHisQ7SnJNcwlFlYXW7c5g/WJho/PGC++hIkGMzWd3z7NNdnX0O
+IX+1nylI/olpzhR/3EdqoQIKB1XRaKAnrswnn2TuYgzVfCwcXZhb3Mliz/L6sJmd4CxT/q30YQ3
0L0LYYEkClfYF8NO4KkGpFxSqz+uJfOwdJgDkcFFqKPfQSP4jS196XxuKdWXccY/e+FDf1nFE2r1
z9fsnDGhmUP9b841sikfWISPVn0E+R/p2HPw4IaiFtKian+FD0WaS318qlinboXuDhWwNqA6gY4Z
R8hdUDciZ1vLU9lFxc/4Bqds+VMQuAvXZlyTKFmPpNWabUnGOFMNqCku0ayOV5omyU4F/Dmlc/jr
gIaCyI85EQzWb+LAlpSXMjcS/nEe6t8dPG+L6DyusN7GcwJcEI5GsI7a+cXzdZBGJtfrULUeLo2S
vwiPmbeisrVWLBAnoGiQ/IIK2u2ODBjrFG+1WcrVYdlBpHrcjjTtwIlevcaakOXVYtNs0ThcaqE8
VCbwaiT8RLdsv+WWhzcnCQ/kOKYkzqmt6wbi29721JKgaiaGyynGcHqdhCZ97O2R+/Q0snOV1Z26
qIRzr8cYElLHhdZwTMv83HHvxE19TtVUsJ+X6vghWqldgxRd+EDd2F8VN3pY0IvvvVTkw8Q31ko8
T8loZJtSQDhoFk5tQ6xTRPg0Dx7XYUC5JTS3YUKgfqa+rk+Dx9ujHTDxAxJ5TOMcSq2s5nH40Yl5
kaXnDXHKZoCBYOaUAjhIICrgSprbpSsU4canzWeHA1fkSOUJD3sTjZSMA8TilXNZtagRqvB2Equ3
qNx6jAUl5jS487x0BcezfprU3np6pAv5l/dofbXVKChTGiQ2E1o1HQvOXEJjrGsCHSpx7HySxH/p
2JuLo1Z6eVspiiYPfxplXk6JKbnTjJGrbFPW3X4YAQVyQ5VF70ex/zN/4Vonlb/fjDycsgLzPK5H
r5gHyPVMsEO0EBAuL15M9oH6hXY0qqc6oOw0295Hgu732Rut4DXHNi6uJaWFyqDSMZMp4Q1G8rP+
SxTOkaDzb+XxK4N86QrWobKfBzvv/DBTaVAffgxLWjdbdGG905hLzSvxQ2hXTTH4Odlh9+Lla67j
d9wM3MQxdBmhafhCJTjfpVCn0qPgjkjdwz3VVICJ72bDaJlbWZM48IE0G1bP8b2tN8dHOZNM7Y57
+ojZe67QWs5KtT2/ZMxW1068n4TLG1L9djqtRTzMiQt5PX/5/ucpLZbVKo9rnQlBBhZzRxUpx+US
Ba0Ah3P9zoakmlXw/Hl2+RHUz9ipHiBZx7XZHhDsQSLZvFk2mDY1KXXtbBO6Xh2y3w6GM3IOjTd+
K993Yh7rh4lk+QRlxdK0ncBY6DGGJsKtgiIFy+LHzVlQfVgN9jHRQ10jcnodYsxZmt6/yO+t1X46
spJiWncN9LjxQk0IM+OfFPyF2pM7nsMvYImPCLnktpWqSQtpH+r+jBFJzfrTuLSWO6g4AP2k4qpL
+gp9qeEIx9JUHY01Bn+oqm8xZsIIFqQ7oa6JxjbVF0b5+JCE/aTXLMK61sxUHzPvOQcwuELMRTFs
1XeSRhNzUt0PPUAc62eVNnhEcCASqYNlpnWVVum6fDj18IPmpZ4cbR+z0x63xdo11XSZSnzfnZED
fVtCzS1tQV9A0vpZAjoUuDc7W8Um0mQdCcHekqmQiq6y+E+LmAwcWgwCgRmZwF5JIsTf6eWEOozZ
7wR/3SxV53UX8SNBtDjypP+HMwXB9KLkKRoQ9cWVPjdsXTWgg4fFRDjCMMbhvz+TmI+CzTDfy8ln
JHSD7M9tKBqVEZFRbB7YATeJmmRgnT+Wtl6DU9vn5cNev9Rd57p8QcPcHnQ1+AjPwD+iZajp8G+m
ijSAa7MgVljqJsy0fKTc0Y5uaQbgYDBqXdyytqNWudGFXZv/LsSzBwNWE8+fuK4O1RKJ+fNpqXUD
yRiAyXg0dARvu2XI0pXA1k6rHNs9pzmfUgpouLs3wWihcGLRnJHmackh4J0B91jKyQ2xvjkkv24l
LSboQSQhbe4NoCyrLjqAaYCc58e/x4N3txHoPiHicRxVXAK+GBvuxbLfmbsY3WGwOqJl56fnquwo
FaCVr4D/6lRLoy64QmLv1fmIm+chmfd/clVsuuspsgdXjypSRK1Vn21/HQYREasmrxEGe4Zu8bNq
ggKvF3n6qU28Kb4iqQr/HMpBEIw0Ob3B3yWB7xYQxurANRUaCVhH32WVniDTSjVXDi5ZAqi9uyXX
tKF8LwirCgYz5bJfU1bAg9ofxb9meJqvDWtn83XDgYss9h27Na6nwpiodqaw7yq5+hZRcjOLPFh1
ZkYrRln6SIa5sV/H5m3hnF9ri8t101+Fco0wHw7lz0ZSHlcYDiQYUdmV9WBBHjrli/9Oh2MYvbWT
D7kF7mx3e4DwfaF5AUNlhfrIW5ZanNxuyXS4oPVjn8lQAkCvH2ovKS91TnzD1jSZb/BLmfFcTs5u
VuwHy8QpbXxfNRczo0UEytXzCPyqpDOoVfc/ophE0BraPf9IFOSSMzYGi2GXPzgKp7mh8U43z4sS
W93ZMprBMr2OlCku5POgpCa7s9ccEx2r1IIa3aThK+z/rdRVxCkCGZjIgg5j0BnUMW0v8zAdR7hw
F07uzR54yTJTFoitISF56QjqCaK8i4aRV8bxHJkFQheV5Yg3ZPrv1SyUtyYjHXzP7Kfz+57OU1lD
FNgjlnW+dNja6EIehV8uomaA33xL51MLf9drqa9ydLu2yUMsRNysuOiM4j5lQm4U9tVlvV7aYfm1
RKzX/lr/B3zvdlhDgI4pmAJKidc5QQtsEc/UYs9d17yJwMIj2/j0ShIG7Hqd7un2Ce5xF0J7m1hs
7Lp8T4bbxVZ0+qfM8xajwprfjdGy0cUrDvbra7N6kH0BG1Jdn+YGZnyJcUhIdb3e+KKT8muy4FhU
yI2xwd3nILvoKAjNlTdQe5XvFmML8u8itdBSQ73HlV43FskTbl2EpCzbNhygXS7ltRPjZuySKjyo
FYxqkRCEUrvW81w2eklwNlgra5TZhl4k7HN2EVx9Nx2PENSbFyvfEaE6k0BXmItfPzm7iBRZlxGy
EGjtQ6VI2ZbahscHXtexTk6GWuJfc4qfmY5JBgvg6IekQHoQH3E0qk5ENkcWBrJ9NLxdZgu0IirP
NAFOg1figOIOjX2phpPsTEz7eBbzUqpgMRwhfY3WpGxT6kgUgeTVfZhVqZLFXH7rpxnfUYiQ/mr9
kGkOQLd9ISluptNnBsIP739D52h/5PqYs1+pNTRto2qTFe2lPMJpWyNAgRiPeznIZXB6G3V49Sc8
+XpoT1QM+Fxq82aLoGaGpljIw0OP3eXh6y8anJTdWkMo/PI+8PLDAtY8YldOQmrICEf/DEVjd+eh
sdWSFVitg8Z/RNolytGaS35hou9FduSWgUXF5trTmC+kj8Mc/kAceLgxwYuPDEz0V4AHZeErVOj8
rzcb3+T3MxNtQm4Hj05UgxZNQYo6TmMDfPH3ML+EUiYVDZTGKwG+LwZltCtvWgfM64NbifG1yGUE
TUaIbTjCLMvGO6hkr7+oYiHMYW4gSFcpvt+tpUOZatNgHp90tZnfu/XBmiz7PEIPpbYJ9j1mgpCV
fvrbqcMcdFWKDE8w+UP/j1Np3NJWlS0Z12edokHKyV98iIFpPYSFcjSrmKywaqFu6KM8uaGHeD6s
4I1clFBbIgsYaRPfma1oJGwe/yu/SN4iqPz/PW2hO3nKwu0CNIM/Ipn7+RQ9OI9iB/sw7HK1ExY1
aZtuXREXFYA9807NC2E33gD1CVGCZ4TIRjJ2LWTsUR5BX/c3Q3wW5seUkLgg8qpn2vW1G8vyy7qG
uZW2ejJtYF5l5KX8CTz47BwhXsCCTqTFsiU09faR57uoWFBdXAWx/B9xpRRbRB+P390m91+l/NXi
LrIJLly1lVYbQyMdYXuioAxxqhdEMg4mm8rSIAi9ZFWkGcUx+xk+X6i+oEevlkx4bnJ0ugPerpPP
xs+kyCCvSkv14dJ6dOPyf9HmsZjkbDknXGeZpJ3edZWdDHJE9ZIroYyzKO0uTbEaAmxGtoUWLBH5
LSw4SkRZ73UqssfTAS0hXTWe93G+qBhuEE7PNmlV48txZXMulOqrTOIGEGzgrYVyZL8+0Sagg/94
eHE/IGXtuc+JfNulQG+nl4SWDYvgK3Wgh71kkXjNLGdeoaXUEip/jZCHfcDW6E8Gq/YhomCwTSMO
/Ova++t45YChfaixHtRYOzpWaf+nF0iIwnRGzen8efSCg87oiwvceMyl/KWnFPa5uyUo8Bnqok4p
23hgbCkPwHYCWe2YDx3+rCqk29R53H4gCETR7kLSiskEUKRJsw2bAMI7VK3rfQhIxnmkYODdoq5J
bjwx/pxp7Ht+cG3oK7F4ua8wSwW2lhpBiKRstmqg42Y7LXpI2EbsFGCcveZsT5mwoG2Hzb/dXnsj
9CPfYVZlKhsleGzSlVavwcVgnnSEfMEBzp4jjOWJG+56uhqV2y0K+e6DVMVI1Yh03VP1zCAbanVc
6FrFbp69ZVXV+QW3zxL3PmXZ71jHu0rZs5lC0Gn2UQzOS+7N/mnMeDfIWCecrPxtvXkULADcC4T3
I1IcSpTkZsfBBuVZ2XTLYXUKokUI6mXywiJHezoyrogkeWeMpQkXHch8XOCvuOfyUJAYWbENrrg8
yoIEQt86SC4CM5KwOAkuoFXWu9FWQ7Zpc980XSP4DrgGOwkJ9y5c3/en6w0j2F7Ci8ufRJ/sG0Fv
tc3H9wzJgr1qfjTp8oaGP9DN06YhVqmLLvUhrPe5adVXnpPxkrRxVa9bdR1dVQb12YC2+R9FxTWa
V3VdD7UzizwB4lPijLgAnuYotDs6Bbr/OmuO95hBWp7/CabP2k1fy340Qgrsxc/9lYN+So7oX9F+
++izvuJGIeS5JkwU0+VhNIVb+e0ihxjv9AHebC613pJNineHWAzoB2X13OSDjZbgJlIYGyo0QFDT
AhdNex4axM539GfICpSaGb2lhQEbZFD5sV7mvU6GrYTsTD4ZYXbxdbOFoBo19ErSk5fPCXQOxI+n
9h2dpkaVT8gu6BNmHzfT78pcnTQrx8fQURRPLqe0bGCvJoDqKOC7MiCD+fAtVPWcrZOFejLlODwG
7WuvznbIQlJK/Obr3PtvH5+3ugGNqakP+Cwrm+KcUB0SKOBcYJOwb5udGi5Ni6q2HDcBndruaYGB
0fg33oz5xptwmYboNTsAFi5lN56R4BrIYUAkOfGvV5iavqFxgPj6uYsvpmiLQJXMunz5lOwA43Ky
F6XV/FqRiB7TRmMsGcllnDDQcu65T8V5eDmSO3pkoNvecJu0BTKhpursqyGtDhoGrC4FYHA2pmr/
J8+6/IcDGO/YwYMHQ5WgeL2KC3hKOJe1jhUi1g1GnXvOhG4TJwzFuynwEIQVOb9fmcEUEzW0S8J/
dInBSX2wBisn7+fyl79UIUckwqdCYfflpgpGRaaSnh3EwPjVfiovvyJJhG3v6IS8K7R+DmJr5nak
cadibER9Bhd75LegU5Aqvk2MSIJBziiib5WhItklEKH9ePE5+mT4M1mW8fyYZMIFalDs4gLBO3hu
sZpCHu5BB4UGZ6pnJkxAosHYhW+wufRf2ApXZOiwvZuDhmhqFxCDDM81YxWzMzYkdixgiEanh4zr
cu6vDBvqGQy/lBZJ9bXjx4WksShti3PuzkW6mb2FME3nPinmGB89gPhHw39vNvibvV1TfdpJCfEJ
P1rCple1b33gvhna2ORsGQUSdrFLQflvpIVmDE0h1rkqW0/CwlIXqaRD9bP+DOzddue5D8Dw+fsQ
x4GltjUWqZvT2O82toohZVvbOu9NWVRFAx2FKz//ETL6JmKW1+PjNxnLory7dbmkjDRKtlDAw+CR
s4RHNKLVny9FTfQa1v8EHDHV61MVdk2Oxi3RKQdZLr7Dalshvx52fu32EKmP/7TP4Jrk7BmAWIVP
U3FIWFbturq1W2XAXGKXM3b1r0Jbr6WfS5ylc2qA6YrSyUQc2o9iMhylIzTmxOOaW+G4IbZJbci1
eiajL59wzixISCRBF3op5IpPw+RBLqCouATFAk8SJXe7Z3HH1XQkxZeoNDCsMM71Ih+J0aYPTCyZ
eQyQCImuNr0Sz0jXV+qjf5/fjijofMhDyQa42+UBwgJsHxF5JqxYrJbix/v1eo8uxJwL3IyrDFfc
nvdlQG5gf3gd/J5wXW5rXsp68GeuFXxKGVk1fZreZUnzMQVm5HwKfY+RMWTyIPG6vbgdQct3Ved8
weVr5bNYk0B5H3Rh8uPtfsiYwWzmBt8e5ZTPtbauWyKslofHZOwpySiMygObaN4jO94/1hVadnnD
Bw345nG4+PCX6f0PtLVlTQ+vv6i2VDDqk6y0y96DetOsctvBWsZUWSgSDpRgDfQm1mYWObcOGPdb
eiezaZ6ouSZwrz+3RfewU19JSt2ZO6BNqHoqwJPubamlGu6ZUukgEJ5IJXV2cC1bc1OVHURWwKep
UTWSozzR//oBRt/y5k3zL3/iVsIv/mzSJrtIpOtdiB4itOgqbCII3YBW/C//24D0lcO7LJ+49tWR
Faody8fdYi9+vNea24JmOimt23zu3Z+TJ50146N/vxENdp9RU3HlfyNJqniLrNUe7omvhYYU9GQ3
qDY5XRPzifFq2/aK2qPphwH30ZHdmR1FgiLhwUwRV7o6jagF0vWPTo7hzSj8lVq0BbFBMI/v6WFo
gyEgp7w8cLlwXGuqvI8QMyL+ShQVCCDLh0+a9cGWTJtg6RPheeDkqRCbl8JntI90SRUwxXgqL6g9
qAVpB+OXmBMW6mNiV8X47IYGgthw4jMpndgXqLbpKtod1BrCCvULK52Z5dBg8ExrpSZ8kVo7iNTF
iE1Xhg9WYH+NzeqcxQbyqKNexKAeeRuj5g/Da6G3eMhwVsZOKXWCS32oDNtjJgUXVx2MdPLoo/Vy
gwbeWiq54GKhhR3NQt9bel46a/H8jAQ5Pms8LBKNyot4VC4SUVHP37I1MqGwJLnvF0TyS/XhBElr
5OdyRPyJevOv4CW1UL3KucD7VCpdbHDctMDWV/n95gN0qC4V5+1lZZjfGGS7Q4hriEKtEck6QmEc
2T1wdksqzvE3kP0MogN4bPr3+kJMkJHSuWZc+00pEbMPH+3YtStpFMrtb6k8Hn8tYp3/069fOy//
T2e4+Xts7z7t7NxmJ5+ZhArDYLs9nqBI5LtIefd9zqzGxWi6+LxRkxGMyukP6RqhWIP0kjHoFF+p
Y0xSdGr2UGKE5ZwrfAGZ8YhI0Q24OiI0p6NIDD8brL15XVrQaPxRWt2JIHEzOWG+I0N4bLkbQAAl
GJo7ufZ2cB0yuaO6t8PKZKFz2UljTl0GrKuah4Jqt5fU4Ynv8Zc1skGCUjri1Dc6AUwYZwcCS4cN
pxR/xWDt57Svzdk+uozQZ8I2aVYSGPSER0J6NNAQP6AIHKRu8gyG64M8eMDU8URJIBj6HQReBj6U
eNb/ghIzS99m0nw5GaEKkstioxFkCAQm7w34eBCM493WucbbwosAqgthHnWzde03Os416r/kJJTd
BJDMX5ulAdMfZgmsLyYp1uLQEWV8fzDayIoHTS8lTA/ULiHP2vMXcvsDAQ0qUgVXaomb7vmUOvsb
wf1lFR7XfBhbZ8rV7mt+zklQXE4eZwdl9FMCU9DeoELaArhYVCuhTqVJp36UqromrdFJJSlVGyE2
PRs0Bqd/7Dd1UgaWwrSnJ0QbU9fZkHXd5xywBc9FKDc8Y4U2L0iUkZCb8cBTZ38XKnnGt/kDGUfK
LQb1U/9ts+m4FEloq4uakQZ5aXqhh3qBWneFkd31TPdZNfeAp2nf2964Gqo0f/4I6O76w+CN9A13
VjmRfL7iCaXHksINTz2QHcJ7P9tU8q3BsnBanj5c6W4ObMtqvOXK1HDIATE2j9ZK9V4yNcKpeqtB
9pv0YuKDsZHzt6KFUyRI9OGguWlq+yuStOxrH26j+nJ+QS7+Y67HhcwJ/ttXCPLAEC9pve4mXmw1
jVfU+rmpu6noEdPMQnyH4vI+buNWFinYcDDyXvHAE2AyUzGwDNETKNNEz818GEtIO1/Wim/9liwE
Mx11HUk2WdX8437+zEhGWLEmaxMTKkDHr4ngz7NuntSaMBOyCqzglf4PI0xAHMOEkZQdCNhgB0EL
WTrADySWey9ovVi8yWv2SWXipZJizNnuleYrJj8hJb9AomTOjnc3ELLfBHM1T0/bCLxyk5pPgnJK
bqfO1Xyw96pbkT0LrPBrBZip1BPv81cxYWFI7mC7mheSHP6jOMFCDnVbFNEUAWOfoVyYLt51ACOw
wx5hG3rl7SDEM4JO9gys/WjAcCVWXBLZPTrJIJ/7M6nNa4nIpv0SgL5RVa9TWAjc8mu/y7M5AyPl
0fv/DKh4TdeQB1Jl1f8Tx69nx1t2WsoRzdOwJb0X9tJyLdF4JQvNv7tCW8rc/gH3bnq5VA9zWVGM
P94kDadUqr4QdzCodz6KdXuJfK/iymCV7dcq9v9d+gb5/1zuDOrM5pK7YUVoDH+mIpuzNC54FWJh
+g/DmTBiIoHk/CAynPVFNoT8IXwXsYLUwzoASyPinMTwVcxHbRJq5WEcruf4OgOM6ChMEsKIHMSx
WD+POEP6M3mtEtFir95wYsqAYUHJcPrkML7b0PCwkboGpoIYk/jXaLCS8je70lDOFz6R81zXW/Jl
1HUW31jg1WGyO2wCzVrODU6fbolAILD9VLsUzo0lqh0poOrJ7QTKGmxBO/O3QkIoeksxQTGIP7LB
3vjnNkyBHhTbRAleVzz9v2YV20Y4u5RQq/G/p+zdyJigZtLrO3eMAzxJSENgNlJmH7chkdwd84Ap
wLwaabzL4ad0HDr1sHAKoLbQwkr+JDk/sdKHipFth/5j1A7u5fOHAvzK0ky6wEskJurIE/mRQkde
e2fP5aEwzO/EPeqOc9XQtOAX+AtxRX7i1caZugyyRcNS5HmjWs2+3QsMDNkoVjFvuvN5dgo+xcpz
P77udljihN2cpWr0m3XnHtWBEQC33xJF5eDGNUr0k7hVFTW/pyRWC8cM9+g7ePOVfeyPxhWmYsTw
L+GdIR5puYoHdDJ7vDWONlzOjKqA/mxp1poumhaZWAuCIVvy60Tej64qSBUN1ltg7kxN7p/9gzOW
NSfRS39mOU8a6lGz3wQ1pIJ+iflM9rKTrpR2DuXCsFltPAbPCcHwbiNCEgAT72stGbhZKeTvJXeV
wJsFaJ3N6IjduS+1nxhyYirbr0zxvojZWbdMzsROon/xjx2kB4LWudzgC6q/kwxpHyo5dvQs+jJe
5GT3amNI2Jtxarpt6Aqv68VvyrmVSDU5fUiL4xorB1ghuN51sb0qR5a9NPYHx+MfN3anVXMEkjvY
Yz5zMUWEHBt9/Xs/6BPmHr+MB2CPms+5xepeMqbZUtTPVtC/zwKzkdxfRz57tYy/Pfn78OCQWw2d
G8BEKziB30Lve6BHVwDMef4VWFa07hrkQrBHIobuQoTHiwO1bca8QAxbdKvQLYgkOCCr+RnvJAY8
B7FA7BfbmtS+DxQrNzenA5a1/cWQf4UV7sfvaiuHkCFS/jnJC03grea/+w3Ge31mCCLKyCt9adpK
LsX7/V55BNgdLNE0YxdfG7Y+4HvJvoW3h77FgRWRZzHxsJDHvJ5wVHXhhFzDd43yVhmBlviC3RY9
QjzPDngf+Y4BKfLy54OjYUOaJ3aaD8+Ac9e5AbEVM0g0n/oDKgNVjFYN5XpqxxQzY7ALhlrCy8zE
/VJNoTpbEf23Cq4BW5lr1yDA7RtwpL902n1daw13otVVgfSnZY7Zys4D5LTUZxY4l/Dp22koe2mB
bYzittQHtMXwPRuhrzxYyYZaC846RYywTa/Dvong3/VRraHyrj3sS9Hp41jAeBa44f1Vg9iqTqA1
sSgePI9zNtFxbgC7luTxRYkyrjZJoYGcpXVNW7WkOYtAvbPP6q79pPDhgwq6FCoUWd1d6Yr+OGRw
c/F+Z+cMAeUqABeBpjf7Rj2EqzfW6bpRDtfsjT4WY6fL+P2kUxMG0PYHoZ8cXhcdVuH5PBWeukg5
/OioCDxBsrj/DvBVCYaGWagANDIS7c1lm3Bhr7kvuneUmFhEhkRx7wS3OX/lS4sUW8K+dR2dVnme
yklAVkSsXzGGkYG+AONALeFcxd2iqLH58WzPNyKAkCBjzSlp00PH3sYQy4gtaCY0hrqAu/6Y4D4R
ce82QLiLqGt4C+7ox21CEs8HRETkYg+5rBbBdO28JbUKczHe3CuecE+M7W6tbDkxGSY93RUcO0iX
uZ1eornZz3pDCAp6+e5nZ9AR5zLZ7pfRufo9C9EZcZSazbRqHEcJ9vqLJcAxO3URxfwBjy8OepnM
bzi6EsPRcQA2UIkXNG4yF5p/8djqawVdAHWh5UXiUkhsTz9bPk3nCHdn5qaqK+aJupJvMwHYrGV3
FXsPSaW79qFN+pvKOhwkQMxddmyfsk2F5EKOzQBMtI1DA5A6luW7wLfAsuJIDN69pENF8eJXjWvf
RerpGgasQgh8Caa8/T2ub55kixuZ94gbq8JZwBmzR4En7fBLxszFjrtkD4QlXiwWZEHRH3ardQdG
EQirmcjIQdOODjtoBX7woYrv4HthmL+0Wolk+cyYazcRpzRjbxq1wG/6w0zHqnvL0vwBCclsymWf
lm9ac1QIeROgJOP4IwRZXfnbJ6CMxc+lpt+v4dvAsZsswPCwaNwvlh4Ywf+5x+q7kj/Am1gchQL9
j4S64PRGepEvLv/sQSd+nMWh3wNEmhy3ega8wPheu9wY+D3sd9rnXY7Wvxf7hXa3y/e4q43lqiOG
WU2EKOXZ4+j1g/w9V+paxLWY1+dPqqABNdEyQjlFZiq+t5TEU3Ywdg/mdDAH5LDqtlklUppX028l
nnMAqdlbOKbeNlFr40S3pb8XMfPkH3F1BU0yEVtrtYOV6/Ua57LLj3Es/ZKpjfb7KU1K1718MZbc
/dmKg8eOI9rO4CZ7zke6mtrMOfwMY4UcBuNYkJMBKXaI6OZdlC71zqWsr/MHreU4mX1a6rzGkinN
VdQBKZzBAHpQLm5nRZBvbfH4qGMD9i3ctnOLNsakhU9GCm7dUbz+EFoXwBkvXU5DLU/jh5wl6B1u
8uKIOdSM4Y9o6jdJeHdvPjj8RY6r2fiA2fXKfsOuZq2jwuxeEGOQMF9aeI7JfEoSpNkLgN85fWpt
f+sh6sZBcLT1ZSBKts8Mr2BqkwD8jkQnKzpdu0Tk//NqqnzwuTYCgQkIRQAx5WMvfoWkqtnsiu24
IPyE2ISZPKi0yAGAgstTzw33Loli51nit3zGU2On4XVA3ojqgCOf+bC6pSEW/DNzRJNZn1Br7M3O
NVY9in+5KvbL0oD+gJAX4FUh2YXt1wPLwq4I11s00rz7OJFtpj/N/88OxlS4vgAz6xqnUur6tv8k
JW5HZgLCMAko40Iv+34E6+G1q5BNcpiiM0b5eDUAXgOztZuV8pGtfJrwounB7OphC9Tq6YQUeTxM
k7ULM4wrse5p3L+rmQw/UJToSX842HJfbY+Ulg8Ha2fPlSJygOXtdM/+PVLtx7Dy78msCiIol+py
vHSla1LsVX5dImnl/YAiXpdxYCdhHF1s6NQcrl1Lpnr1OUFE8wOVtG33YYda10Wuh/c8eGK73t4q
xmDn+aYlpGFpbfK8b1uJfFNShFAB39j2WxgtlABkYLDiDzHw/KcrDePuAW5L2IJoU0H7V8fU0+PL
CsnzDGap/q/nmjlvEE3FWLHWJEEfnwVfkiIii5+70/T5gZOQiEd+zENm7v9HA+rOivZmaktuoEZY
Fm+AzxYp3eFsHMEsU2j7VLFyP5KWZVs2/69Xi5Dq6516ooZCTCw9+a+y3CZo1G1MhH2VaGDmqWKY
en8+ZCm7XJvgvyVNn9af/ki7OPV+lBx2hKqTRO3QMe9Ks2aSOxNsPRe+v14Dj4oJWGdEDnIF1oAW
VislsUl0ZBBYj30I380vnXxLwp2SCOkEHNYn/isDQFNUZvHXqm/8QYlWrpImAqu02E16GmpXMo1D
UZ4Rim8l/uaSuHCBl5up0WyBAPlUdLaeRdUu9FEvVgs1cujC08kg6Cw9N2n/uwl6xxKhpQmBzwuR
66+av+Z8dshSQNzdqJ8A71gJIhgboa4OJ9qCAr/AGhi4f8jpuZEm+vr0wDZVTuwQdDOt2PeHn3Ap
/oFaPn3zP8rTNSxxoe3+lPv3Ds1eVScODppFtGSUaxeuMiaABC2vFUwXjXnQsQDyrVV//0N+MzpO
9znq+JFv1eKKe+H/cj/LHcrNJ7a0liUUZPgqckBNqaAXA9HKCCqYP64XySrrJincqnvS8cTiDRJM
+5GEFzLGZDgo4LsCdOoAsLxHM8Q5/vFoemUCO0sSheelatd9t7c0S0e4w3B5cx56+ycG8vsrTsML
Dvewj4ced3zFaAuzmKUGpOMt7e8aQV7UsKaX65oQaymbrwhS9ESuk6Pe5vFa0yy3Sl7XSSwixj1i
Jmc3jeGy+ZRiLpZZszTIWEiK1tJUQHVp4P7NixWDq3j491OqOhVrVNU4D8eRyYaj1f6xtwPA7YVr
wru916hyVKoSN5MW2oy//cN1yPjCSqdRgAu9KYxbuiBGoS1xlEyxJ0HB6pqM2WU48o1OZ7okH2Yc
ilhzWz3StJ4ZzMQKzFNw/rPJgWkWEQ37hOom6T+pXPf+LbPg7VFDEvaknwHDPURB8u1UNhih/tp+
oL0yLQmEaFwRRr85G/vYhUAOAPyxmTZ7NgY+NLsX5CRdDTzFg0mtHm9Y0bJkBwYnbN+XJeiQG360
9GlPb1FD4bsNW3zDWxqAwxMRd8yXy/rwVfb+zD2PRx0YMFoS2HihTtJ0e5P1w+kpbWnj0TXzIJzb
fLk8PV0g+PoY7uaREok+3xJRTYOQsayvnlK7I4fhIUE0lNRgG4enfvMJTSKp/3UK5f13ldAnDjdA
LrSMRnTxfYLPUn4Iet+kMSGKNuaNOt1RDyetuM/XoTBtnod4Een0sA8iN6makqBP6mm4vJuxnfW8
LbIkjD5nOhdnUX3WTyRuAkqqwdby7imHpTCgimMUb/GNApHmfscA+ywhMS7/B2nKlwrU10acLDH8
7EbFbtT70bI0xy2wNKiZvwDi/5PP7Fv4jwQtCZ05hDCkocvx1HieP5S7S8LydX3pz91kkPEE1wUW
Fl4chO0i3W3gfLAjg7R0x4MNL3pGtLiNpQDw3gyJnzWTdq/3BUkVg1c1ybuf4gjN8W35HS6Ud9mh
okcxl/PH64lfZugNDyinsWCIkBOVQRu6ZCVJYfJ1iwP0DAR8PfUoFvOQpZHehZLR0hp3iiA/yevY
+tIsPvTt6TRn5H7byyCN6/+3vgeCaJxyjkwzNS9y0Jksn+EgrKdBpgUsCLqYTBLyeWlVPpdjd5Hg
QTriox5Kbr+NWvfrE9PZklpPU4kv1X924GpnyTz9kmXSH3SnNXavmScP7+jwOvijn9CEbadfP7DF
Sc+raszj0JgXPjjZH7ieQUV6+H2MvpOiiFKPmLANMJ13AxyC2XAfiL57/WxFyKmWYcWfnl2vLDPe
oH52GeXjGKxTUPcrPYUZfP4g8JLpO3krmw5eg+xJgdXOciBdL+Zg6drDHT1iz0XeQ3koc6kqK2XF
h3RZbuENtIDvfsdTkGByve0kcQXa4Iv50HHN4ZpLCidkiPafxWeHiQV2MycZCdcbcXEBqbJoeVpk
E+B897oVJ3vH3Ixqc/uQoophn+MRWY28RPo3fVBuQDa5leDcvbZaYBM2fcEaEEhkxAuUYf88dP7O
KwPTwCxC4U+odwrKu4bjUR83K8O2TbQPqSCFNJY+h6dp2kCl5qrbV2iXVbHUFEwZFgGVOWkvaKEh
fi2+zUU36/XDEWOwGlY9yRlBGcxCrstXhwwtPwGBMh2rJDbc4ctLl/Qf3k2Q5jeOGkTgSlNR/iQw
3VZdc0w3hC3fESe4BaXVvP6W5S4otisjmEx/4HziD5Gx3Msl6RkbebJatMkNk4vA/EwxMlQg2ug9
0wF6j4pvg9kYvNMEEbQ0J+XO8f9gGH18Wz6n1cQZYD6oe/qFP3eYnD/0PJhKVtHcvcuntAOZuDoj
JYleeG84I4SDOlv3DrlyUDBP/yuX0RdEXa443K1yenBdPxYUC4jvxQFchICAALGfc0Pm08UHu6N0
OO5NYMZlHVat32V2+UAttnMEBs66LBnCjeP2hFG2eWFyE2E6HoxVOyTPtqeLrQeoqYj8OYgPRRTY
JrUut8oKfqUf3e1I5uWbtxm08a3DqcbPcS8lBAk19F3utVm8gLdFr7YUo/26UkoI8cPf0LGMpH4g
uS1gM2WVO9IpnOD0x+uMI0tvg9uAul7ZaRHikSOr9siNz4J4fCvCRS5RRy/2yXyPjRUoZ0/ESxfF
gc8ouTJ+guj69JxVUKZq+j36ZS5Sv3czfESCie8A+ytR+qZkHoOINVbO8wBIS/Hrmp+v83/JcAWK
Hs7KICDz56qyteZZOL7s8ZIAAruaKXKcbc2qm2afJXxZ+XsL2RB7FuQV4jhtZQUo7oGw2fMYLC8x
lL+Csw8oXUUBMRfLrKPv3C72nQFbOw18uszutCCz7sguS6KL3zv1N2wN+HeOBtm1ki5fxULYWTFG
wrAcbMNF+YOdUq+1zM88cdvZI2sP/Tf534hoLH8OeiAO8T5u6PGxDyVn9qPZ31ALzVhyGXQEyWiP
vUlhBXMFBNM2jg8ggb2vbHO9mlZnwGryMwZvd91w7LVS/1XIEiMrdbM481MA4dT+RGgLosi0igqL
6dX0k+UXv6ghHDPkn6uUVvC2rbAZiu/xwhNsOQri/5GB57wCvTcKmVFehqqTbj/6XidKP4aqC+2/
AV/YzA8ezU9vGcfCXefLSTZdwCxqLriCvGdrdSrGsmJ7Kvt1FgJhSbdmWgyoTu2hRcHcm9NcIh8N
zwvWGAYIoV2Kni9Rm2X9lb7+rEwDboNBmgVnxNOczHA+wqFszxPrufd/x1VTPd857qGG+FKEKNPn
f0QzruH8yBg9TeeF3EhKAbs7GUOQ31W+Ncsz8jvIpCN9XaY/mlix/1pftUBzDnIo2PMDc8nR+IGy
7JQ7U0kx9SYgoDisBTfKoi+eA7ucWjdJGLunC9ABZWXShLRiZJxl+Q2WJayHdv/WdUaNIZ26GFA6
iH//kr0MzjIEmu2fB71n/xmpDvnk8D44xsEYgPEG2VPTcPRvLUC3gk3PTrWQfZxLGqrG2LJQN/0r
eP6j2FBJ/xKgCbKd9PFLkfXD/xdAEnf+ZDqdvfFkAmISeXq3NxwBRxo8nUlVbnXPLzXv3QtDIyo4
xxhd9H15UOhEmmYOIw4WNjJs1O7/bE0As5u6MuVufUnnbWOcaVrSm155B3qeicG8U7lz+grYuIrC
T4bpXoQPjKyp1eO3XCekHGsL5UM7sWVqNSyHBXJjivroKjc3f+8JvzLU1jowv6JZMtzRSExjVDHd
/Z4v9Fneou66oF8XihP960iH42q0Z6rzfoukxcC0GC+qyUTEesby9D1aoU46k/+6FINdq574kRbR
9QLcCJ5pGpPUQrsoN6T68J5HWIOBY1/Yq0G3MuZQrVLVDRq5ECxLp8OFZtDaO1PWu2v03z3IAoUU
v7Fqq+cD1/kJ6ceVdxkavV1x2JuvuxuXuA/xGRZbOVOu8aGV/O/OfLJXsDbZHz908p7FWXniBbYz
+1aRRXNc3hnAmRHZFN0voLiOOys8Upu9tfBt+85EusLyBRakIVIAqxof2I7+KzJvps1RUPnNeg7m
MixlpVe6oz7tP12EeixmERg8pxKg3YZ+pJWCxKtR97h1AaAWSStjZWd6uZGuAPv5+AAuAj/BhEDV
twAxaqSnpaQohMWJuWwKrqLBDzXzh8AmxUGieSZmifgksXbpFSvdcf4u28A22GEHvW7KjEb9b2dQ
K9SaPMntiHW+BJ9xiOrcDDVixGyCYQQNyvjki77hC/wq1FTd2qg6J23L0xijC0TBfjBtzMT36bF0
n1ath8rHczPS1Qpt5z9jelOc3o9eX2ezbBExPBayOpmudM/2Z9/b6EgLd+89iPckIsQzCCeTl3tI
JQZm0BGzKmqSXh79PLBEy04n0QvFsE2hTBv35rDS4lVpvphbZS78mShCdAyDgPtmpADFEEkzAkCc
kTU8AT76iCZPrkAa9iBdG1xBI8X99cHO6jvkPJfST46RZFNmHK2df5HAzSMb/tQDkkdyEislEZMh
tlO0jVIahvUQiMMecBUxHM1/0Cut4Q44E7iiEX7facNBMjLR+gQd4NUlgL+6lg86XMTueKTkcykc
bOlT4jhbrplSMpr43kSDrCW9Jdclma9zWYtW5e0aWTho2yDCiKUVngRnpRExs4wUJDfS770cFYgk
pl8gc30IEb0vmU8JLEGlQU0cr7z/wSoe4Xc9GHWcYZj7tRiVnDGeqr6H8s1LpGNFTDnGI5l1dPng
T+rWeECkSm2+W4iOw69K4jMtwQOUgWwBpWpojOd4bGZJ2QcDJBPt2thFpCyadDiBamt5Vzjxw5Ls
R0fFbbGFxX8PmnQuAYnQKoAiLZCrP+mlgEM++/hzktkwm3yDHh1ut24KxffXXp7FhdHrQBPct5LD
wURodyqzXUO+uaI6Ayh15bL2YfY4513nybeJhKavVP8MG2T+04cYn8MKvPK8B3VzA5LUn9Rvq+BX
HcE/POFQJRuk07gBpFRZTsoLSYEFCgfdFWsOl/nRGPONdQ/CJNi22xnF3tiJSIL5CHUUa3x/Lasv
0PNNq5bbOC8YxSypCYDzzzllFHj9qioMri68VRSqbJdITg33GBLO5ei2bk+59iUr5rCLMTrwNAJn
PJQyn+vc7cVwrerloQavjUhlkZSHXQ1kengw1QRzAdlTCNLlbyG4Y1NFlMY0IwwWRQwQiK+ZOpAA
ZXsAf84wEzQxk/fnjmfs38CqhBzq1MOZd7aBzjjzocDbYpDdDTchD/bdvdQMFYTwyrVSF4Cu1Fxi
SuirCXSed4XsoGvPvJOmDEvzUYxaiefoNFRwqB41V30zrE7BZlOEimKPFe+zkGgfZTBo9gUS2Oi6
F34o8rLAdMIsdaH7qWsvzh5ybr4emijrmC3u90r0KTzsXnYd3xNj6vY11WT8ZIo7vsIQNmWqWlK3
5/XiV9nlN9PK4ruPq+BMSH93Z9WiHD1PfgG3u9Q+8mFFHJTZaWMA4rRh4gmzbB4+E0VR3YOqOqdu
9RTL/vxNt6iISV/zy+pDAhszR0tTF1KjuaItGuYXeA0IRg3gR4TnDWkdfgZcvMpmYxZw/3n6xgBz
JqN6KWSMINurPwxnQy1el85Ri55L4jQxGO9yRneofGZn7uk7BJvnzV9D+ObNucktTAr/M5KJzFjB
lbuxznprIofRJumyzq0GxH9BBszr71TF4Voqep2qghD7WIEK0XgKwIIUpUhG9APBn7XHMrch1SkJ
4zRDG48zJ+l7JZG3m04gCsOiQJT2m2gQC4jeHtPU99uOvlG9idd3hzDICo8VdlCUNF95fijg1CZU
609a37wwZBEBjeQ5s5o5eXwZ7f9cu7fW+4hP8xBmtcmdN55ykTlzXE4cGrKm1n+05Sda3cSggmlw
q4WgNaEcgvLbdbpTy270uuIF4sYCc9Gv4n694N0fb+I+vvbctbs+Ayr8t9+MuLAwG9Po1VtkYfpa
vswWe6XyS5T41xUKlydmG5n/Za6DewfOyCBHTw8jWt06+kIZRaWUtXy/qIMEsXS2dkP/e31dW5xK
xAPluNCrmH7aPTvIDEtZXIMlb3WaXoGgaG0b8cvpBAJGZYm+YZzC8CaErgz+Z7Qf6yX6nkpXasBJ
E34VlK3bH1zVTrMMT+olANygCitlVzM+1WAzMX4WLjqdpPBcUlpe8dEzqh+TjUwYF7Pk3oDmOzTF
kxnaUVzgzLEQsJPtExkPW1YbZFy4TvxKg8zguyamlFQcA7/VZd2YJ1bAgASMdHAG5Faul4pXeft/
DFHvi+dyKsXIQ58nQVEM9MBmK2T3AIxyy70pcvfwPJNEUB/Wc4KtbXlDQhEBetsScYqaBvsxHAip
yhjTjp7ZvWcKcoL5wyRBZ3qMDTsOEUcEkn8kaSHcV6tQRQMnTAhHoHz5bR8KLKoqGyeqhWKBhheD
uiLvZNfGUlIenrG7Oh3c2nS0aOobQT/aOUqiwtuWJjn/SokpSe6/mV3+dAk5rNJ3XoktsZIrq0qF
VIKvBKxg7158diwHgiBmZxsgVeTIqcxCuNN9D5wf5V0DNmQ+kf+grYBjBdh7PmrDO5Qv/3RaPr/b
qWm0BSx8iOwbeGNtVBTUAoH17xplTdZgLn+4D+poKNIWDtDTx659nxFRXhD37jU06Bly8/l4EoB8
uuncLLwIaN/XirvpemvlS1gtV8+djtUbhoTGM/KSZQoLjV84MxlRRr6ACpUUAioHwZquh8DeiTZ0
Xj16tKm+dFX9J+HZWSjW4yalZte/LeszBNxSHxz1Pznb8sBH2SJgqggamS9foX6JEVUhUt9GBWQK
UyPtSyjPLdRtQUSvE5DIWFDiHMEjud5zIjDYOb5QP289IK9TKu3xVhoYt1XoXWq0gaSX6vfTCJAJ
4XyLo9qC14skEekEQ8alOxV0oAoyl8vGjDYrTB7XtBKpWjgymop/EBof5ikVXxzA4XkYaHvzFCh4
AKZw74P/VmKI6JR/C9S19chLCHhSHMYtZOqZ4c6eJEZ26P34JIx7Wx4RLMENqz4PhLk2xK6VCKIw
dA27dVL0IL77zKmoEZ92QnMiqpQC4E4ip7r3coijU5Y2C3LPqXEwfrww/oEuCN8U4MeMLNuqY592
SuNs1FhtjZ1D5POPsM9YIK7CcEUjGt6in3gMejBojGCJ9dCCYRxIII2vmgQMBf1YI3pb/6onpna/
mmXenNIXHmjWZTVs6HUkHvfStrlby9kI7LoiTyH+tu8fkUoJUn7LQdo021PJAAZKeWX8HSfjgnpk
UMKDJSC1PTclPb2hBMllH9LktEDi432OM6sp7eF8jF3DcLGyOOLLChutA3utI/8M1KqlcI3W0LSn
0BhHsz+YfgohG+eBIvQLX8Gzvs11dQhP4pCoyJdgR9aZYoCvHrx5tBTrXwB1LXOH3rBzl2WDJMa/
4g3kS+gycXow+gPe6Q7GHq+iq0eU0qZPFMFPUblS3XosVxyUf0LkxAoLL5umLtFd3R71NSQ/XkxI
MwBCgqHuaQmte4zKB3HnAdWncHHMynfYwGp8lyeHRkVMS9qFbw3b4GlP/1QOyzoXETecYXZoJXPe
ydAo/gj+eODYT1O9y4HhFMLe32RhLJl5evZJjhsozRCYNWSoHqFhx7+//v1EvD+UtICehtjicqzm
XxCqBcan45HMFVUaKBJ+I6n18BhDzj32/+v00SG+iOaR1d7bX7EKoSGiYvpEjMQGy+3+zIyCNb1E
jL8jWvNTKgJaInaHqsy1Zh3UcTQgm5Y8Ff2DkKpeb15c3U4zRHOJvS+pC+rqCFctGAfdQkxkcAEn
kgVXGbvCfwIECWj8LKQrhvVkg/sV+LHK7nfexskMTd4zBuolvhcHAyskEpniqshM5gOuJvdZH1UJ
ZlWz1weOssShf+2qhZ7IszaOSGyK7TdO04onrB/0MXJp/AOUFcLhcnjlEpCeSclVFyCmhWmcMC/Y
Hc8ZF6lXj6SW3yBxYMd6Z3vYZbmsebCQ32NbbqpsWe1glvT4hNmfhe11VZ+nnU03GxalVRDVSPjH
XkZiquPuVBhNYUL+CQpMjM6b5/Prgn7ep+IMStiYSRfOS+rgwLgNF7L9FPF9+oz1OZUdpyxIe/D/
uRuIAiQkRoDMedLnKVEeyXzXlz87MBMeYcBWCJGQ3RB2bCG8odT1UpAp5B8bAm/ybl7cstKVIH1R
zGhk8aYj5kzk1bmqoIJp7Jzcz6Ia4Lo9o6YjRu8mmX2sdqF34FvTwf2if2z/uWNTi29gMrg/DLbn
q2qr8pNbX5QHzvwU0NqxjidVJLVFY7WFR6nO8Ne+EWnOraaQIMXSO+dLM22FlXrw14UFSBIAv39B
9cBN452Vab3CBTIdkNWFMgFp/qcYA1oDh0oMCBtENche6M8YYSTlsCA54gxkbmgTUjPLECBCFFra
WAC4D6FAwSgXZ2V0q4il9AYAwnDgocEGGKM6iKdrzDkD+VHlmEIHFQR7w/VxSbQKKPoTkgiz/6Ue
S/LcoW0oAH/W4zRaama/XaI4xmVfSAamM+VowgwE9pZAIPJo135pTt3P38ik8aGEFJql536uOdO8
uQxMP1wzKdwTUZiiLcUi4hhqQfIXaDHwq8XFS50trvTkJhJrDRIWl/1DN2igpF6dpFeFxMQxuz4U
qwZf8em1SEa0eNXcz55+VD3GykBg31TDJaBvWopoeQt43lGZFYES546ZW1RiTib+oVUbtGO8uJbA
LRvMjaodLmK8TzTa8S76CzZMUuFV4IEc0znz3otTSGVHyZLL+u8YjSslqxtmQvHWUAoKCamFVIM4
rGQRv4V+Ubo+ujS/nfjesw1QOES1m0zdC8a2BxZJpAV/LEMKefIoA/H5GTIg2ILMBXS23OgSYGQJ
UeAyHsocEi58en8SZCCv1+uQvJh9SSqfh6vDElsLru4JUVkBfwbGOXluUk9Jwhr5i+MI7iJ5z9Ar
Im0ihg7fhE2nTCcyLKh82Zib/nLVlkqq8SWcTCGE22tgZHDpjREEQM9I0ypww5Si87YHcMe2g85D
YGmqgZm1qtOP5hPZggodRScdewVbmYpsYDN1PEbFKFDGYG+xs3iqchaj5OatNofJgCyhGMRlqwZv
Hi9epfQoHBGNlcIVy1SgqyutAfTCpMzxUjWabg+YQvaax0Y+yCENXhzzVwUXKBuHbSCEApj8BWmG
0+sPnlJwsI6XHC4ioQg2NMt+ekI6ZSquweignJ4/QD9kxReFAojWuclM+nwCeR7E9BHLd+NRrxJ0
DEpeXpFHkm1TJfkvbapo7C0XiMBXZ5yP3IYZ7zwJcTUYU2Prhh1Ahza6BSvztUEMpIhQEUIRsTLh
hiRyeUiJIt/utfHLdYGfa/KBERSVXipp/vRZxfecfqaJZQWMDDirF7+S2lmYSJ8gIPwTYCrTBMy/
U0aj+6euUqXGSIdI5FFTnQWCbIQXtJtQO/N/R+fnKs35zGmnvsfWQ0abUO9A4OVyhiXdIo2dnxpa
We3Us0O19om8es0mfNFeI8R7iZQiEDtQMMEe/DKPth2iuBc9zorJO7BKjN3j87pNIO2xerLUZhbw
hWNksmlqryXx4qt12YtI2MZWnThfXgtI8s9QfU6ZJ+ph/YCXiefLNv6q6tyx0hNHf2jzMwMQH1yH
3qkkYejVmzMisuMozNcxIpBSsMBX2I02pQlEmmG5lIit9lOvt6fp9yG+suC0zABdhpyyVAO63wsr
oJwCQ33rbPmlD2PleFUTpxt0G1L3rdisdugIQwkLyee0aalLig2Z2OHH2MU5aKSLrEBVCDOuqP1g
d7gRVhpYoCuxUCy4zS8LyPZSHP47s70s2yZPQcGFh6NR8XiZxf5SDcs0Wu3R1LzvJz8rezkpQrzE
uOg+JHn/mXGzH7c/L0nGREzv4rD1P8VuhcJPzzcL1O4HghFSpX/e9wXelbzOWZBZHFCYHMwMGhnW
0fLY2FArCckuDZ+QXaS45CXmIFYsJ1Bau1i+RnGBI654M5UsKTloFzyX95jsh6amOrOO50nFwal/
JiZxXecCSw0JzpWphC/HQf72euTxIVPwnsfbwIMWNMZ8QVxIyRsHZDb0WJTlZzsz5NLUUYu+qC7O
f6/ep2JQ8q5+ZQ+iaWg5vS2dh1InC4ez7oXC1B3G+Q0QNYJ3u0Aga8Qn8UbrJa4hwsXDogsUobbI
3lSg9FwzxxS6vvwgZFgVlRjpsnvsw7APMBkrNwzVreOywxR0RkY+7MfNflhQt7g3u2jv4s1mjbzE
NwYynHAUTfb+PoO4GYS+7qDI6KrIwF7l55fB+bgjETkfPhUZRJpUrw9Rn1HF72+sarUMxvqNgKPZ
cjlgge+9Yu9YQHe+rdT/bNAOQVtKfUqfeFJ+ByoulK71yrpoLm22fbxs/PkXM6+8oneg3bzhpM5A
TvRCko0Yw8uty+GDT+uDp4f8DQ9qRDbdyxsvaKvJetKDLcRDl5LLmTFdazhBdJrqTfuEnGP+u80S
glP5CzDu7DG54/BIpdQFyBpUy173X3Ma1DRhbQ9XcPqGFrDZk7+/WxKCuT28UTnkRQFfukNSgJkE
K3uH6gWj4ruW3OKVOAuSOMgJF85DNOvugQqDcXSGSa1esqH1SJQEJrxt9GkKE/bfL6xSP5gA48d5
/SbcbYzq0GSjABPrMry6kji6Yib9oLmaVgm3pGAvBvUt7TSK1vV0w3/ypBmuOaxh1dLK8voNh5Wf
NUUp6Y7dXRk8t3r2EiauekSRarvBSPv8wSnD6HiTISNS5GyvskY+20FAmEf+ozQIH5iUcaEp7zQ7
i6/m9vWYBAQhEbPjuMi/VC1eSrJp+bKMUrbGBiHK2BETgjqaF004MeHAJl0tBXYSIO+RC7PkEFv/
taCFu/UZMk/9uTJbsa0bDaiEZFLToiL8uMDvPaAuCROGxvlOx2qMsuwOBMYjX0sDJyYc2qPsahYq
Q6yiWWYWkmLbEjiwS4kCxzkjkevqihKle4uxHDEsncGGeYRR/5cCfsGI9upeT/jUgbuyOyReYuoM
U3HQKLh+wFBx/KjxEuumuZHw//cIXBS76bpirkVv7f9oZAuIu46wMXnrW5t+iSOYGSs9iTWRvbuK
YRniCPvk97arDnepa7teD4L7YBd4VS5jd8G9tZ/EWYBbWiZ/QtpSnLaTww+2D/ZylcBNahHTANK4
1nbR9kaTrReyPDR/wQhwpMr3a2DbjXjlDX58VSxEbTFJv68phhCpUz27AcWQ9Sm2R/1yHxjimX8e
W/V4fQbVSb3HugrdU479vzuZNru2fv+/hPxZzZgfe5PpQ3twiMMA82dFQo8+7GB4AAQQgzy9/8hN
U/+s0/gmYbO3aYf+K+Wqvaf+OLwUp2Tp6wDrEg+HlRBeTFmYE7Y8TOsltCXrNgQkZseHg+fPJ+yp
XOwUCR1AButOd5l8WDVOrnliMhTgJpblLlHCXHNic3/VhHkE6fdr/2cEqy57uhk8aB/8xrJ0uGV6
ls1OLOnwDnpma9zhz6E2erKifKSWc+W/WTxloxRO0TVR0kg7zV/98DBLUk5OkBlvXceL180GgXmV
7xTOvWUI1Jy1fZ5xAKLaIQdzgqUtmoCX5a4bJ9VQ2PMS9X1w54+WkaBN/1wYSdur8Wk2h0oXq/AS
s0YF8Z9mNZMTCwpgLBGyuVe58UTezmuo8rhj4guQ5TEdYmahyLtLINQB6fNqi29gKWZT+Ec4dd8X
W6Y7mI9xNSSIr7qQcaGWnN1ygxAVYxZet2LkWrk2ZuqraxdB3LME7OspEQ8wPGfk671b5qjV6m9V
zaHRX3FN8w+qTZHUOpS+w7DMnlIcZves/AAu6ML4QCDCCryMQ1r85inLxxYFkqlx4KohRy6TfXqf
tzjjDegsJM1ayDHcjwJdlvbqLc+cXFKmsSRbCV/iH8INv14TTMrri/ii589hD8kr+C0JYI3PwQzq
Hj9/yDOFg4dgCwFImNLeFtiim/BE/p8DdI5UbonCy4eTupVlpOkkH/aYdxH2zgInW1kyaM745nlZ
ZO0JKR58BhAItFS6+Z8fgFQNDxJ9SEcNWWaFsRjhnIaEtg1YJtK/9qA6Wf0atkckohMMFZMj7Mcq
CQfIh6rMmTWzZvZyq+uplWjoOZm/atGgj8Xmh01OSlhb45fCMfDe7f4MjxwETn086U5XckBh546R
wBZRdPG+ekMGc5bNdFbpIcN4yxynSHsHMktLcFaPohlV+P80AKUGdyB0j8FWZhp0bp1h5N2bLm5r
l6nHn8yO022FzBcK956LoOFP7NE9weKZcOs/Myp04GbDR/eutSR9XGAx6Fjgv96YcmKFEgL0vFr7
sthgWoeLYrX02kySZoOV0Jn0cy8a0Qm0wo97g+6QA9HXmT+IVuTXLyeJlEwRCCd6LUTk7pyxwLLx
FJYZfur9X0oeBGBF5LAaZr/VewZ3rjhSGV8GbbyzXMMPJltjwNTJcpxrNnBwrdGi0l192SDcQ5aX
ovzU/WzA8PtajdZPmb5McN7WzqFWgXTz70Kk9otoxh37H3kPZRcuRI9mVN6qPQSJSQ5lpBmPnt7N
z1LK9mCSn8kxUjrkq4tTacYYFX4w3/B8r4GsG52aT6Q4I8evAja4R4OAPvrvwhOi+9fBk2BnXTCX
k67oqYDtuKXLprQ8ybzv5pPIsM7OLVEGyO/6rS3b3mLUkqQyBiCrPY2UevhVq66C5Q+DM10vQv1I
PSJG64S+trjecZRUg0qTYkAe/fYg/BfwyfbyAS+ctodq3r7oq7sEmQqVxbXCt+LLH/RrmvvMzzPY
fpK45j2Huvq4+94700b0eBVStfKv5Qg+KYNqHFiAGM0sEfFI4T/SRMsipmUUmY+dLcY2DGykcfHF
hNX2qmrlygNpnZDEHQo2RifrwhktnP1TVIyJYSyIlMhicArohPN+VNoAkbneAQ/eswgNGUsKP1pW
YaEQZwZ00UMg4bCRpRNOEcdx/dOqMbaBPzBffECsa7rS02mdVy+B8b0/Z2lo1IJjN7yUOgT6s6Za
W9tHwmPyDuRAHo2S5uxzmTNQsZaMa17GWB2RWCr9yzR9oIzuGIB8J4dXooVhtNGDP5FhMYcQ/ZeA
6HCRf5WEY9kDXllklphDkN1gO8jn5quPPdtOs7hn7J/VoHUOdq4vgVsMF+wCNawYWrSJr03GL2GJ
uBv1OhL+T4EU5AIQJzVb34ZbVOP72ggn5rsop2nAOfTZIhwMI/6bppaNNFgXBz8j0xISGldkQNsB
JkFV1/7GWdF7CVvNSP4e7y0Wdox8l4oicf9jSufrc0s0Z2c4FpRW5qnjzxHBGnbYvftp4q4UqggP
7EPRaBlnBTPJR9+uIEnfJ4Cuj7T0/NiuNENQ7Bd/3uVlwxyAdIXrT5/DBhdSIEJ74+a9Dw7in7bd
NNlS9cOb6owWNbfvtXjylRnYWcs3+cz3BK/yr4H0XdGzpqwNhu3rffWZcC3Us5ytqNVB6sLGdnEP
MPmFqSKQWMMLnh5P6vBR0dHBZIzht5Xteq2tHfBC4xC64za9kM1namN5SEaLjV3v27hirmOlQjBZ
dk3PbpJw9wZNLP7YG9hHA7tyZP4urH8gLGR5qUnUjPhllrDWn1bfj+91wGuXHy/Jb3AsaUdzBt/E
nMjR1tTcb6Q4Z/5XOdWucRgWufSquR5dEQEehiu8R6Z5gOu+AfzCAqvrSjJ0A52aAkL5gcCYZAdt
n7lnOLYkdvNGtfY2H3FSmAlt8z1AKncbBYRMUemqxwen5R1k2m/ydFnhXkGXapXlXGAwi61CQYPk
zkWuYx0ZKlGxqIOy2BVutoSLB+Kh3MkRoAJo64b9sBICsN+Zg+R5vA4aphwOlWWLP7bxu0LmA84y
+Le7Wjaa84jEQ9FtBoc2Ooh05HzKsmuZGe6RjjLsl6LDxZ6yU8iybx8YklaSwxliGp+0UxAOQzUO
sswVS08d+Pe9/51pu0n6li+xVeCirfN5du/Mug1199aZRc7JiWWqrAPBbHWSyX90/I9z6x+IXEdj
QLaZDDR5X/VifEnjEtgGWel0rwCh4O4K2XMiiJpNKQEinmAcExKLVxfoDGNmHBrhcz2/DlFadqIx
krvraMRIZneLJaYm4TrVyot1nut6XMsAaGrard9bcx3j+nPZ6A8mIbGVVrZY5HKX7O6ujy9hV8/h
kP5vBj4fTVWhNLUxEsxOzheDhGOXWbIPfKmGXj+RVsRnQZ/5hp1GaiXLC0FYktQDAFGVR6zrfnQT
VC6PUFLxNj8nOMeLs6dAjmIYHPbO2BYFQCG9DrFXctXWfFHtXIahaFprO6mp2hn2yfsJfWRCoeMe
uOyrtmMoQifSrtNTRMQio8pkkxbjYV5ZDhsian84lC7fcY649S9rWgP1AArzkIU7ATY/K2p00eEF
WLniIFH4l16G5yrw0RqWepotWrav0bFYRzeSXi4hQW5eBLSHJKWvi6OIWY6+tCfQdNotOQqkkN0p
lzqlprtEo2m1VOfa/eXnPzV3ReXfnFcR2K8Mgp2Hfg5MNAaYX5S9+bOc7p8/PhEd+8e1CnIFp4XO
+HoVBARky50dx5mM7OOpCc90UNtB6+2NN7qR3m7UaLZ/E+u5d4wubAiCw6Z8OO2jJ8RrkbNeX/hB
fwe6sQ+HCbJRR6Otkkx1brPDq42vhKyQJZlqO2S97XbS/+YHyNGHwqoARTAKb8/WsOwHuoTwKgeR
05h0BgEt5eT1cGk2UnmuxGiucqqd+KsAq3Di2GhMLjt+nUW+Pn1Y+sr2VgFbzt/XGzcsAyOeF1eB
SHfwtkY2+duFVSk/50gmFu9VKWTKOhrJ7fTBZkLgKlmmwcQikOu88rMxQbvW0p4ygkT9iwNdEBrw
+JtStv7rqWjMkRs5a00/fLDH0Ex7IYjWMLAzUFdvqeaiuZW1q+l1+TkWYrykFdvytQv4sHumWfd2
jTpddzPImXosDOZ3g/Wx6fq1e88U4xVYg7Ic+bizC0865qZA/5SFLJoszlx4HwQYMki7F3pM7wcK
CIfv+RMT651sKTrarIpWE3cPj2cpVbiJVv5RM5MnpQsMtyjVKITHQOarFF+yIMMcAqiG71kqlgyF
rc4n07dM/R01fZLeqtZpKryI4D7o2yJvBiAQHH4quyn02V3N12k8OvN44lddAdTgqu/sPLr3Vhrk
xjJvAGdGKckBdMk4+9K3ViwZIlTzCuALyE68mpa+Ta7GKpuHGxlyXF5jJZL6vh5D6Ws4io7h4Bhd
Xt7rhJa1xnRlNkSSsO4LYLbQfJwM88uGxinnDiOJLmEXPw18q1UF790lxDDWBIfERG1OQuRRDbSY
ajb+lxIMUOPTbxLnsaLH+82wsAtwDRMMh8nTCamtT7r0xxwNPTF3UT7HkOEGgf9r4TyF9Q8OjH/k
JhMzHOmzHBY69mdGu/68iKjGboNMuyHAzUMJpmIH7qvGxjhLQQ7cAurSF9J/gFpmiStsdkCaQdnv
Egnygup5McvTxrme0O1J2c3/iIWy5mkZUFdonxbAFprU1kAeg48X/GchVhpaL7Kjnc0TkPPFEJkp
hCD2PMuDkiI0SOPVf+kmcAImFP1BTZJnny4w+3hY91aVPaNCXF0oOFVI9FBHDFQja2Ic0IsYmUWA
R7Bgj/YLNWTXWD95qFJbBtDnW2SMFu/KZpLFGvF8Ykei+UtKydjlQU88EONzGH9S8uAgAPRc9jwx
NYI/zc0xo24LMyZ9AcStxx6XElhfbkk3J3QvfLy6O/vkGrocM8EUUQSqtNShdSodI4qbFIjfMPcD
lRc8k2aM5PS5DlDAeb8ETmdNsB9QrYOM3ihtetQ0Pz7lClLliJWjzHBPUbTGaXXXC836+iL1OKMp
npG3V2+rWGIfTOmk2mQfWFxL6JajF2xqjKZb9dA8QZCw1jiFdatPiPMyOCc/FLw6+zTjbKEY3jqv
01Wj/QaBSQd2dGXOL5PKf3ovnE95T5CkjDpwZgo1wXeqX5YeCNsot4P/30bHRqqazWtWHleIbvUF
C2M6azRxvZygndwj/PHC8m7pNB9vMgSgAPlZSzqMdr2ZyW4S4OJ8HgJzVEvaDY/mtNMeHvPCJrgj
2ghNPlMSiwfRzg78pmFhDZuGK3/xvGI+eeycfjTMksTEzB3n1o4dMaJN8pAbsN/rU6s75HP0wIyz
zscrumtzKWmEMfc3LqHnBNr0ZewdYS3FJH43I4ZbkIGq37s0Lq5O9hFwkxeOKsOjlCPLerwHzmMF
nfowzB91xk9oFZG5SwqynAIXqV/VCt5YAUh/t530h0UO9rVnRz9SSjLthLDymHg7ybIbCgMDuLMB
EWMsP8XnoFz6DSG1kcr8rZA1cg/HqqWrxfVdmm4+eiv9nSq1srnaiJ6bIMUklB4oVfPsEJCvNPgd
QNQQRl59Qq7jqUvfqGUPTKMeej9eC8vxtjSusigpCQgEVETsjVaiRi/tgaLP0RixNmSE4Lbv/ee+
zFMKatuwg5u2VUsBnyTgM2JQit2IQQU4IVVeIETM8b9KgBJndhzWDLbFGJ4rCy4Gg3/rFlWgPE/2
8Ldcu8Qkt0opFZZfPJ9kc/12BY0ixcgOSot+v0pdHhlnBRyXv7VdTSJnP3erps1kbirgJp+mVGUr
OObajogms/p+b3yRrmZLo5brYRLrDltQOtu3wMylMZUoloEjuXOstlU1YjFw0CLwi/rEORR/4+G6
ZMblDjj5FkRH7vqecqUPMN0vOiYkZAMpoLoXnvhXgwTS8ARSq4Bts447/cBzwPY9saHtLpvltVk8
XwoVzM8Iahr262CZ2RxdBWcsbZjqR/mgWq+z9D+Je6vDySmbyvPQjl0E2BYHNGXYc9L6HLgkLhvs
d0b3YXufkIufyqyViGxWueAOkO/VfCIHPDDgACQD5mSLA492WLucp3vUicze9r1Z5ixStXL6d6iG
ql+zmoLeg3mt3cYMyd9URlwOLMhnCJ/RU29gZn2PANK3eCeMWYg9NwGlNV25SLB9yljE6gLgfmDb
zuDn2+Sa16zabXBi8bLu1KZvVMJhUwEtL9JtTiiFzw/Yw86bbfxeLh/yrdeo0on0TwV9aiIx0hBe
GwVELRMNRMbXmWdVo5+DookBH97gYyfYNRNr5LWwmCNHNrk8ztlovZRipP9HKrQCoEYvr8gF0CLz
8FN9TiSxY5ureAeBsyxlxvW1Y0+iDzCdEqYbNcBapvxnN7R7cXWHLnQ5IyL3PhI0vw8MNv7aA2mR
VNpzlSIFM35liAd4uH6JveGvOedJmGTwpxPR3yz7qNX8beEBw3zN7i0Xv27w+fRa+guGOxssqECl
HvzISlSSMW9VzIVZsF6fl/ihv7nv16Mno9OBT99mu20bZM+jVtuBtw5FB7QXAzmxm9S4fiaWeQ30
XO3Awqla3xk073FXQMRJa0pJFwhQHE2xdXwdW1/bOgpFipL+r96XQW3HMCs6HSO4GggfCC0N8Mv8
gzw1n80Cvy+thOt45eMQ98vi/Buc50VJYm3vczMYwKr04QIg13dCbYcXfnYlqTLAmU3L7asul3Hf
dtHQVYaYSM8AJDhM6mFd91z1+NVJ1rssYGcf40V58miOdTAugDdkBfQGtcaOtsDJ/WPbCS72Tw4S
Ct4ATRiIQd7rhzi5eYlyF90oE+gpIDIn36/DiW3zKS2ts7kgsXWsL8su/sRwIHiWUVwnfucOqzzc
mQzrqRR8uZhW36H6cM/v2O8PsAoUtwxPYS/iiPUc9LB8l8dCXyeK+pCGTpiQdTYa7M6ih2qs6eYM
b31sVHAQfTD7x33sNP5WutFx01DsD5gnGmZ0rVeSnyruMxSyB2dgdKacAk6fhiW+7w0H1Ypzogk6
mhdATG7eZTZM8KvH3v77ntIGQAL88ojC3nCQnQjX+eZO/TuVg3GpbaMymJqQxwovabdBKfd8OhT3
gqG+4qknQHnCHQ/zRWiCpykeihEJ1utVqqSORlb+MLEBqJfD4lGDPTd/JFXHrorkzl/EGQUplyQD
I26m6RMWgGbZX5KpxBs+AkRAlBpuXtXTLerwM7+1uJ5aG+I/z5xuZP+mP0UFUPJ9rh0f0XCBhq5C
VyhiOXF4T0HDc5OZI7RDYj/+XQH7x0dzTs3hmCZEWq9FU8hEtoOm1qMk9MFTyAe5lrl0eLU2dKee
l1+hQ/E0FQSCqCuyLaFo6bkbQ904wWLBr14B4FYPBVsAB3fbsZKXlwxIg8F/1ynWpbxlsD7ZH29l
9wdh3jO12HOqJ5UMFykRwPOGlSBFJ1HdjZxBlkMImDSSd2nhJvIeOzj4GMr5JoPgA1C+QPRkUNNN
G83FHfQASlNnXxkGpoQkJOUwC8D92KkMh5TunG8Et9x1OncTeJYtgBiBUwf0vMtoZeZQXz7Sv5cF
UqAXDRuHOBE3RUxt10l47hVhCezktryAb5KGYrdneFd0X8P/c8LxA9+MLmeMmYtJSN5yDs/ymfEs
vCxnuy6PZKldivFkEb/7p2u7O2kk3YPSKeshvBuv8zntpeWefh9LsRPJSAmIGuGr1Kmn7IvFfDdR
LxFFcpa5iqOuq7CBD4K53VnLRYQXQhZAvLaEAKQjzTDdJo1xhpC9od9cPYTMxSxgBNVFLf5yRgT8
7VT1vCNsyvMvH8zZi/s394k8hPHDxHFJc7Ihkq5Bx8+KV6wJQhIRm/5oYSYAY0t/9auKultiovju
+dQKlUpHRkjOYqPGSjjnyS6lMcy28+9A6QFe3pbQXKTAKWaGKwLDTU0uSXV2rPpfaG8BgO8BqSKQ
CCl0fynI51canT7UR3uCZctAw40Wm/c6xVkzgI2UFRJa2+UyYWMvt2swZLudawjsdkKiluosmeOV
UQC9Z8p+cdUmCg6Eta1tMkVNKw6NDgzrXhzxLI3z5L15YFOxmDUqjuKLi8oOGfuHlGJap30Bvm0i
3gxrzWx5s8Pj5lVfQD+qjPc8ZtnLlqdabuw3TjSg2gtUIu9cGE5j9OTpGlTy6e8RPc44S0KHliAi
f+8di5HfcQrnCLWscJBj7ilKJGEa6L5HNCAuCQJw0OhR56FPl+Jcz/xTtoyJDXUBRa8/HZYssueF
LQ4J0E3WnNDcOaoscRMdQCUdsVm6IOBXF3d/AXBYLbrSjaPXjDb+P9xri7FTVG7vFaWj3oFvCdD8
XQFjtbMj3hKTDTCx4FdhCWgvT78xnUHJo34NDWfSpXZbhPV97fpGCWIt7Gr/pvrWrJlfUJg8Ylfp
nY72VKGLIHfwUSIUrnt4rcMDdkpC1+Zrtdm0WrVLOiLpmOk1x9ARiEaldIM499yzigjTneLyUikm
ynfxIPhHewA/sETFM+JdXGoYja9Clv14Hc5k1tL6i3FPqPn5yiTVvWMov1HWk57LPqUTEfSWWEjQ
bv1rINMeNGFTisSJ5DuET8j43I2/ckgvYuVSCCKdLhuIwnpwl4wpZvZzG/YTk/SjupQtQ5RLkt5N
f9WEdVcC5QF2A99tOZDFAUgdci+EDkBoVmyASfgfy3qZ7xlpIoN0kD4cDqbcfdtNUX3yHccLuHNu
6gj3ySu1e6WSCMh3Iz7DW2zR6K9ay/b0O7YMVaF9LfwSlT8bBV5HRr/ViOzgT521/Vf6EE74DN5i
aPhDpThGfxoSk65stNrQ1HGsrgAa0fq5Ox3jJHZB+/wG9ZsM4+KRXSXt6w7aOFER+Tv2qW5ppkkT
MPbnN3mak0XWLD+ZK3n7A3JJvgKXKxNnuEndz2MrFYnIM6g3xCkt0LzNPZZuw7md8adAlf8ZKuU3
FEUXeU5KR3K5DJjsw8EXFNzAqc4ri+OwPQvtyqTxQBPLX6FK7l5go0Kefq3Cdux8rtIdFaIPB+OF
tir3ns+F8a2FWMxU0KdBtmrCVyNt3TAgKkTzRy7AhTTH1GzQSmw3OzDwR2g4XDrSc2tCb2VLtgNm
jhfT+NiGzjbxb/LLyMJinbl66WQQ7p0UnSrrMSFRqkuSZsjZ3h0CkC82Jhk6Gk3f/ndLbsaioGba
PmpR5VxvkHiKHoZ5ZmccBenuXvBk1IvNRWBC2kAqiAvPztheEo8bAq2kNLQzkg+lmwKRdrgRAE5w
nC1qBChX31j0y8puCtbXIEsz+5DxXagcxi+ViMXLJ+bs297OIJZlrJdBqaPMDDAwtEA/ehDaEVhl
99THm2cw9mUPxu80v+KU+gg2Hb5N4u8MJb7JDFuaSjms1ZqZXo0L2T2TA8tF9BpMm7yaIj3grDTM
0hrBQIu7PEEp7LetaW/0CPqEPKialHXa6Ge9xhrfr6qTanG104vWc3ZrANa22mS5rIW2JXtfvZMV
kAT2vVJXQcTSitLiNcWmttjDEyP17wX5w58Gbk1TfKnjD13zHxjgFA1ujEOlwKXWw1Boyvi+dmKL
LQgNq4LCMxDDnLYyqcEzWK+fEX0xkIqhr7zqz1HCYv6mJRGVd9quBxmrcsEkw0BsShMGWwR3Fvak
hLrY5IMAYD+/EdveR2kZwEv3lOGeZs8JLzJscsbUMyH6fuq9m5jEVxifwZ2hqVDegfmwACAl3qtu
gn9v1wu06DVZI2fHFP8m2TA3j7+nBxOVX8GRLPlmVF/yE3djUHgbcqHSYg2c7dzx7W0FJVwSagXP
rQ7zeROpyAensm6gydVsneSG5xX8BttzBY+b66Kft7tfd2WOQ36VbJ+u4U/lRb7Tm8Xumlja4FA+
ccCGMG7g0XTm40HhUv0TVwruUcvXL39lf9C9PQh8JtfnLMdp+tamEBQ7084sWaU28Hu6mq6zQKqR
P7fbdvhc5dxmkQhe9cBXaYbLLEbW3r/0M1dhjNMTB3PTr/F2PBpnFTIitnhi0OH/X9koHY5N7GO9
yt53Lz+kyrOjyNjInEMTY4AwkbDPxpNHeXPI+9spdZ4AbAGBboBQjJBwTtkBiJYSSfmNGDpyhUWO
Fuv2ntHb+MZ/uxXzPz9GfNSvETpkBUu0HIOxY9PXiy6S/uWNFJWmkH5w9on7FXiVYfaK0Dxt1tg3
xbOFnsKcYLc4HVOMBIePCRvx2Vo5sFVhYL4+SG049ciUw63C9Fvvp3wdnN5kt4XyzgumOo+nsaI0
Tbk0JomVpPg+xAKsCWzMFItAm1SuyYjWhvM1JSejC+EzjF1GP7hAqDO/pne8COMzmzR4ZVHQzuBn
FntCe2QmFBNkhILHgPzHcdo3ju+KXSqYm7sYnJymXIkMO7n2N/Xk/lISgzxJEYN+2Udb5g/C0SIl
iHUrl6iCzVwAkwehsgaUilDG8uqGb7pRGesoUB2D9raBS6JN9beZtL57greW3G/gk3h+cDaKf5UX
qyM1Xos6w7h2Jm0QtQY1DcNC+QE+Z12q4OekoK/Lxo9CXONE2zf17hqqyPR7hIemztO3ByKJ7bij
fTcSD4zqekXDzPNW/gzqvOVoELXXjWsU3W2oU6U57ivbvPucnbNPgEEFS/pcK8p7AjhCvkNdhEDt
AjfAsqGzXezkmXFuC0UPK3ig2COgR0pg7wuM+kuVIZQRV+5oPXfZl/IbxHUh1qzknDBJpMNGo2u8
T4Q5tsym9oNwvu0M0gDNlX65twa3x37d54LRlCJgZDcxTRjJW22gMXU/HJcCe4aM8Z6/UUMlIDcd
YL0xoEDOZPKprJBTgq/JZ/O0YPTV1VwmAk9HezXubOrdmyT8/d6OGFkfjpN78gA9Ijd4fAdiiNoI
eRgyIGSB8OpcKWd4yBlkyssHfTiOY9OSW3VOJJs9/XindlBLxhiWDen9P2/uEPIWSvit9pZjuZNP
mJqGT5eqIIaIysikO7EVhi89GzJ7k46iCogNMjvGHiMupyvCBlaWGoZmGQiq6HL66ifACKDF892Y
UMS5SIicRqgGfwmEmNC3Y1CXmBnrZab+dj2AQK96Y7t3Pe3EUsOkMVEZ4M8y1aYojxXlouAZT6Xd
1eohA7Pmph8MDsnAT6KAi/AgerEgUF2tPTaQFhGoh8wcOZfFaBiADaaA41/nECvUds4UG/TAOFqn
lFwPrf2t8uwnIUL76im32xZ8HnQ2o8VSOvJj4ll9QxzyF4L5BXpxc3X2W2GlUXBAc7e3/qxY5qPc
huZMyyAalolpEbcl8keJXkM2KU+jYEsrQxvs/5/IzRW9qazz3b4rgwC9m2Q8wYy00ujtgzIqHZvw
F0zHRQ4Boxwx7L9GgMMtWdeip87iivm1DGaBDTaX7QVuSQUNGqB/mxxpCwrjVrxUMcH3PK23SEYr
W5Lsa5Yb/Z1koM/zLS1JDK+BTksNOd0XmVMsPdzHePg8PHa8g8fVF3BqH7QL7yzHYKWOR67fVLTu
izcB9VL1SnMcmAgh6JsEStKm2q3nkLH5RTINbwhu+b39En3zweFj/t05Qz7vTYCNgVFPham/FlBa
M5q+vrQvkAG+MYTVuGqC77mbmQ+q+DWDFQWKUl3A5MWeG516aThMQkoLLrw7Q1AFiOjs4ADMQc7v
qJVdZGTdleLRZPhpHGyXrLwObG/dEyKWENW12zB6YbTm0FHNmd5SRTrqispiW0a4sN53f0Mfpv27
/z5irjIHP7Stqs3u/xmnsrYx48gW9zb7dQgdDvNu0mP6leKhRetRqIBEjg5GtIYfRVCFOS4/A+Hi
CCPghQkf/m6u7Op+6+5JwCK9PMC67BKkTQY1lnhLe+ri7mWo8gXQmcDdqox9fRlqIdxlFikVUMHP
aVDE8eE7oCC5GptX0/LZuwR+p46+8Yym9ZRcDyD3Yqzk29mIlF2Xv/WDW71FREgaHXmuVHVZzpQp
D1Md7ytj2b1iqoirKh5fD/qos229SN0yqVDfAzboch5Re4jpUyeE1U6enQpamkwuKypcuS/1+GzJ
oFRTLA8a8GcYAyKqxSagANFrMkghOUCGy4jDqbTvE9XgBr9xo53cNZnSF41CAyU3jJGTRHgaSdEf
tS0aFw6A/SLG6xZx5AaVlwh8L+OVj4OOHwP42NPX152UXYxWrUjZ54L0WhHSE4cnLCXv52SwdYR3
s+xwdmRfV+ObtMJPgAu7JoWzRUJ121Xb+wYb3pqilsru7Y5UoiSw3ERApIWvPA4DmqaWZp122K4j
20f4k4XOay0dXPcV4iJNI0KPzf9gxByM0RtRVuJ/jOeun/uDrCf7ZkAWsjQKg1pltMbfz8ID6Ixs
KD9dE8KbMdREeXHHvVawhysSyNpHVXSF1DGPzebBX+FN+hOR1tjDwdcmzXqcjiyT8vZtme559ruV
BdPmq20/rkmq75RFA63grnq6CiZW8YVwe4xdGTNgYgjyEtyeYdxe0e1Dt+W4/kiPHW80FtINT0Vn
TrEmc+Laibza1y5ghPB3Q9YO2jfXWOYKvlrtVM0s9CGCWPYgEA7oLIOo50ymPZwbjWjp56xoGkeS
KesrLTCgA8DylMtiW5IBqOv6prj5w2q4lSXJCmyG9IhL8AnjbTWGtyeN7Dt316j5vYReM6Q/xUwC
SjbTX+hKHdCe+eB6c+IyzeuzpofDTiMxzFkgipDzV2PX3dbU/LZYU/mtAuWtnEYsrVQRXsXnUhwq
SzOshkgwMQYSvd2qwabTdblYSGE/3b/snCKNQSuhrqjX0Qvvqh/WkBk6QIgn2bis018gRM5O/oqK
EnXlxv1Vqn4KdPVcWLRVZHuW6Dl/knT00dxWNM5yTVpffbWldFEt/lpVLIcSikke7iqFkgG9fpba
QzGKOvtasoIEOhBL8Wo+0QCG/bYANZPSiPr3RKDWaBha1MZGe8PZq17skaZqonBuu/qIvoglHZDl
8Oc2pbWjn1Rw51TjUQbV57d9Y22Z79YPJFXtw3fwVSw/3pZ3z09qihcHWjsHfTY8bEjRdgzwgH0K
u58k3mAzdV/JJJGEdAXXgutNLnwQPJ8j+HRD5KTtO1FqolQg6A0ABaZo01skHKemumzzLzoX99qt
HUFM4GBAnbKQCWAjgpCfHgJDB+mu41I2imHfRs6ThlLGFAidF0qcarw8ouxKN8L6R6iO5P3z4Qg0
SIxUfUoTxX7OcsPlOgwure7zXPYLyf2hzCCzrlSA7bM37ueu/FdkDI+ohe1E/vifXJ/7tzQh6vQC
fYlMES+YCRU2IE3YZXyhcFswsu0AmpySWDFtxDO1Hsyx7iUY9aPQqIEYPz96kYe0FPCDQRuE9v2p
fY2N3Qdgm3nmdYcrMQn0+Hk5M9U3uJ1dG3fBzzzMFfSRiQHt0e9DhqSSBbxVJ1melRq0XX7V5Fqj
CkjiabN0IyuyklzNKIzERuhfTsN1BQaAXnJWTMA/vsB5BiSyqcVCn+qTX53vJ9gfJgsBvpoEUP37
BZFbs57TcnFHASlD8zQquBRgHy1pv6B8Nn7ZpmdNk76s1oNJWzoYdvm9gXWGTV2PmYPiPGWhJITS
gJko+7P/3u9b4dx8ItwITLqyEq6/aQlwJ8Flm/339P7+WINqMK5/yRDg8jUtTocEQmDhRhWl2peV
ofoG9qr9EkYOydvhzvF+/JrbIsjU3Tpv4o7mf6hfAEXnLRiJJXabCY7EXF3nMFKp/7QcYnPc5n4X
Sr7eAmFANP3Yx1cBRBJms09aUe1JSVHnW6sLRzaRhNJjePHprBvtb6etMGIN4bRdiox/u3s1Krt5
l1OfaQ4TfFh655zOZaqNUR58AMatth7H6rDbGoACjnMQKr5SvUBJGD7+3ZnBN786gK2l0wGh91eQ
PV0W2TY+LfXEJ0Vo696/Ceyp36Pw6Ho35pepG63KO0garlVCvNYZLefUGG7ytq+FwP71hBiHZ5G2
7rUyQd1fDR8W+nfWE6pjo6/5qBgNZqT1w3XsElnKOxNzQ1ESIB9iNWQSdzNFPZnvyU8O2iSCPWb9
CQdlO0LYKl/mguQ+ycRcuQ4+FOf0tiDYlTWmrzx2gYzQF1KhkUgegBM38nSJHiiEG1opAEd4ZIp9
6U+8KGneQhdlAS6aJ5UJIZYvM+uYRcLQBcDjTz7CcofiodFj0Zxxx7MrLGjeEFZmVGY0WPymX5Lg
QOIjX3+DUR8hZN9onD39pS+DHSL+2RJn6H0MJrtBWEZMQApwFxNp2jMmcL1aKLgTlyHy6GOP8ZhO
QOgxFcit4GVLYZMXGJtRjj7EGyooHGn8cS2bqMWbPGEr0Ier8606+sKjXnwab1+ro1F80gqT5AP1
qtoUl4SqjFr/jppzrQMvhVj4d5emgMJvMLsQYLI=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Miguel Angel Rodriguez Jodar
//
// Create Date: 17:20:11 08/09/2015
// Design Name: SAM Coupé clone
// Module Name: saa1099
// Project Name: SAM Coupé clone
// Target Devices: Spartan 6
// Tool versions: ISE 12.4
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module saa1099 (
input wire clk, // 8 MHz
input wire rst_n,
input wire cs_n,
input wire a0, // 0=data, 1=address
input wire wr_n,
input wire [7:0] din,
output wire [7:0] out_l,
output wire [7:0] out_r
);
// DTACK is not implemented. Sorry about that
reg [7:0] amplit0, amplit1, amplit2, amplit3, amplit4, amplit5;
reg [8:0] freq0, freq1, freq2, freq3, freq4, freq5;
reg [7:0] oct10, oct32, oct54;
reg [7:0] freqenable;
reg [7:0] noiseenable;
reg [7:0] noisegen;
reg [7:0] envelope0, envelope1;
reg [7:0] ctrl; // frequency reset and sound enable for all channels
reg [4:0] addr; // holds the address of the register to write to
// Write values into internal registers
always @(posedge clk) begin
if (rst_n == 1'b0) begin
ctrl <= 8'h00;
end
else begin
if (cs_n == 1'b0 && wr_n == 1'b0) begin
if (a0 == 1'b1)
addr <= din[4:0];
else begin
case (addr)
5'h00: amplit0 <= din;
5'h01: amplit1 <= din;
5'h02: amplit2 <= din;
5'h03: amplit3 <= din;
5'h04: amplit4 <= din;
5'h05: amplit5 <= din;
5'h08: freq0 <= 9'd510 - {1'b0, din};
5'h09: freq1 <= 9'd510 - {1'b0, din};
5'h0A: freq2 <= 9'd510 - {1'b0, din};
5'h0B: freq3 <= 9'd510 - {1'b0, din};
5'h0C: freq4 <= 9'd510 - {1'b0, din};
5'h0D: freq5 <= 9'd510 - {1'b0, din};
5'h10: oct10 <= din;
5'h11: oct32 <= din;
5'h12: oct54 <= din;
5'h14: freqenable <= din;
5'h15: noiseenable <= din;
5'h16: noisegen <= din;
5'h18: envelope0 <= din;
5'h19: envelope1 <= din;
5'h1C: ctrl <= din;
endcase
end
end
end
end
wire gen0_tone;
wire gen1_tone;
wire gen2_tone;
wire gen3_tone;
wire gen4_tone;
wire gen5_tone;
wire pulse_to_noise0, pulse_to_envelope0;
wire pulse_to_noise1, pulse_to_envelope1;
wire noise0, noise1;
wire [4:0] mixout0_l, mixout0_r;
wire [4:0] mixout1_l, mixout1_r;
wire [4:0] mixout2_l, mixout2_r;
wire [4:0] mixout2_l_with_env, mixout2_r_with_env;
wire [4:0] mixout3_l, mixout3_r;
wire [4:0] mixout4_l, mixout4_r;
wire [4:0] mixout5_l, mixout5_r;
wire [4:0] mixout5_l_with_env, mixout5_r_with_env;
// Frequency and noise generators, top half
saa1099_tone_gen freq_gen0 (
.clk(clk),
.octave(oct10[2:0]),
.freq(freq0),
.out(gen0_tone),
.pulseout(pulse_to_noise0)
);
saa1099_tone_gen freq_gen1 (
.clk(clk),
.octave(oct10[6:4]),
.freq(freq1),
.out(gen1_tone),
.pulseout(pulse_to_envelope0)
);
saa1099_tone_gen freq_gen2 (
.clk(clk),
.octave(oct32[2:0]),
.freq(freq2),
.out(gen2_tone),
.pulseout()
);
saa1099_noise_gen noise_gen0 (
.clk(clk),
.rst_n(rst_n),
.pulse_from_gen(pulse_to_noise0),
.noise_freq(noisegen[1:0]),
.out(noise0)
);
// Frequency and noise generators, bottom half
saa1099_tone_gen freq_gen3 (
.clk(clk),
.octave(oct32[6:4]),
.freq(freq3),
.out(gen3_tone),
.pulseout(pulse_to_noise1)
);
saa1099_tone_gen freq_gen4 (
.clk(clk),
.octave(oct54[2:0]),
.freq(freq4),
.out(gen4_tone),
.pulseout(pulse_to_envelope1)
);
saa1099_tone_gen freq_gen5 (
.clk(clk),
.octave(oct54[6:4]),
.freq(freq5),
.out(gen5_tone),
.pulseout()
);
saa1099_noise_gen noise_gen1 (
.clk(clk),
.rst_n(rst_n),
.pulse_from_gen(pulse_to_noise1),
.noise_freq(noisegen[5:4]),
.out(noise1)
);
// Mixers
sa1099_mixer_and_amplitude mixer0 (
.clk(clk),
.en_tone(freqenable[0] == 1'b1 && noisegen[1:0] != 2'd3), // if gen0 is being used to generate noise, don't use this channel for tone output
.en_noise(noiseenable[0]),
.tone(gen0_tone),
.noise(noise0),
.amplitude_l(amplit0[3:0]),
.amplitude_r(amplit0[7:4]),
.out_l(mixout0_l),
.out_r(mixout0_r)
);
sa1099_mixer_and_amplitude mixer1 (
.clk(clk),
.en_tone(freqenable[1] == 1'b1 && envelope0[7] == 1'b0),
.en_noise(noiseenable[1]),
.tone(gen1_tone),
.noise(noise0),
.amplitude_l(amplit1[3:0]),
.amplitude_r(amplit1[7:4]),
.out_l(mixout1_l),
.out_r(mixout1_r)
);
sa1099_mixer_and_amplitude mixer2 (
.clk(clk),
.en_tone(freqenable[2]),
.en_noise(noiseenable[2]),
.tone(gen2_tone),
.noise(noise0),
.amplitude_l(amplit2[3:0]),
.amplitude_r(amplit2[7:4]),
.out_l(mixout2_l),
.out_r(mixout2_r)
);
sa1099_mixer_and_amplitude mixer3 (
.clk(clk),
.en_tone(freqenable[3] == 1'b1 && noisegen[5:4] != 2'd3), // if gen3 is being used to generate noise, don't use this channel for tone output
.en_noise(noiseenable[3]),
.tone(gen3_tone),
.noise(noise1),
.amplitude_l(amplit3[3:0]),
.amplitude_r(amplit3[7:4]),
.out_l(mixout3_l),
.out_r(mixout3_r)
);
sa1099_mixer_and_amplitude mixer4 (
.clk(clk),
.en_tone(freqenable[4] == 1'b1 && envelope1[7] == 1'b0),
.en_noise(noiseenable[4]),
.tone(gen4_tone),
.noise(noise1),
.amplitude_l(amplit4[3:0]),
.amplitude_r(amplit4[7:4]),
.out_l(mixout4_l),
.out_r(mixout4_r)
);
sa1099_mixer_and_amplitude mixer5 (
.clk(clk),
.en_tone(freqenable[5]),
.en_noise(noiseenable[5]),
.tone(gen5_tone),
.noise(noise1),
.amplitude_l(amplit5[3:0]),
.amplitude_r(amplit5[7:4]),
.out_l(mixout5_l),
.out_r(mixout5_r)
);
// Envelope generators
saa1099_envelope_gen envelope_gen0 (
.clk(clk),
.rst_n(rst_n),
.envreg(envelope0),
.write_to_envreg_addr(cs_n == 1'b0 && wr_n == 1'b0 && a0 == 1'b1 && din[4:0] == 5'h18),
.write_to_envreg_data(cs_n == 1'b0 && wr_n == 1'b0 && a0 == 1'b0 && addr == 5'h18),
.pulse_from_tonegen(pulse_to_envelope0),
.tone_en(freqenable[2]),
.noise_en(noiseenable[2]),
.sound_in_left(mixout2_l),
.sound_in_right(mixout2_r),
.sound_out_left(mixout2_l_with_env),
.sound_out_right(mixout2_r_with_env)
);
saa1099_envelope_gen envelope_gen1 (
.clk(clk),
.rst_n(rst_n),
.envreg(envelope1),
.write_to_envreg_addr(cs_n == 1'b0 && wr_n == 1'b0 && a0 == 1'b1 && din[4:0] == 5'h19),
.write_to_envreg_data(cs_n == 1'b0 && wr_n == 1'b0 && a0 == 1'b0 && addr == 5'h19),
.pulse_from_tonegen(pulse_to_envelope1),
.tone_en(freqenable[5]),
.noise_en(noiseenable[5]),
.sound_in_left(mixout5_l),
.sound_in_right(mixout5_r),
.sound_out_left(mixout5_l_with_env),
.sound_out_right(mixout5_r_with_env)
);
// Final mix
saa1099_output_mixer outmix_left (
.clk(clk),
.sound_enable(ctrl[0]),
.i0(mixout0_l),
.i1(mixout1_l),
.i2(mixout2_l_with_env),
.i3(mixout3_l),
.i4(mixout4_l),
.i5(mixout5_l_with_env),
.o(out_l)
);
saa1099_output_mixer outmix_right (
.clk(clk),
.sound_enable(ctrl[0]),
.i0(mixout0_r),
.i1(mixout1_r),
.i2(mixout2_r_with_env),
.i3(mixout3_r),
.i4(mixout4_r),
.i5(mixout5_r_with_env),
.o(out_r)
);
endmodule
module saa1099_tone_gen (
input wire clk,
input wire [2:0] octave,
input wire [8:0] freq,
output reg out,
output reg pulseout
);
reg [7:0] fcounter;
always @* begin
case (octave)
3'd0: fcounter = 8'd255;
3'd1: fcounter = 8'd127;
3'd2: fcounter = 8'd63;
3'd3: fcounter = 8'd31;
3'd4: fcounter = 8'd15;
3'd5: fcounter = 8'd7;
3'd6: fcounter = 8'd3;
3'd7: fcounter = 8'd1;
endcase
end
reg [7:0] count = 8'd0;
always @(posedge clk) begin
if (count == fcounter)
count <= 8'd0;
else
count <= count + 1;
end
reg pulse;
always @* begin
if (count == fcounter)
pulse = 1'b1;
else
pulse = 1'b0;
end
initial out = 1'b0;
reg [8:0] cfinal = 9'd0;
always @(posedge clk) begin
if (pulse == 1'b1) begin
if (cfinal == freq) begin
cfinal <= 9'd0;
out <= ~out;
end
else
cfinal <= cfinal + 1;
end
end
always @* begin
if (pulse == 1'b1 && cfinal == freq)
pulseout = 1'b1;
else
pulseout = 1'b0;
end
endmodule
module saa1099_noise_gen (
input wire clk,
input wire rst_n,
input wire pulse_from_gen,
input wire [1:0] noise_freq,
output wire out
);
reg [10:0] fcounter;
always @* begin
case (noise_freq)
2'd0: fcounter = 11'd255;
2'd1: fcounter = 11'd511;
2'd2: fcounter = 11'd1023;
default: fcounter = 11'd2047; // actually not used
endcase
end
reg [10:0] count = 11'd0;
always @(posedge clk) begin
if (count == fcounter)
count <= 11'd0;
else
count <= count + 1;
end
reg [30:0] lfsr = 31'h11111111;
always @(posedge clk) begin
if (rst_n == 1'b0)
lfsr <= 31'h11111111; // just a seed
if ((noise_freq == 2'd3 && pulse_from_gen == 1'b1) ||
(noise_freq != 2'd3 && count == fcounter)) begin
if ((lfsr[2] ^ lfsr[30]) == 1'b1)
lfsr <= {lfsr[29:0], 1'b1};
else
lfsr <= {lfsr[29:0], 1'b0};
end
end
assign out = lfsr[0];
endmodule
module sa1099_mixer_and_amplitude (
input wire clk,
input wire en_tone,
input wire en_noise,
input wire tone,
input wire noise,
input wire [3:0] amplitude_l,
input wire [3:0] amplitude_r,
output reg [4:0] out_l,
output reg [4:0] out_r
);
reg [4:0] next_out_l, next_out_r;
always @* begin
next_out_l = 5'b0000;
next_out_r = 5'b0000;
if (en_tone == 1'b1)
if (tone == 1'b1) begin
next_out_l = next_out_l + {1'b0, amplitude_l};
next_out_r = next_out_r + {1'b0, amplitude_r};
end
if (en_noise == 1'b1)
if (noise == 1'b1) begin
next_out_l = next_out_l + {1'b0, amplitude_l};
next_out_r = next_out_r + {1'b0, amplitude_r};
end
end
always @(posedge clk) begin
out_l <= next_out_l;
out_r <= next_out_r;
end
endmodule
module saa1099_envelope_gen (
input wire clk,
input wire rst_n,
input wire [7:0] envreg,
input wire write_to_envreg_addr,
input wire write_to_envreg_data,
input wire pulse_from_tonegen,
input wire tone_en,
input wire noise_en,
input wire [4:0] sound_in_left,
input wire [4:0] sound_in_right,
output wire [4:0] sound_out_left,
output wire [4:0] sound_out_right
);
reg [3:0] envelopes[0:511];
integer i;
initial begin
// Generating envelopes
// 0 0 0 : ______________
for (i=0;i<64;i=i+1)
envelopes[{3'b000,i[5:0]}] = 4'd0;
// 0 0 1 : --------------
for (i=0;i<64;i=i+1)
envelopes[{3'b001,i[5:0]}] = 4'd15;
// 0 1 0 : \_____________
for (i=0;i<16;i=i+1)
envelopes[{3'b010,i[5:0]}] = ~i[3:0];
for (i=16;i<64;i=i+1)
envelopes[{3'b010,i[5:0]}] = 4'd0;
// 0 1 1 : \|\|\|\|\|\|\|\
for (i=0;i<64;i=i+1)
envelopes[{3'b011,i[5:0]}] = ~i[3:0];
// 1 0 0 : /\______________
for (i=0;i<16;i=i+1)
envelopes[{3'b100,i[5:0]}] = i[3:0];
for (i=16;i<32;i=i+1)
envelopes[{3'b100,i[5:0]}] = ~i[3:0];
for (i=32;i<64;i=i+1)
envelopes[{3'b100,i[5:0]}] = 4'd0;
// 1 0 1 : /\/\/\/\/\/\/\/\
for (i=0;i<16;i=i+1)
envelopes[{3'b101,i[5:0]}] = i[3:0];
for (i=16;i<32;i=i+1)
envelopes[{3'b101,i[5:0]}] = ~i[3:0];
for (i=32;i<48;i=i+1)
envelopes[{3'b101,i[5:0]}] = i[3:0];
for (i=48;i<64;i=i+1)
envelopes[{3'b101,i[5:0]}] = ~i[3:0];
// 1 1 0 : /|________________
for (i=0;i<16;i=i+1)
envelopes[{3'b110,i[5:0]}] = i[3:0];
for (i=16;i<64;i=i+1)
envelopes[{3'b110,i[5:0]}] = 4'd0;
// 1 1 1 : /|/|/|/|/|/|/|/|/|
for (i=0;i<64;i=i+1)
envelopes[{3'b111,i[5:0]}] = i[3:0];
end
reg write_to_address_prev = 1'b0;
wire write_to_address_edge = (~write_to_address_prev & write_to_envreg_addr);
reg write_to_data_prev = 1'b0;
wire write_to_data_edge = (~write_to_data_prev & write_to_envreg_data);
reg [2:0] envshape = 3'b000;
reg stereoshape = 1'b0;
reg envclock = 1'b0;
wire env_enable = envreg[7];
wire env_resolution = envreg[4];
reg pending_data = 1'b0;
reg [5:0] envcounter = 6'd0;
always @(posedge clk) begin
if (rst_n == 1'b0) begin
envcounter <= 6'd0;
stereoshape <= 1'b0;
envshape <= 3'b000;
envclock <= 1'b0;
write_to_address_prev <= 1'b0;
write_to_data_prev <= 1'b0;
pending_data <= 1'b0;
end
else begin
write_to_address_prev <= write_to_envreg_addr;
write_to_data_prev <= write_to_envreg_data;
if (write_to_data_edge == 1'b1)
pending_data <= 1'b1;
if (env_enable == 1'b1) begin
if (envclock == 1'b0 && pulse_from_tonegen == 1'b1 || envclock == 1'b1 && write_to_address_edge == 1'b1) begin // pulse from internal or external clock?
if (envcounter == 6'd63)
envcounter <= 6'd32;
else begin
if (env_resolution == 1'b0)
envcounter <= envcounter + 1;
else
envcounter <= envcounter + 2;
end
if (envcounter == 6'd0 ||
envcounter >= 6'd15 && (envshape == 3'b000 || envshape == 3'b010 || envshape == 3'b110) ||
envcounter[3:0] == 4'd15 && (envshape == 3'b001 || envshape == 3'b011 || envshape == 3'b111) ||
envcounter >= 6'd31 && envshape == 3'b100 ||
envcounter[4:0] == 5'd31 && envshape ==3'b101) begin // find out when to updated buffered values
if (pending_data == 1'b1) begin // if we reached one of the designated points (3) or (4) and there is pending data, load it
envshape <= envreg[3:1];
stereoshape <= envreg[0];
envclock <= envreg[5];
envcounter <= 6'd0;
pending_data <= 1'b0;
end
end
end
end
end
end
reg [3:0] envleft = 4'b0000;
wire [3:0] envright = (stereoshape == 1'b0)? envleft : ~envleft; // bit 0 of envreg inverts envelope shape
always @(posedge clk)
envleft <= envelopes[{envshape,envcounter}]; // take current envelope from envelopes ROM
wire [4:0] temp_out_left, temp_out_right;
saa1099_amp_env_mixer modulate_left (
.a(sound_in_left),
.b(envleft),
.o(temp_out_left)
);
saa1099_amp_env_mixer modulate_right (
.a(sound_in_right),
.b(envright),
.o(temp_out_right)
);
assign sound_out_left = (env_enable == 1'b0)? sound_in_left : // if envelopes are not enabled, just bypass them
(env_enable == 1'b1 && tone_en == 1'b0 && noise_en == 1'b0)? {envleft, envleft[3]} : // if tone and noise are off, output is envelope signal itself
temp_out_left; // else it is original signal modulated by envelope
assign sound_out_right = (env_enable == 1'b0)? sound_in_right :
(env_enable == 1'b1 && tone_en == 1'b0 && noise_en == 1'b0)? {envright, envright[3]} :
temp_out_right;
endmodule
module saa1099_amp_env_mixer (
input wire [4:0] a, // amplitude
input wire [3:0] b, // envelope
output wire [4:0] o // output
);
wire [6:0] res1 = ((b[0] == 1'b1)? a : 5'h00) + ((b[1] == 1'b1)? {a,1'b0} : 6'h00);
wire [8:0] res2 = ((b[2] == 1'b1)? {a,2'b00} : 7'h00) + ((b[3] == 1'b1)? {a,3'b000} : 8'h00);
wire [8:0] res3 = res1 + res2;
assign o = res3[8:4];
endmodule
module saa1099_output_mixer (
input wire clk,
input wire sound_enable,
input wire [4:0] i0,
input wire [4:0] i1,
input wire [4:0] i2,
input wire [4:0] i3,
input wire [4:0] i4,
input wire [4:0] i5,
output reg [7:0] o
);
reg [7:0] compressor_table[0:255];
initial begin
$readmemh ("compressor_lut.hex", compressor_table);
end
reg [7:0] mix;
always @* begin
if (sound_enable == 1'b1)
mix = i0 + i1 + i2 + i3 + i4 + i5;
else
mix = 8'd0;
end
always @(posedge clk) begin
o <= compressor_table[mix];
end
endmodule
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.