text
stringlengths 938
1.05M
|
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
|
module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
parameter WIDTH = 8;
wire clk_25;
reg [8 : 0] ctr = 3;
wire vs_valid;
wire hs_valid;
assign red_o = hs_valid & vs_valid ? pix[7 : 4] : 0;
assign blue_o = hs_valid & vs_valid ? pix[3 : 0] : 0;
assign green_o = hs_valid & vs_valid? 4'b1111 : 0;
always @(posedge clk_25)
begin
ctr <= ctr + 1;
end
genvar i;
generate
for (i = 0; i < 8; i = i + 1)
begin
//assign led_o[i] = ctr[i + 18];
end
endgenerate
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b101)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_25)
);
vga vga(
.clk(clk_25),
.vs_o(vs_o),
.vs_valid(vs_valid),
.hs_o(hs_o),
.hs_valid(hs_valid)
);
wire [7 : 0] pix;
mandlebrot_factory mandle(
.clk(clk_25),
.raddr(ctr),
.q(pix)
);
endmodule // top
|
//////////////////////////////////////////////////////////////////////
//// ////
//// orpsoc-defines ////
//// ////
//// Top level ORPSoC defines file ////
//// ////
//// Included in toplevel and testbench ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
// Uncomment a `define BOARD_XYZ to configure design RTL for it.
//
// Mainly presets are for internal frequency settings, and what
// external oscillator is expected (ordb1's were made with various
// XTALs.)
//
//////////////////////////////////////////////////////////////////////
`define XILINX
`define XILINX_PLL
`define FPGA_BOARD_XILINX_ML501
`define IOCONFIG_XILINX_ML501
`define BOARD_CLOCK_PERIOD 5000 // 200MHz (pS accuracy for Xilinx sims.)
// `define ADV_DEBUG
`define JTAG_DEBUG
// `define ROM_WB
`define RAM_WB
// `define XILINX_SSRAM
// `define XILINX_DDR2
`define UART0
// `define GPIO0
// `define SPI0
// `define I2C0
// `define I2C1
// `define ETH0
`define ETH0_PHY_RST
// end of included module defines - keep this comment line here, scripts depend on it!!
//
// Arbiter defines
//
// Uncomment to register things through arbiter (hopefully quicker design)
// Instruction bus arbiter
//`define ARBITER_IBUS_REGISTERING
`define ARBITER_IBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
// This has to be kind of long, as DDR2 initialisation can take a little while
// and after reset, and if this is too short we'll always get bus error.
`ifdef XILINX_DDR2
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 6
`endif
// Data bus arbiter
//`define ARBITER_DBUS_REGISTERING
`define ARBITER_DBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`ifdef XILINX_DDR2
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 20
`else
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 6
`endif
// Byte bus (peripheral bus) arbiter
// Don't really need the watchdog here - the databus will pick it up
//`define ARBITER_BYTEBUS_WATCHDOG
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s15 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s15.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s15_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s15 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_1_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** This Verilog HDL file is used for synthesis in chaining DMA design example
//*
//* This file provides the top level for synthesis
//*/
module pcie_4243_hip_s4gx_gen2_x8_128_example_chaining_top (
// inputs:
free_100MHz,
local_rstn_ext,
pcie_rstn,
refclk,
req_compliance_push_button_n,
rx_in0,
rx_in1,
rx_in2,
rx_in3,
rx_in4,
rx_in5,
rx_in6,
rx_in7,
usr_sw,
// outputs:
L0_led,
alive_led,
comp_led,
gen2_led,
lane_active_led,
tx_out0,
tx_out1,
tx_out2,
tx_out3,
tx_out4,
tx_out5,
tx_out6,
tx_out7
)
;
output L0_led;
output alive_led;
output comp_led;
output gen2_led;
output [ 3: 0] lane_active_led;
output tx_out0;
output tx_out1;
output tx_out2;
output tx_out3;
output tx_out4;
output tx_out5;
output tx_out6;
output tx_out7;
input free_100MHz;
input local_rstn_ext;
input pcie_rstn;
input refclk;
input req_compliance_push_button_n;
input rx_in0;
input rx_in1;
input rx_in2;
input rx_in3;
input rx_in4;
input rx_in5;
input rx_in6;
input rx_in7;
input [ 7: 0] usr_sw;
reg L0_led;
reg [ 25: 0] alive_cnt;
reg alive_led;
wire any_rstn;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102" */;
wire clk_out_buf;
reg comp_led;
reg gen2_led;
wire gen2_speed;
reg [ 3: 0] lane_active_led;
wire local_rstn;
wire [ 3: 0] open_lane_width_code;
wire [ 3: 0] open_phy_sel_code;
wire [ 3: 0] open_ref_clk_sel_code;
wire phystatus_ext;
wire [ 1: 0] powerdown_ext;
wire req_compliance_soft_ctrl;
wire [ 7: 0] rxdata0_ext;
wire [ 7: 0] rxdata1_ext;
wire [ 7: 0] rxdata2_ext;
wire [ 7: 0] rxdata3_ext;
wire [ 7: 0] rxdata4_ext;
wire [ 7: 0] rxdata5_ext;
wire [ 7: 0] rxdata6_ext;
wire [ 7: 0] rxdata7_ext;
wire rxdatak0_ext;
wire rxdatak1_ext;
wire rxdatak2_ext;
wire rxdatak3_ext;
wire rxdatak4_ext;
wire rxdatak5_ext;
wire rxdatak6_ext;
wire rxdatak7_ext;
wire rxelecidle0_ext;
wire rxelecidle1_ext;
wire rxelecidle2_ext;
wire rxelecidle3_ext;
wire rxelecidle4_ext;
wire rxelecidle5_ext;
wire rxelecidle6_ext;
wire rxelecidle7_ext;
wire rxpolarity0_ext;
wire rxpolarity1_ext;
wire rxpolarity2_ext;
wire rxpolarity3_ext;
wire rxpolarity4_ext;
wire rxpolarity5_ext;
wire rxpolarity6_ext;
wire rxpolarity7_ext;
wire [ 2: 0] rxstatus0_ext;
wire [ 2: 0] rxstatus1_ext;
wire [ 2: 0] rxstatus2_ext;
wire [ 2: 0] rxstatus3_ext;
wire [ 2: 0] rxstatus4_ext;
wire [ 2: 0] rxstatus5_ext;
wire [ 2: 0] rxstatus6_ext;
wire [ 2: 0] rxstatus7_ext;
wire rxvalid0_ext;
wire rxvalid1_ext;
wire rxvalid2_ext;
wire rxvalid3_ext;
wire rxvalid4_ext;
wire rxvalid5_ext;
wire rxvalid6_ext;
wire rxvalid7_ext;
wire safe_mode;
wire set_compliance_mode;
wire [ 39: 0] test_in;
wire test_in_32_hip;
wire test_in_5_hip;
wire [ 8: 0] test_out_icm;
wire tx_out0;
wire tx_out1;
wire tx_out2;
wire tx_out3;
wire tx_out4;
wire tx_out5;
wire tx_out6;
wire tx_out7;
wire txcompl0_ext;
wire txcompl1_ext;
wire txcompl2_ext;
wire txcompl3_ext;
wire txcompl4_ext;
wire txcompl5_ext;
wire txcompl6_ext;
wire txcompl7_ext;
wire [ 7: 0] txdata0_ext;
wire [ 7: 0] txdata1_ext;
wire [ 7: 0] txdata2_ext;
wire [ 7: 0] txdata3_ext;
wire [ 7: 0] txdata4_ext;
wire [ 7: 0] txdata5_ext;
wire [ 7: 0] txdata6_ext;
wire [ 7: 0] txdata7_ext;
wire txdatak0_ext;
wire txdatak1_ext;
wire txdatak2_ext;
wire txdatak3_ext;
wire txdatak4_ext;
wire txdatak5_ext;
wire txdatak6_ext;
wire txdatak7_ext;
wire txdetectrx_ext;
wire txelecidle0_ext;
wire txelecidle1_ext;
wire txelecidle2_ext;
wire txelecidle3_ext;
wire txelecidle4_ext;
wire txelecidle5_ext;
wire txelecidle6_ext;
wire txelecidle7_ext;
assign safe_mode = 1;
assign local_rstn = safe_mode | local_rstn_ext;
assign any_rstn = pcie_rstn & local_rstn;
assign test_in[39 : 33] = 0;
assign set_compliance_mode = usr_sw[0];
assign req_compliance_soft_ctrl = 0;
assign test_in[32] = test_in_32_hip;
assign test_in[31 : 9] = 0;
assign test_in[8 : 6] = safe_mode ? 4'b010 : usr_sw[3 : 1];
assign test_in[5] = test_in_5_hip;
assign test_in[4 : 0] = 5'b01000;
//reset Synchronizer
always @(posedge clk_out_buf or negedge any_rstn)
begin
if (any_rstn == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//LED logic
always @(posedge clk_out_buf or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
alive_cnt <= 0;
alive_led <= 0;
comp_led <= 0;
L0_led <= 0;
lane_active_led <= 0;
end
else
begin
alive_cnt <= alive_cnt +1;
alive_led <= alive_cnt[25];
comp_led <= ~(test_out_icm[4 : 0] == 5'b00011);
L0_led <= ~(test_out_icm[4 : 0] == 5'b01111);
lane_active_led[3 : 0] <= ~(test_out_icm[8 : 5]);
end
end
//Gen2 LED logic
always @(posedge clk_out_buf or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
gen2_led <= 0;
else
gen2_led <= ~gen2_speed;
end
altpcierd_compliance_test pcie_compliance_test_enable
(
.local_rstn (local_rstn_ext),
.pcie_rstn (pcie_rstn),
.refclk (refclk),
.req_compliance_push_button_n (req_compliance_push_button_n),
.req_compliance_soft_ctrl (req_compliance_soft_ctrl),
.set_compliance_mode (set_compliance_mode),
.test_in_32_hip (test_in_32_hip),
.test_in_5_hip (test_in_5_hip)
);
pcie_4243_hip_s4gx_gen2_x8_128_example_chaining_pipen1b core
(
.core_clk_out (clk_out_buf),
.free_100MHz (free_100MHz),
.gen2_speed (gen2_speed),
.lane_width_code (open_lane_width_code),
.local_rstn (local_rstn),
.pcie_rstn (pcie_rstn),
.phy_sel_code (open_phy_sel_code),
.phystatus_ext (phystatus_ext),
.pipe_mode (1'b0),
.pld_clk (clk_out_buf),
.powerdown_ext (powerdown_ext),
.ref_clk_sel_code (open_ref_clk_sel_code),
.refclk (refclk),
.rx_in0 (rx_in0),
.rx_in1 (rx_in1),
.rx_in2 (rx_in2),
.rx_in3 (rx_in3),
.rx_in4 (rx_in4),
.rx_in5 (rx_in5),
.rx_in6 (rx_in6),
.rx_in7 (rx_in7),
.rxdata0_ext (rxdata0_ext),
.rxdata1_ext (rxdata1_ext),
.rxdata2_ext (rxdata2_ext),
.rxdata3_ext (rxdata3_ext),
.rxdata4_ext (rxdata4_ext),
.rxdata5_ext (rxdata5_ext),
.rxdata6_ext (rxdata6_ext),
.rxdata7_ext (rxdata7_ext),
.rxdatak0_ext (rxdatak0_ext),
.rxdatak1_ext (rxdatak1_ext),
.rxdatak2_ext (rxdatak2_ext),
.rxdatak3_ext (rxdatak3_ext),
.rxdatak4_ext (rxdatak4_ext),
.rxdatak5_ext (rxdatak5_ext),
.rxdatak6_ext (rxdatak6_ext),
.rxdatak7_ext (rxdatak7_ext),
.rxelecidle0_ext (rxelecidle0_ext),
.rxelecidle1_ext (rxelecidle1_ext),
.rxelecidle2_ext (rxelecidle2_ext),
.rxelecidle3_ext (rxelecidle3_ext),
.rxelecidle4_ext (rxelecidle4_ext),
.rxelecidle5_ext (rxelecidle5_ext),
.rxelecidle6_ext (rxelecidle6_ext),
.rxelecidle7_ext (rxelecidle7_ext),
.rxpolarity0_ext (rxpolarity0_ext),
.rxpolarity1_ext (rxpolarity1_ext),
.rxpolarity2_ext (rxpolarity2_ext),
.rxpolarity3_ext (rxpolarity3_ext),
.rxpolarity4_ext (rxpolarity4_ext),
.rxpolarity5_ext (rxpolarity5_ext),
.rxpolarity6_ext (rxpolarity6_ext),
.rxpolarity7_ext (rxpolarity7_ext),
.rxstatus0_ext (rxstatus0_ext),
.rxstatus1_ext (rxstatus1_ext),
.rxstatus2_ext (rxstatus2_ext),
.rxstatus3_ext (rxstatus3_ext),
.rxstatus4_ext (rxstatus4_ext),
.rxstatus5_ext (rxstatus5_ext),
.rxstatus6_ext (rxstatus6_ext),
.rxstatus7_ext (rxstatus7_ext),
.rxvalid0_ext (rxvalid0_ext),
.rxvalid1_ext (rxvalid1_ext),
.rxvalid2_ext (rxvalid2_ext),
.rxvalid3_ext (rxvalid3_ext),
.rxvalid4_ext (rxvalid4_ext),
.rxvalid5_ext (rxvalid5_ext),
.rxvalid6_ext (rxvalid6_ext),
.rxvalid7_ext (rxvalid7_ext),
.test_in (test_in),
.test_out_icm (test_out_icm),
.tx_out0 (tx_out0),
.tx_out1 (tx_out1),
.tx_out2 (tx_out2),
.tx_out3 (tx_out3),
.tx_out4 (tx_out4),
.tx_out5 (tx_out5),
.tx_out6 (tx_out6),
.tx_out7 (tx_out7),
.txcompl0_ext (txcompl0_ext),
.txcompl1_ext (txcompl1_ext),
.txcompl2_ext (txcompl2_ext),
.txcompl3_ext (txcompl3_ext),
.txcompl4_ext (txcompl4_ext),
.txcompl5_ext (txcompl5_ext),
.txcompl6_ext (txcompl6_ext),
.txcompl7_ext (txcompl7_ext),
.txdata0_ext (txdata0_ext),
.txdata1_ext (txdata1_ext),
.txdata2_ext (txdata2_ext),
.txdata3_ext (txdata3_ext),
.txdata4_ext (txdata4_ext),
.txdata5_ext (txdata5_ext),
.txdata6_ext (txdata6_ext),
.txdata7_ext (txdata7_ext),
.txdatak0_ext (txdatak0_ext),
.txdatak1_ext (txdatak1_ext),
.txdatak2_ext (txdatak2_ext),
.txdatak3_ext (txdatak3_ext),
.txdatak4_ext (txdatak4_ext),
.txdatak5_ext (txdatak5_ext),
.txdatak6_ext (txdatak6_ext),
.txdatak7_ext (txdatak7_ext),
.txdetectrx_ext (txdetectrx_ext),
.txelecidle0_ext (txelecidle0_ext),
.txelecidle1_ext (txelecidle1_ext),
.txelecidle2_ext (txelecidle2_ext),
.txelecidle3_ext (txelecidle3_ext),
.txelecidle4_ext (txelecidle4_ext),
.txelecidle5_ext (txelecidle5_ext),
.txelecidle6_ext (txelecidle6_ext),
.txelecidle7_ext (txelecidle7_ext)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:51:52 05/16/2015
// Design Name: IO_memory
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_IO_memory.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: IO_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_IO_memory;
// Inputs
reg clock;
reg IO_write;
reg [11:0] IO_address;
reg [15:0] IO_data_in;
reg [15:0] processor_input;
// Outputs
wire [15:0] IO_data_out;
wire [15:0] processor_output;
// Instantiate the Unit Under Test (UUT)
IO_memory uut (
.clock(clock),
.IO_write(IO_write),
.IO_address(IO_address),
.IO_data_in(IO_data_in),
.IO_data_out(IO_data_out),
.processor_input(processor_input),
.processor_output(processor_output)
);
initial begin
// Initialize Inputs
clock = 0;
IO_write = 0;
IO_address = 0;
IO_data_in = 0;
processor_input = 16'h3131;
// Wait 100 ns for global reset to finish
//#100;
// #2;
// IO_address = 12'h001;
//
// #2;
// IO_address = 12'h002;
//
// #2;
// IO_address = 12'h009;
// IO_data_in = 16'h2121;
// IO_write = 1;
//
// #2;
// IO_address = 12'h002;
// IO_data_in = 0;
// IO_write = 0;
//
// #2;
// IO_address = 12'h009;
//
// #2;
// IO_address = 12'hff0;
//
// #2;
// IO_address = 12'hff1;
// IO_data_in = 16'h5555;
// IO_write = 1;
//
// #2;
// IO_write = 0;
// IO_data_in = 0;
// IO_address = 12'h001;
//
// #2;
// IO_write = 0;
// IO_address = 12'h002;
//
// #2;
// IO_address = 12'hff1;
#30;
IO_address = 12'h000;
#20;
IO_address = 12'h00f;
#20;
IO_address = 12'h000;
#20;
IO_address = 12'hff0;
#40;
IO_address = 12'h001;
#20;
IO_address = 12'h000;
#20;
IO_address = 12'h00a;
IO_data_in = 16'h3169;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'h003;
#20;
IO_address = 12'h00a;
#20;
IO_address = 12'h004;
#20;
IO_address = 12'hff0;
IO_data_in = 16'h3170;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'hff0;
#20;
IO_address = 12'h004;
#20;
IO_address = 12'hff1;
IO_data_in = 16'h3170;
IO_write = 1;
#20;
IO_address = 12'h002;
IO_data_in = 0;
IO_write = 0;
#20;
IO_address = 12'hff1;
#20;
IO_address = 12'h004;
end
always #10 clock = !clock;
endmodule
|
(** * IndProp: Inductively Defined Propositions *)
Require Export Logic.
(* ####################################################### *)
(** * Inductively Defined Propositions *)
(** In the [Logic] chapter we looked at several ways of writing
propositions, including conjunction, disjunction, and quantifiers.
In this chapter, we bring a new tool into the mix: _inductive
definitions_.
Recall that we have seen two ways of stating that a number [n] is
even: We can say (1) [evenb n = true], or (2) [exists k, n =
double k]. Yet another possibility is to say that [n] is even if
we can establish its evenness from the following rules:
- Rule [ev_0]: The number [0] is even.
- Rule [ev_SS]: If [n] is even, then [S (S n)] is even.
To illustrate how this new definition of evenness works, let's use
its rules to show that [4] is even. By rule [ev_SS], it suffices
to show that [2] is even. This, in turn, is again guaranteed by
rule [ev_SS], as long as we can show that [0] is even. But this
last fact follows directly from the [ev_0] rule. *)
(** We will see many definitions like this one during the rest
of the course. For purposes of informal discussions, it is
helpful to have a lightweight notation that makes them easy to
read and write. _Inference rules_ are one such notation: *)
(**
------------ (ev_0)
ev 0
ev n
-------------- (ev_SS)
ev (S (S n))
*)
(** Each of the textual rules above is reformatted here as an
inference rule; the intended reading is that, if the _premises_
above the line all hold, then the _conclusion_ below the line
follows. For example, the rule [ev_SS] says that, if [n]
satisfies [ev], then [S (S n)] also does. If a rule has no
premises above the line, then its conclusion holds
unconditionally.
We can represent a proof using these rules by combining rule
applications into a _proof tree_. Here's how we might transcribe
the above proof that [4] is even: *)
(**
------ (ev_0)
ev 0
------ (ev_SS)
ev 2
------ (ev_SS)
ev 4
*)
(** Why call this a "tree" (rather than a "stack", for example)?
Because, in general, inference rules can have multiple premises.
We will see examples of this below. *)
(** Putting all of this together, we can translate the definition of
evenness into a formal Coq definition using an [Inductive]
declaration, where each constructor corresponds to an inference
rule: *)
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n : nat, ev n -> ev (S (S n)).
(** This definition is different in one crucial respect from
previous uses of [Inductive]: its result is not a [Type], but
rather a function from [nat] to [Prop] -- that is, a property of
numbers. Note that we've already seen other inductive definitions
that result in functions, such as [list], whose type is [Type ->
Type]. What is new here is that, because the [nat] argument of
[ev] appears _unnamed_, to the _right_ of the colon, it is allowed
to take different values in the types of different constructors:
[0] in the type of [ev_0] and [S (S n)] in the type of [ev_SS].
In contrast, the definition of [list] names the [X] parameter
_globally_, to the _left_ of the colon, forcing the result of
[nil] and [cons] to be the same ([list X]). Had we tried to bring
[nat] to the left in defining [ev], we would have seen an error:
*)
Fail Inductive wrong_ev (n : nat) : Prop :=
| wrong_ev_0 : wrong_ev 0
| wrong_ev_SS : forall n, wrong_ev n -> wrong_ev (S (S n)).
(* ===> Error: A parameter of an inductive type n is not
allowed to be used as a bound variable in the type
of its constructor. *)
(** ("Parameter" here is Coq jargon for an argument on the left of the
colon in an [Inductive] definition; "index" is used to refer to
arguments on the right of the colon.) *)
(** We can think of the definition of [ev] as defining a Coq property
[ev : nat -> Prop], together with theorems [ev_0 : ev 0] and
[ev_SS : forall n, ev n -> ev (S (S n))]. Such "constructor
theorems" have the same status as proven theorems. In particular,
we can use Coq's [apply] tactic with the rule names to prove [ev]
for particular numbers... *)
Theorem ev_4 : ev 4.
Proof. apply ev_SS. apply ev_SS. apply ev_0. Qed.
(** ... or we can use function application syntax: *)
Theorem ev_4' : ev 4.
Proof. apply (ev_SS 2 (ev_SS 0 ev_0)). Qed.
(** We can also prove theorems that have hypotheses involving [ev]. *)
Theorem ev_plus4 : forall n, ev n -> ev (4 + n).
Proof.
intros n. simpl. intros Hn.
apply ev_SS. apply ev_SS. apply Hn.
Qed.
(** More generally, we can show that any number multiplied by 2 is even: *)
(** **** Exercise: 1 star (ev_double) *)
Theorem ev_double : forall n,
ev (double n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** * Using Evidence in Proofs *)
(** Besides _constructing_ evidence that numbers are even, we can also
_reason about_ such evidence.
Introducing [ev] with an [Inductive] declaration tells Coq not
only that the constructors [ev_0] and [ev_SS] are valid ways to
build evidence that some number is even, but also that these two
constructors are the _only_ ways to build evidence that numbers
are even (in the sense of [ev]). *)
(** In other words, if someone gives us evidence [E] for the assertion
[ev n], then we know that [E] must have one of two shapes:
- [E] is [ev_0] (and [n] is [O]), or
- [E] is [ev_SS n' E'] (and [n] is [S (S n')], where [E'] is
evidence for [ev n']). *)
(** This suggests that it should be possible to analyze a hypothesis
of the form [ev n] much as we do inductively defined data
structures; in particular, it should be possible to argue by
_induction_ and _case analysis_ on such evidence. Let's look at a
few examples to see what this means in practice. *)
(** ** Inversion on Evidence *)
(** Subtracting two from an even number yields another even number.
We can easily prove this claim with the techniques that we've
already seen, provided that we phrase it in the right way. If we
state it in terms of [evenb], for instance, we can proceed by a
simple case analysis on [n]: *)
Theorem evenb_minus2: forall n,
evenb n = true -> evenb (pred (pred n)) = true.
Proof.
intros [ | [ | n' ] ].
- (* n = 0 *) reflexivity.
- (* n = 1; contradiction *) intros H. inversion H.
- (* n = n' + 2 *) simpl. intros H. apply H.
Qed.
(** We can state the same claim in terms of [ev], but this quickly
leads us to an obstacle: Since [ev] is defined inductively --
rather than as a function -- Coq doesn't know how to simplify a
goal involving [ev n] after case analysis on [n]. As a
consequence, the same proof strategy fails: *)
Theorem ev_minus2: forall n,
ev n -> ev (pred (pred n)).
Proof.
intros [ | [ | n' ] ].
- (* n = 0 *) simpl. intros _. apply ev_0.
- (* n = 1; we're stuck! *) simpl.
Abort.
(** The solution is to perform case analysis on the evidence that [ev
n] _directly_. By the definition of [ev], there are two cases to
consider:
- If that evidence is of the form [ev_0], we know that [n = 0].
Therefore, it suffices to show that [ev (pred (pred 0))] holds.
By the definition of [pred], this is equivalent to showing that
[ev 0] holds, which directly follows from [ev_0].
- Otherwise, that evidence must have the form [ev_SS n' E'], where
[n = S (S n')] and [E'] is evidence for [ev n']. We must then
show that [ev (pred (pred (S (S n'))))] holds, which, after
simplification, follows directly from [E']. *)
(** We can invoke this kind of argument in Coq using the [inversion]
tactic. Besides allowing us to reason about equalities involving
constructors, [inversion] provides a case-analysis principle for
inductively defined propositions. When used in this way, its
syntax is similar to [destruct]: We pass it a list of identifiers
separated by [|] characters to name the arguments to each of the
possible constructors. For instance: *)
Theorem ev_minus2 : forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
inversion E as [| n' E'].
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'. Qed.
(** Note that, in this particular case, it is also possible to replace
[inversion] by [destruct]: *)
Theorem ev_minus2' : forall n,
ev n -> ev (pred (pred n)).
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0 *) simpl. apply ev_0.
- (* E = ev_SS n' E' *) simpl. apply E'. Qed.
(** The difference between the two forms is that [inversion] is more
convenient when used on a hypothesis that consists of an inductive
property applied to a complex expression (as opposed to a single
variable). Here's is a concrete example. Suppose that we wanted
to prove the following variation of [ev_minus2]: *)
Theorem evSS_ev : forall n,
ev (S (S n)) -> ev n.
(** Intuitively, we know that evidence for the hypothesis cannot
consist just of the [ev_0] constructor, since [O] and [S] are
different constructors of the type [nat]; hence, [ev_SS] is the
only case that applies. Unfortunately, [destruct] is not smart
enough to realize this, and it still generates two subgoals. Even
worse, in doing so, it keeps the final goal unchanged, failing to
provide any useful information for completing the proof. *)
Proof.
intros n E.
destruct E as [| n' E'].
- (* E = ev_0. *)
(* We must prove that [n] is even from no assumptions! *)
Abort.
(** What happened, exactly? Calling [destruct] has the effect of
replacing all occurrences of the property argument by the values
that correspond to each constructor. This is enough in the case
of [ev_minus2'] because that argument, [n], is mentioned directly
in the final goal. However, it doesn't help in the case of
[evSS_ev] since the term that gets replaced ([S (S n)]) is not
mentioned anywhere. *)
(** The [inversion] tactic, on the other hand, can detect (1) that the
first case does not apply, and (2) that the [n'] that appears on
the [ev_SS] case must be the same as [n]. This allows us to
complete the proof: *)
Theorem evSS_ev : forall n,
ev (S (S n)) -> ev n.
Proof.
intros n E.
inversion E as [| n' E'].
(* We are in the [E = ev_SS n' E'] case now. *)
apply E'.
Qed.
(** By using [inversion], we can also apply the principle of explosion
to "obviously contradictory" hypotheses involving inductive
properties. For example: *)
Theorem one_not_even : ~ ev 1.
Proof.
intros H. inversion H. Qed.
(** **** Exercise: 1 star (inversion_practice) *)
(** Prove the following results using [inversion]. *)
Theorem SSSSev__even : forall n,
ev (S (S (S (S n)))) -> ev n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem even5_nonsense :
ev 5 -> 2 + 2 = 9.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The way we've used [inversion] here may seem a bit
mysterious at first. Until now, we've only used [inversion] on
equality propositions, to utilize injectivity of constructors or
to discriminate between different constructors. But we see here
that [inversion] can also be applied to analyzing evidence for
inductively defined propositions.
Here's how [inversion] works in general. Suppose the name [I]
refers to an assumption [P] in the current context, where [P] has
been defined by an [Inductive] declaration. Then, for each of the
constructors of [P], [inversion I] generates a subgoal in which
[I] has been replaced by the exact, specific conditions under
which this constructor could have been used to prove [P]. Some of
these subgoals will be self-contradictory; [inversion] throws
these away. The ones that are left represent the cases that must
be proved to establish the original goal. For those, [inversion]
adds all equations into the proof context that must hold of the
arguments given to [P] (e.g., [S (S n') = n] in the proof of
[evSS_ev]). *)
(* ####################################################### *)
(** ** Induction on Evidence *)
(** The [ev_double] exercise above shows that our new notion of
evenness is implied by the two earlier ones (since, by
[even_bool_prop], we already know that those are equivalent to
each other). To show that all three coincide, we just need the
following lemma: *)
Lemma ev_even : forall n,
ev n -> exists k, n = double k.
Proof.
(** We could try to proceed by case analysis or induction on [n]. But
since [ev] is mentioned in a premise, this strategy would probably
lead to a dead end, as in the previous section. Thus, it seems
better to first try inversion on the evidence for [ev]. Indeed,
the first case can be solved trivially. *)
intros n E. inversion E as [| n' E'].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E' *) simpl.
(** Unfortunately, the second case is harder. We need to show [exists
k, S (S n') = double k], but the only available assumption is
[E'], which states that [ev n'] holds. Since this isn't directly
useful, it seems that we are stuck and that performing case
analysis on [E] was a waste of time.
If we look more closely at our second goal, however, we can see
that something interesting happened: By performing case analysis
on [E], we were able to reduce the original result to an similar
one that involves a _different_ piece of evidence for [ev]: [E'].
More formally, we can finish our proof by showing that
exists k', n' = double k',
which is the same as the original statement, but with [n'] instead
of [n]. Indeed, it is not difficult to convince Coq that this
intermediate result suffices. *)
assert (I : (exists k', n' = double k') ->
(exists k, S (S n') = double k)).
{ intros [k' Hk']. rewrite Hk'. exists (S k').
reflexivity. }
apply I. (* reduce the original goal to the new one *)
(** If this looks familiar, it is no coincidence: We've encountered
similar problems in the [Induction] chapter, when trying to use
case analysis to prove results that required induction. And once
again the solution is... induction!
The behavior of [induction] on evidence is the same as its
behavior on data: It causes Coq to generate one subgoal for each
constructor that could have used to build that evidence, while
providing an induction hypotheses for each recursive occurrence of
the property in question.
Let's try our current lemma again: *)
Abort.
Lemma ev_even : forall n,
ev n -> exists k, n = double k.
Proof.
intros n E.
induction E as [|n' E' IH].
- (* E = ev_0 *)
exists 0. reflexivity.
- (* E = ev_SS n' E'
with IH : exists k', n' = double k' *)
destruct IH as [k' Hk'].
rewrite Hk'. exists (S k'). reflexivity.
Qed.
(** Here, we can see that Coq produced an [IH] that corresponds to
[E'], the single recursive occurrence of [ev] in its own
definition. Since [E'] mentions [n'], the induction hypothesis
talks about [n'], as opposed to [n] or some other number. *)
(** The equivalence between the second and third definitions of
evenness now follows. *)
Theorem ev_even_iff : forall n,
ev n <-> exists k, n = double k.
Proof.
intros n. split.
- (* -> *) apply ev_even.
- (* <- *) intros [k Hk]. rewrite Hk. apply ev_double.
Qed.
(** As we will see in later chapters, induction on evidence is a
recurring technique when studying the semantics of programming
languages, where many properties of interest are defined
inductively. The following exercises provide simple examples of
this technique, to help you familiarize yourself with it. *)
(** **** Exercise: 2 stars (ev_sum) *)
Theorem ev_sum : forall n m, ev n -> ev m -> ev (n + m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (ev_alternate) *)
(** In general, there may be multiple ways of defining a
property inductively. For example, here's a (slightly contrived)
alternative definition for [ev]: *)
Inductive ev' : nat -> Prop :=
| ev'_0 : ev' 0
| ev'_2 : ev' 2
| ev'_sum : forall n m, ev' n -> ev' m -> ev' (n + m).
(** Prove that this definition is logically equivalent to
the old one. *)
Theorem ev'_ev : forall n, ev' n <-> ev n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, recommended (ev_ev__ev) *)
(** Finding the appropriate thing to do induction on is a
bit tricky here: *)
Theorem ev_ev__ev : forall n m,
ev (n+m) -> ev n -> ev m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (ev_plus_plus) *)
(** This exercise just requires applying existing lemmas. No
induction or even case analysis is needed, though some of the
rewriting may be tedious. *)
Theorem ev_plus_plus : forall n m p,
ev (n+m) -> ev (n+p) -> ev (m+p).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** * Inductive Relations *)
(** A proposition parameterized by a number (such as [ev])
can be thought of as a _property_ -- i.e., it defines
a subset of [nat], namely those numbers for which the proposition
is provable. In the same way, a two-argument proposition can be
thought of as a _relation_ -- i.e., it defines a set of pairs for
which the proposition is provable. *)
Module LeModule.
(** One useful example is the "less than or equal to"
relation on numbers. *)
(** The following definition should be fairly intuitive. It
says that there are two ways to give evidence that one number is
less than or equal to another: either observe that they are the
same number, or give evidence that the first is less than or equal
to the predecessor of the second. *)
Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** Proofs of facts about [<=] using the constructors [le_n] and
[le_S] follow the same patterns as proofs about properties, like
[ev] above. We can [apply] the constructors to prove [<=]
goals (e.g., to show that [3<=3] or [3<=6]), and we can use
tactics like [inversion] to extract information from [<=]
hypotheses in the context (e.g., to prove that [(2 <= 1) -> 2+2=5].) *)
(** Here are some sanity checks on the definition. (Notice that,
although these are the same kind of simple "unit tests" as we gave
for the testing functions we wrote in the first few lectures, we
must construct their proofs explicitly -- [simpl] and
[reflexivity] don't do the job, because the proofs aren't just a
matter of simplifying computations.) *)
Theorem test_le1 :
3 <= 3.
Proof.
(* WORKED IN CLASS *)
apply le_n. Qed.
Theorem test_le2 :
3 <= 6.
Proof.
(* WORKED IN CLASS *)
apply le_S. apply le_S. apply le_S. apply le_n. Qed.
Theorem test_le3 :
(2 <= 1) -> 2 + 2 = 5.
Proof.
(* WORKED IN CLASS *)
intros H. inversion H. inversion H2. Qed.
(** The "strictly less than" relation [n < m] can now be defined
in terms of [le]. *)
End LeModule.
Definition lt (n m:nat) := le (S n) m.
Notation "m < n" := (lt m n).
(** Here are a few more simple relations on numbers: *)
Inductive square_of : nat -> nat -> Prop :=
sq : forall n:nat, square_of n (n * n).
Inductive next_nat : nat -> nat -> Prop :=
| nn : forall n:nat, next_nat n (S n).
Inductive next_even : nat -> nat -> Prop :=
| ne_1 : forall n, ev (S n) -> next_even n (S n)
| ne_2 : forall n, ev (S (S n)) -> next_even n (S (S n)).
(** **** Exercise: 2 stars, recommended (total_relation) *)
(** Define an inductive binary relation [total_relation] that holds
between every pair of natural numbers. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (empty_relation) *)
(** Define an inductive binary relation [empty_relation] (on numbers)
that never holds. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (le_exercises) *)
(** Here are a number of facts about the [<=] and [<] relations that
we are going to need later in the course. The proofs make good
practice exercises. *)
Lemma le_trans : forall m n o, m <= n -> n <= o -> m <= o.
Proof.
(* FILL IN HERE *) Admitted.
Theorem O_le_n : forall n,
0 <= n.
Proof.
(* FILL IN HERE *) Admitted.
Theorem n_le_m__Sn_le_Sm : forall n m,
n <= m -> S n <= S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem Sn_le_Sm__n_le_m : forall n m,
S n <= S m -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem le_plus_l : forall a b,
a <= a + b.
Proof.
(* FILL IN HERE *) Admitted.
Theorem plus_lt : forall n1 n2 m,
n1 + n2 < m ->
n1 < m /\ n2 < m.
Proof.
unfold lt.
(* FILL IN HERE *) Admitted.
Theorem lt_S : forall n m,
n < m ->
n < S m.
Proof.
(* FILL IN HERE *) Admitted.
Theorem leb_complete : forall n m,
leb n m = true -> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(** Hint: The next one may be easiest to prove by induction on [m]. *)
Theorem leb_correct : forall n m,
n <= m ->
leb n m = true.
Proof.
(* FILL IN HERE *) Admitted.
(** Hint: This theorem can easily be proved without using [induction]. *)
Theorem leb_true_trans : forall n m o,
leb n m = true -> leb m o = true -> leb n o = true.
Proof.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 2 stars, optional (leb_iff) *)
Theorem leb_iff : forall n m,
leb n m = true <-> n <= m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module R.
(** **** Exercise: 3 stars, recommended (R_provability2) *)
(** We can define three-place relations, four-place relations,
etc., in just the same way as binary relations. For example,
consider the following three-place relation on numbers: *)
Inductive R : nat -> nat -> nat -> Prop :=
| c1 : R 0 0 0
| c2 : forall m n o, R m n o -> R (S m) n (S o)
| c3 : forall m n o, R m n o -> R m (S n) (S o)
| c4 : forall m n o, R (S m) (S n) (S (S o)) -> R m n o
| c5 : forall m n o, R m n o -> R n m o.
(** - Which of the following propositions are provable?
- [R 1 1 2]
- [R 2 2 6]
- If we dropped constructor [c5] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
- If we dropped constructor [c4] from the definition of [R],
would the set of provable propositions change? Briefly (1
sentence) explain your answer.
* FILL IN HERE *
[]
*)
(** **** Exercise: 3 stars, optional (R_fact) *)
(** The relation [R] above actually encodes a familiar function.
Figure out which function; then state and prove this equivalence
in Coq? *)
Definition fR : nat -> nat -> nat :=
(* FILL IN HERE *) admit.
Theorem R_equiv_fR : forall m n o, R m n o <-> fR m n = o.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End R.
(** **** Exercise: 4 stars, advanced (subsequence) *)
(** A list is a _subsequence_ of another list if all of the elements
in the first list occur in the same order in the second list,
possibly with some extra elements in between. For example,
[1;2;3]
is a subsequence of each of the lists
[1;2;3]
[1;1;1;2;2;3]
[1;2;7;3]
[5;6;1;9;9;2;7;3;8]
but it is _not_ a subsequence of any of the lists
[1;2]
[1;3]
[5;6;2;1;7;3;8]
- Define an inductive proposition [subseq] on [list nat] that
captures what it means to be a subsequence. (Hint: You'll need
three cases.)
- Prove [subseq_refl] that subsequence is reflexive, that is,
any list is a subsequence of itself.
- Prove [subseq_app] that for any lists [l1], [l2], and [l3],
if [l1] is a subsequence of [l2], then [l1] is also a subsequence
of [l2 ++ l3].
- (Optional, harder) Prove [subseq_trans] that subsequence is
transitive -- that is, if [l1] is a subsequence of [l2] and [l2]
is a subsequence of [l3], then [l1] is a subsequence of [l3].
Hint: choose your induction carefully!
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (R_provability) *)
(** Suppose we give Coq the following definition:
Inductive R : nat -> list nat -> Prop :=
| c1 : R 0 []
| c2 : forall n l, R n l -> R (S n) (n :: l)
| c3 : forall n l, R (S n) l -> R n l.
Which of the following propositions are provable?
- [R 2 [1;0]]
- [R 1 [1;2;1;0]]
- [R 6 [3;2;1;0]]
*)
(** [] *)
(* ############################################################ *)
(** * Case Study: Regular Expressions *)
(** The [ev] property provides a simple example for illustrating
inductive definitions and the basic techniques for reasoning about
them, but it is not terribly exciting -- after all, it is
equivalent to the two non-inductive of evenness that we had
already seen, and does not seem to offer any concrete benefit over
them. To give a better sense of the power of inductive
definitions, we now show how to use them to model a classic
concept in computer science: _regular expressions_. *)
(** Regular expressions are a simple language for describing strings,
defined as elements of the following inductive type. (The names
of the constructors should become clear once we explain their
meaning below.) *)
Inductive reg_exp (T : Type) : Type :=
| EmptySet : reg_exp T
| EmptyStr : reg_exp T
| Char : T -> reg_exp T
| App : reg_exp T -> reg_exp T -> reg_exp T
| Union : reg_exp T -> reg_exp T -> reg_exp T
| Star : reg_exp T -> reg_exp T.
Arguments EmptySet {T}.
Arguments EmptyStr {T}.
Arguments Char {T} _.
Arguments App {T} _ _.
Arguments Union {T} _ _.
Arguments Star {T} _.
(** Note that this definition is _polymorphic_: Regular expressions in
[reg_exp T] describe strings with characters drawn from [T] --
that is, lists of elements of [T]. (We depart slightly from
standard practice in that we do not require the type [T] to be
finite. This results in a somewhat different theory of regular
expressions, but the difference is not significant for our
purposes.)
We connect regular expressions and strings via the following
rules, which define when a regular expression _matches_ some
string:
- The expression [EmptySet] does not match any string.
- The expression [EmptyStr] matches the empty string [[]].
- The expression [Char x] matches the one-character string [[x]].
- If [re1] matches [s1], and [re2] matches [s2], then [App re1
re2] matches [s1 ++ s2].
- If at least one of [re1] and [re2] matches [s], then [Union re1
re2] matches [s].
- Finally, if we can write some string [s] as the concatenation of
a sequence of strings [s = s_1 ++ ... ++ s_k], and the
expression [re] matches each one of the strings [s_i], then
[Star re] matches [s]. (As a special case, the sequence of
strings may be empty, so [Star re] always matches the empty
string [[]] no matter what [re] is.) *)
(** We can easily translate this informal definition into an
[Inductive] one as follows: *)
Inductive exp_match {T} : list T -> reg_exp T -> Prop :=
| MEmpty : exp_match [] EmptyStr
| MChar : forall x, exp_match [x] (Char x)
| MApp : forall s1 re1 s2 re2,
exp_match s1 re1 ->
exp_match s2 re2 ->
exp_match (s1 ++ s2) (App re1 re2)
| MUnionL : forall s1 re1 re2,
exp_match s1 re1 ->
exp_match s1 (Union re1 re2)
| MUnionR : forall re1 s2 re2,
exp_match s2 re2 ->
exp_match s2 (Union re1 re2)
| MStar0 : forall re, exp_match [] (Star re)
| MStarApp : forall s1 s2 re,
exp_match s1 re ->
exp_match s2 (Star re) ->
exp_match (s1 ++ s2) (Star re).
(** Once again, for readability, we can also display this definition
using inference-rule notation. At the same time, let's introduce
a more readable infix notation. *)
Notation "s =~ re" := (exp_match s re) (at level 80).
(**
---------------- (MEmpty)
[] =~ EmptyStr
--------------- (MChar)
[x] =~ Char x
s1 =~ re1 s2 =~ re2
------------------------- (MApp)
s1 ++ s2 =~ App re1 re2
s1 =~ re1
--------------------- (MUnionL)
s1 =~ Union re1 re2
s2 =~ re2
--------------------- (MUnionR)
s2 =~ Union re1 re2
--------------- (MStar0)
[] =~ Star re
s1 =~ re s2 =~ Star re
--------------------------- (MStarApp)
s1 ++ s2 =~ Star re
*)
(** Notice that these rules are not _quite_ the same as the informal
ones that we gave at the beginning of the section. First, we
don't need to include a rule explicitly stating that no string
matches [EmptySet]; we just don't happen to include any rule that
would have the effect of some string matching
[EmptySet]. (Indeed, the syntax of inductive definitions doesn't
even _allow_ us to give such a "negative rule.")
Furthermore, the informal rules for [Union] and [Star] correspond
to two constructors each: [MUnionL] / [MUnionR], and [MStar0] /
[MStarApp]. The result is logically equivalent to the original
rules, but more convenient to use in Coq, since the recursive
occurrences of [exp_match] are given as direct arguments to the
constructors, making it easier to perform induction on evidence.
(The [exp_match_ex1] and [exp_match_ex2] exercises below ask you
to prove that the constructors given in the inductive declaration
and the ones that would arise from a more literal transcription of
the informal rules are indeed equivalent.) *)
(* ############################################################ *)
(** Let's illustrate these rules with a few examples. *)
Example reg_exp_ex1 : [1] =~ Char 1.
Proof.
apply MChar.
Qed.
Example reg_exp_ex2 : [1; 2] =~ App (Char 1) (Char 2).
Proof.
apply (MApp [1] _ [2]).
- apply MChar.
- apply MChar.
Qed.
(** (Notice how the last example applies [MApp] to the strings [[1]]
and [[2]] directly. Since the goal mentions [[1; 2]] instead of
[[1] ++ [2]], Coq wouldn't be able to figure out how to split the
string on its own.)
Using [inversion], we can also show that certain strings do _not_
match a regular expression: *)
Example reg_exp_ex3 : ~ ([1; 2] =~ Char 1).
Proof.
intros H. inversion H.
Qed.
(** We can define helper functions to help write down regular
expressions. The [reg_exp_of_list] function constructs a regular
expression that matches exactly the list that it receives as an
argument: *)
Fixpoint reg_exp_of_list {T} (l : list T) :=
match l with
| [] => EmptyStr
| x :: l' => App (Char x) (reg_exp_of_list l')
end.
Example reg_exp_ex4 : [1; 2; 3] =~ reg_exp_of_list [1; 2; 3].
Proof.
simpl. apply (MApp [1]).
{ apply MChar. }
apply (MApp [2]).
{ apply MChar. }
apply (MApp [3]).
{ apply MChar. }
apply MEmpty.
Qed.
(** We can also prove general facts about [exp_match]. For instance,
the following lemma shows that every string [s] that matches [re]
also matches [Star re]. *)
Lemma MStar1 :
forall T s (re : reg_exp T) ,
s =~ re ->
s =~ Star re.
Proof.
intros T s re H.
rewrite <- (app_nil_r _ s).
apply (MStarApp s [] re).
- apply H.
- apply MStar0.
Qed.
(** (Note the use of [app_nil_r] to change the goal of the theorem to
exactly the same shape expected by [MStarApp].) *)
(** **** Exercise: 3 stars (exp_match_ex1) *)
(** The following lemmas show that the informal matching rules given
at the beginning of the chapter can be obtained from the formal
inductive definition. *)
Lemma empty_is_empty : forall T (s : list T),
~ (s =~ EmptySet).
Proof.
(* FILL IN HERE *) Admitted.
Lemma MUnion' : forall T (s : list T) (re1 re2 : reg_exp T),
s =~ re1 \/ s =~ re2 ->
s =~ Union re1 re2.
Proof.
(* FILL IN HERE *) Admitted.
(** The next lemma is stated in terms of the [fold] function from the
[Poly] chapter: If [ss : list (list T)] represents a sequence of
strings [s1, ..., sn], then [fold app ss []] is the result of
concatenating them all together. *)
Lemma MStar' : forall T (ss : list (list T)) (re : reg_exp T),
(forall s, In s ss -> s =~ re) ->
fold app ss [] =~ Star re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (reg_exp_of_list) *)
(** Prove that [reg_exp_of_list] satisfies the following
specification: *)
Lemma reg_exp_of_list_spec : forall T (s1 s2 : list T),
s1 =~ reg_exp_of_list s2 <-> s1 = s2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Since the definition of [exp_match] has a recursive
structure, we might expect that proofs involving regular
expressions will often require induction on evidence. For
example, suppose that we wanted to prove the following intuitive
result: If a regular expression [re] matches some string [s], then
all elements of [s] must occur somewhere in [re]. To state this
theorem, we first define a function [re_chars] that lists all
characters that occur in a regular expression: *)
Fixpoint re_chars {T} (re : reg_exp T) : list T :=
match re with
| EmptySet => []
| EmptyStr => []
| Char x => [x]
| App re1 re2 => re_chars re1 ++ re_chars re2
| Union re1 re2 => re_chars re1 ++ re_chars re2
| Star re => re_chars re
end.
(** We can then phrase our theorem as follows: *)
Theorem in_re_match : forall T (s : list T) (re : reg_exp T) (x : T),
s =~ re ->
In x s ->
In x (re_chars re).
Proof.
intros T s re x Hmatch Hin.
induction Hmatch
as [
|x'
|s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2 re2 Hmatch IH
|re|s1 s2 re Hmatch1 IH1 Hmatch2 IH2].
(* WORKED IN CLASS *)
- (* MEmpty *)
apply Hin.
- (* MChar *)
apply Hin.
- simpl. rewrite in_app_iff in *.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
left. apply (IH1 Hin).
+ (* In x s2 *)
right. apply (IH2 Hin).
- (* MUnionL *)
simpl. rewrite in_app_iff.
left. apply (IH Hin).
- (* MUnionR *)
simpl. rewrite in_app_iff.
right. apply (IH Hin).
- (* MStar0 *)
destruct Hin.
(** Something interesting happens in the [MStarApp] case. We obtain
_two_ induction hypotheses: One that applies when [x] occurs in
[s1] (which matches [re]), and a second one that applies when [x]
occurs in [s2] (which matches [Star re]). This is a good
illustration of why we need induction on evidence for [exp_match],
as opposed to [re]: The latter would only provide an induction
hypothesis for strings that match [re], which would not allow us
to reason about the case [In x s2]. *)
- (* MStarApp *)
simpl. rewrite in_app_iff in Hin.
destruct Hin as [Hin | Hin].
+ (* In x s1 *)
apply (IH1 Hin).
+ (* In x s2 *)
apply (IH2 Hin).
Qed.
(** **** Exercise: 4 stars (re_not_empty) *)
(** Write a recursive function [re_not_empty] that tests whether a
regular expression matches some string. Prove that your function
is correct. *)
Fixpoint re_not_empty {T} (re : reg_exp T) : bool :=
(* FILL IN HERE *) admit.
Lemma re_not_empty_correct : forall T (re : reg_exp T),
(exists s, s =~ re) <-> re_not_empty re = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ** The [remember] Tactic *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave you
unable to complete the proof. Here's an example: *)
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
(** Just doing an [inversion] on [H1] won't get us very far in the
recursive cases. (Try it!). So we need induction. Here is a naive
first attempt: *)
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** But now, although we get seven cases (as we would expect from the
definition of [exp_match]), we lost a very important bit of
information from [H1]: the fact that [s1] matched something of the
form [Star re]. This means that we have to give proofs for _all_
seven constructors of this definition, even though all but two of
them ([MStar0] and [MStarApp]) are contradictory. We can still
get the proof to go through for a few constructors, such as
[MEmpty]... *)
- (* MEmpty *)
simpl. intros H. apply H.
(** ... but most of them get stuck. For [MChar], for instance, we
must show that
s2 =~ Char x' -> x' :: s2 =~ Char x',
which is clearly impossible. *)
- (* MChar. Stuck... *)
Abort.
(** The problem is that [induction] over a Prop hypothesis only works
properly with hypotheses that are completely general, i.e., ones
in which all the arguments are variables, as opposed to more
complex expressions, such as [Star re]. In this respect it
behaves more like [destruct] than like [inversion].
We can solve this problem by generalizing over the problematic
expressions with an explicit equality: *)
Lemma star_app: forall T (s1 s2 : list T) (re re' : reg_exp T),
s1 =~ re' ->
re' = Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
(** We can now proceed by performing induction over evidence directly,
because the argument to the first hypothesis is sufficiently
general, which means that we can discharge most cases by inverting
the [re' = Star re] equality in the context.
This idiom is so common that Coq provides a tactic to
automatically generate such equations for us, avoiding thus the
need for changing the statements of our theorems. Calling
[remember e as x] causes Coq to (1) replace all occurrences of the
expression [e] by the variable [x], and (2) add an equation [x =
e] to the context. Here's how we can use it to show the above
result: *)
Abort.
Lemma star_app: forall T (s1 s2 : list T) (re : reg_exp T),
s1 =~ Star re ->
s2 =~ Star re ->
s1 ++ s2 =~ Star re.
Proof.
intros T s1 s2 re H1.
remember (Star re) as re'.
(** We now have [Heqre' : re' = Star re]. *)
generalize dependent s2.
induction H1
as [|x'|s1 re1 s2' re2 Hmatch1 IH1 Hmatch2 IH2
|s1 re1 re2 Hmatch IH|re1 s2' re2 Hmatch IH
|re''|s1 s2' re'' Hmatch1 IH1 Hmatch2 IH2].
(** The [Heqre'] is contradictory in most cases, which allows us to
conclude immediately. *)
- (* MEmpty *) inversion Heqre'.
- (* MChar *) inversion Heqre'.
- (* MApp *) inversion Heqre'.
- (* MUnionL *) inversion Heqre'.
- (* MUnionR *) inversion Heqre'.
(** In the interesting cases (those that correspond to [Star]), we can
proceed as usual. Note that the induction hypothesis [IH2] on the
[MStarApp] case mentions an additional premise [Star re'' = Star
re'], which results from the equality generated by [remember]. *)
- (* MStar0 *)
inversion Heqre'. intros s H. apply H.
- (* MStarApp *)
inversion Heqre'. rewrite H0 in IH2, Hmatch1.
intros s2 H1. rewrite <- app_assoc.
apply MStarApp.
+ apply Hmatch1.
+ apply IH2.
* reflexivity.
* apply H1.
Qed.
(** **** Exercise: 4 stars (exp_match_ex2) *)
(** The [MStar''] lemma below (combined with its converse, the
[MStar'] exercise above), shows that our definition of [exp_match]
for [Star] is equivalent to the informal one given previously. *)
Lemma MStar'' : forall T (s : list T) (re : reg_exp T),
s =~ Star re ->
exists ss : list (list T),
s = fold app ss []
/\ forall s', In s' ss -> s' =~ re.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ############################################################ *)
(** **** Exercise: 5 stars, advanced (pumping) *)
Module Pumping.
(** One of the first interesting theorems in the theory of regular
expressions is the so-called _pumping lemma_, which states,
informally, that any sufficiently long string [s] matching a
regular expression [re] can be "pumped" by repeating some middle
section of [s] an arbitrary number of times to produce a new
string also matching [re]. *)
(** To begin, we need to define "sufficiently long." Since we are
working in a constructive logic, we actually need to be able to
calculate, for each regular expression [re], the minimum length
for strings [s] to guarantee "pumpability." *)
Fixpoint pumping_constant {T} (re : reg_exp T) : nat :=
match re with
| EmptySet => 0
| EmptyStr => 1
| Char _ => 2
| App re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Union re1 re2 =>
pumping_constant re1 + pumping_constant re2
| Star _ => 1
end.
(** Next, it is useful to define an auxiliary function that repeats a
string (appends it to itself) some number of times. *)
Fixpoint napp {T} (n : nat) (l : list T) : list T :=
match n with
| 0 => []
| S n' => l ++ napp n' l
end.
Lemma napp_plus: forall T (n m : nat) (l : list T),
napp (n + m) l = napp n l ++ napp m l.
Proof.
intros T n m l.
induction n as [|n IHn].
- reflexivity.
- simpl. rewrite IHn, app_assoc. reflexivity.
Qed.
(** Now, the pumping lemma itself says that, if [s =~ re] and if the
length of [s] is at least the pumping constant of [re], then [s]
can be split into three substrings [s1 ++ s2 ++ s3] in such a way
that [s2] can be repeated any number of times and the result, when
combined with [s1] and [s3] will still match [re]. Since [s2] is
also guaranteed not to be the empty string, this gives us
a (constructive!) way to generate strings matching [re] that are
as long as we like. *)
Lemma pumping : forall T (re : reg_exp T) s,
s =~ re ->
pumping_constant re <= length s ->
exists s1 s2 s3,
s = s1 ++ s2 ++ s3 /\
s2 <> [] /\
forall m, s1 ++ napp m s2 ++ s3 =~ re.
(** To streamline the proof (which you are to fill in), the [omega]
tactic, which is enabled by the following [Require], is helpful in
several places for automatically completing tedious low-level
arguments involving equalities or inequalities over natural
numbers. We'll return to [omega] in a later chapter, but feel
free to experiment with it now if you like. The first case of the
induction gives an example of how it is used. *)
Require Import Coq.omega.Omega.
Proof.
intros T re s Hmatch.
induction Hmatch
as [ | x | s1 re1 s2 re2 Hmatch1 IH1 Hmatch2 IH2
| s1 re1 re2 Hmatch IH | re1 s2 re2 Hmatch IH
| re | s1 s2 re Hmatch1 IH1 Hmatch2 IH2 ].
- (* MEmpty *)
simpl. omega.
(* FILL IN HERE *) Admitted.
End Pumping.
(** [] *)
(* ####################################################### *)
(** * Improving Reflection *)
(** We've seen in the [Logic] chapter that we often need to
relate boolean computations to statements in
[Prop]. Unfortunately, performing this conversion by hand can
result in tedious proof scripts. Consider the proof of the
following theorem: *)
Theorem filter_not_empty_In : forall n l,
filter (beq_nat n) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (beq_nat n m) eqn:H.
+ (* beq_nat n m = true *)
intros _. rewrite beq_nat_true_iff in H. rewrite H.
left. reflexivity.
+ (* beq_nat n m = false *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** In the first branch after [destruct], we explicitly
apply the [beq_nat_true_iff] lemma to the equation generated by
destructing [beq_nat n m], to convert the assumption [beq_nat n m
= true] into the assumption [n = m], which is what we need to
complete this case.
We can streamline this proof by defining an inductive proposition
that yields a better case-analysis principle for [beq_nat n
m]. Instead of generating an equation such as [beq_nat n m =
true], which is not directly useful, this principle gives us right
away the assumption we need: [n = m]. We'll actually define
something a bit more general, which can be used with arbitrary
properties (and not just equalities): *)
Inductive reflect (P : Prop) : bool -> Prop :=
| ReflectT : P -> reflect P true
| ReflectF : ~ P -> reflect P false.
(** The [reflect] property takes two arguments: a proposition
[P] and a boolean [b]. Intuitively, it states that the property
[P] is _reflected_ in (i.e., equivalent to) the boolean [b]: [P]
holds if and only if [b = true]. To see this, notice that, by
definition, the only way we can produce evidence that [reflect P
true] holds is by showing that [P] is true and using the
[ReflectT] constructor. If we invert this statement, this means
that it should be possible to extract evidence for [P] from a
proof of [reflect P true]. Conversely, the only way to show
[reflect P false] is by combining evidence for [~ P] with the
[ReflectF] constructor.
It is easy to formalize this intuition and show that the two
statements are indeed equivalent: *)
Theorem iff_reflect : forall P b, (P <-> b = true) -> reflect P b.
Proof.
intros P [] H.
- apply ReflectT. rewrite H. reflexivity.
- apply ReflectF. rewrite H. intros H'. inversion H'.
Qed.
(** **** Exercise: 2 stars, recommended (reflect_iff) *)
Theorem reflect_iff : forall P b, reflect P b -> (P <-> b = true).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The advantage of [reflect] over the normal "if and only if"
connective is that, by destructing a hypothesis or lemma of the
form [reflect P b], we can perform case analysis on [b] while at
the same time generating appropriate hypothesis in the two
branches ([P] in the first subgoal and [~ P] in the second).
To use [reflect] to produce a better proof of
[filter_not_empty_In], we begin by recasting the
[beq_nat_iff_true] lemma into a more convenient form in terms of
[reflect]: *)
Lemma beq_natP : forall n m, reflect (n = m) (beq_nat n m).
Proof.
intros n m.
apply iff_reflect. rewrite beq_nat_true_iff. reflexivity.
Qed.
(** The new proof of [filter_not_empty_In] now goes as follows.
Notice how the calls to [destruct] and [apply] are combined into a
single call to [destruct]. (To see this clearly, look at the two
proofs of [filter_not_empty_In] in your Coq browser and observe
the differences in proof state at the beginning of the first case
of the [destruct].) *)
Theorem filter_not_empty_In' : forall n l,
filter (beq_nat n) l <> [] ->
In n l.
Proof.
intros n l. induction l as [|m l' IHl'].
- (* l = [] *)
simpl. intros H. apply H. reflexivity.
- (* l = m :: l' *)
simpl. destruct (beq_natP n m) as [H | H].
+ (* n = m *)
intros _. rewrite H. left. reflexivity.
+ (* n <> m *)
intros H'. right. apply IHl'. apply H'.
Qed.
(** Although this technique arguably gives us only a small gain
in convenience for this particular proof, using [reflect]
consistently often leads to shorter and clearer proofs. We'll see
many more examples where [reflect] comes in handy in later
chapters.
The use of the [reflect] property was popularized by _SSReflect_,
a Coq library that has been used to formalize important results in
mathematics, including as the 4-color theorem and the
Feit-Thompson theorem. The name SSReflect stands for _small-scale
reflection_, i.e., the pervasive use of reflection to simplify
small proof steps with boolean computations. *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, recommended (palindromes) *)
(** A palindrome is a sequence that reads the same backwards as
forwards.
- Define an inductive proposition [pal] on [list X] that
captures what it means to be a palindrome. (Hint: You'll need
three cases. Your definition should be based on the structure
of the list; just having a single constructor
c : forall l, l = rev l -> pal l
may seem obvious, but will not work very well.)
- Prove [pal_app_rev] that
forall l, pal (l ++ rev l).
- Prove [pal_rev] that
forall l, pal l -> l = rev l.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, optional (palindrome_converse) *)
(** Again, the converse direction is significantly more difficult, due
to the lack of evidence. Using your definition of [pal] from the
previous exercise, prove that
forall l, l = rev l -> pal l.
*)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (filter_challenge) *)
(** Let's prove that our definition of [filter] from the [Poly]
chapter matches an abstract specification. Here is the
specification, written out informally in English:
A list [l] is an "in-order merge" of [l1] and [l2] if it contains
all the same elements as [l1] and [l2], in the same order as [l1]
and [l2], but possibly interleaved. For example,
[1;4;6;2;3]
is an in-order merge of
[1;6;2]
and
[4;3].
Now, suppose we have a set [X], a function [test: X->bool], and a
list [l] of type [list X]. Suppose further that [l] is an
in-order merge of two lists, [l1] and [l2], such that every item
in [l1] satisfies [test] and no item in [l2] satisfies test. Then
[filter test l = l1].
Translate this specification into a Coq theorem and prove
it. (You'll need to begin by defining what it means for one list
to be a merge of two others. Do this with an inductive relation,
not a [Fixpoint].) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (filter_challenge_2) *)
(** A different way to characterize the behavior of [filter] goes like
this: Among all subsequences of [l] with the property that [test]
evaluates to [true] on all their members, [filter test l] is the
longest. Formalize this claim and prove it. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 4 stars, advanced (NoDup) *)
(** Recall the definition of the [In] property from the [Logic]
chapter, which asserts that a value [x] appears at least once in a
list [l]: *)
(* Fixpoint In (A : Type) (x : A) (l : list A) : Prop :=
match l with
| [] => False
| x' :: l' => x' = x \/ In A x l'
end *)
(** Your first task is to use [In] to define a proposition [disjoint X
l1 l2], which should be provable exactly when [l1] and [l2] are
lists (with elements of type X) that have no elements in
common. *)
(* FILL IN HERE *)
(** Next, use [In] to define an inductive proposition [NoDup X
l], which should be provable exactly when [l] is a list (with
elements of type [X]) where every member is different from every
other. For example, [NoDup nat [1;2;3;4]] and [NoDup
bool []] should be provable, while [NoDup nat [1;2;1]] and
[NoDup bool [true;true]] should not be. *)
(* FILL IN HERE *)
(** Finally, state and prove one or more interesting theorems relating
[disjoint], [NoDup] and [++] (list append). *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, recommended (nostutter) *)
(** Formulating inductive definitions of properties is an important
skill you'll need in this course. Try to solve this exercise
without any help at all.
We say that a list "stutters" if it repeats the same element
consecutively. The property "[nostutter mylist]" means that
[mylist] does not stutter. Formulate an inductive definition for
[nostutter]. (This is different from the [NoDup] property in the
exercise above; the sequence [1;4;1] repeats but does not
stutter.) *)
Inductive nostutter {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Make sure each of these tests succeeds, but feel free to change
the suggested proof (in comments) if the given one doesn't work
for you. Your definition might be different from ours and still
be correct, in which case the examples might need a different
proof. (You'll notice that the suggested proofs use a number of
tactics we haven't talked about, to make them more robust to
different possible ways of defining [nostutter]. You can probably
just uncomment and use them as-is, but you can also prove each
example with more basic tactics.) *)
Example test_nostutter_1: nostutter [3;1;4;1;5;6].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false_iff; auto.
Qed.
*)
Example test_nostutter_2: nostutter (@nil nat).
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false_iff; auto.
Qed.
*)
Example test_nostutter_3: nostutter [5].
(* FILL IN HERE *) Admitted.
(*
Proof. repeat constructor; apply beq_nat_false; auto. Qed.
*)
Example test_nostutter_4: not (nostutter [3;1;1;4]).
(* FILL IN HERE *) Admitted.
(*
Proof. intro.
repeat match goal with
h: nostutter _ |- _ => inversion h; clear h; subst
end.
contradiction H1; auto. Qed.
*)
(** [] *)
(** **** Exercise: 4 stars, advanced (pigeonhole principle) *)
(** The _pigeonhole principle_ states a basic fact about counting: if
we distribute more than [n] items into [n] pigeonholes, some
pigeonhole must contain at least two items. As often happens, this
apparently trivial fact about numbers requires non-trivial
machinery to prove, but we now have enough... *)
(** First prove an easy useful lemma. *)
Lemma in_split : forall (X:Type) (x:X) (l:list X),
In x l ->
exists l1 l2, l = l1 ++ x :: l2.
Proof.
(* FILL IN HERE *) Admitted.
(** Now define a property [repeats] such that [repeats X l] asserts
that [l] contains at least one repeated element (of type [X]). *)
Inductive repeats {X:Type} : list X -> Prop :=
(* FILL IN HERE *)
.
(** Now, here's a way to formalize the pigeonhole principle. Suppose
list [l2] represents a list of pigeonhole labels, and list [l1]
represents the labels assigned to a list of items. If there are
more items than labels, at least two items must have the same
label -- i.e., list [l1] must contain repeats.
This proof is much easier if you use the [excluded_middle]
hypothesis to show that [In] is decidable, i.e. [forall x l, (In x
l) \/ ~ (In x l)]. However, it is also possible to make the proof
go through _without_ assuming that [In] is decidable; if you
manage to do this, you will not need the [excluded_middle]
hypothesis. *)
Theorem pigeonhole_principle: forall (X:Type) (l1 l2:list X),
excluded_middle ->
(forall x, In x l1 -> In x l2) ->
length l2 < length l1 ->
repeats l1.
Proof.
intros X l1. induction l1 as [|x l1' IHl1'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2015-08-11 12:03:04 -0400 (Tue, 11 Aug 2015) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__diode (
DIODE
);
// Module ports
input DIODE;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_FUNCTIONAL_V
|
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Compute] to evaluate a
compound expression involving [next_weekday]. *)
Compute (next_weekday friday).
(* ==> monday : day *)
Compute (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. simpl. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. simpl. reflexivity. Qed.
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. simpl. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. simpl nandb. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. simpl nandb. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. simpl nandb. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. simpl nandb. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := andb b1 (andb b2 b3).
Example test_andb31: (andb3 true true true) = true.
Proof. simpl nandb. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. simpl nandb. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. simpl nandb. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. simpl nandb. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Compute (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. simpl. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. simpl. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Compute (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. simpl. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof.
simpl. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof.
simpl. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. simpl. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool := andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [simpl] to
simplify both sides of the equation, then use [reflexivity] to
check that both sides contain identical values.
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved just
by observing that [0 + n] reduces to [n] no matter what [n] is, a
fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. simpl. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** This is a good place to mention that [reflexivity] is
actually more powerful than it might look at first sight. In the
previous examples, the calls to [simpl] were actually not needed,
because [reflexivity] can perform some simplification
automatically when checking that two sides are equal; [simpl] was
just added for explanation purposes. For instance, here is another
proof of the same theorem: *)
Theorem plus_O_n' : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** As a matter of fact, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than
[simpl] does -- for example, it tries "unfolding" defined terms,
replacing them with their right-hand sides. The reason for this
difference is that, when reflexivity succeeds, the whole goal is
finished and we don't need to look at whatever expanded
expressions [reflexivity] has found; by contrast, [simpl] is used
in situations where we may have to read and understand the new
goal, so we would not want it blindly expanding definitions. *)
(** The form of the theorem we just stated and its proof are
almost exactly the same as the examples above; there are just a
few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Second, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures.
Other similar theorems can be proved with the same pattern. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(** It is worth stepping through these proofs to observe how the
context and the goal change. *)
(** You may want to add calls to [simpl] before [reflexivity] to
see the simplifications that Coq performs on the terms before checking
that they are equal. *)
(** Finally, we should mention that, although powerful enough to
prove some fairly general facts, there are many statements that
cannot be handled by simplification alone. For instance, perhaps
surprisingly, we cannot use it to prove that [0] is also a
"neutral element" for [+] _on the right_. *)
Theorem plus_n_O : forall n, n + 0 = n.
Proof.
intros n. simpl. (* Doesn't do anything! *)
(** (Can you explain why this happens? Step through both proofs
with Coq and notice how the goal and context change.)
When stuck in the middle of a proof, we can use the [Abort]
command to give up on it momentarily. *)
Abort.
(** In the next chapter, we cover a technique that can be used
for proving this goal. *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
(* move both quantifiers into the context *)
intros n m.
(* move the hypothesis into the context *)
intros H.
(* rewrite the goal using the hypothesis *)
rewrite -> H.
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o Hnm Hmo.
rewrite Hnm.
rewrite Hmo.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros HnSm.
rewrite HnSm.
simpl.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
- reflexivity.
- reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. The annotation "[as [| n']]" is called an _intro pattern_.
It tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [-] signs on the second and third lines are called _bullets_,
and delimit parts of the proof that correspond to each generated
subgoal. The code that comes after a bullet is the entire proof
for a subgoal. In this example, each of the subgoals is easily
proved by a single use of [reflexivity] (which itself performs
some simplification, as usual -- e.g., the first one simplifies
[beq_nat (S n' + 1) 0] to [false] by first rewriting [(S n' + 1)]
to [S (n' + 1)], then unfolding [beq_nat], and then simplifying
the [match]).
Marking cases with bullets is entirely optional: if they are not
present, Coq simply asks you to prove each subgoal in sequence,
one at a time. Even so, it is a good idea to use bullets, mainly
for two reasons. First, they make the structure of a proof more
apparent, making it more readable. Second, bullets instruct Coq to
ensure that a subgoal is complete before trying to verify the next
one, preventing proofs for different subgoals from getting mixed
up. These issues become especially important in large
developments, where fragile proofs lead to long debugging sessions.
There are no hard and fast rules for how proofs should be
formatted in Coq -- in particular, where lines should be broken
and how sections of the proof should be indented to indicate their
nested structure. However, if the places where multiple subgoals
are generated are marked with explicit bullets placed at the
beginning of lines, then the proof will be readable almost no
matter what choices are made about other aspects of layout.
This is a good place to mention one other piece of (possibly
obvious) advice about line lengths. Beginning Coq users sometimes
tend to the extremes, either writing each tactic on its own line
or entire proofs on one line. Good style lies somewhere in the
middle. In particular, one reasonable convention is to limit
yourself to 80-character lines. Lines longer than this are hard
to read and can be inconvenient to display and print. Many
editors have features that help enforce this.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
- reflexivity.
- reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices.
It is possible to invoke [destruct] inside a subgoal, generating
yet more proof obligations. In this case, we use different bullets
to mark goals on different "levels." For example: *)
Theorem andb_commutative : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
- destruct c.
+ reflexivity.
+ reflexivity.
- destruct c.
+ reflexivity.
+ reflexivity.
Qed.
(** Here, each pair of calls to [reflexivity] corresponds to
subgoals that were generated after the execution of the [destruct
c] line right above it. Using [+] instead of [-] for these
subgoals allows Coq to distinguish between different levels of
subgoals generated in a proof, making it more robust. Besides [-]
and [+], Coq proofs can also use [*] as a third kind of bullet. If
we encounter a proof that generates more than three levels of
subgoals, we can also enclose individual subgoals with curly
braces ([{ ... }]): *)
Theorem andb_commutative' : forall b c, andb b c = andb c b.
Proof.
intros b c. destruct b.
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
{ destruct c.
{ reflexivity. }
{ reflexivity. } }
Qed.
(** Since curly braces mark both the beginning and the end of a
proof, they can appear on multiple subgoal levels at the same
time, as this example shows. Furthermore, curly braces allow us to
reuse the same bullet shapes at multiple levels in a proof: *)
Theorem andb3_exchange :
forall b c d, andb (andb b c) d = andb (andb b d) c.
Proof.
intros b c d. destruct b.
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
- destruct c.
{ destruct d.
- reflexivity.
- reflexivity. }
{ destruct d.
- reflexivity.
- reflexivity. }
Qed.
(** **** Exercise: 2 stars (andb_true_elim2) *)
(** Prove [andb_true_elim2], marking cases (and subcases) with bullets
when you use [destruct]. *)
Theorem andb_true_elim2 : forall b c : bool,
andb b c = true -> c = true.
Proof.
intros b c.
destruct b as [true | false].
- destruct c as [true | false].
+ intros Hbc. reflexivity.
+ intros Hbc. simpl andb in Hbc. rewrite Hbc. reflexivity.
- destruct c as [true | false].
+ intros Hbc. reflexivity.
+ intros Hbc. simpl andb in Hbc. rewrite Hbc. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n.
destruct n.
- simpl. reflexivity.
- simpl. reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H_f_id b.
rewrite H_f_id. rewrite H_f_id.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f H_f_id b.
rewrite H_f_id. rewrite H_f_id.
destruct b.
- simpl. reflexivity.
- simpl. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
- destruct c.
+ intros H. reflexivity.
+ intros H. simpl andb in H. simpl orb in H. rewrite H. reflexivity.
- destruct c.
+ intros H. simpl andb in H. simpl orb in H. rewrite H. reflexivity.
+ intros H. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| zero : bin
| twice : bin -> bin
| twice_plus_one : bin -> bin.
Fixpoint incr (b : bin) : bin :=
match b with
| zero => twice_plus_one zero
| twice b => twice_plus_one b
| twice_plus_one b => twice (incr b)
end.
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| zero => O
| twice b' => mult (S (S O)) (bin_to_nat b')
| twice_plus_one b' => plus (mult (S (S O)) (bin_to_nat b')) (S O)
end.
Example test_bin_incr1 :
bin_to_nat (incr zero) = S O.
Proof. simpl. reflexivity. Qed.
Definition binary_1 := twice_plus_one zero.
Definition binary_2 := twice binary_1.
Definition binary_3 := twice_plus_one binary_1.
Definition binary_4 := twice binary_2.
Definition binary_5 := twice_plus_one binary_2.
Example test_bin_incr2 :
bin_to_nat (incr binary_4) = 5.
Proof. simpl. reflexivity. Qed.
Example test_bin_incr3 :
bin_to_nat (incr binary_3) = plus 1 (bin_to_nat binary_3).
Proof. simpl. reflexivity. Qed.
Example test_bin_incr4 :
bin_to_nat (incr binary_4) = plus 1 (bin_to_nat binary_4).
Proof. simpl. reflexivity. Qed.
Example test_bin_incr5 :
bin_to_nat (incr binary_5) = plus 1 (bin_to_nat binary_5).
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation symbol in Coq, we can specify its _precedence
level_ and its _associativity_. The precedence level [n] is
specified by writing [at level n]; this helps Coq parse compound
expressions. The associativity setting helps to disambiguate
expressions containing multiple occurrences of the same
symbol. For example, the parameters specified above for [+] and
[*] say that the expression [1+2*3*4] is shorthand for
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation symbol is also associated with a _notation scope_.
Coq tries to guess what scope you mean from context, so when you
write [S(O*O)] it guesses [nat_scope], but when you write the
cartesian product (tuple) type [bool*bool] it guesses
[type_scope]. Occasionally, you may have to help it out with
percent-notation by writing [(x*y)%nat], and sometimes in Coq's
feedback to you it will use [%nat] to indicate what scope a
notation is in.
Notation scopes also apply to numeral notation ([3], [4], [5],
etc.), so you may sometimes see [0%nat], which means [O] (the
natural number [0] that we're using in this chapter), or [0%Z]
which means the Integer zero (which comes from a different part of
the standard library). *)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing."
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
Fixpoint Ackerman (m : nat) (n : nat) : nat :=
match m, n with
| O, _ => S n
| S m', O => Ackerman m' (S 0)
| S m', S n' => Ackerman m' (Ackerman m n')
end.
(** [] *)
(** $Date: 2015-08-10 22:14:48 +0200 (Mon, 10 Aug 2015) $ *)
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// Top level memory sequencer structural block. This block
// instantiates the rank, bank, and column machines.
//*****************************************************************************
`timescale 1ps/1ps
module mc #
(
parameter TCQ = 100, // clk->out delay(sim only)
parameter ADDR_CMD_MODE = "1T", // registered or
// 1Tfered mem?
parameter BANK_WIDTH = 3, // bank address width
parameter BM_CNT_WIDTH = 2, // # BM counter width
// i.e., log2(nBANK_MACHS)
parameter BURST_MODE = "8", // Burst length
parameter CL = 5, // Read CAS latency
// (in clk cyc)
parameter CMD_PIPE_PLUS1 = "ON", // add register stage
// between MC and PHY
parameter COL_WIDTH = 12, // column address width
parameter CS_WIDTH = 4, // # of unique CS outputs
parameter CWL = 5, // Write CAS latency
// (in clk cyc)
parameter DATA_BUF_ADDR_WIDTH = 8, // User request tag (e.g.
// user src/dest buf addr)
parameter DATA_BUF_OFFSET_WIDTH = 1, // User buffer offset width
parameter DATA_WIDTH = 64, // Data bus width
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3", // Memory I/F type:
// "DDR3", "DDR2"
parameter ECC = "OFF", // ECC ON/OFF?
parameter ECC_WIDTH = 8, // # of ECC bits
parameter MAINT_PRESCALER_PERIOD= 200000, // maintenance period (ps)
parameter MC_ERR_ADDR_WIDTH = 31, // # of error address bits
parameter nBANK_MACHS = 4, // # of bank machines (BM)
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
// frequency ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs
// per rank
parameter nREFRESH_BANK = 1, // # of REF cmds to pull-in
parameter nSLOTS = 1, // # DIMM slots in system
parameter ORDERING = "NORM", // request ordering mode
parameter PAYLOAD_WIDTH = 64, // Width of data payload
// from PHY
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // row address width
parameter RTT_NOM = "40", // Nominal ODT value
parameter RTT_WR = "120", // Write ODT value
parameter SLOT_0_CONFIG = 8'b0000_0101, // ranks allowed in slot 0
parameter SLOT_1_CONFIG = 8'b0000_1010, // ranks allowed in slot 1
parameter STARVE_LIMIT = 2, // max # of times a user
// request is allowed to
// lose arbitration when
// reordering is enabled
parameter tCK = 2500, // memory clk period(ns)
parameter tFAW = 40000, // four activate window(ns)
parameter tRAS = 37500, // ACT->PRE cmd period (ns)
parameter tRCD = 12500, // ACT->R/W delay (ns)
parameter tREFI = 7800000, // average periodic
// refresh interval(ns)
parameter tRFC = 110000, // REF->ACT/REF delay (ns)
parameter tRP = 12500, // PRE cmd period (ns)
parameter tRRD = 10000, // ACT->ACT period (ns)
parameter tRTP = 7500, // Read->PRE cmd delay (ns)
parameter tWTR = 7500, // Internal write->read
// delay (ns)
parameter tZQCS = 64, // ZQCS cmd period (CKs)
parameter tZQI = 128_000_000 // ZQCS interval (ns)
)
(
// System inputs
input clk,
input rst,
// Physical memory slot presence
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Native Interface
input [2:0] cmd,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,
input hi_priority,
input size,
input [BANK_WIDTH-1:0] bank,
input [COL_WIDTH-1:0] col,
input [RANK_WIDTH-1:0] rank,
input [ROW_WIDTH-1:0] row,
input use_addr,
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept,
output accept_ns,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
output rd_data_en,
output rd_data_end,
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset,
output reg [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr,
output reg wr_data_en,
output reg [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset,
// ECC interface
input correct_en,
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_single,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
input app_zq_req,
// MC <==> PHY Interface
output reg [nCK_PER_CLK-1:0] mc_ras_n,
output reg [nCK_PER_CLK-1:0] mc_cas_n,
output reg [nCK_PER_CLK-1:0] mc_we_n,
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire mc_reset_n,
output wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
output wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0]mc_wrdata_mask,
output reg mc_wrdata_en,
output wire mc_cmd_wren,
output wire mc_ctl_wren,
output reg [2:0] mc_cmd,
output reg [5:0] mc_data_offset,
output reg [1:0] mc_cas_slot,
output reg [3:0] mc_aux_out0,
output reg [3:0] mc_aux_out1,
output reg [1:0] mc_rank_cnt,
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
input phy_rddata_valid,
input init_calib_complete,
input [6*RANKS-1:0] calib_rd_data_offset
);
assign mc_reset_n = 1'b1; // never reset memory
assign mc_cmd_wren = 1'b1; // always write CMD FIFO(issue DSEL when idle)
assign mc_ctl_wren = 1'b1; // always write CTL FIFO(issue nondata when idle)
// Ensure there is always at least one rank present during operation
`ifdef MC_SVA
ranks_present: assert property
(@(posedge clk) (rst || (|(slot_0_present | slot_1_present))));
`endif
//***************************************************************************
// PHY, datapath, control, bus turnaround delay configuration
//***************************************************************************
localparam nWR_EN2CNFG_RD = 0; // write-enable -> read io_config delay
localparam nWR_EN2CNFG_WR = 0; // write-enable -> write io_config delay
localparam nCNFG2RD_EN = 0; // io_config -> read-enable delay
localparam nCNFG2WR = 0; // io_config -> write delay
localparam nRD_EN2CNFG_WR = 0; // read-enable -> write io_config delay
// Reserved. Do not change.
localparam nPHY_WRLAT = 2;
// always delay write data control unless ECC mode is enabled
localparam DELAY_WR_DATA_CNTRL = ECC == "ON" ? 0 : 1;
// Ensure that write control is delayed for appropriate CWL
/*`ifdef MC_SVA
delay_wr_data_zero_CWL_le_6: assert property
(@(posedge clk) ((CWL > 6) || (DELAY_WR_DATA_CNTRL == 0)));
`endif*/
// Never retrieve WR_DATA_ADDR early
localparam EARLY_WR_DATA_ADDR = "OFF";
//***************************************************************************
// Convert timing parameters from time to clock cycles
//***************************************************************************
localparam nRP = cdiv(tRP, tCK);
localparam nRCD = cdiv(tRCD, tCK);
localparam nRAS = cdiv(tRAS, tCK);
localparam nFAW = cdiv(tFAW, tCK);
localparam nRFC = cdiv(tRFC, tCK);
// Convert tWR. As per specification, write recover for autoprecharge
// cycles doesn't support values of 9 and 11. Round up 9 to 10 and 11 to 12
localparam nWR_CK = cdiv(15000, tCK) ;
localparam nWR = (nWR_CK == 9) ? 10 : (nWR_CK == 11) ? 12 : nWR_CK;
// tRRD, tWTR at tRTP have a 4 cycle floor in DDR3 and 2 cycle floor in DDR2
localparam nRRD_CK = cdiv(tRRD, tCK);
localparam nRRD = (DRAM_TYPE == "DDR3") ? (nRRD_CK < 4) ? 4 : nRRD_CK
: (nRRD_CK < 2) ? 2 : nRRD_CK;
localparam nWTR_CK = cdiv(tWTR, tCK);
localparam nWTR = (DRAM_TYPE == "DDR3") ? (nWTR_CK < 4) ? 4 : nWTR_CK
: (nWTR_CK < 2) ? 2 : nWTR_CK;
localparam nRTP_CK = cdiv(tRTP, tCK);
localparam nRTP = (DRAM_TYPE == "DDR3") ? (nRTP_CK < 4) ? 4 : nRTP_CK
: (nRTP_CK < 2) ? 2 : nRTP_CK;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
//***************************************************************************
// Set up maintenance counter dividers
//***************************************************************************
// CK clock divisor to generate maintenance prescaler period (round down)
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD / (tCK*nCK_PER_CLK);
// Maintenance prescaler divisor for refresh timer. Essentially, this is
// just (tREFI / MAINT_PRESCALER_PERIOD), but we must account for the worst
// case delay from the time we get a tick from the refresh counter to the
// time that we can actually issue the REF command. Thus, subtract tRCD, CL,
// data burst time and tRP for each implemented bank machine to ensure that
// all transactions can complete before tREFI expires
localparam REFRESH_TIMER_DIV = (tREFI-((tRCD+((CL+4)*tCK)+tRP)*nBANK_MACHS))
/ MAINT_PRESCALER_PERIOD;
// Periodic read (RESERVED - not currently required or supported in 7 series)
// tPRDI should only be set to 0
localparam tPRDI = 0; // Do NOT change.
localparam PERIODIC_RD_TIMER_DIV = tPRDI / MAINT_PRESCALER_PERIOD;
// Convert maintenance prescaler from ps to ns
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
// Maintenance prescaler divisor for ZQ calibration (ZQCS) timer
localparam ZQ_TIMER_DIV = tZQI / MAINT_PRESCALER_PERIOD_NS;
// Bus width required to broadcast a single bit rank signal among all the
// bank machines - 1 bit per rank, per bank
localparam RANK_BM_BV_WIDTH = nBANK_MACHS * RANKS;
//***************************************************************************
// Reserved feature control.
//***************************************************************************
// Open page wait mode is reserved.
// nOP_WAIT is the number of states a bank machine will park itself
// on an otherwise inactive open page before closing the page. If
// nOP_WAIT == 0, open page wait mode is disabled. If nOP_WAIT == -1,
// the bank machine will remain parked until the pool of idle bank machines
// are less than LOW_IDLE_CNT. At which point parked bank machines
// are selected to exit until the number of idle bank machines exceeds the
// LOW_IDLE_CNT.
localparam nOP_WAIT = 0; // Open page mode
localparam LOW_IDLE_CNT = 0; // Low idle bank machine threshold
//***************************************************************************
// Internal wires
//***************************************************************************
wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r;
wire [ROW_WIDTH-1:0] col_a;
wire [BANK_WIDTH-1:0] col_ba;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
wire col_periodic_rd;
wire [RANK_WIDTH-1:0] col_ra;
wire col_rmw;
wire col_rd_wr;
wire [ROW_WIDTH-1:0] col_row;
wire col_size;
wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
wire dq_busy_data;
wire ecc_status_valid;
wire [RANKS-1:0] inhbt_act_faw_r;
wire inhbt_rd_config;
wire [RANKS-1:0] inhbt_rd_r;
wire [RANKS-1:0] inhbt_wr_r;
wire inhbt_wr_config;
wire insert_maint_r1;
wire [RANK_WIDTH-1:0] maint_rank_r;
wire maint_req_r;
wire maint_wip_r;
wire maint_zq_r;
wire periodic_rd_ack_r;
wire periodic_rd_r;
wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r;
wire rd_rmw;
wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r;
wire [nBANK_MACHS-1:0] sending_col;
wire [nBANK_MACHS-1:0] sending_row;
wire sent_col;
wire wr_ecc_buf;
wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r;
wire [RANKS-1:0] wtr_inhbt_config_r;
// MC/PHY optional pipeline stage support
wire [nCK_PER_CLK-1:0] mc_ras_n_ns;
wire [nCK_PER_CLK-1:0] mc_cas_n_ns;
wire [nCK_PER_CLK-1:0] mc_we_n_ns;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address_ns;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank_ns;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_ns;
wire [3:0] mc_aux_out0_ns;
wire [3:0] mc_aux_out1_ns;
wire [1:0] mc_rank_cnt_ns = col_ra;
wire [2:0] mc_cmd_ns;
wire [5:0] mc_data_offset_ns;
wire [1:0] mc_cas_slot_ns;
wire mc_wrdata_en_ns;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr_ns;
wire wr_data_en_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset_ns;
wire [RANK_WIDTH:0] io_config_ns;
wire io_config_strobe_ns;
integer i;
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Optional pipeline register stage on MC/PHY interface
//***************************************************************************
generate
if (CMD_PIPE_PLUS1 == "ON") begin : cmd_pipe_plus // register interface
always @(posedge clk) begin
mc_address <= #TCQ mc_address_ns;
mc_bank <= #TCQ mc_bank_ns;
mc_cas_n <= #TCQ mc_cas_n_ns;
mc_cs_n <= #TCQ mc_cs_n_ns;
mc_aux_out0 <= #TCQ mc_aux_out0_ns;
mc_aux_out1 <= #TCQ mc_aux_out1_ns;
mc_cmd <= #TCQ mc_cmd_ns;
mc_ras_n <= #TCQ mc_ras_n_ns;
mc_we_n <= #TCQ mc_we_n_ns;
mc_data_offset <= #TCQ mc_data_offset_ns;
mc_cas_slot <= #TCQ mc_cas_slot_ns;
mc_wrdata_en <= #TCQ mc_wrdata_en_ns;
mc_rank_cnt <= #TCQ mc_rank_cnt_ns;
wr_data_addr <= #TCQ wr_data_addr_ns;
wr_data_en <= #TCQ wr_data_en_ns;
wr_data_offset <= #TCQ wr_data_offset_ns;
end // always @ (posedge clk)
end // block: cmd_pipe_plus
else begin : cmd_pipe_plus0 // don't register interface
always @( mc_address or mc_aux_out0 or mc_aux_out1 or mc_bank or
mc_cas_n or mc_cmd or mc_cs_n or mc_data_offset or
mc_rank_cnt or mc_ras_n or mc_we_n or mc_wrdata_en or
wr_data_addr or wr_data_en or wr_data_offset)
begin
mc_address = #TCQ mc_address_ns;
mc_bank = #TCQ mc_bank_ns;
mc_cas_n = #TCQ mc_cas_n_ns;
mc_cs_n = #TCQ mc_cs_n_ns;
mc_aux_out0 = #TCQ mc_aux_out0_ns;
mc_aux_out1 = #TCQ mc_aux_out1_ns;
mc_cmd = #TCQ mc_cmd_ns;
mc_ras_n = #TCQ mc_ras_n_ns;
mc_we_n = #TCQ mc_we_n_ns;
mc_data_offset = #TCQ mc_data_offset_ns;
mc_cas_slot = #TCQ mc_cas_slot_ns;
mc_wrdata_en = #TCQ mc_wrdata_en_ns;
mc_rank_cnt = #TCQ mc_rank_cnt_ns;
wr_data_addr = #TCQ wr_data_addr_ns;
wr_data_en = #TCQ wr_data_en_ns;
wr_data_offset = #TCQ wr_data_offset_ns;
end // always @ (...
end // block: cmd_pipe_plus0
endgenerate
//***************************************************************************
// Manage rank-level timing and maintanence
//***************************************************************************
rank_mach #
(
// Parameters
.BURST_MODE (BURST_MODE),
.CL (CL),
.CWL (CWL),
.CS_WIDTH (CS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV)
)
rank_mach0
(
// Outputs
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0]),
// Inputs
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.clk (clk),
.init_calib_complete (init_calib_complete),
.insert_maint_r1 (insert_maint_r1),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.rst (rst),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0])
);
//***************************************************************************
// Manage requests, reordering and bank timing
//***************************************************************************
bank_mach#
(
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.CWL (CWL_M),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2RD_EN (nCNFG2RD_EN),
.nCNFG2WR (nCNFG2WR),
.nCS_PER_RANK (nCS_PER_RANK),
.nOP_WAIT (nOP_WAIT),
.nRAS (nRAS),
.nRCD (nRCD),
.nRFC (nRFC),
.nRP (nRP),
.nRTP (nRTP),
.nSLOTS (nSLOTS),
.nWR (nWR),
.ORDERING (ORDERING),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.STARVE_LIMIT (STARVE_LIMIT),
.tZQCS (tZQCS)
)
bank_mach0
(
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank_ns),
.mc_address (mc_address_ns),
.mc_ras_n (mc_ras_n_ns),
.mc_cas_n (mc_cas_n_ns),
.mc_we_n (mc_we_n_ns),
.mc_cs_n (mc_cs_n_ns),
.mc_aux_out0 (mc_aux_out0_ns),
.mc_aux_out1 (mc_aux_out1_ns),
.mc_cmd (mc_cmd_ns),
.mc_data_offset (mc_data_offset_ns),
.mc_cas_slot (mc_cas_slot_ns),
.insert_maint_r1 (insert_maint_r1),
.io_config (io_config_ns[RANK_WIDTH:0]),
.io_config_strobe (io_config_strobe_ns),
.maint_wip_r (maint_wip_r),
.periodic_rd_ack_r (periodic_rd_ack_r),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
// Inputs
.bank (bank[BANK_WIDTH-1:0]),
.calib_rddata_offset (calib_rd_data_offset[5:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.init_calib_complete (init_calib_complete),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_rd_r (inhbt_rd_r[RANKS-1:0]),
.inhbt_wr_r (inhbt_wr_r[RANKS-1:0]),
.inhbt_wr_config (inhbt_wr_config),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.rank (rank[RANK_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.use_addr (use_addr),
.wtr_inhbt_config_r (wtr_inhbt_config_r[RANKS-1:0])
);
//***************************************************************************
// Manage DQ bus
//***************************************************************************
col_mach #
(
// Parameters
.TCQ (TCQ),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DELAY_WR_DATA_CNTRL (DELAY_WR_DATA_CNTRL),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.nPHY_WRLAT (nPHY_WRLAT),
.nRD_EN2CNFG_WR (nRD_EN2CNFG_WR),
.nWR_EN2CNFG_RD (nWR_EN2CNFG_RD),
.nWR_EN2CNFG_WR (nWR_EN2CNFG_WR),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH)
)
col_mach0
(
// Outputs
.mc_wrdata_en (mc_wrdata_en_ns),
.dq_busy_data (dq_busy_data),
.ecc_err_addr (ecc_err_addr[MC_ERR_ADDR_WIDTH-1:0]),
.ecc_status_valid (ecc_status_valid),
.inhbt_rd_config (inhbt_rd_config),
.inhbt_wr_config (inhbt_wr_config),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.rd_rmw (rd_rmw),
.wr_data_addr (wr_data_addr_ns),
.wr_data_en (wr_data_en_ns),
.wr_data_offset (wr_data_offset_ns),
.wr_ecc_buf (wr_ecc_buf),
// Inputs
.clk (clk),
.rst (rst),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.io_config (io_config_ns),
.sent_col (sent_col)
);
//***************************************************************************
// Implement ECC
//***************************************************************************
// Total ECC word length = ECC code width + Data width
localparam CODE_WIDTH = DATA_WIDTH + ECC_WIDTH;
generate
if (ECC == "OFF") begin : ecc_off
assign rd_data = phy_rd_data;
assign mc_wrdata = wr_data;
assign mc_wrdata_mask = wr_data_mask;
assign ecc_single = 4'b0;
assign ecc_multiple = 4'b0;
end
else begin : ecc_on
wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
// Merge and encode
ecc_merge_enc #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_merge_enc0
(
// Outputs
.mc_wrdata (mc_wrdata),
.mc_wrdata_mask (mc_wrdata_mask),
// Inputs
.clk (clk),
.rst (rst),
.h_rows (h_rows),
.rd_merge_data (rd_merge_data),
.raw_not_ecc (raw_not_ecc),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask)
);
// Decode and fix
ecc_dec_fix #
(
// Parameters
.TCQ (TCQ),
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC_WIDTH (ECC_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_dec_fix0
(
// Outputs
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.rd_data (rd_data),
// Inputs
.clk (clk),
.rst (rst),
.correct_en (correct_en),
.phy_rddata (phy_rd_data),
.ecc_status_valid (ecc_status_valid),
.h_rows (h_rows)
);
// ECC Buffer
ecc_buf #
(
// Parameters
.TCQ (TCQ),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK)
)
ecc_buf0
(
// Outputs
.rd_merge_data (rd_merge_data),
// Inputs
.clk (clk),
.rst (rst),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_offset (wr_data_offset),
.wr_ecc_buf (wr_ecc_buf)
);
// Generate ECC table
ecc_gen #
(
// Parameters
.CODE_WIDTH (CODE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.ECC_WIDTH (ECC_WIDTH)
)
ecc_gen0
(
// Outputs
.h_rows (h_rows)
);
`ifdef DISPLAY_H_MATRIX
integer i;
always @(negedge rst) begin
$display ("**********************************************");
$display ("H Matrix:");
for (i=0; i<ECC_WIDTH; i=i+1)
$display ("%b", h_rows[i*CODE_WIDTH+:CODE_WIDTH]);
$display ("**********************************************");
end
`endif
end
endgenerate
endmodule // mc
|
module lab5dram(CLK, RESET, ADDR, DATA, MW, Q, IOA, IOB, IOC, IOD, IOE, IOF, IOG);
input CLK;
input RESET;
input [7:0] ADDR; // 8-bit addresses
input [7:0] DATA; // 8-bit data words
input MW;
output [7:0] Q;
input [7:0] IOA;
input [7:0] IOB;
input [7:0] IOC;
output [7:0] IOD;
output [7:0] IOE;
output [7:0] IOF;
output [7:0] IOG;
reg [7:0] Q;
reg [7:0] IOreg [3:6];
reg [7:0] mem [0:247];
reg [7:0] Q_IO;
reg [7:0] Q_mem;
reg [7:0] ADDR_IO;
reg MW_IO;
reg MW_mem;
always @(*) begin
Q_mem <= mem[ADDR];
end
always @(posedge CLK) begin
// memory is currently initialized with a LUT in 2-byte BCD words
// for the heart rate monitor (big endian)
if(RESET) begin
mem[0] <= 8'b0000_0000; // 0000
mem[1] <= 8'b0000_0000;
mem[2] <= 8'b0000_1000; // 0008
mem[3] <= 8'b0000_0000;
mem[4] <= 8'b0001_0111; // 0017
mem[5] <= 8'b0000_0000;
mem[6] <= 8'b0010_0110; // 0026
mem[7] <= 8'b0000_0000;
mem[8] <= 8'b0011_0101; // 0035
mem[9] <= 8'b0000_0000;
mem[10] <= 8'b0100_0100; // 0044
mem[11] <= 8'b0000_0000;
mem[12] <= 8'b0101_0011; // 0053
mem[13] <= 8'b0000_0000;
mem[14] <= 8'b0110_0010; // 0062
mem[15] <= 8'b0000_0000;
mem[16] <= 8'b0111_0001; // 0071
mem[17] <= 8'b0000_0000;
mem[18] <= 8'b1000_0000; // 0080
mem[19] <= 8'b0000_0000;
mem[20] <= 8'b1000_1001; // 0089
mem[21] <= 8'b0000_0000;
mem[22] <= 8'b1001_1000; // 0098
mem[23] <= 8'b0000_0000;
mem[24] <= 8'b0000_0111; // 0107
mem[25] <= 8'b0000_0001;
mem[26] <= 8'b0001_0110; // 0116
mem[27] <= 8'b0000_0001;
mem[28] <= 8'b0010_0101; // 0125
mem[29] <= 8'b0000_0001;
mem[30] <= 8'b0011_0011; // 0133
mem[31] <= 8'b0000_0001;
mem[32] <= 8'b0100_0010; // 0142
mem[33] <= 8'b0000_0001;
mem[34] <= 8'b0101_0001; // 0151
mem[35] <= 8'b0000_0001;
mem[36] <= 8'b0110_0000; // 0160
mem[37] <= 8'b0000_0001;
mem[38] <= 8'b0110_1001; // 0169
mem[39] <= 8'b0000_0001;
mem[40] <= 8'b0111_1000; // 0178
mem[41] <= 8'b0000_0001;
mem[42] <= 8'b1000_0111; // 0187
mem[43] <= 8'b0000_0001;
mem[44] <= 8'b1001_0110; // 0196
mem[45] <= 8'b0000_0001;
mem[46] <= 8'b0000_0101; // 0205
mem[47] <= 8'b0000_0010;
mem[48] <= 8'b0001_0100; // 0214
mem[49] <= 8'b0000_0010;
mem[50] <= 8'b0010_0011; // 0223
mem[51] <= 8'b0000_0010;
mem[52] <= 8'b0011_0010; // 0232
mem[53] <= 8'b0000_0010;
mem[54] <= 8'b0100_0001; // 0241
mem[55] <= 8'b0000_0010;
mem[56] <= 8'b0101_0000; // 0250
mem[57] <= 8'b0000_0010;
mem[58] <= 8'b0101_1001; // 0259
mem[59] <= 8'b0000_0010;
end
else if(MW_IO == 1'b1) begin
IOreg[ADDR_IO] <= DATA;
end
else if(MW_mem == 1'b1) begin
mem[ADDR] <= DATA;
end
end
assign IOD = IOreg[3];
assign IOE = IOreg[4];
assign IOF = IOreg[5];
assign IOG = IOreg[6];
always @(*) begin
MW_mem = 0;
MW_IO = 0;
ADDR_IO = 0;
Q = 8'd0;
case(ADDR)
8'd249: begin
ADDR_IO = 0;
Q = IOA;
end
8'd250: begin
ADDR_IO = 1;
Q = IOB;
end
8'd251: begin
ADDR_IO = 2;
Q = IOC;
end
8'd252: begin
ADDR_IO = 3;
MW_IO = MW;
end
8'd253: begin
ADDR_IO = 4;
MW_IO = MW;
end
8'd254: begin
ADDR_IO = 5;
MW_IO = MW;
end
8'd255: begin
ADDR_IO = 6;
MW_IO = MW;
end
default: begin // regular memory
if(MW) begin
MW_mem = 1;
end
else begin
Q = Q_mem;
end
end
endcase
end
endmodule
|
`define bsg_xnor_macro(bits) \
if (harden_p && (width_p==bits)) \
begin: macro \
bsg_rp_tsmc_40_XNR2D1BWP_b``bits xnor_gate (.i0(a_i),.i1(b_i),.o); \
end
module bsg_xnor #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
`bsg_xnor_macro(34) else
`bsg_xnor_macro(33) else
`bsg_xnor_macro(32) else
`bsg_xnor_macro(31) else
`bsg_xnor_macro(30) else
`bsg_xnor_macro(29) else
`bsg_xnor_macro(28) else
`bsg_xnor_macro(27) else
`bsg_xnor_macro(26) else
`bsg_xnor_macro(25) else
`bsg_xnor_macro(24) else
`bsg_xnor_macro(23) else
`bsg_xnor_macro(22) else
`bsg_xnor_macro(21) else
`bsg_xnor_macro(20) else
`bsg_xnor_macro(19) else
`bsg_xnor_macro(18) else
`bsg_xnor_macro(17) else
`bsg_xnor_macro(16) else
`bsg_xnor_macro(15) else
`bsg_xnor_macro(14) else
`bsg_xnor_macro(13) else
`bsg_xnor_macro(12) else
`bsg_xnor_macro(11) else
`bsg_xnor_macro(10) else
`bsg_xnor_macro(9) else
`bsg_xnor_macro(8) else
`bsg_xnor_macro(7) else
`bsg_xnor_macro(6) else
`bsg_xnor_macro(5) else
`bsg_xnor_macro(4) else
`bsg_xnor_macro(3) else
`bsg_xnor_macro(2) else
`bsg_xnor_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = ~(a_i ^ b_i);
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_xnor)
|
/* wb_mux. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2013-2019 Olof Kindgren <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
Wishbone multiplexer, burst-compatible
Simple mux with an arbitrary number of slaves.
The parameters MATCH_ADDR and MATCH_MASK are flattened arrays
aw*NUM_SLAVES sized arrays that are used to calculate the
active slave. slave i is selected when
(wb_adr_i & MATCH_MASK[(i+1)*aw-1:i*aw] is equal to
MATCH_ADDR[(i+1)*aw-1:i*aw]
If several regions are overlapping, the slave with the lowest
index is selected. This can be used to have fallback
functionality in the last slave, in case no other slave was
selected.
If no match is found, the wishbone transaction will stall and
an external watchdog is required to abort the transaction
Todo:
Registered master/slave connections
Rewrite with System Verilog 2D arrays when tools support them
*/
module wb_mux
#(parameter dw = 32, // Data width
parameter aw = 32, // Address width
parameter num_slaves = 2, // Number of slaves
parameter [num_slaves*aw-1:0] MATCH_ADDR = 0,
parameter [num_slaves*aw-1:0] MATCH_MASK = 0)
(input wb_clk_i,
input wb_rst_i,
// Master Interface
input [aw-1:0] wbm_adr_i,
input [dw-1:0] wbm_dat_i,
input [3:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
input [2:0] wbm_cti_i,
input [1:0] wbm_bte_i,
output [dw-1:0] wbm_dat_o,
output wbm_ack_o,
output wbm_err_o,
output wbm_rty_o,
// Wishbone Slave interface
output [num_slaves*aw-1:0] wbs_adr_o,
output [num_slaves*dw-1:0] wbs_dat_o,
output [num_slaves*4-1:0] wbs_sel_o,
output [num_slaves-1:0] wbs_we_o,
output [num_slaves-1:0] wbs_cyc_o,
output [num_slaves-1:0] wbs_stb_o,
output [num_slaves*3-1:0] wbs_cti_o,
output [num_slaves*2-1:0] wbs_bte_o,
input [num_slaves*dw-1:0] wbs_dat_i,
input [num_slaves-1:0] wbs_ack_i,
input [num_slaves-1:0] wbs_err_i,
input [num_slaves-1:0] wbs_rty_i);
///////////////////////////////////////////////////////////////////////////////
// Master/slave connection
///////////////////////////////////////////////////////////////////////////////
//Use parameter instead of localparam to work around a bug in Xilinx ISE
parameter slave_sel_bits = num_slaves > 1 ? $clog2(num_slaves) : 1;
reg wbm_err;
wire [slave_sel_bits-1:0] slave_sel;
wire [num_slaves-1:0] match;
genvar idx;
generate
for(idx=0; idx<num_slaves ; idx=idx+1) begin : addr_match
assign match[idx] = (wbm_adr_i & MATCH_MASK[idx*aw+:aw]) == MATCH_ADDR[idx*aw+:aw];
end
endgenerate
//
// Find First 1 - Start from MSB and count downwards, returns 0 when no bit set
//
function [slave_sel_bits-1:0] ff1;
input [num_slaves-1:0] in;
integer i;
begin
ff1 = 0;
for (i = num_slaves-1; i >= 0; i=i-1) begin
if (in[i])
/* verilator lint_off WIDTH */
ff1 = i;
/* verilator lint_on WIDTH */
end
end
endfunction
assign slave_sel = ff1(match);
always @(posedge wb_clk_i)
wbm_err <= wbm_cyc_i & !(|match);
assign wbs_adr_o = {num_slaves{wbm_adr_i}};
assign wbs_dat_o = {num_slaves{wbm_dat_i}};
assign wbs_sel_o = {num_slaves{wbm_sel_i}};
assign wbs_we_o = {num_slaves{wbm_we_i}};
/* verilator lint_off WIDTH */
assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel);
/* verilator lint_on WIDTH */
assign wbs_stb_o = {num_slaves{wbm_stb_i}};
assign wbs_cti_o = {num_slaves{wbm_cti_i}};
assign wbs_bte_o = {num_slaves{wbm_bte_i}};
assign wbm_dat_o = wbs_dat_i[slave_sel*dw+:dw];
assign wbm_ack_o = wbs_ack_i[slave_sel];
assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err;
assign wbm_rty_o = wbs_rty_i[slave_sel];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
// Module ports
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_BEHAVIORAL_V
|
(**************************************************************************
* TLC: A library for Coq *
* Equality *
**************************************************************************)
Set Implicit Arguments.
Require Import LibTactics LibAxioms.
Generalizable Variables A.
(* ********************************************************************** *)
(** * Partial application of Leibnitz' equality *)
(** [= x] is a unary predicate which holds of values equal to [x].
It simply denotes the partial application of equality.
[= x :> A] allows to specify the type. *)
Notation "'=' x :> A" := (fun y => y = x :> A)
(at level 71, x at next level).
Notation "'=' x" := (fun y => y = x)
(at level 71).
(** [<> x] is a unary predicate which holds of values disequal to [x].
It simply denotes the partial application of disequality.
[<> x :> A] allows to specify the type. *)
Notation "'<>' x :> A" := (fun y => y <> x :> A)
(at level 71, x at next level).
Notation "'<>' x" := (fun y => y <> x)
(at level 71).
(* ********************************************************************** *)
(** * Functional extensionality *)
(* ---------------------------------------------------------------------- *)
(** ** Dependent functional extensionality *)
Section FuncExtDep.
Variables (A1 : Type).
Variables (A2 : forall (x1 : A1), Type).
Variables (A3 : forall (x1 : A1) (x2 : A2 x1), Type).
Variables (A4 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2), Type).
Variables (A5 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2) (x4 : A4 x3), Type).
Variables (A6 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2) (x4 : A4 x3) (x5 : A5 x4), Type).
Lemma func_ext_dep_1 : forall (f g : forall (x1:A1), A2 x1),
(forall x1, f x1 = g x1) -> f = g.
Proof using. repeat (intros; apply func_ext_dep). auto. Qed.
Lemma func_ext_dep_2 : forall (f g : forall (x1:A1) (x2:A2 x1), A3 x2),
(forall x1 x2, f x1 x2 = g x1 x2) -> f = g.
Proof using. repeat (intros; apply func_ext_dep). auto. Qed.
Lemma func_ext_dep_3 : forall (f g : forall (x1:A1) (x2:A2 x1) (x3:A3 x2), A4 x3),
(forall x1 x2 x3, f x1 x2 x3 = g x1 x2 x3) -> f = g.
Proof using. repeat (intros; apply func_ext_dep). auto. Qed.
Lemma func_ext_dep_4 : forall (f g: forall (x1:A1) (x2:A2 x1) (x3:A3 x2)
(x4:A4 x3), A5 x4),
(forall x1 x2 x3 x4, f x1 x2 x3 x4 = g x1 x2 x3 x4) -> f = g.
Proof using. repeat (intros; apply func_ext_dep). auto. Qed.
End FuncExtDep.
(* ---------------------------------------------------------------------- *)
(** ** Non-dependent functional extensionality *)
Lemma func_ext_1 : forall A1 B (f g : A1 -> B),
(forall x1, f x1 = g x1) -> f = g.
Proof using. intros. apply~ func_ext_dep_1. Qed.
Lemma func_ext_2 : forall A1 A2 B (f g : A1 -> A2 -> B),
(forall x1 x2, f x1 x2 = g x1 x2) -> f = g.
Proof using. intros. apply~ func_ext_dep_2. Qed.
Lemma func_ext_3 : forall A1 A2 A3 B (f g : A1 -> A2 -> A3 -> B),
(forall x1 x2 x3, f x1 x2 x3 = g x1 x2 x3) -> f = g.
Proof using. intros. apply~ func_ext_dep_3. Qed.
Lemma func_ext_4 : forall A1 A2 A3 A4 B (f g : A1 -> A2 -> A3 -> A4 -> B),
(forall x1 x2 x3 x4, f x1 x2 x3 x4 = g x1 x2 x3 x4) -> f = g.
Proof using. intros. apply~ func_ext_dep_4. Qed.
(* ---------------------------------------------------------------------- *)
(** ** Eta-conversion *)
Lemma func_eta_dep : forall (A:Type) (B:A->Type) (f : forall x, B x),
(fun x1 => f x1) = f.
Proof using. intros. apply~ func_ext_dep. Qed.
Lemma func_eta_1 : forall A1 B (f : A1 -> B),
(fun x1 => f x1) = f.
Proof using. intros. apply~ func_ext_1. Qed.
Lemma func_eta_2 : forall A1 A2 B (f : A1 -> A2 -> B),
(fun x1 x2 => f x1 x2) = f.
Proof using. intros. apply~ func_ext_2. Qed.
Lemma func_eta_3 : forall A1 A2 A3 B (f : A1 -> A2 -> A3 -> B),
(fun x1 x2 x3 => f x1 x2 x3) = f.
Proof using. intros. apply~ func_ext_3. Qed.
Lemma func_eta_4 : forall A1 A2 A3 A4 B (f : A1 -> A2 -> A3 -> A4 -> B),
(fun x1 x2 x3 x4 => f x1 x2 x3 x4) = f.
Proof using. intros. apply~ func_ext_4. Qed.
Hint Rewrite func_eta_1 func_eta_2 func_eta_3 func_eta_4 : rew_eta.
(* ********************************************************************** *)
(** * Predicate extensionality *)
(* ---------------------------------------------------------------------- *)
(** ** Dependend predicates *)
Section PropExt.
Variables (A1 : Type).
Variables (A2 : forall (x1 : A1), Type).
Variables (A3 : forall (x1 : A1) (x2 : A2 x1), Type).
Variables (A4 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2), Type).
Variables (A5 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2) (x4 : A4 x3), Type).
Variables (A6 : forall (x1 : A1) (x2 : A2 x1) (x3 : A3 x2) (x4 : A4 x3) (x5 : A5 x4), Type).
Lemma prop_ext_1 : forall (P Q : forall (x1:A1), Prop),
(forall x1, P x1 <-> Q x1) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
Lemma prop_ext_2 : forall (P Q : forall (x1:A1) (x2:A2 x1), Prop),
(forall x1 x2, P x1 x2 <-> Q x1 x2) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
Lemma prop_ext_3 : forall (P Q : forall (x1:A1) (x2:A2 x1) (x3:A3 x2), Prop),
(forall x1 x2 x3, P x1 x2 x3 <-> Q x1 x2 x3) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
Lemma prop_ext_4 : forall (P Q : forall (x1:A1) (x2:A2 x1) (x3:A3 x2)
(x4:A4 x3), Prop),
(forall x1 x2 x3 x4, P x1 x2 x3 x4 <-> Q x1 x2 x3 x4) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
Lemma prop_ext_5 : forall (P Q : forall (x1:A1) (x2:A2 x1) (x3:A3 x2)
(x4:A4 x3) (x5:A5 x4), Prop),
(forall x1 x2 x3 x4 x5, P x1 x2 x3 x4 x5 <-> Q x1 x2 x3 x4 x5) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
Lemma prop_ext_6 : forall (P Q : forall (x1:A1) (x2:A2 x1) (x3:A3 x2)
(x4:A4 x3) (x5:A5 x4) (x6:A6 x5), Prop),
(forall x1 x2 x3 x4 x5 x6, P x1 x2 x3 x4 x5 x6 <-> Q x1 x2 x3 x4 x5 x6) -> P = Q.
Proof using. repeat (intros; apply func_ext_dep). intros. apply~ prop_ext. Qed.
End PropExt.
(* ---------------------------------------------------------------------- *)
(** ** Non-dependend predicates *)
Lemma prop_ext_nd_1 : forall A1 (P Q : A1 -> Prop),
(forall x1, P x1 <-> Q x1) -> P = Q.
Proof using. intros. apply~ prop_ext_1. Qed.
Lemma prop_ext_nd_2 : forall A1 A2 (P Q : A1 -> A2 -> Prop),
(forall x1 x2, P x1 x2 <-> Q x1 x2) -> P = Q.
Proof using. intros. apply~ prop_ext_2. Qed.
Lemma prop_ext_nd_3 : forall A1 A2 A3 (P Q : A1 -> A2 -> A3 -> Prop),
(forall x1 x2 x3, P x1 x2 x3 <-> Q x1 x2 x3) -> P = Q.
Proof using. intros. apply~ prop_ext_3. Qed.
Lemma prop_ext_nd_4 : forall A1 A2 A3 A4 (P Q : A1 -> A2 -> A3 -> A4 -> Prop),
(forall x1 x2 x3 x4, P x1 x2 x3 x4 <-> Q x1 x2 x3 x4) -> P = Q.
Proof using. intros. apply~ prop_ext_4. Qed.
(* ********************************************************************** *)
(** * Proof Irrelevance *)
(** The proof irrelevance lemma states that two proofs of a same
proposition are always equal. *)
(* ---------------------------------------------------------------------- *)
(** ** Proof of the proof-irrelevance result *)
(** Proof irrelevance is a consequence of propositional extensionality. *)
(* TODO: simplify and beautify the proof *)
Module PIfromExt.
Notation Local inhabited A := A (only parsing).
Lemma prop_ext_to_eq_arrow :
forall (A:Prop), inhabited A -> (A -> A) = A.
Proof using. intros. apply* prop_ext. Qed.
Record retract (A B : Prop) : Prop :=
{ retract_f1 : A -> B;
retract_f2 : B -> A;
retract_comp : forall x, retract_f1 (retract_f2 x) = x }.
Lemma prop_ext_retract_A_A_imp_A :
forall (A:Prop), inhabited A -> retract A (A -> A).
Proof using.
intros A a. rewrite (prop_ext_to_eq_arrow a).
apply~ (@Build_retract A A (fun x => x) (fun x => x)).
Qed.
Record has_fixpoint (A:Prop) : Prop :=
{ has_fixpoint_F : (A -> A) -> A;
has_fixpoint_fix : forall f, has_fixpoint_F f = f (has_fixpoint_F f) }.
Lemma ext_prop_fixpoint :
forall (A:Prop), inhabited A -> has_fixpoint A.
Proof using.
intros A a. destruct (prop_ext_retract_A_A_imp_A a) as [g1 g2 Fix].
set (Y := fun f => (fun x => f (g1 x x)) (g2 (fun x => f (g1 x x)))).
exists Y. intros f. unfold Y at 1. rewrite~ Fix.
Qed.
Inductive boolP : Prop :=
| trueP : boolP
| falseP : boolP.
Definition boolP_elim_redl (C:Prop) (c1 c2:C) :
c1 = boolP_ind c1 c2 trueP := refl_equal c1.
Definition boolP_elim_redr (C:Prop) (c1 c2:C) :
c2 = boolP_ind c1 c2 falseP := refl_equal c2.
Scheme boolP_indd := Induction for boolP Sort Prop.
Lemma aux : trueP = falseP.
Proof using.
case (@ext_prop_fixpoint boolP trueP); intros G Gfix.
set (neg := fun b:boolP => @boolP_ind boolP falseP trueP b).
generalize (refl_equal (G neg)).
pattern (G neg) at 1 in |- *.
apply boolP_indd with (b := G neg); intro Heq.
rewrite (boolP_elim_redl falseP trueP).
change (trueP = neg trueP) in |- *. rewrite Heq. apply Gfix.
rewrite (boolP_elim_redr falseP trueP).
change (neg falseP = falseP) in |- *; rewrite Heq; symmetry in |- *;
apply Gfix.
Qed.
Lemma proof_irrelevance :
forall (P : Prop) (p q : P), p = q.
Proof using.
intros A a1 a2.
set (f := fun b:boolP => match b with trueP => a1 | _ => a2 end).
(* set (f := fun b:boolP => boolP_ind a1 a2 b). *)
rewrite (boolP_elim_redl a1 a2).
change (f trueP = a2) in |- *.
rewrite (boolP_elim_redr a1 a2).
change (f trueP = f falseP) in |- *.
rewrite (aux).
reflexivity.
Qed.
End PIfromExt.
Lemma proof_irrelevance :
forall (P : Prop) (p q : P), p = q.
Proof using. exact PIfromExt.proof_irrelevance. Qed.
(* ---------------------------------------------------------------------- *)
(** ** Consequences of proof irrelevance *)
(** Uniqueness of identity proofs *)
Lemma identity_proofs_unique :
forall (A : Type) (x y : A) (p q : x = y), p = q.
Proof using. intros. apply proof_irrelevance. Qed.
(** Uniqueness of reflexive identity proofs *)
Lemma refl_identity_proofs_unique :
forall (A : Type) (x : A) (p : x = x),
p = refl_equal x.
Proof using. intros. apply proof_irrelevance. Qed.
(** Invariance by substitution of reflexive equality proofs *)
Lemma eq_rect_eq :
forall (A : Type) (p : A) (Q : A -> Type) (x : Q p) (h : p = p),
eq_rect p Q x p h = x.
Proof using. intros. rewrite~ (refl_identity_proofs_unique h). Qed.
(** Streicher's axiom K *)
Lemma streicher_K : forall (A : Type) (x : A) (P : x = x -> Prop),
P (refl_equal x) -> forall (p : x = x), P p.
Proof using. intros. rewrite~ (refl_identity_proofs_unique p). Qed.
(* ---------------------------------------------------------------------- *)
(** ** Injectivity of equality on dependent pairs *)
(** This section establishes that [existT P p x = existT P p y] implies
that [x] is equal to [y]. It indirectly results from the proof
irrelevance property. *)
(** Definition of dependent equality, with non-dependent return type *)
Inductive eq_dep_nd (A : Type) (P : A -> Type)
(p : A) (x : P p) (q : A) (y : P q) : Prop :=
| eq_dep_nd_intro : forall (h : q = p),
x = eq_rect q P y p h -> eq_dep_nd P p x q y.
Implicit Arguments eq_dep_nd [A P p q].
Implicit Arguments eq_dep_nd_intro [A P p q x y].
(** Reflexivity of [eq_dep_nd] *)
Lemma eq_dep_nd_direct : forall (A : Type) (P : A -> Type) (p : A) (x : P p),
eq_dep_nd x x.
Proof using. intros. apply (eq_dep_nd_intro (refl_equal p)). auto. Qed.
(** Injectivity of [eq_dep_nd] *)
Lemma eq_dep_nd_eq :
forall (A : Type) (P : A -> Type) (p : A) (x y : P p),
eq_dep_nd x y -> x = y.
Proof using. introv H. inversions H. rewrite~ eq_rect_eq. Qed.
(** Equality on dependent pairs implies [eq_dep_nd] *)
Lemma eq_sigT_eq_dep_nd :
forall (A : Type) (P : A -> Type) (p q : A) (x : P p) (y : P q),
existT P p x = existT P q y -> eq_dep_nd x y.
Proof using. introv E. dependent rewrite E. simpl. apply eq_dep_nd_direct. Qed.
(** Injectivity of equality on dependent pairs *)
Lemma eq_sigT_to_eq :
forall (A : Type) (P : A -> Type) (p : A) (x y : P p),
existT P p x = existT P p y -> x = y.
Proof using. intros. apply eq_dep_nd_eq. apply~ eq_sigT_eq_dep_nd. Qed.
(* ---------------------------------------------------------------------- *)
(** Irrelevance of the membership property for subsets types *)
(** This is another consequence of proof irrelevance *)
Scheme eq_indd := Induction for eq Sort Prop.
Lemma exist_eq :
forall (A : Type) (P : A->Prop) (x y : A) (p : P x) (q : P y),
x = y -> exist P x p = exist P y q.
Proof using.
intros. rewrite (proof_irrelevance q (eq_rect x P p y H)).
elim H using eq_indd. reflexivity.
Qed.
Lemma existT_eq :
forall (U:Type) (P:U->Prop) (x y:U) (p:P x) (q:P y),
x = y -> existT P x p = existT P y q.
Proof using.
intros. rewrite (proof_irrelevance q (eq_rect x P p y H)).
elim H using eq_indd. reflexivity.
Qed.
(* ********************************************************************** *)
(** * Dependent equality *)
(** In this section, we prove that [eq_dep x y] implies [x = y]. *)
(** Definition of [eq_dep] (copied from the LibPrelude) *)
Inductive eq_dep (A : Type) (P : A -> Type) (p : A) (x : P p)
: forall q, P q -> Prop :=
| eq_dep_refl : eq_dep P p x p x.
Implicit Arguments eq_dep [A P p q].
(** Symmetry of [eq_dep] *)
Lemma eq_dep_sym : forall (A : Type) (P : A -> Type)
(p q : A) (x : P p) (y : P q),
eq_dep x y -> eq_dep y x.
Proof using. introv E. destruct E. constructor. Qed.
(** Transitivity of [eq_dep] *)
Lemma eq_dep_trans : forall (A : Type) (P : A -> Type)
(p q r : A) (y : P q) (x : P p) (z : P r),
eq_dep x y -> eq_dep y z -> eq_dep x z.
Proof using. introv E F. destruct~ E. Qed.
(** Proof of equivalence between [eq_dep_nd] and [eq_dep] *)
Scheme eq_induction := Induction for eq Sort Prop.
Lemma eq_dep_nd_to_eq_dep :
forall (A : Type) (P : A -> Type) (p q : A) (x : P p) (y : P q),
eq_dep_nd x y -> eq_dep x y.
Proof using.
introv E. destruct E as (h,H).
destruct h using eq_induction. subst~. constructor.
Qed.
Lemma eq_dep_to_eq_dep_nd :
forall (A : Type) (P : A -> Type) (p q : A) (x : P p) (y : P q),
eq_dep x y -> eq_dep_nd x y.
Proof using. introv H. destruct H. apply (eq_dep_nd_intro (refl_equal p)); auto. Qed.
(** Injectivity of dependent equality *)
Lemma eq_dep_eq :
forall (A : Type) (P : A -> Type) (p : A) (x y : P p),
eq_dep x y -> x = y.
Proof using. introv R. inversion R. apply eq_dep_nd_eq. apply~ eq_dep_to_eq_dep_nd. Qed.
(** Equality on dependent pairs implies dependent equality *)
Lemma eq_sigT_eq_dep :
forall (A : Type) (P : A -> Type) (p q : A) (x : P p) (y : P q),
existT P p x = existT P q y -> eq_dep x y.
Proof using. introv E. dependent rewrite E. simple~. constructor. Qed.
(* ********************************************************************** *)
(** * John Major's equality *)
(** In this section, we prove that [JMeq x y] implies [x = y]
when both [x] and [y] have the same type. *)
Require Import JMeq.
(** Symmetry, transitivity of [JMeq] *)
Lemma JMeq_sym : forall (A B : Type) (x : A) (y : B),
JMeq x y -> JMeq y x.
Proof using. introv E. destruct~ E. Qed.
Lemma JMeq_trans : forall (A B C : Type) (y : B) (x : A) (z : C),
JMeq x y -> JMeq y z -> JMeq x z.
Proof using. introv E F. destruct~ E. Qed.
Local Hint Immediate JMeq_sym.
(** Relation between [JMeq] and [eq_dep] *)
Lemma JMeq_to_eq_dep : forall (A B : Type) (x : A) (y : B),
JMeq x y -> @eq_dep Type (fun T => T) A x B y.
Proof using. introv E. destruct E. constructor. Qed.
Lemma eq_dep_to_JMeq : forall (A B : Type) (x : A) (y : B),
@eq_dep Type (fun T => T) A x B y -> JMeq x y.
Proof using. introv E. destruct~ E. Qed.
(** Injectivity of [JMeq] *)
Lemma JMeq_eq : forall (A : Type) (x y : A),
JMeq x y -> x = y.
Proof using.
introv E. apply (@eq_dep_eq Type (fun T => T)).
apply~ JMeq_to_eq_dep.
Qed.
(* ********************************************************************** *)
(** * Properties of equality *)
(** This section contains a reformulation of the lemmas provided by
the standard library concerning equality. *)
Implicit Arguments eq [[A]].
(* ---------------------------------------------------------------------- *)
(** ** Equality as an equivalence relation *)
Section EqualityProp.
Variable A : Type.
Implicit Types x y z : A.
(** Reflexivity is captured by the constructor [eq_refl]. *)
(** Symmetry *)
Lemma eq_sym : forall x y,
x = y -> y = x.
Proof using. introv H. destruct~ H. Qed.
(** Transitivity *)
Lemma eq_trans : forall y x z,
x = y -> y = z -> x = z.
Proof using. introv H1 H2. destruct~ H2. Qed.
Lemma eq_trans' : forall y x z,
y = x -> y = z -> x = z.
Proof using. introv H1 H2. destruct~ H2. Qed.
End EqualityProp.
Implicit Arguments eq_trans [A].
Implicit Arguments eq_trans' [A].
(* TODO: two other versions of eq_trans *)
(* ---------------------------------------------------------------------- *)
(** ** Properties of disequality *)
Section DisequalityProp.
Variable A : Type.
Implicit Types x y z : A.
(** Symmetry *)
Lemma neq_sym : forall x y,
x <> y -> y <> x.
Proof using. introv H K. destruct~ K. Qed.
End DisequalityProp.
(* ---------------------------------------------------------------------- *)
(** ** Symmetrized induction principles *)
(* TODO: is this really needed ?*)
Section EqInductionSym.
Variables (A : Type) (x : A).
Definition eq_ind_r : forall (P:A -> Prop),
P x -> forall y, y = x -> P y.
Proof using. introv Px H. elim (sym_eq H). auto. Qed.
Definition eq_rec_r : forall (P:A -> Set),
P x -> forall y, y = x -> P y.
Proof using. introv Px H. elim (sym_eq H). auto. Qed.
Definition eq_rect_r : forall (P:A -> Type),
P x -> forall y, y = x -> P y.
Proof using. introv Px H. elim (sym_eq H). auto. Qed.
End EqInductionSym.
(* ********************************************************************** *)
(** * Equality between function applications *)
(* ---------------------------------------------------------------------- *)
(** ** A same function applied to equal arguments yield equal result *)
Section FuncEq.
Variables (A1 A2 A3 A4 A5 B : Type).
Lemma func_eq_1 : forall (f:A1->B) x1 y1,
x1 = y1 ->
f x1 = f y1.
Proof using. intros. subst~. Qed.
Lemma func_eq_2 : forall (f:A1->A2->B) x1 y1 x2 y2,
x1 = y1 -> x2 = y2 ->
f x1 x2 = f y1 y2.
Proof using. intros. subst~. Qed.
Lemma func_eq_3 : forall (f:A1->A2->A3->B) x1 y1 x2 y2 x3 y3,
x1 = y1 -> x2 = y2 -> x3 = y3 ->
f x1 x2 x3 = f y1 y2 y3.
Proof using. intros. subst~. Qed.
Lemma func_eq_4 : forall (f:A1->A2->A3->A4->B) x1 y1 x2 y2 x3 y3 x4 y4,
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 ->
f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof using. intros. subst~. Qed.
Lemma func_eq_5 : forall (f:A1->A2->A3->A4->A5->B) x1 y1 x2 y2 x3 y3 x4 y4 x5 y5,
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> x5 = y5 ->
f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof using. intros. subst~. Qed.
End FuncEq.
(* TODO: generalize to dependent functions *)
(* ---------------------------------------------------------------------- *)
(** ** Equal functions return equal results *)
Section FuncSame.
Variables (A1 A2 A3 A4 A5 B:Type).
Variables (x1:A1) (x2:A2) (x3:A3) (x4:A4) (x5:A5).
Lemma func_same_1 : forall f g,
f = g -> f x1 = g x1 :> B.
Proof using. intros. subst~. Qed.
Lemma func_same_2 : forall f g,
f = g -> f x1 x2 = g x1 x2 :> B.
Proof using. intros. subst~. Qed.
Lemma func_same_3 : forall f g,
f = g -> f x1 x2 x3 = g x1 x2 x3 :> B.
Proof using. intros. subst~. Qed.
Lemma func_same_4 : forall f g,
f = g -> f x1 x2 x3 x4 = g x1 x2 x3 x4 :> B.
Proof using. intros. subst~. Qed.
Lemma func_same_5 : forall f g,
f = g -> f x1 x2 x3 x4 x5 = g x1 x2 x3 x4 x5 :> B.
Proof using. intros. subst~. Qed.
End FuncSame.
(* ---------------------------------------------------------------------- *)
(** ** Generalization *)
Section FuncEqual.
Variables (A1 A2 A3 A4 A5 B : Type).
Lemma func_equal_1 : forall (f g:A1->B) x1 y1,
f = g ->
x1 = y1 ->
f x1 = g y1.
Proof using. intros. subst~. Qed.
Lemma func_equal_2 : forall (f g:A1->A2->B) x1 y1 x2 y2,
f = g -> x1 = y1 -> x2 = y2 ->
f x1 x2 = f y1 y2.
Proof using. intros. subst~. Qed.
Lemma func_equal_3 : forall (f g:A1->A2->A3->B) x1 y1 x2 y2 x3 y3,
f = g -> x1 = y1 -> x2 = y2 -> x3 = y3 ->
f x1 x2 x3 = f y1 y2 y3.
Proof using. intros. subst~. Qed.
Lemma func_equal_4 : forall (f g:A1->A2->A3->A4->B) x1 y1 x2 y2 x3 y3 x4 y4,
f = g -> x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 ->
f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof using. intros. subst~. Qed.
Lemma func_equal_5 : forall (f g:A1->A2->A3->A4->A5->B) x1 y1 x2 y2 x3 y3 x4 y4 x5 y5,
f = g -> x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> x5 = y5 ->
f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof using. intros. subst~. Qed.
End FuncEqual.
(* ********************************************************************** *)
(** * General definition of extensionality *)
(** The property [Extensional A] captures the fact that the type [A]
features an extensional equality, in the sense that to prove the
equality between two values of type [A] it suffices to prove that
those two values are related by some binary relation. *)
Class Extensional (A:Type) := {
extensional_hyp : A -> A -> Prop;
extensional : forall x y : A, extensional_hyp x y -> x = y }.
(* ---------------------------------------------------------------------- *)
(** ** Tactic to exploit extensionality *)
(** [extens] is a tactic that can be applied to exploit extensionality
on any goal of the form [x = y] when [x] and [y] are functions, or
predicates, or have a type [A] satisfying [Extensional A].
Note: the tactic [extens] automatically calls [intros] if needed. *)
Ltac extens_core :=
hnf;
match goal with
| |- _ = _ :> ?T =>
match T with
| Prop => apply prop_ext
| forall _, Prop => apply prop_ext_1
| forall _ _, Prop => apply prop_ext_2
| forall _ _ _, Prop => apply prop_ext_3
| forall _ _ _ _, Prop => apply prop_ext_4
| forall _ _ _ _ _, Prop => apply prop_ext_5
| forall _ _ _ _ _ _, Prop => apply prop_ext_6
| forall _,_ =>
first [ apply func_ext_dep_4
| apply func_ext_dep_3
| apply func_ext_dep_2
| apply func_ext_dep_1 ]
| _ => apply extensional; try unfold extensional_hyp; simpl
end end.
Ltac extens_base :=
first [ extens_core | intros; extens_core ].
Tactic Notation "extens" :=
extens_base.
Tactic Notation "extens" "~" :=
extens; auto_tilde.
Tactic Notation "extens" "*" :=
extens; auto_star.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hvl__udp_dff_pr_pp_pg_n.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__dfrtp (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire cond0 ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire buf0_out_Q ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hvl__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( RESET_B_delayed === 1'b1 );
buf buf0 (buf0_out_Q, buf_Q );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (Q , buf0_out_Q, VPWR, VGND );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRTP_BEHAVIORAL_PP_V
|
/*
########################################################################
Epiphany eLink AXI Master Module
########################################################################
NOTES:
--write channels: write address, write data, write response
--read channels: read address, read data channel
--'valid' source signal used to show valid address,data,control is available
--'ready' destination ready signal indicates readyness to accept information
--'last' signal indicates the transfer of final data item
--read and write have separate address channels
--read data channel carries read data from slave to master
--write channel includes a byte lane strobe signal for every eight data bits
--there is no acknowledge on write, treated as buffered
--channels are unidirectional
--valid is asserted uncondotionally
--ready occurs cycle after valid
--there can be no combinatorial path between input and output of interface
--destination is permitted to wait for valud before asserting READY
--source is not allowed to wait for READY to assert VALID
--AWVALID must remain asserted until the rising clock edge after slave asserts AWREADY??
--The default state of AWREADY can be either HIGH or LOW. This specification recommends a default state of HIGH.
--During a write burst, the master can assert the WVALID signal only when it drives valid write data.
--The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle.
--The master must assert the WLAST signal while it is driving the final write transfer in the burst.
--_aw=write address channel
--_ar=read address channel
--_r=read data channel
--_w=write data channel
--_b=write response channel
*/
module emaxi(/*autoarg*/
// Outputs
rxwr_wait, rxrd_wait, txrr_access, txrr_packet, m_axi_awid,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awqos,
m_axi_awvalid, m_axi_wid, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen,
m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache,
m_axi_arprot, m_axi_arqos, m_axi_arvalid, m_axi_rready,
// Inputs
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, txrr_wait,
m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid
);
parameter M_IDW = 12;
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
//########################
//ELINK INTERFACE
//########################
//Write request from erx
input rxwr_access;
input [PW-1:0] rxwr_packet;
output rxwr_wait;
//Read request from erx
input rxrd_access;
input [PW-1:0] rxrd_packet;
output rxrd_wait;
//Read respoonse for etx
output txrr_access;
output [PW-1:0] txrr_packet;
input txrr_wait;
//########################
//AXI MASTER INTERFACE
//########################
input m_axi_aclk; // global clock signal.
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [M_IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // indicates last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // indicates that the slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // channel is signaling a valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; //lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; //
output m_axi_arvalid; // valid read address and control information
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [M_IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
//#########################################################################
//REGISTER/WIRE DECLARATIONS
//#########################################################################
reg [31 : 0] m_axi_awaddr;
reg [7:0] m_axi_awlen;
reg [2:0] m_axi_awsize;
reg m_axi_awvalid;
reg [63 : 0] m_axi_wdata;
reg [63 : 0] m_axi_rdata_reg;
reg [7 : 0] m_axi_wstrb;
reg m_axi_wlast;
reg m_axi_wvalid;
reg awvalid_b;
reg [31:0] awaddr_b;
reg [2:0] awsize_b;
reg [7:0] awlen_b;
reg wvalid_b;
reg [63:0] wdata_b;
reg [7:0] wstrb_b;
reg [63 : 0] wdata_aligned;
reg [7 : 0] wstrb_aligned;
reg txrr_access;
reg txrr_access_reg;
reg [31:0] txrr_data;
reg [31:0] txrr_srcaddr;
//wires
wire aw_go;
wire w_go;
wire readinfo_wren;
wire readinfo_full;
wire [47:0] readinfo_out;
wire [47:0] readinfo_in;
wire awvalid_in;
wire [1:0] rxwr_datamode;
wire [AW-1:0] rxwr_dstaddr;
wire [DW-1:0] rxwr_data;
wire [AW-1:0] rxwr_srcaddr;
wire [1:0] rxrd_datamode;
wire [3:0] rxrd_ctrlmode;
wire [AW-1:0] rxrd_dstaddr;
wire [AW-1:0] rxrd_srcaddr;
wire [1:0] txrr_datamode;
wire [3:0] txrr_ctrlmode;
wire [31:0] txrr_dstaddr;
//#########################################################################
//EMESH 2 PACKET CONVERSION
//#########################################################################
//RXWR
packet2emesh p2e_rxwr (
// Outputs
.access_out (),
.write_out (),
.datamode_out (rxwr_datamode[1:0]),
.ctrlmode_out (),
.dstaddr_out (rxwr_dstaddr[AW-1:0]),
.data_out (rxwr_data[DW-1:0]),
.srcaddr_out (rxwr_srcaddr[AW-1:0]),
// Inputs
.packet_in (rxwr_packet[PW-1:0])
);
//RXRD
packet2emesh p2e_rxrd (
// Outputs
.access_out (),
.write_out (),
.datamode_out (rxrd_datamode[1:0]),
.ctrlmode_out (rxrd_ctrlmode[3:0]),
.dstaddr_out (rxrd_dstaddr[AW-1:0]),
.data_out (),
.srcaddr_out (rxrd_srcaddr[AW-1:0]),
// Inputs
.packet_in (rxrd_packet[PW-1:0])
);
//TXRR
emesh2packet e2p (
// Outputs
.packet_out (txrr_packet[PW-1:0]),
// Inputs
.access_in (txrr_access),
.write_in (1'b1),
.datamode_in (txrr_datamode[1:0]),
.ctrlmode_in (txrr_ctrlmode[3:0]),
.dstaddr_in (txrr_dstaddr[AW-1:0]),
.data_in (txrr_data[DW-1:0]),
.srcaddr_in (txrr_srcaddr[AW-1:0])
);
//#########################################################################
//AXI unimplemented constants
//#########################################################################
assign m_axi_awburst[1:0] = 2'b01; //only increment burst supported
assign m_axi_awcache[3:0] = 4'b0000;//TODO: correct value??
assign m_axi_awprot[2:0] = 3'b000;
assign m_axi_awqos[3:0] = 4'b0000;
assign m_axi_awlock = 2'b00;
assign m_axi_arburst[1:0] = 2'b01; //only increment burst supported
assign m_axi_arcache[3:0] = 4'b0000;
assign m_axi_arprot[2:0] = 3'h0;
assign m_axi_arqos[3:0] = 4'h0;
assign m_axi_bready = 1'b1;//tie to wait signal????
//#########################################################################
//Write address channel
//#########################################################################
assign aw_go = m_axi_awvalid & m_axi_awready;
assign w_go = m_axi_wvalid & m_axi_wready;
assign rxwr_wait = awvalid_b | wvalid_b;
assign awvalid_in = rxwr_access & ~awvalid_b & ~wvalid_b;
// generate write-address signals
always @( posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_awvalid <= 1'b0;
m_axi_awaddr[31:0] <= 32'd0;
m_axi_awlen[7:0] <= 8'd0;
m_axi_awsize[2:0] <= 3'd0;
awvalid_b <= 1'b0;
awaddr_b <= 'd0;
awlen_b[7:0] <= 'd0;
awsize_b[2:0] <= 'd0;
end
else
begin
if( ~m_axi_awvalid | aw_go )
begin
if( awvalid_b )
begin
m_axi_awvalid <= 1'b1;
m_axi_awaddr[31:0] <= awaddr_b[31:0];
m_axi_awlen[7:0] <= awlen_b[7:0];
m_axi_awsize[2:0] <= awsize_b[2:0];
end
else
begin
m_axi_awvalid <= awvalid_in;
m_axi_awaddr[31:0] <= rxwr_dstaddr[31:0];
m_axi_awlen[7:0] <= 8'b0;
m_axi_awsize[2:0] <= { 1'b0, rxwr_datamode[1:0]};
end
end
if( awvalid_in & m_axi_awvalid & ~aw_go )
awvalid_b <= 1'b1;
else if( aw_go )
awvalid_b <= 1'b0;
//Pipeline stage
if( awvalid_in )
begin
awaddr_b[31:0] <= rxwr_dstaddr[31:0];
awlen_b[7:0] <= 8'b0;
awsize_b[2:0] <= { 1'b0, rxwr_datamode[1:0] };
end
end // else: !if(~m_axi_aresetn)
//#########################################################################
//Write data alignment circuit
//#########################################################################
always @*
case( rxwr_datamode[1:0] )
2'd0: wdata_aligned[63:0] = { 8{rxwr_data[7:0]}};
2'd1: wdata_aligned[63:0] = { 4{rxwr_data[15:0]}};
2'd2: wdata_aligned[63:0] = { 2{rxwr_data[31:0]}};
default: wdata_aligned[63:0] = { rxwr_srcaddr[31:0], rxwr_data[31:0]};
endcase
always @*
begin
case(rxwr_datamode[1:0])
2'd0: // byte
case(rxwr_dstaddr[2:0])
3'd0: wstrb_aligned[7:0] = 8'h01;
3'd1: wstrb_aligned[7:0] = 8'h02;
3'd2: wstrb_aligned[7:0] = 8'h04;
3'd3: wstrb_aligned[7:0] = 8'h08;
3'd4: wstrb_aligned[7:0] = 8'h10;
3'd5: wstrb_aligned[7:0] = 8'h20;
3'd6: wstrb_aligned[7:0] = 8'h40;
default: wstrb_aligned[7:0] = 8'h80;
endcase
2'd1: // 16b hword
case(rxwr_dstaddr[2:1])
2'd0: wstrb_aligned[7:0] = 8'h03;
2'd1: wstrb_aligned[7:0] = 8'h0c;
2'd2: wstrb_aligned[7:0] = 8'h30;
default: wstrb_aligned[7:0] = 8'hc0;
endcase
2'd2: // 32b word
if(rxwr_dstaddr[2])
wstrb_aligned[7:0] = 8'hf0;
else
wstrb_aligned[7:0] = 8'h0f;
2'd3:
wstrb_aligned[7:0] = 8'hff;
endcase // case (emwr_datamode[1:0])
end // always @ *
//#########################################################################
//Write data channel
//#########################################################################
always @ (posedge m_axi_aclk )
if(~m_axi_aresetn)
begin
m_axi_wvalid <= 1'b0;
m_axi_wdata[63:0] <= 64'b0;
m_axi_wstrb[7:0] <= 8'b0;
m_axi_wlast <= 1'b1; // TODO:bursts!!
wvalid_b <= 1'b0;
wdata_b[63:0] <= 64'b0;
wstrb_b[7:0] <= 8'b0;
end
else
begin
if( ~m_axi_wvalid | w_go )
begin
if( wvalid_b )
begin
m_axi_wvalid <= 1'b1;
m_axi_wdata[63:0] <= wdata_b[63:0];
m_axi_wstrb[7:0] <= wstrb_b[7:0];
end
else
begin
m_axi_wvalid <= awvalid_in;
m_axi_wdata[63:0] <= wdata_aligned[63:0];
m_axi_wstrb[7:0] <= wstrb_aligned[7:0];
end
end // if ( ~axi_wvalid | w_go )
if( rxwr_access & m_axi_wvalid & ~w_go )
wvalid_b <= 1'b1;
else if( w_go )
wvalid_b <= 1'b0;
if( awvalid_in )
begin
wdata_b[63:0] <= wdata_aligned[63:0];
wstrb_b[7:0] <= wstrb_aligned[7:0];
end
end // else: !if(~m_axi_aresetn)
//#########################################################################
//Read request channel
//#########################################################################
//1. read request comes in on ar channel
//2. use src address to match with writes coming back
//3. Assumes in order returns
assign readinfo_in[47:0] =
{
7'b0,
rxrd_srcaddr[31:0],//40:9
rxrd_dstaddr[2:0], //8:6
rxrd_ctrlmode[3:0], //5:2
rxrd_datamode[1:0]
};
fifo_sync
#(
// parameters
.AW (5),
.DW (48))
fifo_readinfo_i
(
// outputs
.rd_data (readinfo_out[47:0]),
.rd_empty (),
.wr_full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wr_data (readinfo_in[47:0]),
.wr_en (m_axi_arvalid & m_axi_arready),
.rd_en (m_axi_rready & m_axi_rvalid)
);
assign txrr_datamode[1:0] = readinfo_out[1:0];
assign txrr_ctrlmode[3:0] = readinfo_out[5:2];
assign txrr_dstaddr[31:0] = readinfo_out[40:9];
//#########################################################################
//Read address channel
//#########################################################################
assign m_axi_araddr[31:0] = rxrd_dstaddr[31:0];
assign m_axi_arsize[2:0] = {1'b0, rxrd_datamode[1:0]};
assign m_axi_arlen[7:0] = 8'd0;
assign m_axi_arvalid = rxrd_access & ~readinfo_full;
assign rxrd_wait = m_axi_arvalid & ~m_axi_arready;
//#########################################################################
//Read response channel
//#########################################################################
assign m_axi_rready = ~txrr_wait; //pass through
always @( posedge m_axi_aclk )
if ( ~m_axi_aresetn )
m_axi_rdata_reg <= 'b0;
else
m_axi_rdata_reg <= m_axi_rdata;
always @( posedge m_axi_aclk )
if( ~m_axi_aresetn )
begin
txrr_data[31:0] <= 32'b0;
txrr_srcaddr[31:0] <= 32'b0;
txrr_access_reg <= 1'b0;
txrr_access <= 1'b0;
end
else
begin
txrr_access_reg <= m_axi_rready & m_axi_rvalid;
txrr_access <= txrr_access_reg;//added pipeline stage for data
// steer read data according to size & host address lsbs
//all data needs to be right aligned
//(this is due to the Epiphany right aligning all words)
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])
3'd0: txrr_data[7:0] <= m_axi_rdata_reg[7:0];
3'd1: txrr_data[7:0] <= m_axi_rdata_reg[15:8];
3'd2: txrr_data[7:0] <= m_axi_rdata_reg[23:16];
3'd3: txrr_data[7:0] <= m_axi_rdata_reg[31:24];
3'd4: txrr_data[7:0] <= m_axi_rdata_reg[39:32];
3'd5: txrr_data[7:0] <= m_axi_rdata_reg[47:40];
3'd6: txrr_data[7:0] <= m_axi_rdata_reg[55:48];
default: txrr_data[7:0] <= m_axi_rdata_reg[63:56];
endcase
2'd1: // 16b hword
case( readinfo_out[8:7] )
2'd0: txrr_data[15:0] <= m_axi_rdata_reg[15:0];
2'd1: txrr_data[15:0] <= m_axi_rdata_reg[31:16];
2'd2: txrr_data[15:0] <= m_axi_rdata_reg[47:32];
default: txrr_data[15:0] <= m_axi_rdata_reg[63:48];
endcase
2'd2: // 32b word
if( readinfo_out[8] )
txrr_data[31:0] <= m_axi_rdata_reg[63:32];
else
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
// 64b word already defined by defaults above
2'd3:
begin // 64b dword
txrr_data[31:0] <= m_axi_rdata_reg[31:0];
txrr_srcaddr[31:0] <= m_axi_rdata_reg[63:32];
end
endcase
end // else: !if( ~m_axi_aresetn )
endmodule // emaxi
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../memory/hdl")
// End:
/*
copyright (c) 2014 adapteva, inc.
contributed by fred huettig <[email protected]>
contributed by andreas olofsson <[email protected]>
this program is free software: you can redistribute it and/or modify
it under the terms of the gnu general public license as published by
the free software foundation, either version 3 of the license, or
(at your option) any later version.
this program is distributed in the hope that it will be useful,
but without any warranty; without even the implied warranty of
merchantability or fitness for a particular purpose. see the
gnu general public license for more details.
you should have received a copy of the gnu general public license
along with this program (see the file copying). if not, see
<http://www.gnu.org/licenses/>.
*/
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2009 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module writes data to the Audio DAC on the Altera DE1 board. *
* *
******************************************************************************/
module Altera_UP_Audio_Out_Serializer (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
left_channel_data,
left_channel_data_en,
right_channel_data,
right_channel_data_en,
// Bidirectionals
// Outputs
left_channel_fifo_write_space,
right_channel_fifo_write_space,
serial_audio_out_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUDIO_DATA_WIDTH = 16;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
input [AUDIO_DATA_WIDTH:1] left_channel_data;
input left_channel_data_en;
input [AUDIO_DATA_WIDTH:1] right_channel_data;
input right_channel_data_en;
// Bidirectionals
// Outputs
output reg [7:0] left_channel_fifo_write_space;
output reg [7:0] right_channel_fifo_write_space;
output reg serial_audio_out_data;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_left_channel;
wire read_right_channel;
wire left_channel_fifo_is_empty;
wire right_channel_fifo_is_empty;
wire left_channel_fifo_is_full;
wire right_channel_fifo_is_full;
wire [6:0] left_channel_fifo_used;
wire [6:0] right_channel_fifo_used;
wire [AUDIO_DATA_WIDTH:1] left_channel_from_fifo;
wire [AUDIO_DATA_WIDTH:1] right_channel_from_fifo;
// Internal Registers
reg left_channel_was_read;
reg [AUDIO_DATA_WIDTH:1] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_fifo_write_space <= 8'h00;
else
left_channel_fifo_write_space <= 8'h80 - {left_channel_fifo_is_full,left_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
right_channel_fifo_write_space <= 8'h00;
else
right_channel_fifo_write_space <= 8'h80 - {right_channel_fifo_is_full,right_channel_fifo_used};
end
always @(posedge clk)
begin
if (reset == 1'b1)
serial_audio_out_data <= 1'b0;
else
serial_audio_out_data <= data_out_shift_reg[AUDIO_DATA_WIDTH];
end
always @(posedge clk)
begin
if (reset == 1'b1)
left_channel_was_read <= 1'b0;
else if (read_left_channel)
left_channel_was_read <=1'b1;
else if (read_right_channel)
left_channel_was_read <=1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (read_left_channel)
data_out_shift_reg <= left_channel_from_fifo;
else if (read_right_channel)
data_out_shift_reg <= right_channel_from_fifo;
else if (left_right_clk_rising_edge | left_right_clk_falling_edge)
data_out_shift_reg <= {AUDIO_DATA_WIDTH{1'b0}};
else if (bit_clk_falling_edge)
data_out_shift_reg <=
{data_out_shift_reg[(AUDIO_DATA_WIDTH - 1):1], 1'b0};
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign read_left_channel = left_right_clk_rising_edge &
~left_channel_fifo_is_empty &
~right_channel_fifo_is_empty;
assign read_right_channel = left_right_clk_falling_edge &
left_channel_was_read;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_SYNC_FIFO Audio_Out_Left_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (left_channel_data_en & ~left_channel_fifo_is_full),
.write_data (left_channel_data),
.read_en (read_left_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (left_channel_fifo_is_empty),
.fifo_is_full (left_channel_fifo_is_full),
.words_used (left_channel_fifo_used),
.read_data (left_channel_from_fifo)
);
defparam
Audio_Out_Left_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Left_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Left_Channel_FIFO.ADDR_WIDTH = 7;
Altera_UP_SYNC_FIFO Audio_Out_Right_Channel_FIFO(
// Inputs
.clk (clk),
.reset (reset),
.write_en (right_channel_data_en & ~right_channel_fifo_is_full),
.write_data (right_channel_data),
.read_en (read_right_channel),
// Bidirectionals
// Outputs
.fifo_is_empty (right_channel_fifo_is_empty),
.fifo_is_full (right_channel_fifo_is_full),
.words_used (right_channel_fifo_used),
.read_data (right_channel_from_fifo)
);
defparam
Audio_Out_Right_Channel_FIFO.DATA_WIDTH = AUDIO_DATA_WIDTH,
Audio_Out_Right_Channel_FIFO.DATA_DEPTH = 128,
Audio_Out_Right_Channel_FIFO.ADDR_WIDTH = 7;
endmodule
|
`default_nettype none
module SysPLL(input wire refclk,
input wire rst,
output wire sys_clk,
output wire sdr_clk,
output wire pit_clk,
output wire locked);
wire [4:0] sub_wire0;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
assign sys_clk = sub_wire1;
assign sdr_clk = sub_wire2;
assign pit_clk = sub_wire3;
assign locked = sub_wire4;
wire sub_wire5 = refclk;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire4),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "-2790",
altpll_component.clk2_divide_by = 25000000,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 596591,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=npll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "sys_clk"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "sys_clk"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "1.193182"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "1.19318200"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-5000.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "refclk"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "npll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-5000"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "25000000"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "596591"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: sys_clk 0 0 0 0 OUTPUT_CLK_EXT VCC "sys_clk"
// Retrieval info: USED_PORT: sdr_clk 0 0 0 0 OUTPUT_CLK_EXT VCC "sdr_clk"
// Retrieval info: USED_PORT: pit_clk 0 0 0 0 OUTPUT_CLK_EXT VCC "pit_clk"
// Retrieval info: USED_PORT: refclk 0 0 0 0 INPUT_CLK_EXT GND "refclk"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 refclk 0 0 0 0
// Retrieval info: CONNECT: sys_clk 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: sdr_clk 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: pit_clk 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL npll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL npll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
`default_nettype none
//------------------------------------------------------------------
//-- This module implements a 128-bit external LFSR that advances --
//-- 512 states per clock. The polynomial for this LFSR is given --
//-- as: p(x) = x^128 + x^126 + x^101 + x^99 + 1 --
//-- --
//-- Saeed Fouladi Fard, PhD, PMC-Sierra --
//------------------------------------------------------------------
module lfsr
(
input wire clk , // clock, rising edge
input wire reset , // reset, sync, active high. At reset the LFSR is set to all ones
input wire [128-1:0] i_seed , // LFSR seed, picked when init=1
input wire i_init , // When high, the LFSR will be seeded with seed. i_init overrides i_advance
input wire i_advance, // When high, state of the LFSR advances by 512 steps
output wire [512-1:0] o_lfsr // State of the LFSR
);
// Internal signals:
reg [128-1:0] lfsr;
initial lfsr = {(512){1'b1}};
integer i;
// XOR-tree for the LFSR
assign o_lfsr[ 0] = lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[ 1] = lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[ 2] = lfsr[96]^lfsr[98]^lfsr[123]^lfsr[125];
assign o_lfsr[ 3] = lfsr[95]^lfsr[97]^lfsr[122]^lfsr[124];
assign o_lfsr[ 4] = lfsr[94]^lfsr[96]^lfsr[121]^lfsr[123];
assign o_lfsr[ 5] = lfsr[93]^lfsr[95]^lfsr[120]^lfsr[122];
assign o_lfsr[ 6] = lfsr[92]^lfsr[94]^lfsr[119]^lfsr[121];
assign o_lfsr[ 7] = lfsr[91]^lfsr[93]^lfsr[118]^lfsr[120];
assign o_lfsr[ 8] = lfsr[90]^lfsr[92]^lfsr[117]^lfsr[119];
assign o_lfsr[ 9] = lfsr[89]^lfsr[91]^lfsr[116]^lfsr[118];
assign o_lfsr[10] = lfsr[88]^lfsr[90]^lfsr[115]^lfsr[117];
assign o_lfsr[11] = lfsr[87]^lfsr[89]^lfsr[114]^lfsr[116];
assign o_lfsr[12] = lfsr[86]^lfsr[88]^lfsr[113]^lfsr[115];
assign o_lfsr[13] = lfsr[85]^lfsr[87]^lfsr[112]^lfsr[114];
assign o_lfsr[14] = lfsr[84]^lfsr[86]^lfsr[111]^lfsr[113];
assign o_lfsr[15] = lfsr[83]^lfsr[85]^lfsr[110]^lfsr[112];
assign o_lfsr[16] = lfsr[82]^lfsr[84]^lfsr[109]^lfsr[111];
assign o_lfsr[17] = lfsr[81]^lfsr[83]^lfsr[108]^lfsr[110];
assign o_lfsr[18] = lfsr[80]^lfsr[82]^lfsr[107]^lfsr[109];
assign o_lfsr[19] = lfsr[79]^lfsr[81]^lfsr[106]^lfsr[108];
assign o_lfsr[20] = lfsr[78]^lfsr[80]^lfsr[105]^lfsr[107];
assign o_lfsr[21] = lfsr[77]^lfsr[79]^lfsr[104]^lfsr[106];
assign o_lfsr[22] = lfsr[76]^lfsr[78]^lfsr[103]^lfsr[105];
assign o_lfsr[23] = lfsr[75]^lfsr[77]^lfsr[102]^lfsr[104];
assign o_lfsr[24] = lfsr[74]^lfsr[76]^lfsr[101]^lfsr[103];
assign o_lfsr[25] = lfsr[73]^lfsr[75]^lfsr[100]^lfsr[102];
assign o_lfsr[26] = lfsr[72]^lfsr[74]^lfsr[99]^lfsr[101];
assign o_lfsr[27] = lfsr[71]^lfsr[73]^lfsr[98]^lfsr[100];
assign o_lfsr[28] = lfsr[70]^lfsr[72]^lfsr[97]^lfsr[99];
assign o_lfsr[29] = lfsr[69]^lfsr[71]^lfsr[96]^lfsr[98];
assign o_lfsr[30] = lfsr[68]^lfsr[70]^lfsr[95]^lfsr[97];
assign o_lfsr[31] = lfsr[67]^lfsr[69]^lfsr[94]^lfsr[96];
assign o_lfsr[32] = lfsr[66]^lfsr[68]^lfsr[93]^lfsr[95];
assign o_lfsr[33] = lfsr[65]^lfsr[67]^lfsr[92]^lfsr[94];
assign o_lfsr[34] = lfsr[64]^lfsr[66]^lfsr[91]^lfsr[93];
assign o_lfsr[35] = lfsr[63]^lfsr[65]^lfsr[90]^lfsr[92];
assign o_lfsr[36] = lfsr[62]^lfsr[64]^lfsr[89]^lfsr[91];
assign o_lfsr[37] = lfsr[61]^lfsr[63]^lfsr[88]^lfsr[90];
assign o_lfsr[38] = lfsr[60]^lfsr[62]^lfsr[87]^lfsr[89];
assign o_lfsr[39] = lfsr[59]^lfsr[61]^lfsr[86]^lfsr[88];
assign o_lfsr[40] = lfsr[58]^lfsr[60]^lfsr[85]^lfsr[87];
assign o_lfsr[41] = lfsr[57]^lfsr[59]^lfsr[84]^lfsr[86];
assign o_lfsr[42] = lfsr[56]^lfsr[58]^lfsr[83]^lfsr[85];
assign o_lfsr[43] = lfsr[55]^lfsr[57]^lfsr[82]^lfsr[84];
assign o_lfsr[44] = lfsr[54]^lfsr[56]^lfsr[81]^lfsr[83];
assign o_lfsr[45] = lfsr[53]^lfsr[55]^lfsr[80]^lfsr[82];
assign o_lfsr[46] = lfsr[52]^lfsr[54]^lfsr[79]^lfsr[81];
assign o_lfsr[47] = lfsr[51]^lfsr[53]^lfsr[78]^lfsr[80];
assign o_lfsr[48] = lfsr[50]^lfsr[52]^lfsr[77]^lfsr[79];
assign o_lfsr[49] = lfsr[49]^lfsr[51]^lfsr[76]^lfsr[78];
assign o_lfsr[50] = lfsr[48]^lfsr[50]^lfsr[75]^lfsr[77];
assign o_lfsr[51] = lfsr[47]^lfsr[49]^lfsr[74]^lfsr[76];
assign o_lfsr[52] = lfsr[46]^lfsr[48]^lfsr[73]^lfsr[75];
assign o_lfsr[53] = lfsr[45]^lfsr[47]^lfsr[72]^lfsr[74];
assign o_lfsr[54] = lfsr[44]^lfsr[46]^lfsr[71]^lfsr[73];
assign o_lfsr[55] = lfsr[43]^lfsr[45]^lfsr[70]^lfsr[72];
assign o_lfsr[56] = lfsr[42]^lfsr[44]^lfsr[69]^lfsr[71];
assign o_lfsr[57] = lfsr[41]^lfsr[43]^lfsr[68]^lfsr[70];
assign o_lfsr[58] = lfsr[40]^lfsr[42]^lfsr[67]^lfsr[69];
assign o_lfsr[59] = lfsr[39]^lfsr[41]^lfsr[66]^lfsr[68];
assign o_lfsr[60] = lfsr[38]^lfsr[40]^lfsr[65]^lfsr[67];
assign o_lfsr[61] = lfsr[37]^lfsr[39]^lfsr[64]^lfsr[66];
assign o_lfsr[62] = lfsr[36]^lfsr[38]^lfsr[63]^lfsr[65];
assign o_lfsr[63] = lfsr[35]^lfsr[37]^lfsr[62]^lfsr[64];
assign o_lfsr[64] = lfsr[34]^lfsr[36]^lfsr[61]^lfsr[63];
assign o_lfsr[65] = lfsr[33]^lfsr[35]^lfsr[60]^lfsr[62];
assign o_lfsr[66] = lfsr[32]^lfsr[34]^lfsr[59]^lfsr[61];
assign o_lfsr[67] = lfsr[31]^lfsr[33]^lfsr[58]^lfsr[60];
assign o_lfsr[68] = lfsr[30]^lfsr[32]^lfsr[57]^lfsr[59];
assign o_lfsr[69] = lfsr[29]^lfsr[31]^lfsr[56]^lfsr[58];
assign o_lfsr[70] = lfsr[28]^lfsr[30]^lfsr[55]^lfsr[57];
assign o_lfsr[71] = lfsr[27]^lfsr[29]^lfsr[54]^lfsr[56];
assign o_lfsr[72] = lfsr[26]^lfsr[28]^lfsr[53]^lfsr[55];
assign o_lfsr[73] = lfsr[25]^lfsr[27]^lfsr[52]^lfsr[54];
assign o_lfsr[74] = lfsr[24]^lfsr[26]^lfsr[51]^lfsr[53];
assign o_lfsr[75] = lfsr[23]^lfsr[25]^lfsr[50]^lfsr[52];
assign o_lfsr[76] = lfsr[22]^lfsr[24]^lfsr[49]^lfsr[51];
assign o_lfsr[77] = lfsr[21]^lfsr[23]^lfsr[48]^lfsr[50];
assign o_lfsr[78] = lfsr[20]^lfsr[22]^lfsr[47]^lfsr[49];
assign o_lfsr[79] = lfsr[19]^lfsr[21]^lfsr[46]^lfsr[48];
assign o_lfsr[80] = lfsr[18]^lfsr[20]^lfsr[45]^lfsr[47];
assign o_lfsr[81] = lfsr[17]^lfsr[19]^lfsr[44]^lfsr[46];
assign o_lfsr[82] = lfsr[16]^lfsr[18]^lfsr[43]^lfsr[45];
assign o_lfsr[83] = lfsr[15]^lfsr[17]^lfsr[42]^lfsr[44];
assign o_lfsr[84] = lfsr[14]^lfsr[16]^lfsr[41]^lfsr[43];
assign o_lfsr[85] = lfsr[13]^lfsr[15]^lfsr[40]^lfsr[42];
assign o_lfsr[86] = lfsr[12]^lfsr[14]^lfsr[39]^lfsr[41];
assign o_lfsr[87] = lfsr[11]^lfsr[13]^lfsr[38]^lfsr[40];
assign o_lfsr[88] = lfsr[10]^lfsr[12]^lfsr[37]^lfsr[39];
assign o_lfsr[89] = lfsr[ 9]^lfsr[11]^lfsr[36]^lfsr[38];
assign o_lfsr[90] = lfsr[ 8]^lfsr[10]^lfsr[35]^lfsr[37];
assign o_lfsr[91] = lfsr[ 7]^lfsr[ 9]^lfsr[34]^lfsr[36];
assign o_lfsr[92] = lfsr[ 6]^lfsr[ 8]^lfsr[33]^lfsr[35];
assign o_lfsr[93] = lfsr[ 5]^lfsr[ 7]^lfsr[32]^lfsr[34];
assign o_lfsr[94] = lfsr[ 4]^lfsr[ 6]^lfsr[31]^lfsr[33];
assign o_lfsr[95] = lfsr[ 3]^lfsr[ 5]^lfsr[30]^lfsr[32];
assign o_lfsr[96] = lfsr[ 2]^lfsr[ 4]^lfsr[29]^lfsr[31];
assign o_lfsr[97] = lfsr[ 1]^lfsr[ 3]^lfsr[28]^lfsr[30];
assign o_lfsr[98] = lfsr[ 0]^lfsr[ 2]^lfsr[27]^lfsr[29];
assign o_lfsr[99] = lfsr[ 1]^lfsr[26]^lfsr[28]^lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[100] = lfsr[ 0]^lfsr[25]^lfsr[27]^lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[101] = lfsr[24]^lfsr[26]^lfsr[96]^lfsr[100]^lfsr[123]^lfsr[127];
assign o_lfsr[102] = lfsr[23]^lfsr[25]^lfsr[95]^lfsr[99]^lfsr[122]^lfsr[126];
assign o_lfsr[103] = lfsr[22]^lfsr[24]^lfsr[94]^lfsr[98]^lfsr[121]^lfsr[125];
assign o_lfsr[104] = lfsr[21]^lfsr[23]^lfsr[93]^lfsr[97]^lfsr[120]^lfsr[124];
assign o_lfsr[105] = lfsr[20]^lfsr[22]^lfsr[92]^lfsr[96]^lfsr[119]^lfsr[123];
assign o_lfsr[106] = lfsr[19]^lfsr[21]^lfsr[91]^lfsr[95]^lfsr[118]^lfsr[122];
assign o_lfsr[107] = lfsr[18]^lfsr[20]^lfsr[90]^lfsr[94]^lfsr[117]^lfsr[121];
assign o_lfsr[108] = lfsr[17]^lfsr[19]^lfsr[89]^lfsr[93]^lfsr[116]^lfsr[120];
assign o_lfsr[109] = lfsr[16]^lfsr[18]^lfsr[88]^lfsr[92]^lfsr[115]^lfsr[119];
assign o_lfsr[110] = lfsr[15]^lfsr[17]^lfsr[87]^lfsr[91]^lfsr[114]^lfsr[118];
assign o_lfsr[111] = lfsr[14]^lfsr[16]^lfsr[86]^lfsr[90]^lfsr[113]^lfsr[117];
assign o_lfsr[112] = lfsr[13]^lfsr[15]^lfsr[85]^lfsr[89]^lfsr[112]^lfsr[116];
assign o_lfsr[113] = lfsr[12]^lfsr[14]^lfsr[84]^lfsr[88]^lfsr[111]^lfsr[115];
assign o_lfsr[114] = lfsr[11]^lfsr[13]^lfsr[83]^lfsr[87]^lfsr[110]^lfsr[114];
assign o_lfsr[115] = lfsr[10]^lfsr[12]^lfsr[82]^lfsr[86]^lfsr[109]^lfsr[113];
assign o_lfsr[116] = lfsr[ 9]^lfsr[11]^lfsr[81]^lfsr[85]^lfsr[108]^lfsr[112];
assign o_lfsr[117] = lfsr[ 8]^lfsr[10]^lfsr[80]^lfsr[84]^lfsr[107]^lfsr[111];
assign o_lfsr[118] = lfsr[ 7]^lfsr[ 9]^lfsr[79]^lfsr[83]^lfsr[106]^lfsr[110];
assign o_lfsr[119] = lfsr[ 6]^lfsr[ 8]^lfsr[78]^lfsr[82]^lfsr[105]^lfsr[109];
assign o_lfsr[120] = lfsr[ 5]^lfsr[ 7]^lfsr[77]^lfsr[81]^lfsr[104]^lfsr[108];
assign o_lfsr[121] = lfsr[ 4]^lfsr[ 6]^lfsr[76]^lfsr[80]^lfsr[103]^lfsr[107];
assign o_lfsr[122] = lfsr[ 3]^lfsr[ 5]^lfsr[75]^lfsr[79]^lfsr[102]^lfsr[106];
assign o_lfsr[123] = lfsr[ 2]^lfsr[ 4]^lfsr[74]^lfsr[78]^lfsr[101]^lfsr[105];
assign o_lfsr[124] = lfsr[ 1]^lfsr[ 3]^lfsr[73]^lfsr[77]^lfsr[100]^lfsr[104];
assign o_lfsr[125] = lfsr[ 0]^lfsr[ 2]^lfsr[72]^lfsr[76]^lfsr[99]^lfsr[103];
assign o_lfsr[126] = lfsr[ 1]^lfsr[71]^lfsr[75]^lfsr[100]^lfsr[102]^lfsr[125]^lfsr[127];
assign o_lfsr[127] = lfsr[ 0]^lfsr[70]^lfsr[74]^lfsr[99]^lfsr[101]^lfsr[124]^lfsr[126];
assign o_lfsr[128] = lfsr[69]^lfsr[73]^lfsr[123]^lfsr[127];
assign o_lfsr[129] = lfsr[68]^lfsr[72]^lfsr[122]^lfsr[126];
assign o_lfsr[130] = lfsr[67]^lfsr[71]^lfsr[121]^lfsr[125];
assign o_lfsr[131] = lfsr[66]^lfsr[70]^lfsr[120]^lfsr[124];
assign o_lfsr[132] = lfsr[65]^lfsr[69]^lfsr[119]^lfsr[123];
assign o_lfsr[133] = lfsr[64]^lfsr[68]^lfsr[118]^lfsr[122];
assign o_lfsr[134] = lfsr[63]^lfsr[67]^lfsr[117]^lfsr[121];
assign o_lfsr[135] = lfsr[62]^lfsr[66]^lfsr[116]^lfsr[120];
assign o_lfsr[136] = lfsr[61]^lfsr[65]^lfsr[115]^lfsr[119];
assign o_lfsr[137] = lfsr[60]^lfsr[64]^lfsr[114]^lfsr[118];
assign o_lfsr[138] = lfsr[59]^lfsr[63]^lfsr[113]^lfsr[117];
assign o_lfsr[139] = lfsr[58]^lfsr[62]^lfsr[112]^lfsr[116];
assign o_lfsr[140] = lfsr[57]^lfsr[61]^lfsr[111]^lfsr[115];
assign o_lfsr[141] = lfsr[56]^lfsr[60]^lfsr[110]^lfsr[114];
assign o_lfsr[142] = lfsr[55]^lfsr[59]^lfsr[109]^lfsr[113];
assign o_lfsr[143] = lfsr[54]^lfsr[58]^lfsr[108]^lfsr[112];
assign o_lfsr[144] = lfsr[53]^lfsr[57]^lfsr[107]^lfsr[111];
assign o_lfsr[145] = lfsr[52]^lfsr[56]^lfsr[106]^lfsr[110];
assign o_lfsr[146] = lfsr[51]^lfsr[55]^lfsr[105]^lfsr[109];
assign o_lfsr[147] = lfsr[50]^lfsr[54]^lfsr[104]^lfsr[108];
assign o_lfsr[148] = lfsr[49]^lfsr[53]^lfsr[103]^lfsr[107];
assign o_lfsr[149] = lfsr[48]^lfsr[52]^lfsr[102]^lfsr[106];
assign o_lfsr[150] = lfsr[47]^lfsr[51]^lfsr[101]^lfsr[105];
assign o_lfsr[151] = lfsr[46]^lfsr[50]^lfsr[100]^lfsr[104];
assign o_lfsr[152] = lfsr[45]^lfsr[49]^lfsr[99]^lfsr[103];
assign o_lfsr[153] = lfsr[44]^lfsr[48]^lfsr[98]^lfsr[102];
assign o_lfsr[154] = lfsr[43]^lfsr[47]^lfsr[97]^lfsr[101];
assign o_lfsr[155] = lfsr[42]^lfsr[46]^lfsr[96]^lfsr[100];
assign o_lfsr[156] = lfsr[41]^lfsr[45]^lfsr[95]^lfsr[99];
assign o_lfsr[157] = lfsr[40]^lfsr[44]^lfsr[94]^lfsr[98];
assign o_lfsr[158] = lfsr[39]^lfsr[43]^lfsr[93]^lfsr[97];
assign o_lfsr[159] = lfsr[38]^lfsr[42]^lfsr[92]^lfsr[96];
assign o_lfsr[160] = lfsr[37]^lfsr[41]^lfsr[91]^lfsr[95];
assign o_lfsr[161] = lfsr[36]^lfsr[40]^lfsr[90]^lfsr[94];
assign o_lfsr[162] = lfsr[35]^lfsr[39]^lfsr[89]^lfsr[93];
assign o_lfsr[163] = lfsr[34]^lfsr[38]^lfsr[88]^lfsr[92];
assign o_lfsr[164] = lfsr[33]^lfsr[37]^lfsr[87]^lfsr[91];
assign o_lfsr[165] = lfsr[32]^lfsr[36]^lfsr[86]^lfsr[90];
assign o_lfsr[166] = lfsr[31]^lfsr[35]^lfsr[85]^lfsr[89];
assign o_lfsr[167] = lfsr[30]^lfsr[34]^lfsr[84]^lfsr[88];
assign o_lfsr[168] = lfsr[29]^lfsr[33]^lfsr[83]^lfsr[87];
assign o_lfsr[169] = lfsr[28]^lfsr[32]^lfsr[82]^lfsr[86];
assign o_lfsr[170] = lfsr[27]^lfsr[31]^lfsr[81]^lfsr[85];
assign o_lfsr[171] = lfsr[26]^lfsr[30]^lfsr[80]^lfsr[84];
assign o_lfsr[172] = lfsr[25]^lfsr[29]^lfsr[79]^lfsr[83];
assign o_lfsr[173] = lfsr[24]^lfsr[28]^lfsr[78]^lfsr[82];
assign o_lfsr[174] = lfsr[23]^lfsr[27]^lfsr[77]^lfsr[81];
assign o_lfsr[175] = lfsr[22]^lfsr[26]^lfsr[76]^lfsr[80];
assign o_lfsr[176] = lfsr[21]^lfsr[25]^lfsr[75]^lfsr[79];
assign o_lfsr[177] = lfsr[20]^lfsr[24]^lfsr[74]^lfsr[78];
assign o_lfsr[178] = lfsr[19]^lfsr[23]^lfsr[73]^lfsr[77];
assign o_lfsr[179] = lfsr[18]^lfsr[22]^lfsr[72]^lfsr[76];
assign o_lfsr[180] = lfsr[17]^lfsr[21]^lfsr[71]^lfsr[75];
assign o_lfsr[181] = lfsr[16]^lfsr[20]^lfsr[70]^lfsr[74];
assign o_lfsr[182] = lfsr[15]^lfsr[19]^lfsr[69]^lfsr[73];
assign o_lfsr[183] = lfsr[14]^lfsr[18]^lfsr[68]^lfsr[72];
assign o_lfsr[184] = lfsr[13]^lfsr[17]^lfsr[67]^lfsr[71];
assign o_lfsr[185] = lfsr[12]^lfsr[16]^lfsr[66]^lfsr[70];
assign o_lfsr[186] = lfsr[11]^lfsr[15]^lfsr[65]^lfsr[69];
assign o_lfsr[187] = lfsr[10]^lfsr[14]^lfsr[64]^lfsr[68];
assign o_lfsr[188] = lfsr[ 9]^lfsr[13]^lfsr[63]^lfsr[67];
assign o_lfsr[189] = lfsr[ 8]^lfsr[12]^lfsr[62]^lfsr[66];
assign o_lfsr[190] = lfsr[ 7]^lfsr[11]^lfsr[61]^lfsr[65];
assign o_lfsr[191] = lfsr[ 6]^lfsr[10]^lfsr[60]^lfsr[64];
assign o_lfsr[192] = lfsr[ 5]^lfsr[ 9]^lfsr[59]^lfsr[63];
assign o_lfsr[193] = lfsr[ 4]^lfsr[ 8]^lfsr[58]^lfsr[62];
assign o_lfsr[194] = lfsr[ 3]^lfsr[ 7]^lfsr[57]^lfsr[61];
assign o_lfsr[195] = lfsr[ 2]^lfsr[ 6]^lfsr[56]^lfsr[60];
assign o_lfsr[196] = lfsr[ 1]^lfsr[ 5]^lfsr[55]^lfsr[59];
assign o_lfsr[197] = lfsr[ 0]^lfsr[ 4]^lfsr[54]^lfsr[58];
assign o_lfsr[198] = lfsr[ 3]^lfsr[53]^lfsr[57]^lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[199] = lfsr[ 2]^lfsr[52]^lfsr[56]^lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[200] = lfsr[ 1]^lfsr[51]^lfsr[55]^lfsr[96]^lfsr[98]^lfsr[123]^lfsr[125];
assign o_lfsr[201] = lfsr[ 0]^lfsr[50]^lfsr[54]^lfsr[95]^lfsr[97]^lfsr[122]^lfsr[124];
assign o_lfsr[202] = lfsr[49]^lfsr[53]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[100]^lfsr[121]^lfsr[123]^lfsr[125]^lfsr[127];
assign o_lfsr[203] = lfsr[48]^lfsr[52]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[99]^lfsr[120]^lfsr[122]^lfsr[124]^lfsr[126];
assign o_lfsr[204] = lfsr[47]^lfsr[51]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[119]^lfsr[121]^lfsr[123]^lfsr[125];
assign o_lfsr[205] = lfsr[46]^lfsr[50]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[118]^lfsr[120]^lfsr[122]^lfsr[124];
assign o_lfsr[206] = lfsr[45]^lfsr[49]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[117]^lfsr[119]^lfsr[121]^lfsr[123];
assign o_lfsr[207] = lfsr[44]^lfsr[48]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[116]^lfsr[118]^lfsr[120]^lfsr[122];
assign o_lfsr[208] = lfsr[43]^lfsr[47]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[115]^lfsr[117]^lfsr[119]^lfsr[121];
assign o_lfsr[209] = lfsr[42]^lfsr[46]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[114]^lfsr[116]^lfsr[118]^lfsr[120];
assign o_lfsr[210] = lfsr[41]^lfsr[45]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[113]^lfsr[115]^lfsr[117]^lfsr[119];
assign o_lfsr[211] = lfsr[40]^lfsr[44]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[112]^lfsr[114]^lfsr[116]^lfsr[118];
assign o_lfsr[212] = lfsr[39]^lfsr[43]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[111]^lfsr[113]^lfsr[115]^lfsr[117];
assign o_lfsr[213] = lfsr[38]^lfsr[42]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[110]^lfsr[112]^lfsr[114]^lfsr[116];
assign o_lfsr[214] = lfsr[37]^lfsr[41]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[109]^lfsr[111]^lfsr[113]^lfsr[115];
assign o_lfsr[215] = lfsr[36]^lfsr[40]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[108]^lfsr[110]^lfsr[112]^lfsr[114];
assign o_lfsr[216] = lfsr[35]^lfsr[39]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[107]^lfsr[109]^lfsr[111]^lfsr[113];
assign o_lfsr[217] = lfsr[34]^lfsr[38]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[106]^lfsr[108]^lfsr[110]^lfsr[112];
assign o_lfsr[218] = lfsr[33]^lfsr[37]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[105]^lfsr[107]^lfsr[109]^lfsr[111];
assign o_lfsr[219] = lfsr[32]^lfsr[36]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[104]^lfsr[106]^lfsr[108]^lfsr[110];
assign o_lfsr[220] = lfsr[31]^lfsr[35]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[103]^lfsr[105]^lfsr[107]^lfsr[109];
assign o_lfsr[221] = lfsr[30]^lfsr[34]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[102]^lfsr[104]^lfsr[106]^lfsr[108];
assign o_lfsr[222] = lfsr[29]^lfsr[33]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[101]^lfsr[103]^lfsr[105]^lfsr[107];
assign o_lfsr[223] = lfsr[28]^lfsr[32]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[100]^lfsr[102]^lfsr[104]^lfsr[106];
assign o_lfsr[224] = lfsr[27]^lfsr[31]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[99]^lfsr[101]^lfsr[103]^lfsr[105];
assign o_lfsr[225] = lfsr[26]^lfsr[30]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[98]^lfsr[100]^lfsr[102]^lfsr[104];
assign o_lfsr[226] = lfsr[25]^lfsr[29]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[97]^lfsr[99]^lfsr[101]^lfsr[103];
assign o_lfsr[227] = lfsr[24]^lfsr[28]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[96]^lfsr[98]^lfsr[100]^lfsr[102];
assign o_lfsr[228] = lfsr[23]^lfsr[27]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[95]^lfsr[97]^lfsr[99]^lfsr[101];
assign o_lfsr[229] = lfsr[22]^lfsr[26]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[100];
assign o_lfsr[230] = lfsr[21]^lfsr[25]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[99];
assign o_lfsr[231] = lfsr[20]^lfsr[24]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[98];
assign o_lfsr[232] = lfsr[19]^lfsr[23]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[97];
assign o_lfsr[233] = lfsr[18]^lfsr[22]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[96];
assign o_lfsr[234] = lfsr[17]^lfsr[21]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[95];
assign o_lfsr[235] = lfsr[16]^lfsr[20]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[94];
assign o_lfsr[236] = lfsr[15]^lfsr[19]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[93];
assign o_lfsr[237] = lfsr[14]^lfsr[18]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[92];
assign o_lfsr[238] = lfsr[13]^lfsr[17]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[91];
assign o_lfsr[239] = lfsr[12]^lfsr[16]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[90];
assign o_lfsr[240] = lfsr[11]^lfsr[15]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[89];
assign o_lfsr[241] = lfsr[10]^lfsr[14]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[88];
assign o_lfsr[242] = lfsr[ 9]^lfsr[13]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[87];
assign o_lfsr[243] = lfsr[ 8]^lfsr[12]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[86];
assign o_lfsr[244] = lfsr[ 7]^lfsr[11]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[85];
assign o_lfsr[245] = lfsr[ 6]^lfsr[10]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[84];
assign o_lfsr[246] = lfsr[ 5]^lfsr[ 9]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[83];
assign o_lfsr[247] = lfsr[ 4]^lfsr[ 8]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[82];
assign o_lfsr[248] = lfsr[ 3]^lfsr[ 7]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[81];
assign o_lfsr[249] = lfsr[ 2]^lfsr[ 6]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[80];
assign o_lfsr[250] = lfsr[ 1]^lfsr[ 5]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[79];
assign o_lfsr[251] = lfsr[ 0]^lfsr[ 4]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[78];
assign o_lfsr[252] = lfsr[ 3]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[253] = lfsr[ 2]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[254] = lfsr[ 1]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[96]^lfsr[98]^lfsr[123]^lfsr[125];
assign o_lfsr[255] = lfsr[ 0]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[95]^lfsr[97]^lfsr[122]^lfsr[124];
assign o_lfsr[256] = lfsr[40]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[100]^lfsr[121]^lfsr[123]^lfsr[125]^lfsr[127];
assign o_lfsr[257] = lfsr[39]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[99]^lfsr[120]^lfsr[122]^lfsr[124]^lfsr[126];
assign o_lfsr[258] = lfsr[38]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[119]^lfsr[121]^lfsr[123]^lfsr[125];
assign o_lfsr[259] = lfsr[37]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[118]^lfsr[120]^lfsr[122]^lfsr[124];
assign o_lfsr[260] = lfsr[36]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[117]^lfsr[119]^lfsr[121]^lfsr[123];
assign o_lfsr[261] = lfsr[35]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[116]^lfsr[118]^lfsr[120]^lfsr[122];
assign o_lfsr[262] = lfsr[34]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[115]^lfsr[117]^lfsr[119]^lfsr[121];
assign o_lfsr[263] = lfsr[33]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[114]^lfsr[116]^lfsr[118]^lfsr[120];
assign o_lfsr[264] = lfsr[32]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[113]^lfsr[115]^lfsr[117]^lfsr[119];
assign o_lfsr[265] = lfsr[31]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[112]^lfsr[114]^lfsr[116]^lfsr[118];
assign o_lfsr[266] = lfsr[30]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[111]^lfsr[113]^lfsr[115]^lfsr[117];
assign o_lfsr[267] = lfsr[29]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[110]^lfsr[112]^lfsr[114]^lfsr[116];
assign o_lfsr[268] = lfsr[28]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[109]^lfsr[111]^lfsr[113]^lfsr[115];
assign o_lfsr[269] = lfsr[27]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[108]^lfsr[110]^lfsr[112]^lfsr[114];
assign o_lfsr[270] = lfsr[26]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[107]^lfsr[109]^lfsr[111]^lfsr[113];
assign o_lfsr[271] = lfsr[25]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[106]^lfsr[108]^lfsr[110]^lfsr[112];
assign o_lfsr[272] = lfsr[24]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[105]^lfsr[107]^lfsr[109]^lfsr[111];
assign o_lfsr[273] = lfsr[23]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[104]^lfsr[106]^lfsr[108]^lfsr[110];
assign o_lfsr[274] = lfsr[22]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[103]^lfsr[105]^lfsr[107]^lfsr[109];
assign o_lfsr[275] = lfsr[21]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[102]^lfsr[104]^lfsr[106]^lfsr[108];
assign o_lfsr[276] = lfsr[20]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[101]^lfsr[103]^lfsr[105]^lfsr[107];
assign o_lfsr[277] = lfsr[19]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[100]^lfsr[102]^lfsr[104]^lfsr[106];
assign o_lfsr[278] = lfsr[18]^lfsr[20]^lfsr[22]^lfsr[24]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[99]^lfsr[101]^lfsr[103]^lfsr[105];
assign o_lfsr[279] = lfsr[17]^lfsr[19]^lfsr[21]^lfsr[23]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[98]^lfsr[100]^lfsr[102]^lfsr[104];
assign o_lfsr[280] = lfsr[16]^lfsr[18]^lfsr[20]^lfsr[22]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[97]^lfsr[99]^lfsr[101]^lfsr[103];
assign o_lfsr[281] = lfsr[15]^lfsr[17]^lfsr[19]^lfsr[21]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[96]^lfsr[98]^lfsr[100]^lfsr[102];
assign o_lfsr[282] = lfsr[14]^lfsr[16]^lfsr[18]^lfsr[20]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[95]^lfsr[97]^lfsr[99]^lfsr[101];
assign o_lfsr[283] = lfsr[13]^lfsr[15]^lfsr[17]^lfsr[19]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[94]^lfsr[96]^lfsr[98]^lfsr[100];
assign o_lfsr[284] = lfsr[12]^lfsr[14]^lfsr[16]^lfsr[18]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[93]^lfsr[95]^lfsr[97]^lfsr[99];
assign o_lfsr[285] = lfsr[11]^lfsr[13]^lfsr[15]^lfsr[17]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[92]^lfsr[94]^lfsr[96]^lfsr[98];
assign o_lfsr[286] = lfsr[10]^lfsr[12]^lfsr[14]^lfsr[16]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[91]^lfsr[93]^lfsr[95]^lfsr[97];
assign o_lfsr[287] = lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[15]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[90]^lfsr[92]^lfsr[94]^lfsr[96];
assign o_lfsr[288] = lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[14]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[89]^lfsr[91]^lfsr[93]^lfsr[95];
assign o_lfsr[289] = lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[88]^lfsr[90]^lfsr[92]^lfsr[94];
assign o_lfsr[290] = lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[87]^lfsr[89]^lfsr[91]^lfsr[93];
assign o_lfsr[291] = lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[86]^lfsr[88]^lfsr[90]^lfsr[92];
assign o_lfsr[292] = lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[85]^lfsr[87]^lfsr[89]^lfsr[91];
assign o_lfsr[293] = lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[84]^lfsr[86]^lfsr[88]^lfsr[90];
assign o_lfsr[294] = lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[83]^lfsr[85]^lfsr[87]^lfsr[89];
assign o_lfsr[295] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[88];
assign o_lfsr[296] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[87];
assign o_lfsr[297] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[86]^lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[298] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[85]^lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[299] = lfsr[ 1]^lfsr[ 3]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[84]^lfsr[96]^lfsr[100]^lfsr[123]^lfsr[127];
assign o_lfsr[300] = lfsr[ 0]^lfsr[ 2]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[83]^lfsr[95]^lfsr[99]^lfsr[122]^lfsr[126];
assign o_lfsr[301] = lfsr[ 1]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[82]^lfsr[94]^lfsr[100]^lfsr[121]^lfsr[127];
assign o_lfsr[302] = lfsr[ 0]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[81]^lfsr[93]^lfsr[99]^lfsr[120]^lfsr[126];
assign o_lfsr[303] = lfsr[20]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[80]^lfsr[92]^lfsr[100]^lfsr[119]^lfsr[127];
assign o_lfsr[304] = lfsr[19]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[79]^lfsr[91]^lfsr[99]^lfsr[118]^lfsr[126];
assign o_lfsr[305] = lfsr[18]^lfsr[20]^lfsr[22]^lfsr[24]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[78]^lfsr[90]^lfsr[98]^lfsr[117]^lfsr[125];
assign o_lfsr[306] = lfsr[17]^lfsr[19]^lfsr[21]^lfsr[23]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[77]^lfsr[89]^lfsr[97]^lfsr[116]^lfsr[124];
assign o_lfsr[307] = lfsr[16]^lfsr[18]^lfsr[20]^lfsr[22]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[76]^lfsr[88]^lfsr[96]^lfsr[115]^lfsr[123];
assign o_lfsr[308] = lfsr[15]^lfsr[17]^lfsr[19]^lfsr[21]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[75]^lfsr[87]^lfsr[95]^lfsr[114]^lfsr[122];
assign o_lfsr[309] = lfsr[14]^lfsr[16]^lfsr[18]^lfsr[20]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[74]^lfsr[86]^lfsr[94]^lfsr[113]^lfsr[121];
assign o_lfsr[310] = lfsr[13]^lfsr[15]^lfsr[17]^lfsr[19]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[73]^lfsr[85]^lfsr[93]^lfsr[112]^lfsr[120];
assign o_lfsr[311] = lfsr[12]^lfsr[14]^lfsr[16]^lfsr[18]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[72]^lfsr[84]^lfsr[92]^lfsr[111]^lfsr[119];
assign o_lfsr[312] = lfsr[11]^lfsr[13]^lfsr[15]^lfsr[17]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[71]^lfsr[83]^lfsr[91]^lfsr[110]^lfsr[118];
assign o_lfsr[313] = lfsr[10]^lfsr[12]^lfsr[14]^lfsr[16]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[70]^lfsr[82]^lfsr[90]^lfsr[109]^lfsr[117];
assign o_lfsr[314] = lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[15]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[69]^lfsr[81]^lfsr[89]^lfsr[108]^lfsr[116];
assign o_lfsr[315] = lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[14]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[68]^lfsr[80]^lfsr[88]^lfsr[107]^lfsr[115];
assign o_lfsr[316] = lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[67]^lfsr[79]^lfsr[87]^lfsr[106]^lfsr[114];
assign o_lfsr[317] = lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[66]^lfsr[78]^lfsr[86]^lfsr[105]^lfsr[113];
assign o_lfsr[318] = lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[65]^lfsr[77]^lfsr[85]^lfsr[104]^lfsr[112];
assign o_lfsr[319] = lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[64]^lfsr[76]^lfsr[84]^lfsr[103]^lfsr[111];
assign o_lfsr[320] = lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[63]^lfsr[75]^lfsr[83]^lfsr[102]^lfsr[110];
assign o_lfsr[321] = lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[62]^lfsr[74]^lfsr[82]^lfsr[101]^lfsr[109];
assign o_lfsr[322] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[61]^lfsr[73]^lfsr[81]^lfsr[100]^lfsr[108];
assign o_lfsr[323] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[60]^lfsr[72]^lfsr[80]^lfsr[99]^lfsr[107];
assign o_lfsr[324] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[59]^lfsr[71]^lfsr[79]^lfsr[100]^lfsr[106]^lfsr[125]^lfsr[127];
assign o_lfsr[325] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[58]^lfsr[70]^lfsr[78]^lfsr[99]^lfsr[105]^lfsr[124]^lfsr[126];
assign o_lfsr[326] = lfsr[ 1]^lfsr[ 3]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[57]^lfsr[69]^lfsr[77]^lfsr[100]^lfsr[104]^lfsr[123]^lfsr[127];
assign o_lfsr[327] = lfsr[ 0]^lfsr[ 2]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[56]^lfsr[68]^lfsr[76]^lfsr[99]^lfsr[103]^lfsr[122]^lfsr[126];
assign o_lfsr[328] = lfsr[ 1]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[55]^lfsr[67]^lfsr[75]^lfsr[100]^lfsr[102]^lfsr[121]^lfsr[127];
assign o_lfsr[329] = lfsr[ 0]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[54]^lfsr[66]^lfsr[74]^lfsr[99]^lfsr[101]^lfsr[120]^lfsr[126];
assign o_lfsr[330] = lfsr[20]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[53]^lfsr[65]^lfsr[73]^lfsr[119]^lfsr[127];
assign o_lfsr[331] = lfsr[19]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[52]^lfsr[64]^lfsr[72]^lfsr[118]^lfsr[126];
assign o_lfsr[332] = lfsr[18]^lfsr[20]^lfsr[22]^lfsr[24]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[51]^lfsr[63]^lfsr[71]^lfsr[117]^lfsr[125];
assign o_lfsr[333] = lfsr[17]^lfsr[19]^lfsr[21]^lfsr[23]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[50]^lfsr[62]^lfsr[70]^lfsr[116]^lfsr[124];
assign o_lfsr[334] = lfsr[16]^lfsr[18]^lfsr[20]^lfsr[22]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[49]^lfsr[61]^lfsr[69]^lfsr[115]^lfsr[123];
assign o_lfsr[335] = lfsr[15]^lfsr[17]^lfsr[19]^lfsr[21]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[48]^lfsr[60]^lfsr[68]^lfsr[114]^lfsr[122];
assign o_lfsr[336] = lfsr[14]^lfsr[16]^lfsr[18]^lfsr[20]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[47]^lfsr[59]^lfsr[67]^lfsr[113]^lfsr[121];
assign o_lfsr[337] = lfsr[13]^lfsr[15]^lfsr[17]^lfsr[19]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[46]^lfsr[58]^lfsr[66]^lfsr[112]^lfsr[120];
assign o_lfsr[338] = lfsr[12]^lfsr[14]^lfsr[16]^lfsr[18]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[45]^lfsr[57]^lfsr[65]^lfsr[111]^lfsr[119];
assign o_lfsr[339] = lfsr[11]^lfsr[13]^lfsr[15]^lfsr[17]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[44]^lfsr[56]^lfsr[64]^lfsr[110]^lfsr[118];
assign o_lfsr[340] = lfsr[10]^lfsr[12]^lfsr[14]^lfsr[16]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[43]^lfsr[55]^lfsr[63]^lfsr[109]^lfsr[117];
assign o_lfsr[341] = lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[15]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[42]^lfsr[54]^lfsr[62]^lfsr[108]^lfsr[116];
assign o_lfsr[342] = lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[14]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[41]^lfsr[53]^lfsr[61]^lfsr[107]^lfsr[115];
assign o_lfsr[343] = lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[40]^lfsr[52]^lfsr[60]^lfsr[106]^lfsr[114];
assign o_lfsr[344] = lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[39]^lfsr[51]^lfsr[59]^lfsr[105]^lfsr[113];
assign o_lfsr[345] = lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[38]^lfsr[50]^lfsr[58]^lfsr[104]^lfsr[112];
assign o_lfsr[346] = lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[37]^lfsr[49]^lfsr[57]^lfsr[103]^lfsr[111];
assign o_lfsr[347] = lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[36]^lfsr[48]^lfsr[56]^lfsr[102]^lfsr[110];
assign o_lfsr[348] = lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[35]^lfsr[47]^lfsr[55]^lfsr[101]^lfsr[109];
assign o_lfsr[349] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[34]^lfsr[46]^lfsr[54]^lfsr[100]^lfsr[108];
assign o_lfsr[350] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[33]^lfsr[45]^lfsr[53]^lfsr[99]^lfsr[107];
assign o_lfsr[351] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[32]^lfsr[44]^lfsr[52]^lfsr[100]^lfsr[106]^lfsr[125]^lfsr[127];
assign o_lfsr[352] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[31]^lfsr[43]^lfsr[51]^lfsr[99]^lfsr[105]^lfsr[124]^lfsr[126];
assign o_lfsr[353] = lfsr[ 1]^lfsr[ 3]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[30]^lfsr[42]^lfsr[50]^lfsr[100]^lfsr[104]^lfsr[123]^lfsr[127];
assign o_lfsr[354] = lfsr[ 0]^lfsr[ 2]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[29]^lfsr[41]^lfsr[49]^lfsr[99]^lfsr[103]^lfsr[122]^lfsr[126];
assign o_lfsr[355] = lfsr[ 1]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[28]^lfsr[40]^lfsr[48]^lfsr[100]^lfsr[102]^lfsr[121]^lfsr[127];
assign o_lfsr[356] = lfsr[ 0]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[27]^lfsr[39]^lfsr[47]^lfsr[99]^lfsr[101]^lfsr[120]^lfsr[126];
assign o_lfsr[357] = lfsr[20]^lfsr[22]^lfsr[24]^lfsr[26]^lfsr[38]^lfsr[46]^lfsr[119]^lfsr[127];
assign o_lfsr[358] = lfsr[19]^lfsr[21]^lfsr[23]^lfsr[25]^lfsr[37]^lfsr[45]^lfsr[118]^lfsr[126];
assign o_lfsr[359] = lfsr[18]^lfsr[20]^lfsr[22]^lfsr[24]^lfsr[36]^lfsr[44]^lfsr[117]^lfsr[125];
assign o_lfsr[360] = lfsr[17]^lfsr[19]^lfsr[21]^lfsr[23]^lfsr[35]^lfsr[43]^lfsr[116]^lfsr[124];
assign o_lfsr[361] = lfsr[16]^lfsr[18]^lfsr[20]^lfsr[22]^lfsr[34]^lfsr[42]^lfsr[115]^lfsr[123];
assign o_lfsr[362] = lfsr[15]^lfsr[17]^lfsr[19]^lfsr[21]^lfsr[33]^lfsr[41]^lfsr[114]^lfsr[122];
assign o_lfsr[363] = lfsr[14]^lfsr[16]^lfsr[18]^lfsr[20]^lfsr[32]^lfsr[40]^lfsr[113]^lfsr[121];
assign o_lfsr[364] = lfsr[13]^lfsr[15]^lfsr[17]^lfsr[19]^lfsr[31]^lfsr[39]^lfsr[112]^lfsr[120];
assign o_lfsr[365] = lfsr[12]^lfsr[14]^lfsr[16]^lfsr[18]^lfsr[30]^lfsr[38]^lfsr[111]^lfsr[119];
assign o_lfsr[366] = lfsr[11]^lfsr[13]^lfsr[15]^lfsr[17]^lfsr[29]^lfsr[37]^lfsr[110]^lfsr[118];
assign o_lfsr[367] = lfsr[10]^lfsr[12]^lfsr[14]^lfsr[16]^lfsr[28]^lfsr[36]^lfsr[109]^lfsr[117];
assign o_lfsr[368] = lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[15]^lfsr[27]^lfsr[35]^lfsr[108]^lfsr[116];
assign o_lfsr[369] = lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[14]^lfsr[26]^lfsr[34]^lfsr[107]^lfsr[115];
assign o_lfsr[370] = lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[13]^lfsr[25]^lfsr[33]^lfsr[106]^lfsr[114];
assign o_lfsr[371] = lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[12]^lfsr[24]^lfsr[32]^lfsr[105]^lfsr[113];
assign o_lfsr[372] = lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[11]^lfsr[23]^lfsr[31]^lfsr[104]^lfsr[112];
assign o_lfsr[373] = lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[10]^lfsr[22]^lfsr[30]^lfsr[103]^lfsr[111];
assign o_lfsr[374] = lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[ 9]^lfsr[21]^lfsr[29]^lfsr[102]^lfsr[110];
assign o_lfsr[375] = lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[ 8]^lfsr[20]^lfsr[28]^lfsr[101]^lfsr[109];
assign o_lfsr[376] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[ 7]^lfsr[19]^lfsr[27]^lfsr[100]^lfsr[108];
assign o_lfsr[377] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[ 6]^lfsr[18]^lfsr[26]^lfsr[99]^lfsr[107];
assign o_lfsr[378] = lfsr[ 1]^lfsr[ 3]^lfsr[ 5]^lfsr[17]^lfsr[25]^lfsr[100]^lfsr[106]^lfsr[125]^lfsr[127];
assign o_lfsr[379] = lfsr[ 0]^lfsr[ 2]^lfsr[ 4]^lfsr[16]^lfsr[24]^lfsr[99]^lfsr[105]^lfsr[124]^lfsr[126];
assign o_lfsr[380] = lfsr[ 1]^lfsr[ 3]^lfsr[15]^lfsr[23]^lfsr[100]^lfsr[104]^lfsr[123]^lfsr[127];
assign o_lfsr[381] = lfsr[ 0]^lfsr[ 2]^lfsr[14]^lfsr[22]^lfsr[99]^lfsr[103]^lfsr[122]^lfsr[126];
assign o_lfsr[382] = lfsr[ 1]^lfsr[13]^lfsr[21]^lfsr[100]^lfsr[102]^lfsr[121]^lfsr[127];
assign o_lfsr[383] = lfsr[ 0]^lfsr[12]^lfsr[20]^lfsr[99]^lfsr[101]^lfsr[120]^lfsr[126];
assign o_lfsr[384] = lfsr[11]^lfsr[19]^lfsr[119]^lfsr[127];
assign o_lfsr[385] = lfsr[10]^lfsr[18]^lfsr[118]^lfsr[126];
assign o_lfsr[386] = lfsr[ 9]^lfsr[17]^lfsr[117]^lfsr[125];
assign o_lfsr[387] = lfsr[ 8]^lfsr[16]^lfsr[116]^lfsr[124];
assign o_lfsr[388] = lfsr[ 7]^lfsr[15]^lfsr[115]^lfsr[123];
assign o_lfsr[389] = lfsr[ 6]^lfsr[14]^lfsr[114]^lfsr[122];
assign o_lfsr[390] = lfsr[ 5]^lfsr[13]^lfsr[113]^lfsr[121];
assign o_lfsr[391] = lfsr[ 4]^lfsr[12]^lfsr[112]^lfsr[120];
assign o_lfsr[392] = lfsr[ 3]^lfsr[11]^lfsr[111]^lfsr[119];
assign o_lfsr[393] = lfsr[ 2]^lfsr[10]^lfsr[110]^lfsr[118];
assign o_lfsr[394] = lfsr[ 1]^lfsr[ 9]^lfsr[109]^lfsr[117];
assign o_lfsr[395] = lfsr[ 0]^lfsr[ 8]^lfsr[108]^lfsr[116];
assign o_lfsr[396] = lfsr[ 7]^lfsr[98]^lfsr[100]^lfsr[107]^lfsr[115]^lfsr[125]^lfsr[127];
assign o_lfsr[397] = lfsr[ 6]^lfsr[97]^lfsr[99]^lfsr[106]^lfsr[114]^lfsr[124]^lfsr[126];
assign o_lfsr[398] = lfsr[ 5]^lfsr[96]^lfsr[98]^lfsr[105]^lfsr[113]^lfsr[123]^lfsr[125];
assign o_lfsr[399] = lfsr[ 4]^lfsr[95]^lfsr[97]^lfsr[104]^lfsr[112]^lfsr[122]^lfsr[124];
assign o_lfsr[400] = lfsr[ 3]^lfsr[94]^lfsr[96]^lfsr[103]^lfsr[111]^lfsr[121]^lfsr[123];
assign o_lfsr[401] = lfsr[ 2]^lfsr[93]^lfsr[95]^lfsr[102]^lfsr[110]^lfsr[120]^lfsr[122];
assign o_lfsr[402] = lfsr[ 1]^lfsr[92]^lfsr[94]^lfsr[101]^lfsr[109]^lfsr[119]^lfsr[121];
assign o_lfsr[403] = lfsr[ 0]^lfsr[91]^lfsr[93]^lfsr[100]^lfsr[108]^lfsr[118]^lfsr[120];
assign o_lfsr[404] = lfsr[90]^lfsr[92]^lfsr[98]^lfsr[99]^lfsr[100]^lfsr[107]^lfsr[117]^lfsr[119]^lfsr[125]^lfsr[127];
assign o_lfsr[405] = lfsr[89]^lfsr[91]^lfsr[97]^lfsr[98]^lfsr[99]^lfsr[106]^lfsr[116]^lfsr[118]^lfsr[124]^lfsr[126];
assign o_lfsr[406] = lfsr[88]^lfsr[90]^lfsr[96]^lfsr[97]^lfsr[98]^lfsr[105]^lfsr[115]^lfsr[117]^lfsr[123]^lfsr[125];
assign o_lfsr[407] = lfsr[87]^lfsr[89]^lfsr[95]^lfsr[96]^lfsr[97]^lfsr[104]^lfsr[114]^lfsr[116]^lfsr[122]^lfsr[124];
assign o_lfsr[408] = lfsr[86]^lfsr[88]^lfsr[94]^lfsr[95]^lfsr[96]^lfsr[103]^lfsr[113]^lfsr[115]^lfsr[121]^lfsr[123];
assign o_lfsr[409] = lfsr[85]^lfsr[87]^lfsr[93]^lfsr[94]^lfsr[95]^lfsr[102]^lfsr[112]^lfsr[114]^lfsr[120]^lfsr[122];
assign o_lfsr[410] = lfsr[84]^lfsr[86]^lfsr[92]^lfsr[93]^lfsr[94]^lfsr[101]^lfsr[111]^lfsr[113]^lfsr[119]^lfsr[121];
assign o_lfsr[411] = lfsr[83]^lfsr[85]^lfsr[91]^lfsr[92]^lfsr[93]^lfsr[100]^lfsr[110]^lfsr[112]^lfsr[118]^lfsr[120];
assign o_lfsr[412] = lfsr[82]^lfsr[84]^lfsr[90]^lfsr[91]^lfsr[92]^lfsr[99]^lfsr[109]^lfsr[111]^lfsr[117]^lfsr[119];
assign o_lfsr[413] = lfsr[81]^lfsr[83]^lfsr[89]^lfsr[90]^lfsr[91]^lfsr[98]^lfsr[108]^lfsr[110]^lfsr[116]^lfsr[118];
assign o_lfsr[414] = lfsr[80]^lfsr[82]^lfsr[88]^lfsr[89]^lfsr[90]^lfsr[97]^lfsr[107]^lfsr[109]^lfsr[115]^lfsr[117];
assign o_lfsr[415] = lfsr[79]^lfsr[81]^lfsr[87]^lfsr[88]^lfsr[89]^lfsr[96]^lfsr[106]^lfsr[108]^lfsr[114]^lfsr[116];
assign o_lfsr[416] = lfsr[78]^lfsr[80]^lfsr[86]^lfsr[87]^lfsr[88]^lfsr[95]^lfsr[105]^lfsr[107]^lfsr[113]^lfsr[115];
assign o_lfsr[417] = lfsr[77]^lfsr[79]^lfsr[85]^lfsr[86]^lfsr[87]^lfsr[94]^lfsr[104]^lfsr[106]^lfsr[112]^lfsr[114];
assign o_lfsr[418] = lfsr[76]^lfsr[78]^lfsr[84]^lfsr[85]^lfsr[86]^lfsr[93]^lfsr[103]^lfsr[105]^lfsr[111]^lfsr[113];
assign o_lfsr[419] = lfsr[75]^lfsr[77]^lfsr[83]^lfsr[84]^lfsr[85]^lfsr[92]^lfsr[102]^lfsr[104]^lfsr[110]^lfsr[112];
assign o_lfsr[420] = lfsr[74]^lfsr[76]^lfsr[82]^lfsr[83]^lfsr[84]^lfsr[91]^lfsr[101]^lfsr[103]^lfsr[109]^lfsr[111];
assign o_lfsr[421] = lfsr[73]^lfsr[75]^lfsr[81]^lfsr[82]^lfsr[83]^lfsr[90]^lfsr[100]^lfsr[102]^lfsr[108]^lfsr[110];
assign o_lfsr[422] = lfsr[72]^lfsr[74]^lfsr[80]^lfsr[81]^lfsr[82]^lfsr[89]^lfsr[99]^lfsr[101]^lfsr[107]^lfsr[109];
assign o_lfsr[423] = lfsr[71]^lfsr[73]^lfsr[79]^lfsr[80]^lfsr[81]^lfsr[88]^lfsr[98]^lfsr[100]^lfsr[106]^lfsr[108];
assign o_lfsr[424] = lfsr[70]^lfsr[72]^lfsr[78]^lfsr[79]^lfsr[80]^lfsr[87]^lfsr[97]^lfsr[99]^lfsr[105]^lfsr[107];
assign o_lfsr[425] = lfsr[69]^lfsr[71]^lfsr[77]^lfsr[78]^lfsr[79]^lfsr[86]^lfsr[96]^lfsr[98]^lfsr[104]^lfsr[106];
assign o_lfsr[426] = lfsr[68]^lfsr[70]^lfsr[76]^lfsr[77]^lfsr[78]^lfsr[85]^lfsr[95]^lfsr[97]^lfsr[103]^lfsr[105];
assign o_lfsr[427] = lfsr[67]^lfsr[69]^lfsr[75]^lfsr[76]^lfsr[77]^lfsr[84]^lfsr[94]^lfsr[96]^lfsr[102]^lfsr[104];
assign o_lfsr[428] = lfsr[66]^lfsr[68]^lfsr[74]^lfsr[75]^lfsr[76]^lfsr[83]^lfsr[93]^lfsr[95]^lfsr[101]^lfsr[103];
assign o_lfsr[429] = lfsr[65]^lfsr[67]^lfsr[73]^lfsr[74]^lfsr[75]^lfsr[82]^lfsr[92]^lfsr[94]^lfsr[100]^lfsr[102];
assign o_lfsr[430] = lfsr[64]^lfsr[66]^lfsr[72]^lfsr[73]^lfsr[74]^lfsr[81]^lfsr[91]^lfsr[93]^lfsr[99]^lfsr[101];
assign o_lfsr[431] = lfsr[63]^lfsr[65]^lfsr[71]^lfsr[72]^lfsr[73]^lfsr[80]^lfsr[90]^lfsr[92]^lfsr[98]^lfsr[100];
assign o_lfsr[432] = lfsr[62]^lfsr[64]^lfsr[70]^lfsr[71]^lfsr[72]^lfsr[79]^lfsr[89]^lfsr[91]^lfsr[97]^lfsr[99];
assign o_lfsr[433] = lfsr[61]^lfsr[63]^lfsr[69]^lfsr[70]^lfsr[71]^lfsr[78]^lfsr[88]^lfsr[90]^lfsr[96]^lfsr[98];
assign o_lfsr[434] = lfsr[60]^lfsr[62]^lfsr[68]^lfsr[69]^lfsr[70]^lfsr[77]^lfsr[87]^lfsr[89]^lfsr[95]^lfsr[97];
assign o_lfsr[435] = lfsr[59]^lfsr[61]^lfsr[67]^lfsr[68]^lfsr[69]^lfsr[76]^lfsr[86]^lfsr[88]^lfsr[94]^lfsr[96];
assign o_lfsr[436] = lfsr[58]^lfsr[60]^lfsr[66]^lfsr[67]^lfsr[68]^lfsr[75]^lfsr[85]^lfsr[87]^lfsr[93]^lfsr[95];
assign o_lfsr[437] = lfsr[57]^lfsr[59]^lfsr[65]^lfsr[66]^lfsr[67]^lfsr[74]^lfsr[84]^lfsr[86]^lfsr[92]^lfsr[94];
assign o_lfsr[438] = lfsr[56]^lfsr[58]^lfsr[64]^lfsr[65]^lfsr[66]^lfsr[73]^lfsr[83]^lfsr[85]^lfsr[91]^lfsr[93];
assign o_lfsr[439] = lfsr[55]^lfsr[57]^lfsr[63]^lfsr[64]^lfsr[65]^lfsr[72]^lfsr[82]^lfsr[84]^lfsr[90]^lfsr[92];
assign o_lfsr[440] = lfsr[54]^lfsr[56]^lfsr[62]^lfsr[63]^lfsr[64]^lfsr[71]^lfsr[81]^lfsr[83]^lfsr[89]^lfsr[91];
assign o_lfsr[441] = lfsr[53]^lfsr[55]^lfsr[61]^lfsr[62]^lfsr[63]^lfsr[70]^lfsr[80]^lfsr[82]^lfsr[88]^lfsr[90];
assign o_lfsr[442] = lfsr[52]^lfsr[54]^lfsr[60]^lfsr[61]^lfsr[62]^lfsr[69]^lfsr[79]^lfsr[81]^lfsr[87]^lfsr[89];
assign o_lfsr[443] = lfsr[51]^lfsr[53]^lfsr[59]^lfsr[60]^lfsr[61]^lfsr[68]^lfsr[78]^lfsr[80]^lfsr[86]^lfsr[88];
assign o_lfsr[444] = lfsr[50]^lfsr[52]^lfsr[58]^lfsr[59]^lfsr[60]^lfsr[67]^lfsr[77]^lfsr[79]^lfsr[85]^lfsr[87];
assign o_lfsr[445] = lfsr[49]^lfsr[51]^lfsr[57]^lfsr[58]^lfsr[59]^lfsr[66]^lfsr[76]^lfsr[78]^lfsr[84]^lfsr[86];
assign o_lfsr[446] = lfsr[48]^lfsr[50]^lfsr[56]^lfsr[57]^lfsr[58]^lfsr[65]^lfsr[75]^lfsr[77]^lfsr[83]^lfsr[85];
assign o_lfsr[447] = lfsr[47]^lfsr[49]^lfsr[55]^lfsr[56]^lfsr[57]^lfsr[64]^lfsr[74]^lfsr[76]^lfsr[82]^lfsr[84];
assign o_lfsr[448] = lfsr[46]^lfsr[48]^lfsr[54]^lfsr[55]^lfsr[56]^lfsr[63]^lfsr[73]^lfsr[75]^lfsr[81]^lfsr[83];
assign o_lfsr[449] = lfsr[45]^lfsr[47]^lfsr[53]^lfsr[54]^lfsr[55]^lfsr[62]^lfsr[72]^lfsr[74]^lfsr[80]^lfsr[82];
assign o_lfsr[450] = lfsr[44]^lfsr[46]^lfsr[52]^lfsr[53]^lfsr[54]^lfsr[61]^lfsr[71]^lfsr[73]^lfsr[79]^lfsr[81];
assign o_lfsr[451] = lfsr[43]^lfsr[45]^lfsr[51]^lfsr[52]^lfsr[53]^lfsr[60]^lfsr[70]^lfsr[72]^lfsr[78]^lfsr[80];
assign o_lfsr[452] = lfsr[42]^lfsr[44]^lfsr[50]^lfsr[51]^lfsr[52]^lfsr[59]^lfsr[69]^lfsr[71]^lfsr[77]^lfsr[79];
assign o_lfsr[453] = lfsr[41]^lfsr[43]^lfsr[49]^lfsr[50]^lfsr[51]^lfsr[58]^lfsr[68]^lfsr[70]^lfsr[76]^lfsr[78];
assign o_lfsr[454] = lfsr[40]^lfsr[42]^lfsr[48]^lfsr[49]^lfsr[50]^lfsr[57]^lfsr[67]^lfsr[69]^lfsr[75]^lfsr[77];
assign o_lfsr[455] = lfsr[39]^lfsr[41]^lfsr[47]^lfsr[48]^lfsr[49]^lfsr[56]^lfsr[66]^lfsr[68]^lfsr[74]^lfsr[76];
assign o_lfsr[456] = lfsr[38]^lfsr[40]^lfsr[46]^lfsr[47]^lfsr[48]^lfsr[55]^lfsr[65]^lfsr[67]^lfsr[73]^lfsr[75];
assign o_lfsr[457] = lfsr[37]^lfsr[39]^lfsr[45]^lfsr[46]^lfsr[47]^lfsr[54]^lfsr[64]^lfsr[66]^lfsr[72]^lfsr[74];
assign o_lfsr[458] = lfsr[36]^lfsr[38]^lfsr[44]^lfsr[45]^lfsr[46]^lfsr[53]^lfsr[63]^lfsr[65]^lfsr[71]^lfsr[73];
assign o_lfsr[459] = lfsr[35]^lfsr[37]^lfsr[43]^lfsr[44]^lfsr[45]^lfsr[52]^lfsr[62]^lfsr[64]^lfsr[70]^lfsr[72];
assign o_lfsr[460] = lfsr[34]^lfsr[36]^lfsr[42]^lfsr[43]^lfsr[44]^lfsr[51]^lfsr[61]^lfsr[63]^lfsr[69]^lfsr[71];
assign o_lfsr[461] = lfsr[33]^lfsr[35]^lfsr[41]^lfsr[42]^lfsr[43]^lfsr[50]^lfsr[60]^lfsr[62]^lfsr[68]^lfsr[70];
assign o_lfsr[462] = lfsr[32]^lfsr[34]^lfsr[40]^lfsr[41]^lfsr[42]^lfsr[49]^lfsr[59]^lfsr[61]^lfsr[67]^lfsr[69];
assign o_lfsr[463] = lfsr[31]^lfsr[33]^lfsr[39]^lfsr[40]^lfsr[41]^lfsr[48]^lfsr[58]^lfsr[60]^lfsr[66]^lfsr[68];
assign o_lfsr[464] = lfsr[30]^lfsr[32]^lfsr[38]^lfsr[39]^lfsr[40]^lfsr[47]^lfsr[57]^lfsr[59]^lfsr[65]^lfsr[67];
assign o_lfsr[465] = lfsr[29]^lfsr[31]^lfsr[37]^lfsr[38]^lfsr[39]^lfsr[46]^lfsr[56]^lfsr[58]^lfsr[64]^lfsr[66];
assign o_lfsr[466] = lfsr[28]^lfsr[30]^lfsr[36]^lfsr[37]^lfsr[38]^lfsr[45]^lfsr[55]^lfsr[57]^lfsr[63]^lfsr[65];
assign o_lfsr[467] = lfsr[27]^lfsr[29]^lfsr[35]^lfsr[36]^lfsr[37]^lfsr[44]^lfsr[54]^lfsr[56]^lfsr[62]^lfsr[64];
assign o_lfsr[468] = lfsr[26]^lfsr[28]^lfsr[34]^lfsr[35]^lfsr[36]^lfsr[43]^lfsr[53]^lfsr[55]^lfsr[61]^lfsr[63];
assign o_lfsr[469] = lfsr[25]^lfsr[27]^lfsr[33]^lfsr[34]^lfsr[35]^lfsr[42]^lfsr[52]^lfsr[54]^lfsr[60]^lfsr[62];
assign o_lfsr[470] = lfsr[24]^lfsr[26]^lfsr[32]^lfsr[33]^lfsr[34]^lfsr[41]^lfsr[51]^lfsr[53]^lfsr[59]^lfsr[61];
assign o_lfsr[471] = lfsr[23]^lfsr[25]^lfsr[31]^lfsr[32]^lfsr[33]^lfsr[40]^lfsr[50]^lfsr[52]^lfsr[58]^lfsr[60];
assign o_lfsr[472] = lfsr[22]^lfsr[24]^lfsr[30]^lfsr[31]^lfsr[32]^lfsr[39]^lfsr[49]^lfsr[51]^lfsr[57]^lfsr[59];
assign o_lfsr[473] = lfsr[21]^lfsr[23]^lfsr[29]^lfsr[30]^lfsr[31]^lfsr[38]^lfsr[48]^lfsr[50]^lfsr[56]^lfsr[58];
assign o_lfsr[474] = lfsr[20]^lfsr[22]^lfsr[28]^lfsr[29]^lfsr[30]^lfsr[37]^lfsr[47]^lfsr[49]^lfsr[55]^lfsr[57];
assign o_lfsr[475] = lfsr[19]^lfsr[21]^lfsr[27]^lfsr[28]^lfsr[29]^lfsr[36]^lfsr[46]^lfsr[48]^lfsr[54]^lfsr[56];
assign o_lfsr[476] = lfsr[18]^lfsr[20]^lfsr[26]^lfsr[27]^lfsr[28]^lfsr[35]^lfsr[45]^lfsr[47]^lfsr[53]^lfsr[55];
assign o_lfsr[477] = lfsr[17]^lfsr[19]^lfsr[25]^lfsr[26]^lfsr[27]^lfsr[34]^lfsr[44]^lfsr[46]^lfsr[52]^lfsr[54];
assign o_lfsr[478] = lfsr[16]^lfsr[18]^lfsr[24]^lfsr[25]^lfsr[26]^lfsr[33]^lfsr[43]^lfsr[45]^lfsr[51]^lfsr[53];
assign o_lfsr[479] = lfsr[15]^lfsr[17]^lfsr[23]^lfsr[24]^lfsr[25]^lfsr[32]^lfsr[42]^lfsr[44]^lfsr[50]^lfsr[52];
assign o_lfsr[480] = lfsr[14]^lfsr[16]^lfsr[22]^lfsr[23]^lfsr[24]^lfsr[31]^lfsr[41]^lfsr[43]^lfsr[49]^lfsr[51];
assign o_lfsr[481] = lfsr[13]^lfsr[15]^lfsr[21]^lfsr[22]^lfsr[23]^lfsr[30]^lfsr[40]^lfsr[42]^lfsr[48]^lfsr[50];
assign o_lfsr[482] = lfsr[12]^lfsr[14]^lfsr[20]^lfsr[21]^lfsr[22]^lfsr[29]^lfsr[39]^lfsr[41]^lfsr[47]^lfsr[49];
assign o_lfsr[483] = lfsr[11]^lfsr[13]^lfsr[19]^lfsr[20]^lfsr[21]^lfsr[28]^lfsr[38]^lfsr[40]^lfsr[46]^lfsr[48];
assign o_lfsr[484] = lfsr[10]^lfsr[12]^lfsr[18]^lfsr[19]^lfsr[20]^lfsr[27]^lfsr[37]^lfsr[39]^lfsr[45]^lfsr[47];
assign o_lfsr[485] = lfsr[ 9]^lfsr[11]^lfsr[17]^lfsr[18]^lfsr[19]^lfsr[26]^lfsr[36]^lfsr[38]^lfsr[44]^lfsr[46];
assign o_lfsr[486] = lfsr[ 8]^lfsr[10]^lfsr[16]^lfsr[17]^lfsr[18]^lfsr[25]^lfsr[35]^lfsr[37]^lfsr[43]^lfsr[45];
assign o_lfsr[487] = lfsr[ 7]^lfsr[ 9]^lfsr[15]^lfsr[16]^lfsr[17]^lfsr[24]^lfsr[34]^lfsr[36]^lfsr[42]^lfsr[44];
assign o_lfsr[488] = lfsr[ 6]^lfsr[ 8]^lfsr[14]^lfsr[15]^lfsr[16]^lfsr[23]^lfsr[33]^lfsr[35]^lfsr[41]^lfsr[43];
assign o_lfsr[489] = lfsr[ 5]^lfsr[ 7]^lfsr[13]^lfsr[14]^lfsr[15]^lfsr[22]^lfsr[32]^lfsr[34]^lfsr[40]^lfsr[42];
assign o_lfsr[490] = lfsr[ 4]^lfsr[ 6]^lfsr[12]^lfsr[13]^lfsr[14]^lfsr[21]^lfsr[31]^lfsr[33]^lfsr[39]^lfsr[41];
assign o_lfsr[491] = lfsr[ 3]^lfsr[ 5]^lfsr[11]^lfsr[12]^lfsr[13]^lfsr[20]^lfsr[30]^lfsr[32]^lfsr[38]^lfsr[40];
assign o_lfsr[492] = lfsr[ 2]^lfsr[ 4]^lfsr[10]^lfsr[11]^lfsr[12]^lfsr[19]^lfsr[29]^lfsr[31]^lfsr[37]^lfsr[39];
assign o_lfsr[493] = lfsr[ 1]^lfsr[ 3]^lfsr[ 9]^lfsr[10]^lfsr[11]^lfsr[18]^lfsr[28]^lfsr[30]^lfsr[36]^lfsr[38];
assign o_lfsr[494] = lfsr[ 0]^lfsr[ 2]^lfsr[ 8]^lfsr[ 9]^lfsr[10]^lfsr[17]^lfsr[27]^lfsr[29]^lfsr[35]^lfsr[37];
assign o_lfsr[495] = lfsr[ 1]^lfsr[ 7]^lfsr[ 8]^lfsr[ 9]^lfsr[16]^lfsr[26]^lfsr[28]^lfsr[34]^lfsr[36]^lfsr[98]^lfsr[100]^lfsr[125]^lfsr[127];
assign o_lfsr[496] = lfsr[ 0]^lfsr[ 6]^lfsr[ 7]^lfsr[ 8]^lfsr[15]^lfsr[25]^lfsr[27]^lfsr[33]^lfsr[35]^lfsr[97]^lfsr[99]^lfsr[124]^lfsr[126];
assign o_lfsr[497] = lfsr[ 5]^lfsr[ 6]^lfsr[ 7]^lfsr[14]^lfsr[24]^lfsr[26]^lfsr[32]^lfsr[34]^lfsr[96]^lfsr[100]^lfsr[123]^lfsr[127];
assign o_lfsr[498] = lfsr[ 4]^lfsr[ 5]^lfsr[ 6]^lfsr[13]^lfsr[23]^lfsr[25]^lfsr[31]^lfsr[33]^lfsr[95]^lfsr[99]^lfsr[122]^lfsr[126];
assign o_lfsr[499] = lfsr[ 3]^lfsr[ 4]^lfsr[ 5]^lfsr[12]^lfsr[22]^lfsr[24]^lfsr[30]^lfsr[32]^lfsr[94]^lfsr[98]^lfsr[121]^lfsr[125];
assign o_lfsr[500] = lfsr[ 2]^lfsr[ 3]^lfsr[ 4]^lfsr[11]^lfsr[21]^lfsr[23]^lfsr[29]^lfsr[31]^lfsr[93]^lfsr[97]^lfsr[120]^lfsr[124];
assign o_lfsr[501] = lfsr[ 1]^lfsr[ 2]^lfsr[ 3]^lfsr[10]^lfsr[20]^lfsr[22]^lfsr[28]^lfsr[30]^lfsr[92]^lfsr[96]^lfsr[119]^lfsr[123];
assign o_lfsr[502] = lfsr[ 0]^lfsr[ 1]^lfsr[ 2]^lfsr[ 9]^lfsr[19]^lfsr[21]^lfsr[27]^lfsr[29]^lfsr[91]^lfsr[95]^lfsr[118]^lfsr[122];
assign o_lfsr[503] = lfsr[ 0]^lfsr[ 1]^lfsr[ 8]^lfsr[18]^lfsr[20]^lfsr[26]^lfsr[28]^lfsr[90]^lfsr[94]^lfsr[98]^lfsr[100]^lfsr[117]^lfsr[121]^lfsr[125]^lfsr[127];
assign o_lfsr[504] = lfsr[ 0]^lfsr[ 7]^lfsr[17]^lfsr[19]^lfsr[25]^lfsr[27]^lfsr[89]^lfsr[93]^lfsr[97]^lfsr[98]^lfsr[99]^lfsr[100]^lfsr[116]^lfsr[120]^lfsr[124]^lfsr[125]^lfsr[126]^lfsr[127];
assign o_lfsr[505] = lfsr[ 6]^lfsr[16]^lfsr[18]^lfsr[24]^lfsr[26]^lfsr[88]^lfsr[92]^lfsr[96]^lfsr[97]^lfsr[99]^lfsr[100]^lfsr[115]^lfsr[119]^lfsr[123]^lfsr[124]^lfsr[126]^lfsr[127];
assign o_lfsr[506] = lfsr[ 5]^lfsr[15]^lfsr[17]^lfsr[23]^lfsr[25]^lfsr[87]^lfsr[91]^lfsr[95]^lfsr[96]^lfsr[98]^lfsr[99]^lfsr[114]^lfsr[118]^lfsr[122]^lfsr[123]^lfsr[125]^lfsr[126];
assign o_lfsr[507] = lfsr[ 4]^lfsr[14]^lfsr[16]^lfsr[22]^lfsr[24]^lfsr[86]^lfsr[90]^lfsr[94]^lfsr[95]^lfsr[97]^lfsr[98]^lfsr[113]^lfsr[117]^lfsr[121]^lfsr[122]^lfsr[124]^lfsr[125];
assign o_lfsr[508] = lfsr[ 3]^lfsr[13]^lfsr[15]^lfsr[21]^lfsr[23]^lfsr[85]^lfsr[89]^lfsr[93]^lfsr[94]^lfsr[96]^lfsr[97]^lfsr[112]^lfsr[116]^lfsr[120]^lfsr[121]^lfsr[123]^lfsr[124];
assign o_lfsr[509] = lfsr[ 2]^lfsr[12]^lfsr[14]^lfsr[20]^lfsr[22]^lfsr[84]^lfsr[88]^lfsr[92]^lfsr[93]^lfsr[95]^lfsr[96]^lfsr[111]^lfsr[115]^lfsr[119]^lfsr[120]^lfsr[122]^lfsr[123];
assign o_lfsr[510] = lfsr[ 1]^lfsr[11]^lfsr[13]^lfsr[19]^lfsr[21]^lfsr[83]^lfsr[87]^lfsr[91]^lfsr[92]^lfsr[94]^lfsr[95]^lfsr[110]^lfsr[114]^lfsr[118]^lfsr[119]^lfsr[121]^lfsr[122];
assign o_lfsr[511] = lfsr[ 0]^lfsr[10]^lfsr[12]^lfsr[18]^lfsr[20]^lfsr[82]^lfsr[86]^lfsr[90]^lfsr[91]^lfsr[93]^lfsr[94]^lfsr[109]^lfsr[113]^lfsr[117]^lfsr[118]^lfsr[120]^lfsr[121];
// To advance the state by N=512 clocks:
localparam N=512;
always @(posedge(clk)) begin : lfsr_clock
if (reset == 1'b1) begin
lfsr <= {(512){1'b1}};
end else begin
if (i_init==1'b1) begin
lfsr <= i_seed;
end else begin
if (i_advance==1'b1) begin
for (i=0; i<128; i=i+1) begin
lfsr[i] <= (N-1>=i) ? o_lfsr[N-1-i]:lfsr[i-N];
end
end
end
end
end // always
endmodule // lfsr
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_PP_V
|
`include "macro.v"
module mem(
input wire reset,
input wire input_write_enable,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire[`REGS_DATA_BUS] input_write_data,
input wire input_write_hilo_enable,
input wire[`REGS_DATA_BUS] input_write_hi_data,
input wire[`REGS_DATA_BUS] input_write_lo_data,
input wire[`ALU_OPERATOR_BUS] input_alu_operator,
input wire[`REGS_DATA_BUS] input_alu_operand2,
input wire[`REGS_DATA_BUS] input_ram_addr,
input wire[`REGS_DATA_BUS] input_ram_read_data,
output reg write_enable,
output reg[`REGS_ADDR_BUS] write_addr,
output reg[`REGS_DATA_BUS] write_data,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_DATA_BUS] ram_addr,
output wire ram_operation, // 0 is read, 1 is write
output reg[`BYTE_SEL_BUS] ram_select_signal,
output reg[`REGS_DATA_BUS] ram_write_data,
output reg ram_chip_enable
);
wire[`REGS_DATA_BUS] zero32;
reg ram_operation_register;
assign ram_operation = ram_operation_register;
assign zero32 = 0; // FIXME: `ZEROWORD should be used here, but 0 is used
always @ (*) begin
if (reset == `ENABLE) begin
write_enable <= `DISABLE;
write_addr <= 0; // FIXME: 0 is used here, but NOPRegAddr is expected
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
write_hilo_enable <= `DISABLE;
write_hi_data <= 0; // FIXME: 0 is used here, but NOPRegAddr is expected
write_lo_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
ram_addr <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
ram_operation_register <= `DISABLE;
ram_select_signal <= 0; // FIXME: 0 is used here, but 4'b0000 is expected
ram_write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
ram_chip_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
write_addr <= input_write_addr;
write_data <= input_write_data;
write_hilo_enable <= input_write_hilo_enable;
write_hi_data <= input_write_hi_data;
write_lo_data <= input_write_lo_data;
ram_operation_register <= `DISABLE;
ram_addr <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
ram_select_signal <= 4'b1111;
ram_chip_enable <= `DISABLE;
case (input_alu_operator)
`OPERATOR_LB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{input_ram_read_data[31]}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{input_ram_read_data[23]}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{input_ram_read_data[15]}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{input_ram_read_data[7]}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_LBU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{24{1'b0}}, input_ram_read_data[31 : 24]};
ram_select_signal <= 4'b1000;
end
2'b01: begin
write_data <= {{24{1'b0}}, input_ram_read_data[23 : 16]};
ram_select_signal <= 4'b0100;
end
2'b10: begin
write_data <= {{24{1'b0}}, input_ram_read_data[15 : 8]};
ram_select_signal <= 4'b0010;
end
2'b11: begin
write_data <= {{24{1'b0}}, input_ram_read_data[7 : 0]};
ram_select_signal <= 4'b0001;
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_LH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{input_ram_read_data[31]}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{input_ram_read_data[15]}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_LHU: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {{16{1'b0}}, input_ram_read_data[31 : 16]};
ram_select_signal <= 4'b1100;
end
2'b10: begin
write_data <= {{16{1'b0}}, input_ram_read_data[15 : 0]};
ram_select_signal <= 4'b0011;
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_LW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
write_data <= input_ram_read_data;
end
`OPERATOR_LWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= input_ram_read_data[31 : 0];
end
2'b01: begin
write_data <= {input_ram_read_data[23 : 0], input_alu_operand2[7 : 0]};
end
2'b10: begin
write_data <= {input_ram_read_data[15 : 0], input_alu_operand2[15 : 0]};
end
2'b11: begin
write_data <= {input_ram_read_data[7 : 0], input_alu_operand2[23 : 0]};
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_LWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_READ;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
write_data <= {input_alu_operand2[31 : 8], input_ram_read_data[31 : 24]};
end
2'b01: begin
write_data <= {input_alu_operand2[31 : 16], input_ram_read_data[31 : 16]};
end
2'b10: begin
write_data <= {input_alu_operand2[31 : 24], input_ram_read_data[31 : 8]};
end
2'b11: begin
write_data <= input_ram_read_data;
end
default: begin
write_data <= 0; // FIXME: 0 is used here, but ZERO_WORD is expected
end
endcase
end
`OPERATOR_SB: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[7 : 0], input_alu_operand2[7 : 0],
input_alu_operand2[7 : 0], input_alu_operand2[7 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
end
2'b01: begin
ram_select_signal <= 4'b0100;
end
2'b10: begin
ram_select_signal <= 4'b0010;
end
2'b11: begin
ram_select_signal <= 4'b0001;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SH: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= {input_alu_operand2[15 : 0], input_alu_operand2[15 : 0]};
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1100;
end
2'b10: begin
ram_select_signal <= 4'b0011;
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SW: begin
ram_addr <= input_ram_addr;
ram_operation_register <= `RAM_WRITE;
ram_write_data <= input_alu_operand2;
ram_select_signal <= 4'b1111;
ram_chip_enable <= `ENABLE;
end
`OPERATOR_SWL: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2;
end
2'b01: begin
ram_select_signal <= 4'b0111;
ram_write_data <= {zero32[7 : 0], input_alu_operand2[31 : 8]};
end
2'b10: begin
ram_select_signal <= 4'b0011;
ram_write_data <= {zero32[15 : 0], input_alu_operand2[31 : 16]};
end
2'b11: begin
ram_select_signal <= 4'b0001;
ram_write_data <= {zero32[23 : 0], input_alu_operand2[31 : 24]};
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
`OPERATOR_SWR: begin
ram_addr <= {input_ram_addr[31 : 2], 2'b00};
ram_operation_register <= `RAM_WRITE;
ram_chip_enable <= `ENABLE;
case (input_ram_addr[1 : 0])
2'b00: begin
ram_select_signal <= 4'b1000;
ram_write_data <= {input_alu_operand2[7 : 0], zero32[23 : 0]};
end
2'b01: begin
ram_select_signal <= 4'b1100;
ram_write_data <= {input_alu_operand2[15 : 0], zero32[15 : 0]};
end
2'b10: begin
ram_select_signal <= 4'b1110;
ram_write_data <= {input_alu_operand2[23 : 0], zero32[7 : 0]};
end
2'b11: begin
ram_select_signal <= 4'b1111;
ram_write_data <= input_alu_operand2[31 : 0];
end
default: begin
ram_select_signal <= 4'b0000;
end
endcase
end
endcase
end
end
endmodule // mem
|
module TestPhaseDelayMain();
/***
This module tests the main module of the phase delay board. It provides a test input signal, and programs the module with several different phase delays, then looks at the output to verify functionality.
Ted Golfinopoulos, 12 Aug 2012
***/
parameter F_CLK=20E6;
parameter F_SIG=100E3;
parameter NUM_SIZE=7;
parameter SEQ_SIZE=NUM_SIZE+4;
reg [SEQ_SIZE-1:0] seq1,seq2,seq3,seq4;
reg clk;
reg [10:0] clkDiv;
reg decoderInput;
reg f1;
wire sigOut;
integer i;
PhaseDelayMain myMain(clk, decoderInput, f1, sigOut);
initial begin
$dumpfile ("TestPhaseDelayMainTestbench.vcd");
$dumpvars;
end
initial begin
$display("\tTime\tProgNum\tsigOut");
$monitor("\t%d\t%b\t%b",$time, f1, sigOut);
end
initial begin
#0
clk=1'b1;
clkDiv=0;
f1=1'b0;
seq1=0; //In phase
seq2=128/4; //90 degrees out of phase
seq3=128/2; //180 degrees out of phase
seq4=3*128/4; //270 degrees out of phase
// seq1=11'b01000000000; //In phase
// seq2=11'b01001000000; //90 degrees out of phase
// seq3=11'b01010000000; //180 degrees out of phase
// seq4=11'b01011000000; //270 degrees out of phase
$display("First sequence");
for(i=0; i<SEQ_SIZE; i=i+1) begin
#1024
decoderInput=seq1[SEQ_SIZE-1-i];
// $display("%d\t%b",i,decoderInput);
end
$display("Second sequence");
for(i=0; i<SEQ_SIZE; i=i+1) begin
#1055
decoderInput=seq2[SEQ_SIZE-1-i];
// $display("%d\t%b",i,decoderInput);
end
$display("Third sequence");
for(i=0; i<SEQ_SIZE; i=i+1) begin
#1055
decoderInput=seq3[SEQ_SIZE-1-i];
// $display("%d\t%b",i,decoderInput);
end
$display("Fourth sequence");
for(i=0; i<SEQ_SIZE; i=i+1) begin
#1055
decoderInput=seq4[SEQ_SIZE-1-i];
// $display("%d\t%b",i,decoderInput);
end
#50 $finish; //Stop simulation.
end
//Synthesize signals at different frequencies
always @(posedge clk) begin
clkDiv=clkDiv+1;
//Assume clkFreq=20E6; then 1/200 is 100 kHz
if(clkDiv%(F_CLK/(2*F_SIG))==0) f1=~f1; //100 kHz, since period of signal is two inversions.
end
//Make clock
always begin
#1
clk=~clk; //Invert clock
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2015 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Application : Vivado HLS
// / / Filename: filt_coef_rom.h
// /___/ /\ Timestamp: Tue May 12 5:00:00 PST 2015
// \ \ / \
// \___\/\___\
//
//Command: N/A
//Device: 7K325T-2
//Design Name: multiSRC
//Purpose:
// This file is the top-level design for multiSRC onboard test.
//Reference:
// XAPP1236
///////////////////////////////////////////////////////////////////////////////
module multiSRC_onboard(
input SYSCLK_N,
input SYSCLK_P,
input GPIO_SW_RIGHT,
input GPIO_SW_CENTER,
output GPIO_LED_CENTER,
output GPIO_LED_LEFT,
output GPIO_LED_RIGHT
);
wire test_start;
wire test_done;
wire test_pass;
wire clk;
wire rst;
//----------------
// for testing
//----------------
reg [26:0] cnt;
always @(posedge clk, posedge rst) begin
// main counter
if(rst) begin
cnt <= 0;
end else begin
cnt <= cnt+1;
end
end
//--------------------------
wire ap_start;
wire ap_ready;
wire ap_idle;
wire ap_done;
wire dut_rst;
wire vld_x;
wire vld_y;
wire [15:0] x;
wire [2:0] rat;
wire [47:0] y;
wire locked;
assign rst=GPIO_SW_CENTER;
assign test_start=GPIO_SW_RIGHT;
assign GPIO_LED_CENTER=test_pass;
assign GPIO_LED_RIGHT=cnt[26];
assign GPIO_LED_LEFT=locked;
clk_wiz_0 CLKPLL
(
// Clock in ports
.clk_in1_p(SYSCLK_P),
.clk_in1_n(SYSCLK_N),
// Clock out ports
.clk_out1(clk),
// Status and control signals
.reset(rst),
.locked(locked)
);
test_bench_onboard TB
(
.clk(clk),
.rst(rst),
.test_start(test_start),
.test_done(test_done),
.test_pass(test_pass),
.ap_ready(ap_ready),
.ap_idle(ap_idle),
.ap_done(ap_done),
.dut_vld_y(vld_y),
.dut_y(y),
.dut_rst(dut_rst),
.dut_start(ap_start),
.dut_vld_x(vld_x),
.dut_x(x),
.dut_rat(rat)
);
multiSRC DUT(
.ap_clk(clk),
.ap_rst(dut_rst),
.ap_start(ap_start),
.ap_done(ap_done),
.ap_idle(ap_idle),
.ap_ready(ap_ready),
.vld_i(vld_x),
.x_i_V(x),
.rat_i_V(rat),
.vld_o(vld_y),
.y_o_V(y)
);
endmodule
|
/*******************************************************************************
* Module: dly01_16
* Date:2014-05-30
* Author: Andrey Filippov
* Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitive)
*
* Copyright (c) 2014 Elphel, Inc.
* dly01_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dly01_16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module dly01_16(
input clk,
input rst,
input [3:0] dly,
input din,
output dout
);
reg [15:0] sr=0;
`ifdef SHREG_SEQUENTIAL_RESET
always @ (posedge clk) begin
sr <= {sr[14:0], din & ~rst};
end
`else
// always @ (posedge rst or posedge clk) begin
always @ (posedge clk) begin
if (rst) sr <=0;
else sr <= {sr[14:0],din};
end
`endif
`ifdef SIMULATION
assign dout = (|sr) ? ((&sr) ? 1'b1 : sr[dly]) : 1'b0 ;
`else
assign dout =sr[dly];
`endif
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Address Input
// File : de3d_tc_addr_in.v
// Author : Frank Bruno
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module handles clamping situations, as well as texture
// mirroring. It takes the UL texel address in, and generates
// the addresses for the 4 texels to the tag. It also generates
// the clip signal to overide the texels out.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
// U_HBI hbi_top Host interface (PCI)
// U_VGA vga_top IBM(TM) Compatible VGA core
// U_DE de_top Drawing engine
// U_DLP dlp_top Display List Processor
// U_DDR3 DDR3 DDR3 Memory interface
// u_crt crt_top Display interface
// u_ramdac ramdac Digital DAC
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_addr_in
(
input de_clk, // DE clock.
input [2:0] bpt_d, // bits per texel.
input [4:0] tfmt_d, // bits per texel.
input pal_mode_d, // Palette mode
input push_uv, // Push uv.
input [10:0] ul_u, /* Upper left texel X */
input [10:0] ul_v, /* Upper left texel Y */
input clamp_x, /* Clamp in X */
input clamp_y, /* Clamp in Y */
input [8:0] bitmask_x, /* X valid bitmask */
input [8:0] bitmask_y, /* Y valid bitmask */
input current_clip, // CLipping.
input [3:0] current_mipmap, // Current MIPMAP #
input current_exact, // Exact.
output reg push_uv_dd, // Push uv delayed.
output reg [2:0] bpt_dd, // bits per texel.
output reg [4:0] tfmt_dd, // bits per texel.
output reg pal_mode_dd, // Palette mode
output [8:0] ul_x, /* Addresses to the tag */
output [8:0] ul_y, /* Addresses to the tag */
output [8:0] ur_x, /* Addresses to the tag */
output [8:0] ur_y, /* Addresses to the tag */
output [8:0] ll_x, /* Addresses to the tag */
output [8:0] ll_y, /* Addresses to the tag */
output [8:0] lr_x, /* Addresses to the tag */
output [8:0] lr_y, /* Addresses to the tag */
output clamp_ul, /* clamping override */
output clamp_ur, /* clamping override */
output clamp_ll, /* clamping override */
output clamp_lr, /* clamping override */
output reg current_clip_dd, // CLipping.
output reg [3:0] current_mipmap_dd, // Current MIPMAP #
output reg current_exact_dd, // Exact.
output reg [4:0] ee_tag_adr_rd,
output reg [4:0] eo_tag_adr_rd,
output reg [4:0] oe_tag_adr_rd,
output reg [4:0] oo_tag_adr_rd
);
// Registers
reg [10:0] ulx_int; /* ul_x going out */
reg [10:0] uly_int; /* ul_y going out */
reg [6:0] ul_tag_adr_bpt;
reg [6:0] ll_tag_adr_bpt;
reg [6:0] ur_tag_adr_bpt;
reg [6:0] lr_tag_adr_bpt;
reg push_uv_d;
reg current_clip_d;
reg [3:0] current_mipmap_d;
reg current_exact_d;
wire [10:0] clamp_mask_x; /* mask for determining clamp in X */
wire [10:0] clamp_mask_y; /* mask for determining clamp in Y */
wire outside_x; /* Outside of 0 - 1 in X */
wire outside_y; /* Outside of 0 - 1 in Y */
wire right_edge; /* Right on final column, treat outside */
wire bottom_edge; /* Right on last row, treat outside */
wire [10:0] ulx_inc; /* incremented UL X coordinate */
wire [10:0] uly_inc; /* incremented UL Y coordinate */
wire [8:0] ul_x_d;
wire [8:0] ul_y_d;
wire [8:0] ur_x_d;
wire [8:0] ur_y_d;
wire [8:0] ll_x_d;
wire [8:0] ll_y_d;
wire [8:0] lr_x_d;
wire [8:0] lr_y_d;
// Generate the mask to only show bits outside of range, note
// that bit 10 is the sign bit, and bit 9 is the overflow, they
// are never masked
assign clamp_mask_x[10:9] = (clamp_x) ? 2'b11 : 2'b00;
assign clamp_mask_x[8:0] = (clamp_x) ? ~bitmask_x : 9'h0;
assign clamp_mask_y[10:9] = (clamp_y) ? 2'b11 : 2'b00;
assign clamp_mask_y[8:0] = (clamp_y) ? ~bitmask_y : 9'h0;
/* non-mirroring */
/* Compute addresses */
// If it is biggest positive #, and clamping, must clamp value to make
// up for missed precision bits in renderer
assign ulx_inc = (clamp_x & (&ul_u[9:0] & ~ul_u[10])) ? ul_u : ul_u + 11'h1;
assign uly_inc = (clamp_y & (&ul_v[9:0] & ~ul_v[10])) ? ul_v : ul_v + 11'h1;
de3d_tc_clamp u0_de3d_tc_clamp_ul
(
.de_clk (de_clk),
.clamp_x (clamp_x),
.clamp_y (clamp_y),
.x (ul_u),
.y (ul_v),
.clamp_mask_x (clamp_mask_x),
.clamp_mask_y (clamp_mask_y),
.bitmask_x (bitmask_x),
.bitmask_y (bitmask_y),
// Outputs.
.clamp (clamp_ul),
.new_x (ul_x),
.new_y (ul_y),
.new_x_d (ul_x_d),
.new_y_d (ul_y_d)
);
de3d_tc_clamp u1_de3d_tc_clamp_ur
(
.de_clk (de_clk),
.clamp_x (clamp_x),
.clamp_y (clamp_y),
.x (ulx_inc),
.y (ul_v),
.clamp_mask_x (clamp_mask_x),
.clamp_mask_y (clamp_mask_y),
.bitmask_x (bitmask_x),
.bitmask_y (bitmask_y),
// Outputs.
.clamp (clamp_ur),
.new_x (ur_x),
.new_y (ur_y),
.new_x_d (ur_x_d),
.new_y_d (ur_y_d)
);
de3d_tc_clamp u2_de3d_tc_clamp_ll
(
.de_clk (de_clk),
.clamp_x (clamp_x),
.clamp_y (clamp_y),
.x (ul_u),
.y (uly_inc),
.clamp_mask_x (clamp_mask_x),
.clamp_mask_y (clamp_mask_y),
.bitmask_x (bitmask_x),
.bitmask_y (bitmask_y),
// Outputs.
.clamp (clamp_ll),
.new_x (ll_x),
.new_y (ll_y),
.new_x_d (ll_x_d),
.new_y_d (ll_y_d)
);
de3d_tc_clamp u3_de3d_tc_clamp_lr
(
.de_clk (de_clk),
.clamp_x (clamp_x),
.clamp_y (clamp_y),
.x (ulx_inc),
.y (uly_inc),
.clamp_mask_x (clamp_mask_x),
.clamp_mask_y (clamp_mask_y),
.bitmask_x (bitmask_x),
.bitmask_y (bitmask_y),
// Outputs.
.clamp (clamp_lr),
.new_x (lr_x),
.new_y (lr_y),
.new_x_d (lr_x_d),
.new_y_d (lr_y_d)
);
wire [14:0] ul_tag_adr_rd; // Upper left tag address.
wire [14:0] ll_tag_adr_rd; // Lower left tag address.
wire [14:0] ur_tag_adr_rd; // Upper right tag address.
wire [14:0] lr_tag_adr_rd; // Lower right tag address.
assign ul_tag_adr_rd = {ul_x_d[8:3], ul_y_d};
assign ll_tag_adr_rd = {ll_x_d[8:3], ll_y_d};
assign ur_tag_adr_rd = {ur_x_d[8:3], ur_y_d};
assign lr_tag_adr_rd = {lr_x_d[8:3], lr_y_d};
//
// xx_tag_adr = {u[8:3],v[8:0]}
// [14:9], [8:0]
//
always @* begin
case(bpt_d)
3'b011: // 8 bits per texel.
begin
ul_tag_adr_bpt = {ul_tag_adr_rd[5:1],ul_tag_adr_rd[11]};
ll_tag_adr_bpt = {ll_tag_adr_rd[5:1],ll_tag_adr_rd[11]};
ur_tag_adr_bpt = {ur_tag_adr_rd[5:1],ur_tag_adr_rd[11]};
lr_tag_adr_bpt = {lr_tag_adr_rd[5:1],lr_tag_adr_rd[11]};
end
3'b100: // 16 bits per texel.
begin
ul_tag_adr_bpt = {ul_tag_adr_rd[4:1],ul_tag_adr_rd[11:10]};
ll_tag_adr_bpt = {ll_tag_adr_rd[4:1],ll_tag_adr_rd[11:10]};
ur_tag_adr_bpt = {ur_tag_adr_rd[4:1],ur_tag_adr_rd[11:10]};
lr_tag_adr_bpt = {lr_tag_adr_rd[4:1],lr_tag_adr_rd[11:10]};
end
default: // 32 bits per texel.
begin
ul_tag_adr_bpt = {ul_tag_adr_rd[3:1],ul_tag_adr_rd[11:9]};
ll_tag_adr_bpt = {ll_tag_adr_rd[3:1],ll_tag_adr_rd[11:9]};
ur_tag_adr_bpt = {ur_tag_adr_rd[3:1],ur_tag_adr_rd[11:9]};
lr_tag_adr_bpt = {lr_tag_adr_rd[3:1],lr_tag_adr_rd[11:9]};
end
endcase
end
always @(posedge de_clk) begin
casex ({ul_tag_adr_bpt[0],ul_tag_adr_rd[0],ur_tag_adr_bpt[0]})
3'b01x:
begin
ee_tag_adr_rd <= ll_tag_adr_bpt[5:1];
oe_tag_adr_rd <= lr_tag_adr_bpt[5:1];
eo_tag_adr_rd <= ul_tag_adr_bpt[5:1];
oo_tag_adr_rd <= ur_tag_adr_bpt[5:1];
end
3'b10x:
begin
ee_tag_adr_rd <= ur_tag_adr_bpt[5:1];
oe_tag_adr_rd <= ul_tag_adr_bpt[5:1];
eo_tag_adr_rd <= lr_tag_adr_bpt[5:1];
oo_tag_adr_rd <= ll_tag_adr_bpt[5:1];
end
3'b11x:
begin
ee_tag_adr_rd <= lr_tag_adr_bpt[5:1];
oe_tag_adr_rd <= ll_tag_adr_bpt[5:1];
eo_tag_adr_rd <= ur_tag_adr_bpt[5:1];
oo_tag_adr_rd <= ul_tag_adr_bpt[5:1];
end
default:
begin
ee_tag_adr_rd <= ul_tag_adr_bpt[5:1];
oe_tag_adr_rd <= ur_tag_adr_bpt[5:1];
eo_tag_adr_rd <= ll_tag_adr_bpt[5:1];
oo_tag_adr_rd <= lr_tag_adr_bpt[5:1];
end
endcase
end
// Delay the uv push by one cycle.
// and clip, mipmap, exact.
always @(posedge de_clk) begin
push_uv_dd <= push_uv_d;
push_uv_d <= push_uv;
current_clip_dd <= current_clip_d;
current_clip_d <= current_clip;
current_mipmap_dd <= current_mipmap_d;
current_mipmap_d <= current_mipmap;
current_exact_dd <= current_exact_d;
current_exact_d <= current_exact;
bpt_dd <= bpt_d;
tfmt_dd <=tfmt_d;
pal_mode_dd <= pal_mode_d;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_SYMBOL_V
`define SKY130_FD_SC_LP__AND3B_SYMBOL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Feb 02 02:37:11 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_axi_intc_0_0_stub.v
// Design : design_1_axi_intc_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_intc,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, intr, irq)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,intr[0:0],irq" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input [0:0]intr;
output irq;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:32:16 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n8838, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A, FPMULT_zero_flag,
FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_Data_array_SWR_3__25_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1212, n1213, n1214, n1216,
n1217, n1218, n1220, n1221, n1222, n1224, n1225, n1226, n1228, n1229,
n1230, n1232, n1233, n1234, n1236, n1238, n1240, n1242, n1244, n1245,
n1246, n1248, n1249, n1250, n1252, n1253, n1254, n1256, n1257, n1258,
n1260, n1261, n1262, n1264, n1265, n1266, n1268, n1269, n1270, n1272,
n1274, n1276, n1278, n1280, n1281, n1282, n1283, n1285, n1287, n1288,
n1290, n1292, n1294, n1295, n1297, n1299, n1301, n1302, n1304, n1306,
n1308, n1309, n1311, n1313, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1327, n1329, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1368, n1369, n1371, n1372, n1374, n1375, n1377,
n1378, n1380, n1381, n1383, n1384, n1386, n1387, n1389, n1390, n1392,
n1393, n1395, n1396, n1398, n1399, n1401, n1402, n1404, n1405, n1407,
n1408, n1410, n1411, n1412, n1413, n1414, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1483, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1521, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2145, n2146,
n2147, n2148, n2149, n2150, n2151, n2193, DP_OP_26J211_126_1325_n18,
DP_OP_26J211_126_1325_n17, DP_OP_26J211_126_1325_n16,
DP_OP_26J211_126_1325_n15, DP_OP_26J211_126_1325_n14,
DP_OP_26J211_126_1325_n8, DP_OP_26J211_126_1325_n7,
DP_OP_26J211_126_1325_n6, DP_OP_26J211_126_1325_n5,
DP_OP_26J211_126_1325_n4, DP_OP_26J211_126_1325_n3,
DP_OP_26J211_126_1325_n2, DP_OP_26J211_126_1325_n1, intadd_479_B_1_,
intadd_479_CI, intadd_479_SUM_2_, intadd_479_SUM_1_,
intadd_479_SUM_0_, intadd_479_n3, intadd_479_n2, intadd_479_n1,
intadd_480_CI, intadd_480_SUM_2_, intadd_480_SUM_1_,
intadd_480_SUM_0_, intadd_480_n3, intadd_480_n2, intadd_480_n1,
add_x_246_A_5_, add_x_246_A_3_, add_x_246_A_2_, add_x_246_A_1_,
add_x_246_A_0_, add_x_246_n19, add_x_246_n2, gt_x_74_A_23_,
gt_x_74_B_23_, add_x_69_n272, add_x_69_n205, add_x_69_n204,
add_x_69_n202, add_x_69_n201, add_x_69_n198, add_x_69_n188,
add_x_69_n186, add_x_69_n113, add_x_69_n94, add_x_69_n85,
add_x_69_n69, add_x_69_n59, add_x_69_n57, add_x_69_n51, add_x_69_n47,
add_x_69_n39, add_x_69_n16, DP_OP_496J211_122_3540_n1514,
DP_OP_496J211_122_3540_n1513, DP_OP_496J211_122_3540_n1512,
DP_OP_496J211_122_3540_n1506, DP_OP_496J211_122_3540_n1502,
DP_OP_496J211_122_3540_n1499, DP_OP_496J211_122_3540_n1498,
DP_OP_496J211_122_3540_n1493, DP_OP_496J211_122_3540_n1478,
DP_OP_496J211_122_3540_n1472, DP_OP_496J211_122_3540_n1462,
DP_OP_496J211_122_3540_n1461, DP_OP_496J211_122_3540_n1203,
DP_OP_496J211_122_3540_n1202, DP_OP_496J211_122_3540_n1199,
DP_OP_496J211_122_3540_n1193, DP_OP_496J211_122_3540_n1192,
DP_OP_496J211_122_3540_n1120, DP_OP_496J211_122_3540_n1114,
DP_OP_496J211_122_3540_n1113, DP_OP_496J211_122_3540_n1108,
DP_OP_496J211_122_3540_n1107, DP_OP_496J211_122_3540_n1103,
DP_OP_496J211_122_3540_n1102, DP_OP_496J211_122_3540_n1063,
DP_OP_496J211_122_3540_n778, DP_OP_497J211_123_1725_n794,
DP_OP_497J211_123_1725_n793, DP_OP_497J211_123_1725_n792,
DP_OP_497J211_123_1725_n791, DP_OP_497J211_123_1725_n782,
DP_OP_497J211_123_1725_n781, DP_OP_497J211_123_1725_n780,
DP_OP_497J211_123_1725_n779, DP_OP_497J211_123_1725_n778,
DP_OP_497J211_123_1725_n716, DP_OP_497J211_123_1725_n705,
DP_OP_497J211_123_1725_n686, DP_OP_497J211_123_1725_n669,
DP_OP_497J211_123_1725_n668, DP_OP_497J211_123_1725_n638,
DP_OP_497J211_123_1725_n631, DP_OP_497J211_123_1725_n392,
DP_OP_497J211_123_1725_n324, DP_OP_497J211_123_1725_n312,
DP_OP_498J211_124_1725_n803, DP_OP_498J211_124_1725_n802,
DP_OP_498J211_124_1725_n801, DP_OP_498J211_124_1725_n797,
DP_OP_498J211_124_1725_n796, DP_OP_498J211_124_1725_n795,
DP_OP_498J211_124_1725_n792, DP_OP_498J211_124_1725_n791,
DP_OP_498J211_124_1725_n790, DP_OP_498J211_124_1725_n789,
DP_OP_498J211_124_1725_n788, DP_OP_498J211_124_1725_n786,
DP_OP_498J211_124_1725_n732, DP_OP_498J211_124_1725_n722,
DP_OP_498J211_124_1725_n718, DP_OP_498J211_124_1725_n645,
DP_OP_498J211_124_1725_n636, DP_OP_498J211_124_1725_n635,
DP_OP_498J211_124_1725_n631, DP_OP_498J211_124_1725_n390,
DP_OP_498J211_124_1725_n362, DP_OP_499J211_125_1651_n62,
DP_OP_499J211_125_1651_n44, DP_OP_499J211_125_1651_n39,
DP_OP_499J211_125_1651_n34, DP_OP_499J211_125_1651_n8,
DP_OP_499J211_125_1651_n6, DP_OP_499J211_125_1651_n5,
DP_OP_499J211_125_1651_n4, DP_OP_499J211_125_1651_n3, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465,
n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475,
n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485,
n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495,
n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505,
n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515,
n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525,
n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535,
n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545,
n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555,
n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565,
n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575,
n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715,
n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725,
n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735,
n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745,
n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755,
n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765,
n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775,
n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785,
n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795,
n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805,
n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815,
n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825,
n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835,
n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845,
n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855,
n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865,
n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875,
n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885,
n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336,
n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346,
n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356,
n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366,
n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376,
n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386,
n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396,
n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406,
n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416,
n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426,
n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436,
n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446,
n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456,
n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466,
n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476,
n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486,
n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496,
n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506,
n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516,
n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526,
n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536,
n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546,
n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556,
n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566,
n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576,
n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586,
n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596,
n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606,
n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616,
n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636,
n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646,
n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656,
n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666,
n7667, n7668, n7673, n7674, n7675, n7676, n7677, n7678, n7679, n7680,
n7681, n7682, n7683, n7684, n7685, n7686, n7687, n7688, n7689, n7690,
n7691, n7692, n7693, n7694, n7695, n7696, n7697, n7698, n7699, n7700,
n7701, n7702, n7703, n7704, n7705, n7706, n7707, n7708, n7709, n7710,
n7711, n7712, n7713, n7714, n7715, n7716, n7717, n7718, n7719, n7720,
n7721, n7722, n7723, n7724, n7725, n7726, n7727, n7728, n7729, n7730,
n7731, n7732, n7733, n7734, n7735, n7736, n7737, n7738, n7739, n7740,
n7741, n7742, n7743, n7744, n7745, n7746, n7747, n7748, n7749, n7750,
n7751, n7752, n7753, n7754, n7755, n7756, n7757, n7758, n7759, n7760,
n7761, n7762, n7763, n7764, n7765, n7766, n7767, n7768, n7769, n7770,
n7771, n7772, n7773, n7774, n7775, n7776, n7777, n7778, n7779, n7780,
n7781, n7782, n7783, n7784, n7785, n7786, n7787, n7788, n7789, n7790,
n7791, n7792, n7793, n7794, n7795, n7796, n7797, n7798, n7799, n7800,
n7801, n7802, n7803, n7804, n7805, n7806, n7807, n7808, n7809, n7810,
n7811, n7812, n7813, n7814, n7815, n7816, n7817, n7818, n7819, n7820,
n7821, n7822, n7823, n7824, n7825, n7826, n7827, n7828, n7829, n7830,
n7831, n7832, n7833, n7834, n7835, n7836, n7837, n7838, n7839, n7840,
n7841, n7842, n7843, n7844, n7845, n7846, n7847, n7848, n7849, n7850,
n7851, n7852, n7853, n7854, n7855, n7856, n7857, n7858, n7859, n7860,
n7861, n7862, n7863, n7864, n7865, n7866, n7867, n7868, n7869, n7870,
n7871, n7872, n7873, n7874, n7875, n7876, n7877, n7878, n7879, n7880,
n7881, n7882, n7883, n7884, n7885, n7886, n7887, n7888, n7889, n7890,
n7891, n7892, n7893, n7894, n7895, n7896, n7897, n7898, n7899, n7900,
n7901, n7902, n7903, n7904, n7905, n7906, n7907, n7908, n7909, n7910,
n7911, n7912, n7913, n7914, n7915, n7916, n7917, n7918, n7919, n7920,
n7921, n7922, n7923, n7924, n7925, n7926, n7927, n7928, n7929, n7930,
n7931, n7932, n7933, n7934, n7935, n7936, n7937, n7938, n7939, n7940,
n7941, n7942, n7943, n7944, n7945, n7946, n7947, n7948, n7949, n7950,
n7951, n7952, n7953, n7954, n7955, n7956, n7957, n7958, n7959, n7960,
n7961, n7962, n7963, n7964, n7965, n7966, n7967, n7968, n7969, n7970,
n7971, n7972, n7973, n7974, n7975, n7976, n7977, n7978, n7979, n7980,
n7981, n7982, n7983, n7984, n7985, n7986, n7987, n7988, n7989, n7990,
n7991, n7992, n7993, n7994, n7995, n7996, n7997, n7998, n7999, n8000,
n8001, n8002, n8003, n8004, n8005, n8006, n8007, n8008, n8009, n8010,
n8011, n8012, n8013, n8014, n8015, n8016, n8017, n8018, n8019, n8020,
n8021, n8022, n8023, n8024, n8025, n8026, n8027, n8028, n8029, n8030,
n8031, n8032, n8033, n8034, n8035, n8036, n8037, n8038, n8039, n8040,
n8041, n8042, n8043, n8044, n8045, n8046, n8047, n8048, n8049, n8050,
n8051, n8052, n8053, n8054, n8055, n8056, n8057, n8058, n8059, n8060,
n8061, n8062, n8063, n8064, n8065, n8066, n8067, n8068, n8069, n8070,
n8071, n8072, n8073, n8074, n8075, n8076, n8077, n8078, n8079, n8080,
n8081, n8082, n8083, n8084, n8085, n8086, n8087, n8088, n8089, n8090,
n8091, n8092, n8093, n8094, n8095, n8096, n8097, n8098, n8099, n8100,
n8101, n8102, n8103, n8104, n8105, n8106, n8107, n8108, n8109, n8110,
n8111, n8112, n8113, n8114, n8115, n8116, n8117, n8118, n8119, n8120,
n8121, n8122, n8123, n8124, n8125, n8126, n8127, n8128, n8129, n8130,
n8131, n8132, n8133, n8134, n8135, n8136, n8137, n8138, n8139, n8140,
n8141, n8142, n8143, n8144, n8145, n8146, n8147, n8148, n8149, n8150,
n8151, n8152, n8153, n8154, n8155, n8156, n8157, n8158, n8159, n8160,
n8161, n8162, n8163, n8164, n8165, n8166, n8167, n8168, n8169, n8170,
n8171, n8172, n8173, n8174, n8175, n8176, n8177, n8178, n8179, n8180,
n8181, n8182, n8183, n8184, n8185, n8186, n8187, n8188, n8189, n8190,
n8191, n8192, n8193, n8194, n8195, n8196, n8197, n8198, n8199, n8200,
n8201, n8202, n8203, n8204, n8205, n8206, n8207, n8208, n8209, n8210,
n8211, n8212, n8213, n8214, n8215, n8216, n8217, n8218, n8219, n8220,
n8221, n8222, n8223, n8224, n8225, n8226, n8227, n8228, n8229, n8230,
n8231, n8232, n8233, n8234, n8235, n8236, n8237, n8238, n8239, n8240,
n8241, n8242, n8243, n8244, n8245, n8246, n8247, n8248, n8249, n8250,
n8251, n8252, n8253, n8254, n8255, n8256, n8257, n8258, n8259, n8260,
n8261, n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269, n8270,
n8271, n8272, n8273, n8274, n8275, n8276, n8277, n8278, n8279, n8280,
n8281, n8282, n8283, n8284, n8285, n8286, n8287, n8288, n8289, n8290,
n8291, n8292, n8293, n8294, n8295, n8296, n8297, n8298, n8299, n8300,
n8301, n8302, n8303, n8304, n8305, n8306, n8307, n8308, n8309, n8310,
n8311, n8312, n8313, n8314, n8315, n8316, n8317, n8318, n8319, n8320,
n8321, n8322, n8323, n8324, n8325, n8326, n8327, n8328, n8329, n8330,
n8331, n8332, n8333, n8334, n8335, n8336, n8337, n8338, n8339, n8340,
n8341, n8342, n8343, n8344, n8345, n8346, n8347, n8348, n8349, n8350,
n8351, n8352, n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360,
n8361, n8362, n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370,
n8371, n8372, n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380,
n8381, n8382, n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390,
n8391, n8392, n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400,
n8401, n8402, n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410,
n8411, n8412, n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420,
n8421, n8422, n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430,
n8431, n8432, n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440,
n8441, n8442, n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450,
n8451, n8452, n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460,
n8461, n8462, n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470,
n8471, n8472, n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480,
n8481, n8482, n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490,
n8491, n8492, n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500,
n8501, n8502, n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510,
n8511, n8512, n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520,
n8521, n8522, n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530,
n8531, n8532, n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540,
n8541, n8542, n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550,
n8551, n8552, n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560,
n8561, n8562, n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570,
n8571, n8572, n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580,
n8581, n8582, n8583, n8584, n8585, n8586, n8587, n8588, n8589, n8590,
n8591, n8592, n8593, n8594, n8595, n8596, n8597, n8598, n8599, n8600,
n8601, n8602, n8603, n8604, n8605, n8606, n8607, n8608, n8609, n8610,
n8611, n8612, n8614, n8615, n8616, n8617, n8618, n8619, n8620, n8621,
n8622, n8623, n8624, n8625, n8626, n8627, n8628, n8629, n8630, n8631,
n8632, n8633, n8634, n8635, n8636, n8637, n8638, n8639, n8640, n8641,
n8642, n8643, n8644, n8645, n8646, n8647, n8648, n8649, n8650, n8651,
n8652, n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660, n8661,
n8662, n8663, n8664, n8665, n8666, n8667, n8668, n8669, n8670, n8671,
n8672, n8673, n8674, n8675, n8676, n8677, n8678, n8679, n8680, n8681,
n8682, n8683, n8684, n8685, n8686, n8687, n8688, n8689, n8690, n8691,
n8692, n8693, n8694, n8695, n8696, n8697, n8698, n8699, n8700, n8701,
n8702, n8703, n8704, n8705, n8706, n8707, n8708, n8709, n8710, n8711,
n8712, n8713, n8714, n8715, n8716, n8717, n8718, n8719, n8720, n8721,
n8722, n8723, n8724, n8725, n8726, n8727, n8728, n8729, n8730, n8731,
n8732, n8733, n8734, n8735, n8736, n8737, n8738, n8739, n8740, n8741,
n8742, n8743, n8744, n8745, n8746, n8747, n8748, n8749, n8750, n8751,
n8752, n8753, n8754, n8755, n8756, n8757, n8758, n8759, n8760, n8761,
n8762, n8763, n8764, n8765, n8766, n8767, n8768, n8769, n8770, n8771,
n8772, n8773, n8774, n8775, n8776, n8777, n8778, n8779, n8780, n8781,
n8782, n8783, n8784, n8785, n8786, n8787, n8788, n8789, n8790, n8791,
n8792, n8793, n8794, n8795, n8796, n8797, n8798, n8799, n8800, n8801,
n8802, n8803, n8804, n8805, n8806, n8807, n8808, n8809, n8810, n8811,
n8812, n8813, n8814, n8815, n8816, n8817, n8818, n8819, n8820, n8821,
n8822, n8823, n8824, n8825, n8826, n8827, n8828, n8829, n8830, n8831,
n8832, n8833, n8834, n8835, n8836, n8837;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [21:0] FPMULT_Add_result;
wire [8:0] FPMULT_exp_oper_result;
wire [31:4] FPMULT_Op_MY;
wire [31:4] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [24:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [3:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [27:25] FPMULT_Sgf_operation_Result;
wire [21:17] FPMULT_Sgf_operation_EVEN1_S_B;
wire [13:5] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [22:3] FPMULT_Adder_M_result_A_adder;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n8577), .Q(
dataA[28]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n8577), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n8576), .Q(
dataB[24]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n8575), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n8575), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n8575), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n8575), .Q(
dataB[30]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n8575), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n8575),
.Q(n2332), .QN(n7798) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n7990), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n7876) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n8544), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n7855) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n2400), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n3179) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n8546), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2296) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n7909) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n7910) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n7912) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n7911) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n7913) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n7925) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n7926) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n7927) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n7928) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n8575), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n7796) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n8586),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n8583),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n7896) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n8581),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n8581),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n7897) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n8580),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n8580),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n7898) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n7899) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n2426),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n7929) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n7900) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n8561),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n8561),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n7901) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n8560),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n8560),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n7902) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n7887) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n7930) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n7888) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n7931) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n7903) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n8557),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n8557),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n7904) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n8556),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n8556),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n7889) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n7932) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n7905) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n8554),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n7906) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n8554),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n7907) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n7933) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n7908) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n8552),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n8552),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n7938) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n7878) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n8551),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n7882) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n8551),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n7974), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n7890) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n8550),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n8550),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n8550),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n8550), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n7891) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n8569),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n8569),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n7934) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n8569),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n7892) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n8568),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n7886) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n8567),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n7935) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n8567),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n7893) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n8567),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n8566),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n7936) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n8566),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n7894) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n8566),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n7937) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n8565),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n7895) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n8564),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n8564),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n8564),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n8564),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n8564),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n8564),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n8564),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n8564),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n8564),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n8595),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n7776),
.Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n7991),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n8562),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n2470),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n7991),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n8594),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n8592),
.Q(cordic_result[22]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n8599), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n2366), .Q(FPMULT_zero_flag) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n2394), .Q(FPMULT_Op_MX[22]), .QN(n8285) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n8596), .Q(FPMULT_Op_MX[20]), .QN(n2226) );
DFFRX4TS R_678 ( .D(n1678), .CK(clk), .RN(n2493), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS R_291 ( .D(n1677), .CK(clk), .RN(n8599), .Q(FPMULT_Op_MX[18]), .QN(
n2304) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[16]), .QN(n8343) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[11]), .QN(n8286) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[4]), .QN(n8489) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n2420), .Q(FPMULT_Op_MX[31]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[22]), .QN(n3175) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[20]), .QN(n3174) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n2384), .Q(FPMULT_Op_MY[9]), .QN(n8486) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n2385), .Q(FPMULT_Op_MY[8]), .QN(n8487) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n2385), .Q(FPMULT_Op_MY[6]), .QN(n8482) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[24]), .QN(n3164) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk),
.RN(n8562), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk),
.RN(n8591), .Q(FPMULT_P_Sgf[21]), .QN(n3158) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk),
.RN(n8592), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk),
.RN(n7991), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n2384), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n2392), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n2392), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n2367), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n2367), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n2367), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n2367), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n2367), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n2368), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n2368), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n2368), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n2368), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n2368), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n8597), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n8597), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n8597), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n8597), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n8597), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n8597), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n8597), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n8597), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n8597), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n8597), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n2363), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n2363), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n2363), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n2363), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n2364), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n2364), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n2364), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n2364), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n2364), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n2364), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n8544), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n8544), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]), .QN(n2448) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]), .QN(n2450) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]), .QN(n2452) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]), .QN(n2454) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]), .QN(n2456) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n7961),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n7957),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]), .QN(n2458) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n8529),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n8548),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n8547),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]), .QN(n2460) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n8528),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n8532),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n7961),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]), .QN(n2462) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n8532), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n8634), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n8530), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n8531), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n8531), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n7961), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n7957), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n8529), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n8528), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n8533),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n8549), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n8536), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n6353),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n6354),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n7987), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n8533),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n8549), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n8536), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n7955),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n7824) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n7799) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n7856) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n7807) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n8544), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n7924), .CK(clk), .RN(n8634),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n8538), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n2401), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n7969),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n7923), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n2421),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n2387), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n7922), .CK(clk), .RN(n7953),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n7921), .CK(clk), .RN(n2401),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n8530),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n7920), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n2400),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n8549), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n8536),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n6354),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n7919), .CK(clk), .RN(n7980),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[10]), .QN(n2465) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[14]), .QN(n2480) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n7955),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[16]), .QN(n2474) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n8542),
.QN(n2289) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n7918), .CK(clk), .RN(n2400),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n7917), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n2347),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n2482) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[20]), .QN(n2476) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n2484) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[18]), .QN(n2478) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n7987),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n8543),
.QN(n2290) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n7987),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n2472) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n2370), .QN(n7805) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n8634), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n7914) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n7875) );
CMPR32X2TS DP_OP_26J211_126_1325_U4 ( .A(n7806), .B(n2459), .C(
DP_OP_26J211_126_1325_n4), .CO(DP_OP_26J211_126_1325_n3), .S(
FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J211_126_1325_U3 ( .A(n7806), .B(n2461), .C(
DP_OP_26J211_126_1325_n3), .CO(DP_OP_26J211_126_1325_n2), .S(
FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J211_126_1325_U2 ( .A(n7806), .B(n2463), .C(
DP_OP_26J211_126_1325_n2), .CO(DP_OP_26J211_126_1325_n1), .S(
FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_479_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n7809), .C(
intadd_479_CI), .CO(intadd_479_n3), .S(intadd_479_SUM_0_) );
CMPR32X2TS intadd_479_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_479_B_1_),
.C(intadd_479_n3), .CO(intadd_479_n2), .S(intadd_479_SUM_1_) );
CMPR32X2TS intadd_479_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n7790), .C(
intadd_479_n2), .CO(intadd_479_n1), .S(intadd_479_SUM_2_) );
DFFSX2TS R_62 ( .D(n8753), .CK(clk), .SN(n7988), .Q(n8504) );
DFFSX2TS R_108 ( .D(n8744), .CK(clk), .SN(n7963), .Q(n8499) );
DFFSX2TS R_169 ( .D(n8711), .CK(clk), .SN(n7978), .Q(n8497) );
DFFSX2TS R_170 ( .D(n8713), .CK(clk), .SN(n7979), .Q(n8496) );
DFFRX4TS R_561 ( .D(n1672), .CK(clk), .RN(n2393), .Q(
DP_OP_497J211_123_1725_n792) );
DFFRX4TS R_300 ( .D(n1659), .CK(clk), .RN(n2420), .Q(
DP_OP_496J211_122_3540_n1506), .QN(n3165) );
DFFRX4TS R_441 ( .D(n1629), .CK(clk), .RN(n2384), .Q(
DP_OP_498J211_124_1725_n790) );
DFFRX4TS R_423 ( .D(n1646), .CK(clk), .RN(n8598), .Q(
DP_OP_496J211_122_3540_n778), .QN(n3167) );
DFFRX4TS R_1704 ( .D(n1643), .CK(clk), .RN(n8604), .Q(
DP_OP_497J211_123_1725_n782), .QN(n2326) );
DFFRX4TS R_656 ( .D(n1642), .CK(clk), .RN(n7993), .Q(
DP_OP_497J211_123_1725_n781) );
DFFRX4TS R_435 ( .D(n1628), .CK(clk), .RN(n2384), .Q(
DP_OP_498J211_124_1725_n789) );
DFFRX4TS R_444 ( .D(n1641), .CK(clk), .RN(n8598), .Q(
DP_OP_497J211_123_1725_n780) );
DFFRX4TS R_614 ( .D(n1666), .CK(clk), .RN(n2494), .Q(
DP_OP_496J211_122_3540_n1513) );
DFFRX4TS R_626 ( .D(n1627), .CK(clk), .RN(n2384), .Q(
DP_OP_498J211_124_1725_n788) );
DFFRX2TS R_633 ( .D(n1322), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX4TS R_1703 ( .D(n1644), .CK(clk), .RN(n8604), .Q(
DP_OP_496J211_122_3540_n1461), .QN(n3144) );
DFFRX4TS R_665 ( .D(n1634), .CK(clk), .RN(n2384), .Q(n8518), .QN(n3145) );
DFFSX2TS R_666 ( .D(n8697), .CK(clk), .SN(n7966), .Q(n8412) );
DFFSX2TS R_669 ( .D(n8709), .CK(clk), .SN(n7958), .Q(n8411) );
DFFRXLTS R_675 ( .D(add_x_246_A_3_), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFSX2TS R_685 ( .D(n8708), .CK(clk), .SN(n7958), .Q(n8409) );
DFFRX4TS R_689 ( .D(n1671), .CK(clk), .RN(n7994), .Q(
DP_OP_496J211_122_3540_n1493), .QN(n3180) );
DFFSX2TS R_692 ( .D(n8695), .CK(clk), .SN(n7958), .Q(n8408) );
DFFSX2TS R_695 ( .D(n8707), .CK(clk), .SN(n7953), .Q(n8407) );
DFFRX4TS R_700 ( .D(n1662), .CK(clk), .RN(n7994), .Q(
DP_OP_498J211_124_1725_n803) );
DFFRX4TS R_703 ( .D(n1674), .CK(clk), .RN(n2393), .Q(
DP_OP_497J211_123_1725_n794), .QN(n8344) );
DFFSX2TS R_706 ( .D(n8679), .CK(clk), .SN(n7955), .Q(n8406) );
DFFSX2TS R_707 ( .D(n8675), .CK(clk), .SN(n7955), .Q(n8405) );
DFFSX2TS R_710 ( .D(n7878), .CK(clk), .SN(n7976), .Q(n8404) );
DFFSX2TS R_711 ( .D(n8678), .CK(clk), .SN(n7976), .Q(n8403) );
DFFSX2TS R_714 ( .D(n7796), .CK(clk), .SN(n2419), .Q(n8402) );
DFFSX2TS R_718 ( .D(n7938), .CK(clk), .SN(n7973), .Q(n8400) );
DFFSX2TS R_719 ( .D(n8692), .CK(clk), .SN(n7975), .Q(n8399) );
DFFSX2TS R_722 ( .D(n7937), .CK(clk), .SN(n7983), .Q(n8398) );
DFFSX2TS R_723 ( .D(n8689), .CK(clk), .SN(n7983), .Q(n8397) );
DFFSX2TS R_727 ( .D(n8681), .CK(clk), .SN(n7983), .Q(n8395) );
DFFSX2TS R_731 ( .D(n8680), .CK(clk), .SN(n7979), .Q(n8393) );
DFFSX2TS R_730 ( .D(n7935), .CK(clk), .SN(n7978), .Q(n8394) );
DFFSX2TS R_735 ( .D(n8682), .CK(clk), .SN(n7979), .Q(n8391) );
DFFSX2TS R_734 ( .D(n7934), .CK(clk), .SN(n7978), .Q(n8392) );
DFFSX2TS R_739 ( .D(n8659), .CK(clk), .SN(n7976), .Q(n8389) );
DFFSX2TS R_738 ( .D(n7908), .CK(clk), .SN(n7976), .Q(n8390) );
DFFSX2TS R_742 ( .D(n7907), .CK(clk), .SN(n7973), .Q(n8388) );
DFFSX2TS R_746 ( .D(n7933), .CK(clk), .SN(n8537), .Q(n8386) );
DFFSX2TS R_747 ( .D(n8690), .CK(clk), .SN(n7958), .Q(n8385) );
DFFSX2TS R_750 ( .D(n7906), .CK(clk), .SN(n7973), .Q(n8384) );
DFFSX2TS R_751 ( .D(n8661), .CK(clk), .SN(n8539), .Q(n8383) );
DFFSX2TS R_754 ( .D(n7905), .CK(clk), .SN(n7973), .Q(n8382) );
DFFSX2TS R_755 ( .D(n8658), .CK(clk), .SN(n7973), .Q(n8381) );
DFFSX2TS R_758 ( .D(n7932), .CK(clk), .SN(n7969), .Q(n8380) );
DFFSX2TS R_759 ( .D(n8688), .CK(clk), .SN(n7969), .Q(n8379) );
DFFSX2TS R_762 ( .D(n7904), .CK(clk), .SN(n7969), .Q(n8378) );
DFFSX2TS R_763 ( .D(n8663), .CK(clk), .SN(n7969), .Q(n8377) );
DFFSX2TS R_766 ( .D(n7903), .CK(clk), .SN(n7970), .Q(n8376) );
DFFSX2TS R_767 ( .D(n8660), .CK(clk), .SN(n7970), .Q(n8375) );
DFFSX2TS R_770 ( .D(n7931), .CK(clk), .SN(n7965), .Q(n8374) );
DFFSX2TS R_771 ( .D(n8686), .CK(clk), .SN(n7966), .Q(n8373) );
DFFSX2TS R_775 ( .D(n8684), .CK(clk), .SN(n7966), .Q(n8371) );
DFFSX2TS R_774 ( .D(n7930), .CK(clk), .SN(n7965), .Q(n8372) );
DFFSX2TS R_778 ( .D(n7902), .CK(clk), .SN(n7965), .Q(n8370) );
DFFSX2TS R_779 ( .D(n8664), .CK(clk), .SN(n7965), .Q(n8369) );
DFFSX2TS R_782 ( .D(n7901), .CK(clk), .SN(n7965), .Q(n8368) );
DFFSX2TS R_783 ( .D(n8667), .CK(clk), .SN(n7965), .Q(n8367) );
DFFSX2TS R_798 ( .D(n7897), .CK(clk), .SN(n7958), .Q(n8360) );
DFFSX2TS R_799 ( .D(n8662), .CK(clk), .SN(n7958), .Q(n8359) );
DFFSX2TS R_802 ( .D(n7896), .CK(clk), .SN(n7958), .Q(n8358) );
DFFSX2TS R_803 ( .D(n8669), .CK(clk), .SN(n7958), .Q(n8357) );
DFFSX2TS R_806 ( .D(n7881), .CK(clk), .SN(n7955), .Q(n8356) );
DFFSX2TS R_822 ( .D(n7884), .CK(clk), .SN(n2469), .Q(n8348) );
DFFSX2TS R_823 ( .D(n8672), .CK(clk), .SN(n2469), .Q(n8347) );
DFFSX2TS R_826 ( .D(n7883), .CK(clk), .SN(n8538), .Q(n8346) );
DFFSX2TS R_827 ( .D(n8671), .CK(clk), .SN(n8530), .Q(n8345) );
DFFRX4TS R_837 ( .D(n1673), .CK(clk), .RN(n2393), .Q(
DP_OP_497J211_123_1725_n793), .QN(n2320) );
DFFRX4TS R_858 ( .D(n1676), .CK(clk), .RN(n2393), .Q(
DP_OP_496J211_122_3540_n1498) );
DFFRX4TS R_848 ( .D(n1648), .CK(clk), .RN(n7995), .Q(n8462) );
DFFRX4TS R_852 ( .D(n1645), .CK(clk), .RN(n7993), .Q(
DP_OP_496J211_122_3540_n1462) );
DFFSX2TS R_866 ( .D(n8652), .CK(clk), .SN(n2387), .Q(n8335) );
DFFSX2TS R_865 ( .D(n7895), .CK(clk), .SN(n7983), .Q(n8336) );
DFFSX2TS R_869 ( .D(n7894), .CK(clk), .SN(n7970), .Q(n8334) );
DFFSX2TS R_870 ( .D(n8656), .CK(clk), .SN(n2421), .Q(n8333) );
DFFSX2TS R_873 ( .D(n7893), .CK(clk), .SN(n7963), .Q(n8332) );
DFFSX2TS R_874 ( .D(n8648), .CK(clk), .SN(n7970), .Q(n8331) );
DFFSX2TS R_877 ( .D(n7892), .CK(clk), .SN(n7979), .Q(n8330) );
DFFSX2TS R_878 ( .D(n8654), .CK(clk), .SN(n7979), .Q(n8329) );
DFFSX2TS R_881 ( .D(n7891), .CK(clk), .SN(n7979), .Q(n8328) );
DFFSX2TS R_882 ( .D(n8649), .CK(clk), .SN(n7979), .Q(n8327) );
DFFSX2TS R_885 ( .D(n7890), .CK(clk), .SN(n7975), .Q(n8326) );
DFFSX2TS R_886 ( .D(n8650), .CK(clk), .SN(n7976), .Q(n8325) );
DFFSX2TS R_889 ( .D(n7889), .CK(clk), .SN(n7970), .Q(n8324) );
DFFSX2TS R_890 ( .D(n8655), .CK(clk), .SN(n7970), .Q(n8323) );
DFFSX2TS R_893 ( .D(n7888), .CK(clk), .SN(n7965), .Q(n8322) );
DFFSX2TS R_894 ( .D(n8653), .CK(clk), .SN(n7965), .Q(n8321) );
DFFSX2TS R_898 ( .D(n8651), .CK(clk), .SN(n7965), .Q(n8319) );
DFFSX2TS R_897 ( .D(n7887), .CK(clk), .SN(n7965), .Q(n8320) );
DFFSX2TS R_901 ( .D(n7886), .CK(clk), .SN(n7979), .Q(n8318) );
DFFSX2TS R_902 ( .D(n8647), .CK(clk), .SN(n7979), .Q(n8317) );
DFFSX2TS R_905 ( .D(n7929), .CK(clk), .SN(n7963), .Q(n8316) );
DFFSX2TS R_913 ( .D(n7927), .CK(clk), .SN(n7953), .Q(n8312) );
DFFSX2TS R_917 ( .D(n7926), .CK(clk), .SN(n7953), .Q(n8310) );
DFFSX2TS R_918 ( .D(n8704), .CK(clk), .SN(n7953), .Q(n8309) );
DFFSX2TS R_921 ( .D(n7925), .CK(clk), .SN(n7953), .Q(n8308) );
DFFSX2TS R_922 ( .D(n8703), .CK(clk), .SN(n7953), .Q(n8307) );
DFFSX2TS R_924 ( .D(n8685), .CK(clk), .SN(n8534), .Q(n8306) );
DFFSX2TS R_927 ( .D(n8694), .CK(clk), .SN(n7973), .Q(n8305) );
DFFSX2TS R_930 ( .D(n8687), .CK(clk), .SN(n7980), .Q(n8304) );
DFFSX2TS R_933 ( .D(n8691), .CK(clk), .SN(n7973), .Q(n8303) );
DFFSX2TS R_936 ( .D(n8693), .CK(clk), .SN(n7970), .Q(n8302) );
DFFSX2TS R_939 ( .D(n8683), .CK(clk), .SN(n7975), .Q(n8301) );
DFFSX2TS R_942 ( .D(n8696), .CK(clk), .SN(n7970), .Q(n8300) );
DFFSX2TS R_950 ( .D(n8698), .CK(clk), .SN(n7963), .Q(n8298) );
DFFSX2TS R_953 ( .D(n8699), .CK(clk), .SN(n7963), .Q(n8297) );
DFFSX2TS R_956 ( .D(n8702), .CK(clk), .SN(n7959), .Q(n8296) );
DFFSX2TS R_976 ( .D(n8754), .CK(clk), .SN(n7975), .Q(n8295) );
DFFSX2TS R_978 ( .D(n8710), .CK(clk), .SN(n7959), .Q(n8294) );
DFFSX2TS R_990 ( .D(n8414), .CK(clk), .SN(n2419), .Q(n8631) );
DFFSX2TS R_1014 ( .D(n8299), .CK(clk), .SN(n2419), .Q(n8630) );
DFFSX2TS R_1016 ( .D(n8293), .CK(clk), .SN(n2419), .Q(n8633) );
DFFRXLTS R_1020 ( .D(n1521), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS R_1031 ( .D(n8292), .CK(clk), .RN(n2418), .Q(n8646) );
DFFSX2TS R_1038 ( .D(n8644), .CK(clk), .SN(n8546), .Q(n8290) );
DFFSX2TS R_1039 ( .D(n8526), .CK(clk), .SN(n8546), .Q(n8289) );
DFFSX2TS R_1040 ( .D(n7548), .CK(clk), .SN(n8546), .Q(n8288) );
DFFSX2TS R_1041 ( .D(n8643), .CK(clk), .SN(n8546), .Q(n8287) );
DFFRX4TS R_1052 ( .D(n1680), .CK(clk), .RN(n8596), .Q(
DP_OP_496J211_122_3540_n1502), .QN(n3166) );
DFFRX4TS R_1053 ( .D(n1668), .CK(clk), .RN(n2493), .Q(
DP_OP_498J211_124_1725_n797) );
DFFRXLTS R_1063 ( .D(FPSENCOS_d_ff3_LUT_out[15]), .CK(clk), .RN(n7956), .Q(
n8284) );
DFFSX2TS R_1074 ( .D(n8282), .CK(clk), .SN(n2469), .Q(n8642) );
DFFRXLTS R_1080 ( .D(FPSENCOS_d_ff3_sh_y_out[14]), .CK(clk), .RN(n7972), .Q(
n8279) );
DFFRXLTS R_1082 ( .D(FPSENCOS_d_ff3_sh_x_out[14]), .CK(clk), .RN(n7972), .Q(
n8278) );
DFFRXLTS R_1096 ( .D(FPSENCOS_d_ff3_sh_y_out[11]), .CK(clk), .RN(n7972), .Q(
n8271) );
DFFRXLTS R_1098 ( .D(FPSENCOS_d_ff3_sh_x_out[11]), .CK(clk), .RN(n7972), .Q(
n8270) );
DFFRXLTS R_1108 ( .D(FPSENCOS_d_ff3_sh_y_out[13]), .CK(clk), .RN(n7968), .Q(
n8265) );
DFFRXLTS R_1110 ( .D(FPSENCOS_d_ff3_sh_x_out[13]), .CK(clk), .RN(n7968), .Q(
n8264) );
DFFRXLTS R_1114 ( .D(FPSENCOS_d_ff3_sh_x_out[3]), .CK(clk), .RN(n7974), .Q(
n8262) );
DFFRXLTS R_1112 ( .D(FPSENCOS_d_ff3_sh_y_out[3]), .CK(clk), .RN(n7974), .Q(
n8263) );
DFFRXLTS R_1167 ( .D(FPSENCOS_d_ff3_sh_y_out[15]), .CK(clk), .RN(n8529), .Q(
n8237) );
DFFRXLTS R_1169 ( .D(FPSENCOS_d_ff3_sh_x_out[15]), .CK(clk), .RN(n8548), .Q(
n8236) );
DFFRXLTS R_1173 ( .D(FPSENCOS_d_ff3_LUT_out[1]), .CK(clk), .RN(n7981), .Q(
n8234) );
DFFRXLTS R_1171 ( .D(FPSENCOS_d_ff3_sh_y_out[1]), .CK(clk), .RN(n7981), .Q(
n8235) );
DFFRXLTS R_1183 ( .D(FPSENCOS_d_ff3_sh_y_out[12]), .CK(clk), .RN(n7972), .Q(
n8229) );
DFFRXLTS R_1185 ( .D(FPSENCOS_d_ff3_LUT_out[12]), .CK(clk), .RN(n7972), .Q(
n8228) );
DFFRXLTS R_1189 ( .D(FPSENCOS_d_ff3_LUT_out[0]), .CK(clk), .RN(n7977), .Q(
n8226) );
DFFRXLTS R_1187 ( .D(FPSENCOS_d_ff3_sh_y_out[0]), .CK(clk), .RN(n7977), .Q(
n8227) );
DFFRXLTS R_1197 ( .D(FPSENCOS_d_ff3_LUT_out[9]), .CK(clk), .RN(n7982), .Q(
n8222) );
DFFRXLTS R_1203 ( .D(FPSENCOS_d_ff3_sh_y_out[2]), .CK(clk), .RN(n7978), .Q(
n8219) );
DFFRXLTS R_1205 ( .D(FPSENCOS_d_ff3_LUT_out[2]), .CK(clk), .RN(n7978), .Q(
n8218) );
DFFRX4TS R_1207 ( .D(n1664), .CK(clk), .RN(n2365), .Q(n8519), .QN(n3173) );
DFFRXLTS R_1275 ( .D(FPSENCOS_d_ff2_Z[1]), .CK(clk), .RN(n7981), .Q(n8188)
);
DFFSX2TS R_1355 ( .D(n1419), .CK(clk), .SN(n8528), .Q(n8152) );
DFFSX2TS R_1353 ( .D(n8610), .CK(clk), .SN(n7961), .Q(n8153) );
DFFRXLTS R_1373 ( .D(FPSENCOS_d_ff3_LUT_out[5]), .CK(clk), .RN(n7971), .Q(
n8150) );
DFFRXLTS R_1375 ( .D(FPSENCOS_d_ff3_LUT_out[3]), .CK(clk), .RN(n7967), .Q(
n8149) );
DFFRXLTS R_1385 ( .D(FPSENCOS_d_ff3_LUT_out[7]), .CK(clk), .RN(n7971), .Q(
n8148) );
DFFRXLTS R_1387 ( .D(FPSENCOS_d_ff3_LUT_out[13]), .CK(clk), .RN(n7960), .Q(
n8147) );
DFFSX2TS R_338_RW_0 ( .D(n8725), .CK(clk), .SN(n7988), .Q(n8475) );
DFFSX2TS R_346_RW_0 ( .D(n8723), .CK(clk), .SN(n7988), .Q(n8472) );
DFFSX2TS R_354_RW_0 ( .D(n8720), .CK(clk), .SN(n7988), .Q(n8470) );
DFFSX2TS R_366_RW_0 ( .D(n8729), .CK(clk), .SN(n7988), .Q(n8466) );
DFFSX2TS R_383_RW_0 ( .D(n8726), .CK(clk), .SN(n7988), .Q(n8457) );
DFFSX2TS R_409_RW_0 ( .D(n8717), .CK(clk), .SN(n7988), .Q(n8449) );
DFFSX2TS R_481_RW_0 ( .D(n8732), .CK(clk), .SN(n7988), .Q(n8440) );
DFFSX2TS R_485_RW_0 ( .D(n8735), .CK(clk), .SN(n7988), .Q(n8438) );
DFFSX1TS R_1413 ( .D(FPMULT_Sgf_operation_Result[27]), .CK(clk), .SN(n2426),
.Q(n8145) );
DFFSX2TS R_1420 ( .D(n1467), .CK(clk), .SN(n7985), .Q(n8142) );
DFFSX2TS R_1418 ( .D(n8608), .CK(clk), .SN(n7985), .Q(n8143) );
DFFSX2TS R_1439 ( .D(n8775), .CK(clk), .SN(n8531), .Q(n8140) );
DFFSX2TS R_1442 ( .D(n8774), .CK(clk), .SN(n2370), .Q(n8139) );
DFFSX2TS R_1445 ( .D(n8791), .CK(clk), .SN(n8549), .Q(n8138) );
DFFSX2TS R_1448 ( .D(n8781), .CK(clk), .SN(n7955), .Q(n8137) );
DFFSX2TS R_1454 ( .D(n8803), .CK(clk), .SN(n8534), .Q(n8135) );
DFFSX2TS R_1457 ( .D(n8770), .CK(clk), .SN(n2370), .Q(n8134) );
DFFSX2TS R_1462 ( .D(n8778), .CK(clk), .SN(n8531), .Q(n8133) );
DFFSX2TS R_1465 ( .D(n8797), .CK(clk), .SN(n2388), .Q(n8132) );
DFFSX2TS R_1471 ( .D(n8777), .CK(clk), .SN(n8531), .Q(n8130) );
DFFSX2TS R_1474 ( .D(n8771), .CK(clk), .SN(n2370), .Q(n8129) );
DFFSX2TS R_1475 ( .D(n8796), .CK(clk), .SN(n2388), .Q(n8128) );
DFFSX2TS R_1477 ( .D(n8795), .CK(clk), .SN(n2388), .Q(n8127) );
DFFSX2TS R_1480 ( .D(n8776), .CK(clk), .SN(n8531), .Q(n8126) );
DFFSX2TS R_1483 ( .D(n8780), .CK(clk), .SN(n7961), .Q(n8125) );
DFFRXLTS R_1484 ( .D(add_x_246_A_5_), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFSX2TS R_1489 ( .D(n8767), .CK(clk), .SN(n8530), .Q(n8124) );
DFFSX2TS R_1492 ( .D(n8766), .CK(clk), .SN(n7961), .Q(n8123) );
DFFSX2TS R_1493 ( .D(n5947), .CK(clk), .SN(n8533), .Q(n8122) );
DFFSX2TS R_1495 ( .D(n8794), .CK(clk), .SN(n8536), .Q(n8121) );
DFFSX2TS R_1499 ( .D(n8779), .CK(clk), .SN(n8536), .Q(n8120) );
DFFSX2TS R_1504 ( .D(n8769), .CK(clk), .SN(n7957), .Q(n8119) );
DFFSX2TS R_1505 ( .D(n8752), .CK(clk), .SN(n7990), .Q(n8118) );
DFFSX2TS R_1520 ( .D(n8827), .CK(clk), .SN(n2400), .Q(n8116) );
DFFSX2TS R_1523 ( .D(n8818), .CK(clk), .SN(n2423), .Q(n8115) );
DFFSX2TS R_1526 ( .D(n8822), .CK(clk), .SN(n2423), .Q(n8114) );
DFFSX2TS R_1529 ( .D(n8821), .CK(clk), .SN(n2423), .Q(n8113) );
DFFSX2TS R_1532 ( .D(n8765), .CK(clk), .SN(n8528), .Q(n8112) );
DFFSX2TS R_1544 ( .D(n8819), .CK(clk), .SN(n2423), .Q(n8109) );
DFFSX2TS R_1547 ( .D(n8800), .CK(clk), .SN(n2388), .Q(n8108) );
DFFSX2TS R_1550 ( .D(n8788), .CK(clk), .SN(n6354), .Q(n8107) );
DFFSX2TS R_1553 ( .D(n8762), .CK(clk), .SN(n7957), .Q(n8106) );
DFFSX2TS R_1559 ( .D(n8758), .CK(clk), .SN(n8539), .Q(n8105) );
DFFSX2TS R_1565 ( .D(n8792), .CK(clk), .SN(n8533), .Q(n8103) );
DFFSX2TS R_1568 ( .D(n8829), .CK(clk), .SN(n2401), .Q(n8102) );
DFFSX2TS R_1574 ( .D(n8804), .CK(clk), .SN(n8535), .Q(n8100) );
DFFSX2TS R_1577 ( .D(n8772), .CK(clk), .SN(n2370), .Q(n8099) );
DFFSX2TS R_1580 ( .D(n8773), .CK(clk), .SN(n2370), .Q(n8098) );
DFFSX2TS R_1583 ( .D(n8768), .CK(clk), .SN(n8532), .Q(n8097) );
DFFSX2TS R_1590 ( .D(n8764), .CK(clk), .SN(n8532), .Q(n8096) );
DFFSX2TS R_1596 ( .D(n8831), .CK(clk), .SN(n2400), .Q(n8095) );
DFFSX2TS R_1602 ( .D(n8816), .CK(clk), .SN(n2423), .Q(n8093) );
DFFSX2TS R_1605 ( .D(n8798), .CK(clk), .SN(n2388), .Q(n8092) );
DFFSX2TS R_1606 ( .D(n5896), .CK(clk), .SN(n8539), .Q(n8091) );
DFFSX2TS R_1608 ( .D(n8759), .CK(clk), .SN(n8539), .Q(n8090) );
DFFSX2TS R_1609 ( .D(n8782), .CK(clk), .SN(n8539), .Q(n8089) );
DFFSX2TS R_1611 ( .D(n8760), .CK(clk), .SN(n8539), .Q(n8088) );
DFFSX2TS R_1612 ( .D(n8783), .CK(clk), .SN(n8539), .Q(n8087) );
DFFSX2TS R_1614 ( .D(n8761), .CK(clk), .SN(n8535), .Q(n8086) );
DFFRXLTS R_1270_RW_0 ( .D(FPSENCOS_d_ff2_Z[0]), .CK(clk), .RN(n7967), .Q(
n8190) );
DFFSX2TS R_1619 ( .D(n8756), .CK(clk), .SN(n7985), .Q(n8085) );
DFFSX2TS R_1625 ( .D(n8757), .CK(clk), .SN(n7985), .Q(n8084) );
DFFSX2TS R_1631 ( .D(n8755), .CK(clk), .SN(n7985), .Q(n8083) );
DFFSX2TS R_1637 ( .D(n8825), .CK(clk), .SN(n2401), .Q(n8082) );
DFFSX2TS R_1640 ( .D(n8823), .CK(clk), .SN(n2400), .Q(n8081) );
DFFSX2TS R_1646 ( .D(n8789), .CK(clk), .SN(n8549), .Q(n8079) );
DFFSX2TS R_1649 ( .D(n8801), .CK(clk), .SN(n2388), .Q(n8078) );
DFFSX2TS R_1657 ( .D(n8606), .CK(clk), .SN(n7964), .Q(n8077) );
DFFSX2TS R_1660 ( .D(n8606), .CK(clk), .SN(n7969), .Q(n8076) );
DFFSX2TS R_1661 ( .D(n8606), .CK(clk), .SN(n7966), .Q(n8075) );
DFFSX2TS R_1662 ( .D(n8606), .CK(clk), .SN(n7959), .Q(n8074) );
DFFSX1TS R_1667 ( .D(FPMULT_Sgf_operation_Result[26]), .CK(clk), .SN(n2425),
.Q(n8072) );
DFFSX2TS R_1670 ( .D(FPMULT_Sgf_operation_Result[25]), .CK(clk), .SN(n2426),
.Q(n8070) );
DFFRX4TS R_1700 ( .D(n1632), .CK(clk), .RN(n8604), .Q(
DP_OP_496J211_122_3540_n1472), .QN(n3150) );
DFFRX4TS R_1699 ( .D(n1638), .CK(clk), .RN(n8598), .Q(
DP_OP_496J211_122_3540_n1478), .QN(n3172) );
DFFSX2TS R_1734 ( .D(n8525), .CK(clk), .SN(n8593), .Q(n8057) );
DFFSX2TS R_1739 ( .D(n8523), .CK(clk), .SN(n7985), .Q(n8056) );
DFFSX2TS R_1752 ( .D(n7826), .CK(clk), .SN(n7963), .Q(n8046) );
DFFSX2TS R_1759 ( .D(n5942), .CK(clk), .SN(n8537), .Q(n8042) );
DFFSX2TS R_1760 ( .D(n8790), .CK(clk), .SN(n6353), .Q(n8041) );
DFFSX2TS R_1762 ( .D(n8799), .CK(clk), .SN(n2388), .Q(n8039) );
DFFSX2TS R_1763 ( .D(n8802), .CK(clk), .SN(n2388), .Q(n8038) );
DFFSX2TS R_1767 ( .D(n8820), .CK(clk), .SN(n2423), .Q(n8034) );
DFFSX2TS R_1768 ( .D(n8834), .CK(clk), .SN(n7988), .Q(n8033) );
DFFSX2TS R_1769 ( .D(n5884), .CK(clk), .SN(n7985), .Q(n8032) );
DFFSX2TS R_1770 ( .D(n5878), .CK(clk), .SN(n7986), .Q(n8031) );
DFFSX2TS R_1771 ( .D(n8763), .CK(clk), .SN(n7985), .Q(n8030) );
DFFSX2TS R_1772 ( .D(n8733), .CK(clk), .SN(n7973), .Q(n8029) );
DFFSX2TS R_1773 ( .D(n8730), .CK(clk), .SN(n7969), .Q(n8028) );
DFFSX2TS R_1775 ( .D(n8742), .CK(clk), .SN(n7959), .Q(n8026) );
DFFSX2TS R_1776 ( .D(n8739), .CK(clk), .SN(n7966), .Q(n8025) );
DFFSX2TS R_1777 ( .D(n8724), .CK(clk), .SN(n7983), .Q(n8024) );
DFFSX2TS R_1778 ( .D(n8721), .CK(clk), .SN(n7983), .Q(n8023) );
DFFSX2TS R_1779 ( .D(n8718), .CK(clk), .SN(n7958), .Q(n8022) );
DFFSX2TS R_1780 ( .D(n8715), .CK(clk), .SN(n8547), .Q(n8021) );
DFFSX2TS R_1781 ( .D(n8712), .CK(clk), .SN(n7979), .Q(n8020) );
DFFSX2TS R_1784 ( .D(n7374), .CK(clk), .SN(n7976), .Q(n8017) );
DFFSX2TS R_1786 ( .D(n8810), .CK(clk), .SN(n2389), .Q(n8015) );
DFFSX2TS R_1789 ( .D(n8824), .CK(clk), .SN(n2401), .Q(n8012) );
DFFSX2TS R_1790 ( .D(n8828), .CK(clk), .SN(n2401), .Q(n8011) );
DFFSX2TS R_1791 ( .D(n8832), .CK(clk), .SN(n2400), .Q(n8010) );
DFFSX2TS R_1792 ( .D(n8784), .CK(clk), .SN(n8539), .Q(n8009) );
DFFSX2TS R_1793 ( .D(n8786), .CK(clk), .SN(n7986), .Q(n8008) );
DFFSX2TS R_1794 ( .D(n8817), .CK(clk), .SN(n2423), .Q(n8007) );
DFFSX2TS R_1795 ( .D(n5946), .CK(clk), .SN(n2423), .Q(n8006) );
DFFSX2TS R_1796 ( .D(n5945), .CK(clk), .SN(n2423), .Q(n8005) );
DFFSX2TS R_1798 ( .D(n8830), .CK(clk), .SN(n2400), .Q(n8003) );
DFFSX2TS R_1799 ( .D(n8787), .CK(clk), .SN(n7986), .Q(n8002) );
DFFSX2TS R_1800 ( .D(n8785), .CK(clk), .SN(n7986), .Q(n8001) );
DFFSX2TS R_1801 ( .D(n8736), .CK(clk), .SN(n8534), .Q(n8000) );
DFFSX2TS R_1802 ( .D(n8826), .CK(clk), .SN(n2401), .Q(n7999) );
DFFSX2TS R_1804 ( .D(n8727), .CK(clk), .SN(n7969), .Q(n7998) );
DFFSX2TS R_1805 ( .D(gt_x_74_A_23_), .CK(clk), .SN(n7985), .Q(n7997) );
DFFRX1TS R_1015 ( .D(n1336), .CK(clk), .RN(n2418), .Q(
FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n7940) );
DFFRXLTS R_1698 ( .D(n8065), .CK(clk), .RN(n7994), .QN(n7916) );
DFFRXLTS R_1705 ( .D(n8062), .CK(clk), .RN(n7994), .QN(n7915) );
DFFRXLTS R_1004 ( .D(n1672), .CK(clk), .RN(n2394), .Q(n8481), .QN(n7877) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_X[28]), .QN(n7860) );
DFFRX1TS R_632 ( .D(n1321), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n7825) );
DFFRX1TS R_947 ( .D(n1335), .CK(clk), .RN(n2418), .Q(
FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n7823) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n8573),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n7822) );
DFFRX1TS R_1030 ( .D(n1333), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n7821) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_var_out[0]), .QN(n7819) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n7809) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n7993), .Q(
FPMULT_FSM_selector_B[0]), .QN(n7808) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n8530), .Q(n8838), .QN(n7939) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n7804) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n8573),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n7802) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n7994), .Q(FPMULT_exp_oper_result[8]), .QN(n7801) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n2367), .Q(
FPMULT_FSM_selector_B[1]), .QN(n7791) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n2365), .Q(
FPMULT_FSM_selector_A), .QN(n7854) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n7790) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n8587),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n7789) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n8635),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n7788) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n7881) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n8575), .Q(NaN_flag)
);
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n7879) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n7880) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n7885) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n7884) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n7883) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n7792) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n7818) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n7813) );
CMPR32X2TS DP_OP_26J211_126_1325_U5 ( .A(DP_OP_26J211_126_1325_n14), .B(
n2457), .C(DP_OP_26J211_126_1325_n5), .CO(DP_OP_26J211_126_1325_n4),
.S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J211_126_1325_U6 ( .A(DP_OP_26J211_126_1325_n15), .B(
n2455), .C(DP_OP_26J211_126_1325_n6), .CO(DP_OP_26J211_126_1325_n5),
.S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J211_126_1325_U7 ( .A(DP_OP_26J211_126_1325_n16), .B(
n2453), .C(DP_OP_26J211_126_1325_n7), .CO(DP_OP_26J211_126_1325_n6),
.S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J211_126_1325_U8 ( .A(DP_OP_26J211_126_1325_n17), .B(
n2451), .C(DP_OP_26J211_126_1325_n8), .CO(DP_OP_26J211_126_1325_n7),
.S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFSX1TS add_x_69_R_1825 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[19]), .CK(clk),
.SN(n7777), .Q(n7775) );
DFFSX1TS add_x_69_R_1824 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[21]), .CK(clk),
.SN(n7777), .Q(n7774) );
DFFSX2TS add_x_69_R_1818 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CK(
clk), .SN(n2426), .Q(n7768) );
DFFSX1TS add_x_69_R_1816 ( .D(add_x_69_n188), .CK(clk), .SN(n7776), .Q(n7766) );
DFFRXLTS add_x_69_R_1656 ( .D(add_x_69_n205), .CK(clk), .RN(n7779), .Q(n7755) );
DFFRXLTS add_x_69_R_1655 ( .D(add_x_69_n204), .CK(clk), .RN(n7778), .Q(n7754) );
DFFSX1TS add_x_69_R_1429 ( .D(add_x_69_n202), .CK(clk), .SN(n7777), .QN(
n7752) );
DFFSX1TS add_x_69_R_1650 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[17]), .CK(clk),
.SN(n7777), .Q(n7750) );
DFFSX1TS add_x_69_R_1506 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[18]), .CK(clk),
.SN(n7777), .Q(n7748) );
DFFRXLTS add_x_69_R_1051 ( .D(add_x_69_n202), .CK(clk), .RN(n7777), .Q(n7745) );
DFFSX1TS add_x_69_R_975 ( .D(add_x_69_n186), .CK(clk), .SN(n7777), .Q(n7744)
);
DFFSX1TS add_x_69_R_651 ( .D(add_x_69_n16), .CK(clk), .SN(n7777), .Q(n7743)
);
DFFSX4TS DP_OP_496J211_122_3540_R_1714 ( .D(n7725), .CK(clk), .SN(n7726),
.Q(DP_OP_496J211_122_3540_n1203) );
DFFSX4TS DP_OP_496J211_122_3540_R_1713 ( .D(n7724), .CK(clk), .SN(n8596),
.Q(DP_OP_496J211_122_3540_n1199) );
DFFSX4TS DP_OP_496J211_122_3540_R_1711 ( .D(n7722), .CK(clk), .SN(n7726),
.Q(DP_OP_496J211_122_3540_n1108) );
DFFSX4TS DP_OP_496J211_122_3540_R_1708 ( .D(n7721), .CK(clk), .SN(n7726),
.Q(DP_OP_496J211_122_3540_n1113), .QN(n7730) );
DFFSX2TS DP_OP_496J211_122_3540_R_1707 ( .D(n7720), .CK(clk), .SN(n7726),
.Q(DP_OP_496J211_122_3540_n1063) );
DFFSX4TS DP_OP_496J211_122_3540_R_1006 ( .D(n7719), .CK(clk), .SN(n2364),
.Q(DP_OP_496J211_122_3540_n1202), .QN(n7728) );
DFFRX4TS DP_OP_496J211_122_3540_R_835 ( .D(n7717), .CK(clk), .RN(n8600), .Q(
n7716), .QN(n7733) );
DFFSX4TS DP_OP_496J211_122_3540_R_701 ( .D(n7715), .CK(clk), .SN(n2368), .Q(
DP_OP_496J211_122_3540_n1192), .QN(n7731) );
DFFSX4TS DP_OP_496J211_122_3540_R_658 ( .D(n7714), .CK(clk), .SN(n7726), .Q(
DP_OP_496J211_122_3540_n1107), .QN(n7727) );
DFFSX4TS DP_OP_496J211_122_3540_R_999 ( .D(n7713), .CK(clk), .SN(n7726), .Q(
DP_OP_496J211_122_3540_n1120) );
DFFSX4TS DP_OP_496J211_122_3540_R_442 ( .D(n7712), .CK(clk), .SN(n7726), .Q(
DP_OP_496J211_122_3540_n1114) );
DFFRX1TS DP_OP_497J211_123_1725_R_860 ( .D(n1676), .CK(clk), .RN(n8599), .Q(
DP_OP_497J211_123_1725_n312) );
DFFSX4TS DP_OP_497J211_123_1725_R_859 ( .D(n7707), .CK(clk), .SN(n8596), .Q(
DP_OP_497J211_123_1725_n324), .QN(n7708) );
DFFSX4TS DP_OP_497J211_123_1725_R_857 ( .D(n7706), .CK(clk), .SN(n2364), .Q(
DP_OP_497J211_123_1725_n631), .QN(n3178) );
DFFSX4TS DP_OP_497J211_123_1725_R_850 ( .D(n7705), .CK(clk), .SN(n8604), .Q(
DP_OP_497J211_123_1725_n392), .QN(n3141) );
DFFRX4TS DP_OP_497J211_123_1725_R_851 ( .D(n1645), .CK(clk), .RN(n7995), .Q(
DP_OP_497J211_123_1725_n686) );
DFFRX4TS DP_OP_497J211_123_1725_R_853 ( .D(n1639), .CK(clk), .RN(n2363), .Q(
DP_OP_497J211_123_1725_n778) );
DFFSX4TS DP_OP_497J211_123_1725_R_690 ( .D(n7704), .CK(clk), .SN(n2394), .Q(
DP_OP_497J211_123_1725_n638) );
DFFRX4TS DP_OP_497J211_123_1725_R_681 ( .D(n1678), .CK(clk), .RN(n8599), .Q(
DP_OP_497J211_123_1725_n705) );
DFFSX4TS DP_OP_497J211_123_1725_R_854 ( .D(n7701), .CK(clk), .SN(n8604), .Q(
DP_OP_497J211_123_1725_n716), .QN(n3177) );
DFFSX4TS DP_OP_498J211_124_1725_R_1045 ( .D(n7696), .CK(clk), .SN(n2385),
.Q(DP_OP_498J211_124_1725_n635) );
DFFRX4TS DP_OP_498J211_124_1725_R_845 ( .D(n1667), .CK(clk), .RN(n2366), .Q(
DP_OP_498J211_124_1725_n796) );
DFFRX4TS DP_OP_498J211_124_1725_R_846 ( .D(n1661), .CK(clk), .RN(n2365), .Q(
DP_OP_498J211_124_1725_n802), .QN(n7698) );
DFFRX4TS DP_OP_498J211_124_1725_R_611 ( .D(n7693), .CK(clk), .RN(n2494), .Q(
DP_OP_498J211_124_1725_n390), .QN(n7700) );
DFFRX4TS DP_OP_498J211_124_1725_R_613 ( .D(n1666), .CK(clk), .RN(n2417), .Q(
DP_OP_498J211_124_1725_n795) );
DFFRX4TS DP_OP_498J211_124_1725_R_615 ( .D(n1660), .CK(clk), .RN(n2368), .Q(
DP_OP_498J211_124_1725_n801) );
DFFSX4TS DP_OP_498J211_124_1725_R_608 ( .D(n7689), .CK(clk), .SN(n2393), .Q(
DP_OP_498J211_124_1725_n732) );
DFFSX4TS DP_OP_498J211_124_1725_R_1043 ( .D(n7690), .CK(clk), .SN(n2420),
.Q(DP_OP_498J211_124_1725_n645) );
DFFSX4TS DP_OP_498J211_124_1725_R_282 ( .D(n5702), .CK(clk), .SN(n2385), .Q(
DP_OP_498J211_124_1725_n636), .QN(n7694) );
DFFSX4TS DP_OP_498J211_124_1725_R_606 ( .D(n7687), .CK(clk), .SN(n2368), .Q(
DP_OP_498J211_124_1725_n722) );
DFFSX1TS DP_OP_499J211_125_1651_R_1682 ( .D(DP_OP_499J211_125_1651_n34),
.CK(clk), .SN(n2425), .QN(n7684) );
DFFSX1TS DP_OP_499J211_125_1651_R_1677 ( .D(DP_OP_499J211_125_1651_n6), .CK(
clk), .SN(n8578), .Q(n7682) );
DFFRXLTS DP_OP_499J211_125_1651_R_1674 ( .D(n7685), .CK(clk), .RN(n2424),
.Q(n7681) );
DFFRXLTS DP_OP_499J211_125_1651_R_1659 ( .D(DP_OP_499J211_125_1651_n8), .CK(
clk), .RN(n2470), .Q(n7680) );
DFFSX1TS DP_OP_499J211_125_1651_R_1658 ( .D(DP_OP_499J211_125_1651_n62),
.CK(clk), .SN(n8562), .Q(n7679) );
DFFRXLTS DP_OP_499J211_125_1651_R_1459 ( .D(DP_OP_499J211_125_1651_n4), .CK(
clk), .RN(n2426), .Q(n7678) );
DFFSX1TS DP_OP_499J211_125_1651_R_1458 ( .D(DP_OP_499J211_125_1651_n39),
.CK(clk), .SN(n2426), .Q(n7677) );
DFFRXLTS DP_OP_499J211_125_1651_R_1377 ( .D(DP_OP_499J211_125_1651_n5), .CK(
clk), .RN(n8591), .Q(n7675) );
DFFSX1TS DP_OP_499J211_125_1651_R_1376 ( .D(DP_OP_499J211_125_1651_n44),
.CK(clk), .SN(n2425), .Q(n7674) );
DFFRXLTS R_657 ( .D(n1630), .CK(clk), .RN(n2385), .QN(n7803) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRXLTS R_1047 ( .D(n1668), .CK(clk), .RN(n2394), .QN(n8340) );
DFFRHQX2TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n2422), .Q(n8523) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[23]), .QN(n8418) );
DFFRXLTS R_1142 ( .D(FPSENCOS_d_ff2_Z[18]), .CK(clk), .RN(n7957), .Q(n8248)
);
DFFSRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .SN(1'b1), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[6]) );
DFFSRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .SN(1'b1),
.RN(n8635), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n7794) );
DFFSRX4TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .SN(1'b1),
.RN(n8635), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n7817) );
DFFRXLTS R_259 ( .D(FPMULT_Adder_M_result_A_adder[22]), .CK(clk), .RN(n8603),
.Q(n8494) );
DFFRXLTS DP_OP_499J211_125_1651_R_1417 ( .D(DP_OP_499J211_125_1651_n3), .CK(
clk), .RN(n2424), .Q(n7676) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n8590), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n7815) );
DFFSX1TS R_5 ( .D(n8621), .CK(clk), .SN(n8591), .Q(n8516) );
DFFRXLTS R_68 ( .D(n1586), .CK(clk), .RN(n7992), .Q(n8502) );
DFFRXLTS R_330 ( .D(n8723), .CK(clk), .RN(n8532), .Q(n8478) );
DFFRXLTS R_389 ( .D(n1803), .CK(clk), .RN(n7968), .Q(n8455) );
DFFRXLTS R_475 ( .D(n1799), .CK(clk), .RN(n7981), .Q(n8443) );
DFFRXLTS R_565 ( .D(n1518), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[1]) );
DFFSX1TS R_743 ( .D(n8657), .CK(clk), .SN(n2370), .Q(n8387) );
DFFRXLTS R_1078 ( .D(FPSENCOS_d_ff3_sh_x_out[5]), .CK(clk), .RN(n7981), .Q(
n8280) );
DFFRXLTS R_1106 ( .D(FPSENCOS_d_ff2_Z[13]), .CK(clk), .RN(n7968), .Q(n8266)
);
DFFRXLTS R_1165 ( .D(FPSENCOS_d_ff2_Z[12]), .CK(clk), .RN(n7975), .Q(n8238)
);
DFFRXLTS R_1263 ( .D(FPSENCOS_d_ff2_Z[8]), .CK(clk), .RN(n7967), .Q(n8194)
);
DFFRXLTS R_1328 ( .D(FPSENCOS_d_ff3_sh_x_out[22]), .CK(clk), .RN(n8547), .Q(
n8162) );
DFFRXLTS R_1358 ( .D(n8835), .CK(clk), .RN(n7957), .Q(n8151) );
DFFRXLTS R_1423 ( .D(n8610), .CK(clk), .RN(n7984), .Q(n8141) );
DFFRXLTS R_1671 ( .D(n1578), .CK(clk), .RN(n2424), .Q(n8069) );
DFFRX1TS R_1748 ( .D(n8731), .CK(clk), .RN(n7967), .Q(n8050) );
DFFSX1TS R_1764 ( .D(n8805), .CK(clk), .SN(n8535), .Q(n8037) );
DFFRXLTS add_x_69_R_1807 ( .D(add_x_69_n39), .CK(clk), .RN(n2424), .Q(n7758)
);
DFFRXLTS add_x_69_R_49 ( .D(add_x_69_n59), .CK(clk), .RN(n7779), .Q(n7740)
);
DFFSHQX1TS DP_OP_496J211_122_3540_R_292 ( .D(n7710), .CK(clk), .SN(n2494),
.Q(n7709) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n8573),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n8536), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n6353), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n6354), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n7867) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRHQX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1569), .CK(
clk), .RN(n8635), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n8533), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n2334) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n8549), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n7797) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n8536), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n7810) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n2365), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFSX4TS R_1718 ( .D(n8521), .CK(clk), .SN(n2469), .Q(n8059), .QN(n2467) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n8575), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n7994), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n8611), .CK(clk),
.RN(n8574), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n6354), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n7816) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n8533), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2294) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n6353), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n7812) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[17]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n8550),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n8549), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n7793) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n8598), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n2366), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n2391), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n2363), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n2385), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n2367), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n2384), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n8576), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk),
.RN(n8592), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[20]) );
DFFSX1TS R_1691 ( .D(n8066), .CK(clk), .SN(n8593), .Q(n8641) );
DFFSX1TS R_1690 ( .D(n8067), .CK(clk), .SN(n8577), .Q(n8640) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n8581),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n8582),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n8584),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n8584),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n8585),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n8586),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n8564),
.Q(cordic_result[31]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n8577), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n8577), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n8536), .Q(result_add_subt[31]), .QN(n2343) );
DFFRX1TS DP_OP_497J211_123_1725_R_679 ( .D(n7702), .CK(clk), .RN(n2494), .Q(
DP_OP_497J211_123_1725_n668) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[0]) );
DFFRX1TS R_1073 ( .D(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk),
.RN(n2423), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n2469), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n7820) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_X[23]) );
DFFSX1TS R_1720 ( .D(n8746), .CK(clk), .SN(n7959), .Q(n2293), .QN(n2337) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n2469), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n7795) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n2366), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n8577),
.Q(operation_reg[1]) );
DFFSX1TS R_1721 ( .D(n8748), .CK(clk), .SN(n2469), .Q(n2292), .QN(n2338) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n2422), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n7873) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n8530), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n7864) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n8538), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n7861) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n2387), .Q(result_add_subt[0]), .QN(n7846) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n2387), .Q(result_add_subt[1]), .QN(n7847) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n7865) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[27]) );
DFFSX1TS R_1761 ( .D(n8793), .CK(clk), .SN(n6354), .Q(n8040) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n8534), .Q(result_add_subt[2]), .QN(n7844) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n8535), .Q(result_add_subt[3]), .QN(n7843) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n8537), .Q(result_add_subt[7]), .QN(n7845) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n6353), .Q(result_add_subt[5]), .QN(n7849) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n6354), .Q(result_add_subt[12]), .QN(n7842) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n6354), .Q(result_add_subt[9]), .QN(n7848) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n8532), .Q(result_add_subt[14]), .QN(n7840) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n8528), .Q(result_add_subt[10]), .QN(n7841) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n8531), .Q(result_add_subt[8]), .QN(n7838) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n7961), .Q(result_add_subt[11]), .QN(n7839) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n2418), .Q(result_add_subt[24]), .QN(n7853) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n2418), .Q(result_add_subt[26]), .QN(n7852) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n8634), .Q(result_add_subt[27]), .QN(n7851) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n8538), .Q(result_add_subt[28]), .QN(n7850) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n7957), .Q(result_add_subt[15]), .QN(n7828) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n8528), .Q(result_add_subt[18]), .QN(n7829) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n8531), .Q(result_add_subt[6]), .QN(n7835) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n8531), .Q(result_add_subt[13]), .QN(n7836) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n8531), .Q(result_add_subt[16]), .QN(n7837) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS R_1128 ( .D(FPSENCOS_d_ff2_X[19]), .CK(clk), .RN(n8529), .Q(n8255)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS R_1116 ( .D(FPSENCOS_d_ff2_X[17]), .CK(clk), .RN(n8539), .Q(n8261)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS R_1104 ( .D(FPSENCOS_d_ff2_X[13]), .CK(clk), .RN(n7969), .Q(n8267)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS R_1229 ( .D(FPSENCOS_d_ff2_X[16]), .CK(clk), .RN(n7968), .Q(n8207)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS R_1199 ( .D(FPSENCOS_d_ff2_X[14]), .CK(clk), .RN(n7972), .Q(n8221)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n8550), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS R_1285 ( .D(FPSENCOS_d_ff2_X[3]), .CK(clk), .RN(n7975), .Q(n8183)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS R_1256 ( .D(FPSENCOS_d_ff2_X[7]), .CK(clk), .RN(n7978), .Q(n8197)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS R_1250 ( .D(FPSENCOS_d_ff2_X[5]), .CK(clk), .RN(n7982), .Q(n8199)
);
DFFRXLTS R_831 ( .D(n1661), .CK(clk), .RN(n2420), .QN(n8490) );
DFFRXLTS R_843 ( .D(n1661), .CK(clk), .RN(n2420), .Q(n8341) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS R_1179 ( .D(FPSENCOS_d_ff2_X[15]), .CK(clk), .RN(n8532), .Q(n8231)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS R_1140 ( .D(FPSENCOS_d_ff2_X[18]), .CK(clk), .RN(n8548), .Q(n8249)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS R_1088 ( .D(FPSENCOS_d_ff2_X[10]), .CK(clk), .RN(n7972), .Q(n8275)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS R_1163 ( .D(FPSENCOS_d_ff2_X[12]), .CK(clk), .RN(n7974), .Q(n8239)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS R_1277 ( .D(FPSENCOS_d_ff2_X[2]), .CK(clk), .RN(n7978), .Q(n8187)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS R_1261 ( .D(FPSENCOS_d_ff2_X[8]), .CK(clk), .RN(n7968), .Q(n8195)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS R_1246 ( .D(FPSENCOS_d_ff2_X[9]), .CK(clk), .RN(n7982), .Q(n8201)
);
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n8634), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n7806) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n8578), .Q(
dataA[27]) );
DFFRX1TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n8578), .Q(
dataA[26]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n8578), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n8578), .Q(
dataA[24]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n8578), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n8576), .Q(
dataB[23]) );
DFFRX1TS R_1717 ( .D(n8060), .CK(clk), .RN(n8576), .Q(n8638) );
DFFRXLTS R_487 ( .D(n1793), .CK(clk), .RN(n7984), .Q(n8437) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n2490) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n8575), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk),
.RN(n2425), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS add_x_246_R_250 ( .D(FPMULT_Sgf_normalized_result[23]), .CK(clk),
.RN(n2417), .Q(n7780) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n2417), .Q(FPMULT_Op_MY[30]), .QN(n8463) );
DFFRXLTS add_x_246_R_251 ( .D(add_x_246_n2), .CK(clk), .RN(n2417), .Q(n7781)
);
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n2417), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk),
.RN(n7991), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS R_471 ( .D(n1797), .CK(clk), .RN(n7982), .Q(n8445) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n8612), .CK(clk), .RN(n2469), .Q(
ready_add_subt), .QN(n7800) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n2347), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n7863) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n7862) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n2391), .Q(underflow_flag_mult), .QN(n7874) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n2369), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n7872) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n2400), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n7871) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n2370), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n7870) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n7980), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n7869) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n7868) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk),
.RN(n2425), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk),
.RN(n8595), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk),
.RN(n8578), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk),
.RN(n8562), .Q(FPMULT_P_Sgf[7]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2340) );
DFFSX2TS R_1719 ( .D(n8522), .CK(clk), .SN(n7980), .Q(n8058), .QN(n2295) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n8569),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n3146) );
DFFRHQX8TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(
clk), .RN(n2494), .Q(n2274) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n2401), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n7951) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n8634), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n7948) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n2422), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n7947) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n2348), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n7946) );
DFFSX1TS R_2 ( .D(n8628), .CK(clk), .SN(n2425), .Q(n8517) );
DFFSX1TS R_8 ( .D(n8614), .CK(clk), .SN(n7776), .Q(n8515) );
DFFSX1TS R_11 ( .D(n8619), .CK(clk), .SN(n8562), .Q(n8514) );
DFFSX1TS R_14 ( .D(n8617), .CK(clk), .SN(n8576), .Q(n8513) );
DFFSX1TS R_17 ( .D(n8623), .CK(clk), .SN(n8594), .Q(n8512) );
DFFSX1TS R_20 ( .D(n8622), .CK(clk), .SN(n8562), .Q(n8511) );
DFFSX1TS R_23 ( .D(n8618), .CK(clk), .SN(n8562), .Q(n8510) );
DFFSX1TS R_26 ( .D(n8620), .CK(clk), .SN(n8593), .Q(n8509) );
DFFSX1TS R_29 ( .D(n8625), .CK(clk), .SN(n8562), .Q(n8508) );
DFFSX1TS R_30 ( .D(n6859), .CK(clk), .SN(n8576), .Q(n8507) );
DFFSX1TS R_32 ( .D(n8624), .CK(clk), .SN(n2470), .Q(n8506) );
DFFRXLTS R_34 ( .D(n1589), .CK(clk), .RN(n8562), .Q(n8505) );
DFFRXLTS R_65 ( .D(n1588), .CK(clk), .RN(n7992), .Q(n8503) );
DFFRXLTS R_71 ( .D(n1587), .CK(clk), .RN(n7992), .Q(n8501) );
DFFRXLTS R_74 ( .D(n1585), .CK(clk), .RN(n7992), .Q(n8500) );
DFFSX1TS R_168 ( .D(n8627), .CK(clk), .SN(n2417), .Q(n8498) );
DFFSX1TS R_174 ( .D(n8615), .CK(clk), .SN(n2417), .Q(n8495) );
DFFSX1TS R_260 ( .D(n8616), .CK(clk), .SN(n2420), .Q(n8493) );
DFFRXLTS R_268 ( .D(n1584), .CK(clk), .RN(n7992), .Q(n8492) );
DFFRXLTS R_272 ( .D(n1583), .CK(clk), .RN(n7992), .Q(n8491) );
DFFRX2TS R_296 ( .D(n1665), .CK(clk), .RN(n2363), .Q(
DP_OP_496J211_122_3540_n1512) );
DFFRXLTS R_334 ( .D(n8741), .CK(clk), .RN(n7984), .Q(n8477) );
DFFRXLTS R_336 ( .D(n1805), .CK(clk), .RN(n7955), .Q(n8476) );
DFFRXLTS R_342 ( .D(n8732), .CK(clk), .RN(n7981), .Q(n8474) );
DFFRXLTS R_344 ( .D(n1806), .CK(clk), .RN(n7981), .Q(n8473) );
DFFRXLTS R_352 ( .D(n1808), .CK(clk), .RN(n8549), .Q(n8471) );
DFFRXLTS R_360 ( .D(n1807), .CK(clk), .RN(n7982), .Q(n8469) );
DFFRXLTS R_364 ( .D(n1802), .CK(clk), .RN(n7990), .Q(n8467) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[28]), .QN(n8465) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[29]), .QN(n8464) );
DFFRXLTS R_373 ( .D(n1801), .CK(clk), .RN(n7967), .Q(n8461) );
DFFRXLTS R_379 ( .D(n8738), .CK(clk), .RN(n8533), .Q(n8459) );
DFFRXLTS R_381 ( .D(n1804), .CK(clk), .RN(n7967), .Q(n8458) );
DFFRXLTS R_387 ( .D(n8716), .CK(clk), .RN(n7958), .Q(n8456) );
DFFRXLTS R_395 ( .D(n8729), .CK(clk), .RN(n7968), .Q(n8453) );
DFFRXLTS R_401 ( .D(n1809), .CK(clk), .RN(n7960), .Q(n8452) );
DFFRXLTS R_404 ( .D(n1629), .CK(clk), .RN(n2385), .QN(n8484) );
DFFRXLTS R_407 ( .D(n1810), .CK(clk), .RN(n7956), .Q(n8450) );
DFFRXLTS R_413 ( .D(n8717), .CK(clk), .RN(n7960), .Q(n8448) );
DFFRXLTS R_417 ( .D(n8735), .CK(clk), .RN(n7981), .Q(n8447) );
DFFRXLTS R_461 ( .D(n8726), .CK(clk), .RN(n7968), .Q(n8446) );
DFFRXLTS R_479 ( .D(n1800), .CK(clk), .RN(n7971), .Q(n8441) );
DFFRXLTS R_483 ( .D(n1798), .CK(clk), .RN(n7971), .Q(n8439) );
DFFRXLTS R_498 ( .D(n1791), .CK(clk), .RN(n7960), .Q(n8433) );
DFFRXLTS R_504 ( .D(n8720), .CK(clk), .RN(n7981), .Q(n8431) );
DFFRXLTS R_508 ( .D(n8745), .CK(clk), .RN(n8548), .Q(n8430) );
DFFSX1TS R_519 ( .D(n8626), .CK(clk), .SN(n7992), .Q(n8426) );
DFFRXLTS R_521 ( .D(n1796), .CK(clk), .RN(n7969), .Q(n8425) );
DFFRXLTS R_528 ( .D(n1792), .CK(clk), .RN(n7962), .Q(n8423) );
DFFRXLTS R_535 ( .D(n1790), .CK(clk), .RN(n7956), .Q(n8421) );
DFFRX1TS R_566 ( .D(n1517), .CK(clk), .RN(n2391), .Q(
FPMULT_Sgf_normalized_result[0]) );
DFFRXLTS R_564 ( .D(n1519), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRXLTS R_579 ( .D(n1582), .CK(clk), .RN(n7992), .Q(n8416) );
DFFRX1TS R_597 ( .D(n1317), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX1TS R_596 ( .D(n1412), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX1TS R_604 ( .D(n1319), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX1TS R_603 ( .D(n1318), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRXLTS R_609 ( .D(n1666), .CK(clk), .RN(n2394), .QN(n8479) );
DFFRX1TS R_634 ( .D(n1323), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRXLTS R_653 ( .D(n6859), .CK(clk), .RN(n7992), .Q(n8413) );
DFFSX1TS R_682 ( .D(n8700), .CK(clk), .SN(n7962), .Q(n8410) );
DFFSX1TS R_715 ( .D(n8670), .CK(clk), .SN(n2369), .Q(n8401) );
DFFSX1TS R_726 ( .D(n7936), .CK(clk), .SN(n2399), .Q(n8396) );
DFFSX1TS R_786 ( .D(n7900), .CK(clk), .SN(n7962), .Q(n8366) );
DFFSX1TS R_787 ( .D(n8666), .CK(clk), .SN(n7962), .Q(n8365) );
DFFSX1TS R_790 ( .D(n7899), .CK(clk), .SN(n7962), .Q(n8364) );
DFFSX1TS R_791 ( .D(n8668), .CK(clk), .SN(n7962), .Q(n8363) );
DFFSX1TS R_794 ( .D(n7898), .CK(clk), .SN(n7962), .Q(n8362) );
DFFSX1TS R_795 ( .D(n8665), .CK(clk), .SN(n7962), .Q(n8361) );
DFFSX1TS R_807 ( .D(n8677), .CK(clk), .SN(n7954), .Q(n8355) );
DFFSX1TS R_810 ( .D(n7879), .CK(clk), .SN(n7954), .Q(n8354) );
DFFSX1TS R_811 ( .D(n8676), .CK(clk), .SN(n7954), .Q(n8353) );
DFFSX1TS R_814 ( .D(n7880), .CK(clk), .SN(n7954), .Q(n8352) );
DFFSX1TS R_815 ( .D(n8674), .CK(clk), .SN(n7954), .Q(n8351) );
DFFSX1TS R_818 ( .D(n7885), .CK(clk), .SN(n7954), .Q(n8350) );
DFFSX1TS R_819 ( .D(n8673), .CK(clk), .SN(n7954), .Q(n8349) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[28]), .QN(n8339) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[29]), .QN(n8338) );
DFFRXLTS R_849 ( .D(n1639), .CK(clk), .RN(n7994), .Q(n8520) );
DFFRX1TS R_855 ( .D(DP_OP_497J211_123_1725_n779), .CK(clk), .RN(n7994), .Q(
n8485) );
DFFSX1TS R_906 ( .D(n8701), .CK(clk), .SN(n7962), .Q(n8315) );
DFFSX1TS R_909 ( .D(n7928), .CK(clk), .SN(n7954), .Q(n8314) );
DFFSX1TS R_910 ( .D(n8706), .CK(clk), .SN(n7954), .Q(n8313) );
DFFSX1TS R_914 ( .D(n8705), .CK(clk), .SN(n7954), .Q(n8311) );
DFFRX1TS R_948 ( .D(n1334), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRXLTS R_1005 ( .D(n1660), .CK(clk), .RN(n2394), .Q(n8488), .QN(n8342) );
DFFRXLTS R_1032 ( .D(n8291), .CK(clk), .RN(n2419), .Q(n8629) );
DFFRXLTS R_1042 ( .D(n1631), .CK(clk), .RN(n2385), .Q(FPMULT_Op_MY[4]), .QN(
n8483) );
DFFRXLTS R_1065 ( .D(FPSENCOS_d_ff3_LUT_out[27]), .CK(clk), .RN(n7952), .Q(
n8283) );
DFFRXLTS R_1076 ( .D(FPSENCOS_d_ff3_sh_y_out[5]), .CK(clk), .RN(n7982), .Q(
n8281) );
DFFRXLTS R_1084 ( .D(FPSENCOS_d_ff2_X[28]), .CK(clk), .RN(n7952), .Q(n8277)
);
DFFRXLTS R_1086 ( .D(FPSENCOS_d_ff2_Z[28]), .CK(clk), .RN(n7952), .Q(n8276)
);
DFFRXLTS R_1090 ( .D(FPSENCOS_d_ff2_Z[10]), .CK(clk), .RN(n7972), .Q(n8274)
);
DFFRXLTS R_1092 ( .D(FPSENCOS_d_ff3_sh_y_out[7]), .CK(clk), .RN(n7978), .Q(
n8273) );
DFFRXLTS R_1094 ( .D(FPSENCOS_d_ff3_sh_x_out[7]), .CK(clk), .RN(n7978), .Q(
n8272) );
DFFRXLTS R_1102 ( .D(FPSENCOS_d_ff2_Z[23]), .CK(clk), .RN(n7955), .Q(n8268)
);
DFFRXLTS R_1118 ( .D(FPSENCOS_d_ff2_Z[17]), .CK(clk), .RN(n8548), .Q(n8260)
);
DFFRXLTS R_1124 ( .D(FPSENCOS_d_ff3_sh_y_out[16]), .CK(clk), .RN(n7968), .Q(
n8257) );
DFFRXLTS R_1126 ( .D(FPSENCOS_d_ff3_sh_x_out[16]), .CK(clk), .RN(n7968), .Q(
n8256) );
DFFRXLTS R_1130 ( .D(FPSENCOS_d_ff2_Z[19]), .CK(clk), .RN(n8529), .Q(n8254)
);
DFFRXLTS R_1138 ( .D(FPSENCOS_d_ff2_Z[30]), .CK(clk), .RN(n7952), .Q(n8250)
);
DFFRXLTS R_1144 ( .D(FPSENCOS_d_ff2_X[25]), .CK(clk), .RN(n2369), .Q(n8247)
);
DFFRXLTS R_1148 ( .D(FPSENCOS_d_ff3_sh_y_out[17]), .CK(clk), .RN(n8547), .Q(
n8245) );
DFFRXLTS R_1150 ( .D(FPSENCOS_d_ff3_sh_x_out[17]), .CK(clk), .RN(n8529), .Q(
n8244) );
DFFRXLTS R_1159 ( .D(FPSENCOS_d_ff2_X[24]), .CK(clk), .RN(n2370), .Q(n8241)
);
DFFRXLTS R_1161 ( .D(FPSENCOS_d_ff2_Z[24]), .CK(clk), .RN(n8548), .Q(n8240)
);
DFFRXLTS R_1181 ( .D(FPSENCOS_d_ff2_Z[15]), .CK(clk), .RN(n8528), .Q(n8230)
);
DFFRXLTS R_1193 ( .D(FPSENCOS_d_ff2_Z[29]), .CK(clk), .RN(n7952), .Q(n8224)
);
DFFRXLTS R_1201 ( .D(FPSENCOS_d_ff2_Z[14]), .CK(clk), .RN(n7972), .Q(n8220)
);
DFFRXLTS R_1211 ( .D(FPSENCOS_d_ff2_Z[27]), .CK(clk), .RN(n7952), .Q(n8216)
);
DFFRXLTS R_1213 ( .D(FPSENCOS_d_ff3_sh_y_out[10]), .CK(clk), .RN(n7971), .Q(
n8215) );
DFFRXLTS R_1215 ( .D(FPSENCOS_d_ff3_LUT_out[10]), .CK(clk), .RN(n7971), .Q(
n8214) );
DFFRXLTS R_1219 ( .D(FPSENCOS_d_ff2_Z[11]), .CK(clk), .RN(n7971), .Q(n8212)
);
DFFRXLTS R_1221 ( .D(FPSENCOS_d_ff3_sh_y_out[4]), .CK(clk), .RN(n7964), .Q(
n8211) );
DFFRXLTS R_1223 ( .D(FPSENCOS_d_ff3_LUT_out[4]), .CK(clk), .RN(n7964), .Q(
n8210) );
DFFRXLTS R_1227 ( .D(FPSENCOS_d_ff2_Z[26]), .CK(clk), .RN(n8548), .Q(n8208)
);
DFFRXLTS R_1231 ( .D(FPSENCOS_d_ff2_Z[16]), .CK(clk), .RN(n7967), .Q(n8206)
);
DFFRXLTS R_1233 ( .D(FPSENCOS_d_ff3_sh_y_out[8]), .CK(clk), .RN(n7967), .Q(
n8205) );
DFFRXLTS R_1235 ( .D(FPSENCOS_d_ff3_LUT_out[8]), .CK(clk), .RN(n7967), .Q(
n8204) );
DFFRXLTS R_1237 ( .D(FPSENCOS_d_ff3_sh_y_out[6]), .CK(clk), .RN(n7964), .Q(
n8203) );
DFFRXLTS R_1239 ( .D(FPSENCOS_d_ff3_LUT_out[6]), .CK(clk), .RN(n7964), .Q(
n8202) );
DFFRXLTS R_1248 ( .D(FPSENCOS_d_ff2_Z[9]), .CK(clk), .RN(n7982), .Q(n8200)
);
DFFRXLTS R_1252 ( .D(FPSENCOS_d_ff2_Z[5]), .CK(clk), .RN(n7982), .Q(n8198)
);
DFFRXLTS R_1258 ( .D(FPSENCOS_d_ff2_Z[7]), .CK(clk), .RN(n7978), .Q(n8196)
);
DFFRXLTS R_1267 ( .D(FPSENCOS_d_ff2_Z[4]), .CK(clk), .RN(n7964), .Q(n8192)
);
DFFRXLTS R_1279 ( .D(FPSENCOS_d_ff2_Z[2]), .CK(clk), .RN(n7977), .Q(n8186)
);
DFFRXLTS R_1281 ( .D(FPSENCOS_d_ff3_sh_y_out[23]), .CK(clk), .RN(n8532), .Q(
n8185) );
DFFRXLTS R_1283 ( .D(FPSENCOS_d_ff3_LUT_out[23]), .CK(clk), .RN(n8532), .Q(
n8184) );
DFFRXLTS R_1287 ( .D(FPSENCOS_d_ff2_Z[3]), .CK(clk), .RN(n7975), .Q(n8182)
);
DFFRXLTS R_1295 ( .D(FPSENCOS_d_ff2_Z[6]), .CK(clk), .RN(n7964), .Q(n8178)
);
DFFRXLTS R_1305 ( .D(FPSENCOS_d_ff3_sh_y_out[24]), .CK(clk), .RN(n2418), .Q(
n8173) );
DFFRXLTS R_1313 ( .D(FPSENCOS_d_ff3_sh_y_out[20]), .CK(clk), .RN(n7960), .Q(
n8169) );
DFFRXLTS R_1315 ( .D(FPSENCOS_d_ff3_sh_x_out[20]), .CK(clk), .RN(n7960), .Q(
n8168) );
DFFRXLTS R_1322 ( .D(FPSENCOS_d_ff3_sh_y_out[19]), .CK(clk), .RN(n7960), .Q(
n8165) );
DFFRXLTS R_1324 ( .D(FPSENCOS_d_ff3_sh_x_out[19]), .CK(clk), .RN(n7960), .Q(
n8164) );
DFFRXLTS R_1326 ( .D(FPSENCOS_d_ff3_sh_y_out[22]), .CK(clk), .RN(n8547), .Q(
n8163) );
DFFRXLTS R_1336 ( .D(FPSENCOS_d_ff3_sh_y_out[30]), .CK(clk), .RN(n8529), .Q(
n8161) );
DFFRXLTS R_1338 ( .D(Data_2[30]), .CK(clk), .RN(n7957), .Q(n8160) );
DFFRXLTS R_1342 ( .D(FPSENCOS_d_ff3_sh_y_out[31]), .CK(clk), .RN(n7975), .Q(
n8159) );
DFFRXLTS R_1344 ( .D(Data_2[31]), .CK(clk), .RN(n7975), .Q(n8158) );
DFFRXLTS R_1346 ( .D(FPSENCOS_d_ff3_sh_y_out[28]), .CK(clk), .RN(n7956), .Q(
n8157) );
DFFRXLTS R_1348 ( .D(FPSENCOS_d_ff3_sh_x_out[28]), .CK(clk), .RN(n7956), .Q(
n8156) );
DFFRXLTS R_1350 ( .D(FPSENCOS_d_ff3_sh_y_out[29]), .CK(clk), .RN(n7956), .Q(
n8155) );
DFFRXLTS R_1352 ( .D(FPSENCOS_d_ff3_sh_x_out[29]), .CK(clk), .RN(n7956), .Q(
n8154) );
DFFRXLTS R_1389 ( .D(FPSENCOS_d_ff3_LUT_out[19]), .CK(clk), .RN(n7956), .Q(
n8146) );
DFFSX1TS R_510_RW_0 ( .D(n8716), .CK(clk), .SN(n7989), .Q(n8429) );
DFFSX1TS R_516_RW_0 ( .D(n8741), .CK(clk), .SN(n7989), .Q(n8427) );
DFFSX1TS R_523_RW_0 ( .D(n8738), .CK(clk), .SN(n7989), .Q(n8424) );
DFFSX1TS R_530_RW_0 ( .D(n8745), .CK(clk), .SN(n7989), .Q(n8422) );
DFFSX1TS R_537_RW_0 ( .D(n8751), .CK(clk), .SN(n7989), .Q(n8420) );
DFFSX1TS R_362_RW_0 ( .D(n8722), .CK(clk), .SN(n7990), .Q(n8468) );
DFFSX1TS R_375_RW_0 ( .D(n8731), .CK(clk), .SN(n7990), .Q(n8460) );
DFFSX1TS R_391_RW_0 ( .D(n8728), .CK(clk), .SN(n7990), .Q(n8454) );
DFFSX1TS R_403_RW_0 ( .D(n8719), .CK(clk), .SN(n7990), .Q(n8451) );
DFFSX1TS R_473_RW_0 ( .D(n8737), .CK(clk), .SN(n7989), .Q(n8444) );
DFFSX1TS R_477_RW_0 ( .D(n8734), .CK(clk), .SN(n7989), .Q(n8442) );
DFFSX1TS R_489_RW_0 ( .D(n8743), .CK(clk), .SN(n7989), .Q(n8436) );
DFFSX1TS R_496_RW_0 ( .D(n8740), .CK(clk), .SN(n7989), .Q(n8434) );
DFFSX1TS R_500_RW_0 ( .D(n8747), .CK(clk), .SN(n7990), .Q(n8432) );
DFFRXLTS R_1414 ( .D(n1580), .CK(clk), .RN(n2425), .Q(n8144) );
DFFSX1TS R_1451 ( .D(n8808), .CK(clk), .SN(n2390), .Q(n8136) );
DFFSX1TS R_1468 ( .D(n8806), .CK(clk), .SN(n7985), .Q(n8131) );
DFFSX1TS R_1517 ( .D(n8807), .CK(clk), .SN(n7966), .Q(n8117) );
DFFSX1TS R_1538 ( .D(n8836), .CK(clk), .SN(n7990), .Q(n8111) );
DFFSX1TS R_1541 ( .D(n8812), .CK(clk), .SN(n2390), .Q(n8110) );
DFFSX1TS R_1562 ( .D(n8811), .CK(clk), .SN(n2390), .Q(n8104) );
DFFSX1TS R_1571 ( .D(n8809), .CK(clk), .SN(n2390), .Q(n8101) );
DFFSX1TS R_1599 ( .D(n8814), .CK(clk), .SN(n2390), .Q(n8094) );
DFFSX1TS R_1643 ( .D(n8833), .CK(clk), .SN(n7990), .Q(n8080) );
DFFRXLTS R_1664 ( .D(n1813), .CK(clk), .RN(n7977), .Q(n8073) );
DFFRXLTS R_1668 ( .D(n1579), .CK(clk), .RN(n2426), .Q(n8071) );
DFFRXLTS R_1684 ( .D(n1811), .CK(clk), .RN(n7977), .Q(n8068) );
DFFSX1TS R_1701 ( .D(n8064), .CK(clk), .SN(n2394), .Q(n8632) );
DFFRXLTS R_1702 ( .D(n8063), .CK(clk), .RN(n2418), .Q(n8645) );
DFFSX1TS R_1716 ( .D(n8061), .CK(clk), .SN(n8593), .Q(n8639) );
DFFRX1TS R_1743 ( .D(n8747), .CK(clk), .RN(n7956), .Q(n8055) );
DFFRX1TS R_1744 ( .D(n8743), .CK(clk), .RN(n7960), .Q(n8054) );
DFFRX1TS R_1745 ( .D(n8740), .CK(clk), .RN(n7982), .Q(n8053) );
DFFRX1TS R_1746 ( .D(n8737), .CK(clk), .RN(n7971), .Q(n8052) );
DFFRX1TS R_1747 ( .D(n8734), .CK(clk), .RN(n7971), .Q(n8051) );
DFFRX1TS R_1749 ( .D(n8728), .CK(clk), .RN(n7967), .Q(n8049) );
DFFRX1TS R_1750 ( .D(n8722), .CK(clk), .RN(n7959), .Q(n8048) );
DFFRX1TS R_1751 ( .D(n8719), .CK(clk), .RN(n7977), .Q(n8047) );
DFFRX1TS R_1753 ( .D(n8725), .CK(clk), .RN(n6352), .Q(n8045) );
DFFSX1TS R_1756 ( .D(n8524), .CK(clk), .SN(n2425), .Q(n8044) );
DFFSX1TS R_1757 ( .D(n7827), .CK(clk), .SN(n2420), .Q(n8043) );
DFFSX1TS R_1765 ( .D(n8813), .CK(clk), .SN(n2390), .Q(n8036) );
DFFSX1TS R_1766 ( .D(n8815), .CK(clk), .SN(n2390), .Q(n8035) );
DFFRX1TS R_1774 ( .D(n8751), .CK(clk), .RN(n7987), .Q(n8027) );
DFFRX1TS R_1782 ( .D(n8714), .CK(clk), .RN(n7977), .Q(n8019) );
DFFRX1TS R_1783 ( .D(n6864), .CK(clk), .RN(n7984), .Q(n8018) );
DFFRX1TS R_1785 ( .D(n8750), .CK(clk), .RN(n7987), .Q(n8016) );
DFFSX1TS R_1787 ( .D(n5914), .CK(clk), .SN(n2390), .Q(n8014) );
DFFSX1TS R_1788 ( .D(n6009), .CK(clk), .SN(n2422), .Q(n8013) );
DFFSX1TS R_1797 ( .D(n8837), .CK(clk), .SN(n7989), .Q(n8004) );
DFFRX1TS R_1806 ( .D(gt_x_74_B_23_), .CK(clk), .RN(n7984), .Q(n7996) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n8598), .Q(
FPMULT_FSM_selector_C), .QN(n7811) );
DFFRXLTS add_x_246_R_570 ( .D(n1517), .CK(clk), .RN(n2391), .Q(
add_x_246_A_0_), .QN(n7786) );
DFFSX1TS add_x_246_R_1706 ( .D(n7785), .CK(clk), .SN(n2392), .Q(
FPMULT_Adder_M_result_A_adder[4]) );
DFFRXLTS add_x_246_R_1486 ( .D(n7784), .CK(clk), .RN(n2391), .Q(
FPMULT_Adder_M_result_A_adder[5]) );
DFFRXLTS add_x_246_R_677 ( .D(n7782), .CK(clk), .RN(n2391), .Q(
FPMULT_Adder_M_result_A_adder[3]) );
DFFRX1TS add_x_246_R_569 ( .D(n1518), .CK(clk), .RN(n2391), .Q(
add_x_246_A_1_) );
DFFRXLTS add_x_246_R_568 ( .D(n1519), .CK(clk), .RN(n2391), .Q(
add_x_246_A_2_) );
DFFSX1TS add_x_69_R_1823 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(n7776), .Q(n7773) );
DFFSX1TS add_x_69_R_1822 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(n7776), .Q(n7772) );
DFFSX1TS add_x_69_R_1821 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(n7776), .Q(n7771) );
DFFSX1TS add_x_69_R_1820 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CK(
clk), .SN(n7776), .Q(n7770) );
DFFSX1TS add_x_69_R_1819 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CK(
clk), .SN(n7776), .Q(n7769) );
DFFRX1TS add_x_69_R_1815 ( .D(n3171), .CK(clk), .RN(n7779), .Q(n7765) );
DFFRX1TS add_x_69_R_1814 ( .D(n5723), .CK(clk), .RN(n7778), .Q(n7764) );
DFFRX1TS add_x_69_R_1813 ( .D(add_x_69_n94), .CK(clk), .RN(n7778), .Q(n7763)
);
DFFSX1TS add_x_69_R_1812 ( .D(add_x_69_n85), .CK(clk), .SN(n7778), .Q(n7762)
);
DFFRX1TS add_x_69_R_1809 ( .D(add_x_69_n57), .CK(clk), .RN(n7778), .Q(n7760)
);
DFFSX1TS add_x_69_R_1654 ( .D(add_x_69_n272), .CK(clk), .SN(n8590), .Q(n7753) );
DFFRXLTS add_x_69_R_1651 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .CK(clk), .RN(n7777), .Q(n7751) );
DFFSX1TS add_x_69_R_1507 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .CK(clk), .SN(n7777), .Q(n7749) );
DFFRXLTS add_x_69_R_1071 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
clk), .RN(n2425), .Q(n7747) );
DFFSX1TS add_x_69_R_1055 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
clk), .SN(n7778), .Q(n7746) );
DFFSX1TS add_x_69_R_57 ( .D(add_x_69_n113), .CK(clk), .SN(n7778), .Q(n7742)
);
DFFRXLTS add_x_69_R_51 ( .D(n4902), .CK(clk), .RN(n7779), .Q(n7741) );
DFFRXLTS add_x_69_R_47 ( .D(n5300), .CK(clk), .RN(n7779), .Q(n7739) );
DFFRXLTS add_x_69_R_45 ( .D(add_x_69_n69), .CK(clk), .RN(n7779), .Q(n7738)
);
DFFRXLTS add_x_69_R_43 ( .D(add_x_69_n51), .CK(clk), .RN(n7779), .Q(n7737)
);
DFFRXLTS add_x_69_R_41 ( .D(n5596), .CK(clk), .RN(n7779), .Q(n7736) );
DFFRXLTS add_x_69_R_39 ( .D(n5443), .CK(clk), .RN(n7779), .Q(n7735) );
DFFRXLTS add_x_69_R_37 ( .D(n3149), .CK(clk), .RN(n2426), .Q(n7734) );
DFFRXLTS DP_OP_497J211_123_1725_R_691 ( .D(n1671), .CK(clk), .RN(n2394), .Q(
DP_OP_497J211_123_1725_n791) );
DFFRX1TS DP_OP_498J211_124_1725_R_283 ( .D(n1630), .CK(clk), .RN(n2384), .Q(
DP_OP_498J211_124_1725_n791) );
DFFRX2TS DP_OP_498J211_124_1725_R_278 ( .D(n1637), .CK(clk), .RN(n7995), .Q(
DP_OP_498J211_124_1725_n786) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS DP_OP_498J211_124_1725_R_607 ( .D(n7692), .CK(clk), .RN(n7995), .Q(
DP_OP_498J211_124_1725_n718) );
DFFRX1TS DP_OP_497J211_123_1725_R_680 ( .D(n7703), .CK(clk), .RN(n2417), .Q(
DP_OP_497J211_123_1725_n669) );
DFFSX2TS DP_OP_496J211_122_3540_R_1712 ( .D(n7723), .CK(clk), .SN(n7994),
.Q(DP_OP_496J211_122_3540_n1193) );
DFFSX1TS R_989 ( .D(n8415), .CK(clk), .SN(n2419), .QN(n7857) );
DFFRHQX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n2347), .Q(result_add_subt[22]) );
DFFRX2TS DP_OP_496J211_122_3540_R_1709_IP ( .D(n3148), .CK(clk), .RN(n2492),
.Q(n7729), .QN(DP_OP_496J211_122_3540_n1102) );
DFFRXLTS DP_OP_496J211_122_3540_R_1710_IP ( .D(n7668), .CK(clk), .RN(n2494),
.Q(n7732) );
DFFRHQX1TS DP_OP_498J211_124_1725_R_1046 ( .D(n1631), .CK(clk), .RN(n2492),
.Q(DP_OP_498J211_124_1725_n792) );
DFFSHQX1TS DP_OP_498J211_124_1725_R_1715 ( .D(n7697), .CK(clk), .SN(n2493),
.Q(DP_OP_498J211_124_1725_n362) );
DFFSHQX1TS DP_OP_498J211_124_1725_R_610 ( .D(n7691), .CK(clk), .SN(n2492),
.Q(n7688) );
DFFRHQX2TS R_842 ( .D(n1667), .CK(clk), .RN(n2494), .Q(
DP_OP_496J211_122_3540_n1514) );
DFFRX1TS DP_OP_498J211_124_1725_R_1044 ( .D(n7695), .CK(clk), .RN(n2493),
.Q(DP_OP_498J211_124_1725_n631) );
DFFRHQX1TS DP_OP_497J211_123_1725_R_856_IP ( .D(n3160), .CK(clk), .RN(n2494),
.Q(n7673) );
DFFRXLTS R_1195 ( .D(FPSENCOS_d_ff3_sh_y_out[9]), .CK(clk), .RN(n7982), .Q(
n8223) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n2418), .Q(result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n2418), .Q(result_add_subt[23]), .QN(n7859) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n2369), .Q(FPADDSUB_left_right_SHT2), .QN(n2344) );
DFFSX1TS add_x_69_R_1817 ( .D(add_x_69_n201), .CK(clk), .SN(n7776), .Q(n7767) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n7814) );
DFFSX1TS add_x_69_R_1758 ( .D(add_x_69_n198), .CK(clk), .SN(n7776), .Q(n7756), .QN(n7757) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n2369), .Q(result_add_subt[21]), .QN(n7830) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n2369), .Q(result_add_subt[19]), .QN(n7831) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n2369), .Q(result_add_subt[20]), .QN(n7832) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n2369), .Q(result_add_subt[17]), .QN(n7833) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n2369), .Q(result_add_subt[4]), .QN(n7834) );
DFFSRX2TS add_x_246_R_1485 ( .D(n7783), .CK(clk), .SN(1'b1), .RN(n2493), .Q(
add_x_246_n19) );
DFFSX4TS DP_OP_496J211_122_3540_R_427 ( .D(n7711), .CK(clk), .SN(n7726), .Q(
DP_OP_496J211_122_3540_n1103) );
DFFRX2TS DP_OP_496J211_122_3540_R_293 ( .D(n1677), .CK(clk), .RN(n7726), .Q(
DP_OP_496J211_122_3540_n1499) );
DFFRHQX2TS DP_OP_496J211_122_3540_R_1001 ( .D(n7718), .CK(clk), .RN(n7726),
.Q(n2270) );
DFFRX4TS R_276 ( .D(n1637), .CK(clk), .RN(n7993), .Q(FPMULT_Op_MY[10]), .QN(
n8417) );
DFFSX2TS R_1828 ( .D(n6040), .CK(clk), .SN(n7962), .Q(n2256) );
DFFSX2TS R_1829 ( .D(n7787), .CK(clk), .SN(n7959), .Q(n2255) );
DFFSX2TS R_1830 ( .D(n8609), .CK(clk), .SN(n2388), .Q(n2254) );
DFFSX2TS R_1831 ( .D(n8607), .CK(clk), .SN(n2390), .Q(n2253), .QN(n2252) );
DFFRXLTS R_1132 ( .D(FPSENCOS_d_ff2_X[21]), .CK(clk), .RN(n8547), .Q(n8253)
);
DFFRXLTS R_1134 ( .D(FPSENCOS_d_ff2_Z[21]), .CK(clk), .RN(n8548), .Q(n8252)
);
DFFRXLTS R_1175 ( .D(FPSENCOS_d_ff2_X[22]), .CK(clk), .RN(n8528), .Q(n8233)
);
DFFRXLTS R_1177 ( .D(FPSENCOS_d_ff2_Z[22]), .CK(clk), .RN(n8532), .Q(n8232)
);
DFFRXLTS R_1120 ( .D(FPSENCOS_d_ff2_X[20]), .CK(clk), .RN(n8528), .Q(n8259)
);
DFFRXLTS R_1122 ( .D(FPSENCOS_d_ff2_Z[20]), .CK(clk), .RN(n7961), .Q(n8258)
);
DFFRXLTS R_1146 ( .D(FPSENCOS_d_ff2_Z[25]), .CK(clk), .RN(n8547), .Q(n8246)
);
DFFRXLTS R_1100 ( .D(FPSENCOS_d_ff2_X[23]), .CK(clk), .RN(n8538), .Q(n8269)
);
DFFRXLTS R_1309 ( .D(FPSENCOS_d_ff3_sh_y_out[18]), .CK(clk), .RN(n8528), .Q(
n8171) );
DFFRXLTS R_1311 ( .D(FPSENCOS_d_ff3_sh_x_out[18]), .CK(clk), .RN(n7960), .Q(
n8170) );
DFFRXLTS R_1289 ( .D(FPSENCOS_d_ff3_sh_y_out[21]), .CK(clk), .RN(n8547), .Q(
n8181) );
DFFRXLTS R_1291 ( .D(FPSENCOS_d_ff3_LUT_out[21]), .CK(clk), .RN(n7961), .Q(
n8180) );
DFFRXLTS R_1318 ( .D(FPSENCOS_d_ff3_sh_y_out[27]), .CK(clk), .RN(n7953), .Q(
n8167) );
DFFRXLTS R_1320 ( .D(FPSENCOS_d_ff3_sh_x_out[27]), .CK(clk), .RN(n8534), .Q(
n8166) );
DFFRXLTS R_1297 ( .D(FPSENCOS_d_ff3_sh_y_out[26]), .CK(clk), .RN(n7973), .Q(
n8177) );
DFFRXLTS R_1299 ( .D(FPSENCOS_d_ff3_LUT_out[26]), .CK(clk), .RN(n8537), .Q(
n8176) );
DFFRXLTS R_1307 ( .D(FPSENCOS_d_ff3_LUT_out[24]), .CK(clk), .RN(n6352), .Q(
n8172) );
DFFRXLTS R_1301 ( .D(FPSENCOS_d_ff3_sh_y_out[25]), .CK(clk), .RN(n8535), .Q(
n8175) );
DFFRXLTS R_1303 ( .D(FPSENCOS_d_ff3_LUT_out[25]), .CK(clk), .RN(n8539), .Q(
n8174) );
DFFSX2TS R_1833 ( .D(n6859), .CK(clk), .SN(n2470), .Q(n2250) );
DFFSX2TS R_1834 ( .D(n8636), .CK(clk), .SN(n7973), .Q(n2249) );
DFFRX2TS R_1835 ( .D(n6859), .CK(clk), .RN(n7991), .Q(n2248) );
DFFSX2TS R_1836 ( .D(n7787), .CK(clk), .SN(n7959), .Q(n2247) );
DFFRX2TS R_1837 ( .D(n5303), .CK(clk), .RN(n7779), .Q(n2246) );
DFFSX2TS DP_OP_498J211_124_1725_R_844_IP ( .D(n3140), .CK(clk), .SN(n2493),
.Q(n7699), .QN(n2227) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n8576), .Q(
dataB[25]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[24]), .QN(n8480) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[30]), .QN(n8337) );
DFFRXLTS add_x_69_R_1810 ( .D(n5717), .CK(clk), .RN(n7778), .Q(n7761) );
DFFRXLTS add_x_69_R_1808 ( .D(add_x_69_n47), .CK(clk), .RN(n7778), .Q(n7759)
);
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n2387), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n7950) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n2347), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n7941) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n7970),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n8530), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n7944) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n7980),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n2399), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n7949) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n2469),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n7953),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n7942) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n8538), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n7945) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n7970),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n7980), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n7943) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n7866) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n2347), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFSX2TS DP_OP_499J211_125_1651_R_1826 ( .D(n7686), .CK(clk), .SN(n2470),
.Q(n7683) );
CMPR32X2TS DP_OP_26J211_126_1325_U9 ( .A(n2449), .B(n7806), .C(
DP_OP_26J211_126_1325_n18), .CO(DP_OP_26J211_126_1325_n8), .S(
FPADDSUB_exp_rslt_NRM2_EW1[0]) );
DFFSX4TS R_1827 ( .D(n8605), .CK(clk), .SN(n7953), .Q(n2260), .QN(n2229) );
DFFRXLTS R_1217 ( .D(FPSENCOS_d_ff2_X[11]), .CK(clk), .RN(n7971), .Q(n8213)
);
DFFRXLTS R_1273 ( .D(FPSENCOS_d_ff2_X[1]), .CK(clk), .RN(n7981), .Q(n8189)
);
DFFRXLTS R_1269 ( .D(FPSENCOS_d_ff2_X[0]), .CK(clk), .RN(n7977), .Q(n8191)
);
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRXLTS R_1293 ( .D(FPSENCOS_d_ff2_X[6]), .CK(clk), .RN(n7964), .Q(n8179)
);
DFFRXLTS R_1265 ( .D(FPSENCOS_d_ff2_X[4]), .CK(clk), .RN(n7964), .Q(n8193)
);
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n8574),
.Q(n2196) );
DFFRXLTS R_1209 ( .D(FPSENCOS_d_ff2_X[27]), .CK(clk), .RN(n7952), .Q(n8217)
);
DFFRXLTS R_1191 ( .D(FPSENCOS_d_ff2_X[29]), .CK(clk), .RN(n7952), .Q(n8225)
);
DFFRX2TS R_1390 ( .D(n8749), .CK(clk), .RN(n7987), .Q(n2291), .QN(n3147) );
DFFRXLTS R_1225 ( .D(FPSENCOS_d_ff2_X[26]), .CK(clk), .RN(n7952), .Q(n8209)
);
DFFRXLTS R_1136 ( .D(FPSENCOS_d_ff2_X[30]), .CK(clk), .RN(n7952), .Q(n8251)
);
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n2421),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRXLTS R_557 ( .D(n1812), .CK(clk), .RN(n7977), .Q(n8419) );
DFFRXLTS R_494 ( .D(n1795), .CK(clk), .RN(n7964), .Q(n8435) );
DFFRXLTS R_514 ( .D(n1794), .CK(clk), .RN(n7956), .Q(n8428) );
CMPR32X2TS intadd_480_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n7809), .C(
intadd_480_CI), .CO(intadd_480_n3), .S(intadd_480_SUM_0_) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n7977), .Q(FPADDSUB_Data_array_SWR_3__25_), .QN(n2341) );
CMPR32X2TS intadd_480_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_479_B_1_),
.C(intadd_480_n3), .CO(intadd_480_n2), .S(intadd_480_SUM_1_) );
DFFRXLTS R_1152 ( .D(FPSENCOS_d_ff2_X[31]), .CK(clk), .RN(n7974), .Q(n8243)
);
DFFRXLTS R_1154 ( .D(FPSENCOS_d_ff2_Z[31]), .CK(clk), .RN(n7974), .Q(n8242)
);
CMPR32X2TS intadd_480_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n7790), .C(
intadd_480_n2), .CO(intadd_480_n1), .S(intadd_480_SUM_2_) );
DFFRX2TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n7974), .Q(FPADDSUB_intAS) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n2421), .Q(result_add_subt[29]), .QN(n7858) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n8530), .Q(result_add_subt[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n6353),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n8549),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n8536),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n6354),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
ADDHXLTS U2219 ( .A(add_x_246_A_5_), .B(n5796), .CO(n7783), .S(n7784) );
NAND2X1TS U2220 ( .A(n5669), .B(n5668), .Y(DP_OP_499J211_125_1651_n3) );
NOR2X1TS U2221 ( .A(n6833), .B(n8713), .Y(n8749) );
OR2X2TS U2222 ( .A(n8291), .B(n1333), .Y(n8292) );
INVX2TS U2223 ( .A(n7409), .Y(n7443) );
INVX2TS U2224 ( .A(n7409), .Y(n7427) );
INVX2TS U2225 ( .A(n7409), .Y(n7407) );
INVX2TS U2226 ( .A(n7337), .Y(n7333) );
INVX2TS U2227 ( .A(n7409), .Y(n7357) );
INVX2TS U2228 ( .A(n8611), .Y(n7412) );
INVX2TS U2229 ( .A(n7441), .Y(n7442) );
INVX2TS U2230 ( .A(n7488), .Y(n7482) );
INVX2TS U2231 ( .A(n7488), .Y(n7484) );
INVX2TS U2232 ( .A(n2407), .Y(n2408) );
BUFX3TS U2233 ( .A(n7385), .Y(n7396) );
BUFX3TS U2234 ( .A(n7385), .Y(n7404) );
BUFX3TS U2235 ( .A(n7374), .Y(n7429) );
INVX2TS U2236 ( .A(n6859), .Y(n8525) );
BUFX3TS U2237 ( .A(n8835), .Y(n7655) );
NOR2X1TS U2238 ( .A(n6833), .B(n7435), .Y(n8748) );
NOR2X1TS U2239 ( .A(n7435), .B(n6858), .Y(n8746) );
BUFX3TS U2240 ( .A(n6863), .Y(n8610) );
INVX2TS U2241 ( .A(n7364), .Y(n7354) );
BUFX3TS U2242 ( .A(n6863), .Y(n7633) );
INVX2TS U2243 ( .A(n5691), .Y(n5693) );
BUFX3TS U2244 ( .A(n8835), .Y(n7637) );
NOR2X1TS U2245 ( .A(n5717), .B(n5716), .Y(n5724) );
NAND2X2TS U2246 ( .A(n3127), .B(n5747), .Y(n5748) );
AOI222X1TS U2247 ( .A0(n6829), .A1(cordic_result[1]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n6825)
);
AOI222X1TS U2248 ( .A0(n6829), .A1(cordic_result[0]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n6818)
);
AOI222X1TS U2249 ( .A0(n6829), .A1(cordic_result[2]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n6830)
);
AOI222X1TS U2250 ( .A0(n6794), .A1(cordic_result[22]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n6782) );
AOI222X1TS U2251 ( .A0(n6794), .A1(cordic_result[28]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n6784) );
AOI222X1TS U2252 ( .A0(n6794), .A1(cordic_result[24]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n6786) );
AOI222X1TS U2253 ( .A0(n6827), .A1(cordic_result[6]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n6828)
);
AOI222X1TS U2254 ( .A0(n6827), .A1(cordic_result[3]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n6823)
);
AOI222X1TS U2255 ( .A0(n6827), .A1(cordic_result[7]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n6826)
);
AOI222X1TS U2256 ( .A0(n6827), .A1(cordic_result[5]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n6822)
);
AOI222X1TS U2257 ( .A0(n6802), .A1(cordic_result[21]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n6779) );
AOI222X1TS U2258 ( .A0(n6802), .A1(cordic_result[20]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n6797) );
AOI222X1TS U2259 ( .A0(n6827), .A1(cordic_result[4]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n6819)
);
AOI222X1TS U2260 ( .A0(n6827), .A1(cordic_result[8]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n6821)
);
AOI222X1TS U2261 ( .A0(n6827), .A1(cordic_result[9]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n6820)
);
INVX2TS U2262 ( .A(n6778), .Y(n6800) );
CLKBUFX3TS U2263 ( .A(n6734), .Y(n6753) );
INVX2TS U2264 ( .A(n6996), .Y(n7031) );
ADDHXLTS U2265 ( .A(add_x_246_A_3_), .B(n5797), .CO(n5795), .S(n7782) );
INVX2TS U2266 ( .A(n6859), .Y(n8524) );
NOR2X4TS U2267 ( .A(n5003), .B(n5002), .Y(add_x_69_n201) );
NAND2X2TS U2268 ( .A(n5641), .B(n5640), .Y(n5647) );
NAND2X1TS U2269 ( .A(n6215), .B(n6214), .Y(n6216) );
BUFX3TS U2270 ( .A(n7308), .Y(n7334) );
BUFX3TS U2271 ( .A(n7385), .Y(n7433) );
BUFX3TS U2272 ( .A(n7634), .Y(n7661) );
INVX2TS U2273 ( .A(n6989), .Y(n7598) );
CLKBUFX2TS U2274 ( .A(n7343), .Y(n7345) );
BUFX3TS U2275 ( .A(n7437), .Y(n7441) );
INVX2TS U2276 ( .A(n7425), .Y(n2407) );
INVX2TS U2277 ( .A(n7508), .Y(n7061) );
CLKBUFX2TS U2278 ( .A(n7634), .Y(n7665) );
INVX2TS U2279 ( .A(n5740), .Y(n3122) );
CLKBUFX2TS U2280 ( .A(n7486), .Y(n7488) );
BUFX3TS U2281 ( .A(n7364), .Y(n7409) );
BUFX3TS U2282 ( .A(n6623), .Y(n7294) );
BUFX3TS U2283 ( .A(n6624), .Y(n6714) );
BUFX3TS U2284 ( .A(n6623), .Y(n6715) );
CLKBUFX2TS U2285 ( .A(n6623), .Y(n7299) );
INVX2TS U2286 ( .A(n6840), .Y(n6641) );
INVX2TS U2287 ( .A(n6840), .Y(n6576) );
INVX6TS U2288 ( .A(n3184), .Y(n5743) );
INVX2TS U2289 ( .A(n6264), .Y(n6857) );
INVX2TS U2290 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n7634) );
OR3X1TS U2291 ( .A(n1519), .B(n1518), .C(n1517), .Y(n5797) );
INVX2TS U2292 ( .A(n5730), .Y(n5753) );
NAND2X1TS U2293 ( .A(n5532), .B(n5526), .Y(n5490) );
AOI211X2TS U2294 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n8526), .B0(
n7093), .C0(n6838), .Y(n6858) );
OR3X2TS U2295 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n7800), .Y(n7340) );
NAND2X1TS U2296 ( .A(n7084), .B(n7052), .Y(n6996) );
INVX2TS U2297 ( .A(n6721), .Y(n6778) );
CLKBUFX2TS U2298 ( .A(n6736), .Y(n6734) );
BUFX3TS U2299 ( .A(n6989), .Y(n7508) );
BUFX3TS U2300 ( .A(n6864), .Y(n7654) );
INVX2TS U2301 ( .A(add_x_69_n59), .Y(n5736) );
NAND2X6TS U2302 ( .A(n2522), .B(n2590), .Y(n5547) );
NOR2X1TS U2303 ( .A(n6647), .B(n7372), .Y(n6188) );
OAI2BB1X1TS U2304 ( .A0N(n2199), .A1N(n6613), .B0(n8517), .Y(n6892) );
AND2X2TS U2305 ( .A(n6602), .B(n6166), .Y(n7827) );
NAND2X2TS U2306 ( .A(n2670), .B(n2818), .Y(n2669) );
CLKBUFX2TS U2307 ( .A(n7408), .Y(n6759) );
BUFX3TS U2308 ( .A(n6730), .Y(n7425) );
BUFX3TS U2309 ( .A(n7426), .Y(n7413) );
NOR2X4TS U2310 ( .A(operation[1]), .B(n7372), .Y(n7385) );
OR4X2TS U2311 ( .A(n7489), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n7486) );
BUFX3TS U2312 ( .A(n6624), .Y(n7293) );
INVX2TS U2313 ( .A(n6264), .Y(n6838) );
NOR2XLTS U2314 ( .A(n6263), .B(n5453), .Y(n5454) );
INVX2TS U2315 ( .A(n7487), .Y(n7489) );
CLKINVX6TS U2316 ( .A(n5763), .Y(n5750) );
INVX2TS U2317 ( .A(n6840), .Y(n6882) );
INVX4TS U2318 ( .A(n5685), .Y(n2590) );
NAND4BBX1TS U2319 ( .AN(n6033), .BN(n6032), .C(n6031), .D(n6030), .Y(n6034)
);
NOR2BX2TS U2320 ( .AN(n6722), .B(n6829), .Y(n6723) );
INVX4TS U2321 ( .A(n2905), .Y(n5671) );
BUFX3TS U2322 ( .A(n6869), .Y(n7372) );
NOR2X4TS U2323 ( .A(n7855), .B(n7629), .Y(n6989) );
AOI2BB2X1TS U2324 ( .B0(n5902), .B1(n6031), .A0N(n5901), .A1N(n5900), .Y(
n6037) );
INVX2TS U2325 ( .A(n6730), .Y(n7408) );
INVX2TS U2326 ( .A(operation[1]), .Y(n6647) );
OAI2BB2XLTS U2327 ( .B0(n7577), .B1(n6025), .A0N(gt_x_74_A_23_), .A1N(n6024),
.Y(n6026) );
INVX2TS U2328 ( .A(n6211), .Y(n2671) );
NAND3X1TS U2329 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n6645),
.C(n7792), .Y(n7282) );
NAND2X6TS U2330 ( .A(n4998), .B(n4999), .Y(n5670) );
BUFX3TS U2331 ( .A(n6832), .Y(n6840) );
OAI222X1TS U2332 ( .A0(n2222), .A1(n8032), .B0(n8112), .B1(n8056), .C0(n8002), .C1(n2215), .Y(n7501) );
XNOR2X1TS U2333 ( .A(n5607), .B(n5606), .Y(n5639) );
BUFX3TS U2334 ( .A(n6581), .Y(n7301) );
NOR2X4TS U2335 ( .A(operation[1]), .B(n7287), .Y(n6624) );
CLKINVX3TS U2336 ( .A(n5759), .Y(n3125) );
INVX2TS U2337 ( .A(n6283), .Y(n6264) );
NAND2X4TS U2338 ( .A(n3029), .B(n2640), .Y(n3027) );
NAND2X2TS U2339 ( .A(n7243), .B(n6212), .Y(n2672) );
NAND2X2TS U2340 ( .A(n6731), .B(n7426), .Y(n6730) );
NAND2X2TS U2341 ( .A(n6854), .B(n6585), .Y(n6869) );
CLKBUFX2TS U2342 ( .A(n7485), .Y(n7487) );
BUFX3TS U2343 ( .A(n6829), .Y(n6794) );
INVX2TS U2344 ( .A(n5561), .Y(n5595) );
INVX6TS U2345 ( .A(n3029), .Y(n2602) );
NOR2X1TS U2346 ( .A(n5899), .B(n7403), .Y(n5900) );
NAND4X1TS U2347 ( .A(n7809), .B(n2360), .C(n7790), .D(intadd_479_B_1_), .Y(
n6731) );
AND2X2TS U2348 ( .A(n6618), .B(FPMULT_FS_Module_state_reg[3]), .Y(n7485) );
XNOR2X1TS U2349 ( .A(DP_OP_26J211_126_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n6806) );
NOR2X4TS U2350 ( .A(n7300), .B(n6719), .Y(n6829) );
NAND2X6TS U2351 ( .A(n2568), .B(n5726), .Y(n2567) );
INVX2TS U2352 ( .A(operation[2]), .Y(n7287) );
AO22X1TS U2353 ( .A0(operation[1]), .A1(n6039), .B0(begin_operation), .B1(
n7297), .Y(n6585) );
OR2X2TS U2354 ( .A(n6699), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n6832) );
AOI211X1TS U2355 ( .A0(n7816), .A1(n6057), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n6669), .Y(n6058) );
NOR2X1TS U2356 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2350), .Y(n5708) );
INVX4TS U2357 ( .A(n5326), .Y(n2506) );
OA22X1TS U2358 ( .A0(n5996), .A1(n7393), .B0(n6024), .B1(gt_x_74_A_23_), .Y(
n6029) );
NOR2X1TS U2359 ( .A(n7302), .B(n6439), .Y(n6719) );
NAND2XLTS U2360 ( .A(n7286), .B(n7285), .Y(n6039) );
NOR3X1TS U2361 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n7813),
.C(n6646), .Y(n6190) );
NOR2X4TS U2362 ( .A(n5482), .B(n5481), .Y(n6248) );
NAND2X6TS U2363 ( .A(n5726), .B(n5725), .Y(n3029) );
NOR2X1TS U2364 ( .A(n5898), .B(n7401), .Y(n5895) );
NAND2X2TS U2365 ( .A(n5150), .B(n5149), .Y(n7240) );
OAI222X1TS U2366 ( .A0(n2219), .A1(n8030), .B0(n8106), .B1(n8056), .C0(n8008), .C1(n2214), .Y(n6435) );
NAND3BX1TS U2367 ( .AN(n6547), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n6546), .Y(n6548) );
BUFX3TS U2368 ( .A(n6581), .Y(n6699) );
OR2X6TS U2369 ( .A(n2980), .B(n4896), .Y(n5726) );
NAND2X4TS U2370 ( .A(n2980), .B(n4896), .Y(n5725) );
INVX2TS U2371 ( .A(n2286), .Y(n5483) );
NOR3X1TS U2372 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n6546) );
BUFX3TS U2373 ( .A(n3179), .Y(n7196) );
CLKBUFX2TS U2374 ( .A(n5774), .Y(n2380) );
NAND3X1TS U2375 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n5813),
.C(n5815), .Y(n6718) );
NOR2X2TS U2376 ( .A(n7794), .B(FPMULT_FS_Module_state_reg[2]), .Y(n6602) );
NOR2X1TS U2377 ( .A(n6016), .B(n7388), .Y(n6014) );
OAI21X1TS U2378 ( .A0(n4900), .A1(n4899), .B0(n4897), .Y(n4898) );
INVX2TS U2379 ( .A(n2359), .Y(n6581) );
NAND2X2TS U2380 ( .A(n2984), .B(n5539), .Y(n2652) );
OAI21X2TS U2381 ( .A0(n7231), .A1(n7228), .B0(n7232), .Y(n5147) );
NAND2BX2TS U2382 ( .AN(n5721), .B(n5444), .Y(n2504) );
CLKBUFX2TS U2383 ( .A(n6494), .Y(n6606) );
NOR2X1TS U2384 ( .A(n5878), .B(n7397), .Y(n6032) );
NOR2X2TS U2385 ( .A(n7229), .B(n7231), .Y(n5148) );
NAND3X1TS U2386 ( .A(FPSENCOS_cont_iter_out[1]), .B(n7303), .C(n6632), .Y(
n6439) );
NAND2BX1TS U2387 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n6189),
.Y(n6646) );
OR2X6TS U2388 ( .A(n4894), .B(n4895), .Y(n2282) );
AND2X6TS U2389 ( .A(n4899), .B(n2301), .Y(n7231) );
NAND2X1TS U2390 ( .A(n5138), .B(n5137), .Y(n7219) );
NAND2X1TS U2391 ( .A(n2736), .B(n5460), .Y(n2733) );
BUFX3TS U2392 ( .A(n5059), .Y(n5149) );
INVX2TS U2393 ( .A(n5721), .Y(n5443) );
NAND2X1TS U2394 ( .A(n7214), .B(n5136), .Y(n7221) );
OAI2BB2XLTS U2395 ( .B0(n7617), .B1(n5933), .A0N(n7369), .A1N(n5932), .Y(
n5939) );
NAND2X2TS U2396 ( .A(n5428), .B(n5427), .Y(n5564) );
CLKBUFX2TS U2397 ( .A(n6202), .Y(n6609) );
NAND2X1TS U2398 ( .A(n6507), .B(n6905), .Y(n5769) );
INVX2TS U2399 ( .A(n7379), .Y(n5914) );
INVX2TS U2400 ( .A(n3133), .Y(n5444) );
OR2X4TS U2401 ( .A(n4899), .B(n2301), .Y(n7232) );
NAND2X2TS U2402 ( .A(n3189), .B(n5460), .Y(n5462) );
NOR2BX1TS U2403 ( .AN(n6038), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n6645) );
OAI21X1TS U2404 ( .A0(n5358), .A1(n5373), .B0(n5375), .Y(n5363) );
INVX2TS U2405 ( .A(n2358), .Y(n2359) );
INVX2TS U2406 ( .A(n5354), .Y(n2988) );
CMPR32X2TS U2407 ( .A(n6976), .B(n6984), .C(n6975), .CO(n6972), .S(n7094) );
INVX2TS U2408 ( .A(n5353), .Y(n2989) );
NOR2X1TS U2409 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n6547),
.Y(n6038) );
INVX4TS U2410 ( .A(n2793), .Y(n5303) );
NOR2X1TS U2411 ( .A(n5376), .B(n5373), .Y(n5379) );
CLKINVX2TS U2412 ( .A(n3120), .Y(n3082) );
NAND3X4TS U2413 ( .A(n2897), .B(n2889), .C(n5331), .Y(n2896) );
NAND2X6TS U2414 ( .A(n2897), .B(n5330), .Y(n2895) );
NAND2BX2TS U2415 ( .AN(n5329), .B(n5327), .Y(n2690) );
NAND2X2TS U2416 ( .A(n2235), .B(n5328), .Y(n5294) );
AND2X2TS U2417 ( .A(n5766), .B(n2350), .Y(n6507) );
NAND2BX2TS U2418 ( .AN(n5816), .B(n6189), .Y(n7302) );
XNOR2X1TS U2419 ( .A(n5141), .B(n5140), .Y(n5146) );
INVX2TS U2420 ( .A(n6988), .Y(n2358) );
CLKBUFX2TS U2421 ( .A(n8074), .Y(n7447) );
INVX2TS U2422 ( .A(n4899), .Y(n2642) );
NAND2X1TS U2423 ( .A(n5314), .B(n5313), .Y(n5315) );
NOR2BX2TS U2424 ( .AN(n5815), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n6189) );
INVX3TS U2425 ( .A(n2280), .Y(n2890) );
NAND2X4TS U2426 ( .A(n3130), .B(n3129), .Y(n4900) );
AOI21X2TS U2427 ( .A0(n3135), .A1(n5311), .B0(n5310), .Y(n5316) );
BUFX3TS U2428 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n6988) );
NOR2BX1TS U2429 ( .AN(n6358), .B(n6263), .Y(n5767) );
NAND2X4TS U2430 ( .A(n5271), .B(n5270), .Y(n5327) );
INVX2TS U2431 ( .A(n4684), .Y(n3026) );
NAND2X2TS U2432 ( .A(n5235), .B(n5234), .Y(n5320) );
INVX2TS U2433 ( .A(n5197), .Y(n5318) );
NAND2X1TS U2434 ( .A(n5062), .B(n5061), .Y(n5064) );
NAND2X6TS U2435 ( .A(n2951), .B(n3117), .Y(n5330) );
NOR2X6TS U2436 ( .A(n5384), .B(n5464), .Y(n2833) );
INVX4TS U2437 ( .A(n2702), .Y(n2235) );
NOR2X1TS U2438 ( .A(n6307), .B(n6319), .Y(n6219) );
NOR2X1TS U2439 ( .A(n5278), .B(n5279), .Y(n5288) );
NAND2X1TS U2440 ( .A(n5279), .B(n5278), .Y(n5287) );
NAND3X2TS U2441 ( .A(n4946), .B(n4945), .C(n5234), .Y(n3117) );
INVX1TS U2442 ( .A(n2229), .Y(n2257) );
NOR2X4TS U2443 ( .A(n5317), .B(n5197), .Y(n2581) );
NOR2X1TS U2444 ( .A(n5396), .B(n5399), .Y(n5554) );
NAND2X4TS U2445 ( .A(n2982), .B(n5491), .Y(n2572) );
NAND2X1TS U2446 ( .A(n5934), .B(n8284), .Y(n5992) );
NAND2X2TS U2447 ( .A(n2233), .B(n5010), .Y(n2676) );
BUFX3TS U2448 ( .A(n2256), .Y(n5998) );
NOR2X2TS U2449 ( .A(n6064), .B(n2489), .Y(n6059) );
INVX2TS U2450 ( .A(n2260), .Y(n2203) );
AO21X1TS U2451 ( .A0(n5338), .A1(n2237), .B0(n2511), .Y(n5423) );
INVX2TS U2452 ( .A(n5137), .Y(n4682) );
CLKBUFX2TS U2453 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2489) );
NAND2X4TS U2454 ( .A(n4885), .B(n4884), .Y(n5491) );
NAND2X4TS U2455 ( .A(n2524), .B(n3070), .Y(n2501) );
NAND2BX2TS U2456 ( .AN(n5339), .B(n5262), .Y(n5422) );
BUFX4TS U2457 ( .A(n2256), .Y(n6872) );
NAND2X2TS U2458 ( .A(n5051), .B(n5094), .Y(n5052) );
INVX3TS U2459 ( .A(n5283), .Y(n3102) );
INVX6TS U2460 ( .A(n2619), .Y(n5317) );
XNOR2X2TS U2461 ( .A(n5369), .B(n5368), .Y(n5466) );
INVX3TS U2462 ( .A(n5008), .Y(n2233) );
INVX6TS U2463 ( .A(n5092), .Y(n5051) );
CLKINVX2TS U2464 ( .A(n5011), .Y(n4993) );
NOR2X4TS U2465 ( .A(n3089), .B(n2745), .Y(n2744) );
NAND2X4TS U2466 ( .A(n3016), .B(n4636), .Y(n3019) );
INVX3TS U2467 ( .A(n5718), .Y(n2503) );
XNOR2X1TS U2468 ( .A(n5570), .B(n5345), .Y(n5417) );
INVX4TS U2469 ( .A(n4996), .Y(n5311) );
CLKXOR2X4TS U2470 ( .A(n2329), .B(n3720), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
OAI2BB1X2TS U2471 ( .A0N(n5193), .A1N(n5192), .B0(n2648), .Y(n5215) );
NAND2X4TS U2472 ( .A(n3689), .B(n3688), .Y(n5309) );
NAND2X4TS U2473 ( .A(n2588), .B(n4905), .Y(n2526) );
ADDHX1TS U2474 ( .A(FPMULT_Sgf_normalized_result[6]), .B(add_x_246_n19),
.CO(n6937), .S(n6940) );
ADDFX2TS U2475 ( .A(n5349), .B(n5348), .CI(n5347), .CO(n5413), .S(n5337) );
NOR2X4TS U2476 ( .A(n2263), .B(n5050), .Y(n5092) );
NAND2X4TS U2477 ( .A(n4086), .B(n4085), .Y(n4905) );
NOR2X1TS U2478 ( .A(n5114), .B(n5111), .Y(n5117) );
NAND2X4TS U2479 ( .A(n4571), .B(n4570), .Y(n5010) );
CLKXOR2X2TS U2480 ( .A(n5339), .B(n5262), .Y(n5342) );
NOR2X1TS U2481 ( .A(n3703), .B(n3700), .Y(n3706) );
NAND2X4TS U2482 ( .A(n2695), .B(n4645), .Y(n2588) );
OAI22X2TS U2483 ( .A0(n5199), .A1(n5338), .B0(n5251), .B1(n2237), .Y(n5247)
);
OAI22X2TS U2484 ( .A0(n2231), .A1(n5261), .B0(n5346), .B1(n5416), .Y(n5343)
);
NAND2X6TS U2485 ( .A(n3095), .B(n3516), .Y(n2791) );
NAND2X6TS U2486 ( .A(n3096), .B(n3095), .Y(n2792) );
NAND3X6TS U2487 ( .A(n3016), .B(n4523), .C(n4636), .Y(n2610) );
NAND2X1TS U2488 ( .A(n5254), .B(n5262), .Y(n4638) );
OR2X6TS U2489 ( .A(n2605), .B(n4475), .Y(n4636) );
AND2X6TS U2490 ( .A(n2559), .B(n2558), .Y(n2328) );
NAND2X1TS U2491 ( .A(n4855), .B(n4618), .Y(n4620) );
OAI22X2TS U2492 ( .A0(n5173), .A1(n5338), .B0(n5199), .B1(n2376), .Y(n5214)
);
OR2X4TS U2493 ( .A(n2318), .B(n3740), .Y(n2968) );
NAND2X2TS U2494 ( .A(n3672), .B(n3671), .Y(n3693) );
NAND2X6TS U2495 ( .A(n2262), .B(n5050), .Y(n5094) );
XNOR2X2TS U2496 ( .A(n5340), .B(n5345), .Y(n5261) );
INVX2TS U2497 ( .A(n4635), .Y(n2612) );
INVX2TS U2498 ( .A(n5181), .Y(n5223) );
INVX2TS U2499 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n4872) );
INVX6TS U2500 ( .A(n5066), .Y(n5105) );
NOR2X1TS U2501 ( .A(n5180), .B(n2354), .Y(n5224) );
NAND2X1TS U2502 ( .A(n3191), .B(n4847), .Y(n4849) );
NOR2X4TS U2503 ( .A(n3672), .B(n3671), .Y(n3694) );
INVX3TS U2504 ( .A(n3692), .Y(n3660) );
INVX4TS U2505 ( .A(n2972), .Y(n2970) );
NAND2X6TS U2506 ( .A(n2731), .B(n2689), .Y(n2589) );
CLKXOR2X4TS U2507 ( .A(n4697), .B(n4696), .Y(n4866) );
NAND2X1TS U2508 ( .A(n5204), .B(n5203), .Y(n4666) );
NAND2BX1TS U2509 ( .AN(n4616), .B(n4920), .Y(n2704) );
INVX6TS U2510 ( .A(n4652), .Y(n2689) );
NAND2X1TS U2511 ( .A(n3735), .B(n3734), .Y(n3736) );
NAND2X1TS U2512 ( .A(n4688), .B(n4687), .Y(n4690) );
NAND2X2TS U2513 ( .A(n2753), .B(n3722), .Y(n3723) );
XNOR2X2TS U2514 ( .A(n5198), .B(n5340), .Y(n5173) );
OAI21X1TS U2515 ( .A0(n3488), .A1(n3088), .B0(n3485), .Y(n2732) );
OAI22X1TS U2516 ( .A0(n2644), .A1(n2240), .B0(n4625), .B1(n4633), .Y(n4631)
);
XOR2X2TS U2517 ( .A(n4756), .B(n4755), .Y(n7209) );
NAND2X4TS U2518 ( .A(n4076), .B(n4075), .Y(n4657) );
INVX4TS U2519 ( .A(n3093), .Y(n2234) );
NOR2X1TS U2520 ( .A(n4917), .B(n2353), .Y(n5168) );
NAND2X2TS U2521 ( .A(n5079), .B(n5078), .Y(n5098) );
INVX6TS U2522 ( .A(n2998), .Y(n2726) );
NAND2X4TS U2523 ( .A(n3620), .B(n3619), .Y(n3631) );
NAND2BX2TS U2524 ( .AN(n4524), .B(n4527), .Y(n4471) );
AOI21X2TS U2525 ( .A0(n4763), .A1(n4760), .B0(n4752), .Y(n4756) );
OR2X4TS U2526 ( .A(n2236), .B(n3095), .Y(n3092) );
OR2X6TS U2527 ( .A(n4076), .B(n4075), .Y(n4658) );
INVX2TS U2528 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n4825) );
INVX2TS U2529 ( .A(n2279), .Y(n2703) );
INVX4TS U2530 ( .A(n4751), .Y(n4763) );
NAND2X1TS U2531 ( .A(n3485), .B(n3733), .Y(n3292) );
NAND2X2TS U2532 ( .A(n4813), .B(n4812), .Y(n5005) );
OAI22X2TS U2533 ( .A0(n4095), .A1(n4093), .B0(n3939), .B1(n4094), .Y(n4090)
);
NOR2X4TS U2534 ( .A(n3560), .B(n3559), .Y(n3093) );
NOR2X2TS U2535 ( .A(n4939), .B(n5212), .Y(n5178) );
NAND2X2TS U2536 ( .A(n2321), .B(n4469), .Y(n2573) );
XNOR2X2TS U2537 ( .A(n5205), .B(n5345), .Y(n5169) );
CLKINVX2TS U2538 ( .A(n3662), .Y(n2877) );
INVX2TS U2539 ( .A(n7207), .Y(n4746) );
INVX6TS U2540 ( .A(n2807), .Y(n4983) );
NOR2X1TS U2541 ( .A(n4829), .B(n4827), .Y(n4587) );
OAI22X1TS U2542 ( .A0(n4941), .A1(n5209), .B0(n4116), .B1(n5210), .Y(n4932)
);
NOR2X6TS U2543 ( .A(n3518), .B(n3517), .Y(n3717) );
NAND2X1TS U2544 ( .A(n3628), .B(n3627), .Y(n3682) );
OR2X6TS U2545 ( .A(n4043), .B(n4042), .Y(n3191) );
INVX2TS U2546 ( .A(n5360), .Y(n3986) );
NOR2X4TS U2547 ( .A(n4586), .B(n4585), .Y(n4829) );
NOR2X1TS U2548 ( .A(n3867), .B(n5212), .Y(n4118) );
NOR2X1TS U2549 ( .A(n4119), .B(n5212), .Y(n4937) );
INVX2TS U2550 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(n4819) );
NAND2X1TS U2551 ( .A(n4805), .B(n4804), .Y(n4807) );
NAND2X2TS U2552 ( .A(n4799), .B(n4798), .Y(n5055) );
INVX2TS U2553 ( .A(n4701), .Y(n4201) );
OR2X4TS U2554 ( .A(n2981), .B(n2312), .Y(n3722) );
INVX4TS U2555 ( .A(n4524), .Y(n2788) );
NAND2X2TS U2556 ( .A(n4267), .B(n4266), .Y(n4761) );
OAI22X2TS U2557 ( .A0(n4633), .A1(n4613), .B0(n4625), .B1(n2644), .Y(n4630)
);
XNOR2X2TS U2558 ( .A(n4938), .B(n4940), .Y(n4116) );
XNOR2X2TS U2559 ( .A(n4319), .B(n4318), .Y(n4320) );
NAND2X1TS U2560 ( .A(n4566), .B(n4565), .Y(n4987) );
INVX2TS U2561 ( .A(n5359), .Y(n3943) );
OAI2BB1X1TS U2562 ( .A0N(n5021), .A1N(n5022), .B0(n2852), .Y(n5069) );
OAI2BB1X2TS U2563 ( .A0N(n4046), .A1N(n2698), .B0(n2696), .Y(n4074) );
NAND2X6TS U2564 ( .A(n3553), .B(n3554), .Y(n3589) );
NAND2X6TS U2565 ( .A(n4468), .B(n4467), .Y(n4527) );
NAND2X6TS U2566 ( .A(n3591), .B(n3590), .Y(n2587) );
INVX6TS U2567 ( .A(n2795), .Y(n2627) );
NAND2X1TS U2568 ( .A(n3557), .B(n3556), .Y(n3626) );
INVX4TS U2569 ( .A(n7206), .Y(n4820) );
AO21X2TS U2570 ( .A0(n4600), .A1(n2243), .B0(n4599), .Y(n4611) );
NAND2X1TS U2571 ( .A(n4473), .B(n4472), .Y(n4567) );
INVX2TS U2572 ( .A(n2284), .Y(n3588) );
NAND2BX1TS U2573 ( .AN(n4108), .B(n5345), .Y(n3966) );
CLKINVX2TS U2574 ( .A(n3737), .Y(n3083) );
CLKXOR2X2TS U2575 ( .A(n2961), .B(n4006), .Y(n4120) );
OAI22X1TS U2576 ( .A0(n4633), .A1(n4601), .B0(n2644), .B1(n4613), .Y(n4610)
);
NAND2X2TS U2577 ( .A(n2948), .B(n3916), .Y(n2946) );
NOR2X1TS U2578 ( .A(n2435), .B(n2299), .Y(n3666) );
BUFX6TS U2579 ( .A(n2623), .Y(n2548) );
INVX2TS U2580 ( .A(n5290), .Y(n3983) );
CMPR32X2TS U2581 ( .A(n5074), .B(n5073), .C(n5072), .CO(n5108), .S(n5076) );
INVX2TS U2582 ( .A(n5002), .Y(n4769) );
INVX2TS U2583 ( .A(n5279), .Y(n4049) );
OR2X2TS U2584 ( .A(n4032), .B(n4031), .Y(n4758) );
OAI21X2TS U2585 ( .A0(n4046), .A1(n2698), .B0(n4045), .Y(n2696) );
NAND2X1TS U2586 ( .A(n2238), .B(n4259), .Y(n4260) );
NOR2X2TS U2587 ( .A(n4582), .B(n4581), .Y(n4803) );
BUFX8TS U2588 ( .A(n2795), .Y(n2749) );
NAND2X2TS U2589 ( .A(n3081), .B(n3499), .Y(n3737) );
OR2X4TS U2590 ( .A(n4200), .B(n4199), .Y(n4702) );
NAND2X6TS U2591 ( .A(n2622), .B(n4376), .Y(n2835) );
OR2X1TS U2592 ( .A(n4780), .B(n4779), .Y(n4781) );
XNOR2X2TS U2593 ( .A(n5252), .B(n4921), .Y(n3960) );
OAI21X2TS U2594 ( .A0(n4977), .A1(n4976), .B0(n4975), .Y(n3109) );
INVX12TS U2595 ( .A(n2513), .Y(n5338) );
NAND2X2TS U2596 ( .A(n4032), .B(n4031), .Y(n4757) );
NAND2X1TS U2597 ( .A(n4027), .B(n3128), .Y(n4699) );
OR2X2TS U2598 ( .A(n3081), .B(n3499), .Y(n3738) );
NOR2BX1TS U2599 ( .AN(n4027), .B(n5212), .Y(n3959) );
INVX2TS U2600 ( .A(n2352), .Y(n2353) );
OAI22X2TS U2601 ( .A0(n4100), .A1(n4600), .B0(n4591), .B1(n2243), .Y(n4590)
);
OR2X2TS U2602 ( .A(n4029), .B(n4028), .Y(n2302) );
CLKXOR2X2TS U2603 ( .A(n4046), .B(n2698), .Y(n2697) );
NAND2X1TS U2604 ( .A(n4548), .B(n4547), .Y(n4368) );
INVX6TS U2605 ( .A(n2781), .Y(n2644) );
AND2X6TS U2606 ( .A(n2376), .B(n2516), .Y(n2513) );
NOR2BX1TS U2607 ( .AN(n4027), .B(n5209), .Y(n4055) );
INVX6TS U2608 ( .A(n2659), .Y(n3183) );
OAI2BB1X2TS U2609 ( .A0N(n4957), .A1N(n3108), .B0(n3106), .Y(n5036) );
OAI22X2TS U2610 ( .A0(n3950), .A1(n4026), .B0(n3978), .B1(n3993), .Y(n4054)
);
NAND2X1TS U2611 ( .A(n4716), .B(n4715), .Y(n4717) );
NAND2XLTS U2612 ( .A(n3505), .B(n3510), .Y(n3513) );
INVX3TS U2613 ( .A(n4365), .Y(n2720) );
INVX6TS U2614 ( .A(n3428), .Y(n2626) );
INVX2TS U2615 ( .A(n3427), .Y(n2625) );
INVX2TS U2616 ( .A(n4604), .Y(n2240) );
NOR2X6TS U2617 ( .A(n4360), .B(n4359), .Y(n2659) );
INVX6TS U2618 ( .A(n2512), .Y(n2376) );
NAND2X2TS U2619 ( .A(n4304), .B(n4303), .Y(n4361) );
NOR2BX2TS U2620 ( .AN(n3570), .B(n3522), .Y(n3600) );
NAND2X2TS U2621 ( .A(n3291), .B(n3290), .Y(n3485) );
NOR2X2TS U2622 ( .A(n3078), .B(n3923), .Y(n2900) );
XNOR2X2TS U2623 ( .A(n4573), .B(n4000), .Y(n4789) );
OAI21X2TS U2624 ( .A0(n4189), .A1(n4710), .B0(n4190), .Y(n4174) );
OAI22X1TS U2625 ( .A0(n2349), .A1(n3606), .B0(n3664), .B1(n3571), .Y(n3599)
);
INVX4TS U2626 ( .A(n3488), .Y(n3086) );
NAND2X4TS U2627 ( .A(n2682), .B(n2681), .Y(n5557) );
XOR2X2TS U2628 ( .A(n2285), .B(n2995), .Y(n3950) );
OR2X6TS U2629 ( .A(n3389), .B(n3388), .Y(n3501) );
CLKINVX6TS U2630 ( .A(n5119), .Y(n2268) );
CLKINVX2TS U2631 ( .A(n4441), .Y(n4507) );
INVX6TS U2632 ( .A(n2990), .Y(n4604) );
INVX4TS U2633 ( .A(n5084), .Y(n4435) );
INVX3TS U2634 ( .A(n4390), .Y(n4436) );
NOR2X4TS U2635 ( .A(n4304), .B(n4303), .Y(n4363) );
NAND2X2TS U2636 ( .A(n4441), .B(n4449), .Y(n4257) );
NAND2X2TS U2637 ( .A(n4417), .B(n4390), .Y(n4190) );
NAND2X6TS U2638 ( .A(n3788), .B(n4626), .Y(n4627) );
INVX4TS U2639 ( .A(n3907), .Y(n5167) );
INVX2TS U2640 ( .A(n3733), .Y(n3088) );
OAI22X2TS U2641 ( .A0(n4536), .A1(n4491), .B0(n5030), .B1(n4440), .Y(n4508)
);
NAND2X2TS U2642 ( .A(n4572), .B(n3999), .Y(n4574) );
BUFX8TS U2643 ( .A(n3883), .Y(n3965) );
XOR2X2TS U2644 ( .A(n4251), .B(n4554), .Y(n2528) );
NAND2X2TS U2645 ( .A(n3997), .B(n3996), .Y(n4780) );
INVX3TS U2646 ( .A(n3078), .Y(n3007) );
OAI22X2TS U2647 ( .A0(n3996), .A1(n2382), .B0(n3995), .B1(n4024), .Y(n4779)
);
NOR2X2TS U2648 ( .A(n3759), .B(n2306), .Y(n2789) );
XNOR2X1TS U2649 ( .A(n4027), .B(n4006), .Y(n4007) );
CLKXOR2X2TS U2650 ( .A(n3827), .B(n3826), .Y(n2595) );
INVX2TS U2651 ( .A(n3582), .Y(n3609) );
INVX2TS U2652 ( .A(n4417), .Y(n4445) );
INVX2TS U2653 ( .A(n4510), .Y(n3013) );
NOR2X4TS U2654 ( .A(n4323), .B(n4350), .Y(n4709) );
NOR2X4TS U2655 ( .A(n3387), .B(n3386), .Y(n3489) );
NOR2X1TS U2656 ( .A(n5030), .B(n4448), .Y(n4496) );
OAI2BB1X2TS U2657 ( .A0N(n3456), .A1N(n2974), .B0(n2973), .Y(n3532) );
INVX3TS U2658 ( .A(n4548), .Y(n4956) );
NOR2X4TS U2659 ( .A(n3808), .B(n3161), .Y(n2646) );
INVX4TS U2660 ( .A(n3867), .Y(n3951) );
NOR2X4TS U2661 ( .A(n3904), .B(n3110), .Y(n3923) );
BUFX8TS U2662 ( .A(n3798), .Y(n4626) );
INVX6TS U2663 ( .A(n4605), .Y(n2442) );
NOR2X2TS U2664 ( .A(n5030), .B(n4491), .Y(n4534) );
OAI2BB2X2TS U2665 ( .B0(n2433), .B1(n7708), .A0N(n2776), .A1N(n7708), .Y(
n3607) );
XOR2X2TS U2666 ( .A(n3605), .B(n2685), .Y(n5402) );
NOR2X1TS U2667 ( .A(n3763), .B(n3758), .Y(n3756) );
INVX8TS U2668 ( .A(n2957), .Y(n3110) );
INVX8TS U2669 ( .A(n3074), .Y(n4936) );
INVX4TS U2670 ( .A(n4411), .Y(n5070) );
OAI2BB2X1TS U2671 ( .B0(n3393), .B1(n7708), .A0N(n3445), .A1N(n7708), .Y(
n3528) );
NOR2X2TS U2672 ( .A(n3150), .B(n3173), .Y(n4971) );
AOI21X2TS U2673 ( .A0(n3872), .A1(n2966), .B0(n3871), .Y(n2991) );
INVX6TS U2674 ( .A(n2928), .Y(n4027) );
NOR2X2TS U2675 ( .A(n2730), .B(n2539), .Y(n2538) );
CLKXOR2X4TS U2676 ( .A(n2727), .B(n2316), .Y(n4026) );
XOR2X2TS U2677 ( .A(n3836), .B(n3172), .Y(n2618) );
ADDFHX2TS U2678 ( .A(n4487), .B(n4486), .CI(n4485), .CO(n4551), .S(n4488) );
ADDFHX2TS U2679 ( .A(n4338), .B(n4337), .CI(n4336), .CO(n4418), .S(n4357) );
INVX3TS U2680 ( .A(n4323), .Y(n4389) );
NOR2X1TS U2681 ( .A(DP_OP_498J211_124_1725_n722), .B(n4972), .Y(n4968) );
OAI2BB1X2TS U2682 ( .A0N(n3363), .A1N(n2798), .B0(n2797), .Y(n3403) );
NOR2X1TS U2683 ( .A(n4973), .B(n4451), .Y(n4480) );
NAND2X1TS U2684 ( .A(n3845), .B(n3840), .Y(n3833) );
OR2X4TS U2685 ( .A(n3378), .B(n3377), .Y(n3469) );
INVX4TS U2686 ( .A(n2686), .Y(n3826) );
NAND2BXLTS U2687 ( .AN(DP_OP_496J211_122_3540_n778), .B(n2316), .Y(n3076) );
INVX6TS U2688 ( .A(n3421), .Y(n2435) );
NOR2X1TS U2689 ( .A(DP_OP_498J211_124_1725_n722), .B(n4483), .Y(n4487) );
NOR2X4TS U2690 ( .A(n4972), .B(n4450), .Y(n4481) );
AOI21X2TS U2691 ( .A0(n2940), .A1(n3828), .B0(n3830), .Y(n3119) );
OAI21X2TS U2692 ( .A0(n3514), .A1(n2317), .B0(n3473), .Y(n2767) );
XNOR2X2TS U2693 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n3863) );
OAI21X2TS U2694 ( .A0(n4316), .A1(n2785), .B0(n2786), .Y(n2783) );
NAND2X2TS U2695 ( .A(n3814), .B(n3813), .Y(n3906) );
BUFX6TS U2696 ( .A(n3791), .Y(n2429) );
INVX2TS U2697 ( .A(n3412), .Y(n3429) );
NOR2X1TS U2698 ( .A(n3582), .B(n3573), .Y(n3504) );
BUFX6TS U2699 ( .A(n4549), .Y(n2379) );
BUFX8TS U2700 ( .A(n2851), .Y(n2837) );
NAND2X2TS U2701 ( .A(n3544), .B(n3543), .Y(n2679) );
CLKAND2X2TS U2702 ( .A(n3495), .B(n2918), .Y(n2920) );
NAND2X1TS U2703 ( .A(n2315), .B(n3870), .Y(n3004) );
INVX4TS U2704 ( .A(n4299), .Y(n4970) );
INVX4TS U2705 ( .A(n4218), .Y(n4537) );
OAI21X2TS U2706 ( .A0(n3908), .A1(n3911), .B0(n2727), .Y(n3814) );
NAND2X2TS U2707 ( .A(n3810), .B(n3823), .Y(n3754) );
BUFX16TS U2708 ( .A(n2851), .Y(n4954) );
NOR2X6TS U2709 ( .A(n3781), .B(n3800), .Y(n3818) );
NAND3X2TS U2710 ( .A(n2940), .B(n3884), .C(n3785), .Y(n2963) );
OR2X2TS U2711 ( .A(n4405), .B(n4402), .Y(n4406) );
NAND2X2TS U2712 ( .A(n4734), .B(n4733), .Y(n4739) );
NOR2X2TS U2713 ( .A(n4450), .B(n2275), .Y(n4456) );
NAND2X2TS U2714 ( .A(n3248), .B(n3473), .Y(n3253) );
NAND2X6TS U2715 ( .A(n2884), .B(n2883), .Y(n3708) );
ADDHX2TS U2716 ( .A(n4142), .B(n4141), .CO(n4245), .S(n4138) );
NAND2X2TS U2717 ( .A(n2862), .B(n2867), .Y(n2861) );
ADDFHX2TS U2718 ( .A(n4400), .B(n4399), .CI(n4398), .CO(n4452), .S(n4415) );
NAND2X1TS U2719 ( .A(n3522), .B(n3541), .Y(n3472) );
CLKINVX2TS U2720 ( .A(n3758), .Y(n3037) );
NOR2X1TS U2721 ( .A(n4484), .B(n4451), .Y(n4398) );
NOR2X1TS U2722 ( .A(n4242), .B(DP_OP_498J211_124_1725_n636), .Y(n4143) );
NAND2X1TS U2723 ( .A(n7729), .B(DP_OP_496J211_122_3540_n1103), .Y(n3755) );
INVX2TS U2724 ( .A(n2710), .Y(n2440) );
XOR2X4TS U2725 ( .A(n3794), .B(n3780), .Y(n3800) );
INVX4TS U2726 ( .A(n4276), .Y(n4335) );
INVX4TS U2727 ( .A(n3657), .Y(n2542) );
INVX2TS U2728 ( .A(n3358), .Y(n3423) );
NAND2X2TS U2729 ( .A(n3450), .B(n3449), .Y(n2883) );
NOR2X2TS U2730 ( .A(n4450), .B(n4483), .Y(n4399) );
NAND2BX1TS U2731 ( .AN(DP_OP_498J211_124_1725_n636), .B(n4294), .Y(n4140) );
BUFX3TS U2732 ( .A(n3790), .Y(n3823) );
NAND2X4TS U2733 ( .A(n2727), .B(n3068), .Y(n3067) );
NAND2BX2TS U2734 ( .AN(n2313), .B(n3447), .Y(n3473) );
NAND2X4TS U2735 ( .A(n3136), .B(n3420), .Y(n3421) );
INVX4TS U2736 ( .A(n3786), .Y(n4099) );
NOR2X2TS U2737 ( .A(n4166), .B(n4243), .Y(n4141) );
AND2X4TS U2738 ( .A(n3761), .B(n3762), .Y(n2536) );
ADDHX2TS U2739 ( .A(n4396), .B(n4395), .CO(n4454), .S(n4392) );
OR2X2TS U2740 ( .A(n3496), .B(n2922), .Y(n2918) );
INVX3TS U2741 ( .A(n3782), .Y(n3884) );
CMPR32X2TS U2742 ( .A(n4232), .B(n4231), .C(n4230), .CO(n4289), .S(n4236) );
CMPR32X2TS U2743 ( .A(n3335), .B(n3334), .C(n3333), .CO(n3370), .S(n3284) );
INVX2TS U2744 ( .A(n3321), .Y(n3331) );
XOR2X1TS U2745 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2578) );
NOR2X4TS U2746 ( .A(n3358), .B(n3312), .Y(n3728) );
NOR2X1TS U2747 ( .A(n4450), .B(n4451), .Y(n4351) );
NOR2X6TS U2748 ( .A(n3397), .B(n3412), .Y(n3250) );
INVX4TS U2749 ( .A(n4213), .Y(n2437) );
NOR2BX1TS U2750 ( .AN(DP_OP_496J211_122_3540_n778), .B(n3145), .Y(n3746) );
NOR2X4TS U2751 ( .A(n4972), .B(n4355), .Y(n4396) );
NOR2X2TS U2752 ( .A(n3258), .B(n3257), .Y(n3288) );
NOR2X4TS U2753 ( .A(n4355), .B(n2275), .Y(n4354) );
NOR2BX2TS U2754 ( .AN(n3166), .B(n6893), .Y(n3832) );
NAND2X2TS U2755 ( .A(n7731), .B(DP_OP_496J211_122_3540_n1193), .Y(n3795) );
INVX2TS U2756 ( .A(n3317), .Y(n3606) );
NOR2X2TS U2757 ( .A(n4185), .B(n8489), .Y(n4154) );
NOR2X6TS U2758 ( .A(DP_OP_498J211_124_1725_n722), .B(n4451), .Y(n2867) );
NAND2X1TS U2759 ( .A(n4195), .B(n4194), .Y(n4196) );
NOR2X2TS U2760 ( .A(n4484), .B(n4391), .Y(n4352) );
BUFX4TS U2761 ( .A(n3393), .Y(n2428) );
NOR2X2TS U2762 ( .A(n4242), .B(n4166), .Y(n4153) );
OR2X4TS U2763 ( .A(n3136), .B(n3480), .Y(n2881) );
NOR2X2TS U2764 ( .A(n3480), .B(n3479), .Y(n3496) );
NAND3X6TS U2765 ( .A(n3872), .B(n2966), .C(n3873), .Y(n2959) );
CLKINVX6TS U2766 ( .A(n3447), .Y(n2241) );
OAI2BB1X2TS U2767 ( .A0N(n3400), .A1N(n3401), .B0(n2561), .Y(n3451) );
NAND2X4TS U2768 ( .A(DP_OP_498J211_124_1725_n803), .B(
DP_OP_498J211_124_1725_n790), .Y(n2849) );
INVX6TS U2769 ( .A(n4293), .Y(n2840) );
INVX12TS U2770 ( .A(n3538), .Y(n7454) );
INVX4TS U2771 ( .A(n8519), .Y(n4243) );
OR2X4TS U2772 ( .A(n2771), .B(n2320), .Y(n3318) );
NAND2X2TS U2773 ( .A(n7730), .B(DP_OP_496J211_122_3540_n1114), .Y(n2711) );
INVX8TS U2774 ( .A(n2655), .Y(n2776) );
NOR2X6TS U2775 ( .A(n3116), .B(n3869), .Y(n3872) );
BUFX4TS U2776 ( .A(DP_OP_496J211_122_3540_n1472), .Y(n6860) );
NAND3X4TS U2777 ( .A(n3876), .B(n3877), .C(n3879), .Y(n2728) );
NOR2X1TS U2778 ( .A(n3538), .B(n3166), .Y(n3453) );
NOR2X1TS U2779 ( .A(DP_OP_497J211_123_1725_n716), .B(n3166), .Y(n3352) );
INVX6TS U2780 ( .A(n4213), .Y(n2436) );
OR2X2TS U2781 ( .A(n3321), .B(n3305), .Y(n3204) );
INVX6TS U2782 ( .A(n3760), .Y(n3877) );
INVX2TS U2783 ( .A(n3278), .Y(n3519) );
NOR2X6TS U2784 ( .A(n3355), .B(DP_OP_497J211_123_1725_n716), .Y(n3556) );
NOR2X2TS U2785 ( .A(n3174), .B(n2226), .Y(n3353) );
NOR2X2TS U2786 ( .A(n4450), .B(n4391), .Y(n4275) );
INVX12TS U2787 ( .A(n3610), .Y(n2433) );
INVX4TS U2788 ( .A(n4207), .Y(n4491) );
INVX4TS U2789 ( .A(n3231), .Y(n3422) );
NOR2X6TS U2790 ( .A(n3745), .B(DP_OP_496J211_122_3540_n1102), .Y(n3876) );
INVX3TS U2791 ( .A(n2730), .Y(n3879) );
NAND2X2TS U2792 ( .A(n2856), .B(n7699), .Y(n2855) );
INVX2TS U2793 ( .A(FPMULT_Op_MY[22]), .Y(n2684) );
INVX4TS U2794 ( .A(n3306), .Y(n3571) );
NOR2X1TS U2795 ( .A(n3145), .B(n4451), .Y(n4301) );
INVX6TS U2796 ( .A(FPMULT_Op_MY[9]), .Y(n4484) );
OR2X6TS U2797 ( .A(n3144), .B(n4255), .Y(n3761) );
OAI21X2TS U2798 ( .A0(n3266), .A1(n3267), .B0(n3265), .Y(n2910) );
INVX6TS U2799 ( .A(n4206), .Y(n4495) );
INVX2TS U2800 ( .A(FPMULT_Op_MX[22]), .Y(n2683) );
NAND2X2TS U2801 ( .A(n3321), .B(n3305), .Y(n4727) );
NOR2X4TS U2802 ( .A(n3538), .B(n2226), .Y(n3401) );
INVX8TS U2803 ( .A(n4180), .Y(n4331) );
NOR2X2TS U2804 ( .A(n3310), .B(n3166), .Y(n3309) );
NAND2X1TS U2805 ( .A(n3247), .B(n2768), .Y(n2628) );
NAND2X2TS U2806 ( .A(n3180), .B(n3165), .Y(n3770) );
BUFX4TS U2807 ( .A(n3769), .Y(n3774) );
OAI2BB1X2TS U2808 ( .A0N(n2762), .A1N(n2761), .B0(n3213), .Y(n2760) );
NAND2BX2TS U2809 ( .AN(n7700), .B(n4220), .Y(n2856) );
NAND2X4TS U2810 ( .A(n3762), .B(n2496), .Y(n2495) );
CLKXOR2X4TS U2811 ( .A(n2899), .B(n2898), .Y(n3215) );
ADDHX1TS U2812 ( .A(DP_OP_497J211_123_1725_n794), .B(
DP_OP_496J211_122_3540_n1502), .CO(n3317), .S(n3306) );
CMPR22X2TS U2813 ( .A(n3323), .B(n3322), .CO(n3325), .S(n3557) );
CLKXOR2X4TS U2814 ( .A(DP_OP_498J211_124_1725_n362), .B(n7688), .Y(n2314) );
INVX12TS U2815 ( .A(DP_OP_498J211_124_1725_n797), .Y(n4483) );
INVX2TS U2816 ( .A(DP_OP_496J211_122_3540_n1103), .Y(n2496) );
NOR2X2TS U2817 ( .A(n2643), .B(DP_OP_497J211_123_1725_n324), .Y(n3481) );
BUFX4TS U2818 ( .A(FPMULT_Op_MX[16]), .Y(n2936) );
NOR2X4TS U2819 ( .A(n4166), .B(n4211), .Y(n4162) );
INVX8TS U2820 ( .A(FPMULT_Op_MY[8]), .Y(n4450) );
NOR2X2TS U2821 ( .A(n3310), .B(n8285), .Y(n3357) );
NOR2X2TS U2822 ( .A(n2226), .B(n3310), .Y(n3323) );
NAND2X2TS U2823 ( .A(n7673), .B(n3279), .Y(n3255) );
NOR2X4TS U2824 ( .A(n3310), .B(n3355), .Y(n3465) );
AND2X4TS U2825 ( .A(n3230), .B(DP_OP_497J211_123_1725_n392), .Y(n3408) );
CMPR22X2TS U2826 ( .A(DP_OP_498J211_124_1725_n790), .B(n6900), .CO(n4217),
.S(n4206) );
NOR2X4TS U2827 ( .A(n4391), .B(n4355), .Y(n4472) );
INVX6TS U2828 ( .A(DP_OP_498J211_124_1725_n795), .Y(n4391) );
INVX2TS U2829 ( .A(n2270), .Y(n2521) );
INVX8TS U2830 ( .A(DP_OP_498J211_124_1725_n801), .Y(n4165) );
INVX8TS U2831 ( .A(DP_OP_497J211_123_1725_n686), .Y(n3310) );
OR2X2TS U2832 ( .A(DP_OP_497J211_123_1725_n686), .B(
DP_OP_497J211_123_1725_n778), .Y(n3230) );
NOR2X2TS U2833 ( .A(n2870), .B(DP_OP_497J211_123_1725_n638), .Y(n3212) );
NOR2X4TS U2834 ( .A(n3232), .B(n3270), .Y(n3209) );
NOR2X2TS U2835 ( .A(DP_OP_497J211_123_1725_n324), .B(n3240), .Y(n3268) );
BUFX12TS U2836 ( .A(FPMULT_Op_MY[8]), .Y(n6900) );
XOR2X2TS U2837 ( .A(n2917), .B(n2916), .Y(n2769) );
NOR2X2TS U2838 ( .A(DP_OP_497J211_123_1725_n324), .B(n3232), .Y(n3221) );
NOR2X6TS U2839 ( .A(n3270), .B(DP_OP_497J211_123_1725_n631), .Y(n2898) );
NOR2X6TS U2840 ( .A(n3480), .B(DP_OP_497J211_123_1725_n638), .Y(n2975) );
NOR2X2TS U2841 ( .A(n3240), .B(n3479), .Y(n3241) );
NAND2X6TS U2842 ( .A(n3293), .B(n2653), .Y(n3139) );
INVX6TS U2843 ( .A(DP_OP_497J211_123_1725_n778), .Y(n3232) );
INVX6TS U2844 ( .A(DP_OP_497J211_123_1725_n780), .Y(n3240) );
NOR2X4TS U2845 ( .A(n2748), .B(n3538), .Y(n2871) );
BUFX8TS U2846 ( .A(n3300), .Y(n2868) );
NAND2X6TS U2847 ( .A(n3279), .B(n2654), .Y(n3294) );
INVX16TS U2848 ( .A(DP_OP_497J211_123_1725_n781), .Y(n2870) );
BUFX6TS U2849 ( .A(DP_OP_497J211_123_1725_n780), .Y(n5707) );
AND2X6TS U2850 ( .A(n3538), .B(n2870), .Y(n3300) );
BUFX8TS U2851 ( .A(FPMULT_Op_MY[20]), .Y(n3860) );
INVX2TS U2852 ( .A(n2250), .Y(n2197) );
INVX2TS U2853 ( .A(n2197), .Y(n2198) );
INVX2TS U2854 ( .A(n2197), .Y(n2199) );
INVX2TS U2855 ( .A(n2257), .Y(n2200) );
INVX2TS U2856 ( .A(n2200), .Y(n2201) );
INVX2TS U2857 ( .A(n2200), .Y(n2202) );
INVX2TS U2858 ( .A(n2203), .Y(n2204) );
CLKINVX3TS U2859 ( .A(n2203), .Y(n2205) );
INVX2TS U2860 ( .A(n2255), .Y(n2206) );
INVX2TS U2861 ( .A(n2206), .Y(n2207) );
INVX2TS U2862 ( .A(n2206), .Y(n2208) );
INVX2TS U2863 ( .A(n2249), .Y(n2209) );
INVX2TS U2864 ( .A(n2209), .Y(n2210) );
INVX2TS U2865 ( .A(n2209), .Y(n2211) );
INVX2TS U2866 ( .A(n2209), .Y(n2212) );
INVX2TS U2867 ( .A(n2253), .Y(n2213) );
INVX2TS U2868 ( .A(n2213), .Y(n2214) );
INVX2TS U2869 ( .A(n2213), .Y(n2215) );
INVX2TS U2870 ( .A(n2213), .Y(n2216) );
INVX2TS U2871 ( .A(n2213), .Y(n2217) );
INVX2TS U2872 ( .A(n2254), .Y(n2218) );
INVX2TS U2873 ( .A(n2218), .Y(n2219) );
CLKINVX3TS U2874 ( .A(n2218), .Y(n2220) );
INVX2TS U2875 ( .A(n2218), .Y(n2221) );
CLKINVX3TS U2876 ( .A(n2218), .Y(n2222) );
NAND2X1TS U2877 ( .A(n3908), .B(n3911), .Y(n3813) );
BUFX3TS U2878 ( .A(n2870), .Y(n2748) );
BUFX4TS U2879 ( .A(n3786), .Y(n2576) );
OA21X1TS U2880 ( .A0(n4405), .A1(n4404), .B0(n4403), .Y(n3163) );
INVX4TS U2881 ( .A(n4324), .Y(n5029) );
ADDFX2TS U2882 ( .A(n4540), .B(n4539), .CI(n4538), .CO(n4951), .S(n4559) );
OAI22X1TS U2883 ( .A0(n4627), .A1(n4098), .B0(n4588), .B1(n4626), .Y(n4595)
);
CMPR22X2TS U2884 ( .A(DP_OP_498J211_124_1725_n791), .B(n6899), .CO(n4299),
.S(n4218) );
INVX6TS U2885 ( .A(n3910), .Y(n4093) );
OAI21X2TS U2886 ( .A0(n4065), .A1(n2943), .B0(n4064), .Y(n2941) );
INVX2TS U2887 ( .A(n3573), .Y(n3614) );
AND2X2TS U2888 ( .A(n3419), .B(n3480), .Y(n3420) );
INVX2TS U2889 ( .A(n2882), .Y(n3639) );
NOR2X1TS U2890 ( .A(DP_OP_498J211_124_1725_n722), .B(n2275), .Y(n4544) );
INVX2TS U2891 ( .A(n4562), .Y(n2677) );
OR2X2TS U2892 ( .A(n8285), .B(n8343), .Y(n2299) );
NOR2X4TS U2893 ( .A(n3480), .B(n2320), .Y(n3269) );
INVX4TS U2894 ( .A(n2314), .Y(n2377) );
XNOR2X2TS U2895 ( .A(n2812), .B(n2811), .Y(n2810) );
NOR2X1TS U2896 ( .A(n4973), .B(n2275), .Y(n4969) );
NOR2X1TS U2897 ( .A(n5341), .B(n2354), .Y(n5421) );
NOR2X2TS U2898 ( .A(n3174), .B(n3166), .Y(n2563) );
NAND2BX2TS U2899 ( .AN(n2933), .B(n3269), .Y(n2932) );
INVX2TS U2900 ( .A(n3543), .Y(n2739) );
NAND2X1TS U2901 ( .A(n5080), .B(n5098), .Y(n5081) );
ADDFHX2TS U2902 ( .A(n4969), .B(n4968), .CI(n4967), .CO(n5476), .S(n5391) );
OAI22X1TS U2903 ( .A0(n5417), .A1(n5416), .B0(n2231), .B1(n5346), .Y(n5414)
);
NAND2X2TS U2904 ( .A(n2806), .B(n4950), .Y(n4564) );
OR2X1TS U2905 ( .A(n4018), .B(n4003), .Y(n3751) );
INVX2TS U2906 ( .A(n7213), .Y(n4879) );
OAI21X1TS U2907 ( .A0(n4828), .A1(n4827), .B0(n4826), .Y(n4833) );
NAND2X1TS U2908 ( .A(n2269), .B(n5118), .Y(n5387) );
NOR2X2TS U2909 ( .A(n3355), .B(n3538), .Y(n3356) );
OAI22X2TS U2910 ( .A0(n4008), .A1(n4933), .B0(n4934), .B1(n4007), .Y(n5275)
);
NAND2X1TS U2911 ( .A(n4645), .B(n4905), .Y(n4647) );
BUFX4TS U2912 ( .A(n2587), .Y(n2557) );
INVX6TS U2913 ( .A(FPMULT_Op_MX[16]), .Y(n3479) );
NAND2X4TS U2914 ( .A(n2629), .B(n2628), .Y(n3447) );
NAND2X4TS U2915 ( .A(n2605), .B(n4475), .Y(n4635) );
INVX2TS U2916 ( .A(n4306), .Y(n4307) );
INVX2TS U2917 ( .A(n5143), .Y(n5054) );
OAI211XLTS U2918 ( .A0(n5941), .A1(n7371), .B0(n5939), .C0(n5938), .Y(n5944)
);
NOR2X1TS U2919 ( .A(n5174), .B(n5212), .Y(n5202) );
OR2X1TS U2920 ( .A(n5276), .B(n5275), .Y(n5297) );
NAND2X1TS U2921 ( .A(n5381), .B(n5380), .Y(n5600) );
OAI21XLTS U2922 ( .A0(n7186), .A1(n7191), .B0(n7187), .Y(n5847) );
NAND2X6TS U2923 ( .A(n3189), .B(n5461), .Y(n2736) );
NAND2X1TS U2924 ( .A(n3582), .B(n3573), .Y(n3508) );
INVX4TS U2925 ( .A(n4179), .Y(n4407) );
CLKBUFX2TS U2926 ( .A(n6191), .Y(n6603) );
NOR2XLTS U2927 ( .A(n6403), .B(n6397), .Y(n5846) );
NAND2X1TS U2928 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[22]), .Y(n2681) );
OAI21XLTS U2929 ( .A0(n5826), .A1(n6362), .B0(n5825), .Y(n5827) );
NOR2XLTS U2930 ( .A(n6563), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n6564) );
NOR2X4TS U2931 ( .A(n3689), .B(n3688), .Y(n4996) );
NAND2X2TS U2932 ( .A(n2760), .B(n2758), .Y(n3226) );
NOR2BX1TS U2933 ( .AN(n3493), .B(n3514), .Y(n3046) );
INVX6TS U2934 ( .A(n2859), .Y(n2860) );
OAI21XLTS U2935 ( .A0(n7392), .A1(n6012), .B0(n7391), .Y(n6013) );
NAND2X1TS U2936 ( .A(n5409), .B(n5566), .Y(n5355) );
OAI21XLTS U2937 ( .A0(n5660), .A1(n5632), .B0(n5631), .Y(n5637) );
OR2X1TS U2938 ( .A(n4731), .B(n4730), .Y(n4732) );
AND4X1TS U2939 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n6804), .Y(n6805) );
BUFX3TS U2940 ( .A(n5561), .Y(n5486) );
NOR2X2TS U2941 ( .A(n3342), .B(n3422), .Y(n3260) );
NOR2X4TS U2942 ( .A(n3487), .B(n3486), .Y(n3484) );
AOI21X2TS U2943 ( .A0(n6162), .A1(n6158), .B0(n6093), .Y(n6153) );
NOR2XLTS U2944 ( .A(n7861), .B(n2486), .Y(n6086) );
OAI21XLTS U2945 ( .A0(n6335), .A1(n6236), .B0(n6235), .Y(n6240) );
XNOR2X2TS U2946 ( .A(n4193), .B(n4192), .Y(n4706) );
OAI21XLTS U2947 ( .A0(n6604), .A1(n6498), .B0(n6497), .Y(n6499) );
OAI21XLTS U2948 ( .A0(n6404), .A1(n6403), .B0(n6402), .Y(n6406) );
NOR2X1TS U2949 ( .A(n5553), .B(n3186), .Y(n5610) );
OR2X4TS U2950 ( .A(n2755), .B(n2596), .Y(n3716) );
BUFX3TS U2951 ( .A(n2256), .Y(n5934) );
NOR2X6TS U2952 ( .A(n7250), .B(n6213), .Y(n5151) );
NAND2X2TS U2953 ( .A(n3487), .B(n3486), .Y(n3735) );
NOR2XLTS U2954 ( .A(n7062), .B(n2339), .Y(n7063) );
NOR2XLTS U2955 ( .A(n7071), .B(n7029), .Y(n7006) );
NOR2XLTS U2956 ( .A(n7074), .B(n7029), .Y(n7001) );
NAND2X1TS U2957 ( .A(n4851), .B(n4850), .Y(n4852) );
OAI21XLTS U2958 ( .A0(n7190), .A1(n7172), .B0(n7171), .Y(n7177) );
NAND2X2TS U2959 ( .A(n5750), .B(n5739), .Y(n5745) );
NOR2X1TS U2960 ( .A(n6699), .B(n7824), .Y(n6283) );
INVX4TS U2961 ( .A(n2229), .Y(n2259) );
NAND2X1TS U2962 ( .A(n5934), .B(n8283), .Y(n5892) );
NOR2XLTS U2963 ( .A(n2339), .B(n7077), .Y(n7078) );
AOI31XLTS U2964 ( .A0(n7593), .A1(n7592), .A2(n7591), .B0(n7595), .Y(n7596)
);
NAND2X1TS U2965 ( .A(n5513), .B(n5533), .Y(n5514) );
BUFX3TS U2966 ( .A(n6723), .Y(n6824) );
CLKINVX3TS U2967 ( .A(n6778), .Y(n6796) );
NOR2XLTS U2968 ( .A(n2361), .B(n7322), .Y(n7324) );
BUFX3TS U2969 ( .A(n6624), .Y(n6711) );
NOR2X4TS U2970 ( .A(n6647), .B(operation[2]), .Y(n6623) );
AOI21X2TS U2971 ( .A0(n6211), .A1(n5151), .B0(n5129), .Y(n5153) );
NAND3X6TS U2972 ( .A(n3085), .B(n3084), .C(n3735), .Y(n3739) );
INVX2TS U2973 ( .A(n1662), .Y(n6426) );
NOR3X1TS U2974 ( .A(n1321), .B(n1322), .C(n1323), .Y(n6878) );
NAND2X1TS U2975 ( .A(n6581), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n6280) );
OAI2BB1X1TS U2976 ( .A0N(n8043), .A1N(n5452), .B0(n8498), .Y(n6358) );
NAND2X2TS U2977 ( .A(n6651), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6263) );
ADDHXLTS U2978 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n6937), .CO(n6935),
.S(n6938) );
INVX2TS U2979 ( .A(n7519), .Y(n6816) );
BUFX3TS U2980 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n2350) );
AND2X4TS U2981 ( .A(n8523), .B(n7595), .Y(n6863) );
BUFX3TS U2982 ( .A(n7385), .Y(n7432) );
AO22X1TS U2983 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n6581), .B0(
n6882), .B1(n7092), .Y(n6817) );
INVX2TS U2984 ( .A(n2244), .Y(n2355) );
BUFX3TS U2985 ( .A(n6190), .Y(n7426) );
INVX2TS U2986 ( .A(n8611), .Y(n7406) );
INVX2TS U2987 ( .A(n7334), .Y(n7338) );
INVX2TS U2988 ( .A(n7334), .Y(n7332) );
INVX2TS U2989 ( .A(n7424), .Y(n7353) );
INVX2TS U2990 ( .A(n2196), .Y(intadd_479_B_1_) );
INVX2TS U2991 ( .A(n7297), .Y(n6661) );
NOR2X4TS U2992 ( .A(operation[1]), .B(operation[2]), .Y(n7297) );
INVX2TS U2993 ( .A(n8835), .Y(n8607) );
NOR2X2TS U2994 ( .A(FPMULT_Sgf_operation_EVEN1_S_B[17]), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(add_x_69_n198) );
NOR2XLTS U2995 ( .A(n7687), .B(n7689), .Y(n7692) );
NAND2X1TS U2996 ( .A(n5715), .B(n2794), .Y(n5717) );
OAI21XLTS U2997 ( .A0(n6682), .A1(n6832), .B0(n6681), .Y(n2077) );
OAI211XLTS U2998 ( .A0(n8612), .A1(n7853), .B0(n6816), .C0(n6814), .Y(n1474)
);
OAI21XLTS U2999 ( .A0(n6587), .A1(n6586), .B0(n7288), .Y(n2151) );
OAI21XLTS U3000 ( .A0(n6763), .A1(n6762), .B0(n6761), .Y(n1733) );
BUFX3TS U3001 ( .A(n7413), .Y(n8611) );
NOR2X2TS U3002 ( .A(n7654), .B(n7595), .Y(n8835) );
BUFX3TS U3003 ( .A(n7385), .Y(n7374) );
BUFX3TS U3004 ( .A(n8835), .Y(n8608) );
OAI21XLTS U3005 ( .A0(n6682), .A1(n8526), .B0(n6680), .Y(n1332) );
OAI21XLTS U3006 ( .A0(n2196), .A1(n7322), .B0(n6634), .Y(n2131) );
CLKINVX3TS U3007 ( .A(n7663), .Y(busy) );
INVX2TS U3008 ( .A(n7627), .Y(n2412) );
NAND3X6TS U3009 ( .A(n5460), .B(n5463), .C(n2736), .Y(n2985) );
AND2X8TS U3010 ( .A(n4983), .B(n2806), .Y(n2228) );
AND2X4TS U3011 ( .A(n3470), .B(n3469), .Y(n2230) );
INVX4TS U3012 ( .A(n7452), .Y(n2244) );
CLKINVX3TS U3013 ( .A(n2244), .Y(n2357) );
NAND2X4TS U3014 ( .A(n3963), .B(n3962), .Y(n2231) );
BUFX3TS U3015 ( .A(n6862), .Y(n6864) );
CLKINVX3TS U3016 ( .A(n8523), .Y(n6862) );
BUFX3TS U3017 ( .A(n7424), .Y(n7364) );
CLKINVX3TS U3018 ( .A(n6548), .Y(n6559) );
BUFX3TS U3019 ( .A(n6559), .Y(n7424) );
AND2X4TS U3020 ( .A(n2981), .B(n2312), .Y(n3721) );
INVX4TS U3021 ( .A(n3721), .Y(n2753) );
INVX2TS U3022 ( .A(n5157), .Y(n3580) );
OA21X4TS U3023 ( .A0(n2986), .A1(n3923), .B0(n3007), .Y(n2232) );
INVX2TS U3024 ( .A(n2961), .Y(n5211) );
NAND2X6TS U3025 ( .A(n2530), .B(n5395), .Y(n5406) );
AOI21X2TS U3026 ( .A0(n4856), .A1(n4749), .B0(n4692), .Y(n4697) );
NAND2X6TS U3027 ( .A(n2712), .B(n2713), .Y(n2631) );
INVX12TS U3028 ( .A(add_x_69_n272), .Y(n6252) );
NAND2X6TS U3029 ( .A(n2323), .B(n5153), .Y(add_x_69_n272) );
CLKMX2X2TS U3030 ( .A(n7254), .B(FPMULT_P_Sgf[18]), .S0(n7216), .Y(n1571) );
NAND2X2TS U3031 ( .A(n2669), .B(n7251), .Y(n6217) );
NAND2X4TS U3032 ( .A(n2672), .B(n2671), .Y(n2670) );
INVX4TS U3033 ( .A(n6210), .Y(n7243) );
NAND2X4TS U3034 ( .A(n2820), .B(n5126), .Y(n7251) );
INVX4TS U3035 ( .A(n2265), .Y(n2825) );
CLKMX2X2TS U3036 ( .A(n7223), .B(FPMULT_P_Sgf[13]), .S0(n8524), .Y(n1566) );
NAND2X4TS U3037 ( .A(n2970), .B(n2499), .Y(n2969) );
INVX3TS U3038 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n4680) );
CLKMX2X2TS U3039 ( .A(n7217), .B(FPMULT_P_Sgf[12]), .S0(n8525), .Y(n1565) );
NOR2X4TS U3040 ( .A(n3742), .B(n3740), .Y(n2745) );
NAND2X4TS U3041 ( .A(n3019), .B(n4635), .Y(n3018) );
INVX2TS U3042 ( .A(n5409), .Y(n5563) );
OR2X2TS U3043 ( .A(n7214), .B(n5136), .Y(n7215) );
NAND2X4TS U3044 ( .A(n5353), .B(n5354), .Y(n5566) );
CLKMX2X2TS U3045 ( .A(n7213), .B(FPMULT_P_Sgf[11]), .S0(n7253), .Y(n1564) );
NAND2X4TS U3046 ( .A(n2548), .B(n3589), .Y(n3555) );
CLKMX2X2TS U3047 ( .A(n7212), .B(FPMULT_P_Sgf[10]), .S0(n6955), .Y(n1563) );
OR2X2TS U3048 ( .A(n4813), .B(n4812), .Y(n4811) );
NAND2X4TS U3049 ( .A(n4043), .B(n4042), .Y(n4847) );
ADDHX1TS U3050 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n5787), .CO(
add_x_246_n2), .S(FPMULT_Adder_M_result_A_adder[22]) );
NAND2BX2TS U3051 ( .AN(n6817), .B(n7434), .Y(n7435) );
NAND2X2TS U3052 ( .A(n6817), .B(n7434), .Y(n8713) );
INVX6TS U3053 ( .A(n2412), .Y(n2413) );
ADDHX2TS U3054 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n6908), .CO(n5787),
.S(n6909) );
CLKMX2X2TS U3055 ( .A(n6915), .B(FPMULT_Add_result[18]), .S0(n6921), .Y(
n1606) );
ADDHX1TS U3056 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n6912), .CO(n6910),
.S(n6913) );
ADDHX2TS U3057 ( .A(n3956), .B(n3955), .CO(n3972), .S(n3974) );
INVX2TS U3058 ( .A(n5203), .Y(n5257) );
AOI211X1TS U3059 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6698), .B0(n6697), .C0(n6696), .Y(n6702) );
ADDHX1TS U3060 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n6914), .CO(n6912),
.S(n6915) );
CLKINVX2TS U3061 ( .A(n7520), .Y(n6808) );
CLKMX2X2TS U3062 ( .A(n6917), .B(FPMULT_Add_result[17]), .S0(n6921), .Y(
n1607) );
CLKMX2X2TS U3063 ( .A(n6919), .B(FPMULT_Add_result[16]), .S0(n6921), .Y(
n1608) );
ADDHX1TS U3064 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n6916), .CO(n6914),
.S(n6917) );
ADDFHX2TS U3065 ( .A(n3667), .B(n3666), .CI(n3665), .CO(n3697), .S(n3669) );
CLKMX2X2TS U3066 ( .A(FPMULT_exp_oper_result[5]), .B(n7099), .S0(n6981), .Y(
n1544) );
OR2X2TS U3067 ( .A(n4794), .B(n4793), .Y(n3176) );
ADDHX1TS U3068 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n6918), .CO(n6916),
.S(n6919) );
NAND3BX2TS U3069 ( .AN(n6014), .B(n6011), .C(n6010), .Y(n6036) );
AOI211X1TS U3070 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6698), .B0(n6067), .C0(n6058), .Y(n6671) );
CLKMX2X2TS U3071 ( .A(FPMULT_exp_oper_result[4]), .B(n7098), .S0(n6981), .Y(
n1545) );
AOI2BB2X1TS U3072 ( .B0(n7424), .B1(n7423), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n7422), .Y(n1849) );
AOI2BB2X1TS U3073 ( .B0(n6559), .B1(n7363), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n7422), .Y(n1947) );
BUFX16TS U3074 ( .A(n4001), .Y(n4108) );
CLKMX2X2TS U3075 ( .A(FPMULT_exp_oper_result[3]), .B(n7097), .S0(n6981), .Y(
n1546) );
INVX4TS U3076 ( .A(n6838), .Y(n6855) );
AOI2BB2X1TS U3077 ( .B0(n6559), .B1(n7419), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n7422), .Y(n1851) );
AOI2BB2X1TS U3078 ( .B0(FPADDSUB_left_right_SHT2), .B1(n7085), .A0N(n7081),
.A1N(n7029), .Y(n6184) );
OR2X2TS U3079 ( .A(n6336), .B(n6335), .Y(n6340) );
INVX2TS U3080 ( .A(n2442), .Y(n2271) );
INVX4TS U3081 ( .A(n2409), .Y(n2411) );
XOR2X1TS U3082 ( .A(n6593), .B(n6592), .Y(n6598) );
AOI2BB2X1TS U3083 ( .B0(n6559), .B1(n7321), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n7422), .Y(n2123) );
OR2X2TS U3084 ( .A(n1673), .B(n1661), .Y(n7717) );
AND2X2TS U3085 ( .A(n4782), .B(n4781), .Y(n4783) );
OAI21X1TS U3086 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n6065), .Y(n6066) );
NOR2X4TS U3087 ( .A(n4510), .B(n4251), .Y(n4258) );
BUFX3TS U3088 ( .A(n4026), .Y(n3072) );
NAND2BX1TS U3089 ( .AN(n2382), .B(n2442), .Y(n3789) );
MX2X1TS U3090 ( .A(FPMULT_exp_oper_result[2]), .B(n7096), .S0(n6981), .Y(
n1547) );
MX2X1TS U3091 ( .A(FPMULT_exp_oper_result[1]), .B(n7095), .S0(n6981), .Y(
n1548) );
AOI2BB2X1TS U3092 ( .B0(n6559), .B1(n7358), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n7422), .Y(n1949) );
INVX12TS U3093 ( .A(n2617), .Y(n5209) );
INVX2TS U3094 ( .A(n2268), .Y(n2269) );
INVX4TS U3095 ( .A(n7413), .Y(n6775) );
INVX4TS U3096 ( .A(n6559), .Y(n7330) );
INVX4TS U3097 ( .A(n7364), .Y(n7325) );
NAND2X1TS U3098 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(n7629), .Y(n6815) );
OR2X2TS U3099 ( .A(n1643), .B(n1631), .Y(n3148) );
NAND2X1TS U3100 ( .A(n6283), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n6286) );
INVX4TS U3101 ( .A(n7426), .Y(n6755) );
INVX4TS U3102 ( .A(n7426), .Y(n6750) );
CLKMX2X2TS U3103 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n2356), .Y(
n1679) );
NOR2X1TS U3104 ( .A(n6014), .B(n7562), .Y(n6015) );
INVX4TS U3105 ( .A(n6859), .Y(n7253) );
INVX4TS U3106 ( .A(n6859), .Y(n7216) );
NAND2X1TS U3107 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n6680)
);
INVX4TS U3108 ( .A(n6859), .Y(n6955) );
NAND3X1TS U3109 ( .A(n6059), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n7812),
.Y(n6060) );
NAND2X1TS U3110 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n6700)
);
NAND4X1TS U3111 ( .A(n8641), .B(n8640), .C(n8639), .D(n7274), .Y(n7276) );
OAI211X1TS U3112 ( .A0(n8633), .A1(n8646), .B0(n6691), .C0(n6690), .Y(n6697)
);
AO22X1TS U3113 ( .A0(n2244), .A1(Data_1[31]), .B0(n7452), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
INVX3TS U3114 ( .A(n2244), .Y(n6901) );
NAND2X1TS U3115 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B(n7629), .Y(n6814) );
AO22X1TS U3116 ( .A0(n2244), .A1(Data_2[31]), .B0(n7452), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
AOI2BB2X1TS U3117 ( .B0(n7602), .B1(n7601), .A0N(n7601), .A1N(n7602), .Y(
n7603) );
OAI21X1TS U3118 ( .A0(n6201), .A1(n6220), .B0(n6200), .Y(n6202) );
INVX4TS U3119 ( .A(n2244), .Y(n2356) );
NOR2X4TS U3120 ( .A(n6905), .B(n7811), .Y(n5774) );
AO22X1TS U3121 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[18]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
NOR2X1TS U3122 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n6064), .Y(n6068) );
AO22X1TS U3123 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[20]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22X1TS U3124 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[19]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
CLKMX2X2TS U3125 ( .A(n7803), .B(n5701), .S0(n2244), .Y(n5702) );
OR2X2TS U3126 ( .A(n3556), .B(n3557), .Y(n3185) );
INVX4TS U3127 ( .A(n7827), .Y(n6939) );
NAND2X1TS U3128 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(n7629), .Y(n6811) );
INVX1TS U3129 ( .A(n6453), .Y(n6343) );
AND2X2TS U3130 ( .A(n4735), .B(n4739), .Y(n7211) );
NAND2X4TS U3131 ( .A(n3761), .B(n2495), .Y(n3875) );
OAI21X1TS U3132 ( .A0(n7157), .A1(n6377), .B0(n6376), .Y(n6380) );
AO22X1TS U3133 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
XOR2X1TS U3134 ( .A(n6335), .B(n7743), .Y(n5770) );
AO22X1TS U3135 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22X1TS U3136 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n7658), .Y(n7924) );
AO22X1TS U3137 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[29]), .B0(n7599), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
AO22X1TS U3138 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22X1TS U3139 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n7658), .Y(n7921) );
AO22X1TS U3140 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22X1TS U3141 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22X1TS U3142 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22X1TS U3143 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
OAI211X2TS U3144 ( .A0(n2204), .A1(n8332), .B0(n8331), .C0(n5929), .Y(n7369)
);
NAND2X1TS U3145 ( .A(n2358), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n6287) );
OAI211X2TS U3146 ( .A0(n2204), .A1(n8330), .B0(n8329), .C0(n5921), .Y(n7614)
);
AO22X1TS U3147 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n7658), .Y(n7920) );
AO22X1TS U3148 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n7663), .Y(n7922) );
AO22X1TS U3149 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22X1TS U3150 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22X1TS U3151 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
AO22X1TS U3152 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22X1TS U3153 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n7658), .Y(n7923) );
AO22X1TS U3154 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n7663), .Y(n7919) );
AO22X1TS U3155 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n7663),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
AO22X1TS U3156 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[30]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
AO22X1TS U3157 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[28]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22X1TS U3158 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22X1TS U3159 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[26]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22X1TS U3160 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
OAI211X4TS U3161 ( .A0(n2202), .A1(n8350), .B0(n8349), .C0(n5879), .Y(n7398)
);
AO22X1TS U3162 ( .A0(n7648), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n7663), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
AO22X1TS U3163 ( .A0(n7089), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n7599), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22X1TS U3164 ( .A0(n7089), .A1(FPADDSUB_DMP_SFG[23]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
OAI211X4TS U3165 ( .A0(n2201), .A1(n8316), .B0(n8315), .C0(n5999), .Y(n7576)
);
AO22X1TS U3166 ( .A0(n7342), .A1(result_add_subt[2]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22X1TS U3167 ( .A0(n8643), .A1(n8523), .B0(n8644), .B1(n6854), .Y(n2150)
);
AND2X2TS U3168 ( .A(n6651), .B(n5708), .Y(n8637) );
NAND2X4TS U3169 ( .A(n6602), .B(n5708), .Y(n7452) );
AO22X1TS U3170 ( .A0(n7342), .A1(result_add_subt[1]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
OAI211X4TS U3171 ( .A0(n2202), .A1(n8346), .B0(n8345), .C0(n5875), .Y(n7395)
);
INVX4TS U3172 ( .A(n2403), .Y(n7084) );
INVX4TS U3173 ( .A(n2335), .Y(n2373) );
AO22X1TS U3174 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22X1TS U3175 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
OAI211X2TS U3176 ( .A0(n2260), .A1(n8334), .B0(n8333), .C0(n5908), .Y(n7378)
);
AO22X1TS U3177 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
OAI211X4TS U3178 ( .A0(n2260), .A1(n8400), .B0(n8399), .C0(n5953), .Y(n7638)
);
AO22X1TS U3179 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n7939), .Y(n7917) );
AO22X1TS U3180 ( .A0(n7648), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n7663), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22X1TS U3181 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22X1TS U3182 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n7663), .Y(n7918) );
AO22X1TS U3183 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n7663),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22X1TS U3184 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[25]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22X1TS U3185 ( .A0(n7089), .A1(FPADDSUB_DMP_SFG[24]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22X1TS U3186 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22X1TS U3187 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
NOR2X1TS U3188 ( .A(n2297), .B(n2342), .Y(n7265) );
INVX4TS U3189 ( .A(n7548), .Y(n7557) );
INVX2TS U3190 ( .A(n3878), .Y(n2539) );
INVX2TS U3191 ( .A(FPMULT_Op_MX[20]), .Y(n2771) );
INVX4TS U3192 ( .A(n7548), .Y(n7629) );
NOR2X4TS U3193 ( .A(n3232), .B(n2320), .Y(n3282) );
INVX4TS U3194 ( .A(n7548), .Y(n7622) );
AND2X4TS U3195 ( .A(n7732), .B(DP_OP_496J211_122_3540_n1120), .Y(n3908) );
AO22XLTS U3196 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n7287),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND3X1TS U3197 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n8642),
.C(n7795), .Y(n7288) );
INVX4TS U3198 ( .A(n7798), .Y(n7303) );
INVX1TS U3199 ( .A(DP_OP_496J211_122_3540_n1514), .Y(n7467) );
INVX8TS U3200 ( .A(DP_OP_496J211_122_3540_n1472), .Y(n4255) );
CLKMX2X2TS U3201 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(n6979) );
CLKMX2X2TS U3202 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(n6957) );
CLKMX2X2TS U3203 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(n6960) );
CLKMX2X2TS U3204 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(n6964) );
OR2X2TS U3205 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n6158) );
OR2X2TS U3206 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n5867) );
INVX4TS U3207 ( .A(add_x_69_n201), .Y(n5004) );
MX2X2TS U3208 ( .A(n6253), .B(FPMULT_P_Sgf[20]), .S0(n7216), .Y(n1573) );
NAND2X4TS U3209 ( .A(n2505), .B(n2504), .Y(n5440) );
NAND2X4TS U3210 ( .A(n5741), .B(n3122), .Y(n3121) );
XNOR2X2TS U3211 ( .A(n6217), .B(n6216), .Y(n6218) );
NAND2X6TS U3212 ( .A(n3063), .B(n5324), .Y(n2510) );
OR2X2TS U3213 ( .A(n5667), .B(n3192), .Y(n5669) );
CLKMX2X2TS U3214 ( .A(n7239), .B(FPMULT_P_Sgf[16]), .S0(n8525), .Y(n1569) );
NAND2X4TS U3215 ( .A(n5481), .B(n5482), .Y(n6249) );
NAND2X6TS U3216 ( .A(n2926), .B(n5727), .Y(n2568) );
CLKMX2X2TS U3217 ( .A(n7236), .B(FPMULT_P_Sgf[15]), .S0(n8524), .Y(n1568) );
NAND2X4TS U3218 ( .A(n2503), .B(n4901), .Y(n2502) );
INVX8TS U3219 ( .A(n5161), .Y(add_x_69_n59) );
NOR2X1TS U3220 ( .A(n5723), .B(n5722), .Y(add_x_69_n85) );
NAND2X4TS U3221 ( .A(n5718), .B(n4903), .Y(n2524) );
CLKMX2X2TS U3222 ( .A(n7227), .B(FPMULT_P_Sgf[14]), .S0(n8525), .Y(n1567) );
INVX8TS U3223 ( .A(n4902), .Y(n5718) );
INVX6TS U3224 ( .A(n5719), .Y(n5300) );
INVX2TS U3225 ( .A(n3171), .Y(add_x_69_n113) );
NAND2X2TS U3226 ( .A(n3712), .B(n5154), .Y(n3713) );
BUFX16TS U3227 ( .A(n2830), .Y(n2823) );
NAND3X4TS U3228 ( .A(n2318), .B(n2972), .C(n3740), .Y(n2971) );
NAND3X6TS U3229 ( .A(n2847), .B(n2846), .C(n4950), .Y(n2845) );
NAND2X6TS U3230 ( .A(n3560), .B(n3559), .Y(n3740) );
NAND2X6TS U3231 ( .A(n5237), .B(n5236), .Y(n5328) );
NAND3X4TS U3232 ( .A(n2827), .B(n2826), .C(n5100), .Y(n2527) );
INVX3TS U3233 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n4878) );
INVX2TS U3234 ( .A(n5592), .Y(n5585) );
INVX4TS U3235 ( .A(n3718), .Y(n2236) );
NAND2X4TS U3236 ( .A(n2989), .B(n2988), .Y(n5409) );
NOR2X6TS U3237 ( .A(n5428), .B(n5427), .Y(n5565) );
NAND2X4TS U3238 ( .A(n4644), .B(n4642), .Y(n2715) );
INVX4TS U3239 ( .A(n4905), .Y(n2583) );
NAND2X4TS U3240 ( .A(n2763), .B(n2753), .Y(n2752) );
XNOR2X1TS U3241 ( .A(n5637), .B(n5636), .Y(n5649) );
ADDFHX2TS U3242 ( .A(n5412), .B(n5411), .CI(n5410), .CO(n5428), .S(n5353) );
OAI21X1TS U3243 ( .A0(n5660), .A1(n5659), .B0(n5658), .Y(n5666) );
ADDFHX2TS U3244 ( .A(n5426), .B(n5425), .CI(n5424), .CO(n5567), .S(n5411) );
AO22X1TS U3245 ( .A0(n7091), .A1(n6371), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n7599), .Y(n1353) );
NOR2X2TS U3246 ( .A(n1318), .B(n1319), .Y(n8414) );
AND2X4TS U3247 ( .A(n3660), .B(n3695), .Y(n3652) );
OAI2BB1X2TS U3248 ( .A0N(n6599), .A1N(n6108), .B0(n6107), .Y(n1317) );
INVX2TS U3249 ( .A(n7209), .Y(n4864) );
NAND2X4TS U3250 ( .A(n2753), .B(n3083), .Y(n2751) );
ADDFHX2TS U3251 ( .A(n5247), .B(n5246), .CI(n5245), .CO(n5352), .S(n5244) );
NOR2X1TS U3252 ( .A(n5571), .B(n2354), .Y(n5573) );
NOR2X1TS U3253 ( .A(n6858), .B(n8713), .Y(n8752) );
CLKMX2X2TS U3254 ( .A(n6909), .B(FPMULT_Add_result[21]), .S0(n6943), .Y(
n1603) );
NAND2X4TS U3255 ( .A(n2803), .B(n2802), .Y(n4824) );
INVX4TS U3256 ( .A(n2412), .Y(n2374) );
XOR2X1TS U3257 ( .A(n6113), .B(n6112), .Y(n6118) );
OAI21X1TS U3258 ( .A0(n5654), .A1(n5653), .B0(n5652), .Y(n5655) );
ADDFHX2TS U3259 ( .A(n5257), .B(n5256), .CI(n5255), .CO(n5336), .S(n5243) );
CLKMX2X2TS U3260 ( .A(n6911), .B(FPMULT_Add_result[20]), .S0(n6943), .Y(
n1604) );
OAI211X1TS U3261 ( .A0(n6568), .A1(n7548), .B0(n6816), .C0(n6567), .Y(n1473)
);
CLKMX2X2TS U3262 ( .A(n6913), .B(FPMULT_Add_result[19]), .S0(n6921), .Y(
n1605) );
AOI2BB2X1TS U3263 ( .B0(n8523), .B1(n7597), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n8523), .Y(n1364) );
ADDHX2TS U3264 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n6910), .CO(n6908),
.S(n6911) );
NAND2X1TS U3265 ( .A(n3064), .B(n5272), .Y(n4948) );
INVX4TS U3266 ( .A(n5549), .Y(n4925) );
NOR2X1TS U3267 ( .A(n6600), .B(n1336), .Y(n8293) );
OAI21X1TS U3268 ( .A0(n8612), .A1(n2343), .B0(n6809), .Y(n1358) );
INVX2TS U3269 ( .A(n5604), .Y(n5219) );
OAI21X1TS U3270 ( .A0(n6808), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n7521),
.Y(n6809) );
OAI21X1TS U3271 ( .A0(n6684), .A1(n6832), .B0(n6672), .Y(n2079) );
AO21X1TS U3272 ( .A0(underflow_flag_addsubt), .A1(n7548), .B0(n7519), .Y(
n1414) );
OAI211X2TS U3273 ( .A0(n6071), .A1(n7857), .B0(n6070), .C0(n6691), .Y(n7092)
);
AOI2BB1X1TS U3274 ( .A0N(n7629), .A1N(overflow_flag_addsubt), .B0(n7521),
.Y(n1413) );
AND2X2TS U3275 ( .A(n3751), .B(n5273), .Y(n4901) );
AO22X1TS U3276 ( .A0(n7521), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(
result_add_subt[30]), .B1(n7548), .Y(n1468) );
INVX2TS U3277 ( .A(n2766), .Y(n3291) );
AO21X1TS U3278 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n6539), .B0(
n6906), .Y(n1625) );
XOR2X1TS U3279 ( .A(n6132), .B(n6131), .Y(n6137) );
OAI21X1TS U3280 ( .A0(n2296), .A1(n6684), .B0(n6683), .Y(n1320) );
OAI21X1TS U3281 ( .A0(n6702), .A1(n8526), .B0(n6700), .Y(n1324) );
OAI21X1TS U3282 ( .A0(n6702), .A1(n6840), .B0(n6701), .Y(n2078) );
ADDFHX2TS U3283 ( .A(n4020), .B(n4019), .CI(n4018), .CO(n4034), .S(n4032) );
OAI2BB1X2TS U3284 ( .A0N(n3505), .A1N(n3046), .B0(n3494), .Y(n3045) );
CLKMX2X2TS U3285 ( .A(FPMULT_exp_oper_result[7]), .B(n7103), .S0(n6981), .Y(
n1542) );
NAND2BX2TS U3286 ( .AN(n5418), .B(n4632), .Y(n5575) );
INVX3TS U3287 ( .A(n5275), .Y(n4051) );
NAND3BX1TS U3288 ( .AN(n7103), .B(n7480), .C(n7102), .Y(n7104) );
ADDFHX2TS U3289 ( .A(n5178), .B(n5177), .CI(n5176), .CO(n5200), .S(n5185) );
AOI211X1TS U3290 ( .A0(n2489), .A1(n6068), .B0(n6067), .C0(n6678), .Y(n6070)
);
AO21X1TS U3291 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n8526), .B0(n7093),
.Y(n1316) );
NOR2X1TS U3292 ( .A(n6649), .B(n6892), .Y(n6650) );
XOR2X1TS U3293 ( .A(n6151), .B(n6150), .Y(n6156) );
OAI21X1TS U3294 ( .A0(n5618), .A1(n5396), .B0(n5398), .Y(n5160) );
OAI21X1TS U3295 ( .A0(n5618), .A1(n5617), .B0(n5556), .Y(n5558) );
NAND2BX1TS U3296 ( .AN(n6649), .B(n6892), .Y(n6621) );
NAND4BX1TS U3297 ( .AN(n7101), .B(n7100), .C(n7099), .D(n7098), .Y(n7102) );
NAND2X4TS U3298 ( .A(n3387), .B(n3386), .Y(n3490) );
ADDFHX2TS U3299 ( .A(n3404), .B(n3403), .CI(n3402), .CO(n3457), .S(n3426) );
CLKMX2X2TS U3300 ( .A(FPMULT_exp_oper_result[6]), .B(n7100), .S0(n6981), .Y(
n1543) );
INVX12TS U3301 ( .A(n2353), .Y(n5345) );
ADDFHX2TS U3302 ( .A(n4631), .B(n4630), .CI(n4629), .CO(n4632), .S(n5262) );
NOR2BX2TS U3303 ( .AN(n4108), .B(n2353), .Y(n4920) );
NOR2X1TS U3304 ( .A(n6763), .B(n7284), .Y(n6040) );
INVX3TS U3305 ( .A(n3274), .Y(n3474) );
OAI21X1TS U3306 ( .A0(n6727), .A1(n6778), .B0(n6726), .Y(n1697) );
AO22X1TS U3307 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n7405), .Y(n1905) );
AO22X1TS U3308 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n7482), .B0(
mult_result[11]), .B1(n7483), .Y(n1504) );
AO22X1TS U3309 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n7405), .Y(n1963) );
AO22X1TS U3310 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n7414), .Y(n1871) );
AO22X1TS U3311 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n7482), .B0(
mult_result[10]), .B1(n7483), .Y(n1505) );
OAI21X1TS U3312 ( .A0(n6604), .A1(n6482), .B0(n6481), .Y(n6483) );
AO22X1TS U3313 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n7482), .B0(
mult_result[9]), .B1(n7493), .Y(n1506) );
AO22X1TS U3314 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n7416), .Y(n1860) );
AO22X1TS U3315 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n7414), .Y(n1863) );
NAND2X6TS U3316 ( .A(n4093), .B(n3915), .Y(n4094) );
AO22X1TS U3317 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n7416), .Y(n1859) );
AO22X1TS U3318 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n7416), .Y(n1857) );
AO22X1TS U3319 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n7414), .Y(n1861) );
AO22X1TS U3320 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n7482), .B0(
mult_result[8]), .B1(n7483), .Y(n1507) );
AO22X1TS U3321 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n7414), .Y(n1862) );
AO22X1TS U3322 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n7414), .Y(n1873) );
AO21X1TS U3323 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n7515), .B0(n6185),
.Y(n1182) );
AO22X1TS U3324 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n7482), .B0(
mult_result[7]), .B1(n7493), .Y(n1508) );
AO22X1TS U3325 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n7484), .B0(
mult_result[20]), .B1(n7489), .Y(n1495) );
AO22X1TS U3326 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n7411), .Y(n1889) );
AO22X1TS U3327 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n7484), .B0(
mult_result[21]), .B1(n7489), .Y(n1494) );
AO22X1TS U3328 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n7405), .Y(n1907) );
AO22X1TS U3329 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n7482), .B0(
mult_result[6]), .B1(n7493), .Y(n1509) );
OAI21X1TS U3330 ( .A0(n5703), .A1(n7691), .B0(n5704), .Y(n7693) );
INVX4TS U3331 ( .A(n2512), .Y(n2237) );
AO22X1TS U3332 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n7484), .B0(
mult_result[22]), .B1(n7489), .Y(n1493) );
AO22X1TS U3333 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n7411), .Y(n1893) );
AO22X1TS U3334 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n7417), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n7416), .Y(n2007) );
CLKAND2X2TS U3335 ( .A(n3498), .B(n3506), .Y(n2308) );
AO22X1TS U3336 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n7482), .B0(
mult_result[15]), .B1(n7483), .Y(n1500) );
AO22X1TS U3337 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n7405), .Y(n1901) );
AO22X1TS U3338 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n7414), .Y(n1867) );
AO22X1TS U3339 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n7417), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n7416), .Y(n1999) );
OAI21X1TS U3340 ( .A0(n6604), .A1(n6471), .B0(n6470), .Y(n6472) );
AO22X1TS U3341 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n7405), .Y(n1961) );
AO22X1TS U3342 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n7405), .Y(n1965) );
AO22X1TS U3343 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n7411), .Y(n1881) );
ADDFHX2TS U3344 ( .A(n3369), .B(n3368), .CI(n3367), .CO(n3380), .S(n3378) );
AO22X1TS U3345 ( .A0(n7512), .A1(n7506), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
AO22X1TS U3346 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n7484), .B0(
mult_result[16]), .B1(n7483), .Y(n1499) );
AO22X1TS U3347 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n7482), .B0(
mult_result[14]), .B1(n7483), .Y(n1501) );
AO22X1TS U3348 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n7416), .Y(n1856) );
AO22X1TS U3349 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n7484), .B0(
mult_result[17]), .B1(n7483), .Y(n1498) );
AO22X1TS U3350 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n7482), .B0(
mult_result[13]), .B1(n7483), .Y(n1502) );
AO22X1TS U3351 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n7414), .Y(n1875) );
NOR2X1TS U3352 ( .A(n2435), .B(DP_OP_497J211_123_1725_n324), .Y(n3698) );
AO22X1TS U3353 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n7416), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n7367), .Y(n1945) );
AO22X1TS U3354 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n7414), .Y(n1877) );
AO22X1TS U3355 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n7484), .B0(
mult_result[18]), .B1(n7483), .Y(n1497) );
AO22X1TS U3356 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n7411), .Y(n1883) );
AO22X1TS U3357 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n7405), .Y(n1903) );
OAI21X1TS U3358 ( .A0(n6604), .A1(n6514), .B0(n6513), .Y(n6515) );
AO22X1TS U3359 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n7414), .Y(n1869) );
OAI21X1TS U3360 ( .A0(n6604), .A1(n6504), .B0(n6503), .Y(n6505) );
AO22X1TS U3361 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n7484), .B0(
mult_result[19]), .B1(n7489), .Y(n1496) );
AO22X1TS U3362 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n7405), .Y(n1954) );
AO22X1TS U3363 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n7411), .Y(n1897) );
AO22X1TS U3364 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n7411), .Y(n1891) );
AO22X1TS U3365 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n7482), .B0(
mult_result[12]), .B1(n7483), .Y(n1503) );
AO22X1TS U3366 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n7489), .Y(n1513) );
AO22X1TS U3367 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n7405), .Y(n1899) );
OAI21X1TS U3368 ( .A0(n5082), .A1(n5111), .B0(n5113), .Y(n5087) );
AO22X1TS U3369 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n7414), .Y(n1865) );
NAND2X2TS U3370 ( .A(n4191), .B(n4190), .Y(n4192) );
AO22X1TS U3371 ( .A0(n7355), .A1(n6560), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
AO22X1TS U3372 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n7481), .B0(
mult_result[3]), .B1(n7489), .Y(n1512) );
AO22X1TS U3373 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n7489), .Y(n1514) );
AO22X1TS U3374 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n7405), .Y(n1909) );
AO22X1TS U3375 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n7411), .Y(n1879) );
OAI21X1TS U3376 ( .A0(n7434), .A1(n6570), .B0(n6855), .Y(n2081) );
AO22X1TS U3377 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n7481), .B0(
mult_result[4]), .B1(n7493), .Y(n1511) );
AO22X1TS U3378 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n7416), .Y(n1858) );
AO22X1TS U3379 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n7411), .Y(n1887) );
AO22X1TS U3380 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n7481), .B0(
mult_result[5]), .B1(n7493), .Y(n1510) );
XOR2X1TS U3381 ( .A(n6074), .B(n5864), .Y(n5872) );
AO22X1TS U3382 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n7411), .Y(n1885) );
AO22X1TS U3383 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n7489), .Y(n1515) );
AO22X1TS U3384 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n7411), .Y(n1895) );
AO22X1TS U3385 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n2407), .Y(n1985) );
OAI21X1TS U3386 ( .A0(n7321), .A1(n7322), .B0(n6633), .Y(n2135) );
OAI21X1TS U3387 ( .A0(n7319), .A1(n7327), .B0(n6637), .Y(n2119) );
AO22X1TS U3388 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n2407), .Y(n1977) );
AO22X1TS U3389 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n7331), .B1(
Data_1[2]), .Y(n2112) );
NAND2BX1TS U3390 ( .AN(n7316), .B(n7315), .Y(n2125) );
OAI21X1TS U3391 ( .A0(n7713), .A1(n5709), .B0(n5710), .Y(n7718) );
OAI21X1TS U3392 ( .A0(n3508), .A1(n3507), .B0(n3506), .Y(n3509) );
OAI21X1TS U3393 ( .A0(n2361), .A1(n7320), .B0(n6655), .Y(n2118) );
OAI21X1TS U3394 ( .A0(n5504), .A1(n5503), .B0(n5502), .Y(n5505) );
AO22X1TS U3395 ( .A0(n7428), .A1(n6550), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
AO22X1TS U3396 ( .A0(n7444), .A1(n7366), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
CLKMX2X2TS U3397 ( .A(FPMULT_exp_oper_result[0]), .B(n7094), .S0(n6981), .Y(
n1549) );
NOR2X1TS U3398 ( .A(n7696), .B(n7690), .Y(n7695) );
OAI21X1TS U3399 ( .A0(n7329), .A1(n6636), .B0(n6635), .Y(n2133) );
OAI21X1TS U3400 ( .A0(n7330), .A1(intadd_480_CI), .B0(n6644), .Y(n1953) );
INVX2TS U3401 ( .A(n4574), .Y(n4575) );
OAI21X1TS U3402 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n7329), .B0(n6639),
.Y(n2116) );
AOI2BB2X1TS U3403 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n7420), .A0N(n7420),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n6560) );
OAI21X1TS U3404 ( .A0(n7330), .A1(intadd_479_CI), .B0(n6642), .Y(n1855) );
AO22X1TS U3405 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n7331), .B1(
Data_1[7]), .Y(n2107) );
AO22X1TS U3406 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n7331), .B1(
Data_1[8]), .Y(n2106) );
NOR2X4TS U3407 ( .A(n3728), .B(n3250), .Y(n3252) );
AO22X1TS U3408 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n7337), .B1(
Data_1[28]), .Y(n2086) );
AO22X1TS U3409 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n7308), .B1(
Data_1[13]), .Y(n2101) );
AO22X1TS U3410 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n7337), .B1(
Data_1[27]), .Y(n2087) );
OAI21X1TS U3411 ( .A0(n6604), .A1(n6532), .B0(n6531), .Y(n6533) );
AO22X1TS U3412 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n7334), .B1(
Data_1[14]), .Y(n2100) );
AO22X1TS U3413 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n7334), .B1(
Data_1[15]), .Y(n2099) );
AO22X1TS U3414 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n7335), .B1(
Data_1[26]), .Y(n2088) );
AO22X1TS U3415 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n7335), .B1(
Data_1[16]), .Y(n2098) );
OR2X2TS U3416 ( .A(n7690), .B(n7689), .Y(n7691) );
OAI21X1TS U3417 ( .A0(n6604), .A1(n6523), .B0(n6522), .Y(n6524) );
AO22X1TS U3418 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n7335), .B1(
Data_1[25]), .Y(n2089) );
AO22X1TS U3419 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n7335), .B1(
Data_1[17]), .Y(n2097) );
AO22X1TS U3420 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n7335), .B1(
Data_1[24]), .Y(n2090) );
AOI222X1TS U3421 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n6732) );
AO22X1TS U3422 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n7335), .B1(
Data_1[18]), .Y(n2096) );
OAI211X1TS U3423 ( .A0(n6985), .A1(n7478), .B0(n6617), .C0(n6440), .Y(n1695)
);
OAI21X1TS U3424 ( .A0(n2350), .A1(n6620), .B0(n6619), .Y(n1692) );
AO22X1TS U3425 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n7334), .B1(
Data_1[22]), .Y(n2092) );
AO22X1TS U3426 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n7335), .B1(
Data_1[21]), .Y(n2093) );
AO22X1TS U3427 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n7335), .B1(
Data_1[19]), .Y(n2095) );
AO22X1TS U3428 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n7335), .B1(
Data_1[20]), .Y(n2094) );
AO22X1TS U3429 ( .A0(n7512), .A1(n6448), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
NAND4BX1TS U3430 ( .AN(n1644), .B(n6877), .C(n6876), .D(n6875), .Y(n8062) );
AO22X1TS U3431 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n7331), .B1(
Data_1[4]), .Y(n2110) );
AO22X1TS U3432 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n7337), .B1(
Data_1[31]), .Y(n2083) );
AO22X1TS U3433 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n7337), .B1(
Data_1[29]), .Y(n2085) );
AO22X1TS U3434 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n7331), .B1(
Data_1[3]), .Y(n2111) );
AO22X1TS U3435 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n7331), .B1(
Data_1[5]), .Y(n2109) );
AO22X1TS U3436 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n7337), .B1(
Data_1[30]), .Y(n2084) );
INVX8TS U3437 ( .A(n3421), .Y(n3664) );
AO22X1TS U3438 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n7331), .B1(
Data_1[6]), .Y(n2108) );
AO22X1TS U3439 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[3]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
AO22X1TS U3440 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
NAND2X6TS U3441 ( .A(n3067), .B(n3747), .Y(n3856) );
AO22X1TS U3442 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[7]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
AO22X1TS U3443 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n7422),
.B1(FPSENCOS_d_ff2_X[21]), .Y(n1964) );
AO22X1TS U3444 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[15]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
AO22X1TS U3445 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
INVX4TS U3446 ( .A(n4258), .Y(n2238) );
AO22X1TS U3447 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22X1TS U3448 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22X1TS U3449 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[2]), .Y(n2002) );
NAND2X1TS U3450 ( .A(n5366), .B(n5365), .Y(n5386) );
AO22X1TS U3451 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[0]), .Y(n2006) );
NAND3X1TS U3452 ( .A(n7279), .B(n7325), .C(n7286), .Y(n7280) );
AO22X1TS U3453 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22X1TS U3454 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
NOR2X1TS U3455 ( .A(n7062), .B(n7029), .Y(n7020) );
AO22X1TS U3456 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n7422),
.B1(FPSENCOS_d_ff2_X[12]), .Y(n1982) );
AO22X1TS U3457 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[22]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22X1TS U3458 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22X1TS U3459 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
INVX4TS U3460 ( .A(n3965), .Y(n2239) );
AO22X1TS U3461 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
NOR2X1TS U3462 ( .A(n1642), .B(n1630), .Y(n7714) );
OAI21X1TS U3463 ( .A0(n7788), .A1(n6653), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n6617) );
INVX1TS U3464 ( .A(n4521), .Y(n2614) );
NOR2X1TS U3465 ( .A(n1674), .B(n1662), .Y(n7715) );
NAND2X6TS U3466 ( .A(n4026), .B(n3075), .Y(n3993) );
AO22X1TS U3467 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
NOR2X1TS U3468 ( .A(n1672), .B(n1660), .Y(n7719) );
NAND4BX1TS U3469 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n6562), .C(n6561),
.D(n6568), .Y(n6563) );
AO22X1TS U3470 ( .A0(n7428), .A1(FPSENCOS_d_ff2_X[31]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
NOR2X1TS U3471 ( .A(n1641), .B(n1629), .Y(n7721) );
AO22X1TS U3472 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22X1TS U3473 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n7422),
.B1(intadd_480_SUM_2_), .Y(n1950) );
AO22X1TS U3474 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n7422),
.B1(intadd_480_SUM_1_), .Y(n1951) );
AO22X1TS U3475 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1734) );
AO22X1TS U3476 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n7334), .B1(
Data_1[9]), .Y(n2105) );
AO22X1TS U3477 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n7422),
.B1(intadd_480_SUM_0_), .Y(n1952) );
AOI211X1TS U3478 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n6653), .B0(n7480), .C0(n7487), .Y(n6619) );
AO22X1TS U3479 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n7308), .B1(
Data_1[10]), .Y(n2104) );
AO22X1TS U3480 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n7308), .B1(
Data_1[11]), .Y(n2103) );
AO22X1TS U3481 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n7308), .B1(
Data_1[12]), .Y(n2102) );
AO22X1TS U3482 ( .A0(n7512), .A1(n6437), .B0(n7634), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
OAI21X1TS U3483 ( .A0(n6604), .A1(n6465), .B0(n6464), .Y(n6466) );
AO22X1TS U3484 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22X1TS U3485 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
OAI21X1TS U3486 ( .A0(n7491), .A1(underflow_flag_mult), .B0(n7490), .Y(n7492) );
AO22X1TS U3487 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
OAI21X1TS U3488 ( .A0(n7418), .A1(n8679), .B0(n7421), .Y(n6550) );
AO22X1TS U3489 ( .A0(n7361), .A1(intadd_479_SUM_2_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
AO22X1TS U3490 ( .A0(n7361), .A1(intadd_479_SUM_1_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
AO22X1TS U3491 ( .A0(n7361), .A1(intadd_479_SUM_0_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22X1TS U3492 ( .A0(n7409), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22X1TS U3493 ( .A0(n7333), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n7331), .B1(region_flag[1]), .Y(n2136) );
AO22X1TS U3494 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[6]), .Y(n1994) );
NAND2BX1TS U3495 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n7330), .Y(n2115) );
AO22X1TS U3496 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[17]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
ADDFHX2TS U3497 ( .A(n3615), .B(n3614), .CI(n3613), .CO(n3641), .S(n3598) );
AO22X1TS U3498 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[5]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
BUFX12TS U3499 ( .A(n2777), .Y(n3610) );
OR2X2TS U3500 ( .A(n6605), .B(n6604), .Y(n6611) );
OAI21X1TS U3501 ( .A0(n2356), .A1(n2938), .B0(n2937), .Y(n1675) );
AO22X1TS U3502 ( .A0(n7410), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22X1TS U3503 ( .A0(n7333), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n7334), .B1(region_flag[0]), .Y(n2137) );
AO22X1TS U3504 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[9]), .Y(n1988) );
INVX1TS U3505 ( .A(n1643), .Y(n6877) );
INVX1TS U3506 ( .A(n1642), .Y(n6876) );
AO22X1TS U3507 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22X1TS U3508 ( .A0(n7409), .A1(FPSENCOS_d_ff2_X[13]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
AO22X1TS U3509 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22X1TS U3510 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22X1TS U3511 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[16]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
AO22X1TS U3512 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n7335), .B1(
Data_1[23]), .Y(n2091) );
AO22X1TS U3513 ( .A0(n7410), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22X1TS U3514 ( .A0(n7424), .A1(n7319), .B0(n7353), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
AO22X1TS U3515 ( .A0(n7428), .A1(intadd_479_B_1_), .B0(n7357), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
OAI21X1TS U3516 ( .A0(n6601), .A1(n7285), .B0(n7330), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
AO22X1TS U3517 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n7331), .B1(
Data_1[1]), .Y(n2113) );
AO22X1TS U3518 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[1]), .Y(n2004) );
ADDFHX2TS U3519 ( .A(n4447), .B(n4446), .CI(n4445), .CO(n4492), .S(n4437) );
AO22X1TS U3520 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n7331), .B1(
Data_1[0]), .Y(n2114) );
AO22X1TS U3521 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[14]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22X1TS U3522 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n7515),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
AO22X1TS U3523 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22X1TS U3524 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22X1TS U3525 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22X1TS U3526 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n7515),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22X1TS U3527 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22X1TS U3528 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
ADDFHX2TS U3529 ( .A(n3415), .B(n3414), .CI(n3413), .CO(n3432), .S(n3416) );
NAND2BX1TS U3530 ( .AN(n3158), .B(n8524), .Y(n5523) );
OAI21X1TS U3531 ( .A0(n6335), .A1(n6204), .B0(n6203), .Y(n6207) );
AO22X1TS U3532 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[11]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
AO22X1TS U3533 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22X1TS U3534 ( .A0(n7361), .A1(n7360), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
AO22X1TS U3535 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[10]), .Y(n1986) );
NOR2X1TS U3536 ( .A(n7055), .B(n2339), .Y(n7056) );
OAI21X1TS U3537 ( .A0(n6335), .A1(n6223), .B0(n6222), .Y(n6226) );
AO22X1TS U3538 ( .A0(n6989), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n7598), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
NOR2X1TS U3539 ( .A(n7058), .B(n7029), .Y(n7023) );
AO22X1TS U3540 ( .A0(n7508), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22X1TS U3541 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
NOR2X1TS U3542 ( .A(n7051), .B(n7029), .Y(n7030) );
CLKMX2X2TS U3543 ( .A(Data_2[18]), .B(DP_OP_496J211_122_3540_n1462), .S0(
n6901), .Y(n1645) );
AO22X1TS U3544 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
XOR2X1TS U3545 ( .A(n4520), .B(n4567), .Y(n4521) );
OAI21X1TS U3546 ( .A0(n7359), .A1(n7860), .B0(n7362), .Y(n7360) );
AO22X1TS U3547 ( .A0(n7508), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
NOR2X1TS U3548 ( .A(n6606), .B(n2246), .Y(n6501) );
NOR2X1TS U3549 ( .A(n7065), .B(n2339), .Y(n7066) );
CLKMX2X2TS U3550 ( .A(Data_2[11]), .B(DP_OP_496J211_122_3540_n1478), .S0(
n2357), .Y(n1638) );
CLKMX2X2TS U3551 ( .A(Data_2[13]), .B(n8485), .S0(n6962), .Y(
DP_OP_497J211_123_1725_n779) );
CLKMX2X2TS U3552 ( .A(Data_2[5]), .B(n6860), .S0(n2357), .Y(n1632) );
OAI21X1TS U3553 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n6943), .B0(
n6569), .Y(n1624) );
NOR2X1TS U3554 ( .A(n7055), .B(n7029), .Y(n7026) );
NOR2X1TS U3555 ( .A(n7065), .B(n7029), .Y(n7017) );
NOR2X1TS U3556 ( .A(n7058), .B(n2339), .Y(n7059) );
OAI211X1TS U3557 ( .A0(n7409), .A1(n7909), .B0(n6640), .C0(n6656), .Y(n2132)
);
AO22X1TS U3558 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
NOR2X1TS U3559 ( .A(n7051), .B(n2339), .Y(n7053) );
AO22X1TS U3560 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
CLKMX2X2TS U3561 ( .A(Data_2[1]), .B(DP_OP_498J211_124_1725_n789), .S0(n6901), .Y(n1628) );
CLKMX2X2TS U3562 ( .A(Data_1[12]), .B(n7468), .S0(n2357), .Y(n1671) );
CLKMX2X2TS U3563 ( .A(Data_2[14]), .B(n5707), .S0(n6962), .Y(n1641) );
CLKMX2X2TS U3564 ( .A(Data_1[15]), .B(DP_OP_497J211_123_1725_n794), .S0(
n2356), .Y(n1674) );
CLKMX2X2TS U3565 ( .A(Data_1[8]), .B(DP_OP_496J211_122_3540_n1514), .S0(
n7452), .Y(n1667) );
CLKMX2X2TS U3566 ( .A(Data_2[17]), .B(DP_OP_496J211_122_3540_n1461), .S0(
n6962), .Y(n1644) );
CLKMX2X2TS U3567 ( .A(Data_1[5]), .B(n8519), .S0(n7452), .Y(n1664) );
CLKMX2X2TS U3568 ( .A(Data_1[17]), .B(DP_OP_496J211_122_3540_n1498), .S0(
n2356), .Y(n1676) );
CLKMX2X2TS U3569 ( .A(Data_1[13]), .B(n8481), .S0(n2357), .Y(n1672) );
NOR2X1TS U3570 ( .A(n6606), .B(n7759), .Y(n6529) );
NOR2X4TS U3571 ( .A(n6755), .B(n6731), .Y(n6736) );
CLKMX2X2TS U3572 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n2357), .Y(
n1637) );
AOI2BB2X1TS U3573 ( .B0(n7307), .B1(n7819), .A0N(n7819), .A1N(n7307), .Y(
n2139) );
NOR2X1TS U3574 ( .A(n6606), .B(n7761), .Y(n6511) );
CLKMX2X2TS U3575 ( .A(Data_2[19]), .B(DP_OP_496J211_122_3540_n778), .S0(
n6901), .Y(n1646) );
NOR2X1TS U3576 ( .A(n6606), .B(n7760), .Y(n6520) );
AO22X1TS U3577 ( .A0(n7512), .A1(n7497), .B0(n7634), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
OAI211X1TS U3578 ( .A0(n7377), .A1(n5970), .B0(n5969), .C0(n5973), .Y(n5985)
);
NOR2X1TS U3579 ( .A(n5966), .B(n7566), .Y(n5967) );
NOR2X1TS U3580 ( .A(n2339), .B(n7081), .Y(n7083) );
NAND3X1TS U3581 ( .A(n5970), .B(n5969), .C(n7377), .Y(n5971) );
NAND2XLTS U3582 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n6573) );
OAI21X1TS U3583 ( .A0(n6414), .A1(n6363), .B0(n6362), .Y(n6366) );
INVX6TS U3584 ( .A(n3818), .Y(n2242) );
OAI21X1TS U3585 ( .A0(n6335), .A1(n6306), .B0(n6305), .Y(n6309) );
NOR2X4TS U3586 ( .A(FPMULT_FSM_selector_C), .B(n5769), .Y(n5768) );
NAND3X4TS U3587 ( .A(n2666), .B(n2664), .C(n4404), .Y(n4343) );
OAI21X1TS U3588 ( .A0(n6335), .A1(n6318), .B0(n6317), .Y(n6323) );
OAI211X2TS U3589 ( .A0(n7381), .A1(n5963), .B0(n5981), .C0(n5962), .Y(n5983)
);
OAI21X1TS U3590 ( .A0(n7180), .A1(n7135), .B0(n7144), .Y(n7137) );
NOR2X1TS U3591 ( .A(n7071), .B(n2339), .Y(n7072) );
OAI21X1TS U3592 ( .A0(n7190), .A1(n7143), .B0(n7142), .Y(n7147) );
OAI21X1TS U3593 ( .A0(n7180), .A1(n7179), .B0(n7178), .Y(n7182) );
OAI21X1TS U3594 ( .A0(n7193), .A1(n7192), .B0(n7191), .Y(n7195) );
NOR2X1TS U3595 ( .A(n7068), .B(n2339), .Y(n7069) );
NOR2X1TS U3596 ( .A(n7077), .B(n7029), .Y(n6997) );
NOR2X1TS U3597 ( .A(n7068), .B(n7029), .Y(n7014) );
AO22X1TS U3598 ( .A0(n8523), .A1(n7603), .B0(n6862), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO21X1TS U3599 ( .A0(n7293), .A1(begin_operation), .B0(n2492), .Y(n6616) );
NOR2X1TS U3600 ( .A(n6032), .B(n7575), .Y(n5877) );
NOR2X1TS U3601 ( .A(n7074), .B(n2339), .Y(n7075) );
INVX2TS U3602 ( .A(n3449), .Y(n2886) );
OAI211X2TS U3603 ( .A0(n7391), .A1(n6001), .B0(n6029), .C0(n6000), .Y(n6022)
);
ADDHX2TS U3604 ( .A(n3411), .B(n3410), .CO(n3430), .S(n3405) );
AO22X1TS U3605 ( .A0(n7512), .A1(n7500), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
NOR2X1TS U3606 ( .A(n6478), .B(n7765), .Y(n6462) );
ADDFHX2TS U3607 ( .A(n3332), .B(n3331), .CI(n3330), .CO(n3364), .S(n3371) );
NOR2X1TS U3608 ( .A(n6478), .B(n7764), .Y(n6468) );
OAI21X1TS U3609 ( .A0(n7190), .A1(n7129), .B0(n7128), .Y(n7133) );
NOR2X1TS U3610 ( .A(n6478), .B(n7763), .Y(n6479) );
AO22X1TS U3611 ( .A0(n7451), .A1(result_add_subt[29]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1768) );
AO22X1TS U3612 ( .A0(n7451), .A1(result_add_subt[27]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(n1774) );
AO22X1TS U3613 ( .A0(n7446), .A1(result_add_subt[30]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1732) );
AO22X1TS U3614 ( .A0(n7451), .A1(result_add_subt[26]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(n1777) );
NOR2X1TS U3615 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n6562) );
AO22X1TS U3616 ( .A0(n7440), .A1(result_add_subt[29]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1769) );
OAI211X2TS U3617 ( .A0(n7303), .A1(n2196), .B0(n6636), .C0(n7318), .Y(n7311)
);
NAND2BX1TS U3618 ( .AN(n7625), .B(n7378), .Y(n5972) );
AO22X1TS U3619 ( .A0(n7440), .A1(result_add_subt[24]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22X1TS U3620 ( .A0(n7440), .A1(result_add_subt[26]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
NAND2BX1TS U3621 ( .AN(n7392), .B(n7576), .Y(n6000) );
AO22X1TS U3622 ( .A0(n7440), .A1(result_add_subt[27]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22X1TS U3623 ( .A0(n7440), .A1(result_add_subt[28]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
NAND2X4TS U3624 ( .A(n2554), .B(n2553), .Y(n3449) );
OAI21X1TS U3625 ( .A0(gt_x_74_A_23_), .A1(n6024), .B0(n7393), .Y(n6025) );
AO22X1TS U3626 ( .A0(n7440), .A1(result_add_subt[22]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22X1TS U3627 ( .A0(n7446), .A1(result_add_subt[15]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22X1TS U3628 ( .A0(n7446), .A1(result_add_subt[18]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22X1TS U3629 ( .A0(n7446), .A1(result_add_subt[21]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22X1TS U3630 ( .A0(n7446), .A1(result_add_subt[19]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22X1TS U3631 ( .A0(n7446), .A1(result_add_subt[20]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22X1TS U3632 ( .A0(n7446), .A1(result_add_subt[17]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
OAI21X1TS U3633 ( .A0(n7386), .A1(n5976), .B0(n7384), .Y(n5977) );
OAI21X1TS U3634 ( .A0(n7382), .A1(n5964), .B0(n7381), .Y(n5965) );
NAND2X4TS U3635 ( .A(n3875), .B(n3879), .Y(n2729) );
AO22X1TS U3636 ( .A0(n7451), .A1(result_add_subt[25]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1780) );
AO22X1TS U3637 ( .A0(n7442), .A1(result_add_subt[30]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22X1TS U3638 ( .A0(n7440), .A1(result_add_subt[25]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1781) );
AO22X1TS U3639 ( .A0(n7442), .A1(result_add_subt[29]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
NAND3X1TS U3640 ( .A(n5884), .B(n5883), .C(n7398), .Y(n5886) );
AO22X1TS U3641 ( .A0(n7442), .A1(result_add_subt[8]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22X1TS U3642 ( .A0(n7442), .A1(result_add_subt[22]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
NOR2X1TS U3643 ( .A(n6306), .B(n6201), .Y(n6191) );
AO22X1TS U3644 ( .A0(n7451), .A1(result_add_subt[23]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1786) );
AO22X1TS U3645 ( .A0(n7440), .A1(result_add_subt[23]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1787) );
AO22X1TS U3646 ( .A0(n7451), .A1(result_add_subt[30]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1731) );
INVX3TS U3647 ( .A(n3324), .Y(n3338) );
NOR2X4TS U3648 ( .A(n4025), .B(n3772), .Y(n3782) );
AO22X1TS U3649 ( .A0(n7440), .A1(result_add_subt[0]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22X1TS U3650 ( .A0(n7346), .A1(result_add_subt[5]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
AO22X1TS U3651 ( .A0(n7451), .A1(result_add_subt[22]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22X1TS U3652 ( .A0(n7352), .A1(result_add_subt[15]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22X1TS U3653 ( .A0(n7352), .A1(result_add_subt[18]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22X1TS U3654 ( .A0(n7352), .A1(result_add_subt[21]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22X1TS U3655 ( .A0(n7341), .A1(result_add_subt[1]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22X1TS U3656 ( .A0(n7346), .A1(result_add_subt[4]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22X1TS U3657 ( .A0(n7346), .A1(result_add_subt[8]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22X1TS U3658 ( .A0(n7442), .A1(result_add_subt[31]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AO22X1TS U3659 ( .A0(n7346), .A1(result_add_subt[11]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22X1TS U3660 ( .A0(n7346), .A1(result_add_subt[7]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22X1TS U3661 ( .A0(n7341), .A1(result_add_subt[0]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
AO22X1TS U3662 ( .A0(n7346), .A1(result_add_subt[2]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
OAI31X4TS U3663 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n7818),
.A2(n6646), .B0(n7282), .Y(n7308) );
AO22X1TS U3664 ( .A0(n7346), .A1(result_add_subt[9]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22X1TS U3665 ( .A0(n7451), .A1(result_add_subt[28]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22X1TS U3666 ( .A0(n7346), .A1(result_add_subt[3]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22X1TS U3667 ( .A0(n7451), .A1(result_add_subt[24]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(n1783) );
OR2X2TS U3668 ( .A(n5403), .B(n5402), .Y(n5614) );
AO22X1TS U3669 ( .A0(n7442), .A1(result_add_subt[20]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22X1TS U3670 ( .A0(n7352), .A1(result_add_subt[12]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22X1TS U3671 ( .A0(n7352), .A1(result_add_subt[19]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22X1TS U3672 ( .A0(n7352), .A1(result_add_subt[20]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22X1TS U3673 ( .A0(n7346), .A1(result_add_subt[10]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22X1TS U3674 ( .A0(n7352), .A1(result_add_subt[14]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22X1TS U3675 ( .A0(n7352), .A1(result_add_subt[17]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
ADDHX2TS U3676 ( .A(n3329), .B(n3328), .CO(n3410), .S(n3336) );
AO22X1TS U3677 ( .A0(n7346), .A1(result_add_subt[6]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22X1TS U3678 ( .A0(n7352), .A1(result_add_subt[13]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22X1TS U3679 ( .A0(n7352), .A1(result_add_subt[16]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22X1TS U3680 ( .A0(n7446), .A1(result_add_subt[13]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22X1TS U3681 ( .A0(n7446), .A1(result_add_subt[16]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
OR2X2TS U3682 ( .A(n6905), .B(FPMULT_FSM_selector_C), .Y(n6542) );
NAND2BX1TS U3683 ( .AN(n7382), .B(n7563), .Y(n5962) );
NAND2BX1TS U3684 ( .AN(n7390), .B(n7578), .Y(n6018) );
AO22X1TS U3685 ( .A0(n7442), .A1(result_add_subt[23]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
OAI21X1TS U3686 ( .A0(n6232), .A1(n6224), .B0(n6231), .Y(n6233) );
OR2X4TS U3687 ( .A(n5454), .B(n6614), .Y(n6859) );
AO22X1TS U3688 ( .A0(n7442), .A1(result_add_subt[21]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22X1TS U3689 ( .A0(n7446), .A1(result_add_subt[14]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
INVX6TS U3690 ( .A(n2518), .Y(n3787) );
AO22X1TS U3691 ( .A0(n7442), .A1(result_add_subt[19]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
NAND2BX1TS U3692 ( .AN(n7378), .B(n7625), .Y(n5969) );
NAND2XLTS U3693 ( .A(n6581), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n6277) );
OAI211X1TS U3694 ( .A0(n6261), .A1(n6263), .B0(n5808), .C0(n6649), .Y(n1693)
);
BUFX6TS U3695 ( .A(n3791), .Y(n2243) );
OAI21XLTS U3696 ( .A0(n6717), .A1(n7853), .B0(n6663), .Y(op_result[24]) );
OAI21XLTS U3697 ( .A0(n6717), .A1(n2343), .B0(n6666), .Y(op_result[31]) );
OAI21XLTS U3698 ( .A0(n6717), .A1(n7852), .B0(n6665), .Y(op_result[26]) );
OAI21XLTS U3699 ( .A0(n6661), .A1(n7843), .B0(n6627), .Y(op_result[3]) );
OAI21XLTS U3700 ( .A0(n6661), .A1(n7846), .B0(n6686), .Y(op_result[0]) );
OAI21XLTS U3701 ( .A0(n6661), .A1(n7847), .B0(n6688), .Y(op_result[1]) );
OAI21XLTS U3702 ( .A0(n6717), .A1(n7851), .B0(n6662), .Y(op_result[27]) );
OAI21XLTS U3703 ( .A0(n6713), .A1(n7839), .B0(n6687), .Y(op_result[11]) );
OAI21XLTS U3704 ( .A0(n6717), .A1(n7523), .B0(n6667), .Y(op_result[22]) );
OAI21XLTS U3705 ( .A0(n6713), .A1(n7842), .B0(n6712), .Y(op_result[12]) );
OAI21XLTS U3706 ( .A0(n6717), .A1(n7830), .B0(n6716), .Y(op_result[21]) );
OAI21XLTS U3707 ( .A0(n6717), .A1(n7832), .B0(n6709), .Y(op_result[20]) );
OAI21XLTS U3708 ( .A0(n6713), .A1(n7841), .B0(n6685), .Y(op_result[10]) );
OAI21XLTS U3709 ( .A0(n6717), .A1(n7831), .B0(n6710), .Y(op_result[19]) );
OAI21XLTS U3710 ( .A0(n6713), .A1(n7836), .B0(n6704), .Y(op_result[13]) );
OAI21XLTS U3711 ( .A0(n6713), .A1(n7840), .B0(n6706), .Y(op_result[14]) );
OAI21XLTS U3712 ( .A0(n6713), .A1(n7828), .B0(n6705), .Y(op_result[15]) );
OAI21XLTS U3713 ( .A0(n6717), .A1(n7829), .B0(n6703), .Y(op_result[18]) );
OAI21XLTS U3714 ( .A0(n6713), .A1(n7837), .B0(n6707), .Y(op_result[16]) );
OAI21XLTS U3715 ( .A0(n6717), .A1(n7850), .B0(n6664), .Y(op_result[28]) );
OAI21XLTS U3716 ( .A0(n6713), .A1(n7833), .B0(n6708), .Y(op_result[17]) );
AO22X1TS U3717 ( .A0(n7512), .A1(n7510), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22X1TS U3718 ( .A0(n7347), .A1(result_add_subt[10]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22X1TS U3719 ( .A0(n7605), .A1(n7555), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22X1TS U3720 ( .A0(n7512), .A1(n7507), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22X1TS U3721 ( .A0(n7605), .A1(n7553), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AO22X1TS U3722 ( .A0(n7347), .A1(result_add_subt[12]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22X1TS U3723 ( .A0(n7347), .A1(result_add_subt[11]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
NAND2BX1TS U3724 ( .AN(n7569), .B(n7399), .Y(n5885) );
AO22X1TS U3725 ( .A0(n7605), .A1(n7558), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AO22X1TS U3726 ( .A0(n7438), .A1(result_add_subt[24]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
NAND2BX1TS U3727 ( .AN(n7399), .B(n7569), .Y(n5883) );
AO22X1TS U3728 ( .A0(n7512), .A1(n7511), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22X1TS U3729 ( .A0(n7347), .A1(result_add_subt[8]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
OAI211X2TS U3730 ( .A0(n2259), .A1(n8388), .B0(n8387), .C0(n5911), .Y(n7379)
);
AO22X1TS U3731 ( .A0(n7347), .A1(result_add_subt[6]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22X1TS U3732 ( .A0(n7351), .A1(result_add_subt[18]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22X1TS U3733 ( .A0(n7539), .A1(n7513), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
AO22X1TS U3734 ( .A0(n7539), .A1(n7516), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
NOR2X6TS U3735 ( .A(n4205), .B(n4204), .Y(n4736) );
OAI21X1TS U3736 ( .A0(n6335), .A1(n6294), .B0(n6293), .Y(n6299) );
AO22X1TS U3737 ( .A0(n7347), .A1(result_add_subt[4]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
CLKINVX2TS U3738 ( .A(n7302), .Y(n7304) );
AO22X1TS U3739 ( .A0(n7539), .A1(n7514), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
OAI21X1TS U3740 ( .A0(n6444), .A1(n8756), .B0(n6446), .Y(n6436) );
INVX6TS U3741 ( .A(n3445), .Y(n2351) );
AO22X1TS U3742 ( .A0(n7539), .A1(n7524), .B0(n7526), .B1(
FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
AO22X1TS U3743 ( .A0(n7351), .A1(result_add_subt[15]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
ADDFHX2TS U3744 ( .A(n3556), .B(n3320), .CI(n3319), .CO(n3332), .S(n3334) );
AO22X1TS U3745 ( .A0(n7539), .A1(n7527), .B0(n7526), .B1(
FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
AO22X1TS U3746 ( .A0(n7539), .A1(n7529), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
OAI211X2TS U3747 ( .A0(n2259), .A1(n8378), .B0(n8377), .C0(n5990), .Y(n7387)
);
AO22X1TS U3748 ( .A0(n7438), .A1(result_add_subt[25]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22X1TS U3749 ( .A0(n7539), .A1(n7531), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AO22X1TS U3750 ( .A0(n7438), .A1(result_add_subt[26]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22X1TS U3751 ( .A0(n7539), .A1(n7533), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AO22X1TS U3752 ( .A0(n7539), .A1(n7535), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AO22X1TS U3753 ( .A0(n7512), .A1(n7509), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
NOR2X1TS U3754 ( .A(n7286), .B(n7441), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
ADDFHX2TS U3755 ( .A(n4518), .B(n4223), .CI(n4222), .CO(n4298), .S(n4231) );
AO22X1TS U3756 ( .A0(n7539), .A1(n7538), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
AO22X1TS U3757 ( .A0(n7605), .A1(n7541), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
NOR2X4TS U3758 ( .A(n3342), .B(n3441), .Y(n3276) );
AO22X1TS U3759 ( .A0(n7438), .A1(result_add_subt[27]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22X1TS U3760 ( .A0(n7347), .A1(result_add_subt[5]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22X1TS U3761 ( .A0(n7605), .A1(n7543), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
OAI211X2TS U3762 ( .A0(n2259), .A1(n8362), .B0(n8361), .C0(n6002), .Y(n7389)
);
AO22X1TS U3763 ( .A0(n7347), .A1(result_add_subt[9]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22X1TS U3764 ( .A0(n7605), .A1(n7545), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AO22X1TS U3765 ( .A0(n7438), .A1(result_add_subt[28]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22X1TS U3766 ( .A0(n7605), .A1(n7547), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AO22X1TS U3767 ( .A0(n7512), .A1(n1467), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AND2X2TS U3768 ( .A(n4474), .B(n4567), .Y(n4475) );
AO22X1TS U3769 ( .A0(n7347), .A1(result_add_subt[7]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22X1TS U3770 ( .A0(n7605), .A1(n7551), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AO22X1TS U3771 ( .A0(n7347), .A1(result_add_subt[3]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22X1TS U3772 ( .A0(n7645), .A1(n7626), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22X1TS U3773 ( .A0(n7645), .A1(n7630), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22X1TS U3774 ( .A0(n7645), .A1(n7632), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22X1TS U3775 ( .A0(n7344), .A1(result_add_subt[7]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22X1TS U3776 ( .A0(n7645), .A1(n7635), .B0(n7650), .B1(
FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
AO22X1TS U3777 ( .A0(n7645), .A1(n7639), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22X1TS U3778 ( .A0(n7645), .A1(n7640), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
AO22X1TS U3779 ( .A0(n7645), .A1(n7641), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22X1TS U3780 ( .A0(n7645), .A1(n7643), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22X1TS U3781 ( .A0(n7645), .A1(n7644), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22X1TS U3782 ( .A0(n7667), .A1(n7646), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22X1TS U3783 ( .A0(n7351), .A1(result_add_subt[0]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
AO22X1TS U3784 ( .A0(n7667), .A1(n7647), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22X1TS U3785 ( .A0(n7667), .A1(n7649), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1242) );
AO22X1TS U3786 ( .A0(n7667), .A1(n7651), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22X1TS U3787 ( .A0(n7667), .A1(n7653), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22X1TS U3788 ( .A0(n7667), .A1(n7657), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22X1TS U3789 ( .A0(n7667), .A1(n7659), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22X1TS U3790 ( .A0(n7667), .A1(n7660), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22X1TS U3791 ( .A0(n7344), .A1(result_add_subt[6]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
AO22X1TS U3792 ( .A0(n7438), .A1(result_add_subt[12]), .B0(n7343), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22X1TS U3793 ( .A0(n7667), .A1(n7662), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22X1TS U3794 ( .A0(n7351), .A1(result_add_subt[1]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
ADDFHX2TS U3795 ( .A(n4394), .B(n4393), .CI(n4392), .CO(n4459), .S(n4414) );
AO22X1TS U3796 ( .A0(n7667), .A1(n7666), .B0(n7665), .B1(
FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22X1TS U3797 ( .A0(n6356), .A1(n6861), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AND2X2TS U3798 ( .A(n3467), .B(n3625), .Y(n3517) );
AO22X1TS U3799 ( .A0(n7645), .A1(n7623), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22X1TS U3800 ( .A0(n7438), .A1(result_add_subt[11]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22X1TS U3801 ( .A0(n7438), .A1(result_add_subt[9]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
CLKBUFX3TS U3802 ( .A(n6180), .Y(n2381) );
NAND2BX1TS U3803 ( .AN(n7395), .B(n7575), .Y(n6030) );
AO22X1TS U3804 ( .A0(n7351), .A1(result_add_subt[17]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
INVX1TS U3805 ( .A(gt_x_74_A_23_), .Y(n7574) );
AO22X1TS U3806 ( .A0(n7344), .A1(result_add_subt[5]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
AO22X1TS U3807 ( .A0(n7438), .A1(result_add_subt[10]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22X1TS U3808 ( .A0(n7605), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n7604), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22X1TS U3809 ( .A0(n7351), .A1(result_add_subt[14]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22X1TS U3810 ( .A0(n7351), .A1(result_add_subt[4]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22X1TS U3811 ( .A0(n7605), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n7604), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
AO22X1TS U3812 ( .A0(n7351), .A1(result_add_subt[16]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22X1TS U3813 ( .A0(n7438), .A1(result_add_subt[13]), .B0(n7343), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22X1TS U3814 ( .A0(n7351), .A1(result_add_subt[3]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
INVX2TS U3815 ( .A(n2812), .Y(n2809) );
AO22X1TS U3816 ( .A0(n7351), .A1(result_add_subt[2]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
OAI21XLTS U3817 ( .A0(n6661), .A1(n7835), .B0(n6631), .Y(op_result[6]) );
OAI21XLTS U3818 ( .A0(n6661), .A1(n7849), .B0(n6630), .Y(op_result[5]) );
OAI21XLTS U3819 ( .A0(n6661), .A1(n7834), .B0(n6626), .Y(op_result[4]) );
OAI21XLTS U3820 ( .A0(n6661), .A1(n7845), .B0(n6629), .Y(op_result[7]) );
OAI21XLTS U3821 ( .A0(n6713), .A1(n7848), .B0(n6628), .Y(op_result[9]) );
OAI21XLTS U3822 ( .A0(n6713), .A1(n7838), .B0(n6625), .Y(op_result[8]) );
OAI21XLTS U3823 ( .A0(n6661), .A1(n7844), .B0(n6657), .Y(op_result[2]) );
NAND2BX1TS U3824 ( .AN(n6238), .B(n6237), .Y(n6239) );
OAI211X2TS U3825 ( .A0(n2259), .A1(n8320), .B0(n8319), .C0(n5918), .Y(n7373)
);
AO22X1TS U3826 ( .A0(n6355), .A1(n6868), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22X1TS U3827 ( .A0(n6355), .A1(n7610), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
OAI211X2TS U3828 ( .A0(n2260), .A1(n8318), .B0(n8317), .C0(n5931), .Y(n7368)
);
NOR2X1TS U3829 ( .A(n7817), .B(n2350), .Y(n6166) );
INVX12TS U3830 ( .A(n3408), .Y(n3342) );
OAI211X2TS U3831 ( .A0(n2260), .A1(n8328), .B0(n8327), .C0(n5936), .Y(n7370)
);
NAND2XLTS U3832 ( .A(n7548), .B(result_add_subt[25]), .Y(n6567) );
OAI211X4TS U3833 ( .A0(n2204), .A1(n8398), .B0(n8397), .C0(n5909), .Y(n7625)
);
OAI211X2TS U3834 ( .A0(n2202), .A1(n8322), .B0(n8321), .C0(n5924), .Y(n7376)
);
AO22X1TS U3835 ( .A0(n6355), .A1(n7619), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
AO22X1TS U3836 ( .A0(n6355), .A1(n6871), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
OAI211X2TS U3837 ( .A0(n2259), .A1(n8324), .B0(n8323), .C0(n5906), .Y(n7377)
);
AND2X2TS U3838 ( .A(n7600), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6424) );
OAI21X1TS U3839 ( .A0(n6238), .A1(n6231), .B0(n6237), .Y(n6198) );
AO22X1TS U3840 ( .A0(n6355), .A1(n7616), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22X1TS U3841 ( .A0(n6355), .A1(n6870), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22X1TS U3842 ( .A0(n6355), .A1(n6865), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
CMPR22X2TS U3843 ( .A(n3206), .B(n3205), .CO(n3210), .S(n3283) );
AO22X1TS U3844 ( .A0(n6355), .A1(n7613), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22X1TS U3845 ( .A0(n6355), .A1(n7607), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
AO22X1TS U3846 ( .A0(n6355), .A1(n6866), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
OAI211X2TS U3847 ( .A0(n8023), .A1(n8059), .B0(n6046), .C0(n6045), .Y(n1808)
);
OAI211X2TS U3848 ( .A0(n2201), .A1(n8312), .B0(n8311), .C0(n5874), .Y(n7571)
);
OAI211X2TS U3849 ( .A0(n8025), .A1(n8059), .B0(n6850), .C0(n6849), .Y(n1796)
);
OAI211X2TS U3850 ( .A0(n2205), .A1(n8404), .B0(n8403), .C0(n6874), .Y(n7602)
);
OAI211X2TS U3851 ( .A0(n2205), .A1(n8368), .B0(n8367), .C0(n5991), .Y(n7391)
);
OAI211X2TS U3852 ( .A0(n7998), .A1(n2468), .B0(n6837), .C0(n6836), .Y(n1804)
);
OAI211X2TS U3853 ( .A0(n8024), .A1(n8058), .B0(n6168), .C0(n6167), .Y(n1805)
);
INVX2TS U3854 ( .A(n7548), .Y(n8612) );
INVX8TS U3855 ( .A(n3316), .Y(n3612) );
OAI211X2TS U3856 ( .A0(n8028), .A1(n2468), .B0(n6552), .C0(n6551), .Y(n1802)
);
OAI211X2TS U3857 ( .A0(n8029), .A1(n8059), .B0(n6247), .C0(n6246), .Y(n1800)
);
OAI211X2TS U3858 ( .A0(n8026), .A1(n8059), .B0(n6846), .C0(n6845), .Y(n1794)
);
NOR2X1TS U3859 ( .A(n6052), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n6056) );
OAI211X2TS U3860 ( .A0(n8000), .A1(n8059), .B0(n6351), .C0(n6350), .Y(n1798)
);
NOR2X1TS U3861 ( .A(n6054), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n6055) );
OAI211X2TS U3862 ( .A0(n2259), .A1(n8358), .B0(n8357), .C0(n5995), .Y(n7393)
);
OAI211X2TS U3863 ( .A0(n8021), .A1(n2371), .B0(n6044), .C0(n6043), .Y(n1811)
);
AND2X2TS U3864 ( .A(n6602), .B(n2350), .Y(n6618) );
OAI211X2TS U3865 ( .A0(n8024), .A1(n8059), .B0(n6554), .C0(n6553), .Y(n1806)
);
OAI211X2TS U3866 ( .A0(n2205), .A1(n8308), .B0(n8307), .C0(n5764), .Y(
gt_x_74_B_23_) );
ADDFHX2TS U3867 ( .A(n4352), .B(DP_OP_498J211_124_1725_n718), .CI(n4351),
.CO(n4416), .S(n4327) );
OAI211X2TS U3868 ( .A0(n8023), .A1(n8058), .B0(n6187), .C0(n6186), .Y(n1807)
);
OAI211X2TS U3869 ( .A0(n7998), .A1(n8058), .B0(n6835), .C0(n6834), .Y(n1803)
);
INVX1TS U3870 ( .A(n7665), .Y(n6356) );
AO22X1TS U3871 ( .A0(n8644), .A1(busy), .B0(n8643), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
OAI211X2TS U3872 ( .A0(n2205), .A1(n8314), .B0(n8313), .C0(n5880), .Y(n7580)
);
OAI21X1TS U3873 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n5802), .Y(n5803) );
OAI211X2TS U3874 ( .A0(n8000), .A1(n8058), .B0(n6171), .C0(n6170), .Y(n1797)
);
OAI211X2TS U3875 ( .A0(n8029), .A1(n8058), .B0(n6245), .C0(n6244), .Y(n1799)
);
NOR2X4TS U3876 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n6991), .Y(n6178)
);
OAI21X1TS U3877 ( .A0(n6335), .A1(n7767), .B0(n7745), .Y(n5789) );
NOR2X6TS U3878 ( .A(n2683), .B(n3174), .Y(n3455) );
NOR2X4TS U3879 ( .A(n3232), .B(n3479), .Y(n2899) );
NOR2X4TS U3880 ( .A(n7196), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6371) );
NOR2X4TS U3881 ( .A(n4973), .B(DP_OP_498J211_124_1725_n732), .Y(n4400) );
OAI21X1TS U3882 ( .A0(n6397), .A1(n6402), .B0(n6398), .Y(n5845) );
OR2X2TS U3883 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n2491), .Y(n2335)
);
NOR2X4TS U3884 ( .A(n3295), .B(n3479), .Y(n3482) );
OAI21X1TS U3885 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n6953), .B0(n3154), .Y(
n6954) );
OR2X2TS U3886 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n7012), .Y(n6181)
);
INVX2TS U3887 ( .A(n7088), .Y(n7089) );
NAND2X6TS U3888 ( .A(n5707), .B(n3860), .Y(n3297) );
INVX12TS U3889 ( .A(n4294), .Y(n2953) );
OAI21X1TS U3890 ( .A0(n6295), .A1(n7766), .B0(n6296), .Y(n6193) );
CLKINVX2TS U3891 ( .A(n6587), .Y(n7289) );
NOR2X1TS U3892 ( .A(n7794), .B(n6620), .Y(n5807) );
NAND2X6TS U3893 ( .A(n4451), .B(n4211), .Y(n4220) );
OAI21X1TS U3894 ( .A0(n5820), .A1(n6376), .B0(n5819), .Y(n5821) );
ADDHX2TS U3895 ( .A(n6860), .B(DP_OP_496J211_122_3540_n1478), .CO(n4411),
.S(n4324) );
INVX1TS U3896 ( .A(n6449), .Y(n6255) );
NAND3X1TS U3897 ( .A(n7261), .B(n7260), .C(n7259), .Y(n8060) );
OAI32X1TS U3898 ( .A0(n7287), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n6588) );
CLKAND2X2TS U3899 ( .A(n7941), .B(FPADDSUB_DMP_SFG[9]), .Y(n5833) );
BUFX16TS U3900 ( .A(n4255), .Y(n2245) );
INVX12TS U3901 ( .A(DP_OP_498J211_124_1725_n789), .Y(n4166) );
AO22X4TS U3902 ( .A0(n8290), .A1(n8289), .B0(n8288), .B1(n8287), .Y(n7548)
);
NAND2X4TS U3903 ( .A(n7727), .B(DP_OP_496J211_122_3540_n1108), .Y(n2579) );
CLKMX2X2TS U3904 ( .A(n8072), .B(n8071), .S0(n8044), .Y(n1579) );
CLKMX2X2TS U3905 ( .A(n8145), .B(n8144), .S0(n8044), .Y(n1580) );
OR2X2TS U3906 ( .A(n7788), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6620) );
INVX6TS U3907 ( .A(DP_OP_498J211_124_1725_n802), .Y(n4211) );
OR3X4TS U3908 ( .A(FPSENCOS_cont_var_out[1]), .B(n7819), .C(n7800), .Y(n7339) );
NOR2X1TS U3909 ( .A(add_x_246_A_1_), .B(add_x_246_A_0_), .Y(n6941) );
NOR2X1TS U3910 ( .A(n7801), .B(n7854), .Y(n6983) );
OR2X2TS U3911 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n6101) );
INVX4TS U3912 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n7088) );
OR2X2TS U3913 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n6120) );
CLKMX2X2TS U3914 ( .A(n8070), .B(n8069), .S0(n8044), .Y(n1578) );
CLKINVX2TS U3915 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n8679) );
INVX12TS U3916 ( .A(DP_OP_498J211_124_1725_n796), .Y(n4451) );
OR2X2TS U3917 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n6139) );
INVX8TS U3918 ( .A(DP_OP_497J211_123_1725_n792), .Y(n3220) );
INVX8TS U3919 ( .A(DP_OP_497J211_123_1725_n782), .Y(n3295) );
NOR2X1TS U3920 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n5814) );
NAND3X1TS U3921 ( .A(n5811), .B(n5810), .C(n5809), .Y(n5812) );
BUFX3TS U3922 ( .A(n8077), .Y(n5986) );
AOI22X1TS U3923 ( .A0(n8074), .A1(n8175), .B0(n5998), .B1(n8174), .Y(n5874)
);
AOI22X1TS U3924 ( .A0(n8074), .A1(n8173), .B0(n5998), .B1(n8172), .Y(n5876)
);
AOI22X1TS U3925 ( .A0(n8074), .A1(n8177), .B0(n5998), .B1(n8176), .Y(n5880)
);
AOI22X1TS U3926 ( .A0(n8074), .A1(n8167), .B0(n2208), .B1(n8166), .Y(n5882)
);
AOI22X1TS U3927 ( .A0(n8074), .A1(n8181), .B0(n5998), .B1(n8180), .Y(n5999)
);
AOI22X1TS U3928 ( .A0(n8074), .A1(n8171), .B0(n2208), .B1(n8170), .Y(n6004)
);
BUFX3TS U3929 ( .A(n5904), .Y(n2251) );
AOI22X1TS U3930 ( .A0(n8076), .A1(n8269), .B0(n6005), .B1(n8268), .Y(n5765)
);
AOI22X1TS U3931 ( .A0(n8076), .A1(n8247), .B0(n6005), .B1(n8246), .Y(n5873)
);
AOI22X1TS U3932 ( .A0(n8076), .A1(n8259), .B0(n6005), .B1(n8258), .Y(n5991)
);
AOI22X1TS U3933 ( .A0(n8076), .A1(n8233), .B0(n6005), .B1(n8232), .Y(n5995)
);
AOI22X1TS U3934 ( .A0(n8076), .A1(n8253), .B0(n6005), .B1(n8252), .Y(n5997)
);
OAI21X1TS U3935 ( .A0(n7371), .A1(n5941), .B0(n7370), .Y(n5940) );
OAI2BB2XLTS U3936 ( .B0(n7564), .B1(n5977), .A0N(n7386), .A1N(n5976), .Y(
n5978) );
OAI2BB2XLTS U3937 ( .B0(n7638), .B1(n5965), .A0N(n7382), .A1N(n5964), .Y(
n5980) );
OAI211X1TS U3938 ( .A0(n2260), .A1(n8336), .B0(n8335), .C0(n5916), .Y(n7375)
);
OAI211X4TS U3939 ( .A0(n2202), .A1(n8366), .B0(n8365), .C0(n6006), .Y(n7390)
);
OAI211X4TS U3940 ( .A0(n2204), .A1(n8384), .B0(n8383), .C0(n5956), .Y(n7384)
);
OAI211X4TS U3941 ( .A0(n2259), .A1(n8390), .B0(n8389), .C0(n5952), .Y(n7381)
);
OAI211X4TS U3942 ( .A0(n2205), .A1(n8370), .B0(n8369), .C0(n5905), .Y(n7388)
);
OAI211X4TS U3943 ( .A0(n2202), .A1(n8310), .B0(n8309), .C0(n5876), .Y(n7575)
);
OAI211X4TS U3944 ( .A0(n2205), .A1(n8364), .B0(n8363), .C0(n5997), .Y(n7392)
);
OAI211X4TS U3945 ( .A0(n2205), .A1(n8354), .B0(n8353), .C0(n5894), .Y(n7401)
);
OAI211X1TS U3946 ( .A0(n2205), .A1(n8406), .B0(n8405), .C0(n5889), .Y(n7400)
);
OAI211X4TS U3947 ( .A0(n2202), .A1(n8352), .B0(n8351), .C0(n5881), .Y(n7399)
);
OAI211X4TS U3948 ( .A0(n2205), .A1(n8348), .B0(n8347), .C0(n5873), .Y(n7397)
);
OAI211X4TS U3949 ( .A0(n2259), .A1(n8402), .B0(n8401), .C0(n5765), .Y(
gt_x_74_A_23_) );
OAI211X4TS U3950 ( .A0(n2202), .A1(n8374), .B0(n8373), .C0(n5920), .Y(n7584)
);
OAI211X4TS U3951 ( .A0(n2259), .A1(n8372), .B0(n8371), .C0(n5915), .Y(n7582)
);
OAI211X4TS U3952 ( .A0(n2205), .A1(n8356), .B0(n8355), .C0(n5891), .Y(n7403)
);
NOR2X4TS U3953 ( .A(n4844), .B(n4843), .Y(n5456) );
NOR2X6TS U3954 ( .A(n3819), .B(n2277), .Y(n2902) );
XOR2X4TS U3955 ( .A(n3595), .B(n2261), .Y(n3616) );
XOR2X4TS U3956 ( .A(n3596), .B(n3597), .Y(n2261) );
NAND3X6TS U3957 ( .A(n3003), .B(n3002), .C(n5675), .Y(n2267) );
NAND3X6TS U3958 ( .A(n3003), .B(n3002), .C(n5675), .Y(n3000) );
NAND3X4TS U3959 ( .A(n2687), .B(n2688), .C(n3695), .Y(n2545) );
NOR2X8TS U3960 ( .A(n3591), .B(n3590), .Y(n3681) );
ADDFHX2TS U3961 ( .A(n5214), .B(n5633), .CI(n5213), .CO(n5242), .S(n5228) );
ADDFHX2TS U3962 ( .A(n5224), .B(n5223), .CI(n5222), .CO(n5249), .S(n5213) );
NOR2X6TS U3963 ( .A(n4294), .B(n2274), .Y(n4402) );
BUFX16TS U3964 ( .A(FPMULT_Op_MX[4]), .Y(n4294) );
CLKINVX6TS U3965 ( .A(n4583), .Y(n3945) );
NAND2X2TS U3966 ( .A(n4584), .B(n4583), .Y(n4826) );
NOR2X2TS U3967 ( .A(n4584), .B(n4583), .Y(n4827) );
AND2X8TS U3968 ( .A(n5441), .B(n5440), .Y(n5685) );
INVX12TS U3969 ( .A(n8518), .Y(n4397) );
OAI22X2TS U3970 ( .A0(n4549), .A1(n4495), .B0(n2437), .B1(n4550), .Y(n4383)
);
INVX4TS U3971 ( .A(n4734), .Y(n4203) );
INVX12TS U3972 ( .A(DP_OP_498J211_124_1725_n788), .Y(n4185) );
NOR2X4TS U3973 ( .A(n4295), .B(n4276), .Y(n4714) );
NOR2X8TS U3974 ( .A(n4996), .B(n5312), .Y(n5282) );
NAND2X4TS U3975 ( .A(n3038), .B(n3036), .Y(n5259) );
INVX8TS U3976 ( .A(n2594), .Y(n5208) );
ADDFHX4TS U3977 ( .A(n4926), .B(n4925), .CI(n4924), .CO(n5164), .S(n4911) );
NAND2X4TS U3978 ( .A(n2929), .B(n2930), .Y(n2712) );
NAND3X6TS U3979 ( .A(n2929), .B(n2930), .C(n3660), .Y(n2687) );
NOR2X4TS U3980 ( .A(n3484), .B(n3088), .Y(n3087) );
OAI2BB1X4TS U3981 ( .A0N(n4699), .A1N(n5142), .B0(n3171), .Y(n3130) );
XNOR2X4TS U3982 ( .A(n3289), .B(n3375), .Y(n3290) );
NOR2X4TS U3983 ( .A(n4397), .B(n2275), .Y(n4395) );
NOR2X4TS U3984 ( .A(n4972), .B(n4397), .Y(n4455) );
NAND2X6TS U3985 ( .A(n5445), .B(n2904), .Y(n3050) );
XNOR2X4TS U3986 ( .A(n2633), .B(n5157), .Y(n2635) );
NAND2X6TS U3987 ( .A(DP_OP_496J211_122_3540_n1493), .B(
DP_OP_496J211_122_3540_n1506), .Y(n3769) );
XOR2X4TS U3988 ( .A(n4294), .B(n2936), .Y(n2955) );
ADDFHX4TS U3989 ( .A(n4463), .B(n4462), .CI(n4461), .CO(n4502), .S(n4464) );
NOR2X2TS U3990 ( .A(n5071), .B(n5032), .Y(n5073) );
BUFX12TS U3991 ( .A(n5030), .Y(n5071) );
AND2X4TS U3992 ( .A(n5698), .B(n5689), .Y(n3011) );
ADDFHX4TS U3993 ( .A(n5190), .B(n5189), .CI(n5188), .CO(n5218), .S(n5192) );
NAND2X6TS U3994 ( .A(n4869), .B(n4868), .Y(n5463) );
XNOR2X4TS U3995 ( .A(n4853), .B(n4852), .Y(n7212) );
XNOR2X2TS U3996 ( .A(n2867), .B(n2866), .Y(n2865) );
CLKXOR2X4TS U3997 ( .A(n4457), .B(n2865), .Y(n4460) );
ADDFX2TS U3998 ( .A(n4039), .B(n4038), .CI(n4037), .CO(n4061), .S(n4040) );
OAI22X4TS U3999 ( .A0(n4009), .A1(n4093), .B0(n4002), .B1(n4094), .Y(n4039)
);
NAND2X4TS U4000 ( .A(n4894), .B(n4895), .Y(n5727) );
NAND2X4TS U4001 ( .A(n4636), .B(n4635), .Y(n4637) );
XNOR2X4TS U4002 ( .A(n5042), .B(n5041), .Y(n2262) );
XNOR2X4TS U4003 ( .A(n5042), .B(n5041), .Y(n2263) );
NAND2X6TS U4004 ( .A(n2657), .B(DP_OP_498J211_124_1725_n390), .Y(n2839) );
NAND2X4TS U4005 ( .A(n2665), .B(n2657), .Y(n2664) );
AND2X8TS U4006 ( .A(n2843), .B(n5051), .Y(n2264) );
NAND2BX2TS U4007 ( .AN(n4027), .B(n4936), .Y(n3750) );
NOR2X4TS U4008 ( .A(n2994), .B(n2993), .Y(n2992) );
NAND2X4TS U4009 ( .A(n5123), .B(n5122), .Y(n5495) );
NAND2X2TS U4010 ( .A(n2843), .B(n5093), .Y(n2842) );
NAND2X4TS U4011 ( .A(DP_OP_496J211_122_3540_n1462), .B(FPMULT_Op_MY[6]), .Y(
n3878) );
XNOR2X4TS U4012 ( .A(n4704), .B(n4703), .Y(n7207) );
OR2X4TS U4013 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3850) );
OAI22X2TS U4014 ( .A0(n4941), .A1(n5210), .B0(n5175), .B1(n5209), .Y(n5176)
);
NAND2X6TS U4015 ( .A(n4563), .B(n4562), .Y(n4950) );
OAI22X4TS U4016 ( .A0(n2837), .A1(n4440), .B0(n2379), .B1(n4491), .Y(n4386)
);
NAND2X4TS U4017 ( .A(n3015), .B(n3014), .Y(n4263) );
NAND2X6TS U4018 ( .A(n5449), .B(n2267), .Y(n5450) );
NOR2X4TS U4019 ( .A(n5697), .B(n2319), .Y(DP_OP_499J211_125_1651_n62) );
OR2X2TS U4020 ( .A(n1521), .B(n5795), .Y(n5796) );
NAND3X8TS U4021 ( .A(n3135), .B(n3042), .C(n5282), .Y(n3039) );
NAND2X4TS U4022 ( .A(n3087), .B(n3086), .Y(n3085) );
CLKAND2X2TS U4023 ( .A(n5698), .B(n3000), .Y(n2319) );
NAND2X4TS U4024 ( .A(n4523), .B(n4522), .Y(n3017) );
INVX6TS U4025 ( .A(n2613), .Y(n2599) );
NAND2X4TS U4026 ( .A(n2264), .B(n2833), .Y(n2832) );
NAND2X2TS U4027 ( .A(n4773), .B(n4772), .Y(n4775) );
OAI2BB1X4TS U4028 ( .A0N(n2824), .A1N(n5364), .B0(n5495), .Y(n2265) );
NAND2X2TS U4029 ( .A(n2755), .B(n3515), .Y(n3715) );
NAND2X6TS U4030 ( .A(n2726), .B(n2806), .Y(n2846) );
NOR2BX2TS U4031 ( .AN(n2382), .B(n2429), .Y(n3999) );
ADDFHX4TS U4032 ( .A(n3892), .B(n3891), .CI(n3890), .CO(n3928), .S(n4578) );
XOR2X4TS U4033 ( .A(n5105), .B(n4564), .Y(n2266) );
NAND2X6TS U4034 ( .A(n2575), .B(n2574), .Y(n3596) );
NOR2X6TS U4035 ( .A(n3632), .B(n3681), .Y(n2930) );
NAND2X4TS U4036 ( .A(n4425), .B(n4424), .Y(n4469) );
NAND2X4TS U4037 ( .A(n4427), .B(n4426), .Y(n4641) );
INVX6TS U4038 ( .A(n2999), .Y(n2848) );
NAND2X8TS U4039 ( .A(n3120), .B(n3190), .Y(n2983) );
OR2X6TS U4040 ( .A(n4869), .B(n4868), .Y(n3120) );
ADDHX4TS U4041 ( .A(n3981), .B(n4574), .CO(n3921), .S(n4016) );
INVX4TS U4042 ( .A(n4576), .Y(n3981) );
NOR2X8TS U4043 ( .A(n2702), .B(n5329), .Y(n2897) );
NOR2X2TS U4044 ( .A(n3992), .B(n3072), .Y(n3066) );
BUFX8TS U4045 ( .A(n2889), .Y(n2604) );
OAI22X4TS U4046 ( .A0(n2303), .A1(n4004), .B0(n3924), .B1(n2593), .Y(n4058)
);
INVX12TS U4047 ( .A(n2287), .Y(n2843) );
OAI21X2TS U4048 ( .A0(n4662), .A1(n4857), .B0(n4858), .Y(n4663) );
BUFX16TS U4049 ( .A(n2824), .Y(n2667) );
AOI21X2TS U4050 ( .A0(n5591), .A1(n2701), .B0(n5594), .Y(n5628) );
OAI22X2TS U4051 ( .A0(n2231), .A1(n4112), .B0(n4918), .B1(n5416), .Y(n4919)
);
NAND2X6TS U4052 ( .A(n3501), .B(n3502), .Y(n2770) );
NAND2X8TS U4053 ( .A(n5696), .B(n5689), .Y(n3010) );
OAI21X2TS U4054 ( .A0(n3288), .A1(n3287), .B0(n3286), .Y(n3375) );
XNOR2X4TS U4055 ( .A(n3787), .B(n2430), .Y(n3798) );
INVX6TS U4056 ( .A(n5746), .Y(n3127) );
NAND2X8TS U4057 ( .A(n2678), .B(n2677), .Y(n2806) );
INVX4TS U4058 ( .A(n4563), .Y(n2678) );
OAI2BB1X2TS U4059 ( .A0N(n3423), .A1N(n2542), .B0(n2541), .Y(n3435) );
NOR2X6TS U4060 ( .A(n5441), .B(n5440), .Y(n5546) );
NAND2X6TS U4061 ( .A(n2848), .B(n2806), .Y(n2847) );
INVX8TS U4062 ( .A(n5735), .Y(n5754) );
XNOR2X2TS U4063 ( .A(n5462), .B(n5461), .Y(n5484) );
OR2X2TS U4064 ( .A(n4797), .B(n4796), .Y(n3155) );
NOR2X6TS U4065 ( .A(n4577), .B(n4576), .Y(n4771) );
INVX8TS U4066 ( .A(n5546), .Y(n2522) );
NAND3X6TS U4067 ( .A(n2747), .B(n2743), .C(n5284), .Y(n3100) );
NAND2X8TS U4068 ( .A(n2566), .B(n2905), .Y(n3003) );
XOR2X4TS U4069 ( .A(n5205), .B(n5167), .Y(n4010) );
NAND2X4TS U4070 ( .A(n2282), .B(n5727), .Y(n3030) );
NAND2X4TS U4071 ( .A(n4226), .B(n4225), .Y(n4306) );
ADDFHX2TS U4072 ( .A(n4286), .B(n4285), .CI(n4284), .CO(n4345), .S(n4225) );
NOR2X2TS U4073 ( .A(n4483), .B(n4973), .Y(n4546) );
NOR2X4TS U4074 ( .A(n4483), .B(n4397), .Y(n4353) );
INVX12TS U4075 ( .A(n2667), .Y(n5095) );
INVX8TS U4076 ( .A(n5094), .Y(n2272) );
XOR2X4TS U4077 ( .A(n2273), .B(n5179), .Y(n3961) );
INVX2TS U4078 ( .A(n5198), .Y(n2273) );
BUFX12TS U4079 ( .A(n3963), .Y(n5416) );
NAND2X4TS U4080 ( .A(n3888), .B(n3887), .Y(n2586) );
NAND2BX2TS U4081 ( .AN(n5142), .B(n4648), .Y(n3129) );
XNOR2X4TS U4082 ( .A(n3806), .B(n2439), .Y(n3893) );
AOI22X2TS U4083 ( .A0(n6097), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n7599), .Y(n6098) );
OAI21X4TS U4084 ( .A0(n6153), .A1(n6147), .B0(n6148), .Y(n6143) );
OAI21X2TS U4085 ( .A0(n7153), .A1(n7165), .B0(n7154), .Y(n6381) );
NAND2X6TS U4086 ( .A(n5436), .B(n5435), .Y(n5690) );
NAND2X2TS U4087 ( .A(n2860), .B(n3051), .Y(n2904) );
NAND2X4TS U4088 ( .A(n3754), .B(n3753), .Y(n3809) );
OAI22X2TS U4089 ( .A0(n3934), .A1(n5209), .B0(n5210), .B1(n5212), .Y(n3956)
);
INVX8TS U4090 ( .A(n3880), .Y(n4605) );
BUFX12TS U4091 ( .A(n2823), .Y(n2829) );
NAND2X8TS U4092 ( .A(n2272), .B(n2843), .Y(n2841) );
AND2X8TS U4093 ( .A(n3062), .B(n2333), .Y(n2287) );
NOR2X4TS U4094 ( .A(n2442), .B(n3964), .Y(n3889) );
OR2X8TS U4095 ( .A(n4425), .B(n4424), .Y(n2321) );
INVX4TS U4096 ( .A(n5407), .Y(n5481) );
NAND2X4TS U4097 ( .A(n3835), .B(n2699), .Y(n3854) );
XOR2X4TS U4098 ( .A(n2285), .B(n2707), .Y(n3868) );
NAND3X6TS U4099 ( .A(n2572), .B(n2984), .C(n2571), .Y(n2570) );
OR2X8TS U4100 ( .A(n4893), .B(n4892), .Y(n2984) );
OR2X8TS U4101 ( .A(n4846), .B(n4845), .Y(n3189) );
INVX8TS U4102 ( .A(n5118), .Y(n4505) );
INVX2TS U4103 ( .A(n5661), .Y(n5258) );
ADDFHX2TS U4104 ( .A(n5265), .B(n5264), .CI(n5263), .CO(n5266), .S(n5661) );
XOR2X2TS U4105 ( .A(n2441), .B(n3787), .Y(n3788) );
INVX6TS U4106 ( .A(n5127), .Y(n5356) );
OAI21X1TS U4107 ( .A0(n5510), .A1(n5385), .B0(n5387), .Y(n5369) );
INVX6TS U4108 ( .A(n2658), .Y(n2836) );
NAND2X8TS U4109 ( .A(n2715), .B(n4641), .Y(n3016) );
OAI21X4TS U4110 ( .A0(n4235), .A1(n4234), .B0(n4233), .Y(n4264) );
NOR2X4TS U4111 ( .A(n4183), .B(n4182), .Y(n4235) );
AND2X8TS U4112 ( .A(n5537), .B(n5538), .Y(n3079) );
NOR2X8TS U4113 ( .A(n5535), .B(n5531), .Y(n5537) );
NAND2X4TS U4114 ( .A(n3227), .B(n3249), .Y(n3228) );
NAND2X4TS U4115 ( .A(n3397), .B(n3412), .Y(n3249) );
NOR2X8TS U4116 ( .A(n3553), .B(n3554), .Y(n2549) );
NAND2X4TS U4117 ( .A(n2639), .B(n2874), .Y(n2592) );
INVX4TS U4118 ( .A(n2639), .Y(n2713) );
OAI21X4TS U4119 ( .A0(n3544), .A1(n3543), .B0(n3542), .Y(n2680) );
INVX6TS U4120 ( .A(n5608), .Y(n5638) );
NOR2X2TS U4121 ( .A(n7520), .B(n7548), .Y(n7519) );
XNOR2X4TS U4122 ( .A(n3110), .B(n2430), .Y(n4100) );
NAND2X6TS U4123 ( .A(FPMULT_Sgf_operation_EVEN1_S_B[18]), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(add_x_69_n188) );
ADDFHX4TS U4124 ( .A(n4963), .B(n4962), .CI(n4961), .CO(n5022), .S(n4952) );
OAI21X1TS U4125 ( .A0(n5022), .A1(n5021), .B0(n5020), .Y(n2852) );
NOR2X4TS U4126 ( .A(n2860), .B(n3048), .Y(n7244) );
OAI22X2TS U4127 ( .A0(n2349), .A1(n3446), .B0(n3664), .B1(n3422), .Y(n3437)
);
XNOR2X4TS U4128 ( .A(n4936), .B(n4938), .Y(n3978) );
OAI21X4TS U4129 ( .A0(n7244), .A1(n7240), .B0(n7245), .Y(n6211) );
NAND2X4TS U4130 ( .A(n2863), .B(n2861), .Y(n4485) );
OAI2BB2X4TS U4131 ( .B0(n2349), .B1(DP_OP_497J211_123_1725_n312), .A0N(n3611), .A1N(n7708), .Y(n3643) );
NAND2BX4TS U4132 ( .AN(n3818), .B(n3805), .Y(n2277) );
OR2X8TS U4133 ( .A(n4086), .B(n4085), .Y(n4645) );
ADDFHX4TS U4134 ( .A(n4132), .B(n4131), .CI(n4130), .CO(n4134), .S(n4086) );
OAI22X4TS U4135 ( .A0(n3925), .A1(n2593), .B0(n2303), .B1(n3924), .Y(n3938)
);
ADDFHX2TS U4136 ( .A(n3372), .B(n3371), .CI(n3370), .CO(n3382), .S(n3377) );
NOR2X8TS U4137 ( .A(n5235), .B(n5234), .Y(n5319) );
ADDFHX4TS U4138 ( .A(n5172), .B(n5171), .CI(n5170), .CO(n5229), .S(n5191) );
OAI21X4TS U4139 ( .A0(n2231), .A1(n2354), .B0(n3966), .Y(n4097) );
ADDFHX4TS U4140 ( .A(n4129), .B(n4128), .CI(n4127), .CO(n4909), .S(n4132) );
ADDFHX4TS U4141 ( .A(n3919), .B(n3918), .CI(n3917), .CO(n4129), .S(n3991) );
NAND3X6TS U4142 ( .A(n2694), .B(n2693), .C(n2692), .Y(n2691) );
NAND2X6TS U4143 ( .A(n2939), .B(n2817), .Y(n3785) );
INVX2TS U4144 ( .A(n3775), .Y(n2939) );
XNOR2X4TS U4145 ( .A(n3774), .B(n3773), .Y(n2817) );
NOR2X6TS U4146 ( .A(n2868), .B(n3298), .Y(n3293) );
NOR2X6TS U4147 ( .A(n6248), .B(n5518), .Y(n5532) );
OAI22X2TS U4148 ( .A0(n5031), .A1(n5070), .B0(n5030), .B1(n5029), .Y(n5074)
);
NAND2X4TS U4149 ( .A(n2983), .B(n5491), .Y(n2571) );
XOR2X4TS U4150 ( .A(n4819), .B(n4820), .Y(n2805) );
NAND2X8TS U4151 ( .A(n2998), .B(n2999), .Y(n5066) );
ADDFHX4TS U4152 ( .A(n3552), .B(n3551), .CI(n3550), .CO(n3554), .S(n3464) );
OAI22X2TS U4153 ( .A0(n2349), .A1(n3441), .B0(n2434), .B1(n3519), .Y(n3436)
);
NAND2X4TS U4154 ( .A(n4180), .B(n4218), .Y(n3058) );
NAND2BX4TS U4155 ( .AN(n3166), .B(n6893), .Y(n3840) );
NAND2X4TS U4156 ( .A(n4014), .B(n4037), .Y(n3064) );
NOR2X4TS U4157 ( .A(n3066), .B(n3065), .Y(n4037) );
NOR2X6TS U4158 ( .A(n3240), .B(DP_OP_497J211_123_1725_n638), .Y(n3206) );
OAI2BB1X2TS U4159 ( .A0N(n2864), .A1N(n2866), .B0(n4457), .Y(n2863) );
BUFX8TS U4160 ( .A(DP_OP_498J211_124_1725_n797), .Y(n6893) );
ADDFHX4TS U4161 ( .A(n3549), .B(n3548), .CI(n3547), .CO(n3577), .S(n3552) );
OAI2BB1X4TS U4162 ( .A0N(n3418), .A1N(n3417), .B0(n2716), .Y(n3439) );
OAI21X4TS U4163 ( .A0(n3417), .A1(n3418), .B0(n3416), .Y(n2716) );
NAND2X8TS U4164 ( .A(n2908), .B(n3716), .Y(n3097) );
NAND3X8TS U4165 ( .A(n2752), .B(n3722), .C(n2751), .Y(n2908) );
INVX2TS U4166 ( .A(n4235), .Y(n4184) );
OAI22X2TS U4167 ( .A0(n3409), .A1(n3612), .B0(n3342), .B1(n2299), .Y(n3415)
);
OAI22X4TS U4168 ( .A0(n2837), .A1(n4955), .B0(n4549), .B1(n5032), .Y(n4554)
);
INVX16TS U4169 ( .A(n2776), .Y(n3521) );
NAND2BX1TS U4170 ( .AN(n3318), .B(n2776), .Y(n2778) );
OAI22X2TS U4171 ( .A0(n4970), .A1(n2603), .B0(n4537), .B1(n2378), .Y(n4341)
);
OAI21X1TS U4172 ( .A0(n7230), .A1(n7229), .B0(n7228), .Y(n7235) );
AND2X6TS U4173 ( .A(n3904), .B(n3110), .Y(n3078) );
OAI21X4TS U4174 ( .A0(n3399), .A1(n2556), .B0(n3398), .Y(n2554) );
NAND2X6TS U4175 ( .A(DP_OP_497J211_123_1725_n782), .B(
DP_OP_497J211_123_1725_n793), .Y(n2916) );
NAND2X4TS U4176 ( .A(n5707), .B(DP_OP_497J211_123_1725_n793), .Y(n2761) );
OAI2BB1X4TS U4177 ( .A0N(n3267), .A1N(n3266), .B0(n2910), .Y(n3522) );
NAND2X4TS U4178 ( .A(n2283), .B(n4904), .Y(n2525) );
NAND2X6TS U4179 ( .A(n2283), .B(n2583), .Y(n2582) );
NAND3X6TS U4180 ( .A(n4645), .B(n2695), .C(n2283), .Y(n2584) );
OAI22X2TS U4181 ( .A0(n5031), .A1(n4550), .B0(n5071), .B1(n4495), .Y(n4540)
);
ADDFHX2TS U4182 ( .A(n5415), .B(n5414), .CI(n5413), .CO(n5569), .S(n5424) );
XNOR2X4TS U4183 ( .A(n5570), .B(n5198), .Y(n5251) );
OAI22X4TS U4184 ( .A0(n4923), .A1(n2237), .B0(n5338), .B1(n4107), .Y(n4912)
);
OAI22X2TS U4185 ( .A0(n2436), .A1(n4537), .B0(n2377), .B1(n4970), .Y(n4409)
);
OAI2BB1X4TS U4186 ( .A0N(n4335), .A1N(n4334), .B0(n4333), .Y(n4408) );
NOR2BX2TS U4187 ( .AN(n3740), .B(n3093), .Y(n3131) );
NOR2X4TS U4188 ( .A(DP_OP_497J211_123_1725_n631), .B(n2320), .Y(n3208) );
NOR2X4TS U4189 ( .A(DP_OP_497J211_123_1725_n631), .B(n3479), .Y(n2976) );
NOR2X4TS U4190 ( .A(DP_OP_497J211_123_1725_n631), .B(
DP_OP_497J211_123_1725_n638), .Y(n4730) );
NOR2X4TS U4191 ( .A(DP_OP_497J211_123_1725_n631), .B(n3220), .Y(n3205) );
NAND2X6TS U4192 ( .A(n2742), .B(n3102), .Y(n2747) );
NOR2X8TS U4193 ( .A(n2630), .B(n3690), .Y(n5312) );
NAND2X8TS U4194 ( .A(n4514), .B(n4515), .Y(n4526) );
XOR2X4TS U4195 ( .A(n2754), .B(n2908), .Y(n4676) );
OA21X2TS U4196 ( .A0(n3514), .A1(n3513), .B0(n3512), .Y(n2312) );
NOR2X4TS U4197 ( .A(n2236), .B(n3516), .Y(n3091) );
OAI22X2TS U4198 ( .A0(n2351), .A1(n3441), .B0(n3342), .B1(n3519), .Y(n3350)
);
ADDFHX4TS U4199 ( .A(n5241), .B(n5240), .CI(n5239), .CO(n5334), .S(n5267) );
ADDFHX4TS U4200 ( .A(n5250), .B(n5249), .CI(n5248), .CO(n5351), .S(n5240) );
ADDFHX4TS U4201 ( .A(n5639), .B(n5638), .CI(n3149), .CO(n5648), .S(n5626) );
ADDFHX4TS U4202 ( .A(n4289), .B(n4288), .CI(n4287), .CO(n4344), .S(n4226) );
ADDFHX4TS U4203 ( .A(n4789), .B(n4014), .CI(n4013), .CO(n4046), .S(n4035) );
NOR2BX2TS U4204 ( .AN(n4027), .B(n4933), .Y(n4947) );
OAI21X4TS U4205 ( .A0(n3768), .A1(n3782), .B0(n3885), .Y(n3777) );
ADDFHX2TS U4206 ( .A(n4023), .B(n4022), .CI(n4021), .CO(n4036), .S(n4031) );
NOR2X4TS U4207 ( .A(n5565), .B(n5563), .Y(n5591) );
XNOR2X4TS U4208 ( .A(n5419), .B(n5345), .Y(n5346) );
OAI22X2TS U4209 ( .A0(n5165), .A1(n2303), .B0(n2593), .B1(n5207), .Y(n5227)
);
NAND2X8TS U4210 ( .A(n4946), .B(n4945), .Y(n2619) );
ADDFHX2TS U4211 ( .A(n3946), .B(n3945), .CI(n3944), .CO(n4091), .S(n3988) );
ADDFHX2TS U4212 ( .A(n5184), .B(n5604), .CI(n5183), .CO(n5217), .S(n5163) );
NOR2X6TS U4213 ( .A(n5644), .B(n5643), .Y(n5646) );
ADDFHX4TS U4214 ( .A(n3382), .B(n3381), .CI(n3380), .CO(n3424), .S(n3387) );
NOR2X4TS U4215 ( .A(n5097), .B(n5099), .Y(n5102) );
NOR2X6TS U4216 ( .A(n5079), .B(n5078), .Y(n5099) );
NAND2X4TS U4217 ( .A(n4972), .B(n3173), .Y(n4401) );
OAI21X4TS U4218 ( .A0(n5762), .A1(n5735), .B0(n2977), .Y(add_x_69_n205) );
OAI22X2TS U4219 ( .A0(n3409), .A1(n3571), .B0(n3342), .B1(n3606), .Y(n3366)
);
AND2X4TS U4220 ( .A(n3035), .B(n3034), .Y(n4273) );
INVX2TS U4221 ( .A(n4363), .Y(n4305) );
ADDFHX4TS U4222 ( .A(n5305), .B(n5304), .CI(n5303), .CO(n5371), .S(n5306) );
NOR2X4TS U4223 ( .A(n4450), .B(DP_OP_498J211_124_1725_n732), .Y(n3035) );
OAI21X4TS U4224 ( .A0(n7121), .A1(n7115), .B0(n7116), .Y(n7111) );
NOR2X4TS U4225 ( .A(n2651), .B(n3082), .Y(n5493) );
NOR2BX2TS U4226 ( .AN(n4108), .B(n4093), .Y(n4029) );
ADDFHX4TS U4227 ( .A(n5217), .B(n5216), .CI(n5215), .CO(n5268), .S(n5231) );
BUFX12TS U4228 ( .A(n3101), .Y(n2742) );
ADDFHX2TS U4229 ( .A(n3437), .B(n3436), .CI(n3435), .CO(n3547), .S(n3438) );
ADDFHX4TS U4230 ( .A(n5164), .B(n5163), .CI(n5162), .CO(n5233), .S(n5194) );
XNOR2X4TS U4231 ( .A(n4916), .B(n5345), .Y(n4112) );
OAI22X2TS U4232 ( .A0(n4002), .A1(n4093), .B0(n4001), .B1(n4094), .Y(n4020)
);
NAND2X4TS U4233 ( .A(n2546), .B(n3711), .Y(n5154) );
OAI21X4TS U4234 ( .A0(n5535), .A1(n5534), .B0(n5533), .Y(n5536) );
XOR2X4TS U4235 ( .A(n2815), .B(n3070), .Y(n4897) );
XOR2X4TS U4236 ( .A(n4065), .B(n2943), .Y(n2942) );
ADDFHX4TS U4237 ( .A(n4082), .B(n4081), .CI(n4080), .CO(n4083), .S(n4076) );
NOR2X6TS U4238 ( .A(n5487), .B(n5486), .Y(n5531) );
ADDFHX2TS U4239 ( .A(n4842), .B(n4841), .CI(n4840), .CO(n4862), .S(n4843) );
NAND2X2TS U4240 ( .A(n4758), .B(n4757), .Y(n4759) );
NOR2BX1TS U4241 ( .AN(n4108), .B(n5416), .Y(n3946) );
NAND2BX1TS U4242 ( .AN(n4108), .B(n5198), .Y(n3947) );
XNOR2X2TS U4243 ( .A(n4108), .B(n5345), .Y(n3967) );
NAND2X4TS U4244 ( .A(n4846), .B(n4845), .Y(n5460) );
INVX4TS U4245 ( .A(n2985), .Y(n2982) );
XNOR2X4TS U4246 ( .A(n3727), .B(n3726), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
INVX3TS U4247 ( .A(n3264), .Y(n3726) );
XOR2X2TS U4248 ( .A(n3022), .B(n3287), .Y(n3021) );
NAND2BX2TS U4249 ( .AN(n3023), .B(n3259), .Y(n3022) );
INVX6TS U4250 ( .A(n2509), .Y(n2500) );
ADDFHX4TS U4251 ( .A(n3991), .B(n3990), .CI(n3989), .CO(n4131), .S(n4077) );
OAI22X2TS U4252 ( .A0(n5338), .A1(n3948), .B0(n2376), .B1(n3961), .Y(n3919)
);
NAND2X4TS U4253 ( .A(n4992), .B(n4991), .Y(n5009) );
CMPR22X2TS U4254 ( .A(n4413), .B(n4412), .CO(n4443), .S(n4388) );
NAND2X8TS U4255 ( .A(n5532), .B(n5537), .Y(n5763) );
ADDFHX4TS U4256 ( .A(n4891), .B(n4890), .CI(n4889), .CO(n4892), .S(n4885) );
AOI21X2TS U4257 ( .A0(n4856), .A1(n4664), .B0(n4663), .Y(n4669) );
ADDFHX4TS U4258 ( .A(n3361), .B(n3360), .CI(n3359), .CO(n3391), .S(n3381) );
OAI22X2TS U4259 ( .A0(n3521), .A1(n3441), .B0(n3393), .B1(n3519), .Y(n3360)
);
AND2X4TS U4260 ( .A(n3043), .B(n3737), .Y(n2330) );
NAND2X4TS U4261 ( .A(n4893), .B(n4892), .Y(n5539) );
NOR2X8TS U4262 ( .A(n4946), .B(n4945), .Y(n5197) );
OAI22X4TS U4263 ( .A0(n4095), .A1(n4094), .B0(n5167), .B1(n4093), .Y(n4929)
);
AOI21X4TS U4264 ( .A0(n2834), .A1(n5694), .B0(n5642), .Y(
DP_OP_499J211_125_1651_n34) );
NOR2X8TS U4265 ( .A(n5464), .B(n3153), .Y(n5497) );
OR2X4TS U4266 ( .A(n5494), .B(n3152), .Y(n3153) );
NAND2X8TS U4267 ( .A(n2979), .B(n5739), .Y(n5762) );
XNOR2X4TS U4268 ( .A(n3110), .B(n2438), .Y(n3894) );
XOR2X4TS U4269 ( .A(n4807), .B(n4806), .Y(n4813) );
NAND2X6TS U4270 ( .A(n2280), .B(n2500), .Y(n3063) );
XNOR2X4TS U4271 ( .A(n5179), .B(n4921), .Y(n3924) );
NAND2X4TS U4272 ( .A(n5326), .B(n5325), .Y(n5686) );
NAND2X4TS U4273 ( .A(n4780), .B(n4779), .Y(n4782) );
INVX2TS U4274 ( .A(n4780), .Y(n4022) );
AOI21X4TS U4275 ( .A0(n5141), .A1(n3176), .B0(n4795), .Y(n5053) );
OAI21X2TS U4276 ( .A0(n5130), .A1(n4787), .B0(n5131), .Y(n5141) );
XOR2X4TS U4277 ( .A(n3883), .B(n3880), .Y(n2781) );
XNOR2X4TS U4278 ( .A(n4750), .B(n4856), .Y(n4837) );
NOR2X4TS U4279 ( .A(n5763), .B(n5762), .Y(add_x_69_n204) );
NOR2X4TS U4280 ( .A(n3342), .B(n2298), .Y(n3339) );
XNOR2X4TS U4281 ( .A(n2598), .B(n2597), .Y(n2755) );
NAND2X4TS U4282 ( .A(n3500), .B(n2770), .Y(n2597) );
INVX6TS U4283 ( .A(n5679), .Y(n5689) );
INVX8TS U4284 ( .A(n2882), .Y(n2349) );
OA21X4TS U4285 ( .A0(n3695), .A1(n3694), .B0(n3693), .Y(n2873) );
OAI2BB1X2TS U4286 ( .A0N(n3663), .A1N(n3662), .B0(n2875), .Y(n3672) );
OAI21X2TS U4287 ( .A0(n3662), .A1(n3663), .B0(n3661), .Y(n2875) );
ADDFHX4TS U4288 ( .A(n3670), .B(n3669), .CI(n3668), .CO(n3696), .S(n3663) );
ADDFHX4TS U4289 ( .A(n3434), .B(n3433), .CI(n3432), .CO(n3548), .S(n3440) );
ADDFHX4TS U4290 ( .A(n3431), .B(n3430), .CI(n3429), .CO(n3535), .S(n3433) );
XNOR2X4TS U4291 ( .A(n3135), .B(n4997), .Y(n5719) );
NOR2X4TS U4292 ( .A(n2950), .B(n2240), .Y(n2948) );
ADDHX4TS U4293 ( .A(DP_OP_496J211_122_3540_n1513), .B(FPMULT_Op_MX[19]),
.CO(n3778), .S(n3772) );
ADDFHX4TS U4294 ( .A(n4561), .B(n4560), .CI(n4559), .CO(n4975), .S(n4530) );
ADDFHX4TS U4295 ( .A(n4494), .B(n4493), .CI(n4492), .CO(n4560), .S(n4501) );
ADDFHX2TS U4296 ( .A(n4533), .B(n4532), .CI(n4531), .CO(n4953), .S(n4561) );
NOR2X2TS U4297 ( .A(n5495), .B(n5494), .Y(n5467) );
AOI21X2TS U4298 ( .A0(n5538), .A1(n5526), .B0(n5488), .Y(n5489) );
NOR2X4TS U4299 ( .A(n5040), .B(n5039), .Y(n5097) );
ADDFHX4TS U4300 ( .A(n5069), .B(n5068), .CI(n5067), .CO(n5079), .S(n5039) );
OAI22X2TS U4301 ( .A0(n4633), .A1(n3771), .B0(n4102), .B1(n2644), .Y(n4103)
);
ADDFHX4TS U4302 ( .A(n4883), .B(n4882), .CI(n4881), .CO(n4884), .S(n4869) );
NOR2X8TS U4303 ( .A(n5435), .B(n5436), .Y(n5679) );
XNOR2X4TS U4304 ( .A(n3495), .B(n2922), .Y(n2921) );
NAND3X4TS U4305 ( .A(n2929), .B(n2874), .C(n2930), .Y(n2591) );
NOR2X4TS U4306 ( .A(n3692), .B(n3694), .Y(n2874) );
ADDFHX4TS U4307 ( .A(n5628), .B(n5627), .CI(n5626), .CO(n5641), .S(n5624) );
NAND2X8TS U4308 ( .A(n2624), .B(n2775), .Y(n2795) );
NAND3X6TS U4309 ( .A(n2714), .B(n2770), .C(n3500), .Y(n2624) );
NAND2X6TS U4310 ( .A(n3428), .B(n3427), .Y(n2714) );
OR2X8TS U4311 ( .A(n3089), .B(n3742), .Y(n2318) );
AND2X8TS U4312 ( .A(n3687), .B(n3686), .Y(n3089) );
NOR2X8TS U4313 ( .A(n3687), .B(n3686), .Y(n3742) );
NAND2X4TS U4314 ( .A(n5448), .B(n5447), .Y(n5675) );
XNOR2X4TS U4315 ( .A(n2929), .B(n2637), .Y(n3687) );
NAND2X4TS U4316 ( .A(n2638), .B(n2557), .Y(n2637) );
OR2X4TS U4317 ( .A(n4427), .B(n4426), .Y(n4642) );
XOR2X4TS U4318 ( .A(n4470), .B(n2573), .Y(n4427) );
XOR2X4TS U4319 ( .A(n6252), .B(n6251), .Y(n6253) );
NOR2X8TS U4320 ( .A(n5128), .B(n3105), .Y(n6213) );
BUFX12TS U4321 ( .A(n5127), .Y(n3105) );
ADDFHX4TS U4322 ( .A(n4341), .B(n4340), .CI(n4339), .CO(n4385), .S(n4356) );
NAND2X4TS U4323 ( .A(n3055), .B(n3053), .Y(n4340) );
NOR2X8TS U4324 ( .A(n5236), .B(n5237), .Y(n2702) );
XOR2X4TS U4325 ( .A(n5570), .B(n5167), .Y(n4095) );
NAND2X8TS U4326 ( .A(n2946), .B(n2945), .Y(n5570) );
NAND2X4TS U4327 ( .A(n3775), .B(n3895), .Y(n3783) );
NAND2X4TS U4328 ( .A(n4084), .B(n4083), .Y(n4653) );
ADDFHX4TS U4329 ( .A(n4079), .B(n4078), .CI(n4077), .CO(n4085), .S(n4084) );
OAI2BB1X4TS U4330 ( .A0N(n4900), .A1N(n4899), .B0(n4898), .Y(n4998) );
NAND2BX1TS U4331 ( .AN(n5593), .B(n5592), .Y(n5594) );
OAI21X4TS U4332 ( .A0(n5566), .A1(n5565), .B0(n5564), .Y(n5593) );
OR2X8TS U4333 ( .A(n2781), .B(n2239), .Y(n4633) );
ADDFHX4TS U4334 ( .A(n4543), .B(n4542), .CI(n4541), .CO(n4979), .S(n4528) );
NOR2X8TS U4335 ( .A(n2266), .B(n4570), .Y(n5008) );
XOR2X4TS U4336 ( .A(n5105), .B(n4564), .Y(n4571) );
OAI22X2TS U4337 ( .A0(n5070), .A1(n2603), .B0(n5029), .B1(n2378), .Y(n4444)
);
NOR2X4TS U4338 ( .A(n7237), .B(n7244), .Y(n6212) );
XNOR2X4TS U4339 ( .A(n2890), .B(n2509), .Y(n2700) );
XOR2X4TS U4340 ( .A(n3514), .B(n3253), .Y(n3024) );
XNOR2X4TS U4341 ( .A(n5761), .B(n5760), .Y(FPMULT_Sgf_operation_Result[25])
);
OAI21X4TS U4342 ( .A0(n6252), .A1(n5756), .B0(n5755), .Y(n5761) );
NOR2X8TS U4343 ( .A(n5536), .B(n3079), .Y(n5735) );
NOR2X8TS U4344 ( .A(n5740), .B(n5746), .Y(n2979) );
AND2X8TS U4345 ( .A(n2800), .B(n4790), .Y(n5746) );
NAND2X2TS U4346 ( .A(n3785), .B(n3783), .Y(n3776) );
AOI21X4TS U4347 ( .A0(n5754), .A1(n5739), .B0(n5743), .Y(n5744) );
OAI21X4TS U4348 ( .A0(n5455), .A1(n5456), .B0(n5457), .Y(n5461) );
AOI21X4TS U4349 ( .A0(n5091), .A1(n5089), .B0(n4836), .Y(n5455) );
NAND2X4TS U4350 ( .A(n4843), .B(n4844), .Y(n5457) );
XNOR2X4TS U4351 ( .A(n4767), .B(n4766), .Y(n4799) );
NAND2X2TS U4352 ( .A(n4765), .B(n4764), .Y(n4767) );
NAND2X8TS U4353 ( .A(n3518), .B(n3517), .Y(n3718) );
NOR2X8TS U4354 ( .A(n4999), .B(n4998), .Y(n5672) );
XNOR2X4TS U4355 ( .A(n2700), .B(n5324), .Y(n4999) );
AND2X8TS U4356 ( .A(n5695), .B(n5694), .Y(n7685) );
OR2X4TS U4357 ( .A(n5641), .B(n5640), .Y(n5694) );
NOR2X8TS U4358 ( .A(n2546), .B(n3711), .Y(n5155) );
XOR2X4TS U4359 ( .A(n2547), .B(n2872), .Y(n2546) );
NAND3X4TS U4360 ( .A(n2591), .B(n2592), .C(n2873), .Y(n2547) );
NOR2X8TS U4361 ( .A(n5646), .B(n5691), .Y(n5695) );
NOR2X8TS U4362 ( .A(n5624), .B(n5625), .Y(n5691) );
INVX6TS U4363 ( .A(n2817), .Y(n3895) );
OAI2BB1X4TS U4364 ( .A0N(n4065), .A1N(n2943), .B0(n2941), .Y(n3990) );
XNOR2X4TS U4365 ( .A(n5619), .B(n3187), .Y(n3149) );
OAI21X4TS U4366 ( .A0(n5155), .A1(n5284), .B0(n5154), .Y(n3041) );
CMPR22X2TS U4367 ( .A(n4747), .B(n4746), .CO(n4839), .S(n4823) );
XOR2X4TS U4368 ( .A(n4838), .B(n2645), .Y(n4844) );
XOR2X4TS U4369 ( .A(n4837), .B(n4839), .Y(n2645) );
NOR2X8TS U4370 ( .A(n5512), .B(n5608), .Y(n5535) );
NAND2X2TS U4371 ( .A(n5311), .B(n5309), .Y(n4997) );
ADDFHX4TS U4372 ( .A(n3462), .B(n3461), .CI(n3460), .CO(n3463), .S(n3428) );
ADDFHX2TS U4373 ( .A(n3440), .B(n3439), .CI(n3438), .CO(n3551), .S(n3460) );
XOR2X4TS U4374 ( .A(n2328), .B(n2288), .Y(n3689) );
OAI21X4TS U4375 ( .A0(n5444), .A1(n5443), .B0(n2620), .Y(n2505) );
OAI21X4TS U4376 ( .A0(n2542), .A1(n3423), .B0(n2544), .Y(n2541) );
ADDFHX2TS U4377 ( .A(n3600), .B(n3599), .CI(n3598), .CO(n3649), .S(n3592) );
ADDFHX2TS U4378 ( .A(n4864), .B(n4863), .CI(n4862), .CO(n4881), .S(n4845) );
NAND2X2TS U4379 ( .A(n5364), .B(n2264), .Y(n2822) );
MX2X1TS U4380 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(n6973) );
OAI21X2TS U4381 ( .A0(n4334), .A1(n4335), .B0(n4332), .Y(n4333) );
INVX2TS U4382 ( .A(n2727), .Y(n3909) );
NOR3X6TS U4383 ( .A(DP_OP_496J211_122_3540_n1107), .B(
DP_OP_496J211_122_3540_n1113), .C(n2521), .Y(n2520) );
INVX2TS U4384 ( .A(n2986), .Y(n3113) );
INVX12TS U4385 ( .A(n2996), .Y(n4921) );
INVX2TS U4386 ( .A(n4565), .Y(n4296) );
NAND2X4TS U4387 ( .A(n3779), .B(n2967), .Y(n2956) );
INVX2TS U4388 ( .A(DP_OP_496J211_122_3540_n1193), .Y(n2993) );
NAND2X2TS U4389 ( .A(DP_OP_496J211_122_3540_n1499), .B(
DP_OP_496J211_122_3540_n1512), .Y(n2307) );
INVX2TS U4390 ( .A(n2240), .Y(n3008) );
INVX2TS U4391 ( .A(n3623), .Y(n3362) );
NAND2X4TS U4392 ( .A(n2947), .B(n2949), .Y(n2945) );
AOI21X2TS U4393 ( .A0(n3007), .A1(n3923), .B0(n2240), .Y(n2947) );
INVX2TS U4394 ( .A(n2917), .Y(n2914) );
NAND2X1TS U4395 ( .A(n5549), .B(n5548), .Y(n5599) );
NAND2X1TS U4396 ( .A(n5361), .B(n5374), .Y(n5362) );
NAND2X1TS U4397 ( .A(n5630), .B(n5653), .Y(n5606) );
NAND2X1TS U4398 ( .A(n3708), .B(n3707), .Y(n5398) );
NAND2X1TS U4399 ( .A(n5157), .B(n5156), .Y(n5397) );
XOR2X1TS U4400 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[22]), .Y(n2685) );
INVX2TS U4401 ( .A(n3724), .Y(n3020) );
NAND2X1TS U4402 ( .A(n6290), .B(n6194), .Y(n6306) );
MX2X1TS U4403 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(n6976) );
MX2X1TS U4404 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(n6967) );
CLKAND2X2TS U4405 ( .A(n7870), .B(n2479), .Y(n6079) );
CLKAND2X2TS U4406 ( .A(n7872), .B(n2481), .Y(n5860) );
INVX2TS U4407 ( .A(n4584), .Y(n3944) );
NAND2BX2TS U4408 ( .AN(n4402), .B(n4404), .Y(n2838) );
NAND2X4TS U4409 ( .A(n3141), .B(n7673), .Y(n2654) );
INVX2TS U4410 ( .A(n4615), .Y(n4927) );
NAND2X4TS U4411 ( .A(n2535), .B(n2534), .Y(n2540) );
NAND2X4TS U4412 ( .A(n4526), .B(n4527), .Y(n2724) );
NAND2X4TS U4413 ( .A(n2658), .B(n4526), .Y(n2725) );
INVX4TS U4414 ( .A(n3294), .Y(n3299) );
INVX2TS U4415 ( .A(n2871), .Y(n3301) );
INVX2TS U4416 ( .A(n4936), .Y(n2995) );
NAND2X2TS U4417 ( .A(n3856), .B(n3855), .Y(n3859) );
INVX2TS U4418 ( .A(n5572), .Y(n2352) );
NAND2X4TS U4419 ( .A(n3136), .B(n2880), .Y(n2879) );
NAND2X1TS U4420 ( .A(n3828), .B(n3748), .Y(n3749) );
INVX6TS U4421 ( .A(n3099), .Y(n2560) );
INVX4TS U4422 ( .A(n3557), .Y(n3340) );
INVX2TS U4423 ( .A(n3283), .Y(n3341) );
INVX4TS U4424 ( .A(n3254), .Y(n3441) );
NAND2BXLTS U4425 ( .AN(n7370), .B(n7611), .Y(n5938) );
OAI21X2TS U4426 ( .A0(n4838), .A1(n4839), .B0(n4837), .Y(n2737) );
NOR2X4TS U4427 ( .A(n3044), .B(n6898), .Y(n2961) );
NAND2X4TS U4428 ( .A(n3681), .B(n2557), .Y(n2558) );
INVX4TS U4429 ( .A(n3256), .Y(n3446) );
NAND2X4TS U4430 ( .A(n2934), .B(n2932), .Y(n3478) );
OAI21X2TS U4431 ( .A0(n3269), .A1(n2935), .B0(n3268), .Y(n2934) );
INVX2TS U4432 ( .A(n4371), .Y(n2719) );
NAND2X4TS U4433 ( .A(n4309), .B(n4306), .Y(n2721) );
NOR2X4TS U4434 ( .A(n4160), .B(n4165), .Y(n4172) );
INVX4TS U4435 ( .A(n4223), .Y(n4204) );
NOR2X4TS U4436 ( .A(n4269), .B(n4268), .Y(n4270) );
NAND2X1TS U4437 ( .A(n3466), .B(n3465), .Y(n3625) );
INVX4TS U4438 ( .A(n4188), .Y(n4712) );
INVX4TS U4439 ( .A(n4673), .Y(n4671) );
NAND2X2TS U4440 ( .A(n2284), .B(n3099), .Y(n2796) );
NAND2X2TS U4441 ( .A(n3234), .B(n3233), .Y(n3261) );
INVX2TS U4442 ( .A(n3213), .Y(n2276) );
INVX2TS U4443 ( .A(n3234), .Y(n2596) );
AND2X2TS U4444 ( .A(n5429), .B(n5564), .Y(n5430) );
NOR2X1TS U4445 ( .A(n6195), .B(n7772), .Y(n6307) );
NOR2X1TS U4446 ( .A(n6205), .B(n7768), .Y(n6450) );
AOI2BB1XLTS U4447 ( .A0N(n6051), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6052) );
AOI2BB1XLTS U4448 ( .A0N(n7823), .A1N(n8629), .B0(n6053), .Y(n6054) );
NOR3XLTS U4449 ( .A(n8646), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n7807),
.Y(n6053) );
OR2X1TS U4450 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n7131) );
NAND2X1TS U4451 ( .A(n3120), .B(n5463), .Y(n2734) );
NOR3XLTS U4452 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n7257) );
MX2X1TS U4453 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(n6970) );
NAND2X1TS U4454 ( .A(n5635), .B(n5652), .Y(n5636) );
INVX8TS U4455 ( .A(n3715), .Y(n3516) );
CLKAND2X2TS U4456 ( .A(begin_operation), .B(operation[1]), .Y(n7283) );
NAND3XLTS U4457 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n7272) );
AOI31XLTS U4458 ( .A0(n7270), .A1(n7269), .A2(n7268), .B0(n7275), .Y(n7273)
);
INVX2TS U4459 ( .A(n6091), .Y(n5863) );
INVX2TS U4460 ( .A(n6147), .Y(n6149) );
CLKAND2X2TS U4461 ( .A(n7871), .B(n2475), .Y(n6075) );
CLKAND2X2TS U4462 ( .A(n7869), .B(n2477), .Y(n6083) );
OAI21XLTS U4463 ( .A0(n8802), .A1(n7620), .B0(n7572), .Y(n7573) );
OAI21XLTS U4464 ( .A0(n7614), .A1(n8796), .B0(n7579), .Y(n7590) );
OAI21X2TS U4465 ( .A0(n5767), .A1(n6614), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n6905) );
OAI21X2TS U4466 ( .A0(n6213), .A1(n7251), .B0(n6214), .Y(n5129) );
OAI31X1TS U4467 ( .A0(n2350), .A1(n6263), .A2(n6262), .B0(n7811), .Y(n1690)
);
NOR2X1TS U4468 ( .A(n1335), .B(n1334), .Y(n8299) );
INVX2TS U4469 ( .A(n3785), .Y(n2965) );
ADDFX2TS U4470 ( .A(n6893), .B(DP_OP_496J211_122_3540_n1502), .CI(n3802),
.CO(n3803), .S(n3781) );
NOR2X4TS U4471 ( .A(n4292), .B(n4290), .Y(n2657) );
INVX2TS U4472 ( .A(n4220), .Y(n4290) );
NOR2X1TS U4473 ( .A(n4402), .B(n7700), .Y(n2665) );
ADDFHX2TS U4474 ( .A(DP_OP_496J211_122_3540_n1514), .B(FPMULT_Op_MX[20]),
.CI(n3778), .CO(n3802), .S(n3775) );
INVX2TS U4475 ( .A(n3819), .Y(n3821) );
INVX2TS U4476 ( .A(n4401), .Y(n4405) );
OR2X2TS U4477 ( .A(n4972), .B(n3173), .Y(n4403) );
OAI21X2TS U4478 ( .A0(n4957), .A1(n3108), .B0(n4956), .Y(n3106) );
NOR2X4TS U4479 ( .A(n5706), .B(n6893), .Y(n4292) );
NOR2X2TS U4480 ( .A(n5029), .B(n2603), .Y(n4413) );
NAND2X1TS U4481 ( .A(n7728), .B(DP_OP_496J211_122_3540_n1203), .Y(n3773) );
NAND2X1TS U4482 ( .A(n7716), .B(DP_OP_496J211_122_3540_n1199), .Y(n3780) );
INVX2TS U4483 ( .A(n2966), .Y(n2927) );
INVX2TS U4484 ( .A(n2954), .Y(n2944) );
INVX4TS U4485 ( .A(n5391), .Y(n3108) );
INVX2TS U4486 ( .A(n4251), .Y(n4555) );
OAI22X1TS U4487 ( .A0(n4536), .A1(n4537), .B0(n4954), .B1(n4970), .Y(n4539)
);
INVX2TS U4488 ( .A(n5366), .Y(n4532) );
INVX2TS U4489 ( .A(n5365), .Y(n4533) );
NAND2X1TS U4490 ( .A(n2303), .B(n5208), .Y(n3036) );
INVX2TS U4491 ( .A(n5207), .Y(n3038) );
NAND2X4TS U4492 ( .A(n2382), .B(n3772), .Y(n3885) );
NAND2X6TS U4493 ( .A(n3808), .B(n3161), .Y(n2986) );
OAI21X2TS U4494 ( .A0(FPMULT_Op_MY[22]), .A1(FPMULT_Op_MY[10]), .B0(n2576),
.Y(n2577) );
XNOR2X2TS U4495 ( .A(n5198), .B(n4916), .Y(n3948) );
NAND2X1TS U4496 ( .A(n2523), .B(n3907), .Y(n3998) );
XNOR2X2TS U4497 ( .A(n4921), .B(n4916), .Y(n4004) );
INVX4TS U4498 ( .A(n4292), .Y(n2858) );
OR2X4TS U4499 ( .A(n4242), .B(n4483), .Y(n4291) );
INVX2TS U4500 ( .A(n4985), .Y(n4332) );
NAND2X2TS U4501 ( .A(n4300), .B(n3056), .Y(n3055) );
NAND2X1TS U4502 ( .A(n4566), .B(n3058), .Y(n3056) );
NAND2BX1TS U4503 ( .AN(n4566), .B(n3054), .Y(n3053) );
INVX2TS U4504 ( .A(n3058), .Y(n3054) );
CLKXOR2X2TS U4505 ( .A(n3790), .B(n2430), .Y(n3792) );
NOR2X2TS U4506 ( .A(n7733), .B(DP_OP_496J211_122_3540_n1192), .Y(n2967) );
NOR2X2TS U4507 ( .A(DP_OP_496J211_122_3540_n1192), .B(
DP_OP_496J211_122_3540_n1199), .Y(n2994) );
NOR2X4TS U4508 ( .A(n2953), .B(n8343), .Y(n2954) );
OR2X4TS U4509 ( .A(n8519), .B(DP_OP_496J211_122_3540_n1498), .Y(n3870) );
NAND2X1TS U4510 ( .A(n4397), .B(n3167), .Y(n3068) );
OR2X2TS U4511 ( .A(n3806), .B(n6898), .Y(n3904) );
NAND2X1TS U4512 ( .A(n3873), .B(n2307), .Y(n3874) );
INVX2TS U4513 ( .A(n3875), .Y(n2535) );
NAND2X2TS U4514 ( .A(n3876), .B(n3877), .Y(n2534) );
OAI22X1TS U4515 ( .A0(n5031), .A1(n4970), .B0(n5071), .B1(n4537), .Y(n4961)
);
NOR2X2TS U4516 ( .A(n5071), .B(n4970), .Y(n5027) );
NAND2X4TS U4517 ( .A(n3177), .B(n3178), .Y(n3279) );
XOR2X1TS U4518 ( .A(n3764), .B(n3758), .Y(n3759) );
BUFX3TS U4519 ( .A(n5208), .Y(n2593) );
INVX2TS U4520 ( .A(n4921), .Y(n5207) );
XNOR2X2TS U4521 ( .A(n5252), .B(n5345), .Y(n5221) );
INVX2TS U4522 ( .A(n2866), .Y(n2862) );
INVX2TS U4523 ( .A(n2867), .Y(n2864) );
INVX2TS U4524 ( .A(n5276), .Y(n2698) );
INVX2TS U4525 ( .A(n4018), .Y(n4038) );
INVX2TS U4526 ( .A(n2849), .Y(n2675) );
INVX4TS U4527 ( .A(n4180), .Y(n2603) );
INVX2TS U4528 ( .A(n2314), .Y(n2378) );
ADDFX2TS U4529 ( .A(n4473), .B(n4203), .CI(n4202), .CO(n4232), .S(n4208) );
ADDFHX2TS U4530 ( .A(n4433), .B(n4432), .CI(n4431), .CO(n4479), .S(n4428) );
INVX2TS U4531 ( .A(n4350), .Y(n4382) );
NOR2X6TS U4532 ( .A(DP_OP_498J211_124_1725_n635), .B(n2953), .Y(n2812) );
NAND2X2TS U4533 ( .A(n8519), .B(n7694), .Y(n2813) );
ADDFHX2TS U4534 ( .A(n4246), .B(n4245), .CI(n4244), .CO(n4252), .S(n4247) );
NOR2X1TS U4535 ( .A(DP_OP_498J211_124_1725_n635), .B(n4242), .Y(n4246) );
ADDFHX2TS U4536 ( .A(n4241), .B(n4240), .CI(n4239), .CO(n4254), .S(n4248) );
NOR2X2TS U4537 ( .A(n4160), .B(n4243), .Y(n4240) );
NOR2X2TS U4538 ( .A(n2245), .B(n7698), .Y(n4241) );
NOR2X2TS U4539 ( .A(n3173), .B(DP_OP_498J211_124_1725_n635), .Y(n2785) );
AND2X2TS U4540 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J211_122_3540_n1514), .Y(
n3829) );
INVX2TS U4541 ( .A(n3748), .Y(n3830) );
NAND2X2TS U4542 ( .A(n2986), .B(n3007), .Y(n2949) );
INVX2TS U4543 ( .A(n3110), .Y(n4625) );
OR2X2TS U4544 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J211_122_3540_n1513), .Y(
n3828) );
XNOR2X2TS U4545 ( .A(n3951), .B(n4936), .Y(n3994) );
OAI22X2TS U4546 ( .A0(n2433), .A1(n3571), .B0(n3521), .B1(n3606), .Y(n3536)
);
AND2X2TS U4547 ( .A(n3408), .B(DP_OP_497J211_123_1725_n324), .Y(n3411) );
INVX2TS U4548 ( .A(n2916), .Y(n2913) );
XNOR2X2TS U4549 ( .A(n3931), .B(n4936), .Y(n3992) );
INVX2TS U4550 ( .A(n4921), .Y(n2278) );
NAND2BX1TS U4551 ( .AN(n4920), .B(n4616), .Y(n2705) );
XNOR2X2TS U4552 ( .A(n5570), .B(n4921), .Y(n5165) );
INVX2TS U4553 ( .A(n5380), .Y(n4128) );
ADDFHX2TS U4554 ( .A(n4126), .B(n4125), .CI(n4124), .CO(n4910), .S(n4087) );
INVX2TS U4555 ( .A(n5381), .Y(n4124) );
INVX2TS U4556 ( .A(n5548), .Y(n4924) );
ADDFX2TS U4557 ( .A(n5109), .B(n5108), .CI(n5107), .CO(n5110), .S(n5078) );
NOR2XLTS U4558 ( .A(n5071), .B(n5070), .Y(n5109) );
NAND2X2TS U4559 ( .A(FPMULT_Op_MY[9]), .B(DP_OP_498J211_124_1725_n797), .Y(
n2866) );
INVX8TS U4560 ( .A(FPMULT_Op_MX[11]), .Y(n4972) );
INVX6TS U4561 ( .A(DP_OP_496J211_122_3540_n1478), .Y(n4973) );
NOR2X1TS U4562 ( .A(n4661), .B(n4857), .Y(n4664) );
NAND2X1TS U4563 ( .A(n4667), .B(n4666), .Y(n4668) );
AOI21X2TS U4564 ( .A0(n4856), .A1(n4855), .B0(n4854), .Y(n4861) );
NAND2X1TS U4565 ( .A(n4859), .B(n4858), .Y(n4860) );
NAND2X1TS U4566 ( .A(n4749), .B(n4748), .Y(n4750) );
AO21X1TS U4567 ( .A0(n2302), .A1(n4699), .B0(n4030), .Y(n3156) );
ADDFHX2TS U4568 ( .A(n4358), .B(n4357), .CI(n4356), .CO(n4378), .S(n4303) );
NAND2X1TS U4569 ( .A(n4579), .B(n4578), .Y(n4764) );
OR2X1TS U4570 ( .A(n4578), .B(n4579), .Y(n4765) );
AOI2BB1X2TS U4571 ( .A0N(n3840), .A1N(n2709), .B0(n3848), .Y(n2708) );
NAND2X4TS U4572 ( .A(n3871), .B(n3873), .Y(n2960) );
XNOR2X2TS U4573 ( .A(n4938), .B(n4006), .Y(n3932) );
NAND2BX1TS U4574 ( .AN(n4027), .B(n4940), .Y(n3934) );
INVX2TS U4575 ( .A(n5419), .Y(n5420) );
AO21X1TS U4576 ( .A0(n4627), .A1(n4626), .B0(n2271), .Y(n4629) );
NOR2X4TS U4577 ( .A(DP_OP_497J211_123_1725_n324), .B(
DP_OP_497J211_123_1725_n631), .Y(n2915) );
NOR2X1TS U4578 ( .A(n3994), .B(n3993), .Y(n3065) );
NAND2X1TS U4579 ( .A(n3993), .B(n3750), .Y(n4003) );
INVX2TS U4580 ( .A(n5103), .Y(n5016) );
INVX2TS U4581 ( .A(n5097), .Y(n5065) );
AND2X2TS U4582 ( .A(n4983), .B(n5015), .Y(n3159) );
NAND3X4TS U4583 ( .A(n2228), .B(n5066), .C(n5065), .Y(n2827) );
NAND2X4TS U4584 ( .A(n5103), .B(n5065), .Y(n2826) );
NAND2X1TS U4585 ( .A(n4586), .B(n4585), .Y(n4830) );
ADDFHX2TS U4586 ( .A(n3594), .B(n3593), .CI(n3592), .CO(n3635), .S(n3618) );
ADDFHX2TS U4587 ( .A(n3649), .B(n3648), .CI(n3647), .CO(n3661), .S(n3633) );
NOR2X4TS U4588 ( .A(n3651), .B(n3650), .Y(n3692) );
NOR2X2TS U4589 ( .A(n2326), .B(DP_OP_497J211_123_1725_n324), .Y(n2922) );
NOR2X4TS U4590 ( .A(n2870), .B(n3479), .Y(n2935) );
INVX2TS U4591 ( .A(n2935), .Y(n2933) );
INVX2TS U4592 ( .A(n5234), .Y(n3118) );
INVX2TS U4593 ( .A(n4914), .Y(n5190) );
ADDFHX2TS U4594 ( .A(n5230), .B(n5229), .CI(n5228), .CO(n5239), .S(n5232) );
CLKXOR2X2TS U4595 ( .A(n4632), .B(n5418), .Y(n5415) );
INVX2TS U4596 ( .A(n2731), .Y(n4656) );
INVX2TS U4597 ( .A(n2695), .Y(n4646) );
NAND2X1TS U4598 ( .A(n5367), .B(n5386), .Y(n5368) );
NAND2X1TS U4599 ( .A(n2302), .B(n4698), .Y(n4700) );
INVX2TS U4600 ( .A(n4686), .Y(n4688) );
NAND2X1TS U4601 ( .A(n4695), .B(n4694), .Y(n4696) );
NAND2X1TS U4602 ( .A(n5466), .B(n5465), .Y(n5494) );
CLKXOR2X2TS U4603 ( .A(n5510), .B(n5121), .Y(n5122) );
NAND2X1TS U4604 ( .A(n5120), .B(n5387), .Y(n5121) );
NOR2X1TS U4605 ( .A(n4984), .B(n4985), .Y(n5047) );
NAND2X1TS U4606 ( .A(n4985), .B(n4984), .Y(n5046) );
AOI21X1TS U4607 ( .A0(n3182), .A1(n4989), .B0(n4988), .Y(n5048) );
INVX2TS U4608 ( .A(n5136), .Y(n4675) );
NAND2X1TS U4609 ( .A(n3142), .B(n4638), .Y(n4639) );
NAND2X2TS U4610 ( .A(n4264), .B(n4263), .Y(n2903) );
INVX2TS U4611 ( .A(n4236), .Y(n3014) );
INVX2TS U4612 ( .A(n4237), .Y(n3015) );
NAND2X2TS U4613 ( .A(DP_OP_498J211_124_1725_n802), .B(n7694), .Y(n2850) );
ADDFHX2TS U4614 ( .A(n4156), .B(DP_OP_498J211_124_1725_n631), .CI(n4155),
.CO(n4159), .S(n4168) );
NOR2X2TS U4615 ( .A(DP_OP_498J211_124_1725_n636), .B(n4165), .Y(n4156) );
NOR2X2TS U4616 ( .A(n4160), .B(n7698), .Y(n4155) );
NAND2X4TS U4617 ( .A(n2660), .B(n4361), .Y(n4377) );
OR2X1TS U4618 ( .A(n4519), .B(n4518), .Y(n3168) );
OR2X1TS U4619 ( .A(n4473), .B(n4472), .Y(n4474) );
INVX2TS U4620 ( .A(n4803), .Y(n4805) );
OR2X4TS U4621 ( .A(n7698), .B(n4185), .Y(n4223) );
INVX2TS U4622 ( .A(n5010), .Y(n4949) );
XOR2X1TS U4623 ( .A(n4775), .B(n4774), .Y(n4797) );
NOR2X1TS U4624 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n3836) );
NAND2BX1TS U4625 ( .AN(n8486), .B(n7454), .Y(n3835) );
OAI21X2TS U4626 ( .A0(n6899), .A1(n7454), .B0(n6900), .Y(n2699) );
INVX2TS U4627 ( .A(n4936), .Y(n5177) );
XOR2X2TS U4628 ( .A(n2285), .B(n5212), .Y(n4941) );
BUFX6TS U4629 ( .A(n3866), .Y(n4933) );
NAND2X4TS U4630 ( .A(n3866), .B(n3865), .Y(n4934) );
NAND2X1TS U4631 ( .A(n3399), .B(n2556), .Y(n2553) );
INVX2TS U4632 ( .A(n3450), .Y(n2885) );
AOI2BB2X1TS U4633 ( .B0(n2882), .B1(n7708), .A0N(DP_OP_497J211_123_1725_n312), .A1N(n3664), .Y(n3640) );
BUFX4TS U4634 ( .A(n2870), .Y(n2643) );
NAND2X1TS U4635 ( .A(n5276), .B(n5275), .Y(n5296) );
NAND2BX1TS U4636 ( .AN(n4037), .B(n4947), .Y(n5272) );
NAND2X1TS U4637 ( .A(n4018), .B(n4003), .Y(n5273) );
CLKXOR2X2TS U4638 ( .A(n4818), .B(n2805), .Y(n4821) );
CLKXOR2X2TS U4639 ( .A(n4817), .B(n4828), .Y(n4822) );
XOR2X1TS U4640 ( .A(n5087), .B(n5086), .Y(n2333) );
NAND2BX1TS U4641 ( .AN(DP_OP_497J211_123_1725_n324), .B(
DP_OP_496J211_122_3540_n1461), .Y(n3638) );
NOR2X1TS U4642 ( .A(n3342), .B(n3571), .Y(n3343) );
INVX2TS U4643 ( .A(n3627), .Y(n3345) );
INVX2TS U4644 ( .A(n3514), .Y(n2907) );
ADDFHX2TS U4645 ( .A(n3351), .B(n3350), .CI(n3349), .CO(n3367), .S(n3285) );
INVX4TS U4646 ( .A(n3541), .Y(n3581) );
NOR2X4TS U4647 ( .A(n5329), .B(n5328), .Y(n2894) );
INVX2TS U4648 ( .A(n5327), .Y(n2893) );
AOI2BB2XLTS U4649 ( .B0(n7371), .B1(n5941), .A0N(n5940), .A1N(n7611), .Y(
n5943) );
NAND2X1TS U4650 ( .A(n5084), .B(n5083), .Y(n5112) );
NAND2X1TS U4651 ( .A(n5044), .B(n5043), .Y(n5113) );
NAND2X2TS U4652 ( .A(n4875), .B(n4874), .Y(n4876) );
NAND2X1TS U4653 ( .A(n4184), .B(n4233), .Y(n4187) );
INVX2TS U4654 ( .A(n3771), .Y(n4025) );
INVX4TS U4655 ( .A(n3908), .Y(n4024) );
INVX2TS U4656 ( .A(n2835), .Y(n4470) );
OAI21X1TS U4657 ( .A0(n4311), .A1(n4373), .B0(n4372), .Y(n4374) );
NAND2X1TS U4658 ( .A(n4365), .B(n4370), .Y(n4373) );
NOR2X1TS U4659 ( .A(n4364), .B(n4367), .Y(n4370) );
NOR2X1TS U4660 ( .A(n4783), .B(n4786), .Y(n5130) );
OR2X2TS U4661 ( .A(n4799), .B(n4798), .Y(n5056) );
NOR2X1TS U4662 ( .A(n6224), .B(n6238), .Y(n6199) );
NOR2X1TS U4663 ( .A(n5604), .B(n5605), .Y(n5650) );
NOR2X2TS U4664 ( .A(n5360), .B(n5359), .Y(n5376) );
OAI21X2TS U4665 ( .A0(n5289), .A1(n5288), .B0(n5287), .Y(n5378) );
NAND2X1TS U4666 ( .A(n5360), .B(n5359), .Y(n5374) );
NAND2X1TS U4667 ( .A(n5291), .B(n5290), .Y(n5375) );
ADDFHX2TS U4668 ( .A(n5187), .B(n5186), .CI(n5185), .CO(n5634), .S(n5605) );
AO21X1TS U4669 ( .A0(n4934), .A1(n4933), .B0(n2707), .Y(n5187) );
NAND2X1TS U4670 ( .A(n5584), .B(n5583), .Y(n5592) );
XOR3X1TS U4671 ( .A(n5582), .B(n5581), .C(n5580), .Y(n5583) );
NAND2X1TS U4672 ( .A(n5550), .B(n5599), .Y(n5551) );
INVX2TS U4673 ( .A(n3545), .Y(n3707) );
NAND2X4TS U4674 ( .A(n2680), .B(n2679), .Y(n5157) );
NOR2X1TS U4675 ( .A(n3623), .B(n3622), .Y(n3654) );
AOI21X1TS U4676 ( .A0(n3683), .A1(n3684), .B0(n3629), .Y(n3655) );
NAND2X1TS U4677 ( .A(n3623), .B(n3622), .Y(n3653) );
NAND2X4TS U4678 ( .A(n2639), .B(n3660), .Y(n2688) );
NAND2X2TS U4679 ( .A(n3651), .B(n3650), .Y(n3695) );
INVX2TS U4680 ( .A(n3681), .Y(n2638) );
AND2X2TS U4681 ( .A(n3621), .B(n3631), .Y(n2288) );
OR2X6TS U4682 ( .A(n3464), .B(n3463), .Y(n2284) );
NAND2X4TS U4683 ( .A(n3464), .B(n3463), .Y(n3099) );
NAND2X2TS U4684 ( .A(n2775), .B(n2714), .Y(n2598) );
NAND2X2TS U4685 ( .A(n3378), .B(n3377), .Y(n3468) );
OR2X2TS U4686 ( .A(n3285), .B(n3284), .Y(n3376) );
NAND2X2TS U4687 ( .A(n3098), .B(n3581), .Y(n3274) );
INVX2TS U4688 ( .A(n3522), .Y(n3098) );
INVX2TS U4689 ( .A(n5566), .Y(n2987) );
INVX2TS U4690 ( .A(n5238), .Y(n2693) );
INVX2TS U4691 ( .A(n5328), .Y(n5238) );
NAND2X1TS U4692 ( .A(n5280), .B(n5287), .Y(n5281) );
XOR2X1TS U4693 ( .A(n6341), .B(n7676), .Y(n6342) );
NAND2X1TS U4694 ( .A(n6219), .B(n6199), .Y(n6201) );
INVX2TS U4695 ( .A(n4707), .Y(n4703) );
OAI21X2TS U4696 ( .A0(n4712), .A1(n4709), .B0(n4710), .Y(n4193) );
XNOR2X1TS U4697 ( .A(n4198), .B(n4197), .Y(n4705) );
NAND2X2TS U4698 ( .A(n4706), .B(n4705), .Y(n4707) );
NAND2X4TS U4699 ( .A(n3032), .B(n3031), .Y(n4673) );
INVX2TS U4700 ( .A(n4374), .Y(n3031) );
INVX2TS U4701 ( .A(n4375), .Y(n3032) );
NAND2X2TS U4702 ( .A(n4375), .B(n4374), .Y(n4672) );
INVX2TS U4703 ( .A(n4851), .Y(n4322) );
INVX2TS U4704 ( .A(n6381), .Y(n6404) );
NOR2XLTS U4705 ( .A(n6377), .B(n5820), .Y(n5822) );
NAND2X1TS U4706 ( .A(n5605), .B(n5604), .Y(n5653) );
AO21X1TS U4707 ( .A0(n5210), .A1(n5209), .B0(n5212), .Y(n5265) );
NOR2X1TS U4708 ( .A(n2961), .B(n5212), .Y(n5264) );
NAND2X1TS U4709 ( .A(n5634), .B(n5633), .Y(n5652) );
NAND2X1TS U4710 ( .A(n3657), .B(n3656), .Y(n3702) );
NAND2X1TS U4711 ( .A(n3677), .B(n3676), .Y(n3701) );
INVX2TS U4712 ( .A(n3699), .Y(n2872) );
OR2X1TS U4713 ( .A(n3466), .B(n3465), .Y(n3467) );
NAND2X1TS U4714 ( .A(n5089), .B(n5088), .Y(n5090) );
INVX2TS U4715 ( .A(n5309), .Y(n5310) );
INVX2TS U4716 ( .A(n3286), .Y(n3023) );
NAND2X1TS U4717 ( .A(n4743), .B(n4742), .Y(n4745) );
NAND2X1TS U4718 ( .A(n3204), .B(n4727), .Y(n4729) );
NAND2X4TS U4719 ( .A(n2641), .B(n5727), .Y(n2640) );
CLKBUFX2TS U4720 ( .A(n8076), .Y(n5904) );
NOR2X2TS U4721 ( .A(n6450), .B(n6453), .Y(n6491) );
OR2X1TS U4722 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n7107) );
OAI2BB2XLTS U4723 ( .B0(n7656), .B1(n6013), .A0N(n7392), .A1N(n6012), .Y(
n6028) );
NAND3BXLTS U4724 ( .AN(DP_OP_498J211_124_1725_n788), .B(n8417), .C(n8418),
.Y(n7458) );
INVX4TS U4725 ( .A(n2274), .Y(n2275) );
NAND2X2TS U4726 ( .A(n4702), .B(n4701), .Y(n4704) );
XNOR2X2TS U4727 ( .A(n4763), .B(n4762), .Y(n7208) );
NAND2X1TS U4728 ( .A(n4761), .B(n4760), .Y(n4762) );
NAND2X1TS U4729 ( .A(n4754), .B(n4753), .Y(n4755) );
ADDHXLTS U4730 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n6935), .CO(n6933),
.S(n6936) );
ADDHXLTS U4731 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n6931), .CO(n6929),
.S(n6932) );
ADDHXLTS U4732 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n6927), .CO(n6925),
.S(n6928) );
XOR2X1TS U4733 ( .A(n4713), .B(n4712), .Y(n7205) );
XOR2X1TS U4734 ( .A(n4718), .B(n4717), .Y(n7204) );
XOR2X1TS U4735 ( .A(n4740), .B(n4739), .Y(n7202) );
ADDHXLTS U4736 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n6920), .CO(n6918),
.S(n6922) );
INVX2TS U4737 ( .A(n7134), .Y(n7180) );
INVX2TS U4738 ( .A(n5155), .Y(n3712) );
INVX2TS U4739 ( .A(n2318), .Y(n2499) );
XNOR2X1TS U4740 ( .A(n3260), .B(n3236), .Y(n3237) );
NAND2X1TS U4741 ( .A(n3238), .B(n3237), .Y(n3264) );
NAND2X1TS U4742 ( .A(n4721), .B(n4720), .Y(n4723) );
NAND2X2TS U4743 ( .A(n5128), .B(n3105), .Y(n6214) );
NAND2X2TS U4744 ( .A(n6212), .B(n5151), .Y(n5152) );
NAND2X1TS U4745 ( .A(n5736), .B(n5713), .Y(n5716) );
NAND2X6TS U4746 ( .A(n2740), .B(n3691), .Y(n5284) );
INVX2TS U4747 ( .A(n5283), .Y(n5285) );
NAND2X2TS U4748 ( .A(n3716), .B(n3715), .Y(n2754) );
CLKXOR2X2TS U4749 ( .A(n3736), .B(n2732), .Y(n4863) );
NAND2X4TS U4750 ( .A(n2765), .B(n2766), .Y(n3733) );
INVX2TS U4751 ( .A(n3290), .Y(n2765) );
NAND2X2TS U4752 ( .A(n3024), .B(n3021), .Y(n3724) );
OR2X4TS U4753 ( .A(n3024), .B(n3021), .Y(n3725) );
NAND2X4TS U4754 ( .A(n3010), .B(n5690), .Y(n3009) );
OAI21X2TS U4755 ( .A0(n6092), .A1(n6091), .B0(n6090), .Y(n6162) );
OAI21X2TS U4756 ( .A0(n6595), .A1(n6589), .B0(n6590), .Y(n5868) );
INVX2TS U4757 ( .A(n6589), .Y(n6591) );
CLKAND2X2TS U4758 ( .A(n7873), .B(FPADDSUB_DMP_SFG[12]), .Y(n5840) );
INVX2TS U4759 ( .A(n5739), .Y(n5742) );
CLKAND2X2TS U4760 ( .A(n7868), .B(n2473), .Y(n6087) );
AO21XLTS U4761 ( .A0(n6255), .A1(n6290), .B0(n6292), .Y(n6258) );
INVX2TS U4762 ( .A(n8838), .Y(n7642) );
BUFX3TS U4763 ( .A(n7939), .Y(n7663) );
INVX2TS U4764 ( .A(n7088), .Y(n7600) );
NOR2X1TS U4765 ( .A(n4185), .B(DP_OP_498J211_124_1725_n645), .Y(n7210) );
OR2X1TS U4766 ( .A(n4734), .B(n4733), .Y(n4735) );
NAND2X2TS U4767 ( .A(n5541), .B(n5540), .Y(n5751) );
BUFX3TS U4768 ( .A(FPMULT_Op_MY[9]), .Y(n6899) );
NAND4BXLTS U4769 ( .AN(DP_OP_496J211_122_3540_n1498), .B(n8337), .C(n8338),
.D(n8339), .Y(n7462) );
NOR2XLTS U4770 ( .A(FPMULT_Op_MX[18]), .B(n2772), .Y(n7464) );
NAND3XLTS U4771 ( .A(n8343), .B(n8344), .C(n2320), .Y(n2772) );
NAND4BXLTS U4772 ( .AN(n7454), .B(n8463), .C(n8464), .D(n8465), .Y(n7455) );
BUFX3TS U4773 ( .A(n6759), .Y(n6774) );
BUFX3TS U4774 ( .A(n7408), .Y(n6754) );
MX2X1TS U4775 ( .A(Data_1[10]), .B(n2274), .S0(n6901), .Y(n1669) );
MX2X1TS U4776 ( .A(n7207), .B(FPMULT_P_Sgf[7]), .S0(n8524), .Y(n1560) );
MX2X1TS U4777 ( .A(n7208), .B(FPMULT_P_Sgf[8]), .S0(n8525), .Y(n1561) );
MX2X1TS U4778 ( .A(n7206), .B(FPMULT_P_Sgf[6]), .S0(n7253), .Y(n1559) );
MX2X1TS U4779 ( .A(n7209), .B(FPMULT_P_Sgf[9]), .S0(n7216), .Y(n1562) );
NAND4XLTS U4780 ( .A(n7097), .B(n7096), .C(n7095), .D(n7094), .Y(n7101) );
MX2X1TS U4781 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n6977), .Y(n1653)
);
MX2X1TS U4782 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n6977), .Y(n1652)
);
MX2X1TS U4783 ( .A(n6938), .B(FPMULT_Add_result[7]), .S0(n6939), .Y(n1617)
);
MX2X1TS U4784 ( .A(n6936), .B(FPMULT_Add_result[8]), .S0(n6921), .Y(n1616)
);
MX2X1TS U4785 ( .A(n6934), .B(FPMULT_Add_result[9]), .S0(n6939), .Y(n1615)
);
MX2X1TS U4786 ( .A(n6932), .B(FPMULT_Add_result[10]), .S0(n6939), .Y(n1614)
);
MX2X1TS U4787 ( .A(n6930), .B(FPMULT_Add_result[11]), .S0(n6921), .Y(n1613)
);
MX2X1TS U4788 ( .A(n6928), .B(FPMULT_Add_result[12]), .S0(n6939), .Y(n1612)
);
MX2X1TS U4789 ( .A(n6926), .B(FPMULT_Add_result[13]), .S0(n6939), .Y(n1611)
);
MX2X1TS U4790 ( .A(n6924), .B(FPMULT_Add_result[14]), .S0(n6921), .Y(n1610)
);
MX2X1TS U4791 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n6977), .Y(n1682)
);
MX2X1TS U4792 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n6977), .Y(n1685)
);
OR2X1TS U4793 ( .A(n7281), .B(n6719), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
MX2X1TS U4794 ( .A(n7205), .B(FPMULT_P_Sgf[5]), .S0(n6955), .Y(n1558) );
MX2X1TS U4795 ( .A(FPMULT_Adder_M_result_A_adder[4]), .B(
FPMULT_Add_result[4]), .S0(n6939), .Y(n1620) );
MX2X1TS U4796 ( .A(n6940), .B(FPMULT_Add_result[6]), .S0(n6939), .Y(n1618)
);
MX2X1TS U4797 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n6977), .Y(n1657)
);
MX2X1TS U4798 ( .A(n7203), .B(FPMULT_P_Sgf[3]), .S0(n8524), .Y(n1556) );
CLKAND2X2TS U4799 ( .A(n7215), .B(n7221), .Y(n7217) );
MX2X1TS U4800 ( .A(n7204), .B(FPMULT_P_Sgf[4]), .S0(n7216), .Y(n1557) );
XNOR2X1TS U4801 ( .A(n2670), .B(n7252), .Y(n7254) );
MX2X1TS U4802 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n6990), .Y(n1256) );
MX2X1TS U4803 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6977), .Y(n1654)
);
MX2X1TS U4804 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n6977), .Y(n1684)
);
MX2X1TS U4805 ( .A(n7249), .B(FPMULT_P_Sgf[17]), .S0(n8525), .Y(n1570) );
MX2X1TS U4806 ( .A(n7202), .B(FPMULT_P_Sgf[2]), .S0(n7253), .Y(n1555) );
NAND2X1TS U4807 ( .A(n6250), .B(n6249), .Y(n6251) );
MX2X1TS U4808 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n7452), .Y(n1651)
);
MX2X1TS U4809 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n7517), .Y(n1354) );
MX2X1TS U4810 ( .A(n6922), .B(FPMULT_Add_result[15]), .S0(n6939), .Y(n1609)
);
MX2X1TS U4811 ( .A(FPMULT_Adder_M_result_A_adder[5]), .B(
FPMULT_Add_result[5]), .S0(n6943), .Y(n1619) );
MX2X1TS U4812 ( .A(FPMULT_Adder_M_result_A_adder[3]), .B(
FPMULT_Add_result[3]), .S0(n6943), .Y(n1621) );
MX2X1TS U4813 ( .A(n6942), .B(FPMULT_Add_result[2]), .S0(n6943), .Y(n1622)
);
MX2X1TS U4814 ( .A(n6944), .B(FPMULT_Add_result[1]), .S0(n6943), .Y(n1623)
);
XOR2XLTS U4815 ( .A(n7190), .B(n7189), .Y(n7200) );
MX2X1TS U4816 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n6962), .Y(n1686)
);
OAI21XLTS U4817 ( .A0(n7434), .A1(n2344), .B0(n6832), .Y(n2080) );
MX2X1TS U4818 ( .A(n6987), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n6955),
.Y(n1540) );
XOR2XLTS U4819 ( .A(n6392), .B(n6391), .Y(n6396) );
XOR2XLTS U4820 ( .A(n7157), .B(n7156), .Y(n7162) );
NAND2X1TS U4821 ( .A(n7242), .B(n7240), .Y(n7238) );
XOR2XLTS U4822 ( .A(n6414), .B(n6413), .Y(n6423) );
OAI31X1TS U4823 ( .A0(n7307), .A1(FPSENCOS_cont_var_out[1]), .A2(n7819),
.B0(n6856), .Y(n2138) );
NAND2X1TS U4824 ( .A(n5724), .B(n5714), .Y(add_x_69_n39) );
NAND2X1TS U4825 ( .A(n5667), .B(n3192), .Y(n5668) );
MX2X1TS U4826 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n7452), .Y(n1650)
);
MX2X1TS U4827 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n7508), .Y(n1268) );
INVX2TS U4828 ( .A(n5699), .Y(n5645) );
NAND2X1TS U4829 ( .A(n5694), .B(n5647), .Y(DP_OP_499J211_125_1651_n4) );
CLKBUFX2TS U4830 ( .A(n5696), .Y(n5697) );
NAND2X1TS U4831 ( .A(n5690), .B(n5689), .Y(DP_OP_499J211_125_1651_n8) );
NAND2X1TS U4832 ( .A(n5700), .B(n5699), .Y(DP_OP_499J211_125_1651_n6) );
INVX2TS U4833 ( .A(n5647), .Y(n5642) );
INVX2TS U4834 ( .A(add_x_69_n188), .Y(add_x_69_n186) );
INVX2TS U4835 ( .A(n3516), .Y(n3094) );
NAND2X1TS U4836 ( .A(n3730), .B(n3729), .Y(n3732) );
NAND2X1TS U4837 ( .A(n5737), .B(n5736), .Y(add_x_69_n57) );
INVX2TS U4838 ( .A(add_x_69_n69), .Y(n5715) );
INVX2TS U4839 ( .A(n5303), .Y(n2794) );
NAND2X1TS U4840 ( .A(n5738), .B(n5720), .Y(add_x_69_n94) );
XOR2X2TS U4841 ( .A(n3081), .B(n3499), .Y(n3080) );
INVX2TS U4842 ( .A(n4863), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
NAND2X1TS U4843 ( .A(n3725), .B(n3724), .Y(n3727) );
AO21XLTS U4844 ( .A0(n7304), .A1(n6439), .B0(n6438), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
INVX2TS U4845 ( .A(n7284), .Y(n6601) );
MX2X1TS U4846 ( .A(FPMULT_exp_oper_result[8]), .B(n7105), .S0(n6981), .Y(
n1541) );
OAI2BB1X1TS U4847 ( .A0N(n6599), .A1N(n6137), .B0(n6136), .Y(n1321) );
OAI2BB2XLTS U4848 ( .B0(n6855), .B1(n2294), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n6882), .Y(n8750) );
AND3X1TS U4849 ( .A(n6575), .B(n6574), .C(n6573), .Y(n7826) );
NAND2X1TS U4850 ( .A(n5759), .B(n5758), .Y(n5760) );
MX2X1TS U4851 ( .A(Data_1[9]), .B(n6893), .S0(n7452), .Y(n1668) );
MX2X1TS U4852 ( .A(Data_1[21]), .B(DP_OP_496J211_122_3540_n1502), .S0(n2356),
.Y(n1680) );
MX2X1TS U4853 ( .A(Data_2[21]), .B(n7454), .S0(n6901), .Y(n1648) );
MX2X1TS U4854 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n6962), .Y(n1689)
);
MX2X1TS U4855 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n6962), .Y(n1688)
);
MX2X1TS U4856 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n6962), .Y(n1687)
);
OAI21X2TS U4857 ( .A0(n2357), .A1(n2774), .B0(n2773), .Y(n1673) );
INVX2TS U4858 ( .A(Data_1[14]), .Y(n2774) );
NAND2X1TS U4859 ( .A(n2355), .B(DP_OP_497J211_123_1725_n793), .Y(n2773) );
CLKBUFX3TS U4860 ( .A(n7957), .Y(n2469) );
CLKINVX3TS U4861 ( .A(n2346), .Y(n2369) );
MX2X1TS U4862 ( .A(Data_1[3]), .B(n5706), .S0(n2356), .Y(n1662) );
MX2X1TS U4863 ( .A(Data_2[7]), .B(n8518), .S0(n2355), .Y(n1634) );
MX2X1TS U4864 ( .A(Data_2[0]), .B(DP_OP_498J211_124_1725_n788), .S0(n6901),
.Y(n1627) );
OAI2BB1X1TS U4865 ( .A0N(n6599), .A1N(n6118), .B0(n6117), .Y(n1318) );
OAI2BB1X1TS U4866 ( .A0N(n6599), .A1N(n6127), .B0(n6126), .Y(n1319) );
CLKINVX3TS U4867 ( .A(n2386), .Y(n2419) );
MX2X1TS U4868 ( .A(Data_2[15]), .B(DP_OP_497J211_123_1725_n781), .S0(n6962),
.Y(n1642) );
MX2X1TS U4869 ( .A(Data_2[16]), .B(DP_OP_497J211_123_1725_n782), .S0(n6962),
.Y(n1643) );
MX2X1TS U4870 ( .A(Data_2[2]), .B(DP_OP_498J211_124_1725_n790), .S0(n6901),
.Y(n1629) );
MX2X1TS U4871 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n6977), .Y(n1656)
);
MX2X1TS U4872 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n6977), .Y(n1655)
);
MX2X1TS U4873 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n6977), .Y(n1683)
);
MX2X1TS U4874 ( .A(Data_1[0]), .B(DP_OP_496J211_122_3540_n1506), .S0(n2355),
.Y(n1659) );
MX2X1TS U4875 ( .A(Data_1[6]), .B(DP_OP_496J211_122_3540_n1512), .S0(n2356),
.Y(n1665) );
MX2X1TS U4876 ( .A(n2473), .B(FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n7508), .Y(
n1208) );
MX2X1TS U4877 ( .A(n2487), .B(FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n6989), .Y(
n1212) );
MX2X1TS U4878 ( .A(n2479), .B(FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n7508), .Y(
n1216) );
MX2X1TS U4879 ( .A(n2486), .B(FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n7508), .Y(
n1220) );
MX2X1TS U4880 ( .A(n2485), .B(FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n7508), .Y(
n1224) );
MX2X1TS U4881 ( .A(n2477), .B(FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n7508), .Y(
n1228) );
MX2X1TS U4882 ( .A(n2483), .B(FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n6989), .Y(
n1232) );
MX2X1TS U4883 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n6990), .Y(n1236) );
MX2X1TS U4884 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n6990), .Y(n1240) );
MX2X1TS U4885 ( .A(n2488), .B(FPADDSUB_DMP_SHT2_EWSW[13]), .S0(n7517), .Y(
n1244) );
MX2X1TS U4886 ( .A(n2475), .B(FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n7508), .Y(
n1248) );
MX2X1TS U4887 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n6990), .Y(n1252) );
MX2X1TS U4888 ( .A(n2481), .B(FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n6989), .Y(
n1260) );
MX2X1TS U4889 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n6990), .Y(n1264) );
MX2X1TS U4890 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n6990), .Y(n1274) );
MX2X1TS U4891 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n6990), .Y(n1281) );
MX2X1TS U4892 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n7517), .Y(n1288) );
MX2X1TS U4893 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n7517), .Y(n1295) );
MX2X1TS U4894 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n6990), .Y(n1302) );
MX2X1TS U4895 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n6990), .Y(n1309) );
MX2X1TS U4896 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n6990), .Y(n1325) );
XOR2XLTS U4897 ( .A(n7119), .B(n7118), .Y(n7124) );
AO22XLTS U4898 ( .A0(n2359), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n6581), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1359) );
MX2X1TS U4899 ( .A(n7092), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n8526),
.Y(n1411) );
MX2X1TS U4900 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6988), .Y(n1420) );
MX2X1TS U4901 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n6988), .Y(n1425) );
MX2X1TS U4902 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n6988), .Y(n1430) );
MX2X1TS U4903 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n6988), .Y(n1435) );
AO22XLTS U4904 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[27]), .B0(n3179), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
MX2X1TS U4905 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n6988), .Y(n1440) );
MX2X1TS U4906 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n6988), .Y(n1445) );
MX2X1TS U4907 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n6988), .Y(n1450) );
MX2X1TS U4908 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n6988), .Y(n1455) );
OAI21XLTS U4909 ( .A0(n1419), .A1(n7499), .B0(n7498), .Y(n7500) );
MX2X1TS U4910 ( .A(n7210), .B(FPMULT_P_Sgf[0]), .S0(n6955), .Y(n1553) );
MX2X1TS U4911 ( .A(n7211), .B(FPMULT_P_Sgf[1]), .S0(n7216), .Y(n1554) );
NAND2X1TS U4912 ( .A(n5520), .B(n5519), .Y(n5521) );
NAND2X1TS U4913 ( .A(n5526), .B(n5534), .Y(n5527) );
MX2X1TS U4914 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n2355), .Y(n1633) );
MX2X1TS U4915 ( .A(Data_2[8]), .B(n6900), .S0(n2357), .Y(n1635) );
MX2X1TS U4916 ( .A(Data_2[9]), .B(n6899), .S0(n2355), .Y(n1636) );
MX2X1TS U4917 ( .A(Data_2[20]), .B(n3860), .S0(n6901), .Y(n1647) );
MX2X1TS U4918 ( .A(Data_2[22]), .B(FPMULT_Op_MY[22]), .S0(n6901), .Y(n1649)
);
MX2X1TS U4919 ( .A(Data_1[4]), .B(n4294), .S0(n7452), .Y(n1663) );
MX2X1TS U4920 ( .A(Data_1[11]), .B(n6898), .S0(n7452), .Y(n1670) );
INVX2TS U4921 ( .A(Data_1[16]), .Y(n2938) );
NAND2X1TS U4922 ( .A(n2356), .B(n2936), .Y(n2937) );
MX2X1TS U4923 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n2356), .Y(n1677)
);
MX2X1TS U4924 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n2355), .Y(n1678)
);
MX2X1TS U4925 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n2356), .Y(n1681)
);
AOI32X1TS U4926 ( .A0(n7303), .A1(n7409), .A2(n7319), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n7325), .Y(n6637) );
OAI211XLTS U4927 ( .A0(n6559), .A1(n7911), .B0(n7320), .C0(n6656), .Y(n2122)
);
OAI211XLTS U4928 ( .A0(n7364), .A1(n7910), .B0(n7317), .C0(n6640), .Y(n2126)
);
MX2X1TS U4929 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n7089), .S0(n8643),
.Y(n2146) );
AOI2BB2XLTS U4930 ( .B0(n2196), .B1(n7305), .A0N(n7305), .A1N(n2196), .Y(
n2141) );
NOR2X4TS U4931 ( .A(DP_OP_496J211_122_3540_n1462), .B(FPMULT_Op_MY[6]), .Y(
n2730) );
INVX12TS U4932 ( .A(n2549), .Y(n2623) );
XNOR2X4TS U4933 ( .A(n5406), .B(n3186), .Y(n5712) );
NOR2BX4TS U4934 ( .AN(n8462), .B(n8285), .Y(n3537) );
INVX12TS U4935 ( .A(n8462), .Y(n3538) );
NAND2X6TS U4936 ( .A(n2621), .B(n4469), .Y(n4525) );
NAND2X4TS U4937 ( .A(n2321), .B(n2835), .Y(n2621) );
OAI21X4TS U4938 ( .A0(n2521), .A1(DP_OP_496J211_122_3540_n1113), .B0(
DP_OP_496J211_122_3540_n1114), .Y(n2580) );
INVX6TS U4939 ( .A(n2531), .Y(n2532) );
ADDFHX4TS U4940 ( .A(n3483), .B(n3482), .CI(n3481), .CO(n3495), .S(n3477) );
CLKINVX6TS U4941 ( .A(n3656), .Y(n3406) );
CLKINVX6TS U4942 ( .A(n3708), .Y(n3546) );
OAI2BB2X2TS U4943 ( .B0(n3521), .B1(n7708), .A0N(n3520), .A1N(n7708), .Y(
n3570) );
NAND2X4TS U4944 ( .A(n3183), .B(n4376), .Y(n3033) );
ADDHX4TS U4945 ( .A(n4302), .B(n4301), .CO(n4329), .S(n4566) );
XOR2X4TS U4946 ( .A(n2757), .B(n2276), .Y(n3214) );
ADDFHX2TS U4947 ( .A(n4953), .B(n4952), .CI(n4951), .CO(n5019), .S(n4980) );
NOR2X6TS U4948 ( .A(n2433), .B(n2298), .Y(n2780) );
XOR2X4TS U4949 ( .A(n3044), .B(n8286), .Y(n2285) );
NAND2X4TS U4950 ( .A(n4360), .B(n4359), .Y(n4376) );
NOR2X4TS U4951 ( .A(n2675), .B(n2565), .Y(n2674) );
INVX2TS U4952 ( .A(n2565), .Y(n2673) );
ADDFHX4TS U4953 ( .A(n3392), .B(n3391), .CI(n3390), .CO(n3462), .S(n3388) );
NOR2X4TS U4954 ( .A(n4483), .B(n4355), .Y(n4302) );
NOR2X4TS U4955 ( .A(n4451), .B(n4355), .Y(n3034) );
NAND2X4TS U4956 ( .A(n3028), .B(n3027), .Y(n2808) );
ADDFHX4TS U4957 ( .A(n3540), .B(DP_OP_497J211_123_1725_n668), .CI(n3539),
.CO(n3574), .S(n3542) );
NOR2X4TS U4958 ( .A(n2953), .B(n4160), .Y(n4142) );
XNOR2X4TS U4959 ( .A(n4604), .B(n2430), .Y(n4591) );
INVX4TS U4960 ( .A(n2780), .Y(n2779) );
INVX8TS U4961 ( .A(n5325), .Y(n2507) );
ADDFHX2TS U4962 ( .A(n4603), .B(n2440), .CI(n4602), .CO(n4608), .S(n4596) );
ADDFHX4TS U4963 ( .A(n4929), .B(n4928), .CI(n4927), .CO(n5184), .S(n4943) );
ADDFHX4TS U4964 ( .A(n3903), .B(n3902), .CI(n3901), .CO(n4110), .S(n3968) );
OAI22X2TS U4965 ( .A0(n5173), .A1(n2237), .B0(n4923), .B1(n5338), .Y(n5170)
);
ADDFHX4TS U4966 ( .A(n4880), .B(n4879), .CI(n4878), .CO(n4887), .S(n4889) );
OAI21X4TS U4967 ( .A0(n3250), .A1(n3729), .B0(n3249), .Y(n2735) );
INVX4TS U4968 ( .A(n3916), .Y(n3905) );
XOR2X2TS U4969 ( .A(n2789), .B(n3887), .Y(n2516) );
NOR2X6TS U4970 ( .A(n5757), .B(n5751), .Y(n2801) );
NAND3X6TS U4971 ( .A(n2881), .B(n2879), .C(n2878), .Y(n2882) );
NOR2X4TS U4972 ( .A(n3113), .B(n2646), .Y(n3114) );
AOI21X4TS U4973 ( .A0(n5754), .A1(n5753), .B0(n5752), .Y(n5755) );
ADDFHX4TS U4974 ( .A(n4888), .B(n4887), .CI(n4886), .CO(n4678), .S(n4893) );
XOR2X4TS U4975 ( .A(n5252), .B(n5167), .Y(n3982) );
ADDFHX2TS U4976 ( .A(n5579), .B(n5578), .CI(n5577), .CO(n5580), .S(n5568) );
OAI22X2TS U4977 ( .A0(n3960), .A1(n5208), .B0(n3925), .B1(n2303), .Y(n3917)
);
XOR2X4TS U4978 ( .A(n5419), .B(n2278), .Y(n4922) );
NAND2X4TS U4979 ( .A(n3311), .B(n3419), .Y(n3296) );
ADDFHX2TS U4980 ( .A(n5220), .B(n5219), .CI(n5218), .CO(n5241), .S(n5216) );
AND2X4TS U4981 ( .A(n2587), .B(n3589), .Y(n2327) );
NAND2X6TS U4982 ( .A(n3137), .B(n3311), .Y(n3136) );
OAI22X2TS U4983 ( .A0(n3996), .A1(n3797), .B0(n3799), .B1(n4024), .Y(n3979)
);
XOR2X4TS U4984 ( .A(n2901), .B(n2900), .Y(n5340) );
OAI22X4TS U4985 ( .A0(n3996), .A1(n3799), .B0(n3893), .B1(n4024), .Y(n3891)
);
NOR2X2TS U4986 ( .A(n3175), .B(n2226), .Y(n3454) );
OR2X1TS U4987 ( .A(n3419), .B(n3480), .Y(n2878) );
CLKAND2X2TS U4988 ( .A(n3419), .B(n3480), .Y(n2880) );
INVX4TS U4989 ( .A(n3456), .Y(n2551) );
NAND3X4TS U4990 ( .A(n3102), .B(n5282), .C(n3135), .Y(n2743) );
NAND2X4TS U4991 ( .A(n3097), .B(n3091), .Y(n3090) );
INVX6TS U4992 ( .A(n3097), .Y(n3096) );
INVX4TS U4993 ( .A(n3397), .Y(n2974) );
INVX16TS U4994 ( .A(n4099), .Y(n2430) );
OAI22X2TS U4995 ( .A0(n4933), .A1(n3868), .B0(n4934), .B1(n3932), .Y(n3957)
);
NOR2X4TS U4996 ( .A(n3166), .B(n2684), .Y(n3540) );
ADDFX2TS U4997 ( .A(n5569), .B(n5568), .CI(n5567), .CO(n5584), .S(n5427) );
NAND2X6TS U4998 ( .A(n5643), .B(n5644), .Y(n5699) );
XOR2X2TS U4999 ( .A(n2305), .B(n2616), .Y(n2615) );
OAI21X1TS U5000 ( .A0(n2274), .A1(FPMULT_Op_MX[22]), .B0(n2305), .Y(n3807)
);
INVX8TS U5001 ( .A(n2710), .Y(n2438) );
XNOR2X4TS U5002 ( .A(n4616), .B(n4920), .Y(n2279) );
XNOR2X4TS U5003 ( .A(n2889), .B(n2581), .Y(n2280) );
NOR2X4TS U5004 ( .A(n4615), .B(n4616), .Y(n4691) );
NOR2X8TS U5005 ( .A(n2740), .B(n3691), .Y(n5283) );
XNOR2X4TS U5006 ( .A(n4604), .B(n2439), .Y(n3881) );
XOR2X4TS U5007 ( .A(n2620), .B(n2281), .Y(n5447) );
XOR2X4TS U5008 ( .A(n3133), .B(n5721), .Y(n2281) );
NOR2X2TS U5009 ( .A(n3175), .B(n2304), .Y(n3354) );
NOR2X4TS U5010 ( .A(n3175), .B(n3355), .Y(n2556) );
INVX12TS U5011 ( .A(n2511), .Y(n5198) );
NAND2X4TS U5012 ( .A(n7521), .B(n7520), .Y(n7627) );
OR2X8TS U5013 ( .A(n4133), .B(n4134), .Y(n2283) );
XNOR2X4TS U5014 ( .A(n2831), .B(n5465), .Y(n2286) );
OR2X1TS U5015 ( .A(dataB[30]), .B(dataB[24]), .Y(n2297) );
INVX2TS U5016 ( .A(n2346), .Y(n2348) );
CLKINVX3TS U5017 ( .A(n2346), .Y(n2422) );
XNOR2X4TS U5018 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_497J211_123_1725_n793), .Y(
n2298) );
XOR2X1TS U5019 ( .A(n5007), .B(n5006), .Y(n2300) );
CLKXOR2X2TS U5020 ( .A(n5145), .B(n5144), .Y(n2301) );
NAND2X6TS U5021 ( .A(n2595), .B(n5208), .Y(n2303) );
XNOR2X4TS U5022 ( .A(n3071), .B(n3795), .Y(n2305) );
CLKXOR2X2TS U5023 ( .A(n3764), .B(n3765), .Y(n2306) );
AND2X2TS U5024 ( .A(n3493), .B(n3508), .Y(n2309) );
AND2X2TS U5025 ( .A(n3831), .B(n3744), .Y(n2310) );
AND2X2TS U5026 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n6805), .Y(n2311) );
INVX2TS U5027 ( .A(n5538), .Y(n5485) );
XNOR2X4TS U5028 ( .A(n2497), .B(n3266), .Y(n2313) );
AND2X4TS U5029 ( .A(n3239), .B(n3264), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
NAND2X2TS U5030 ( .A(n8519), .B(DP_OP_496J211_122_3540_n1498), .Y(n2315) );
XNOR2X2TS U5031 ( .A(n6900), .B(n3860), .Y(n3855) );
CLKXOR2X2TS U5032 ( .A(DP_OP_496J211_122_3540_n778), .B(n3145), .Y(n2316) );
AND2X2TS U5033 ( .A(n2241), .B(n2313), .Y(n2317) );
CLKXOR2X4TS U5034 ( .A(n3834), .B(n3833), .Y(n3931) );
NAND2X2TS U5035 ( .A(n3965), .B(n3964), .Y(n5572) );
NAND2X4TS U5036 ( .A(n3770), .B(n3774), .Y(n3771) );
CLKINVX6TS U5037 ( .A(n3771), .Y(n2382) );
INVX2TS U5038 ( .A(n2762), .Y(n2759) );
INVX2TS U5039 ( .A(n5395), .Y(n5553) );
NAND2X2TS U5040 ( .A(n2274), .B(n4294), .Y(n4404) );
AND2X4TS U5041 ( .A(n4188), .B(n4175), .Y(n2322) );
OR2X4TS U5042 ( .A(n5152), .B(n6210), .Y(n2323) );
NAND2X4TS U5043 ( .A(n3389), .B(n3388), .Y(n3500) );
INVX4TS U5044 ( .A(n5464), .Y(n5364) );
NAND2X2TS U5045 ( .A(n3175), .B(n3295), .Y(n3311) );
INVX2TS U5046 ( .A(n2818), .Y(n7250) );
AND2X2TS U5047 ( .A(n5285), .B(n5284), .Y(n2324) );
NAND2X1TS U5048 ( .A(n3274), .B(n3472), .Y(n2325) );
INVX2TS U5049 ( .A(n2552), .Y(n3676) );
AND2X2TS U5050 ( .A(n3097), .B(n3094), .Y(n2329) );
INVX2TS U5051 ( .A(n2919), .Y(n3604) );
AOI21X2TS U5052 ( .A0(n2922), .A1(n3496), .B0(n2920), .Y(n2919) );
CLKBUFX2TS U5053 ( .A(n5719), .Y(n5720) );
INVX2TS U5054 ( .A(n4947), .Y(n4014) );
NAND2X2TS U5055 ( .A(n8417), .B(n3172), .Y(n4940) );
INVX2TS U5056 ( .A(n5466), .Y(n5384) );
CLKBUFX2TS U5057 ( .A(FPMULT_Op_MX[11]), .Y(n6898) );
NOR2X4TS U5058 ( .A(n7811), .B(n5769), .Y(n6544) );
INVX2TS U5059 ( .A(n3064), .Y(n5274) );
NAND2X1TS U5060 ( .A(n2372), .B(n7050), .Y(n2336) );
NOR2X1TS U5061 ( .A(n3310), .B(n2304), .Y(n3515) );
INVX2TS U5062 ( .A(n4699), .Y(n4648) );
NAND2X4TS U5063 ( .A(n2403), .B(n7050), .Y(n2339) );
INVX2TS U5064 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n7050) );
OR2X1TS U5065 ( .A(dataB[26]), .B(dataB[29]), .Y(n2342) );
INVX2TS U5066 ( .A(n5733), .Y(n4790) );
CLKBUFX2TS U5067 ( .A(n2420), .Y(n8596) );
CLKBUFX2TS U5068 ( .A(n8596), .Y(n8599) );
INVX2TS U5069 ( .A(n6254), .Y(n8634) );
CLKBUFX3TS U5070 ( .A(n2347), .Y(n8534) );
NOR2X2TS U5071 ( .A(n2439), .B(n3822), .Y(n3812) );
OAI22X2TS U5072 ( .A0(n3521), .A1(n3571), .B0(n3393), .B1(n3606), .Y(n3444)
);
NAND2X6TS U5073 ( .A(n3001), .B(n2282), .Y(n2926) );
OAI22X4TS U5074 ( .A0(n3996), .A1(n3995), .B0(n3797), .B1(n4024), .Y(n4572)
);
AOI21X4TS U5075 ( .A0(n4766), .A1(n4765), .B0(n4580), .Y(n4806) );
OR2X4TS U5076 ( .A(n2860), .B(n3051), .Y(n3049) );
INVX4TS U5077 ( .A(n4449), .Y(n4506) );
NAND2X4TS U5078 ( .A(n2282), .B(n3001), .Y(n2601) );
NAND2X4TS U5079 ( .A(n2282), .B(n3001), .Y(n2641) );
NAND2X4TS U5080 ( .A(n4685), .B(n4684), .Y(n5729) );
INVX6TS U5081 ( .A(n4685), .Y(n2569) );
OAI22X4TS U5082 ( .A0(n2303), .A1(n4005), .B0(n5208), .B1(n4004), .Y(n4052)
);
INVX2TS U5083 ( .A(n3844), .Y(n3112) );
OAI22X2TS U5084 ( .A0(n2433), .A1(n3612), .B0(n3521), .B1(n2299), .Y(n3565)
);
ADDFHX4TS U5085 ( .A(n4089), .B(n4088), .CI(n4087), .CO(n4908), .S(n4130) );
ADDHX4TS U5086 ( .A(n4097), .B(n4096), .CO(n4928), .S(n4114) );
NAND2X6TS U5087 ( .A(n2438), .B(n4024), .Y(n3996) );
NAND2X4TS U5088 ( .A(n3005), .B(n2944), .Y(n2958) );
NAND2X4TS U5089 ( .A(n4220), .B(n7699), .Y(n4212) );
AOI21X2TS U5090 ( .A0(n2233), .A1(n5013), .B0(n4949), .Y(n4995) );
NAND2X4TS U5091 ( .A(n2612), .B(n4523), .Y(n2611) );
OAI22X2TS U5092 ( .A0(n3639), .A1(n3612), .B0(n2434), .B1(n2299), .Y(n3603)
);
NOR2X4TS U5093 ( .A(n5541), .B(n5540), .Y(n5730) );
INVX2TS U5094 ( .A(n2338), .Y(n2345) );
INVX2TS U5095 ( .A(n8634), .Y(n2346) );
INVX2TS U5096 ( .A(n2346), .Y(n2347) );
OAI22X2TS U5097 ( .A0(n2349), .A1(n3519), .B0(n3664), .B1(n3441), .Y(n3525)
);
OAI22X2TS U5098 ( .A0(n2349), .A1(n2299), .B0(n2435), .B1(n3612), .Y(n3642)
);
OAI2BB2X2TS U5099 ( .B0(n3409), .B1(n7708), .A0N(n3408), .A1N(n7708), .Y(
n3431) );
INVX4TS U5100 ( .A(n3445), .Y(n3409) );
OAI22X2TS U5101 ( .A0(n2351), .A1(n3422), .B0(n3446), .B1(n3342), .Y(n3257)
);
INVX2TS U5102 ( .A(n2352), .Y(n2354) );
INVX2TS U5103 ( .A(n2332), .Y(n2360) );
INVX2TS U5104 ( .A(n7303), .Y(n2361) );
INVX2TS U5105 ( .A(n8596), .Y(n2362) );
INVX2TS U5106 ( .A(n2362), .Y(n2363) );
INVX2TS U5107 ( .A(n2362), .Y(n2364) );
CLKBUFX2TS U5108 ( .A(n2493), .Y(n8600) );
CLKBUFX3TS U5109 ( .A(n2493), .Y(n7995) );
INVX2TS U5110 ( .A(n2383), .Y(n2365) );
INVX2TS U5111 ( .A(n2383), .Y(n2366) );
INVX2TS U5112 ( .A(n2362), .Y(n2367) );
INVX2TS U5113 ( .A(n2362), .Y(n2368) );
INVX2TS U5114 ( .A(n2346), .Y(n2370) );
INVX2TS U5115 ( .A(n2295), .Y(n2371) );
INVX2TS U5116 ( .A(n2335), .Y(n2372) );
INVX2TS U5117 ( .A(n2337), .Y(n2375) );
OAI22X1TS U5118 ( .A0(n4954), .A1(n4407), .B0(n2379), .B1(n4448), .Y(n4358)
);
OAI22X2TS U5119 ( .A0(n4549), .A1(n4407), .B0(n2437), .B1(n4448), .Y(n4285)
);
INVX2TS U5120 ( .A(n8599), .Y(n2383) );
INVX2TS U5121 ( .A(n2383), .Y(n2384) );
INVX2TS U5122 ( .A(n2383), .Y(n2385) );
CLKBUFX3TS U5123 ( .A(n2348), .Y(n8537) );
CLKBUFX3TS U5124 ( .A(n2347), .Y(n8535) );
INVX2TS U5125 ( .A(n6354), .Y(n2386) );
INVX2TS U5126 ( .A(n2386), .Y(n2387) );
INVX2TS U5127 ( .A(n2386), .Y(n2388) );
INVX2TS U5128 ( .A(n2386), .Y(n2389) );
INVX2TS U5129 ( .A(n2346), .Y(n2390) );
CLKBUFX3TS U5130 ( .A(n8537), .Y(n8539) );
INVX2TS U5131 ( .A(n2362), .Y(n2391) );
INVX2TS U5132 ( .A(n2383), .Y(n2392) );
INVX2TS U5133 ( .A(n2362), .Y(n2393) );
INVX2TS U5134 ( .A(n2383), .Y(n2394) );
INVX2TS U5135 ( .A(n2336), .Y(n2395) );
INVX2TS U5136 ( .A(n2336), .Y(n2396) );
INVX2TS U5137 ( .A(n6181), .Y(n2397) );
INVX2TS U5138 ( .A(n6181), .Y(n2398) );
INVX2TS U5139 ( .A(n2346), .Y(n2399) );
INVX2TS U5140 ( .A(n2386), .Y(n2400) );
INVX2TS U5141 ( .A(n6254), .Y(n2401) );
INVX2TS U5142 ( .A(FPADDSUB_left_right_SHT2), .Y(n2402) );
INVX2TS U5143 ( .A(n2402), .Y(n2403) );
INVX2TS U5144 ( .A(n2402), .Y(n2404) );
INVX2TS U5145 ( .A(n3147), .Y(n2405) );
INVX2TS U5146 ( .A(n3147), .Y(n2406) );
INVX2TS U5147 ( .A(n6544), .Y(n2409) );
INVX2TS U5148 ( .A(n2409), .Y(n2410) );
INVX2TS U5149 ( .A(n5768), .Y(n2414) );
INVX2TS U5150 ( .A(n2414), .Y(n2415) );
INVX2TS U5151 ( .A(n2414), .Y(n2416) );
NOR4X1TS U5152 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n5798) );
AOI222X1TS U5153 ( .A0(n6794), .A1(cordic_result[25]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n6789) );
NOR2XLTS U5154 ( .A(n6653), .B(n6652), .Y(n1694) );
INVX2TS U5155 ( .A(n8637), .Y(n2417) );
CLKBUFX2TS U5156 ( .A(n7995), .Y(n8601) );
NOR4X2TS U5157 ( .A(n2350), .B(FPMULT_FS_Module_state_reg[0]), .C(n7817),
.D(n7788), .Y(n7296) );
CLKINVX3TS U5158 ( .A(n6254), .Y(n2418) );
AOI32X1TS U5159 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n7434), .A2(
n7301), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n8636), .Y(n6672)
);
AOI32X1TS U5160 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n7434), .A2(
n8526), .B0(n2491), .B1(n8636), .Y(n6701) );
AOI32X1TS U5161 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n7434), .A2(
n8526), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n8636), .Y(n6681)
);
NAND2X4TS U5162 ( .A(n6581), .B(n7658), .Y(n7434) );
CLKMX2X2TS U5163 ( .A(n6218), .B(FPMULT_P_Sgf[19]), .S0(n7216), .Y(n1572) );
NOR3BX2TS U5164 ( .AN(n6059), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n6674) );
AOI21X2TS U5165 ( .A0(n2373), .A1(n1813), .B0(n7005), .Y(n7077) );
AOI21X2TS U5166 ( .A0(n1807), .A1(n2373), .B0(n6998), .Y(n7058) );
OAI21X1TS U5167 ( .A0(n7043), .A1(n7012), .B0(n7011), .Y(n6998) );
CLKBUFX3TS U5168 ( .A(n8576), .Y(n8562) );
OAI211X4TS U5169 ( .A0(n8026), .A1(n8058), .B0(n6175), .C0(n6174), .Y(n1793)
);
OAI211X4TS U5170 ( .A0(n8025), .A1(n8058), .B0(n6848), .C0(n6847), .Y(n1795)
);
NAND2X2TS U5171 ( .A(n6618), .B(n7817), .Y(n7477) );
NAND2X4TS U5172 ( .A(n2340), .B(n7084), .Y(n7029) );
CLKBUFX3TS U5173 ( .A(n8593), .Y(n8576) );
AND2X4TS U5174 ( .A(n7052), .B(n2403), .Y(n7082) );
CLKBUFX3TS U5175 ( .A(n8593), .Y(n8578) );
OAI21XLTS U5176 ( .A0(n2359), .A1(n7806), .B0(n6855), .Y(n1352) );
BUFX3TS U5177 ( .A(n8534), .Y(n8547) );
BUFX3TS U5178 ( .A(n8535), .Y(n8548) );
INVX2TS U5179 ( .A(n8637), .Y(n2420) );
CLKBUFX2TS U5180 ( .A(n7993), .Y(n8603) );
INVX2TS U5181 ( .A(n2386), .Y(n2421) );
OAI211XLTS U5182 ( .A0(n8612), .A1(n7850), .B0(n6816), .C0(n6810), .Y(n1470)
);
OAI211XLTS U5183 ( .A0(n8612), .A1(n7851), .B0(n6816), .C0(n6812), .Y(n1471)
);
OAI211XLTS U5184 ( .A0(n8612), .A1(n7852), .B0(n6816), .C0(n6815), .Y(n1472)
);
BUFX3TS U5185 ( .A(n2348), .Y(n6354) );
CLKBUFX3TS U5186 ( .A(n7955), .Y(n7959) );
CLKBUFX3TS U5187 ( .A(n7961), .Y(n7955) );
CLKBUFX3TS U5188 ( .A(n6352), .Y(n7970) );
CLKBUFX3TS U5189 ( .A(n8534), .Y(n6352) );
AOI222X1TS U5190 ( .A0(n6802), .A1(cordic_result[23]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n6781) );
CLKBUFX3TS U5191 ( .A(n7991), .Y(n7776) );
AOI222X1TS U5192 ( .A0(n6794), .A1(cordic_result[30]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n6729) );
AOI222X1TS U5193 ( .A0(n6794), .A1(cordic_result[29]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n6795) );
AOI222X1TS U5194 ( .A0(n6794), .A1(cordic_result[27]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n6792) );
AOI222X1TS U5195 ( .A0(n6794), .A1(cordic_result[26]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n6790) );
NAND2X4TS U5196 ( .A(n7216), .B(n7477), .Y(n6981) );
NOR4X1TS U5197 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n7457) );
NOR2X1TS U5198 ( .A(n7865), .B(n2488), .Y(n5843) );
NOR2X1TS U5199 ( .A(n7864), .B(n2487), .Y(n6073) );
OR2X1TS U5200 ( .A(n7873), .B(FPADDSUB_DMP_SFG[12]), .Y(n5841) );
CLKINVX3TS U5201 ( .A(n2386), .Y(n2423) );
INVX2TS U5202 ( .A(rst), .Y(n2424) );
INVX2TS U5203 ( .A(rst), .Y(n2425) );
INVX2TS U5204 ( .A(rst), .Y(n2426) );
NOR2X2TS U5205 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n7795),
.Y(n6587) );
XNOR2X2TS U5206 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3844) );
NAND2X1TS U5207 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3847) );
INVX2TS U5208 ( .A(n6985), .Y(n2427) );
BUFX6TS U5209 ( .A(n6945), .Y(n6984) );
OAI22X2TS U5210 ( .A0(n3521), .A1(n2298), .B0(n3318), .B1(n3393), .Y(n2544)
);
INVX2TS U5211 ( .A(n2430), .Y(n4599) );
XNOR2X2TS U5212 ( .A(n3806), .B(n2430), .Y(n3882) );
INVX2TS U5213 ( .A(n2430), .Y(n2616) );
INVX2TS U5214 ( .A(n6204), .Y(n2431) );
INVX2TS U5215 ( .A(n6203), .Y(n2432) );
INVX6TS U5216 ( .A(n3610), .Y(n2434) );
OAI22X1TS U5217 ( .A0(n3639), .A1(n3318), .B0(n2435), .B1(n2298), .Y(n3569)
);
NOR2X1TS U5218 ( .A(n2435), .B(n3446), .Y(n3526) );
NAND2BX1TS U5219 ( .AN(n4108), .B(n4921), .Y(n2997) );
NOR2BX1TS U5220 ( .AN(n4108), .B(n5208), .Y(n4013) );
XNOR2X1TS U5221 ( .A(n4921), .B(n4108), .Y(n4005) );
INVX2TS U5222 ( .A(n4108), .Y(n2523) );
INVX2TS U5223 ( .A(n2710), .Y(n2439) );
INVX2TS U5224 ( .A(n2440), .Y(n4612) );
OAI21X2TS U5225 ( .A0(n3810), .A1(n3823), .B0(n2440), .Y(n3753) );
XNOR2X2TS U5226 ( .A(n2439), .B(n3895), .Y(n3995) );
XNOR2X2TS U5227 ( .A(n3790), .B(n2438), .Y(n3791) );
CLKINVX12TS U5228 ( .A(n4605), .Y(n2441) );
OR2X1TS U5229 ( .A(n2442), .B(n3965), .Y(n3962) );
XNOR2X1TS U5230 ( .A(n2442), .B(n4604), .Y(n4614) );
XNOR2X2TS U5231 ( .A(n2442), .B(n2305), .Y(n4098) );
XNOR2X1TS U5232 ( .A(n2441), .B(n3895), .Y(n3900) );
XNOR2X2TS U5233 ( .A(n2442), .B(n3110), .Y(n4606) );
CLKBUFX2TS U5234 ( .A(n6178), .Y(n2443) );
INVX2TS U5235 ( .A(n6542), .Y(n2444) );
INVX2TS U5236 ( .A(n6542), .Y(n2445) );
INVX2TS U5237 ( .A(n6542), .Y(n2446) );
NOR2XLTS U5238 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n6953) );
NOR2XLTS U5239 ( .A(n7758), .B(n6606), .Y(n6607) );
INVX2TS U5240 ( .A(n2252), .Y(n2447) );
NOR4BX2TS U5241 ( .AN(n6671), .B(n6689), .C(n8645), .D(n6670), .Y(n6684) );
OAI33X4TS U5242 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n7822), .B0(n7789), .B1(
n7802), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6724) );
NOR4X1TS U5243 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n8067) );
NOR4X1TS U5244 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n8066) );
OR2X2TS U5245 ( .A(n4706), .B(n4705), .Y(n4708) );
INVX2TS U5246 ( .A(n2448), .Y(n2449) );
INVX2TS U5247 ( .A(n2450), .Y(n2451) );
INVX2TS U5248 ( .A(n2452), .Y(n2453) );
INVX2TS U5249 ( .A(n2454), .Y(n2455) );
INVX2TS U5250 ( .A(n2456), .Y(n2457) );
INVX2TS U5251 ( .A(n2458), .Y(n2459) );
INVX2TS U5252 ( .A(n2460), .Y(n2461) );
INVX2TS U5253 ( .A(n2462), .Y(n2463) );
NOR4X1TS U5254 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[12]), .C(
FPMULT_P_Sgf[11]), .D(FPMULT_P_Sgf[10]), .Y(n5799) );
NOR2X2TS U5255 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n7421), .Y(n7420) );
XNOR2X1TS U5256 ( .A(n2860), .B(n5446), .Y(n3052) );
NOR2X2TS U5257 ( .A(n7323), .B(n7313), .Y(n7321) );
NOR2X2TS U5258 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_479_B_1_), .Y(
n7323) );
AOI31XLTS U5259 ( .A0(n7266), .A1(n7265), .A2(n7264), .B0(dataB[27]), .Y(
n7277) );
OAI21X2TS U5260 ( .A0(n8009), .A1(n2221), .B0(n8105), .Y(n7511) );
INVX2TS U5261 ( .A(n6570), .Y(n2464) );
NAND2X2TS U5262 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2464), .Y(n7011)
);
NOR2X2TS U5263 ( .A(n7767), .B(n7756), .Y(n6290) );
NAND2X1TS U5264 ( .A(n6955), .B(FPMULT_P_Sgf[23]), .Y(n5516) );
INVX2TS U5265 ( .A(n5540), .Y(n3233) );
NAND2X1TS U5266 ( .A(n7253), .B(FPMULT_P_Sgf[22]), .Y(n5529) );
AOI21X2TS U5267 ( .A0(n7753), .A1(n7754), .B0(n7755), .Y(n6449) );
AOI211X1TS U5268 ( .A0(n7809), .A1(n2361), .B0(n7325), .C0(n7318), .Y(n6659)
);
OAI21X2TS U5269 ( .A0(n8497), .A1(n8496), .B0(n6042), .Y(n1812) );
NAND2X4TS U5270 ( .A(n2808), .B(n5734), .Y(n5741) );
INVX2TS U5271 ( .A(n5734), .Y(n4777) );
XNOR2X2TS U5272 ( .A(n3951), .B(n4006), .Y(n4008) );
INVX2TS U5273 ( .A(n4006), .Y(n2707) );
OAI32X1TS U5274 ( .A0(n7305), .A1(n7302), .A2(n2361), .B0(n7809), .B1(n7305),
.Y(n2142) );
NOR3X4TS U5275 ( .A(n7302), .B(n7809), .C(n2361), .Y(n7305) );
OAI21X2TS U5276 ( .A0(n6632), .A1(n2361), .B0(n7318), .Y(n7313) );
NAND2X2TS U5277 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_479_B_1_), .Y(
n7318) );
INVX2TS U5278 ( .A(n2465), .Y(n2466) );
AOI222X4TS U5279 ( .A0(n6802), .A1(cordic_result[15]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n6780) );
AOI222X4TS U5280 ( .A0(n6802), .A1(cordic_result[18]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n6783) );
AOI222X4TS U5281 ( .A0(n6827), .A1(cordic_result[11]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n6777) );
AOI222X4TS U5282 ( .A0(n6802), .A1(cordic_result[19]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n6785) );
AOI222X4TS U5283 ( .A0(n6802), .A1(cordic_result[17]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n6803) );
AOI222X4TS U5284 ( .A0(n6802), .A1(cordic_result[13]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n6791) );
AOI222X4TS U5285 ( .A0(n6802), .A1(cordic_result[16]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n6798) );
AOI222X4TS U5286 ( .A0(n6802), .A1(cordic_result[14]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n6787) );
AOI222X4TS U5287 ( .A0(n6827), .A1(cordic_result[10]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n6788) );
AOI222X4TS U5288 ( .A0(n6827), .A1(cordic_result[12]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n6799) );
AOI21X2TS U5289 ( .A0(n2373), .A1(FPADDSUB_Data_array_SWR_3__25_), .B0(n7005), .Y(n7081) );
NAND2X1TS U5290 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n7116) );
AOI222X4TS U5291 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n6838), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n6882), .Y(n8736) );
NOR4X2TS U5292 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n5815) );
INVX4TS U5293 ( .A(n2244), .Y(n6977) );
OAI21XLTS U5294 ( .A0(n7369), .A1(n5932), .B0(n7368), .Y(n5933) );
NAND2BX1TS U5295 ( .AN(n3164), .B(n7253), .Y(n5544) );
OAI211XLTS U5296 ( .A0(n8612), .A1(n7859), .B0(n6816), .C0(n6811), .Y(n1475)
);
OAI211XLTS U5297 ( .A0(n8612), .A1(n7858), .B0(n6816), .C0(n6813), .Y(n1469)
);
NOR3X1TS U5298 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n5813) );
INVX2TS U5299 ( .A(n2467), .Y(n2468) );
OAI21X2TS U5300 ( .A0(n8020), .A1(n8059), .B0(n6169), .Y(n1813) );
NOR3X1TS U5301 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n7489), .Y(n7490) );
NOR2X1TS U5302 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6692) );
INVX2TS U5303 ( .A(rst), .Y(n2470) );
CLKBUFX3TS U5304 ( .A(n8635), .Y(n8592) );
CLKBUFX3TS U5305 ( .A(n8635), .Y(n8595) );
CLKBUFX3TS U5306 ( .A(n8635), .Y(n8594) );
CLKBUFX3TS U5307 ( .A(n8635), .Y(n8591) );
CLKBUFX3TS U5308 ( .A(n8635), .Y(n8593) );
BUFX3TS U5309 ( .A(n8118), .Y(n2471) );
CLKBUFX2TS U5310 ( .A(n8118), .Y(n6851) );
AOI222X4TS U5311 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n6838), .C0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n6641), .Y(n8730) );
INVX2TS U5312 ( .A(n2472), .Y(n2473) );
INVX2TS U5313 ( .A(n2474), .Y(n2475) );
INVX2TS U5314 ( .A(n2476), .Y(n2477) );
INVX2TS U5315 ( .A(n2478), .Y(n2479) );
AOI32X1TS U5316 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2334), .A2(n2294),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2334), .Y(n6057) );
INVX2TS U5317 ( .A(n2480), .Y(n2481) );
NAND2X1TS U5318 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5865) );
INVX2TS U5319 ( .A(n2482), .Y(n2483) );
INVX2TS U5320 ( .A(n2484), .Y(n2485) );
CLKBUFX2TS U5321 ( .A(FPADDSUB_DMP_SFG[21]), .Y(n2486) );
INVX2TS U5322 ( .A(n2290), .Y(n2487) );
NAND2X1TS U5323 ( .A(n2487), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6090) );
INVX2TS U5324 ( .A(n2289), .Y(n2488) );
NOR2X1TS U5325 ( .A(n2488), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6589) );
NOR2BX2TS U5326 ( .AN(n6065), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n6675) );
AOI222X4TS U5327 ( .A0(n6581), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n6576), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n6857), .Y(n8727) );
AOI222X4TS U5328 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n2489),
.B1(n6857), .C0(FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n6641), .Y(n8733)
);
INVX2TS U5329 ( .A(n2490), .Y(n2491) );
NAND2BX2TS U5330 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n7012) );
NAND3X1TS U5331 ( .A(n7050), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(n2491),
.Y(n7038) );
INVX2TS U5332 ( .A(n8637), .Y(n2492) );
INVX2TS U5333 ( .A(n8637), .Y(n2493) );
INVX2TS U5334 ( .A(n8637), .Y(n2494) );
INVX4TS U5335 ( .A(n3762), .Y(n3745) );
XOR2X4TS U5336 ( .A(n3265), .B(n3267), .Y(n2497) );
XOR2X4TS U5337 ( .A(n2498), .B(n3268), .Y(n3267) );
XOR2X4TS U5338 ( .A(n3269), .B(n2935), .Y(n2498) );
NAND2X8TS U5339 ( .A(n2502), .B(n2501), .Y(n2509) );
NAND2X8TS U5340 ( .A(n2529), .B(n5685), .Y(n2656) );
NAND2X8TS U5341 ( .A(n2507), .B(n2506), .Y(n2529) );
XNOR2X4TS U5342 ( .A(n3000), .B(n5547), .Y(
FPMULT_Sgf_operation_EVEN1_S_B[18]) );
NOR2X8TS U5343 ( .A(n5447), .B(n5448), .Y(n5673) );
XNOR2X4TS U5344 ( .A(n5323), .B(n5322), .Y(n3133) );
NAND2X8TS U5345 ( .A(n2510), .B(n2508), .Y(n2620) );
NAND2X4TS U5346 ( .A(n2509), .B(n2890), .Y(n2508) );
OAI22X4TS U5347 ( .A0(n5338), .A1(n3961), .B0(n2237), .B1(n4107), .Y(n4115)
);
XNOR2X4TS U5348 ( .A(n5205), .B(n5198), .Y(n4107) );
XNOR2X4TS U5349 ( .A(n2515), .B(n2514), .Y(n5205) );
NAND2X4TS U5350 ( .A(n3821), .B(n3820), .Y(n2514) );
NAND2X2TS U5351 ( .A(n2962), .B(n3817), .Y(n2515) );
XOR2X4TS U5352 ( .A(n3888), .B(n3887), .Y(n2511) );
XOR2X4TS U5353 ( .A(n2517), .B(n2306), .Y(n2512) );
XOR2X4TS U5354 ( .A(n3757), .B(n3756), .Y(n2517) );
XNOR2X4TS U5355 ( .A(n3760), .B(n3755), .Y(n2518) );
NOR2X8TS U5356 ( .A(n2520), .B(n2519), .Y(n3760) );
OAI21X4TS U5357 ( .A0(DP_OP_496J211_122_3540_n1107), .A1(
DP_OP_496J211_122_3540_n1114), .B0(DP_OP_496J211_122_3540_n1108), .Y(
n2519) );
NAND2X8TS U5358 ( .A(n3144), .B(n4255), .Y(n3762) );
AOI21X4TS U5359 ( .A0(n7686), .A1(n5695), .B0(n2834), .Y(
DP_OP_499J211_125_1651_n39) );
AOI21X4TS U5360 ( .A0(n7686), .A1(n5700), .B0(n5645), .Y(
DP_OP_499J211_125_1651_n44) );
NAND2X8TS U5361 ( .A(n5450), .B(n5451), .Y(n7686) );
AND2X8TS U5362 ( .A(n2522), .B(n2529), .Y(n5698) );
XNOR2X4TS U5363 ( .A(n3907), .B(n4916), .Y(n4002) );
XNOR2X4TS U5364 ( .A(n5179), .B(n3907), .Y(n4009) );
XOR2X4TS U5365 ( .A(n5340), .B(n5167), .Y(n3940) );
XOR2X4TS U5366 ( .A(n5419), .B(n5167), .Y(n3939) );
NAND3X8TS U5367 ( .A(n2728), .B(n2729), .C(n3878), .Y(n2727) );
XNOR2X4TS U5368 ( .A(n2526), .B(n2525), .Y(n3070) );
XOR2X4TS U5369 ( .A(n2527), .B(n5081), .Y(n3062) );
XOR2X4TS U5370 ( .A(n2528), .B(n4510), .Y(n4556) );
INVX12TS U5371 ( .A(DP_OP_498J211_124_1725_n790), .Y(n4160) );
NAND2X1TS U5372 ( .A(n2529), .B(n5686), .Y(n5687) );
NAND2X8TS U5373 ( .A(n3039), .B(n3040), .Y(n2530) );
NAND2X2TS U5374 ( .A(n2530), .B(n5610), .Y(n5560) );
NAND2X1TS U5375 ( .A(n2530), .B(n3188), .Y(n5619) );
XOR2X4TS U5376 ( .A(n2530), .B(n5395), .Y(n5161) );
CLKINVX6TS U5377 ( .A(n2636), .Y(n2531) );
INVX6TS U5378 ( .A(n5156), .Y(n2636) );
NAND3X8TS U5379 ( .A(n2533), .B(n2923), .C(n3589), .Y(n2929) );
NAND3X4TS U5380 ( .A(n2327), .B(n2923), .C(n2533), .Y(n2559) );
NAND3X8TS U5381 ( .A(n2623), .B(n2627), .C(n2284), .Y(n2533) );
XOR2X4TS U5382 ( .A(n2537), .B(n2536), .Y(n3880) );
OAI21X4TS U5383 ( .A0(n3760), .A1(DP_OP_496J211_122_3540_n1102), .B0(
DP_OP_496J211_122_3540_n1103), .Y(n2537) );
XOR2X4TS U5384 ( .A(n2540), .B(n2538), .Y(n3883) );
NAND2X4TS U5385 ( .A(n5330), .B(n2235), .Y(n2692) );
INVX2TS U5386 ( .A(n5182), .Y(n5222) );
XNOR2X4TS U5387 ( .A(n2543), .B(n3423), .Y(n3392) );
XOR2X4TS U5388 ( .A(n3657), .B(n2544), .Y(n2543) );
INVX12TS U5389 ( .A(n3520), .Y(n3393) );
XNOR2X4TS U5390 ( .A(n2545), .B(n3674), .Y(n2740) );
XOR2X4TS U5391 ( .A(n2550), .B(n3397), .Y(n3458) );
XOR2X4TS U5392 ( .A(n2552), .B(n2551), .Y(n2550) );
XNOR2X4TS U5393 ( .A(n2887), .B(n3448), .Y(n2552) );
XOR2X4TS U5394 ( .A(n3398), .B(n2555), .Y(n3395) );
XOR2X4TS U5395 ( .A(n3399), .B(n2556), .Y(n2555) );
INVX12TS U5396 ( .A(DP_OP_497J211_123_1725_n705), .Y(n3355) );
NAND2X8TS U5397 ( .A(n2623), .B(n2560), .Y(n2923) );
OAI21X4TS U5398 ( .A0(n3400), .A1(n3401), .B0(n2563), .Y(n2561) );
XOR2X4TS U5399 ( .A(n2562), .B(n3401), .Y(n3394) );
XOR2X4TS U5400 ( .A(n3400), .B(n2563), .Y(n2562) );
XNOR2X4TS U5401 ( .A(n2850), .B(n2564), .Y(n4158) );
XNOR2X4TS U5402 ( .A(n2565), .B(n2849), .Y(n2564) );
NOR2X8TS U5403 ( .A(DP_OP_498J211_124_1725_n645), .B(n2245), .Y(n2565) );
NOR2X8TS U5404 ( .A(n5673), .B(n5672), .Y(n2566) );
NAND2X8TS U5405 ( .A(n2567), .B(n5725), .Y(n2905) );
NAND2X8TS U5406 ( .A(n2569), .B(n3026), .Y(n2750) );
NAND2X8TS U5407 ( .A(n2750), .B(n5728), .Y(n2909) );
NAND2X8TS U5408 ( .A(n2570), .B(n5539), .Y(n5728) );
NAND2X4TS U5409 ( .A(n2632), .B(n3584), .Y(n2574) );
OAI21X4TS U5410 ( .A0(n2632), .A1(n3584), .B0(n3583), .Y(n2575) );
OAI2BB1X4TS U5411 ( .A0N(FPMULT_Op_MY[10]), .A1N(FPMULT_Op_MY[22]), .B0(
n2577), .Y(n3764) );
XOR2X4TS U5412 ( .A(n2576), .B(n2578), .Y(n3763) );
XNOR2X4TS U5413 ( .A(n2580), .B(n2579), .Y(n3786) );
NAND3X8TS U5414 ( .A(n2584), .B(n4904), .C(n2582), .Y(n2889) );
NAND2X8TS U5415 ( .A(n2589), .B(n4653), .Y(n2695) );
XOR2X4TS U5416 ( .A(n2586), .B(n2585), .Y(n3963) );
XOR2X4TS U5417 ( .A(n3889), .B(n2239), .Y(n2585) );
OR2X8TS U5418 ( .A(n3632), .B(n2587), .Y(n2931) );
NOR2X8TS U5419 ( .A(n3620), .B(n3619), .Y(n3632) );
NAND2X8TS U5420 ( .A(n2931), .B(n3631), .Y(n2639) );
INVX12TS U5421 ( .A(FPMULT_Op_MY[6]), .Y(n4355) );
XNOR2X4TS U5422 ( .A(n3816), .B(n3815), .Y(n2594) );
NAND2X4TS U5423 ( .A(n2613), .B(n4521), .Y(n4522) );
NAND2X8TS U5424 ( .A(n2599), .B(n2614), .Y(n4523) );
INVX2TS U5425 ( .A(n3307), .Y(n2798) );
XNOR2X4TS U5426 ( .A(n2600), .B(n3363), .Y(n3384) );
XNOR2X4TS U5427 ( .A(n3623), .B(n3307), .Y(n2600) );
NAND3X8TS U5428 ( .A(n2602), .B(n5727), .C(n2601), .Y(n3028) );
XOR2X4TS U5429 ( .A(n3787), .B(n3172), .Y(n3765) );
NOR2X4TS U5430 ( .A(n4440), .B(n2603), .Y(n4209) );
OAI22X2TS U5431 ( .A0(n4491), .A1(n2603), .B0(n2378), .B1(n4440), .Y(n4229)
);
XOR2X4TS U5432 ( .A(n4471), .B(n4476), .Y(n2605) );
OAI2BB1X4TS U5433 ( .A0N(n4913), .A1N(n4912), .B0(n2606), .Y(n5193) );
OAI21X2TS U5434 ( .A0(n4912), .A1(n4913), .B0(n2607), .Y(n2606) );
XOR2X4TS U5435 ( .A(n2609), .B(n2607), .Y(n4942) );
XOR2X4TS U5436 ( .A(n2703), .B(n2608), .Y(n2607) );
INVX2TS U5437 ( .A(n4919), .Y(n2608) );
XOR2X4TS U5438 ( .A(n4912), .B(n4913), .Y(n2609) );
NAND3X8TS U5439 ( .A(n2611), .B(n4522), .C(n2610), .Y(n5013) );
XNOR2X4TS U5440 ( .A(n4517), .B(n4516), .Y(n2613) );
OAI22X4TS U5441 ( .A0(n2243), .A1(n3882), .B0(n2615), .B1(n4600), .Y(n3903)
);
OAI22X4TS U5442 ( .A0(n2615), .A1(n2243), .B0(n4600), .B1(n2925), .Y(n3898)
);
NAND2X8TS U5443 ( .A(n5209), .B(n3838), .Y(n5210) );
XOR2X4TS U5444 ( .A(n3837), .B(n2618), .Y(n2617) );
NAND2X6TS U5445 ( .A(n3118), .B(n2619), .Y(n2952) );
NAND2X6TS U5446 ( .A(n3183), .B(n4377), .Y(n2622) );
NAND2X8TS U5447 ( .A(n2626), .B(n2625), .Y(n2775) );
OAI21X4TS U5448 ( .A0(n3247), .A1(n2768), .B0(n3246), .Y(n2629) );
OAI21X4TS U5449 ( .A0(n5312), .A1(n5309), .B0(n5313), .Y(n3101) );
NAND2X4TS U5450 ( .A(n2630), .B(n3690), .Y(n5313) );
XOR2X4TS U5451 ( .A(n2631), .B(n3652), .Y(n2630) );
BUFX6TS U5452 ( .A(n2635), .Y(n2632) );
XOR2X4TS U5453 ( .A(n3581), .B(n2636), .Y(n2633) );
OAI2BB1X4TS U5454 ( .A0N(n2532), .A1N(n3581), .B0(n2634), .Y(n3602) );
OAI21X4TS U5455 ( .A0(n3581), .A1(n2532), .B0(n3580), .Y(n2634) );
NAND2X8TS U5456 ( .A(n2909), .B(n5729), .Y(n3001) );
XOR2X4TS U5457 ( .A(n4900), .B(n2642), .Y(n2814) );
XOR2X4TS U5458 ( .A(n2676), .B(n5013), .Y(n4899) );
AND2X2TS U5459 ( .A(n2781), .B(n2382), .Y(n3901) );
OAI22X1TS U5460 ( .A0(n4633), .A1(n4592), .B0(n4601), .B1(n2644), .Y(n4602)
);
NOR2X8TS U5461 ( .A(n2646), .B(n3923), .Y(n3916) );
OAI21X4TS U5462 ( .A0(n2950), .A1(n2646), .B0(n2986), .Y(n2901) );
OAI22X4TS U5463 ( .A0(n4106), .A1(n2303), .B0(n5208), .B1(n4922), .Y(n4913)
);
XOR2X4TS U5464 ( .A(n2647), .B(n3008), .Y(n5419) );
OAI21X4TS U5465 ( .A0(n3905), .A1(n2950), .B0(n2232), .Y(n2647) );
OAI21X4TS U5466 ( .A0(n5193), .A1(n5192), .B0(n5191), .Y(n2648) );
XNOR2X4TS U5467 ( .A(n2649), .B(n5191), .Y(n5195) );
XNOR2X4TS U5468 ( .A(n5193), .B(n5192), .Y(n2649) );
XNOR2X4TS U5469 ( .A(n2652), .B(n2650), .Y(n5541) );
OAI21X4TS U5470 ( .A0(n2983), .A1(n2651), .B0(n5491), .Y(n2650) );
INVX4TS U5471 ( .A(n2985), .Y(n2651) );
OAI21X4TS U5472 ( .A0(n5518), .A1(n6249), .B0(n5519), .Y(n5538) );
BUFX16TS U5473 ( .A(n3294), .Y(n2653) );
XOR2X4TS U5474 ( .A(n3303), .B(n3304), .Y(n2655) );
NAND2X8TS U5475 ( .A(n2656), .B(n5686), .Y(n5696) );
NOR2X8TS U5476 ( .A(n4514), .B(n4515), .Y(n2658) );
OR2X8TS U5477 ( .A(n4362), .B(n4363), .Y(n2660) );
NOR2X8TS U5478 ( .A(n2661), .B(n4307), .Y(n4362) );
AND2X8TS U5479 ( .A(n4308), .B(n4309), .Y(n2661) );
NAND3X8TS U5480 ( .A(n2663), .B(n4291), .C(n2662), .Y(n4293) );
NAND2X4TS U5481 ( .A(n6893), .B(n2227), .Y(n2662) );
NAND2X4TS U5482 ( .A(n5706), .B(n2227), .Y(n2663) );
NAND2BX4TS U5483 ( .AN(n4402), .B(n4293), .Y(n2666) );
AOI2BB2X4TS U5484 ( .B0(n2824), .B1(n2833), .A0N(n5495), .A1N(n5384), .Y(
n2828) );
NAND2X8TS U5485 ( .A(n2841), .B(n5093), .Y(n2824) );
AND2X8TS U5486 ( .A(n2668), .B(n3163), .Y(n5030) );
NAND2BX4TS U5487 ( .AN(n4406), .B(n3134), .Y(n2668) );
NAND2X8TS U5488 ( .A(n2840), .B(n2839), .Y(n3134) );
OAI22X4TS U5489 ( .A0(n2850), .A1(n2674), .B0(n2849), .B1(n2673), .Y(n4137)
);
OAI2BB1X4TS U5490 ( .A0N(n2684), .A1N(n2683), .B0(n3605), .Y(n2682) );
XNOR2X4TS U5491 ( .A(n3763), .B(n3037), .Y(n2686) );
NAND2X8TS U5492 ( .A(n2924), .B(n4657), .Y(n2731) );
XNOR2X4TS U5493 ( .A(n2691), .B(n2690), .Y(n5372) );
NOR2X8TS U5494 ( .A(n5271), .B(n5270), .Y(n5329) );
NAND3X6TS U5495 ( .A(n2604), .B(n5331), .C(n2235), .Y(n2694) );
XOR2X4TS U5496 ( .A(n2697), .B(n4045), .Y(n4042) );
XNOR2X4TS U5497 ( .A(n3854), .B(n3863), .Y(n4006) );
AOI21X4TS U5498 ( .A0(n2701), .A1(n5409), .B0(n2987), .Y(n5431) );
AOI21X2TS U5499 ( .A0(n2701), .A1(n5591), .B0(n5593), .Y(n5586) );
XNOR2X4TS U5500 ( .A(n2701), .B(n5355), .Y(n5434) );
NAND3X8TS U5501 ( .A(n2896), .B(n2895), .C(n2892), .Y(n2701) );
OAI2BB1X4TS U5502 ( .A0N(n2705), .A1N(n4919), .B0(n2704), .Y(n5172) );
XNOR2X4TS U5503 ( .A(n2706), .B(n3844), .Y(n4938) );
OAI21X4TS U5504 ( .A0(n3843), .A1(n3768), .B0(n3842), .Y(n2706) );
INVX2TS U5505 ( .A(n3840), .Y(n3849) );
OA21X4TS U5506 ( .A0(n3852), .A1(n3851), .B0(n2708), .Y(n3073) );
INVX2TS U5507 ( .A(n3850), .Y(n2709) );
XNOR2X4TS U5508 ( .A(DP_OP_496J211_122_3540_n1063), .B(
DP_OP_496J211_122_3540_n1120), .Y(n2710) );
XOR2X4TS U5509 ( .A(n2711), .B(n2521), .Y(n3790) );
OAI21X4TS U5510 ( .A0(n4670), .A1(n4671), .B0(n4672), .Y(n4644) );
AOI21X4TS U5511 ( .A0(n4853), .A1(n4850), .B0(n4322), .Y(n4670) );
XOR2X4TS U5512 ( .A(n2717), .B(n3417), .Y(n3425) );
XOR2X4TS U5513 ( .A(n3416), .B(n3418), .Y(n2717) );
INVX4TS U5514 ( .A(n3312), .Y(n3407) );
XNOR2X4TS U5515 ( .A(n2718), .B(n4256), .Y(n4268) );
OAI21X4TS U5516 ( .A0(n4311), .A1(n2720), .B0(n2719), .Y(n2718) );
NOR2X8TS U5517 ( .A(n4174), .B(n2322), .Y(n4311) );
XNOR2X4TS U5518 ( .A(n4308), .B(n2721), .Y(n4269) );
NAND2X6TS U5519 ( .A(n2723), .B(n2722), .Y(n4309) );
INVX2TS U5520 ( .A(n4225), .Y(n2722) );
INVX4TS U5521 ( .A(n4226), .Y(n2723) );
NAND2BX4TS U5522 ( .AN(n4238), .B(n2903), .Y(n4308) );
NAND2X8TS U5523 ( .A(n2725), .B(n2724), .Y(n2998) );
NOR2X4TS U5524 ( .A(n3307), .B(n3324), .Y(n4719) );
NOR2X4TS U5525 ( .A(n4211), .B(DP_OP_498J211_124_1725_n635), .Y(n4145) );
NAND2BX2TS U5526 ( .AN(n2761), .B(n2759), .Y(n2758) );
XOR2X4TS U5527 ( .A(n2761), .B(n2759), .Y(n2757) );
XNOR2X4TS U5528 ( .A(n2734), .B(n2733), .Y(n5487) );
AOI21X4TS U5529 ( .A0(n3252), .A1(n3251), .B0(n2735), .Y(n3514) );
NOR2X4TS U5530 ( .A(n2643), .B(n2320), .Y(n3219) );
OAI2BB1X4TS U5531 ( .A0N(n4839), .A1N(n4838), .B0(n2737), .Y(n4865) );
XOR2X4TS U5532 ( .A(n2738), .B(n3542), .Y(n3545) );
XOR2X4TS U5533 ( .A(n3544), .B(n2739), .Y(n2738) );
XNOR2X4TS U5534 ( .A(n2741), .B(n3584), .Y(n3578) );
XNOR2X4TS U5535 ( .A(n2635), .B(n3583), .Y(n2741) );
NAND2X8TS U5536 ( .A(n2746), .B(n2744), .Y(n3135) );
NAND3X8TS U5537 ( .A(n2790), .B(n2234), .C(n3741), .Y(n2746) );
NAND2X4TS U5538 ( .A(n2750), .B(n5729), .Y(n3025) );
NAND2X4TS U5539 ( .A(DP_OP_497J211_123_1725_n781), .B(
DP_OP_497J211_123_1725_n792), .Y(n2762) );
INVX4TS U5540 ( .A(n3043), .Y(n2763) );
XOR2X4TS U5541 ( .A(n2764), .B(n3246), .Y(n3397) );
XOR2X4TS U5542 ( .A(n3247), .B(n2768), .Y(n2764) );
XOR2X4TS U5543 ( .A(n2767), .B(n2325), .Y(n2766) );
XNOR2X4TS U5544 ( .A(n2769), .B(n2915), .Y(n2768) );
NOR2X8TS U5545 ( .A(n2870), .B(n3270), .Y(n2917) );
NAND2X6TS U5546 ( .A(n2779), .B(n2778), .Y(n3456) );
XNOR2X4TS U5547 ( .A(n3137), .B(n3296), .Y(n2777) );
NAND2X4TS U5548 ( .A(n4133), .B(n4134), .Y(n4904) );
NOR2X4TS U5549 ( .A(n2782), .B(n2812), .Y(n2787) );
INVX2TS U5550 ( .A(n2811), .Y(n2782) );
OAI2BB1X4TS U5551 ( .A0N(n2785), .A1N(n4316), .B0(n2783), .Y(n4974) );
XNOR2X4TS U5552 ( .A(n2784), .B(n4316), .Y(n4547) );
XNOR2X4TS U5553 ( .A(n2786), .B(n2785), .Y(n2784) );
OAI22X4TS U5554 ( .A0(n2813), .A1(n2787), .B0(n2811), .B1(n2809), .Y(n2786)
);
NAND3X8TS U5555 ( .A(n2836), .B(n4525), .C(n2788), .Y(n2999) );
XNOR2X4TS U5556 ( .A(n3964), .B(n2441), .Y(n3887) );
NOR2X2TS U5557 ( .A(n4331), .B(n4495), .Y(n4214) );
ADDFX2TS U5558 ( .A(n4482), .B(n4481), .CI(n4480), .CO(n4553), .S(n4490) );
NOR2X4TS U5559 ( .A(n4160), .B(DP_OP_498J211_124_1725_n645), .Y(n4163) );
ADDFHX4TS U5560 ( .A(n4283), .B(n4282), .CI(n4281), .CO(n4347), .S(n4287) );
INVX2TS U5561 ( .A(n4205), .Y(n4216) );
INVX2TS U5562 ( .A(n4224), .Y(n4297) );
INVX4TS U5563 ( .A(n2868), .Y(n3302) );
ADDFHX4TS U5564 ( .A(n3341), .B(n3340), .CI(n3339), .CO(n3348), .S(n3333) );
ADDFHX4TS U5565 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3529), .S(n3461) );
NOR2X8TS U5566 ( .A(n5732), .B(n5731), .Y(n5757) );
OAI22X2TS U5567 ( .A0(n5031), .A1(n5032), .B0(n5071), .B1(n4955), .Y(n5037)
);
OAI21X4TS U5568 ( .A0(n3731), .A1(n3728), .B0(n3729), .Y(n3229) );
INVX8TS U5569 ( .A(n4525), .Y(n4476) );
INVX4TS U5570 ( .A(n3742), .Y(n2790) );
NAND3X8TS U5571 ( .A(n3718), .B(n2792), .C(n2791), .Y(n3741) );
XNOR2X4TS U5572 ( .A(n5286), .B(n2324), .Y(n2793) );
XOR2X4TS U5573 ( .A(n2796), .B(n2749), .Y(n3518) );
OAI21X4TS U5574 ( .A0(n3363), .A1(n2798), .B0(n3362), .Y(n2797) );
OA21X4TS U5575 ( .A0(n3184), .A1(n5746), .B0(n5747), .Y(n3124) );
NAND2X8TS U5576 ( .A(n2799), .B(n5733), .Y(n5747) );
INVX3TS U5577 ( .A(n2800), .Y(n2799) );
XOR2X4TS U5578 ( .A(n3030), .B(n3001), .Y(n2800) );
NOR2X8TS U5579 ( .A(n3125), .B(n2801), .Y(n3184) );
NAND2X2TS U5580 ( .A(n4819), .B(n4820), .Y(n2802) );
OAI2BB1X4TS U5581 ( .A0N(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .A1N(n2804),
.B0(n4818), .Y(n2803) );
INVX2TS U5582 ( .A(n4820), .Y(n2804) );
OR2X8TS U5583 ( .A(n4950), .B(n2807), .Y(n2854) );
NOR2X8TS U5584 ( .A(n4981), .B(n4982), .Y(n2807) );
AND3X8TS U5585 ( .A(n3028), .B(n3027), .C(n4777), .Y(n5740) );
INVX12TS U5586 ( .A(DP_OP_498J211_124_1725_n803), .Y(n4242) );
XNOR2X4TS U5587 ( .A(n2813), .B(n2810), .Y(n4253) );
NAND2X4TS U5588 ( .A(DP_OP_496J211_122_3540_n1472), .B(
DP_OP_498J211_124_1725_n803), .Y(n2811) );
XNOR2X4TS U5589 ( .A(n4897), .B(n2814), .Y(n2980) );
XOR2X4TS U5590 ( .A(n4902), .B(n4901), .Y(n2815) );
XNOR2X4TS U5591 ( .A(n2816), .B(n5110), .Y(n5123) );
OAI21X4TS U5592 ( .A0(n5106), .A1(n5105), .B0(n5104), .Y(n2816) );
XNOR2X2TS U5593 ( .A(n2430), .B(n3895), .Y(n3801) );
NAND2X4TS U5594 ( .A(n5304), .B(n2819), .Y(n2818) );
INVX2TS U5595 ( .A(n5126), .Y(n2819) );
INVX2TS U5596 ( .A(n5304), .Y(n2820) );
XOR2X4TS U5597 ( .A(n2844), .B(n2842), .Y(n5304) );
XOR2X4TS U5598 ( .A(n2821), .B(n5384), .Y(n5407) );
OAI21X4TS U5599 ( .A0(n2829), .A1(n2822), .B0(n2825), .Y(n2821) );
AOI21X4TS U5600 ( .A0(n5014), .A1(n5013), .B0(n5012), .Y(n2830) );
NAND2X8TS U5601 ( .A(n2854), .B(n5015), .Y(n5103) );
OAI21X4TS U5602 ( .A0(n2832), .A1(n2823), .B0(n2828), .Y(n2831) );
NAND2X4TS U5603 ( .A(n2836), .B(n4526), .Y(n4516) );
OAI21X4TS U5604 ( .A0(n5691), .A1(n5699), .B0(n5692), .Y(n2834) );
NOR2X8TS U5605 ( .A(n4468), .B(n4467), .Y(n4524) );
XOR2X4TS U5606 ( .A(n3134), .B(n2838), .Y(n2851) );
OR2X4TS U5607 ( .A(n3062), .B(n2333), .Y(n5093) );
OAI21X4TS U5608 ( .A0(n2830), .A1(n5092), .B0(n5094), .Y(n2844) );
NOR2X8TS U5609 ( .A(n4992), .B(n4991), .Y(n5011) );
XOR2X4TS U5610 ( .A(n2845), .B(n3159), .Y(n4992) );
XOR2X4TS U5611 ( .A(n2853), .B(n5022), .Y(n5023) );
XOR2X4TS U5612 ( .A(n5020), .B(n5021), .Y(n2853) );
XNOR2X4TS U5613 ( .A(n2857), .B(n2855), .Y(n4221) );
NAND2X6TS U5614 ( .A(n4291), .B(n2858), .Y(n2857) );
NAND2X2TS U5615 ( .A(n2860), .B(n3048), .Y(n7245) );
XNOR2X4TS U5616 ( .A(n2823), .B(n5052), .Y(n2859) );
AOI2BB1X4TS U5617 ( .A0N(n3300), .A1N(n3297), .B0(n2871), .Y(n3138) );
XNOR2X4TS U5618 ( .A(n3661), .B(n2876), .Y(n3650) );
XOR2X4TS U5619 ( .A(n3663), .B(n2877), .Y(n2876) );
OAI2BB1X4TS U5620 ( .A0N(n2886), .A1N(n2885), .B0(n3448), .Y(n2884) );
XOR2X4TS U5621 ( .A(n3450), .B(n3449), .Y(n2887) );
XNOR2X4TS U5622 ( .A(n3805), .B(n2888), .Y(n5179) );
NAND2X4TS U5623 ( .A(n3817), .B(n2242), .Y(n2888) );
NAND3X8TS U5624 ( .A(n3783), .B(n2964), .C(n2963), .Y(n3805) );
XNOR2X4TS U5625 ( .A(n2891), .B(n3555), .Y(n3560) );
OAI21X4TS U5626 ( .A0(n2749), .A1(n3588), .B0(n3099), .Y(n2891) );
NOR2X8TS U5627 ( .A(n2894), .B(n2893), .Y(n2892) );
NOR2X8TS U5628 ( .A(n5319), .B(n5197), .Y(n5331) );
AND2X6TS U5629 ( .A(n2899), .B(n2898), .Y(n3218) );
NOR2X8TS U5630 ( .A(n2902), .B(n3804), .Y(n2950) );
INVX12TS U5631 ( .A(DP_OP_496J211_122_3540_n1461), .Y(n3480) );
XOR2X4TS U5632 ( .A(n2906), .B(n2309), .Y(n3486) );
OAI2BB1X4TS U5633 ( .A0N(n3505), .A1N(n2907), .B0(n3475), .Y(n2906) );
OAI2BB1X4TS U5634 ( .A0N(n3597), .A1N(n3596), .B0(n2911), .Y(n3634) );
OAI21X4TS U5635 ( .A0(n3596), .A1(n3597), .B0(n3595), .Y(n2911) );
OAI21X4TS U5636 ( .A0(n2916), .A1(n2914), .B0(n2912), .Y(n3271) );
OAI21X4TS U5637 ( .A0(n2913), .A1(n2917), .B0(n2915), .Y(n2912) );
INVX12TS U5638 ( .A(DP_OP_497J211_123_1725_n794), .Y(n3270) );
INVX2TS U5639 ( .A(n3632), .Y(n3621) );
XNOR2X4TS U5640 ( .A(n2921), .B(n3496), .Y(n3573) );
OR2X8TS U5641 ( .A(n5673), .B(n5670), .Y(n3002) );
NAND2X6TS U5642 ( .A(n4658), .B(n4659), .Y(n2924) );
OAI21X4TS U5643 ( .A0(n4873), .A1(n4877), .B0(n4875), .Y(n4659) );
OAI22X2TS U5644 ( .A0(n3801), .A1(n4600), .B0(n2243), .B1(n2925), .Y(n3890)
);
XNOR2X2TS U5645 ( .A(n2576), .B(n3800), .Y(n2925) );
AND2X8TS U5646 ( .A(n5442), .B(n5698), .Y(n5449) );
NOR2X6TS U5647 ( .A(n5680), .B(n5679), .Y(n5442) );
NOR2X8TS U5648 ( .A(n5437), .B(n5438), .Y(n5680) );
NAND2BX4TS U5649 ( .AN(n2927), .B(n3006), .Y(n3005) );
INVX4TS U5650 ( .A(n2940), .Y(n3768) );
XOR2X4TS U5651 ( .A(n2940), .B(n3749), .Y(n2928) );
NOR2X8TS U5652 ( .A(n4294), .B(n2936), .Y(n3869) );
XOR2X4TS U5653 ( .A(FPMULT_Op_MX[22]), .B(n2936), .Y(n3316) );
NAND3X8TS U5654 ( .A(n2960), .B(n2959), .C(n2307), .Y(n2940) );
XOR2X4TS U5655 ( .A(n2942), .B(n4064), .Y(n4082) );
OAI22X4TS U5656 ( .A0(n3940), .A1(n4093), .B0(n4094), .B1(n3982), .Y(n2943)
);
AOI21X4TS U5657 ( .A0(n5331), .A1(n2604), .B0(n5330), .Y(n5295) );
NAND2X6TS U5658 ( .A(n2952), .B(n5235), .Y(n2951) );
XOR2X4TS U5659 ( .A(n2966), .B(n2955), .Y(n3806) );
NAND2X8TS U5660 ( .A(n2956), .B(n2992), .Y(n2966) );
OAI21X4TS U5661 ( .A0(n3769), .A1(DP_OP_496J211_122_3540_n1202), .B0(
DP_OP_496J211_122_3540_n1203), .Y(n3779) );
XOR2X4TS U5662 ( .A(n2958), .B(n3004), .Y(n2957) );
NAND2X6TS U5663 ( .A(n3115), .B(n2315), .Y(n3871) );
OAI22X4TS U5664 ( .A0(n3868), .A1(n4934), .B0(n4933), .B1(n4120), .Y(n4117)
);
NAND2X2TS U5665 ( .A(n2242), .B(n3805), .Y(n2962) );
NAND2BX4TS U5666 ( .AN(n2965), .B(n3784), .Y(n2964) );
NAND3X8TS U5667 ( .A(n2971), .B(n2969), .C(n2968), .Y(n4902) );
NAND3X8TS U5668 ( .A(n3090), .B(n2234), .C(n3092), .Y(n2972) );
OAI21X4TS U5669 ( .A0(n2974), .A1(n3456), .B0(n2552), .Y(n2973) );
AND2X4TS U5670 ( .A(n2976), .B(n2975), .Y(n3245) );
XOR2X4TS U5671 ( .A(n2976), .B(n2975), .Y(n3217) );
AOI21X4TS U5672 ( .A0(n2979), .A1(n5743), .B0(n2978), .Y(n2977) );
OAI21X4TS U5673 ( .A0(n5740), .A1(n5747), .B0(n5741), .Y(n2978) );
XOR2X4TS U5674 ( .A(n3503), .B(n3502), .Y(n2981) );
XNOR2X4TS U5675 ( .A(n2991), .B(n3874), .Y(n2990) );
NOR2X4TS U5676 ( .A(n3556), .B(n3305), .Y(n3328) );
XOR2X4TS U5677 ( .A(n3305), .B(n3556), .Y(n3344) );
XOR2X4TS U5678 ( .A(n3052), .B(n5445), .Y(n5448) );
OAI22X2TS U5679 ( .A0(n2303), .A1(n5207), .B0(n2593), .B1(n2997), .Y(n4015)
);
XOR2X4TS U5680 ( .A(n3826), .B(n3809), .Y(n2996) );
INVX2TS U5681 ( .A(n3869), .Y(n3006) );
INVX2TS U5682 ( .A(n4215), .Y(n4519) );
XNOR2X4TS U5683 ( .A(n3035), .B(n3034), .Y(n4215) );
AOI21X4TS U5684 ( .A0(n3011), .A1(n2267), .B0(n3009), .Y(n5684) );
OAI2BB1X4TS U5685 ( .A0N(n4555), .A1N(n3013), .B0(n3012), .Y(n4958) );
OAI21X4TS U5686 ( .A0(n3013), .A1(n4555), .B0(n4554), .Y(n3012) );
XOR2X4TS U5687 ( .A(n4977), .B(n4976), .Y(n3061) );
XNOR2X4TS U5688 ( .A(n3018), .B(n3017), .Y(n5142) );
NOR2BX4TS U5689 ( .AN(n2238), .B(n4250), .Y(n4365) );
AOI21X4TS U5690 ( .A0(n3726), .A1(n3725), .B0(n3020), .Y(n3488) );
XNOR2X4TS U5691 ( .A(n3025), .B(n5728), .Y(n5732) );
XNOR2X4TS U5692 ( .A(n3033), .B(n4377), .Y(n4375) );
AOI21X4TS U5693 ( .A0(n3042), .A1(n3101), .B0(n3041), .Y(n3040) );
NOR2X8TS U5694 ( .A(n5155), .B(n5283), .Y(n3042) );
INVX2TS U5695 ( .A(n4676), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
NAND2X6TS U5696 ( .A(n3738), .B(n3739), .Y(n3043) );
OA21X4TS U5697 ( .A0(n3262), .A1(n3263), .B0(n3261), .Y(n3287) );
OAI2BB1X4TS U5698 ( .A0N(n2940), .A1N(n3853), .B0(n3073), .Y(n3044) );
XOR2X4TS U5699 ( .A(n3045), .B(n2308), .Y(n3499) );
XOR2X4TS U5700 ( .A(n3047), .B(n3491), .Y(n3081) );
NOR2X8TS U5701 ( .A(n2230), .B(n3379), .Y(n3491) );
NAND2BX4TS U5702 ( .AN(n3489), .B(n3490), .Y(n3047) );
INVX2TS U5703 ( .A(n2300), .Y(n3048) );
NAND2X8TS U5704 ( .A(n3050), .B(n3049), .Y(n5307) );
INVX2TS U5705 ( .A(n5446), .Y(n3051) );
XOR2X4TS U5706 ( .A(n4300), .B(n3057), .Y(n4281) );
XOR2X4TS U5707 ( .A(n4566), .B(n3058), .Y(n3057) );
AND2X8TS U5708 ( .A(n4177), .B(n7688), .Y(n4180) );
OAI2BB1X4TS U5709 ( .A0N(n4386), .A1N(n4385), .B0(n3059), .Y(n4465) );
OAI21X4TS U5710 ( .A0(n4385), .A1(n4386), .B0(n4384), .Y(n3059) );
XNOR2X4TS U5711 ( .A(n3060), .B(n4385), .Y(n4422) );
XNOR2X4TS U5712 ( .A(n4384), .B(n4386), .Y(n3060) );
XOR2X4TS U5713 ( .A(n3061), .B(n4975), .Y(n4978) );
XOR2X4TS U5714 ( .A(n3856), .B(n3855), .Y(n3074) );
CLKBUFX3TS U5715 ( .A(n5680), .Y(n3069) );
NOR2X8TS U5716 ( .A(n3111), .B(n3803), .Y(n3819) );
XOR2X4TS U5717 ( .A(n2305), .B(n3112), .Y(n3111) );
OAI21X4TS U5718 ( .A0(n3794), .A1(n7733), .B0(DP_OP_496J211_122_3540_n1199),
.Y(n3071) );
AOI21X4TS U5719 ( .A0(n5318), .A1(n2889), .B0(n5317), .Y(n5323) );
OAI22X4TS U5720 ( .A0(n5177), .A1(n3072), .B0(n3935), .B1(n3993), .Y(n3958)
);
XOR2X4TS U5721 ( .A(n3076), .B(n3077), .Y(n3075) );
XNOR2X4TS U5722 ( .A(n5211), .B(n4936), .Y(n3935) );
INVX2TS U5723 ( .A(n3855), .Y(n3077) );
OAI21X4TS U5724 ( .A0(n5763), .A1(n6252), .B0(n5735), .Y(n5543) );
XOR2X4TS U5725 ( .A(n3739), .B(n3080), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
INVX2TS U5726 ( .A(n3484), .Y(n3734) );
OR2X4TS U5727 ( .A(n3484), .B(n3485), .Y(n3084) );
INVX12TS U5728 ( .A(n3717), .Y(n3095) );
XNOR2X4TS U5729 ( .A(n3522), .B(n3570), .Y(n3564) );
XNOR2X4TS U5730 ( .A(n3100), .B(n3713), .Y(n3714) );
XOR2X4TS U5731 ( .A(n3103), .B(n2653), .Y(n3520) );
NOR2X8TS U5732 ( .A(n3298), .B(n3104), .Y(n3103) );
INVX6TS U5733 ( .A(n3297), .Y(n3104) );
XNOR2X4TS U5734 ( .A(n5125), .B(n5124), .Y(n5127) );
XOR2X4TS U5735 ( .A(n3107), .B(n4957), .Y(n4960) );
XOR2X4TS U5736 ( .A(n4956), .B(n3108), .Y(n3107) );
OAI2BB1X4TS U5737 ( .A0N(n4976), .A1N(n4977), .B0(n3109), .Y(n5017) );
NAND2X4TS U5738 ( .A(n3803), .B(n3111), .Y(n3820) );
XNOR2X4TS U5739 ( .A(n2950), .B(n3114), .Y(n5252) );
NAND2X4TS U5740 ( .A(n2954), .B(n3870), .Y(n3115) );
INVX4TS U5741 ( .A(n3870), .Y(n3116) );
XOR2X4TS U5742 ( .A(n3119), .B(n2310), .Y(n3867) );
XNOR2X4TS U5743 ( .A(n3123), .B(n3121), .Y(FPMULT_Sgf_operation_Result[27])
);
OAI21X4TS U5744 ( .A0(n3126), .A1(n5742), .B0(n3124), .Y(n3123) );
OAI21X4TS U5745 ( .A0(n3157), .A1(n5754), .B0(n3127), .Y(n3126) );
INVX2TS U5746 ( .A(n4026), .Y(n3128) );
XOR2X4TS U5747 ( .A(n3132), .B(n3171), .Y(n4649) );
XNOR2X4TS U5748 ( .A(n3131), .B(n3741), .Y(n3171) );
XNOR2X4TS U5749 ( .A(n5142), .B(n4648), .Y(n3132) );
NOR2X4TS U5750 ( .A(n3220), .B(n3295), .Y(n3223) );
NAND2X8TS U5751 ( .A(n3139), .B(n3138), .Y(n3137) );
INVX8TS U5752 ( .A(n5714), .Y(n5596) );
NAND2BX1TS U5753 ( .AN(n2382), .B(n2430), .Y(n3796) );
ADDFHX4TS U5754 ( .A(n4466), .B(n4465), .CI(n4464), .CO(n4499), .S(n4429) );
ADDFHX4TS U5755 ( .A(n4229), .B(n4228), .CI(n4227), .CO(n4288), .S(n4237) );
ADDFHX4TS U5756 ( .A(n4052), .B(n4051), .CI(n4050), .CO(n4068), .S(n4059) );
INVX4TS U5757 ( .A(n4847), .Y(n4044) );
NAND2X2TS U5758 ( .A(n3283), .B(n3282), .Y(n4742) );
INVX2TS U5759 ( .A(n4578), .Y(n3920) );
XOR2X4TS U5760 ( .A(n4669), .B(n4668), .Y(n4880) );
NOR2X8TS U5761 ( .A(n4397), .B(DP_OP_498J211_124_1725_n732), .Y(n4473) );
XOR2X4TS U5762 ( .A(n4861), .B(n4860), .Y(n4870) );
ADDFHX2TS U5763 ( .A(n4937), .B(n4936), .CI(n4935), .CO(n5186), .S(n4930) );
OAI22X2TS U5764 ( .A0(n4934), .A1(n4120), .B0(n4933), .B1(n2707), .Y(n4935)
);
NOR2X4TS U5765 ( .A(n4166), .B(DP_OP_498J211_124_1725_n645), .Y(n4733) );
NOR2X6TS U5766 ( .A(n3342), .B(n3612), .Y(n3329) );
ADDFHX4TS U5767 ( .A(n3988), .B(n3987), .CI(n3986), .CO(n4088), .S(n4078) );
ADDFHX2TS U5768 ( .A(n3528), .B(n3527), .CI(n3526), .CO(n3567), .S(n3534) );
ADDHX4TS U5769 ( .A(n4164), .B(n4163), .CO(n4171), .S(n4205) );
ADDFHX4TS U5770 ( .A(n3338), .B(n3337), .CI(n3336), .CO(n3413), .S(n3361) );
NOR2X4TS U5771 ( .A(n4822), .B(n4821), .Y(n5060) );
ADDFHX4TS U5772 ( .A(n3938), .B(n3937), .CI(n3936), .CO(n3942), .S(n4064) );
OAI22X2TS U5773 ( .A0(n4106), .A1(n5208), .B0(n3960), .B1(n2303), .Y(n4126)
);
XNOR2X4TS U5774 ( .A(n4833), .B(n4832), .Y(n4834) );
ADDFHX4TS U5775 ( .A(n4058), .B(n4057), .CI(n4056), .CO(n4065), .S(n4066) );
ADDHX4TS U5776 ( .A(n8518), .B(DP_OP_496J211_122_3540_n778), .CO(n3811), .S(
n3911) );
ADDFHX2TS U5777 ( .A(n4498), .B(n4497), .CI(n4496), .CO(n4538), .S(n4504) );
XNOR2X2TS U5778 ( .A(n5252), .B(n5198), .Y(n4923) );
ADDFHX4TS U5779 ( .A(n4966), .B(n4965), .CI(n4964), .CO(n5021), .S(n4959) );
OAI22X2TS U5780 ( .A0(n5031), .A1(n4407), .B0(n4954), .B1(n4448), .Y(n4384)
);
ADDFHX4TS U5781 ( .A(n2313), .B(n3536), .CI(n3535), .CO(n3584), .S(n3549) );
ADDFHX2TS U5782 ( .A(n5168), .B(n5167), .CI(n5166), .CO(n5226), .S(n5188) );
ADDFHX4TS U5783 ( .A(n3525), .B(n3524), .CI(n3523), .CO(n3586), .S(n3531) );
ADDFHX4TS U5784 ( .A(n4911), .B(n4910), .CI(n4909), .CO(n5196), .S(n4906) );
ADDFHX2TS U5785 ( .A(n4420), .B(n4419), .CI(n4418), .CO(n4431), .S(n4423) );
OAI22X2TS U5786 ( .A0(n2349), .A1(n3571), .B0(n2434), .B1(n3606), .Y(n3568)
);
XNOR2X4TS U5787 ( .A(n5340), .B(n4921), .Y(n4106) );
ADDFHX4TS U5788 ( .A(n5196), .B(n5195), .CI(n5194), .CO(n5234), .S(n4946) );
OAI22X2TS U5789 ( .A0(n3982), .A1(n4093), .B0(n4010), .B1(n4094), .Y(n4047)
);
OAI22X2TS U5790 ( .A0(n4010), .A1(n4093), .B0(n4009), .B1(n4094), .Y(n4050)
);
NOR2X4TS U5791 ( .A(n3295), .B(DP_OP_497J211_123_1725_n638), .Y(n3213) );
ADDFHX4TS U5792 ( .A(n3985), .B(n3984), .CI(n3983), .CO(n3987), .S(n4069) );
ADDFHX4TS U5793 ( .A(n4558), .B(n4557), .CI(n4556), .CO(n4976), .S(n4542) );
ADDFHX4TS U5794 ( .A(n4624), .B(n4623), .CI(n4622), .CO(n5254), .S(n5203) );
ADDFHX2TS U5795 ( .A(n4612), .B(n4611), .CI(n4610), .CO(n4624), .S(n4609) );
ADDFHX4TS U5796 ( .A(n4055), .B(n4054), .CI(n4053), .CO(n5290), .S(n5278) );
ADDFHX2TS U5797 ( .A(n5028), .B(n5027), .CI(n5026), .CO(n5077), .S(n5020) );
ADDFHX2TS U5798 ( .A(n5038), .B(n5037), .CI(n5036), .CO(n5075), .S(n5025) );
ADDFHX4TS U5799 ( .A(n4513), .B(n4512), .CI(n4511), .CO(n4541), .S(n4478) );
NOR2X4TS U5800 ( .A(n4484), .B(DP_OP_498J211_124_1725_n732), .Y(n4274) );
ADDFHX2TS U5801 ( .A(n4410), .B(n4409), .CI(n4408), .CO(n4439), .S(n4419) );
XNOR2X4TS U5802 ( .A(n2940), .B(n3886), .Y(n4001) );
ADDHX4TS U5803 ( .A(n3209), .B(n3208), .CO(n3216), .S(n3305) );
CMPR22X2TS U5804 ( .A(n4535), .B(n4534), .CO(n4963), .S(n4531) );
ADDFHX4TS U5805 ( .A(n3315), .B(n3314), .CI(n3313), .CO(n3656), .S(n3623) );
ADDHX4TS U5806 ( .A(n3309), .B(n3308), .CO(n3315), .S(n3627) );
OAI22X2TS U5807 ( .A0(n3940), .A1(n4094), .B0(n3939), .B1(n4093), .Y(n3941)
);
OAI22X2TS U5808 ( .A0(n3409), .A1(n2298), .B0(n3342), .B1(n3318), .Y(n3347)
);
ADDFHX2TS U5809 ( .A(n3444), .B(n3443), .CI(n3442), .CO(n3523), .S(n3459) );
ADDFHX4TS U5810 ( .A(n4506), .B(n4505), .CI(n2268), .CO(n4558), .S(n4503) );
NAND2X4TS U5811 ( .A(n4577), .B(n4576), .Y(n4772) );
ADDFHX4TS U5812 ( .A(n4423), .B(n4422), .CI(n4421), .CO(n4424), .S(n4360) );
ADDFHX2TS U5813 ( .A(n3609), .B(n3608), .CI(n3607), .CO(n3645), .S(n3601) );
ADDFHX4TS U5814 ( .A(n5202), .B(n5201), .CI(n5200), .CO(n5662), .S(n5633) );
ADDFHX4TS U5815 ( .A(n3245), .B(n3244), .CI(n3243), .CO(n3265), .S(n3246) );
OAI22X2TS U5816 ( .A0(n3393), .A1(n2298), .B0(n2351), .B1(n3318), .Y(n3365)
);
OAI22X2TS U5817 ( .A0(n3393), .A1(n3571), .B0(n2351), .B1(n3606), .Y(n3414)
);
ADDFHX2TS U5818 ( .A(n3569), .B(n3568), .CI(n3567), .CO(n3593), .S(n3585) );
OAI22X2TS U5819 ( .A0(n5031), .A1(n4448), .B0(n5071), .B1(n4407), .Y(n4434)
);
ADDFHX4TS U5820 ( .A(n4380), .B(n4379), .CI(n4378), .CO(n4430), .S(n4359) );
ADDHX4TS U5821 ( .A(n3242), .B(n3241), .CO(n3272), .S(n3244) );
ADDFHX4TS U5822 ( .A(n3455), .B(n3454), .CI(n3453), .CO(n3543), .S(n3450) );
ADDFHX4TS U5823 ( .A(n4553), .B(n4552), .CI(n4551), .CO(n5392), .S(n5365) );
ADDFHX4TS U5824 ( .A(n4509), .B(n4508), .CI(n4507), .CO(n4557), .S(n4511) );
NOR2X8TS U5825 ( .A(DP_OP_497J211_123_1725_n716), .B(n2304), .Y(n3466) );
NOR2X4TS U5826 ( .A(DP_OP_497J211_123_1725_n716), .B(n8285), .Y(n3400) );
ADDFHX4TS U5827 ( .A(n4249), .B(n4248), .CI(n4247), .CO(n4510), .S(n4441) );
ADDFHX4TS U5828 ( .A(n4346), .B(n4345), .CI(n4344), .CO(n4421), .S(n4304) );
ADDHX4TS U5829 ( .A(n4326), .B(n4325), .CO(n4412), .S(n4334) );
NOR2X4TS U5830 ( .A(n4331), .B(n4955), .Y(n4326) );
NAND2X2TS U5831 ( .A(n3863), .B(n3854), .Y(n3837) );
ADDFHX2TS U5832 ( .A(n4546), .B(n4545), .CI(n4544), .CO(n4967), .S(n4552) );
NOR2X4TS U5833 ( .A(n4166), .B(n4165), .Y(n4164) );
OAI22X2TS U5834 ( .A0(n3881), .A1(n3996), .B0(n4612), .B1(n4024), .Y(n4105)
);
ADDFHX4TS U5835 ( .A(n3226), .B(n3225), .CI(n3224), .CO(n3412), .S(n3358) );
ADDFHX4TS U5836 ( .A(n4416), .B(n4415), .CI(n4414), .CO(n5083), .S(n5043) );
ADDFHX4TS U5837 ( .A(n6899), .B(n7454), .CI(n3752), .CO(n3758), .S(n3810) );
ADDFHX4TS U5838 ( .A(n4275), .B(n4274), .CI(n4273), .CO(n4985), .S(n4565) );
OAI22X2TS U5839 ( .A0(n4922), .A1(n2303), .B0(n5165), .B1(n5208), .Y(n5171)
);
ADDFHX4TS U5840 ( .A(n3327), .B(n3326), .CI(n3325), .CO(n3622), .S(n3628) );
ADDFHX4TS U5841 ( .A(n3216), .B(n3215), .CI(n3214), .CO(n3312), .S(n3307) );
ADDHX4TS U5842 ( .A(n3930), .B(n3929), .CO(n3918), .S(n3936) );
OAI22X4TS U5843 ( .A0(n5338), .A1(n3949), .B0(n2237), .B1(n3948), .Y(n3984)
);
OAI22X4TS U5844 ( .A0(n5338), .A1(n2511), .B0(n2237), .B1(n3947), .Y(n3985)
);
CMPR22X2TS U5845 ( .A(n4012), .B(n4011), .CO(n5279), .S(n5276) );
OAI22X4TS U5846 ( .A0(n3994), .A1(n3072), .B0(n4027), .B1(n3993), .Y(n4018)
);
ADDFHX4TS U5847 ( .A(n3928), .B(n3927), .CI(n3926), .CO(n4583), .S(n4582) );
NOR2X8TS U5848 ( .A(n4397), .B(n4391), .Y(n4518) );
ADDHX4TS U5849 ( .A(n4162), .B(n4161), .CO(n4170), .S(n4219) );
ADDFHX4TS U5850 ( .A(n4254), .B(n4253), .CI(n4252), .CO(n4548), .S(n4251) );
ADDFHX4TS U5851 ( .A(n3970), .B(n3969), .CI(n3968), .CO(n4585), .S(n4584) );
CMPR22X2TS U5852 ( .A(n3898), .B(n3897), .CO(n3970), .S(n3927) );
ADDFHX4TS U5853 ( .A(n4159), .B(n4158), .CI(n4157), .CO(n4417), .S(n4350) );
ADDFHX4TS U5854 ( .A(n3426), .B(n3425), .CI(n3424), .CO(n3427), .S(n3389) );
NAND2X4TS U5855 ( .A(n5732), .B(n5731), .Y(n5759) );
ADDFHX2TS U5856 ( .A(n5077), .B(n5076), .CI(n5075), .CO(n5107), .S(n5067) );
ADDFHX4TS U5857 ( .A(n3579), .B(n3578), .CI(n3577), .CO(n3617), .S(n3561) );
ADDFHX4TS U5858 ( .A(n3396), .B(n3395), .CI(n3394), .CO(n3677), .S(n3657) );
ADDFHX2TS U5859 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3396), .S(n3313) );
NOR2X8TS U5860 ( .A(n5123), .B(n5122), .Y(n5464) );
ADDFHX4TS U5861 ( .A(n4017), .B(n4016), .CI(n4015), .CO(n4048), .S(n4045) );
ADDFHX4TS U5862 ( .A(n3212), .B(n3211), .CI(n3210), .CO(n3324), .S(n3321) );
OAI22X2TS U5863 ( .A0(n4536), .A1(n4955), .B0(n2837), .B1(n5032), .Y(n4962)
);
BUFX20TS U5864 ( .A(n4536), .Y(n5031) );
ADDFHX4TS U5865 ( .A(n3976), .B(n3975), .CI(n3974), .CO(n5359), .S(n5291) );
OAI22X2TS U5866 ( .A0(n2837), .A1(n4495), .B0(n2379), .B1(n4550), .Y(n4463)
);
OAI22X2TS U5867 ( .A0(n2837), .A1(n5029), .B0(n4549), .B1(n5070), .Y(n4966)
);
OAI22X2TS U5868 ( .A0(n4549), .A1(n4440), .B0(n2437), .B1(n4491), .Y(n4349)
);
OAI22X2TS U5869 ( .A0(n4549), .A1(n4955), .B0(n2437), .B1(n5032), .Y(n4497)
);
OAI22X2TS U5870 ( .A0(n4549), .A1(n4537), .B0(n2437), .B1(n4970), .Y(n4447)
);
ADDFHX4TS U5871 ( .A(n4329), .B(n4328), .CI(n4327), .CO(n5044), .S(n4984) );
ADDFHX4TS U5872 ( .A(n3921), .B(n3922), .CI(n3920), .CO(n3929), .S(n4057) );
INVX4TS U5873 ( .A(n4873), .Y(n4874) );
XNOR2X4TS U5874 ( .A(n5419), .B(n5198), .Y(n5199) );
ADDFHX2TS U5875 ( .A(n4118), .B(n4936), .CI(n4117), .CO(n4931), .S(n4121) );
XNOR2X4TS U5876 ( .A(n5205), .B(n4921), .Y(n3925) );
ADDFHX4TS U5877 ( .A(n4460), .B(n4459), .CI(n4458), .CO(n5119), .S(n5084) );
ADDFHX4TS U5878 ( .A(n4170), .B(n4169), .CI(n4168), .CO(n4323), .S(n4295) );
ADDFHX4TS U5879 ( .A(n4173), .B(n4172), .CI(n4171), .CO(n4276), .S(n4224) );
ADDFHX4TS U5880 ( .A(n4152), .B(n4151), .CI(n4150), .CO(n4449), .S(n4390) );
ADDFHX2TS U5881 ( .A(n4145), .B(n4144), .CI(n4143), .CO(n4244), .S(n4151) );
NAND2X1TS U5882 ( .A(n1667), .B(n1661), .Y(n3140) );
OR2X2TS U5883 ( .A(n5254), .B(n5262), .Y(n3142) );
OA21X4TS U5884 ( .A0(n4829), .A1(n4826), .B0(n4830), .Y(n3143) );
INVX2TS U5885 ( .A(n4572), .Y(n4573) );
OA21XLTS U5886 ( .A0(n5510), .A1(n5509), .B0(n5508), .Y(n3151) );
CLKXOR2X2TS U5887 ( .A(n5479), .B(n5478), .Y(n3152) );
OR2X2TS U5888 ( .A(FPMULT_FSM_selector_B[1]), .B(n7808), .Y(n3154) );
INVX2TS U5889 ( .A(n5723), .Y(n5738) );
NAND2X1TS U5890 ( .A(add_x_69_n113), .B(n5718), .Y(n5723) );
AND2X4TS U5891 ( .A(add_x_69_n272), .B(n5750), .Y(n3157) );
NAND2X1TS U5892 ( .A(n7701), .B(n7706), .Y(n3160) );
XNOR2X4TS U5893 ( .A(n3806), .B(n6898), .Y(n3161) );
OR2X1TS U5894 ( .A(n4195), .B(n4194), .Y(n3162) );
AO22XLTS U5895 ( .A0(n5896), .A1(n7570), .B0(n8784), .B1(n7569), .Y(n3169)
);
AO22XLTS U5896 ( .A0(n8786), .A1(n7575), .B0(n7574), .B1(gt_x_74_B_23_), .Y(
n3170) );
NOR2BX2TS U5897 ( .AN(n6614), .B(FPMULT_FS_Module_state_reg[1]), .Y(n6945)
);
CLKBUFX2TS U5898 ( .A(DP_OP_496J211_122_3540_n1493), .Y(n7468) );
OR2X4TS U5899 ( .A(n4224), .B(n4219), .Y(n3181) );
OR2X2TS U5900 ( .A(n4565), .B(n4566), .Y(n3182) );
CLKXOR2X2TS U5901 ( .A(n5405), .B(n5404), .Y(n3186) );
OA21XLTS U5902 ( .A0(n5618), .A1(n5617), .B0(n5616), .Y(n3187) );
AND2X2TS U5903 ( .A(n5610), .B(n5609), .Y(n3188) );
OR2X8TS U5904 ( .A(n4885), .B(n4884), .Y(n3190) );
XOR2X1TS U5905 ( .A(n5666), .B(n5665), .Y(n3192) );
OR2X1TS U5906 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n3193) );
OR2X1TS U5907 ( .A(n7941), .B(FPADDSUB_DMP_SFG[9]), .Y(n3194) );
AO22XLTS U5908 ( .A0(n8783), .A1(n7568), .B0(n8782), .B1(n7567), .Y(n3195)
);
AO22XLTS U5909 ( .A0(n5914), .A1(n7566), .B0(n8805), .B1(n7625), .Y(n3196)
);
AO22XLTS U5910 ( .A0(n8810), .A1(n7638), .B0(n8815), .B1(n7565), .Y(n3197)
);
AO22XLTS U5911 ( .A0(n8813), .A1(n7564), .B0(n8820), .B1(n7563), .Y(n3198)
);
AO22XLTS U5912 ( .A0(n8832), .A1(n7560), .B0(n8824), .B1(n7652), .Y(n3199)
);
AO22XLTS U5913 ( .A0(n6009), .A1(n7562), .B0(n8834), .B1(n7561), .Y(n3200)
);
AO22XLTS U5914 ( .A0(n8837), .A1(n7577), .B0(n8830), .B1(n7576), .Y(n3201)
);
INVX2TS U5915 ( .A(n5392), .Y(n4964) );
NAND2X2TS U5916 ( .A(n4401), .B(n4403), .Y(n4342) );
OAI21X2TS U5917 ( .A0(n5100), .A1(n5099), .B0(n5098), .Y(n5101) );
NOR2X1TS U5918 ( .A(n3664), .B(n3519), .Y(n3566) );
ADDFHX2TS U5919 ( .A(FPMULT_Op_MX[20]), .B(n3860), .CI(n3537), .CO(n3576),
.S(n3539) );
NAND2X2TS U5920 ( .A(n4993), .B(n5009), .Y(n4994) );
NOR2X1TS U5921 ( .A(n5968), .B(n7380), .Y(n5966) );
OR2X1TS U5922 ( .A(n5662), .B(n5661), .Y(n5664) );
NAND2X1TS U5923 ( .A(n5382), .B(n5600), .Y(n5383) );
NAND2X1TS U5924 ( .A(n2491), .B(n7814), .Y(n6991) );
NAND2X1TS U5925 ( .A(n5554), .B(n5614), .Y(n5617) );
NAND2X1TS U5926 ( .A(n2488), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6590) );
OR2X1TS U5927 ( .A(n6306), .B(n6230), .Y(n6223) );
INVX2TS U5928 ( .A(n7173), .Y(n7175) );
OR2X1TS U5929 ( .A(n7870), .B(n2479), .Y(n6080) );
OAI21X2TS U5930 ( .A0(n7218), .A1(n7221), .B0(n7219), .Y(n7224) );
NAND2X1TS U5931 ( .A(n6069), .B(n7807), .Y(n6668) );
OAI21X2TS U5932 ( .A0(n6113), .A1(n6086), .B0(n6085), .Y(n6103) );
OAI21X1TS U5933 ( .A0(n6692), .A1(n6695), .B0(n6066), .Y(n6678) );
INVX2TS U5934 ( .A(n5717), .Y(n5737) );
INVX2TS U5935 ( .A(FPMULT_zero_flag), .Y(n7478) );
OR2X1TS U5936 ( .A(FPSENCOS_d_ff2_X[23]), .B(n2360), .Y(intadd_480_CI) );
INVX2TS U5937 ( .A(result_add_subt[22]), .Y(n7523) );
INVX2TS U5938 ( .A(n6718), .Y(n7300) );
OAI2BB1X1TS U5939 ( .A0N(n6599), .A1N(n6146), .B0(n6145), .Y(n1322) );
INVX2TS U5940 ( .A(n1646), .Y(n7701) );
INVX4TS U5941 ( .A(n2244), .Y(n6962) );
INVX2TS U5942 ( .A(DP_OP_497J211_123_1725_n779), .Y(n7706) );
CLKMX2X2TS U5943 ( .A(Data_2[12]), .B(n8520), .S0(n6962), .Y(n1639) );
INVX2TS U5944 ( .A(n1639), .Y(n3202) );
NOR2BX1TS U5945 ( .AN(n3202), .B(n1627), .Y(n3203) );
INVX2TS U5946 ( .A(n3203), .Y(n7668) );
CLKMX2X2TS U5947 ( .A(Data_1[2]), .B(n8341), .S0(n2357), .Y(n1661) );
CLKMX2X2TS U5948 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n6901), .Y(n1631)
);
NOR2X2TS U5953 ( .A(n3240), .B(n3220), .Y(n3211) );
NOR2X2TS U5954 ( .A(n3283), .B(n3282), .Y(n4741) );
NOR2X2TS U5955 ( .A(n3232), .B(n3220), .Y(n4731) );
NAND2X2TS U5956 ( .A(n4731), .B(n4730), .Y(n4744) );
OAI21X2TS U5957 ( .A0(n4741), .A1(n4744), .B0(n4742), .Y(n4728) );
INVX2TS U5958 ( .A(n4727), .Y(n3207) );
AOI21X4TS U5959 ( .A0(n3204), .A1(n4728), .B0(n3207), .Y(n4722) );
NAND2X2TS U5960 ( .A(n3307), .B(n3324), .Y(n4720) );
OAI21X4TS U5961 ( .A0(n4722), .A1(n4719), .B0(n4720), .Y(n3251) );
INVX4TS U5962 ( .A(n3251), .Y(n3731) );
NOR2X4TS U5963 ( .A(n3240), .B(n8344), .Y(n3222) );
NAND2X2TS U5964 ( .A(n3312), .B(n3358), .Y(n3729) );
ADDFHX4TS U5965 ( .A(n3219), .B(n3218), .CI(n3217), .CO(n3247), .S(n3224) );
NOR2X4TS U5966 ( .A(n3480), .B(n3220), .Y(n3242) );
ADDFHX4TS U5967 ( .A(n3223), .B(n3222), .CI(n3221), .CO(n3243), .S(n3225) );
INVX2TS U5968 ( .A(n3250), .Y(n3227) );
XNOR2X4TS U5969 ( .A(n3229), .B(n3228), .Y(n3238) );
INVX2TS U5970 ( .A(n3515), .Y(n3234) );
NOR2X2TS U5971 ( .A(n3232), .B(DP_OP_497J211_123_1725_n638), .Y(n5540) );
NOR2X4TS U5972 ( .A(n3234), .B(n3233), .Y(n3262) );
INVX2TS U5973 ( .A(n3262), .Y(n3235) );
NAND2X1TS U5974 ( .A(n3235), .B(n3261), .Y(n3236) );
OR2X2TS U5975 ( .A(n3238), .B(n3237), .Y(n3239) );
NOR2X2TS U5976 ( .A(n3295), .B(n8344), .Y(n3273) );
INVX2TS U5977 ( .A(n2317), .Y(n3248) );
INVX2TS U5978 ( .A(n4731), .Y(n3277) );
INVX2TS U5979 ( .A(n3465), .Y(n3281) );
INVX2TS U5980 ( .A(n4730), .Y(n3280) );
XOR2X4TS U5981 ( .A(n3255), .B(DP_OP_497J211_123_1725_n392), .Y(n3445) );
ADDHX1TS U5982 ( .A(DP_OP_497J211_123_1725_n791), .B(FPMULT_Op_MX[18]), .CO(
n3256), .S(n3231) );
INVX2TS U5983 ( .A(n3288), .Y(n3259) );
NAND2X2TS U5984 ( .A(n3258), .B(n3257), .Y(n3286) );
INVX2TS U5985 ( .A(n3260), .Y(n3263) );
NOR2X2TS U5986 ( .A(n3480), .B(n3270), .Y(n3483) );
ADDFHX4TS U5987 ( .A(n3273), .B(n3272), .CI(n3271), .CO(n3476), .S(n3266) );
ADDFHX4TS U5988 ( .A(n3277), .B(n3276), .CI(n3275), .CO(n3351), .S(n3258) );
ADDHX1TS U5989 ( .A(DP_OP_497J211_123_1725_n792), .B(
DP_OP_497J211_123_1725_n705), .CO(n3278), .S(n3254) );
NOR2X8TS U5990 ( .A(n3860), .B(n5707), .Y(n3298) );
OAI22X1TS U5991 ( .A0(n3393), .A1(n3422), .B0(n2351), .B1(n3446), .Y(n3349)
);
CMPR32X2TS U5992 ( .A(n3281), .B(n3466), .C(n3280), .CO(n3335), .S(n3275) );
INVX2TS U5993 ( .A(n3282), .Y(n3320) );
INVX2TS U5994 ( .A(n3466), .Y(n3319) );
NOR2X2TS U5995 ( .A(n3174), .B(n2304), .Y(n3322) );
NAND2X2TS U5996 ( .A(n3285), .B(n3284), .Y(n3373) );
NAND2X2TS U5997 ( .A(n3376), .B(n3373), .Y(n3289) );
XNOR2X4TS U5998 ( .A(n3086), .B(n3292), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
NAND2BX4TS U5999 ( .AN(n3175), .B(DP_OP_497J211_123_1725_n782), .Y(n3419) );
OAI21X4TS U6000 ( .A0(n3299), .A1(n3298), .B0(n3297), .Y(n3304) );
NAND2X4TS U6001 ( .A(n3302), .B(n3301), .Y(n3303) );
OAI22X2TS U6002 ( .A0(n2434), .A1(n3441), .B0(n3521), .B1(n3519), .Y(n3404)
);
NOR2X4TS U6003 ( .A(DP_OP_497J211_123_1725_n716), .B(n2771), .Y(n3308) );
OAI22X1TS U6004 ( .A0(n2349), .A1(n3422), .B0(n2434), .B1(n3446), .Y(n3402)
);
NOR2X2TS U6005 ( .A(n3174), .B(n3355), .Y(n3327) );
NOR2X2TS U6006 ( .A(n3538), .B(n2304), .Y(n3326) );
INVX2TS U6007 ( .A(n3628), .Y(n3330) );
INVX4TS U6008 ( .A(n3622), .Y(n3337) );
OAI22X1TS U6009 ( .A0(n3393), .A1(n3441), .B0(n2351), .B1(n3519), .Y(n3372)
);
ADDFHX2TS U6010 ( .A(n3345), .B(n3344), .CI(n3343), .CO(n3363), .S(n3346) );
OAI22X1TS U6011 ( .A0(n3521), .A1(n3422), .B0(n2428), .B1(n3446), .Y(n3369)
);
ADDFHX2TS U6012 ( .A(n3348), .B(n3347), .CI(n3346), .CO(n3359), .S(n3368) );
ADDHX4TS U6013 ( .A(n3357), .B(n3356), .CO(n3398), .S(n3314) );
OAI22X1TS U6014 ( .A0(n2433), .A1(n3422), .B0(n3521), .B1(n3446), .Y(n3385)
);
ADDFHX2TS U6015 ( .A(n3366), .B(n3365), .CI(n3364), .CO(n3417), .S(n3383) );
INVX2TS U6016 ( .A(n3373), .Y(n3374) );
AO21X4TS U6017 ( .A0(n3376), .A1(n3375), .B0(n3374), .Y(n3470) );
INVX4TS U6018 ( .A(n3468), .Y(n3379) );
ADDFHX2TS U6019 ( .A(n3385), .B(n3384), .CI(n3383), .CO(n3390), .S(n3386) );
OAI21X4TS U6020 ( .A0(n3491), .A1(n3489), .B0(n3490), .Y(n3502) );
OAI22X1TS U6021 ( .A0(n3393), .A1(n3612), .B0(n2351), .B1(n2299), .Y(n3443)
);
INVX2TS U6022 ( .A(n3677), .Y(n3442) );
CMPR22X2TS U6023 ( .A(FPMULT_Op_MX[18]), .B(DP_OP_497J211_123_1725_n686),
.CO(n3452), .S(n3399) );
ADDFHX4TS U6024 ( .A(n3407), .B(n3406), .CI(n3405), .CO(n3434), .S(n3418) );
OAI22X2TS U6025 ( .A0(n2349), .A1(n2298), .B0(n2434), .B1(n3318), .Y(n3524)
);
OAI22X2TS U6026 ( .A0(n3521), .A1(n3612), .B0(n2428), .B1(n2299), .Y(n3527)
);
ADDFHX4TS U6027 ( .A(n3452), .B(DP_OP_497J211_123_1725_n669), .CI(n3451),
.CO(n3544), .S(n3448) );
NAND2X2TS U6028 ( .A(n3469), .B(n3468), .Y(n3471) );
XNOR2X4TS U6029 ( .A(n3471), .B(n3470), .Y(n3487) );
NOR2X2TS U6030 ( .A(n2317), .B(n3474), .Y(n3505) );
OAI21X4TS U6031 ( .A0(n3474), .A1(n3473), .B0(n3472), .Y(n3511) );
INVX2TS U6032 ( .A(n3511), .Y(n3475) );
ADDFHX4TS U6033 ( .A(n3478), .B(n3477), .CI(n3476), .CO(n3582), .S(n3541) );
INVX2TS U6034 ( .A(n3504), .Y(n3493) );
INVX2TS U6035 ( .A(n3508), .Y(n3492) );
AOI21X1TS U6036 ( .A0(n3511), .A1(n3493), .B0(n3492), .Y(n3494) );
INVX2TS U6037 ( .A(n3638), .Y(n3497) );
NOR2X2TS U6038 ( .A(n3604), .B(n3497), .Y(n3507) );
INVX2TS U6039 ( .A(n3507), .Y(n3498) );
NAND2X1TS U6040 ( .A(n3604), .B(n3497), .Y(n3506) );
NAND2X4TS U6041 ( .A(n3501), .B(n3500), .Y(n3503) );
NOR2X1TS U6042 ( .A(n3504), .B(n3507), .Y(n3510) );
AOI21X1TS U6043 ( .A0(n3511), .A1(n3510), .B0(n3509), .Y(n3512) );
ADDFHX4TS U6044 ( .A(n3531), .B(n3530), .CI(n3529), .CO(n3562), .S(n3550) );
ADDFHX4TS U6045 ( .A(n3534), .B(n3533), .CI(n3532), .CO(n3579), .S(n3530) );
NOR2X2TS U6046 ( .A(n3175), .B(n8285), .Y(n3572) );
ADDFHX4TS U6047 ( .A(n2241), .B(n3546), .CI(n3545), .CO(n3583), .S(n3533) );
NAND2X1TS U6048 ( .A(n3185), .B(n3626), .Y(n3558) );
CLKXOR2X2TS U6049 ( .A(n3558), .B(n3625), .Y(n3559) );
ADDFHX4TS U6050 ( .A(n3563), .B(n3562), .CI(n3561), .CO(n3590), .S(n3553) );
ADDFHX2TS U6051 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n3594), .S(n3587) );
ADDFHX4TS U6052 ( .A(DP_OP_496J211_122_3540_n1502), .B(n7454), .CI(n3572),
.CO(n3605), .S(n3575) );
INVX2TS U6053 ( .A(n5402), .Y(n3615) );
ADDFHX4TS U6054 ( .A(n3576), .B(n3575), .CI(n3574), .CO(n5403), .S(n5156) );
INVX2TS U6055 ( .A(n5403), .Y(n3613) );
NOR2X2TS U6056 ( .A(n3664), .B(n3318), .Y(n3608) );
ADDFHX4TS U6057 ( .A(n3587), .B(n3586), .CI(n3585), .CO(n3595), .S(n3563) );
ADDFHX4TS U6058 ( .A(n3603), .B(n3602), .CI(n3601), .CO(n3648), .S(n3597) );
CLKINVX6TS U6059 ( .A(n5557), .Y(n5611) );
NOR2X1TS U6060 ( .A(n2435), .B(n3606), .Y(n3636) );
INVX2TS U6061 ( .A(n2434), .Y(n3611) );
ADDFHX4TS U6062 ( .A(n3618), .B(n3617), .CI(n3616), .CO(n3619), .S(n3591) );
INVX2TS U6063 ( .A(n3654), .Y(n3624) );
NAND2X1TS U6064 ( .A(n3624), .B(n3653), .Y(n3630) );
OR2X2TS U6065 ( .A(n3628), .B(n3627), .Y(n3683) );
NAND2X1TS U6066 ( .A(n3626), .B(n3625), .Y(n3684) );
INVX2TS U6067 ( .A(n3682), .Y(n3629) );
CLKXOR2X2TS U6068 ( .A(n3630), .B(n3655), .Y(n3688) );
ADDFHX4TS U6069 ( .A(n3635), .B(n3634), .CI(n3633), .CO(n3651), .S(n3620) );
CMPR32X2TS U6070 ( .A(n2919), .B(n3637), .C(n3636), .CO(n3670), .S(n3646) );
ADDHX1TS U6071 ( .A(n3638), .B(n5611), .CO(n3667), .S(n3637) );
INVX2TS U6072 ( .A(n3640), .Y(n3665) );
ADDFHX2TS U6073 ( .A(n3643), .B(n3642), .CI(n3641), .CO(n3668), .S(n3644) );
ADDFHX4TS U6074 ( .A(n3646), .B(n3645), .CI(n3644), .CO(n3662), .S(n3647) );
OAI21X2TS U6075 ( .A0(n3655), .A1(n3654), .B0(n3653), .Y(n3705) );
INVX2TS U6076 ( .A(n3705), .Y(n3675) );
NOR2X2TS U6077 ( .A(n3657), .B(n3656), .Y(n3700) );
INVX2TS U6078 ( .A(n3700), .Y(n3658) );
NAND2X1TS U6079 ( .A(n3658), .B(n3702), .Y(n3659) );
CLKXOR2X2TS U6080 ( .A(n3675), .B(n3659), .Y(n3690) );
INVX2TS U6081 ( .A(n3694), .Y(n3673) );
NAND2X2TS U6082 ( .A(n3673), .B(n3693), .Y(n3674) );
OAI21X1TS U6083 ( .A0(n3675), .A1(n3700), .B0(n3702), .Y(n3680) );
NOR2X2TS U6084 ( .A(n3677), .B(n3676), .Y(n3703) );
INVX2TS U6085 ( .A(n3703), .Y(n3678) );
NAND2X1TS U6086 ( .A(n3678), .B(n3701), .Y(n3679) );
XNOR2X2TS U6087 ( .A(n3680), .B(n3679), .Y(n3691) );
NAND2X1TS U6088 ( .A(n3683), .B(n3682), .Y(n3685) );
XNOR2X2TS U6089 ( .A(n3685), .B(n3684), .Y(n3686) );
CMPR32X2TS U6090 ( .A(n3698), .B(n3697), .C(n3696), .CO(n3699), .S(n3671) );
OAI21X1TS U6091 ( .A0(n3703), .A1(n3702), .B0(n3701), .Y(n3704) );
AOI21X4TS U6092 ( .A0(n3706), .A1(n3705), .B0(n3704), .Y(n5618) );
NOR2X2TS U6093 ( .A(n3707), .B(n3708), .Y(n5396) );
INVX2TS U6094 ( .A(n5396), .Y(n3709) );
NAND2X1TS U6095 ( .A(n3709), .B(n5398), .Y(n3710) );
CLKXOR2X2TS U6096 ( .A(n5618), .B(n3710), .Y(n3711) );
INVX8TS U6097 ( .A(n3714), .Y(add_x_69_n69) );
INVX2TS U6098 ( .A(n3717), .Y(n3719) );
NAND2X2TS U6099 ( .A(n3719), .B(n3718), .Y(n3720) );
XOR2X4TS U6100 ( .A(n2330), .B(n3723), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
INVX2TS U6101 ( .A(n3728), .Y(n3730) );
CLKXOR2X2TS U6102 ( .A(n3732), .B(n3731), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
NOR2BX4TS U6103 ( .AN(n7709), .B(DP_OP_496J211_122_3540_n1512), .Y(n3743) );
INVX4TS U6104 ( .A(n3743), .Y(n3873) );
NAND2X2TS U6105 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J211_122_3540_n1513),
.Y(n3748) );
OR2X4TS U6106 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J211_122_3540_n1514), .Y(
n3831) );
INVX2TS U6107 ( .A(n3829), .Y(n3744) );
INVX2TS U6108 ( .A(n3746), .Y(n3747) );
NAND2X2TS U6109 ( .A(n3826), .B(n3809), .Y(n3757) );
NAND2BX4TS U6110 ( .AN(n3787), .B(n3172), .Y(n3964) );
OAI21X2TS U6111 ( .A0(n3765), .A1(n3764), .B0(n3763), .Y(n3767) );
NAND2X2TS U6112 ( .A(n3765), .B(n3764), .Y(n3766) );
NAND2X4TS U6113 ( .A(n3767), .B(n3766), .Y(n3888) );
XNOR2X4TS U6114 ( .A(n3777), .B(n3776), .Y(n4916) );
INVX6TS U6115 ( .A(n3779), .Y(n3794) );
NAND2X4TS U6116 ( .A(n3800), .B(n3781), .Y(n3817) );
INVX2TS U6117 ( .A(n3885), .Y(n3784) );
OAI22X2TS U6118 ( .A0(n4627), .A1(n2271), .B0(n3789), .B1(n4626), .Y(n4581)
);
INVX2TS U6119 ( .A(n4581), .Y(n3930) );
NAND2X8TS U6120 ( .A(n3792), .B(n2429), .Y(n4600) );
XNOR2X1TS U6121 ( .A(n2430), .B(n2382), .Y(n3793) );
OAI22X2TS U6122 ( .A0(n4600), .A1(n3793), .B0(n2243), .B1(n3801), .Y(n3980)
);
XNOR2X2TS U6123 ( .A(n3800), .B(n2440), .Y(n3797) );
XNOR2X2TS U6124 ( .A(n2305), .B(n2438), .Y(n3799) );
INVX4TS U6125 ( .A(n4579), .Y(n3922) );
OAI22X4TS U6126 ( .A0(n4600), .A1(n4599), .B0(n2243), .B1(n3796), .Y(n4576)
);
NOR2BX1TS U6127 ( .AN(n2382), .B(n3798), .Y(n3892) );
OAI21X4TS U6128 ( .A0(n3819), .A1(n3817), .B0(n3820), .Y(n3804) );
OAI2BB1X4TS U6129 ( .A0N(FPMULT_Op_MX[22]), .A1N(n2274), .B0(n3807), .Y(
n3808) );
XOR2X4TS U6130 ( .A(n3810), .B(n3823), .Y(n3825) );
ADDFHX4TS U6131 ( .A(n6900), .B(n3860), .CI(n3811), .CO(n3752), .S(n3822) );
XNOR2X4TS U6132 ( .A(n3825), .B(n3812), .Y(n3816) );
XNOR2X4TS U6133 ( .A(n2440), .B(n3822), .Y(n3914) );
NAND2X2TS U6134 ( .A(n3906), .B(n3914), .Y(n3815) );
XOR2X1TS U6135 ( .A(n3823), .B(n3822), .Y(n3824) );
NOR2X2TS U6136 ( .A(n3825), .B(n3824), .Y(n3827) );
NAND2X2TS U6137 ( .A(n3828), .B(n3831), .Y(n3846) );
INVX2TS U6138 ( .A(n3846), .Y(n3839) );
AOI21X4TS U6139 ( .A0(n3831), .A1(n3830), .B0(n3829), .Y(n3851) );
INVX2TS U6140 ( .A(n3851), .Y(n3841) );
AOI21X4TS U6141 ( .A0(n2940), .A1(n3839), .B0(n3841), .Y(n3834) );
INVX6TS U6142 ( .A(n3832), .Y(n3845) );
XNOR2X2TS U6143 ( .A(n3931), .B(n4940), .Y(n3953) );
OR2X2TS U6144 ( .A(n3175), .B(n3172), .Y(n3838) );
NAND2X2TS U6145 ( .A(n3839), .B(n3845), .Y(n3843) );
AOI21X4TS U6146 ( .A0(n3841), .A1(n3845), .B0(n3849), .Y(n3842) );
OAI22X1TS U6147 ( .A0(n3953), .A1(n5210), .B0(n4116), .B1(n5209), .Y(n4123)
);
INVX4TS U6148 ( .A(n4940), .Y(n5212) );
NAND2X4TS U6149 ( .A(n3845), .B(n3850), .Y(n3852) );
NOR2X2TS U6150 ( .A(n3846), .B(n3852), .Y(n3853) );
INVX2TS U6151 ( .A(n3847), .Y(n3848) );
XNOR2X4TS U6152 ( .A(n8486), .B(n7454), .Y(n3861) );
NOR2X1TS U6153 ( .A(n6900), .B(n3860), .Y(n3857) );
XNOR2X1TS U6154 ( .A(n3861), .B(n3857), .Y(n3858) );
XOR2X4TS U6155 ( .A(n3859), .B(n3858), .Y(n3866) );
XOR2X1TS U6156 ( .A(n3860), .B(n7454), .Y(n3862) );
NOR2X1TS U6157 ( .A(n3862), .B(n3861), .Y(n3864) );
XOR2X1TS U6158 ( .A(n3864), .B(n3863), .Y(n3865) );
XNOR2X2TS U6159 ( .A(n2442), .B(n3800), .Y(n3899) );
OAI22X2TS U6160 ( .A0(n4627), .A1(n3899), .B0(n4098), .B1(n4626), .Y(n4111)
);
OAI22X4TS U6161 ( .A0(n3894), .A1(n3996), .B0(n3881), .B1(n4024), .Y(n3902)
);
OAI22X2TS U6162 ( .A0(n4100), .A1(n2243), .B0(n4600), .B1(n3882), .Y(n4104)
);
INVX2TS U6163 ( .A(n3895), .Y(n4102) );
INVX2TS U6164 ( .A(n4586), .Y(n4092) );
NAND2X2TS U6165 ( .A(n3885), .B(n3884), .Y(n3886) );
OAI22X2TS U6166 ( .A0(n3894), .A1(n4024), .B0(n3996), .B1(n3893), .Y(n3897)
);
XNOR2X1TS U6167 ( .A(n2442), .B(n2382), .Y(n3896) );
OAI22X1TS U6168 ( .A0(n4627), .A1(n3896), .B0(n3900), .B1(n4626), .Y(n3926)
);
OAI22X2TS U6169 ( .A0(n3900), .A1(n4627), .B0(n3899), .B1(n4626), .Y(n3969)
);
XNOR2X4TS U6170 ( .A(n3906), .B(n3914), .Y(n3907) );
XOR2X2TS U6171 ( .A(n3908), .B(n3911), .Y(n3912) );
XNOR2X2TS U6172 ( .A(n3909), .B(n3912), .Y(n3910) );
NOR2X1TS U6173 ( .A(n3912), .B(n3911), .Y(n3913) );
CLKXOR2X2TS U6174 ( .A(n3914), .B(n3913), .Y(n3915) );
NOR2BX1TS U6175 ( .AN(n4001), .B(n2376), .Y(n4056) );
INVX4TS U6176 ( .A(n4582), .Y(n3937) );
XNOR2X2TS U6177 ( .A(n3931), .B(n4006), .Y(n3952) );
OAI22X2TS U6178 ( .A0(n3952), .A1(n4934), .B0(n4933), .B1(n3932), .Y(n3976)
);
XNOR2X2TS U6179 ( .A(n3951), .B(n4940), .Y(n3954) );
XNOR2X1TS U6180 ( .A(n4027), .B(n4940), .Y(n3933) );
OAI22X2TS U6181 ( .A0(n3954), .A1(n5209), .B0(n3933), .B1(n5210), .Y(n3975)
);
OAI22X2TS U6182 ( .A0(n3950), .A1(n3993), .B0(n3935), .B1(n3072), .Y(n3955)
);
ADDFHX2TS U6183 ( .A(n3943), .B(n3942), .CI(n3941), .CO(n4089), .S(n3989) );
XNOR2X1TS U6184 ( .A(n5198), .B(n4001), .Y(n3949) );
OAI22X1TS U6185 ( .A0(n4008), .A1(n4934), .B0(n3952), .B1(n4933), .Y(n4053)
);
OAI22X1TS U6186 ( .A0(n3954), .A1(n5210), .B0(n3953), .B1(n5209), .Y(n3973)
);
ADDFHX2TS U6187 ( .A(n3959), .B(n3958), .CI(n3957), .CO(n4122), .S(n3971) );
OAI22X4TS U6188 ( .A0(n2231), .A1(n3967), .B0(n5416), .B1(n4112), .Y(n4096)
);
INVX2TS U6189 ( .A(n4585), .Y(n4113) );
ADDFHX2TS U6190 ( .A(n3973), .B(n3972), .CI(n3971), .CO(n5381), .S(n5360) );
INVX2TS U6191 ( .A(n5291), .Y(n4071) );
NAND2BX1TS U6192 ( .AN(n4027), .B(n4006), .Y(n3977) );
OAI22X2TS U6193 ( .A0(n4934), .A1(n2707), .B0(n4933), .B1(n3977), .Y(n4012)
);
OAI22X4TS U6194 ( .A0(n3992), .A1(n3993), .B0(n3978), .B1(n3072), .Y(n4011)
);
CMPR22X2TS U6195 ( .A(n3980), .B(n3979), .CO(n4579), .S(n4577) );
INVX2TS U6196 ( .A(n4577), .Y(n4017) );
INVX2TS U6197 ( .A(n4779), .Y(n4023) );
NAND2BX1TS U6198 ( .AN(n2382), .B(n2439), .Y(n3997) );
NAND2X1TS U6199 ( .A(n4094), .B(n3998), .Y(n4021) );
INVX2TS U6200 ( .A(n3999), .Y(n4000) );
INVX2TS U6201 ( .A(n4003), .Y(n4019) );
NOR2BX1TS U6202 ( .AN(n4025), .B(n4024), .Y(n5135) );
INVX2TS U6203 ( .A(n5135), .Y(n4028) );
NAND2X2TS U6204 ( .A(n4029), .B(n4028), .Y(n4698) );
INVX2TS U6205 ( .A(n4698), .Y(n4030) );
INVX2TS U6206 ( .A(n4757), .Y(n4033) );
AOI21X4TS U6207 ( .A0(n4758), .A1(n3156), .B0(n4033), .Y(n4689) );
ADDFHX4TS U6208 ( .A(n4036), .B(n4035), .CI(n4034), .CO(n4060), .S(n4041) );
NOR2X4TS U6209 ( .A(n4041), .B(n4040), .Y(n4686) );
NAND2X2TS U6210 ( .A(n4041), .B(n4040), .Y(n4687) );
OAI21X4TS U6211 ( .A0(n4689), .A1(n4686), .B0(n4687), .Y(n4848) );
AOI21X4TS U6212 ( .A0(n3191), .A1(n4848), .B0(n4044), .Y(n4877) );
ADDFHX2TS U6213 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n4070), .S(n4073) );
INVX4TS U6214 ( .A(n5278), .Y(n4067) );
ADDFHX4TS U6215 ( .A(n4061), .B(n4060), .CI(n4059), .CO(n4062), .S(n4043) );
NOR2X6TS U6216 ( .A(n4063), .B(n4062), .Y(n4873) );
NAND2X4TS U6217 ( .A(n4063), .B(n4062), .Y(n4875) );
ADDFHX4TS U6218 ( .A(n4068), .B(n4067), .CI(n4066), .CO(n4081), .S(n4072) );
ADDFHX2TS U6219 ( .A(n4071), .B(n4070), .CI(n4069), .CO(n4079), .S(n4080) );
ADDFHX4TS U6220 ( .A(n4074), .B(n4073), .CI(n4072), .CO(n4075), .S(n4063) );
NOR2X8TS U6221 ( .A(n4084), .B(n4083), .Y(n4652) );
ADDFHX2TS U6222 ( .A(n4092), .B(n4091), .CI(n4090), .CO(n4944), .S(n4127) );
XNOR2X1TS U6223 ( .A(n2441), .B(n3806), .Y(n4588) );
INVX2TS U6224 ( .A(n3800), .Y(n4592) );
OAI22X2TS U6225 ( .A0(n4633), .A1(n4102), .B0(n2644), .B1(n4592), .Y(n4589)
);
ADDFHX2TS U6226 ( .A(n4105), .B(n4104), .CI(n4103), .CO(n4593), .S(n4109) );
ADDFHX4TS U6227 ( .A(n4111), .B(n4110), .CI(n4109), .CO(n4616), .S(n4586) );
XNOR2X2TS U6228 ( .A(n5179), .B(n5345), .Y(n4918) );
ADDFHX4TS U6229 ( .A(n4115), .B(n4114), .CI(n4113), .CO(n4926), .S(n4125) );
INVX2TS U6230 ( .A(n3931), .Y(n4119) );
ADDFHX4TS U6231 ( .A(n4123), .B(n4122), .CI(n4121), .CO(n5548), .S(n5380) );
NOR2X2TS U6232 ( .A(DP_OP_498J211_124_1725_n635), .B(n4165), .Y(n4149) );
NOR2X4TS U6233 ( .A(n8489), .B(n4166), .Y(n4136) );
NOR2X4TS U6234 ( .A(n4185), .B(n4243), .Y(n4135) );
NOR2X4TS U6235 ( .A(n2245), .B(n4165), .Y(n4144) );
ADDHX4TS U6236 ( .A(n4136), .B(n4135), .CO(n4139), .S(n4148) );
ADDFHX2TS U6237 ( .A(n4139), .B(n4138), .CI(n4137), .CO(n4249), .S(n4150) );
INVX2TS U6238 ( .A(n4140), .Y(n4239) );
NOR2X2TS U6239 ( .A(n4449), .B(n4441), .Y(n4250) );
INVX2TS U6240 ( .A(n4250), .Y(n4146) );
NAND2X2TS U6241 ( .A(n4146), .B(n4257), .Y(n4176) );
ADDFHX2TS U6242 ( .A(n4149), .B(n4148), .CI(n4147), .CO(n4152), .S(n4157) );
NOR2X6TS U6243 ( .A(n4417), .B(n4390), .Y(n4189) );
NOR2X4TS U6244 ( .A(n4185), .B(n4242), .Y(n4161) );
CMPR22X2TS U6245 ( .A(n4154), .B(n4153), .CO(n4147), .S(n4169) );
NOR2X4TS U6246 ( .A(n4189), .B(n4709), .Y(n4175) );
NOR2X4TS U6247 ( .A(DP_OP_498J211_124_1725_n636), .B(
DP_OP_498J211_124_1725_n645), .Y(n4173) );
NOR2X6TS U6248 ( .A(n4185), .B(n4165), .Y(n4734) );
NAND2X2TS U6249 ( .A(n4205), .B(n4204), .Y(n4737) );
OAI21X2TS U6250 ( .A0(n4736), .A1(n4739), .B0(n4737), .Y(n4726) );
NAND2X2TS U6251 ( .A(n4224), .B(n4219), .Y(n4724) );
INVX2TS U6252 ( .A(n4724), .Y(n4167) );
AOI21X2TS U6253 ( .A0(n3181), .A1(n4726), .B0(n4167), .Y(n4718) );
NAND2X2TS U6254 ( .A(n4295), .B(n4276), .Y(n4715) );
OAI21X4TS U6255 ( .A0(n4718), .A1(n4714), .B0(n4715), .Y(n4188) );
NAND2X2TS U6256 ( .A(n4350), .B(n4323), .Y(n4710) );
XOR2X4TS U6257 ( .A(n4176), .B(n4311), .Y(n4200) );
INVX2TS U6258 ( .A(n4733), .Y(n4210) );
NAND2X4TS U6259 ( .A(DP_OP_498J211_124_1725_n732), .B(
DP_OP_498J211_124_1725_n645), .Y(n4177) );
INVX4TS U6260 ( .A(n4178), .Y(n4440) );
INVX2TS U6261 ( .A(n4472), .Y(n4202) );
ADDHX1TS U6262 ( .A(FPMULT_Op_MY[6]), .B(DP_OP_498J211_124_1725_n788), .CO(
n4181), .S(n4179) );
INVX4TS U6263 ( .A(n4181), .Y(n4448) );
OAI22X2TS U6264 ( .A0(n2378), .A1(n4407), .B0(n4331), .B1(n4448), .Y(n4182)
);
NAND2X2TS U6265 ( .A(n4183), .B(n4182), .Y(n4233) );
NOR2X2TS U6266 ( .A(n4355), .B(DP_OP_498J211_124_1725_n732), .Y(n4426) );
INVX2TS U6267 ( .A(n4426), .Y(n4195) );
INVX2TS U6268 ( .A(n7210), .Y(n4194) );
NOR2X1TS U6269 ( .A(n4331), .B(n4407), .Y(n4198) );
INVX2TS U6270 ( .A(n4198), .Y(n4186) );
AND2X2TS U6271 ( .A(n4196), .B(n4186), .Y(n4234) );
CLKXOR2X2TS U6272 ( .A(n4187), .B(n4234), .Y(n4199) );
INVX2TS U6273 ( .A(n4189), .Y(n4191) );
NAND2X1TS U6274 ( .A(n3162), .B(n4196), .Y(n4197) );
NAND2X4TS U6275 ( .A(n4200), .B(n4199), .Y(n4701) );
AOI21X4TS U6276 ( .A0(n4702), .A1(n4703), .B0(n4201), .Y(n4751) );
INVX2TS U6277 ( .A(n4473), .Y(n4222) );
ADDHX1TS U6278 ( .A(n8518), .B(DP_OP_498J211_124_1725_n789), .CO(n4207), .S(
n4178) );
ADDFHX4TS U6279 ( .A(n4210), .B(n4209), .CI(n4208), .CO(n4228), .S(n4183) );
XOR2X4TS U6280 ( .A(n7700), .B(n4212), .Y(n4213) );
OAI22X1TS U6281 ( .A0(n2436), .A1(n4407), .B0(n2378), .B1(n4448), .Y(n4227)
);
ADDFHX4TS U6282 ( .A(n4216), .B(n4215), .CI(n4214), .CO(n4283), .S(n4230) );
INVX4TS U6283 ( .A(n4217), .Y(n4550) );
OAI22X2TS U6284 ( .A0(n2377), .A1(n4495), .B0(n4331), .B1(n4550), .Y(n4282)
);
INVX2TS U6285 ( .A(n4518), .Y(n4279) );
INVX4TS U6286 ( .A(n4219), .Y(n4278) );
OAI22X1TS U6287 ( .A0(n2436), .A1(n4440), .B0(n2377), .B1(n4491), .Y(n4286)
);
BUFX8TS U6288 ( .A(DP_OP_498J211_124_1725_n803), .Y(n5706) );
INVX12TS U6289 ( .A(n4221), .Y(n4549) );
NAND2X2TS U6290 ( .A(n4237), .B(n4236), .Y(n4262) );
INVX2TS U6291 ( .A(n4262), .Y(n4238) );
NAND2X2TS U6292 ( .A(n4251), .B(n4510), .Y(n4259) );
OAI21X4TS U6293 ( .A0(n4258), .A1(n4257), .B0(n4259), .Y(n4371) );
NOR2X2TS U6294 ( .A(n3150), .B(n2953), .Y(n4316) );
NOR2X2TS U6295 ( .A(n4548), .B(n4547), .Y(n4364) );
INVX2TS U6296 ( .A(n4364), .Y(n4313) );
NAND2X1TS U6297 ( .A(n4313), .B(n4368), .Y(n4256) );
INVX4TS U6298 ( .A(n4270), .Y(n4754) );
OAI21X4TS U6299 ( .A0(n4311), .A1(n4250), .B0(n4257), .Y(n4261) );
XNOR2X4TS U6300 ( .A(n4261), .B(n4260), .Y(n4267) );
NAND2X2TS U6301 ( .A(n4263), .B(n4262), .Y(n4265) );
XNOR2X2TS U6302 ( .A(n4265), .B(n4264), .Y(n4266) );
OR2X4TS U6303 ( .A(n4267), .B(n4266), .Y(n4760) );
NAND2X2TS U6304 ( .A(n4754), .B(n4760), .Y(n4272) );
NAND2X2TS U6305 ( .A(n4269), .B(n4268), .Y(n4753) );
OA21X4TS U6306 ( .A0(n4761), .A1(n4270), .B0(n4753), .Y(n4271) );
OAI21X4TS U6307 ( .A0(n4751), .A1(n4272), .B0(n4271), .Y(n4853) );
XNOR2X4TS U6308 ( .A(n4332), .B(n4335), .Y(n4280) );
INVX6TS U6309 ( .A(n4277), .Y(n4955) );
ADDHX4TS U6310 ( .A(n4279), .B(n4278), .CO(n4325), .S(n4300) );
XNOR2X4TS U6311 ( .A(n4280), .B(n4334), .Y(n4348) );
INVX2TS U6312 ( .A(n4295), .Y(n4338) );
OAI22X2TS U6313 ( .A0(n2437), .A1(n4495), .B0(n2378), .B1(n4550), .Y(n4337)
);
ADDFHX2TS U6314 ( .A(n4298), .B(n4297), .CI(n4296), .CO(n4336), .S(n4284) );
INVX2TS U6315 ( .A(n4984), .Y(n4339) );
NAND2X4TS U6316 ( .A(n4305), .B(n4361), .Y(n4310) );
XOR2X4TS U6317 ( .A(n4310), .B(n4362), .Y(n4321) );
NAND2X1TS U6318 ( .A(n4365), .B(n4313), .Y(n4315) );
INVX2TS U6319 ( .A(n4368), .Y(n4312) );
AOI21X1TS U6320 ( .A0(n4371), .A1(n4313), .B0(n4312), .Y(n4314) );
OAI21X2TS U6321 ( .A0(n4311), .A1(n4315), .B0(n4314), .Y(n4319) );
NOR2X2TS U6322 ( .A(n4974), .B(n4971), .Y(n4367) );
INVX2TS U6323 ( .A(n4367), .Y(n4317) );
NAND2X1TS U6324 ( .A(n4974), .B(n4971), .Y(n4366) );
NAND2X1TS U6325 ( .A(n4317), .B(n4366), .Y(n4318) );
OR2X4TS U6326 ( .A(n4321), .B(n4320), .Y(n4850) );
NAND2X2TS U6327 ( .A(n4321), .B(n4320), .Y(n4851) );
INVX2TS U6328 ( .A(n5044), .Y(n4387) );
ADDHX1TS U6329 ( .A(DP_OP_498J211_124_1725_n792), .B(
DP_OP_498J211_124_1725_n786), .CO(n4330), .S(n4277) );
INVX4TS U6330 ( .A(n4330), .Y(n5032) );
OAI22X1TS U6331 ( .A0(n2377), .A1(n4955), .B0(n4331), .B1(n5032), .Y(n4410)
);
XOR2X4TS U6332 ( .A(n4343), .B(n4342), .Y(n4536) );
ADDFHX4TS U6333 ( .A(n4349), .B(n4348), .CI(n4347), .CO(n4380), .S(n4346) );
NOR2X2TS U6334 ( .A(DP_OP_498J211_124_1725_n722), .B(n4391), .Y(n4394) );
ADDHX4TS U6335 ( .A(n4354), .B(n4353), .CO(n4393), .S(n4328) );
INVX2TS U6336 ( .A(n5043), .Y(n4381) );
OAI21X1TS U6337 ( .A0(n4368), .A1(n4367), .B0(n4366), .Y(n4369) );
AOI21X1TS U6338 ( .A0(n4371), .A1(n4370), .B0(n4369), .Y(n4372) );
ADDFHX2TS U6339 ( .A(n4383), .B(n4382), .CI(n4381), .CO(n4466), .S(n4379) );
ADDFHX4TS U6340 ( .A(n4389), .B(n4388), .CI(n4387), .CO(n4462), .S(n4420) );
OAI22X1TS U6341 ( .A0(n5031), .A1(n4440), .B0(n4954), .B1(n4491), .Y(n4461)
);
NOR2X2TS U6342 ( .A(n4973), .B(n4391), .Y(n4457) );
OAI22X1TS U6343 ( .A0(n2436), .A1(n4955), .B0(n2377), .B1(n5032), .Y(n4442)
);
INVX4TS U6344 ( .A(n5083), .Y(n4446) );
ADDFHX4TS U6345 ( .A(n4430), .B(n4429), .CI(n4428), .CO(n4467), .S(n4425) );
ADDFHX4TS U6346 ( .A(n4436), .B(n4435), .CI(n4434), .CO(n4513), .S(n4433) );
ADDFHX4TS U6347 ( .A(n4439), .B(n4438), .CI(n4437), .CO(n4512), .S(n4432) );
OAI22X2TS U6348 ( .A0(n4954), .A1(n4537), .B0(n4549), .B1(n4970), .Y(n4509)
);
ADDFHX4TS U6349 ( .A(n4444), .B(n4443), .CI(n4442), .CO(n4494), .S(n4438) );
OAI22X2TS U6350 ( .A0(n5031), .A1(n4495), .B0(n4954), .B1(n4550), .Y(n4493)
);
OAI22X1TS U6351 ( .A0(n2436), .A1(n5029), .B0(n2377), .B1(n5070), .Y(n4498)
);
NOR2X2TS U6352 ( .A(n4484), .B(n2275), .Y(n4482) );
ADDFHX4TS U6353 ( .A(n4454), .B(n4453), .CI(n4452), .CO(n4489), .S(n4458) );
CMPR22X2TS U6354 ( .A(n4456), .B(n4455), .CO(n4486), .S(n4453) );
OAI21X4TS U6355 ( .A0(n4476), .A1(n4524), .B0(n4527), .Y(n4517) );
ADDFHX4TS U6356 ( .A(n4479), .B(n4478), .CI(n4477), .CO(n4515), .S(n4468) );
NOR2X2TS U6357 ( .A(n4484), .B(n4972), .Y(n4545) );
ADDFHX4TS U6358 ( .A(n4490), .B(n4489), .CI(n4488), .CO(n5366), .S(n5118) );
OAI22X2TS U6359 ( .A0(n4549), .A1(n5029), .B0(n2436), .B1(n5070), .Y(n4535)
);
ADDFHX4TS U6360 ( .A(n4501), .B(n4500), .CI(n4499), .CO(n4529), .S(n4477) );
ADDFHX4TS U6361 ( .A(n4504), .B(n4503), .CI(n4502), .CO(n4543), .S(n4500) );
NAND2X2TS U6362 ( .A(n4519), .B(n4518), .Y(n4568) );
NAND2X1TS U6363 ( .A(n3168), .B(n4568), .Y(n4520) );
ADDFHX4TS U6364 ( .A(n4530), .B(n4529), .CI(n4528), .CO(n4562), .S(n4514) );
INVX2TS U6365 ( .A(n4547), .Y(n4957) );
NOR2X2TS U6366 ( .A(n5030), .B(n4550), .Y(n4965) );
NAND2X1TS U6367 ( .A(n3182), .B(n4987), .Y(n4569) );
NAND2X1TS U6368 ( .A(n4568), .B(n4567), .Y(n4989) );
XNOR2X2TS U6369 ( .A(n4569), .B(n4989), .Y(n4570) );
INVX2TS U6370 ( .A(n4782), .Y(n4788) );
AOI21X4TS U6371 ( .A0(n4572), .A1(n4788), .B0(n4575), .Y(n4774) );
OAI21X4TS U6372 ( .A0(n4771), .A1(n4774), .B0(n4772), .Y(n4766) );
INVX2TS U6373 ( .A(n4764), .Y(n4580) );
NAND2X2TS U6374 ( .A(n4582), .B(n4581), .Y(n4804) );
OAI21X4TS U6375 ( .A0(n4803), .A1(n4806), .B0(n4804), .Y(n4816) );
OAI2BB1X4TS U6376 ( .A0N(n4587), .A1N(n4816), .B0(n3143), .Y(n4856) );
INVX2TS U6377 ( .A(n4856), .Y(n4621) );
OAI22X1TS U6378 ( .A0(n4627), .A1(n4588), .B0(n4606), .B1(n4626), .Y(n4598)
);
ADDFHX2TS U6379 ( .A(n2439), .B(n4590), .CI(n4589), .CO(n4597), .S(n4594) );
OAI22X2TS U6380 ( .A0(n4591), .A1(n4600), .B0(n2243), .B1(n4599), .Y(n4603)
);
INVX2TS U6381 ( .A(n2305), .Y(n4601) );
ADDFHX4TS U6382 ( .A(n4595), .B(n4594), .CI(n4593), .CO(n4914), .S(n4615) );
NOR2X4TS U6383 ( .A(n4915), .B(n4914), .Y(n4693) );
NOR2X4TS U6384 ( .A(n4691), .B(n4693), .Y(n4855) );
ADDFHX4TS U6385 ( .A(n4598), .B(n4597), .CI(n4596), .CO(n5181), .S(n4915) );
INVX2TS U6386 ( .A(n3806), .Y(n4613) );
OAI22X1TS U6387 ( .A0(n4627), .A1(n4606), .B0(n4614), .B1(n4626), .Y(n4607)
);
NOR2X4TS U6388 ( .A(n5181), .B(n5182), .Y(n4857) );
ADDFHX4TS U6389 ( .A(n4609), .B(n4608), .CI(n4607), .CO(n5204), .S(n5182) );
INVX2TS U6390 ( .A(n4630), .Y(n4623) );
OAI22X1TS U6391 ( .A0(n4627), .A1(n4614), .B0(n2271), .B1(n4626), .Y(n4622)
);
NOR2X4TS U6392 ( .A(n5204), .B(n5203), .Y(n4665) );
NOR2X2TS U6393 ( .A(n4857), .B(n4665), .Y(n4618) );
NAND2X4TS U6394 ( .A(n4616), .B(n4615), .Y(n4748) );
NAND2X2TS U6395 ( .A(n4915), .B(n4914), .Y(n4694) );
OAI21X4TS U6396 ( .A0(n4693), .A1(n4748), .B0(n4694), .Y(n4854) );
NAND2X2TS U6397 ( .A(n5182), .B(n5181), .Y(n4858) );
OAI21X1TS U6398 ( .A0(n4665), .A1(n4858), .B0(n4666), .Y(n4617) );
AOI21X2TS U6399 ( .A0(n4854), .A1(n4618), .B0(n4617), .Y(n4619) );
OAI21X4TS U6400 ( .A0(n4621), .A1(n4620), .B0(n4619), .Y(n4640) );
INVX2TS U6401 ( .A(n4638), .Y(n4628) );
AOI21X2TS U6402 ( .A0(n4640), .A1(n3142), .B0(n4628), .Y(n4634) );
NOR2X2TS U6403 ( .A(n4633), .B(n2240), .Y(n5418) );
XOR2X2TS U6404 ( .A(n4634), .B(n5415), .Y(n4683) );
XNOR2X4TS U6405 ( .A(n3016), .B(n4637), .Y(n5137) );
XNOR2X2TS U6406 ( .A(n4640), .B(n4639), .Y(n4677) );
NAND2X4TS U6407 ( .A(n4642), .B(n4641), .Y(n4643) );
XNOR2X4TS U6408 ( .A(n4644), .B(n4643), .Y(n5136) );
XOR2X4TS U6409 ( .A(n4647), .B(n4646), .Y(n4650) );
ADDFHX4TS U6410 ( .A(n4651), .B(n4650), .CI(n4649), .CO(n4896), .S(n4894) );
INVX2TS U6411 ( .A(n4652), .Y(n4654) );
NAND2X2TS U6412 ( .A(n4654), .B(n4653), .Y(n4655) );
XOR2X4TS U6413 ( .A(n4656), .B(n4655), .Y(n4679) );
NAND2X4TS U6414 ( .A(n4658), .B(n4657), .Y(n4660) );
XNOR2X4TS U6415 ( .A(n4660), .B(n4659), .Y(n4888) );
INVX2TS U6416 ( .A(n4855), .Y(n4661) );
INVX2TS U6417 ( .A(n4854), .Y(n4662) );
INVX2TS U6418 ( .A(n4665), .Y(n4667) );
NAND2X2TS U6419 ( .A(n4673), .B(n4672), .Y(n4674) );
XOR2X4TS U6420 ( .A(n4670), .B(n4674), .Y(n7213) );
ADDFHX2TS U6421 ( .A(n4677), .B(n4676), .CI(n4675), .CO(n4681), .S(n4886) );
ADDFHX4TS U6422 ( .A(n4680), .B(n4679), .CI(n4678), .CO(n4895), .S(n4685) );
ADDFHX2TS U6423 ( .A(n4683), .B(n4682), .CI(n4681), .CO(n4651), .S(n4684) );
CLKXOR2X2TS U6424 ( .A(n4690), .B(n4689), .Y(n4867) );
INVX2TS U6425 ( .A(n4691), .Y(n4749) );
INVX2TS U6426 ( .A(n4748), .Y(n4692) );
INVX2TS U6427 ( .A(n4693), .Y(n4695) );
XNOR2X1TS U6428 ( .A(n4700), .B(n4699), .Y(n4747) );
AND2X4TS U6429 ( .A(n4708), .B(n4707), .Y(n7206) );
INVX2TS U6430 ( .A(n4709), .Y(n4711) );
NAND2X1TS U6431 ( .A(n4711), .B(n4710), .Y(n4713) );
INVX2TS U6432 ( .A(n7205), .Y(n4810) );
INVX2TS U6433 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n4809) );
INVX2TS U6434 ( .A(n4714), .Y(n4716) );
INVX2TS U6435 ( .A(n7204), .Y(n4770) );
INVX2TS U6436 ( .A(n4719), .Y(n4721) );
CLKXOR2X2TS U6437 ( .A(n4723), .B(n4722), .Y(n5002) );
NAND2X1TS U6438 ( .A(n3181), .B(n4724), .Y(n4725) );
XNOR2X1TS U6439 ( .A(n4726), .B(n4725), .Y(n7203) );
INVX2TS U6440 ( .A(n7203), .Y(n4778) );
XNOR2X2TS U6441 ( .A(n4729), .B(n4728), .Y(n5734) );
AND2X2TS U6442 ( .A(n4732), .B(n4744), .Y(n5731) );
INVX2TS U6443 ( .A(n5731), .Y(n4785) );
INVX2TS U6444 ( .A(n7211), .Y(n4784) );
OR2X2TS U6445 ( .A(n4785), .B(n4784), .Y(n4792) );
INVX2TS U6446 ( .A(n4736), .Y(n4738) );
NAND2X1TS U6447 ( .A(n4738), .B(n4737), .Y(n4740) );
INVX2TS U6448 ( .A(n7202), .Y(n4791) );
INVX2TS U6449 ( .A(n4741), .Y(n4743) );
CLKXOR2X2TS U6450 ( .A(n4745), .B(n4744), .Y(n5733) );
INVX2TS U6451 ( .A(n4761), .Y(n4752) );
XNOR2X2TS U6452 ( .A(n4759), .B(n3156), .Y(n4842) );
INVX2TS U6453 ( .A(n7208), .Y(n4841) );
INVX2TS U6454 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n4840) );
ADDFHX4TS U6455 ( .A(n4770), .B(n4769), .CI(n4768), .CO(n4808), .S(n4798) );
INVX2TS U6456 ( .A(n4771), .Y(n4773) );
ADDFHX4TS U6457 ( .A(n4778), .B(n4777), .CI(n4776), .CO(n4768), .S(n4796) );
NAND2X2TS U6458 ( .A(n5056), .B(n3155), .Y(n4802) );
XNOR2X1TS U6459 ( .A(n4785), .B(n4784), .Y(n4786) );
INVX2TS U6460 ( .A(n5133), .Y(n4787) );
NAND2X1TS U6461 ( .A(n4783), .B(n4786), .Y(n5131) );
XNOR2X1TS U6462 ( .A(n4789), .B(n4788), .Y(n4794) );
CMPR32X2TS U6463 ( .A(n4792), .B(n4791), .C(n4790), .CO(n4776), .S(n4793) );
NAND2X1TS U6464 ( .A(n4794), .B(n4793), .Y(n5139) );
INVX2TS U6465 ( .A(n5139), .Y(n4795) );
NAND2X2TS U6466 ( .A(n4797), .B(n4796), .Y(n5143) );
INVX2TS U6467 ( .A(n5055), .Y(n4800) );
AOI21X4TS U6468 ( .A0(n5056), .A1(n5054), .B0(n4800), .Y(n4801) );
OAI21X4TS U6469 ( .A0(n4802), .A1(n5053), .B0(n4801), .Y(n5006) );
ADDFHX4TS U6470 ( .A(n4810), .B(n4809), .CI(n4808), .CO(n4818), .S(n4812) );
INVX2TS U6471 ( .A(n5005), .Y(n4814) );
AOI21X4TS U6472 ( .A0(n5006), .A1(n4811), .B0(n4814), .Y(n5063) );
INVX2TS U6473 ( .A(n4827), .Y(n4815) );
NAND2X1TS U6474 ( .A(n4815), .B(n4826), .Y(n4817) );
INVX2TS U6475 ( .A(n4816), .Y(n4828) );
NAND2X2TS U6476 ( .A(n4822), .B(n4821), .Y(n5061) );
OAI21X4TS U6477 ( .A0(n5063), .A1(n5060), .B0(n5061), .Y(n5091) );
ADDFHX4TS U6478 ( .A(n4825), .B(n4824), .CI(n4823), .CO(n4838), .S(n4835) );
INVX2TS U6479 ( .A(n4829), .Y(n4831) );
NAND2X1TS U6480 ( .A(n4831), .B(n4830), .Y(n4832) );
OR2X4TS U6481 ( .A(n4835), .B(n4834), .Y(n5089) );
NAND2X2TS U6482 ( .A(n4835), .B(n4834), .Y(n5088) );
INVX2TS U6483 ( .A(n5088), .Y(n4836) );
XNOR2X2TS U6484 ( .A(n4849), .B(n4848), .Y(n4883) );
INVX4TS U6485 ( .A(n7212), .Y(n4871) );
INVX2TS U6486 ( .A(n4857), .Y(n4859) );
ADDFHX4TS U6487 ( .A(n4867), .B(n4866), .CI(n4865), .CO(n4868), .S(n4846) );
ADDFHX4TS U6488 ( .A(n4872), .B(n4871), .CI(n4870), .CO(n4891), .S(n4882) );
XOR2X4TS U6489 ( .A(n4877), .B(n4876), .Y(n4890) );
INVX2TS U6490 ( .A(n4901), .Y(n4903) );
ADDFHX4TS U6491 ( .A(n4908), .B(n4907), .CI(n4906), .CO(n4945), .S(n4133) );
INVX2TS U6492 ( .A(n4915), .Y(n5189) );
INVX2TS U6493 ( .A(n4916), .Y(n4917) );
OAI22X2TS U6494 ( .A0(n5169), .A1(n5416), .B0(n2231), .B1(n4918), .Y(n5166)
);
ADDFHX4TS U6495 ( .A(n4932), .B(n4931), .CI(n4930), .CO(n5604), .S(n5549) );
INVX2TS U6496 ( .A(n4938), .Y(n4939) );
XNOR2X4TS U6497 ( .A(n5211), .B(n4940), .Y(n5175) );
INVX2TS U6498 ( .A(n5605), .Y(n5183) );
ADDFHX4TS U6499 ( .A(n4944), .B(n4943), .CI(n4942), .CO(n5162), .S(n4907) );
XOR2X1TS U6500 ( .A(n4948), .B(n5273), .Y(n5302) );
OAI22X1TS U6501 ( .A0(n5031), .A1(n5029), .B0(n4954), .B1(n5070), .Y(n5038)
);
ADDFHX4TS U6502 ( .A(n4960), .B(n4959), .CI(n4958), .CO(n5024), .S(n4977) );
INVX2TS U6503 ( .A(n5476), .Y(n5028) );
INVX2TS U6504 ( .A(n4971), .Y(n5035) );
NOR2X2TS U6505 ( .A(n4973), .B(n4972), .Y(n5475) );
INVX2TS U6506 ( .A(n5475), .Y(n5034) );
INVX4TS U6507 ( .A(n4974), .Y(n5033) );
ADDFHX4TS U6508 ( .A(n4980), .B(n4979), .CI(n4978), .CO(n4982), .S(n4563) );
NAND2X4TS U6509 ( .A(n4982), .B(n4981), .Y(n5015) );
INVX2TS U6510 ( .A(n5047), .Y(n4986) );
NAND2X1TS U6511 ( .A(n4986), .B(n5046), .Y(n4990) );
INVX2TS U6512 ( .A(n4987), .Y(n4988) );
CLKXOR2X2TS U6513 ( .A(n4990), .B(n5048), .Y(n4991) );
XOR2X4TS U6514 ( .A(n4995), .B(n4994), .Y(n5059) );
INVX4TS U6515 ( .A(n5059), .Y(n5301) );
INVX4TS U6516 ( .A(n5672), .Y(n5000) );
NAND2X4TS U6517 ( .A(n5000), .B(n5670), .Y(n5001) );
XOR2X4TS U6518 ( .A(n5671), .B(n5001), .Y(n5003) );
NAND2X4TS U6519 ( .A(n5003), .B(n5002), .Y(add_x_69_n202) );
NAND2X4TS U6520 ( .A(n5004), .B(add_x_69_n202), .Y(add_x_69_n16) );
NAND2X1TS U6521 ( .A(n4811), .B(n5005), .Y(n5007) );
NOR2X4TS U6522 ( .A(n5008), .B(n5011), .Y(n5014) );
OAI21X4TS U6523 ( .A0(n5011), .A1(n5010), .B0(n5009), .Y(n5012) );
OAI2BB1X4TS U6524 ( .A0N(n2228), .A1N(n5066), .B0(n5016), .Y(n5042) );
ADDFHX4TS U6525 ( .A(n5019), .B(n5018), .CI(n5017), .CO(n5040), .S(n4981) );
ADDFHX4TS U6526 ( .A(n5025), .B(n5024), .CI(n5023), .CO(n5068), .S(n5018) );
ADDFX2TS U6527 ( .A(n5035), .B(n5034), .CI(n5033), .CO(n5072), .S(n5026) );
NAND2X4TS U6528 ( .A(n5040), .B(n5039), .Y(n5100) );
NAND2X4TS U6529 ( .A(n5065), .B(n5100), .Y(n5041) );
NOR2X2TS U6530 ( .A(n5043), .B(n5044), .Y(n5111) );
INVX2TS U6531 ( .A(n5111), .Y(n5045) );
NAND2X1TS U6532 ( .A(n5045), .B(n5113), .Y(n5049) );
OAI21X2TS U6533 ( .A0(n5048), .A1(n5047), .B0(n5046), .Y(n5116) );
INVX2TS U6534 ( .A(n5116), .Y(n5082) );
CLKXOR2X2TS U6535 ( .A(n5049), .B(n5082), .Y(n5050) );
INVX2TS U6536 ( .A(n5053), .Y(n5144) );
AOI21X1TS U6537 ( .A0(n5144), .A1(n3155), .B0(n5054), .Y(n5058) );
NAND2X1TS U6538 ( .A(n5056), .B(n5055), .Y(n5057) );
CLKXOR2X2TS U6539 ( .A(n5058), .B(n5057), .Y(n5150) );
INVX2TS U6540 ( .A(n5060), .Y(n5062) );
CLKXOR2X2TS U6541 ( .A(n5064), .B(n5063), .Y(n5126) );
INVX2TS U6542 ( .A(n5099), .Y(n5080) );
NOR2X2TS U6543 ( .A(n5084), .B(n5083), .Y(n5114) );
INVX2TS U6544 ( .A(n5114), .Y(n5085) );
NAND2X1TS U6545 ( .A(n5085), .B(n5112), .Y(n5086) );
XNOR2X2TS U6546 ( .A(n5091), .B(n5090), .Y(n5128) );
INVX4TS U6547 ( .A(n2264), .Y(n5096) );
OAI21X4TS U6548 ( .A0(n5096), .A1(n2823), .B0(n5095), .Y(n5125) );
NAND2X4TS U6549 ( .A(n2228), .B(n5102), .Y(n5106) );
AOI21X4TS U6550 ( .A0(n5103), .A1(n5102), .B0(n5101), .Y(n5104) );
OAI21X1TS U6551 ( .A0(n5114), .A1(n5113), .B0(n5112), .Y(n5115) );
AOI21X4TS U6552 ( .A0(n5117), .A1(n5116), .B0(n5115), .Y(n5510) );
NOR2X2TS U6553 ( .A(n5118), .B(n2269), .Y(n5385) );
INVX2TS U6554 ( .A(n5385), .Y(n5120) );
NAND2X2TS U6555 ( .A(n5364), .B(n5495), .Y(n5124) );
INVX2TS U6556 ( .A(n5130), .Y(n5132) );
NAND2X1TS U6557 ( .A(n5132), .B(n5131), .Y(n5134) );
XNOR2X1TS U6558 ( .A(n5134), .B(n5133), .Y(n5138) );
NOR2X2TS U6559 ( .A(n5138), .B(n5137), .Y(n7218) );
CMPR32X2TS U6560 ( .A(n3233), .B(n4194), .C(n5135), .CO(n5133), .S(n7214) );
NAND2X1TS U6561 ( .A(n3176), .B(n5139), .Y(n5140) );
NOR2X2TS U6562 ( .A(n5146), .B(n5142), .Y(n7229) );
NAND2X1TS U6563 ( .A(n3155), .B(n5143), .Y(n5145) );
NAND2X2TS U6564 ( .A(n5146), .B(n5142), .Y(n7228) );
AOI21X4TS U6565 ( .A0(n7224), .A1(n5148), .B0(n5147), .Y(n6210) );
NOR2X2TS U6566 ( .A(n5150), .B(n5149), .Y(n7237) );
NOR2X2TS U6567 ( .A(n5156), .B(n5157), .Y(n5399) );
INVX2TS U6568 ( .A(n5399), .Y(n5158) );
NAND2X1TS U6569 ( .A(n5158), .B(n5397), .Y(n5159) );
XNOR2X2TS U6570 ( .A(n5160), .B(n5159), .Y(n5395) );
OAI22X1TS U6571 ( .A0(n5221), .A1(n5416), .B0(n5169), .B1(n2231), .Y(n5225)
);
INVX2TS U6572 ( .A(n2285), .Y(n5174) );
OAI22X4TS U6573 ( .A0(n5175), .A1(n5210), .B0(n5209), .B1(n5212), .Y(n5263)
);
INVX2TS U6574 ( .A(n5263), .Y(n5201) );
INVX2TS U6575 ( .A(n5179), .Y(n5180) );
INVX2TS U6576 ( .A(n5634), .Y(n5220) );
INVX2TS U6577 ( .A(n5662), .Y(n5246) );
INVX2TS U6578 ( .A(n5633), .Y(n5245) );
INVX2TS U6579 ( .A(n5204), .Y(n5256) );
INVX2TS U6580 ( .A(n5205), .Y(n5206) );
NOR2X2TS U6581 ( .A(n5206), .B(n2354), .Y(n5260) );
OAI22X1TS U6582 ( .A0(n5261), .A1(n5416), .B0(n5221), .B1(n2231), .Y(n5250)
);
ADDFHX2TS U6583 ( .A(n5227), .B(n5226), .CI(n5225), .CO(n5248), .S(n5230) );
ADDFHX4TS U6584 ( .A(n5233), .B(n5232), .CI(n5231), .CO(n5237), .S(n5235) );
ADDFX2TS U6585 ( .A(n5244), .B(n5243), .CI(n5242), .CO(n5333), .S(n5269) );
OAI22X2TS U6586 ( .A0(n5251), .A1(n5338), .B0(n2376), .B1(n2511), .Y(n5349)
);
INVX2TS U6587 ( .A(n5252), .Y(n5253) );
NOR2X2TS U6588 ( .A(n5253), .B(n2354), .Y(n5348) );
INVX2TS U6589 ( .A(n5254), .Y(n5347) );
ADDFHX2TS U6590 ( .A(n5260), .B(n5259), .CI(n5258), .CO(n5344), .S(n5255) );
INVX2TS U6591 ( .A(n5266), .Y(n5339) );
ADDFHX4TS U6592 ( .A(n5269), .B(n5268), .CI(n5267), .CO(n5270), .S(n5236) );
OAI21X2TS U6593 ( .A0(n5274), .A1(n5273), .B0(n5272), .Y(n5298) );
INVX2TS U6594 ( .A(n5296), .Y(n5277) );
AOI21X2TS U6595 ( .A0(n5298), .A1(n5297), .B0(n5277), .Y(n5289) );
INVX2TS U6596 ( .A(n5288), .Y(n5280) );
XOR2X1TS U6597 ( .A(n5289), .B(n5281), .Y(n5305) );
AOI21X4TS U6598 ( .A0(n3135), .A1(n5282), .B0(n2742), .Y(n5286) );
INVX2TS U6599 ( .A(n5378), .Y(n5358) );
NOR2X2TS U6600 ( .A(n5291), .B(n5290), .Y(n5373) );
INVX2TS U6601 ( .A(n5373), .Y(n5292) );
NAND2X1TS U6602 ( .A(n5292), .B(n5375), .Y(n5293) );
XOR2X1TS U6603 ( .A(n5358), .B(n5293), .Y(n5357) );
XOR2X4TS U6604 ( .A(n5295), .B(n5294), .Y(n5308) );
NAND2X1TS U6605 ( .A(n5297), .B(n5296), .Y(n5299) );
XNOR2X1TS U6606 ( .A(n5299), .B(n5298), .Y(n5446) );
ADDFHX4TS U6607 ( .A(n5302), .B(n5301), .CI(n5300), .CO(n5445), .S(n5324) );
ADDFHX4TS U6608 ( .A(n5308), .B(n5307), .CI(n5306), .CO(n5326), .S(n5441) );
INVX2TS U6609 ( .A(n5312), .Y(n5314) );
XOR2X4TS U6610 ( .A(n5316), .B(n5315), .Y(n5721) );
INVX2TS U6611 ( .A(n5319), .Y(n5321) );
NAND2X4TS U6612 ( .A(n5321), .B(n5320), .Y(n5322) );
ADDFHX4TS U6613 ( .A(n5334), .B(n5333), .CI(n5332), .CO(n5354), .S(n5271) );
ADDFHX2TS U6614 ( .A(n5337), .B(n5336), .CI(n5335), .CO(n5412), .S(n5350) );
INVX2TS U6615 ( .A(n5340), .Y(n5341) );
ADDFHX2TS U6616 ( .A(n5344), .B(n5343), .CI(n5342), .CO(n5425), .S(n5335) );
ADDFHX2TS U6617 ( .A(n5352), .B(n5351), .CI(n5350), .CO(n5410), .S(n5332) );
ADDFHX4TS U6618 ( .A(n5357), .B(add_x_69_n69), .CI(n5356), .CO(n5433), .S(
n5370) );
INVX2TS U6619 ( .A(n5376), .Y(n5361) );
XNOR2X1TS U6620 ( .A(n5363), .B(n5362), .Y(n5408) );
NOR2X2TS U6621 ( .A(n5365), .B(n5366), .Y(n5388) );
INVX2TS U6622 ( .A(n5388), .Y(n5367) );
ADDFHX4TS U6623 ( .A(n5372), .B(n5371), .CI(n5370), .CO(n5436), .S(n5325) );
OAI21X1TS U6624 ( .A0(n5376), .A1(n5375), .B0(n5374), .Y(n5377) );
AOI21X4TS U6625 ( .A0(n5379), .A1(n5378), .B0(n5377), .Y(n5660) );
NOR2X2TS U6626 ( .A(n5380), .B(n5381), .Y(n5598) );
INVX2TS U6627 ( .A(n5598), .Y(n5382) );
XOR2X1TS U6628 ( .A(n5660), .B(n5383), .Y(n5562) );
NOR2X2TS U6629 ( .A(n5385), .B(n5388), .Y(n5501) );
INVX2TS U6630 ( .A(n5501), .Y(n5390) );
OAI21X2TS U6631 ( .A0(n5388), .A1(n5387), .B0(n5386), .Y(n5507) );
INVX2TS U6632 ( .A(n5507), .Y(n5389) );
OAI21X1TS U6633 ( .A0(n5510), .A1(n5390), .B0(n5389), .Y(n5394) );
NOR2X1TS U6634 ( .A(n5392), .B(n5391), .Y(n5500) );
INVX2TS U6635 ( .A(n5500), .Y(n5472) );
NAND2X1TS U6636 ( .A(n5392), .B(n5391), .Y(n5504) );
NAND2X1TS U6637 ( .A(n5472), .B(n5504), .Y(n5393) );
XNOR2X2TS U6638 ( .A(n5394), .B(n5393), .Y(n5465) );
INVX2TS U6639 ( .A(n5554), .Y(n5401) );
OAI21X2TS U6640 ( .A0(n5399), .A1(n5398), .B0(n5397), .Y(n5615) );
INVX2TS U6641 ( .A(n5615), .Y(n5400) );
OAI21X1TS U6642 ( .A0(n5618), .A1(n5401), .B0(n5400), .Y(n5405) );
NAND2X1TS U6643 ( .A(n5403), .B(n5402), .Y(n5612) );
NAND2X1TS U6644 ( .A(n5614), .B(n5612), .Y(n5404) );
ADDFHX4TS U6645 ( .A(n5408), .B(add_x_69_n59), .CI(n5407), .CO(n5589), .S(
n5432) );
OAI22X1TS U6646 ( .A0(n5417), .A1(n2231), .B0(n5416), .B1(n2354), .Y(n5579)
);
INVX2TS U6647 ( .A(n5418), .Y(n5576) );
NOR2X2TS U6648 ( .A(n5420), .B(n2354), .Y(n5574) );
CMPR32X2TS U6649 ( .A(n5423), .B(n5422), .C(n5421), .CO(n5577), .S(n5426) );
INVX2TS U6650 ( .A(n5565), .Y(n5429) );
XNOR2X4TS U6651 ( .A(n5431), .B(n5430), .Y(n5588) );
ADDFHX4TS U6652 ( .A(n5434), .B(n5433), .CI(n5432), .CO(n5438), .S(n5435) );
NAND2X4TS U6653 ( .A(n5438), .B(n5437), .Y(n5681) );
OAI21X4TS U6654 ( .A0(n5680), .A1(n5690), .B0(n5681), .Y(n5439) );
AOI21X4TS U6655 ( .A0(n5696), .A1(n5442), .B0(n5439), .Y(n5451) );
NOR2X2TS U6656 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n6651) );
NAND2X1TS U6657 ( .A(n2350), .B(n6358), .Y(n5453) );
NOR3X2TS U6658 ( .A(n7788), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[0]), .Y(n6614) );
INVX2TS U6659 ( .A(n5456), .Y(n5458) );
NAND2X2TS U6660 ( .A(n5458), .B(n5457), .Y(n5459) );
CLKXOR2X2TS U6661 ( .A(n5455), .B(n5459), .Y(n5482) );
NOR2X8TS U6662 ( .A(n5484), .B(n5483), .Y(n5518) );
NOR2X4TS U6663 ( .A(n5464), .B(n5494), .Y(n5468) );
NAND2X2TS U6664 ( .A(n2264), .B(n5468), .Y(n5470) );
AOI21X4TS U6665 ( .A0(n2667), .A1(n5468), .B0(n5467), .Y(n5469) );
OAI21X4TS U6666 ( .A0(n2829), .A1(n5470), .B0(n5469), .Y(n5480) );
NAND2X1TS U6667 ( .A(n5501), .B(n5472), .Y(n5474) );
INVX2TS U6668 ( .A(n5504), .Y(n5471) );
AOI21X1TS U6669 ( .A0(n5507), .A1(n5472), .B0(n5471), .Y(n5473) );
OAI21X1TS U6670 ( .A0(n5510), .A1(n5474), .B0(n5473), .Y(n5479) );
NOR2X2TS U6671 ( .A(n5476), .B(n5475), .Y(n5503) );
INVX2TS U6672 ( .A(n5503), .Y(n5477) );
NAND2X1TS U6673 ( .A(n5476), .B(n5475), .Y(n5502) );
NAND2X1TS U6674 ( .A(n5477), .B(n5502), .Y(n5478) );
XNOR2X4TS U6675 ( .A(n5480), .B(n3152), .Y(n5561) );
INVX4TS U6676 ( .A(n5531), .Y(n5526) );
NAND2X4TS U6677 ( .A(n5484), .B(n5483), .Y(n5519) );
NAND2X4TS U6678 ( .A(n5487), .B(n5486), .Y(n5534) );
INVX2TS U6679 ( .A(n5534), .Y(n5488) );
OAI21X4TS U6680 ( .A0(n6252), .A1(n5490), .B0(n5489), .Y(n5515) );
NAND2X2TS U6681 ( .A(n3190), .B(n5491), .Y(n5492) );
XNOR2X4TS U6682 ( .A(n5493), .B(n5492), .Y(n5512) );
NAND2X2TS U6683 ( .A(n2264), .B(n5497), .Y(n5499) );
NOR2X2TS U6684 ( .A(n5495), .B(n3153), .Y(n5496) );
AOI21X4TS U6685 ( .A0(n2667), .A1(n5497), .B0(n5496), .Y(n5498) );
OAI21X4TS U6686 ( .A0(n2829), .A1(n5499), .B0(n5498), .Y(n5511) );
NOR2X1TS U6687 ( .A(n5500), .B(n5503), .Y(n5506) );
NAND2X1TS U6688 ( .A(n5501), .B(n5506), .Y(n5509) );
AOI21X1TS U6689 ( .A0(n5507), .A1(n5506), .B0(n5505), .Y(n5508) );
XNOR2X4TS U6690 ( .A(n5511), .B(n3151), .Y(n5608) );
INVX2TS U6691 ( .A(n5535), .Y(n5513) );
NAND2X2TS U6692 ( .A(n5512), .B(n5608), .Y(n5533) );
XOR2X4TS U6693 ( .A(n5515), .B(n5514), .Y(n5517) );
OAI21X4TS U6694 ( .A0(n5517), .A1(n7253), .B0(n5516), .Y(n1576) );
OAI21X4TS U6695 ( .A0(n6252), .A1(n6248), .B0(n6249), .Y(n5522) );
INVX2TS U6696 ( .A(n5518), .Y(n5520) );
XOR2X4TS U6697 ( .A(n5522), .B(n5521), .Y(n5524) );
OAI21X4TS U6698 ( .A0(n5524), .A1(n6955), .B0(n5523), .Y(n1574) );
INVX2TS U6699 ( .A(n5532), .Y(n5525) );
OAI21X4TS U6700 ( .A0(n6252), .A1(n5525), .B0(n5485), .Y(n5528) );
XOR2X4TS U6701 ( .A(n5528), .B(n5527), .Y(n5530) );
OAI21X4TS U6702 ( .A0(n5530), .A1(n6955), .B0(n5529), .Y(n1575) );
NAND2X2TS U6703 ( .A(n5753), .B(n5751), .Y(n5542) );
XOR2X4TS U6704 ( .A(n5543), .B(n5542), .Y(n5545) );
OAI21X4TS U6705 ( .A0(n5545), .A1(n7253), .B0(n5544), .Y(n1577) );
OAI21X1TS U6706 ( .A0(n5660), .A1(n5598), .B0(n5600), .Y(n5552) );
NOR2X2TS U6707 ( .A(n5549), .B(n5548), .Y(n5601) );
INVX2TS U6708 ( .A(n5601), .Y(n5550) );
XNOR2X1TS U6709 ( .A(n5552), .B(n5551), .Y(n5597) );
INVX2TS U6710 ( .A(n5612), .Y(n5555) );
AOI21X1TS U6711 ( .A0(n5615), .A1(n5614), .B0(n5555), .Y(n5556) );
XNOR2X1TS U6712 ( .A(n5558), .B(n5557), .Y(n5609) );
INVX2TS U6713 ( .A(n5609), .Y(n5559) );
XOR2X4TS U6714 ( .A(n5560), .B(n5559), .Y(n5714) );
ADDFHX4TS U6715 ( .A(n5562), .B(n2286), .CI(n5712), .CO(n5623), .S(n5590) );
XOR2X4TS U6716 ( .A(n5620), .B(n5623), .Y(n5587) );
INVX2TS U6717 ( .A(n5570), .Y(n5571) );
XNOR2X1TS U6718 ( .A(n5573), .B(n5572), .Y(n5582) );
CMPR32X2TS U6719 ( .A(n5576), .B(n5575), .C(n5574), .CO(n5581), .S(n5578) );
XOR2X4TS U6720 ( .A(n5586), .B(n5585), .Y(n5622) );
XOR2X4TS U6721 ( .A(n5587), .B(n5622), .Y(n5643) );
ADDFHX4TS U6722 ( .A(n5589), .B(n5590), .CI(n5588), .CO(n5644), .S(n5437) );
ADDFHX4TS U6723 ( .A(n5597), .B(n5596), .CI(n5595), .CO(n5627), .S(n5620) );
NOR2X2TS U6724 ( .A(n5598), .B(n5601), .Y(n5651) );
INVX2TS U6725 ( .A(n5651), .Y(n5603) );
OAI21X2TS U6726 ( .A0(n5601), .A1(n5600), .B0(n5599), .Y(n5657) );
INVX2TS U6727 ( .A(n5657), .Y(n5602) );
OAI21X1TS U6728 ( .A0(n5660), .A1(n5603), .B0(n5602), .Y(n5607) );
INVX2TS U6729 ( .A(n5650), .Y(n5630) );
NAND2X1TS U6730 ( .A(n5612), .B(n5611), .Y(n5613) );
AOI21X1TS U6731 ( .A0(n5615), .A1(n5614), .B0(n5613), .Y(n5616) );
OAI21X2TS U6732 ( .A0(n5622), .A1(n5623), .B0(n5620), .Y(n5621) );
OAI2BB1X4TS U6733 ( .A0N(n5623), .A1N(n5622), .B0(n5621), .Y(n5625) );
NAND2X4TS U6734 ( .A(n5625), .B(n5624), .Y(n5692) );
NAND2X1TS U6735 ( .A(n5651), .B(n5630), .Y(n5632) );
INVX2TS U6736 ( .A(n5653), .Y(n5629) );
AOI21X1TS U6737 ( .A0(n5657), .A1(n5630), .B0(n5629), .Y(n5631) );
NOR2X2TS U6738 ( .A(n5634), .B(n5633), .Y(n5654) );
INVX2TS U6739 ( .A(n5654), .Y(n5635) );
INVX4TS U6740 ( .A(n5646), .Y(n5700) );
ADDHX2TS U6741 ( .A(n5649), .B(n5648), .CO(n5667), .S(n5640) );
NOR2X1TS U6742 ( .A(n5650), .B(n5654), .Y(n5656) );
NAND2X1TS U6743 ( .A(n5651), .B(n5656), .Y(n5659) );
AOI21X1TS U6744 ( .A0(n5657), .A1(n5656), .B0(n5655), .Y(n5658) );
NAND2X1TS U6745 ( .A(n5662), .B(n5661), .Y(n5663) );
NAND2X1TS U6746 ( .A(n5664), .B(n5663), .Y(n5665) );
OAI21X4TS U6747 ( .A0(n5672), .A1(n5671), .B0(n5670), .Y(n5678) );
BUFX3TS U6748 ( .A(n5673), .Y(n5674) );
INVX4TS U6749 ( .A(n5674), .Y(n5676) );
NAND2X4TS U6750 ( .A(n5676), .B(n5675), .Y(n5677) );
XNOR2X4TS U6751 ( .A(n5678), .B(n5677), .Y(
FPMULT_Sgf_operation_EVEN1_S_B[17]) );
INVX4TS U6752 ( .A(n3069), .Y(n5682) );
NAND2X4TS U6753 ( .A(n5682), .B(n5681), .Y(n5683) );
XOR2X4TS U6754 ( .A(n5684), .B(n5683), .Y(FPMULT_Sgf_operation_EVEN1_S_B[21]) );
AOI21X4TS U6755 ( .A0(n2267), .A1(n2522), .B0(n5685), .Y(n5688) );
XOR2X4TS U6756 ( .A(n5688), .B(n5687), .Y(FPMULT_Sgf_operation_EVEN1_S_B[19]) );
NAND2X4TS U6757 ( .A(n5693), .B(n5692), .Y(DP_OP_499J211_125_1651_n5) );
INVX2TS U6758 ( .A(n1659), .Y(n7690) );
INVX2TS U6759 ( .A(n1665), .Y(n7689) );
CLKMX2X2TS U6760 ( .A(Data_1[7]), .B(DP_OP_496J211_122_3540_n1513), .S0(
n2357), .Y(n1666) );
CLKMX2X2TS U6761 ( .A(Data_1[1]), .B(n8488), .S0(n2355), .Y(n1660) );
NOR2X1TS U6762 ( .A(n1666), .B(n1660), .Y(n5703) );
NAND2X1TS U6763 ( .A(n1666), .B(n1660), .Y(n5704) );
INVX2TS U6764 ( .A(n1631), .Y(n7696) );
INVX2TS U6765 ( .A(n1637), .Y(n7687) );
INVX2TS U6766 ( .A(Data_2[3]), .Y(n5701) );
INVX2TS U6767 ( .A(n5702), .Y(n1630) );
INVX2TS U6768 ( .A(n5703), .Y(n5705) );
NAND2X1TS U6769 ( .A(n5705), .B(n5704), .Y(n7697) );
ADDHXLTS U6770 ( .A(n1678), .B(n1646), .CO(n7702), .S(n7703) );
INVX2TS U6771 ( .A(n1671), .Y(n7704) );
INVX2TS U6772 ( .A(n1676), .Y(n7707) );
NAND2X1TS U6773 ( .A(n1645), .B(n1639), .Y(n7705) );
NAND2X1TS U6774 ( .A(n1642), .B(n1630), .Y(n7722) );
NAND2X1TS U6775 ( .A(n1639), .B(n1627), .Y(n7713) );
NOR2X1TS U6776 ( .A(DP_OP_497J211_123_1725_n779), .B(n1628), .Y(n5709) );
NAND2X1TS U6777 ( .A(DP_OP_497J211_123_1725_n779), .B(n1628), .Y(n5710) );
INVX2TS U6778 ( .A(n1677), .Y(n7710) );
CLKBUFX3TS U6779 ( .A(n2367), .Y(n7993) );
CLKBUFX3TS U6780 ( .A(n8598), .Y(n7726) );
INVX2TS U6781 ( .A(n5709), .Y(n5711) );
NAND2X1TS U6782 ( .A(n5711), .B(n5710), .Y(n7720) );
NAND2X1TS U6783 ( .A(n1672), .B(n1660), .Y(n7725) );
NAND2X1TS U6784 ( .A(n1673), .B(n1661), .Y(n7724) );
NAND2X1TS U6785 ( .A(n1643), .B(n1631), .Y(n7711) );
NAND2X1TS U6786 ( .A(n1674), .B(n1662), .Y(n7723) );
NAND2X1TS U6787 ( .A(n1641), .B(n1629), .Y(n7712) );
INVX2TS U6788 ( .A(rst), .Y(n8635) );
CLKINVX1TS U6789 ( .A(n5712), .Y(n5713) );
INVX2TS U6790 ( .A(n5713), .Y(add_x_69_n51) );
INVX2TS U6791 ( .A(n5724), .Y(add_x_69_n47) );
NAND2X1TS U6792 ( .A(n5720), .B(n5721), .Y(n5722) );
BUFX3TS U6793 ( .A(n8593), .Y(n7779) );
CLKBUFX3TS U6794 ( .A(n2426), .Y(n7777) );
CLKBUFX3TS U6795 ( .A(n8562), .Y(n7778) );
NOR2X8TS U6796 ( .A(n5730), .B(n5757), .Y(n5739) );
OAI21X4TS U6797 ( .A0(n6252), .A1(n5745), .B0(n5744), .Y(n5749) );
XNOR2X4TS U6798 ( .A(n5749), .B(n5748), .Y(FPMULT_Sgf_operation_Result[26])
);
NAND2X2TS U6799 ( .A(n5750), .B(n5753), .Y(n5756) );
INVX2TS U6800 ( .A(n5751), .Y(n5752) );
INVX2TS U6801 ( .A(n5757), .Y(n5758) );
AOI22X1TS U6802 ( .A0(n8074), .A1(n8185), .B0(n5998), .B1(n8184), .Y(n5764)
);
BUFX3TS U6803 ( .A(n2256), .Y(n6005) );
NAND2X1TS U6804 ( .A(n6263), .B(n6620), .Y(n5766) );
BUFX3TS U6805 ( .A(n6449), .Y(n6335) );
OAI2BB1X1TS U6806 ( .A0N(n2198), .A1N(n5770), .B0(n8426), .Y(n6880) );
BUFX3TS U6807 ( .A(n5774), .Y(n6540) );
INVX2TS U6808 ( .A(n6507), .Y(n6440) );
AOI22X1TS U6809 ( .A0(n2380), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n6440), .Y(n5771) );
OAI2BB1X1TS U6810 ( .A0N(n2445), .A1N(n6880), .B0(n5771), .Y(n5772) );
AOI21X1TS U6811 ( .A0(n2411), .A1(FPMULT_Add_result[4]), .B0(n5772), .Y(
n5773) );
OAI2BB1X1TS U6812 ( .A0N(n2416), .A1N(n1580), .B0(n5773), .Y(n1521) );
AOI22X1TS U6813 ( .A0(n6540), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n6539), .Y(n5775) );
OAI2BB1X1TS U6814 ( .A0N(n2444), .A1N(n1580), .B0(n5775), .Y(n5776) );
AOI21X1TS U6815 ( .A0(n2410), .A1(FPMULT_Add_result[3]), .B0(n5776), .Y(
n5777) );
OAI2BB1X1TS U6816 ( .A0N(n2415), .A1N(n1579), .B0(n5777), .Y(add_x_246_A_3_)
);
AOI22X1TS U6817 ( .A0(n2380), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n6907), .Y(n5778) );
OAI2BB1X1TS U6818 ( .A0N(n2446), .A1N(n1579), .B0(n5778), .Y(n5779) );
AOI21X1TS U6819 ( .A0(n2410), .A1(FPMULT_Add_result[2]), .B0(n5779), .Y(
n5780) );
OAI2BB1X1TS U6820 ( .A0N(n2415), .A1N(n1578), .B0(n5780), .Y(n1519) );
AOI22X1TS U6821 ( .A0(n5774), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n6440), .Y(n5781) );
OAI2BB1X1TS U6822 ( .A0N(n2445), .A1N(n1578), .B0(n5781), .Y(n5782) );
AOI21X1TS U6823 ( .A0(n2410), .A1(FPMULT_Add_result[1]), .B0(n5782), .Y(
n5783) );
OAI2BB1X1TS U6824 ( .A0N(n2415), .A1N(FPMULT_P_Sgf[24]), .B0(n5783), .Y(
n1518) );
AOI22X1TS U6825 ( .A0(n2380), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n6539), .Y(n5784) );
OAI2BB1X1TS U6826 ( .A0N(n2444), .A1N(FPMULT_P_Sgf[24]), .B0(n5784), .Y(
n5785) );
AOI21X1TS U6827 ( .A0(n2410), .A1(FPMULT_Add_result[0]), .B0(n5785), .Y(
n5786) );
OAI2BB1X1TS U6828 ( .A0N(FPMULT_P_Sgf[23]), .A1N(n2415), .B0(n5786), .Y(
n1517) );
XNOR2X1TS U6829 ( .A(n1521), .B(n5795), .Y(n7785) );
NAND2X1TS U6830 ( .A(n7750), .B(n7751), .Y(n6192) );
NAND2X1TS U6831 ( .A(n7757), .B(n6192), .Y(n5788) );
XNOR2X1TS U6832 ( .A(n5789), .B(n5788), .Y(n5790) );
NAND2X1TS U6833 ( .A(n5790), .B(n8413), .Y(n5791) );
OAI2BB1X1TS U6834 ( .A0N(n8057), .A1N(n8416), .B0(n5791), .Y(n1582) );
INVX2TS U6835 ( .A(n6507), .Y(n6539) );
AOI22X1TS U6836 ( .A0(n6540), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n6907), .Y(n5792) );
OAI2BB1X1TS U6837 ( .A0N(n2446), .A1N(n1582), .B0(n5792), .Y(n5793) );
AOI21X1TS U6838 ( .A0(n6544), .A1(FPMULT_Add_result[5]), .B0(n5793), .Y(
n5794) );
OAI2BB1X1TS U6839 ( .A0N(n5768), .A1N(n6880), .B0(n5794), .Y(add_x_246_A_5_)
);
NOR4X1TS U6840 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[16]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[14]), .Y(n5806) );
NOR4X1TS U6841 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n5805) );
NOR4X1TS U6842 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n5801) );
NOR3XLTS U6843 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[1]), .C(
FPMULT_P_Sgf[0]), .Y(n5800) );
AND4X1TS U6844 ( .A(n5801), .B(n5800), .C(n5799), .D(n5798), .Y(n5804) );
XOR2X1TS U6845 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n7491) );
MXI2X1TS U6846 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n7491), .Y(n5802) );
AOI31X1TS U6847 ( .A0(n5806), .A1(n5805), .A2(n5804), .B0(n5803), .Y(n6261)
);
OAI221XLTS U6848 ( .A0(n2350), .A1(FPMULT_FS_Module_state_reg[0]), .B0(n3146), .B1(n7794), .C0(n7788), .Y(n5808) );
NAND2X1TS U6849 ( .A(n3146), .B(n5807), .Y(n6649) );
NOR4X1TS U6850 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n5811) );
NOR4X1TS U6851 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n5810) );
NOR4X1TS U6852 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n5809) );
NOR4X1TS U6853 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n5812),
.Y(n8061) );
AOI21X1TS U6854 ( .A0(operation[1]), .A1(ack_operation), .B0(n6718), .Y(
n7281) );
NAND2X1TS U6855 ( .A(n5814), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n5816) );
NOR2X2TS U6856 ( .A(n7790), .B(intadd_479_B_1_), .Y(n6632) );
BUFX3TS U6857 ( .A(n6424), .Y(n6599) );
NAND2X1TS U6858 ( .A(n7943), .B(n7805), .Y(n7167) );
NOR2X1TS U6859 ( .A(n7951), .B(FPADDSUB_DMP_SFG[0]), .Y(n5818) );
NAND2X1TS U6860 ( .A(n7951), .B(FPADDSUB_DMP_SFG[0]), .Y(n5817) );
OAI21X1TS U6861 ( .A0(n7167), .A1(n5818), .B0(n5817), .Y(n6375) );
NOR2X1TS U6862 ( .A(n7950), .B(FPADDSUB_DMP_SFG[1]), .Y(n6377) );
NOR2X1TS U6863 ( .A(n7949), .B(FPADDSUB_DMP_SFG[2]), .Y(n5820) );
NAND2X1TS U6864 ( .A(n7950), .B(FPADDSUB_DMP_SFG[1]), .Y(n6376) );
NAND2X1TS U6865 ( .A(n7949), .B(FPADDSUB_DMP_SFG[2]), .Y(n5819) );
AOI21X1TS U6866 ( .A0(n6375), .A1(n5822), .B0(n5821), .Y(n6359) );
NOR2X1TS U6867 ( .A(n7948), .B(FPADDSUB_DMP_SFG[3]), .Y(n6386) );
NOR2X1TS U6868 ( .A(n7947), .B(FPADDSUB_DMP_SFG[4]), .Y(n5824) );
NOR2X1TS U6869 ( .A(n6386), .B(n5824), .Y(n6361) );
NOR2X1TS U6870 ( .A(n7942), .B(FPADDSUB_DMP_SFG[5]), .Y(n6363) );
NOR2X1TS U6871 ( .A(n7946), .B(FPADDSUB_DMP_SFG[6]), .Y(n5826) );
NOR2X1TS U6872 ( .A(n6363), .B(n5826), .Y(n5828) );
NAND2X1TS U6873 ( .A(n6361), .B(n5828), .Y(n5830) );
NAND2X1TS U6874 ( .A(n7948), .B(FPADDSUB_DMP_SFG[3]), .Y(n6387) );
NAND2X1TS U6875 ( .A(n7947), .B(FPADDSUB_DMP_SFG[4]), .Y(n5823) );
OAI21X1TS U6876 ( .A0(n5824), .A1(n6387), .B0(n5823), .Y(n6360) );
NAND2X1TS U6877 ( .A(n7942), .B(FPADDSUB_DMP_SFG[5]), .Y(n6362) );
NAND2X1TS U6878 ( .A(n7946), .B(FPADDSUB_DMP_SFG[6]), .Y(n5825) );
AOI21X1TS U6879 ( .A0(n6360), .A1(n5828), .B0(n5827), .Y(n5829) );
OAI21X1TS U6880 ( .A0(n6359), .A1(n5830), .B0(n5829), .Y(n7125) );
NOR2X1TS U6881 ( .A(n7945), .B(FPADDSUB_DMP_SFG[7]), .Y(n7143) );
NOR2X1TS U6882 ( .A(n7944), .B(FPADDSUB_DMP_SFG[8]), .Y(n5832) );
NOR2X1TS U6883 ( .A(n7143), .B(n5832), .Y(n7126) );
NAND2X1TS U6884 ( .A(n7126), .B(n3194), .Y(n7172) );
NOR2X1TS U6885 ( .A(n7914), .B(n2466), .Y(n5835) );
NOR2X1TS U6886 ( .A(n7172), .B(n5835), .Y(n5837) );
NAND2X1TS U6887 ( .A(n7945), .B(FPADDSUB_DMP_SFG[7]), .Y(n7142) );
NAND2X1TS U6888 ( .A(n7944), .B(FPADDSUB_DMP_SFG[8]), .Y(n5831) );
OAI21X1TS U6889 ( .A0(n5832), .A1(n7142), .B0(n5831), .Y(n7127) );
AOI21X1TS U6890 ( .A0(n7127), .A1(n3194), .B0(n5833), .Y(n7171) );
NAND2X1TS U6891 ( .A(n7914), .B(FPADDSUB_DMP_SFG[10]), .Y(n5834) );
OAI21X1TS U6892 ( .A0(n7171), .A1(n5835), .B0(n5834), .Y(n5836) );
AOI21X2TS U6893 ( .A0(n7125), .A1(n5837), .B0(n5836), .Y(n7119) );
NOR2X1TS U6894 ( .A(n7866), .B(FPADDSUB_DMP_SFG[11]), .Y(n5839) );
NAND2X1TS U6895 ( .A(n7866), .B(FPADDSUB_DMP_SFG[11]), .Y(n5838) );
OAI21X4TS U6896 ( .A0(n7119), .A1(n5839), .B0(n5838), .Y(n7109) );
AOI21X4TS U6897 ( .A0(n7109), .A1(n5841), .B0(n5840), .Y(n6593) );
NAND2X1TS U6898 ( .A(n7865), .B(n2488), .Y(n5842) );
OAI21X4TS U6899 ( .A0(n6593), .A1(n5843), .B0(n5842), .Y(n5862) );
NAND2X1TS U6900 ( .A(n5867), .B(n5865), .Y(n5856) );
INVX2TS U6901 ( .A(n5856), .Y(n5844) );
XNOR2X1TS U6902 ( .A(n5862), .B(n5844), .Y(n5859) );
NOR2X1TS U6903 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n7153) );
NAND2X1TS U6904 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n7165) );
NAND2X1TS U6905 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n7154) );
NOR2X2TS U6906 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6403) );
NOR2X2TS U6907 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6397) );
NAND2X1TS U6908 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6402) );
NAND2X1TS U6909 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6398) );
AOI21X1TS U6910 ( .A0(n6381), .A1(n5846), .B0(n5845), .Y(n6367) );
NOR2X1TS U6911 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6390) );
NOR2X2TS U6912 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6410) );
NOR2X1TS U6913 ( .A(n6390), .B(n6410), .Y(n6369) );
NOR2X2TS U6914 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n7192) );
NOR2X2TS U6915 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n7186) );
NOR2X1TS U6916 ( .A(n7192), .B(n7186), .Y(n5848) );
NAND2X1TS U6917 ( .A(n6369), .B(n5848), .Y(n5850) );
NAND2X1TS U6918 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6415) );
NAND2X1TS U6919 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6411) );
OAI21X1TS U6920 ( .A0(n6410), .A1(n6415), .B0(n6411), .Y(n6368) );
NAND2X1TS U6921 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n7191) );
NAND2X1TS U6922 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n7187) );
AOI21X1TS U6923 ( .A0(n6368), .A1(n5848), .B0(n5847), .Y(n5849) );
OAI21X2TS U6924 ( .A0(n6367), .A1(n5850), .B0(n5849), .Y(n7134) );
NOR2X1TS U6925 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n7135) );
INVX2TS U6926 ( .A(n7135), .Y(n7145) );
NAND2X1TS U6927 ( .A(n7145), .B(n7131), .Y(n7179) );
NOR2X2TS U6928 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n7173) );
NOR2X1TS U6929 ( .A(n7179), .B(n7173), .Y(n5854) );
NAND2X1TS U6930 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n7144) );
INVX2TS U6931 ( .A(n7144), .Y(n5852) );
NAND2X1TS U6932 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n7130) );
INVX2TS U6933 ( .A(n7130), .Y(n5851) );
AOI21X1TS U6934 ( .A0(n7131), .A1(n5852), .B0(n5851), .Y(n7178) );
NAND2X1TS U6935 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n7174) );
OAI21X1TS U6936 ( .A0(n7178), .A1(n7173), .B0(n7174), .Y(n5853) );
AOI21X4TS U6937 ( .A0(n7134), .A1(n5854), .B0(n5853), .Y(n7121) );
NOR2X1TS U6938 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n7115) );
NAND2X1TS U6939 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n7106) );
INVX2TS U6940 ( .A(n7106), .Y(n5855) );
AOI21X4TS U6941 ( .A0(n7111), .A1(n7107), .B0(n5855), .Y(n6595) );
XNOR2X1TS U6942 ( .A(n5868), .B(n5856), .Y(n5857) );
BUFX3TS U6943 ( .A(n7088), .Y(n7599) );
AOI22X1TS U6944 ( .A0(n5857), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n7599), .Y(n5858) );
OAI2BB1X1TS U6945 ( .A0N(n6599), .A1N(n5859), .B0(n5858), .Y(n1335) );
OR2X1TS U6946 ( .A(n7872), .B(n2481), .Y(n5861) );
AOI21X4TS U6947 ( .A0(n5862), .A1(n5861), .B0(n5860), .Y(n6074) );
NOR2X1TS U6948 ( .A(n2487), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6091) );
NAND2X1TS U6949 ( .A(n5863), .B(n6090), .Y(n5869) );
INVX2TS U6950 ( .A(n5869), .Y(n5864) );
INVX2TS U6951 ( .A(n5865), .Y(n5866) );
AOI21X4TS U6952 ( .A0(n5868), .A1(n5867), .B0(n5866), .Y(n6092) );
XOR2X1TS U6953 ( .A(n6092), .B(n5869), .Y(n5870) );
AOI22X1TS U6954 ( .A0(n5870), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n7599), .Y(n5871) );
OAI2BB1X1TS U6955 ( .A0N(n6599), .A1N(n5872), .B0(n5871), .Y(n1334) );
INVX2TS U6956 ( .A(n7571), .Y(n5878) );
AOI22X1TS U6957 ( .A0(n5904), .A1(n8241), .B0(n6005), .B1(n8240), .Y(n5875)
);
AOI22X1TS U6958 ( .A0(n7397), .A1(n5878), .B0(n7395), .B1(n5877), .Y(n5887)
);
AOI22X1TS U6959 ( .A0(n5904), .A1(n8209), .B0(n6872), .B1(n8208), .Y(n5879)
);
INVX2TS U6960 ( .A(n7580), .Y(n5884) );
AOI22X1TS U6961 ( .A0(n8076), .A1(n8217), .B0(n6872), .B1(n8216), .Y(n5881)
);
NAND3X2TS U6962 ( .A(n8407), .B(n5882), .C(n5892), .Y(n7569) );
OAI21X1TS U6963 ( .A0(n7398), .A1(n5884), .B0(n5883), .Y(n6033) );
OAI211X1TS U6964 ( .A0(n5887), .A1(n6033), .B0(n5886), .C0(n5885), .Y(n5902)
);
AOI22X1TS U6965 ( .A0(n7447), .A1(n8157), .B0(n2208), .B1(n8156), .Y(n5888)
);
NAND3X2TS U6966 ( .A(n8409), .B(n5888), .C(n5892), .Y(n7570) );
AOI22X1TS U6967 ( .A0(n8076), .A1(n8277), .B0(n6872), .B1(n8276), .Y(n5889)
);
INVX2TS U6968 ( .A(n7400), .Y(n5896) );
AOI22X1TS U6969 ( .A0(n7447), .A1(n8161), .B0(n8017), .B1(n8160), .Y(n5890)
);
NAND2X2TS U6970 ( .A(n8294), .B(n5890), .Y(n7568) );
INVX2TS U6971 ( .A(n7568), .Y(n5899) );
BUFX3TS U6972 ( .A(n8077), .Y(n6873) );
AOI22X1TS U6973 ( .A0(n6873), .A1(n8251), .B0(n6872), .B1(n8250), .Y(n5891)
);
AOI22X1TS U6974 ( .A0(n7447), .A1(n8155), .B0(n2208), .B1(n8154), .Y(n5893)
);
NAND3X2TS U6975 ( .A(n8411), .B(n5893), .C(n5892), .Y(n7567) );
INVX2TS U6976 ( .A(n7567), .Y(n5898) );
AOI22X1TS U6977 ( .A0(n8076), .A1(n8225), .B0(n6872), .B1(n8224), .Y(n5894)
);
AOI211X2TS U6978 ( .A0(n7570), .A1(n5896), .B0(n5900), .C0(n5895), .Y(n6031)
);
NOR3X1TS U6979 ( .A(n5896), .B(n5895), .C(n7570), .Y(n5897) );
AOI221X1TS U6980 ( .A0(n7403), .A1(n5899), .B0(n7401), .B1(n5898), .C0(n5897), .Y(n5901) );
AOI22X1TS U6981 ( .A0(n5986), .A1(n8245), .B0(n2207), .B1(n8244), .Y(n5903)
);
NAND3X2TS U6982 ( .A(n8412), .B(n5903), .C(n5992), .Y(n7652) );
INVX2TS U6983 ( .A(n7652), .Y(n6016) );
AOI22X1TS U6984 ( .A0(n2251), .A1(n8261), .B0(n6005), .B1(n8260), .Y(n5905)
);
BUFX3TS U6985 ( .A(n8075), .Y(n5935) );
BUFX3TS U6986 ( .A(n2256), .Y(n5989) );
AOI22X1TS U6987 ( .A0(n5935), .A1(n8195), .B0(n5989), .B1(n8194), .Y(n5906)
);
AOI22X1TS U6988 ( .A0(n5986), .A1(n8205), .B0(n5998), .B1(n8204), .Y(n5907)
);
OAI211X4TS U6989 ( .A0(n2259), .A1(n8380), .B0(n8379), .C0(n5907), .Y(n7583)
);
INVX2TS U6990 ( .A(n7583), .Y(n5970) );
AOI22X1TS U6991 ( .A0(n5935), .A1(n8201), .B0(n5989), .B1(n8200), .Y(n5908)
);
AOI22X1TS U6992 ( .A0(n5986), .A1(n8223), .B0(n5998), .B1(n8222), .Y(n5909)
);
AOI22X1TS U6993 ( .A0(n5986), .A1(n8215), .B0(n5998), .B1(n8214), .Y(n5910)
);
OAI211X4TS U6994 ( .A0(n2201), .A1(n8386), .B0(n8385), .C0(n5910), .Y(n7566)
);
AOI22X1TS U6995 ( .A0(n2251), .A1(n8275), .B0(n5989), .B1(n8274), .Y(n5911)
);
AOI22X1TS U6996 ( .A0(n5986), .A1(n8271), .B0(n2207), .B1(n8270), .Y(n5912)
);
NAND2X1TS U6997 ( .A(n2256), .B(n8148), .Y(n5922) );
NAND3X2TS U6998 ( .A(n8303), .B(n5912), .C(n5922), .Y(n7565) );
INVX2TS U6999 ( .A(n7565), .Y(n5968) );
AOI22X1TS U7000 ( .A0(n2251), .A1(n8213), .B0(n5989), .B1(n8212), .Y(n5913)
);
OAI211X4TS U7001 ( .A0(n2204), .A1(n8382), .B0(n8381), .C0(n5913), .Y(n7380)
);
AOI21X1TS U7002 ( .A0(n7566), .A1(n5914), .B0(n5966), .Y(n5973) );
AOI22X1TS U7003 ( .A0(n6873), .A1(n8211), .B0(n6872), .B1(n8210), .Y(n5915)
);
AOI22X1TS U7004 ( .A0(n5935), .A1(n8199), .B0(n5989), .B1(n8198), .Y(n5916)
);
INVX2TS U7005 ( .A(n7375), .Y(n5942) );
AOI22X1TS U7006 ( .A0(n6873), .A1(n8281), .B0(n2208), .B1(n8280), .Y(n5917)
);
NAND2X1TS U7007 ( .A(n5934), .B(n8150), .Y(n5954) );
NAND3X2TS U7008 ( .A(n8306), .B(n5917), .C(n5954), .Y(n7581) );
AOI22X1TS U7009 ( .A0(n5935), .A1(n8193), .B0(n5934), .B1(n8192), .Y(n5918)
);
OAI2BB1X1TS U7010 ( .A0N(n5942), .A1N(n7581), .B0(n7373), .Y(n5919) );
OAI22X1TS U7011 ( .A0(n7582), .A1(n5919), .B0(n5942), .B1(n7581), .Y(n5951)
);
AOI22X1TS U7012 ( .A0(n6873), .A1(n8203), .B0(n5998), .B1(n8202), .Y(n5920)
);
AOI22X1TS U7013 ( .A0(n5935), .A1(n8197), .B0(n5989), .B1(n8196), .Y(n5921)
);
INVX2TS U7014 ( .A(n7614), .Y(n5947) );
AOI22X1TS U7015 ( .A0(n6873), .A1(n8273), .B0(n2207), .B1(n8272), .Y(n5923)
);
NAND3X2TS U7016 ( .A(n8304), .B(n5923), .C(n5922), .Y(n6867) );
AOI22X1TS U7017 ( .A0(n5935), .A1(n8179), .B0(n5934), .B1(n8178), .Y(n5924)
);
OAI2BB1X1TS U7018 ( .A0N(n5947), .A1N(n6867), .B0(n7376), .Y(n5925) );
OAI22X1TS U7019 ( .A0(n7584), .A1(n5925), .B0(n5947), .B1(n6867), .Y(n5950)
);
INVX2TS U7020 ( .A(n7373), .Y(n5945) );
AOI22X1TS U7021 ( .A0(n6873), .A1(n8263), .B0(n2247), .B1(n8262), .Y(n5926)
);
NAND2X1TS U7022 ( .A(n5934), .B(n8149), .Y(n5987) );
NAND3X2TS U7023 ( .A(n8301), .B(n5926), .C(n5987), .Y(n7608) );
INVX2TS U7024 ( .A(n7608), .Y(n5941) );
AOI22X1TS U7025 ( .A0(n5935), .A1(n8183), .B0(n5934), .B1(n8182), .Y(n5927)
);
OAI211X4TS U7026 ( .A0(n2260), .A1(n8326), .B0(n8325), .C0(n5927), .Y(n7371)
);
AOI22X1TS U7027 ( .A0(n6873), .A1(n8227), .B0(n6872), .B1(n8226), .Y(n5928)
);
OAI211X4TS U7028 ( .A0(n2201), .A1(n8394), .B0(n8393), .C0(n5928), .Y(n7617)
);
AOI22X1TS U7029 ( .A0(n5935), .A1(n8189), .B0(n5934), .B1(n8188), .Y(n5929)
);
AOI22X1TS U7030 ( .A0(n6873), .A1(n8235), .B0(n6872), .B1(n8234), .Y(n5930)
);
OAI211X4TS U7031 ( .A0(n2260), .A1(n8396), .B0(n8395), .C0(n5930), .Y(n7620)
);
INVX2TS U7032 ( .A(n7620), .Y(n5932) );
AOI22X1TS U7033 ( .A0(n5935), .A1(n8191), .B0(n8190), .B1(n5934), .Y(n5931)
);
AOI22X1TS U7034 ( .A0(n5935), .A1(n8187), .B0(n5934), .B1(n8186), .Y(n5936)
);
AOI22X1TS U7035 ( .A0(n6873), .A1(n8219), .B0(n6872), .B1(n8218), .Y(n5937)
);
OAI211X4TS U7036 ( .A0(n2260), .A1(n8392), .B0(n8391), .C0(n5937), .Y(n7611)
);
AOI222X1TS U7037 ( .A0(n7582), .A1(n5945), .B0(n5944), .B1(n5943), .C0(n7581), .C1(n5942), .Y(n5949) );
INVX2TS U7038 ( .A(n7376), .Y(n5946) );
AOI22X1TS U7039 ( .A0(n6867), .A1(n5947), .B0(n7584), .B1(n5946), .Y(n5948)
);
OAI32X1TS U7040 ( .A0(n5951), .A1(n5950), .A2(n5949), .B0(n5948), .B1(n5950),
.Y(n5984) );
AOI22X1TS U7041 ( .A0(n2251), .A1(n8239), .B0(n6005), .B1(n8238), .Y(n5952)
);
AOI22X1TS U7042 ( .A0(n5986), .A1(n8229), .B0(n5998), .B1(n8228), .Y(n5953)
);
INVX2TS U7043 ( .A(n7638), .Y(n5963) );
AOI22X1TS U7044 ( .A0(n5986), .A1(n8279), .B0(n2207), .B1(n8278), .Y(n5955)
);
NAND3X2TS U7045 ( .A(n8305), .B(n5955), .C(n5954), .Y(n7564) );
INVX2TS U7046 ( .A(n7564), .Y(n5959) );
AOI22X1TS U7047 ( .A0(n2251), .A1(n8221), .B0(n5989), .B1(n8220), .Y(n5956)
);
AOI22X1TS U7048 ( .A0(n5986), .A1(n8237), .B0(n2247), .B1(n8236), .Y(n5957)
);
NAND3X2TS U7049 ( .A(n8408), .B(n5957), .C(n5992), .Y(n7561) );
INVX2TS U7050 ( .A(n7561), .Y(n5976) );
AOI22X1TS U7051 ( .A0(n2251), .A1(n8231), .B0(n5989), .B1(n8230), .Y(n5958)
);
OAI211X4TS U7052 ( .A0(n2204), .A1(n8360), .B0(n8359), .C0(n5958), .Y(n7386)
);
OA22X2TS U7053 ( .A0(n5959), .A1(n7384), .B0(n5976), .B1(n7386), .Y(n5981)
);
AOI22X1TS U7054 ( .A0(n2251), .A1(n8267), .B0(n5989), .B1(n8266), .Y(n5960)
);
OAI211X4TS U7055 ( .A0(n2260), .A1(n8376), .B0(n8375), .C0(n5960), .Y(n7382)
);
AOI22X1TS U7056 ( .A0(n5986), .A1(n8265), .B0(n2207), .B1(n8264), .Y(n5961)
);
NAND2X1TS U7057 ( .A(n2256), .B(n8147), .Y(n6003) );
NAND3X2TS U7058 ( .A(n8302), .B(n5961), .C(n6003), .Y(n7563) );
INVX2TS U7059 ( .A(n7563), .Y(n5964) );
AOI22X1TS U7060 ( .A0(n7380), .A1(n5968), .B0(n7379), .B1(n5967), .Y(n5975)
);
AOI21X1TS U7061 ( .A0(n5972), .A1(n5971), .B0(n5983), .Y(n5974) );
OAI2BB2X1TS U7062 ( .B0(n5975), .B1(n5983), .A0N(n5974), .A1N(n5973), .Y(
n5979) );
AOI211X1TS U7063 ( .A0(n5981), .A1(n5980), .B0(n5979), .C0(n5978), .Y(n5982)
);
OAI31X1TS U7064 ( .A0(n5985), .A1(n5984), .A2(n5983), .B0(n5982), .Y(n6011)
);
AOI22X1TS U7065 ( .A0(n5986), .A1(n8257), .B0(n2208), .B1(n8256), .Y(n5988)
);
NAND3X2TS U7066 ( .A(n8300), .B(n5988), .C(n5987), .Y(n7562) );
AOI22X1TS U7067 ( .A0(n2251), .A1(n8207), .B0(n5989), .B1(n8206), .Y(n5990)
);
INVX2TS U7068 ( .A(n7387), .Y(n6009) );
AOI22X1TS U7069 ( .A0(n7447), .A1(n8169), .B0(n2208), .B1(n8168), .Y(n5993)
);
NAND3X2TS U7070 ( .A(n8410), .B(n5993), .C(n5992), .Y(n7656) );
INVX2TS U7071 ( .A(n7656), .Y(n6001) );
AOI22X1TS U7072 ( .A0(n7447), .A1(n8163), .B0(n2208), .B1(n8162), .Y(n5994)
);
NAND2X1TS U7073 ( .A(n2256), .B(n8146), .Y(n6007) );
NAND3X2TS U7074 ( .A(n8296), .B(n5994), .C(n6007), .Y(n7577) );
INVX2TS U7075 ( .A(n7577), .Y(n5996) );
INVX2TS U7076 ( .A(gt_x_74_B_23_), .Y(n6024) );
AOI22X1TS U7077 ( .A0(n2251), .A1(n8249), .B0(n6005), .B1(n8248), .Y(n6002)
);
NAND3X2TS U7078 ( .A(n8298), .B(n6004), .C(n6003), .Y(n7560) );
INVX2TS U7079 ( .A(n7560), .Y(n6019) );
AOI22X1TS U7080 ( .A0(n2251), .A1(n8255), .B0(n6005), .B1(n8254), .Y(n6006)
);
AOI22X1TS U7081 ( .A0(n8074), .A1(n8165), .B0(n2208), .B1(n8164), .Y(n6008)
);
NAND3X2TS U7082 ( .A(n8297), .B(n6008), .C(n6007), .Y(n7578) );
OAI21X1TS U7083 ( .A0(n7389), .A1(n6019), .B0(n6018), .Y(n6023) );
AOI211X1TS U7084 ( .A0(n7562), .A1(n6009), .B0(n6022), .C0(n6023), .Y(n6010)
);
INVX2TS U7085 ( .A(n7576), .Y(n6012) );
AOI22X1TS U7086 ( .A0(n7388), .A1(n6016), .B0(n7387), .B1(n6015), .Y(n6021)
);
INVX2TS U7087 ( .A(n7578), .Y(n6017) );
AOI32X1TS U7088 ( .A0(n6019), .A1(n6018), .A2(n7389), .B0(n7390), .B1(n6017),
.Y(n6020) );
OAI32X1TS U7089 ( .A0(n6023), .A1(n6022), .A2(n6021), .B0(n6020), .B1(n6022),
.Y(n6027) );
AOI211X1TS U7090 ( .A0(n6029), .A1(n6028), .B0(n6027), .C0(n6026), .Y(n6035)
);
AOI32X4TS U7091 ( .A0(n6037), .A1(n6036), .A2(n6035), .B0(n6034), .B1(n6037),
.Y(n7595) );
AOI22X1TS U7092 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n6587), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n8642),
.Y(n6854) );
OR4X2TS U7093 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n6547) );
NAND4X2TS U7094 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n6038),
.C(n7792), .D(n7815), .Y(n7286) );
NAND3X2TS U7095 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n6645),
.C(n7815), .Y(n7285) );
INVX2TS U7096 ( .A(n6188), .Y(n6763) );
NAND2X1TS U7097 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n7284) );
OAI22X1TS U7098 ( .A0(n8021), .A1(n8059), .B0(n8020), .B1(n2371), .Y(n6041)
);
AOI21X1TS U7099 ( .A0(n2212), .A1(n8419), .B0(n6041), .Y(n6042) );
AOI22X1TS U7100 ( .A0(n2210), .A1(n8068), .B0(n2345), .B1(n8047), .Y(n6044)
);
AOI22X1TS U7101 ( .A0(n2405), .A1(n8429), .B0(n6851), .B1(n8019), .Y(n6043)
);
AOI22X1TS U7102 ( .A0(n2211), .A1(n8471), .B0(n2406), .B1(n8470), .Y(n6046)
);
AOI22X1TS U7103 ( .A0(n2375), .A1(n8048), .B0(n2471), .B1(n8047), .Y(n6045)
);
AOI22X1TS U7104 ( .A0(n2210), .A1(n8450), .B0(n2405), .B1(n8449), .Y(n6048)
);
AOI22X1TS U7105 ( .A0(n2375), .A1(n8047), .B0(n6851), .B1(n8456), .Y(n6047)
);
OAI211X4TS U7106 ( .A0(n8022), .A1(n8059), .B0(n6048), .C0(n6047), .Y(n1810)
);
AOI22X1TS U7107 ( .A0(n2210), .A1(n8452), .B0(n2405), .B1(n8451), .Y(n6050)
);
AOI22X1TS U7108 ( .A0(n2345), .A1(n8048), .B0(n6851), .B1(n8448), .Y(n6049)
);
OAI211X4TS U7109 ( .A0(n8022), .A1(n2371), .B0(n6050), .C0(n6049), .Y(n1809)
);
BUFX3TS U7110 ( .A(n6581), .Y(n8526) );
NOR2BX2TS U7111 ( .AN(n8633), .B(n8646), .Y(n6069) );
NOR2X2TS U7112 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n6668), .Y(n6698) );
INVX2TS U7113 ( .A(n6698), .Y(n6064) );
NAND2X1TS U7114 ( .A(n7812), .B(n7793), .Y(n6673) );
NOR2BX4TS U7115 ( .AN(n6674), .B(n6673), .Y(n6065) );
AOI21X1TS U7116 ( .A0(n7825), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n6051) );
AOI211X1TS U7117 ( .A0(n6675), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n6056),
.C0(n6055), .Y(n6061) );
NAND2X1TS U7118 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n6059), .Y(n6693) );
OAI22X1TS U7119 ( .A0(n6693), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n7821),
.B1(n8629), .Y(n6067) );
NAND2X4TS U7120 ( .A(n6675), .B(n7810), .Y(n6669) );
AOI31X1TS U7121 ( .A0(n6061), .A1(n6671), .A2(n6060), .B0(n7301), .Y(n7093)
);
INVX2TS U7122 ( .A(n6858), .Y(n6833) );
AOI21X1TS U7123 ( .A0(n8630), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n6062) );
OAI31X1TS U7124 ( .A0(n6062), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n8631), .Y(n6063) );
INVX2TS U7125 ( .A(n6063), .Y(n6071) );
INVX2TS U7126 ( .A(n6669), .Y(n6679) );
NAND3X2TS U7127 ( .A(n6679), .B(n7797), .C(n7816), .Y(n6695) );
NAND2X1TS U7128 ( .A(n6069), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n6691) );
BUFX3TS U7129 ( .A(n7642), .Y(n7658) );
NAND2X1TS U7130 ( .A(n7864), .B(n2487), .Y(n6072) );
OAI21X4TS U7131 ( .A0(n6074), .A1(n6073), .B0(n6072), .Y(n6160) );
OR2X1TS U7132 ( .A(n7871), .B(n2475), .Y(n6076) );
AOI21X4TS U7133 ( .A0(n6160), .A1(n6076), .B0(n6075), .Y(n6151) );
NOR2X1TS U7134 ( .A(n7863), .B(n2483), .Y(n6078) );
NAND2X1TS U7135 ( .A(n7863), .B(n2483), .Y(n6077) );
OAI21X4TS U7136 ( .A0(n6151), .A1(n6078), .B0(n6077), .Y(n6141) );
AOI21X4TS U7137 ( .A0(n6141), .A1(n6080), .B0(n6079), .Y(n6132) );
NOR2X1TS U7138 ( .A(n7862), .B(n2485), .Y(n6082) );
NAND2X1TS U7139 ( .A(n7862), .B(n2485), .Y(n6081) );
OAI21X4TS U7140 ( .A0(n6132), .A1(n6082), .B0(n6081), .Y(n6122) );
OR2X1TS U7141 ( .A(n7869), .B(n2477), .Y(n6084) );
AOI21X4TS U7142 ( .A0(n6122), .A1(n6084), .B0(n6083), .Y(n6113) );
NAND2X1TS U7143 ( .A(n7861), .B(n2486), .Y(n6085) );
OR2X1TS U7144 ( .A(n7868), .B(n2473), .Y(n6088) );
AOI21X1TS U7145 ( .A0(n6103), .A1(n6088), .B0(n6087), .Y(n6089) );
XOR2X1TS U7146 ( .A(n6089), .B(n7875), .Y(n6099) );
NAND2X1TS U7147 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n6157) );
INVX2TS U7148 ( .A(n6157), .Y(n6093) );
NOR2X1TS U7149 ( .A(n2483), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6147) );
NAND2X1TS U7150 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6148) );
NAND2X1TS U7151 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n6138) );
INVX2TS U7152 ( .A(n6138), .Y(n6094) );
AOI21X4TS U7153 ( .A0(n6143), .A1(n6139), .B0(n6094), .Y(n6134) );
NOR2X1TS U7154 ( .A(n2485), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6128) );
NAND2X1TS U7155 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6129) );
OAI21X4TS U7156 ( .A0(n6134), .A1(n6128), .B0(n6129), .Y(n6124) );
NAND2X1TS U7157 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n6119) );
INVX2TS U7158 ( .A(n6119), .Y(n6095) );
AOI21X4TS U7159 ( .A0(n6124), .A1(n6120), .B0(n6095), .Y(n6115) );
NOR2X1TS U7160 ( .A(n2486), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6109) );
NAND2X1TS U7161 ( .A(n2486), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6110) );
OAI21X4TS U7162 ( .A0(n6115), .A1(n6109), .B0(n6110), .Y(n6105) );
NAND2X1TS U7163 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n6100) );
INVX2TS U7164 ( .A(n6100), .Y(n6096) );
AOI21X4TS U7165 ( .A0(n6105), .A1(n6101), .B0(n6096), .Y(n7090) );
XOR2X1TS U7166 ( .A(n7090), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n6097) );
OAI2BB1X2TS U7167 ( .A0N(n6599), .A1N(n6099), .B0(n6098), .Y(n1412) );
NAND2X1TS U7168 ( .A(n6101), .B(n6100), .Y(n6104) );
INVX2TS U7169 ( .A(n6104), .Y(n6102) );
XNOR2X1TS U7170 ( .A(n6103), .B(n6102), .Y(n6108) );
XNOR2X1TS U7171 ( .A(n6105), .B(n6104), .Y(n6106) );
AOI22X1TS U7172 ( .A0(n6106), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n7599), .Y(n6107) );
NOR2X4TS U7173 ( .A(n1412), .B(n1317), .Y(n8415) );
INVX2TS U7174 ( .A(n6109), .Y(n6111) );
NAND2X1TS U7175 ( .A(n6111), .B(n6110), .Y(n6114) );
INVX2TS U7176 ( .A(n6114), .Y(n6112) );
XOR2X1TS U7177 ( .A(n6115), .B(n6114), .Y(n6116) );
BUFX3TS U7178 ( .A(n6371), .Y(n7138) );
AOI22X1TS U7179 ( .A0(n6116), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n7599), .Y(n6117) );
NAND2X1TS U7180 ( .A(n6120), .B(n6119), .Y(n6123) );
INVX2TS U7181 ( .A(n6123), .Y(n6121) );
XNOR2X1TS U7182 ( .A(n6122), .B(n6121), .Y(n6127) );
XNOR2X1TS U7183 ( .A(n6124), .B(n6123), .Y(n6125) );
BUFX3TS U7184 ( .A(n7088), .Y(n7159) );
AOI22X1TS U7185 ( .A0(n6125), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n7159), .Y(n6126) );
INVX2TS U7186 ( .A(n6128), .Y(n6130) );
NAND2X1TS U7187 ( .A(n6130), .B(n6129), .Y(n6133) );
INVX2TS U7188 ( .A(n6133), .Y(n6131) );
XOR2X1TS U7189 ( .A(n6134), .B(n6133), .Y(n6135) );
AOI22X1TS U7190 ( .A0(n6135), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n7159), .Y(n6136) );
NAND2X1TS U7191 ( .A(n6139), .B(n6138), .Y(n6142) );
INVX2TS U7192 ( .A(n6142), .Y(n6140) );
XNOR2X1TS U7193 ( .A(n6141), .B(n6140), .Y(n6146) );
XNOR2X1TS U7194 ( .A(n6143), .B(n6142), .Y(n6144) );
AOI22X1TS U7195 ( .A0(n6144), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n7159), .Y(n6145) );
NAND2X1TS U7196 ( .A(n6149), .B(n6148), .Y(n6152) );
INVX2TS U7197 ( .A(n6152), .Y(n6150) );
XOR2X1TS U7198 ( .A(n6153), .B(n6152), .Y(n6154) );
AOI22X1TS U7199 ( .A0(n6154), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n7159), .Y(n6155) );
OAI2BB1X1TS U7200 ( .A0N(n6599), .A1N(n6156), .B0(n6155), .Y(n1323) );
AND2X4TS U7201 ( .A(n8415), .B(n8414), .Y(n6879) );
NAND2X2TS U7202 ( .A(n6879), .B(n6878), .Y(n8291) );
BUFX3TS U7203 ( .A(n6424), .Y(n7201) );
NAND2X1TS U7204 ( .A(n6158), .B(n6157), .Y(n6161) );
INVX2TS U7205 ( .A(n6161), .Y(n6159) );
XNOR2X1TS U7206 ( .A(n6160), .B(n6159), .Y(n6165) );
XNOR2X1TS U7207 ( .A(n6162), .B(n6161), .Y(n6163) );
AOI22X1TS U7208 ( .A0(n6163), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n7159), .Y(n6164) );
OAI2BB1X1TS U7209 ( .A0N(n7201), .A1N(n6165), .B0(n6164), .Y(n1333) );
AOI22X1TS U7210 ( .A0(n2210), .A1(n8476), .B0(n2405), .B1(n8475), .Y(n6168)
);
AOI22X1TS U7211 ( .A0(n2345), .A1(n8049), .B0(n8118), .B1(n8478), .Y(n6167)
);
AOI22X1TS U7212 ( .A0(n2210), .A1(n8073), .B0(n2375), .B1(n8019), .Y(n6169)
);
AOI22X1TS U7213 ( .A0(n2212), .A1(n8445), .B0(n2406), .B1(n8444), .Y(n6171)
);
AOI22X1TS U7214 ( .A0(n2292), .A1(n8053), .B0(n8118), .B1(n8447), .Y(n6170)
);
AOI22X1TS U7215 ( .A0(n2211), .A1(n8461), .B0(n2406), .B1(n8460), .Y(n6173)
);
AOI22X1TS U7216 ( .A0(n2292), .A1(n8051), .B0(n8118), .B1(n8453), .Y(n6172)
);
OAI211X4TS U7217 ( .A0(n8028), .A1(n8058), .B0(n6173), .C0(n6172), .Y(n1801)
);
AOI22X1TS U7218 ( .A0(n2212), .A1(n8437), .B0(n2406), .B1(n8436), .Y(n6175)
);
AOI22X1TS U7219 ( .A0(n2345), .A1(n8055), .B0(n6851), .B1(n8477), .Y(n6174)
);
BUFX3TS U7220 ( .A(n7598), .Y(n7515) );
NOR2X2TS U7221 ( .A(n7814), .B(n7011), .Y(n7034) );
INVX2TS U7222 ( .A(n1809), .Y(n6176) );
INVX2TS U7223 ( .A(n1813), .Y(n7007) );
OAI22X1TS U7224 ( .A0(n6176), .A1(n7012), .B0(n7007), .B1(n6991), .Y(n6177)
);
AOI211X2TS U7225 ( .A0(n2373), .A1(n1805), .B0(n7034), .C0(n6177), .Y(n7051)
);
AOI21X1TS U7226 ( .A0(n2471), .A1(n8027), .B0(n8016), .Y(n6179) );
OAI211X1TS U7227 ( .A0(n8046), .A1(n3147), .B0(n8504), .C0(n6179), .Y(n6881)
);
AOI22X1TS U7228 ( .A0(n1797), .A1(n2443), .B0(n6881), .B1(n2396), .Y(n6183)
);
INVX2TS U7229 ( .A(n7038), .Y(n6180) );
AOI22X1TS U7230 ( .A0(n1801), .A1(n2381), .B0(n1793), .B1(n2398), .Y(n6182)
);
OAI211X1TS U7231 ( .A0(n7051), .A1(n7050), .B0(n6183), .C0(n6182), .Y(n7085)
);
INVX2TS U7232 ( .A(FPADDSUB_bit_shift_SHT2), .Y(n6570) );
NOR2X2TS U7233 ( .A(n2372), .B(n6570), .Y(n7005) );
NOR2X4TS U7234 ( .A(n2340), .B(n6570), .Y(n7052) );
AOI21X1TS U7235 ( .A0(n6184), .A1(n6996), .B0(n7598), .Y(n6185) );
AOI22X1TS U7236 ( .A0(n2212), .A1(n8469), .B0(n2291), .B1(n8468), .Y(n6187)
);
AOI22X1TS U7237 ( .A0(n2345), .A1(n8045), .B0(n8118), .B1(n8431), .Y(n6186)
);
AND3X2TS U7238 ( .A(FPSENCOS_cont_var_out[1]), .B(n6188), .C(n7819), .Y(
n7787) );
NOR2X1TS U7239 ( .A(n7748), .B(n7749), .Y(n6256) );
NOR2X2TS U7240 ( .A(n7775), .B(n7773), .Y(n6295) );
NOR2X1TS U7241 ( .A(n6256), .B(n6295), .Y(n6194) );
XOR2X1TS U7242 ( .A(n7679), .B(n7680), .Y(n6195) );
NOR2X2TS U7243 ( .A(n7774), .B(n7771), .Y(n6319) );
XNOR2X1TS U7244 ( .A(n7683), .B(n7682), .Y(n6196) );
NOR2X2TS U7245 ( .A(n6196), .B(n7770), .Y(n6224) );
XOR2X1TS U7246 ( .A(n7674), .B(n7675), .Y(n6197) );
NOR2X2TS U7247 ( .A(n6197), .B(n7769), .Y(n6238) );
INVX2TS U7248 ( .A(n6603), .Y(n6204) );
OAI2BB1X1TS U7249 ( .A0N(n7757), .A1N(n7752), .B0(n6192), .Y(n6292) );
NAND2X1TS U7250 ( .A(n7775), .B(n7773), .Y(n6296) );
AOI21X1TS U7251 ( .A0(n6292), .A1(n6194), .B0(n6193), .Y(n6220) );
NAND2X1TS U7252 ( .A(n6195), .B(n7772), .Y(n6313) );
NAND2X1TS U7253 ( .A(n7774), .B(n7771), .Y(n6320) );
OAI21X1TS U7254 ( .A0(n6319), .A1(n6313), .B0(n6320), .Y(n6221) );
NAND2X1TS U7255 ( .A(n6196), .B(n7770), .Y(n6231) );
NAND2X1TS U7256 ( .A(n6197), .B(n7769), .Y(n6237) );
AOI21X1TS U7257 ( .A0(n6221), .A1(n6199), .B0(n6198), .Y(n6200) );
INVX2TS U7258 ( .A(n6609), .Y(n6203) );
XOR2X1TS U7259 ( .A(n7677), .B(n7678), .Y(n6205) );
INVX2TS U7260 ( .A(n6450), .Y(n6338) );
NAND2X1TS U7261 ( .A(n6205), .B(n7768), .Y(n6452) );
NAND2X1TS U7262 ( .A(n6338), .B(n6452), .Y(n6206) );
XNOR2X1TS U7263 ( .A(n6207), .B(n6206), .Y(n6208) );
NAND2X1TS U7264 ( .A(n6208), .B(n2248), .Y(n6209) );
OAI2BB1X1TS U7265 ( .A0N(n8057), .A1N(n8505), .B0(n6209), .Y(n1589) );
INVX2TS U7266 ( .A(n6213), .Y(n6215) );
INVX2TS U7267 ( .A(n6219), .Y(n6230) );
INVX2TS U7268 ( .A(n6220), .Y(n6316) );
INVX2TS U7269 ( .A(n6316), .Y(n6305) );
INVX2TS U7270 ( .A(n6221), .Y(n6232) );
OA21XLTS U7271 ( .A0(n6305), .A1(n6230), .B0(n6232), .Y(n6222) );
INVX2TS U7272 ( .A(n6224), .Y(n6229) );
NAND2X1TS U7273 ( .A(n6229), .B(n6231), .Y(n6225) );
XNOR2X1TS U7274 ( .A(n6226), .B(n6225), .Y(n6227) );
NAND2X1TS U7275 ( .A(n6227), .B(n2248), .Y(n6228) );
OAI2BB1X1TS U7276 ( .A0N(n8057), .A1N(n8501), .B0(n6228), .Y(n1587) );
NOR2X1TS U7277 ( .A(n6230), .B(n6224), .Y(n6234) );
INVX2TS U7278 ( .A(n6306), .Y(n6312) );
NAND2X1TS U7279 ( .A(n6234), .B(n6312), .Y(n6236) );
AOI21X1TS U7280 ( .A0(n6316), .A1(n6234), .B0(n6233), .Y(n6235) );
XNOR2X1TS U7281 ( .A(n6240), .B(n6239), .Y(n6241) );
NAND2X1TS U7282 ( .A(n6241), .B(n2248), .Y(n6242) );
OAI2BB1X1TS U7283 ( .A0N(n8057), .A1N(n8503), .B0(n6242), .Y(n1588) );
NOR3XLTS U7284 ( .A(FPSENCOS_cont_var_out[1]), .B(n7819), .C(n6763), .Y(
n6243) );
CLKBUFX2TS U7285 ( .A(n6243), .Y(n8606) );
AOI22X1TS U7286 ( .A0(n2211), .A1(n8443), .B0(n2406), .B1(n8442), .Y(n6245)
);
AOI22X1TS U7287 ( .A0(n2292), .A1(n8052), .B0(n8118), .B1(n8474), .Y(n6244)
);
AOI22X1TS U7288 ( .A0(n2212), .A1(n8441), .B0(n2291), .B1(n8440), .Y(n6247)
);
AOI22X1TS U7289 ( .A0(n2375), .A1(n8051), .B0(n2471), .B1(n8050), .Y(n6246)
);
INVX2TS U7290 ( .A(n6248), .Y(n6250) );
BUFX3TS U7291 ( .A(n8593), .Y(n8550) );
NAND2X1TS U7292 ( .A(n7302), .B(n8550), .Y(n6254) );
CLKBUFX3TS U7293 ( .A(n2348), .Y(n8549) );
OAI33X4TS U7294 ( .A0(n7820), .A1(n8642), .A2(n7795), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n8643) );
INVX2TS U7295 ( .A(n8643), .Y(n8644) );
INVX2TS U7296 ( .A(n6256), .Y(n6291) );
NAND2X1TS U7297 ( .A(n6291), .B(n7766), .Y(n6257) );
XNOR2X1TS U7298 ( .A(n6258), .B(n6257), .Y(n6259) );
NAND2X1TS U7299 ( .A(n6259), .B(n2248), .Y(n6260) );
OAI2BB1X1TS U7300 ( .A0N(n8057), .A1N(n8491), .B0(n6260), .Y(n1583) );
INVX2TS U7301 ( .A(n6261), .Y(n6262) );
NAND2X1TS U7302 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n6267) );
NAND2X1TS U7303 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n6266) );
NAND2X1TS U7304 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n6265) );
NAND3X1TS U7305 ( .A(n6267), .B(n6266), .C(n6265), .Y(n8741) );
NAND2X1TS U7306 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n6270) );
NAND2X1TS U7307 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n6269) );
NAND2X1TS U7308 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n6268) );
NAND3X1TS U7309 ( .A(n6270), .B(n6269), .C(n6268), .Y(n8751) );
NAND2X1TS U7310 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n6273) );
NAND2X1TS U7311 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n6272) );
NAND2X1TS U7312 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n6271) );
NAND3X1TS U7313 ( .A(n6273), .B(n6272), .C(n6271), .Y(n8745) );
NAND2X1TS U7314 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n6276) );
NAND2X1TS U7315 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n6275) );
NAND2X1TS U7316 ( .A(n2296), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n6274) );
NAND3X1TS U7317 ( .A(n6276), .B(n6275), .C(n6274), .Y(n8726) );
NAND2X1TS U7318 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n6279) );
NAND2X1TS U7319 ( .A(n6882), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n6278) );
NAND3X1TS U7320 ( .A(n6279), .B(n6278), .C(n6277), .Y(n8720) );
NAND2X1TS U7321 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6282) );
NAND2X1TS U7322 ( .A(n6882), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n6281) );
NAND3X1TS U7323 ( .A(n6282), .B(n6281), .C(n6280), .Y(n8716) );
NAND2X1TS U7324 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n6285) );
NAND2X1TS U7325 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n6284) );
NAND3X1TS U7326 ( .A(n6286), .B(n6285), .C(n6284), .Y(n8723) );
NAND2X1TS U7327 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n6289) );
NAND2X1TS U7328 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6288) );
NAND3X1TS U7329 ( .A(n6289), .B(n6288), .C(n6287), .Y(n8717) );
NAND2X1TS U7330 ( .A(n6290), .B(n6291), .Y(n6294) );
AOI21X1TS U7331 ( .A0(n6292), .A1(n6291), .B0(n7744), .Y(n6293) );
INVX2TS U7332 ( .A(n6295), .Y(n6297) );
NAND2X1TS U7333 ( .A(n6297), .B(n6296), .Y(n6298) );
XNOR2X1TS U7334 ( .A(n6299), .B(n6298), .Y(n6300) );
NAND2X1TS U7335 ( .A(n6300), .B(n2248), .Y(n6301) );
OAI2BB1X1TS U7336 ( .A0N(n8057), .A1N(n8492), .B0(n6301), .Y(n1584) );
AOI22X1TS U7337 ( .A0(n6540), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n6440), .Y(n6302) );
OAI2BB1X1TS U7338 ( .A0N(n2445), .A1N(n1588), .B0(n6302), .Y(n6303) );
AOI21X1TS U7339 ( .A0(n6544), .A1(FPMULT_Add_result[11]), .B0(n6303), .Y(
n6304) );
OAI2BB1X1TS U7340 ( .A0N(n2416), .A1N(n1587), .B0(n6304), .Y(n1528) );
INVX2TS U7341 ( .A(n6307), .Y(n6315) );
NAND2X1TS U7342 ( .A(n6315), .B(n6313), .Y(n6308) );
XNOR2X1TS U7343 ( .A(n6309), .B(n6308), .Y(n6310) );
NAND2X1TS U7344 ( .A(n6310), .B(n2248), .Y(n6311) );
OAI2BB1X1TS U7345 ( .A0N(n8057), .A1N(n8500), .B0(n6311), .Y(n1585) );
NAND2X1TS U7346 ( .A(n6312), .B(n6315), .Y(n6318) );
INVX2TS U7347 ( .A(n6313), .Y(n6314) );
AOI21X1TS U7348 ( .A0(n6316), .A1(n6315), .B0(n6314), .Y(n6317) );
INVX2TS U7349 ( .A(n6319), .Y(n6321) );
NAND2X1TS U7350 ( .A(n6321), .B(n6320), .Y(n6322) );
XNOR2X1TS U7351 ( .A(n6323), .B(n6322), .Y(n6324) );
NAND2X1TS U7352 ( .A(n6324), .B(n2248), .Y(n6325) );
OAI2BB1X1TS U7353 ( .A0N(n8057), .A1N(n8502), .B0(n6325), .Y(n1586) );
AOI22X1TS U7354 ( .A0(n6540), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n6440), .Y(n6326) );
OAI2BB1X1TS U7355 ( .A0N(n2446), .A1N(n1586), .B0(n6326), .Y(n6327) );
AOI21X1TS U7356 ( .A0(n2411), .A1(FPMULT_Add_result[9]), .B0(n6327), .Y(
n6328) );
OAI2BB1X1TS U7357 ( .A0N(n5768), .A1N(n1585), .B0(n6328), .Y(n1526) );
AOI22X1TS U7358 ( .A0(n5774), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n6539), .Y(n6329) );
OAI2BB1X1TS U7359 ( .A0N(n2444), .A1N(n1587), .B0(n6329), .Y(n6330) );
AOI21X1TS U7360 ( .A0(n2411), .A1(FPMULT_Add_result[10]), .B0(n6330), .Y(
n6331) );
OAI2BB1X1TS U7361 ( .A0N(n2416), .A1N(n1586), .B0(n6331), .Y(n1527) );
AOI22X1TS U7362 ( .A0(n2380), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n6907), .Y(n6332) );
OAI2BB1X1TS U7363 ( .A0N(n2445), .A1N(n1589), .B0(n6332), .Y(n6333) );
AOI21X1TS U7364 ( .A0(n6544), .A1(FPMULT_Add_result[12]), .B0(n6333), .Y(
n6334) );
OAI2BB1X1TS U7365 ( .A0N(n5768), .A1N(n1588), .B0(n6334), .Y(n1529) );
NAND2X1TS U7366 ( .A(n6603), .B(n6338), .Y(n6336) );
INVX2TS U7367 ( .A(n6452), .Y(n6337) );
AOI21X1TS U7368 ( .A0(n2432), .A1(n6338), .B0(n6337), .Y(n6339) );
NAND2X1TS U7369 ( .A(n6340), .B(n6339), .Y(n6345) );
AOI21X1TS U7370 ( .A0(n7683), .A1(n7681), .B0(n7684), .Y(n6341) );
NOR2X2TS U7371 ( .A(n6342), .B(n7746), .Y(n6453) );
NAND2X1TS U7372 ( .A(n6342), .B(n7747), .Y(n6451) );
NAND2X1TS U7373 ( .A(n6343), .B(n6451), .Y(n6344) );
XNOR2X1TS U7374 ( .A(n6345), .B(n6344), .Y(n6346) );
OAI2BB1X1TS U7375 ( .A0N(n2198), .A1N(n6346), .B0(n8508), .Y(n6884) );
AOI22X1TS U7376 ( .A0(n6540), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n6539), .Y(n6347) );
OAI2BB1X1TS U7377 ( .A0N(n6884), .A1N(n2445), .B0(n6347), .Y(n6348) );
AOI21X1TS U7378 ( .A0(n6544), .A1(FPMULT_Add_result[13]), .B0(n6348), .Y(
n6349) );
OAI2BB1X1TS U7379 ( .A0N(n2416), .A1N(n1589), .B0(n6349), .Y(n1530) );
INVX2TS U7380 ( .A(n7787), .Y(n8605) );
AOI22X1TS U7381 ( .A0(n2211), .A1(n8439), .B0(n2291), .B1(n8438), .Y(n6351)
);
AOI22X1TS U7382 ( .A0(n2293), .A1(n8052), .B0(n2471), .B1(n8051), .Y(n6350)
);
CLKBUFX2TS U7383 ( .A(n2348), .Y(n6353) );
CLKBUFX3TS U7384 ( .A(n8634), .Y(n7989) );
CLKBUFX2TS U7385 ( .A(n8548), .Y(n7986) );
CLKBUFX3TS U7386 ( .A(n7986), .Y(n7985) );
CLKBUFX3TS U7387 ( .A(n2401), .Y(n7990) );
CLKBUFX3TS U7388 ( .A(n8534), .Y(n7973) );
CLKBUFX3TS U7389 ( .A(n6352), .Y(n7979) );
CLKBUFX3TS U7390 ( .A(n7980), .Y(n7988) );
CLKBUFX3TS U7391 ( .A(n7963), .Y(n7965) );
CLKBUFX2TS U7392 ( .A(n8548), .Y(n7966) );
BUFX3TS U7393 ( .A(n7966), .Y(n8527) );
BUFX3TS U7394 ( .A(n8537), .Y(n8545) );
CLKBUFX2TS U7395 ( .A(n8547), .Y(n7963) );
BUFX3TS U7396 ( .A(n2363), .Y(n8598) );
BUFX3TS U7397 ( .A(n8604), .Y(n7994) );
BUFX3TS U7398 ( .A(n7994), .Y(n8597) );
BUFX3TS U7399 ( .A(n8535), .Y(n8542) );
BUFX3TS U7400 ( .A(n8534), .Y(n8543) );
BUFX3TS U7401 ( .A(n7980), .Y(n8538) );
BUFX3TS U7402 ( .A(n2422), .Y(n8532) );
CLKBUFX2TS U7403 ( .A(n8535), .Y(n7976) );
BUFX3TS U7404 ( .A(n7976), .Y(n8531) );
CLKBUFX2TS U7405 ( .A(n7986), .Y(n7983) );
BUFX3TS U7406 ( .A(n6352), .Y(n8540) );
CLKBUFX3TS U7407 ( .A(n8537), .Y(n8529) );
BUFX3TS U7408 ( .A(n8594), .Y(n8581) );
BUFX3TS U7409 ( .A(n8594), .Y(n8580) );
BUFX3TS U7410 ( .A(n8594), .Y(n8579) );
BUFX3TS U7411 ( .A(n8578), .Y(n8561) );
BUFX3TS U7412 ( .A(n8593), .Y(n8559) );
BUFX3TS U7413 ( .A(n8576), .Y(n8558) );
BUFX3TS U7414 ( .A(n7959), .Y(n8544) );
CLKBUFX3TS U7415 ( .A(n2348), .Y(n8546) );
BUFX3TS U7416 ( .A(n8592), .Y(n8572) );
BUFX3TS U7417 ( .A(n8592), .Y(n8571) );
BUFX3TS U7418 ( .A(n8592), .Y(n8570) );
BUFX3TS U7419 ( .A(n8595), .Y(n8590) );
BUFX3TS U7420 ( .A(n8595), .Y(n8589) );
BUFX3TS U7421 ( .A(n8595), .Y(n8588) );
BUFX3TS U7422 ( .A(n8591), .Y(n8564) );
CLKBUFX2TS U7423 ( .A(n8576), .Y(n7991) );
BUFX3TS U7424 ( .A(n2493), .Y(n8602) );
BUFX3TS U7425 ( .A(n8592), .Y(n8555) );
BUFX3TS U7426 ( .A(n8594), .Y(n8554) );
BUFX3TS U7427 ( .A(n8591), .Y(n8552) );
CLKBUFX2TS U7428 ( .A(n8593), .Y(n8577) );
BUFX3TS U7429 ( .A(n8591), .Y(n8569) );
BUFX3TS U7430 ( .A(n8591), .Y(n8568) );
BUFX3TS U7431 ( .A(n8591), .Y(n8567) );
BUFX3TS U7432 ( .A(n8591), .Y(n8566) );
BUFX3TS U7433 ( .A(n8591), .Y(n8565) );
BUFX3TS U7434 ( .A(n7959), .Y(n7974) );
BUFX3TS U7435 ( .A(n8594), .Y(n8583) );
BUFX3TS U7436 ( .A(n8595), .Y(n8551) );
BUFX3TS U7437 ( .A(n8592), .Y(n8573) );
BUFX3TS U7438 ( .A(n8595), .Y(n8587) );
BUFX3TS U7439 ( .A(n8592), .Y(n8575) );
BUFX3TS U7440 ( .A(n8594), .Y(n8582) );
BUFX3TS U7441 ( .A(n8594), .Y(n8584) );
BUFX3TS U7442 ( .A(n8595), .Y(n8585) );
BUFX3TS U7443 ( .A(n8595), .Y(n8586) );
BUFX3TS U7444 ( .A(n8592), .Y(n8574) );
BUFX3TS U7445 ( .A(n8537), .Y(n8528) );
CLKBUFX3TS U7446 ( .A(n2347), .Y(n7975) );
BUFX3TS U7447 ( .A(n7980), .Y(n7987) );
BUFX3TS U7448 ( .A(n6352), .Y(n7967) );
BUFX3TS U7449 ( .A(n6352), .Y(n7968) );
BUFX3TS U7450 ( .A(n8537), .Y(n7978) );
BUFX3TS U7451 ( .A(n6352), .Y(n7982) );
BUFX3TS U7452 ( .A(n8535), .Y(n7972) );
BUFX3TS U7453 ( .A(n8535), .Y(n7957) );
BUFX3TS U7454 ( .A(n8530), .Y(n7971) );
BUFX3TS U7455 ( .A(n6352), .Y(n7984) );
BUFX3TS U7456 ( .A(n8529), .Y(n7964) );
BUFX3TS U7457 ( .A(n7957), .Y(n7960) );
BUFX3TS U7458 ( .A(n7986), .Y(n7981) );
BUFX3TS U7459 ( .A(n8534), .Y(n7961) );
CLKBUFX3TS U7460 ( .A(n6352), .Y(n7969) );
CLKBUFX3TS U7461 ( .A(n2369), .Y(n7962) );
BUFX3TS U7462 ( .A(n7955), .Y(n7956) );
BUFX3TS U7463 ( .A(n2347), .Y(n7977) );
BUFX3TS U7464 ( .A(n8537), .Y(n8541) );
CLKBUFX3TS U7465 ( .A(n8578), .Y(n7992) );
BUFX3TS U7466 ( .A(n8599), .Y(n8604) );
INVX2TS U7467 ( .A(n7876), .Y(n6355) );
OAI21X1TS U7468 ( .A0(n8038), .A1(n2220), .B0(n8078), .Y(n7619) );
BUFX3TS U7469 ( .A(n7634), .Y(n7631) );
OAI21X1TS U7470 ( .A0(n8122), .A1(n2216), .B0(n8121), .Y(n6866) );
OAI21X1TS U7471 ( .A0(n8040), .A1(n2221), .B0(n8103), .Y(n7610) );
BUFX3TS U7472 ( .A(n7634), .Y(n7604) );
OAI21X1TS U7473 ( .A0(n8039), .A1(n2217), .B0(n8132), .Y(n6870) );
OAI21X1TS U7474 ( .A0(n8039), .A1(n2222), .B0(n8092), .Y(n7616) );
OAI21X1TS U7475 ( .A0(n8038), .A1(n2215), .B0(n8108), .Y(n6871) );
OAI21X1TS U7476 ( .A0(n8040), .A1(n2216), .B0(n8138), .Y(n6868) );
OAI21X1TS U7477 ( .A0(n8128), .A1(n2217), .B0(n8127), .Y(n7613) );
OAI21X1TS U7478 ( .A0(n8041), .A1(n2220), .B0(n8079), .Y(n7607) );
OAI21X1TS U7479 ( .A0(n8041), .A1(n2215), .B0(n8107), .Y(n6865) );
OAI21X1TS U7480 ( .A0(n8004), .A1(n2221), .B0(n8111), .Y(n6861) );
INVX2TS U7481 ( .A(n7827), .Y(n6943) );
ADDHXLTS U7482 ( .A(n7780), .B(n7781), .CO(n5452), .S(n6357) );
OAI2BB1X1TS U7483 ( .A0N(n8043), .A1N(n6357), .B0(n8495), .Y(n6902) );
NAND2X1TS U7484 ( .A(n6921), .B(n6902), .Y(n8615) );
NAND2X1TS U7485 ( .A(n6939), .B(n6358), .Y(n8627) );
OAI2BB1X1TS U7486 ( .A0N(n8043), .A1N(n8494), .B0(n8493), .Y(n6537) );
NAND2X1TS U7487 ( .A(n6939), .B(n6537), .Y(n8616) );
INVX2TS U7488 ( .A(n6359), .Y(n6401) );
AOI21X1TS U7489 ( .A0(n6401), .A1(n6361), .B0(n6360), .Y(n6414) );
INVX2TS U7490 ( .A(n7192), .Y(n6364) );
NAND2X1TS U7491 ( .A(n6364), .B(n7191), .Y(n6370) );
INVX2TS U7492 ( .A(n6370), .Y(n6365) );
XNOR2X1TS U7493 ( .A(n6366), .B(n6365), .Y(n6374) );
INVX2TS U7494 ( .A(n6367), .Y(n6418) );
AOI21X1TS U7495 ( .A0(n6418), .A1(n6369), .B0(n6368), .Y(n7193) );
XOR2X1TS U7496 ( .A(n7193), .B(n6370), .Y(n6372) );
BUFX3TS U7497 ( .A(n6371), .Y(n7197) );
AOI22X1TS U7498 ( .A0(n6372), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n7196), .Y(n6373) );
OAI2BB1X1TS U7499 ( .A0N(n6424), .A1N(n6374), .B0(n6373), .Y(n1343) );
INVX2TS U7500 ( .A(n6375), .Y(n7157) );
INVX2TS U7501 ( .A(n6403), .Y(n6378) );
NAND2X1TS U7502 ( .A(n6378), .B(n6402), .Y(n6382) );
INVX2TS U7503 ( .A(n6382), .Y(n6379) );
XNOR2X1TS U7504 ( .A(n6380), .B(n6379), .Y(n6385) );
XOR2X1TS U7505 ( .A(n6404), .B(n6382), .Y(n6383) );
AOI22X1TS U7506 ( .A0(n6383), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n7196), .Y(n6384) );
OAI2BB1X1TS U7507 ( .A0N(n6424), .A1N(n6385), .B0(n6384), .Y(n1347) );
INVX2TS U7508 ( .A(n6386), .Y(n6389) );
INVX2TS U7509 ( .A(n6387), .Y(n6388) );
AOI21X1TS U7510 ( .A0(n6401), .A1(n6389), .B0(n6388), .Y(n6392) );
INVX2TS U7511 ( .A(n6390), .Y(n6417) );
NAND2X1TS U7512 ( .A(n6417), .B(n6415), .Y(n6393) );
INVX2TS U7513 ( .A(n6393), .Y(n6391) );
XNOR2X1TS U7514 ( .A(n6418), .B(n6393), .Y(n6394) );
AOI22X1TS U7515 ( .A0(n6394), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n7196), .Y(n6395) );
OAI2BB1X1TS U7516 ( .A0N(n6424), .A1N(n6396), .B0(n6395), .Y(n1345) );
INVX2TS U7517 ( .A(n6397), .Y(n6399) );
NAND2X1TS U7518 ( .A(n6399), .B(n6398), .Y(n6405) );
INVX2TS U7519 ( .A(n6405), .Y(n6400) );
XNOR2X1TS U7520 ( .A(n6401), .B(n6400), .Y(n6409) );
XNOR2X1TS U7521 ( .A(n6406), .B(n6405), .Y(n6407) );
AOI22X1TS U7522 ( .A0(n6407), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n7196), .Y(n6408) );
OAI2BB1X1TS U7523 ( .A0N(n6424), .A1N(n6409), .B0(n6408), .Y(n1346) );
INVX2TS U7524 ( .A(n6410), .Y(n6412) );
NAND2X1TS U7525 ( .A(n6412), .B(n6411), .Y(n6419) );
INVX2TS U7526 ( .A(n6419), .Y(n6413) );
INVX2TS U7527 ( .A(n6415), .Y(n6416) );
AOI21X1TS U7528 ( .A0(n6418), .A1(n6417), .B0(n6416), .Y(n6420) );
XOR2X1TS U7529 ( .A(n6420), .B(n6419), .Y(n6421) );
AOI22X1TS U7530 ( .A0(n6421), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n7196), .Y(n6422) );
OAI2BB1X1TS U7531 ( .A0N(n6424), .A1N(n6423), .B0(n6422), .Y(n1344) );
INVX2TS U7532 ( .A(n1664), .Y(n6425) );
AND4X1TS U7533 ( .A(n7689), .B(n6426), .C(n7690), .D(n6425), .Y(n8064) );
AOI22X1TS U7534 ( .A0(n6540), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n6539), .Y(n6427) );
OAI2BB1X1TS U7535 ( .A0N(n2444), .A1N(n1584), .B0(n6427), .Y(n6428) );
AOI21X1TS U7536 ( .A0(n2411), .A1(FPMULT_Add_result[7]), .B0(n6428), .Y(
n6429) );
OAI2BB1X1TS U7537 ( .A0N(n2416), .A1N(n1583), .B0(n6429), .Y(n1524) );
AOI22X1TS U7538 ( .A0(n2380), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n6440), .Y(n6430) );
OAI2BB1X1TS U7539 ( .A0N(n2444), .A1N(n1583), .B0(n6430), .Y(n6431) );
AOI21X1TS U7540 ( .A0(n2411), .A1(FPMULT_Add_result[6]), .B0(n6431), .Y(
n6432) );
OAI2BB1X1TS U7541 ( .A0N(n5768), .A1N(n1582), .B0(n6432), .Y(n1523) );
AOI222X1TS U7542 ( .A0(n8153), .A1(n7996), .B0(n8152), .B1(n8018), .C0(n7997), .C1(n8151), .Y(n6433) );
INVX2TS U7543 ( .A(n6433), .Y(n1419) );
AOI222X1TS U7544 ( .A0(n8143), .A1(n7996), .B0(n8142), .B1(n8018), .C0(n7997), .C1(n8141), .Y(n6434) );
INVX2TS U7545 ( .A(n6434), .Y(n1467) );
INVX2TS U7546 ( .A(n6435), .Y(n8762) );
OAI222X4TS U7547 ( .A0(n2214), .A1(n8030), .B0(n8083), .B1(n8056), .C0(n8008), .C1(n2219), .Y(n7507) );
INVX2TS U7548 ( .A(n7507), .Y(n8755) );
OAI222X4TS U7549 ( .A0(n2214), .A1(n8031), .B0(n8085), .B1(n8056), .C0(n8001), .C1(n2219), .Y(n7509) );
INVX2TS U7550 ( .A(n7509), .Y(n8756) );
INVX2TS U7551 ( .A(n7661), .Y(n7512) );
INVX2TS U7552 ( .A(n1467), .Y(n7499) );
NAND2X1TS U7553 ( .A(n1419), .B(n7499), .Y(n7498) );
INVX2TS U7554 ( .A(n7498), .Y(n7496) );
NOR2X1TS U7555 ( .A(n8762), .B(n7507), .Y(n7494) );
OAI22X1TS U7556 ( .A0(n7496), .A1(n7494), .B0(n6435), .B1(n8755), .Y(n6445)
);
OAI222X4TS U7557 ( .A0(n2220), .A1(n8031), .B0(n8096), .B1(n8056), .C0(n8001), .C1(n2217), .Y(n6444) );
NAND2X1TS U7558 ( .A(n6444), .B(n8756), .Y(n6446) );
XNOR2X1TS U7559 ( .A(n6445), .B(n6436), .Y(n6437) );
NOR3XLTS U7560 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n7818),
.C(n6646), .Y(n6438) );
INVX2TS U7561 ( .A(n8736), .Y(n8738) );
AOI22X1TS U7562 ( .A0(n5774), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n6907), .Y(n6441) );
OAI2BB1X1TS U7563 ( .A0N(n2446), .A1N(n1585), .B0(n6441), .Y(n6442) );
AOI21X1TS U7564 ( .A0(n2411), .A1(FPMULT_Add_result[8]), .B0(n6442), .Y(
n6443) );
OAI2BB1X1TS U7565 ( .A0N(n5768), .A1N(n1584), .B0(n6443), .Y(n1525) );
INVX2TS U7566 ( .A(n6444), .Y(n8764) );
INVX2TS U7567 ( .A(n7501), .Y(n8765) );
AOI22X1TS U7568 ( .A0(n7509), .A1(n8764), .B0(n6446), .B1(n6445), .Y(n7502)
);
OAI222X4TS U7569 ( .A0(n2216), .A1(n8032), .B0(n8084), .B1(n8056), .C0(n8002), .C1(n2222), .Y(n7510) );
NOR2X1TS U7570 ( .A(n8765), .B(n7510), .Y(n7503) );
AOI21X1TS U7571 ( .A0(n7510), .A1(n8765), .B0(n7503), .Y(n6447) );
XNOR2X1TS U7572 ( .A(n7502), .B(n6447), .Y(n6448) );
BUFX3TS U7573 ( .A(n6449), .Y(n6604) );
NAND2X1TS U7574 ( .A(n2431), .B(n6491), .Y(n6456) );
OAI21X1TS U7575 ( .A0(n6453), .A1(n6452), .B0(n6451), .Y(n6493) );
INVX2TS U7576 ( .A(n6493), .Y(n6478) );
INVX2TS U7577 ( .A(n6478), .Y(n6454) );
AOI21X1TS U7578 ( .A0(n2432), .A1(n6491), .B0(n6454), .Y(n6455) );
OAI21X1TS U7579 ( .A0(n6604), .A1(n6456), .B0(n6455), .Y(n6457) );
XOR2X1TS U7580 ( .A(n6457), .B(n7742), .Y(n6458) );
OAI2BB1X1TS U7581 ( .A0N(n8507), .A1N(n6458), .B0(n8506), .Y(n6883) );
AOI22X1TS U7582 ( .A0(n5774), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n6907), .Y(n6459) );
OAI2BB1X1TS U7583 ( .A0N(n6883), .A1N(n2446), .B0(n6459), .Y(n6460) );
AOI21X1TS U7584 ( .A0(n2411), .A1(FPMULT_Add_result[14]), .B0(n6460), .Y(
n6461) );
OAI2BB1X1TS U7585 ( .A0N(n6884), .A1N(n2416), .B0(n6461), .Y(n1531) );
INVX2TS U7586 ( .A(n6491), .Y(n6477) );
NOR2X1TS U7587 ( .A(n6477), .B(n7765), .Y(n6463) );
NAND2X1TS U7588 ( .A(n6603), .B(n6463), .Y(n6465) );
AOI21X1TS U7589 ( .A0(n6609), .A1(n6463), .B0(n6462), .Y(n6464) );
XNOR2X1TS U7590 ( .A(n6466), .B(n7741), .Y(n6467) );
OAI2BB1X1TS U7591 ( .A0N(n2199), .A1N(n6467), .B0(n8512), .Y(n6888) );
NOR2X1TS U7592 ( .A(n6477), .B(n7764), .Y(n6469) );
NAND2X1TS U7593 ( .A(n2431), .B(n6469), .Y(n6471) );
AOI21X1TS U7594 ( .A0(n2432), .A1(n6469), .B0(n6468), .Y(n6470) );
XNOR2X1TS U7595 ( .A(n6472), .B(n7739), .Y(n6473) );
OAI2BB1X1TS U7596 ( .A0N(n2199), .A1N(n6473), .B0(n8511), .Y(n6887) );
AOI22X1TS U7597 ( .A0(n5774), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n6440), .Y(n6474) );
OAI2BB1X1TS U7598 ( .A0N(n6887), .A1N(n2444), .B0(n6474), .Y(n6475) );
AOI21X1TS U7599 ( .A0(n6544), .A1(FPMULT_Add_result[16]), .B0(n6475), .Y(
n6476) );
OAI2BB1X1TS U7600 ( .A0N(n6888), .A1N(n5768), .B0(n6476), .Y(n1533) );
NOR2X1TS U7601 ( .A(n7763), .B(n6477), .Y(n6480) );
NAND2X1TS U7602 ( .A(n2431), .B(n6480), .Y(n6482) );
AOI21X1TS U7603 ( .A0(n6609), .A1(n6480), .B0(n6479), .Y(n6481) );
XNOR2X1TS U7604 ( .A(n6483), .B(n7735), .Y(n6484) );
OAI2BB1X1TS U7605 ( .A0N(n2199), .A1N(n6484), .B0(n8516), .Y(n6891) );
AOI22X1TS U7606 ( .A0(n6540), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n6907), .Y(n6485) );
OAI2BB1X1TS U7607 ( .A0N(n6891), .A1N(n2445), .B0(n6485), .Y(n6486) );
AOI21X1TS U7608 ( .A0(n2411), .A1(FPMULT_Add_result[17]), .B0(n6486), .Y(
n6487) );
OAI2BB1X1TS U7609 ( .A0N(n6887), .A1N(n2416), .B0(n6487), .Y(n1534) );
AOI22X1TS U7610 ( .A0(n6540), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n6539), .Y(n6488) );
OAI2BB1X1TS U7611 ( .A0N(n6888), .A1N(n2446), .B0(n6488), .Y(n6489) );
AOI21X1TS U7612 ( .A0(n6544), .A1(FPMULT_Add_result[15]), .B0(n6489), .Y(
n6490) );
OAI2BB1X1TS U7613 ( .A0N(n6883), .A1N(n5768), .B0(n6490), .Y(n1532) );
NAND2X2TS U7614 ( .A(n7762), .B(n6491), .Y(n6492) );
INVX2TS U7615 ( .A(n6492), .Y(n6496) );
NAND2X1TS U7616 ( .A(n2431), .B(n6496), .Y(n6498) );
NAND2X1TS U7617 ( .A(n7762), .B(n6493), .Y(n6494) );
INVX2TS U7618 ( .A(n6606), .Y(n6495) );
AOI21X1TS U7619 ( .A0(n2432), .A1(n6496), .B0(n6495), .Y(n6497) );
XNOR2X1TS U7620 ( .A(n6499), .B(n2246), .Y(n6500) );
OAI2BB1X1TS U7621 ( .A0N(n2199), .A1N(n6500), .B0(n8509), .Y(n6885) );
NOR2X1TS U7622 ( .A(n6492), .B(n2246), .Y(n6502) );
NAND2X1TS U7623 ( .A(n6502), .B(n2431), .Y(n6504) );
AOI21X1TS U7624 ( .A0(n2432), .A1(n6502), .B0(n6501), .Y(n6503) );
XNOR2X1TS U7625 ( .A(n6505), .B(n7738), .Y(n6506) );
OAI2BB1X1TS U7626 ( .A0N(n2199), .A1N(n6506), .B0(n8514), .Y(n6890) );
INVX2TS U7627 ( .A(n6507), .Y(n6907) );
AOI22X1TS U7628 ( .A0(n6540), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n6440), .Y(n6508) );
OAI2BB1X1TS U7629 ( .A0N(n6890), .A1N(n2445), .B0(n6508), .Y(n6509) );
AOI21X1TS U7630 ( .A0(n2411), .A1(FPMULT_Add_result[19]), .B0(n6509), .Y(
n6510) );
OAI2BB1X1TS U7631 ( .A0N(n6885), .A1N(n2416), .B0(n6510), .Y(n1536) );
NOR2X1TS U7632 ( .A(n6492), .B(n7761), .Y(n6512) );
NAND2X1TS U7633 ( .A(n6512), .B(n2431), .Y(n6514) );
AOI21X1TS U7634 ( .A0(n2432), .A1(n6512), .B0(n6511), .Y(n6513) );
XNOR2X1TS U7635 ( .A(n6515), .B(n7740), .Y(n6516) );
OAI2BB1X1TS U7636 ( .A0N(n2199), .A1N(n6516), .B0(n8510), .Y(n6886) );
AOI22X1TS U7637 ( .A0(n5774), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n6539), .Y(n6517) );
OAI2BB1X1TS U7638 ( .A0N(n6886), .A1N(n2446), .B0(n6517), .Y(n6518) );
AOI21X1TS U7639 ( .A0(n6544), .A1(FPMULT_Add_result[20]), .B0(n6518), .Y(
n6519) );
OAI2BB1X1TS U7640 ( .A0N(n6890), .A1N(n5768), .B0(n6519), .Y(n1537) );
NOR2X1TS U7641 ( .A(n6492), .B(n7760), .Y(n6521) );
NAND2X1TS U7642 ( .A(n6521), .B(n6603), .Y(n6523) );
AOI21X1TS U7643 ( .A0(n6609), .A1(n6521), .B0(n6520), .Y(n6522) );
XNOR2X1TS U7644 ( .A(n6524), .B(n7737), .Y(n6525) );
OAI2BB1X1TS U7645 ( .A0N(n2198), .A1N(n6525), .B0(n8513), .Y(n6889) );
AOI22X1TS U7646 ( .A0(n6540), .A1(n6537), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n6539), .Y(n6526) );
OAI2BB1X1TS U7647 ( .A0N(n6889), .A1N(n2444), .B0(n6526), .Y(n6527) );
AOI21X1TS U7648 ( .A0(n2411), .A1(FPMULT_Add_result[21]), .B0(n6527), .Y(
n6528) );
OAI2BB1X1TS U7649 ( .A0N(n6886), .A1N(n2416), .B0(n6528), .Y(n1538) );
NOR2X1TS U7650 ( .A(n6492), .B(n7759), .Y(n6530) );
NAND2X1TS U7651 ( .A(n6530), .B(n6603), .Y(n6532) );
AOI21X1TS U7652 ( .A0(n6609), .A1(n6530), .B0(n6529), .Y(n6531) );
XNOR2X1TS U7653 ( .A(n6533), .B(n7736), .Y(n6534) );
OAI2BB1X1TS U7654 ( .A0N(n2198), .A1N(n6534), .B0(n8515), .Y(n6903) );
AOI22X1TS U7655 ( .A0(n5774), .A1(n6902), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n6907), .Y(n6535) );
OAI2BB1X1TS U7656 ( .A0N(n6903), .A1N(n2445), .B0(n6535), .Y(n6536) );
AOI21X1TS U7657 ( .A0(n6544), .A1(n6537), .B0(n6536), .Y(n6538) );
OAI2BB1X1TS U7658 ( .A0N(n6889), .A1N(n5768), .B0(n6538), .Y(n1539) );
AOI22X1TS U7659 ( .A0(n5774), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n6440), .Y(n6541) );
OAI2BB1X1TS U7660 ( .A0N(n6885), .A1N(n2444), .B0(n6541), .Y(n6543) );
AOI21X1TS U7661 ( .A0(n6544), .A1(FPMULT_Add_result[18]), .B0(n6543), .Y(
n6545) );
OAI2BB1X1TS U7662 ( .A0N(n6891), .A1N(n2416), .B0(n6545), .Y(n1535) );
NAND2X2TS U7663 ( .A(n6559), .B(n7809), .Y(n7329) );
INVX2TS U7664 ( .A(n7329), .Y(n7309) );
INVX2TS U7665 ( .A(n7323), .Y(n6636) );
AOI22X1TS U7666 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n7325), .B0(n7309),
.B1(n7311), .Y(n6549) );
OAI2BB1X1TS U7667 ( .A0N(n7318), .A1N(n6636), .B0(n7364), .Y(n6656) );
NAND2X1TS U7668 ( .A(n6549), .B(n6656), .Y(n2134) );
BUFX3TS U7669 ( .A(n6559), .Y(n7361) );
BUFX3TS U7670 ( .A(n7424), .Y(n7428) );
NOR2X2TS U7671 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_479_n1), .Y(n7418) );
NAND2X1TS U7672 ( .A(n7418), .B(n8679), .Y(n7421) );
AOI22X1TS U7673 ( .A0(n2211), .A1(n8467), .B0(n2291), .B1(n8466), .Y(n6552)
);
AOI22X1TS U7674 ( .A0(n2293), .A1(n8050), .B0(n2471), .B1(n8049), .Y(n6551)
);
AOI22X1TS U7675 ( .A0(n2210), .A1(n8473), .B0(n2405), .B1(n8472), .Y(n6554)
);
AOI22X1TS U7676 ( .A0(n2375), .A1(n8045), .B0(n2471), .B1(n8048), .Y(n6553)
);
AOI22X1TS U7677 ( .A0(n1810), .A1(n2443), .B0(n1802), .B1(n2396), .Y(n6556)
);
AOI22X1TS U7678 ( .A0(n1806), .A1(n2397), .B0(FPADDSUB_Data_array_SWR_3__25_), .B1(n2381), .Y(n6555) );
NAND2X1TS U7679 ( .A(n6556), .B(n6555), .Y(n7044) );
AOI22X1TS U7680 ( .A0(n1809), .A1(n2443), .B0(n1801), .B1(n2396), .Y(n6558)
);
AOI22X1TS U7681 ( .A0(n1805), .A1(n2398), .B0(n1813), .B1(n2381), .Y(n6557)
);
NAND2X1TS U7682 ( .A(n6558), .B(n6557), .Y(n7045) );
AOI221X1TS U7683 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7044), .B0(n2344),
.B1(n7045), .C0(n7052), .Y(n7556) );
MXI2X1TS U7684 ( .A(n7556), .B(n7914), .S0(n7515), .Y(n1195) );
BUFX3TS U7685 ( .A(n6559), .Y(n7355) );
INVX2TS U7686 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n6568) );
INVX2TS U7687 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n6561) );
NOR2BX1TS U7688 ( .AN(n6564), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n6565)
);
NOR2BX2TS U7689 ( .AN(n6565), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n6566)
);
NAND2BX4TS U7690 ( .AN(n6806), .B(n6566), .Y(n7520) );
CLKBUFX3TS U7691 ( .A(n2348), .Y(n7980) );
CLKBUFX3TS U7692 ( .A(n2418), .Y(n7954) );
CLKBUFX3TS U7693 ( .A(n8546), .Y(n7958) );
CLKBUFX3TS U7694 ( .A(n2348), .Y(n8536) );
BUFX3TS U7695 ( .A(n2348), .Y(n8533) );
CLKBUFX3TS U7696 ( .A(n7983), .Y(n8530) );
BUFX3TS U7697 ( .A(n2470), .Y(n8560) );
BUFX3TS U7698 ( .A(n2470), .Y(n8557) );
CLKBUFX3TS U7699 ( .A(n8594), .Y(n8563) );
BUFX3TS U7700 ( .A(n2470), .Y(n8553) );
BUFX3TS U7701 ( .A(n2470), .Y(n8556) );
CLKBUFX3TS U7702 ( .A(n8547), .Y(n7953) );
BUFX3TS U7703 ( .A(n8529), .Y(n7952) );
INVX2TS U7704 ( .A(n7575), .Y(n8763) );
NAND2X1TS U7705 ( .A(n6943), .B(FPMULT_Add_result[0]), .Y(n6569) );
AOI22X1TS U7706 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n7289), .B1(n8642),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
INVX2TS U7707 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n8282)
);
AOI22X1TS U7708 ( .A0(n6857), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n8526), .Y(n6571) );
OAI21X1TS U7709 ( .A0(n2334), .A1(n6832), .B0(n6571), .Y(n8719) );
AOI22X1TS U7710 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n6857), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n7301), .Y(n6572) );
OAI21X1TS U7711 ( .A0(n7940), .A1(n6832), .B0(n6572), .Y(n8737) );
NAND2X1TS U7712 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6575) );
NAND2X1TS U7713 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n6574) );
INVX2TS U7714 ( .A(n8741), .Y(n8739) );
INVX2TS U7715 ( .A(n8751), .Y(n8744) );
INVX2TS U7716 ( .A(n8745), .Y(n8742) );
INVX2TS U7717 ( .A(n8726), .Y(n8724) );
INVX2TS U7718 ( .A(n8720), .Y(n8718) );
INVX2TS U7719 ( .A(n8716), .Y(n8712) );
INVX2TS U7720 ( .A(n8723), .Y(n8721) );
INVX2TS U7721 ( .A(n8717), .Y(n8715) );
AOI22X1TS U7722 ( .A0(n6882), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n2358), .Y(n6577) );
OAI21X1TS U7723 ( .A0(n7793), .A1(n6855), .B0(n6577), .Y(n8740) );
AOI22X1TS U7724 ( .A0(n6641), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2358), .Y(n6578) );
OAI21X1TS U7725 ( .A0(n7810), .A1(n6855), .B0(n6578), .Y(n8743) );
AOI22X1TS U7726 ( .A0(n6882), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n2358), .Y(n6579) );
OAI21X1TS U7727 ( .A0(n7816), .A1(n6855), .B0(n6579), .Y(n8747) );
AOI22X1TS U7728 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n6641), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n7301), .Y(n6580) );
OAI21X1TS U7729 ( .A0(n7867), .A1(n6855), .B0(n6580), .Y(n8734) );
INVX2TS U7730 ( .A(n8727), .Y(n8729) );
AOI22X1TS U7731 ( .A0(n6576), .A1(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2358), .Y(n6582) );
OAI21X1TS U7732 ( .A0(n6855), .A1(n7821), .B0(n6582), .Y(n8725) );
AOI22X1TS U7733 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n6882), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n7301), .Y(n6583) );
OAI21X1TS U7734 ( .A0(n7823), .A1(n6855), .B0(n6583), .Y(n8728) );
AOI22X1TS U7735 ( .A0(n2489), .A1(n6576), .B0(FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n7301), .Y(n6584) );
OAI21X1TS U7736 ( .A0(n7807), .A1(n6855), .B0(n6584), .Y(n8731) );
AOI22X1TS U7737 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n7820), .B0(n6585), .B1(n8642), .Y(n6586) );
INVX2TS U7738 ( .A(n6588), .Y(overflow_flag) );
NAND2X1TS U7739 ( .A(n6591), .B(n6590), .Y(n6594) );
INVX2TS U7740 ( .A(n6594), .Y(n6592) );
XOR2X1TS U7741 ( .A(n6595), .B(n6594), .Y(n6596) );
AOI22X1TS U7742 ( .A0(n6596), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n7599), .Y(n6597) );
OAI2BB1X1TS U7743 ( .A0N(n6599), .A1N(n6598), .B0(n6597), .Y(n1336) );
INVX2TS U7744 ( .A(n8299), .Y(n6600) );
NAND3X1TS U7745 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n7819), .Y(n7343) );
BUFX3TS U7746 ( .A(n7343), .Y(n7437) );
INVX2TS U7747 ( .A(n7510), .Y(n8757) );
INVX2TS U7748 ( .A(n7477), .Y(n7480) );
NOR2X1TS U7749 ( .A(n6492), .B(n7758), .Y(n6608) );
NAND2X1TS U7750 ( .A(n6608), .B(n6603), .Y(n6605) );
AOI21X1TS U7751 ( .A0(n6609), .A1(n6608), .B0(n6607), .Y(n6610) );
NAND2X1TS U7752 ( .A(n6611), .B(n6610), .Y(n6612) );
XNOR2X1TS U7753 ( .A(n6612), .B(n7734), .Y(n6613) );
OAI31X1TS U7754 ( .A0(n7480), .A1(n7827), .A2(n7791), .B0(n6621), .Y(n1550)
);
INVX2TS U7755 ( .A(n6632), .Y(n7319) );
NAND2X1TS U7756 ( .A(n7309), .B(n7319), .Y(n6640) );
OAI2BB1X1TS U7757 ( .A0N(ack_operation), .A1N(n6624), .B0(n7296), .Y(n6615)
);
NAND2X1TS U7758 ( .A(n6616), .B(n6615), .Y(n6653) );
AOI211X1TS U7759 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n6621), .B0(n7480),
.C0(n7827), .Y(n6622) );
INVX2TS U7760 ( .A(n6622), .Y(n1551) );
BUFX3TS U7761 ( .A(n6661), .Y(n6713) );
AOI22X1TS U7762 ( .A0(n6623), .A1(cordic_result[8]), .B0(n6711), .B1(
mult_result[8]), .Y(n6625) );
AOI22X1TS U7763 ( .A0(n6623), .A1(cordic_result[4]), .B0(n6711), .B1(
mult_result[4]), .Y(n6626) );
AOI22X1TS U7764 ( .A0(n7299), .A1(cordic_result[3]), .B0(n6711), .B1(
mult_result[3]), .Y(n6627) );
AOI22X1TS U7765 ( .A0(n6623), .A1(cordic_result[9]), .B0(n6711), .B1(
mult_result[9]), .Y(n6628) );
AOI22X1TS U7766 ( .A0(n6623), .A1(cordic_result[7]), .B0(n6711), .B1(
mult_result[7]), .Y(n6629) );
AOI22X1TS U7767 ( .A0(n6623), .A1(cordic_result[5]), .B0(n6711), .B1(
mult_result[5]), .Y(n6630) );
AOI22X1TS U7768 ( .A0(n6623), .A1(cordic_result[6]), .B0(n6711), .B1(
mult_result[6]), .Y(n6631) );
NAND2X2TS U7769 ( .A(n7424), .B(FPSENCOS_cont_iter_out[1]), .Y(n7322) );
AOI211X1TS U7770 ( .A0(n7303), .A1(n7790), .B0(n2196), .C0(n7329), .Y(n7316)
);
AOI21X1TS U7771 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n7330), .B0(n7316),
.Y(n6633) );
AOI21X1TS U7772 ( .A0(n7303), .A1(n2196), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n6638) );
AOI22X1TS U7773 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n7325), .B0(n7309),
.B1(n6638), .Y(n6634) );
NOR3X1TS U7774 ( .A(n2196), .B(n2361), .C(n7322), .Y(n6658) );
AOI21X1TS U7775 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n7330), .B0(n6658),
.Y(n6635) );
NAND2X1TS U7776 ( .A(n7364), .B(n2360), .Y(n7327) );
INVX2TS U7777 ( .A(n8730), .Y(n8732) );
AOI22X1TS U7778 ( .A0(n7409), .A1(n6638), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n7330), .Y(n6639) );
INVX2TS U7779 ( .A(n7322), .Y(n7314) );
NAND2X1TS U7780 ( .A(n7314), .B(n7311), .Y(n7317) );
INVX2TS U7781 ( .A(n8733), .Y(n8735) );
NAND2X1TS U7782 ( .A(n7303), .B(n7796), .Y(intadd_479_CI) );
INVX2TS U7783 ( .A(n7327), .Y(n6643) );
AOI22X1TS U7784 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n6643), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n7330), .Y(n6642) );
AOI22X1TS U7785 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n6643), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n7330), .Y(n6644) );
BUFX3TS U7786 ( .A(n7308), .Y(n7337) );
INVX2TS U7787 ( .A(operation[0]), .Y(n6648) );
OAI32X1TS U7788 ( .A0(n7333), .A1(n6648), .A2(n6647), .B0(n7789), .B1(n7337),
.Y(n2082) );
AOI211XLTS U7789 ( .A0(n6945), .A1(n7478), .B0(n6651), .C0(n6650), .Y(n6652)
);
NAND2X1TS U7790 ( .A(n7314), .B(n7319), .Y(n7320) );
NAND2X1TS U7791 ( .A(n7303), .B(n7319), .Y(n6654) );
AOI22X1TS U7792 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n7325), .B0(n7309),
.B1(n6654), .Y(n6655) );
AOI22X1TS U7793 ( .A0(n6623), .A1(cordic_result[2]), .B0(n6624), .B1(
mult_result[2]), .Y(n6657) );
AOI211X1TS U7794 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n7325), .B0(n6659),
.C0(n6658), .Y(n6660) );
OAI31X1TS U7795 ( .A0(n7303), .A1(FPSENCOS_cont_iter_out[3]), .A2(n7329),
.B0(n6660), .Y(n2129) );
BUFX3TS U7796 ( .A(n6661), .Y(n6717) );
AOI22X1TS U7797 ( .A0(cordic_result[27]), .A1(n7294), .B0(n7293), .B1(
mult_result[27]), .Y(n6662) );
AOI22X1TS U7798 ( .A0(n7294), .A1(cordic_result[24]), .B0(n7293), .B1(
mult_result[24]), .Y(n6663) );
AOI22X1TS U7799 ( .A0(n7294), .A1(cordic_result[28]), .B0(n7293), .B1(
mult_result[28]), .Y(n6664) );
AOI22X1TS U7800 ( .A0(cordic_result[26]), .A1(n7294), .B0(n7293), .B1(
mult_result[26]), .Y(n6665) );
AOI22X1TS U7801 ( .A0(cordic_result[31]), .A1(n7294), .B0(n7293), .B1(
mult_result[31]), .Y(n6666) );
AOI22X1TS U7802 ( .A0(n7294), .A1(cordic_result[22]), .B0(n6714), .B1(
mult_result[22]), .Y(n6667) );
INVX2TS U7803 ( .A(n7434), .Y(n8636) );
AOI21X1TS U7804 ( .A0(n7856), .A1(n7799), .B0(n6668), .Y(n6689) );
OAI22X1TS U7805 ( .A0(n7797), .A1(n6669), .B0(n6695), .B1(n2334), .Y(n6670)
);
AOI22X1TS U7806 ( .A0(n6675), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n6674),
.B1(n6673), .Y(n6676) );
INVX1TS U7807 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n7152) );
AOI32X1TS U7808 ( .A0(n2294), .A1(n6676), .A2(n7152), .B0(n6695), .B1(n6676),
.Y(n6677) );
AOI211X1TS U7809 ( .A0(n6679), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n6678),
.C0(n6677), .Y(n6682) );
INVX2TS U7810 ( .A(n6863), .Y(n8609) );
NAND2X1TS U7811 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n6683)
);
AOI22X1TS U7812 ( .A0(n7299), .A1(cordic_result[10]), .B0(n6711), .B1(
mult_result[10]), .Y(n6685) );
AOI22X1TS U7813 ( .A0(n7299), .A1(cordic_result[0]), .B0(n6624), .B1(
mult_result[0]), .Y(n6686) );
AOI22X1TS U7814 ( .A0(n7299), .A1(cordic_result[11]), .B0(n6711), .B1(
mult_result[11]), .Y(n6687) );
AOI22X1TS U7815 ( .A0(n7299), .A1(cordic_result[1]), .B0(n6624), .B1(
mult_result[1]), .Y(n6688) );
INVX2TS U7816 ( .A(n6689), .Y(n6690) );
INVX2TS U7817 ( .A(n6692), .Y(n6694) );
OAI31X1TS U7818 ( .A0(n6695), .A1(n6694), .A2(n2294), .B0(n6693), .Y(n6696)
);
INVX2TS U7819 ( .A(n7377), .Y(n8817) );
INVX2TS U7820 ( .A(n7371), .Y(n8790) );
INVX2TS U7821 ( .A(n7370), .Y(n8793) );
INVX2TS U7822 ( .A(n7398), .Y(n8787) );
INVX2TS U7823 ( .A(n7368), .Y(n8799) );
INVX2TS U7824 ( .A(n7390), .Y(n8828) );
INVX2TS U7825 ( .A(n7391), .Y(n8826) );
INVX2TS U7826 ( .A(n6867), .Y(n8796) );
INVX2TS U7827 ( .A(n7392), .Y(n8830) );
INVX2TS U7828 ( .A(n7393), .Y(n8837) );
INVX2TS U7829 ( .A(n7395), .Y(n8786) );
INVX2TS U7830 ( .A(n7369), .Y(n8802) );
INVX2TS U7831 ( .A(n7397), .Y(n8785) );
INVX2TS U7832 ( .A(n7399), .Y(n8784) );
INVX2TS U7833 ( .A(n7401), .Y(n8782) );
INVX2TS U7834 ( .A(n7403), .Y(n8783) );
INVX2TS U7835 ( .A(n7378), .Y(n8805) );
INVX2TS U7836 ( .A(n7380), .Y(n8815) );
INVX2TS U7837 ( .A(n7381), .Y(n8810) );
INVX2TS U7838 ( .A(n7382), .Y(n8820) );
INVX2TS U7839 ( .A(n7384), .Y(n8813) );
INVX2TS U7840 ( .A(n7386), .Y(n8834) );
INVX2TS U7841 ( .A(n7388), .Y(n8824) );
INVX2TS U7842 ( .A(n7389), .Y(n8832) );
AOI22X1TS U7843 ( .A0(n6715), .A1(cordic_result[18]), .B0(n6714), .B1(
mult_result[18]), .Y(n6703) );
AOI22X1TS U7844 ( .A0(n6715), .A1(cordic_result[13]), .B0(n6714), .B1(
mult_result[13]), .Y(n6704) );
AOI22X1TS U7845 ( .A0(n6715), .A1(cordic_result[15]), .B0(n6714), .B1(
mult_result[15]), .Y(n6705) );
AOI22X1TS U7846 ( .A0(n6715), .A1(cordic_result[14]), .B0(n6714), .B1(
mult_result[14]), .Y(n6706) );
AOI22X1TS U7847 ( .A0(n6715), .A1(cordic_result[16]), .B0(n6714), .B1(
mult_result[16]), .Y(n6707) );
AOI22X1TS U7848 ( .A0(n6715), .A1(cordic_result[17]), .B0(n6714), .B1(
mult_result[17]), .Y(n6708) );
AOI22X1TS U7849 ( .A0(n6715), .A1(cordic_result[20]), .B0(n6714), .B1(
mult_result[20]), .Y(n6709) );
AOI22X1TS U7850 ( .A0(n6715), .A1(cordic_result[19]), .B0(n6714), .B1(
mult_result[19]), .Y(n6710) );
AOI22X1TS U7851 ( .A0(n6715), .A1(cordic_result[12]), .B0(n6711), .B1(
mult_result[12]), .Y(n6712) );
AOI22X1TS U7852 ( .A0(n6715), .A1(cordic_result[21]), .B0(n6714), .B1(
mult_result[21]), .Y(n6716) );
XNOR2X1TS U7853 ( .A(n6724), .B(FPSENCOS_d_ff_Xn[31]), .Y(n6727) );
XNOR2X1TS U7854 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n6720) );
XNOR2X1TS U7855 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n6720),
.Y(n6722) );
NOR2X2TS U7856 ( .A(n6794), .B(n6722), .Y(n6721) );
BUFX3TS U7857 ( .A(n6824), .Y(n6793) );
XOR2X1TS U7858 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n6724), .Y(n6725) );
AOI22X1TS U7859 ( .A0(n6794), .A1(cordic_result[31]), .B0(n6793), .B1(n6725),
.Y(n6726) );
INVX2TS U7860 ( .A(n6778), .Y(n6728) );
INVX2TS U7861 ( .A(n6729), .Y(n1698) );
INVX2TS U7862 ( .A(n6732), .Y(n1735) );
AOI222X1TS U7863 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n6733) );
INVX2TS U7864 ( .A(n6733), .Y(n1737) );
AOI222X1TS U7865 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n6735) );
INVX2TS U7866 ( .A(n6735), .Y(n1736) );
BUFX3TS U7867 ( .A(n6736), .Y(n6772) );
AOI222X1TS U7868 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n6759), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n6737) );
INVX2TS U7869 ( .A(n6737), .Y(n1751) );
AOI222X1TS U7870 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n6738) );
INVX2TS U7871 ( .A(n6738), .Y(n1747) );
AOI222X1TS U7872 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n6739) );
INVX2TS U7873 ( .A(n6739), .Y(n1750) );
AOI222X1TS U7874 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n6740) );
INVX2TS U7875 ( .A(n6740), .Y(n1739) );
AOI222X1TS U7876 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n6741) );
INVX2TS U7877 ( .A(n6741), .Y(n1752) );
AOI222X1TS U7878 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n6742) );
INVX2TS U7879 ( .A(n6742), .Y(n1740) );
AOI222X1TS U7880 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n6743) );
INVX2TS U7881 ( .A(n6743), .Y(n1745) );
AOI222X1TS U7882 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n6744) );
INVX2TS U7883 ( .A(n6744), .Y(n1742) );
AOI222X1TS U7884 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n6745) );
INVX2TS U7885 ( .A(n6745), .Y(n1753) );
AOI222X1TS U7886 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n6746) );
INVX2TS U7887 ( .A(n6746), .Y(n1744) );
AOI222X1TS U7888 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n6747) );
INVX2TS U7889 ( .A(n6747), .Y(n1743) );
AOI222X1TS U7890 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n6748) );
INVX2TS U7891 ( .A(n6748), .Y(n1749) );
AOI222X1TS U7892 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n2407), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n6749) );
INVX2TS U7893 ( .A(n6749), .Y(n1746) );
AOI222X1TS U7894 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n2407), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n6751) );
INVX2TS U7895 ( .A(n6751), .Y(n1748) );
AOI222X1TS U7896 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n6752) );
INVX2TS U7897 ( .A(n6752), .Y(n1738) );
AOI222X1TS U7898 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n6756) );
INVX2TS U7899 ( .A(n6756), .Y(n1741) );
INVX2TS U7900 ( .A(n7413), .Y(n7417) );
AOI222X1TS U7901 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n6757)
);
INVX2TS U7902 ( .A(n6757), .Y(n1764) );
AOI222X1TS U7903 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n6758)
);
INVX2TS U7904 ( .A(n6758), .Y(n1763) );
BUFX3TS U7905 ( .A(n6759), .Y(n7416) );
AOI222X1TS U7906 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n6734), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n7416), .Y(n6760)
);
INVX2TS U7907 ( .A(n6760), .Y(n1766) );
AOI2BB2XLTS U7908 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n7819), .A0N(n7819),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n6762) );
BUFX3TS U7909 ( .A(n7372), .Y(n7449) );
AOI22X1TS U7910 ( .A0(operation[0]), .A1(n7433), .B0(FPADDSUB_intAS), .B1(
n7449), .Y(n6761) );
AOI222X1TS U7911 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n6764)
);
INVX2TS U7912 ( .A(n6764), .Y(n1759) );
AOI222X1TS U7913 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n6765)
);
INVX2TS U7914 ( .A(n6765), .Y(n1758) );
AOI222X1TS U7915 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n6766)
);
INVX2TS U7916 ( .A(n6766), .Y(n1760) );
AOI222X1TS U7917 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n6767)
);
INVX2TS U7918 ( .A(n6767), .Y(n1757) );
AOI222X1TS U7919 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n6768)
);
INVX2TS U7920 ( .A(n6768), .Y(n1761) );
AOI222X1TS U7921 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n7416), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n6769)
);
INVX2TS U7922 ( .A(n6769), .Y(n1765) );
AOI222X1TS U7923 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n6770) );
INVX2TS U7924 ( .A(n6770), .Y(n1754) );
AOI222X1TS U7925 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n6771) );
INVX2TS U7926 ( .A(n6771), .Y(n1756) );
AOI222X1TS U7927 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n6759), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n6773) );
INVX2TS U7928 ( .A(n6773), .Y(n1755) );
AOI222X1TS U7929 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n6776)
);
INVX2TS U7930 ( .A(n6776), .Y(n1762) );
BUFX3TS U7931 ( .A(n6829), .Y(n6827) );
INVX2TS U7932 ( .A(n6777), .Y(n1717) );
BUFX3TS U7933 ( .A(n6829), .Y(n6802) );
BUFX3TS U7934 ( .A(n6824), .Y(n6801) );
INVX2TS U7935 ( .A(n6779), .Y(n1707) );
INVX2TS U7936 ( .A(n6780), .Y(n1713) );
INVX2TS U7937 ( .A(n6781), .Y(n1705) );
INVX2TS U7938 ( .A(n6782), .Y(n1706) );
INVX2TS U7939 ( .A(n6783), .Y(n1710) );
INVX2TS U7940 ( .A(n6784), .Y(n1700) );
INVX2TS U7941 ( .A(n6785), .Y(n1709) );
INVX2TS U7942 ( .A(n6786), .Y(n1704) );
INVX2TS U7943 ( .A(n6787), .Y(n1714) );
INVX2TS U7944 ( .A(n6788), .Y(n1718) );
INVX2TS U7945 ( .A(n6789), .Y(n1703) );
INVX2TS U7946 ( .A(n6790), .Y(n1702) );
INVX2TS U7947 ( .A(n6791), .Y(n1715) );
INVX2TS U7948 ( .A(n6792), .Y(n1701) );
INVX2TS U7949 ( .A(n6795), .Y(n1699) );
INVX2TS U7950 ( .A(n6797), .Y(n1708) );
INVX2TS U7951 ( .A(n6798), .Y(n1712) );
INVX2TS U7952 ( .A(n6799), .Y(n1716) );
INVX2TS U7953 ( .A(n6803), .Y(n1711) );
AND4X1TS U7954 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n6804) );
OAI2BB1X2TS U7955 ( .A0N(n2311), .A1N(n6806), .B0(n7629), .Y(n6807) );
INVX4TS U7956 ( .A(n6807), .Y(n7521) );
NAND2X1TS U7957 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(n7629), .Y(n6810) );
NAND2X1TS U7958 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n7629), .Y(n6812) );
NAND2X1TS U7959 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n7629), .Y(n6813) );
INVX2TS U7960 ( .A(n6818), .Y(n1728) );
INVX2TS U7961 ( .A(n6819), .Y(n1724) );
INVX2TS U7962 ( .A(n6820), .Y(n1719) );
INVX2TS U7963 ( .A(n6821), .Y(n1720) );
INVX2TS U7964 ( .A(n6822), .Y(n1723) );
INVX2TS U7965 ( .A(n6823), .Y(n1725) );
INVX2TS U7966 ( .A(n6825), .Y(n1727) );
INVX2TS U7967 ( .A(n6826), .Y(n1721) );
INVX2TS U7968 ( .A(n6828), .Y(n1722) );
INVX2TS U7969 ( .A(n6830), .Y(n1726) );
AOI21X1TS U7970 ( .A0(n6840), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n8526),
.Y(n6831) );
OAI21X1TS U7971 ( .A0(n6832), .A1(n7152), .B0(n6831), .Y(n8714) );
AOI22X1TS U7972 ( .A0(n2211), .A1(n8455), .B0(n2406), .B1(n8454), .Y(n6835)
);
AOI22X1TS U7973 ( .A0(n2345), .A1(n8050), .B0(n6851), .B1(n8446), .Y(n6834)
);
AOI22X1TS U7974 ( .A0(n2212), .A1(n8458), .B0(n2291), .B1(n8457), .Y(n6837)
);
AOI22X1TS U7975 ( .A0(n2375), .A1(n8049), .B0(n2471), .B1(n8045), .Y(n6836)
);
INVX2TS U7976 ( .A(n8746), .Y(n8522) );
INVX2TS U7977 ( .A(n8748), .Y(n8521) );
AOI22X1TS U7978 ( .A0(n6838), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n2358), .Y(n6839) );
OAI21X1TS U7979 ( .A0(n7797), .A1(n6840), .B0(n6839), .Y(n8722) );
AOI22X1TS U7980 ( .A0(n2211), .A1(n8421), .B0(n2406), .B1(n8420), .Y(n6842)
);
AOI22X1TS U7981 ( .A0(n2292), .A1(n8016), .B0(n8118), .B1(n8055), .Y(n6841)
);
OAI211X1TS U7982 ( .A0(n8046), .A1(n8058), .B0(n6842), .C0(n6841), .Y(n1790)
);
AOI22X1TS U7983 ( .A0(n2212), .A1(n8433), .B0(n2406), .B1(n8432), .Y(n6844)
);
AOI22X1TS U7984 ( .A0(n2293), .A1(n8027), .B0(n8118), .B1(n8430), .Y(n6843)
);
OAI211X1TS U7985 ( .A0(n8046), .A1(n8059), .B0(n6844), .C0(n6843), .Y(n1791)
);
AOI22X1TS U7986 ( .A0(n2212), .A1(n8428), .B0(n2291), .B1(n8427), .Y(n6846)
);
AOI22X1TS U7987 ( .A0(n2375), .A1(n8054), .B0(n2471), .B1(n8053), .Y(n6845)
);
AOI22X1TS U7988 ( .A0(n2211), .A1(n8435), .B0(n2406), .B1(n8434), .Y(n6848)
);
AOI22X1TS U7989 ( .A0(n2345), .A1(n8054), .B0(n6851), .B1(n8459), .Y(n6847)
);
AOI22X1TS U7990 ( .A0(n2211), .A1(n8425), .B0(n2291), .B1(n8424), .Y(n6850)
);
AOI22X1TS U7991 ( .A0(n2375), .A1(n8053), .B0(n2471), .B1(n8052), .Y(n6849)
);
AOI22X1TS U7992 ( .A0(n2212), .A1(n8423), .B0(n2291), .B1(n8422), .Y(n6853)
);
AOI22X1TS U7993 ( .A0(n2293), .A1(n8055), .B0(n2471), .B1(n8054), .Y(n6852)
);
OAI211X1TS U7994 ( .A0(n8499), .A1(n2468), .B0(n6853), .C0(n6852), .Y(n1792)
);
NAND2X1TS U7995 ( .A(n7285), .B(n7302), .Y(n7278) );
NOR2X2TS U7996 ( .A(ready_add_subt), .B(n7278), .Y(n7307) );
OAI21XLTS U7997 ( .A0(n7307), .A1(n7819), .B0(FPSENCOS_cont_var_out[1]), .Y(
n6856) );
AOI21X1TS U7998 ( .A0(n6858), .A1(n8714), .B0(n6857), .Y(n8711) );
OR4X2TS U7999 ( .A(n1638), .B(n1632), .C(n1628), .D(n1639), .Y(n8065) );
AOI22X1TS U8000 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n7787), .B0(n7568),
.B1(n7449), .Y(n8710) );
BUFX3TS U8001 ( .A(n6862), .Y(n7624) );
AOI22X1TS U8002 ( .A0(n7577), .A1(n7637), .B0(n6861), .B1(n7624), .Y(n8836)
);
BUFX3TS U8003 ( .A(n7372), .Y(n7431) );
AOI22X1TS U8004 ( .A0(Data_2[22]), .A1(n7432), .B0(n7577), .B1(n7431), .Y(
n8702) );
OAI21X1TS U8005 ( .A0(n8011), .A1(n2217), .B0(n8129), .Y(n7533) );
BUFX3TS U8006 ( .A(n6862), .Y(n7537) );
AOI22X1TS U8007 ( .A0(n7578), .A1(n8610), .B0(n7533), .B1(n7537), .Y(n8771)
);
OAI21X1TS U8008 ( .A0(n8011), .A1(n2222), .B0(n8116), .Y(n7659) );
AOI22X1TS U8009 ( .A0(n7578), .A1(n7655), .B0(n7659), .B1(n7654), .Y(n8827)
);
AOI22X1TS U8010 ( .A0(Data_2[19]), .A1(n7432), .B0(n7578), .B1(n7431), .Y(
n8699) );
OAI21X1TS U8011 ( .A0(n8010), .A1(n2221), .B0(n8095), .Y(n7662) );
AOI22X1TS U8012 ( .A0(n7560), .A1(n7655), .B0(n7662), .B1(n7654), .Y(n8831)
);
AOI22X1TS U8013 ( .A0(Data_2[18]), .A1(n7432), .B0(n7560), .B1(n7431), .Y(
n8698) );
OAI21X1TS U8014 ( .A0(n8013), .A1(n2220), .B0(n8115), .Y(n7646) );
BUFX3TS U8015 ( .A(n6864), .Y(n7636) );
AOI22X1TS U8016 ( .A0(n7562), .A1(n7637), .B0(n7646), .B1(n7636), .Y(n8818)
);
OAI21X1TS U8017 ( .A0(n8013), .A1(n2215), .B0(n8130), .Y(n7547) );
AOI22X1TS U8018 ( .A0(n7562), .A1(n7633), .B0(n7547), .B1(n6862), .Y(n8777)
);
AOI22X1TS U8019 ( .A0(Data_2[16]), .A1(n7404), .B0(n7562), .B1(n7431), .Y(
n8696) );
AOI22X1TS U8020 ( .A0(n7608), .A1(n7633), .B0(n6865), .B1(n6862), .Y(n8788)
);
BUFX3TS U8021 ( .A(n7372), .Y(n7430) );
AOI22X1TS U8022 ( .A0(Data_2[3]), .A1(n7429), .B0(n7608), .B1(n7430), .Y(
n8683) );
OAI21X1TS U8023 ( .A0(n8034), .A1(n2221), .B0(n8109), .Y(n7647) );
AOI22X1TS U8024 ( .A0(n7563), .A1(n7637), .B0(n7647), .B1(n7636), .Y(n8819)
);
OAI21X1TS U8025 ( .A0(n8034), .A1(n2447), .B0(n8126), .Y(n7545) );
AOI22X1TS U8026 ( .A0(n7563), .A1(n7633), .B0(n7545), .B1(n6864), .Y(n8776)
);
AOI22X1TS U8027 ( .A0(Data_2[13]), .A1(n7432), .B0(n7563), .B1(n7431), .Y(
n8693) );
OAI21X1TS U8028 ( .A0(n8035), .A1(n2222), .B0(n8094), .Y(n7643) );
AOI22X1TS U8029 ( .A0(n7565), .A1(n7637), .B0(n7643), .B1(n7636), .Y(n8814)
);
OAI21X1TS U8030 ( .A0(n8035), .A1(n2216), .B0(n8120), .Y(n7553) );
AOI22X1TS U8031 ( .A0(n7565), .A1(n7633), .B0(n7553), .B1(n6862), .Y(n8779)
);
AOI22X1TS U8032 ( .A0(Data_2[11]), .A1(n7429), .B0(n7565), .B1(n7430), .Y(
n8691) );
AOI22X1TS U8033 ( .A0(n6867), .A1(n6863), .B0(n6866), .B1(n7624), .Y(n8794)
);
AOI22X1TS U8034 ( .A0(Data_2[7]), .A1(n7429), .B0(n6867), .B1(n7430), .Y(
n8687) );
OAI21X1TS U8035 ( .A0(n8036), .A1(n2221), .B0(n8110), .Y(n7641) );
AOI22X1TS U8036 ( .A0(n7564), .A1(n7637), .B0(n7641), .B1(n7636), .Y(n8812)
);
AOI22X1TS U8037 ( .A0(Data_2[14]), .A1(n7432), .B0(n7564), .B1(n7431), .Y(
n8694) );
OAI21X1TS U8038 ( .A0(n8042), .A1(n2216), .B0(n8131), .Y(n7630) );
AOI22X1TS U8039 ( .A0(n7581), .A1(n6863), .B0(n7630), .B1(n7636), .Y(n8806)
);
OAI21X1TS U8040 ( .A0(n8042), .A1(n2222), .B0(n8117), .Y(n7632) );
AOI22X1TS U8041 ( .A0(n7581), .A1(n7637), .B0(n7632), .B1(n7636), .Y(n8807)
);
AOI22X1TS U8042 ( .A0(Data_2[5]), .A1(n7429), .B0(n7581), .B1(n7430), .Y(
n8685) );
AOI22X1TS U8043 ( .A0(Data_2[24]), .A1(n7433), .B0(n7575), .B1(n7449), .Y(
n8704) );
AOI22X1TS U8044 ( .A0(Data_2[25]), .A1(n7433), .B0(n7571), .B1(n7449), .Y(
n8705) );
AOI22X1TS U8045 ( .A0(Data_2[26]), .A1(n7433), .B0(n7580), .B1(n7449), .Y(
n8706) );
OAI21X1TS U8046 ( .A0(n8003), .A1(n2222), .B0(n8102), .Y(n7660) );
AOI22X1TS U8047 ( .A0(n7576), .A1(n7655), .B0(n7660), .B1(n7654), .Y(n8829)
);
AOI22X1TS U8048 ( .A0(Data_2[21]), .A1(n7432), .B0(n7576), .B1(n7431), .Y(
n8701) );
OAI21X1TS U8049 ( .A0(n8005), .A1(n2220), .B0(n8114), .Y(n7651) );
AOI22X1TS U8050 ( .A0(n7582), .A1(n7655), .B0(n7651), .B1(n7654), .Y(n8822)
);
AOI22X1TS U8051 ( .A0(Data_2[4]), .A1(n7429), .B0(n7582), .B1(n7430), .Y(
n8684) );
OAI21X1TS U8052 ( .A0(n8006), .A1(n2221), .B0(n8113), .Y(n7649) );
AOI22X1TS U8053 ( .A0(n7584), .A1(n7637), .B0(n7649), .B1(n7654), .Y(n8821)
);
OAI21X1TS U8054 ( .A0(n8006), .A1(n2217), .B0(n8140), .Y(n7543) );
AOI22X1TS U8055 ( .A0(n7584), .A1(n7633), .B0(n7543), .B1(n7537), .Y(n8775)
);
AOI22X1TS U8056 ( .A0(Data_2[6]), .A1(n7429), .B0(n7584), .B1(n7430), .Y(
n8686) );
OAI21X1TS U8057 ( .A0(n8007), .A1(n2222), .B0(n8093), .Y(n7644) );
AOI22X1TS U8058 ( .A0(n7583), .A1(n7637), .B0(n7644), .B1(n7636), .Y(n8816)
);
AOI22X1TS U8059 ( .A0(Data_2[8]), .A1(n7429), .B0(n7583), .B1(n7430), .Y(
n8688) );
OAI21X1TS U8060 ( .A0(n8014), .A1(n2220), .B0(n8104), .Y(n7640) );
AOI22X1TS U8061 ( .A0(n7566), .A1(n7637), .B0(n7640), .B1(n7636), .Y(n8811)
);
OAI21X1TS U8062 ( .A0(n8014), .A1(n2217), .B0(n8137), .Y(n7558) );
AOI22X1TS U8063 ( .A0(n7633), .A1(n7566), .B0(n7558), .B1(n6862), .Y(n8781)
);
AOI22X1TS U8064 ( .A0(Data_2[10]), .A1(n7429), .B0(n7566), .B1(n7430), .Y(
n8690) );
AOI22X1TS U8065 ( .A0(n7611), .A1(n6863), .B0(n6868), .B1(n6862), .Y(n8791)
);
BUFX3TS U8066 ( .A(n6869), .Y(n7402) );
AOI22X1TS U8067 ( .A0(Data_2[2]), .A1(n7429), .B0(n7611), .B1(n7402), .Y(
n8682) );
AOI22X1TS U8068 ( .A0(n7617), .A1(n6863), .B0(n6870), .B1(n7624), .Y(n8797)
);
AOI22X1TS U8069 ( .A0(Data_2[0]), .A1(n7404), .B0(n7617), .B1(n7402), .Y(
n8680) );
AOI22X1TS U8070 ( .A0(n7620), .A1(n6863), .B0(n6871), .B1(n7624), .Y(n8800)
);
AOI22X1TS U8071 ( .A0(Data_2[1]), .A1(n7404), .B0(n7620), .B1(n7402), .Y(
n8681) );
OAI21X1TS U8072 ( .A0(n8037), .A1(n2215), .B0(n8135), .Y(n7623) );
AOI22X1TS U8073 ( .A0(n7625), .A1(n6863), .B0(n7623), .B1(n7624), .Y(n8803)
);
AOI22X1TS U8074 ( .A0(n6873), .A1(n8243), .B0(n6872), .B1(n8242), .Y(n6874)
);
AOI22X1TS U8075 ( .A0(Data_1[31]), .A1(n7404), .B0(n7602), .B1(n7402), .Y(
n8678) );
AOI22X1TS U8076 ( .A0(n7569), .A1(n8608), .B0(n7511), .B1(n6864), .Y(n8758)
);
OAI21X1TS U8077 ( .A0(n8033), .A1(n2220), .B0(n8080), .Y(n7666) );
AOI22X1TS U8078 ( .A0(n7561), .A1(n7655), .B0(n7666), .B1(n7654), .Y(n8833)
);
AOI22X1TS U8079 ( .A0(Data_2[15]), .A1(n7432), .B0(n7561), .B1(n7431), .Y(
n8695) );
INVX2TS U8080 ( .A(n1641), .Y(n6875) );
NOR2BX1TS U8081 ( .AN(n6879), .B(n6878), .Y(n8063) );
NAND2X1TS U8082 ( .A(n6955), .B(n6880), .Y(n8626) );
AOI22X1TS U8083 ( .A0(n6641), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n6881),
.B1(n8636), .Y(n8753) );
NAND2X1TS U8084 ( .A(n6955), .B(n6883), .Y(n8624) );
NAND2X1TS U8085 ( .A(n7253), .B(n6884), .Y(n8625) );
NAND2X1TS U8086 ( .A(n7216), .B(n6885), .Y(n8620) );
NAND2X1TS U8087 ( .A(n8524), .B(n6886), .Y(n8618) );
NAND2X1TS U8088 ( .A(n8524), .B(n6887), .Y(n8622) );
NAND2X1TS U8089 ( .A(n8524), .B(n6888), .Y(n8623) );
NAND2X1TS U8090 ( .A(n7253), .B(n6889), .Y(n8617) );
NAND2X1TS U8091 ( .A(n8525), .B(n6890), .Y(n8619) );
NAND2X1TS U8092 ( .A(n8525), .B(n6903), .Y(n8614) );
NAND2X1TS U8093 ( .A(n8525), .B(n6891), .Y(n8621) );
NAND2X1TS U8094 ( .A(n7216), .B(n6892), .Y(n8628) );
NOR2BX1TS U8095 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6894) );
XOR2X1TS U8096 ( .A(n7806), .B(n6894), .Y(DP_OP_26J211_126_1325_n14) );
NOR2BX1TS U8097 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6895) );
XOR2X1TS U8098 ( .A(n7806), .B(n6895), .Y(DP_OP_26J211_126_1325_n15) );
NOR2BX1TS U8099 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6896) );
XOR2X1TS U8100 ( .A(n7806), .B(n6896), .Y(DP_OP_26J211_126_1325_n16) );
NOR2BX1TS U8101 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6897) );
XOR2X1TS U8102 ( .A(n7806), .B(n6897), .Y(DP_OP_26J211_126_1325_n17) );
XOR2X1TS U8103 ( .A(n7806), .B(n3193), .Y(DP_OP_26J211_126_1325_n18) );
MXI2X1TS U8104 ( .A(n6903), .B(n6902), .S0(FPMULT_FSM_selector_C), .Y(n6904)
);
AOI21X1TS U8105 ( .A0(n6905), .A1(n6904), .B0(n6907), .Y(n6906) );
INVX2TS U8106 ( .A(n7827), .Y(n6921) );
ADDHXLTS U8107 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n6923), .CO(n6920),
.S(n6924) );
ADDHXLTS U8108 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n6925), .CO(n6923),
.S(n6926) );
ADDHXLTS U8109 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n6929), .CO(n6927),
.S(n6930) );
ADDHXLTS U8110 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n6933), .CO(n6931),
.S(n6934) );
XOR2X1TS U8111 ( .A(add_x_246_A_2_), .B(n6941), .Y(n6942) );
AOI2BB2XLTS U8112 ( .B0(add_x_246_A_1_), .B1(n7786), .A0N(n7786), .A1N(
add_x_246_A_1_), .Y(n6944) );
NAND2X1TS U8113 ( .A(n7477), .B(n7854), .Y(n1691) );
NOR3BX1TS U8114 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n6946) );
XOR2X1TS U8115 ( .A(n6984), .B(n6946), .Y(n6980) );
OAI2BB1X1TS U8116 ( .A0N(FPMULT_Op_MY[29]), .A1N(n7791), .B0(n3154), .Y(
n6947) );
XOR2X1TS U8117 ( .A(n6984), .B(n6947), .Y(n6958) );
OAI2BB1X1TS U8118 ( .A0N(FPMULT_Op_MY[28]), .A1N(n7791), .B0(n3154), .Y(
n6948) );
XOR2X1TS U8119 ( .A(n6984), .B(n6948), .Y(n6961) );
OAI2BB1X1TS U8120 ( .A0N(FPMULT_Op_MY[27]), .A1N(n7791), .B0(n3154), .Y(
n6949) );
XOR2X1TS U8121 ( .A(n6984), .B(n6949), .Y(n6965) );
OAI2BB1X1TS U8122 ( .A0N(FPMULT_Op_MY[26]), .A1N(n7791), .B0(n3154), .Y(
n6950) );
XOR2X1TS U8123 ( .A(n6984), .B(n6950), .Y(n6968) );
OAI2BB1X1TS U8124 ( .A0N(FPMULT_Op_MY[25]), .A1N(n7791), .B0(n3154), .Y(
n6951) );
XOR2X1TS U8125 ( .A(n6984), .B(n6951), .Y(n6971) );
OAI2BB1X1TS U8126 ( .A0N(FPMULT_Op_MY[24]), .A1N(n7791), .B0(n3154), .Y(
n6952) );
XOR2X1TS U8127 ( .A(n6984), .B(n6952), .Y(n6974) );
XOR2X1TS U8128 ( .A(n6984), .B(n6954), .Y(n6975) );
CMPR32X2TS U8129 ( .A(n6958), .B(n6957), .C(n6956), .CO(n6978), .S(n7100) );
CMPR32X2TS U8130 ( .A(n6961), .B(n6960), .C(n6959), .CO(n6956), .S(n7099) );
CMPR32X2TS U8131 ( .A(n6965), .B(n6964), .C(n6963), .CO(n6959), .S(n7098) );
CMPR32X2TS U8132 ( .A(n6968), .B(n6967), .C(n6966), .CO(n6963), .S(n7097) );
CMPR32X2TS U8133 ( .A(n6971), .B(n6970), .C(n6969), .CO(n6966), .S(n7096) );
CMPR32X2TS U8134 ( .A(n6974), .B(n6973), .C(n6972), .CO(n6969), .S(n7095) );
CMPR32X2TS U8135 ( .A(n6980), .B(n6979), .C(n6978), .CO(n6982), .S(n7103) );
CMPR32X2TS U8136 ( .A(n2427), .B(n6983), .C(n6982), .CO(n6986), .S(n7105) );
INVX2TS U8137 ( .A(n6984), .Y(n6985) );
XNOR2X1TS U8138 ( .A(n6986), .B(n6985), .Y(n6987) );
BUFX3TS U8139 ( .A(n6989), .Y(n7517) );
BUFX3TS U8140 ( .A(n6989), .Y(n6990) );
INVX2TS U8141 ( .A(n1810), .Y(n6992) );
OAI22X1TS U8142 ( .A0(n6992), .A1(n7012), .B0(n2341), .B1(n6991), .Y(n6993)
);
AOI211X2TS U8143 ( .A0(n2373), .A1(n1806), .B0(n7034), .C0(n6993), .Y(n7055)
);
AOI22X1TS U8144 ( .A0(n1802), .A1(n2381), .B0(n1794), .B1(n2398), .Y(n6995)
);
AOI22X1TS U8145 ( .A0(n1798), .A1(n6178), .B0(n1790), .B1(n2396), .Y(n6994)
);
OAI211X1TS U8146 ( .A0(n7055), .A1(n2340), .B0(n6995), .C0(n6994), .Y(n7079)
);
AOI211X1TS U8147 ( .A0(n2404), .A1(n7079), .B0(n7031), .C0(n6997), .Y(n7522)
);
MXI2X1TS U8148 ( .A(n7522), .B(n7868), .S0(n7598), .Y(n1183) );
INVX2TS U8149 ( .A(n1811), .Y(n7043) );
AOI22X1TS U8150 ( .A0(n1799), .A1(n6178), .B0(n1791), .B1(n2395), .Y(n7000)
);
AOI22X1TS U8151 ( .A0(n1803), .A1(n6180), .B0(n1795), .B1(n2397), .Y(n6999)
);
OAI211X1TS U8152 ( .A0(n7058), .A1(n7050), .B0(n7000), .C0(n6999), .Y(n7076)
);
AOI21X2TS U8153 ( .A0(n2373), .A1(n1812), .B0(n7005), .Y(n7074) );
AOI211X1TS U8154 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7076), .B0(n7031),
.C0(n7001), .Y(n7530) );
MXI2X1TS U8155 ( .A(n7530), .B(n7861), .S0(n7515), .Y(n1184) );
INVX2TS U8156 ( .A(n1812), .Y(n7039) );
OAI21X1TS U8157 ( .A0(n7039), .A1(n7012), .B0(n7011), .Y(n7002) );
AOI21X2TS U8158 ( .A0(n1808), .A1(n2373), .B0(n7002), .Y(n7062) );
AOI22X1TS U8159 ( .A0(n1800), .A1(n6178), .B0(n1792), .B1(n2395), .Y(n7004)
);
AOI22X1TS U8160 ( .A0(n1804), .A1(n6180), .B0(n1796), .B1(n2397), .Y(n7003)
);
OAI211X1TS U8161 ( .A0(n7062), .A1(n2340), .B0(n7004), .C0(n7003), .Y(n7073)
);
AOI21X2TS U8162 ( .A0(n2373), .A1(n1811), .B0(n7005), .Y(n7071) );
AOI211X1TS U8163 ( .A0(n2404), .A1(n7073), .B0(n7031), .C0(n7006), .Y(n7534)
);
MXI2X1TS U8164 ( .A(n7534), .B(n7869), .S0(n7061), .Y(n1185) );
OAI21X1TS U8165 ( .A0(n7007), .A1(n7012), .B0(n7011), .Y(n7008) );
AOI21X2TS U8166 ( .A0(n1809), .A1(n2372), .B0(n7008), .Y(n7065) );
AOI22X1TS U8167 ( .A0(n1801), .A1(n6178), .B0(n1793), .B1(n2395), .Y(n7010)
);
AOI22X1TS U8168 ( .A0(n1805), .A1(n6180), .B0(n1797), .B1(n2397), .Y(n7009)
);
OAI211X1TS U8169 ( .A0(n7065), .A1(n7050), .B0(n7010), .C0(n7009), .Y(n7070)
);
OAI21X1TS U8170 ( .A0(n2341), .A1(n7012), .B0(n7011), .Y(n7013) );
AOI21X2TS U8171 ( .A0(n1810), .A1(n2373), .B0(n7013), .Y(n7068) );
AOI211X1TS U8172 ( .A0(n2404), .A1(n7070), .B0(n7031), .C0(n7014), .Y(n7532)
);
MXI2X1TS U8173 ( .A(n7532), .B(n7862), .S0(n7061), .Y(n1186) );
AOI22X1TS U8174 ( .A0(n1802), .A1(n6178), .B0(n1794), .B1(n2395), .Y(n7016)
);
AOI22X1TS U8175 ( .A0(n1806), .A1(n2381), .B0(n1798), .B1(n2397), .Y(n7015)
);
OAI211X1TS U8176 ( .A0(n7068), .A1(n2340), .B0(n7016), .C0(n7015), .Y(n7067)
);
AOI211X1TS U8177 ( .A0(n2404), .A1(n7067), .B0(n7031), .C0(n7017), .Y(n7528)
);
MXI2X1TS U8178 ( .A(n7528), .B(n7870), .S0(n7515), .Y(n1187) );
AOI22X1TS U8179 ( .A0(n1807), .A1(n2381), .B0(n1799), .B1(n2397), .Y(n7019)
);
AOI22X1TS U8180 ( .A0(n1803), .A1(n6178), .B0(n1795), .B1(n2395), .Y(n7018)
);
OAI211X1TS U8181 ( .A0(n7071), .A1(n7050), .B0(n7019), .C0(n7018), .Y(n7064)
);
AOI211X1TS U8182 ( .A0(n2404), .A1(n7064), .B0(n7031), .C0(n7020), .Y(n7536)
);
MXI2X1TS U8183 ( .A(n7536), .B(n7863), .S0(n7061), .Y(n1188) );
AOI22X1TS U8184 ( .A0(n1808), .A1(n6180), .B0(n1800), .B1(n2397), .Y(n7022)
);
AOI22X1TS U8185 ( .A0(n1804), .A1(n6178), .B0(n1796), .B1(n2395), .Y(n7021)
);
OAI211X1TS U8186 ( .A0(n7074), .A1(n2340), .B0(n7022), .C0(n7021), .Y(n7060)
);
AOI211X1TS U8187 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7060), .B0(n7031),
.C0(n7023), .Y(n7546) );
MXI2X1TS U8188 ( .A(n7546), .B(n7871), .S0(n7061), .Y(n1189) );
AOI22X1TS U8189 ( .A0(n1809), .A1(n2381), .B0(n1801), .B1(n2398), .Y(n7025)
);
AOI22X1TS U8190 ( .A0(n1805), .A1(n6178), .B0(n1797), .B1(n2395), .Y(n7024)
);
OAI211X1TS U8191 ( .A0(n7077), .A1(n2340), .B0(n7025), .C0(n7024), .Y(n7057)
);
AOI211X1TS U8192 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7057), .B0(n7031),
.C0(n7026), .Y(n7525) );
MXI2X1TS U8193 ( .A(n7525), .B(n7864), .S0(n7515), .Y(n1190) );
AOI22X1TS U8194 ( .A0(n1810), .A1(n6180), .B0(n1802), .B1(n2397), .Y(n7028)
);
AOI22X1TS U8195 ( .A0(n1806), .A1(n6178), .B0(n1798), .B1(n2395), .Y(n7027)
);
OAI211X1TS U8196 ( .A0(n7081), .A1(n2340), .B0(n7028), .C0(n7027), .Y(n7054)
);
AOI211X1TS U8197 ( .A0(n2404), .A1(n7054), .B0(n7031), .C0(n7030), .Y(n7554)
);
MXI2X1TS U8198 ( .A(n7554), .B(n7872), .S0(n7086), .Y(n1191) );
AOI21X1TS U8199 ( .A0(n1803), .A1(n2398), .B0(n7052), .Y(n7033) );
AOI22X1TS U8200 ( .A0(n1807), .A1(n2443), .B0(n1799), .B1(n2396), .Y(n7032)
);
OAI211X1TS U8201 ( .A0(n7043), .A1(n7038), .B0(n7033), .C0(n7032), .Y(n7048)
);
INVX2TS U8202 ( .A(n2443), .Y(n7042) );
NOR2X1TS U8203 ( .A(n7052), .B(n7034), .Y(n7041) );
AOI22X1TS U8204 ( .A0(n1808), .A1(n2398), .B0(n1804), .B1(n2396), .Y(n7035)
);
OAI211X1TS U8205 ( .A0(n7039), .A1(n7042), .B0(n7041), .C0(n7035), .Y(n7049)
);
AOI22X1TS U8206 ( .A0(n2404), .A1(n7048), .B0(n7049), .B1(n2344), .Y(n7544)
);
MXI2X1TS U8207 ( .A(n7544), .B(n7865), .S0(n7515), .Y(n1192) );
AOI21X1TS U8208 ( .A0(n1804), .A1(n2398), .B0(n7052), .Y(n7037) );
AOI22X1TS U8209 ( .A0(n1808), .A1(n2443), .B0(n1800), .B1(n2396), .Y(n7036)
);
OAI211X1TS U8210 ( .A0(n7039), .A1(n7038), .B0(n7037), .C0(n7036), .Y(n7046)
);
AOI22X1TS U8211 ( .A0(n1807), .A1(n2398), .B0(n1803), .B1(n2396), .Y(n7040)
);
OAI211X1TS U8212 ( .A0(n7043), .A1(n7042), .B0(n7041), .C0(n7040), .Y(n7047)
);
AOI22X1TS U8213 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7046), .B0(n7047),
.B1(n2344), .Y(n7559) );
MXI2X1TS U8214 ( .A(n7559), .B(n7873), .S0(n7061), .Y(n1193) );
AOI221X1TS U8215 ( .A0(n2404), .A1(n7045), .B0(n2344), .B1(n7044), .C0(n7052), .Y(n7552) );
MXI2X1TS U8216 ( .A(n7552), .B(n7866), .S0(n7515), .Y(n1194) );
AOI22X1TS U8217 ( .A0(n2404), .A1(n7047), .B0(n7046), .B1(n2344), .Y(n7621)
);
MXI2X1TS U8218 ( .A(n7621), .B(n7941), .S0(n7086), .Y(n1196) );
AOI22X1TS U8219 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7049), .B0(n7048),
.B1(n2344), .Y(n7549) );
MXI2X1TS U8220 ( .A(n7549), .B(n7944), .S0(n7515), .Y(n1197) );
AOI211X1TS U8221 ( .A0(n7054), .A1(n7084), .B0(n7053), .C0(n7082), .Y(n7612)
);
MXI2X1TS U8222 ( .A(n7612), .B(n7945), .S0(n7061), .Y(n1198) );
AOI211X1TS U8223 ( .A0(n7057), .A1(n7084), .B0(n7056), .C0(n7082), .Y(n7542)
);
BUFX3TS U8224 ( .A(n7061), .Y(n7086) );
MXI2X1TS U8225 ( .A(n7542), .B(n7946), .S0(n7086), .Y(n1199) );
AOI211X1TS U8226 ( .A0(n7060), .A1(n7084), .B0(n7059), .C0(n7082), .Y(n7628)
);
MXI2X1TS U8227 ( .A(n7628), .B(n7942), .S0(n7061), .Y(n1200) );
AOI211X1TS U8228 ( .A0(n7064), .A1(n7084), .B0(n7063), .C0(n7082), .Y(n7540)
);
MXI2X1TS U8229 ( .A(n7540), .B(n7947), .S0(n7086), .Y(n1201) );
AOI211X1TS U8230 ( .A0(n7067), .A1(n7084), .B0(n7066), .C0(n7082), .Y(n7606)
);
MXI2X1TS U8231 ( .A(n7606), .B(n7948), .S0(n7086), .Y(n1202) );
AOI211X1TS U8232 ( .A0(n7070), .A1(n7084), .B0(n7069), .C0(n7082), .Y(n7609)
);
MXI2X1TS U8233 ( .A(n7609), .B(n7949), .S0(n7086), .Y(n1203) );
AOI211X1TS U8234 ( .A0(n7073), .A1(n7084), .B0(n7072), .C0(n7082), .Y(n7618)
);
MXI2X1TS U8235 ( .A(n7618), .B(n7950), .S0(n7086), .Y(n1204) );
AOI211X1TS U8236 ( .A0(n7076), .A1(n7084), .B0(n7075), .C0(n7082), .Y(n7615)
);
MXI2X1TS U8237 ( .A(n7615), .B(n7951), .S0(n7086), .Y(n1205) );
AOI211X1TS U8238 ( .A0(n7079), .A1(n2344), .B0(n7078), .C0(n7082), .Y(n7080)
);
MXI2X1TS U8239 ( .A(n7080), .B(n7943), .S0(n7086), .Y(n1206) );
AOI211X1TS U8240 ( .A0(n7085), .A1(n2344), .B0(n7083), .C0(n7082), .Y(n7087)
);
MXI2X1TS U8241 ( .A(n7087), .B(n7805), .S0(n7086), .Y(n1207) );
NAND2X1TS U8242 ( .A(n7090), .B(n7875), .Y(n7091) );
OAI22X1TS U8243 ( .A0(n7105), .A1(n7104), .B0(n7480), .B1(n7874), .Y(n1516)
);
NAND2X1TS U8244 ( .A(n7107), .B(n7106), .Y(n7110) );
INVX2TS U8245 ( .A(n7110), .Y(n7108) );
XNOR2X1TS U8246 ( .A(n7109), .B(n7108), .Y(n7114) );
XNOR2X1TS U8247 ( .A(n7111), .B(n7110), .Y(n7112) );
AOI22X1TS U8248 ( .A0(n7112), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n7159), .Y(n7113) );
OAI2BB1X1TS U8249 ( .A0N(n7201), .A1N(n7114), .B0(n7113), .Y(n1337) );
INVX2TS U8250 ( .A(n7115), .Y(n7117) );
NAND2X1TS U8251 ( .A(n7117), .B(n7116), .Y(n7120) );
INVX2TS U8252 ( .A(n7120), .Y(n7118) );
XOR2X1TS U8253 ( .A(n7121), .B(n7120), .Y(n7122) );
AOI22X1TS U8254 ( .A0(n7122), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n7159), .Y(n7123) );
OAI2BB1X1TS U8255 ( .A0N(n7201), .A1N(n7124), .B0(n7123), .Y(n1338) );
INVX2TS U8256 ( .A(n7125), .Y(n7190) );
INVX2TS U8257 ( .A(n7126), .Y(n7129) );
INVX2TS U8258 ( .A(n7127), .Y(n7128) );
NAND2X1TS U8259 ( .A(n7131), .B(n7130), .Y(n7136) );
INVX2TS U8260 ( .A(n7136), .Y(n7132) );
XNOR2X1TS U8261 ( .A(n7133), .B(n7132), .Y(n7141) );
XNOR2X1TS U8262 ( .A(n7137), .B(n7136), .Y(n7139) );
AOI22X1TS U8263 ( .A0(n7139), .A1(n7138), .B0(n2489), .B1(n7159), .Y(n7140)
);
OAI2BB1X1TS U8264 ( .A0N(n7201), .A1N(n7141), .B0(n7140), .Y(n1340) );
NAND2X1TS U8265 ( .A(n7145), .B(n7144), .Y(n7148) );
INVX2TS U8266 ( .A(n7148), .Y(n7146) );
XNOR2X1TS U8267 ( .A(n7147), .B(n7146), .Y(n7151) );
XOR2X1TS U8268 ( .A(n7180), .B(n7148), .Y(n7149) );
AOI22X1TS U8269 ( .A0(n7149), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n7159), .Y(n7150) );
OAI2BB1X1TS U8270 ( .A0N(n7201), .A1N(n7151), .B0(n7150), .Y(n1341) );
MXI2X1TS U8271 ( .A(n7152), .B(n7805), .S0(n7600), .Y(n1351) );
INVX2TS U8272 ( .A(n7153), .Y(n7155) );
NAND2X1TS U8273 ( .A(n7155), .B(n7154), .Y(n7158) );
INVX2TS U8274 ( .A(n7158), .Y(n7156) );
XOR2X1TS U8275 ( .A(n7158), .B(n7165), .Y(n7160) );
AOI22X1TS U8276 ( .A0(n7160), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n7159), .Y(n7161) );
OAI2BB1X1TS U8277 ( .A0N(n7201), .A1N(n7162), .B0(n7161), .Y(n1348) );
XNOR2X1TS U8278 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n7805), .Y(n7164) );
AOI22X1TS U8279 ( .A0(n7197), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n7196), .Y(n7163) );
OAI2BB1X1TS U8280 ( .A0N(n7201), .A1N(n7164), .B0(n7163), .Y(n1350) );
OR2X1TS U8281 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n7166) );
CLKAND2X2TS U8282 ( .A(n7166), .B(n7165), .Y(n7168) );
XOR2XLTS U8283 ( .A(n7168), .B(n7167), .Y(n7170) );
AOI22X1TS U8284 ( .A0(n7168), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n7196), .Y(n7169) );
OAI2BB1X1TS U8285 ( .A0N(n7201), .A1N(n7170), .B0(n7169), .Y(n1349) );
NAND2X1TS U8286 ( .A(n7175), .B(n7174), .Y(n7181) );
INVX2TS U8287 ( .A(n7181), .Y(n7176) );
XNOR2X1TS U8288 ( .A(n7177), .B(n7176), .Y(n7185) );
XNOR2X1TS U8289 ( .A(n7182), .B(n7181), .Y(n7183) );
AOI22X1TS U8290 ( .A0(n7183), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n7196), .Y(n7184) );
OAI2BB1X1TS U8291 ( .A0N(n7201), .A1N(n7185), .B0(n7184), .Y(n1339) );
INVX2TS U8292 ( .A(n7186), .Y(n7188) );
NAND2X1TS U8293 ( .A(n7188), .B(n7187), .Y(n7194) );
INVX2TS U8294 ( .A(n7194), .Y(n7189) );
XNOR2X1TS U8295 ( .A(n7195), .B(n7194), .Y(n7198) );
AOI22X1TS U8296 ( .A0(n7198), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n7196), .Y(n7199) );
OAI2BB1X1TS U8297 ( .A0N(n7201), .A1N(n7200), .B0(n7199), .Y(n1342) );
INVX2TS U8298 ( .A(n7218), .Y(n7220) );
NAND2X1TS U8299 ( .A(n7220), .B(n7219), .Y(n7222) );
XOR2X1TS U8300 ( .A(n7222), .B(n7221), .Y(n7223) );
INVX2TS U8301 ( .A(n7224), .Y(n7230) );
INVX2TS U8302 ( .A(n7229), .Y(n7225) );
NAND2X1TS U8303 ( .A(n7225), .B(n7228), .Y(n7226) );
XOR2X1TS U8304 ( .A(n7230), .B(n7226), .Y(n7227) );
INVX2TS U8305 ( .A(n7231), .Y(n7233) );
NAND2X1TS U8306 ( .A(n7233), .B(n7232), .Y(n7234) );
XNOR2X1TS U8307 ( .A(n7235), .B(n7234), .Y(n7236) );
INVX2TS U8308 ( .A(n7237), .Y(n7242) );
XNOR2X1TS U8309 ( .A(n7238), .B(n7243), .Y(n7239) );
INVX2TS U8310 ( .A(n7240), .Y(n7241) );
AOI21X1TS U8311 ( .A0(n7243), .A1(n7242), .B0(n7241), .Y(n7248) );
INVX2TS U8312 ( .A(n7244), .Y(n7246) );
NAND2X1TS U8313 ( .A(n7246), .B(n7245), .Y(n7247) );
XOR2X1TS U8314 ( .A(n7248), .B(n7247), .Y(n7249) );
NAND2X1TS U8315 ( .A(n2818), .B(n7251), .Y(n7252) );
NOR4X1TS U8316 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n7261) );
NOR4X1TS U8317 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n7260) );
NOR4X1TS U8318 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n7258) );
NOR4X1TS U8319 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n7256) );
NOR4X1TS U8320 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n7255) );
AND4X1TS U8321 ( .A(n7258), .B(n7257), .C(n7256), .D(n7255), .Y(n7259) );
NOR4BX1TS U8322 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n7266) );
NAND4XLTS U8323 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n7263) );
NAND4XLTS U8324 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n7262) );
OR3X1TS U8325 ( .A(n8638), .B(n7263), .C(n7262), .Y(n7267) );
NOR3X1TS U8326 ( .A(dataB[25]), .B(dataB[31]), .C(n7267), .Y(n7264) );
NOR4X1TS U8327 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[26]), .D(dataA[28]),
.Y(n7270) );
NOR4X1TS U8328 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n7269) );
NOR4BX1TS U8329 ( .AN(operation_reg[1]), .B(dataA[31]), .C(operation_reg[0]),
.D(n8638), .Y(n7268) );
NOR2X1TS U8330 ( .A(operation_reg[1]), .B(n7267), .Y(n7275) );
NAND4XLTS U8331 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n7271) );
OAI31X1TS U8332 ( .A0(n7273), .A1(n7272), .A2(n7271), .B0(dataB[27]), .Y(
n7274) );
OAI2BB2XLTS U8333 ( .B0(n7277), .B1(n7276), .A0N(n7275), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NOR3X1TS U8334 ( .A(n7426), .B(n7337), .C(n7278), .Y(n7279) );
OAI22X1TS U8335 ( .A0(n7281), .A1(n7280), .B0(n7283), .B1(n7282), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U8336 ( .AN(n7283), .B(n7282), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U8337 ( .A0(n7442), .A1(n7286), .B0(n7285), .B1(n7284), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NAND2X1TS U8338 ( .A(n7289), .B(n7288), .Y(n2193) );
AOI22X1TS U8339 ( .A0(cordic_result[30]), .A1(n7294), .B0(n7293), .B1(
mult_result[30]), .Y(n7290) );
OAI2BB1X1TS U8340 ( .A0N(n7297), .A1N(result_add_subt[30]), .B0(n7290), .Y(
op_result[30]) );
AOI22X1TS U8341 ( .A0(cordic_result[29]), .A1(n7294), .B0(n7293), .B1(
mult_result[29]), .Y(n7291) );
OAI2BB1X1TS U8342 ( .A0N(n7297), .A1N(result_add_subt[29]), .B0(n7291), .Y(
op_result[29]) );
AOI22X1TS U8343 ( .A0(cordic_result[25]), .A1(n7294), .B0(n7293), .B1(
mult_result[25]), .Y(n7292) );
OAI2BB1X1TS U8344 ( .A0N(n7297), .A1N(result_add_subt[25]), .B0(n7292), .Y(
op_result[25]) );
AOI22X1TS U8345 ( .A0(cordic_result[23]), .A1(n7294), .B0(n7293), .B1(
mult_result[23]), .Y(n7295) );
OAI2BB1X1TS U8346 ( .A0N(n7297), .A1N(result_add_subt[23]), .B0(n7295), .Y(
op_result[23]) );
AOI22X1TS U8347 ( .A0(n7297), .A1(ready_add_subt), .B0(n6624), .B1(n7296),
.Y(n7298) );
OAI2BB1X1TS U8348 ( .A0N(n7300), .A1N(n7299), .B0(n7298), .Y(operation_ready) );
AOI22X1TS U8349 ( .A0(n8644), .A1(n7654), .B0(n7661), .B1(n8643), .Y(n2149)
);
AOI22X1TS U8350 ( .A0(n8644), .A1(n7661), .B0(n7658), .B1(n8643), .Y(n2148)
);
AOI22X1TS U8351 ( .A0(n8644), .A1(n7599), .B0(n7301), .B1(n8643), .Y(n2145)
);
AOI22X1TS U8352 ( .A0(n7304), .A1(n7303), .B0(n2361), .B1(n7302), .Y(n2143)
);
NAND2X1TS U8353 ( .A(n2196), .B(n7305), .Y(n7306) );
XNOR2X1TS U8354 ( .A(FPSENCOS_cont_iter_out[3]), .B(n7306), .Y(n2140) );
BUFX3TS U8355 ( .A(n7308), .Y(n7331) );
AOI22X1TS U8356 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n7325), .B0(n7309),
.B1(n7313), .Y(n7310) );
NAND2X1TS U8357 ( .A(n7310), .B(n7317), .Y(n2130) );
AOI22X1TS U8358 ( .A0(n7409), .A1(n7311), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n7330), .Y(n7312) );
NAND2X1TS U8359 ( .A(n7312), .B(n7320), .Y(n2128) );
AOI22X1TS U8360 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n7325), .B0(n7314),
.B1(n7313), .Y(n7315) );
OAI221XLTS U8361 ( .A0(n7364), .A1(n7912), .B0(n7354), .B1(n7318), .C0(n7317), .Y(n2124) );
BUFX3TS U8362 ( .A(n7364), .Y(n7422) );
OAI221XLTS U8363 ( .A0(n7364), .A1(n7913), .B0(n7354), .B1(n7321), .C0(n7320), .Y(n2120) );
AOI22X1TS U8364 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n7325), .B0(n7324),
.B1(n7323), .Y(n7328) );
AOI32X1TS U8365 ( .A0(n7329), .A1(n7328), .A2(n7327), .B0(n2196), .B1(n7328),
.Y(n2117) );
BUFX3TS U8366 ( .A(n7308), .Y(n7335) );
INVX2TS U8367 ( .A(n7334), .Y(n7336) );
INVX2TS U8368 ( .A(n7345), .Y(n7351) );
BUFX3TS U8369 ( .A(n7339), .Y(n7439) );
INVX2TS U8370 ( .A(n7439), .Y(n7440) );
BUFX3TS U8371 ( .A(n7340), .Y(n7348) );
INVX2TS U8372 ( .A(n7348), .Y(n7341) );
INVX2TS U8373 ( .A(n7339), .Y(n7342) );
INVX2TS U8374 ( .A(n7348), .Y(n7346) );
INVX2TS U8375 ( .A(n7339), .Y(n7347) );
INVX2TS U8376 ( .A(n7345), .Y(n7344) );
BUFX3TS U8377 ( .A(n7339), .Y(n7349) );
BUFX3TS U8378 ( .A(n7340), .Y(n7350) );
INVX2TS U8379 ( .A(n7345), .Y(n7438) );
INVX2TS U8380 ( .A(n7348), .Y(n7352) );
INVX2TS U8381 ( .A(n7439), .Y(n7446) );
BUFX3TS U8382 ( .A(n7339), .Y(n7445) );
BUFX3TS U8383 ( .A(n7437), .Y(n7436) );
BUFX3TS U8384 ( .A(n7340), .Y(n7450) );
INVX2TS U8385 ( .A(n7450), .Y(n7451) );
BUFX3TS U8386 ( .A(n7424), .Y(n7410) );
OA22X1TS U8387 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n7426), .Y(n2005) );
OA22X1TS U8388 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n8611), .Y(n2003) );
OA22X1TS U8389 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n8611), .Y(n2001) );
OA22X1TS U8390 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n8611), .Y(n1997) );
OA22X1TS U8391 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n8611), .Y(n1995) );
OA22X1TS U8392 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n8611), .Y(n1993) );
INVX2TS U8393 ( .A(n7413), .Y(n7367) );
AO22X1TS U8394 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n6759), .Y(n1991) );
AO22X1TS U8395 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n6759), .Y(n1989) );
OA22X1TS U8396 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n8611), .Y(n1987) );
BUFX3TS U8397 ( .A(n7413), .Y(n7356) );
OA22X1TS U8398 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n7356), .Y(n1983) );
OA22X1TS U8399 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n8611), .Y(n1981) );
OA22X1TS U8400 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n7356), .Y(n1979) );
OA22X1TS U8401 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n7356), .Y(n1975) );
OA22X1TS U8402 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n7356), .Y(n1973) );
AO22X1TS U8403 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n6759), .Y(n1971) );
OA22X1TS U8404 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n7356), .Y(n1969) );
OA22X1TS U8405 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n7356), .Y(n1967) );
BUFX3TS U8406 ( .A(n2407), .Y(n7405) );
OA22X1TS U8407 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n7356), .Y(n1960) );
OA22X1TS U8408 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n7356), .Y(n1959) );
OA22X1TS U8409 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n7356), .Y(n1958) );
OA22X1TS U8410 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n6730), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n7356), .Y(n1957) );
OA22X1TS U8411 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n7426), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n6730), .Y(n1956) );
OA22X1TS U8412 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n7413), .Y(n1955) );
NOR2X1TS U8413 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_480_n1), .Y(n7359) );
AOI21X1TS U8414 ( .A0(intadd_480_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n7359),
.Y(n7358) );
OR3X1TS U8415 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_480_n1), .Y(n7362) );
NOR2X1TS U8416 ( .A(FPSENCOS_d_ff2_X[29]), .B(n7362), .Y(n7365) );
AOI21X1TS U8417 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n7362), .B0(n7365), .Y(
n7363) );
BUFX3TS U8418 ( .A(n7364), .Y(n7444) );
XOR2X1TS U8419 ( .A(FPSENCOS_d_ff2_X[30]), .B(n7365), .Y(n7366) );
AOI22X1TS U8420 ( .A0(n7433), .A1(Data_1[0]), .B0(n7368), .B1(n7372), .Y(
n8647) );
AOI22X1TS U8421 ( .A0(Data_1[1]), .A1(n7433), .B0(n7369), .B1(n7372), .Y(
n8648) );
AOI22X1TS U8422 ( .A0(Data_1[2]), .A1(n7385), .B0(n7370), .B1(n7372), .Y(
n8649) );
AOI22X1TS U8423 ( .A0(Data_1[3]), .A1(n7385), .B0(n7371), .B1(n7372), .Y(
n8650) );
AOI22X1TS U8424 ( .A0(Data_1[4]), .A1(n7385), .B0(n7373), .B1(n7372), .Y(
n8651) );
BUFX3TS U8425 ( .A(n6869), .Y(n7383) );
AOI22X1TS U8426 ( .A0(Data_1[5]), .A1(n7374), .B0(n7375), .B1(n7383), .Y(
n8652) );
AOI22X1TS U8427 ( .A0(Data_1[6]), .A1(n7374), .B0(n7376), .B1(n7383), .Y(
n8653) );
AOI22X1TS U8428 ( .A0(Data_1[7]), .A1(n7374), .B0(n7614), .B1(n7383), .Y(
n8654) );
AOI22X1TS U8429 ( .A0(Data_1[8]), .A1(n7374), .B0(n7377), .B1(n7383), .Y(
n8655) );
AOI22X1TS U8430 ( .A0(Data_1[9]), .A1(n7385), .B0(n7378), .B1(n7383), .Y(
n8656) );
AOI22X1TS U8431 ( .A0(Data_1[10]), .A1(n7385), .B0(n7379), .B1(n7383), .Y(
n8657) );
AOI22X1TS U8432 ( .A0(Data_1[11]), .A1(n7374), .B0(n7380), .B1(n7383), .Y(
n8658) );
AOI22X1TS U8433 ( .A0(Data_1[12]), .A1(n7374), .B0(n7381), .B1(n7383), .Y(
n8659) );
AOI22X1TS U8434 ( .A0(Data_1[13]), .A1(n7374), .B0(n7382), .B1(n7383), .Y(
n8660) );
AOI22X1TS U8435 ( .A0(Data_1[14]), .A1(n7374), .B0(n7384), .B1(n7383), .Y(
n8661) );
BUFX3TS U8436 ( .A(n6869), .Y(n7394) );
AOI22X1TS U8437 ( .A0(Data_1[15]), .A1(n7396), .B0(n7386), .B1(n7394), .Y(
n8662) );
AOI22X1TS U8438 ( .A0(Data_1[16]), .A1(n7396), .B0(n7387), .B1(n7394), .Y(
n8663) );
AOI22X1TS U8439 ( .A0(Data_1[17]), .A1(n7396), .B0(n7388), .B1(n7394), .Y(
n8664) );
AOI22X1TS U8440 ( .A0(Data_1[18]), .A1(n7396), .B0(n7389), .B1(n7394), .Y(
n8665) );
AOI22X1TS U8441 ( .A0(Data_1[19]), .A1(n7396), .B0(n7390), .B1(n7394), .Y(
n8666) );
AOI22X1TS U8442 ( .A0(Data_1[20]), .A1(n7396), .B0(n7391), .B1(n7394), .Y(
n8667) );
AOI22X1TS U8443 ( .A0(Data_1[21]), .A1(n7396), .B0(n7392), .B1(n7394), .Y(
n8668) );
AOI22X1TS U8444 ( .A0(Data_1[22]), .A1(n7396), .B0(n7393), .B1(n7394), .Y(
n8669) );
AOI22X1TS U8445 ( .A0(Data_1[23]), .A1(n7396), .B0(gt_x_74_A_23_), .B1(n7394), .Y(n8670) );
AOI22X1TS U8446 ( .A0(Data_1[24]), .A1(n7396), .B0(n7395), .B1(n7394), .Y(
n8671) );
AOI22X1TS U8447 ( .A0(Data_1[25]), .A1(n7404), .B0(n7397), .B1(n7402), .Y(
n8672) );
AOI22X1TS U8448 ( .A0(Data_1[26]), .A1(n7404), .B0(n7398), .B1(n7402), .Y(
n8673) );
AOI22X1TS U8449 ( .A0(Data_1[27]), .A1(n7404), .B0(n7399), .B1(n7402), .Y(
n8674) );
AOI22X1TS U8450 ( .A0(Data_1[28]), .A1(n7404), .B0(n7400), .B1(n7402), .Y(
n8675) );
AOI22X1TS U8451 ( .A0(Data_1[29]), .A1(n7404), .B0(n7401), .B1(n7402), .Y(
n8676) );
AOI22X1TS U8452 ( .A0(Data_1[30]), .A1(n7404), .B0(n7403), .B1(n7402), .Y(
n8677) );
AOI22X1TS U8453 ( .A0(n7440), .A1(n2343), .B0(n7804), .B1(n7439), .Y(n1910)
);
BUFX3TS U8454 ( .A(n2407), .Y(n7411) );
INVX2TS U8455 ( .A(n7413), .Y(n7415) );
BUFX3TS U8456 ( .A(n2407), .Y(n7414) );
AOI21X1TS U8457 ( .A0(intadd_479_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n7418),
.Y(n7419) );
AOI21X1TS U8458 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n7421), .B0(n7420), .Y(
n7423) );
OAI22X1TS U8459 ( .A0(n7426), .A1(n7878), .B0(n7804), .B1(n7425), .Y(n1847)
);
AOI22X1TS U8460 ( .A0(Data_2[9]), .A1(n7429), .B0(n7625), .B1(n7430), .Y(
n8689) );
AOI22X1TS U8461 ( .A0(Data_2[12]), .A1(n7432), .B0(n7638), .B1(n7430), .Y(
n8692) );
AOI22X1TS U8462 ( .A0(Data_2[17]), .A1(n7432), .B0(n7652), .B1(n7431), .Y(
n8697) );
AOI22X1TS U8463 ( .A0(Data_2[20]), .A1(n7432), .B0(n7656), .B1(n7431), .Y(
n8700) );
AOI22X1TS U8464 ( .A0(Data_2[23]), .A1(n7433), .B0(gt_x_74_B_23_), .B1(n7449), .Y(n8703) );
AOI22X1TS U8465 ( .A0(Data_2[27]), .A1(n7433), .B0(n7569), .B1(n7449), .Y(
n8707) );
AOI22X1TS U8466 ( .A0(Data_2[28]), .A1(n7433), .B0(n7570), .B1(n7449), .Y(
n8708) );
AOI22X1TS U8467 ( .A0(Data_2[29]), .A1(n7433), .B0(n7567), .B1(n7449), .Y(
n8709) );
OAI22X1TS U8468 ( .A0(n8711), .A1(n7435), .B0(n7434), .B1(n2341), .Y(n1814)
);
AOI22X1TS U8469 ( .A0(n7447), .A1(n8159), .B0(n8017), .B1(n8158), .Y(n7448)
);
NAND2X1TS U8470 ( .A(n8295), .B(n7448), .Y(n7594) );
AOI22X1TS U8471 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n7787), .B0(n7594),
.B1(n7449), .Y(n8754) );
AOI22X1TS U8472 ( .A0(n7451), .A1(n2343), .B0(n7882), .B1(n7450), .Y(n1729)
);
NOR4X1TS U8473 ( .A(FPMULT_Op_MY[22]), .B(n3860), .C(
DP_OP_496J211_122_3540_n1462), .D(DP_OP_496J211_122_3540_n778), .Y(
n7453) );
INVX2TS U8474 ( .A(n7455), .Y(n7456) );
NAND4XLTS U8475 ( .A(n7457), .B(n7453), .C(n7915), .D(n7456), .Y(n7476) );
AND4X1TS U8476 ( .A(n8482), .B(n8483), .C(n7803), .D(n8484), .Y(n7461) );
NOR4BBX1TS U8477 ( .AN(n8486), .BN(n8487), .C(n8485), .D(n8518), .Y(n7460)
);
INVX2TS U8478 ( .A(n7458), .Y(n7459) );
NAND4XLTS U8479 ( .A(n7916), .B(n7461), .C(n7460), .D(n7459), .Y(n7475) );
NOR4X1TS U8480 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[25]), .D(FPMULT_Op_MX[23]), .Y(n7466) );
NOR4BX1TS U8481 ( .AN(n8285), .B(DP_OP_496J211_122_3540_n1502), .C(
FPMULT_Op_MX[19]), .D(FPMULT_Op_MX[20]), .Y(n7465) );
INVX2TS U8482 ( .A(n7462), .Y(n7463) );
NAND4XLTS U8483 ( .A(n7466), .B(n7465), .C(n7464), .D(n7463), .Y(n7474) );
AND4X1TS U8484 ( .A(n8489), .B(n8490), .C(n7877), .D(n8342), .Y(n7472) );
AND4X1TS U8485 ( .A(n2275), .B(n8340), .C(n7467), .D(n8286), .Y(n7471) );
NAND3BXLTS U8486 ( .AN(n7468), .B(n8479), .C(n8480), .Y(n7469) );
INVX2TS U8487 ( .A(n7469), .Y(n7470) );
NAND4XLTS U8488 ( .A(n8632), .B(n7472), .C(n7471), .D(n7470), .Y(n7473) );
OA22X1TS U8489 ( .A0(n7476), .A1(n7475), .B0(n7474), .B1(n7473), .Y(n7479)
);
AOI22X1TS U8490 ( .A0(n7480), .A1(n7479), .B0(n7478), .B1(n7477), .Y(n1626)
);
INVX2TS U8491 ( .A(n7488), .Y(n7481) );
INVX2TS U8492 ( .A(n7487), .Y(n7493) );
INVX2TS U8493 ( .A(n7487), .Y(n7483) );
OA22X1TS U8494 ( .A0(FPMULT_exp_oper_result[0]), .A1(n7488), .B0(n7485),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U8495 ( .A0(FPMULT_exp_oper_result[1]), .A1(n7486), .B0(n7485),
.B1(mult_result[24]), .Y(n1491) );
OA22X1TS U8496 ( .A0(FPMULT_exp_oper_result[2]), .A1(n7486), .B0(n7485),
.B1(mult_result[25]), .Y(n1490) );
OA22X1TS U8497 ( .A0(FPMULT_exp_oper_result[3]), .A1(n7488), .B0(n7485),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U8498 ( .A0(FPMULT_exp_oper_result[4]), .A1(n7486), .B0(n7485),
.B1(mult_result[27]), .Y(n1488) );
OA22X1TS U8499 ( .A0(FPMULT_exp_oper_result[5]), .A1(n7486), .B0(n7485),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U8500 ( .A0(FPMULT_exp_oper_result[6]), .A1(n7486), .B0(n7487),
.B1(mult_result[29]), .Y(n1486) );
OA22X1TS U8501 ( .A0(FPMULT_exp_oper_result[7]), .A1(n7488), .B0(n7487),
.B1(mult_result[30]), .Y(n1485) );
OAI2BB1X1TS U8502 ( .A0N(mult_result[31]), .A1N(n7493), .B0(n7492), .Y(n1483) );
AOI21X1TS U8503 ( .A0(n7507), .A1(n8762), .B0(n7494), .Y(n7495) );
XNOR2X1TS U8504 ( .A(n7496), .B(n7495), .Y(n7497) );
OAI22X1TS U8505 ( .A0(n7503), .A1(n7502), .B0(n7501), .B1(n8757), .Y(n7505)
);
OAI21X1TS U8506 ( .A0(n8009), .A1(n2217), .B0(n8123), .Y(n7518) );
XNOR2X1TS U8507 ( .A(n7518), .B(n7511), .Y(n7504) );
XOR2X1TS U8508 ( .A(n7505), .B(n7504), .Y(n7506) );
OAI21X1TS U8509 ( .A0(n8091), .A1(n2222), .B0(n8090), .Y(n7513) );
AOI22X1TS U8510 ( .A0(n7570), .A1(n8608), .B0(n7513), .B1(n6864), .Y(n8759)
);
OAI21X1TS U8511 ( .A0(n8089), .A1(n2220), .B0(n8088), .Y(n7514) );
AOI22X1TS U8512 ( .A0(n7567), .A1(n8608), .B0(n7514), .B1(n6864), .Y(n8760)
);
OAI21X1TS U8513 ( .A0(n8087), .A1(n2221), .B0(n8086), .Y(n7516) );
AOI22X1TS U8514 ( .A0(n7568), .A1(n8608), .B0(n7516), .B1(n7537), .Y(n8761)
);
BUFX3TS U8515 ( .A(n7634), .Y(n7526) );
INVX2TS U8516 ( .A(n7663), .Y(n7648) );
INVX2TS U8517 ( .A(n7661), .Y(n7539) );
AOI22X1TS U8518 ( .A0(n7569), .A1(n8610), .B0(n7518), .B1(n7537), .Y(n8766)
);
OAI22X1TS U8519 ( .A0(n8612), .A1(n7523), .B0(n7522), .B1(n2413), .Y(n1410)
);
OAI21X1TS U8520 ( .A0(n8004), .A1(n2217), .B0(n8124), .Y(n7524) );
AOI22X1TS U8521 ( .A0(n7577), .A1(n8610), .B0(n7524), .B1(n7537), .Y(n8767)
);
OAI22X1TS U8522 ( .A0(n8612), .A1(n7828), .B0(n7525), .B1(n2374), .Y(n1407)
);
OAI21X1TS U8523 ( .A0(n8033), .A1(n2215), .B0(n8097), .Y(n7527) );
AOI22X1TS U8524 ( .A0(n7561), .A1(n8610), .B0(n7527), .B1(n7537), .Y(n8768)
);
OAI22X1TS U8525 ( .A0(n7557), .A1(n7829), .B0(n7528), .B1(n7627), .Y(n1404)
);
OAI21X1TS U8526 ( .A0(n8010), .A1(n2216), .B0(n8119), .Y(n7529) );
AOI22X1TS U8527 ( .A0(n7560), .A1(n8610), .B0(n7529), .B1(n7537), .Y(n8769)
);
BUFX3TS U8528 ( .A(n7634), .Y(n7550) );
OAI22X1TS U8529 ( .A0(n7557), .A1(n7830), .B0(n7530), .B1(n2374), .Y(n1401)
);
OAI21X1TS U8530 ( .A0(n8003), .A1(n2215), .B0(n8134), .Y(n7531) );
AOI22X1TS U8531 ( .A0(n7576), .A1(n8610), .B0(n7531), .B1(n7537), .Y(n8770)
);
OAI22X1TS U8532 ( .A0(n7557), .A1(n7831), .B0(n7532), .B1(n2374), .Y(n1398)
);
OAI22X1TS U8533 ( .A0(n7557), .A1(n7832), .B0(n7534), .B1(n2374), .Y(n1395)
);
OAI21X1TS U8534 ( .A0(n7999), .A1(n2216), .B0(n8099), .Y(n7535) );
AOI22X1TS U8535 ( .A0(n7656), .A1(n8610), .B0(n7535), .B1(n7537), .Y(n8772)
);
OAI22X1TS U8536 ( .A0(n7557), .A1(n7833), .B0(n7536), .B1(n2374), .Y(n1392)
);
OAI21X1TS U8537 ( .A0(n8012), .A1(n2217), .B0(n8098), .Y(n7538) );
AOI22X1TS U8538 ( .A0(n7652), .A1(n8610), .B0(n7538), .B1(n7537), .Y(n8773)
);
OAI22X1TS U8539 ( .A0(n7557), .A1(n7834), .B0(n7540), .B1(n2374), .Y(n1389)
);
OAI21X1TS U8540 ( .A0(n8005), .A1(n2215), .B0(n8139), .Y(n7541) );
AOI22X1TS U8541 ( .A0(n7582), .A1(n7633), .B0(n7541), .B1(n6864), .Y(n8774)
);
INVX2TS U8542 ( .A(n7661), .Y(n7605) );
OAI22X1TS U8543 ( .A0(n7557), .A1(n7835), .B0(n7542), .B1(n7627), .Y(n1386)
);
OAI22X1TS U8544 ( .A0(n7557), .A1(n7836), .B0(n7544), .B1(n7627), .Y(n1383)
);
OAI22X1TS U8545 ( .A0(n7557), .A1(n7837), .B0(n7546), .B1(n7627), .Y(n1380)
);
OAI22X1TS U8546 ( .A0(n7622), .A1(n7838), .B0(n7549), .B1(n7627), .Y(n1377)
);
OAI21X1TS U8547 ( .A0(n8007), .A1(n2216), .B0(n8133), .Y(n7551) );
AOI22X1TS U8548 ( .A0(n7633), .A1(n7583), .B0(n7551), .B1(n6864), .Y(n8778)
);
OAI22X1TS U8549 ( .A0(n7622), .A1(n7839), .B0(n7552), .B1(n2374), .Y(n1374)
);
OAI22X1TS U8550 ( .A0(n7622), .A1(n7840), .B0(n7554), .B1(n2413), .Y(n1371)
);
OAI21X1TS U8551 ( .A0(n8036), .A1(n2216), .B0(n8125), .Y(n7555) );
AOI22X1TS U8552 ( .A0(n7564), .A1(n7633), .B0(n7555), .B1(n6864), .Y(n8780)
);
OAI22X1TS U8553 ( .A0(n7557), .A1(n7841), .B0(n7556), .B1(n2413), .Y(n1368)
);
OAI22X1TS U8554 ( .A0(n7622), .A1(n7842), .B0(n7559), .B1(n2413), .Y(n1365)
);
NOR4X1TS U8555 ( .A(n3199), .B(n3200), .C(n3198), .D(n3197), .Y(n7593) );
AOI22X1TS U8556 ( .A0(n8785), .A1(n7571), .B0(n8802), .B1(n7620), .Y(n7572)
);
NOR4X1TS U8557 ( .A(n3196), .B(n3195), .C(n3169), .D(n7573), .Y(n7592) );
AOI22X1TS U8558 ( .A0(n7578), .A1(n8828), .B0(n8826), .B1(n7656), .Y(n7579)
);
AOI22X1TS U8559 ( .A0(n7617), .A1(n8799), .B0(n8787), .B1(n7580), .Y(n7588)
);
AOI22X1TS U8560 ( .A0(n7611), .A1(n8793), .B0(n8790), .B1(n7608), .Y(n7587)
);
AOI22X1TS U8561 ( .A0(n7582), .A1(n5945), .B0(n5942), .B1(n7581), .Y(n7586)
);
AOI22X1TS U8562 ( .A0(n7584), .A1(n5946), .B0(n8817), .B1(n7583), .Y(n7585)
);
NAND4XLTS U8563 ( .A(n7588), .B(n7587), .C(n7586), .D(n7585), .Y(n7589) );
NOR4X1TS U8564 ( .A(n3170), .B(n3201), .C(n7590), .D(n7589), .Y(n7591) );
CLKXOR2X2TS U8565 ( .A(n7594), .B(FPADDSUB_intAS), .Y(n7601) );
OAI22X1TS U8566 ( .A0(n7602), .A1(n7596), .B0(n7595), .B1(n7601), .Y(n7597)
);
OAI22X1TS U8567 ( .A0(n7622), .A1(n7843), .B0(n7606), .B1(n2413), .Y(n1331)
);
AOI22X1TS U8568 ( .A0(n7608), .A1(n8608), .B0(n7607), .B1(n6862), .Y(n8789)
);
OAI22X1TS U8569 ( .A0(n7622), .A1(n7844), .B0(n7609), .B1(n2413), .Y(n1315)
);
AOI22X1TS U8570 ( .A0(n7611), .A1(n8608), .B0(n7610), .B1(n7624), .Y(n8792)
);
OAI22X1TS U8571 ( .A0(n7622), .A1(n7845), .B0(n7612), .B1(n2413), .Y(n1308)
);
AOI22X1TS U8572 ( .A0(n7614), .A1(n6863), .B0(n7613), .B1(n7624), .Y(n8795)
);
OAI22X1TS U8573 ( .A0(n7622), .A1(n7846), .B0(n7615), .B1(n2413), .Y(n1301)
);
AOI22X1TS U8574 ( .A0(n7617), .A1(n8608), .B0(n7616), .B1(n7624), .Y(n8798)
);
OAI22X1TS U8575 ( .A0(n7622), .A1(n7847), .B0(n7618), .B1(n2413), .Y(n1294)
);
AOI22X1TS U8576 ( .A0(n7620), .A1(n8608), .B0(n7619), .B1(n7624), .Y(n8801)
);
OAI22X1TS U8577 ( .A0(n7622), .A1(n7848), .B0(n7621), .B1(n7627), .Y(n1287)
);
INVX2TS U8578 ( .A(n7665), .Y(n7645) );
OAI21X1TS U8579 ( .A0(n8037), .A1(n2222), .B0(n8100), .Y(n7626) );
AOI22X1TS U8580 ( .A0(n7625), .A1(n8608), .B0(n7626), .B1(n7624), .Y(n8804)
);
OAI22X1TS U8581 ( .A0(n7629), .A1(n7849), .B0(n7628), .B1(n2413), .Y(n1280)
);
OAI21X1TS U8582 ( .A0(n8015), .A1(n2215), .B0(n8136), .Y(n7635) );
AOI22X1TS U8583 ( .A0(n7638), .A1(n7633), .B0(n7635), .B1(n7636), .Y(n8808)
);
BUFX3TS U8584 ( .A(n7634), .Y(n7650) );
OAI21X1TS U8585 ( .A0(n8015), .A1(n2220), .B0(n8101), .Y(n7639) );
AOI22X1TS U8586 ( .A0(n7638), .A1(n7637), .B0(n7639), .B1(n7636), .Y(n8809)
);
INVX2TS U8587 ( .A(n7663), .Y(n7664) );
INVX2TS U8588 ( .A(n7665), .Y(n7667) );
OAI21X1TS U8589 ( .A0(n8012), .A1(n2220), .B0(n8081), .Y(n7653) );
AOI22X1TS U8590 ( .A0(n7652), .A1(n7655), .B0(n7653), .B1(n7654), .Y(n8823)
);
OAI21X1TS U8591 ( .A0(n7999), .A1(n2221), .B0(n8082), .Y(n7657) );
AOI22X1TS U8592 ( .A0(n7656), .A1(n7655), .B0(n7657), .B1(n7654), .Y(n8825)
);
AO22XLTS U8593 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U8594 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
endmodule
|
// -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer with Packet FIFO
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_w_upsizer_pktfifo #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter C_CLK_CONV = 1'b0,
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1,
// Log2 of Up-Sizing ratio for data.
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Global Signals
input wire S_AXI_ACLK,
input wire M_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire M_AXI_ARESETN,
// Command Interface
input wire [C_AXI_ADDR_WIDTH-1:0] cmd_si_addr,
input wire [8-1:0] cmd_si_len,
input wire [3-1:0] cmd_si_size,
input wire [2-1:0] cmd_si_burst,
output wire cmd_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWREGION,
input wire [4-1:0] S_AXI_AWQOS,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [8-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWREGION,
output wire [4-1:0] M_AXI_AWQOS,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE
);
localparam integer P_SI_BYTES = C_S_AXI_DATA_WIDTH / 8;
localparam integer P_MI_BYTES = C_M_AXI_DATA_WIDTH / 8;
localparam integer P_MAX_BYTES = 1024 / 8;
localparam integer P_SI_SIZE = f_ceil_log2(P_SI_BYTES);
localparam integer P_MI_SIZE = f_ceil_log2(P_MI_BYTES);
localparam integer P_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer P_RATIO_LOG = f_ceil_log2(P_RATIO);
localparam integer P_NUM_BUF = (P_RATIO > 16) ? 32 : (P_RATIO * 2);
localparam integer P_NUM_BUF_LOG = f_ceil_log2(P_NUM_BUF);
localparam integer P_AWFIFO_TRESHOLD = P_NUM_BUF - 2;
localparam integer P_M_WBUFFER_WIDTH = P_MI_BYTES * 9;
localparam integer P_M_WBUFFER_DEPTH = 512;
localparam integer P_M_WBUFFER_DEPTH_LOG = 9;
localparam integer P_M_WBUFFER_WORDS = P_M_WBUFFER_DEPTH / P_NUM_BUF;
localparam integer P_M_WBUFFER_WORDS_LOG = f_ceil_log2(P_M_WBUFFER_WORDS);
localparam integer P_MAX_RBUFFER_BYTES_LOG = f_ceil_log2((P_M_WBUFFER_DEPTH / 4) * P_MAX_BYTES);
localparam [1:0] P_INCR = 2'b01, P_WRAP = 2'b10, P_FIXED = 2'b00;
localparam [1:0] S_IDLE = 2'b00, S_WRITING = 2'b01, S_AWFULL = 2'b11;
localparam [2:0] M_IDLE = 3'b000, M_ISSUE1 = 3'b001, M_WRITING1 = 3'b011, M_AW_STALL = 3'b010, M_AW_DONE1 = 3'b110, M_ISSUE2 = 3'b111, M_WRITING2 = 3'b101, M_AW_DONE2 = 3'b100;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_AWFIFO_WIDTH = 29 + C_AXI_ADDR_WIDTH + P_MI_SIZE;
localparam integer P_COMMON_CLOCK = (C_CLK_CONV & C_AXI_IS_ACLK_ASYNC) ? 0 : 1;
reg S_AXI_WREADY_i;
reg M_AXI_AWVALID_i;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR_i;
wire [7:0] M_AXI_AWLEN_i;
wire [2:0] M_AXI_AWSIZE_i;
wire [1:0] M_AXI_AWBURST_i;
wire M_AXI_AWLOCK_i;
reg M_AXI_WVALID_i;
reg M_AXI_WLAST_i;
wire S_AXI_AWLOCK_i;
reg aw_push;
wire push_ready;
wire aw_ready;
reg load_si_ptr;
reg [1:0] si_state;
reg [1:0] si_state_ns;
reg S_AXI_WREADY_ns;
reg aw_pop;
reg aw_pop_extend;
wire aw_pop_event;
wire aw_pop_resync;
reg cmd_ready_i;
wire si_buf_en;
reg [P_NUM_BUF_LOG-1:0] si_buf;
reg [P_NUM_BUF_LOG-1:0] buf_cnt;
reg [P_M_WBUFFER_WORDS_LOG-1:0] si_ptr;
reg [1:0] si_burst;
reg [2:0] si_size;
reg [P_SI_BYTES-1:0] si_be;
wire [P_MI_BYTES-1:0] si_we;
reg [P_SI_BYTES-1:0] si_wrap_be_next;
reg [P_MI_SIZE-P_SI_SIZE-1:0] si_word;
reg [P_MI_SIZE-P_SI_SIZE-1:0] si_wrap_word_next;
reg [3:0] si_wrap_cnt;
reg [2:0] mi_state;
reg [2:0] mi_state_ns;
reg M_AXI_AWVALID_ns;
reg M_AXI_WVALID_ns;
reg load_mi_ptr;
reg load_mi_next;
reg load_mi_d1;
reg load_mi_d2;
reg first_load_mi_d1;
wire mi_w_done;
reg mi_last;
reg mi_last_d1;
reg next_valid;
reg [P_NUM_BUF_LOG-1:0] mi_buf;
reg [P_M_WBUFFER_WORDS_LOG-1:0] mi_ptr;
reg [7:0] mi_wcnt;
wire mi_buf_en;
wire mi_awvalid;
reg [1:0] mi_burst;
reg [2:0] mi_size;
reg [P_MI_BYTES-1:0] mi_be;
reg [P_MI_BYTES-1:0] mi_be_d1;
reg [P_MI_BYTES-1:0] mi_wstrb_mask_d2;
reg [P_MI_BYTES-1:0] mi_wrap_be_next;
reg [P_MI_SIZE-1:0] mi_addr;
reg [P_MI_SIZE-1:0] mi_addr_d1;
wire [P_MI_SIZE-1:0] si_last_index;
wire [P_MI_SIZE-1:0] si_last_index_reg;
wire [P_MI_SIZE-1:0] mi_last_index_reg;
reg [P_MI_SIZE-1:0] mi_last_index_reg_d0;
reg [P_MI_SIZE-1:0] mi_last_index_reg_d1;
reg [P_MI_SIZE-1:0] next_mi_last_index_reg;
reg mi_first;
reg mi_first_d1;
reg [3:0] mi_wrap_cnt;
reg [7:0] next_mi_len;
reg [1:0] next_mi_burst;
reg [2:0] next_mi_size;
reg [P_MI_SIZE+4-1:0] next_mi_addr;
wire [P_M_WBUFFER_WIDTH-1:0] si_wpayload;
wire [P_M_WBUFFER_WIDTH-1:0] mi_wpayload;
wire [P_M_WBUFFER_DEPTH_LOG-1:0] si_buf_addr;
wire [P_M_WBUFFER_DEPTH_LOG-1:0] mi_buf_addr;
wire s_awvalid_reg;
wire s_awready_reg;
wire [C_AXI_ADDR_WIDTH-1:0] s_awaddr_reg;
wire [7:0] s_awlen_reg;
wire [2:0] s_awsize_reg;
wire [1:0] s_awburst_reg;
wire s_awlock_reg;
wire [3:0] s_awcache_reg;
wire [2:0] s_awprot_reg;
wire [3:0] s_awqos_reg;
wire [3:0] s_awregion_reg;
wire m_aclk;
wire m_aresetn;
wire s_aresetn;
wire aw_fifo_s_aclk;
wire aw_fifo_m_aclk;
wire aw_fifo_aresetn;
wire awpop_reset;
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire fast_aclk;
reg fast_aresetn_r;
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Byte-enable pattern, for a full SI data-width transfer, at the given starting address.
function [P_SI_BYTES-1:0] f_si_be_init
(
input [P_SI_SIZE-1:0] addr,
input [2:0] size
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_SI_BYTES; i=i+1) begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_be_init[i] = addr_i[ 1 : 0] == i[ 1 : 0];
2'h1: f_si_be_init[i] = addr_i[ 1 : 1] == i[ 1 : 1];
default: f_si_be_init[i] = 1'b1;
endcase
3: case (size[1:0])
2'h0: f_si_be_init[i] = addr_i[ 2 : 0] == i[ 2 : 0];
2'h1: f_si_be_init[i] = addr_i[ 2 : 1] == i[ 2 : 1];
2'h2: f_si_be_init[i] = addr_i[ 2 : 2] == i[ 2 : 2];
default: f_si_be_init[i] = 1'b1;
endcase
4: case (size)
3'h0: f_si_be_init[i] = addr_i[ 3 : 0] == i[ 3 : 0];
3'h1: f_si_be_init[i] = addr_i[ 3 : 1] == i[ 3 : 1];
3'h2: f_si_be_init[i] = addr_i[ 3 : 2] == i[ 3 : 2];
3'h3: f_si_be_init[i] = addr_i[ 3 : 3] == i[ 3 : 3];
default: f_si_be_init[i] = 1'b1;
endcase
5: case (size)
3'h0: f_si_be_init[i] = addr_i[ 4 : 0] == i[ 4 : 0];
3'h1: f_si_be_init[i] = addr_i[ 4 : 1] == i[ 4 : 1];
3'h2: f_si_be_init[i] = addr_i[ 4 : 2] == i[ 4 : 2];
3'h3: f_si_be_init[i] = addr_i[ 4 : 3] == i[ 4 : 3];
3'h4: f_si_be_init[i] = addr_i[ 4 : 4] == i[ 4 : 4];
default: f_si_be_init[i] = 1'b1;
endcase
6: case (size)
3'h0: f_si_be_init[i] = addr_i[ 5 : 0] == i[ 5 : 0];
3'h1: f_si_be_init[i] = addr_i[ 5 : 1] == i[ 5 : 1];
3'h2: f_si_be_init[i] = addr_i[ 5 : 2] == i[ 5 : 2];
3'h3: f_si_be_init[i] = addr_i[ 5 : 3] == i[ 5 : 3];
3'h4: f_si_be_init[i] = addr_i[ 5 : 4] == i[ 5 : 4];
3'h5: f_si_be_init[i] = addr_i[ 5 : 5] == i[ 5 : 5];
default: f_si_be_init[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable pattern, for a full MI data-width transfer, at the given starting address.
function [P_MI_BYTES-1:0] f_mi_be_init
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_MI_BYTES; i=i+1) begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 2 : 0] == i[ 2 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 2 : 1] == i[ 2 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 2 : 2] == i[ 2 : 2];
default: f_mi_be_init[i] = 1'b1; // Fully-packed
endcase
4: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 3 : 0] == i[ 3 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 3 : 1] == i[ 3 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 3 : 2] == i[ 3 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 3 : 3] == i[ 3 : 3];
default: f_mi_be_init[i] = 1'b1;
endcase
5: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 4 : 0] == i[ 4 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 4 : 1] == i[ 4 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 4 : 2] == i[ 4 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 4 : 3] == i[ 4 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 4 : 4] == i[ 4 : 4];
default: f_mi_be_init[i] = 1'b1;
endcase
6: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 5 : 0] == i[ 5 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 5 : 1] == i[ 5 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 5 : 2] == i[ 5 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 5 : 3] == i[ 5 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 5 : 4] == i[ 5 : 4];
3'h5: f_mi_be_init[i] = addr_i[ 5 : 5] == i[ 5 : 5];
default: f_mi_be_init[i] = 1'b1;
endcase
7: case (size)
3'h0: f_mi_be_init[i] = addr_i[ 6 : 0] == i[ 6 : 0];
3'h1: f_mi_be_init[i] = addr_i[ 6 : 1] == i[ 6 : 1];
3'h2: f_mi_be_init[i] = addr_i[ 6 : 2] == i[ 6 : 2];
3'h3: f_mi_be_init[i] = addr_i[ 6 : 3] == i[ 6 : 3];
3'h4: f_mi_be_init[i] = addr_i[ 6 : 4] == i[ 6 : 4];
3'h5: f_mi_be_init[i] = addr_i[ 6 : 5] == i[ 6 : 5];
3'h6: f_mi_be_init[i] = addr_i[ 6 : 6] == i[ 6 : 6];
default: f_mi_be_init[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable mask for the first fully-packed MI transfer (mask off ragged-head burst).
function [P_MI_BYTES-1:0] f_mi_be_first_mask
(
input [P_MI_SIZE-1:0] addr
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_mi_be_first_mask[i] = (i >= {1'b0, addr});
end
end
endfunction
// Index of last byte written in last MI transfer.
function [P_MI_SIZE-1:0] f_mi_be_last_index
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len,
input [1:0] burst
);
reg [P_MI_SIZE-1:0] bytes;
reg [P_MI_SIZE-1:0] mask;
begin
case (P_SI_SIZE)
2: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
endcase
3: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
endcase
4: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
endcase
5: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
3'h5: begin bytes = {len, 5'b0}; mask = {5{1'b1}}; end
endcase
6: case (size)
3'h0: begin bytes = len ; mask = 1'b0 ; end
3'h1: begin bytes = {len, 1'b0}; mask = {1{1'b1}}; end
3'h2: begin bytes = {len, 2'b0}; mask = {2{1'b1}}; end
3'h3: begin bytes = {len, 3'b0}; mask = {3{1'b1}}; end
3'h4: begin bytes = {len, 4'b0}; mask = {4{1'b1}}; end
3'h5: begin bytes = {len, 5'b0}; mask = {5{1'b1}}; end
3'h6: begin bytes = {len, 6'b0}; mask = {6{1'b1}}; end
endcase
endcase
case (burst)
P_INCR:
f_mi_be_last_index = (addr + bytes) | mask;
P_WRAP:
f_mi_be_last_index = addr | bytes | mask;
P_FIXED:
f_mi_be_last_index = {P_MI_SIZE{1'b1}};
endcase
end
endfunction
// Byte-enable mask for the last fully-packed MI transfer (mask off ragged-tail burst).
function [P_MI_BYTES-1:0] f_mi_be_last_mask
(
input [P_MI_SIZE-1:0] index
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_mi_be_last_mask[i] = (i <= {1'b0, index});
end
end
endfunction
// Byte-enable pattern, within the SI data-width, of the transfer at the wrap boundary.
function [P_SI_BYTES-1:0] f_si_wrap_be
(
input [P_SI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_SI_BYTES; i=i+1) begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[1:0]) : ({addr_i[1:1], 1'b0} == i[1:0]);
2'h1: f_si_wrap_be[i] = ( 1'b0 == i[1:1]);
default: f_si_wrap_be[i] = 1'b1;
endcase
3: case (size[1:0])
2'h0: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[2:0]) : len[1] ? ({addr_i[2:2], 2'b0} == i[2:0]) : ({addr_i[2:1], 1'b0} == i[2:0]);
2'h1: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[2:1]) : ({addr_i[2:2], 1'b0} == i[2:1]);
2'h2: f_si_wrap_be[i] = ( 1'b0 == i[2:2]);
default: f_si_wrap_be[i] = 1'b1;
endcase
4: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[3:0]) : len[2] ? ({addr_i[3:3], 3'b0} == i[3:0]) : len[1] ? ({addr_i[3:2], 2'b0} == i[3:0]) : ({addr_i[3:1], 1'b0} == i[3:0]);
3'h1: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[3:1]) : len[1] ? ({addr_i[3:3], 2'b0} == i[3:1]) : ({addr_i[3:2], 1'b0} == i[3:1]);
3'h2: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[3:2]) : ({addr_i[3:3], 1'b0} == i[3:2]);
3'h3: f_si_wrap_be[i] = ( 1'b0 == i[3:3]);
default: f_si_wrap_be[i] = 1'b1;
endcase
5: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ({addr_i[4:4], 4'b0} == i[4:0]) : len[2] ? ({addr_i[4:3], 3'b0} == i[4:0]) : len[1] ? ({addr_i[4:2], 2'b0} == i[4:0]) : ({addr_i[4:1], 1'b0} == i[4:0]);
3'h1: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[4:1]) : len[2] ? ({addr_i[4:4], 3'b0} == i[4:1]) : len[1] ? ({addr_i[4:3], 2'b0} == i[4:1]) : ({addr_i[4:2], 1'b0} == i[4:1]);
3'h2: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[4:2]) : len[1] ? ({addr_i[4:4], 2'b0} == i[4:2]) : ({addr_i[4:3], 1'b0} == i[4:2]);
3'h3: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[4:3]) : ({addr_i[4:4], 1'b0} == i[4:3]);
3'h4: f_si_wrap_be[i] = ( 1'b0 == i[4:4]);
default: f_si_wrap_be[i] = 1'b1;
endcase
6: case (size)
3'h0: f_si_wrap_be[i] = len[3] ? ({addr_i[5:4], 4'b0} == i[5:0]) : len[2] ? ({addr_i[5:3], 3'b0} == i[5:0]) : len[1] ? ({addr_i[5:2], 2'b0} == i[5:0]) : ({addr_i[5:1], 1'b0} == i[5:0]);
3'h1: f_si_wrap_be[i] = len[3] ? ({addr_i[5:5], 4'b0} == i[5:1]) : len[2] ? ({addr_i[5:4], 3'b0} == i[5:1]) : len[1] ? ({addr_i[5:3], 2'b0} == i[5:1]) : ({addr_i[5:2], 1'b0} == i[5:1]);
3'h2: f_si_wrap_be[i] = len[3] ? ( 4'b0 == i[5:2]) : len[2] ? ({addr_i[5:5], 3'b0} == i[5:2]) : len[1] ? ({addr_i[5:4], 2'b0} == i[5:2]) : ({addr_i[5:3], 1'b0} == i[5:2]);
3'h3: f_si_wrap_be[i] = len[2] ? ( 3'b0 == i[5:3]) : len[1] ? ({addr_i[5:5], 2'b0} == i[5:3]) : ({addr_i[5:4], 1'b0} == i[5:3]);
3'h4: f_si_wrap_be[i] = len[1] ? ( 2'b0 == i[5:4]) : ({addr_i[5:5], 1'b0} == i[5:4]);
3'h5: f_si_wrap_be[i] = ( 1'b0 == i[5:5]);
default: f_si_wrap_be[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Byte-enable pattern, within the MI data-width, of the transfer at the wrap boundary.
function [P_MI_BYTES-1:0] f_mi_wrap_be
(
input [P_MI_SIZE-1:0] addr,
input [2:0] size,
input [7:0] len
);
integer i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
for (i=0; i<P_MI_BYTES; i=i+1) begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[2:0]) : len[1] ? ({addr_i[2:2], 2'b0} == i[2:0]) : ({addr_i[2:1], 1'b0} == i[2:0]);
3'h1: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[2:1]) : ({addr_i[2:2], 1'b0} == i[2:1]);
3'h2: f_mi_wrap_be[i] = ( 1'b0 == i[2:2]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
4: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[3:0]) : len[2] ? ({addr_i[3:3], 3'b0} == i[3:0]) : len[1] ? ({addr_i[3:2], 2'b0} == i[3:0]) : ({addr_i[3:1], 1'b0} == i[3:0]);
3'h1: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[3:1]) : len[1] ? ({addr_i[3:3], 2'b0} == i[3:1]) : ({addr_i[3:2], 1'b0} == i[3:1]);
3'h2: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[3:2]) : ({addr_i[3:3], 1'b0} == i[3:2]);
3'h3: f_mi_wrap_be[i] = ( 1'b0 == i[3:3]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
5: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[4:4], 4'b0} == i[4:0]) : len[2] ? ({addr_i[4:3], 3'b0} == i[4:0]) : len[1] ? ({addr_i[4:2], 2'b0} == i[4:0]) : ({addr_i[4:1], 1'b0} == i[4:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[4:1]) : len[2] ? ({addr_i[4:4], 3'b0} == i[4:1]) : len[1] ? ({addr_i[4:3], 2'b0} == i[4:1]) : ({addr_i[4:2], 1'b0} == i[4:1]);
3'h2: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[4:2]) : len[1] ? ({addr_i[4:4], 2'b0} == i[4:2]) : ({addr_i[4:3], 1'b0} == i[4:2]);
3'h3: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[4:3]) : ({addr_i[4:4], 1'b0} == i[4:3]);
3'h4: f_mi_wrap_be[i] = ( 1'b0 == i[4:4]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
6: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[5:4], 4'b0} == i[5:0]) : len[2] ? ({addr_i[5:3], 3'b0} == i[5:0]) : len[1] ? ({addr_i[5:2], 2'b0} == i[5:0]) : ({addr_i[5:1], 1'b0} == i[5:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ({addr_i[5:5], 4'b0} == i[5:1]) : len[2] ? ({addr_i[5:4], 3'b0} == i[5:1]) : len[1] ? ({addr_i[5:3], 2'b0} == i[5:1]) : ({addr_i[5:2], 1'b0} == i[5:1]);
3'h2: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[5:2]) : len[2] ? ({addr_i[5:5], 3'b0} == i[5:2]) : len[1] ? ({addr_i[5:4], 2'b0} == i[5:2]) : ({addr_i[5:3], 1'b0} == i[5:2]);
3'h3: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[5:3]) : len[1] ? ({addr_i[5:5], 2'b0} == i[5:3]) : ({addr_i[5:4], 1'b0} == i[5:3]);
3'h4: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[5:4]) : ({addr_i[5:5], 1'b0} == i[5:4]);
3'h5: f_mi_wrap_be[i] = ( 1'b0 == i[5:5]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
7: case (size)
3'h0: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:4], 4'b0} == i[6:0]) : len[2] ? ({addr_i[6:3], 3'b0} == i[6:0]) : len[1] ? ({addr_i[6:2], 2'b0} == i[6:0]) : ({addr_i[6:1], 1'b0} == i[6:0]);
3'h1: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:5], 4'b0} == i[6:1]) : len[2] ? ({addr_i[6:4], 3'b0} == i[6:1]) : len[1] ? ({addr_i[6:3], 2'b0} == i[6:1]) : ({addr_i[6:2], 1'b0} == i[6:1]);
3'h2: f_mi_wrap_be[i] = len[3] ? ({addr_i[6:6], 4'b0} == i[6:2]) : len[2] ? ({addr_i[6:5], 3'b0} == i[6:2]) : len[1] ? ({addr_i[6:4], 2'b0} == i[6:2]) : ({addr_i[6:3], 1'b0} == i[6:2]);
3'h3: f_mi_wrap_be[i] = len[3] ? ( 4'b0 == i[6:3]) : len[2] ? ({addr_i[6:6], 3'b0} == i[6:3]) : len[1] ? ({addr_i[6:5], 2'b0} == i[6:3]) : ({addr_i[6:4], 1'b0} == i[6:3]);
3'h4: f_mi_wrap_be[i] = len[2] ? ( 3'b0 == i[6:4]) : len[1] ? ({addr_i[6:6], 2'b0} == i[6:4]) : ({addr_i[6:5], 1'b0} == i[6:4]);
3'h5: f_mi_wrap_be[i] = len[1] ? ( 2'b0 == i[6:5]) : ({addr_i[6:6], 1'b0} == i[6:5]);
3'h6: f_mi_wrap_be[i] = ( 1'b0 == i[6:6]);
default: f_mi_wrap_be[i] = 1'b1;
endcase
endcase
end
end
endfunction
// Number of SI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_si_wrap_cnt
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
default: start = addr_i[ 2 +: 4];
endcase
3: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
2'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
endcase
f_si_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Number of MI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_mi_wrap_cnt
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
7: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
3'h6: start = addr_i[ 6 +: 4];
default: start = addr_i[ 7 +: 4];
endcase
endcase
f_mi_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Mask of address bits used to point to buffer line (MI data-width) of first SI wrap transfer.
function [2:0] f_si_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_RATIO_LOG)
1: case (P_SI_SIZE)
6: case (size)
3'h6: f_si_wrap_mask = len[3:1];
3'h5: f_si_wrap_mask = len[3:2];
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_si_wrap_mask = len[3:1];
3'h4: f_si_wrap_mask = len[3:2];
3'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_si_wrap_mask = len[3:1];
3'h3: f_si_wrap_mask = len[3:2];
3'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:1];
2'h2: f_si_wrap_mask = len[3:2];
2'h1: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:1];
2'h1: f_si_wrap_mask = len[3:2];
default: f_si_wrap_mask = len[3:3];
endcase
endcase
2: case (P_SI_SIZE)
5: case (size)
3'h5: f_si_wrap_mask = len[3:2];
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_si_wrap_mask = len[3:2];
3'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:2];
2'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:2];
2'h1: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
endcase
3: case (P_SI_SIZE)
4: case (size)
3'h4: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
2: case (size[1:0])
2'h2: f_si_wrap_mask = len[3:3];
default: f_si_wrap_mask = 0 ;
endcase
endcase
default: f_si_wrap_mask = 0 ;
endcase
end
endfunction
// Mask of address bits used to point to buffer line of first MI wrap transfer.
function [2:0] f_mi_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_RATIO_LOG)
1: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h6: f_mi_wrap_mask = len[3:1];
3'h5: f_mi_wrap_mask = len[3:2];
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h5: f_mi_wrap_mask = len[3:1];
3'h4: f_mi_wrap_mask = len[3:2];
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h4: f_mi_wrap_mask = len[3:1];
3'h3: f_mi_wrap_mask = len[3:2];
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_mi_wrap_mask = {len[2:1], 1'b1};
3'h3: f_mi_wrap_mask = len[3:1];
3'h2: f_mi_wrap_mask = len[3:2];
3'h1: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
3: case (size[1:0])
2'h3: f_mi_wrap_mask = {len[2:1], 1'b1};
2'h2: f_mi_wrap_mask = len[3:1];
2'h1: f_mi_wrap_mask = len[3:2];
default: f_mi_wrap_mask = len[3:3];
endcase
endcase
2: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h5: f_mi_wrap_mask = len[3:2];
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h4: f_mi_wrap_mask = len[3:2];
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h3: f_mi_wrap_mask = len[3:2];
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
4: case (size)
3'h4: f_mi_wrap_mask = {len[1:1], 1'b1};
3'h2: f_mi_wrap_mask = len[3:2];
3'h1: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
endcase
3: case (P_MI_SIZE)
7: case (size)
3'h7: f_mi_wrap_mask = 1'b1;
3'h4: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
6: case (size)
3'h6: f_mi_wrap_mask = 1'b1;
3'h3: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
5: case (size)
3'h5: f_mi_wrap_mask = 1'b1;
3'h2: f_mi_wrap_mask = len[3:3];
default: f_mi_wrap_mask = 0 ;
endcase
endcase
default: f_mi_wrap_mask = 0 ;
endcase
end
endfunction
// Index of SI transfer within buffer line following wrap
function [P_MI_SIZE-P_SI_SIZE-1:0] f_si_wrap_word
(
input [(P_MI_SIZE+4-1):0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_MI_SIZE-P_SI_SIZE-1:0] mask;
begin
case (P_SI_SIZE)
2: case (size[1:0])
3'h2: mask = {len[3:1], {1{1'b1}}};
3'h1: mask = len[3:1];
default: mask = len[3:2];
endcase
3: case (size)
3'h3: mask = {len[3:1], {1{1'b1}}};
3'h2: mask = len[3:1];
3'h1: mask = len[3:2];
default: mask = len[3:3];
endcase
4: case (size)
3'h4: mask = {len[3:1], {1{1'b1}}};
3'h3: mask = len[3:1];
3'h2: mask = len[3:2];
3'h1: mask = len[3:3];
default: mask = 0;
endcase
5: case (size)
3'h5: mask = {len[3:1], {1{1'b1}}};
3'h4: mask = len[3:1];
3'h3: mask = len[3:2];
3'h2: mask = len[3:3];
default: mask = 0;
endcase
6: case (size)
3'h6: mask = {len[3:1], {1{1'b1}}};
3'h5: mask = len[3:1];
3'h4: mask = len[3:2];
3'h3: mask = len[3:3];
default: mask = 0;
endcase
endcase
f_si_wrap_word = addr[P_MI_SIZE-1 : P_SI_SIZE] & ~mask;
end
endfunction
// Complete byte-enable pattern for writing SI data word to buffer (MI data-width).
function [P_MI_BYTES-1:0] f_si_we
(
input [P_RATIO_LOG-1:0] word, // Index of SI transfer within buffer line
input [P_SI_BYTES-1:0] be // Byte-enable pattern within SI transfer (SI data-width)
);
integer i;
begin
for (i=0; i<P_RATIO; i=i+1) begin
f_si_we[i*P_SI_BYTES +: P_SI_BYTES] = (i == word) ? be : 0;
end
end
endfunction
// Rotate byte-enable mask around SI-width boundary.
function [P_SI_BYTES-1:0] f_si_be_rot
(
input [P_SI_BYTES-1:0] be, // Byte-enable pattern within SI transfer (SI data-width)
input [2:0] size
);
reg [63:0] be_i;
begin
be_i = be;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_si_be_rot = {be_i[0 +: ( 4 - 1)], be_i[ 3 -: 1]};
2'h1: f_si_be_rot = {be_i[0 +: ( 4 - 2)], be_i[ 3 -: 2]};
default: f_si_be_rot = {4{1'b1}};
endcase
3: case (size[1:0])
2'h0: f_si_be_rot = {be_i[0 +: ( 8 - 1)], be_i[ 7 -: 1]};
2'h1: f_si_be_rot = {be_i[0 +: ( 8 - 2)], be_i[ 7 -: 2]};
2'h2: f_si_be_rot = {be_i[0 +: ( 8 - 4)], be_i[ 7 -: 4]};
default: f_si_be_rot = {8{1'b1}};
endcase
4: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (16 - 1)], be_i[15 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (16 - 2)], be_i[15 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (16 - 4)], be_i[15 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (16 - 8)], be_i[15 -: 8]};
default: f_si_be_rot = {16{1'b1}};
endcase
5: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (32 - 1)], be_i[31 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (32 - 2)], be_i[31 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (32 - 4)], be_i[31 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (32 - 8)], be_i[31 -: 8]};
3'h4: f_si_be_rot = {be_i[0 +: (32 - 16)], be_i[31 -: 16]};
default: f_si_be_rot = {32{1'b1}};
endcase
6: case (size)
3'h0: f_si_be_rot = {be_i[0 +: (64 - 1)], be_i[63 -: 1]};
3'h1: f_si_be_rot = {be_i[0 +: (64 - 2)], be_i[63 -: 2]};
3'h2: f_si_be_rot = {be_i[0 +: (64 - 4)], be_i[63 -: 4]};
3'h3: f_si_be_rot = {be_i[0 +: (64 - 8)], be_i[63 -: 8]};
3'h4: f_si_be_rot = {be_i[0 +: (64 - 16)], be_i[63 -: 16]};
3'h5: f_si_be_rot = {be_i[0 +: (64 - 32)], be_i[63 -: 32]};
default: f_si_be_rot = {64{1'b1}};
endcase
endcase
end
endfunction
// Rotate byte-enable mask around MI-width boundary.
function [P_MI_BYTES-1:0] f_mi_be_rot
(
input [P_MI_BYTES-1:0] be, // Byte-enable pattern within MI transfer
input [2:0] size
);
reg [127:0] be_i;
begin
be_i = be;
case (P_MI_SIZE)
3: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 8 - 1)], be_i[ 7 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 8 - 2)], be_i[ 7 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 8 - 4)], be_i[ 7 -: 4]};
default: f_mi_be_rot = {8{1'b1}};
endcase
4: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 16 - 1)], be_i[ 15 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 16 - 2)], be_i[ 15 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 16 - 4)], be_i[ 15 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 16 - 8)], be_i[ 15 -: 8]};
default: f_mi_be_rot = {16{1'b1}};
endcase
5: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 32 - 1)], be_i[ 31 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 32 - 2)], be_i[ 31 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 32 - 4)], be_i[ 31 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 32 - 8)], be_i[ 31 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: ( 32 - 16)], be_i[ 31 -: 16]};
default: f_mi_be_rot = {32{1'b1}};
endcase
6: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: ( 64 - 1)], be_i[ 63 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: ( 64 - 2)], be_i[ 63 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: ( 64 - 4)], be_i[ 63 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: ( 64 - 8)], be_i[ 63 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: ( 64 - 16)], be_i[ 63 -: 16]};
3'h5: f_mi_be_rot = {be_i[0 +: ( 64 - 32)], be_i[ 63 -: 32]};
default: f_mi_be_rot = {64{1'b1}};
endcase
7: case (size)
3'h0: f_mi_be_rot = {be_i[0 +: (128 - 1)], be_i[127 -: 1]};
3'h1: f_mi_be_rot = {be_i[0 +: (128 - 2)], be_i[127 -: 2]};
3'h2: f_mi_be_rot = {be_i[0 +: (128 - 4)], be_i[127 -: 4]};
3'h3: f_mi_be_rot = {be_i[0 +: (128 - 8)], be_i[127 -: 8]};
3'h4: f_mi_be_rot = {be_i[0 +: (128 - 16)], be_i[127 -: 16]};
3'h5: f_mi_be_rot = {be_i[0 +: (128 - 32)], be_i[127 -: 32]};
3'h6: f_mi_be_rot = {be_i[0 +: (128 - 64)], be_i[127 -: 64]};
default: f_mi_be_rot = {128{1'b1}};
endcase
endcase
end
endfunction
function [P_SI_BYTES*9-1:0] f_wpayload
(
input [C_S_AXI_DATA_WIDTH-1:0] wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb
);
integer i;
begin
for (i=0; i<P_SI_BYTES; i=i+1) begin
f_wpayload[i*9 +: 9] = {wstrb[i], wdata[i*8 +: 8]};
end
end
endfunction
function [C_M_AXI_DATA_WIDTH-1:0] f_wdata
(
input [P_MI_BYTES*9-1:0] wpayload
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_wdata[i*8 +: 8] = wpayload[i*9 +: 8];
end
end
endfunction
function [C_M_AXI_DATA_WIDTH/8-1:0] f_wstrb
(
input [P_MI_BYTES*9-1:0] wpayload
);
integer i;
begin
for (i=0; i<P_MI_BYTES; i=i+1) begin
f_wstrb[i] = wpayload[i*9+8];
end
end
endfunction
generate
if (C_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = M_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign aw_fifo_s_aclk = S_AXI_ACLK;
assign aw_fifo_m_aclk = M_AXI_ACLK;
assign aw_fifo_aresetn = S_AXI_ARESETN & M_AXI_ARESETN;
assign awpop_reset = ~S_AXI_ARESETN | ~M_AXI_ARESETN;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end else begin : gen_sync_conv
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = M_AXI_ACLK;
end else begin : gen_fastclk_si
assign fast_aclk = S_AXI_ACLK;
end
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = fast_aresetn_r;
assign s_aresetn = fast_aresetn_r;
assign aw_fifo_s_aclk = fast_aclk;
assign aw_fifo_m_aclk = 1'b0;
assign aw_fifo_aresetn = fast_aresetn_r;
assign s_sample_cycle_early = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign s_sample_cycle = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE;
assign m_sample_cycle_early = P_SI_LT_MI ? SAMPLE_CYCLE_EARLY : 1'b1;
assign m_sample_cycle = P_SI_LT_MI ? SAMPLE_CYCLE : 1'b1;
always @(posedge fast_aclk) begin
if (~S_AXI_ARESETN | ~M_AXI_ARESETN) begin
fast_aresetn_r <= 1'b0;
end else if (S_AXI_ARESETN & M_AXI_ARESETN & SAMPLE_CYCLE_EARLY) begin
fast_aresetn_r <= 1'b1;
end
end
end
end else begin : gen_no_clk_conv
assign m_aclk = S_AXI_ACLK;
assign m_aresetn = S_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign aw_fifo_s_aclk = S_AXI_ACLK;
assign aw_fifo_m_aclk = 1'b0;
assign aw_fifo_aresetn = S_AXI_ARESETN;
assign fast_aclk = S_AXI_ACLK;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end
assign S_AXI_WREADY = S_AXI_WREADY_i;
assign S_AXI_AWLOCK_i = S_AXI_AWLOCK[0];
assign si_buf_en = S_AXI_WVALID & S_AXI_WREADY_i;
assign cmd_ready = cmd_ready_i;
assign s_awready_reg = aw_push;
assign si_last_index = f_mi_be_last_index(cmd_si_addr[0 +: P_MI_SIZE], cmd_si_size, cmd_si_len, cmd_si_burst);
assign push_ready = s_awvalid_reg & aw_ready & (buf_cnt != P_AWFIFO_TRESHOLD);
always @ * begin
aw_push = 1'b0;
load_si_ptr = 1'b0;
si_state_ns = si_state;
S_AXI_WREADY_ns = S_AXI_WREADY_i;
case (si_state)
S_IDLE: begin
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
S_AXI_WREADY_ns = 1'b1;
si_state_ns = S_WRITING;
end
end
S_WRITING: begin
if (S_AXI_WVALID & S_AXI_WREADY_i & S_AXI_WLAST) begin
if (push_ready) begin
aw_push = m_sample_cycle; // Sample strobe when AW FIFO is on faster M_AXI_ACLK.
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for new AW command
si_state_ns = S_IDLE;
end
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for AW FIFO push
si_state_ns = S_AWFULL;
end
end
end
S_AWFULL: begin
if (push_ready) begin
aw_push = m_sample_cycle; // Sample strobe when AW FIFO is on faster M_AXI_ACLK.
if (S_AXI_AWVALID) begin
load_si_ptr = 1'b1;
S_AXI_WREADY_ns = 1'b1;
si_state_ns = S_WRITING;
end else begin
S_AXI_WREADY_ns = 1'b0; //stall W-channel waiting for new AW command
si_state_ns = S_IDLE;
end
end
end
default: si_state_ns = S_IDLE;
endcase
end
always @ (posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
si_state <= S_IDLE;
S_AXI_WREADY_i <= 1'b0;
si_buf <= 0;
buf_cnt <= 0;
cmd_ready_i <= 1'b0;
end else begin
si_state <= si_state_ns;
S_AXI_WREADY_i <= S_AXI_WREADY_ns;
cmd_ready_i <= aw_pop_resync;
if (aw_push) begin
si_buf <= si_buf + 1;
end
if (aw_push & ~aw_pop_resync) begin
buf_cnt <= buf_cnt + 1;
end else if (~aw_push & aw_pop_resync & |buf_cnt) begin
buf_cnt <= buf_cnt - 1;
end
end
end
always @ (posedge S_AXI_ACLK) begin
if (load_si_ptr) begin
if (cmd_si_burst == P_WRAP) begin
si_ptr <= cmd_si_addr[P_MI_SIZE +: 3] & f_si_wrap_mask(cmd_si_size, cmd_si_len);
end else begin
si_ptr <= 0;
end
si_burst <= cmd_si_burst;
si_size <= cmd_si_size;
si_be <= f_si_be_init(cmd_si_addr[0 +: P_SI_SIZE], cmd_si_size);
si_word <= cmd_si_addr[P_MI_SIZE-1 : P_SI_SIZE];
si_wrap_cnt <= f_si_wrap_cnt(cmd_si_addr[0 +: (P_MI_SIZE + 4)], cmd_si_size, cmd_si_len);
si_wrap_be_next <= f_si_wrap_be(cmd_si_addr[0 +: P_SI_SIZE], cmd_si_size, cmd_si_len);
si_wrap_word_next <= f_si_wrap_word(cmd_si_addr[0 +: (P_MI_SIZE + 4)], cmd_si_size, cmd_si_len);
end else if (si_buf_en) begin
if (si_burst == P_FIXED) begin
si_ptr <= si_ptr + 1;
end else if ((si_burst == P_WRAP) && (si_wrap_cnt == 0)) begin
si_ptr <= 0;
si_be <= si_wrap_be_next;
si_word <= si_wrap_word_next;
end else begin
if (si_be[P_SI_BYTES-1]) begin
if (&si_word) begin
si_ptr <= si_ptr + 1; // Wrap long INCR bursts around end of buffer
end
si_word <= si_word + 1;
end
si_be <= f_si_be_rot(si_be, si_size);
end
si_wrap_cnt <= si_wrap_cnt - 1;
end
end
always @ * begin
mi_state_ns = mi_state;
M_AXI_AWVALID_ns = M_AXI_AWVALID_i;
M_AXI_WVALID_ns = M_AXI_WVALID_i;
aw_pop = 1'b0;
load_mi_ptr = 1'b0;
load_mi_next = 1'b0;
case (mi_state)
M_IDLE: begin // mi_state = 0
M_AXI_AWVALID_ns = 1'b0;
M_AXI_WVALID_ns = 1'b0;
if (mi_awvalid) begin
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end
end
M_ISSUE1: begin // mi_state = 1
M_AXI_AWVALID_ns = 1'b1;
mi_state_ns = M_WRITING1;
end
M_WRITING1: begin // mi_state = 3
M_AXI_WVALID_ns = 1'b1;
if (M_AXI_AWREADY) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
M_AXI_AWVALID_ns = 1'b0;
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end else begin
mi_state_ns = M_AW_DONE1;
end
end else if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_AW_STALL;
end
end
M_AW_STALL: begin // mi_state = 2
if (M_AXI_AWREADY) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
M_AXI_AWVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end
end
M_AW_DONE1: begin // mi_state = 6
if (mi_awvalid) begin
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end else if (~mi_last & ~mi_last_d1 & ~M_AXI_WLAST_i) begin
load_mi_next = 1'b1;
mi_state_ns = M_ISSUE2;
end
end else if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
mi_state_ns = M_IDLE;
end
end
M_ISSUE2: begin // mi_state = 7
M_AXI_AWVALID_ns = 1'b1;
if (mi_w_done) begin
M_AXI_WVALID_ns = 1'b0;
load_mi_ptr = 1'b1;
mi_state_ns = M_ISSUE1;
end else begin
mi_state_ns = M_WRITING2;
end
end
M_WRITING2: begin // mi_state = 5
if (M_AXI_AWREADY) begin
M_AXI_AWVALID_ns = 1'b0;
if (mi_w_done) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
mi_state_ns = M_AW_DONE1;
end else begin
mi_state_ns = M_AW_DONE2;
end
end else if (mi_w_done) begin
mi_state_ns = M_WRITING1;
end
end
M_AW_DONE2: begin // mi_state = 4
if (mi_w_done) begin
aw_pop = s_sample_cycle; // Sample strobe when AW FIFO is on faster S_AXI_ACLK.
mi_state_ns = M_AW_DONE1;
end
end
default: mi_state_ns = M_IDLE;
endcase
end
always @ (posedge m_aclk) begin
if (~m_aresetn) begin
mi_state <= M_IDLE;
mi_buf <= 0;
M_AXI_AWVALID_i <= 1'b0;
M_AXI_WVALID_i <= 1'b0;
mi_last <= 1'b0;
mi_last_d1 <= 1'b0;
M_AXI_WLAST_i <= 1'b0;
mi_wstrb_mask_d2 <= {P_MI_BYTES{1'b1}};
first_load_mi_d1 <= 1'b0;
next_valid <= 1'b0;
end else begin
mi_state <= mi_state_ns;
M_AXI_AWVALID_i <= M_AXI_AWVALID_ns;
M_AXI_WVALID_i <= M_AXI_WVALID_ns;
if (mi_buf_en & mi_last) begin
mi_buf <= mi_buf + 1;
end
if (load_mi_ptr) begin
mi_last <= (M_AXI_AWLEN_i == 0);
M_AXI_WLAST_i <= 1'b0;
end else if (mi_buf_en) begin
M_AXI_WLAST_i <= mi_last_d1;
mi_last_d1 <= mi_last;
if (first_load_mi_d1) begin
mi_wstrb_mask_d2 <= mi_be_d1 &
(mi_first_d1 ? f_mi_be_first_mask(mi_addr_d1) : {P_MI_BYTES{1'b1}}) &
(mi_last_d1 ? f_mi_be_last_mask(mi_last_index_reg_d1) : {P_MI_BYTES{1'b1}});
end
if (mi_last) begin
mi_last <= next_valid & (next_mi_len == 0);
end else begin
mi_last <= (mi_wcnt == 1);
end
end
if (load_mi_d1) begin
first_load_mi_d1 <= 1'b1; // forever
end
if (mi_last & mi_buf_en) begin
next_valid <= 1'b0;
end else if (load_mi_next) begin
next_valid <= 1'b1;
end
if (m_sample_cycle) begin
aw_pop_extend <= 1'b0;
end else if (aw_pop) begin
aw_pop_extend <= 1'b1;
end
end
end
assign mi_buf_en = (M_AXI_WVALID_i & M_AXI_WREADY) | load_mi_d1 | load_mi_d2;
assign mi_w_done = M_AXI_WVALID_i & M_AXI_WREADY & M_AXI_WLAST_i;
always @ (posedge m_aclk) begin
load_mi_d2 <= load_mi_d1;
load_mi_d1 <= load_mi_ptr;
if (load_mi_ptr) begin
if (M_AXI_AWBURST_i == P_WRAP) begin
mi_ptr <= M_AXI_AWADDR_i[P_MI_SIZE +: 3] & f_mi_wrap_mask(M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
end else begin
mi_ptr <= 0;
end
mi_wcnt <= M_AXI_AWLEN_i;
mi_burst <= M_AXI_AWBURST_i;
mi_size <= M_AXI_AWSIZE_i;
mi_be <= f_mi_be_init(M_AXI_AWADDR_i[0 +: P_MI_SIZE], M_AXI_AWSIZE_i);
mi_wrap_cnt <= f_mi_wrap_cnt(M_AXI_AWADDR_i[0 +: (P_MI_SIZE + 4)], M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
mi_wrap_be_next <= f_mi_wrap_be(M_AXI_AWADDR_i[0 +: P_MI_SIZE], M_AXI_AWSIZE_i, M_AXI_AWLEN_i);
mi_first <= 1'b1;
mi_addr <= M_AXI_AWADDR_i[0 +: P_MI_SIZE];
mi_last_index_reg_d0 <= mi_last_index_reg;
end else if (mi_buf_en) begin
mi_be_d1 <= mi_be;
mi_first_d1 <= mi_first;
mi_last_index_reg_d1 <= mi_last_index_reg_d0;
mi_addr_d1 <= mi_addr;
if (mi_last) begin
if (next_mi_burst == P_WRAP) begin
mi_ptr <= next_mi_addr[P_MI_SIZE +: 3] & f_mi_wrap_mask(next_mi_size, next_mi_len);
end else begin
mi_ptr <= 0;
end
if (next_valid) begin
mi_wcnt <= next_mi_len;
mi_addr <= next_mi_addr[0 +: P_MI_SIZE];
mi_last_index_reg_d0 <= next_mi_last_index_reg;
end
mi_burst <= next_mi_burst;
mi_size <= next_mi_size;
mi_be <= f_mi_be_init(next_mi_addr[0 +: P_MI_SIZE], next_mi_size);
mi_wrap_cnt <= f_mi_wrap_cnt(next_mi_addr, next_mi_size, next_mi_len);
mi_wrap_be_next <= f_mi_wrap_be(next_mi_addr[0 +: P_MI_SIZE], next_mi_size, next_mi_len);
mi_first <= 1'b1;
end else begin
mi_first <= 1'b0;
if (mi_burst == P_FIXED) begin
mi_ptr <= mi_ptr + 1;
end else if ((mi_burst == P_WRAP) && (mi_wrap_cnt == 0)) begin
mi_ptr <= 0;
mi_be <= mi_wrap_be_next;
end else begin
if (mi_be[P_MI_BYTES-1]) begin
mi_ptr <= (mi_ptr + 1); // Wrap long INCR bursts around end of buffer
end
mi_be <= f_mi_be_rot(mi_be, mi_size);
end
mi_wcnt <= mi_wcnt - 1;
mi_wrap_cnt <= mi_wrap_cnt - 1;
end
end
if (load_mi_next) begin
next_mi_len <= M_AXI_AWLEN_i;
next_mi_burst <= M_AXI_AWBURST_i;
next_mi_size <= M_AXI_AWSIZE_i;
next_mi_addr <= M_AXI_AWADDR_i[0 +: (P_MI_SIZE + 4)];
next_mi_last_index_reg <= mi_last_index_reg;
end
end
assign si_wpayload = {P_RATIO{f_wpayload(S_AXI_WDATA,S_AXI_WSTRB)}};
assign M_AXI_WDATA = f_wdata(mi_wpayload);
assign M_AXI_WSTRB = f_wstrb(mi_wpayload) & mi_wstrb_mask_d2 & {P_MI_BYTES{M_AXI_WVALID_i}};
assign M_AXI_WVALID = M_AXI_WVALID_i;
assign M_AXI_WLAST = M_AXI_WLAST_i;
assign M_AXI_AWVALID = M_AXI_AWVALID_i;
assign M_AXI_AWADDR = M_AXI_AWADDR_i;
assign M_AXI_AWLEN = M_AXI_AWLEN_i;
assign M_AXI_AWSIZE = M_AXI_AWSIZE_i;
assign M_AXI_AWBURST = M_AXI_AWBURST_i;
assign M_AXI_AWLOCK = {1'b0,M_AXI_AWLOCK_i};
assign si_buf_addr = {si_buf, si_ptr};
assign mi_buf_addr = {mi_buf, mi_ptr};
assign si_we = f_si_we(si_word, si_be);
blk_mem_gen_v8_3_3 #(
.C_FAMILY(C_FAMILY),
.C_XDEVICEFAMILY(C_FAMILY),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("BlankString"),
.C_INIT_FILE("BlankString"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(P_MI_BYTES),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(P_M_WBUFFER_WIDTH),
.C_READ_WIDTH_A(P_M_WBUFFER_WIDTH),
.C_WRITE_DEPTH_A(P_M_WBUFFER_DEPTH),
.C_READ_DEPTH_A(P_M_WBUFFER_DEPTH),
.C_ADDRA_WIDTH(P_M_WBUFFER_DEPTH_LOG),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(P_MI_BYTES),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(P_M_WBUFFER_WIDTH),
.C_READ_WIDTH_B(P_M_WBUFFER_WIDTH),
.C_WRITE_DEPTH_B(P_M_WBUFFER_DEPTH),
.C_READ_DEPTH_B(P_M_WBUFFER_DEPTH),
.C_ADDRB_WIDTH(P_M_WBUFFER_DEPTH_LOG),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(1),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("GENERATE_X_ONLY"),
.C_COMMON_CLK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_USE_BRAM_BLOCK(0)
) w_buffer (
.clka(S_AXI_ACLK),
.rsta(1'b0),
.ena(si_buf_en),
.regcea(1'b1),
.wea(si_we),
.addra(si_buf_addr),
.dina(si_wpayload),
.douta(),
.clkb(m_aclk),
.rstb(1'b0),
.enb(mi_buf_en),
.regceb(1'b1),
.web({P_MI_BYTES{1'b0}}),
.addrb(mi_buf_addr),
.dinb({P_M_WBUFFER_WIDTH{1'b0}}),
.doutb(mi_wpayload),
.injectsbiterr(1'b0),
.injectdbiterr(1'b0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wdata({P_M_WBUFFER_WIDTH{1'b0}}),
.s_axi_wstrb({P_MI_BYTES{1'b0}}),
.s_axi_wlast(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_injectdbiterr(1'b0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc(),
.sleep(1'b0),
.eccpipece(1'b0)
);
fifo_generator_v13_1_1 #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_MEMORY_TYPE(1),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_AXIS_TYPE(0),
.C_HAS_AXI_ID(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_DIN_WIDTH_WACH(P_AWFIFO_WIDTH),
.C_DIN_WIDTH_WDCH(37),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(P_AWFIFO_WIDTH),
.C_DIN_WIDTH_RDCH(35),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(P_MI_SIZE),
.C_AXI_AWUSER_WIDTH(P_MI_SIZE),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(2),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_WDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_WRCH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_APPLICATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0)
) dw_fifogen_aw (
.s_aclk(aw_fifo_s_aclk),
.m_aclk(aw_fifo_m_aclk),
.s_aresetn(aw_fifo_aresetn),
.s_axi_awid (1'b0),
.s_axi_awaddr (s_awaddr_reg),
.s_axi_awlen (s_awlen_reg),
.s_axi_awsize (s_awsize_reg),
.s_axi_awburst (s_awburst_reg),
.s_axi_awlock (s_awlock_reg),
.s_axi_awcache (s_awcache_reg),
.s_axi_awprot (s_awprot_reg),
.s_axi_awqos (s_awqos_reg),
.s_axi_awregion (s_awregion_reg),
.s_axi_awuser (si_last_index_reg),
.s_axi_awvalid (aw_push),
.s_axi_awready (aw_ready),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr (M_AXI_AWADDR_i),
.m_axi_awlen (M_AXI_AWLEN_i),
.m_axi_awsize (M_AXI_AWSIZE_i),
.m_axi_awburst (M_AXI_AWBURST_i),
.m_axi_awlock (M_AXI_AWLOCK_i),
.m_axi_awcache (M_AXI_AWCACHE),
.m_axi_awprot (M_AXI_AWPROT),
.m_axi_awqos (M_AXI_AWQOS),
.m_axi_awregion (M_AXI_AWREGION),
.m_axi_awuser (mi_last_index_reg),
.m_axi_awvalid (mi_awvalid),
.m_axi_awready (aw_pop),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(1'b0),
.s_axi_araddr({C_AXI_ADDR_WIDTH{1'b0}}),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser({P_MI_SIZE{1'b0}}),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
axi_register_slice_v2_1_9_axi_register_slice #(
.C_FAMILY(C_FAMILY),
.C_AXI_PROTOCOL(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(1),
.C_AXI_AWUSER_WIDTH(P_MI_SIZE),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(0),
.C_REG_CONFIG_B(0),
.C_REG_CONFIG_AR(0),
.C_REG_CONFIG_R(0)
) s_aw_reg (
.aclk(S_AXI_ACLK),
.aresetn(s_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr (S_AXI_AWADDR),
.s_axi_awlen (S_AXI_AWLEN),
.s_axi_awsize (S_AXI_AWSIZE),
.s_axi_awburst (S_AXI_AWBURST),
.s_axi_awlock (S_AXI_AWLOCK_i),
.s_axi_awcache (S_AXI_AWCACHE),
.s_axi_awprot (S_AXI_AWPROT),
.s_axi_awregion(S_AXI_AWREGION),
.s_axi_awqos (S_AXI_AWQOS),
.s_axi_awuser (si_last_index),
.s_axi_awvalid (S_AXI_AWVALID),
.s_axi_awready (S_AXI_AWREADY),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b00),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_buser(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.s_axi_arid(1'b0),
.s_axi_araddr({C_AXI_ADDR_WIDTH{1'B0}}),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arregion(4'b0),
.s_axi_arqos(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_ruser(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_awid(),
.m_axi_awaddr (s_awaddr_reg),
.m_axi_awlen (s_awlen_reg),
.m_axi_awsize (s_awsize_reg),
.m_axi_awburst (s_awburst_reg),
.m_axi_awlock (s_awlock_reg),
.m_axi_awcache (s_awcache_reg),
.m_axi_awprot (s_awprot_reg),
.m_axi_awregion(s_awregion_reg),
.m_axi_awqos (s_awqos_reg),
.m_axi_awuser (si_last_index_reg),
.m_axi_awvalid (s_awvalid_reg),
.m_axi_awready (s_awready_reg),
.m_axi_wid(),
.m_axi_wuser(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.m_axi_arid(),
.m_axi_aruser(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready()
);
if (C_CLK_CONV && C_AXI_IS_ACLK_ASYNC) begin : gen_awpop_fifo
fifo_generator_v13_1_1 #(
.C_DIN_WIDTH(1),
.C_DOUT_WIDTH(1),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) dw_fifogen_awpop (
.clk(1'b0),
.wr_clk(M_AXI_ACLK),
.rd_clk(S_AXI_ACLK),
.rst(awpop_reset),
.wr_rst(1'b0),
.rd_rst(1'b0),
.srst(1'b0),
.din(1'b0),
.dout(),
.full(),
.empty(aw_pop_event),
.wr_en(aw_pop),
.rd_en(aw_pop_resync),
.backup(1'b0),
.backup_marker(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
assign aw_pop_resync = ~aw_pop_event;
end else begin : gen_no_awpop_fifo
assign aw_pop_resync = aw_pop | aw_pop_extend;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2O_1_V
`define SKY130_FD_SC_HS__A2BB2O_1_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a2bb2o_1 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2O_1_V
|
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_active,
tbp_timer_ready,
tbp_load,
data_complete,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
reg [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
reg int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
wire [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_active;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_active;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_active [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_ap_to_valid_greater_than_trc_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_active = bank_active;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign valid_combi = (valid | load_tbp) & ~flush_tbp;
// Decide which TBP to load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
load_tbp_index <= 0;
end
else
begin
load_tbp_index <= ~valid_combi & (valid_combi + 1);
end
end
// Assert when TBP is full to prevent further load
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_tbp_full <= 0;
end
else
begin
int_tbp_full <= &valid_combi;
end
end
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & nor_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || rmw_partial[j] || rmw_correct[j] || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = data_complete[i];
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst [i] <= 1'b0;
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst [i] <= 1'b1;
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
or_wrt [i] <= 1'b0;
nor_wrt[i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
or_wrt [i] <= |wrt_combi[i];
nor_wrt[i] <= ~|wrt_combi[i];
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && cmd_gen_load)
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush[i]] > 1) ? (trc_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush[i]] > 1) ? (row_timer[log2_open_row_pass_flush[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else if (CFG_REG_GRANT == 1 && open_row_pass_r[i])
begin
if (t_param_rd_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[log2_open_row_pass_flush_r[i]] > 1) ? (trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[log2_open_row_pass_flush_r[i]] > 1) ? (row_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
else
begin
if (t_param_rd_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_wr_ap_to_valid > ((trc_timer[i] > 1) ? (trc_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i] <= 1'b0;
end
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Row timer logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0 && !trc_timer_pre_ready[log2_open_row_pass_flush[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !trc_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
trc_timer [i] <= trc_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_ap_to_valid_greater_than_trc_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_ap_to_valid > trc_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
row_timer_combi[i] = trc_timer[i] - 1'b1;
end
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if
(
(CFG_REG_GRANT == 0 && open_row_pass [i]) ||
(CFG_REG_GRANT == 1 && open_row_pass_r[i])
)
begin
if (CFG_REG_GRANT == 0)
begin
row_timer [i] <= row_timer_combi[log2_open_row_pass_flush[i]];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else if (CFG_REG_GRANT == 1 && !row_timer_pre_ready[log2_open_row_pass_flush_r[i]])
begin
row_timer [i] <= row_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
row_timer [i] <= 1'b0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i])
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_active[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (precharged_combi[j])
begin
int_bank_active[i][j] <= 1'b0;
end
else if (activated_combi[j])
begin
int_bank_active[i][j] <= 1'b1;
end
end
else
begin
int_bank_active[i][j] <= 1'b0; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_active[i] = |int_bank_active[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
module ER_CDE_Handler(ER_CDE, clk, HEX0, HEX1, HEX2, HEX3, HEX1DP);
input[7:0] ER_CDE;
input clk;
output reg[6:0] HEX0, HEX1, HEX2, HEX3;
output reg HEX1DP;
always @(posedge clk) begin
case (ER_CDE[7:0])
8'b00000000: begin //No Error
HEX0 = 7'b0000000;
HEX1 = 7'b0000000;
HEX2 = 7'b0000000;
HEX3 = 7'b0000000;
HEX1DP = 1'b0; end
8'b00000001: begin //Tried to load in stack range
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b0000110;
HEX1DP = 1'b1; end
8'b00000010: begin //Tried to store in stack range
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1011011;
HEX1DP = 1'b1; end
8'b00000011: begin //Tried to PUSH full stack (overflow)
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1001111;
HEX1DP = 1'b1; end
8'b00000100: begin //Tried to POP empty stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1100110;
HEX1DP = 1'b1; end
8'b00000101: begin //Tried to Return PC with empty stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1101101;
HEX1DP = 1'b1; end
8'b00000110: begin //Tried to Call with full stack
HEX0 = 7'b1111001;
HEX1 = 7'b1010000;
HEX2 = 7'b0111111;
HEX3 = 7'b1111101;
HEX1DP = 1'b1; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_SYMBOL_V
`define SKY130_FD_SC_HS__O2BB2AI_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_keys (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 3: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 3: 0] d1_data_in;
reg [ 3: 0] d2_data_in;
wire [ 3: 0] data_in;
reg [ 3: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 3: 0] edge_detect;
wire irq;
reg [ 3: 0] irq_mask;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2018 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openGFX430.v
//
// *Module Description:
// openGFX430 testbench
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 205 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2015-07-15 22:59:52 +0200 (Wed, 15 Jul 2015) $
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module tb_openGFX430;
//
// Wire & Register definition
//------------------------------
`define CLK_PERIOD 50 // 20 MHz
// LT24 Interface
wire [15:0] lt24_lcd_din;
wire lt24_lcd_cs_n;
wire lt24_lcd_rd_n;
wire lt24_lcd_wr_n;
wire lt24_lcd_rs;
wire [15:0] lt24_lcd_dout;
wire lt24_lcd_d_en;
wire lt24_lcd_reset_n;
wire lt24_lcd_on;
wire lt24_adc_cs_n;
wire lt24_adc_dclk;
wire lt24_adc_busy;
wire lt24_adc_din;
wire lt24_adc_dout;
wire lt24_adc_penirq_n;
// Generic screen interface
wire screen_refresh_active;
wire screen_refresh_data_request;
wire screen_refresh_data_ready;
wire [15:0] screen_refresh_data;
wire [`LPIX_MSB:0] screen_display_width;
wire [`LPIX_MSB:0] screen_display_height;
wire [`SPIX_MSB:0] screen_display_size;
// Video Memory interface
wire [`VRAM_MSB:0] vid_ram_addr;
wire vid_ram_wen;
wire vid_ram_cen;
wire [15:0] vid_ram_din;
wire [15:0] vid_ram_dout;
// LUT Memory interface
`ifdef WITH_PROGRAMMABLE_LUT
wire [`LRAM_MSB:0] lut_ram_addr;
wire lut_ram_wen;
wire lut_ram_cen;
wire [15:0] lut_ram_din;
wire [15:0] lut_ram_dout;
`endif
// Peripherals interface
reg [15:0] per_addr;
reg [15:0] per_din;
reg [1:0] per_we;
reg per_en;
wire [15:0] per_dout_lt24;
wire [15:0] per_dout_gfx;
wire [15:0] per_dout;
// Clock / Reset
reg mclk;
reg puc_rst;
// Others
wire dbg_freeze;
wire irq_gfx;
wire irq_lt24_lcd;
wire irq_lt24_adc;
// Testbench variables
integer tb_idx;
reg [8*32-1:0] tb_string;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// Peripheral interface tasks
`include "peripheral_tasks.v"
// Registers & Fields definitions
`include "register_def_openGFX430.v"
`include "register_def_if_lt24.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Memories
//------------------------------
initial
begin
for (tb_idx=0; tb_idx < (1<<`VRAM_MSB); tb_idx=tb_idx+1)
vid_ram_0.mem[tb_idx] = 16'h0000;
for (tb_idx=0; tb_idx < (1<<`LRAM_MSB); tb_idx=tb_idx+1)
lut_ram_0.mem[tb_idx] = 16'h0000;
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
mclk = 1'b0;
forever
begin
#(`CLK_PERIOD/2);
mclk = ~mclk;
end
end
initial
begin
puc_rst = 1'b0;
#93;
puc_rst = 1'b1;
#593;
puc_rst = 1'b0;
end
initial
begin
error = 0;
stimulus_done = 0;
tb_string = "";
per_addr = 14'h0000;
per_din = 16'h0000;
per_we = 2'h0;
per_en = 1'h0;
end
//
// Video Memory
//----------------------------------
ram #(`VRAM_MSB, (1<<(`VRAM_AWIDTH+1))) vid_ram_0 (
// OUTPUTs
.ram_dout ( vid_ram_dout ), // Video Memory data output
// INPUTs
.ram_addr ( vid_ram_addr ), // Video Memory address
.ram_cen ( vid_ram_cen ), // Video Memory chip enable (low active)
.ram_clk ( mclk ), // Video Memory clock
.ram_din ( vid_ram_din ), // Video Memory data input
.ram_wen ( {2{vid_ram_wen}} ) // Video Memory write enable (low active)
);
//
// LUT Memory
//----------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
ram #(`LRAM_MSB, (1<<(`LRAM_AWIDTH+1))) lut_ram_0 (
// OUTPUTs
.ram_dout ( lut_ram_dout ), // LUT Memory data output
// INPUTs
.ram_addr ( lut_ram_addr ), // LUT Memory address
.ram_cen ( lut_ram_cen ), // LUT Memory chip enable (low active)
.ram_clk ( mclk ), // LUT Memory clock
.ram_din ( lut_ram_din ), // LUT Memory data input
.ram_wen ( {2{lut_ram_wen}} ) // LUT Memory write enable (low active)
);
`endif
//
// LT24 Model
//----------------------------------
lt24Model lt24Model_inst (
// OUTPUTs
.lt24_lcd_d_o ( lt24_lcd_din ), // LT24 LCD Data input
.lt24_adc_busy_o ( lt24_adc_busy ), // LT24 ADC Busy
.lt24_adc_dout_o ( lt24_adc_dout ), // LT24 ADC Data Out
.lt24_adc_penirq_n_o ( lt24_adc_penirq_n ), // LT24 ADC Pen Interrupt
// INPUTs
.lt24_lcd_cs_n_i ( lt24_lcd_cs_n ), // LT24 LDC Chip select (Active low)
.lt24_lcd_rd_n_i ( lt24_lcd_rd_n ), // LT24 LDC Read strobe (Active low)
.lt24_lcd_wr_n_i ( lt24_lcd_wr_n ), // LT24 LDC Write strobe (Active low)
.lt24_lcd_rs_i ( lt24_lcd_rs ), // LT24 LDC Command/Param selection (Cmd=0/Param=1)
.lt24_lcd_d_i ( lt24_lcd_dout ), // LT24 LDC Data output
.lt24_lcd_d_en_i ( lt24_lcd_d_en ), // LT24 LDC Data output enable
.lt24_lcd_reset_n_i ( lt24_lcd_reset_n ), // LT24 LDC Reset (Active Low)
.lt24_lcd_on_i ( lt24_lcd_on ), // LT24 LDC on/off
.lt24_adc_cs_n_i ( lt24_adc_cs_n ), // LT24 ADC Chip Select
.lt24_adc_dclk_i ( lt24_adc_dclk ), // LT24 ADC Clock
.lt24_adc_din_i ( lt24_adc_din ) // LT24 ADC Data In
);
//
// LT24 Interface
//----------------------------------
ogfx_if_lt24 dut_if_lt24 (
// Clock & Reset
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
// Peripheral Interface
.per_addr_i ( per_addr[13:0] ), // Peripheral address
.per_en_i ( per_en ), // Peripheral enable (high active)
.per_we_i ( per_we ), // Peripheral write enable (high active)
.per_din_i ( per_din ), // Peripheral data input
.per_dout_o ( per_dout_lt24 ), // Peripheral data output
.irq_lt24_lcd_o ( irq_lt24_lcd ), // LT24 LCD interface interrupt
.irq_lt24_adc_o ( irq_lt24_adc ), // LT24 ADC interface interrupt
// LT24 LCD Interface
.lt24_lcd_d_i ( lt24_lcd_din ), // LT24 Data input
.lt24_lcd_cs_n_o ( lt24_lcd_cs_n ), // LT24 Chip select (Active low)
.lt24_lcd_rd_n_o ( lt24_lcd_rd_n ), // LT24 Read strobe (Active low)
.lt24_lcd_wr_n_o ( lt24_lcd_wr_n ), // LT24 Write strobe (Active low)
.lt24_lcd_rs_o ( lt24_lcd_rs ), // LT24 Command/Param selection (Cmd=0/Param=1)
.lt24_lcd_d_o ( lt24_lcd_dout ), // LT24 Data output
.lt24_lcd_d_en_o ( lt24_lcd_d_en ), // LT24 Data output enable
.lt24_lcd_reset_n_o ( lt24_lcd_reset_n ), // LT24 Reset (Active Low)
.lt24_lcd_on_o ( lt24_lcd_on ), // LT24 on/off
// LT24 ADC Interface
.lt24_adc_busy_i ( lt24_adc_busy ), // LT24 ADC Busy
.lt24_adc_dout_i ( lt24_adc_dout ), // LT24 ADC Data Out
.lt24_adc_penirq_n_i ( lt24_adc_penirq_n ), // LT24 ADC Pen Interrupt
.lt24_adc_cs_n_o ( lt24_adc_cs_n ), // LT24 ADC Chip Select
.lt24_adc_dclk_o ( lt24_adc_dclk ), // LT24 ADC Clock
.lt24_adc_din_o ( lt24_adc_din ), // LT24 ADC Data In
// openGFX430 Interface
.screen_display_size_i ( screen_display_size ), // Display size configuration (number of pixels)
.screen_refresh_data_i ( screen_refresh_data ), // Display refresh data
.screen_refresh_data_ready_i ( screen_refresh_data_ready ), // Display refresh new data is ready
.screen_refresh_data_request_o ( screen_refresh_data_request ), // Display refresh new data request
.screen_refresh_active_o ( screen_refresh_active ) // Display refresh on going
);
//
// openGFX430 Instance
//----------------------------------
openGFX430 dut (
// Clock & Reset
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
// Peripheral Interface
.per_addr_i ( per_addr[13:0] ), // Peripheral address
.per_en_i ( per_en ), // Peripheral enable (high active)
.per_we_i ( per_we ), // Peripheral write enable (high active)
.per_din_i ( per_din ), // Peripheral data input
.per_dout_o ( per_dout_gfx ), // Peripheral data output
.dbg_freeze_i ( dbg_freeze ), // Freeze address auto-incr on read
.irq_gfx_o ( irq_gfx ), // Graphic Controller interrupt
// LUT SRAM Interface
`ifdef WITH_PROGRAMMABLE_LUT
.lut_ram_dout_i ( lut_ram_dout ), // LUT-RAM data output
.lut_ram_addr_o ( lut_ram_addr ), // LUT-RAM address
.lut_ram_wen_o ( lut_ram_wen ), // LUT-RAM write enable (active low)
.lut_ram_cen_o ( lut_ram_cen ), // LUT-RAM enable (active low)
.lut_ram_din_o ( lut_ram_din ), // LUT-RAM data input
`endif
// VIDEO SRAM Interface
.vid_ram_dout_i ( vid_ram_dout ), // Video-RAM data output
.vid_ram_addr_o ( vid_ram_addr ), // Video-RAM address
.vid_ram_wen_o ( vid_ram_wen ), // Video-RAM write enable (active low)
.vid_ram_cen_o ( vid_ram_cen ), // Video-RAM enable (active low)
.vid_ram_din_o ( vid_ram_din ), // Video-RAM data input
// Generic Screen Interface
.screen_refresh_active_i ( screen_refresh_active ), // Display refresh on going
.screen_refresh_data_request_i ( screen_refresh_data_request ), // Display refresh new data request
.screen_refresh_data_ready_o ( screen_refresh_data_ready ), // Display refresh new data is ready
.screen_refresh_data_o ( screen_refresh_data ), // Display refresh data
.screen_display_width_o ( screen_display_width ), // Display width configuration (number of pixels)
.screen_display_height_o ( screen_display_height ), // Display height configuration (number of pixels)
.screen_display_size_o ( screen_display_size ) // Display size configuration (number of pixels)
);
assign per_dout = per_dout_lt24 | per_dout_gfx;
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef NODUMP
`else
`ifdef VPD_FILE
$vcdplusfile("tb_openGFX430.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openGFX430.trn");
$recordvars;
`else
$dumpfile("tb_openGFX430.vcd");
$dumpvars(0, tb_openGFX430);
`endif
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#(1000ms);
`else
`ifdef LONG_TIMEOUT
#(100ms);
`else
#(10ms);
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$display("");
$finish;
`endif
end
initial // Normal end of test
begin
@(posedge stimulus_done);
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$display("");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
task tb_skip_finish;
input [65*8-1:0] skip_string;
begin
$display(" ===============================================");
$display("| SIMULATION SKIPPED |");
$display("%s", skip_string);
$display(" ===============================================");
$display("");
$finish;
end
endtask
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 10,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 29,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 50000,
altpll_component.intended_device_family = "Cyclone",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "20.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "58.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "29"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "50000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Stratix IV" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 11.0SP1 cbx_altiobuf_out 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ cbx_stratixv 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_io_obuf 2 stratixiv_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mem_if_ddr3_phy_0001_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obufa_o;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] oe_b;
wire [0:0] oe_w;
stratixiv_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(oe_b)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "stratixiv_io_obuf";
stratixiv_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(oe_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({14{1'b0}}),
.seriesterminationcontrol({14{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.shift_series_termination_control = "false",
obufa_0.lpm_type = "stratixiv_io_obuf";
stratixiv_pseudo_diff_out pseudo_diffa_0
(
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]));
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_b = 1'b1,
oe_w = 1'b1;
endmodule //altera_mem_if_ddr3_phy_0001_clock_pair_generator
//VALID FILE
|
// DM9000A.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module DM9000A (
input wire iCLK, // clk.clk
input wire iOSC_50, // avalon_slave_0_export.export
inout wire [15:0] ENET_DATA, // .export
output wire ENET_CMD, // .export
output wire ENET_RD_N, // .export
output wire ENET_WR_N, // .export
output wire ENET_CS_N, // .export
output wire ENET_RST_N, // .export
output wire ENET_CLK, // .export
input wire ENET_INT, // .export
input wire [15:0] iDATA, // avalon_slave_0.writedata
input wire iCMD, // .address
input wire iRD_N, // .read_n
input wire iWR_N, // .write_n
input wire iCS_N, // .chipselect_n
output wire [15:0] oDATA, // .readdata
output wire oINT, // avalon_slave_0_irq.irq
input wire iRST_N // reset_n.reset_n
);
DM9000A_IF dm9000a (
.iCLK (iCLK), // clk.clk
.iOSC_50 (iOSC_50), // avalon_slave_0_export.export
.ENET_DATA (ENET_DATA), // .export
.ENET_CMD (ENET_CMD), // .export
.ENET_RD_N (ENET_RD_N), // .export
.ENET_WR_N (ENET_WR_N), // .export
.ENET_CS_N (ENET_CS_N), // .export
.ENET_RST_N (ENET_RST_N), // .export
.ENET_CLK (ENET_CLK), // .export
.ENET_INT (ENET_INT), // .export
.iDATA (iDATA), // avalon_slave_0.writedata
.iCMD (iCMD), // .address
.iRD_N (iRD_N), // .read_n
.iWR_N (iWR_N), // .write_n
.iCS_N (iCS_N), // .chipselect_n
.oDATA (oDATA), // .readdata
.oINT (oINT), // avalon_slave_0_irq.irq
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/02/2017 11:05:01 PM
// Design Name:
// Module Name: edge_detect_sim
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: from http://www.doulos.com/knowhow/fpga/synchronisation/downloads/edge_detect.v
//
//////////////////////////////////////////////////////////////////////////////////
module edge_detect_sim;
reg clk, async;
wire rise, fall;
edge_detect uut (
.async_sig(async),
.clk(clk),
.rise(rise),
.fall(fall)
);
initial begin
clk = 0;
async = 0;
while ($time < 1000) begin
clk <= ~clk;
#5; // ns
end
end
// Produce a randomly-changing async signal.
integer seed;
time delay;
initial
begin
while ($time < 1000) begin
@(negedge clk);
// wait for a random number of ns
delay = $dist_uniform(seed, 50, 100);
#delay;
async = ~ async;
end
end
endmodule
|
module cordic_rom (
address,
X5,
Y5,clk);
input [3:0] address;
input clk;
output reg [21:0] X5;
output reg [21:0] Y5;
parameter[21:0] c0=22'b0111111111101010101010;
parameter[21:0] c1=22'b0111111101101010110010;
parameter[21:0] c2=22'b0111111001101011100010;
parameter[21:0] c3=22'b0111110011101101111010;
parameter[21:0] c4=22'b0111101011110011011001;
parameter[21:0] c5=22'b0111100001111101111101;
parameter[21:0] c6=22'b0111010110010000000101;
parameter[21:0] c7=22'b0111001000101100101011;
parameter[21:0] c8=22'b0110111001010111001000;
parameter[21:0] c9=22'b0110101000010011010010;
parameter[21:0] c10=22'b0110010101100101011001;
parameter[21:0] c11=22'b0110000001010010001001;
parameter[21:0] c12=22'b0101101011011110100110;
parameter[21:0] s0=22'b0000001111111111101010;
parameter[21:0] s1=22'b0000101111111011000000;
parameter[21:0] s2=22'b0001001111101010010111;
parameter[21:0] s3=22'b0001101111000101110100;
parameter[21:0] s4=22'b0010001110000101011111;
parameter[21:0] s5=22'b0010101100100001101011;
parameter[21:0] s6=22'b0011001010010010101111;
parameter[21:0] s7=22'b0011100111010001001111;
parameter[21:0] s8=22'b0100000011010101111100;
parameter[21:0] s9=22'b0100011110011001110101;
parameter[21:0] s10=22'b0100111000010110001001;
parameter[21:0] s11=22'b0101010001000100011001;
parameter[21:0] s12=22'b0101101000011110011001;//ÎÄÏ×ÖеÄÊý¾Ý
always@(posedge clk)
begin
case(address)
4'b0000:
begin
X5<=c0;
Y5<=s0;
end
4'b0001:
begin
X5<=c1;
Y5<=s1;
end
4'b0010:
begin
X5<=c2;
Y5<=s2;
end
4'b0011:
begin
X5<=c3;
Y5<=s3;
end
4'b0100:
begin
X5<=c4;
Y5<=s4;
end
4'b0101:
begin
X5<=c5;
Y5<=s5;
end
4'b0110:
begin
X5<=c6;
Y5<=s6;
end
4'b0111:
begin
X5<=c7;
Y5<=s7;
end
4'b1000:
begin
X5<=c8;
Y5<=s8;
end
4'b1001:
begin
X5<=c9;
Y5<=s9;
end
4'b1010:
begin
X5<=c10;
Y5<=s10;
end
4'b1011:
begin
X5<=c11;
Y5<=s11;
end
4'b1100:
begin
X5<=c12;
Y5<=s12;
end
default:
begin
X5<=0;
Y5<=0;
end
endcase
end
/*
always @(posedge clk)
begin
case(address)
4'd0:begin
X5=22'b0111111111101010101010;
Y5=22'b0000001111111111101010;
end
4'd1:begin
X5=22'b0111111101101010110010;
Y5=22'b0000101111111011000000;
end
4'd2:begin
X5=22'b0111111001101011100010;
Y5= 22'b0001001111101010010111;
end
4'd3:begin
X5=22'b0111110011101101111010;
Y5=22'b0001101111000101110100;
end
4'd4:begin
X5=22'b0111101011110011011001;
Y5=22'b0010001110000101011111;
end
4'd5:begin
X5=22'b0111100001111101111101;
Y5=22'b0010101100100001101011;
end
4'd6:begin
X5=22'b0111010110010000000101;
Y5=22'b0011001010010010101111;
end
4'd7:begin
X5=22'b0111001000101100101011;
Y5=22'b0011100111010001001111;
end
4'd8:begin
X5=22'b0110111001010111001000;
Y5=22'b0100000011010101111100;
end
4'd9:begin
X5=22'b0110101000010011010010;
Y5=22'b0100011110011001110101;
end
4'd10:begin
X5=22'b0110010101100101011001;
Y5=22'b0100111000010110001001;
end
4'd11:begin
X5=22'b0110000001010010001001;
Y5=22'b0101010001000100011001;
end
4'd12:begin
X5=22'b0101101011011110100110;
Y5=22'b0101101000011110011001;
end
default:begin
X5=0;
Y5=0;
$display("error address=%b",address);
end
endcase
end
*/
endmodule
|
module arbitrator(
//input
reset,
clk,
request0,
release0,
request1,
release1,
request2,
release2,
request3,
release3,
request4,
release4,
request5,
release5,
//output
permit0,
permit1,
permit2,
permit3,
permit4,
permit5
//state
);
input reset;
input clk;
input request0;
input release0;
input request1;
input release1;
input request2;
input release2;
input request3;
input release3;
input request4;
input release4;
input request5;
input release5;
output permit0;
output permit1;
output permit2;
output permit3;
output permit4;
output permit5;
//output [3:0] state;
reg permit0;
reg permit1;
reg permit2;
reg permit3;
reg permit4;
reg permit5;
parameter REQUEST0 =4'b0000;
parameter REQUEST1 =4'b0001;
parameter REQUEST2 =4'b0010;
parameter REQUEST3 =4'b0011;
parameter REQUEST4 =4'b0100;
parameter REQUEST5 =4'b0101;
parameter WAIT_RELEASE =4'b0110;
parameter WAIT_CYCLES =4'b0111;
parameter FINISH =4'b1111;
reg [3:0] state;
reg [2:0] count;
reg [3:0] index;
always@ (posedge clk or negedge reset)
begin
if(!reset)
begin
state <= REQUEST0;
permit0 <= 0;
permit1 <= 0;
permit2 <= 0;
permit3 <= 0;
permit4 <= 0;
permit5 <= 0;
index <= 0;
count <=0;
end
else
begin
case (state)
REQUEST0:
begin
if(request0)
begin
permit0 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST1;
end
else
begin
state <= REQUEST1;
end
end
REQUEST1:
begin
if(request1)
begin
permit1 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST2;
end
else
begin
state <= REQUEST2;
end
end
REQUEST2:
begin
if(request2)
begin
permit2 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST3;
end
else
begin
state <= REQUEST3;
end
end
REQUEST3:
begin
if(request3)
begin
permit3 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST4;
end
else
begin
state <= REQUEST4;
end
end
REQUEST4:
begin
if(request4)
begin
permit4 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST5;
end
else
begin
state <= REQUEST5;
end
end
REQUEST5:
begin
if(request5)
begin
permit5 <= 1;
state <= WAIT_RELEASE;
index <= REQUEST0;
end
else
begin
state <= REQUEST0;
end
end
WAIT_RELEASE:
begin
if(release0 | release1 | release2 | release3 | release4 | release5)
begin
permit0 <= 0;
permit1 <= 0;
permit2 <= 0;
permit3 <= 0;
permit4 <= 0;
permit5 <= 0;
count <= 0;
state <= WAIT_CYCLES;
end
else
state <= WAIT_RELEASE;
end
WAIT_CYCLES:
begin
if(count==4)
state <= FINISH;
else
count <= count+1;
end
FINISH:
begin
state <= index;
end
default:state <= REQUEST0;
endcase
end
end
endmodule
|
// system.v
// Generated using ACDS version 14.0 200 at 2015.04.28.12:22:51
`timescale 1 ps / 1 ps
module system (
input wire clk_50_clk, // clk_50.clk
input wire reset_50_reset_n, // reset_50.reset_n
output wire kernel_clk_clk, // kernel_clk.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
wire acl_iface_kernel_clk_clk; // acl_iface:kernel_clk_clk -> [Gaussian_Filter_system:clock, avs_Gaussian_cra_cra_ring:clk, cra_root:clk, irq_mapper:clk, mm_interconnect_0:acl_iface_kernel_clk_clk, mm_interconnect_1:acl_iface_kernel_clk_clk]
wire acl_iface_kernel_clk2x_clk; // acl_iface:kernel_clk2x_clk -> Gaussian_Filter_system:clock2x
wire acl_iface_kernel_reset_reset; // acl_iface:kernel_reset_reset_n -> [Gaussian_Filter_system:resetn, avs_Gaussian_cra_cra_ring:rst_n, cra_root:rst_n, irq_mapper:reset, mm_interconnect_0:Gaussian_Filter_system_clock_reset_reset_reset_bridge_in_reset_reset, mm_interconnect_1:cra_root_reset_reset_bridge_in_reset_reset]
wire avs_gaussian_cra_cra_ring_ring_in_waitrequest; // avs_Gaussian_cra_cra_ring:ri_waitrequest -> cra_root:ro_waitrequest
wire [7:0] cra_root_ring_out_byteena; // cra_root:ro_byteena -> avs_Gaussian_cra_cra_ring:ri_byteena
wire [63:0] cra_root_ring_out_data; // cra_root:ro_data -> avs_Gaussian_cra_cra_ring:ri_data
wire cra_root_ring_out_write; // cra_root:ro_write -> avs_Gaussian_cra_cra_ring:ri_write
wire cra_root_ring_out_read; // cra_root:ro_read -> avs_Gaussian_cra_cra_ring:ri_read
wire [3:0] cra_root_ring_out_addr; // cra_root:ro_addr -> avs_Gaussian_cra_cra_ring:ri_addr
wire cra_root_ring_out_datavalid; // cra_root:ro_datavalid -> avs_Gaussian_cra_cra_ring:ri_datavalid
wire avs_gaussian_cra_cra_ring_cra_master_waitrequest; // Gaussian_Filter_system:avs_Gaussian_cra_waitrequest -> avs_Gaussian_cra_cra_ring:avm_waitrequest
wire [63:0] avs_gaussian_cra_cra_ring_cra_master_writedata; // avs_Gaussian_cra_cra_ring:avm_writedata -> Gaussian_Filter_system:avs_Gaussian_cra_writedata
wire [3:0] avs_gaussian_cra_cra_ring_cra_master_address; // avs_Gaussian_cra_cra_ring:avm_addr -> Gaussian_Filter_system:avs_Gaussian_cra_address
wire avs_gaussian_cra_cra_ring_cra_master_write; // avs_Gaussian_cra_cra_ring:avm_write -> Gaussian_Filter_system:avs_Gaussian_cra_write
wire avs_gaussian_cra_cra_ring_cra_master_read; // avs_Gaussian_cra_cra_ring:avm_read -> Gaussian_Filter_system:avs_Gaussian_cra_read
wire [63:0] avs_gaussian_cra_cra_ring_cra_master_readdata; // Gaussian_Filter_system:avs_Gaussian_cra_readdata -> avs_Gaussian_cra_cra_ring:avm_readdata
wire avs_gaussian_cra_cra_ring_cra_master_readdatavalid; // Gaussian_Filter_system:avs_Gaussian_cra_readdatavalid -> avs_Gaussian_cra_cra_ring:avm_readdatavalid
wire [7:0] avs_gaussian_cra_cra_ring_cra_master_byteenable; // avs_Gaussian_cra_cra_ring:avm_byteena -> Gaussian_Filter_system:avs_Gaussian_cra_byteenable
wire cra_root_ring_in_waitrequest; // cra_root:ri_waitrequest -> avs_Gaussian_cra_cra_ring:ro_waitrequest
wire [7:0] avs_gaussian_cra_cra_ring_ring_out_byteena; // avs_Gaussian_cra_cra_ring:ro_byteena -> cra_root:ri_byteena
wire [63:0] avs_gaussian_cra_cra_ring_ring_out_data; // avs_Gaussian_cra_cra_ring:ro_data -> cra_root:ri_data
wire avs_gaussian_cra_cra_ring_ring_out_write; // avs_Gaussian_cra_cra_ring:ro_write -> cra_root:ri_write
wire avs_gaussian_cra_cra_ring_ring_out_read; // avs_Gaussian_cra_cra_ring:ro_read -> cra_root:ri_read
wire [3:0] avs_gaussian_cra_cra_ring_ring_out_addr; // avs_Gaussian_cra_cra_ring:ro_addr -> cra_root:ri_addr
wire avs_gaussian_cra_cra_ring_ring_out_datavalid; // avs_Gaussian_cra_cra_ring:ro_datavalid -> cra_root:ri_datavalid
wire gaussian_filter_system_avm_memgmem0_port_0_0_rw_waitrequest; // mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_waitrequest -> Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_waitrequest
wire [4:0] gaussian_filter_system_avm_memgmem0_port_0_0_rw_burstcount; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_burstcount -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_burstcount
wire [255:0] gaussian_filter_system_avm_memgmem0_port_0_0_rw_writedata; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_writedata -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_writedata
wire [29:0] gaussian_filter_system_avm_memgmem0_port_0_0_rw_address; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_address -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_address
wire gaussian_filter_system_avm_memgmem0_port_0_0_rw_write; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_write -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_write
wire gaussian_filter_system_avm_memgmem0_port_0_0_rw_read; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_read -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_read
wire [255:0] gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdata; // mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_readdata -> Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_readdata
wire gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdatavalid; // mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_readdatavalid -> Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_readdatavalid
wire [31:0] gaussian_filter_system_avm_memgmem0_port_0_0_rw_byteenable; // Gaussian_Filter_system:avm_memgmem0_port_0_0_rw_byteenable -> mm_interconnect_0:Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_byteenable
wire mm_interconnect_0_acl_iface_kernel_mem0_waitrequest; // acl_iface:kernel_mem0_waitrequest -> mm_interconnect_0:acl_iface_kernel_mem0_waitrequest
wire [4:0] mm_interconnect_0_acl_iface_kernel_mem0_burstcount; // mm_interconnect_0:acl_iface_kernel_mem0_burstcount -> acl_iface:kernel_mem0_burstcount
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_writedata; // mm_interconnect_0:acl_iface_kernel_mem0_writedata -> acl_iface:kernel_mem0_writedata
wire [29:0] mm_interconnect_0_acl_iface_kernel_mem0_address; // mm_interconnect_0:acl_iface_kernel_mem0_address -> acl_iface:kernel_mem0_address
wire mm_interconnect_0_acl_iface_kernel_mem0_write; // mm_interconnect_0:acl_iface_kernel_mem0_write -> acl_iface:kernel_mem0_write
wire mm_interconnect_0_acl_iface_kernel_mem0_read; // mm_interconnect_0:acl_iface_kernel_mem0_read -> acl_iface:kernel_mem0_read
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_readdata; // acl_iface:kernel_mem0_readdata -> mm_interconnect_0:acl_iface_kernel_mem0_readdata
wire mm_interconnect_0_acl_iface_kernel_mem0_debugaccess; // mm_interconnect_0:acl_iface_kernel_mem0_debugaccess -> acl_iface:kernel_mem0_debugaccess
wire mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid; // acl_iface:kernel_mem0_readdatavalid -> mm_interconnect_0:acl_iface_kernel_mem0_readdatavalid
wire [31:0] mm_interconnect_0_acl_iface_kernel_mem0_byteenable; // mm_interconnect_0:acl_iface_kernel_mem0_byteenable -> acl_iface:kernel_mem0_byteenable
wire [0:0] acl_iface_kernel_cra_burstcount; // acl_iface:kernel_cra_burstcount -> mm_interconnect_1:acl_iface_kernel_cra_burstcount
wire acl_iface_kernel_cra_waitrequest; // mm_interconnect_1:acl_iface_kernel_cra_waitrequest -> acl_iface:kernel_cra_waitrequest
wire [29:0] acl_iface_kernel_cra_address; // acl_iface:kernel_cra_address -> mm_interconnect_1:acl_iface_kernel_cra_address
wire [63:0] acl_iface_kernel_cra_writedata; // acl_iface:kernel_cra_writedata -> mm_interconnect_1:acl_iface_kernel_cra_writedata
wire acl_iface_kernel_cra_write; // acl_iface:kernel_cra_write -> mm_interconnect_1:acl_iface_kernel_cra_write
wire acl_iface_kernel_cra_read; // acl_iface:kernel_cra_read -> mm_interconnect_1:acl_iface_kernel_cra_read
wire [63:0] acl_iface_kernel_cra_readdata; // mm_interconnect_1:acl_iface_kernel_cra_readdata -> acl_iface:kernel_cra_readdata
wire acl_iface_kernel_cra_debugaccess; // acl_iface:kernel_cra_debugaccess -> mm_interconnect_1:acl_iface_kernel_cra_debugaccess
wire [7:0] acl_iface_kernel_cra_byteenable; // acl_iface:kernel_cra_byteenable -> mm_interconnect_1:acl_iface_kernel_cra_byteenable
wire acl_iface_kernel_cra_readdatavalid; // mm_interconnect_1:acl_iface_kernel_cra_readdatavalid -> acl_iface:kernel_cra_readdatavalid
wire mm_interconnect_1_cra_root_cra_slave_waitrequest; // cra_root:avs_waitrequest -> mm_interconnect_1:cra_root_cra_slave_waitrequest
wire [63:0] mm_interconnect_1_cra_root_cra_slave_writedata; // mm_interconnect_1:cra_root_cra_slave_writedata -> cra_root:avs_writedata
wire [3:0] mm_interconnect_1_cra_root_cra_slave_address; // mm_interconnect_1:cra_root_cra_slave_address -> cra_root:avs_addr
wire mm_interconnect_1_cra_root_cra_slave_write; // mm_interconnect_1:cra_root_cra_slave_write -> cra_root:avs_write
wire mm_interconnect_1_cra_root_cra_slave_read; // mm_interconnect_1:cra_root_cra_slave_read -> cra_root:avs_read
wire [63:0] mm_interconnect_1_cra_root_cra_slave_readdata; // cra_root:avs_readdata -> mm_interconnect_1:cra_root_cra_slave_readdata
wire mm_interconnect_1_cra_root_cra_slave_readdatavalid; // cra_root:avs_readdatavalid -> mm_interconnect_1:cra_root_cra_slave_readdatavalid
wire [7:0] mm_interconnect_1_cra_root_cra_slave_byteenable; // mm_interconnect_1:cra_root_cra_slave_byteenable -> cra_root:avs_byteena
wire irq_mapper_receiver0_irq; // Gaussian_Filter_system:kernel_irq -> irq_mapper:receiver0_irq
wire [0:0] acl_iface_kernel_irq_irq; // irq_mapper:sender_irq -> acl_iface:kernel_irq_irq
system_acl_iface acl_iface (
.config_clk_clk (clk_50_clk), // config_clk.clk
.reset_n (reset_50_reset_n), // global_reset.reset_n
.kernel_pll_refclk_clk (clk_50_clk), // kernel_pll_refclk.clk
.kernel_clk_clk (acl_iface_kernel_clk_clk), // kernel_clk.clk
.kernel_reset_reset_n (acl_iface_kernel_reset_reset), // kernel_reset.reset_n
.kernel_clk2x_clk (acl_iface_kernel_clk2x_clk), // kernel_clk2x.clk
.kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // kernel_mem0.waitrequest
.kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // .address
.kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess), // .debugaccess
.acl_kernel_clk_kernel_pll_locked_export (), // acl_kernel_clk_kernel_pll_locked.export
.kernel_clk_snoop_clk (kernel_clk_clk), // kernel_clk_snoop.clk
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ba (memory_mem_ba), // .mem_ba
.memory_mem_ck (memory_mem_ck), // .mem_ck
.memory_mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.memory_mem_cke (memory_mem_cke), // .mem_cke
.memory_mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.memory_mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.memory_mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.memory_mem_we_n (memory_mem_we_n), // .mem_we_n
.memory_mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.memory_mem_dq (memory_mem_dq), // .mem_dq
.memory_mem_dqs (memory_mem_dqs), // .mem_dqs
.memory_mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.memory_mem_odt (memory_mem_odt), // .mem_odt
.memory_mem_dm (memory_mem_dm), // .mem_dm
.memory_oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.peripheral_hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // peripheral.hps_io_emac1_inst_TX_CLK
.peripheral_hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.peripheral_hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.peripheral_hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.peripheral_hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.peripheral_hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.peripheral_hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.peripheral_hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.peripheral_hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.peripheral_hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.peripheral_hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.peripheral_hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.peripheral_hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.peripheral_hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.peripheral_hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.peripheral_hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.peripheral_hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.peripheral_hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.peripheral_hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.peripheral_hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.peripheral_hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.peripheral_hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.peripheral_hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.peripheral_hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.peripheral_hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.acl_internal_memorg_kernel_mode (), // acl_internal_memorg_kernel.mode
.kernel_irq_irq (acl_iface_kernel_irq_irq), // kernel_irq.irq
.kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.kernel_cra_address (acl_iface_kernel_cra_address), // .address
.kernel_cra_write (acl_iface_kernel_cra_write), // .write
.kernel_cra_read (acl_iface_kernel_cra_read), // .read
.kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.kernel_interface_acl_bsp_memorg_host_mode () // kernel_interface_acl_bsp_memorg_host.mode
);
Gaussian_Filter_system gaussian_filter_system (
.clock (acl_iface_kernel_clk_clk), // clock_reset.clk
.resetn (acl_iface_kernel_reset_reset), // clock_reset_reset.reset_n
.clock2x (acl_iface_kernel_clk2x_clk), // clock_reset2x.clk
.avs_Gaussian_cra_read (avs_gaussian_cra_cra_ring_cra_master_read), // avs_Gaussian_cra.read
.avs_Gaussian_cra_write (avs_gaussian_cra_cra_ring_cra_master_write), // .write
.avs_Gaussian_cra_address (avs_gaussian_cra_cra_ring_cra_master_address), // .address
.avs_Gaussian_cra_writedata (avs_gaussian_cra_cra_ring_cra_master_writedata), // .writedata
.avs_Gaussian_cra_byteenable (avs_gaussian_cra_cra_ring_cra_master_byteenable), // .byteenable
.avs_Gaussian_cra_waitrequest (avs_gaussian_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.avs_Gaussian_cra_readdata (avs_gaussian_cra_cra_ring_cra_master_readdata), // .readdata
.avs_Gaussian_cra_readdatavalid (avs_gaussian_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.kernel_irq (irq_mapper_receiver0_irq), // kernel_irq.irq
.avm_memgmem0_port_0_0_rw_address (gaussian_filter_system_avm_memgmem0_port_0_0_rw_address), // avm_memgmem0_port_0_0_rw.address
.avm_memgmem0_port_0_0_rw_read (gaussian_filter_system_avm_memgmem0_port_0_0_rw_read), // .read
.avm_memgmem0_port_0_0_rw_write (gaussian_filter_system_avm_memgmem0_port_0_0_rw_write), // .write
.avm_memgmem0_port_0_0_rw_burstcount (gaussian_filter_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.avm_memgmem0_port_0_0_rw_writedata (gaussian_filter_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.avm_memgmem0_port_0_0_rw_byteenable (gaussian_filter_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.avm_memgmem0_port_0_0_rw_readdata (gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.avm_memgmem0_port_0_0_rw_waitrequest (gaussian_filter_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.avm_memgmem0_port_0_0_rw_readdatavalid (gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdatavalid) // .readdatavalid
);
cra_ring_root #(
.ADDR_W (4),
.DATA_W (64),
.ID_W (0)
) cra_root (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avs_write (mm_interconnect_1_cra_root_cra_slave_write), // cra_slave.write
.avs_addr (mm_interconnect_1_cra_root_cra_slave_address), // .address
.avs_byteena (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.avs_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.avs_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.avs_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest), // .waitrequest
.avs_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.ri_write (avs_gaussian_cra_cra_ring_ring_out_write), // ring_in.write
.ri_addr (avs_gaussian_cra_cra_ring_ring_out_addr), // .addr
.ri_byteena (avs_gaussian_cra_cra_ring_ring_out_byteena), // .byteena
.ri_data (avs_gaussian_cra_cra_ring_ring_out_data), // .data
.ri_read (avs_gaussian_cra_cra_ring_ring_out_read), // .read
.ri_datavalid (avs_gaussian_cra_cra_ring_ring_out_datavalid), // .datavalid
.ri_waitrequest (cra_root_ring_in_waitrequest), // .waitrequest
.ro_read (cra_root_ring_out_read), // ring_out.read
.ro_write (cra_root_ring_out_write), // .write
.ro_addr (cra_root_ring_out_addr), // .addr
.ro_data (cra_root_ring_out_data), // .data
.ro_byteena (cra_root_ring_out_byteena), // .byteena
.ro_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ro_waitrequest (avs_gaussian_cra_cra_ring_ring_in_waitrequest) // .waitrequest
);
cra_ring_node #(
.RING_ADDR_W (4),
.CRA_ADDR_W (4),
.DATA_W (64),
.ID_W (0),
.ID (32'b00000000000000000000000000000000)
) avs_gaussian_cra_cra_ring (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avm_read (avs_gaussian_cra_cra_ring_cra_master_read), // cra_master.read
.avm_write (avs_gaussian_cra_cra_ring_cra_master_write), // .write
.avm_addr (avs_gaussian_cra_cra_ring_cra_master_address), // .address
.avm_byteena (avs_gaussian_cra_cra_ring_cra_master_byteenable), // .byteenable
.avm_writedata (avs_gaussian_cra_cra_ring_cra_master_writedata), // .writedata
.avm_readdata (avs_gaussian_cra_cra_ring_cra_master_readdata), // .readdata
.avm_readdatavalid (avs_gaussian_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.avm_waitrequest (avs_gaussian_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.ri_read (cra_root_ring_out_read), // ring_in.read
.ri_write (cra_root_ring_out_write), // .write
.ri_addr (cra_root_ring_out_addr), // .addr
.ri_data (cra_root_ring_out_data), // .data
.ri_byteena (cra_root_ring_out_byteena), // .byteena
.ri_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ri_waitrequest (avs_gaussian_cra_cra_ring_ring_in_waitrequest), // .waitrequest
.ro_read (avs_gaussian_cra_cra_ring_ring_out_read), // ring_out.read
.ro_write (avs_gaussian_cra_cra_ring_ring_out_write), // .write
.ro_addr (avs_gaussian_cra_cra_ring_ring_out_addr), // .addr
.ro_data (avs_gaussian_cra_cra_ring_ring_out_data), // .data
.ro_byteena (avs_gaussian_cra_cra_ring_ring_out_byteena), // .byteena
.ro_datavalid (avs_gaussian_cra_cra_ring_ring_out_datavalid), // .datavalid
.ro_waitrequest (cra_root_ring_in_waitrequest) // .waitrequest
);
system_mm_interconnect_0 mm_interconnect_0 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.Gaussian_Filter_system_clock_reset_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // Gaussian_Filter_system_clock_reset_reset_reset_bridge_in_reset.reset
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_address (gaussian_filter_system_avm_memgmem0_port_0_0_rw_address), // Gaussian_Filter_system_avm_memgmem0_port_0_0_rw.address
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_waitrequest (gaussian_filter_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_burstcount (gaussian_filter_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_byteenable (gaussian_filter_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_read (gaussian_filter_system_avm_memgmem0_port_0_0_rw_read), // .read
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_readdata (gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_readdatavalid (gaussian_filter_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_write (gaussian_filter_system_avm_memgmem0_port_0_0_rw_write), // .write
.Gaussian_Filter_system_avm_memgmem0_port_0_0_rw_writedata (gaussian_filter_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.acl_iface_kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // acl_iface_kernel_mem0.address
.acl_iface_kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.acl_iface_kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.acl_iface_kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.acl_iface_kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.acl_iface_kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.acl_iface_kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.acl_iface_kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.acl_iface_kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // .waitrequest
.acl_iface_kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess) // .debugaccess
);
system_mm_interconnect_1 mm_interconnect_1 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.cra_root_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // cra_root_reset_reset_bridge_in_reset.reset
.acl_iface_kernel_cra_address (acl_iface_kernel_cra_address), // acl_iface_kernel_cra.address
.acl_iface_kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.acl_iface_kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.acl_iface_kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.acl_iface_kernel_cra_read (acl_iface_kernel_cra_read), // .read
.acl_iface_kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.acl_iface_kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.acl_iface_kernel_cra_write (acl_iface_kernel_cra_write), // .write
.acl_iface_kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.acl_iface_kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.cra_root_cra_slave_address (mm_interconnect_1_cra_root_cra_slave_address), // cra_root_cra_slave.address
.cra_root_cra_slave_write (mm_interconnect_1_cra_root_cra_slave_write), // .write
.cra_root_cra_slave_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.cra_root_cra_slave_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.cra_root_cra_slave_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.cra_root_cra_slave_byteenable (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.cra_root_cra_slave_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.cra_root_cra_slave_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest) // .waitrequest
);
system_irq_mapper irq_mapper (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (~acl_iface_kernel_reset_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (acl_iface_kernel_irq_irq) // sender.irq
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo8_256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo8_256 (
input wire clock,
input wire [7:0] data,
input wire rdreq,
input wire sclr,
input wire wrreq,
output wire empty,
output wire full,
output wire [7:0] q,
output wire [8:0] usedw
);
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty ( empty ),
.full ( full ),
.q ( q ),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.usedw ( usedw ));
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone IV E",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo8_256_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module ahb_dummy (
input wire HCLK,
input wire HRESET_N,
input wire [`w_HADDR-1:0] HADDR,
input wire [`w_HTRANS-1:0] HTRANS,
input wire [`w_HBURST-1:0] HBURST,
input wire HWRITE,
input wire [`w_HSIZE-1:0] HSIZE,
input wire HSEL,
input wire [`w_HWDATA-1:0] HWDATA,
input wire HREADY_I,
output reg [`w_HRDATA-1:0] HRDATA,
output reg HREADY_O,
output wire [1:0] HRESP
);
assign HRESP = 2'h0;
always @(posedge HCLK) begin
if (!HRESET_N) begin
HRDATA <= `w_HRDATA'h0;
HREADY_O <= 1'b0;
end
else begin
HRDATA <= `w_HRDATA'h5A;
HREADY_O <= $urandom();
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND4_PP_BLACKBOX_V
/**
* and4: 4-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o311a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_PP_SYMBOL_V
|
//======================================================================
//
// gcm_ghash.v
// -----------
// GHASH module for the GCM core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module gcm_ghash(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [127 : 0] h0,
input wire [127 : 0] x,
output wire [127 : 0] y,
output wire ready
);
//----------------------------------------------------------------
// Gaolis multiplication functions.
//----------------------------------------------------------------
function [127 : 0] gm2(input [127 : 0] op);
begin
gm2 = {op[126 : 0], 1'b0} ^ (128'h1b & {128{op[127]}});
end
endfunction // gm2
function [127 : 0] gm3(input [127 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [127 : 0] gm4(input [127 : 0] op);
begin
gm4 = gm2(gm2(op));
end
endfunction // gm4
function [127 : 0] gm7(input [127 : 0] op);
begin
gm7 = gm4(op) ^ gm3(op);
end
endfunction // gm7
function [127 : 0] gm8(input [127 : 0] op);
begin
gm8 = gm2(gm4(op));
end
endfunction // gm8
function [127 : 0] gm16(input [127 : 0] op);
begin
gm16 = gm4(gm4(op));
end
endfunction // gm16
function [127 : 0] gm128(input [127 : 0] op);
begin
gm128 = gm8(gm16(op));
end
endfunction // gm128
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] op_reg;
reg [127 : 0] res_new;
reg [127 : 0] res_reg;
reg [127 : 0] pipe1_reg;
reg [127 : 0] pipe1_new;
reg [127 : 0] pipe2_reg;
reg [127 : 0] pipe2_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign y = res_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
op_reg <= 128'h0;
res_reg <= 128'h0;
pipe1_reg <= 128'h0;
pipe2_reg <= 128'h0;
end
else
begin
op_reg <= op;
res_reg <= res_new;
pipe1_reg <= pipe1_new;
pipe2_reg <= pipe2_new;
end
end // reg_update
//----------------------------------------------------------------
// gmult_logic
//----------------------------------------------------------------
always @*
begin : gmult_logic
pipe1_new = gm128(op_reg);
pipe2_new = gm7(op_reg) + gm2(op_reg) + op_reg + 1'b1;
res_new = pipe1_reg + pipe2_reg;
end // gmult_logic
endmodule // gcm_gmult
//======================================================================
// EOF gcm_ghash.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRBP_PP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_PP_SYMBOL_V
|
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module basys3_demo (
input clk,
output tx,
input rx,
input [15:0] sw,
output [15:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
wire iomem_valid;
reg iomem_ready;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
reg [31:0] iomem_rdata;
reg [31:0] gpio;
assign led = gpio[15:0];
always @(posedge clk) begin
if (!resetn) begin
gpio <= 0;
end else begin
iomem_ready <= 0;
if (iomem_valid && !iomem_ready && iomem_addr[31:24] == 8'h 03) begin
iomem_ready <= 1;
iomem_rdata <= {sw, gpio[15:0]};
if (iomem_wstrb[0]) gpio[ 7: 0] <= iomem_wdata[ 7: 0];
if (iomem_wstrb[1]) gpio[15: 8] <= iomem_wdata[15: 8];
if (iomem_wstrb[2]) gpio[23:16] <= iomem_wdata[23:16];
if (iomem_wstrb[3]) gpio[31:24] <= iomem_wdata[31:24];
end
end
end
picosoc_noflash soc (
.clk (clk),
.resetn (resetn ),
.ser_tx (tx),
.ser_rx (rx),
.irq_5 (1'b0 ),
.irq_6 (1'b0 ),
.irq_7 (1'b0 ),
.iomem_valid (iomem_valid ),
.iomem_ready (iomem_ready ),
.iomem_wstrb (iomem_wstrb ),
.iomem_addr (iomem_addr ),
.iomem_wdata (iomem_wdata ),
.iomem_rdata (iomem_rdata )
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_register.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_register.v,v $
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
// synopsys translate_off
`include "rtl/verilog/dbg_interface/timescale.v"
// synopsys translate_on
module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input [WIDTH-1:0] Default;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
//always @ (posedge Clk or posedge Reset)
always @ (posedge Clk)
begin
if(Reset)
DataOut[WIDTH-1:0]<=#1 Default;
else
begin
if(Write) // write
DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];
end
end
endmodule // Register
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dirvec_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: dirvec_dp.v
*/
////////////////////////////////////////////////////////////////////////
module sctag_dirvec_dp( /*AUTOARG*/
// Outputs
dirdp_req_vec_c6, dirdp_way_info_c7, dirdp_inval_pckt_c7, so,
// Inputs
se, si, ic_cam_hit, dc_cam_hit, tagdp_lkup_addr11_c5, sel_mux1_c6,
sel_mux2_c6, sel_mux3_c6, mux_vec_sel_c6, rclk
) ;
input se, si;
input [127:0] ic_cam_hit;
input [127:0] dc_cam_hit;
input tagdp_lkup_addr11_c5;
input [ 3:0] sel_mux1_c6;
input [ 3:0] sel_mux2_c6;
input sel_mux3_c6;
input [ 3:0] mux_vec_sel_c6;
input rclk;
output [ 7:0] dirdp_req_vec_c6;
output [ 2:0] dirdp_way_info_c7;
output [111:0] dirdp_inval_pckt_c7;
output so;
wire [127:0] dc_cam_hit_c6;
wire [127:0] ic_cam_hit_c6;
wire [127:0] dc_cam_hit_c5;
wire [ 63:0] ic_cam_hit_c5;
wire [111:0] dirdp_inval_pckt_c6;
wire [ 2:0] dirvecdp_way_info_c6;
wire [111:0] dirdp_inval_pckt_c7;
wire [ 2:0] dirvecdp_way_info_c7;
//************************************************************************************
// FLOP INVAL PCKT TILL C6
//************************************************************************************
dff_s #(112) ff_dirdp_inval_pckt_c7 (.din(dirdp_inval_pckt_c6[111:0]),
.clk(rclk),
.q(dirdp_inval_pckt_c7[111:0]),
.se(se),
.si(),
.so());
//************************************************************************************
// FLOP way INFO PCKT TILL C6
//************************************************************************************
dff_s #(3) ff_dirvecdp_way_info_c7 (.din(dirvecdp_way_info_c6[2:0]),
.clk(rclk),
.q(dirvecdp_way_info_c7[2:0]),
.se(se),
.si(),
.so());
assign dirdp_way_info_c7 = dirvecdp_way_info_c7 ;
//*****************************************************************************
// PIPELINE FOR DIR VEC GENERATION
// DC cam hit has to be 128 b.
// IC cam hit is 64b and the 128b output of icdir needs to be muxed.
//*****************************************************************************
assign dc_cam_hit_c5 = dc_cam_hit ;
dff_s #(128) ff_dc_cam_hit_c6 ( .din(dc_cam_hit_c5[127:0]),
.clk(rclk),
.q(dc_cam_hit_c6[127:0]),
.se(se),
.si(),
.so());
mux2ds #(32) mux1_cam_hit_c5 ( .dout(ic_cam_hit_c5[31:0]),
.in0(ic_cam_hit[31:0]),
.in1(ic_cam_hit[63:32]),
.sel0(~tagdp_lkup_addr11_c5),
.sel1(tagdp_lkup_addr11_c5));
mux2ds #(32) mux2_cam_hit_c5 ( .dout(ic_cam_hit_c5[63:32]),
.in0(ic_cam_hit[95:64]),
.in1(ic_cam_hit[127:96]),
.sel0(~tagdp_lkup_addr11_c5),
.sel1(tagdp_lkup_addr11_c5));
dff_s #(32) ff_dc1_cam_hit_c6 ( .din(ic_cam_hit_c5[31:0]),
.clk(rclk),
.q(ic_cam_hit_c6[31:0]),
.se(se),
.si(),
.so());
dff_s #(32) ff_dc2_cam_hit_c6 ( .din(ic_cam_hit_c5[63:32]),
.clk(rclk),
.q(ic_cam_hit_c6[95:64]),
.se(se),
.si(),
.so());
//*****************************************************************************
// FORM THE 112b PACKET in C4 ( step 1)
// Get the request vect to be sent to oq_dp
// Get the I$ and D$ invalidation way for L1 load misses.
// DC cam hit has to be 128 b.
// IC cam hit is 64b and the 128b output of icdir needs to be muxed.
//*****************************************************************************
// BITS 0 - 31 CORRESPOND to INDEX <5:4> = 00 for D$
// INDEX <5>=0 for I$
// GENERATED CODE
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec0_c6;
wire ic_dir_vec0_c6;
wire dir_hit_vec0_c6 ;
wire [1:0] enc_dc_vec0_way_c6;
wire [1:0] enc_ic_vec0_way_c6;
wire [1:0] enc_c_vec0_way_c6;
wire [2:0] way_way_vld0_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec4_c6;
wire ic_dir_vec4_c6;
wire dir_hit_vec4_c6 ;
wire [1:0] enc_dc_vec4_way_c6;
wire [1:0] enc_ic_vec4_way_c6;
wire [1:0] enc_c_vec4_way_c6;
wire [2:0] way_way_vld4_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec8_c6;
wire ic_dir_vec8_c6;
wire dir_hit_vec8_c6 ;
wire [1:0] enc_dc_vec8_way_c6;
wire [1:0] enc_ic_vec8_way_c6;
wire [1:0] enc_c_vec8_way_c6;
wire [2:0] way_way_vld8_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec12_c6;
wire ic_dir_vec12_c6;
wire dir_hit_vec12_c6 ;
wire [1:0] enc_dc_vec12_way_c6;
wire [1:0] enc_ic_vec12_way_c6;
wire [1:0] enc_c_vec12_way_c6;
wire [2:0] way_way_vld12_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec16_c6;
wire ic_dir_vec16_c6;
wire dir_hit_vec16_c6 ;
wire [1:0] enc_dc_vec16_way_c6;
wire [1:0] enc_ic_vec16_way_c6;
wire [1:0] enc_c_vec16_way_c6;
wire [2:0] way_way_vld16_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec20_c6;
wire ic_dir_vec20_c6;
wire dir_hit_vec20_c6 ;
wire [1:0] enc_dc_vec20_way_c6;
wire [1:0] enc_ic_vec20_way_c6;
wire [1:0] enc_c_vec20_way_c6;
wire [2:0] way_way_vld20_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec24_c6;
wire ic_dir_vec24_c6;
wire dir_hit_vec24_c6 ;
wire [1:0] enc_dc_vec24_way_c6;
wire [1:0] enc_ic_vec24_way_c6;
wire [1:0] enc_c_vec24_way_c6;
wire [2:0] way_way_vld24_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec28_c6;
wire ic_dir_vec28_c6;
wire dir_hit_vec28_c6 ;
wire [1:0] enc_dc_vec28_way_c6;
wire [1:0] enc_ic_vec28_way_c6;
wire [1:0] enc_c_vec28_way_c6;
wire [2:0] way_way_vld28_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec0_c6 = ( dc_cam_hit_c6[0] | dc_cam_hit_c6[1] |
dc_cam_hit_c6[2] | dc_cam_hit_c6[3] ) ;
// indicates whether I
assign ic_dir_vec0_c6 = ( ic_cam_hit_c6[0] | ic_cam_hit_c6[1] |
ic_cam_hit_c6[2] | ic_cam_hit_c6[3] ) ;
// indicates whether hit
assign dir_hit_vec0_c6 = dc_dir_vec0_c6 | ic_dir_vec0_c6 ;
// hit way in D
assign enc_dc_vec0_way_c6[0] = dc_cam_hit_c6[1] | dc_cam_hit_c6[3] ;
assign enc_dc_vec0_way_c6[1] = dc_cam_hit_c6[2] | dc_cam_hit_c6[3] ;
// hit way in I
assign enc_ic_vec0_way_c6[0] = ic_cam_hit_c6[1] | ic_cam_hit_c6[3] ;
assign enc_ic_vec0_way_c6[1] = ic_cam_hit_c6[2] | ic_cam_hit_c6[3] ;
mux2ds #(2) mux2_c_vec0_way ( .dout(enc_c_vec0_way_c6[1:0]),
.in0(enc_dc_vec0_way_c6[1:0]),
.in1(enc_ic_vec0_way_c6[1:0]),
.sel0(~ic_dir_vec0_c6),
.sel1(ic_dir_vec0_c6));
assign way_way_vld0_c6[0] = enc_c_vec0_way_c6[0] ;
assign way_way_vld0_c6[1] = enc_c_vec0_way_c6[1] ;
assign way_way_vld0_c6[2] = dir_hit_vec0_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec4_c6 = ( dc_cam_hit_c6[4] | dc_cam_hit_c6[5] |
dc_cam_hit_c6[6] | dc_cam_hit_c6[7] ) ;
// indicates whether I
assign ic_dir_vec4_c6 = ( ic_cam_hit_c6[4] | ic_cam_hit_c6[5] |
ic_cam_hit_c6[6] | ic_cam_hit_c6[7] ) ;
// indicates whether hit
assign dir_hit_vec4_c6 = dc_dir_vec4_c6 | ic_dir_vec4_c6 ;
// hit way in D
assign enc_dc_vec4_way_c6[0] = dc_cam_hit_c6[5] | dc_cam_hit_c6[7] ;
assign enc_dc_vec4_way_c6[1] = dc_cam_hit_c6[6] | dc_cam_hit_c6[7] ;
// hit way in I
assign enc_ic_vec4_way_c6[0] = ic_cam_hit_c6[5] | ic_cam_hit_c6[7] ;
assign enc_ic_vec4_way_c6[1] = ic_cam_hit_c6[6] | ic_cam_hit_c6[7] ;
mux2ds #(2) mux2_c_vec4_way ( .dout(enc_c_vec4_way_c6[1:0]),
.in0(enc_dc_vec4_way_c6[1:0]),
.in1(enc_ic_vec4_way_c6[1:0]),
.sel0(~ic_dir_vec4_c6),
.sel1(ic_dir_vec4_c6));
assign way_way_vld4_c6[0] = enc_c_vec4_way_c6[0] ;
assign way_way_vld4_c6[1] = enc_c_vec4_way_c6[1] ;
assign way_way_vld4_c6[2] = dir_hit_vec4_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec8_c6 = ( dc_cam_hit_c6[8] | dc_cam_hit_c6[9] |
dc_cam_hit_c6[10] | dc_cam_hit_c6[11] ) ;
// indicates whether I
assign ic_dir_vec8_c6 = ( ic_cam_hit_c6[8] | ic_cam_hit_c6[9] |
ic_cam_hit_c6[10] | ic_cam_hit_c6[11] ) ;
// indicates whether hit
assign dir_hit_vec8_c6 = dc_dir_vec8_c6 | ic_dir_vec8_c6 ;
// hit way in D
assign enc_dc_vec8_way_c6[0] = dc_cam_hit_c6[9] | dc_cam_hit_c6[11] ;
assign enc_dc_vec8_way_c6[1] = dc_cam_hit_c6[10] | dc_cam_hit_c6[11] ;
// hit way in I
assign enc_ic_vec8_way_c6[0] = ic_cam_hit_c6[9] | ic_cam_hit_c6[11] ;
assign enc_ic_vec8_way_c6[1] = ic_cam_hit_c6[10] | ic_cam_hit_c6[11] ;
mux2ds #(2) mux2_c_vec8_way ( .dout(enc_c_vec8_way_c6[1:0]),
.in0(enc_dc_vec8_way_c6[1:0]),
.in1(enc_ic_vec8_way_c6[1:0]),
.sel0(~ic_dir_vec8_c6),
.sel1(ic_dir_vec8_c6));
assign way_way_vld8_c6[0] = enc_c_vec8_way_c6[0] ;
assign way_way_vld8_c6[1] = enc_c_vec8_way_c6[1] ;
assign way_way_vld8_c6[2] = dir_hit_vec8_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec12_c6 = ( dc_cam_hit_c6[12] | dc_cam_hit_c6[13] |
dc_cam_hit_c6[14] | dc_cam_hit_c6[15] ) ;
// indicates whether I
assign ic_dir_vec12_c6 = ( ic_cam_hit_c6[12] | ic_cam_hit_c6[13] |
ic_cam_hit_c6[14] | ic_cam_hit_c6[15] ) ;
// indicates whether hit
assign dir_hit_vec12_c6 = dc_dir_vec12_c6 | ic_dir_vec12_c6 ;
// hit way in D
assign enc_dc_vec12_way_c6[0] = dc_cam_hit_c6[13] | dc_cam_hit_c6[15] ;
assign enc_dc_vec12_way_c6[1] = dc_cam_hit_c6[14] | dc_cam_hit_c6[15] ;
// hit way in I
assign enc_ic_vec12_way_c6[0] = ic_cam_hit_c6[13] | ic_cam_hit_c6[15] ;
assign enc_ic_vec12_way_c6[1] = ic_cam_hit_c6[14] | ic_cam_hit_c6[15] ;
mux2ds #(2) mux2_c_vec12_way ( .dout(enc_c_vec12_way_c6[1:0]),
.in0(enc_dc_vec12_way_c6[1:0]),
.in1(enc_ic_vec12_way_c6[1:0]),
.sel0(~ic_dir_vec12_c6),
.sel1(ic_dir_vec12_c6));
assign way_way_vld12_c6[0] = enc_c_vec12_way_c6[0] ;
assign way_way_vld12_c6[1] = enc_c_vec12_way_c6[1] ;
assign way_way_vld12_c6[2] = dir_hit_vec12_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec16_c6 = ( dc_cam_hit_c6[16] | dc_cam_hit_c6[17] |
dc_cam_hit_c6[18] | dc_cam_hit_c6[19] ) ;
// indicates whether I
assign ic_dir_vec16_c6 = ( ic_cam_hit_c6[16] | ic_cam_hit_c6[17] |
ic_cam_hit_c6[18] | ic_cam_hit_c6[19] ) ;
// indicates whether hit
assign dir_hit_vec16_c6 = dc_dir_vec16_c6 | ic_dir_vec16_c6 ;
// hit way in D
assign enc_dc_vec16_way_c6[0] = dc_cam_hit_c6[17] | dc_cam_hit_c6[19] ;
assign enc_dc_vec16_way_c6[1] = dc_cam_hit_c6[18] | dc_cam_hit_c6[19] ;
// hit way in I
assign enc_ic_vec16_way_c6[0] = ic_cam_hit_c6[17] | ic_cam_hit_c6[19] ;
assign enc_ic_vec16_way_c6[1] = ic_cam_hit_c6[18] | ic_cam_hit_c6[19] ;
mux2ds #(2) mux2_c_vec16_way ( .dout(enc_c_vec16_way_c6[1:0]),
.in0(enc_dc_vec16_way_c6[1:0]),
.in1(enc_ic_vec16_way_c6[1:0]),
.sel0(~ic_dir_vec16_c6),
.sel1(ic_dir_vec16_c6));
assign way_way_vld16_c6[0] = enc_c_vec16_way_c6[0] ;
assign way_way_vld16_c6[1] = enc_c_vec16_way_c6[1] ;
assign way_way_vld16_c6[2] = dir_hit_vec16_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec20_c6 = ( dc_cam_hit_c6[20] | dc_cam_hit_c6[21] |
dc_cam_hit_c6[22] | dc_cam_hit_c6[23] ) ;
// indicates whether I
assign ic_dir_vec20_c6 = ( ic_cam_hit_c6[20] | ic_cam_hit_c6[21] |
ic_cam_hit_c6[22] | ic_cam_hit_c6[23] ) ;
// indicates whether hit
assign dir_hit_vec20_c6 = dc_dir_vec20_c6 | ic_dir_vec20_c6 ;
// hit way in D
assign enc_dc_vec20_way_c6[0] = dc_cam_hit_c6[21] | dc_cam_hit_c6[23] ;
assign enc_dc_vec20_way_c6[1] = dc_cam_hit_c6[22] | dc_cam_hit_c6[23] ;
// hit way in I
assign enc_ic_vec20_way_c6[0] = ic_cam_hit_c6[21] | ic_cam_hit_c6[23] ;
assign enc_ic_vec20_way_c6[1] = ic_cam_hit_c6[22] | ic_cam_hit_c6[23] ;
mux2ds #(2) mux2_c_vec20_way ( .dout(enc_c_vec20_way_c6[1:0]),
.in0(enc_dc_vec20_way_c6[1:0]),
.in1(enc_ic_vec20_way_c6[1:0]),
.sel0(~ic_dir_vec20_c6),
.sel1(ic_dir_vec20_c6));
assign way_way_vld20_c6[0] = enc_c_vec20_way_c6[0] ;
assign way_way_vld20_c6[1] = enc_c_vec20_way_c6[1] ;
assign way_way_vld20_c6[2] = dir_hit_vec20_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec24_c6 = ( dc_cam_hit_c6[24] | dc_cam_hit_c6[25] |
dc_cam_hit_c6[26] | dc_cam_hit_c6[27] ) ;
// indicates whether I
assign ic_dir_vec24_c6 = ( ic_cam_hit_c6[24] | ic_cam_hit_c6[25] |
ic_cam_hit_c6[26] | ic_cam_hit_c6[27] ) ;
// indicates whether hit
assign dir_hit_vec24_c6 = dc_dir_vec24_c6 | ic_dir_vec24_c6 ;
// hit way in D
assign enc_dc_vec24_way_c6[0] = dc_cam_hit_c6[25] | dc_cam_hit_c6[27] ;
assign enc_dc_vec24_way_c6[1] = dc_cam_hit_c6[26] | dc_cam_hit_c6[27] ;
// hit way in I
assign enc_ic_vec24_way_c6[0] = ic_cam_hit_c6[25] | ic_cam_hit_c6[27] ;
assign enc_ic_vec24_way_c6[1] = ic_cam_hit_c6[26] | ic_cam_hit_c6[27] ;
mux2ds #(2) mux2_c_vec24_way ( .dout(enc_c_vec24_way_c6[1:0]),
.in0(enc_dc_vec24_way_c6[1:0]),
.in1(enc_ic_vec24_way_c6[1:0]),
.sel0(~ic_dir_vec24_c6),
.sel1(ic_dir_vec24_c6));
assign way_way_vld24_c6[0] = enc_c_vec24_way_c6[0] ;
assign way_way_vld24_c6[1] = enc_c_vec24_way_c6[1] ;
assign way_way_vld24_c6[2] = dir_hit_vec24_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec28_c6 = ( dc_cam_hit_c6[28] | dc_cam_hit_c6[29] |
dc_cam_hit_c6[30] | dc_cam_hit_c6[31] ) ;
// indicates whether I
assign ic_dir_vec28_c6 = ( ic_cam_hit_c6[28] | ic_cam_hit_c6[29] |
ic_cam_hit_c6[30] | ic_cam_hit_c6[31] ) ;
// indicates whether hit
assign dir_hit_vec28_c6 = dc_dir_vec28_c6 | ic_dir_vec28_c6 ;
// hit way in D
assign enc_dc_vec28_way_c6[0] = dc_cam_hit_c6[29] | dc_cam_hit_c6[31] ;
assign enc_dc_vec28_way_c6[1] = dc_cam_hit_c6[30] | dc_cam_hit_c6[31] ;
// hit way in I
assign enc_ic_vec28_way_c6[0] = ic_cam_hit_c6[29] | ic_cam_hit_c6[31] ;
assign enc_ic_vec28_way_c6[1] = ic_cam_hit_c6[30] | ic_cam_hit_c6[31] ;
mux2ds #(2) mux2_c_vec28_way ( .dout(enc_c_vec28_way_c6[1:0]),
.in0(enc_dc_vec28_way_c6[1:0]),
.in1(enc_ic_vec28_way_c6[1:0]),
.sel0(~ic_dir_vec28_c6),
.sel1(ic_dir_vec28_c6));
assign way_way_vld28_c6[0] = enc_c_vec28_way_c6[0] ;
assign way_way_vld28_c6[1] = enc_c_vec28_way_c6[1] ;
assign way_way_vld28_c6[2] = dir_hit_vec28_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating way wayvld00 ******************/
wire [2:0] way_wayvld00_mux1_c6;
wire [2:0] way_wayvld00_mux2_c6;
wire [2:0] way_wayvld00_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux1_c6[2:0]),
.in0(way_way_vld0_c6[2:0]),
.in1(way_way_vld4_c6[2:0]),
.in2(way_way_vld8_c6[2:0]),
.in3(way_way_vld12_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux2_c6[2:0]),
.in0(way_way_vld16_c6[2:0]),
.in1(way_way_vld20_c6[2:0]),
.in2(way_way_vld24_c6[2:0]),
.in3(way_way_vld28_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux3_c6[2:0]),
.in0(way_wayvld00_mux1_c6[2:0]),
.in1(way_wayvld00_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** END code for generating way wayvld00 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec32_c6;
wire dir_hit_vec32_c6 ;
wire [1:0] enc_dc_vec32_way_c6;
wire [1:0] enc_c_vec32_way_c6;
wire [2:0] way_way_vld32_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec36_c6;
wire dir_hit_vec36_c6 ;
wire [1:0] enc_dc_vec36_way_c6;
wire [1:0] enc_c_vec36_way_c6;
wire [2:0] way_way_vld36_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec40_c6;
wire dir_hit_vec40_c6 ;
wire [1:0] enc_dc_vec40_way_c6;
wire [1:0] enc_c_vec40_way_c6;
wire [2:0] way_way_vld40_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec44_c6;
wire dir_hit_vec44_c6 ;
wire [1:0] enc_dc_vec44_way_c6;
wire [1:0] enc_c_vec44_way_c6;
wire [2:0] way_way_vld44_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec48_c6;
wire dir_hit_vec48_c6 ;
wire [1:0] enc_dc_vec48_way_c6;
wire [1:0] enc_c_vec48_way_c6;
wire [2:0] way_way_vld48_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec52_c6;
wire dir_hit_vec52_c6 ;
wire [1:0] enc_dc_vec52_way_c6;
wire [1:0] enc_c_vec52_way_c6;
wire [2:0] way_way_vld52_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec56_c6;
wire dir_hit_vec56_c6 ;
wire [1:0] enc_dc_vec56_way_c6;
wire [1:0] enc_c_vec56_way_c6;
wire [2:0] way_way_vld56_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec60_c6;
wire dir_hit_vec60_c6 ;
wire [1:0] enc_dc_vec60_way_c6;
wire [1:0] enc_c_vec60_way_c6;
wire [2:0] way_way_vld60_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec32_c6 = ( dc_cam_hit_c6[32] | dc_cam_hit_c6[33] |
dc_cam_hit_c6[34] | dc_cam_hit_c6[35] ) ;
// hit way in D
assign enc_dc_vec32_way_c6[0] = dc_cam_hit_c6[33] | dc_cam_hit_c6[35] ;
assign enc_dc_vec32_way_c6[1] = dc_cam_hit_c6[34] | dc_cam_hit_c6[35] ;
assign dir_hit_vec32_c6 = dc_dir_vec32_c6 ;
assign enc_c_vec32_way_c6[1:0] = enc_dc_vec32_way_c6[1:0] ;
assign way_way_vld32_c6[0] = enc_c_vec32_way_c6[0] ;
assign way_way_vld32_c6[1] = enc_c_vec32_way_c6[1] ;
assign way_way_vld32_c6[2] = dir_hit_vec32_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec36_c6 = ( dc_cam_hit_c6[36] | dc_cam_hit_c6[37] |
dc_cam_hit_c6[38] | dc_cam_hit_c6[39] ) ;
// hit way in D
assign enc_dc_vec36_way_c6[0] = dc_cam_hit_c6[37] | dc_cam_hit_c6[39] ;
assign enc_dc_vec36_way_c6[1] = dc_cam_hit_c6[38] | dc_cam_hit_c6[39] ;
assign dir_hit_vec36_c6 = dc_dir_vec36_c6 ;
assign enc_c_vec36_way_c6[1:0] = enc_dc_vec36_way_c6[1:0] ;
assign way_way_vld36_c6[0] = enc_c_vec36_way_c6[0] ;
assign way_way_vld36_c6[1] = enc_c_vec36_way_c6[1] ;
assign way_way_vld36_c6[2] = dir_hit_vec36_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec40_c6 = ( dc_cam_hit_c6[40] | dc_cam_hit_c6[41] |
dc_cam_hit_c6[42] | dc_cam_hit_c6[43] ) ;
// hit way in D
assign enc_dc_vec40_way_c6[0] = dc_cam_hit_c6[41] | dc_cam_hit_c6[43] ;
assign enc_dc_vec40_way_c6[1] = dc_cam_hit_c6[42] | dc_cam_hit_c6[43] ;
assign dir_hit_vec40_c6 = dc_dir_vec40_c6 ;
assign enc_c_vec40_way_c6[1:0] = enc_dc_vec40_way_c6[1:0] ;
assign way_way_vld40_c6[0] = enc_c_vec40_way_c6[0] ;
assign way_way_vld40_c6[1] = enc_c_vec40_way_c6[1] ;
assign way_way_vld40_c6[2] = dir_hit_vec40_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec44_c6 = ( dc_cam_hit_c6[44] | dc_cam_hit_c6[45] |
dc_cam_hit_c6[46] | dc_cam_hit_c6[47] ) ;
// hit way in D
assign enc_dc_vec44_way_c6[0] = dc_cam_hit_c6[45] | dc_cam_hit_c6[47] ;
assign enc_dc_vec44_way_c6[1] = dc_cam_hit_c6[46] | dc_cam_hit_c6[47] ;
assign dir_hit_vec44_c6 = dc_dir_vec44_c6 ;
assign enc_c_vec44_way_c6[1:0] = enc_dc_vec44_way_c6[1:0] ;
assign way_way_vld44_c6[0] = enc_c_vec44_way_c6[0] ;
assign way_way_vld44_c6[1] = enc_c_vec44_way_c6[1] ;
assign way_way_vld44_c6[2] = dir_hit_vec44_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec48_c6 = ( dc_cam_hit_c6[48] | dc_cam_hit_c6[49] |
dc_cam_hit_c6[50] | dc_cam_hit_c6[51] ) ;
// hit way in D
assign enc_dc_vec48_way_c6[0] = dc_cam_hit_c6[49] | dc_cam_hit_c6[51] ;
assign enc_dc_vec48_way_c6[1] = dc_cam_hit_c6[50] | dc_cam_hit_c6[51] ;
assign dir_hit_vec48_c6 = dc_dir_vec48_c6 ;
assign enc_c_vec48_way_c6[1:0] = enc_dc_vec48_way_c6[1:0] ;
assign way_way_vld48_c6[0] = enc_c_vec48_way_c6[0] ;
assign way_way_vld48_c6[1] = enc_c_vec48_way_c6[1] ;
assign way_way_vld48_c6[2] = dir_hit_vec48_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec52_c6 = ( dc_cam_hit_c6[52] | dc_cam_hit_c6[53] |
dc_cam_hit_c6[54] | dc_cam_hit_c6[55] ) ;
// hit way in D
assign enc_dc_vec52_way_c6[0] = dc_cam_hit_c6[53] | dc_cam_hit_c6[55] ;
assign enc_dc_vec52_way_c6[1] = dc_cam_hit_c6[54] | dc_cam_hit_c6[55] ;
assign dir_hit_vec52_c6 = dc_dir_vec52_c6 ;
assign enc_c_vec52_way_c6[1:0] = enc_dc_vec52_way_c6[1:0] ;
assign way_way_vld52_c6[0] = enc_c_vec52_way_c6[0] ;
assign way_way_vld52_c6[1] = enc_c_vec52_way_c6[1] ;
assign way_way_vld52_c6[2] = dir_hit_vec52_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec56_c6 = ( dc_cam_hit_c6[56] | dc_cam_hit_c6[57] |
dc_cam_hit_c6[58] | dc_cam_hit_c6[59] ) ;
// hit way in D
assign enc_dc_vec56_way_c6[0] = dc_cam_hit_c6[57] | dc_cam_hit_c6[59] ;
assign enc_dc_vec56_way_c6[1] = dc_cam_hit_c6[58] | dc_cam_hit_c6[59] ;
assign dir_hit_vec56_c6 = dc_dir_vec56_c6 ;
assign enc_c_vec56_way_c6[1:0] = enc_dc_vec56_way_c6[1:0] ;
assign way_way_vld56_c6[0] = enc_c_vec56_way_c6[0] ;
assign way_way_vld56_c6[1] = enc_c_vec56_way_c6[1] ;
assign way_way_vld56_c6[2] = dir_hit_vec56_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec60_c6 = ( dc_cam_hit_c6[60] | dc_cam_hit_c6[61] |
dc_cam_hit_c6[62] | dc_cam_hit_c6[63] ) ;
// hit way in D
assign enc_dc_vec60_way_c6[0] = dc_cam_hit_c6[61] | dc_cam_hit_c6[63] ;
assign enc_dc_vec60_way_c6[1] = dc_cam_hit_c6[62] | dc_cam_hit_c6[63] ;
assign dir_hit_vec60_c6 = dc_dir_vec60_c6 ;
assign enc_c_vec60_way_c6[1:0] = enc_dc_vec60_way_c6[1:0] ;
assign way_way_vld60_c6[0] = enc_c_vec60_way_c6[0] ;
assign way_way_vld60_c6[1] = enc_c_vec60_way_c6[1] ;
assign way_way_vld60_c6[2] = dir_hit_vec60_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld01_mux1_c6;
wire [2:0] way_wayvld01_mux2_c6;
wire [2:0] way_wayvld01_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux1_c6[2:0]),
.in0(way_way_vld32_c6[2:0]),
.in1(way_way_vld36_c6[2:0]),
.in2(way_way_vld40_c6[2:0]),
.in3(way_way_vld44_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux2_c6[2:0]),
.in0(way_way_vld48_c6[2:0]),
.in1(way_way_vld52_c6[2:0]),
.in2(way_way_vld56_c6[2:0]),
.in3(way_way_vld60_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux3_c6[2:0]),
.in0(way_wayvld01_mux1_c6[2:0]),
.in1(way_wayvld01_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec64_c6;
wire ic_dir_vec64_c6;
wire dir_hit_vec64_c6 ;
wire [1:0] enc_dc_vec64_way_c6;
wire [1:0] enc_ic_vec64_way_c6;
wire [1:0] enc_c_vec64_way_c6;
wire [2:0] way_way_vld64_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec68_c6;
wire ic_dir_vec68_c6;
wire dir_hit_vec68_c6 ;
wire [1:0] enc_dc_vec68_way_c6;
wire [1:0] enc_ic_vec68_way_c6;
wire [1:0] enc_c_vec68_way_c6;
wire [2:0] way_way_vld68_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec72_c6;
wire ic_dir_vec72_c6;
wire dir_hit_vec72_c6 ;
wire [1:0] enc_dc_vec72_way_c6;
wire [1:0] enc_ic_vec72_way_c6;
wire [1:0] enc_c_vec72_way_c6;
wire [2:0] way_way_vld72_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec76_c6;
wire ic_dir_vec76_c6;
wire dir_hit_vec76_c6 ;
wire [1:0] enc_dc_vec76_way_c6;
wire [1:0] enc_ic_vec76_way_c6;
wire [1:0] enc_c_vec76_way_c6;
wire [2:0] way_way_vld76_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec80_c6;
wire ic_dir_vec80_c6;
wire dir_hit_vec80_c6 ;
wire [1:0] enc_dc_vec80_way_c6;
wire [1:0] enc_ic_vec80_way_c6;
wire [1:0] enc_c_vec80_way_c6;
wire [2:0] way_way_vld80_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec84_c6;
wire ic_dir_vec84_c6;
wire dir_hit_vec84_c6 ;
wire [1:0] enc_dc_vec84_way_c6;
wire [1:0] enc_ic_vec84_way_c6;
wire [1:0] enc_c_vec84_way_c6;
wire [2:0] way_way_vld84_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec88_c6;
wire ic_dir_vec88_c6;
wire dir_hit_vec88_c6 ;
wire [1:0] enc_dc_vec88_way_c6;
wire [1:0] enc_ic_vec88_way_c6;
wire [1:0] enc_c_vec88_way_c6;
wire [2:0] way_way_vld88_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec92_c6;
wire ic_dir_vec92_c6;
wire dir_hit_vec92_c6 ;
wire [1:0] enc_dc_vec92_way_c6;
wire [1:0] enc_ic_vec92_way_c6;
wire [1:0] enc_c_vec92_way_c6;
wire [2:0] way_way_vld92_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec64_c6 = ( dc_cam_hit_c6[64] | dc_cam_hit_c6[65] |
dc_cam_hit_c6[66] | dc_cam_hit_c6[67] ) ;
// indicates whether I hit
assign ic_dir_vec64_c6 = ( ic_cam_hit_c6[64] | ic_cam_hit_c6[65] |
ic_cam_hit_c6[66] | ic_cam_hit_c6[67] ) ;
// indicates whether hit
assign dir_hit_vec64_c6 = dc_dir_vec64_c6 | ic_dir_vec64_c6 ;
// D hit way
assign enc_dc_vec64_way_c6[0] = dc_cam_hit_c6[65] | dc_cam_hit_c6[67] ;
assign enc_dc_vec64_way_c6[1] = dc_cam_hit_c6[66] | dc_cam_hit_c6[67] ;
// I hit way
assign enc_ic_vec64_way_c6[0] = ic_cam_hit_c6[65] | ic_cam_hit_c6[67] ;
assign enc_ic_vec64_way_c6[1] = ic_cam_hit_c6[66] | ic_cam_hit_c6[67] ;
mux2ds #(2) mux2_c_vec64_way ( .dout(enc_c_vec64_way_c6[1:0]),
.in0(enc_dc_vec64_way_c6[1:0]),
.in1(enc_ic_vec64_way_c6[1:0]),
.sel0(~ic_dir_vec64_c6),
.sel1(ic_dir_vec64_c6));
assign way_way_vld64_c6[0] = enc_c_vec64_way_c6[0] ;
assign way_way_vld64_c6[1] = enc_c_vec64_way_c6[1] ;
assign way_way_vld64_c6[2] = dir_hit_vec64_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec68_c6 = ( dc_cam_hit_c6[68] | dc_cam_hit_c6[69] |
dc_cam_hit_c6[70] | dc_cam_hit_c6[71] ) ;
// indicates whether I hit
assign ic_dir_vec68_c6 = ( ic_cam_hit_c6[68] | ic_cam_hit_c6[69] |
ic_cam_hit_c6[70] | ic_cam_hit_c6[71] ) ;
// indicates whether hit
assign dir_hit_vec68_c6 = dc_dir_vec68_c6 | ic_dir_vec68_c6 ;
// D hit way
assign enc_dc_vec68_way_c6[0] = dc_cam_hit_c6[69] | dc_cam_hit_c6[71] ;
assign enc_dc_vec68_way_c6[1] = dc_cam_hit_c6[70] | dc_cam_hit_c6[71] ;
// I hit way
assign enc_ic_vec68_way_c6[0] = ic_cam_hit_c6[69] | ic_cam_hit_c6[71] ;
assign enc_ic_vec68_way_c6[1] = ic_cam_hit_c6[70] | ic_cam_hit_c6[71] ;
mux2ds #(2) mux2_c_vec68_way ( .dout(enc_c_vec68_way_c6[1:0]),
.in0(enc_dc_vec68_way_c6[1:0]),
.in1(enc_ic_vec68_way_c6[1:0]),
.sel0(~ic_dir_vec68_c6),
.sel1(ic_dir_vec68_c6));
assign way_way_vld68_c6[0] = enc_c_vec68_way_c6[0] ;
assign way_way_vld68_c6[1] = enc_c_vec68_way_c6[1] ;
assign way_way_vld68_c6[2] = dir_hit_vec68_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec72_c6 = ( dc_cam_hit_c6[72] | dc_cam_hit_c6[73] |
dc_cam_hit_c6[74] | dc_cam_hit_c6[75] ) ;
// indicates whether I hit
assign ic_dir_vec72_c6 = ( ic_cam_hit_c6[72] | ic_cam_hit_c6[73] |
ic_cam_hit_c6[74] | ic_cam_hit_c6[75] ) ;
// indicates whether hit
assign dir_hit_vec72_c6 = dc_dir_vec72_c6 | ic_dir_vec72_c6 ;
// D hit way
assign enc_dc_vec72_way_c6[0] = dc_cam_hit_c6[73] | dc_cam_hit_c6[75] ;
assign enc_dc_vec72_way_c6[1] = dc_cam_hit_c6[74] | dc_cam_hit_c6[75] ;
// I hit way
assign enc_ic_vec72_way_c6[0] = ic_cam_hit_c6[73] | ic_cam_hit_c6[75] ;
assign enc_ic_vec72_way_c6[1] = ic_cam_hit_c6[74] | ic_cam_hit_c6[75] ;
mux2ds #(2) mux2_c_vec72_way ( .dout(enc_c_vec72_way_c6[1:0]),
.in0(enc_dc_vec72_way_c6[1:0]),
.in1(enc_ic_vec72_way_c6[1:0]),
.sel0(~ic_dir_vec72_c6),
.sel1(ic_dir_vec72_c6));
assign way_way_vld72_c6[0] = enc_c_vec72_way_c6[0] ;
assign way_way_vld72_c6[1] = enc_c_vec72_way_c6[1] ;
assign way_way_vld72_c6[2] = dir_hit_vec72_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec76_c6 = ( dc_cam_hit_c6[76] | dc_cam_hit_c6[77] |
dc_cam_hit_c6[78] | dc_cam_hit_c6[79] ) ;
// indicates whether I hit
assign ic_dir_vec76_c6 = ( ic_cam_hit_c6[76] | ic_cam_hit_c6[77] |
ic_cam_hit_c6[78] | ic_cam_hit_c6[79] ) ;
// indicates whether hit
assign dir_hit_vec76_c6 = dc_dir_vec76_c6 | ic_dir_vec76_c6 ;
// D hit way
assign enc_dc_vec76_way_c6[0] = dc_cam_hit_c6[77] | dc_cam_hit_c6[79] ;
assign enc_dc_vec76_way_c6[1] = dc_cam_hit_c6[78] | dc_cam_hit_c6[79] ;
// I hit way
assign enc_ic_vec76_way_c6[0] = ic_cam_hit_c6[77] | ic_cam_hit_c6[79] ;
assign enc_ic_vec76_way_c6[1] = ic_cam_hit_c6[78] | ic_cam_hit_c6[79] ;
mux2ds #(2) mux2_c_vec76_way ( .dout(enc_c_vec76_way_c6[1:0]),
.in0(enc_dc_vec76_way_c6[1:0]),
.in1(enc_ic_vec76_way_c6[1:0]),
.sel0(~ic_dir_vec76_c6),
.sel1(ic_dir_vec76_c6));
assign way_way_vld76_c6[0] = enc_c_vec76_way_c6[0] ;
assign way_way_vld76_c6[1] = enc_c_vec76_way_c6[1] ;
assign way_way_vld76_c6[2] = dir_hit_vec76_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec80_c6 = ( dc_cam_hit_c6[80] | dc_cam_hit_c6[81] |
dc_cam_hit_c6[82] | dc_cam_hit_c6[83] ) ;
// indicates whether I hit
assign ic_dir_vec80_c6 = ( ic_cam_hit_c6[80] | ic_cam_hit_c6[81] |
ic_cam_hit_c6[82] | ic_cam_hit_c6[83] ) ;
// indicates whether hit
assign dir_hit_vec80_c6 = dc_dir_vec80_c6 | ic_dir_vec80_c6 ;
// D hit way
assign enc_dc_vec80_way_c6[0] = dc_cam_hit_c6[81] | dc_cam_hit_c6[83] ;
assign enc_dc_vec80_way_c6[1] = dc_cam_hit_c6[82] | dc_cam_hit_c6[83] ;
// I hit way
assign enc_ic_vec80_way_c6[0] = ic_cam_hit_c6[81] | ic_cam_hit_c6[83] ;
assign enc_ic_vec80_way_c6[1] = ic_cam_hit_c6[82] | ic_cam_hit_c6[83] ;
mux2ds #(2) mux2_c_vec80_way ( .dout(enc_c_vec80_way_c6[1:0]),
.in0(enc_dc_vec80_way_c6[1:0]),
.in1(enc_ic_vec80_way_c6[1:0]),
.sel0(~ic_dir_vec80_c6),
.sel1(ic_dir_vec80_c6));
assign way_way_vld80_c6[0] = enc_c_vec80_way_c6[0] ;
assign way_way_vld80_c6[1] = enc_c_vec80_way_c6[1] ;
assign way_way_vld80_c6[2] = dir_hit_vec80_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec84_c6 = ( dc_cam_hit_c6[84] | dc_cam_hit_c6[85] |
dc_cam_hit_c6[86] | dc_cam_hit_c6[87] ) ;
// indicates whether I hit
assign ic_dir_vec84_c6 = ( ic_cam_hit_c6[84] | ic_cam_hit_c6[85] |
ic_cam_hit_c6[86] | ic_cam_hit_c6[87] ) ;
// indicates whether hit
assign dir_hit_vec84_c6 = dc_dir_vec84_c6 | ic_dir_vec84_c6 ;
// D hit way
assign enc_dc_vec84_way_c6[0] = dc_cam_hit_c6[85] | dc_cam_hit_c6[87] ;
assign enc_dc_vec84_way_c6[1] = dc_cam_hit_c6[86] | dc_cam_hit_c6[87] ;
// I hit way
assign enc_ic_vec84_way_c6[0] = ic_cam_hit_c6[85] | ic_cam_hit_c6[87] ;
assign enc_ic_vec84_way_c6[1] = ic_cam_hit_c6[86] | ic_cam_hit_c6[87] ;
mux2ds #(2) mux2_c_vec84_way ( .dout(enc_c_vec84_way_c6[1:0]),
.in0(enc_dc_vec84_way_c6[1:0]),
.in1(enc_ic_vec84_way_c6[1:0]),
.sel0(~ic_dir_vec84_c6),
.sel1(ic_dir_vec84_c6));
assign way_way_vld84_c6[0] = enc_c_vec84_way_c6[0] ;
assign way_way_vld84_c6[1] = enc_c_vec84_way_c6[1] ;
assign way_way_vld84_c6[2] = dir_hit_vec84_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec88_c6 = ( dc_cam_hit_c6[88] | dc_cam_hit_c6[89] |
dc_cam_hit_c6[90] | dc_cam_hit_c6[91] ) ;
// indicates whether I hit
assign ic_dir_vec88_c6 = ( ic_cam_hit_c6[88] | ic_cam_hit_c6[89] |
ic_cam_hit_c6[90] | ic_cam_hit_c6[91] ) ;
// indicates whether hit
assign dir_hit_vec88_c6 = dc_dir_vec88_c6 | ic_dir_vec88_c6 ;
// D hit way
assign enc_dc_vec88_way_c6[0] = dc_cam_hit_c6[89] | dc_cam_hit_c6[91] ;
assign enc_dc_vec88_way_c6[1] = dc_cam_hit_c6[90] | dc_cam_hit_c6[91] ;
// I hit way
assign enc_ic_vec88_way_c6[0] = ic_cam_hit_c6[89] | ic_cam_hit_c6[91] ;
assign enc_ic_vec88_way_c6[1] = ic_cam_hit_c6[90] | ic_cam_hit_c6[91] ;
mux2ds #(2) mux2_c_vec88_way ( .dout(enc_c_vec88_way_c6[1:0]),
.in0(enc_dc_vec88_way_c6[1:0]),
.in1(enc_ic_vec88_way_c6[1:0]),
.sel0(~ic_dir_vec88_c6),
.sel1(ic_dir_vec88_c6));
assign way_way_vld88_c6[0] = enc_c_vec88_way_c6[0] ;
assign way_way_vld88_c6[1] = enc_c_vec88_way_c6[1] ;
assign way_way_vld88_c6[2] = dir_hit_vec88_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec92_c6 = ( dc_cam_hit_c6[92] | dc_cam_hit_c6[93] |
dc_cam_hit_c6[94] | dc_cam_hit_c6[95] ) ;
// indicates whether I hit
assign ic_dir_vec92_c6 = ( ic_cam_hit_c6[92] | ic_cam_hit_c6[93] |
ic_cam_hit_c6[94] | ic_cam_hit_c6[95] ) ;
// indicates whether hit
assign dir_hit_vec92_c6 = dc_dir_vec92_c6 | ic_dir_vec92_c6 ;
// D hit way
assign enc_dc_vec92_way_c6[0] = dc_cam_hit_c6[93] | dc_cam_hit_c6[95] ;
assign enc_dc_vec92_way_c6[1] = dc_cam_hit_c6[94] | dc_cam_hit_c6[95] ;
// I hit way
assign enc_ic_vec92_way_c6[0] = ic_cam_hit_c6[93] | ic_cam_hit_c6[95] ;
assign enc_ic_vec92_way_c6[1] = ic_cam_hit_c6[94] | ic_cam_hit_c6[95] ;
mux2ds #(2) mux2_c_vec92_way ( .dout(enc_c_vec92_way_c6[1:0]),
.in0(enc_dc_vec92_way_c6[1:0]),
.in1(enc_ic_vec92_way_c6[1:0]),
.sel0(~ic_dir_vec92_c6),
.sel1(ic_dir_vec92_c6));
assign way_way_vld92_c6[0] = enc_c_vec92_way_c6[0] ;
assign way_way_vld92_c6[1] = enc_c_vec92_way_c6[1] ;
assign way_way_vld92_c6[2] = dir_hit_vec92_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld10_mux1_c6;
wire [2:0] way_wayvld10_mux2_c6;
wire [2:0] way_wayvld10_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux1_c6[2:0]),
.in0(way_way_vld64_c6[2:0]),
.in1(way_way_vld68_c6[2:0]),
.in2(way_way_vld72_c6[2:0]),
.in3(way_way_vld76_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux2_c6[2:0]),
.in0(way_way_vld80_c6[2:0]),
.in1(way_way_vld84_c6[2:0]),
.in2(way_way_vld88_c6[2:0]),
.in3(way_way_vld92_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux3_c6[2:0]),
.in0(way_wayvld10_mux1_c6[2:0]),
.in1(way_wayvld10_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec96_c6;
wire dir_hit_vec96_c6 ;
wire [1:0] enc_dc_vec96_way_c6;
wire [1:0] enc_c_vec96_way_c6;
wire [2:0] way_way_vld96_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec100_c6;
wire dir_hit_vec100_c6 ;
wire [1:0] enc_dc_vec100_way_c6;
wire [1:0] enc_c_vec100_way_c6;
wire [2:0] way_way_vld100_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec104_c6;
wire dir_hit_vec104_c6 ;
wire [1:0] enc_dc_vec104_way_c6;
wire [1:0] enc_c_vec104_way_c6;
wire [2:0] way_way_vld104_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec108_c6;
wire dir_hit_vec108_c6 ;
wire [1:0] enc_dc_vec108_way_c6;
wire [1:0] enc_c_vec108_way_c6;
wire [2:0] way_way_vld108_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec112_c6;
wire dir_hit_vec112_c6 ;
wire [1:0] enc_dc_vec112_way_c6;
wire [1:0] enc_c_vec112_way_c6;
wire [2:0] way_way_vld112_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec116_c6;
wire dir_hit_vec116_c6 ;
wire [1:0] enc_dc_vec116_way_c6;
wire [1:0] enc_c_vec116_way_c6;
wire [2:0] way_way_vld116_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec120_c6;
wire dir_hit_vec120_c6 ;
wire [1:0] enc_dc_vec120_way_c6;
wire [1:0] enc_c_vec120_way_c6;
wire [2:0] way_way_vld120_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec124_c6;
wire dir_hit_vec124_c6 ;
wire [1:0] enc_dc_vec124_way_c6;
wire [1:0] enc_c_vec124_way_c6;
wire [2:0] way_way_vld124_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec96_c6 = ( dc_cam_hit_c6[96] | dc_cam_hit_c6[97] |
dc_cam_hit_c6[98] | dc_cam_hit_c6[99] ) ;
// D hit way
assign dir_hit_vec96_c6 = dc_dir_vec96_c6 ;
// hit way
assign enc_dc_vec96_way_c6[0] = dc_cam_hit_c6[97] | dc_cam_hit_c6[99] ;
assign enc_dc_vec96_way_c6[1] = dc_cam_hit_c6[98] | dc_cam_hit_c6[99] ;
assign enc_c_vec96_way_c6[1:0] = enc_dc_vec96_way_c6[1:0] ;
assign way_way_vld96_c6[0] = enc_c_vec96_way_c6[0] ;
assign way_way_vld96_c6[1] = enc_c_vec96_way_c6[1] ;
assign way_way_vld96_c6[2] = dir_hit_vec96_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec100_c6 = ( dc_cam_hit_c6[100] | dc_cam_hit_c6[101] |
dc_cam_hit_c6[102] | dc_cam_hit_c6[103] ) ;
// D hit way
assign dir_hit_vec100_c6 = dc_dir_vec100_c6 ;
// hit way
assign enc_dc_vec100_way_c6[0] = dc_cam_hit_c6[101] | dc_cam_hit_c6[103] ;
assign enc_dc_vec100_way_c6[1] = dc_cam_hit_c6[102] | dc_cam_hit_c6[103] ;
assign enc_c_vec100_way_c6[1:0] = enc_dc_vec100_way_c6[1:0] ;
assign way_way_vld100_c6[0] = enc_c_vec100_way_c6[0] ;
assign way_way_vld100_c6[1] = enc_c_vec100_way_c6[1] ;
assign way_way_vld100_c6[2] = dir_hit_vec100_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec104_c6 = ( dc_cam_hit_c6[104] | dc_cam_hit_c6[105] |
dc_cam_hit_c6[106] | dc_cam_hit_c6[107] ) ;
// D hit way
assign dir_hit_vec104_c6 = dc_dir_vec104_c6 ;
// hit way
assign enc_dc_vec104_way_c6[0] = dc_cam_hit_c6[105] | dc_cam_hit_c6[107] ;
assign enc_dc_vec104_way_c6[1] = dc_cam_hit_c6[106] | dc_cam_hit_c6[107] ;
assign enc_c_vec104_way_c6[1:0] = enc_dc_vec104_way_c6[1:0] ;
assign way_way_vld104_c6[0] = enc_c_vec104_way_c6[0] ;
assign way_way_vld104_c6[1] = enc_c_vec104_way_c6[1] ;
assign way_way_vld104_c6[2] = dir_hit_vec104_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec108_c6 = ( dc_cam_hit_c6[108] | dc_cam_hit_c6[109] |
dc_cam_hit_c6[110] | dc_cam_hit_c6[111] ) ;
// D hit way
assign dir_hit_vec108_c6 = dc_dir_vec108_c6 ;
// hit way
assign enc_dc_vec108_way_c6[0] = dc_cam_hit_c6[109] | dc_cam_hit_c6[111] ;
assign enc_dc_vec108_way_c6[1] = dc_cam_hit_c6[110] | dc_cam_hit_c6[111] ;
assign enc_c_vec108_way_c6[1:0] = enc_dc_vec108_way_c6[1:0] ;
assign way_way_vld108_c6[0] = enc_c_vec108_way_c6[0] ;
assign way_way_vld108_c6[1] = enc_c_vec108_way_c6[1] ;
assign way_way_vld108_c6[2] = dir_hit_vec108_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec112_c6 = ( dc_cam_hit_c6[112] | dc_cam_hit_c6[113] |
dc_cam_hit_c6[114] | dc_cam_hit_c6[115] ) ;
// D hit way
assign dir_hit_vec112_c6 = dc_dir_vec112_c6 ;
// hit way
assign enc_dc_vec112_way_c6[0] = dc_cam_hit_c6[113] | dc_cam_hit_c6[115] ;
assign enc_dc_vec112_way_c6[1] = dc_cam_hit_c6[114] | dc_cam_hit_c6[115] ;
assign enc_c_vec112_way_c6[1:0] = enc_dc_vec112_way_c6[1:0] ;
assign way_way_vld112_c6[0] = enc_c_vec112_way_c6[0] ;
assign way_way_vld112_c6[1] = enc_c_vec112_way_c6[1] ;
assign way_way_vld112_c6[2] = dir_hit_vec112_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec116_c6 = ( dc_cam_hit_c6[116] | dc_cam_hit_c6[117] |
dc_cam_hit_c6[118] | dc_cam_hit_c6[119] ) ;
// D hit way
assign dir_hit_vec116_c6 = dc_dir_vec116_c6 ;
// hit way
assign enc_dc_vec116_way_c6[0] = dc_cam_hit_c6[117] | dc_cam_hit_c6[119] ;
assign enc_dc_vec116_way_c6[1] = dc_cam_hit_c6[118] | dc_cam_hit_c6[119] ;
assign enc_c_vec116_way_c6[1:0] = enc_dc_vec116_way_c6[1:0] ;
assign way_way_vld116_c6[0] = enc_c_vec116_way_c6[0] ;
assign way_way_vld116_c6[1] = enc_c_vec116_way_c6[1] ;
assign way_way_vld116_c6[2] = dir_hit_vec116_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec120_c6 = ( dc_cam_hit_c6[120] | dc_cam_hit_c6[121] |
dc_cam_hit_c6[122] | dc_cam_hit_c6[123] ) ;
// D hit way
assign dir_hit_vec120_c6 = dc_dir_vec120_c6 ;
// hit way
assign enc_dc_vec120_way_c6[0] = dc_cam_hit_c6[121] | dc_cam_hit_c6[123] ;
assign enc_dc_vec120_way_c6[1] = dc_cam_hit_c6[122] | dc_cam_hit_c6[123] ;
assign enc_c_vec120_way_c6[1:0] = enc_dc_vec120_way_c6[1:0] ;
assign way_way_vld120_c6[0] = enc_c_vec120_way_c6[0] ;
assign way_way_vld120_c6[1] = enc_c_vec120_way_c6[1] ;
assign way_way_vld120_c6[2] = dir_hit_vec120_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec124_c6 = ( dc_cam_hit_c6[124] | dc_cam_hit_c6[125] |
dc_cam_hit_c6[126] | dc_cam_hit_c6[127] ) ;
// D hit way
assign dir_hit_vec124_c6 = dc_dir_vec124_c6 ;
// hit way
assign enc_dc_vec124_way_c6[0] = dc_cam_hit_c6[125] | dc_cam_hit_c6[127] ;
assign enc_dc_vec124_way_c6[1] = dc_cam_hit_c6[126] | dc_cam_hit_c6[127] ;
assign enc_c_vec124_way_c6[1:0] = enc_dc_vec124_way_c6[1:0] ;
assign way_way_vld124_c6[0] = enc_c_vec124_way_c6[0] ;
assign way_way_vld124_c6[1] = enc_c_vec124_way_c6[1] ;
assign way_way_vld124_c6[2] = dir_hit_vec124_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld11_mux1_c6;
wire [2:0] way_wayvld11_mux2_c6;
wire [2:0] way_wayvld11_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux1_c6[2:0]),
.in0(way_way_vld96_c6[2:0]),
.in1(way_way_vld100_c6[2:0]),
.in2(way_way_vld104_c6[2:0]),
.in3(way_way_vld108_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux2_c6[2:0]),
.in0(way_way_vld112_c6[2:0]),
.in1(way_way_vld116_c6[2:0]),
.in2(way_way_vld120_c6[2:0]),
.in3(way_way_vld124_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux3_c6[2:0]),
.in0(way_wayvld11_mux1_c6[2:0]),
.in1(way_wayvld11_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
//*******************************************************************************************
// REQUEST VEC FORMATION
//*******************************************************************************************
assign dirdp_req_vec_c6[0] = dir_hit_vec0_c6 | dir_hit_vec32_c6 | dir_hit_vec64_c6 | dir_hit_vec96_c6 ;
assign dirdp_req_vec_c6[1] = dir_hit_vec4_c6 | dir_hit_vec36_c6 | dir_hit_vec68_c6 | dir_hit_vec100_c6 ;
assign dirdp_req_vec_c6[2] = dir_hit_vec8_c6 | dir_hit_vec40_c6 | dir_hit_vec72_c6 | dir_hit_vec104_c6 ;
assign dirdp_req_vec_c6[3] = dir_hit_vec12_c6 | dir_hit_vec44_c6 | dir_hit_vec76_c6 | dir_hit_vec108_c6 ;
assign dirdp_req_vec_c6[4] = dir_hit_vec16_c6 | dir_hit_vec48_c6 | dir_hit_vec80_c6 | dir_hit_vec112_c6 ;
assign dirdp_req_vec_c6[5] = dir_hit_vec20_c6 | dir_hit_vec52_c6 | dir_hit_vec84_c6 | dir_hit_vec116_c6 ;
assign dirdp_req_vec_c6[6] = dir_hit_vec24_c6 | dir_hit_vec56_c6 | dir_hit_vec88_c6 | dir_hit_vec120_c6 ;
assign dirdp_req_vec_c6[7] = dir_hit_vec28_c6 | dir_hit_vec60_c6 | dir_hit_vec92_c6 | dir_hit_vec124_c6 ;
//*******************************************************************************************
// INVALIDATE PACKET FORMATION
//*******************************************************************************************
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[31:0] = { enc_c_vec28_way_c6, ic_dir_vec28_c6, dc_dir_vec28_c6,
enc_c_vec24_way_c6, ic_dir_vec24_c6, dc_dir_vec24_c6,
enc_c_vec20_way_c6, ic_dir_vec20_c6, dc_dir_vec20_c6,
enc_c_vec16_way_c6, ic_dir_vec16_c6, dc_dir_vec16_c6,
enc_c_vec12_way_c6, ic_dir_vec12_c6, dc_dir_vec12_c6,
enc_c_vec8_way_c6, ic_dir_vec8_c6, dc_dir_vec8_c6,
enc_c_vec4_way_c6, ic_dir_vec4_c6, dc_dir_vec4_c6,
enc_c_vec0_way_c6, ic_dir_vec0_c6, dc_dir_vec0_c6
} ;
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[55:32] = { enc_c_vec60_way_c6, dc_dir_vec60_c6,
enc_c_vec56_way_c6, dc_dir_vec56_c6,
enc_c_vec52_way_c6, dc_dir_vec52_c6,
enc_c_vec48_way_c6, dc_dir_vec48_c6,
enc_c_vec44_way_c6, dc_dir_vec44_c6,
enc_c_vec40_way_c6, dc_dir_vec40_c6,
enc_c_vec36_way_c6, dc_dir_vec36_c6,
enc_c_vec32_way_c6, dc_dir_vec32_c6
} ;
assign dirdp_inval_pckt_c6[87:56] = { enc_c_vec92_way_c6, ic_dir_vec92_c6, dc_dir_vec92_c6,
enc_c_vec88_way_c6, ic_dir_vec88_c6, dc_dir_vec88_c6,
enc_c_vec84_way_c6, ic_dir_vec84_c6, dc_dir_vec84_c6,
enc_c_vec80_way_c6, ic_dir_vec80_c6, dc_dir_vec80_c6,
enc_c_vec76_way_c6, ic_dir_vec76_c6, dc_dir_vec76_c6,
enc_c_vec72_way_c6, ic_dir_vec72_c6, dc_dir_vec72_c6,
enc_c_vec68_way_c6, ic_dir_vec68_c6, dc_dir_vec68_c6,
enc_c_vec64_way_c6, ic_dir_vec64_c6, dc_dir_vec64_c6
} ;
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[111:88] = { enc_c_vec124_way_c6, dc_dir_vec124_c6,
enc_c_vec120_way_c6, dc_dir_vec120_c6,
enc_c_vec116_way_c6, dc_dir_vec116_c6,
enc_c_vec112_way_c6, dc_dir_vec112_c6,
enc_c_vec108_way_c6, dc_dir_vec108_c6,
enc_c_vec104_way_c6, dc_dir_vec104_c6,
enc_c_vec100_way_c6, dc_dir_vec100_c6,
enc_c_vec96_way_c6, dc_dir_vec96_c6
} ;
//*******************************************************************************************
// GENERATION OR WAY AND WAYVLD FOR THE CPX RETURN
//*******************************************************************************************
mux4ds #(3) mux_way_waywayvld_c6 ( .dout(dirvecdp_way_info_c6[2:0]),
.in0(way_wayvld00_mux3_c6[2:0]),
.in1(way_wayvld01_mux3_c6[2:0]),
.in2(way_wayvld10_mux3_c6[2:0]),
.in3(way_wayvld11_mux3_c6[2:0]),
.sel0(mux_vec_sel_c6[0]),
.sel1(mux_vec_sel_c6[1]),
.sel2(mux_vec_sel_c6[2]),
.sel3(mux_vec_sel_c6[3]));
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:49:07 03/26/2015
// Design Name: lifo_top
// Module Name: D:/Modelsim Projects/Xilinx/assignment5/lifo_top_tb.v
// Project Name: assignment5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: lifo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module lifo_top_tb;
// Inputs
reg [5:0] vector_in;
reg reset;
reg clk;
// Outputs
wire [3:0] data_out;
wire empty_flag;
wire full_flag;
//Instantiate the Unit Under Test (UUT)
lifo_top lifo (
.data_out(data_out),
.empty_flag(empty_flag),
.full_flag(full_flag),
.vector_in(vector_in),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
// vector_in = 0;
reset = 1;
clk = 1;
// Wait 100 ns for global reset to finish
// #100;
// Add stimulus here
// 4 writes
#2 reset = 0; vector_in = 6'b10_1111;
#2 vector_in = 6'b10_1110;
#2 vector_in = 6'b10_1101;
#2 vector_in = 6'b10_1001;
#2 vector_in = 6'b00_1001;
// 4 reads
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b00_1001;
// 4 writes
#2 vector_in = 6'b10_0000;
#2 vector_in = 6'b10_0001;
#2 vector_in = 6'b10_0111;
#2 vector_in = 6'b10_0110;
#2 vector_in = 6'b00_1001;
// 4 more writes
#2 vector_in = 6'b10_0000;
#2 vector_in = 6'b10_0001;
#2 vector_in = 6'b10_0111;
#2 vector_in = 6'b10_0110;
#2 vector_in = 6'b00_1001;
// 2 Reads
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b01_1001;
#2 vector_in = 6'b00_1001;
// 2 writes
#2 vector_in = 6'b10_1101;
#2 vector_in = 6'b10_1001;
#2 vector_in = 6'b00_1000;
#2 $finish;
end
always
#1 clk = ~clk;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_pr/sky130_fd_sc_hdll__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_hdll__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hdll__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/11 16:03:48
// Design Name:
// Module Name: lab4_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab4_1(
input CP,M,D,C,B,A,LD,CLR,
output reg Qd,Qc,Qb,Qa,Qcc
);
reg [3:0] count;
always @(posedge CP or negedge CLR or negedge LD)
begin
if(CLR == 0)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(LD == 0)
begin
count = {D,C,B,A};
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
else if(M == 1)
begin
if(count ==15)
begin
count = 0;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count = count + 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
else
begin
if(count == 0)
begin
count = 15;
{Qd,Qc,Qb,Qa} = count;
Qcc = 0;
end
else
begin
count =count - 1;
{Qd,Qc,Qb,Qa} = count;
Qcc = 1;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2A_BEHAVIORAL_V
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2014, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: [1] THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and [2] Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications)). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
//
// Version 1.1 - 4th March 2010.
// Derived from kcpsm6.vhd Version 1.1 (9th February 2011) by Nick Sawyer.
// Version 1.2 - 4th October 2012.
// Addition of WebTalk information.
// Version 1.3 - 21st May 2014.
// Disassembly of 'STAR sX, kk' instruction added to the simulation
// code. No changes to functionality or the physical implementation.
//
// Ken Chapman
// Xilinx Ltd
// Benchmark House
// 203 Brooklands Road
// Weybridge
// Surrey KT13 ORH
// United Kingdom
//
// [email protected]
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Format of this file.
//
// The module defines the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the implementation.
// The Unisim Library is used to define Xilinx primitives. It is also used during
// simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
//
///////////////////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Main Entity for kcpsm6 with WebTalk Attributes
//
(* CORE_GENERATION_INFO = "kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}" *)
module kcpsm6 (address, instruction, bram_enable, in_port, out_port, port_id, write_strobe, k_write_strobe, read_strobe, interrupt, interrupt_ack, sleep, reset, clk) ;
parameter [7:0] hwbuild = 8'h00 ;
parameter [11:0] interrupt_vector = 12'h3FF ;
parameter integer scratch_pad_memory_size = 64 ;
output [11:0] address ;
input [17:0] instruction ;
output bram_enable ;
input [7:0] in_port ;
output [7:0] out_port ;
output [7:0] port_id ;
output write_strobe ;
output k_write_strobe ;
output read_strobe ;
input interrupt ;
output interrupt_ack ;
input sleep ;
input reset ;
input clk ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Start of Main Architecture for kcpsm6
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Signals used in kcpsm6
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// State Machine and Interrupt
//
wire [2:1] t_state_value ;
wire [2:1] t_state ;
wire run_value ;
wire run ;
wire internal_reset_value ;
wire internal_reset ;
wire sync_sleep ;
wire int_enable_type ;
wire interrupt_enable_value ;
wire interrupt_enable ;
wire sync_interrupt ;
wire active_interrupt_value ;
wire active_interrupt ;
//
// Arithmetic and Logical Functions
//
wire [2:0] arith_logical_sel ;
wire arith_carry_in ;
wire arith_carry_value ;
wire arith_carry ;
wire [7:0] half_arith_logical ;
wire [7:0] logical_carry_mask ;
wire [7:0] carry_arith_logical ;
wire [7:0] arith_logical_value ;
wire [7:0] arith_logical_result ;
//
// Shift and Rotate Functions
//
wire [7:0] shift_rotate_value ;
wire [7:0] shift_rotate_result ;
wire shift_in_bit ;
//
// ALU structure
//
wire [7:0] alu_result ;
wire [1:0] alu_mux_sel_value ;
wire [1:0] alu_mux_sel ;
//
// Strobes
//
wire strobe_type ;
wire write_strobe_value ;
wire k_write_strobe_value ;
wire read_strobe_value ;
//
// Flags
//
wire flag_enable_type ;
wire flag_enable_value ;
wire flag_enable ;
wire lower_parity ;
wire lower_parity_sel ;
wire carry_lower_parity ;
wire upper_parity ;
wire parity ;
wire shift_carry_value ;
wire shift_carry ;
wire carry_flag_value ;
wire carry_flag ;
wire use_zero_flag_value ;
wire use_zero_flag ;
wire drive_carry_in_zero ;
wire carry_in_zero ;
wire lower_zero ;
wire lower_zero_sel ;
wire carry_lower_zero ;
wire middle_zero ;
wire middle_zero_sel ;
wire carry_middle_zero ;
wire upper_zero_sel ;
wire zero_flag_value ;
wire zero_flag ;
//
// Scratch Pad Memory
//
wire spm_enable_value ;
wire spm_enable ;
wire [7:0] spm_ram_data ;
wire [7:0] spm_data ;
//
// Registers
//
wire regbank_type ;
wire bank_value ;
wire bank ;
wire loadstar_type ;
wire sx_addr4_value ;
wire register_enable_type ;
wire register_enable_value ;
wire register_enable ;
wire [4:0] sx_addr ;
wire [4:0] sy_addr ;
wire [7:0] sx ;
wire [7:0] sy ;
//
// Second Operand
//
wire [7:0] sy_or_kk ;
//
// Program Counter
//
wire pc_move_is_valid ;
wire move_type ;
wire returni_type ;
wire [2:0] pc_mode ;
wire [11:0] register_vector ;
wire [11:0] half_pc ;
wire [10:0] carry_pc ;
wire [11:0] pc_value ;
wire [11:0] pc ;
wire [11:0] pc_vector ;
//
// Program Counter Stack
//
wire push_stack ;
wire pop_stack ;
wire [11:0] stack_memory ;
wire [11:0] return_vector ;
wire stack_carry_flag ;
wire shadow_carry_flag ;
wire stack_zero_flag ;
wire shadow_zero_value ;
wire shadow_zero_flag ;
wire stack_bank ;
wire shadow_bank ;
wire stack_bit ;
wire special_bit ;
wire [4:0] half_pointer_value ;
wire [4:0] feed_pointer_value ;
wire [4:0] stack_pointer_carry ;
wire [4:0] stack_pointer_value ;
wire [4:0] stack_pointer ;
//
//
//
//**********************************************************************************
//
// Signals between these *** lines are only made visible during simulation
//
//synthesis translate_off
//
reg [1:152] kcpsm6_opcode ;
reg [1:128] kcpsm6_status ;
reg [7:0] sim_s0 ;
reg [7:0] sim_s1 ;
reg [7:0] sim_s2 ;
reg [7:0] sim_s3 ;
reg [7:0] sim_s4 ;
reg [7:0] sim_s5 ;
reg [7:0] sim_s6 ;
reg [7:0] sim_s7 ;
reg [7:0] sim_s8 ;
reg [7:0] sim_s9 ;
reg [7:0] sim_sA ;
reg [7:0] sim_sB ;
reg [7:0] sim_sC ;
reg [7:0] sim_sD ;
reg [7:0] sim_sE ;
reg [7:0] sim_sF ;
reg [7:0] sim_spm00 ;
reg [7:0] sim_spm01 ;
reg [7:0] sim_spm02 ;
reg [7:0] sim_spm03 ;
reg [7:0] sim_spm04 ;
reg [7:0] sim_spm05 ;
reg [7:0] sim_spm06 ;
reg [7:0] sim_spm07 ;
reg [7:0] sim_spm08 ;
reg [7:0] sim_spm09 ;
reg [7:0] sim_spm0A ;
reg [7:0] sim_spm0B ;
reg [7:0] sim_spm0C ;
reg [7:0] sim_spm0D ;
reg [7:0] sim_spm0E ;
reg [7:0] sim_spm0F ;
reg [7:0] sim_spm10 ;
reg [7:0] sim_spm11 ;
reg [7:0] sim_spm12 ;
reg [7:0] sim_spm13 ;
reg [7:0] sim_spm14 ;
reg [7:0] sim_spm15 ;
reg [7:0] sim_spm16 ;
reg [7:0] sim_spm17 ;
reg [7:0] sim_spm18 ;
reg [7:0] sim_spm19 ;
reg [7:0] sim_spm1A ;
reg [7:0] sim_spm1B ;
reg [7:0] sim_spm1C ;
reg [7:0] sim_spm1D ;
reg [7:0] sim_spm1E ;
reg [7:0] sim_spm1F ;
reg [7:0] sim_spm20 ;
reg [7:0] sim_spm21 ;
reg [7:0] sim_spm22 ;
reg [7:0] sim_spm23 ;
reg [7:0] sim_spm24 ;
reg [7:0] sim_spm25 ;
reg [7:0] sim_spm26 ;
reg [7:0] sim_spm27 ;
reg [7:0] sim_spm28 ;
reg [7:0] sim_spm29 ;
reg [7:0] sim_spm2A ;
reg [7:0] sim_spm2B ;
reg [7:0] sim_spm2C ;
reg [7:0] sim_spm2D ;
reg [7:0] sim_spm2E ;
reg [7:0] sim_spm2F ;
reg [7:0] sim_spm30 ;
reg [7:0] sim_spm31 ;
reg [7:0] sim_spm32 ;
reg [7:0] sim_spm33 ;
reg [7:0] sim_spm34 ;
reg [7:0] sim_spm35 ;
reg [7:0] sim_spm36 ;
reg [7:0] sim_spm37 ;
reg [7:0] sim_spm38 ;
reg [7:0] sim_spm39 ;
reg [7:0] sim_spm3A ;
reg [7:0] sim_spm3B ;
reg [7:0] sim_spm3C ;
reg [7:0] sim_spm3D ;
reg [7:0] sim_spm3E ;
reg [7:0] sim_spm3F ;
reg [7:0] sim_spm40 ;
reg [7:0] sim_spm41 ;
reg [7:0] sim_spm42 ;
reg [7:0] sim_spm43 ;
reg [7:0] sim_spm44 ;
reg [7:0] sim_spm45 ;
reg [7:0] sim_spm46 ;
reg [7:0] sim_spm47 ;
reg [7:0] sim_spm48 ;
reg [7:0] sim_spm49 ;
reg [7:0] sim_spm4A ;
reg [7:0] sim_spm4B ;
reg [7:0] sim_spm4C ;
reg [7:0] sim_spm4D ;
reg [7:0] sim_spm4E ;
reg [7:0] sim_spm4F ;
reg [7:0] sim_spm50 ;
reg [7:0] sim_spm51 ;
reg [7:0] sim_spm52 ;
reg [7:0] sim_spm53 ;
reg [7:0] sim_spm54 ;
reg [7:0] sim_spm55 ;
reg [7:0] sim_spm56 ;
reg [7:0] sim_spm57 ;
reg [7:0] sim_spm58 ;
reg [7:0] sim_spm59 ;
reg [7:0] sim_spm5A ;
reg [7:0] sim_spm5B ;
reg [7:0] sim_spm5C ;
reg [7:0] sim_spm5D ;
reg [7:0] sim_spm5E ;
reg [7:0] sim_spm5F ;
reg [7:0] sim_spm60 ;
reg [7:0] sim_spm61 ;
reg [7:0] sim_spm62 ;
reg [7:0] sim_spm63 ;
reg [7:0] sim_spm64 ;
reg [7:0] sim_spm65 ;
reg [7:0] sim_spm66 ;
reg [7:0] sim_spm67 ;
reg [7:0] sim_spm68 ;
reg [7:0] sim_spm69 ;
reg [7:0] sim_spm6A ;
reg [7:0] sim_spm6B ;
reg [7:0] sim_spm6C ;
reg [7:0] sim_spm6D ;
reg [7:0] sim_spm6E ;
reg [7:0] sim_spm6F ;
reg [7:0] sim_spm70 ;
reg [7:0] sim_spm71 ;
reg [7:0] sim_spm72 ;
reg [7:0] sim_spm73 ;
reg [7:0] sim_spm74 ;
reg [7:0] sim_spm75 ;
reg [7:0] sim_spm76 ;
reg [7:0] sim_spm77 ;
reg [7:0] sim_spm78 ;
reg [7:0] sim_spm79 ;
reg [7:0] sim_spm7A ;
reg [7:0] sim_spm7B ;
reg [7:0] sim_spm7C ;
reg [7:0] sim_spm7D ;
reg [7:0] sim_spm7E ;
reg [7:0] sim_spm7F ;
reg [7:0] sim_spm80 ;
reg [7:0] sim_spm81 ;
reg [7:0] sim_spm82 ;
reg [7:0] sim_spm83 ;
reg [7:0] sim_spm84 ;
reg [7:0] sim_spm85 ;
reg [7:0] sim_spm86 ;
reg [7:0] sim_spm87 ;
reg [7:0] sim_spm88 ;
reg [7:0] sim_spm89 ;
reg [7:0] sim_spm8A ;
reg [7:0] sim_spm8B ;
reg [7:0] sim_spm8C ;
reg [7:0] sim_spm8D ;
reg [7:0] sim_spm8E ;
reg [7:0] sim_spm8F ;
reg [7:0] sim_spm90 ;
reg [7:0] sim_spm91 ;
reg [7:0] sim_spm92 ;
reg [7:0] sim_spm93 ;
reg [7:0] sim_spm94 ;
reg [7:0] sim_spm95 ;
reg [7:0] sim_spm96 ;
reg [7:0] sim_spm97 ;
reg [7:0] sim_spm98 ;
reg [7:0] sim_spm99 ;
reg [7:0] sim_spm9A ;
reg [7:0] sim_spm9B ;
reg [7:0] sim_spm9C ;
reg [7:0] sim_spm9D ;
reg [7:0] sim_spm9E ;
reg [7:0] sim_spm9F ;
reg [7:0] sim_spmA0 ;
reg [7:0] sim_spmA1 ;
reg [7:0] sim_spmA2 ;
reg [7:0] sim_spmA3 ;
reg [7:0] sim_spmA4 ;
reg [7:0] sim_spmA5 ;
reg [7:0] sim_spmA6 ;
reg [7:0] sim_spmA7 ;
reg [7:0] sim_spmA8 ;
reg [7:0] sim_spmA9 ;
reg [7:0] sim_spmAA ;
reg [7:0] sim_spmAB ;
reg [7:0] sim_spmAC ;
reg [7:0] sim_spmAD ;
reg [7:0] sim_spmAE ;
reg [7:0] sim_spmAF ;
reg [7:0] sim_spmB0 ;
reg [7:0] sim_spmB1 ;
reg [7:0] sim_spmB2 ;
reg [7:0] sim_spmB3 ;
reg [7:0] sim_spmB4 ;
reg [7:0] sim_spmB5 ;
reg [7:0] sim_spmB6 ;
reg [7:0] sim_spmB7 ;
reg [7:0] sim_spmB8 ;
reg [7:0] sim_spmB9 ;
reg [7:0] sim_spmBA ;
reg [7:0] sim_spmBB ;
reg [7:0] sim_spmBC ;
reg [7:0] sim_spmBD ;
reg [7:0] sim_spmBE ;
reg [7:0] sim_spmBF ;
reg [7:0] sim_spmC0 ;
reg [7:0] sim_spmC1 ;
reg [7:0] sim_spmC2 ;
reg [7:0] sim_spmC3 ;
reg [7:0] sim_spmC4 ;
reg [7:0] sim_spmC5 ;
reg [7:0] sim_spmC6 ;
reg [7:0] sim_spmC7 ;
reg [7:0] sim_spmC8 ;
reg [7:0] sim_spmC9 ;
reg [7:0] sim_spmCA ;
reg [7:0] sim_spmCB ;
reg [7:0] sim_spmCC ;
reg [7:0] sim_spmCD ;
reg [7:0] sim_spmCE ;
reg [7:0] sim_spmCF ;
reg [7:0] sim_spmD0 ;
reg [7:0] sim_spmD1 ;
reg [7:0] sim_spmD2 ;
reg [7:0] sim_spmD3 ;
reg [7:0] sim_spmD4 ;
reg [7:0] sim_spmD5 ;
reg [7:0] sim_spmD6 ;
reg [7:0] sim_spmD7 ;
reg [7:0] sim_spmD8 ;
reg [7:0] sim_spmD9 ;
reg [7:0] sim_spmDA ;
reg [7:0] sim_spmDB ;
reg [7:0] sim_spmDC ;
reg [7:0] sim_spmDD ;
reg [7:0] sim_spmDE ;
reg [7:0] sim_spmDF ;
reg [7:0] sim_spmE0 ;
reg [7:0] sim_spmE1 ;
reg [7:0] sim_spmE2 ;
reg [7:0] sim_spmE3 ;
reg [7:0] sim_spmE4 ;
reg [7:0] sim_spmE5 ;
reg [7:0] sim_spmE6 ;
reg [7:0] sim_spmE7 ;
reg [7:0] sim_spmE8 ;
reg [7:0] sim_spmE9 ;
reg [7:0] sim_spmEA ;
reg [7:0] sim_spmEB ;
reg [7:0] sim_spmEC ;
reg [7:0] sim_spmED ;
reg [7:0] sim_spmEE ;
reg [7:0] sim_spmEF ;
reg [7:0] sim_spmF0 ;
reg [7:0] sim_spmF1 ;
reg [7:0] sim_spmF2 ;
reg [7:0] sim_spmF3 ;
reg [7:0] sim_spmF4 ;
reg [7:0] sim_spmF5 ;
reg [7:0] sim_spmF6 ;
reg [7:0] sim_spmF7 ;
reg [7:0] sim_spmF8 ;
reg [7:0] sim_spmF9 ;
reg [7:0] sim_spmFA ;
reg [7:0] sim_spmFB ;
reg [7:0] sim_spmFC ;
reg [7:0] sim_spmFD ;
reg [7:0] sim_spmFE ;
reg [7:0] sim_spmFF ;
//
// initialise the values
//
initial begin
kcpsm6_status = "A,NZ,NC,ID,Reset" ;
kcpsm6_opcode = "LOAD s0, s0 " ;
sim_s0 = 8'h00 ;
sim_s1 = 8'h00 ;
sim_s2 = 8'h00 ;
sim_s3 = 8'h00 ;
sim_s4 = 8'h00 ;
sim_s5 = 8'h00 ;
sim_s6 = 8'h00 ;
sim_s7 = 8'h00 ;
sim_s8 = 8'h00 ;
sim_s9 = 8'h00 ;
sim_sA = 8'h00 ;
sim_sB = 8'h00 ;
sim_sC = 8'h00 ;
sim_sD = 8'h00 ;
sim_sE = 8'h00 ;
sim_sF = 8'h00 ;
sim_spm00 = 8'h00 ;
sim_spm01 = 8'h00 ;
sim_spm02 = 8'h00 ;
sim_spm03 = 8'h00 ;
sim_spm04 = 8'h00 ;
sim_spm05 = 8'h00 ;
sim_spm06 = 8'h00 ;
sim_spm07 = 8'h00 ;
sim_spm08 = 8'h00 ;
sim_spm09 = 8'h00 ;
sim_spm0A = 8'h00 ;
sim_spm0B = 8'h00 ;
sim_spm0C = 8'h00 ;
sim_spm0D = 8'h00 ;
sim_spm0E = 8'h00 ;
sim_spm0F = 8'h00 ;
sim_spm10 = 8'h00 ;
sim_spm11 = 8'h00 ;
sim_spm12 = 8'h00 ;
sim_spm13 = 8'h00 ;
sim_spm14 = 8'h00 ;
sim_spm15 = 8'h00 ;
sim_spm16 = 8'h00 ;
sim_spm17 = 8'h00 ;
sim_spm18 = 8'h00 ;
sim_spm19 = 8'h00 ;
sim_spm1A = 8'h00 ;
sim_spm1B = 8'h00 ;
sim_spm1C = 8'h00 ;
sim_spm1D = 8'h00 ;
sim_spm1E = 8'h00 ;
sim_spm1F = 8'h00 ;
sim_spm20 = 8'h00 ;
sim_spm21 = 8'h00 ;
sim_spm22 = 8'h00 ;
sim_spm23 = 8'h00 ;
sim_spm24 = 8'h00 ;
sim_spm25 = 8'h00 ;
sim_spm26 = 8'h00 ;
sim_spm27 = 8'h00 ;
sim_spm28 = 8'h00 ;
sim_spm29 = 8'h00 ;
sim_spm2A = 8'h00 ;
sim_spm2B = 8'h00 ;
sim_spm2C = 8'h00 ;
sim_spm2D = 8'h00 ;
sim_spm2E = 8'h00 ;
sim_spm2F = 8'h00 ;
sim_spm30 = 8'h00 ;
sim_spm31 = 8'h00 ;
sim_spm32 = 8'h00 ;
sim_spm33 = 8'h00 ;
sim_spm34 = 8'h00 ;
sim_spm35 = 8'h00 ;
sim_spm36 = 8'h00 ;
sim_spm37 = 8'h00 ;
sim_spm38 = 8'h00 ;
sim_spm39 = 8'h00 ;
sim_spm3A = 8'h00 ;
sim_spm3B = 8'h00 ;
sim_spm3C = 8'h00 ;
sim_spm3D = 8'h00 ;
sim_spm3E = 8'h00 ;
sim_spm3F = 8'h00 ;
sim_spm40 = 8'h00 ;
sim_spm41 = 8'h00 ;
sim_spm42 = 8'h00 ;
sim_spm43 = 8'h00 ;
sim_spm44 = 8'h00 ;
sim_spm45 = 8'h00 ;
sim_spm46 = 8'h00 ;
sim_spm47 = 8'h00 ;
sim_spm48 = 8'h00 ;
sim_spm49 = 8'h00 ;
sim_spm4A = 8'h00 ;
sim_spm4B = 8'h00 ;
sim_spm4C = 8'h00 ;
sim_spm4D = 8'h00 ;
sim_spm4E = 8'h00 ;
sim_spm4F = 8'h00 ;
sim_spm50 = 8'h00 ;
sim_spm51 = 8'h00 ;
sim_spm52 = 8'h00 ;
sim_spm53 = 8'h00 ;
sim_spm54 = 8'h00 ;
sim_spm55 = 8'h00 ;
sim_spm56 = 8'h00 ;
sim_spm57 = 8'h00 ;
sim_spm58 = 8'h00 ;
sim_spm59 = 8'h00 ;
sim_spm5A = 8'h00 ;
sim_spm5B = 8'h00 ;
sim_spm5C = 8'h00 ;
sim_spm5D = 8'h00 ;
sim_spm5E = 8'h00 ;
sim_spm5F = 8'h00 ;
sim_spm60 = 8'h00 ;
sim_spm61 = 8'h00 ;
sim_spm62 = 8'h00 ;
sim_spm63 = 8'h00 ;
sim_spm64 = 8'h00 ;
sim_spm65 = 8'h00 ;
sim_spm66 = 8'h00 ;
sim_spm67 = 8'h00 ;
sim_spm68 = 8'h00 ;
sim_spm69 = 8'h00 ;
sim_spm6A = 8'h00 ;
sim_spm6B = 8'h00 ;
sim_spm6C = 8'h00 ;
sim_spm6D = 8'h00 ;
sim_spm6E = 8'h00 ;
sim_spm6F = 8'h00 ;
sim_spm70 = 8'h00 ;
sim_spm71 = 8'h00 ;
sim_spm72 = 8'h00 ;
sim_spm73 = 8'h00 ;
sim_spm74 = 8'h00 ;
sim_spm75 = 8'h00 ;
sim_spm76 = 8'h00 ;
sim_spm77 = 8'h00 ;
sim_spm78 = 8'h00 ;
sim_spm79 = 8'h00 ;
sim_spm7A = 8'h00 ;
sim_spm7B = 8'h00 ;
sim_spm7C = 8'h00 ;
sim_spm7D = 8'h00 ;
sim_spm7E = 8'h00 ;
sim_spm7F = 8'h00 ;
sim_spm80 = 8'h00 ;
sim_spm81 = 8'h00 ;
sim_spm82 = 8'h00 ;
sim_spm83 = 8'h00 ;
sim_spm84 = 8'h00 ;
sim_spm85 = 8'h00 ;
sim_spm86 = 8'h00 ;
sim_spm87 = 8'h00 ;
sim_spm88 = 8'h00 ;
sim_spm89 = 8'h00 ;
sim_spm8A = 8'h00 ;
sim_spm8B = 8'h00 ;
sim_spm8C = 8'h00 ;
sim_spm8D = 8'h00 ;
sim_spm8E = 8'h00 ;
sim_spm8F = 8'h00 ;
sim_spm90 = 8'h00 ;
sim_spm91 = 8'h00 ;
sim_spm92 = 8'h00 ;
sim_spm93 = 8'h00 ;
sim_spm94 = 8'h00 ;
sim_spm95 = 8'h00 ;
sim_spm96 = 8'h00 ;
sim_spm97 = 8'h00 ;
sim_spm98 = 8'h00 ;
sim_spm99 = 8'h00 ;
sim_spm9A = 8'h00 ;
sim_spm9B = 8'h00 ;
sim_spm9C = 8'h00 ;
sim_spm9D = 8'h00 ;
sim_spm9E = 8'h00 ;
sim_spm9F = 8'h00 ;
sim_spmA0 = 8'h00 ;
sim_spmA1 = 8'h00 ;
sim_spmA2 = 8'h00 ;
sim_spmA3 = 8'h00 ;
sim_spmA4 = 8'h00 ;
sim_spmA5 = 8'h00 ;
sim_spmA6 = 8'h00 ;
sim_spmA7 = 8'h00 ;
sim_spmA8 = 8'h00 ;
sim_spmA9 = 8'h00 ;
sim_spmAA = 8'h00 ;
sim_spmAB = 8'h00 ;
sim_spmAC = 8'h00 ;
sim_spmAD = 8'h00 ;
sim_spmAE = 8'h00 ;
sim_spmAF = 8'h00 ;
sim_spmB0 = 8'h00 ;
sim_spmB1 = 8'h00 ;
sim_spmB2 = 8'h00 ;
sim_spmB3 = 8'h00 ;
sim_spmB4 = 8'h00 ;
sim_spmB5 = 8'h00 ;
sim_spmB6 = 8'h00 ;
sim_spmB7 = 8'h00 ;
sim_spmB8 = 8'h00 ;
sim_spmB9 = 8'h00 ;
sim_spmBA = 8'h00 ;
sim_spmBB = 8'h00 ;
sim_spmBC = 8'h00 ;
sim_spmBD = 8'h00 ;
sim_spmBE = 8'h00 ;
sim_spmBF = 8'h00 ;
sim_spmC0 = 8'h00 ;
sim_spmC1 = 8'h00 ;
sim_spmC2 = 8'h00 ;
sim_spmC3 = 8'h00 ;
sim_spmC4 = 8'h00 ;
sim_spmC5 = 8'h00 ;
sim_spmC6 = 8'h00 ;
sim_spmC7 = 8'h00 ;
sim_spmC8 = 8'h00 ;
sim_spmC9 = 8'h00 ;
sim_spmCA = 8'h00 ;
sim_spmCB = 8'h00 ;
sim_spmCC = 8'h00 ;
sim_spmCD = 8'h00 ;
sim_spmCE = 8'h00 ;
sim_spmCF = 8'h00 ;
sim_spmD0 = 8'h00 ;
sim_spmD1 = 8'h00 ;
sim_spmD2 = 8'h00 ;
sim_spmD3 = 8'h00 ;
sim_spmD4 = 8'h00 ;
sim_spmD5 = 8'h00 ;
sim_spmD6 = 8'h00 ;
sim_spmD7 = 8'h00 ;
sim_spmD8 = 8'h00 ;
sim_spmD9 = 8'h00 ;
sim_spmDA = 8'h00 ;
sim_spmDB = 8'h00 ;
sim_spmDC = 8'h00 ;
sim_spmDD = 8'h00 ;
sim_spmDE = 8'h00 ;
sim_spmDF = 8'h00 ;
sim_spmE0 = 8'h00 ;
sim_spmE1 = 8'h00 ;
sim_spmE2 = 8'h00 ;
sim_spmE3 = 8'h00 ;
sim_spmE4 = 8'h00 ;
sim_spmE5 = 8'h00 ;
sim_spmE6 = 8'h00 ;
sim_spmE7 = 8'h00 ;
sim_spmE8 = 8'h00 ;
sim_spmE9 = 8'h00 ;
sim_spmEA = 8'h00 ;
sim_spmEB = 8'h00 ;
sim_spmEC = 8'h00 ;
sim_spmED = 8'h00 ;
sim_spmEE = 8'h00 ;
sim_spmEF = 8'h00 ;
sim_spmF0 = 8'h00 ;
sim_spmF1 = 8'h00 ;
sim_spmF2 = 8'h00 ;
sim_spmF3 = 8'h00 ;
sim_spmF4 = 8'h00 ;
sim_spmF5 = 8'h00 ;
sim_spmF6 = 8'h00 ;
sim_spmF7 = 8'h00 ;
sim_spmF8 = 8'h00 ;
sim_spmF9 = 8'h00 ;
sim_spmFA = 8'h00 ;
sim_spmFB = 8'h00 ;
sim_spmFC = 8'h00 ;
sim_spmFD = 8'h00 ;
sim_spmFE = 8'h00 ;
sim_spmFF = 8'h00 ;
end
//
//synthesis translate_on
//
//**********************************************************************************
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Start of kcpsm6 circuit description
//
// Summary of all primitives defined.
//
// 29 x LUT6 79 LUTs
// 50 x LUT6_2
// 48 x FD 82 flip-flops
// 20 x FDR (Depending on the value of 'hwbuild' up)
// 0 x FDS (to eight FDR will be replaced by FDS )
// 14 x FDRE
// 29 x MUXCY
// 27 x XORCY
// 4 x RAM32M (16 LUTs)
//
// 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
// (8 LUTs) (16 LUTs) (32 LUTs)
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Perform check of generic to report error as soon as possible.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
initial begin
if (scratch_pad_memory_size != 64 && scratch_pad_memory_size != 128 && scratch_pad_memory_size != 256) begin
#1;
$display("\n\nInvalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256.\n\n");
$finish;
end
end
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// State Machine and Control
//
//
// 1 x LUT6
// 4 x LUT6_2
// 9 x FD
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = "kcpsm6_control" *)
LUT6_2 #(
.INIT (64'hFFFFF55500000EEE))
reset_lut(
.I0 (run),
.I1 (internal_reset),
.I2 (stack_pointer_carry[4]),
.I3 (t_state[2]),
.I4 (reset),
.I5 (1'b1),
.O5 (run_value),
.O6 (internal_reset_value));
(* HBLKNM = "kcpsm6_control" *)
FD run_flop (
.D (run_value),
.Q (run),
.C (clk));
(* HBLKNM = "kcpsm6_control" *)
FD internal_reset_flop(
.D (internal_reset_value),
.Q (internal_reset),
.C (clk));
(* HBLKNM = "kcpsm6_decode2" *)
FD sync_sleep_flop(
.D (sleep),
.Q (sync_sleep),
.C (clk));
(* HBLKNM = "kcpsm6_control" *)
LUT6_2 #(
.INIT (64'h0083000B00C4004C))
t_state_lut(
.I0 (t_state[1]),
.I1 (t_state[2]),
.I2 (sync_sleep),
.I3 (internal_reset),
.I4 (special_bit),
.I5 (1'b1),
.O5 (t_state_value[1]),
.O6 (t_state_value[2]));
(* HBLKNM = "kcpsm6_control" *)
FD t_state1_flop (
.D (t_state_value[1]),
.Q (t_state[1]),
.C (clk));
(* HBLKNM = "kcpsm6_control" *)
FD t_state2_flop (
.D (t_state_value[2]),
.Q (t_state[2]),
.C (clk));
(* HBLKNM = "kcpsm6_decode0" *)
LUT6_2 #(
.INIT (64'h0010000000000800))
int_enable_type_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[15]),
.I3 (instruction[16]),
.I4 (instruction[17]),
.I5 (1'b1),
.O5 (loadstar_type),
.O6 (int_enable_type)) ;
(* HBLKNM = "kcpsm6_decode0" *)
LUT6 #(
.INIT (64'h000000000000CAAA))
interrupt_enable_lut(
.I0 (interrupt_enable),
.I1 (instruction[0]),
.I2 (int_enable_type),
.I3 (t_state[1]),
.I4 (active_interrupt),
.I5 (internal_reset),
.O (interrupt_enable_value));
(* HBLKNM = "kcpsm6_decode0" *)
FD interrupt_enable_flop (
.D (interrupt_enable_value),
.Q (interrupt_enable),
.C (clk));
(* HBLKNM = "kcpsm6_decode2" *)
FD sync_interrupt_flop (
.D (interrupt),
.Q (sync_interrupt),
.C (clk));
(* HBLKNM = "kcpsm6_control" *)
LUT6_2 # (
.INIT (64'hCC33FF0080808080))
active_interrupt_lut(
.I0 (interrupt_enable),
.I1 (t_state[2]),
.I2 (sync_interrupt),
.I3 (bank),
.I4 (loadstar_type),
.I5 (1'b1),
.O5 (active_interrupt_value),
.O6 (sx_addr4_value));
(* HBLKNM = "kcpsm6_control" *)
FD active_interrupt_flop (
.D (active_interrupt_value),
.Q (active_interrupt),
.C (clk));
(* HBLKNM = "kcpsm6_decode1" *)
FD interrupt_ack_flop (
.D (active_interrupt),
.Q (interrupt_ack),
.C (clk));
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Decoders
//
//
// 2 x LUT6
// 10 x LUT6_2
// 2 x FD
// 6 x FDR
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Decoding for Program Counter and Stack
//
(* HBLKNM = "kcpsm6_decode0" *)
LUT6 #(
.INIT (64'h5A3CFFFF00000000))
pc_move_is_valid_lut(
.I0 (carry_flag),
.I1 (zero_flag),
.I2 (instruction[14]),
.I3 (instruction[15]),
.I4 (instruction[16]),
.I5 (instruction[17]),
.O (pc_move_is_valid)) ;
(* HBLKNM = "kcpsm6_decode0" *)
LUT6_2 # (
.INIT (64'h7777027700000200))
move_type_lut(
.I0 (instruction[12]),
.I1 (instruction[13]),
.I2 (instruction[14]),
.I3 (instruction[15]),
.I4 (instruction[16]),
.I5 (1'b1),
.O5 (returni_type),
.O6 (move_type)) ;
(* HBLKNM = "kcpsm6_vector1" *)
LUT6_2 # (
.INIT (64'h0000F000000023FF))
pc_mode1_lut(
.I0 (instruction[12]),
.I1 (returni_type),
.I2 (move_type),
.I3 (pc_move_is_valid),
.I4 (active_interrupt),
.I5 (1'b1),
.O5 (pc_mode[0]),
.O6 (pc_mode[1])) ;
(* HBLKNM = "kcpsm6_vector1" *)
LUT6 # (
.INIT (64'hFFFFFFFF00040000))
pc_mode2_lut(
.I0 (instruction[12]),
.I1 (instruction[14]),
.I2 (instruction[15]),
.I3 (instruction[16]),
.I4 (instruction[17]),
.I5 (active_interrupt),
.O (pc_mode[2])) ;
(* HBLKNM = "kcpsm6_stack1" *)
LUT6_2 # (
.INIT (64'hFFFF100000002000))
push_pop_lut(
.I0 (instruction[12]),
.I1 (instruction[13]),
.I2 (move_type),
.I3 (pc_move_is_valid),
.I4 (active_interrupt),
.I5 (1'b1),
.O5 (pop_stack),
.O6 (push_stack)) ;
//
// Decoding for ALU
//
(* HBLKNM = "kcpsm6_decode2" *)
LUT6_2 #(
.INIT (64'h03CA000004200000))
alu_decode0_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[15]),
.I3 (instruction[16]),
.I4 (1'b1),
.I5 (1'b1),
.O5 (alu_mux_sel_value[0]),
.O6 (arith_logical_sel[0])) ;
(* HBLKNM = "kcpsm6_decode2" *)
FD alu_mux_sel0_flop(
.D (alu_mux_sel_value[0]),
.Q (alu_mux_sel[0]),
.C (clk)) ;
(* HBLKNM = "kcpsm6_decode1" *)
LUT6_2 #(
.INIT (64'h7708000000000F00))
alu_decode1_lut(
.I0 (carry_flag),
.I1 (instruction[13]),
.I2 (instruction[14]),
.I3 (instruction[15]),
.I4 (instruction[16]),
.I5 (1'b1),
.O5 (alu_mux_sel_value[1]),
.O6 (arith_carry_in)) ;
(* HBLKNM = "kcpsm6_decode1" *)
FD alu_mux_sel1_flop (
.D (alu_mux_sel_value[1]),
.Q (alu_mux_sel[1]),
.C (clk)) ;
(* HBLKNM = "kcpsm6_decode2" *)
LUT6_2 # (
.INIT (64'hD000000002000000))
alu_decode2_lut(
.I0 (instruction[14]),
.I1 (instruction[15]),
.I2 (instruction[16]),
.I3 (1'b1),
.I4 (1'b1),
.I5 (1'b1),
.O5 (arith_logical_sel[1]),
.O6 (arith_logical_sel[2])) ;
//
// Decoding for strobes and enables
//
(* HBLKNM = "kcpsm6_strobes" *)
LUT6_2 # (
.INIT (64'h00013F3F0010F7CE))
register_enable_type_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[15]),
.I3 (instruction[16]),
.I4 (instruction[17]),
.I5 (1'b1),
.O5 (flag_enable_type),
.O6 (register_enable_type)) ;
(* HBLKNM = "kcpsm6_strobes" *)
LUT6_2 # (
.INIT (64'hC0CC0000A0AA0000))
register_enable_lut(
.I0 (flag_enable_type),
.I1 (register_enable_type),
.I2 (instruction[12]),
.I3 (instruction[17]),
.I4 (t_state[1]),
.I5 (1'b1),
.O5 (flag_enable_value),
.O6 (register_enable_value)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR flag_enable_flop (
.D (flag_enable_value),
.Q (flag_enable),
.R (active_interrupt),
.C (clk)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR register_enable_flop (
.D (register_enable_value),
.Q (register_enable),
.R (active_interrupt),
.C (clk)) ;
(* HBLKNM = "kcpsm6_strobes" *)
LUT6_2 # (
.INIT (64'h8000000020000000))
spm_enable_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[17]),
.I3 (strobe_type),
.I4 (t_state[1]),
.I5 (1'b1),
.O5 (k_write_strobe_value),
.O6 (spm_enable_value)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR k_write_strobe_flop (
.D (k_write_strobe_value),
.Q (k_write_strobe),
.R (active_interrupt),
.C (clk)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR spm_enable_flop (
.D (spm_enable_value),
.Q (spm_enable),
.R (active_interrupt),
.C (clk)) ;
(* HBLKNM = "kcpsm6_strobes" *)
LUT6_2 # (
.INIT (64'h4000000001000000))
read_strobe_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[17]),
.I3 (strobe_type),
.I4 (t_state[1]),
.I5 (1'b1),
.O5 (read_strobe_value),
.O6 (write_strobe_value)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR write_strobe_flop (
.D (write_strobe_value),
.Q (write_strobe),
.R (active_interrupt),
.C (clk)) ;
(* HBLKNM = "kcpsm6_strobes" *)
FDR read_strobe_flop (
.D (read_strobe_value),
.Q (read_strobe),
.R (active_interrupt),
.C (clk)) ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Register bank control
//
//
// 2 x LUT6
// 1 x FDR
// 1 x FD
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = "kcpsm6_stack1" *)
LUT6 # (
.INIT (64'h0080020000000000))
regbank_type_lut(
.I0 (instruction[12]),
.I1 (instruction[13]),
.I2 (instruction[14]),
.I3 (instruction[15]),
.I4 (instruction[16]),
.I5 (instruction[17]),
.O (regbank_type)) ;
(* HBLKNM = "kcpsm6_stack1" *)
LUT6 # (
.INIT (64'hACACFF00FF00FF00))
bank_lut(
.I0 (instruction[0]),
.I1 (shadow_bank),
.I2 (instruction[16]),
.I3 (bank),
.I4 (regbank_type),
.I5 (t_state[1]),
.O (bank_value)) ;
(* HBLKNM = "kcpsm6_stack1" *)
FDR bank_flop (
.D (bank_value),
.Q (bank),
.R (internal_reset),
.C (clk)) ;
(* HBLKNM = "kcpsm6_control" *)
FD sx_addr4_flop (
.D (sx_addr4_value),
.Q (sx_addr[4]),
.C (clk)) ;
assign sx_addr[3:0] = instruction[11:8] ;
assign sy_addr = {bank, instruction[7:4]} ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Flags
//
//
// 3 x LUT6
// 5 x LUT6_2
// 3 x FD
// 2 x FDRE
// 2 x XORCY
// 5 x MUXCY
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = "kcpsm6_control" *)
XORCY arith_carry_xorcy (
.LI (1'b0),
.CI (carry_arith_logical[7]),
.O (arith_carry_value)) ;
(* HBLKNM = "kcpsm6_control" *)
FD arith_carry_flop (
.D (arith_carry_value),
.Q (arith_carry),
.C (clk)) ;
(* HBLKNM = "kcpsm6_decode2" *)
LUT6_2 # (
.INIT (64'h0000000087780000))
lower_parity_lut(
.I0 (instruction[13]),
.I1 (carry_flag),
.I2 (arith_logical_result[0]),
.I3 (arith_logical_result[1]),
.I4 (1'b1),
.I5 (1'b1),
.O5 (lower_parity),
.O6 (lower_parity_sel)) ;
(* HBLKNM = "kcpsm6_decode2" *)
MUXCY parity_muxcy (
.DI (lower_parity),
.CI (1'b0),
.S (lower_parity_sel),
.O (carry_lower_parity)) ;
(* HBLKNM = "kcpsm6_decode2" *)
LUT6 #(
.INIT (64'h6996966996696996))
upper_parity_lut(
.I0 (arith_logical_result[2]),
.I1 (arith_logical_result[3]),
.I2 (arith_logical_result[4]),
.I3 (arith_logical_result[5]),
.I4 (arith_logical_result[6]),
.I5 (arith_logical_result[7]),
.O (upper_parity)) ;
(* HBLKNM = "kcpsm6_decode2" *)
XORCY parity_xorcy(
.LI (upper_parity),
.CI (carry_lower_parity),
.O (parity)) ;
(* HBLKNM = "kcpsm6_decode1" *)
LUT6 #(
.INIT (64'hFFFFAACCF0F0F0F0))
shift_carry_lut(
.I0 (sx[0]),
.I1 (sx[7]),
.I2 (shadow_carry_flag),
.I3 (instruction[3]),
.I4 (instruction[7]),
.I5 (instruction[16]),
.O (shift_carry_value)) ;
(* HBLKNM = "kcpsm6_decode1" *)
FD shift_carry_flop(
.D (shift_carry_value),
.Q (shift_carry),
.C (clk)) ;
(* HBLKNM = "kcpsm6_flags" *)
LUT6_2 #(
.INIT (64'h3333AACCF0AA0000))
carry_flag_lut(
.I0 (shift_carry),
.I1 (arith_carry),
.I2 (parity),
.I3 (instruction[14]),
.I4 (instruction[15]),
.I5 (instruction[16]),
.O5 (drive_carry_in_zero),
.O6 (carry_flag_value)) ;
(* HBLKNM = "kcpsm6_flags" *)
FDRE carry_flag_flop(
.D (carry_flag_value),
.Q (carry_flag),
.CE (flag_enable),
.R (internal_reset),
.C (clk)) ;
(* HBLKNM = "kcpsm6_flags" *)
MUXCY init_zero_muxcy(
.DI (drive_carry_in_zero),
.CI (1'b0),
.S (carry_flag_value),
.O (carry_in_zero)) ;
(* HBLKNM = "kcpsm6_decode1" *)
LUT6_2 # (
.INIT (64'hA280000000F000F0))
use_zero_flag_lut(
.I0 (instruction[13]),
.I1 (instruction[14]),
.I2 (instruction[15]),
.I3 (instruction[16]),
.I4 (1'b1),
.I5 (1'b1),
.O5 (strobe_type),
.O6 (use_zero_flag_value)) ;
(* HBLKNM = "kcpsm6_decode1" *)
FD use_zero_flag_flop(
.D (use_zero_flag_value),
.Q (use_zero_flag),
.C (clk)) ;
(* HBLKNM = "kcpsm6_flags" *)
LUT6_2 #(
.INIT (64'h0000000000000001))
lower_zero_lut(
.I0 (alu_result[0]),
.I1 (alu_result[1]),
.I2 (alu_result[2]),
.I3 (alu_result[3]),
.I4 (alu_result[4]),
.I5 (1'b1),
.O5 (lower_zero),
.O6 (lower_zero_sel)) ;
(* HBLKNM = "kcpsm6_flags" *)
MUXCY lower_zero_muxcy(
.DI (lower_zero),
.CI (carry_in_zero),
.S (lower_zero_sel),
.O (carry_lower_zero)) ;
(* HBLKNM = "kcpsm6_flags" *)
LUT6_2 # (
.INIT (64'h0000000D00000000))
middle_zero_lut(
.I0 (use_zero_flag),
.I1 (zero_flag),
.I2 (alu_result[5]),
.I3 (alu_result[6]),
.I4 (alu_result[7]),
.I5 (1'b1),
.O5 (middle_zero),
.O6 (middle_zero_sel)) ;
(* HBLKNM = "kcpsm6_flags" *)
MUXCY middle_zero_muxcy(
.DI (middle_zero),
.CI (carry_lower_zero),
.S (middle_zero_sel),
.O (carry_middle_zero)) ;
(* HBLKNM = "kcpsm6_flags" *)
LUT6 #(
.INIT (64'hFBFF000000000000))
upper_zero_lut(
.I0 (instruction[14]),
.I1 (instruction[15]),
.I2 (instruction[16]),
.I3 (1'b1),
.I4 (1'b1),
.I5 (1'b1),
.O (upper_zero_sel)) ;
(* HBLKNM = "kcpsm6_flags" *)
MUXCY upper_zero_muxcy(
.DI (shadow_zero_flag),
.CI (carry_middle_zero),
.S (upper_zero_sel),
.O (zero_flag_value)) ;
(* HBLKNM = "kcpsm6_flags" *)
FDRE zero_flag_flop(
.D (zero_flag_value),
.Q (zero_flag),
.CE (flag_enable),
.R (internal_reset),
.C (clk)) ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// 12-bit Program Address Generation
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Prepare 12-bit vector from the sX and sY register outputs.
//
assign register_vector = {sx[3:0], sy} ;
genvar i ;
generate
for (i = 0 ; i <= 11 ; i = i+1)
begin : address_loop
parameter [7:0] id4 = 8'h30 + i/4 ;
parameter [7:0] id8 = 8'h30 + i/8 ;
parameter [7:0] ip4d8 = 8'h30 + (i+4)/8 ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Selection of vector to load program counter
//
// instruction[12]
// 0 Constant aaa from instruction(11:0)
// 1 Return vector from stack
//
// 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
// Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
//
// 6 x LUT6_2
// 12 x FD
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Pipeline output of the stack memory
//
(* HBLKNM = {"kcpsm6_stack_ram",ip4d8} *)
FD return_vector_flop(
.D (stack_memory[i]),
.Q (return_vector[i]),
.C (clk));
//
// Multiplex instruction constant address and output from stack.
// 2 bits per LUT so only generate when 'i' is even.
//
if (i % 2 == 0) begin: output_data
(* HBLKNM = {"kcpsm6_vector",id8} *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
pc_vector_mux_lut(
.I0 (instruction[i]),
.I1 (return_vector[i]),
.I2 (instruction[i+1]),
.I3 (return_vector[i+1]),
.I4 (instruction[12]),
.I5 (1'b1),
.O5 (pc_vector[i]),
.O6 (pc_vector[i+1]));
end //output_data
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Program Counter
//
// Reset by internal_reset has highest priority.
// Enabled by t_state[1] has second priority.
//
// The function performed is defined by pc_mode(2:0).
//
// pc_mode [2] [1] [0]
// 0 0 1 pc+1 for normal program flow.
// 1 0 0 Forces interrupt vector value (+0) during active interrupt.
// The vector is defined by a generic with default value FF0 hex.
// 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
// 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
// 0 1 1 pc_vector+1 for 'RETURN'.
//
// Note that pc_mode[0] is High during operations that require an increment to occur.
// The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
// pc_mode[0] also has to be connected to the start of the carry chain.
//
// 3 Slices
// 12 x LUT6
// 11 x MUXCY
// 12 x XORCY
// 12 x FDRE
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = {"kcpsm6_pc",id4} *)
FDRE pc_flop(
.D (pc_value[i]),
.Q (pc[i]),
.R (internal_reset),
.CE (t_state[1]),
.C (clk));
if (i == 0) begin: lsb_pc
//
// Logic of LSB must invert selected value when pc_mode[0] is High.
// The interrupt vector is defined by a generic.
//
if (interrupt_vector[i] == 1'b0) begin: low_int_vector
(* HBLKNM = {"kcpsm6_pc",id4} *)
LUT6 #(
.INIT (64'h00AA000033CC0F00))
pc_lut(
.I0 (register_vector[i]),
.I1 (pc_vector[i]),
.I2 (pc[i]),
.I3 (pc_mode[0]),
.I4 (pc_mode[1]),
.I5 (pc_mode[2]),
.O (half_pc[i]));
end //low_int_vector
if (interrupt_vector[i] == 1'b1) begin: high_int_vector
(* HBLKNM = {"kcpsm6_pc",id4} *)
LUT6 #(
.INIT (64'h00AA00FF33CC0F00))
pc_lut(
.I0 (register_vector[i]),
.I1 (pc_vector[i]),
.I2 (pc[i]),
.I3 (pc_mode[0]),
.I4 (pc_mode[1]),
.I5 (pc_mode[2]),
.O (half_pc[i]));
end //high_int_vector
//
// pc_mode[0] connected to first MUXCY and carry input is 1'b0
//
(* HBLKNM = {"kcpsm6_pc",id4} *)
XORCY pc_xorcy(
.LI (half_pc[i]),
.CI (1'b0),
.O (pc_value[i]));
(* HBLKNM = {"kcpsm6_pc",id4} *)
MUXCY pc_muxcy(
.DI (pc_mode[0]),
.CI (1'b0),
.S (half_pc[i]),
.O (carry_pc[i]));
end //lsb_pc
if (i > 0) begin : upper_pc
//
// Logic of upper section selects required value.
// The interrupt vector is defined by a generic.
//
if (interrupt_vector[i] == 1'b0) begin: low_int_vector
(* HBLKNM = {"kcpsm6_pc",id4} *)
LUT6 #(
.INIT (64'h00AA0000CCCCF000))
pc_lut(
.I0 (register_vector[i]),
.I1 (pc_vector[i]),
.I2 (pc[i]),
.I3 (pc_mode[0]),
.I4 (pc_mode[1]),
.I5 (pc_mode[2]),
.O (half_pc[i]));
end //low_int_vector
if (interrupt_vector[i] == 1'b1) begin: high_int_vector
(* HBLKNM = {"kcpsm6_pc",id4} *)
LUT6 #(
.INIT (64'h00AA00FFCCCCF000))
pc_lut(
.I0 (register_vector[i]),
.I1 (pc_vector[i]),
.I2 (pc[i]),
.I3 (pc_mode[0]),
.I4 (pc_mode[1]),
.I5 (pc_mode[2]),
.O (half_pc[i]));
end //high_int_vector
//
// Carry chain implementing remainder of increment function
//
(* HBLKNM = {"kcpsm6_pc",id4} *)
XORCY pc_xorcy(
.LI (half_pc[i]),
.CI (carry_pc[i-1]),
.O (pc_value[i]));
//
// No MUXCY required at the top of the chain
//
if (i < 11) begin: mid_pc
(* HBLKNM = {"kcpsm6_pc",id4} *)
MUXCY pc_muxcy(
.DI (1'b0),
.CI (carry_pc[i-1]),
.S (half_pc[i]),
.O (carry_pc[i]));
end //mid_pc
end //upper_pc
//
///////////////////////////////////////////////////////////////////////////////////////////
//
end //address_loop
endgenerate
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Stack
// Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
// Also preserves flags and bank selection during interrupt.
//
// 2 x RAM32M
// 4 x FD
// 5 x FDR
// 1 x LUT6
// 4 x LUT6_2
// 5 x XORCY
// 5 x MUXCY
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = "kcpsm6_stack_ram0" *)
FD shadow_carry_flag_flop(
.D (stack_carry_flag),
.Q (shadow_carry_flag),
.C (clk)) ;
(* HBLKNM = "kcpsm6_stack_ram0" *)
FD stack_zero_flop(
.D (stack_zero_flag),
.Q (shadow_zero_value),
.C (clk)) ;
(* HBLKNM = "kcpsm6_decode1" *)
FD shadow_zero_flag_flop(
.D (shadow_zero_value),
.Q (shadow_zero_flag),
.C (clk)) ;
(* HBLKNM = "kcpsm6_stack_ram0" *)
FD shadow_bank_flop(
.D (stack_bank),
.Q (shadow_bank),
.C (clk)) ;
(* HBLKNM = "kcpsm6_stack_ram0" *)
FD stack_bit_flop(
.D (stack_bit),
.Q (special_bit),
.C (clk)) ;
(* HBLKNM = "kcpsm6_stack_ram0" *)
RAM32M #(
.INIT_A (64'h0000000000000000),
.INIT_B (64'h0000000000000000),
.INIT_C (64'h0000000000000000),
.INIT_D (64'h0000000000000000))
stack_ram_low (
.DOA ({stack_zero_flag, stack_carry_flag}),
.DOB ({stack_bit, stack_bank}),
.DOC (stack_memory[1:0]),
.DOD (stack_memory[3:2]),
.ADDRA (stack_pointer[4:0]),
.ADDRB (stack_pointer[4:0]),
.ADDRC (stack_pointer[4:0]),
.ADDRD (stack_pointer[4:0]),
.DIA ({zero_flag, carry_flag}),
.DIB ({run, bank}),
.DIC (pc[1:0]),
.DID (pc[3:2]),
.WE (t_state[1]),
.WCLK (clk));
(* HBLKNM = "kcpsm6_stack_ram1" *)
RAM32M #(
.INIT_A (64'h0000000000000000),
.INIT_B (64'h0000000000000000),
.INIT_C (64'h0000000000000000),
.INIT_D (64'h0000000000000000))
stack_ram_high(
.DOA (stack_memory[5:4]),
.DOB (stack_memory[7:6]),
.DOC (stack_memory[9:8]),
.DOD (stack_memory[11:10]),
.ADDRA (stack_pointer[4:0]),
.ADDRB (stack_pointer[4:0]),
.ADDRC (stack_pointer[4:0]),
.ADDRD (stack_pointer[4:0]),
.DIA (pc[5:4]),
.DIB (pc[7:6]),
.DIC (pc[9:8]),
.DID (pc[11:10]),
.WE (t_state[1]),
.WCLK (clk));
generate
for (i = 0 ; i <= 4 ; i = i+1)
begin : stack_loop
parameter [7:0] id4 = 8'h30 + i/4 ;
if (i == 0) begin: lsb_stack
(* HBLKNM = {"kcpsm6_stack",id4} *)
FDR pointer_flop(
.D (stack_pointer_value[i]),
.Q (stack_pointer[i]),
.R (internal_reset),
.C (clk)) ;
(* HBLKNM = {"kcpsm6_stack",id4} *)
LUT6_2 #(
.INIT (64'h001529AAAAAAAAAA))
stack_pointer_lut(
.I0 (stack_pointer[i]),
.I1 (pop_stack),
.I2 (push_stack),
.I3 (t_state[1]),
.I4 (t_state[2]),
.I5 (1'b1),
.O5 (feed_pointer_value[i]),
.O6 (half_pointer_value[i]));
(* HBLKNM = {"kcpsm6_stack",id4} *)
XORCY stack_xorcy(
.LI (half_pointer_value[i]),
.CI (1'b0),
.O (stack_pointer_value[i]));
(* HBLKNM = {"kcpsm6_stack",id4} *)
MUXCY stack_muxcy(
.DI (feed_pointer_value[i]),
.CI (1'b0),
.S (half_pointer_value[i]),
.O (stack_pointer_carry[i]));
end //lsb_stack
if (i > 0) begin: upper_stack
(* HBLKNM = {"kcpsm6_stack",id4} *)
FDR pointer_flop(
.D (stack_pointer_value[i]),
.Q (stack_pointer[i]),
.R (internal_reset),
.C (clk)) ;
(* HBLKNM = {"kcpsm6_stack",id4} *)
LUT6_2 #(
.INIT (64'h002A252AAAAAAAAA))
stack_pointer_lut(
.I0 (stack_pointer[i]),
.I1 (pop_stack),
.I2 (push_stack),
.I3 (t_state[1]),
.I4 (t_state[2]),
.I5 (1'b1),
.O5 (feed_pointer_value[i]),
.O6 (half_pointer_value[i]));
(* HBLKNM = {"kcpsm6_stack",id4} *)
XORCY stack_xorcy(
.LI (half_pointer_value[i]),
.CI (stack_pointer_carry[i-1]),
.O (stack_pointer_value[i]));
(* HBLKNM = {"kcpsm6_stack",id4} *)
MUXCY stack_muxcy(
.DI (feed_pointer_value[i]),
.CI (stack_pointer_carry[i-1]),
.S (half_pointer_value[i]),
.O (stack_pointer_carry[i]));
end //upper_stack
end //stack_loop
endgenerate
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// 8-bit Data Path
//
///////////////////////////////////////////////////////////////////////////////////////////
//
generate
for (i = 0 ; i <= 7 ; i = i+1)
begin : data_path_loop
parameter [7:0] id1 = 8'h30 + i ;
parameter [7:0] id2 = 8'h30 + i/2 ;
parameter [7:0] id4 = 8'h30 + i/4 ;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Selection of second operand to ALU and port_id
//
// instruction[12]
// 0 Register sY
// 1 Constant kk
//
// 4 x LUT6_2
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// 2 bits per LUT so only generate when 'i' is even
//
if (i % 2 == 0) begin: output_data
(* HBLKNM = "kcpsm6_port_id" *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
sy_kk_mux_lut(
.I0 (sy[i]),
.I1 (instruction[i]),
.I2 (sy[i+1]),
.I3 (instruction[i+1]),
.I4 (instruction[12]),
.I5 (1'b1),
.O5 (sy_or_kk[i]),
.O6 (sy_or_kk[i+1]));
end //output_data
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Selection of out_port value
//
// instruction[13]
// 0 Register sX
// 1 Constant kk from instruction(11:4)
//
// 4 x LUT6_2
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// 2 bits per LUT so only generate when 'i' is even
//
if (i % 2 == 0) begin: second_operand
(* HBLKNM = "kcpsm6_out_port" *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
out_port_lut(
.I0 (sx[i]),
.I1 (instruction[i+4]),
.I2 (sx[i+1]),
.I3 (instruction[i+5]),
.I4 (instruction[13]),
.I5 (1'b1),
.O5 (out_port[i]),
.O6 (out_port[i+1]));
end //second_operand;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Arithmetic and Logical operations
//
// Definition of....
// ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
// LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
//
// arith_logical_sel [2] [1] [0]
// 0 0 0 - LOAD
// 0 0 1 - AND
// 0 1 0 - OR
// 0 1 1 - XOR
// 1 X 0 - SUB
// 1 X 1 - ADD
//
// Includes pipeline stage.
//
// 2 Slices
// 8 x LUT6_2
// 8 x MUXCY
// 8 x XORCY
// 8 x FD
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = {"kcpsm6_add",id4} *)
LUT6_2 #(
.INIT (64'h69696E8ACCCC0000))
arith_logical_lut(
.I0 (sy_or_kk[i]),
.I1 (sx[i]),
.I2 (arith_logical_sel[0]),
.I3 (arith_logical_sel[1]),
.I4 (arith_logical_sel[2]),
.I5 (1'b1),
.O5 (logical_carry_mask[i]),
.O6 (half_arith_logical[i]));
(* HBLKNM = {"kcpsm6_add",id4} *)
FD arith_logical_flop(
.D (arith_logical_value[i]),
.Q (arith_logical_result[i]),
.C (clk)) ;
if (i == 0) begin: lsb_arith_logical
//
// Carry input to first MUXCY and XORCY
//
(* HBLKNM = {"kcpsm6_add",id4} *)
MUXCY arith_logical_muxcy(
.DI (logical_carry_mask[i]),
.CI (arith_carry_in),
.S (half_arith_logical[i]),
.O (carry_arith_logical[i]));
(* HBLKNM = {"kcpsm6_add",id4} *)
XORCY arith_logical_xorcy(
.LI (half_arith_logical[i]),
.CI (arith_carry_in),
.O (arith_logical_value[i]));
end //lsb_arith_logical
if (i > 0) begin: upper_arith_logical
//
// Main carry chain
//
(* HBLKNM = {"kcpsm6_add",id4} *)
MUXCY arith_logical_muxcy(
.DI (logical_carry_mask[i]),
.CI (carry_arith_logical[i-1]),
.S (half_arith_logical[i]),
.O (carry_arith_logical[i]));
(* HBLKNM = {"kcpsm6_add",id4} *)
XORCY arith_logical_xorcy(
.LI (half_arith_logical[i]),
.CI (carry_arith_logical[i-1]),
.O (arith_logical_value[i]));
end //upper_arith_logical;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Shift and Rotate operations
//
// Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
//
// instruction [3] [2] [1] [0]
// 0 1 1 0 - SL0
// 0 1 1 1 - SL1
// 0 1 0 0 - SLX
// 0 0 0 0 - SLA
// 0 0 1 0 - RL
// 1 1 1 0 - SR0
// 1 1 1 1 - SR1
// 1 0 1 0 - SRX
// 1 0 0 0 - SRA
// 1 1 0 0 - RR
//
// instruction[3]
// 0 - Left
// 1 - Right
//
// instruction [2] [1] Bit shifted in
// 0 0 Carry_flag
// 0 1 sX[7]
// 1 0 sX[0]
// 1 1 instruction[0]
//
// Includes pipeline stage.
//
// 4 x LUT6_2
// 1 x LUT6
// 8 x FD
//
///////////////////////////////////////////////////////////////////////////////////////////
//
if (hwbuild[i] == 1'b0) begin: low_hwbuild
//
// Reset Flip-flop to form 1'b0 for this bit of HWBUILD
//
(* HBLKNM = "kcpsm6_sandr" *)
FDR shift_rotate_flop(
.D (shift_rotate_value[i]),
.Q (shift_rotate_result[i]),
.R (instruction[7]),
.C (clk)) ;
end // low_hwbuild;
if (hwbuild[i] == 1'b1) begin: high_hwbuild
//
// Set Flip-flop to form 1'b1 for this bit of HWBUILD
//
(* HBLKNM = "kcpsm6_sandr" *)
FDS shift_rotate_flop(
.D (shift_rotate_value[i]),
.Q (shift_rotate_result[i]),
.S (instruction[7]),
.C (clk)) ;
end // high_hwbuild;
if (i == 0) begin: lsb_shift_rotate
//
// Select bit to be shifted or rotated into result
//
(* HBLKNM = "kcpsm6_decode1" *)
LUT6 #(
.INIT (64'hBFBC8F8CB3B08380))
shift_bit_lut(
.I0 (instruction[0]),
.I1 (instruction[1]),
.I2 (instruction[2]),
.I3 (carry_flag),
.I4 (sx[0]),
.I5 (sx[7]),
.O (shift_in_bit));
//
// Define lower bits of result
//
(* HBLKNM = "kcpsm6_sandr" *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
shift_rotate_lut(
.I0 (shift_in_bit),
.I1 (sx[i+1]),
.I2 (sx[i]),
.I3 (sx[i+2]),
.I4 (instruction[3]),
.I5 (1'b1),
.O5 (shift_rotate_value[i]),
.O6 (shift_rotate_value[i+1]));
end // lsb_shift_rotate;
if (i == 2 || i == 4) begin: mid_shift_rotate
//
// Define middle bits of result
//
(* HBLKNM = "kcpsm6_sandr" *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
shift_rotate_lut(
.I0 (sx[i-1]),
.I1 (sx[i+1]),
.I2 (sx[i]),
.I3 (sx[i+2]),
.I4 (instruction[3]),
.I5 (1'b1),
.O5 (shift_rotate_value[i]),
.O6 (shift_rotate_value[i+1]));
end // mid_shift_rotate;
if (i == 6) begin: msb_shift_rotate
//
// Define upper bits of result
//
(* HBLKNM = "kcpsm6_sandr" *)
LUT6_2 #(
.INIT (64'hFF00F0F0CCCCAAAA))
shift_rotate_lut(
.I0 (sx[i-1]),
.I1 (sx[i+1]),
.I2 (sx[i]),
.I3 (shift_in_bit),
.I4 (instruction[3]),
.I5 (1'b1),
.O5 (shift_rotate_value[i]),
.O6 (shift_rotate_value[i+1]));
end // msb_shift_rotate;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Multiplex outputs from ALU functions, scratch pad memory and input port.
//
// alu_mux_sel [1] [0]
// 0 0 Arithmetic and Logical Instructions
// 0 1 Shift and Rotate Instructions
// 1 0 Input Port
// 1 1 Scratch Pad Memory
//
// 8 x LUT6
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = {"kcpsm6_alu",id4} *)
LUT6 #(
.INIT (64'hFF00F0F0CCCCAAAA))
alu_mux_lut(
.I0 (arith_logical_result[i]),
.I1 (shift_rotate_result[i]),
.I2 (in_port[i]),
.I3 (spm_data[i]),
.I4 (alu_mux_sel[0]),
.I5 (alu_mux_sel[1]),
.O (alu_result[i]));
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Scratchpad Memory with output register.
//
// The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
// The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
// bytes at an additional cost of 2 and 6 Slices.
//
//
// 8 x RAM256X1S (256 bytes).
// 8 x RAM128X1S (128 bytes).
// 2 x RAM64M (64 bytes).
//
// 8 x FD.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
if (scratch_pad_memory_size == 64) begin : small_spm
(* HBLKNM = {"kcpsm6_spm",id4} *)
FD spm_flop(
.D (spm_ram_data[i]),
.Q (spm_data[i]),
.C (clk)) ;
if (i == 0 || i == 4) begin: small_spm_ram
RAM64M #(
.INIT_A (64'h0000000000000000),
.INIT_B (64'h0000000000000000),
.INIT_C (64'h0000000000000000),
.INIT_D (64'h0000000000000000))
spm_ram(
.DOA (spm_ram_data[i]),
.DOB (spm_ram_data[i+1]),
.DOC (spm_ram_data[i+2]),
.DOD (spm_ram_data[i+3]),
.ADDRA (sy_or_kk[5:0]),
.ADDRB (sy_or_kk[5:0]),
.ADDRC (sy_or_kk[5:0]),
.ADDRD (sy_or_kk[5:0]),
.DIA (sx[i]),
.DIB (sx[i+1]),
.DIC (sx[i+2]),
.DID (sx[i+3]),
.WE (spm_enable),
.WCLK (clk));
end // small_spm_ram;
end // small_spm;
if (scratch_pad_memory_size == 128) begin : medium_spm
(* HBLKNM = {"kcpsm6_spm",id2} *)
RAM128X1S #(
.INIT (128'h00000000000000000000000000000000))
spm_ram(
.D (sx[i]),
.WE (spm_enable),
.WCLK (clk),
.A0 (sy_or_kk[0]),
.A1 (sy_or_kk[1]),
.A2 (sy_or_kk[2]),
.A3 (sy_or_kk[3]),
.A4 (sy_or_kk[4]),
.A5 (sy_or_kk[5]),
.A6 (sy_or_kk[6]),
.O (spm_ram_data[i]));
(* HBLKNM = {"kcpsm6_spm",id2} *)
FD spm_flop(
.D (spm_ram_data[i]),
.Q (spm_data[i]),
.C (clk)) ;
end // medium_spm;
if (scratch_pad_memory_size == 256) begin : large_spm
(* HBLKNM = {"kcpsm6_spm",id1} *)
RAM256X1S #(
.INIT (256'h0000000000000000000000000000000000000000000000000000000000000000))
spm_ram (
.D (sx[i]),
.WE (spm_enable),
.WCLK (clk),
.A (sy_or_kk),
.O (spm_ram_data[i]));
(* HBLKNM = {"kcpsm6_spm",id1} *)
FD spm_flop(
.D (spm_ram_data[i]),
.Q (spm_data[i]),
.C (clk)) ;
end // large_spm;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
end // data_path_loop;
endgenerate
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Two Banks of 16 General Purpose Registers.
//
// sx_addr - Address for sX is formed by bank select and instruction[11:8]
// sy_addr - Address for sY is formed by bank select and instruction[7:4]
//
// 2 Slices
// 2 x RAM32M
//
///////////////////////////////////////////////////////////////////////////////////////////
//
(* HBLKNM = "kcpsm6_reg0" *)
RAM32M #(
.INIT_A (64'h0000000000000000),
.INIT_B (64'h0000000000000000),
.INIT_C (64'h0000000000000000),
.INIT_D (64'h0000000000000000))
lower_reg_banks(
.DOA (sy[1:0]),
.DOB (sx[1:0]),
.DOC (sy[3:2]),
.DOD (sx[3:2]),
.ADDRA (sy_addr),
.ADDRB (sx_addr),
.ADDRC (sy_addr),
.ADDRD (sx_addr),
.DIA (alu_result[1:0]),
.DIB (alu_result[1:0]),
.DIC (alu_result[3:2]),
.DID (alu_result[3:2]),
.WE (register_enable),
.WCLK (clk));
(* HBLKNM = "kcpsm6_reg1" *)
RAM32M #(
.INIT_A (64'h0000000000000000),
.INIT_B (64'h0000000000000000),
.INIT_C (64'h0000000000000000),
.INIT_D (64'h0000000000000000))
upper_reg_banks(
.DOA (sy[5:4]),
.DOB (sx[5:4]),
.DOC (sy[7:6]),
.DOD (sx[7:6]),
.ADDRA (sy_addr),
.ADDRB (sx_addr),
.ADDRC (sy_addr),
.ADDRD (sx_addr),
.DIA (alu_result[5:4]),
.DIB (alu_result[5:4]),
.DIC (alu_result[7:6]),
.DID (alu_result[7:6]),
.WE (register_enable),
.WCLK (clk));
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Connections to KCPSM6 outputs.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
assign address = pc;
assign bram_enable = t_state[2];
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// Connections KCPSM6 Outputs.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
assign port_id = sy_or_kk;
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// End of description for kcpsm6 macro.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// *****************************************************
// * Code for simulation purposes only after this line *
// *****************************************************
//
//
// Disassemble the instruction codes to form a text string for display.
// Determine status of reset and flags and present in the form of a text string.
// Provide signals to simulate the contents of each register and scratch pad memory
// location.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//All of this section is ignored during synthesis.
//synthesis translate_off
//
//
// Variables for contents of each register in each bank
//
reg [7:0] bank_a_s0 ;
reg [7:0] bank_a_s1 ;
reg [7:0] bank_a_s2 ;
reg [7:0] bank_a_s3 ;
reg [7:0] bank_a_s4 ;
reg [7:0] bank_a_s5 ;
reg [7:0] bank_a_s6 ;
reg [7:0] bank_a_s7 ;
reg [7:0] bank_a_s8 ;
reg [7:0] bank_a_s9 ;
reg [7:0] bank_a_sa ;
reg [7:0] bank_a_sb ;
reg [7:0] bank_a_sc ;
reg [7:0] bank_a_sd ;
reg [7:0] bank_a_se ;
reg [7:0] bank_a_sf ;
reg [7:0] bank_b_s0 ;
reg [7:0] bank_b_s1 ;
reg [7:0] bank_b_s2 ;
reg [7:0] bank_b_s3 ;
reg [7:0] bank_b_s4 ;
reg [7:0] bank_b_s5 ;
reg [7:0] bank_b_s6 ;
reg [7:0] bank_b_s7 ;
reg [7:0] bank_b_s8 ;
reg [7:0] bank_b_s9 ;
reg [7:0] bank_b_sa ;
reg [7:0] bank_b_sb ;
reg [7:0] bank_b_sc ;
reg [7:0] bank_b_sd ;
reg [7:0] bank_b_se ;
reg [7:0] bank_b_sf ;
//
initial begin
bank_a_s0 = 8'h00 ;
bank_a_s1 = 8'h00 ;
bank_a_s2 = 8'h00 ;
bank_a_s3 = 8'h00 ;
bank_a_s4 = 8'h00 ;
bank_a_s5 = 8'h00 ;
bank_a_s6 = 8'h00 ;
bank_a_s7 = 8'h00 ;
bank_a_s8 = 8'h00 ;
bank_a_s9 = 8'h00 ;
bank_a_sa = 8'h00 ;
bank_a_sb = 8'h00 ;
bank_a_sc = 8'h00 ;
bank_a_sd = 8'h00 ;
bank_a_se = 8'h00 ;
bank_a_sf = 8'h00 ;
bank_b_s0 = 8'h00 ;
bank_b_s1 = 8'h00 ;
bank_b_s2 = 8'h00 ;
bank_b_s3 = 8'h00 ;
bank_b_s4 = 8'h00 ;
bank_b_s5 = 8'h00 ;
bank_b_s6 = 8'h00 ;
bank_b_s7 = 8'h00 ;
bank_b_s8 = 8'h00 ;
bank_b_s9 = 8'h00 ;
bank_b_sa = 8'h00 ;
bank_b_sb = 8'h00 ;
bank_b_sc = 8'h00 ;
bank_b_sd = 8'h00 ;
bank_b_se = 8'h00 ;
bank_b_sf = 8'h00 ;
end
//
// Temporary variables for instruction decoding
//
wire [1:16] sx_decode ; //sX register specification
wire [1:16] sy_decode ; //sY register specification
wire [1:16] kk_decode ; //constant value specification
wire [1:24] aaa_decode ; //address specification
wire clk_del ; // Delayed clock for simulation
//
/////////////////////////////////////////////////////////////////////////////////////////
//
// Function to convert 4-bit binary nibble to hexadecimal character
//
/////////////////////////////////////////////////////////////////////////////////////////
//
function [1:8] hexcharacter ;
input [3:0] nibble ;
begin
case (nibble)
4'b0000 : hexcharacter = "0" ;
4'b0001 : hexcharacter = "1" ;
4'b0010 : hexcharacter = "2" ;
4'b0011 : hexcharacter = "3" ;
4'b0100 : hexcharacter = "4" ;
4'b0101 : hexcharacter = "5" ;
4'b0110 : hexcharacter = "6" ;
4'b0111 : hexcharacter = "7" ;
4'b1000 : hexcharacter = "8" ;
4'b1001 : hexcharacter = "9" ;
4'b1010 : hexcharacter = "A" ;
4'b1011 : hexcharacter = "B" ;
4'b1100 : hexcharacter = "C" ;
4'b1101 : hexcharacter = "D" ;
4'b1110 : hexcharacter = "E" ;
4'b1111 : hexcharacter = "F" ;
endcase
end
endfunction
//
/////////////////////////////////////////////////////////////////////////////////////////
//
// decode first register sX
assign sx_decode[1:8] = "s";
assign sx_decode[9:16] = hexcharacter(instruction[11:8]);
// decode second register sY
assign sy_decode[1:8] = "s";
assign sy_decode[9:16] = hexcharacter(instruction[7:4]);
// decode constant value
assign kk_decode[1:8] = hexcharacter(instruction[7:4]);
assign kk_decode[9:16] = hexcharacter(instruction[3:0]);
// address value
assign aaa_decode[1:8] = hexcharacter(instruction[11:8]);
assign aaa_decode[9:16] = hexcharacter(instruction[7:4]);
assign aaa_decode[17:24] = hexcharacter(instruction[3:0]);
assign #200 clk_del = clk ;
// decode instruction
//always @ (clk or instruction or carry_flag or zero_flag or bank or interrupt_enable)
always @ (posedge clk_del)
begin : simulation
case (instruction[17:12])
6'b000000 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", sy_decode, " "} ;
6'b000001 : kcpsm6_opcode <= {"LOAD ", sx_decode, ", ", kk_decode, " "} ;
6'b010110 : kcpsm6_opcode <= {"STAR ", sx_decode, ", ", sy_decode, " "} ;
6'b010111 : kcpsm6_opcode <= {"STAR ", sx_decode, ", ", kk_decode, " "} ;
6'b000010 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", sy_decode, " "} ;
6'b000011 : kcpsm6_opcode <= {"AND ", sx_decode, ", ", kk_decode, " "} ;
6'b000100 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", sy_decode, " "} ;
6'b000101 : kcpsm6_opcode <= {"OR ", sx_decode, ", ", kk_decode, " "} ;
6'b000110 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", sy_decode, " "} ;
6'b000111 : kcpsm6_opcode <= {"XOR ", sx_decode, ", ", kk_decode, " "} ;
6'b001100 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", sy_decode, " "} ;
6'b001101 : kcpsm6_opcode <= {"TEST ", sx_decode, ", ", kk_decode, " "} ;
6'b001110 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", sy_decode, " "} ;
6'b001111 : kcpsm6_opcode <= {"TESTCY ", sx_decode, ", ", kk_decode, " "} ;
6'b010000 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", sy_decode, " "} ;
6'b010001 : kcpsm6_opcode <= {"ADD ", sx_decode, ", ", kk_decode, " "} ;
6'b010010 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", sy_decode, " "} ;
6'b010011 : kcpsm6_opcode <= {"ADDCY ", sx_decode, ", ", kk_decode, " "} ;
6'b011000 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", sy_decode, " "} ;
6'b011001 : kcpsm6_opcode <= {"SUB ", sx_decode, ", ", kk_decode, " "} ;
6'b011010 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", sy_decode, " "} ;
6'b011011 : kcpsm6_opcode <= {"SUBCY ", sx_decode, ", ", kk_decode, " "} ;
6'b011100 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", sy_decode, " "} ;
6'b011101 : kcpsm6_opcode <= {"COMPARE ", sx_decode, ", ", kk_decode, " "} ;
6'b011110 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", sy_decode, " "} ;
6'b011111 : kcpsm6_opcode <= {"COMPARECY ", sx_decode, ", ", kk_decode, " "} ;
6'b010100 : begin
if (instruction[7] == 1'b1)
kcpsm6_opcode <= {"HWBUILD ", sx_decode, " "} ;
else
case (instruction[3:0])
4'b0110 : kcpsm6_opcode <= {"SL0 ", sx_decode, " "} ;
4'b0111 : kcpsm6_opcode <= {"SL1 ", sx_decode, " "} ;
4'b0100 : kcpsm6_opcode <= {"SLX ", sx_decode, " "} ;
4'b0000 : kcpsm6_opcode <= {"SLA ", sx_decode, " "} ;
4'b0010 : kcpsm6_opcode <= {"RL ", sx_decode, " "} ;
4'b1110 : kcpsm6_opcode <= {"SR0 ", sx_decode, " "} ;
4'b1111 : kcpsm6_opcode <= {"SR1 ", sx_decode, " "} ;
4'b1010 : kcpsm6_opcode <= {"SRX ", sx_decode, " "} ;
4'b1000 : kcpsm6_opcode <= {"SRA ", sx_decode, " "} ;
4'b1100 : kcpsm6_opcode <= {"RR ", sx_decode, " "} ;
default : kcpsm6_opcode <= "Invalid Instruction";
endcase
end
6'b101100 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", (", sy_decode, ") "} ;
6'b101101 : kcpsm6_opcode <= {"OUTPUT ", sx_decode, ", ", kk_decode, " "} ;
6'b101011 : kcpsm6_opcode <= {"OUTPUTK ", aaa_decode[1:16], ", ", aaa_decode[17:24], " " };
6'b001000 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", (", sy_decode, ") "} ;
6'b001001 : kcpsm6_opcode <= {"INPUT ", sx_decode, ", ", kk_decode, " "} ;
6'b101110 : kcpsm6_opcode <= {"STORE ", sx_decode, ", (", sy_decode, ") "} ;
6'b101111 : kcpsm6_opcode <= {"STORE ", sx_decode, ", ", kk_decode, " "} ;
6'b001010 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", (", sy_decode, ") "} ;
6'b001011 : kcpsm6_opcode <= {"FETCH ", sx_decode, ", ", kk_decode, " "} ;
6'b100010 : kcpsm6_opcode <= {"JUMP ", aaa_decode, " "} ;
6'b110010 : kcpsm6_opcode <= {"JUMP Z, ", aaa_decode, " "} ;
6'b110110 : kcpsm6_opcode <= {"JUMP NZ, ", aaa_decode, " "} ;
6'b111010 : kcpsm6_opcode <= {"JUMP C, ", aaa_decode, " "} ;
6'b111110 : kcpsm6_opcode <= {"JUMP NC, ", aaa_decode, " "} ;
6'b100110 : kcpsm6_opcode <= {"JUMP@ (", sx_decode, ", ", sy_decode, ") "} ;
6'b100000 : kcpsm6_opcode <= {"CALL ", aaa_decode, " "} ;
6'b110000 : kcpsm6_opcode <= {"CALL Z, ", aaa_decode, " "} ;
6'b110100 : kcpsm6_opcode <= {"CALL NZ, ", aaa_decode, " "} ;
6'b111000 : kcpsm6_opcode <= {"CALL C, ", aaa_decode, " "} ;
6'b111100 : kcpsm6_opcode <= {"CALL NC, ", aaa_decode, " "} ;
6'b100100 : kcpsm6_opcode <= {"CALL@ (", sx_decode, ", ", sy_decode, ") "} ;
6'b100101 : kcpsm6_opcode <= {"RETURN "} ;
6'b110001 : kcpsm6_opcode <= {"RETURN Z "} ;
6'b110101 : kcpsm6_opcode <= {"RETURN NZ "} ;
6'b111001 : kcpsm6_opcode <= {"RETURN C "} ;
6'b111101 : kcpsm6_opcode <= {"RETURN NC "} ;
6'b100001 : kcpsm6_opcode <= {"LOAD&RETURN ", sx_decode, ", ", kk_decode, " "} ;
6'b101001 : begin
case (instruction[0])
1'b0 : kcpsm6_opcode <= "RETURNI DISABLE ";
1'b1 : kcpsm6_opcode <= "RETURNI ENABLE ";
default : kcpsm6_opcode <= "Invalid Instruction";
endcase
end
6'b101000 : begin
case (instruction[0])
1'b0 : kcpsm6_opcode <= "DISABLE INTERRUPT ";
1'b1 : kcpsm6_opcode <= "ENABLE INTERRUPT ";
default : kcpsm6_opcode <= "Invalid Instruction";
endcase
end
6'b110111 : begin
case (instruction[0])
1'b0 : kcpsm6_opcode <= "REGBANK A ";
1'b1 : kcpsm6_opcode <= "REGBANK B ";
default : kcpsm6_opcode <= "Invalid Instruction";
endcase
end
default : kcpsm6_opcode <= "Invalid Instruction";
endcase
// Flag status information
if (zero_flag == 1'b0)
kcpsm6_status[17:40] <= "NZ,";
else
kcpsm6_status[17:40] <= " Z,";
if (carry_flag == 1'b0)
kcpsm6_status[41:64] <= "NC,";
else
kcpsm6_status[41:64] <= " C,";
if (interrupt_enable == 1'b0)
kcpsm6_status[65:80] <= "ID";
else
kcpsm6_status[65:80] <= "IE";
// Operational status
if (clk) begin
if (internal_reset == 1'b1)
kcpsm6_status[81 : 128] <= ",Reset";
else
if (sync_sleep == 1'b1 && t_state == 2'b00)
kcpsm6_status[81 : 128] <= ",Sleep";
else
kcpsm6_status[81 : 128] <= " ";
end
// Simulation of register contents
if (clk) begin
if (register_enable == 1'b1) begin
case (sx_addr)
5'b00000 : bank_a_s0 <= alu_result ;
5'b00001 : bank_a_s1 <= alu_result ;
5'b00010 : bank_a_s2 <= alu_result ;
5'b00011 : bank_a_s3 <= alu_result ;
5'b00100 : bank_a_s4 <= alu_result ;
5'b00101 : bank_a_s5 <= alu_result ;
5'b00110 : bank_a_s6 <= alu_result ;
5'b00111 : bank_a_s7 <= alu_result ;
5'b01000 : bank_a_s8 <= alu_result ;
5'b01001 : bank_a_s9 <= alu_result ;
5'b01010 : bank_a_sa <= alu_result ;
5'b01011 : bank_a_sb <= alu_result ;
5'b01100 : bank_a_sc <= alu_result ;
5'b01101 : bank_a_sd <= alu_result ;
5'b01110 : bank_a_se <= alu_result ;
5'b01111 : bank_a_sf <= alu_result ;
5'b10000 : bank_b_s0 <= alu_result ;
5'b10001 : bank_b_s1 <= alu_result ;
5'b10010 : bank_b_s2 <= alu_result ;
5'b10011 : bank_b_s3 <= alu_result ;
5'b10100 : bank_b_s4 <= alu_result ;
5'b10101 : bank_b_s5 <= alu_result ;
5'b10110 : bank_b_s6 <= alu_result ;
5'b10111 : bank_b_s7 <= alu_result ;
5'b11000 : bank_b_s8 <= alu_result ;
5'b11001 : bank_b_s9 <= alu_result ;
5'b11010 : bank_b_sa <= alu_result ;
5'b11011 : bank_b_sb <= alu_result ;
5'b11100 : bank_b_sc <= alu_result ;
5'b11101 : bank_b_sd <= alu_result ;
5'b11110 : bank_b_se <= alu_result ;
5'b11111 : bank_b_sf <= alu_result ;
endcase
end
//simulation of scratch pad memory contents
if (spm_enable == 1'b1) begin
case (sy_or_kk)
8'b00000000 : sim_spm00 <= sx;
8'b00000001 : sim_spm01 <= sx;
8'b00000010 : sim_spm02 <= sx;
8'b00000011 : sim_spm03 <= sx;
8'b00000100 : sim_spm04 <= sx;
8'b00000101 : sim_spm05 <= sx;
8'b00000110 : sim_spm06 <= sx;
8'b00000111 : sim_spm07 <= sx;
8'b00001000 : sim_spm08 <= sx;
8'b00001001 : sim_spm09 <= sx;
8'b00001010 : sim_spm0A <= sx;
8'b00001011 : sim_spm0B <= sx;
8'b00001100 : sim_spm0C <= sx;
8'b00001101 : sim_spm0D <= sx;
8'b00001110 : sim_spm0E <= sx;
8'b00001111 : sim_spm0F <= sx;
8'b00010000 : sim_spm10 <= sx;
8'b00010001 : sim_spm11 <= sx;
8'b00010010 : sim_spm12 <= sx;
8'b00010011 : sim_spm13 <= sx;
8'b00010100 : sim_spm14 <= sx;
8'b00010101 : sim_spm15 <= sx;
8'b00010110 : sim_spm16 <= sx;
8'b00010111 : sim_spm17 <= sx;
8'b00011000 : sim_spm18 <= sx;
8'b00011001 : sim_spm19 <= sx;
8'b00011010 : sim_spm1A <= sx;
8'b00011011 : sim_spm1B <= sx;
8'b00011100 : sim_spm1C <= sx;
8'b00011101 : sim_spm1D <= sx;
8'b00011110 : sim_spm1E <= sx;
8'b00011111 : sim_spm1F <= sx;
8'b00100000 : sim_spm20 <= sx;
8'b00100001 : sim_spm21 <= sx;
8'b00100010 : sim_spm22 <= sx;
8'b00100011 : sim_spm23 <= sx;
8'b00100100 : sim_spm24 <= sx;
8'b00100101 : sim_spm25 <= sx;
8'b00100110 : sim_spm26 <= sx;
8'b00100111 : sim_spm27 <= sx;
8'b00101000 : sim_spm28 <= sx;
8'b00101001 : sim_spm29 <= sx;
8'b00101010 : sim_spm2A <= sx;
8'b00101011 : sim_spm2B <= sx;
8'b00101100 : sim_spm2C <= sx;
8'b00101101 : sim_spm2D <= sx;
8'b00101110 : sim_spm2E <= sx;
8'b00101111 : sim_spm2F <= sx;
8'b00110000 : sim_spm30 <= sx;
8'b00110001 : sim_spm31 <= sx;
8'b00110010 : sim_spm32 <= sx;
8'b00110011 : sim_spm33 <= sx;
8'b00110100 : sim_spm34 <= sx;
8'b00110101 : sim_spm35 <= sx;
8'b00110110 : sim_spm36 <= sx;
8'b00110111 : sim_spm37 <= sx;
8'b00111000 : sim_spm38 <= sx;
8'b00111001 : sim_spm39 <= sx;
8'b00111010 : sim_spm3A <= sx;
8'b00111011 : sim_spm3B <= sx;
8'b00111100 : sim_spm3C <= sx;
8'b00111101 : sim_spm3D <= sx;
8'b00111110 : sim_spm3E <= sx;
8'b00111111 : sim_spm3F <= sx;
8'b01000000 : sim_spm40 <= sx;
8'b01000001 : sim_spm41 <= sx;
8'b01000010 : sim_spm42 <= sx;
8'b01000011 : sim_spm43 <= sx;
8'b01000100 : sim_spm44 <= sx;
8'b01000101 : sim_spm45 <= sx;
8'b01000110 : sim_spm46 <= sx;
8'b01000111 : sim_spm47 <= sx;
8'b01001000 : sim_spm48 <= sx;
8'b01001001 : sim_spm49 <= sx;
8'b01001010 : sim_spm4A <= sx;
8'b01001011 : sim_spm4B <= sx;
8'b01001100 : sim_spm4C <= sx;
8'b01001101 : sim_spm4D <= sx;
8'b01001110 : sim_spm4E <= sx;
8'b01001111 : sim_spm4F <= sx;
8'b01010000 : sim_spm50 <= sx;
8'b01010001 : sim_spm51 <= sx;
8'b01010010 : sim_spm52 <= sx;
8'b01010011 : sim_spm53 <= sx;
8'b01010100 : sim_spm54 <= sx;
8'b01010101 : sim_spm55 <= sx;
8'b01010110 : sim_spm56 <= sx;
8'b01010111 : sim_spm57 <= sx;
8'b01011000 : sim_spm58 <= sx;
8'b01011001 : sim_spm59 <= sx;
8'b01011010 : sim_spm5A <= sx;
8'b01011011 : sim_spm5B <= sx;
8'b01011100 : sim_spm5C <= sx;
8'b01011101 : sim_spm5D <= sx;
8'b01011110 : sim_spm5E <= sx;
8'b01011111 : sim_spm5F <= sx;
8'b01100000 : sim_spm60 <= sx;
8'b01100001 : sim_spm61 <= sx;
8'b01100010 : sim_spm62 <= sx;
8'b01100011 : sim_spm63 <= sx;
8'b01100100 : sim_spm64 <= sx;
8'b01100101 : sim_spm65 <= sx;
8'b01100110 : sim_spm66 <= sx;
8'b01100111 : sim_spm67 <= sx;
8'b01101000 : sim_spm68 <= sx;
8'b01101001 : sim_spm69 <= sx;
8'b01101010 : sim_spm6A <= sx;
8'b01101011 : sim_spm6B <= sx;
8'b01101100 : sim_spm6C <= sx;
8'b01101101 : sim_spm6D <= sx;
8'b01101110 : sim_spm6E <= sx;
8'b01101111 : sim_spm6F <= sx;
8'b01110000 : sim_spm70 <= sx;
8'b01110001 : sim_spm71 <= sx;
8'b01110010 : sim_spm72 <= sx;
8'b01110011 : sim_spm73 <= sx;
8'b01110100 : sim_spm74 <= sx;
8'b01110101 : sim_spm75 <= sx;
8'b01110110 : sim_spm76 <= sx;
8'b01110111 : sim_spm77 <= sx;
8'b01111000 : sim_spm78 <= sx;
8'b01111001 : sim_spm79 <= sx;
8'b01111010 : sim_spm7A <= sx;
8'b01111011 : sim_spm7B <= sx;
8'b01111100 : sim_spm7C <= sx;
8'b01111101 : sim_spm7D <= sx;
8'b01111110 : sim_spm7E <= sx;
8'b01111111 : sim_spm7F <= sx;
8'b10000000 : sim_spm80 <= sx;
8'b10000001 : sim_spm81 <= sx;
8'b10000010 : sim_spm82 <= sx;
8'b10000011 : sim_spm83 <= sx;
8'b10000100 : sim_spm84 <= sx;
8'b10000101 : sim_spm85 <= sx;
8'b10000110 : sim_spm86 <= sx;
8'b10000111 : sim_spm87 <= sx;
8'b10001000 : sim_spm88 <= sx;
8'b10001001 : sim_spm89 <= sx;
8'b10001010 : sim_spm8A <= sx;
8'b10001011 : sim_spm8B <= sx;
8'b10001100 : sim_spm8C <= sx;
8'b10001101 : sim_spm8D <= sx;
8'b10001110 : sim_spm8E <= sx;
8'b10001111 : sim_spm8F <= sx;
8'b10010000 : sim_spm90 <= sx;
8'b10010001 : sim_spm91 <= sx;
8'b10010010 : sim_spm92 <= sx;
8'b10010011 : sim_spm93 <= sx;
8'b10010100 : sim_spm94 <= sx;
8'b10010101 : sim_spm95 <= sx;
8'b10010110 : sim_spm96 <= sx;
8'b10010111 : sim_spm97 <= sx;
8'b10011000 : sim_spm98 <= sx;
8'b10011001 : sim_spm99 <= sx;
8'b10011010 : sim_spm9A <= sx;
8'b10011011 : sim_spm9B <= sx;
8'b10011100 : sim_spm9C <= sx;
8'b10011101 : sim_spm9D <= sx;
8'b10011110 : sim_spm9E <= sx;
8'b10011111 : sim_spm9F <= sx;
8'b10100000 : sim_spmA0 <= sx;
8'b10100001 : sim_spmA1 <= sx;
8'b10100010 : sim_spmA2 <= sx;
8'b10100011 : sim_spmA3 <= sx;
8'b10100100 : sim_spmA4 <= sx;
8'b10100101 : sim_spmA5 <= sx;
8'b10100110 : sim_spmA6 <= sx;
8'b10100111 : sim_spmA7 <= sx;
8'b10101000 : sim_spmA8 <= sx;
8'b10101001 : sim_spmA9 <= sx;
8'b10101010 : sim_spmAA <= sx;
8'b10101011 : sim_spmAB <= sx;
8'b10101100 : sim_spmAC <= sx;
8'b10101101 : sim_spmAD <= sx;
8'b10101110 : sim_spmAE <= sx;
8'b10101111 : sim_spmAF <= sx;
8'b10110000 : sim_spmB0 <= sx;
8'b10110001 : sim_spmB1 <= sx;
8'b10110010 : sim_spmB2 <= sx;
8'b10110011 : sim_spmB3 <= sx;
8'b10110100 : sim_spmB4 <= sx;
8'b10110101 : sim_spmB5 <= sx;
8'b10110110 : sim_spmB6 <= sx;
8'b10110111 : sim_spmB7 <= sx;
8'b10111000 : sim_spmB8 <= sx;
8'b10111001 : sim_spmB9 <= sx;
8'b10111010 : sim_spmBA <= sx;
8'b10111011 : sim_spmBB <= sx;
8'b10111100 : sim_spmBC <= sx;
8'b10111101 : sim_spmBD <= sx;
8'b10111110 : sim_spmBE <= sx;
8'b10111111 : sim_spmBF <= sx;
8'b11000000 : sim_spmC0 <= sx;
8'b11000001 : sim_spmC1 <= sx;
8'b11000010 : sim_spmC2 <= sx;
8'b11000011 : sim_spmC3 <= sx;
8'b11000100 : sim_spmC4 <= sx;
8'b11000101 : sim_spmC5 <= sx;
8'b11000110 : sim_spmC6 <= sx;
8'b11000111 : sim_spmC7 <= sx;
8'b11001000 : sim_spmC8 <= sx;
8'b11001001 : sim_spmC9 <= sx;
8'b11001010 : sim_spmCA <= sx;
8'b11001011 : sim_spmCB <= sx;
8'b11001100 : sim_spmCC <= sx;
8'b11001101 : sim_spmCD <= sx;
8'b11001110 : sim_spmCE <= sx;
8'b11001111 : sim_spmCF <= sx;
8'b11010000 : sim_spmD0 <= sx;
8'b11010001 : sim_spmD1 <= sx;
8'b11010010 : sim_spmD2 <= sx;
8'b11010011 : sim_spmD3 <= sx;
8'b11010100 : sim_spmD4 <= sx;
8'b11010101 : sim_spmD5 <= sx;
8'b11010110 : sim_spmD6 <= sx;
8'b11010111 : sim_spmD7 <= sx;
8'b11011000 : sim_spmD8 <= sx;
8'b11011001 : sim_spmD9 <= sx;
8'b11011010 : sim_spmDA <= sx;
8'b11011011 : sim_spmDB <= sx;
8'b11011100 : sim_spmDC <= sx;
8'b11011101 : sim_spmDD <= sx;
8'b11011110 : sim_spmDE <= sx;
8'b11011111 : sim_spmDF <= sx;
8'b11100000 : sim_spmE0 <= sx;
8'b11100001 : sim_spmE1 <= sx;
8'b11100010 : sim_spmE2 <= sx;
8'b11100011 : sim_spmE3 <= sx;
8'b11100100 : sim_spmE4 <= sx;
8'b11100101 : sim_spmE5 <= sx;
8'b11100110 : sim_spmE6 <= sx;
8'b11100111 : sim_spmE7 <= sx;
8'b11101000 : sim_spmE8 <= sx;
8'b11101001 : sim_spmE9 <= sx;
8'b11101010 : sim_spmEA <= sx;
8'b11101011 : sim_spmEB <= sx;
8'b11101100 : sim_spmEC <= sx;
8'b11101101 : sim_spmED <= sx;
8'b11101110 : sim_spmEE <= sx;
8'b11101111 : sim_spmEF <= sx;
8'b11110000 : sim_spmF0 <= sx;
8'b11110001 : sim_spmF1 <= sx;
8'b11110010 : sim_spmF2 <= sx;
8'b11110011 : sim_spmF3 <= sx;
8'b11110100 : sim_spmF4 <= sx;
8'b11110101 : sim_spmF5 <= sx;
8'b11110110 : sim_spmF6 <= sx;
8'b11110111 : sim_spmF7 <= sx;
8'b11111000 : sim_spmF8 <= sx;
8'b11111001 : sim_spmF9 <= sx;
8'b11111010 : sim_spmFA <= sx;
8'b11111011 : sim_spmFB <= sx;
8'b11111100 : sim_spmFC <= sx;
8'b11111101 : sim_spmFD <= sx;
8'b11111110 : sim_spmFE <= sx;
8'b11111111 : sim_spmFF <= sx;
endcase
end
end
//
// Assignment of internal register variables to active registers
//
if (bank == 1'b0) begin
kcpsm6_status[1:16] <= "A,";
sim_s0 <= bank_a_s0 ;
sim_s1 <= bank_a_s1 ;
sim_s2 <= bank_a_s2 ;
sim_s3 <= bank_a_s3 ;
sim_s4 <= bank_a_s4 ;
sim_s5 <= bank_a_s5 ;
sim_s6 <= bank_a_s6 ;
sim_s7 <= bank_a_s7 ;
sim_s8 <= bank_a_s8 ;
sim_s9 <= bank_a_s9 ;
sim_sA <= bank_a_sa ;
sim_sB <= bank_a_sb ;
sim_sC <= bank_a_sc ;
sim_sD <= bank_a_sd ;
sim_sE <= bank_a_se ;
sim_sF <= bank_a_sf ;
end
else begin
kcpsm6_status[1:16] <= "B,";
sim_s0 <= bank_b_s0 ;
sim_s1 <= bank_b_s1 ;
sim_s2 <= bank_b_s2 ;
sim_s3 <= bank_b_s3 ;
sim_s4 <= bank_b_s4 ;
sim_s5 <= bank_b_s5 ;
sim_s6 <= bank_b_s6 ;
sim_s7 <= bank_b_s7 ;
sim_s8 <= bank_b_s8 ;
sim_s9 <= bank_b_s9 ;
sim_sA <= bank_b_sa ;
sim_sB <= bank_b_sb ;
sim_sC <= bank_b_sc ;
sim_sD <= bank_b_sd ;
sim_sE <= bank_b_se ;
sim_sF <= bank_b_sf ;
end
//
//
end //process simulation;
//synthesis translate_on
//
// **************************
// * End of simulation code *
// **************************
//
//
///////////////////////////////////////////////////////////////////////////////////////////
//
endmodule
//
///////////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE kcpsm6.v
//
///////////////////////////////////////////////////////////////////////////////////////////
|
/****************************************
Decode Unit
****************************************/
`include "core.h"
`default_nettype none
module decoder(
//System
input wire iCLOCK,
input wire inRESET,
//Free
//input wire iFREE_DEFAULT,
input wire iRESET_SYNC,
//Previous
/*
input wire iPREVIOUS_INST_VALID,
input wire iPREVIOUS_FAULT_PAGEFAULT,
input wire iPREVIOUS_FAULT_PRIVILEGE_ERROR,
input wire iPREVIOUS_FAULT_INVALID_INST,
input wire iPREVIOUS_PAGING_ENA,
input wire iPREVIOUS_KERNEL_ACCESS,
input wire iPREVIOUS_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_INST,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
*/
input wire iPREVIOUS_COMMON_VALID,
input wire iPREVIOUS_0_INST_VALID,
input wire iPREVIOUS_0_PAGEFAULT,
input wire iPREVIOUS_0_PAGING_ENA,
input wire iPREVIOUS_0_KERNEL_ACCESS,
input wire iPREVIOUS_0_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_0_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_0_INST,
input wire iPREVIOUS_1_INST_VALID,
input wire iPREVIOUS_1_PAGEFAULT,
input wire iPREVIOUS_1_PAGING_ENA,
input wire iPREVIOUS_1_KERNEL_ACCESS,
input wire iPREVIOUS_1_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_1_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_1_INST,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Next-0
output wire oNEXT_COMMON_VALID,
output wire oNEXT_0_VALID,
output wire oNEXT_0_FAULT_PAGEFAULT,
output wire oNEXT_0_FAULT_PRIVILEGE_ERROR,
output wire oNEXT_0_FAULT_INVALID_INST,
output wire oNEXT_0_PAGING_ENA,
output wire oNEXT_0_KERNEL_ACCESS,
output wire oNEXT_0_BRANCH_PREDICT,
output wire [31:0] oNEXT_0_BRANCH_PREDICT_ADDR,
output wire oNEXT_0_SOURCE0_ACTIVE,
output wire oNEXT_0_SOURCE1_ACTIVE,
output wire oNEXT_0_SOURCE0_SYSREG,
output wire oNEXT_0_SOURCE1_SYSREG,
output wire oNEXT_0_SOURCE0_SYSREG_RENAME,
output wire oNEXT_0_SOURCE1_SYSREG_RENAME,
output wire oNEXT_0_ADV_ACTIVE, //++
output wire oNEXT_0_DESTINATION_SYSREG,
output wire oNEXT_0_DEST_RENAME,
output wire oNEXT_0_WRITEBACK,
output wire oNEXT_0_FLAGS_WRITEBACK,
output wire oNEXT_0_FRONT_COMMIT_WAIT,
output wire [4:0] oNEXT_0_CMD,
output wire [3:0] oNEXT_0_CC_AFE,
output wire [4:0] oNEXT_0_SOURCE0,
output wire [31:0] oNEXT_0_SOURCE1,
output wire [5:0] oNEXT_0_ADV_DATA, //++
output wire oNEXT_0_SOURCE0_FLAGS,
output wire oNEXT_0_SOURCE1_IMM,
output wire [4:0] oNEXT_0_DESTINATION,
output wire oNEXT_0_EX_SYS_REG,
output wire oNEXT_0_EX_SYS_LDST,
output wire oNEXT_0_EX_LOGIC,
output wire oNEXT_0_EX_SHIFT,
output wire oNEXT_0_EX_ADDER,
output wire oNEXT_0_EX_MUL,
output wire oNEXT_0_EX_SDIV,
output wire oNEXT_0_EX_UDIV,
output wire oNEXT_0_EX_LDST,
output wire oNEXT_0_EX_BRANCH,
output wire oNEXT_1_VALID,
output wire oNEXT_1_FAULT_PAGEFAULT,
output wire oNEXT_1_FAULT_PRIVILEGE_ERROR,
output wire oNEXT_1_FAULT_INVALID_INST,
output wire oNEXT_1_PAGING_ENA,
output wire oNEXT_1_KERNEL_ACCESS,
output wire oNEXT_1_BRANCH_PREDICT,
output wire [31:0] oNEXT_1_BRANCH_PREDICT_ADDR,
output wire oNEXT_1_SOURCE0_ACTIVE,
output wire oNEXT_1_SOURCE1_ACTIVE,
output wire oNEXT_1_SOURCE0_SYSREG,
output wire oNEXT_1_SOURCE1_SYSREG,
output wire oNEXT_1_SOURCE0_SYSREG_RENAME,
output wire oNEXT_1_SOURCE1_SYSREG_RENAME,
output wire oNEXT_1_ADV_ACTIVE, //++
output wire oNEXT_1_DESTINATION_SYSREG,
output wire oNEXT_1_DEST_RENAME,
output wire oNEXT_1_WRITEBACK,
output wire oNEXT_1_FLAGS_WRITEBACK,
output wire oNEXT_1_FRONT_COMMIT_WAIT,
output wire [4:0] oNEXT_1_CMD,
output wire [3:0] oNEXT_1_CC_AFE,
output wire [4:0] oNEXT_1_SOURCE0,
output wire [31:0] oNEXT_1_SOURCE1,
output wire [5:0] oNEXT_1_ADV_DATA, //++
output wire oNEXT_1_SOURCE0_FLAGS,
output wire oNEXT_1_SOURCE1_IMM,
output wire [4:0] oNEXT_1_DESTINATION,
output wire oNEXT_1_EX_SYS_REG,
output wire oNEXT_1_EX_SYS_LDST,
output wire oNEXT_1_EX_LOGIC,
output wire oNEXT_1_EX_SHIFT,
output wire oNEXT_1_EX_ADDER,
output wire oNEXT_1_EX_MUL,
output wire oNEXT_1_EX_SDIV,
output wire oNEXT_1_EX_UDIV,
output wire oNEXT_1_EX_LDST,
output wire oNEXT_1_EX_BRANCH,
output wire [31:0] oNEXT_PC,
input wire iNEXT_LOCK
);
wire decode_0_source0_active;
wire decode_0_source1_active;
wire decode_0_source0_sysreg;
wire decode_0_source1_sysreg;
wire decode_0_source0_sysreg_rename;
wire decode_0_source1_sysreg_rename;
wire decode_0_adv_active;
wire decode_0_destination_sysreg;
wire decode_0_dest_rename;
wire decode_0_writeback;
wire decode_0_flags_writeback;
wire decode_0_front_commit_wait;
wire [4:0] decode_0_cmd;
wire [3:0] decode_0_cc_afe;
wire [4:0] decode_0_source0;
wire [31:0] decode_0_source1;
wire [5:0] decode_0_adv_data;
wire decode_0_source0_flags;
wire decode_0_source1_imm;
wire [4:0] decode_0_destination;
wire decode_0_ex_sys_reg;
wire decode_0_ex_sys_ldst;
wire decode_0_ex_logic;
wire decode_0_ex_shift;
wire decode_0_ex_adder;
wire decode_0_ex_mul;
wire decode_0_ex_sdiv;
wire decode_0_ex_udiv;
wire decode_0_ex_ldst;
wire decode_0_ex_branch;
wire decode_1_source0_active;
wire decode_1_source1_active;
wire decode_1_source0_sysreg;
wire decode_1_source1_sysreg;
wire decode_1_source0_sysreg_rename;
wire decode_1_source1_sysreg_rename;
wire decode_1_adv_active;
wire decode_1_destination_sysreg;
wire decode_1_dest_rename;
wire decode_1_writeback;
wire decode_1_flags_writeback;
wire decode_1_front_commit_wait;
wire [4:0] decode_1_cmd;
wire [3:0] decode_1_cc_afe;
wire [4:0] decode_1_source0;
wire [31:0] decode_1_source1;
wire [5:0] decode_1_adv_data;
wire decode_1_source0_flags;
wire decode_1_source1_imm;
wire [4:0] decode_1_destination;
wire decode_1_ex_sys_reg;
wire decode_1_ex_sys_ldst;
wire decode_1_ex_logic;
wire decode_1_ex_shift;
wire decode_1_ex_adder;
wire decode_1_ex_mul;
wire decode_1_ex_sdiv;
wire decode_1_ex_udiv;
wire decode_1_ex_ldst;
wire decode_1_ex_branch;
//synthesis translate_off
wire decode_0_error;
wire decode_1_error;
//synthesis translate_on
/****************************************
Auth & MMU Check
****************************************/
wire instcheck_0_mmu_irq40;
wire instcheck_0_mmu_irq41;
wire instcheck_0_mmu_irq42;
wire instcheck_0_auth_irq41;
wire instcheck_1_mmu_irq40;
wire instcheck_1_mmu_irq41;
wire instcheck_1_mmu_irq42;
wire instcheck_1_auth_irq41;
/*
decode_mmucheck MMUCHECK_PIPE0(
.iPAGING_ENA(),
.iKERNEL_ACCESS(),
.iMMU_FLAGS(),
.oIRQ40(instcheck_0_mmu_irq40),
.oIRQ41(instcheck_0_mmu_irq41),
.oIRQ42(instcheck_0_mmu_irq42)
);
decode_authcheck AUCHCHECK_PIPE0(
.iINSTRUCTION(iPREVIOUS_0_INST),
.iKERNEL_ACCESS(),
.iMMU_FLAGS(),
.oIRQ41(instcheck_0_auth_irq41)
);
*/
assign instcheck_0_mmu_irq40 = 1'b0;
assign instcheck_0_mmu_irq41 = 1'b0;
assign instcheck_0_mmu_irq42 = 1'b0;
assign instcheck_0_auth_irq41 = 1'b0;
assign instcheck_1_mmu_irq40 = 1'b0;
assign instcheck_1_mmu_irq41 = 1'b0;
assign instcheck_1_mmu_irq42 = 1'b0;
assign instcheck_1_auth_irq41 = 1'b0;
/****************************************
Instruction Decode
****************************************/
decode_function DECODE_FUNCTION0(
//Input
.iINSTLUCTION(iPREVIOUS_0_INST),
//Info
.oINF_ERROR(decode_0_error),
//Decode
.oDECODE_SOURCE0_ACTIVE(decode_0_source0_active),
.oDECODE_SOURCE1_ACTIVE(decode_0_source1_active),
.oDECODE_SOURCE0_SYSREG(decode_0_source0_sysreg),
.oDECODE_SOURCE1_SYSREG(decode_0_source1_sysreg),
.oDECODE_SOURCE0_SYSREG_RENAME(decode_0_source0_sysreg_rename),
.oDECODE_SOURCE1_SYSREG_RENAME(decode_0_source1_sysreg_rename),
.oDECODE_ADV_ACTIVE(decode_0_adv_active),
.oDECODE_DESTINATION_SYSREG(decode_0_destination_sysreg),
.oDECODE_DEST_RENAME(decode_0_dest_rename),
.oDECODE_WRITEBACK(decode_0_writeback),
.oDECODE_FLAGS_WRITEBACK(decode_0_flags_writeback),
.oDECODE_FRONT_COMMIT_WAIT(decode_0_front_commit_wait), //???
.oDECODE_CMD(decode_0_cmd),
.oDECODE_CC_AFE(decode_0_cc_afe),
.oDECODE_SOURCE0(decode_0_source0),
.oDECODE_SOURCE1(decode_0_source1),
.oDECODE_ADV_DATA(decode_0_adv_data),
.oDECODE_SOURCE0_FLAGS(decode_0_source0_flags),
.oDECODE_SOURCE1_IMM(decode_0_source1_imm),
.oDECODE_DESTINATION(decode_0_destination),
.oDECODE_EX_SYS_REG(decode_0_ex_sys_reg),
.oDECODE_EX_SYS_LDST(decode_0_ex_sys_ldst),
.oDECODE_EX_LOGIC(decode_0_ex_logic),
.oDECODE_EX_SHIFT(decode_0_ex_shift),
.oDECODE_EX_ADDER(decode_0_ex_adder),
.oDECODE_EX_MUL(decode_0_ex_mul),
.oDECODE_EX_SDIV(decode_0_ex_sdiv),
.oDECODE_EX_UDIV(decode_0_ex_udiv),
.oDECODE_EX_LDST(decode_0_ex_ldst),
.oDECODE_EX_BRANCH(decode_0_ex_branch)
);
decode_function DECODE_FUNCTION1(
//Input
.iINSTLUCTION(iPREVIOUS_1_INST),
//Info
.oINF_ERROR(decode_1_error),
//Decode
.oDECODE_SOURCE0_ACTIVE(decode_1_source0_active),
.oDECODE_SOURCE1_ACTIVE(decode_1_source1_active),
.oDECODE_SOURCE0_SYSREG(decode_1_source0_sysreg),
.oDECODE_SOURCE1_SYSREG(decode_1_source1_sysreg),
.oDECODE_SOURCE0_SYSREG_RENAME(decode_1_source0_sysreg_rename),
.oDECODE_SOURCE1_SYSREG_RENAME(decode_1_source1_sysreg_rename),
.oDECODE_ADV_ACTIVE(decode_1_adv_active),
.oDECODE_DESTINATION_SYSREG(decode_1_destination_sysreg),
.oDECODE_DEST_RENAME(decode_1_dest_rename),
.oDECODE_WRITEBACK(decode_1_writeback),
.oDECODE_FLAGS_WRITEBACK(decode_1_flags_writeback),
.oDECODE_FRONT_COMMIT_WAIT(decode_1_front_commit_wait), //???
.oDECODE_CMD(decode_1_cmd),
.oDECODE_CC_AFE(decode_1_cc_afe),
.oDECODE_SOURCE0(decode_1_source0),
.oDECODE_SOURCE1(decode_1_source1),
.oDECODE_ADV_DATA(decode_1_adv_data),
.oDECODE_SOURCE0_FLAGS(decode_1_source0_flags),
.oDECODE_SOURCE1_IMM(decode_1_source1_imm),
.oDECODE_DESTINATION(decode_1_destination),
.oDECODE_EX_SYS_REG(decode_1_ex_sys_reg),
.oDECODE_EX_SYS_LDST(decode_1_ex_sys_ldst),
.oDECODE_EX_LOGIC(decode_1_ex_logic),
.oDECODE_EX_SHIFT(decode_1_ex_shift),
.oDECODE_EX_ADDER(decode_1_ex_adder),
.oDECODE_EX_MUL(decode_1_ex_mul),
.oDECODE_EX_SDIV(decode_1_ex_sdiv),
.oDECODE_EX_UDIV(decode_1_ex_udiv),
.oDECODE_EX_LDST(decode_1_ex_ldst),
.oDECODE_EX_BRANCH(decode_1_ex_branch)
);
/****************************************
Condition
****************************************/
wire stage_reg_system_busy;
wire stage_reg_pipe0_busy;
wire stage_reg_pipe1_busy;
wire latch_busy = stage_reg_system_busy || stage_reg_pipe0_busy || stage_reg_pipe1_busy;
wire latch_enable_condition = iPREVIOUS_COMMON_VALID && !latch_busy;
/****************************************
This -> Next
****************************************/
pipeline_register #(108) PIPELINE_REG_SYSTEM(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//
.iPREV_REQ(latch_enable_condition),
.oPREV_BUSY(stage_reg_system_busy),
.iPREV_DATA(
{
//0-Pipe
instcheck_0_mmu_irq42,
(instcheck_0_mmu_irq41 || instcheck_0_auth_irq41),
(instcheck_0_mmu_irq40 || iPREVIOUS_0_PAGEFAULT),
iPREVIOUS_0_PAGING_ENA,
iPREVIOUS_0_KERNEL_ACCESS,
iPREVIOUS_0_BRANCH_PREDICT,
iPREVIOUS_0_BRANCH_PREDICT_ADDR,
//1-Pipe
instcheck_1_mmu_irq42,
(instcheck_1_mmu_irq41 || instcheck_1_auth_irq41),
(instcheck_1_mmu_irq40 || iPREVIOUS_1_PAGEFAULT),
iPREVIOUS_1_PAGING_ENA,
iPREVIOUS_1_KERNEL_ACCESS,
iPREVIOUS_1_BRANCH_PREDICT,
iPREVIOUS_1_BRANCH_PREDICT_ADDR,
//Program Counter
iPREVIOUS_PC
}
),
//
.oNEXT_REQ(oNEXT_COMMON_VALID),
.iNEXT_BUSY(iNEXT_LOCK),
.oNEXT_DATA(
{
oNEXT_0_FAULT_PAGEFAULT,
oNEXT_0_FAULT_PRIVILEGE_ERROR,
oNEXT_0_FAULT_INVALID_INST,
oNEXT_0_PAGING_ENA,
oNEXT_0_KERNEL_ACCESS,
oNEXT_0_BRANCH_PREDICT,
oNEXT_0_BRANCH_PREDICT_ADDR,
oNEXT_1_FAULT_PAGEFAULT,
oNEXT_1_FAULT_PRIVILEGE_ERROR,
oNEXT_1_FAULT_INVALID_INST,
oNEXT_1_PAGING_ENA,
oNEXT_1_KERNEL_ACCESS,
oNEXT_1_BRANCH_PREDICT,
oNEXT_1_BRANCH_PREDICT_ADDR,
oNEXT_PC
}
)
);
wire nexe_decode_0_valid;
wire nexe_decode_1_valid;
pipeline_register #(82) PIPELINE_REG_PIPE0(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//
.iPREV_REQ(latch_enable_condition),
.oPREV_BUSY(stage_reg_pipe0_busy),
.iPREV_DATA(
{
iPREVIOUS_0_INST_VALID,
decode_0_source0_active,
decode_0_source1_active,
decode_0_source0_sysreg,
decode_0_source1_sysreg,
decode_0_source0_sysreg_rename,
decode_0_source1_sysreg_rename,
decode_0_adv_data,
decode_0_adv_active,
decode_0_destination_sysreg,
decode_0_dest_rename,
decode_0_writeback,
decode_0_flags_writeback,
decode_0_front_commit_wait,
decode_0_cmd,
decode_0_cc_afe,
decode_0_source0,
decode_0_source1,
decode_0_source0_flags,
decode_0_source1_imm,
decode_0_destination,
decode_0_ex_sys_reg,
decode_0_ex_sys_ldst,
decode_0_ex_logic,
decode_0_ex_shift,
decode_0_ex_adder,
decode_0_ex_mul,
decode_0_ex_sdiv,
decode_0_ex_udiv,
decode_0_ex_ldst,
decode_0_ex_branch
}
),
//
.oNEXT_REQ(),
.iNEXT_BUSY(iNEXT_LOCK),
.oNEXT_DATA(
{
nexe_decode_0_valid,//oNEXT_0_VALID,
oNEXT_0_SOURCE0_ACTIVE,
oNEXT_0_SOURCE1_ACTIVE,
oNEXT_0_SOURCE0_SYSREG,
oNEXT_0_SOURCE1_SYSREG,
oNEXT_0_SOURCE0_SYSREG_RENAME,
oNEXT_0_SOURCE1_SYSREG_RENAME,
oNEXT_0_ADV_DATA,
oNEXT_0_ADV_ACTIVE, //++
oNEXT_0_DESTINATION_SYSREG,
oNEXT_0_DEST_RENAME,
oNEXT_0_WRITEBACK,
oNEXT_0_FLAGS_WRITEBACK,
oNEXT_0_FRONT_COMMIT_WAIT,
oNEXT_0_CMD,
oNEXT_0_CC_AFE,
oNEXT_0_SOURCE0,
oNEXT_0_SOURCE1,
oNEXT_0_SOURCE0_FLAGS,
oNEXT_0_SOURCE1_IMM,
oNEXT_0_DESTINATION,
oNEXT_0_EX_SYS_REG,
oNEXT_0_EX_SYS_LDST,
oNEXT_0_EX_LOGIC,
oNEXT_0_EX_SHIFT,
oNEXT_0_EX_ADDER,
oNEXT_0_EX_MUL,
oNEXT_0_EX_SDIV,
oNEXT_0_EX_UDIV,
oNEXT_0_EX_LDST,
oNEXT_0_EX_BRANCH
}
)
);
pipeline_register #(82) PIPELINE_REG_PIPE1(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(iRESET_SYNC),
//
.iPREV_REQ(latch_enable_condition),
.oPREV_BUSY(stage_reg_pipe1_busy),
.iPREV_DATA(
{
iPREVIOUS_1_INST_VALID,
decode_1_source0_active,
decode_1_source1_active,
decode_1_source0_sysreg,
decode_1_source1_sysreg,
decode_1_source0_sysreg_rename,
decode_1_source1_sysreg_rename,
decode_1_adv_data,
decode_1_adv_active,
decode_1_destination_sysreg,
decode_1_dest_rename,
decode_1_writeback,
decode_1_flags_writeback,
decode_1_front_commit_wait,
decode_1_cmd,
decode_1_cc_afe,
decode_1_source0,
decode_1_source1,
decode_1_source0_flags,
decode_1_source1_imm,
decode_1_destination,
decode_1_ex_sys_reg,
decode_1_ex_sys_ldst,
decode_1_ex_logic,
decode_1_ex_shift,
decode_1_ex_adder,
decode_1_ex_mul,
decode_1_ex_sdiv,
decode_1_ex_udiv,
decode_1_ex_ldst,
decode_1_ex_branch
}
),
//
.oNEXT_REQ(),
.iNEXT_BUSY(iNEXT_LOCK),
.oNEXT_DATA(
{
nexe_decode_1_valid,//oNEXT_1_VALID,
oNEXT_1_SOURCE0_ACTIVE,
oNEXT_1_SOURCE1_ACTIVE,
oNEXT_1_SOURCE0_SYSREG,
oNEXT_1_SOURCE1_SYSREG,
oNEXT_1_SOURCE0_SYSREG_RENAME,
oNEXT_1_SOURCE1_SYSREG_RENAME,
oNEXT_1_ADV_DATA,
oNEXT_1_ADV_ACTIVE, //++
oNEXT_1_DESTINATION_SYSREG,
oNEXT_1_DEST_RENAME,
oNEXT_1_WRITEBACK,
oNEXT_1_FLAGS_WRITEBACK,
oNEXT_1_FRONT_COMMIT_WAIT,
oNEXT_1_CMD,
oNEXT_1_CC_AFE,
oNEXT_1_SOURCE0,
oNEXT_1_SOURCE1,
oNEXT_1_SOURCE0_FLAGS,
oNEXT_1_SOURCE1_IMM,
oNEXT_1_DESTINATION,
oNEXT_1_EX_SYS_REG,
oNEXT_1_EX_SYS_LDST,
oNEXT_1_EX_LOGIC,
oNEXT_1_EX_SHIFT,
oNEXT_1_EX_ADDER,
oNEXT_1_EX_MUL,
oNEXT_1_EX_SDIV,
oNEXT_1_EX_UDIV,
oNEXT_1_EX_LDST,
oNEXT_1_EX_BRANCH
}
)
);
assign oNEXT_0_VALID = !iRESET_SYNC && nexe_decode_0_valid;
assign oNEXT_1_VALID = !iRESET_SYNC && nexe_decode_1_valid;
assign oPREVIOUS_LOCK = latch_busy;
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__CLKMUX2_PP_SYMBOL_V
/**
* clkmux2: Clock mux.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkmux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_PP_SYMBOL_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module tiny(clk, reset, sel, addr, w, data, out, done);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [8:0] rom_addr;
wire [27:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select
select0 (sel, addr, fsm_addr, w, ram_a_addr, ram_a_w);
rom
rom0 (clk, rom_addr, rom_q);
FSM
fsm0 (clk, reset, rom_addr, rom_q, fsm_addr, ram_b_addr, ram_b_w, pe_ctrl, done);
const_
const0 (clk, ram_a_addr, const0_out, const0_effective),
const1 (clk, ram_b_addr, const1_out, const1_effective);
ram
ram0 (clk, ram_a_w, ram_a_addr, data, ram_a_data_out, ram_b_w, ram_b_addr[5:0], ram_b_data_in, ram_b_data_out);
muxer
muxer0 (ram_a_data_out, const0_out, const0_effective, muxer0_out),
muxer1 (ram_b_data_out, const1_out, const1_effective, muxer1_out);
PE
pe0 (clk, reset, pe_ctrl, muxer1_out, muxer0_out[`WIDTH:0], muxer0_out[`WIDTH:0], ram_b_data_in[`WIDTH:0]);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
module select(sel, addr_in, addr_fsm_in, w_in, addr_out, w_out);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
module muxer(from_ram, from_const, const_effective, out);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
|
module edma (/*AUTOARG*/
// Outputs
mi_dout, edma_access, edma_packet,
// Inputs
reset, clk, mi_en, mi_we, mi_addr, mi_din, edma_wait
);
/******************************/
/*Compile Time Parameters */
/******************************/
parameter RFAW = 6;
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
/******************************/
input reset; //async reset
input clk;
/*****************************/
/*REGISTER INTERFACE */
/*****************************/
input mi_en;
input mi_we;
input [RFAW+1:0] mi_addr;
input [63:0] mi_din;
output [31:0] mi_dout;
/*****************************/
/*DMA TRANSACTION */
/*****************************/
output edma_access;
output [PW-1:0] edma_packet;
input edma_wait;
assign edma_access=1'b0;
assign edma_packet='d0;
assign mi_dout='d0;
/*
//registers
reg [AW-1:0] edma_srcaddr_reg;
reg [AW-1:0] edma_dstaddr_reg;
reg [AW-1:0] edma_count_reg;
reg [AW-1:0] edma_stride_reg;
reg [8:0] edma_cfg_reg;
reg [1:0] edma_status_reg;
reg [31:0] mi_dout;
//wires
wire edma_write;
wire edma_read;
wire edma_cfg_write ;
wire edma_srcaddr_write;
wire edma_dstaddr_write;
wire edma_stride_write;
wire edma_count_write;
wire edma_message;
wire edma_expired;
wire edma_last_tran;
wire edma_error;
wire edma_enable;
//read/write decode
assign edma_write = mi_en & mi_we;
assign edma_read = mi_en & ~mi_we;
//DMA configuration
assign edma_cfg_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACFG);
assign edma_srcaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASRCADDR);
assign edma_dstaddr_write = edma_write & (mi_addr[RFAW+1:2]==`EDMADSTADDR);
assign edma_count_write = edma_write & (mi_addr[RFAW+1:2]==`EDMACOUNT);
assign edma_stride_write = edma_write & (mi_addr[RFAW+1:2]==`EDMASTRIDE);
//###########################
//# DMACFG
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_cfg_reg[8:0] <= 'd0;
else if (edma_cfg_write)
edma_cfg_reg[8:0] <= mi_din[8:0];
assign edma_enable = edma_cfg_reg[0]; //should be zero
assign edma_message = edma_cfg_reg[8];
assign edma_access = edma_enable & ~edma_expired;
assign edma_write = edma_cfg_reg[1]; //only 1 for test pattern
assign edma_datamode[1:0] = edma_cfg_reg[3:2];
assign edma_ctrlmode[3:0] = (edma_message & edma_last_tran) ? 4'b1100 : edma_cfg_reg[7:4];
//###########################
//# DMASTATUS
//###########################
//Misalignment
assign edma_error = ((edma_srcaddr_reg[0] | edma_dstaddr_reg[0]) & (edma_datamode[1:0]!=2'b00)) | //16/32/64
((edma_srcaddr_reg[1] | edma_dstaddr_reg[1]) & (edma_datamode[1])) | //32/64
((edma_srcaddr_reg[2] | edma_dstaddr_reg[2]) & (edma_datamode[1:0]==2'b11)); //64
always @ (posedge clk or posedge reset)
if(reset)
edma_status_reg[1:0] <= 'd0;
else if (edma_cfg_write)
edma_status_reg[1:0] <= mi_din[1:0];
else if (edma_enable)
begin
edma_status_reg[0] <= edma_enable & ~edma_expired;//dma busy
edma_status_reg[1] <= edma_status_reg[1] | (edma_enable & edma_error);
end
//###########################
//# EDMASRCADDR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_srcaddr_reg[AW-1:0] <= 'd0;
else if (edma_srcaddr_write)
edma_srcaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_srcaddr_reg[AW-1:0] <= edma_srcaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_srcaddr[31:0] = edma_srcaddr_reg[31:0];
//###########################
//# EDMADSTADR
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_dstaddr_reg[AW-1:0] <= 'd0;
else if (edma_dstaddr_write)
edma_dstaddr_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_dstaddr_reg[AW-1:0] <= edma_dstaddr_reg[AW-1:0] + (1<<edma_datamode[1:0]);
assign edma_dstaddr[31:0] = edma_dstaddr_reg[31:0];
//###########################
//# EDMACOUNT
//###########################
always @ (posedge clk or posedge reset)
if(reset)
edma_count_reg[AW-1:0] <= 'd0;
else if (edma_count_write)
edma_count_reg[AW-1:0] <= mi_din[AW-1:0];
else if (edma_enable & ~edma_wait)
edma_count_reg[AW-1:0] <= edma_count_reg[AW-1:0] - 1'b1;
assign edma_last_tran = (edma_count_reg[AW-1:0]==32'b1);
assign edma_expired = (edma_count_reg[AW-1:0]==32'b0);
//###########################
//# EDMASTRIDE
//###########################
//NOTE: not supported yet, need to think about feature...
always @ (posedge clk or posedge reset)
if(reset)
edma_stride_reg[AW-1:0] <= 'd0;
else if (edma_stride_write)
edma_stride_reg[AW-1:0] <= mi_din[AW-1:0];
//###########################
//# DUMMY DATA
//###########################
assign edma_data[31:0] = TEST_PATTERN;
//###########################
//# PACKET CREATION
//###########################
emesh2packet e2p (
// Outputs
.packet_out (edma_packet[PW-1:0]),
// Inputs
.access_in (edma_access),
.write_in (edma_write),
.datamode_in (edma_datamode[1:0]),
.ctrlmode_in (edma_ctrlmode[3:0]),
.dstaddr_in (edma_dstaddr[AW-1:0]),
.data_in (edma_data[DW-1:0]),
.srcaddr_in (edma_srcaddr_in[AW-1:0]));
//###############################
//# DATA READBACK MUX
//###############################
//Pipelineing readback
always @ (posedge clk)
if(edma_read)
case(mi_addr[RFAW+1:2])
`EDMACFG: mi_dout[31:0] <= {23'b0, edma_cfg_reg[8:0]};
`EDMASTATUS: mi_dout[31:0] <= {30'b0, edma_status_reg[1:0]};
`EDMASRCADDR:mi_dout[31:0] <= {edma_srcaddr_reg[31:0]};
`EDMADSTADDR:mi_dout[31:0] <= {edma_dstaddr_reg[31:0]};
`EDMACOUNT: mi_dout[31:0] <= {edma_count_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else
begin
default: mi_dout[31:0] <= 32'd0;
end
*/
endmodule // edma
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__TAP_PP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAP_PP_BLACKBOX_V
|
/* verilator lint_off IMPLICIT */
/* verilator lint_off UNDRIVEN */
/* verilator lint_off UNUSED */
/* verilator lint_off UNOPTFLAT */
module psram_axi(MEM_ADDR_OUT, MEM_CEN, MEM_OEN, MEM_WEN, MEM_BEN, MEM_ADV, MEM_CRE
, MEM_DATA_I, MEM_DATA_O, MEM_DATA_T, s00_axi_aclk, s00_axi_aresetn
, s00_axi_awid, s00_axi_awaddr, s00_axi_awlen, s00_axi_awsize, s00_axi_awburst
, s00_axi_awlock, s00_axi_awcache, s00_axi_awprot, s00_axi_awqos
, s00_axi_awregion, s00_axi_awuser, s00_axi_awvalid, s00_axi_awready
, s00_axi_wdata, s00_axi_wstrb, s00_axi_wlast, s00_axi_wuser, s00_axi_wvalid
, s00_axi_wready, s00_axi_bid, s00_axi_bresp, s00_axi_buser, s00_axi_bvalid
, s00_axi_bready, s00_axi_arid, s00_axi_araddr, s00_axi_arlen, s00_axi_arsize
, s00_axi_arburst, s00_axi_arlock, s00_axi_arcache, s00_axi_arprot
, s00_axi_arqos, s00_axi_arregion, s00_axi_aruser, s00_axi_arvalid
, s00_axi_arready, s00_axi_rid, s00_axi_rdata, s00_axi_rresp, s00_axi_rlast
, s00_axi_ruser, s00_axi_rvalid, s00_axi_rready);
output [22:0] MEM_ADDR_OUT;
output MEM_CEN;
output MEM_OEN;
output MEM_WEN;
output [1:0] MEM_BEN;
output MEM_ADV;
output MEM_CRE;
input [15:0] MEM_DATA_I;
output [15:0] MEM_DATA_O;
output [15:0] MEM_DATA_T;
input s00_axi_aclk;
input s00_axi_aresetn;
input [1:0] s00_axi_awid;
input [23:0] s00_axi_awaddr;
input [7:0] s00_axi_awlen;
input [2:0] s00_axi_awsize;
input [1:0] s00_axi_awburst;
input s00_axi_awlock;
input [3:0] s00_axi_awcache;
input [2:0] s00_axi_awprot;
input [3:0] s00_axi_awqos;
input [3:0] s00_axi_awregion;
input [1:0] s00_axi_awuser;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0] s00_axi_wdata;
input [3:0] s00_axi_wstrb;
input s00_axi_wlast;
input [1:0] s00_axi_wuser;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0] s00_axi_bid;
output [1:0] s00_axi_bresp;
output [1:0] s00_axi_buser;
output s00_axi_bvalid;
input s00_axi_bready;
input [1:0] s00_axi_arid;
input [23:0] s00_axi_araddr;
input [7:0] s00_axi_arlen;
input [2:0] s00_axi_arsize;
input [1:0] s00_axi_arburst;
input s00_axi_arlock;
input [3:0] s00_axi_arcache;
input [2:0] s00_axi_arprot;
input [3:0] s00_axi_arqos;
input [3:0] s00_axi_arregion;
input [1:0] s00_axi_aruser;
input s00_axi_arvalid;
output s00_axi_arready;
output [1:0] s00_axi_rid;
output [31:0] s00_axi_rdata;
output [1:0] s00_axi_rresp;
output s00_axi_rlast;
output [1:0] s00_axi_ruser;
output s00_axi_rvalid;
input s00_axi_rready;
wire [8:0] i_psram_sub_AsyncPSRAMinst_ce_cycle_counter;
wire [6:0] i_psram_sub_AsyncPSRAMinst_waitcount;
wire [18:0] i_psram_sub_AsyncPSRAMinst_last_page_read;
wire [1:0] i_psram_sub_AsyncPSRAMinst_state;
wire [6:0] i_psram_sub_AsyncPSRAMinst_cycle_time;
wire [1:0] i_psram_sub_mem_byte_en;
wire [22:0] i_psram_sub_mem_addr;
wire [23:0] i_psram_sub_axi_awaddr;
wire [23:0] i_psram_sub_axi_araddr;
wire [15:0] i_psram_sub_mem_data_wr;
wire [23:0] i_psram_sub_function_sub;
wire [23:0] i_psram_sub_function_sub_0;
wire [22:0] i_psram_sub_function_plus_2;
wire [7:0] i_psram_sub_axi_awlen;
wire [7:0] i_psram_sub_axi_awlen_cntr;
wire [7:0] i_psram_sub_axi_arlen;
wire [7:0] i_psram_sub_axi_arlen_cntr;
wire [2:0] i_psram_sub_state;
wire [2:0] i_psram_sub_state_5;
wire \MEM_DATA_T[0] ;
assign s00_axi_buser[1] = 1'b0;
assign s00_axi_buser[0] = 1'b0;
assign s00_axi_ruser[1] = 1'b0;
assign s00_axi_ruser[0] = 1'b0;
assign s00_axi_rid[0] = s00_axi_arid[0];
assign s00_axi_rid[1] = s00_axi_arid[1];
assign s00_axi_bid[0] = s00_axi_awid[0];
assign s00_axi_bid[1] = s00_axi_awid[1];
assign MEM_DATA_T[15] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[14] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[13] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[12] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[11] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[10] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[9] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[8] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[7] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[6] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[5] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[4] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[3] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[2] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[1] = \MEM_DATA_T[0] ;
assign MEM_DATA_T[0] = \MEM_DATA_T[0] ;
notech_inv i_02687(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[0]), .Z
(i_psram_sub_AsyncPSRAMinst_n_107));
notech_nand2 i_12686(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[0]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[1]), .Z(n_55));
notech_nand2 i_22685(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[1]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[2]), .Z(n_56));
notech_nand2 i_32684(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[2]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[3]), .Z(n_57));
notech_nand2 i_42683(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[3]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[4]), .Z(n_58));
notech_nand2 i_52682(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[4]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[5]), .Z(n_59));
notech_nand2 i_62681(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[5]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[6]), .Z(n_60));
notech_nand2 i_72680(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[6]),
.B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[7]), .Z(n_61));
notech_inv i_92679(.A(i_psram_sub_AsyncPSRAMinst_n_107), .Z(n_63));
notech_inv i_102678(.A(n_55), .Z(n_100));
notech_nor2 i_112677(.A(i_psram_sub_AsyncPSRAMinst_n_107), .B(n_56), .Z(n_65
));
notech_nor2 i_122676(.A(n_55), .B(n_57), .Z(n_66));
notech_nor2 i_132675(.A(n_56), .B(n_58), .Z(n_67));
notech_nor2 i_142674(.A(n_57), .B(n_59), .Z(n_68));
notech_nor2 i_152673(.A(n_58), .B(n_60), .Z(n_69));
notech_nor2 i_162672(.A(n_59), .B(n_61), .Z(n_70));
notech_nand2 i_222671(.A(n_63), .B(n_67), .Z(n_76));
notech_nand2 i_232670(.A(n_100), .B(n_68), .Z(n_77));
notech_nand2 i_242669(.A(n_65), .B(n_69), .Z(n_78));
notech_nand2 i_252668(.A(n_66), .B(n_70), .Z(n_79));
notech_inv i_312667(.A(n_76), .Z(n_85));
notech_inv i_322666(.A(n_77), .Z(n_86));
notech_inv i_332665(.A(n_78), .Z(n_87));
notech_inv i_342664(.A(n_79), .Z(n_108));
notech_xor2 i_372663(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[1]),
.B(n_63), .Z(i_psram_sub_AsyncPSRAMinst_n_108));
notech_xor2 i_382662(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[2]),
.B(n_100), .Z(i_psram_sub_AsyncPSRAMinst_n_109));
notech_xor2 i_392661(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[3]),
.B(n_65), .Z(i_psram_sub_AsyncPSRAMinst_n_110));
notech_xor2 i_402660(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[4]),
.B(n_66), .Z(i_psram_sub_AsyncPSRAMinst_n_111));
notech_xor2 i_412659(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[5]),
.B(n_85), .Z(i_psram_sub_AsyncPSRAMinst_n_112));
notech_xor2 i_422658(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[6]),
.B(n_86), .Z(i_psram_sub_AsyncPSRAMinst_n_113));
notech_xor2 i_432657(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[7]),
.B(n_87), .Z(i_psram_sub_AsyncPSRAMinst_n_114));
notech_xor2 i_442656(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[8]),
.B(n_108), .Z(i_psram_sub_AsyncPSRAMinst_n_115));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2606(.A(i_psram_sub_command), .Z
(i_psram_sub_AsyncPSRAMinst_n_2970));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2605(.A(MEM_OEN), .Z(\MEM_DATA_T[0]
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2604(.A(MEM_CEN), .Z(i_psram_sub_AsyncPSRAMinst_n_2968
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2603(.A(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_2967
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2602(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[7]), .Z(i_psram_sub_AsyncPSRAMinst_n_2966));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2601(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_2965));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2600(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2964));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2599(.A(MEM_ADDR_OUT[22]), .Z(i_psram_sub_AsyncPSRAMinst_n_2963
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2598(.A(MEM_ADDR_OUT[21]), .Z(i_psram_sub_AsyncPSRAMinst_n_2962
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2597(.A(MEM_ADDR_OUT[20]), .Z(i_psram_sub_AsyncPSRAMinst_n_2961
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2596(.A(MEM_ADDR_OUT[19]), .Z(i_psram_sub_AsyncPSRAMinst_n_2960
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2595(.A(MEM_ADDR_OUT[18]), .Z(i_psram_sub_AsyncPSRAMinst_n_2959
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2594(.A(MEM_ADDR_OUT[17]), .Z(i_psram_sub_AsyncPSRAMinst_n_2958
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2593(.A(MEM_ADDR_OUT[16]), .Z(i_psram_sub_AsyncPSRAMinst_n_2957
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2592(.A(MEM_ADDR_OUT[15]), .Z(i_psram_sub_AsyncPSRAMinst_n_2956
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2591(.A(MEM_ADDR_OUT[14]), .Z(i_psram_sub_AsyncPSRAMinst_n_2955
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2590(.A(MEM_ADDR_OUT[13]), .Z(i_psram_sub_AsyncPSRAMinst_n_2954
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2589(.A(MEM_ADDR_OUT[12]), .Z(i_psram_sub_AsyncPSRAMinst_n_2953
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2588(.A(MEM_ADDR_OUT[11]), .Z(i_psram_sub_AsyncPSRAMinst_n_2952
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2587(.A(MEM_ADDR_OUT[10]), .Z(i_psram_sub_AsyncPSRAMinst_n_2951
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2586(.A(MEM_ADDR_OUT[9]), .Z(i_psram_sub_AsyncPSRAMinst_n_2950
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2585(.A(MEM_ADDR_OUT[8]), .Z(i_psram_sub_AsyncPSRAMinst_n_2949
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2584(.A(MEM_ADDR_OUT[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_2948
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2583(.A(MEM_ADDR_OUT[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2947
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2582(.A(MEM_ADDR_OUT[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_2946
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2581(.A(MEM_ADDR_OUT[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_2945
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2580(.A(MEM_ADDR_OUT[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2944
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2579(.A(MEM_ADDR_OUT[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_2943
));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2578(.A(i_psram_sub_mem_addr[22]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2942));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2577(.A(i_psram_sub_mem_addr[21]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2941));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2576(.A(i_psram_sub_mem_addr[20]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2940));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2575(.A(i_psram_sub_mem_addr[19]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2939));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2574(.A(i_psram_sub_mem_addr[18]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2938));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2573(.A(i_psram_sub_mem_addr[17]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2937));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2572(.A(i_psram_sub_mem_addr[16]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2936));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2571(.A(i_psram_sub_mem_addr[15]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2935));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2570(.A(i_psram_sub_mem_addr[14]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2934));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2569(.A(i_psram_sub_mem_addr[13]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2933));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2568(.A(i_psram_sub_mem_addr[12]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2932));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2567(.A(i_psram_sub_mem_addr[11]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2931));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2566(.A(i_psram_sub_mem_addr[10]
), .Z(i_psram_sub_AsyncPSRAMinst_n_2930));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2565(.A(i_psram_sub_mem_addr[9])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2929));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2564(.A(i_psram_sub_mem_addr[8])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2928));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2563(.A(i_psram_sub_mem_addr[6])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2927));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2562(.A(i_psram_sub_mem_addr[5])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2926));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2561(.A(i_psram_sub_mem_addr[3])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2925));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2560(.A(i_psram_sub_mem_addr[2])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2924));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2559(.A(i_psram_sub_mem_addr[1])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2923));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2558(.A(i_psram_sub_mem_addr[0])
, .Z(i_psram_sub_AsyncPSRAMinst_n_2922));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2557(.A(i_psram_sub_AsyncPSRAMinst_cen_old
), .Z(i_psram_sub_AsyncPSRAMinst_n_2921));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2556(.A(i_psram_sub_AsyncPSRAMinst_state
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2920));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2555(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_2919));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2554(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2918));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2553(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_2917));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2552(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_2916));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2551(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_2915));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2550(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2914));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2549(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_2913));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2548(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_2912));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2547(.A(i_psram_sub_AsyncPSRAMinst_n_549
), .Z(i_psram_sub_AsyncPSRAMinst_n_2911));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2546(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2910));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2545(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_2909));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2544(.A(i_psram_sub_AsyncPSRAMinst_n_539
), .Z(i_psram_sub_AsyncPSRAMinst_n_2908));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2543(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_2907));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2542(.A(i_psram_sub_AsyncPSRAMinst_n_534
), .Z(i_psram_sub_AsyncPSRAMinst_n_2906));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2541(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_2905));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2540(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2904));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2539(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[16]), .Z(i_psram_sub_AsyncPSRAMinst_n_2903));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2538(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[15]), .Z(i_psram_sub_AsyncPSRAMinst_n_2902));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2537(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[11]), .Z(i_psram_sub_AsyncPSRAMinst_n_2901));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2536(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[10]), .Z(i_psram_sub_AsyncPSRAMinst_n_2900));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2535(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .Z(i_psram_sub_AsyncPSRAMinst_n_2899));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2534(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_2898));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2533(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2897));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2532(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2896));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2531(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_2895));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2530(.A(i_psram_sub_AsyncPSRAMinst_n_791
), .Z(i_psram_sub_AsyncPSRAMinst_n_2894));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2529(.A(i_psram_sub_AsyncPSRAMinst_n_786
), .Z(i_psram_sub_AsyncPSRAMinst_n_2893));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2528(.A(i_psram_sub_AsyncPSRAMinst_n_781
), .Z(i_psram_sub_AsyncPSRAMinst_n_2892));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2527(.A(i_psram_sub_AsyncPSRAMinst_n_776
), .Z(i_psram_sub_AsyncPSRAMinst_n_2891));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2526(.A(i_psram_sub_AsyncPSRAMinst_n_771
), .Z(i_psram_sub_AsyncPSRAMinst_n_2890));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2525(.A(i_psram_sub_AsyncPSRAMinst_n_766
), .Z(i_psram_sub_AsyncPSRAMinst_n_2889));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2524(.A(i_psram_sub_AsyncPSRAMinst_n_761
), .Z(i_psram_sub_AsyncPSRAMinst_n_2888));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2523(.A(i_psram_sub_AsyncPSRAMinst_n_756
), .Z(i_psram_sub_AsyncPSRAMinst_n_2887));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2522(.A(i_psram_sub_AsyncPSRAMinst_n_751
), .Z(i_psram_sub_AsyncPSRAMinst_n_2886));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2521(.A(i_psram_sub_AsyncPSRAMinst_n_746
), .Z(i_psram_sub_AsyncPSRAMinst_n_2885));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2520(.A(i_psram_sub_AsyncPSRAMinst_n_741
), .Z(i_psram_sub_AsyncPSRAMinst_n_2884));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2519(.A(i_psram_sub_AsyncPSRAMinst_n_736
), .Z(i_psram_sub_AsyncPSRAMinst_n_2883));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2518(.A(i_psram_sub_AsyncPSRAMinst_n_731
), .Z(i_psram_sub_AsyncPSRAMinst_n_2882));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2517(.A(i_psram_sub_AsyncPSRAMinst_n_726
), .Z(i_psram_sub_AsyncPSRAMinst_n_2881));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2516(.A(i_psram_sub_AsyncPSRAMinst_n_721
), .Z(i_psram_sub_AsyncPSRAMinst_n_2880));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2515(.A(i_psram_sub_AsyncPSRAMinst_n_711
), .Z(i_psram_sub_AsyncPSRAMinst_n_2879));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2514(.A(i_psram_sub_AsyncPSRAMinst_n_706
), .Z(i_psram_sub_AsyncPSRAMinst_n_2878));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2513(.A(i_psram_sub_AsyncPSRAMinst_n_696
), .Z(i_psram_sub_AsyncPSRAMinst_n_2877));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2512(.A(i_psram_sub_AsyncPSRAMinst_n_691
), .Z(i_psram_sub_AsyncPSRAMinst_n_2876));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2511(.A(i_psram_sub_AsyncPSRAMinst_n_686
), .Z(i_psram_sub_AsyncPSRAMinst_n_2875));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2510(.A(i_psram_sub_AsyncPSRAMinst_n_681
), .Z(i_psram_sub_AsyncPSRAMinst_n_2874));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2509(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .Z(i_psram_sub_AsyncPSRAMinst_n_2873));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2508(.A(i_psram_sub_AsyncPSRAMinst_n_508
), .Z(i_psram_sub_AsyncPSRAMinst_n_2872));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2507(.A(i_psram_sub_AsyncPSRAMinst_n_505
), .Z(i_psram_sub_AsyncPSRAMinst_n_2871));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2506(.A(i_psram_sub_AsyncPSRAMinst_n_274
), .Z(i_psram_sub_AsyncPSRAMinst_n_2870));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2505(.A(i_psram_sub_AsyncPSRAMinst_n_642
), .Z(i_psram_sub_AsyncPSRAMinst_n_2869));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2504(.A(i_psram_sub_AsyncPSRAMinst_n_568
), .Z(i_psram_sub_AsyncPSRAMinst_n_2868));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2503(.A(i_psram_sub_AsyncPSRAMinst_n_247
), .Z(i_psram_sub_AsyncPSRAMinst_n_2867));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2502(.A(i_psram_sub_AsyncPSRAMinst_n_559
), .Z(i_psram_sub_AsyncPSRAMinst_n_2866));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2501(.A(i_psram_sub_AsyncPSRAMinst_n_446
), .Z(i_psram_sub_AsyncPSRAMinst_n_2865));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2500(.A(i_psram_sub_AsyncPSRAMinst_n_542
), .Z(i_psram_sub_AsyncPSRAMinst_n_2864));
notech_inv i_psram_sub_AsyncPSRAMinst_i_2499(.A(i_psram_sub_AsyncPSRAMinst_n_637
), .Z(i_psram_sub_AsyncPSRAMinst_n_2863));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_2047(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_BEN[0]), .B(i_psram_sub_AsyncPSRAMinst_n_187), .Z(i_psram_sub_AsyncPSRAMinst_n_2857
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_LBN_reg(.CP(s00_axi_aclk),
.D(i_psram_sub_AsyncPSRAMinst_n_2857), .SD(1'b1), .Q(MEM_BEN[0]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_15(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[15]), .SD(1'b1), .Q(MEM_DATA_O[15]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_14(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[14]), .SD(1'b1), .Q(MEM_DATA_O[14]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_13(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[13]), .SD(1'b1), .Q(MEM_DATA_O[13]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_12(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[12]), .SD(1'b1), .Q(MEM_DATA_O[12]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_11(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[11]), .SD(1'b1), .Q(MEM_DATA_O[11]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_10(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[10]), .SD(1'b1), .Q(MEM_DATA_O[10]
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_9(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[9]), .SD(1'b1), .Q(MEM_DATA_O[9])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_8(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[8]), .SD(1'b1), .Q(MEM_DATA_O[8])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_7(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[7]), .SD(1'b1), .Q(MEM_DATA_O[7])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[6]), .SD(1'b1), .Q(MEM_DATA_O[6])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[5]), .SD(1'b1), .Q(MEM_DATA_O[5])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[4]), .SD(1'b1), .Q(MEM_DATA_O[4])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[3]), .SD(1'b1), .Q(MEM_DATA_O[3])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[2]), .SD(1'b1), .Q(MEM_DATA_O[2])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[1]), .SD(1'b1), .Q(MEM_DATA_O[1])
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_DATA_O_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_mem_data_wr[0]), .SD(1'b1), .Q(MEM_DATA_O[0])
);
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1975(.S(i_psram_sub_AsyncPSRAMinst_n_422
), .A(i_psram_sub_mem_idle), .B(i_psram_sub_AsyncPSRAMinst_n_423
), .Z(i_psram_sub_AsyncPSRAMinst_n_2819));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_idle_reg(.CP(s00_axi_aclk)
, .D(i_psram_sub_AsyncPSRAMinst_n_2819), .SD(1'b1), .Q(i_psram_sub_mem_idle
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_102(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_2867
), .C(i_psram_sub_AsyncPSRAMinst_n_232), .Z(\i_psram_sub_AsyncPSRAMinst_state_3[1]
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1967(.S(i_psram_sub_AsyncPSRAMinst_n_422
), .A(MEM_CRE), .B(i_psram_sub_AsyncPSRAMinst_n_490), .Z(i_psram_sub_AsyncPSRAMinst_n_2813
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_CRE_reg(.CP(s00_axi_aclk),
.D(i_psram_sub_AsyncPSRAMinst_n_2813), .SD(1'b1), .Q(MEM_CRE)
);
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1959(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_BEN[1]), .B(i_psram_sub_AsyncPSRAMinst_n_443), .Z(i_psram_sub_AsyncPSRAMinst_n_2807
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_UBN_reg(.CP(s00_axi_aclk),
.D(i_psram_sub_AsyncPSRAMinst_n_2807), .SD(1'b1), .Q(MEM_BEN[1]
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_100(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_235
), .C(i_psram_sub_AsyncPSRAMinst_n_351), .Z(i_psram_sub_AsyncPSRAMinst_n_187
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1951(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[31] ), .B(i_psram_sub_AsyncPSRAMinst_n_376
), .Z(i_psram_sub_AsyncPSRAMinst_n_2801));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_15(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2801), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[31]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_99(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .Z(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1943(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[30] ), .B(i_psram_sub_AsyncPSRAMinst_n_374
), .Z(i_psram_sub_AsyncPSRAMinst_n_2795));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_14(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2795), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[30]
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_98(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_2919
), .C(i_psram_sub_AsyncPSRAMinst_n_351), .Z(i_psram_sub_AsyncPSRAMinst_n_423
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1935(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[29] ), .B(i_psram_sub_AsyncPSRAMinst_n_373
), .Z(i_psram_sub_AsyncPSRAMinst_n_2789));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_13(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2789), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[29]
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_97(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_238), .C(s00_axi_aresetn),
.Z(i_psram_sub_AsyncPSRAMinst_n_422));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1927(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[28] ), .B(i_psram_sub_AsyncPSRAMinst_n_372
), .Z(i_psram_sub_AsyncPSRAMinst_n_2783));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_12(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2783), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[28]
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_95(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_236
), .C(i_psram_sub_AsyncPSRAMinst_n_351), .Z(i_psram_sub_AsyncPSRAMinst_n_443
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1919(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[27] ), .B(i_psram_sub_AsyncPSRAMinst_n_371
), .Z(i_psram_sub_AsyncPSRAMinst_n_2777));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_11(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2777), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[27]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_93(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_237
), .Z(\i_psram_sub_AsyncPSRAMinst_nbus_19[0] ));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1911(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[26] ), .B(i_psram_sub_AsyncPSRAMinst_n_369
), .Z(i_psram_sub_AsyncPSRAMinst_n_2771));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_10(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2771), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[26]
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_73(.A(i_psram_sub_AsyncPSRAMinst_n_451
), .B(i_psram_sub_AsyncPSRAMinst_state[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_663
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1903(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[25] ), .B(i_psram_sub_AsyncPSRAMinst_n_368
), .Z(i_psram_sub_AsyncPSRAMinst_n_2765));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_9(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2765), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[25]
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_72(.A(i_psram_sub_command), .B(i_psram_sub_AsyncPSRAMinst_n_2919
), .C(i_psram_sub_AsyncPSRAMinst_n_498), .Z(i_psram_sub_AsyncPSRAMinst_n_803
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1895(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[24] ), .B(i_psram_sub_AsyncPSRAMinst_n_367
), .Z(i_psram_sub_AsyncPSRAMinst_n_2759));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_8(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2759), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[24]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_69(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_239), .Z(i_psram_sub_AsyncPSRAMinst_n_194
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1887(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[23] ), .B(i_psram_sub_AsyncPSRAMinst_n_366
), .Z(i_psram_sub_AsyncPSRAMinst_n_2753));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_7(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2753), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[23]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_65(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_240), .Z(i_psram_sub_AsyncPSRAMinst_n_209
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1879(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[22] ), .B(i_psram_sub_AsyncPSRAMinst_n_364
), .Z(i_psram_sub_AsyncPSRAMinst_n_2747));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2747), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[22]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_64(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_241), .Z(i_psram_sub_AsyncPSRAMinst_n_214
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1871(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[21] ), .B(i_psram_sub_AsyncPSRAMinst_n_363
), .Z(i_psram_sub_AsyncPSRAMinst_n_2741));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2741), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[21]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_63(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_242), .Z(i_psram_sub_AsyncPSRAMinst_n_219
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1863(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[20] ), .B(i_psram_sub_AsyncPSRAMinst_n_362
), .Z(i_psram_sub_AsyncPSRAMinst_n_2735));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2735), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[20]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_62(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_243), .Z(i_psram_sub_AsyncPSRAMinst_n_224
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1855(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[19] ), .B(i_psram_sub_AsyncPSRAMinst_n_361
), .Z(i_psram_sub_AsyncPSRAMinst_n_2729));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2729), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[19]
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_61(.A(i_psram_sub_AsyncPSRAMinst_n_379
), .B(i_psram_sub_AsyncPSRAMinst_n_244), .Z(i_psram_sub_AsyncPSRAMinst_n_229
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1847(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[18] ), .B(i_psram_sub_AsyncPSRAMinst_n_359
), .Z(i_psram_sub_AsyncPSRAMinst_n_2723));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2723), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[18]
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_59(.A(i_psram_sub_AsyncPSRAMinst_n_2967
), .B(i_psram_sub_AsyncPSRAMinst_n_383), .C(i_psram_sub_AsyncPSRAMinst_n_382
), .D(i_psram_sub_AsyncPSRAMinst_n_247), .Z(i_psram_sub_AsyncPSRAMinst_n_564
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1839(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[17] ), .B(i_psram_sub_AsyncPSRAMinst_n_358
), .Z(i_psram_sub_AsyncPSRAMinst_n_2717));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2717), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[17]
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_58(.A(i_psram_sub_AsyncPSRAMinst_state
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_2919), .C(i_psram_sub_AsyncPSRAMinst_n_2967
), .D(i_psram_sub_AsyncPSRAMinst_n_2869), .Z(i_psram_sub_AsyncPSRAMinst_n_563
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1831(.S(\i_psram_sub_AsyncPSRAMinst_nbus_19[0]
), .A(\i_psram_sub_axi_rdata_0[16] ), .B(i_psram_sub_AsyncPSRAMinst_n_357
), .Z(i_psram_sub_AsyncPSRAMinst_n_2711));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_data_rd_i_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2711), .SD(1'b1), .Q(\i_psram_sub_axi_rdata_0[16]
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_57(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_2920
), .C(i_psram_sub_AsyncPSRAMinst_n_253), .Z(i_psram_sub_AsyncPSRAMinst_n_473
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1823(.S(i_psram_sub_AsyncPSRAMinst_n_422
), .A(MEM_WEN), .B(i_psram_sub_AsyncPSRAMinst_n_663), .Z(i_psram_sub_AsyncPSRAMinst_n_2705
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_MEM_WEN_reg(.CP(s00_axi_aclk),
.D(i_psram_sub_AsyncPSRAMinst_n_2705), .SD(1'b1), .Q(MEM_WEN)
);
notech_or4 i_psram_sub_AsyncPSRAMinst_i_56(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_cem_time_expired), .C(i_psram_sub_AsyncPSRAMinst_n_2863
), .D(i_psram_sub_AsyncPSRAMinst_n_2970), .Z(i_psram_sub_AsyncPSRAMinst_n_484
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1815(.S(i_psram_sub_AsyncPSRAMinst_n_422
), .A(MEM_OEN), .B(i_psram_sub_AsyncPSRAMinst_n_803), .Z(i_psram_sub_AsyncPSRAMinst_n_2699
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_oen_i_reg(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2699), .SD(1'b1), .Q(MEM_OEN)
);
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_55(.A(i_psram_sub_AsyncPSRAMinst_n_522
), .B(i_psram_sub_AsyncPSRAMinst_n_255), .Z(i_psram_sub_AsyncPSRAMinst_n_519
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1807(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_2899
), .B(i_psram_sub_AsyncPSRAMinst_cem_time_expired), .Z(i_psram_sub_AsyncPSRAMinst_n_2693
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cem_time_expired_reg(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2693), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cem_time_expired
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_54(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_493
), .Z(\i_psram_sub_AsyncPSRAMinst_nbus_15[0] ));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1799(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_381
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[8]), .Z(i_psram_sub_AsyncPSRAMinst_n_2687
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_8(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2687), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[8]));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_53(.A(i_psram_sub_AsyncPSRAMinst_n_258
), .B(i_psram_sub_AsyncPSRAMinst_n_256), .Z(i_psram_sub_AsyncPSRAMinst_n_524
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1791(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_229
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[7]), .Z(i_psram_sub_AsyncPSRAMinst_n_2681
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_7(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2681), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[7]));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_52(.A(i_psram_sub_AsyncPSRAMinst_n_262
), .B(i_psram_sub_AsyncPSRAMinst_n_438), .C(i_psram_sub_AsyncPSRAMinst_n_437
), .Z(i_psram_sub_AsyncPSRAMinst_n_529));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1783(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_224
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_2675
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2675), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[6]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_51(.A(i_psram_sub_AsyncPSRAMinst_n_269
), .B(i_psram_sub_AsyncPSRAMinst_n_2907), .C(i_psram_sub_AsyncPSRAMinst_n_561
), .D(i_psram_sub_AsyncPSRAMinst_n_555), .Z(i_psram_sub_AsyncPSRAMinst_n_534
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1775(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_219
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2669
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2669), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[5]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_50(.A(i_psram_sub_AsyncPSRAMinst_n_278
), .B(i_psram_sub_AsyncPSRAMinst_n_2909), .C(i_psram_sub_AsyncPSRAMinst_n_551
), .D(i_psram_sub_AsyncPSRAMinst_n_553), .Z(i_psram_sub_AsyncPSRAMinst_n_539
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1767(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_214
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_2663
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2663), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[4]));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_49(.A(i_psram_sub_AsyncPSRAMinst_n_450
), .B(i_psram_sub_AsyncPSRAMinst_n_449), .C(i_psram_sub_AsyncPSRAMinst_n_448
), .D(i_psram_sub_AsyncPSRAMinst_n_452), .Z(i_psram_sub_AsyncPSRAMinst_n_544
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1759(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_209
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_2657
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2657), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[3]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_48(.A(i_psram_sub_AsyncPSRAMinst_n_291
), .B(i_psram_sub_AsyncPSRAMinst_n_2912), .C(i_psram_sub_AsyncPSRAMinst_n_516
), .D(i_psram_sub_AsyncPSRAMinst_n_509), .Z(i_psram_sub_AsyncPSRAMinst_n_549
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1751(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_378
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_2651
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2651), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[2]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_26(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2922), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2943), .Z(i_psram_sub_AsyncPSRAMinst_n_681
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1743(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_377
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_2645
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2645), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[1]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_25(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2923), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2944), .Z(i_psram_sub_AsyncPSRAMinst_n_686
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1735(.S(MEM_CEN), .A(i_psram_sub_AsyncPSRAMinst_n_194
), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_2639
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_ce_cycle_counter_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2639), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[0]));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cen_old_reg(.CP(s00_axi_aclk),
.D(MEM_CEN), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cen_old)
);
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_24(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2924), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2945), .Z(i_psram_sub_AsyncPSRAMinst_n_691
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1723(.S(i_psram_sub_AsyncPSRAMinst_n_563
), .A(MEM_CEN), .B(i_psram_sub_AsyncPSRAMinst_n_564), .Z(i_psram_sub_AsyncPSRAMinst_n_2631
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_cen_i_reg(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2631), .SD(1'b1), .Q(MEM_CEN)
);
notech_reg_set i_psram_sub_AsyncPSRAMinst_state_reg_1(.CP(s00_axi_aclk),
.D(\i_psram_sub_AsyncPSRAMinst_state_3[1] ), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_state
[1]));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_1716(.A(i_psram_sub_AsyncPSRAMinst_n_664
), .B(1'b1), .C(i_psram_sub_AsyncPSRAMinst_n_490), .Z(i_psram_sub_AsyncPSRAMinst_n_2628
));
notech_reg_set i_psram_sub_AsyncPSRAMinst_state_reg_0(.CP(s00_axi_aclk),
.D(i_psram_sub_AsyncPSRAMinst_n_2628), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_state
[0]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_23(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2925), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2946), .Z(i_psram_sub_AsyncPSRAMinst_n_696
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_1709(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[6]), .B(i_psram_sub_AsyncPSRAMinst_state[0]), .C(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_2624));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2624), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[6]));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_22(.A(i_psram_sub_AsyncPSRAMinst_n_487
), .B(i_psram_sub_AsyncPSRAMinst_n_486), .C(i_psram_sub_AsyncPSRAMinst_n_490
), .Z(i_psram_sub_AsyncPSRAMinst_n_701));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_1701(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_2618));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2618), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_21(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2926), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2947), .Z(i_psram_sub_AsyncPSRAMinst_n_706
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_1693(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_2612));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2612), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_20(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2927), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2948), .Z(i_psram_sub_AsyncPSRAMinst_n_711
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_1685(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_2606));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2606), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[3]));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_19(.A(i_psram_sub_AsyncPSRAMinst_n_489
), .B(i_psram_sub_AsyncPSRAMinst_n_488), .C(i_psram_sub_AsyncPSRAMinst_n_490
), .Z(i_psram_sub_AsyncPSRAMinst_n_716));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1675(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(i_psram_sub_AsyncPSRAMinst_cycle_time[2]), .B(i_psram_sub_AsyncPSRAMinst_n_484
), .Z(i_psram_sub_AsyncPSRAMinst_n_2597));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2597), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_18(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2928), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2949), .Z(i_psram_sub_AsyncPSRAMinst_n_721
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_1667(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_2914)
, .Z(i_psram_sub_AsyncPSRAMinst_n_2591));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2591), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_17(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2929), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2950), .Z(i_psram_sub_AsyncPSRAMinst_n_726
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1659(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(i_psram_sub_AsyncPSRAMinst_cycle_time[0]), .B(i_psram_sub_AsyncPSRAMinst_n_473
), .Z(i_psram_sub_AsyncPSRAMinst_n_2585));
notech_reg_set i_psram_sub_AsyncPSRAMinst_cycle_time_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2585), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_cycle_time
[0]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_16(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2930), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2951), .Z(i_psram_sub_AsyncPSRAMinst_n_731
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1651(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[6]), .B(i_psram_sub_AsyncPSRAMinst_n_2911
), .Z(i_psram_sub_AsyncPSRAMinst_n_2579));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2579), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[6]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_15(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2931), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2952), .Z(i_psram_sub_AsyncPSRAMinst_n_736
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1643(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[5]), .B(i_psram_sub_AsyncPSRAMinst_n_544
), .Z(i_psram_sub_AsyncPSRAMinst_n_2573));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2573), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[5]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_14(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2932), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2953), .Z(i_psram_sub_AsyncPSRAMinst_n_741
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1635(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[4]), .B(i_psram_sub_AsyncPSRAMinst_n_2908
), .Z(i_psram_sub_AsyncPSRAMinst_n_2567));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2567), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[4]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_13(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2933), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2954), .Z(i_psram_sub_AsyncPSRAMinst_n_746
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1627(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[3]), .B(i_psram_sub_AsyncPSRAMinst_n_2906
), .Z(i_psram_sub_AsyncPSRAMinst_n_2561));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2561), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[3]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_12(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2934), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2955), .Z(i_psram_sub_AsyncPSRAMinst_n_751
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1619(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[2]), .B(i_psram_sub_AsyncPSRAMinst_n_529
), .Z(i_psram_sub_AsyncPSRAMinst_n_2555));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2555), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[2]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_11(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2935), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2956), .Z(i_psram_sub_AsyncPSRAMinst_n_756
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1611(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[1]), .B(i_psram_sub_AsyncPSRAMinst_n_524
), .Z(i_psram_sub_AsyncPSRAMinst_n_2549));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2549), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[1]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_10(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2936), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2957), .Z(i_psram_sub_AsyncPSRAMinst_n_761
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1603(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_waitcount[0]), .B(i_psram_sub_AsyncPSRAMinst_n_519
), .Z(i_psram_sub_AsyncPSRAMinst_n_2543));
notech_reg_set i_psram_sub_AsyncPSRAMinst_waitcount_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2543), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_waitcount
[0]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_9(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2937), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2958), .Z(i_psram_sub_AsyncPSRAMinst_n_766
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1595(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[18]), .B(i_psram_sub_AsyncPSRAMinst_n_485
), .Z(i_psram_sub_AsyncPSRAMinst_n_2537));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_18(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2537), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[18]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_8(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2938), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2959), .Z(i_psram_sub_AsyncPSRAMinst_n_771
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1587(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[17]), .B(i_psram_sub_AsyncPSRAMinst_n_483
), .Z(i_psram_sub_AsyncPSRAMinst_n_2531));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_17(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2531), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[17]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_7(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2939), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2960), .Z(i_psram_sub_AsyncPSRAMinst_n_776
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1579(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[16]), .B(i_psram_sub_AsyncPSRAMinst_n_482
), .Z(i_psram_sub_AsyncPSRAMinst_n_2525));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_16(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2525), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[16]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_6(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2940), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2961), .Z(i_psram_sub_AsyncPSRAMinst_n_781
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1571(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[15]), .B(i_psram_sub_AsyncPSRAMinst_n_481
), .Z(i_psram_sub_AsyncPSRAMinst_n_2519));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_15(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2519), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[15]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_5(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2941), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2962), .Z(i_psram_sub_AsyncPSRAMinst_n_786
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1563(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[14]), .B(i_psram_sub_AsyncPSRAMinst_n_480
), .Z(i_psram_sub_AsyncPSRAMinst_n_2513));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_14(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2513), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[14]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_4(.A(i_psram_sub_AsyncPSRAMinst_n_498
), .B(i_psram_sub_AsyncPSRAMinst_n_2942), .C(i_psram_sub_AsyncPSRAMinst_n_497
), .D(i_psram_sub_AsyncPSRAMinst_n_2963), .Z(i_psram_sub_AsyncPSRAMinst_n_791
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1555(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[13]), .B(i_psram_sub_AsyncPSRAMinst_n_479
), .Z(i_psram_sub_AsyncPSRAMinst_n_2507));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_13(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2507), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[13]));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_3(.A(i_psram_sub_AsyncPSRAMinst_n_348
), .B(i_psram_sub_AsyncPSRAMinst_n_349), .Z(i_psram_sub_AsyncPSRAMinst_n_674
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1547(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[12]), .B(i_psram_sub_AsyncPSRAMinst_n_478
), .Z(i_psram_sub_AsyncPSRAMinst_n_2501));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_12(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2501), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[12]));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_2(.A(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .B(i_psram_sub_AsyncPSRAMinst_n_351), .Z(i_psram_sub_AsyncPSRAMinst_n_673
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1539(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[11]), .B(i_psram_sub_AsyncPSRAMinst_n_477
), .Z(i_psram_sub_AsyncPSRAMinst_n_2495));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_11(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2495), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[11]));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_1(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_352
), .C(i_psram_sub_AsyncPSRAMinst_n_351), .Z(i_psram_sub_AsyncPSRAMinst_n_451
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1531(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[10]), .B(i_psram_sub_AsyncPSRAMinst_n_476
), .Z(i_psram_sub_AsyncPSRAMinst_n_2489));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_10(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2489), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[10]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_400(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_500), .C(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .D(i_psram_sub_AsyncPSRAMinst_n_233), .Z(i_psram_sub_AsyncPSRAMinst_n_664
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1523(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[9]), .B(i_psram_sub_AsyncPSRAMinst_n_475
), .Z(i_psram_sub_AsyncPSRAMinst_n_2483));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_9(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2483), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[9]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1515(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[8]), .B(i_psram_sub_AsyncPSRAMinst_n_474
), .Z(i_psram_sub_AsyncPSRAMinst_n_2477));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_8(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2477), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[8]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1507(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[7]), .B(i_psram_sub_AsyncPSRAMinst_n_472
), .Z(i_psram_sub_AsyncPSRAMinst_n_2471));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_7(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2471), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[7]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1499(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[6]), .B(i_psram_sub_AsyncPSRAMinst_n_471
), .Z(i_psram_sub_AsyncPSRAMinst_n_2465));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2465), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[6]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1491(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[5]), .B(i_psram_sub_AsyncPSRAMinst_n_470
), .Z(i_psram_sub_AsyncPSRAMinst_n_2459));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2459), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[5]));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_121(.A(i_psram_sub_AsyncPSRAMinst_n_657
), .B(i_psram_sub_AsyncPSRAMinst_n_652), .C(i_psram_sub_AsyncPSRAMinst_n_2965
), .D(i_psram_sub_AsyncPSRAMinst_n_2964), .Z(i_psram_sub_AsyncPSRAMinst_n_658
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1483(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[4]), .B(i_psram_sub_AsyncPSRAMinst_n_469
), .Z(i_psram_sub_AsyncPSRAMinst_n_2453));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2453), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[4]));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_426(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[2]), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[1]), .C(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[8]), .D(i_psram_sub_AsyncPSRAMinst_n_2966), .Z(i_psram_sub_AsyncPSRAMinst_n_657
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1475(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[3]), .B(i_psram_sub_AsyncPSRAMinst_n_468
), .Z(i_psram_sub_AsyncPSRAMinst_n_2447));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2447), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[3]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1467(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[2]), .B(i_psram_sub_AsyncPSRAMinst_n_467
), .Z(i_psram_sub_AsyncPSRAMinst_n_2441));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2441), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[2]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1459(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[1]), .B(i_psram_sub_AsyncPSRAMinst_n_466
), .Z(i_psram_sub_AsyncPSRAMinst_n_2435));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2435), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[1]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1451(.S(\i_psram_sub_AsyncPSRAMinst_nbus_15[0]
), .A(i_psram_sub_AsyncPSRAMinst_last_page_read[0]), .B(i_psram_sub_AsyncPSRAMinst_n_465
), .Z(i_psram_sub_AsyncPSRAMinst_n_2429));
notech_reg_set i_psram_sub_AsyncPSRAMinst_last_page_read_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2429), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_last_page_read
[0]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1443(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[22]), .B(i_psram_sub_AsyncPSRAMinst_n_2894),
.Z(i_psram_sub_AsyncPSRAMinst_n_2423));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_22(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2423), .SD(1'b1), .Q(MEM_ADDR_OUT
[22]));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_429(.A(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[3]), .B(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter[0]), .C(i_psram_sub_AsyncPSRAMinst_ce_cycle_counter
[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_652));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1435(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[21]), .B(i_psram_sub_AsyncPSRAMinst_n_2893),
.Z(i_psram_sub_AsyncPSRAMinst_n_2417));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_21(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2417), .SD(1'b1), .Q(MEM_ADDR_OUT
[21]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1427(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[20]), .B(i_psram_sub_AsyncPSRAMinst_n_2892),
.Z(i_psram_sub_AsyncPSRAMinst_n_2411));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_20(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2411), .SD(1'b1), .Q(MEM_ADDR_OUT
[20]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1419(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[19]), .B(i_psram_sub_AsyncPSRAMinst_n_2891),
.Z(i_psram_sub_AsyncPSRAMinst_n_2405));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_19(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2405), .SD(1'b1), .Q(MEM_ADDR_OUT
[19]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1411(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[18]), .B(i_psram_sub_AsyncPSRAMinst_n_2890),
.Z(i_psram_sub_AsyncPSRAMinst_n_2399));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_18(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2399), .SD(1'b1), .Q(MEM_ADDR_OUT
[18]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1403(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[17]), .B(i_psram_sub_AsyncPSRAMinst_n_2889),
.Z(i_psram_sub_AsyncPSRAMinst_n_2393));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_17(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2393), .SD(1'b1), .Q(MEM_ADDR_OUT
[17]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1395(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[16]), .B(i_psram_sub_AsyncPSRAMinst_n_2888),
.Z(i_psram_sub_AsyncPSRAMinst_n_2387));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_16(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2387), .SD(1'b1), .Q(MEM_ADDR_OUT
[16]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1387(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[15]), .B(i_psram_sub_AsyncPSRAMinst_n_2887),
.Z(i_psram_sub_AsyncPSRAMinst_n_2381));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_15(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2381), .SD(1'b1), .Q(MEM_ADDR_OUT
[15]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1379(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[14]), .B(i_psram_sub_AsyncPSRAMinst_n_2886),
.Z(i_psram_sub_AsyncPSRAMinst_n_2375));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_14(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2375), .SD(1'b1), .Q(MEM_ADDR_OUT
[14]));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_133(.A(i_psram_sub_AsyncPSRAMinst_n_386
), .B(i_psram_sub_AsyncPSRAMinst_n_384), .C(i_psram_sub_AsyncPSRAMinst_n_436
), .D(i_psram_sub_AsyncPSRAMinst_n_568), .Z(i_psram_sub_AsyncPSRAMinst_n_642
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1371(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[13]), .B(i_psram_sub_AsyncPSRAMinst_n_2885),
.Z(i_psram_sub_AsyncPSRAMinst_n_2369));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_13(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2369), .SD(1'b1), .Q(MEM_ADDR_OUT
[13]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1363(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[12]), .B(i_psram_sub_AsyncPSRAMinst_n_2884),
.Z(i_psram_sub_AsyncPSRAMinst_n_2363));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_12(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2363), .SD(1'b1), .Q(MEM_ADDR_OUT
[12]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1355(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[11]), .B(i_psram_sub_AsyncPSRAMinst_n_2883),
.Z(i_psram_sub_AsyncPSRAMinst_n_2357));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_11(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2357), .SD(1'b1), .Q(MEM_ADDR_OUT
[11]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1347(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[10]), .B(i_psram_sub_AsyncPSRAMinst_n_2882),
.Z(i_psram_sub_AsyncPSRAMinst_n_2351));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_10(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2351), .SD(1'b1), .Q(MEM_ADDR_OUT
[10]));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_104(.A(i_psram_sub_AsyncPSRAMinst_n_634
), .B(i_psram_sub_AsyncPSRAMinst_n_624), .C(i_psram_sub_AsyncPSRAMinst_n_612
), .D(i_psram_sub_AsyncPSRAMinst_n_601), .Z(i_psram_sub_AsyncPSRAMinst_n_637
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1339(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[9]), .B(i_psram_sub_AsyncPSRAMinst_n_2881), .Z
(i_psram_sub_AsyncPSRAMinst_n_2345));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_9(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2345), .SD(1'b1), .Q(MEM_ADDR_OUT
[9]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1331(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[8]), .B(i_psram_sub_AsyncPSRAMinst_n_2880), .Z
(i_psram_sub_AsyncPSRAMinst_n_2339));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_8(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2339), .SD(1'b1), .Q(MEM_ADDR_OUT
[8]));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_447(.A(i_psram_sub_AsyncPSRAMinst_page_valid
), .B(i_psram_sub_AsyncPSRAMinst_n_631), .C(i_psram_sub_AsyncPSRAMinst_n_387
), .D(i_psram_sub_AsyncPSRAMinst_n_629), .Z(i_psram_sub_AsyncPSRAMinst_n_634
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1323(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[7]), .B(i_psram_sub_AsyncPSRAMinst_n_716), .Z
(i_psram_sub_AsyncPSRAMinst_n_2333));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_7(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2333), .SD(1'b1), .Q(MEM_ADDR_OUT
[7]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1315(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[6]), .B(i_psram_sub_AsyncPSRAMinst_n_2879), .Z
(i_psram_sub_AsyncPSRAMinst_n_2327));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_6(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2327), .SD(1'b1), .Q(MEM_ADDR_OUT
[6]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1307(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[5]), .B(i_psram_sub_AsyncPSRAMinst_n_2878), .Z
(i_psram_sub_AsyncPSRAMinst_n_2321));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_5(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2321), .SD(1'b1), .Q(MEM_ADDR_OUT
[5]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_441(.A(i_psram_sub_mem_addr[4]),
.B(i_psram_sub_AsyncPSRAMinst_n_2895), .C(i_psram_sub_AsyncPSRAMinst_n_2926
), .D(i_psram_sub_AsyncPSRAMinst_last_page_read[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_631
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1299(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[4]), .B(i_psram_sub_AsyncPSRAMinst_n_701), .Z
(i_psram_sub_AsyncPSRAMinst_n_2315));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_4(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2315), .SD(1'b1), .Q(MEM_ADDR_OUT
[4]));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_446(.A(i_psram_sub_AsyncPSRAMinst_n_628
), .B(i_psram_sub_AsyncPSRAMinst_n_396), .C(i_psram_sub_AsyncPSRAMinst_n_626
), .Z(i_psram_sub_AsyncPSRAMinst_n_629));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1291(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[3]), .B(i_psram_sub_AsyncPSRAMinst_n_2877), .Z
(i_psram_sub_AsyncPSRAMinst_n_2309));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_3(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2309), .SD(1'b1), .Q(MEM_ADDR_OUT
[3]));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_443(.A(i_psram_sub_mem_addr[5]),
.B(i_psram_sub_AsyncPSRAMinst_n_2896), .C(i_psram_sub_AsyncPSRAMinst_last_page_read
[2]), .D(i_psram_sub_AsyncPSRAMinst_n_2927), .Z(i_psram_sub_AsyncPSRAMinst_n_628
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1283(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[2]), .B(i_psram_sub_AsyncPSRAMinst_n_2876), .Z
(i_psram_sub_AsyncPSRAMinst_n_2303));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_2(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2303), .SD(1'b1), .Q(MEM_ADDR_OUT
[2]));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1275(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[1]), .B(i_psram_sub_AsyncPSRAMinst_n_2875), .Z
(i_psram_sub_AsyncPSRAMinst_n_2297));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_1(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2297), .SD(1'b1), .Q(MEM_ADDR_OUT
[1]));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_444(.A(i_psram_sub_mem_addr[7])
, .B(i_psram_sub_AsyncPSRAMinst_last_page_read[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_626
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1267(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(MEM_ADDR_OUT[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2874), .Z
(i_psram_sub_AsyncPSRAMinst_n_2291));
notech_reg_set i_psram_sub_AsyncPSRAMinst_mem_addr_out_i_reg_0(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2291), .SD(1'b1), .Q(MEM_ADDR_OUT
[0]));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_456(.A(i_psram_sub_AsyncPSRAMinst_n_619
), .B(i_psram_sub_AsyncPSRAMinst_n_402), .C(i_psram_sub_AsyncPSRAMinst_n_622
), .D(i_psram_sub_AsyncPSRAMinst_n_618), .Z(i_psram_sub_AsyncPSRAMinst_n_624
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1259(.S(i_psram_sub_AsyncPSRAMinst_n_673
), .A(i_psram_sub_AsyncPSRAMinst_page_valid), .B(i_psram_sub_AsyncPSRAMinst_n_674
), .Z(i_psram_sub_AsyncPSRAMinst_n_2285));
notech_reg_set i_psram_sub_AsyncPSRAMinst_page_valid_reg(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2285), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_page_valid
));
notech_mux2 i_psram_sub_AsyncPSRAMinst_i_1251(.S(\i_psram_sub_AsyncPSRAMinst_nbus_16[0]
), .A(i_psram_sub_AsyncPSRAMinst_current_cmd), .B(i_psram_sub_AsyncPSRAMinst_n_451
), .Z(i_psram_sub_AsyncPSRAMinst_n_2279));
notech_reg_set i_psram_sub_AsyncPSRAMinst_current_cmd_reg(.CP(s00_axi_aclk
), .D(i_psram_sub_AsyncPSRAMinst_n_2279), .SD(1'b1), .Q(i_psram_sub_AsyncPSRAMinst_current_cmd
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_448(.A(i_psram_sub_AsyncPSRAMinst_n_2928
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_622
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_449(.A(i_psram_sub_mem_addr[9]),
.B(i_psram_sub_AsyncPSRAMinst_n_2897), .C(i_psram_sub_AsyncPSRAMinst_n_2930
), .D(i_psram_sub_AsyncPSRAMinst_last_page_read[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_619
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_455(.A(i_psram_sub_AsyncPSRAMinst_n_617
), .B(i_psram_sub_AsyncPSRAMinst_n_408), .C(i_psram_sub_AsyncPSRAMinst_n_614
), .Z(i_psram_sub_AsyncPSRAMinst_n_618));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_452(.A(i_psram_sub_mem_addr[10])
, .B(i_psram_sub_AsyncPSRAMinst_n_2898), .C(i_psram_sub_AsyncPSRAMinst_last_page_read
[7]), .D(i_psram_sub_AsyncPSRAMinst_n_2931), .Z(i_psram_sub_AsyncPSRAMinst_n_617
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_453(.A(i_psram_sub_AsyncPSRAMinst_n_2932
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[8]), .Z(i_psram_sub_AsyncPSRAMinst_n_614
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_466(.A(i_psram_sub_AsyncPSRAMinst_n_607
), .B(i_psram_sub_AsyncPSRAMinst_n_414), .C(i_psram_sub_AsyncPSRAMinst_n_609
), .D(i_psram_sub_AsyncPSRAMinst_n_606), .Z(i_psram_sub_AsyncPSRAMinst_n_612
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_458(.A(i_psram_sub_AsyncPSRAMinst_n_2933
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[9]), .Z(i_psram_sub_AsyncPSRAMinst_n_609
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_459(.A(i_psram_sub_mem_addr[14])
, .B(i_psram_sub_AsyncPSRAMinst_n_2900), .C(i_psram_sub_AsyncPSRAMinst_n_2935
), .D(i_psram_sub_AsyncPSRAMinst_last_page_read[11]), .Z(i_psram_sub_AsyncPSRAMinst_n_607
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_465(.A(i_psram_sub_AsyncPSRAMinst_n_604
), .B(i_psram_sub_AsyncPSRAMinst_n_419), .C(i_psram_sub_AsyncPSRAMinst_n_602
), .Z(i_psram_sub_AsyncPSRAMinst_n_606));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_462(.A(i_psram_sub_mem_addr[15])
, .B(i_psram_sub_AsyncPSRAMinst_n_2901), .C(i_psram_sub_AsyncPSRAMinst_last_page_read
[12]), .D(i_psram_sub_AsyncPSRAMinst_n_2936), .Z(i_psram_sub_AsyncPSRAMinst_n_604
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_463(.A(i_psram_sub_AsyncPSRAMinst_n_2937
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[13]), .Z(i_psram_sub_AsyncPSRAMinst_n_602
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_475(.A(i_psram_sub_AsyncPSRAMinst_n_596
), .B(i_psram_sub_AsyncPSRAMinst_n_426), .C(i_psram_sub_AsyncPSRAMinst_n_598
), .D(i_psram_sub_AsyncPSRAMinst_n_594), .Z(i_psram_sub_AsyncPSRAMinst_n_601
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_467(.A(i_psram_sub_AsyncPSRAMinst_n_2938
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[14]), .Z(i_psram_sub_AsyncPSRAMinst_n_598
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_468(.A(i_psram_sub_mem_addr[19])
, .B(i_psram_sub_AsyncPSRAMinst_n_2902), .C(i_psram_sub_AsyncPSRAMinst_n_2940
), .D(i_psram_sub_AsyncPSRAMinst_last_page_read[16]), .Z(i_psram_sub_AsyncPSRAMinst_n_596
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_474(.A(i_psram_sub_AsyncPSRAMinst_n_593
), .B(i_psram_sub_AsyncPSRAMinst_n_431), .C(i_psram_sub_AsyncPSRAMinst_n_591
), .Z(i_psram_sub_AsyncPSRAMinst_n_594));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_471(.A(i_psram_sub_mem_addr[20])
, .B(i_psram_sub_AsyncPSRAMinst_n_2903), .C(i_psram_sub_AsyncPSRAMinst_last_page_read
[17]), .D(i_psram_sub_AsyncPSRAMinst_n_2941), .Z(i_psram_sub_AsyncPSRAMinst_n_593
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_472(.A(i_psram_sub_AsyncPSRAMinst_n_2942
), .B(i_psram_sub_AsyncPSRAMinst_last_page_read[18]), .Z(i_psram_sub_AsyncPSRAMinst_n_591
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_116(.A(i_psram_sub_AsyncPSRAMinst_n_2866
), .B(i_psram_sub_AsyncPSRAMinst_n_586), .C(i_psram_sub_AsyncPSRAMinst_n_432
), .Z(i_psram_sub_AsyncPSRAMinst_n_588));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_478(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_2915), .C(i_psram_sub_AsyncPSRAMinst_n_2916
), .D(i_psram_sub_AsyncPSRAMinst_waitcount[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_586
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_110(.A(i_psram_sub_AsyncPSRAMinst_n_441
), .B(i_psram_sub_AsyncPSRAMinst_n_433), .C(i_psram_sub_AsyncPSRAMinst_n_2866
), .Z(i_psram_sub_AsyncPSRAMinst_n_568));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_497(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[3]), .B(i_psram_sub_AsyncPSRAMinst_n_2913), .Z(i_psram_sub_AsyncPSRAMinst_n_562
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_499(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_442),
.Z(i_psram_sub_AsyncPSRAMinst_n_561));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_105(.A(i_psram_sub_AsyncPSRAMinst_n_2864
), .B(i_psram_sub_AsyncPSRAMinst_n_444), .C(i_psram_sub_AsyncPSRAMinst_n_445
), .D(i_psram_sub_AsyncPSRAMinst_n_2865), .Z(i_psram_sub_AsyncPSRAMinst_n_559
));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_137(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_556)
);
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_500(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[1]), .C(i_psram_sub_AsyncPSRAMinst_n_2907
), .Z(i_psram_sub_AsyncPSRAMinst_n_555));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_505(.A(i_psram_sub_AsyncPSRAMinst_n_507
), .B(i_psram_sub_AsyncPSRAMinst_n_447), .Z(i_psram_sub_AsyncPSRAMinst_n_553
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_506(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_2909
), .Z(i_psram_sub_AsyncPSRAMinst_n_551));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_513(.A(i_psram_sub_AsyncPSRAMinst_n_2864
), .B(i_psram_sub_AsyncPSRAMinst_n_2916), .Z(i_psram_sub_AsyncPSRAMinst_n_543
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_103(.A(i_psram_sub_AsyncPSRAMinst_n_2912
), .B(i_psram_sub_AsyncPSRAMinst_cycle_time[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_542
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_516(.A(i_psram_sub_AsyncPSRAMinst_n_2872
), .B(i_psram_sub_AsyncPSRAMinst_cycle_time[6]), .C(i_psram_sub_AsyncPSRAMinst_waitcount
[5]), .D(i_psram_sub_AsyncPSRAMinst_n_293), .Z(i_psram_sub_AsyncPSRAMinst_n_538
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_517(.A(i_psram_sub_AsyncPSRAMinst_n_294
), .B(i_psram_sub_AsyncPSRAMinst_waitcount[4]), .C(i_psram_sub_AsyncPSRAMinst_n_507
), .D(i_psram_sub_AsyncPSRAMinst_n_446), .Z(i_psram_sub_AsyncPSRAMinst_n_533
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_115(.A(i_psram_sub_AsyncPSRAMinst_n_463
), .B(i_psram_sub_AsyncPSRAMinst_n_441), .C(i_psram_sub_AsyncPSRAMinst_n_462
), .D(i_psram_sub_AsyncPSRAMinst_n_461), .Z(i_psram_sub_AsyncPSRAMinst_n_532
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_518(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[3]), .B(i_psram_sub_AsyncPSRAMinst_n_295), .C(i_psram_sub_AsyncPSRAMinst_n_2871
), .D(i_psram_sub_AsyncPSRAMinst_n_441), .Z(i_psram_sub_AsyncPSRAMinst_n_530
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_130(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_299), .C(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .D(i_psram_sub_AsyncPSRAMinst_n_297), .Z(i_psram_sub_AsyncPSRAMinst_n_526
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_134(.A(i_psram_sub_AsyncPSRAMinst_n_231
), .B(i_psram_sub_AsyncPSRAMinst_n_518), .Z(i_psram_sub_AsyncPSRAMinst_n_522
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_107(.A(i_psram_sub_AsyncPSRAMinst_n_463
), .B(i_psram_sub_AsyncPSRAMinst_n_441), .C(i_psram_sub_AsyncPSRAMinst_n_462
), .Z(i_psram_sub_AsyncPSRAMinst_n_521));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_119(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2967), .Z(i_psram_sub_AsyncPSRAMinst_n_518
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_528(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[5]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_464),
.Z(i_psram_sub_AsyncPSRAMinst_n_516));
notech_nor2 i_psram_sub_AsyncPSRAMinst_i_530(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[6]), .B(i_psram_sub_AsyncPSRAMinst_n_514), .Z(i_psram_sub_AsyncPSRAMinst_n_515
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_117(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .B(i_psram_sub_AsyncPSRAMinst_cycle_time[0]), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_514));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_529(.A(i_psram_sub_AsyncPSRAMinst_n_507
), .B(i_psram_sub_AsyncPSRAMinst_waitcount[4]), .C(i_psram_sub_AsyncPSRAMinst_n_2912
), .Z(i_psram_sub_AsyncPSRAMinst_n_509));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_114(.A(i_psram_sub_AsyncPSRAMinst_n_507
), .B(i_psram_sub_AsyncPSRAMinst_waitcount[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_508
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_106(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[2]), .C(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .D(i_psram_sub_AsyncPSRAMinst_waitcount[3]), .Z(i_psram_sub_AsyncPSRAMinst_n_507
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_113(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_505
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_136(.A(i_psram_sub_go), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_500));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_131(.A(i_psram_sub_go), .B(s00_axi_aresetn
), .C(i_psram_sub_AsyncPSRAMinst_n_2920), .Z(i_psram_sub_AsyncPSRAMinst_n_498
));
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_132(.A(s00_axi_aresetn), .B(i_psram_sub_AsyncPSRAMinst_n_2920
), .C(i_psram_sub_go), .Z(i_psram_sub_AsyncPSRAMinst_n_497));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_139(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2920), .Z(i_psram_sub_AsyncPSRAMinst_n_493
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_140(.A(i_psram_sub_AsyncPSRAMinst_cem_time_expired
), .B(i_psram_sub_AsyncPSRAMinst_n_2968), .Z(i_psram_sub_AsyncPSRAMinst_n_491
));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_96(.A(i_psram_sub_AsyncPSRAMinst_state
[1]), .B(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_490)
);
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_341(.A(i_psram_sub_go), .B(i_psram_sub_mem_addr
[7]), .C(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_489)
);
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_340(.A(MEM_ADDR_OUT[7]), .B(s00_axi_aresetn
), .C(i_psram_sub_go), .Z(i_psram_sub_AsyncPSRAMinst_n_488));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_335(.A(i_psram_sub_go), .B(i_psram_sub_mem_addr
[4]), .C(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_487)
);
notech_nao3 i_psram_sub_AsyncPSRAMinst_i_334(.A(MEM_ADDR_OUT[4]), .B(s00_axi_aresetn
), .C(i_psram_sub_go), .Z(i_psram_sub_AsyncPSRAMinst_n_486));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_27(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[22]), .Z(i_psram_sub_AsyncPSRAMinst_n_485
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_28(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[21]), .Z(i_psram_sub_AsyncPSRAMinst_n_483
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_291590(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[20]), .Z(i_psram_sub_AsyncPSRAMinst_n_482
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_31(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[19]), .Z(i_psram_sub_AsyncPSRAMinst_n_481
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_32(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[18]), .Z(i_psram_sub_AsyncPSRAMinst_n_480
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_33(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[17]), .Z(i_psram_sub_AsyncPSRAMinst_n_479
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_34(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[16]), .Z(i_psram_sub_AsyncPSRAMinst_n_478
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_35(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[15]), .Z(i_psram_sub_AsyncPSRAMinst_n_477
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_36(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[14]), .Z(i_psram_sub_AsyncPSRAMinst_n_476
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_37(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[13]), .Z(i_psram_sub_AsyncPSRAMinst_n_475
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_38(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[12]), .Z(i_psram_sub_AsyncPSRAMinst_n_474
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_39(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[11]), .Z(i_psram_sub_AsyncPSRAMinst_n_472
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_40(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[10]), .Z(i_psram_sub_AsyncPSRAMinst_n_471
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_41(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[9]), .Z(i_psram_sub_AsyncPSRAMinst_n_470
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_42(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[8]), .Z(i_psram_sub_AsyncPSRAMinst_n_469
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_43(.A(MEM_ADDR_OUT[7]), .B(i_psram_sub_AsyncPSRAMinst_current_cmd
), .C(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_468));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_44(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[6]), .Z(i_psram_sub_AsyncPSRAMinst_n_467
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_45(.A(i_psram_sub_AsyncPSRAMinst_current_cmd
), .B(s00_axi_aresetn), .C(MEM_ADDR_OUT[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_466
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_46(.A(MEM_ADDR_OUT[4]), .B(i_psram_sub_AsyncPSRAMinst_current_cmd
), .C(s00_axi_aresetn), .Z(i_psram_sub_AsyncPSRAMinst_n_465));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_143(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .B(i_psram_sub_AsyncPSRAMinst_cycle_time[3]), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]), .D(i_psram_sub_AsyncPSRAMinst_n_515), .Z(i_psram_sub_AsyncPSRAMinst_n_464
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_129(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_2915), .Z(i_psram_sub_AsyncPSRAMinst_n_463
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_126(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_2914), .Z(i_psram_sub_AsyncPSRAMinst_n_462
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_127(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2913), .Z(i_psram_sub_AsyncPSRAMinst_n_461
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_310(.A(i_psram_sub_AsyncPSRAMinst_n_292
), .B(i_psram_sub_AsyncPSRAMinst_n_2967), .Z(i_psram_sub_AsyncPSRAMinst_n_454
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_146(.A(i_psram_sub_AsyncPSRAMinst_n_514
), .B(i_psram_sub_AsyncPSRAMinst_n_543), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]), .D(i_psram_sub_AsyncPSRAMinst_n_2917), .Z(i_psram_sub_AsyncPSRAMinst_n_453
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_303(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[5]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_285),
.Z(i_psram_sub_AsyncPSRAMinst_n_452));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_302(.A(i_psram_sub_AsyncPSRAMinst_n_453
), .B(i_psram_sub_AsyncPSRAMinst_n_2872), .C(s00_axi_aresetn), .D
(i_psram_sub_AsyncPSRAMinst_n_2910), .Z(i_psram_sub_AsyncPSRAMinst_n_450
));
notech_nor2 i_psram_sub_AsyncPSRAMinst_i_304(.A(i_psram_sub_AsyncPSRAMinst_n_522
), .B(i_psram_sub_AsyncPSRAMinst_n_2910), .Z(i_psram_sub_AsyncPSRAMinst_n_449
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_125(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[5]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_508),
.D(i_psram_sub_AsyncPSRAMinst_n_2918), .Z(i_psram_sub_AsyncPSRAMinst_n_448
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_149(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .B(i_psram_sub_AsyncPSRAMinst_n_514), .C(i_psram_sub_AsyncPSRAMinst_n_543
), .D(i_psram_sub_AsyncPSRAMinst_n_444), .Z(i_psram_sub_AsyncPSRAMinst_n_447
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_295(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[4]), .B(i_psram_sub_AsyncPSRAMinst_n_2917), .Z(i_psram_sub_AsyncPSRAMinst_n_446
));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_294(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .B(i_psram_sub_AsyncPSRAMinst_n_2909), .Z(i_psram_sub_AsyncPSRAMinst_n_445
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_109(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[5]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[5]), .Z(i_psram_sub_AsyncPSRAMinst_n_444
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_153(.A(i_psram_sub_AsyncPSRAMinst_n_2866
), .B(i_psram_sub_AsyncPSRAMinst_n_2916), .C(i_psram_sub_AsyncPSRAMinst_n_514
), .Z(i_psram_sub_AsyncPSRAMinst_n_442));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_280(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[3]), .B(i_psram_sub_AsyncPSRAMinst_n_2916), .Z(i_psram_sub_AsyncPSRAMinst_n_441
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_158(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_568), .C(i_psram_sub_AsyncPSRAMinst_n_2914
), .D(i_psram_sub_AsyncPSRAMinst_n_2913), .Z(i_psram_sub_AsyncPSRAMinst_n_440
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_159(.A(i_psram_sub_AsyncPSRAMinst_n_461
), .B(i_psram_sub_AsyncPSRAMinst_cycle_time[2]), .C(i_psram_sub_AsyncPSRAMinst_n_2868
), .D(i_psram_sub_AsyncPSRAMinst_n_2914), .Z(i_psram_sub_AsyncPSRAMinst_n_439
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_275(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_439), .C(i_psram_sub_AsyncPSRAMinst_n_2967
), .D(i_psram_sub_AsyncPSRAMinst_n_2905), .Z(i_psram_sub_AsyncPSRAMinst_n_438
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_274(.A(i_psram_sub_AsyncPSRAMinst_n_440
), .B(i_psram_sub_AsyncPSRAMinst_n_556), .C(i_psram_sub_AsyncPSRAMinst_waitcount
[1]), .D(i_psram_sub_AsyncPSRAMinst_n_2905), .Z(i_psram_sub_AsyncPSRAMinst_n_437
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_111(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_436
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_267(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[3]), .B(i_psram_sub_AsyncPSRAMinst_n_2907), .Z(i_psram_sub_AsyncPSRAMinst_n_433
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_269(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_2904), .Z(i_psram_sub_AsyncPSRAMinst_n_432
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_225(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[17]), .B(i_psram_sub_AsyncPSRAMinst_n_2941), .Z(i_psram_sub_AsyncPSRAMinst_n_431
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_230(.A(i_psram_sub_mem_addr[19
]), .B(i_psram_sub_AsyncPSRAMinst_n_2902), .Z(i_psram_sub_AsyncPSRAMinst_n_426
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_235(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[12]), .B(i_psram_sub_AsyncPSRAMinst_n_2936), .Z(i_psram_sub_AsyncPSRAMinst_n_419
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_240(.A(i_psram_sub_mem_addr[14
]), .B(i_psram_sub_AsyncPSRAMinst_n_2900), .Z(i_psram_sub_AsyncPSRAMinst_n_414
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_248(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[7]), .B(i_psram_sub_AsyncPSRAMinst_n_2931), .Z(i_psram_sub_AsyncPSRAMinst_n_408
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_255(.A(i_psram_sub_mem_addr[9]
), .B(i_psram_sub_AsyncPSRAMinst_n_2897), .Z(i_psram_sub_AsyncPSRAMinst_n_402
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_260(.A(i_psram_sub_AsyncPSRAMinst_last_page_read
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_2927), .Z(i_psram_sub_AsyncPSRAMinst_n_396
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_265(.A(i_psram_sub_mem_addr[4]
), .B(i_psram_sub_AsyncPSRAMinst_n_2895), .Z(i_psram_sub_AsyncPSRAMinst_n_387
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_176(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[0]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_386
));
notech_xor2 i_psram_sub_AsyncPSRAMinst_i_175(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .B(i_psram_sub_AsyncPSRAMinst_waitcount[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_384
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_195(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2920), .C(i_psram_sub_AsyncPSRAMinst_n_2873
), .Z(i_psram_sub_AsyncPSRAMinst_n_383));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_194(.A(i_psram_sub_AsyncPSRAMinst_n_2919
), .B(i_psram_sub_AsyncPSRAMinst_n_245), .C(i_psram_sub_AsyncPSRAMinst_state
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_382));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_60(.A(i_psram_sub_AsyncPSRAMinst_n_115
), .B(i_psram_sub_AsyncPSRAMinst_n_658), .C(i_psram_sub_AsyncPSRAMinst_cen_old
), .Z(i_psram_sub_AsyncPSRAMinst_n_381));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_71(.A(i_psram_sub_AsyncPSRAMinst_cen_old
), .B(i_psram_sub_AsyncPSRAMinst_n_658), .Z(i_psram_sub_AsyncPSRAMinst_n_379
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_66(.A(i_psram_sub_AsyncPSRAMinst_n_109
), .B(i_psram_sub_AsyncPSRAMinst_n_658), .C(i_psram_sub_AsyncPSRAMinst_cen_old
), .Z(i_psram_sub_AsyncPSRAMinst_n_378));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_67(.A(i_psram_sub_AsyncPSRAMinst_n_108
), .B(i_psram_sub_AsyncPSRAMinst_n_658), .C(i_psram_sub_AsyncPSRAMinst_cen_old
), .Z(i_psram_sub_AsyncPSRAMinst_n_377));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_177(.A(i_psram_sub_AsyncPSRAMinst_n_463
), .B(i_psram_sub_AsyncPSRAMinst_n_441), .C(i_psram_sub_AsyncPSRAMinst_n_462
), .D(i_psram_sub_AsyncPSRAMinst_n_2913), .Z(i_psram_sub_AsyncPSRAMinst_n_231
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_178(.A(i_psram_sub_go), .B(i_psram_sub_AsyncPSRAMinst_cem_time_expired
), .C(i_psram_sub_AsyncPSRAMinst_n_2919), .D(i_psram_sub_AsyncPSRAMinst_n_2920
), .Z(i_psram_sub_AsyncPSRAMinst_n_232));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_167(.A(i_psram_sub_AsyncPSRAMinst_n_532
), .B(i_psram_sub_AsyncPSRAMinst_n_356), .C(i_psram_sub_AsyncPSRAMinst_n_588
), .Z(i_psram_sub_AsyncPSRAMinst_n_233));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_184(.A(i_psram_sub_mem_byte_en
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2920), .Z(i_psram_sub_AsyncPSRAMinst_n_235
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_185(.A(i_psram_sub_mem_byte_en
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_2920), .Z(i_psram_sub_AsyncPSRAMinst_n_236
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_186(.A(i_psram_sub_AsyncPSRAMinst_n_642
), .B(i_psram_sub_AsyncPSRAMinst_state[1]), .C(i_psram_sub_AsyncPSRAMinst_n_2873
), .D(i_psram_sub_AsyncPSRAMinst_n_2919), .Z(i_psram_sub_AsyncPSRAMinst_n_237
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_187(.A(i_psram_sub_AsyncPSRAMinst_state
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_642), .Z(i_psram_sub_AsyncPSRAMinst_n_238
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_188(.A(i_psram_sub_AsyncPSRAMinst_n_107
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_239
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_189(.A(i_psram_sub_AsyncPSRAMinst_n_110
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_240
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_190(.A(i_psram_sub_AsyncPSRAMinst_n_111
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_241
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_191(.A(i_psram_sub_AsyncPSRAMinst_n_112
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_242
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_192(.A(i_psram_sub_AsyncPSRAMinst_n_113
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_243
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_193(.A(i_psram_sub_AsyncPSRAMinst_n_114
), .B(i_psram_sub_AsyncPSRAMinst_n_2921), .Z(i_psram_sub_AsyncPSRAMinst_n_244
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_163(.A(i_psram_sub_AsyncPSRAMinst_cem_time_expired
), .B(i_psram_sub_AsyncPSRAMinst_n_246), .Z(i_psram_sub_AsyncPSRAMinst_n_245
));
notech_nor2 i_psram_sub_AsyncPSRAMinst_i_196(.A(i_psram_sub_go), .B(i_psram_sub_AsyncPSRAMinst_n_2968
), .Z(i_psram_sub_AsyncPSRAMinst_n_246));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_197(.A(i_psram_sub_go), .B(i_psram_sub_AsyncPSRAMinst_n_2919
), .C(i_psram_sub_AsyncPSRAMinst_n_2920), .D(i_psram_sub_AsyncPSRAMinst_n_248
), .Z(i_psram_sub_AsyncPSRAMinst_n_247));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_171(.A(i_psram_sub_command), .B
(i_psram_sub_AsyncPSRAMinst_n_637), .Z(i_psram_sub_AsyncPSRAMinst_n_248
));
notech_nand3 i_psram_sub_AsyncPSRAMinst_i_219(.A(i_psram_sub_go), .B(i_psram_sub_command
), .C(i_psram_sub_AsyncPSRAMinst_n_254), .Z(i_psram_sub_AsyncPSRAMinst_n_253
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_162(.A(i_psram_sub_AsyncPSRAMinst_cem_time_expired
), .B(i_psram_sub_AsyncPSRAMinst_n_2863), .Z(i_psram_sub_AsyncPSRAMinst_n_254
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_266(.A(i_psram_sub_AsyncPSRAMinst_n_588
), .B(i_psram_sub_AsyncPSRAMinst_n_518), .Z(i_psram_sub_AsyncPSRAMinst_n_255
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_270(.A(i_psram_sub_AsyncPSRAMinst_n_257
), .B(i_psram_sub_AsyncPSRAMinst_waitcount[1]), .C(i_psram_sub_AsyncPSRAMinst_n_518
), .Z(i_psram_sub_AsyncPSRAMinst_n_256));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_160(.A(i_psram_sub_AsyncPSRAMinst_n_436
), .B(i_psram_sub_AsyncPSRAMinst_n_568), .C(i_psram_sub_AsyncPSRAMinst_n_2914
), .D(i_psram_sub_AsyncPSRAMinst_cycle_time[0]), .Z(i_psram_sub_AsyncPSRAMinst_n_257
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_271(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_n_259),
.D(i_psram_sub_AsyncPSRAMinst_n_2904), .Z(i_psram_sub_AsyncPSRAMinst_n_258
));
notech_or4 i_psram_sub_AsyncPSRAMinst_i_161(.A(i_psram_sub_AsyncPSRAMinst_n_436
), .B(i_psram_sub_AsyncPSRAMinst_n_568), .C(i_psram_sub_AsyncPSRAMinst_n_2913
), .D(i_psram_sub_AsyncPSRAMinst_cycle_time[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_259
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_276(.A(i_psram_sub_AsyncPSRAMinst_n_263
), .B(i_psram_sub_AsyncPSRAMinst_n_518), .Z(i_psram_sub_AsyncPSRAMinst_n_262
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_156(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .B(i_psram_sub_AsyncPSRAMinst_n_505), .C(i_psram_sub_AsyncPSRAMinst_n_2905
), .D(i_psram_sub_AsyncPSRAMinst_n_265), .Z(i_psram_sub_AsyncPSRAMinst_n_263
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_157(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .B(i_psram_sub_AsyncPSRAMinst_n_2913), .C(i_psram_sub_AsyncPSRAMinst_n_2868
), .Z(i_psram_sub_AsyncPSRAMinst_n_265));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_151(.A(i_psram_sub_AsyncPSRAMinst_n_273
), .B(i_psram_sub_AsyncPSRAMinst_n_518), .C(i_psram_sub_AsyncPSRAMinst_n_2967
), .D(i_psram_sub_AsyncPSRAMinst_n_271), .Z(i_psram_sub_AsyncPSRAMinst_n_269
));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_152(.A(i_psram_sub_AsyncPSRAMinst_n_526
), .B(i_psram_sub_AsyncPSRAMinst_n_2870), .Z(i_psram_sub_AsyncPSRAMinst_n_271
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_155(.A(i_psram_sub_AsyncPSRAMinst_n_463
), .B(i_psram_sub_AsyncPSRAMinst_n_462), .C(i_psram_sub_AsyncPSRAMinst_n_2866
), .D(i_psram_sub_AsyncPSRAMinst_n_562), .Z(i_psram_sub_AsyncPSRAMinst_n_273
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_293(.A(i_psram_sub_AsyncPSRAMinst_n_2905
), .B(i_psram_sub_AsyncPSRAMinst_n_2904), .C(i_psram_sub_AsyncPSRAMinst_n_2916
), .D(i_psram_sub_AsyncPSRAMinst_n_559), .Z(i_psram_sub_AsyncPSRAMinst_n_274
));
notech_ao4 i_psram_sub_AsyncPSRAMinst_i_147(.A(i_psram_sub_AsyncPSRAMinst_n_518
), .B(i_psram_sub_AsyncPSRAMinst_n_231), .C(i_psram_sub_AsyncPSRAMinst_n_280
), .D(i_psram_sub_AsyncPSRAMinst_n_2967), .Z(i_psram_sub_AsyncPSRAMinst_n_278
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_148(.A(i_psram_sub_AsyncPSRAMinst_n_526
), .B(i_psram_sub_AsyncPSRAMinst_n_530), .C(i_psram_sub_AsyncPSRAMinst_n_281
), .Z(i_psram_sub_AsyncPSRAMinst_n_280));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_299(.A(i_psram_sub_AsyncPSRAMinst_n_507
), .B(i_psram_sub_AsyncPSRAMinst_n_282), .Z(i_psram_sub_AsyncPSRAMinst_n_281
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_150(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .B(i_psram_sub_AsyncPSRAMinst_n_542), .C(i_psram_sub_AsyncPSRAMinst_n_444
), .Z(i_psram_sub_AsyncPSRAMinst_n_282));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_145(.A(i_psram_sub_AsyncPSRAMinst_n_526
), .B(i_psram_sub_AsyncPSRAMinst_n_530), .C(i_psram_sub_AsyncPSRAMinst_n_533
), .D(i_psram_sub_AsyncPSRAMinst_n_286), .Z(i_psram_sub_AsyncPSRAMinst_n_285
));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_305(.A(i_psram_sub_AsyncPSRAMinst_n_508
), .B(i_psram_sub_AsyncPSRAMinst_n_2864), .Z(i_psram_sub_AsyncPSRAMinst_n_286
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_141(.A(i_psram_sub_AsyncPSRAMinst_n_522
), .B(i_psram_sub_AsyncPSRAMinst_n_454), .C(i_psram_sub_AsyncPSRAMinst_n_448
), .Z(i_psram_sub_AsyncPSRAMinst_n_291));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_142(.A(i_psram_sub_AsyncPSRAMinst_n_526
), .B(i_psram_sub_AsyncPSRAMinst_n_530), .C(i_psram_sub_AsyncPSRAMinst_n_533
), .D(i_psram_sub_AsyncPSRAMinst_n_538), .Z(i_psram_sub_AsyncPSRAMinst_n_292
));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_144(.A(i_psram_sub_AsyncPSRAMinst_cycle_time
[6]), .B(i_psram_sub_AsyncPSRAMinst_n_446), .C(i_psram_sub_AsyncPSRAMinst_n_532
), .D(i_psram_sub_AsyncPSRAMinst_n_2918), .Z(i_psram_sub_AsyncPSRAMinst_n_293
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_170(.A(i_psram_sub_AsyncPSRAMinst_n_461
), .B(i_psram_sub_AsyncPSRAMinst_n_521), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[4]), .Z(i_psram_sub_AsyncPSRAMinst_n_294));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_172(.A(i_psram_sub_AsyncPSRAMinst_n_463
), .B(i_psram_sub_AsyncPSRAMinst_n_461), .C(i_psram_sub_AsyncPSRAMinst_n_462
), .D(i_psram_sub_AsyncPSRAMinst_n_2916), .Z(i_psram_sub_AsyncPSRAMinst_n_295
));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_173(.A(i_psram_sub_AsyncPSRAMinst_n_461
), .B(i_psram_sub_AsyncPSRAMinst_n_463), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_297));
notech_ao3 i_psram_sub_AsyncPSRAMinst_i_174(.A(i_psram_sub_AsyncPSRAMinst_n_462
), .B(i_psram_sub_AsyncPSRAMinst_n_461), .C(i_psram_sub_AsyncPSRAMinst_cycle_time
[2]), .Z(i_psram_sub_AsyncPSRAMinst_n_299));
notech_and4 i_psram_sub_AsyncPSRAMinst_i_393(.A(i_psram_sub_AsyncPSRAMinst_page_valid
), .B(i_psram_sub_AsyncPSRAMinst_n_491), .C(s00_axi_aresetn), .D
(i_psram_sub_AsyncPSRAMinst_n_2919), .Z(i_psram_sub_AsyncPSRAMinst_n_348
));
notech_and3 i_psram_sub_AsyncPSRAMinst_i_396(.A(i_psram_sub_AsyncPSRAMinst_state
[0]), .B(s00_axi_aresetn), .C(i_psram_sub_AsyncPSRAMinst_current_cmd
), .Z(i_psram_sub_AsyncPSRAMinst_n_349));
notech_nor2 i_psram_sub_AsyncPSRAMinst_i_397(.A(i_psram_sub_go), .B(i_psram_sub_AsyncPSRAMinst_state
[1]), .Z(i_psram_sub_AsyncPSRAMinst_n_351));
notech_nand2 i_psram_sub_AsyncPSRAMinst_i_398(.A(i_psram_sub_command), .B
(i_psram_sub_AsyncPSRAMinst_n_2920), .Z(i_psram_sub_AsyncPSRAMinst_n_352
));
notech_or2 i_psram_sub_AsyncPSRAMinst_i_183(.A(i_psram_sub_AsyncPSRAMinst_waitcount
[0]), .B(i_psram_sub_AsyncPSRAMinst_n_2913), .Z(i_psram_sub_AsyncPSRAMinst_n_356
));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_94(.A(MEM_DATA_I[0]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_357));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_92(.A(MEM_DATA_I[1]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_358));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_91(.A(MEM_DATA_I[2]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_359));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_90(.A(MEM_DATA_I[3]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_361));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_89(.A(MEM_DATA_I[4]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_362));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_88(.A(MEM_DATA_I[5]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_363));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_87(.A(MEM_DATA_I[6]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_364));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_86(.A(MEM_DATA_I[7]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_366));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_85(.A(MEM_DATA_I[8]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_367));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_84(.A(MEM_DATA_I[9]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_368));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_83(.A(MEM_DATA_I[10]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_369));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_82(.A(MEM_DATA_I[11]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_371));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_81(.A(MEM_DATA_I[12]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_372));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_79(.A(MEM_DATA_I[13]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_373));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_76(.A(MEM_DATA_I[14]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_374));
notech_and2 i_psram_sub_AsyncPSRAMinst_i_75(.A(MEM_DATA_I[15]), .B(s00_axi_aresetn
), .Z(i_psram_sub_AsyncPSRAMinst_n_376));
notech_inv i_02655(.A(i_psram_sub_mem_addr[0]), .Z(i_psram_sub_function_plus_2
[0]));
notech_nand2 i_12654(.A(i_psram_sub_mem_addr[0]), .B(i_psram_sub_mem_addr
[1]), .Z(n_1391736));
notech_nand2 i_22653(.A(i_psram_sub_mem_addr[1]), .B(i_psram_sub_mem_addr
[2]), .Z(n_1401735));
notech_nand2 i_32652(.A(i_psram_sub_mem_addr[2]), .B(i_psram_sub_mem_addr
[3]), .Z(n_1411734));
notech_nand2 i_42651(.A(i_psram_sub_mem_addr[3]), .B(i_psram_sub_mem_addr
[4]), .Z(n_1421733));
notech_nand2 i_52650(.A(i_psram_sub_mem_addr[4]), .B(i_psram_sub_mem_addr
[5]), .Z(n_1431732));
notech_nand2 i_62649(.A(i_psram_sub_mem_addr[5]), .B(i_psram_sub_mem_addr
[6]), .Z(n_1441731));
notech_nand2 i_72648(.A(i_psram_sub_mem_addr[6]), .B(i_psram_sub_mem_addr
[7]), .Z(n_1451730));
notech_nand2 i_82647(.A(i_psram_sub_mem_addr[7]), .B(i_psram_sub_mem_addr
[8]), .Z(n_1461729));
notech_nand2 i_92646(.A(i_psram_sub_mem_addr[8]), .B(i_psram_sub_mem_addr
[9]), .Z(n_1471728));
notech_nand2 i_102645(.A(i_psram_sub_mem_addr[9]), .B(i_psram_sub_mem_addr
[10]), .Z(n_1481727));
notech_nand2 i_112644(.A(i_psram_sub_mem_addr[10]), .B(i_psram_sub_mem_addr
[11]), .Z(n_1491726));
notech_nand2 i_122643(.A(i_psram_sub_mem_addr[11]), .B(i_psram_sub_mem_addr
[12]), .Z(n_1501725));
notech_nand2 i_132642(.A(i_psram_sub_mem_addr[12]), .B(i_psram_sub_mem_addr
[13]), .Z(n_1511724));
notech_nand2 i_142641(.A(i_psram_sub_mem_addr[13]), .B(i_psram_sub_mem_addr
[14]), .Z(n_1521723));
notech_nand2 i_152640(.A(i_psram_sub_mem_addr[14]), .B(i_psram_sub_mem_addr
[15]), .Z(n_153));
notech_nand2 i_162639(.A(i_psram_sub_mem_addr[15]), .B(i_psram_sub_mem_addr
[16]), .Z(n_1541722));
notech_nand2 i_172638(.A(i_psram_sub_mem_addr[16]), .B(i_psram_sub_mem_addr
[17]), .Z(n_155));
notech_nand2 i_182637(.A(i_psram_sub_mem_addr[17]), .B(i_psram_sub_mem_addr
[18]), .Z(n_1561721));
notech_nand2 i_192636(.A(i_psram_sub_mem_addr[18]), .B(i_psram_sub_mem_addr
[19]), .Z(n_1571720));
notech_nand2 i_202635(.A(i_psram_sub_mem_addr[19]), .B(i_psram_sub_mem_addr
[20]), .Z(n_1581719));
notech_nand2 i_21(.A(i_psram_sub_mem_addr[20]), .B(i_psram_sub_mem_addr[
21]), .Z(n_1591718));
notech_inv i_232634(.A(i_psram_sub_function_plus_2[0]), .Z(n_1611717));
notech_inv i_242633(.A(n_1391736), .Z(n_2771716));
notech_nor2 i_252632(.A(i_psram_sub_function_plus_2[0]), .B(n_1401735),
.Z(n_1631715));
notech_nor2 i_262631(.A(n_1391736), .B(n_1411734), .Z(n_1641714));
notech_nor2 i_272630(.A(n_1401735), .B(n_1421733), .Z(n_1651713));
notech_nor2 i_282629(.A(n_1411734), .B(n_1431732), .Z(n_1661712));
notech_nor2 i_292628(.A(n_1421733), .B(n_1441731), .Z(n_1671711));
notech_nor2 i_302627(.A(n_1431732), .B(n_1451730), .Z(n_1681710));
notech_nor2 i_312626(.A(n_1441731), .B(n_1461729), .Z(n_1691709));
notech_nor2 i_322625(.A(n_1451730), .B(n_1471728), .Z(n_1701708));
notech_nor2 i_332624(.A(n_1461729), .B(n_1481727), .Z(n_1711707));
notech_nor2 i_342623(.A(n_1471728), .B(n_1491726), .Z(n_1721706));
notech_nor2 i_352622(.A(n_1481727), .B(n_1501725), .Z(n_1731705));
notech_nor2 i_362621(.A(n_1491726), .B(n_1511724), .Z(n_1741704));
notech_nor2 i_372620(.A(n_1501725), .B(n_1521723), .Z(n_175));
notech_nor2 i_382619(.A(n_1511724), .B(n_153), .Z(n_1761703));
notech_nor2 i_392618(.A(n_1521723), .B(n_1541722), .Z(n_1771702));
notech_nor2 i_402617(.A(n_153), .B(n_155), .Z(n_1781701));
notech_nor2 i_412616(.A(n_1541722), .B(n_1561721), .Z(n_179));
notech_nor2 i_422615(.A(n_155), .B(n_1571720), .Z(n_1801700));
notech_nor2 i_43(.A(n_1561721), .B(n_1581719), .Z(n_1811699));
notech_nor2 i_442614(.A(n_1571720), .B(n_1591718), .Z(n_1821698));
notech_inv i_462613(.A(n_1611717), .Z(n_1841697));
notech_inv i_472612(.A(n_2771716), .Z(n_1851696));
notech_inv i_482611(.A(n_1631715), .Z(n_1861695));
notech_inv i_492610(.A(n_1641714), .Z(n_2781694));
notech_nand2 i_502609(.A(n_1611717), .B(n_1651713), .Z(n_1881693));
notech_nand2 i_512608(.A(n_2771716), .B(n_1661712), .Z(n_1891692));
notech_nand2 i_522607(.A(n_1631715), .B(n_1671711), .Z(n_1901691));
notech_nand2 i_532606(.A(n_1641714), .B(n_1681710), .Z(n_1911690));
notech_nand2 i_542605(.A(n_1651713), .B(n_1691709), .Z(n_1921689));
notech_nand2 i_552604(.A(n_1661712), .B(n_1701708), .Z(n_1931688));
notech_nand2 i_562603(.A(n_1671711), .B(n_1711707), .Z(n_1941687));
notech_nand2 i_572602(.A(n_1681710), .B(n_1721706), .Z(n_1951686));
notech_nand2 i_582601(.A(n_1691709), .B(n_1731705), .Z(n_1961685));
notech_nand2 i_592600(.A(n_1701708), .B(n_1741704), .Z(n_197));
notech_nand2 i_602599(.A(n_1711707), .B(n_175), .Z(n_1981684));
notech_nand2 i_612598(.A(n_1721706), .B(n_1761703), .Z(n_1991683));
notech_nand2 i_622597(.A(n_1731705), .B(n_1771702), .Z(n_2001682));
notech_nand2 i_632596(.A(n_1741704), .B(n_1781701), .Z(n_2011681));
notech_nand2 i_642595(.A(n_175), .B(n_179), .Z(n_2021680));
notech_nand2 i_652594(.A(n_1761703), .B(n_1801700), .Z(n_203));
notech_nand2 i_662593(.A(n_1771702), .B(n_1811699), .Z(n_204));
notech_nand2 i_672592(.A(n_1781701), .B(n_1821698), .Z(n_205));
notech_inv i_692591(.A(n_1841697), .Z(n_2071679));
notech_inv i_702590(.A(n_1851696), .Z(n_2081678));
notech_inv i_71(.A(n_1861695), .Z(n_2091677));
notech_inv i_722589(.A(n_2781694), .Z(n_2101676));
notech_inv i_73(.A(n_1881693), .Z(n_2111675));
notech_inv i_742588(.A(n_1891692), .Z(n_2121674));
notech_nor2 i_772587(.A(n_1841697), .B(n_1921689), .Z(n_2151673));
notech_nor2 i_782586(.A(n_1851696), .B(n_1931688), .Z(n_2161672));
notech_nor2 i_792585(.A(n_1861695), .B(n_1941687), .Z(n_2171671));
notech_nor2 i_802584(.A(n_2781694), .B(n_1951686), .Z(n_2181670));
notech_nor2 i_812583(.A(n_1881693), .B(n_1961685), .Z(n_2191669));
notech_nor2 i_822582(.A(n_1891692), .B(n_197), .Z(n_2201668));
notech_nor2 i_832581(.A(n_1901691), .B(n_1981684), .Z(n_2211667));
notech_nor2 i_842580(.A(n_1911690), .B(n_1991683), .Z(n_2221666));
notech_nor2 i_852579(.A(n_1921689), .B(n_2001682), .Z(n_2231665));
notech_nor2 i_862578(.A(n_1931688), .B(n_2011681), .Z(n_2241664));
notech_nor2 i_872577(.A(n_1941687), .B(n_2021680), .Z(n_2251663));
notech_nor2 i_882576(.A(n_1951686), .B(n_203), .Z(n_226));
notech_nor2 i_892575(.A(n_1961685), .B(n_204), .Z(n_227));
notech_nor2 i_902574(.A(n_197), .B(n_205), .Z(n_2281662));
notech_inv i_922573(.A(n_2071679), .Z(n_2301661));
notech_inv i_93(.A(n_2081678), .Z(n_2311660));
notech_inv i_94(.A(n_2091677), .Z(n_2321659));
notech_inv i_95(.A(n_2101676), .Z(n_2331658));
notech_inv i_962572(.A(n_2111675), .Z(n_2341657));
notech_inv i_972571(.A(n_2121674), .Z(n_235));
notech_inv i_1002570(.A(n_2151673), .Z(n_2381656));
notech_inv i_1012569(.A(n_2161672), .Z(n_2391655));
notech_inv i_1022568(.A(n_2171671), .Z(n_2401654));
notech_inv i_1032567(.A(n_2181670), .Z(n_241));
notech_inv i_1042566(.A(n_2191669), .Z(n_2421653));
notech_inv i_1052565(.A(n_2201668), .Z(n_2431652));
notech_inv i_1062564(.A(n_2211667), .Z(n_2441651));
notech_inv i_1072563(.A(n_2221666), .Z(n_2821650));
notech_nand2 i_1082562(.A(n_2071679), .B(n_2231665), .Z(n_2461649));
notech_nand2 i_109(.A(n_2081678), .B(n_2241664), .Z(n_2471648));
notech_nand2 i_110(.A(n_2091677), .B(n_2251663), .Z(n_2481647));
notech_nand2 i_111(.A(n_2101676), .B(n_226), .Z(n_2491646));
notech_nand2 i_112(.A(n_2111675), .B(n_227), .Z(n_250));
notech_nand2 i_113(.A(n_2121674), .B(n_2281662), .Z(n_251));
notech_inv i_1382561(.A(n_2301661), .Z(n_2861645));
notech_inv i_1392560(.A(i_psram_sub_mem_addr[1]), .Z(n_2891644));
notech_nand2 i_1402559(.A(n_2891644), .B(n_2301661), .Z(n_2901643));
notech_nand2 i_1412558(.A(i_psram_sub_mem_addr[1]), .B(n_2861645), .Z(n_2871642
));
notech_nand2 i_1422557(.A(n_2871642), .B(n_2901643), .Z(n_2881641));
notech_inv i_1432556(.A(n_2881641), .Z(i_psram_sub_function_plus_2[1])
);
notech_inv i_1442555(.A(n_2311660), .Z(n_2911640));
notech_inv i_1452554(.A(i_psram_sub_mem_addr[2]), .Z(n_2941639));
notech_nand2 i_1462553(.A(n_2941639), .B(n_2311660), .Z(n_2951638));
notech_nand2 i_1472552(.A(i_psram_sub_mem_addr[2]), .B(n_2911640), .Z(n_2921637
));
notech_nand2 i_1482551(.A(n_2921637), .B(n_2951638), .Z(n_2931636));
notech_inv i_1492550(.A(n_2931636), .Z(i_psram_sub_function_plus_2[2])
);
notech_inv i_1502549(.A(n_2321659), .Z(n_2961635));
notech_inv i_1512548(.A(i_psram_sub_mem_addr[3]), .Z(n_2991634));
notech_nand2 i_1522547(.A(n_2991634), .B(n_2321659), .Z(n_3001633));
notech_nand2 i_1532546(.A(i_psram_sub_mem_addr[3]), .B(n_2961635), .Z(n_2971632
));
notech_nand2 i_1542545(.A(n_2971632), .B(n_3001633), .Z(n_2981631));
notech_inv i_1552544(.A(n_2981631), .Z(i_psram_sub_function_plus_2[3])
);
notech_inv i_1562543(.A(n_2331658), .Z(n_3011630));
notech_inv i_1572542(.A(i_psram_sub_mem_addr[4]), .Z(n_3041629));
notech_nand2 i_1582541(.A(n_3041629), .B(n_2331658), .Z(n_3051628));
notech_nand2 i_1592540(.A(i_psram_sub_mem_addr[4]), .B(n_3011630), .Z(n_3021627
));
notech_nand2 i_1602539(.A(n_3021627), .B(n_3051628), .Z(n_3031626));
notech_inv i_1612538(.A(n_3031626), .Z(i_psram_sub_function_plus_2[4])
);
notech_inv i_1622537(.A(n_2341657), .Z(n_3061625));
notech_inv i_1632536(.A(i_psram_sub_mem_addr[5]), .Z(n_3091624));
notech_nand2 i_1642535(.A(n_3091624), .B(n_2341657), .Z(n_3101623));
notech_nand2 i_1652534(.A(i_psram_sub_mem_addr[5]), .B(n_3061625), .Z(n_3071622
));
notech_nand2 i_1662533(.A(n_3071622), .B(n_3101623), .Z(n_3081621));
notech_inv i_1672532(.A(n_3081621), .Z(i_psram_sub_function_plus_2[5])
);
notech_inv i_1682531(.A(n_235), .Z(n_3111620));
notech_inv i_1692530(.A(i_psram_sub_mem_addr[6]), .Z(n_3141619));
notech_nand2 i_1702529(.A(n_3141619), .B(n_235), .Z(n_3151618));
notech_nand2 i_1712528(.A(i_psram_sub_mem_addr[6]), .B(n_3111620), .Z(n_3121617
));
notech_nand2 i_1722527(.A(n_3121617), .B(n_3151618), .Z(n_3131616));
notech_inv i_1732526(.A(n_3131616), .Z(i_psram_sub_function_plus_2[6])
);
notech_inv i_1742525(.A(n_1901691), .Z(n_3161615));
notech_inv i_1752524(.A(i_psram_sub_mem_addr[7]), .Z(n_3191614));
notech_nand2 i_1762523(.A(n_3191614), .B(n_1901691), .Z(n_3201613));
notech_nand2 i_1772522(.A(i_psram_sub_mem_addr[7]), .B(n_3161615), .Z(n_3171612
));
notech_nand2 i_1782521(.A(n_3171612), .B(n_3201613), .Z(n_3181611));
notech_inv i_1792520(.A(n_3181611), .Z(i_psram_sub_function_plus_2[7])
);
notech_inv i_1802519(.A(n_1911690), .Z(n_3211610));
notech_inv i_1812518(.A(i_psram_sub_mem_addr[8]), .Z(n_3241609));
notech_nand2 i_1822517(.A(n_3241609), .B(n_1911690), .Z(n_3251608));
notech_nand2 i_1832516(.A(i_psram_sub_mem_addr[8]), .B(n_3211610), .Z(n_3221607
));
notech_nand2 i_1842515(.A(n_3221607), .B(n_3251608), .Z(n_3231606));
notech_inv i_1852514(.A(n_3231606), .Z(i_psram_sub_function_plus_2[8])
);
notech_inv i_1862513(.A(n_2381656), .Z(n_3261605));
notech_inv i_1872512(.A(i_psram_sub_mem_addr[9]), .Z(n_3291604));
notech_nand2 i_1882511(.A(n_3291604), .B(n_2381656), .Z(n_3301603));
notech_nand2 i_1892510(.A(i_psram_sub_mem_addr[9]), .B(n_3261605), .Z(n_3271602
));
notech_nand2 i_1902509(.A(n_3271602), .B(n_3301603), .Z(n_3281601));
notech_inv i_1912508(.A(n_3281601), .Z(i_psram_sub_function_plus_2[9])
);
notech_inv i_1922507(.A(n_2391655), .Z(n_3311600));
notech_inv i_1932506(.A(i_psram_sub_mem_addr[10]), .Z(n_3341599));
notech_nand2 i_1942505(.A(n_3341599), .B(n_2391655), .Z(n_3351598));
notech_nand2 i_1952504(.A(i_psram_sub_mem_addr[10]), .B(n_3311600), .Z(n_3321597
));
notech_nand2 i_1962503(.A(n_3321597), .B(n_3351598), .Z(n_3331596));
notech_inv i_1972502(.A(n_3331596), .Z(i_psram_sub_function_plus_2[10])
);
notech_inv i_1982501(.A(n_2401654), .Z(n_3361595));
notech_inv i_1992500(.A(i_psram_sub_mem_addr[11]), .Z(n_3391594));
notech_nand2 i_2002499(.A(n_3391594), .B(n_2401654), .Z(n_3401593));
notech_nand2 i_2012498(.A(i_psram_sub_mem_addr[11]), .B(n_3361595), .Z(n_3371592
));
notech_nand2 i_2022497(.A(n_3371592), .B(n_3401593), .Z(n_3381591));
notech_inv i_2032496(.A(n_3381591), .Z(i_psram_sub_function_plus_2[11])
);
notech_inv i_2042495(.A(n_241), .Z(n_3411590));
notech_inv i_2052494(.A(i_psram_sub_mem_addr[12]), .Z(n_3441589));
notech_nand2 i_2062493(.A(n_3441589), .B(n_241), .Z(n_3451588));
notech_nand2 i_2072492(.A(i_psram_sub_mem_addr[12]), .B(n_3411590), .Z(n_3421587
));
notech_nand2 i_2082491(.A(n_3421587), .B(n_3451588), .Z(n_3431586));
notech_inv i_2092490(.A(n_3431586), .Z(i_psram_sub_function_plus_2[12])
);
notech_inv i_2102489(.A(n_2421653), .Z(n_3461585));
notech_inv i_2112488(.A(i_psram_sub_mem_addr[13]), .Z(n_3491584));
notech_nand2 i_2122487(.A(n_3491584), .B(n_2421653), .Z(n_3501583));
notech_nand2 i_2132486(.A(i_psram_sub_mem_addr[13]), .B(n_3461585), .Z(n_3471582
));
notech_nand2 i_2142485(.A(n_3471582), .B(n_3501583), .Z(n_3481581));
notech_inv i_2152484(.A(n_3481581), .Z(i_psram_sub_function_plus_2[13])
);
notech_inv i_2162483(.A(n_2431652), .Z(n_3511580));
notech_inv i_2172482(.A(i_psram_sub_mem_addr[14]), .Z(n_3541579));
notech_nand2 i_2182481(.A(n_3541579), .B(n_2431652), .Z(n_3551578));
notech_nand2 i_2192480(.A(i_psram_sub_mem_addr[14]), .B(n_3511580), .Z(n_3521577
));
notech_nand2 i_2202479(.A(n_3521577), .B(n_3551578), .Z(n_3531576));
notech_inv i_2212478(.A(n_3531576), .Z(i_psram_sub_function_plus_2[14])
);
notech_inv i_2222477(.A(n_2441651), .Z(n_3561575));
notech_inv i_2232476(.A(i_psram_sub_mem_addr[15]), .Z(n_3591574));
notech_nand2 i_2242475(.A(n_3591574), .B(n_2441651), .Z(n_3601573));
notech_nand2 i_2252474(.A(i_psram_sub_mem_addr[15]), .B(n_3561575), .Z(n_3571572
));
notech_nand2 i_2262473(.A(n_3571572), .B(n_3601573), .Z(n_3581571));
notech_inv i_2272472(.A(n_3581571), .Z(i_psram_sub_function_plus_2[15])
);
notech_inv i_2282471(.A(n_2821650), .Z(n_3611570));
notech_inv i_2292470(.A(i_psram_sub_mem_addr[16]), .Z(n_3641569));
notech_nand2 i_2302469(.A(n_3641569), .B(n_2821650), .Z(n_3651568));
notech_nand2 i_2312468(.A(i_psram_sub_mem_addr[16]), .B(n_3611570), .Z(n_3621567
));
notech_nand2 i_2322467(.A(n_3621567), .B(n_3651568), .Z(n_3631566));
notech_inv i_2332466(.A(n_3631566), .Z(i_psram_sub_function_plus_2[16])
);
notech_inv i_2342465(.A(n_2461649), .Z(n_3661565));
notech_inv i_2352464(.A(i_psram_sub_mem_addr[17]), .Z(n_3691564));
notech_nand2 i_2362463(.A(n_3691564), .B(n_2461649), .Z(n_3701563));
notech_nand2 i_2372462(.A(i_psram_sub_mem_addr[17]), .B(n_3661565), .Z(n_3671562
));
notech_nand2 i_2382461(.A(n_3671562), .B(n_3701563), .Z(n_3681561));
notech_inv i_2392460(.A(n_3681561), .Z(i_psram_sub_function_plus_2[17])
);
notech_inv i_2402459(.A(n_2471648), .Z(n_3711560));
notech_inv i_2412458(.A(i_psram_sub_mem_addr[18]), .Z(n_3741559));
notech_nand2 i_2422457(.A(n_3741559), .B(n_2471648), .Z(n_3751558));
notech_nand2 i_2432456(.A(i_psram_sub_mem_addr[18]), .B(n_3711560), .Z(n_3721557
));
notech_nand2 i_2442455(.A(n_3721557), .B(n_3751558), .Z(n_3731556));
notech_inv i_2452454(.A(n_3731556), .Z(i_psram_sub_function_plus_2[18])
);
notech_inv i_2462453(.A(n_2481647), .Z(n_3761555));
notech_inv i_2472452(.A(i_psram_sub_mem_addr[19]), .Z(n_3791554));
notech_nand2 i_2482451(.A(n_3791554), .B(n_2481647), .Z(n_3801553));
notech_nand2 i_2492450(.A(i_psram_sub_mem_addr[19]), .B(n_3761555), .Z(n_3771552
));
notech_nand2 i_2502449(.A(n_3771552), .B(n_3801553), .Z(n_3781551));
notech_inv i_2512448(.A(n_3781551), .Z(i_psram_sub_function_plus_2[19])
);
notech_inv i_2522447(.A(n_2491646), .Z(n_381));
notech_inv i_2532446(.A(i_psram_sub_mem_addr[20]), .Z(n_384));
notech_nand2 i_2542445(.A(n_384), .B(n_2491646), .Z(n_385));
notech_nand2 i_2552444(.A(i_psram_sub_mem_addr[20]), .B(n_381), .Z(n_382
));
notech_nand2 i_2562443(.A(n_382), .B(n_385), .Z(n_383));
notech_inv i_2572442(.A(n_383), .Z(i_psram_sub_function_plus_2[20]));
notech_inv i_258(.A(n_250), .Z(n_3861550));
notech_inv i_259(.A(i_psram_sub_mem_addr[21]), .Z(n_3891549));
notech_nand2 i_260(.A(n_3891549), .B(n_250), .Z(n_3901548));
notech_nand2 i_261(.A(i_psram_sub_mem_addr[21]), .B(n_3861550), .Z(n_3871547
));
notech_nand2 i_262(.A(n_3871547), .B(n_3901548), .Z(n_3881546));
notech_inv i_263(.A(n_3881546), .Z(i_psram_sub_function_plus_2[21]));
notech_inv i_2642441(.A(n_251), .Z(n_3911545));
notech_inv i_2652440(.A(i_psram_sub_mem_addr[22]), .Z(n_3941544));
notech_nand2 i_2662439(.A(n_3941544), .B(n_251), .Z(n_3951543));
notech_nand2 i_2672438(.A(i_psram_sub_mem_addr[22]), .B(n_3911545), .Z(n_3921542
));
notech_nand2 i_2682437(.A(n_3921542), .B(n_3951543), .Z(n_3931541));
notech_inv i_269(.A(n_3931541), .Z(i_psram_sub_function_plus_2[22]));
notech_inv i_122436(.A(n_2491525), .Z(n_3711414));
notech_inv i_172435(.A(n_4181343), .Z(n_4691274));
notech_inv i_492434(.A(n_2421532), .Z(n_3631422));
notech_inv i_591707(.A(n_2421532), .Z(n_6251413));
notech_inv i_592433(.A(i_psram_sub_axi_awaddr[1]), .Z(n_2651524));
notech_inv i_602432(.A(i_psram_sub_axi_awaddr[10]), .Z(n_2741515));
notech_inv i_611706(.A(n_6421389), .Z(n_6901309));
notech_inv i_612431(.A(i_psram_sub_axi_awaddr[11]), .Z(n_2751514));
notech_inv i_621705(.A(i_psram_sub_axi_awaddr[11]), .Z(n_6021456));
notech_inv i_622430(.A(i_psram_sub_axi_awaddr[12]), .Z(n_2761513));
notech_inv i_631704(.A(n_6011455), .Z(n_6491378));
notech_inv i_632429(.A(i_psram_sub_axi_awaddr[13]), .Z(n_2771512));
notech_inv i_641703(.A(i_psram_sub_axi_awaddr[13]), .Z(n_6061450));
notech_inv i_642428(.A(i_psram_sub_axi_awaddr[14]), .Z(n_2781511));
notech_inv i_651702(.A(n_6891308), .Z(n_7371232));
notech_inv i_652427(.A(i_psram_sub_axi_awaddr[15]), .Z(n_2791510));
notech_inv i_661701(.A(i_psram_sub_axi_awaddr[15]), .Z(n_6101444));
notech_inv i_662426(.A(i_psram_sub_axi_awaddr[16]), .Z(n_2801509));
notech_inv i_671700(.A(n_6091443), .Z(n_6571366));
notech_inv i_672425(.A(i_psram_sub_axi_awaddr[17]), .Z(n_2811508));
notech_inv i_681699(.A(i_psram_sub_axi_awaddr[17]), .Z(n_6141438));
notech_inv i_682424(.A(i_psram_sub_axi_awaddr[18]), .Z(n_2821507));
notech_inv i_691698(.A(n_6581365), .Z(n_7061285));
notech_inv i_692423(.A(i_psram_sub_axi_awaddr[19]), .Z(n_2831506));
notech_inv i_701697(.A(i_psram_sub_axi_awaddr[19]), .Z(n_6181432));
notech_inv i_702422(.A(i_psram_sub_axi_awaddr[20]), .Z(n_2841505));
notech_inv i_711696(.A(n_6171431), .Z(n_6651354));
notech_inv i_711695(.A(i_psram_sub_axi_awaddr[21]), .Z(n_2851504));
notech_inv i_741694(.A(i_psram_sub_axi_awaddr[21]), .Z(n_6221426));
notech_inv i_741693(.A(i_psram_sub_axi_awaddr[22]), .Z(n_2861503));
notech_inv i_741692(.A(n_4171344), .Z(n_4681275));
notech_inv i_761691(.A(n_6401392), .Z(n_6881312));
notech_inv i_761690(.A(i_psram_sub_axi_awaddr[10]), .Z(n_6001459));
notech_inv i_761689(.A(n_5991458), .Z(n_6471381));
notech_inv i_761688(.A(i_psram_sub_axi_awaddr[12]), .Z(n_6041453));
notech_inv i_761687(.A(n_6871311), .Z(n_7351235));
notech_inv i_761686(.A(i_psram_sub_axi_awaddr[14]), .Z(n_6081447));
notech_inv i_761685(.A(n_6071446), .Z(n_6551369));
notech_inv i_761684(.A(i_psram_sub_axi_awaddr[16]), .Z(n_6121441));
notech_inv i_761683(.A(n_6561368), .Z(n_7041288));
notech_inv i_761682(.A(i_psram_sub_axi_awaddr[18]), .Z(n_6161435));
notech_inv i_761681(.A(n_6151434), .Z(n_6631357));
notech_inv i_761680(.A(i_psram_sub_axi_awaddr[20]), .Z(n_6201429));
notech_inv i_741679(.A(n_4671276), .Z(n_5221224));
notech_inv i_761678(.A(n_5971461), .Z(n_6451384));
notech_inv i_761677(.A(n_6851314), .Z(n_7331238));
notech_inv i_761676(.A(n_6051449), .Z(n_6531372));
notech_inv i_761675(.A(n_6541371), .Z(n_7021291));
notech_inv i_761674(.A(n_6131437), .Z(n_6611360));
notech_inv i_741673(.A(n_3701415), .Z(n_4191342));
notech_inv i_741672(.A(n_4661277), .Z(n_5211225));
notech_inv i_741671(.A(n_3641421), .Z(n_4111350));
notech_inv i_761670(.A(n_5951463), .Z(n_6431387));
notech_inv i_761669(.A(n_6831317), .Z(n_7311241));
notech_inv i_761668(.A(n_6031452), .Z(n_6511375));
notech_inv i_761667(.A(n_6521374), .Z(n_7001294));
notech_inv i_761666(.A(n_6111440), .Z(n_6591363));
notech_inv i_741665(.A(n_4651278), .Z(n_5201226));
notech_inv i_761664(.A(n_6811320), .Z(n_7291244));
notech_inv i_761663(.A(n_6501377), .Z(n_6981297));
notech_inv i_761662(.A(n_4641279), .Z(n_7441213));
notech_inv i_761661(.A(n_6791323), .Z(n_7271247));
notech_inv i_761660(.A(n_6481380), .Z(n_6961300));
notech_inv i_741659(.A(n_2491525), .Z(n_4711273));
notech_inv i_761658(.A(n_6461383), .Z(n_6941303));
notech_inv i_762421(.A(n_6441386), .Z(n_6921306));
notech_inv i_741657(.A(n_2941500), .Z(n_7671193));
notech_inv i_742420(.A(i_psram_sub_axi_awaddr[1]), .Z(n_7621194));
notech_inv i_1250(.A(i_psram_sub_axi_awaddr[0]), .Z(n_7571195));
notech_inv i_22419(.A(s00_axi_awlen[0]), .Z(n_2181540));
notech_inv i_32418(.A(s00_axi_awlen[1]), .Z(n_2191539));
notech_inv i_42417(.A(s00_axi_awlen[2]), .Z(n_2201538));
notech_inv i_52416(.A(s00_axi_awlen[3]), .Z(n_2211537));
notech_inv i_62415(.A(s00_axi_awlen[4]), .Z(n_2221536));
notech_inv i_72414(.A(s00_axi_awlen[5]), .Z(n_2231535));
notech_inv i_82413(.A(s00_axi_awlen[6]), .Z(n_2241534));
notech_inv i_92412(.A(s00_axi_awlen[7]), .Z(n_2251533));
notech_nor2 i_262411(.A(i_psram_sub_axi_awaddr[2]), .B(n_2181540), .Z(n_2421532
));
notech_nor2 i_272410(.A(i_psram_sub_axi_awaddr[3]), .B(n_2191539), .Z(n_2431531
));
notech_nor2 i_282409(.A(i_psram_sub_axi_awaddr[4]), .B(n_2201538), .Z(n_2441530
));
notech_nor2 i_292408(.A(i_psram_sub_axi_awaddr[5]), .B(n_2211537), .Z(n_2451529
));
notech_nor2 i_302407(.A(i_psram_sub_axi_awaddr[6]), .B(n_2221536), .Z(n_2461528
));
notech_nor2 i_312406(.A(i_psram_sub_axi_awaddr[7]), .B(n_2231535), .Z(n_2471527
));
notech_nor2 i_322405(.A(i_psram_sub_axi_awaddr[8]), .B(n_2241534), .Z(n_2481526
));
notech_nor2 i_332404(.A(i_psram_sub_axi_awaddr[9]), .B(n_2251533), .Z(n_2491525
));
notech_nand2 i_502403(.A(i_psram_sub_axi_awaddr[2]), .B(n_2181540), .Z(n_2661523
));
notech_nand2 i_512402(.A(i_psram_sub_axi_awaddr[3]), .B(n_2191539), .Z(n_2671522
));
notech_nand2 i_522401(.A(i_psram_sub_axi_awaddr[4]), .B(n_2201538), .Z(n_2681521
));
notech_nand2 i_532400(.A(i_psram_sub_axi_awaddr[5]), .B(n_2211537), .Z(n_2691520
));
notech_nand2 i_542399(.A(i_psram_sub_axi_awaddr[6]), .B(n_2221536), .Z(n_2701519
));
notech_nand2 i_552398(.A(i_psram_sub_axi_awaddr[7]), .B(n_2231535), .Z(n_2711518
));
notech_nand2 i_562397(.A(i_psram_sub_axi_awaddr[8]), .B(n_2241534), .Z(n_2721517
));
notech_nand2 i_572396(.A(i_psram_sub_axi_awaddr[9]), .B(n_2251533), .Z(n_2731516
));
notech_inv i_722395(.A(i_psram_sub_axi_awaddr[0]), .Z(n_2881502));
notech_inv i_772394(.A(n_2421532), .Z(n_2931501));
notech_nand2 i_782393(.A(n_2931501), .B(n_2661523), .Z(n_2941500));
notech_inv i_792392(.A(n_2431531), .Z(n_2951499));
notech_nand2 i_802391(.A(n_2951499), .B(n_2671522), .Z(n_2961498));
notech_inv i_812390(.A(n_2441530), .Z(n_2971497));
notech_nand2 i_822389(.A(n_2971497), .B(n_2681521), .Z(n_2981496));
notech_inv i_832388(.A(n_2451529), .Z(n_2991495));
notech_nand2 i_842387(.A(n_2991495), .B(n_2691520), .Z(n_3001494));
notech_inv i_852386(.A(n_2461528), .Z(n_3011493));
notech_nand2 i_862385(.A(n_3011493), .B(n_2701519), .Z(n_3021492));
notech_inv i_872384(.A(n_2471527), .Z(n_3031491));
notech_nand2 i_882383(.A(n_3031491), .B(n_2711518), .Z(n_3041490));
notech_inv i_892382(.A(n_2481526), .Z(n_3051489));
notech_nand2 i_902381(.A(n_3051489), .B(n_2721517), .Z(n_3061488));
notech_inv i_912380(.A(n_2491525), .Z(n_3071487));
notech_nand2 i_922379(.A(n_3071487), .B(n_2731516), .Z(n_3081486));
notech_or2 i_3602378(.A(n_2421532), .B(n_2651524), .Z(n_5821485));
notech_and2 i_3612377(.A(n_5821485), .B(n_2661523), .Z(n_5811484));
notech_inv i_3622376(.A(n_5811484), .Z(n_3391483));
notech_or2 i_3632375(.A(n_2431531), .B(n_2661523), .Z(n_5841482));
notech_and2 i_3642374(.A(n_5841482), .B(n_2671522), .Z(n_5831481));
notech_inv i_3652373(.A(n_5831481), .Z(n_3401480));
notech_or2 i_3662372(.A(n_2441530), .B(n_2671522), .Z(n_5861479));
notech_and2 i_3672371(.A(n_5861479), .B(n_2681521), .Z(n_5851478));
notech_inv i_3682370(.A(n_5851478), .Z(n_3411477));
notech_or2 i_3692369(.A(n_2451529), .B(n_2681521), .Z(n_5881476));
notech_and2 i_3702368(.A(n_5881476), .B(n_2691520), .Z(n_5871475));
notech_inv i_3712367(.A(n_5871475), .Z(n_3421474));
notech_or2 i_3722366(.A(n_2461528), .B(n_2691520), .Z(n_5901473));
notech_and2 i_3732365(.A(n_5901473), .B(n_2701519), .Z(n_5891472));
notech_inv i_3742364(.A(n_5891472), .Z(n_3431471));
notech_or2 i_3752363(.A(n_2471527), .B(n_2701519), .Z(n_5921470));
notech_and2 i_3762362(.A(n_5921470), .B(n_2711518), .Z(n_5911469));
notech_inv i_3772361(.A(n_5911469), .Z(n_3441468));
notech_or2 i_3782360(.A(n_2481526), .B(n_2711518), .Z(n_5941467));
notech_and2 i_3792359(.A(n_5941467), .B(n_2721517), .Z(n_5931466));
notech_inv i_3802358(.A(n_5931466), .Z(n_3451465));
notech_or2 i_3812357(.A(n_2491525), .B(n_2721517), .Z(n_5961464));
notech_and2 i_3822356(.A(n_5961464), .B(n_2731516), .Z(n_5951463));
notech_inv i_3832355(.A(n_5951463), .Z(n_3461462));
notech_and2 i_3852354(.A(n_2731516), .B(n_2741515), .Z(n_5971461));
notech_inv i_3862353(.A(n_5971461), .Z(n_3471460));
notech_and2 i_3882352(.A(n_6001459), .B(n_2751514), .Z(n_5991458));
notech_inv i_3892351(.A(n_5991458), .Z(n_3481457));
notech_and2 i_3912350(.A(n_6021456), .B(n_2761513), .Z(n_6011455));
notech_inv i_3922349(.A(n_6011455), .Z(n_3491454));
notech_and2 i_3942348(.A(n_6041453), .B(n_2771512), .Z(n_6031452));
notech_inv i_3952347(.A(n_6031452), .Z(n_3501451));
notech_and2 i_3972346(.A(n_6061450), .B(n_2781511), .Z(n_6051449));
notech_inv i_3982345(.A(n_6051449), .Z(n_3511448));
notech_and2 i_4002344(.A(n_6081447), .B(n_2791510), .Z(n_6071446));
notech_inv i_4012343(.A(n_6071446), .Z(n_3521445));
notech_and2 i_4032342(.A(n_6101444), .B(n_2801509), .Z(n_6091443));
notech_inv i_4042341(.A(n_6091443), .Z(n_3531442));
notech_and2 i_4062340(.A(n_6121441), .B(n_2811508), .Z(n_6111440));
notech_inv i_4072339(.A(n_6111440), .Z(n_3541439));
notech_and2 i_4092338(.A(n_6141438), .B(n_2821507), .Z(n_6131437));
notech_inv i_4102337(.A(n_6131437), .Z(n_3551436));
notech_and2 i_4122336(.A(n_6161435), .B(n_2831506), .Z(n_6151434));
notech_inv i_4132335(.A(n_6151434), .Z(n_3561433));
notech_and2 i_4152334(.A(n_6181432), .B(n_2841505), .Z(n_6171431));
notech_inv i_4162333(.A(n_6171431), .Z(n_3571430));
notech_and2 i_4182332(.A(n_6201429), .B(n_2851504), .Z(n_6191428));
notech_inv i_4192331(.A(n_6191428), .Z(n_3581427));
notech_and2 i_4212330(.A(n_6221426), .B(n_2861503), .Z(n_6211425));
notech_inv i_4222329(.A(n_6211425), .Z(n_3591424));
notech_inv i_1442328(.A(n_2881502), .Z(n_3601423));
notech_nor2 i_1482327(.A(n_2421532), .B(n_2431531), .Z(n_3641421));
notech_nor2 i_1492326(.A(n_2431531), .B(n_2441530), .Z(n_3651420));
notech_nor2 i_1502325(.A(n_2441530), .B(n_2451529), .Z(n_3661419));
notech_nor2 i_1512324(.A(n_2451529), .B(n_2461528), .Z(n_3671418));
notech_nor2 i_1522323(.A(n_2461528), .B(n_2471527), .Z(n_3681417));
notech_nor2 i_1532322(.A(n_2471527), .B(n_2481526), .Z(n_3691416));
notech_nor2 i_1542321(.A(n_2481526), .B(n_2491525), .Z(n_3701415));
notech_or2 i_4272320(.A(n_6251413), .B(n_3391483), .Z(n_6261412));
notech_inv i_4282319(.A(n_6261412), .Z(n_3861411));
notech_or2 i_4302318(.A(n_3641421), .B(n_3401480), .Z(n_6281410));
notech_inv i_4312317(.A(n_6281410), .Z(n_3871409));
notech_and2 i_4322316(.A(n_3651420), .B(n_3391483), .Z(n_6291408));
notech_or2 i_4332315(.A(n_6291408), .B(n_3411477), .Z(n_6301407));
notech_inv i_4342314(.A(n_6301407), .Z(n_3881406));
notech_and2 i_4352313(.A(n_3661419), .B(n_3401480), .Z(n_6311405));
notech_or2 i_4362312(.A(n_6311405), .B(n_3421474), .Z(n_6321404));
notech_inv i_4372311(.A(n_6321404), .Z(n_3891403));
notech_and2 i_4382310(.A(n_3671418), .B(n_3411477), .Z(n_6331402));
notech_or2 i_4392309(.A(n_6331402), .B(n_3431471), .Z(n_6341401));
notech_inv i_4402308(.A(n_6341401), .Z(n_3901400));
notech_and2 i_4412307(.A(n_3681417), .B(n_3421474), .Z(n_6351399));
notech_or2 i_4422306(.A(n_6351399), .B(n_3441468), .Z(n_6361398));
notech_inv i_4432305(.A(n_6361398), .Z(n_3911397));
notech_and2 i_4442304(.A(n_3691416), .B(n_3431471), .Z(n_6371396));
notech_or2 i_4452303(.A(n_6371396), .B(n_3451465), .Z(n_6381395));
notech_inv i_4462302(.A(n_6381395), .Z(n_3921394));
notech_and2 i_4472301(.A(n_3701415), .B(n_3441468), .Z(n_6391393));
notech_or2 i_4482300(.A(n_6391393), .B(n_3461462), .Z(n_6401392));
notech_inv i_4492299(.A(n_6401392), .Z(n_3931391));
notech_and2 i_4502298(.A(n_3711414), .B(n_3451465), .Z(n_6411390));
notech_or2 i_4512297(.A(n_6411390), .B(n_3471460), .Z(n_6421389));
notech_inv i_4522296(.A(n_6421389), .Z(n_3941388));
notech_or2 i_4542295(.A(n_6431387), .B(n_3481457), .Z(n_6441386));
notech_inv i_4552294(.A(n_6441386), .Z(n_3951385));
notech_or2 i_4572293(.A(n_6451384), .B(n_3491454), .Z(n_6461383));
notech_inv i_4582292(.A(n_6461383), .Z(n_3961382));
notech_or2 i_4602291(.A(n_6471381), .B(n_3501451), .Z(n_6481380));
notech_inv i_4612290(.A(n_6481380), .Z(n_3971379));
notech_or2 i_4632289(.A(n_6491378), .B(n_3511448), .Z(n_6501377));
notech_inv i_4642288(.A(n_6501377), .Z(n_3981376));
notech_or2 i_4662287(.A(n_6511375), .B(n_3521445), .Z(n_6521374));
notech_inv i_4672286(.A(n_6521374), .Z(n_3991373));
notech_or2 i_4692285(.A(n_6531372), .B(n_3531442), .Z(n_6541371));
notech_inv i_4702284(.A(n_6541371), .Z(n_4001370));
notech_or2 i_4722283(.A(n_6551369), .B(n_3541439), .Z(n_6561368));
notech_inv i_4732282(.A(n_6561368), .Z(n_4011367));
notech_or2 i_4752281(.A(n_6571366), .B(n_3551436), .Z(n_6581365));
notech_inv i_4762280(.A(n_6581365), .Z(n_4021364));
notech_or2 i_4782279(.A(n_6591363), .B(n_3561433), .Z(n_6601362));
notech_inv i_4792278(.A(n_6601362), .Z(n_4031361));
notech_or2 i_4812277(.A(n_6611360), .B(n_3571430), .Z(n_6621359));
notech_inv i_4822276(.A(n_6621359), .Z(n_4041358));
notech_or2 i_4842275(.A(n_6631357), .B(n_3581427), .Z(n_6641356));
notech_inv i_4852274(.A(n_6641356), .Z(n_4051355));
notech_or2 i_4872273(.A(n_6651354), .B(n_3591424), .Z(n_6661353));
notech_inv i_4882272(.A(n_6661353), .Z(n_4061352));
notech_inv i_1912271(.A(n_3601423), .Z(n_4071351));
notech_nand2 i_1962270(.A(n_3631422), .B(n_3651420), .Z(n_4121349));
notech_nand2 i_1972269(.A(n_3641421), .B(n_3661419), .Z(n_4131348));
notech_nand2 i_1982268(.A(n_3651420), .B(n_3671418), .Z(n_4141347));
notech_nand2 i_1992267(.A(n_3661419), .B(n_3681417), .Z(n_4151346));
notech_nand2 i_2002266(.A(n_3671418), .B(n_3691416), .Z(n_4161345));
notech_nand2 i_2012265(.A(n_3681417), .B(n_3701415), .Z(n_4171344));
notech_nand2 i_2022264(.A(n_3691416), .B(n_3711414), .Z(n_4181343));
notech_inv i_2172263(.A(n_3861411), .Z(n_4331341));
notech_or2 i_4892262(.A(n_4111350), .B(n_4071351), .Z(n_6681340));
notech_and2 i_4902261(.A(n_6681340), .B(n_3871409), .Z(n_6671339));
notech_inv i_4912260(.A(n_6671339), .Z(n_4341338));
notech_and2 i_4932259(.A(n_4121349), .B(n_3881406), .Z(n_6691337));
notech_inv i_4942258(.A(n_6691337), .Z(n_4351336));
notech_and2 i_4962257(.A(n_4131348), .B(n_3891403), .Z(n_6711335));
notech_inv i_4972256(.A(n_6711335), .Z(n_4361334));
notech_or2 i_4982255(.A(n_4141347), .B(n_3861411), .Z(n_6741333));
notech_and2 i_4992254(.A(n_6741333), .B(n_3901400), .Z(n_6731332));
notech_inv i_5002253(.A(n_6731332), .Z(n_4371331));
notech_or2 i_5012252(.A(n_4151346), .B(n_3871409), .Z(n_6761330));
notech_and2 i_5022251(.A(n_6761330), .B(n_3911397), .Z(n_6751329));
notech_inv i_5032250(.A(n_6751329), .Z(n_4381328));
notech_or2 i_5042249(.A(n_4161345), .B(n_3881406), .Z(n_6781327));
notech_and2 i_5052248(.A(n_6781327), .B(n_3921394), .Z(n_6771326));
notech_inv i_5062247(.A(n_6771326), .Z(n_4391325));
notech_or2 i_5072246(.A(n_4171344), .B(n_3891403), .Z(n_6801324));
notech_and2 i_5082245(.A(n_6801324), .B(n_3931391), .Z(n_6791323));
notech_inv i_5092244(.A(n_6791323), .Z(n_4401322));
notech_or2 i_5102243(.A(n_4181343), .B(n_3901400), .Z(n_6821321));
notech_and2 i_5112242(.A(n_6821321), .B(n_3941388), .Z(n_6811320));
notech_inv i_5122241(.A(n_6811320), .Z(n_4411319));
notech_or2 i_5132240(.A(n_4191342), .B(n_3911397), .Z(n_6841318));
notech_and2 i_5142239(.A(n_6841318), .B(n_3951385), .Z(n_6831317));
notech_inv i_5152238(.A(n_6831317), .Z(n_4421316));
notech_or2 i_5162237(.A(n_2491525), .B(n_3921394), .Z(n_6861315));
notech_and2 i_5172236(.A(n_6861315), .B(n_3961382), .Z(n_6851314));
notech_inv i_5182235(.A(n_6851314), .Z(n_4431313));
notech_and2 i_5202234(.A(n_6881312), .B(n_3971379), .Z(n_6871311));
notech_inv i_5212233(.A(n_6871311), .Z(n_4441310));
notech_and2 i_5232232(.A(n_6901309), .B(n_3981376), .Z(n_6891308));
notech_inv i_5242231(.A(n_6891308), .Z(n_4451307));
notech_and2 i_5262230(.A(n_6921306), .B(n_3991373), .Z(n_6911305));
notech_inv i_5272229(.A(n_6911305), .Z(n_4461304));
notech_and2 i_5292228(.A(n_6941303), .B(n_4001370), .Z(n_6931302));
notech_inv i_5302227(.A(n_6931302), .Z(n_4471301));
notech_and2 i_5322226(.A(n_6961300), .B(n_4011367), .Z(n_6951299));
notech_inv i_5332225(.A(n_6951299), .Z(n_4481298));
notech_and2 i_5352224(.A(n_6981297), .B(n_4021364), .Z(n_6971296));
notech_inv i_5362223(.A(n_6971296), .Z(n_4491295));
notech_and2 i_5382222(.A(n_7001294), .B(n_4031361), .Z(n_6991293));
notech_inv i_5392221(.A(n_6991293), .Z(n_4501292));
notech_and2 i_5412220(.A(n_7021291), .B(n_4041358), .Z(n_7011290));
notech_inv i_5422219(.A(n_7011290), .Z(n_4511289));
notech_and2 i_5442218(.A(n_7041288), .B(n_4051355), .Z(n_7031287));
notech_inv i_5452217(.A(n_7031287), .Z(n_4521286));
notech_and2 i_5472216(.A(n_7061285), .B(n_4061352), .Z(n_7051284));
notech_inv i_5482215(.A(n_7051284), .Z(n_4531283));
notech_inv i_2382214(.A(n_4071351), .Z(n_4541282));
notech_nor2 i_2462213(.A(n_4111350), .B(n_4151346), .Z(n_4621281));
notech_nor2 i_2472212(.A(n_4121349), .B(n_4161345), .Z(n_4631280));
notech_nor2 i_2482211(.A(n_4131348), .B(n_4171344), .Z(n_4641279));
notech_nor2 i_2492210(.A(n_4141347), .B(n_4181343), .Z(n_4651278));
notech_nor2 i_2502209(.A(n_4151346), .B(n_4191342), .Z(n_4661277));
notech_nor2 i_2512208(.A(n_4161345), .B(n_2491525), .Z(n_4671276));
notech_inv i_2642207(.A(n_4331341), .Z(n_4801272));
notech_inv i_2652206(.A(n_4341338), .Z(n_4811271));
notech_inv i_2662205(.A(n_4351336), .Z(n_4821270));
notech_inv i_2672204(.A(n_4361334), .Z(n_4831269));
notech_inv i_2682203(.A(n_4371331), .Z(n_4841268));
notech_and2 i_5492202(.A(n_4621281), .B(n_4541282), .Z(n_7071267));
notech_or2 i_5502201(.A(n_7071267), .B(n_4381328), .Z(n_7081266));
notech_or2 i_5532200(.A(n_4631280), .B(n_4391325), .Z(n_7101265));
notech_or2 i_5562199(.A(n_4641279), .B(n_4401322), .Z(n_7121264));
notech_and2 i_5582198(.A(n_4651278), .B(n_4331341), .Z(n_7131263));
notech_or2 i_5592197(.A(n_7131263), .B(n_4411319), .Z(n_7141262));
notech_and2 i_5612196(.A(n_4661277), .B(n_4341338), .Z(n_7151261));
notech_or2 i_5622195(.A(n_7151261), .B(n_4421316), .Z(n_7161260));
notech_and2 i_5642194(.A(n_4671276), .B(n_4351336), .Z(n_7171259));
notech_or2 i_5652193(.A(n_7171259), .B(n_4431313), .Z(n_7181258));
notech_and2 i_5672192(.A(n_4681275), .B(n_4361334), .Z(n_7191257));
notech_or2 i_5682191(.A(n_7191257), .B(n_4441310), .Z(n_7201256));
notech_and2 i_5702190(.A(n_4691274), .B(n_4371331), .Z(n_7211255));
notech_or2 i_5712189(.A(n_7211255), .B(n_4451307), .Z(n_7221254));
notech_and2 i_5732188(.A(n_3701415), .B(n_4381328), .Z(n_7231253));
notech_or2 i_5742187(.A(n_7231253), .B(n_4461304), .Z(n_7241252));
notech_inv i_5752186(.A(n_7241252), .Z(n_4931251));
notech_and2 i_5762185(.A(n_4711273), .B(n_4391325), .Z(n_7251250));
notech_or2 i_5772184(.A(n_7251250), .B(n_4471301), .Z(n_7261249));
notech_inv i_5782183(.A(n_7261249), .Z(n_4941248));
notech_or2 i_5802182(.A(n_7271247), .B(n_4481298), .Z(n_7281246));
notech_inv i_5812181(.A(n_7281246), .Z(n_4951245));
notech_or2 i_5832180(.A(n_7291244), .B(n_4491295), .Z(n_7301243));
notech_inv i_5842179(.A(n_7301243), .Z(n_4961242));
notech_or2 i_5862178(.A(n_7311241), .B(n_4501292), .Z(n_7321240));
notech_inv i_5872177(.A(n_7321240), .Z(n_4971239));
notech_or2 i_5892176(.A(n_7331238), .B(n_4511289), .Z(n_7341237));
notech_inv i_5902175(.A(n_7341237), .Z(n_4981236));
notech_or2 i_5922174(.A(n_7351235), .B(n_4521286), .Z(n_7361234));
notech_inv i_5932173(.A(n_7361234), .Z(n_4991233));
notech_or2 i_5952172(.A(n_7371232), .B(n_4531283), .Z(n_7381231));
notech_inv i_5962171(.A(n_7381231), .Z(n_5001230));
notech_inv i_2852170(.A(n_4541282), .Z(n_5011229));
notech_nand2 i_3012169(.A(n_4621281), .B(n_3701415), .Z(n_5171228));
notech_nand2 i_3022168(.A(n_4631280), .B(n_4711273), .Z(n_5181227));
notech_inv i_3112167(.A(n_4801272), .Z(n_5271223));
notech_inv i_3122166(.A(n_4811271), .Z(n_5281222));
notech_inv i_3132165(.A(n_4821270), .Z(n_5291221));
notech_inv i_3142164(.A(n_4831269), .Z(n_5301220));
notech_inv i_3152163(.A(n_4841268), .Z(n_5311219));
notech_or2 i_5972162(.A(n_5171228), .B(n_5011229), .Z(n_7401218));
notech_and2 i_5982161(.A(n_7401218), .B(n_4931251), .Z(n_7391217));
notech_inv i_5992160(.A(n_7391217), .Z(n_5401216));
notech_and2 i_6012159(.A(n_5181227), .B(n_4941248), .Z(n_7411215));
notech_inv i_6022158(.A(n_7411215), .Z(n_5411214));
notech_and2 i_6042157(.A(n_7441213), .B(n_4951245), .Z(n_7431212));
notech_inv i_6052156(.A(n_7431212), .Z(n_5421211));
notech_or2 i_6062155(.A(n_5201226), .B(n_4801272), .Z(n_7461210));
notech_and2 i_6072154(.A(n_7461210), .B(n_4961242), .Z(n_7451209));
notech_inv i_6082153(.A(n_7451209), .Z(n_5431208));
notech_or2 i_6092152(.A(n_5211225), .B(n_4811271), .Z(n_7481207));
notech_and2 i_6102151(.A(n_7481207), .B(n_4971239), .Z(n_7471206));
notech_inv i_6112150(.A(n_7471206), .Z(n_5441205));
notech_or2 i_6122149(.A(n_5221224), .B(n_4821270), .Z(n_7501204));
notech_and2 i_6132148(.A(n_7501204), .B(n_4981236), .Z(n_7491203));
notech_inv i_6142147(.A(n_7491203), .Z(n_5451202));
notech_or2 i_6152146(.A(n_4171344), .B(n_4831269), .Z(n_7521201));
notech_and2 i_6162145(.A(n_7521201), .B(n_4991233), .Z(n_7511200));
notech_inv i_6172144(.A(n_7511200), .Z(n_5461199));
notech_or2 i_6182143(.A(n_4181343), .B(n_4841268), .Z(n_7541198));
notech_and2 i_6192142(.A(n_7541198), .B(n_5001230), .Z(n_7531197));
notech_inv i_6202141(.A(n_7531197), .Z(n_5471196));
notech_inv i_6262140(.A(n_7571195), .Z(i_psram_sub_function_sub_0[0]));
notech_inv i_6322139(.A(n_7621194), .Z(i_psram_sub_function_sub_0[1]));
notech_inv i_6382138(.A(n_7671193), .Z(i_psram_sub_function_sub_0[2]));
notech_inv i_6392137(.A(n_5271223), .Z(n_7701192));
notech_inv i_6402136(.A(n_2961498), .Z(n_7731191));
notech_nand2 i_6412135(.A(n_7731191), .B(n_5271223), .Z(n_7741190));
notech_nand2 i_6422134(.A(n_2961498), .B(n_7701192), .Z(n_7711189));
notech_nand2 i_6432133(.A(n_7711189), .B(n_7741190), .Z(n_7721188));
notech_inv i_6442132(.A(n_7721188), .Z(i_psram_sub_function_sub_0[3]));
notech_inv i_6452131(.A(n_5281222), .Z(n_7751187));
notech_inv i_6462130(.A(n_2981496), .Z(n_7781186));
notech_nand2 i_6472129(.A(n_7781186), .B(n_5281222), .Z(n_7791185));
notech_nand2 i_6482128(.A(n_2981496), .B(n_7751187), .Z(n_7761184));
notech_nand2 i_6492127(.A(n_7761184), .B(n_7791185), .Z(n_7771183));
notech_inv i_6502126(.A(n_7771183), .Z(i_psram_sub_function_sub_0[4]));
notech_inv i_6512125(.A(n_5291221), .Z(n_7801182));
notech_inv i_6522124(.A(n_3001494), .Z(n_7831181));
notech_nand2 i_6532123(.A(n_7831181), .B(n_5291221), .Z(n_7841180));
notech_nand2 i_6542122(.A(n_3001494), .B(n_7801182), .Z(n_7811179));
notech_nand2 i_6552121(.A(n_7811179), .B(n_7841180), .Z(n_7821178));
notech_inv i_6562120(.A(n_7821178), .Z(i_psram_sub_function_sub_0[5]));
notech_inv i_6572119(.A(n_5301220), .Z(n_7851177));
notech_inv i_6582118(.A(n_3021492), .Z(n_7881176));
notech_nand2 i_6592117(.A(n_7881176), .B(n_5301220), .Z(n_7891175));
notech_nand2 i_6602116(.A(n_3021492), .B(n_7851177), .Z(n_7861174));
notech_nand2 i_6612115(.A(n_7861174), .B(n_7891175), .Z(n_7871173));
notech_inv i_6622114(.A(n_7871173), .Z(i_psram_sub_function_sub_0[6]));
notech_inv i_6632113(.A(n_5311219), .Z(n_7901172));
notech_inv i_6642112(.A(n_3041490), .Z(n_7931171));
notech_nand2 i_6652111(.A(n_7931171), .B(n_5311219), .Z(n_7941170));
notech_nand2 i_6662110(.A(n_3041490), .B(n_7901172), .Z(n_7911169));
notech_nand2 i_6672109(.A(n_7911169), .B(n_7941170), .Z(n_7921168));
notech_inv i_6682108(.A(n_7921168), .Z(i_psram_sub_function_sub_0[7]));
notech_inv i_6692107(.A(n_7081266), .Z(n_7951167));
notech_inv i_6702106(.A(n_3061488), .Z(n_7981166));
notech_nand2 i_6712105(.A(n_7981166), .B(n_7081266), .Z(n_7991165));
notech_nand2 i_6722104(.A(n_3061488), .B(n_7951167), .Z(n_7961164));
notech_nand2 i_6732103(.A(n_7961164), .B(n_7991165), .Z(n_7971163));
notech_inv i_6742102(.A(n_7971163), .Z(i_psram_sub_function_sub_0[8]));
notech_inv i_6752101(.A(n_7101265), .Z(n_8001162));
notech_inv i_6762100(.A(n_3081486), .Z(n_8031161));
notech_nand2 i_6772099(.A(n_8031161), .B(n_7101265), .Z(n_8041160));
notech_nand2 i_6782098(.A(n_3081486), .B(n_8001162), .Z(n_8011159));
notech_nand2 i_6792097(.A(n_8011159), .B(n_8041160), .Z(n_8021158));
notech_inv i_6802096(.A(n_8021158), .Z(i_psram_sub_function_sub_0[9]));
notech_inv i_6812095(.A(n_7121264), .Z(n_8051157));
notech_inv i_6822094(.A(i_psram_sub_axi_awaddr[10]), .Z(n_8081156));
notech_nand2 i_6832093(.A(n_8081156), .B(n_7121264), .Z(n_8091155));
notech_nand2 i_6842092(.A(i_psram_sub_axi_awaddr[10]), .B(n_8051157), .Z
(n_8061154));
notech_nand2 i_6852091(.A(n_8061154), .B(n_8091155), .Z(n_8071153));
notech_inv i_6862090(.A(n_8071153), .Z(i_psram_sub_function_sub_0[10])
);
notech_inv i_6872089(.A(n_7141262), .Z(n_8101152));
notech_inv i_6882088(.A(i_psram_sub_axi_awaddr[11]), .Z(n_8131151));
notech_nand2 i_6892087(.A(n_8131151), .B(n_7141262), .Z(n_8141150));
notech_nand2 i_6902086(.A(i_psram_sub_axi_awaddr[11]), .B(n_8101152), .Z
(n_8111149));
notech_nand2 i_6912085(.A(n_8111149), .B(n_8141150), .Z(n_8121148));
notech_inv i_6922084(.A(n_8121148), .Z(i_psram_sub_function_sub_0[11])
);
notech_inv i_6932083(.A(n_7161260), .Z(n_8151147));
notech_inv i_6942082(.A(i_psram_sub_axi_awaddr[12]), .Z(n_8181146));
notech_nand2 i_6952081(.A(n_8181146), .B(n_7161260), .Z(n_8191145));
notech_nand2 i_6962080(.A(i_psram_sub_axi_awaddr[12]), .B(n_8151147), .Z
(n_8161144));
notech_nand2 i_6972079(.A(n_8161144), .B(n_8191145), .Z(n_8171143));
notech_inv i_6982078(.A(n_8171143), .Z(i_psram_sub_function_sub_0[12])
);
notech_inv i_6992077(.A(n_7181258), .Z(n_8201142));
notech_inv i_7002076(.A(i_psram_sub_axi_awaddr[13]), .Z(n_8231141));
notech_nand2 i_7012075(.A(n_8231141), .B(n_7181258), .Z(n_8241140));
notech_nand2 i_7022074(.A(i_psram_sub_axi_awaddr[13]), .B(n_8201142), .Z
(n_8211139));
notech_nand2 i_7032073(.A(n_8211139), .B(n_8241140), .Z(n_8221138));
notech_inv i_7042072(.A(n_8221138), .Z(i_psram_sub_function_sub_0[13])
);
notech_inv i_7052071(.A(n_7201256), .Z(n_8251137));
notech_inv i_7062070(.A(i_psram_sub_axi_awaddr[14]), .Z(n_8281136));
notech_nand2 i_7072069(.A(n_8281136), .B(n_7201256), .Z(n_8291135));
notech_nand2 i_7082068(.A(i_psram_sub_axi_awaddr[14]), .B(n_8251137), .Z
(n_8261134));
notech_nand2 i_7092067(.A(n_8261134), .B(n_8291135), .Z(n_8271133));
notech_inv i_7102066(.A(n_8271133), .Z(i_psram_sub_function_sub_0[14])
);
notech_inv i_7112065(.A(n_7221254), .Z(n_8301132));
notech_inv i_7122064(.A(i_psram_sub_axi_awaddr[15]), .Z(n_8331131));
notech_nand2 i_7132063(.A(n_8331131), .B(n_7221254), .Z(n_8341130));
notech_nand2 i_7142062(.A(i_psram_sub_axi_awaddr[15]), .B(n_8301132), .Z
(n_8311129));
notech_nand2 i_7152061(.A(n_8311129), .B(n_8341130), .Z(n_8321128));
notech_inv i_7162060(.A(n_8321128), .Z(i_psram_sub_function_sub_0[15])
);
notech_inv i_7172059(.A(n_5401216), .Z(n_8351127));
notech_inv i_7182058(.A(i_psram_sub_axi_awaddr[16]), .Z(n_8381126));
notech_nand2 i_7192057(.A(n_8381126), .B(n_5401216), .Z(n_8391125));
notech_nand2 i_7202056(.A(i_psram_sub_axi_awaddr[16]), .B(n_8351127), .Z
(n_8361124));
notech_nand2 i_7212055(.A(n_8361124), .B(n_8391125), .Z(n_8371123));
notech_inv i_7222054(.A(n_8371123), .Z(i_psram_sub_function_sub_0[16])
);
notech_inv i_7232053(.A(n_5411214), .Z(n_8401122));
notech_inv i_7242052(.A(i_psram_sub_axi_awaddr[17]), .Z(n_8431121));
notech_nand2 i_7252051(.A(n_8431121), .B(n_5411214), .Z(n_8441120));
notech_nand2 i_7262050(.A(i_psram_sub_axi_awaddr[17]), .B(n_8401122), .Z
(n_8411119));
notech_nand2 i_7272049(.A(n_8411119), .B(n_8441120), .Z(n_8421118));
notech_inv i_7282048(.A(n_8421118), .Z(i_psram_sub_function_sub_0[17])
);
notech_inv i_7292047(.A(n_5421211), .Z(n_8451117));
notech_inv i_7302046(.A(i_psram_sub_axi_awaddr[18]), .Z(n_8481116));
notech_nand2 i_7312045(.A(n_8481116), .B(n_5421211), .Z(n_8491115));
notech_nand2 i_7322044(.A(i_psram_sub_axi_awaddr[18]), .B(n_8451117), .Z
(n_8461114));
notech_nand2 i_7332043(.A(n_8461114), .B(n_8491115), .Z(n_8471113));
notech_inv i_7342042(.A(n_8471113), .Z(i_psram_sub_function_sub_0[18])
);
notech_inv i_7352041(.A(n_5431208), .Z(n_8501112));
notech_inv i_7362040(.A(i_psram_sub_axi_awaddr[19]), .Z(n_8531111));
notech_nand2 i_7372039(.A(n_8531111), .B(n_5431208), .Z(n_8541110));
notech_nand2 i_7382038(.A(i_psram_sub_axi_awaddr[19]), .B(n_8501112), .Z
(n_8511109));
notech_nand2 i_7392037(.A(n_8511109), .B(n_8541110), .Z(n_8521108));
notech_inv i_7402036(.A(n_8521108), .Z(i_psram_sub_function_sub_0[19])
);
notech_inv i_7412035(.A(n_5441205), .Z(n_8551107));
notech_inv i_7422034(.A(i_psram_sub_axi_awaddr[20]), .Z(n_8581106));
notech_nand2 i_7432033(.A(n_8581106), .B(n_5441205), .Z(n_8591105));
notech_nand2 i_7442032(.A(i_psram_sub_axi_awaddr[20]), .B(n_8551107), .Z
(n_8561104));
notech_nand2 i_7452031(.A(n_8561104), .B(n_8591105), .Z(n_8571103));
notech_inv i_7462030(.A(n_8571103), .Z(i_psram_sub_function_sub_0[20])
);
notech_inv i_7472029(.A(n_5451202), .Z(n_8601102));
notech_inv i_7482028(.A(i_psram_sub_axi_awaddr[21]), .Z(n_8631101));
notech_nand2 i_7492027(.A(n_8631101), .B(n_5451202), .Z(n_8641100));
notech_nand2 i_7502026(.A(i_psram_sub_axi_awaddr[21]), .B(n_8601102), .Z
(n_8611099));
notech_nand2 i_7512025(.A(n_8611099), .B(n_8641100), .Z(n_8621098));
notech_inv i_7522024(.A(n_8621098), .Z(i_psram_sub_function_sub_0[21])
);
notech_inv i_7532023(.A(n_5461199), .Z(n_8651097));
notech_inv i_7542022(.A(i_psram_sub_axi_awaddr[22]), .Z(n_8681096));
notech_nand2 i_7552021(.A(n_8681096), .B(n_5461199), .Z(n_8691095));
notech_nand2 i_7562020(.A(i_psram_sub_axi_awaddr[22]), .B(n_8651097), .Z
(n_8661094));
notech_nand2 i_7572019(.A(n_8661094), .B(n_8691095), .Z(n_8671093));
notech_inv i_7582018(.A(n_8671093), .Z(i_psram_sub_function_sub_0[22])
);
notech_inv i_7592017(.A(n_5471196), .Z(n_8701092));
notech_inv i_7602016(.A(i_psram_sub_axi_awaddr[23]), .Z(n_8731091));
notech_nand2 i_7612015(.A(n_8731091), .B(n_5471196), .Z(n_8741090));
notech_nand2 i_7622014(.A(i_psram_sub_axi_awaddr[23]), .B(n_8701092), .Z
(n_8711089));
notech_nand2 i_7632013(.A(n_8711089), .B(n_8741090), .Z(n_8721088));
notech_inv i_7642012(.A(n_8721088), .Z(i_psram_sub_function_sub_0[23])
);
notech_inv i_02011(.A(i_psram_sub_axi_awaddr[2]), .Z(\i_psram_sub_axi_awaddr_0[2]
));
notech_nand2 i_12010(.A(i_psram_sub_axi_awaddr[2]), .B(i_psram_sub_axi_awaddr
[3]), .Z(n_1331071));
notech_nand2 i_22009(.A(i_psram_sub_axi_awaddr[3]), .B(i_psram_sub_axi_awaddr
[4]), .Z(n_1341070));
notech_nand2 i_32008(.A(i_psram_sub_axi_awaddr[4]), .B(i_psram_sub_axi_awaddr
[5]), .Z(n_1351069));
notech_nand2 i_42007(.A(i_psram_sub_axi_awaddr[5]), .B(i_psram_sub_axi_awaddr
[6]), .Z(n_1361068));
notech_nand2 i_52006(.A(i_psram_sub_axi_awaddr[6]), .B(i_psram_sub_axi_awaddr
[7]), .Z(n_1371067));
notech_nand2 i_62005(.A(i_psram_sub_axi_awaddr[7]), .B(i_psram_sub_axi_awaddr
[8]), .Z(n_1381066));
notech_nand2 i_72004(.A(i_psram_sub_axi_awaddr[8]), .B(i_psram_sub_axi_awaddr
[9]), .Z(n_1391065));
notech_nand2 i_82003(.A(i_psram_sub_axi_awaddr[9]), .B(i_psram_sub_axi_awaddr
[10]), .Z(n_1401064));
notech_nand2 i_92002(.A(i_psram_sub_axi_awaddr[10]), .B(i_psram_sub_axi_awaddr
[11]), .Z(n_1411063));
notech_nand2 i_102001(.A(i_psram_sub_axi_awaddr[11]), .B(i_psram_sub_axi_awaddr
[12]), .Z(n_1421062));
notech_nand2 i_112000(.A(i_psram_sub_axi_awaddr[12]), .B(i_psram_sub_axi_awaddr
[13]), .Z(n_1431061));
notech_nand2 i_121999(.A(i_psram_sub_axi_awaddr[13]), .B(i_psram_sub_axi_awaddr
[14]), .Z(n_1441060));
notech_nand2 i_131998(.A(i_psram_sub_axi_awaddr[14]), .B(i_psram_sub_axi_awaddr
[15]), .Z(n_1451059));
notech_nand2 i_141997(.A(i_psram_sub_axi_awaddr[15]), .B(i_psram_sub_axi_awaddr
[16]), .Z(n_1461058));
notech_nand2 i_151996(.A(i_psram_sub_axi_awaddr[16]), .B(i_psram_sub_axi_awaddr
[17]), .Z(n_1471057));
notech_nand2 i_161995(.A(i_psram_sub_axi_awaddr[17]), .B(i_psram_sub_axi_awaddr
[18]), .Z(n_1481056));
notech_nand2 i_171994(.A(i_psram_sub_axi_awaddr[18]), .B(i_psram_sub_axi_awaddr
[19]), .Z(n_1491055));
notech_nand2 i_181993(.A(i_psram_sub_axi_awaddr[19]), .B(i_psram_sub_axi_awaddr
[20]), .Z(n_1501054));
notech_nand2 i_191992(.A(i_psram_sub_axi_awaddr[20]), .B(i_psram_sub_axi_awaddr
[21]), .Z(n_1511053));
notech_nand2 i_201991(.A(i_psram_sub_axi_awaddr[21]), .B(i_psram_sub_axi_awaddr
[22]), .Z(n_1521052));
notech_inv i_221990(.A(\i_psram_sub_axi_awaddr_0[2] ), .Z(n_1541051));
notech_inv i_231989(.A(n_1331071), .Z(n_2651050));
notech_nor2 i_241988(.A(\i_psram_sub_axi_awaddr_0[2] ), .B(n_1341070), .Z
(n_1561049));
notech_nor2 i_251987(.A(n_1331071), .B(n_1351069), .Z(n_1571048));
notech_nor2 i_261986(.A(n_1341070), .B(n_1361068), .Z(n_1581047));
notech_nor2 i_271985(.A(n_1351069), .B(n_1371067), .Z(n_1591046));
notech_nor2 i_281984(.A(n_1361068), .B(n_1381066), .Z(n_1601045));
notech_nor2 i_291983(.A(n_1371067), .B(n_1391065), .Z(n_1611044));
notech_nor2 i_301982(.A(n_1381066), .B(n_1401064), .Z(n_1621043));
notech_nor2 i_311981(.A(n_1391065), .B(n_1411063), .Z(n_1631042));
notech_nor2 i_321980(.A(n_1401064), .B(n_1421062), .Z(n_1641041));
notech_nor2 i_331979(.A(n_1411063), .B(n_1431061), .Z(n_1651040));
notech_nor2 i_341978(.A(n_1421062), .B(n_1441060), .Z(n_1661039));
notech_nor2 i_351977(.A(n_1431061), .B(n_1451059), .Z(n_1671038));
notech_nor2 i_361976(.A(n_1441060), .B(n_1461058), .Z(n_1681037));
notech_nor2 i_371975(.A(n_1451059), .B(n_1471057), .Z(n_1691036));
notech_nor2 i_381974(.A(n_1461058), .B(n_1481056), .Z(n_1701035));
notech_nor2 i_391973(.A(n_1471057), .B(n_1491055), .Z(n_1711034));
notech_nor2 i_401972(.A(n_1481056), .B(n_1501054), .Z(n_1721033));
notech_nor2 i_411971(.A(n_1491055), .B(n_1511053), .Z(n_1731032));
notech_nor2 i_421970(.A(n_1501054), .B(n_1521052), .Z(n_1741031));
notech_inv i_441969(.A(n_1541051), .Z(n_1761030));
notech_inv i_451968(.A(n_2651050), .Z(n_1771029));
notech_inv i_461967(.A(n_1561049), .Z(n_1781028));
notech_inv i_471966(.A(n_1571048), .Z(n_2661027));
notech_nand2 i_481965(.A(n_1541051), .B(n_1581047), .Z(n_1801026));
notech_nand2 i_491964(.A(n_2651050), .B(n_1591046), .Z(n_1811025));
notech_nand2 i_501963(.A(n_1561049), .B(n_1601045), .Z(n_1821024));
notech_nand2 i_511962(.A(n_1571048), .B(n_1611044), .Z(n_1831023));
notech_nand2 i_521961(.A(n_1581047), .B(n_1621043), .Z(n_1841022));
notech_nand2 i_531960(.A(n_1591046), .B(n_1631042), .Z(n_1851021));
notech_nand2 i_541959(.A(n_1601045), .B(n_1641041), .Z(n_1861020));
notech_nand2 i_551958(.A(n_1611044), .B(n_1651040), .Z(n_1871019));
notech_nand2 i_561957(.A(n_1621043), .B(n_1661039), .Z(n_1881018));
notech_nand2 i_571956(.A(n_1631042), .B(n_1671038), .Z(n_1891017));
notech_nand2 i_581955(.A(n_1641041), .B(n_1681037), .Z(n_1901016));
notech_nand2 i_591954(.A(n_1651040), .B(n_1691036), .Z(n_1911015));
notech_nand2 i_601953(.A(n_1661039), .B(n_1701035), .Z(n_1921014));
notech_nand2 i_611952(.A(n_1671038), .B(n_1711034), .Z(n_1931013));
notech_nand2 i_621951(.A(n_1681037), .B(n_1721033), .Z(n_1941012));
notech_nand2 i_631950(.A(n_1691036), .B(n_1731032), .Z(n_1951011));
notech_nand2 i_641949(.A(n_1701035), .B(n_1741031), .Z(n_1961010));
notech_inv i_661948(.A(n_1761030), .Z(n_1981009));
notech_inv i_671947(.A(n_1771029), .Z(n_1991008));
notech_inv i_681946(.A(n_1781028), .Z(n_2001007));
notech_inv i_691945(.A(n_2661027), .Z(n_2011006));
notech_inv i_701944(.A(n_1801026), .Z(n_2021005));
notech_nor2 i_741943(.A(n_1761030), .B(n_1841022), .Z(n_2061004));
notech_nor2 i_751942(.A(n_1771029), .B(n_1851021), .Z(n_2071003));
notech_nor2 i_761941(.A(n_1781028), .B(n_1861020), .Z(n_2081002));
notech_nor2 i_771940(.A(n_2661027), .B(n_1871019), .Z(n_2091001));
notech_nor2 i_781939(.A(n_1801026), .B(n_1881018), .Z(n_2101000));
notech_nor2 i_791938(.A(n_1811025), .B(n_1891017), .Z(n_211999));
notech_nor2 i_801937(.A(n_1821024), .B(n_1901016), .Z(n_212998));
notech_nor2 i_811936(.A(n_1831023), .B(n_1911015), .Z(n_213997));
notech_nor2 i_821935(.A(n_1841022), .B(n_1921014), .Z(n_214996));
notech_nor2 i_831934(.A(n_1851021), .B(n_1931013), .Z(n_215995));
notech_nor2 i_841933(.A(n_1861020), .B(n_1941012), .Z(n_216994));
notech_nor2 i_851932(.A(n_1871019), .B(n_1951011), .Z(n_217993));
notech_nor2 i_861931(.A(n_1881018), .B(n_1961010), .Z(n_218992));
notech_inv i_881930(.A(n_1981009), .Z(n_220991));
notech_inv i_891929(.A(n_1991008), .Z(n_221990));
notech_inv i_901928(.A(n_2001007), .Z(n_222989));
notech_inv i_911927(.A(n_2011006), .Z(n_223988));
notech_inv i_921926(.A(n_2021005), .Z(n_224987));
notech_inv i_961925(.A(n_2061004), .Z(n_228986));
notech_inv i_971924(.A(n_2071003), .Z(n_229985));
notech_inv i_981923(.A(n_2081002), .Z(n_230984));
notech_inv i_991922(.A(n_2091001), .Z(n_231983));
notech_inv i_1001921(.A(n_2101000), .Z(n_232982));
notech_inv i_1011920(.A(n_211999), .Z(n_233981));
notech_inv i_1021919(.A(n_212998), .Z(n_234980));
notech_inv i_1031918(.A(n_213997), .Z(n_272979));
notech_nand2 i_1041917(.A(n_1981009), .B(n_214996), .Z(n_236978));
notech_nand2 i_1051916(.A(n_1991008), .B(n_215995), .Z(n_237977));
notech_nand2 i_1061915(.A(n_2001007), .B(n_216994), .Z(n_238976));
notech_nand2 i_1071914(.A(n_2011006), .B(n_217993), .Z(n_239975));
notech_nand2 i_1081913(.A(n_2021005), .B(n_218992), .Z(n_240974));
notech_inv i_1321912(.A(n_220991), .Z(n_276973));
notech_inv i_1331911(.A(i_psram_sub_axi_awaddr[3]), .Z(n_279972));
notech_nand2 i_1341910(.A(n_279972), .B(n_220991), .Z(n_280971));
notech_nand2 i_1351909(.A(i_psram_sub_axi_awaddr[3]), .B(n_276973), .Z(n_277970
));
notech_nand2 i_1361908(.A(n_277970), .B(n_280971), .Z(n_278969));
notech_inv i_1371907(.A(n_278969), .Z(\i_psram_sub_axi_awaddr_0[3] ));
notech_inv i_1381906(.A(n_221990), .Z(n_281968));
notech_inv i_1391905(.A(i_psram_sub_axi_awaddr[4]), .Z(n_284967));
notech_nand2 i_1401904(.A(n_284967), .B(n_221990), .Z(n_285966));
notech_nand2 i_1411903(.A(i_psram_sub_axi_awaddr[4]), .B(n_281968), .Z(n_282965
));
notech_nand2 i_1421902(.A(n_282965), .B(n_285966), .Z(n_283964));
notech_inv i_1431901(.A(n_283964), .Z(\i_psram_sub_axi_awaddr_0[4] ));
notech_inv i_1441900(.A(n_222989), .Z(n_286963));
notech_inv i_1451899(.A(i_psram_sub_axi_awaddr[5]), .Z(n_289962));
notech_nand2 i_1461898(.A(n_289962), .B(n_222989), .Z(n_290961));
notech_nand2 i_1471897(.A(i_psram_sub_axi_awaddr[5]), .B(n_286963), .Z(n_287960
));
notech_nand2 i_1481896(.A(n_287960), .B(n_290961), .Z(n_288959));
notech_inv i_1491895(.A(n_288959), .Z(\i_psram_sub_axi_awaddr_0[5] ));
notech_inv i_1501894(.A(n_223988), .Z(n_291958));
notech_inv i_1511893(.A(i_psram_sub_axi_awaddr[6]), .Z(n_294957));
notech_nand2 i_1521892(.A(n_294957), .B(n_223988), .Z(n_295956));
notech_nand2 i_1531891(.A(i_psram_sub_axi_awaddr[6]), .B(n_291958), .Z(n_292955
));
notech_nand2 i_1541890(.A(n_292955), .B(n_295956), .Z(n_293954));
notech_inv i_1551889(.A(n_293954), .Z(\i_psram_sub_axi_awaddr_0[6] ));
notech_inv i_1561888(.A(n_224987), .Z(n_296953));
notech_inv i_1571887(.A(i_psram_sub_axi_awaddr[7]), .Z(n_299952));
notech_nand2 i_1581886(.A(n_299952), .B(n_224987), .Z(n_300951));
notech_nand2 i_1591885(.A(i_psram_sub_axi_awaddr[7]), .B(n_296953), .Z(n_297950
));
notech_nand2 i_1601884(.A(n_297950), .B(n_300951), .Z(n_298949));
notech_inv i_1611883(.A(n_298949), .Z(\i_psram_sub_axi_awaddr_0[7] ));
notech_inv i_1621882(.A(n_1811025), .Z(n_301948));
notech_inv i_1631881(.A(i_psram_sub_axi_awaddr[8]), .Z(n_304947));
notech_nand2 i_1641880(.A(n_304947), .B(n_1811025), .Z(n_305946));
notech_nand2 i_1651879(.A(i_psram_sub_axi_awaddr[8]), .B(n_301948), .Z(n_302945
));
notech_nand2 i_1661878(.A(n_302945), .B(n_305946), .Z(n_303944));
notech_inv i_1671877(.A(n_303944), .Z(\i_psram_sub_axi_awaddr_0[8] ));
notech_inv i_1681876(.A(n_1821024), .Z(n_306943));
notech_inv i_1691875(.A(i_psram_sub_axi_awaddr[9]), .Z(n_309942));
notech_nand2 i_1701874(.A(n_309942), .B(n_1821024), .Z(n_310941));
notech_nand2 i_1711873(.A(i_psram_sub_axi_awaddr[9]), .B(n_306943), .Z(n_307940
));
notech_nand2 i_1721872(.A(n_307940), .B(n_310941), .Z(n_308939));
notech_inv i_1731871(.A(n_308939), .Z(\i_psram_sub_axi_awaddr_0[9] ));
notech_inv i_1741870(.A(n_1831023), .Z(n_311938));
notech_inv i_1751869(.A(i_psram_sub_axi_awaddr[10]), .Z(n_314937));
notech_nand2 i_1761868(.A(n_314937), .B(n_1831023), .Z(n_315936));
notech_nand2 i_1771867(.A(i_psram_sub_axi_awaddr[10]), .B(n_311938), .Z(n_312935
));
notech_nand2 i_1781866(.A(n_312935), .B(n_315936), .Z(n_313934));
notech_inv i_1791865(.A(n_313934), .Z(\i_psram_sub_axi_awaddr_0[10] ));
notech_inv i_1801864(.A(n_228986), .Z(n_316933));
notech_inv i_1811863(.A(i_psram_sub_axi_awaddr[11]), .Z(n_319932));
notech_nand2 i_1821862(.A(n_319932), .B(n_228986), .Z(n_320931));
notech_nand2 i_1831861(.A(i_psram_sub_axi_awaddr[11]), .B(n_316933), .Z(n_317930
));
notech_nand2 i_1841860(.A(n_317930), .B(n_320931), .Z(n_318929));
notech_inv i_1851859(.A(n_318929), .Z(\i_psram_sub_axi_awaddr_0[11] ));
notech_inv i_1861858(.A(n_229985), .Z(n_321928));
notech_inv i_1871857(.A(i_psram_sub_axi_awaddr[12]), .Z(n_324927));
notech_nand2 i_1881856(.A(n_324927), .B(n_229985), .Z(n_325926));
notech_nand2 i_1891855(.A(i_psram_sub_axi_awaddr[12]), .B(n_321928), .Z(n_322925
));
notech_nand2 i_1901854(.A(n_322925), .B(n_325926), .Z(n_323924));
notech_inv i_1911853(.A(n_323924), .Z(\i_psram_sub_axi_awaddr_0[12] ));
notech_inv i_1921852(.A(n_230984), .Z(n_326923));
notech_inv i_1931851(.A(i_psram_sub_axi_awaddr[13]), .Z(n_329922));
notech_nand2 i_1941850(.A(n_329922), .B(n_230984), .Z(n_330921));
notech_nand2 i_1951849(.A(i_psram_sub_axi_awaddr[13]), .B(n_326923), .Z(n_327920
));
notech_nand2 i_1961848(.A(n_327920), .B(n_330921), .Z(n_328919));
notech_inv i_1971847(.A(n_328919), .Z(\i_psram_sub_axi_awaddr_0[13] ));
notech_inv i_1981846(.A(n_231983), .Z(n_331918));
notech_inv i_1991845(.A(i_psram_sub_axi_awaddr[14]), .Z(n_334917));
notech_nand2 i_2001844(.A(n_334917), .B(n_231983), .Z(n_335916));
notech_nand2 i_2011843(.A(i_psram_sub_axi_awaddr[14]), .B(n_331918), .Z(n_332915
));
notech_nand2 i_2021842(.A(n_332915), .B(n_335916), .Z(n_333914));
notech_inv i_2031841(.A(n_333914), .Z(\i_psram_sub_axi_awaddr_0[14] ));
notech_inv i_2041840(.A(n_232982), .Z(n_336913));
notech_inv i_2051839(.A(i_psram_sub_axi_awaddr[15]), .Z(n_339912));
notech_nand2 i_2061838(.A(n_339912), .B(n_232982), .Z(n_340911));
notech_nand2 i_2071837(.A(i_psram_sub_axi_awaddr[15]), .B(n_336913), .Z(n_337910
));
notech_nand2 i_2081836(.A(n_337910), .B(n_340911), .Z(n_338909));
notech_inv i_2091835(.A(n_338909), .Z(\i_psram_sub_axi_awaddr_0[15] ));
notech_inv i_2101834(.A(n_233981), .Z(n_341908));
notech_inv i_2111833(.A(i_psram_sub_axi_awaddr[16]), .Z(n_344907));
notech_nand2 i_2121832(.A(n_344907), .B(n_233981), .Z(n_345906));
notech_nand2 i_2131831(.A(i_psram_sub_axi_awaddr[16]), .B(n_341908), .Z(n_342905
));
notech_nand2 i_2141830(.A(n_342905), .B(n_345906), .Z(n_343904));
notech_inv i_2151829(.A(n_343904), .Z(\i_psram_sub_axi_awaddr_0[16] ));
notech_inv i_2161828(.A(n_234980), .Z(n_346903));
notech_inv i_2171827(.A(i_psram_sub_axi_awaddr[17]), .Z(n_349902));
notech_nand2 i_2181826(.A(n_349902), .B(n_234980), .Z(n_350901));
notech_nand2 i_2191825(.A(i_psram_sub_axi_awaddr[17]), .B(n_346903), .Z(n_347900
));
notech_nand2 i_2201824(.A(n_347900), .B(n_350901), .Z(n_348899));
notech_inv i_2211823(.A(n_348899), .Z(\i_psram_sub_axi_awaddr_0[17] ));
notech_inv i_2221822(.A(n_272979), .Z(n_351898));
notech_inv i_2231821(.A(i_psram_sub_axi_awaddr[18]), .Z(n_354897));
notech_nand2 i_2241820(.A(n_354897), .B(n_272979), .Z(n_355896));
notech_nand2 i_2251819(.A(i_psram_sub_axi_awaddr[18]), .B(n_351898), .Z(n_352895
));
notech_nand2 i_2261818(.A(n_352895), .B(n_355896), .Z(n_353894));
notech_inv i_2271817(.A(n_353894), .Z(\i_psram_sub_axi_awaddr_0[18] ));
notech_inv i_2281816(.A(n_236978), .Z(n_356893));
notech_inv i_2291815(.A(i_psram_sub_axi_awaddr[19]), .Z(n_359892));
notech_nand2 i_2301814(.A(n_359892), .B(n_236978), .Z(n_360891));
notech_nand2 i_2311813(.A(i_psram_sub_axi_awaddr[19]), .B(n_356893), .Z(n_357890
));
notech_nand2 i_2321812(.A(n_357890), .B(n_360891), .Z(n_358889));
notech_inv i_2331811(.A(n_358889), .Z(\i_psram_sub_axi_awaddr_0[19] ));
notech_inv i_2341810(.A(n_237977), .Z(n_361888));
notech_inv i_2351809(.A(i_psram_sub_axi_awaddr[20]), .Z(n_364887));
notech_nand2 i_2361808(.A(n_364887), .B(n_237977), .Z(n_365886));
notech_nand2 i_2371807(.A(i_psram_sub_axi_awaddr[20]), .B(n_361888), .Z(n_362885
));
notech_nand2 i_2381806(.A(n_362885), .B(n_365886), .Z(n_363884));
notech_inv i_2391805(.A(n_363884), .Z(\i_psram_sub_axi_awaddr_0[20] ));
notech_inv i_2401804(.A(n_238976), .Z(n_366883));
notech_inv i_2411803(.A(i_psram_sub_axi_awaddr[21]), .Z(n_369882));
notech_nand2 i_2421802(.A(n_369882), .B(n_238976), .Z(n_370881));
notech_nand2 i_2431801(.A(i_psram_sub_axi_awaddr[21]), .B(n_366883), .Z(n_367880
));
notech_nand2 i_2441800(.A(n_367880), .B(n_370881), .Z(n_368879));
notech_inv i_2451799(.A(n_368879), .Z(\i_psram_sub_axi_awaddr_0[21] ));
notech_inv i_2461798(.A(n_239975), .Z(n_371878));
notech_inv i_2471797(.A(i_psram_sub_axi_awaddr[22]), .Z(n_374877));
notech_nand2 i_2481796(.A(n_374877), .B(n_239975), .Z(n_375876));
notech_nand2 i_2491795(.A(i_psram_sub_axi_awaddr[22]), .B(n_371878), .Z(n_372875
));
notech_nand2 i_2501794(.A(n_372875), .B(n_375876), .Z(n_373874));
notech_inv i_2511793(.A(n_373874), .Z(\i_psram_sub_axi_awaddr_0[22] ));
notech_inv i_2521792(.A(n_240974), .Z(n_376873));
notech_inv i_2531791(.A(i_psram_sub_axi_awaddr[23]), .Z(n_379872));
notech_nand2 i_2541790(.A(n_379872), .B(n_240974), .Z(n_380871));
notech_nand2 i_2551789(.A(i_psram_sub_axi_awaddr[23]), .B(n_376873), .Z(n_377870
));
notech_nand2 i_2561788(.A(n_377870), .B(n_380871), .Z(n_378869));
notech_inv i_2571787(.A(n_378869), .Z(\i_psram_sub_axi_awaddr_0[23] ));
notech_inv i_121786(.A(n_249), .Z(n_371801));
notech_inv i_171785(.A(n_418), .Z(n_469));
notech_inv i_491784(.A(n_242), .Z(n_363809));
notech_inv i_591656(.A(n_242), .Z(n_625));
notech_inv i_591783(.A(i_psram_sub_axi_araddr[1]), .Z(n_265862));
notech_inv i_601782(.A(i_psram_sub_axi_araddr[10]), .Z(n_274));
notech_inv i_611655(.A(n_642), .Z(n_690));
notech_inv i_611781(.A(i_psram_sub_axi_araddr[11]), .Z(n_275));
notech_inv i_621654(.A(i_psram_sub_axi_araddr[11]), .Z(n_602));
notech_inv i_621780(.A(i_psram_sub_axi_araddr[12]), .Z(n_276859));
notech_inv i_631653(.A(n_601), .Z(n_649));
notech_inv i_631779(.A(i_psram_sub_axi_araddr[13]), .Z(n_277858));
notech_inv i_641652(.A(i_psram_sub_axi_araddr[13]), .Z(n_606));
notech_inv i_641778(.A(i_psram_sub_axi_araddr[14]), .Z(n_278857));
notech_inv i_651651(.A(n_689), .Z(n_737));
notech_inv i_65(.A(i_psram_sub_axi_araddr[15]), .Z(n_279856));
notech_inv i_661650(.A(i_psram_sub_axi_araddr[15]), .Z(n_610));
notech_inv i_661777(.A(i_psram_sub_axi_araddr[16]), .Z(n_280855));
notech_inv i_671649(.A(n_609), .Z(n_657));
notech_inv i_671776(.A(i_psram_sub_axi_araddr[17]), .Z(n_281854));
notech_inv i_681648(.A(i_psram_sub_axi_araddr[17]), .Z(n_614));
notech_inv i_681775(.A(i_psram_sub_axi_araddr[18]), .Z(n_282853));
notech_inv i_691647(.A(n_658), .Z(n_706));
notech_inv i_691774(.A(i_psram_sub_axi_araddr[19]), .Z(n_283852));
notech_inv i_701646(.A(i_psram_sub_axi_araddr[19]), .Z(n_618));
notech_inv i_701773(.A(i_psram_sub_axi_araddr[20]), .Z(n_284851));
notech_inv i_711645(.A(n_617), .Z(n_665));
notech_inv i_711644(.A(i_psram_sub_axi_araddr[21]), .Z(n_285850));
notech_inv i_741643(.A(i_psram_sub_axi_araddr[21]), .Z(n_622));
notech_inv i_741642(.A(i_psram_sub_axi_araddr[22]), .Z(n_286849));
notech_inv i_741641(.A(n_417), .Z(n_468));
notech_inv i_761640(.A(n_640), .Z(n_688));
notech_inv i_761639(.A(i_psram_sub_axi_araddr[10]), .Z(n_600));
notech_inv i_761638(.A(n_599), .Z(n_647));
notech_inv i_761637(.A(i_psram_sub_axi_araddr[12]), .Z(n_604));
notech_inv i_761636(.A(n_687), .Z(n_735));
notech_inv i_761635(.A(i_psram_sub_axi_araddr[14]), .Z(n_608));
notech_inv i_761634(.A(n_607), .Z(n_655));
notech_inv i_761633(.A(i_psram_sub_axi_araddr[16]), .Z(n_612));
notech_inv i_761632(.A(n_656), .Z(n_704));
notech_inv i_761631(.A(i_psram_sub_axi_araddr[18]), .Z(n_616));
notech_inv i_761630(.A(n_615), .Z(n_663));
notech_inv i_761629(.A(i_psram_sub_axi_araddr[20]), .Z(n_620));
notech_inv i_741628(.A(n_467), .Z(n_522));
notech_inv i_761627(.A(n_597), .Z(n_645));
notech_inv i_761626(.A(n_685), .Z(n_733));
notech_inv i_761625(.A(n_605), .Z(n_653));
notech_inv i_761624(.A(n_654), .Z(n_702));
notech_inv i_761623(.A(n_613), .Z(n_661));
notech_inv i_741622(.A(n_370802), .Z(n_419));
notech_inv i_741621(.A(n_466), .Z(n_521));
notech_inv i_741620(.A(n_364808), .Z(n_411));
notech_inv i_761619(.A(n_595), .Z(n_643));
notech_inv i_761618(.A(n_683), .Z(n_731));
notech_inv i_761617(.A(n_603), .Z(n_651));
notech_inv i_761616(.A(n_652), .Z(n_700));
notech_inv i_761615(.A(n_611), .Z(n_659));
notech_inv i_741614(.A(n_465), .Z(n_520));
notech_inv i_761613(.A(n_681), .Z(n_729));
notech_inv i_761612(.A(n_650), .Z(n_698));
notech_inv i_761611(.A(n_464), .Z(n_744));
notech_inv i_761610(.A(n_679), .Z(n_727));
notech_inv i_761609(.A(n_648), .Z(n_696));
notech_inv i_741608(.A(n_249), .Z(n_471));
notech_inv i_761607(.A(n_646), .Z(n_694));
notech_inv i_761772(.A(n_644), .Z(n_692));
notech_inv i_741606(.A(n_294846), .Z(n_767));
notech_inv i_741771(.A(i_psram_sub_axi_araddr[1]), .Z(n_762));
notech_inv i_741605(.A(i_psram_sub_axi_araddr[0]), .Z(n_757));
notech_inv i_21770(.A(s00_axi_arlen[0]), .Z(n_218868));
notech_inv i_31769(.A(s00_axi_arlen[1]), .Z(n_219));
notech_inv i_41768(.A(s00_axi_arlen[2]), .Z(n_220867));
notech_inv i_51767(.A(s00_axi_arlen[3]), .Z(n_221866));
notech_inv i_61766(.A(s00_axi_arlen[4]), .Z(n_222865));
notech_inv i_71765(.A(s00_axi_arlen[5]), .Z(n_223864));
notech_inv i_81764(.A(s00_axi_arlen[6]), .Z(n_224863));
notech_inv i_91763(.A(s00_axi_arlen[7]), .Z(n_225));
notech_nor2 i_261762(.A(i_psram_sub_axi_araddr[2]), .B(n_218868), .Z(n_242
));
notech_nor2 i_271761(.A(i_psram_sub_axi_araddr[3]), .B(n_219), .Z(n_243)
);
notech_nor2 i_281760(.A(i_psram_sub_axi_araddr[4]), .B(n_220867), .Z(n_244
));
notech_nor2 i_291759(.A(i_psram_sub_axi_araddr[5]), .B(n_221866), .Z(n_245
));
notech_nor2 i_301758(.A(i_psram_sub_axi_araddr[6]), .B(n_222865), .Z(n_246
));
notech_nor2 i_311757(.A(i_psram_sub_axi_araddr[7]), .B(n_223864), .Z(n_247
));
notech_nor2 i_321756(.A(i_psram_sub_axi_araddr[8]), .B(n_224863), .Z(n_248
));
notech_nor2 i_331755(.A(i_psram_sub_axi_araddr[9]), .B(n_225), .Z(n_249)
);
notech_nand2 i_501754(.A(i_psram_sub_axi_araddr[2]), .B(n_218868), .Z(n_266861
));
notech_nand2 i_511753(.A(i_psram_sub_axi_araddr[3]), .B(n_219), .Z(n_267
));
notech_nand2 i_521752(.A(i_psram_sub_axi_araddr[4]), .B(n_220867), .Z(n_268
));
notech_nand2 i_531751(.A(i_psram_sub_axi_araddr[5]), .B(n_221866), .Z(n_269
));
notech_nand2 i_541750(.A(i_psram_sub_axi_araddr[6]), .B(n_222865), .Z(n_270
));
notech_nand2 i_551749(.A(i_psram_sub_axi_araddr[7]), .B(n_223864), .Z(n_271
));
notech_nand2 i_561748(.A(i_psram_sub_axi_araddr[8]), .B(n_224863), .Z(n_272860
));
notech_nand2 i_571747(.A(i_psram_sub_axi_araddr[9]), .B(n_225), .Z(n_273
));
notech_inv i_72(.A(i_psram_sub_axi_araddr[0]), .Z(n_288848));
notech_inv i_771746(.A(n_242), .Z(n_293847));
notech_nand2 i_781745(.A(n_293847), .B(n_266861), .Z(n_294846));
notech_inv i_791744(.A(n_243), .Z(n_295845));
notech_nand2 i_801743(.A(n_295845), .B(n_267), .Z(n_296844));
notech_inv i_811742(.A(n_244), .Z(n_297843));
notech_nand2 i_821741(.A(n_297843), .B(n_268), .Z(n_298842));
notech_inv i_831740(.A(n_245), .Z(n_299841));
notech_nand2 i_841739(.A(n_299841), .B(n_269), .Z(n_300840));
notech_inv i_851738(.A(n_246), .Z(n_301839));
notech_nand2 i_861737(.A(n_301839), .B(n_270), .Z(n_302838));
notech_inv i_87(.A(n_247), .Z(n_303837));
notech_nand2 i_881736(.A(n_303837), .B(n_271), .Z(n_304836));
notech_inv i_891735(.A(n_248), .Z(n_305835));
notech_nand2 i_901734(.A(n_305835), .B(n_272860), .Z(n_306834));
notech_inv i_911733(.A(n_249), .Z(n_307833));
notech_nand2 i_921732(.A(n_307833), .B(n_273), .Z(n_308832));
notech_or2 i_360(.A(n_242), .B(n_265862), .Z(n_582));
notech_and2 i_361(.A(n_582), .B(n_266861), .Z(n_581));
notech_inv i_362(.A(n_581), .Z(n_339831));
notech_or2 i_363(.A(n_243), .B(n_266861), .Z(n_584));
notech_and2 i_364(.A(n_584), .B(n_267), .Z(n_583));
notech_inv i_365(.A(n_583), .Z(n_340830));
notech_or2 i_366(.A(n_244), .B(n_267), .Z(n_586));
notech_and2 i_367(.A(n_586), .B(n_268), .Z(n_585));
notech_inv i_368(.A(n_585), .Z(n_341829));
notech_or2 i_369(.A(n_245), .B(n_268), .Z(n_588));
notech_and2 i_370(.A(n_588), .B(n_269), .Z(n_587));
notech_inv i_371(.A(n_587), .Z(n_342828));
notech_or2 i_372(.A(n_246), .B(n_269), .Z(n_590));
notech_and2 i_373(.A(n_590), .B(n_270), .Z(n_589));
notech_inv i_374(.A(n_589), .Z(n_343827));
notech_or2 i_375(.A(n_247), .B(n_270), .Z(n_592));
notech_and2 i_376(.A(n_592), .B(n_271), .Z(n_591));
notech_inv i_377(.A(n_591), .Z(n_344826));
notech_or2 i_378(.A(n_248), .B(n_271), .Z(n_594));
notech_and2 i_379(.A(n_594), .B(n_272860), .Z(n_593));
notech_inv i_380(.A(n_593), .Z(n_345825));
notech_or2 i_381(.A(n_249), .B(n_272860), .Z(n_596));
notech_and2 i_382(.A(n_596), .B(n_273), .Z(n_595));
notech_inv i_383(.A(n_595), .Z(n_346824));
notech_and2 i_385(.A(n_273), .B(n_274), .Z(n_597));
notech_inv i_386(.A(n_597), .Z(n_347823));
notech_and2 i_388(.A(n_600), .B(n_275), .Z(n_599));
notech_inv i_389(.A(n_599), .Z(n_348822));
notech_and2 i_391(.A(n_602), .B(n_276859), .Z(n_601));
notech_inv i_392(.A(n_601), .Z(n_349821));
notech_and2 i_394(.A(n_604), .B(n_277858), .Z(n_603));
notech_inv i_395(.A(n_603), .Z(n_350820));
notech_and2 i_397(.A(n_606), .B(n_278857), .Z(n_605));
notech_inv i_398(.A(n_605), .Z(n_351819));
notech_and2 i_400(.A(n_608), .B(n_279856), .Z(n_607));
notech_inv i_401(.A(n_607), .Z(n_352818));
notech_and2 i_403(.A(n_610), .B(n_280855), .Z(n_609));
notech_inv i_404(.A(n_609), .Z(n_353817));
notech_and2 i_406(.A(n_612), .B(n_281854), .Z(n_611));
notech_inv i_407(.A(n_611), .Z(n_354816));
notech_and2 i_409(.A(n_614), .B(n_282853), .Z(n_613));
notech_inv i_410(.A(n_613), .Z(n_355815));
notech_and2 i_412(.A(n_616), .B(n_283852), .Z(n_615));
notech_inv i_413(.A(n_615), .Z(n_356814));
notech_and2 i_415(.A(n_618), .B(n_284851), .Z(n_617));
notech_inv i_416(.A(n_617), .Z(n_357813));
notech_and2 i_418(.A(n_620), .B(n_285850), .Z(n_619));
notech_inv i_419(.A(n_619), .Z(n_358812));
notech_and2 i_421(.A(n_622), .B(n_286849), .Z(n_621));
notech_inv i_422(.A(n_621), .Z(n_359811));
notech_inv i_1441731(.A(n_288848), .Z(n_360810));
notech_nor2 i_1481730(.A(n_242), .B(n_243), .Z(n_364808));
notech_nor2 i_1491729(.A(n_243), .B(n_244), .Z(n_365807));
notech_nor2 i_1501728(.A(n_244), .B(n_245), .Z(n_366806));
notech_nor2 i_1511727(.A(n_245), .B(n_246), .Z(n_367805));
notech_nor2 i_1521726(.A(n_246), .B(n_247), .Z(n_368804));
notech_nor2 i_1531725(.A(n_247), .B(n_248), .Z(n_369803));
notech_nor2 i_1541724(.A(n_248), .B(n_249), .Z(n_370802));
notech_or2 i_427(.A(n_625), .B(n_339831), .Z(n_626));
notech_inv i_428(.A(n_626), .Z(n_386));
notech_or2 i_430(.A(n_364808), .B(n_340830), .Z(n_628));
notech_inv i_431(.A(n_628), .Z(n_387));
notech_and2 i_432(.A(n_365807), .B(n_339831), .Z(n_629));
notech_or2 i_433(.A(n_629), .B(n_341829), .Z(n_630));
notech_inv i_434(.A(n_630), .Z(n_388));
notech_and2 i_435(.A(n_366806), .B(n_340830), .Z(n_631));
notech_or2 i_436(.A(n_631), .B(n_342828), .Z(n_632));
notech_inv i_437(.A(n_632), .Z(n_389));
notech_and2 i_438(.A(n_367805), .B(n_341829), .Z(n_633));
notech_or2 i_439(.A(n_633), .B(n_343827), .Z(n_634));
notech_inv i_440(.A(n_634), .Z(n_390));
notech_and2 i_441(.A(n_368804), .B(n_342828), .Z(n_635));
notech_or2 i_442(.A(n_635), .B(n_344826), .Z(n_636));
notech_inv i_443(.A(n_636), .Z(n_391));
notech_and2 i_444(.A(n_369803), .B(n_343827), .Z(n_637));
notech_or2 i_445(.A(n_637), .B(n_345825), .Z(n_638));
notech_inv i_446(.A(n_638), .Z(n_392));
notech_and2 i_447(.A(n_370802), .B(n_344826), .Z(n_639));
notech_or2 i_448(.A(n_639), .B(n_346824), .Z(n_640));
notech_inv i_449(.A(n_640), .Z(n_393));
notech_and2 i_450(.A(n_371801), .B(n_345825), .Z(n_641));
notech_or2 i_451(.A(n_641), .B(n_347823), .Z(n_642));
notech_inv i_452(.A(n_642), .Z(n_394));
notech_or2 i_454(.A(n_643), .B(n_348822), .Z(n_644));
notech_inv i_455(.A(n_644), .Z(n_395));
notech_or2 i_457(.A(n_645), .B(n_349821), .Z(n_646));
notech_inv i_458(.A(n_646), .Z(n_396));
notech_or2 i_460(.A(n_647), .B(n_350820), .Z(n_648));
notech_inv i_461(.A(n_648), .Z(n_397));
notech_or2 i_463(.A(n_649), .B(n_351819), .Z(n_650));
notech_inv i_464(.A(n_650), .Z(n_398));
notech_or2 i_466(.A(n_651), .B(n_352818), .Z(n_652));
notech_inv i_467(.A(n_652), .Z(n_399));
notech_or2 i_469(.A(n_653), .B(n_353817), .Z(n_654));
notech_inv i_470(.A(n_654), .Z(n_400));
notech_or2 i_472(.A(n_655), .B(n_354816), .Z(n_656));
notech_inv i_473(.A(n_656), .Z(n_401));
notech_or2 i_475(.A(n_657), .B(n_355815), .Z(n_658));
notech_inv i_476(.A(n_658), .Z(n_402));
notech_or2 i_478(.A(n_659), .B(n_356814), .Z(n_660));
notech_inv i_479(.A(n_660), .Z(n_403));
notech_or2 i_481(.A(n_661), .B(n_357813), .Z(n_662));
notech_inv i_482(.A(n_662), .Z(n_404));
notech_or2 i_484(.A(n_663), .B(n_358812), .Z(n_664));
notech_inv i_485(.A(n_664), .Z(n_405));
notech_or2 i_487(.A(n_665), .B(n_359811), .Z(n_666));
notech_inv i_488(.A(n_666), .Z(n_406));
notech_inv i_1911723(.A(n_360810), .Z(n_407));
notech_nand2 i_1961722(.A(n_363809), .B(n_365807), .Z(n_412));
notech_nand2 i_1971721(.A(n_364808), .B(n_366806), .Z(n_413));
notech_nand2 i_1981720(.A(n_365807), .B(n_367805), .Z(n_414));
notech_nand2 i_1991719(.A(n_366806), .B(n_368804), .Z(n_415));
notech_nand2 i_2001718(.A(n_367805), .B(n_369803), .Z(n_416));
notech_nand2 i_2011717(.A(n_368804), .B(n_370802), .Z(n_417));
notech_nand2 i_2021716(.A(n_369803), .B(n_371801), .Z(n_418));
notech_inv i_2171715(.A(n_386), .Z(n_433));
notech_or2 i_489(.A(n_411), .B(n_407), .Z(n_668));
notech_and2 i_490(.A(n_668), .B(n_387), .Z(n_667));
notech_inv i_491(.A(n_667), .Z(n_434));
notech_and2 i_493(.A(n_412), .B(n_388), .Z(n_669));
notech_inv i_494(.A(n_669), .Z(n_435));
notech_and2 i_496(.A(n_413), .B(n_389), .Z(n_671));
notech_inv i_497(.A(n_671), .Z(n_436));
notech_or2 i_498(.A(n_414), .B(n_386), .Z(n_674));
notech_and2 i_499(.A(n_674), .B(n_390), .Z(n_673));
notech_inv i_500(.A(n_673), .Z(n_437));
notech_or2 i_501(.A(n_415), .B(n_387), .Z(n_676));
notech_and2 i_502(.A(n_676), .B(n_391), .Z(n_675));
notech_inv i_503(.A(n_675), .Z(n_438));
notech_or2 i_504(.A(n_416), .B(n_388), .Z(n_678));
notech_and2 i_505(.A(n_678), .B(n_392), .Z(n_677));
notech_inv i_506(.A(n_677), .Z(n_439));
notech_or2 i_507(.A(n_417), .B(n_389), .Z(n_680));
notech_and2 i_508(.A(n_680), .B(n_393), .Z(n_679));
notech_inv i_509(.A(n_679), .Z(n_440));
notech_or2 i_510(.A(n_418), .B(n_390), .Z(n_682));
notech_and2 i_511(.A(n_682), .B(n_394), .Z(n_681));
notech_inv i_512(.A(n_681), .Z(n_441));
notech_or2 i_513(.A(n_419), .B(n_391), .Z(n_684));
notech_and2 i_514(.A(n_684), .B(n_395), .Z(n_683));
notech_inv i_515(.A(n_683), .Z(n_442));
notech_or2 i_516(.A(n_249), .B(n_392), .Z(n_686));
notech_and2 i_517(.A(n_686), .B(n_396), .Z(n_685));
notech_inv i_518(.A(n_685), .Z(n_443));
notech_and2 i_520(.A(n_688), .B(n_397), .Z(n_687));
notech_inv i_521(.A(n_687), .Z(n_444));
notech_and2 i_523(.A(n_690), .B(n_398), .Z(n_689));
notech_inv i_524(.A(n_689), .Z(n_445));
notech_and2 i_526(.A(n_692), .B(n_399), .Z(n_691));
notech_inv i_527(.A(n_691), .Z(n_446));
notech_and2 i_529(.A(n_694), .B(n_400), .Z(n_693));
notech_inv i_530(.A(n_693), .Z(n_447));
notech_and2 i_532(.A(n_696), .B(n_401), .Z(n_695));
notech_inv i_533(.A(n_695), .Z(n_448));
notech_and2 i_535(.A(n_698), .B(n_402), .Z(n_697));
notech_inv i_536(.A(n_697), .Z(n_449));
notech_and2 i_538(.A(n_700), .B(n_403), .Z(n_699));
notech_inv i_539(.A(n_699), .Z(n_450));
notech_and2 i_541(.A(n_702), .B(n_404), .Z(n_701));
notech_inv i_542(.A(n_701), .Z(n_451));
notech_and2 i_544(.A(n_704), .B(n_405), .Z(n_703));
notech_inv i_545(.A(n_703), .Z(n_452));
notech_and2 i_547(.A(n_706), .B(n_406), .Z(n_705));
notech_inv i_548(.A(n_705), .Z(n_453));
notech_inv i_2381714(.A(n_407), .Z(n_454));
notech_nor2 i_2461713(.A(n_411), .B(n_415), .Z(n_462));
notech_nor2 i_2471712(.A(n_412), .B(n_416), .Z(n_463));
notech_nor2 i_2481711(.A(n_413), .B(n_417), .Z(n_464));
notech_nor2 i_2491710(.A(n_414), .B(n_418), .Z(n_465));
notech_nor2 i_2501709(.A(n_415), .B(n_419), .Z(n_466));
notech_nor2 i_2511708(.A(n_416), .B(n_249), .Z(n_467));
notech_inv i_264(.A(n_433), .Z(n_480));
notech_inv i_265(.A(n_434), .Z(n_481));
notech_inv i_266(.A(n_435), .Z(n_482));
notech_inv i_267(.A(n_436), .Z(n_483));
notech_inv i_268(.A(n_437), .Z(n_484));
notech_and2 i_549(.A(n_462), .B(n_454), .Z(n_707));
notech_or2 i_550(.A(n_707), .B(n_438), .Z(n_708));
notech_or2 i_553(.A(n_463), .B(n_439), .Z(n_710));
notech_or2 i_556(.A(n_464), .B(n_440), .Z(n_712));
notech_and2 i_558(.A(n_465), .B(n_433), .Z(n_713));
notech_or2 i_559(.A(n_713), .B(n_441), .Z(n_714));
notech_and2 i_561(.A(n_466), .B(n_434), .Z(n_715));
notech_or2 i_562(.A(n_715), .B(n_442), .Z(n_716));
notech_and2 i_564(.A(n_467), .B(n_435), .Z(n_717));
notech_or2 i_565(.A(n_717), .B(n_443), .Z(n_718));
notech_and2 i_567(.A(n_468), .B(n_436), .Z(n_719));
notech_or2 i_568(.A(n_719), .B(n_444), .Z(n_720));
notech_and2 i_570(.A(n_469), .B(n_437), .Z(n_721));
notech_or2 i_571(.A(n_721), .B(n_445), .Z(n_722));
notech_and2 i_573(.A(n_370802), .B(n_438), .Z(n_723));
notech_or2 i_574(.A(n_723), .B(n_446), .Z(n_724));
notech_inv i_575(.A(n_724), .Z(n_493));
notech_and2 i_576(.A(n_471), .B(n_439), .Z(n_725));
notech_or2 i_577(.A(n_725), .B(n_447), .Z(n_726));
notech_inv i_578(.A(n_726), .Z(n_494));
notech_or2 i_580(.A(n_727), .B(n_448), .Z(n_728));
notech_inv i_581(.A(n_728), .Z(n_495));
notech_or2 i_583(.A(n_729), .B(n_449), .Z(n_730));
notech_inv i_584(.A(n_730), .Z(n_496));
notech_or2 i_586(.A(n_731), .B(n_450), .Z(n_732));
notech_inv i_587(.A(n_732), .Z(n_497));
notech_or2 i_589(.A(n_733), .B(n_451), .Z(n_734));
notech_inv i_590(.A(n_734), .Z(n_498));
notech_or2 i_592(.A(n_735), .B(n_452), .Z(n_736));
notech_inv i_593(.A(n_736), .Z(n_499));
notech_or2 i_595(.A(n_737), .B(n_453), .Z(n_738));
notech_inv i_596(.A(n_738), .Z(n_500));
notech_inv i_285(.A(n_454), .Z(n_501));
notech_nand2 i_301(.A(n_462), .B(n_370802), .Z(n_517));
notech_nand2 i_302(.A(n_463), .B(n_471), .Z(n_518));
notech_inv i_311(.A(n_480), .Z(n_527));
notech_inv i_312(.A(n_481), .Z(n_528));
notech_inv i_313(.A(n_482), .Z(n_529));
notech_inv i_314(.A(n_483), .Z(n_530));
notech_inv i_315(.A(n_484), .Z(n_531));
notech_or2 i_597(.A(n_517), .B(n_501), .Z(n_740));
notech_and2 i_598(.A(n_740), .B(n_493), .Z(n_739));
notech_inv i_599(.A(n_739), .Z(n_540));
notech_and2 i_601(.A(n_518), .B(n_494), .Z(n_741));
notech_inv i_602(.A(n_741), .Z(n_541));
notech_and2 i_604(.A(n_744), .B(n_495), .Z(n_743));
notech_inv i_605(.A(n_743), .Z(n_542));
notech_or2 i_606(.A(n_520), .B(n_480), .Z(n_746));
notech_and2 i_607(.A(n_746), .B(n_496), .Z(n_745));
notech_inv i_608(.A(n_745), .Z(n_543));
notech_or2 i_609(.A(n_521), .B(n_481), .Z(n_748));
notech_and2 i_610(.A(n_748), .B(n_497), .Z(n_747));
notech_inv i_611(.A(n_747), .Z(n_544));
notech_or2 i_612(.A(n_522), .B(n_482), .Z(n_750));
notech_and2 i_613(.A(n_750), .B(n_498), .Z(n_749));
notech_inv i_614(.A(n_749), .Z(n_545));
notech_or2 i_615(.A(n_417), .B(n_483), .Z(n_752));
notech_and2 i_616(.A(n_752), .B(n_499), .Z(n_751));
notech_inv i_617(.A(n_751), .Z(n_546));
notech_or2 i_618(.A(n_418), .B(n_484), .Z(n_754));
notech_and2 i_619(.A(n_754), .B(n_500), .Z(n_753));
notech_inv i_620(.A(n_753), .Z(n_547));
notech_inv i_626(.A(n_757), .Z(i_psram_sub_function_sub[0]));
notech_inv i_632(.A(n_762), .Z(i_psram_sub_function_sub[1]));
notech_inv i_638(.A(n_767), .Z(i_psram_sub_function_sub[2]));
notech_inv i_639(.A(n_527), .Z(n_770));
notech_inv i_640(.A(n_296844), .Z(n_773));
notech_nand2 i_641(.A(n_773), .B(n_527), .Z(n_774));
notech_nand2 i_642(.A(n_296844), .B(n_770), .Z(n_771));
notech_nand2 i_643(.A(n_771), .B(n_774), .Z(n_772));
notech_inv i_644(.A(n_772), .Z(i_psram_sub_function_sub[3]));
notech_inv i_645(.A(n_528), .Z(n_775));
notech_inv i_646(.A(n_298842), .Z(n_778));
notech_nand2 i_647(.A(n_778), .B(n_528), .Z(n_779));
notech_nand2 i_648(.A(n_298842), .B(n_775), .Z(n_776));
notech_nand2 i_649(.A(n_776), .B(n_779), .Z(n_777));
notech_inv i_650(.A(n_777), .Z(i_psram_sub_function_sub[4]));
notech_inv i_651(.A(n_529), .Z(n_780));
notech_inv i_652(.A(n_300840), .Z(n_783));
notech_nand2 i_653(.A(n_783), .B(n_529), .Z(n_784));
notech_nand2 i_654(.A(n_300840), .B(n_780), .Z(n_781));
notech_nand2 i_655(.A(n_781), .B(n_784), .Z(n_782));
notech_inv i_656(.A(n_782), .Z(i_psram_sub_function_sub[5]));
notech_inv i_657(.A(n_530), .Z(n_785));
notech_inv i_658(.A(n_302838), .Z(n_788));
notech_nand2 i_659(.A(n_788), .B(n_530), .Z(n_789));
notech_nand2 i_660(.A(n_302838), .B(n_785), .Z(n_786));
notech_nand2 i_661(.A(n_786), .B(n_789), .Z(n_787));
notech_inv i_662(.A(n_787), .Z(i_psram_sub_function_sub[6]));
notech_inv i_663(.A(n_531), .Z(n_790));
notech_inv i_664(.A(n_304836), .Z(n_793));
notech_nand2 i_665(.A(n_793), .B(n_531), .Z(n_794));
notech_nand2 i_666(.A(n_304836), .B(n_790), .Z(n_791));
notech_nand2 i_667(.A(n_791), .B(n_794), .Z(n_792));
notech_inv i_668(.A(n_792), .Z(i_psram_sub_function_sub[7]));
notech_inv i_669(.A(n_708), .Z(n_795));
notech_inv i_670(.A(n_306834), .Z(n_798));
notech_nand2 i_671(.A(n_798), .B(n_708), .Z(n_799));
notech_nand2 i_672(.A(n_306834), .B(n_795), .Z(n_796));
notech_nand2 i_673(.A(n_796), .B(n_799), .Z(n_797));
notech_inv i_674(.A(n_797), .Z(i_psram_sub_function_sub[8]));
notech_inv i_675(.A(n_710), .Z(n_800));
notech_inv i_676(.A(n_308832), .Z(n_803));
notech_nand2 i_677(.A(n_803), .B(n_710), .Z(n_804));
notech_nand2 i_678(.A(n_308832), .B(n_800), .Z(n_801));
notech_nand2 i_679(.A(n_801), .B(n_804), .Z(n_802));
notech_inv i_680(.A(n_802), .Z(i_psram_sub_function_sub[9]));
notech_inv i_681(.A(n_712), .Z(n_805));
notech_inv i_682(.A(i_psram_sub_axi_araddr[10]), .Z(n_808));
notech_nand2 i_683(.A(n_808), .B(n_712), .Z(n_809));
notech_nand2 i_684(.A(i_psram_sub_axi_araddr[10]), .B(n_805), .Z(n_806)
);
notech_nand2 i_685(.A(n_806), .B(n_809), .Z(n_807));
notech_inv i_686(.A(n_807), .Z(i_psram_sub_function_sub[10]));
notech_inv i_687(.A(n_714), .Z(n_810));
notech_inv i_688(.A(i_psram_sub_axi_araddr[11]), .Z(n_813));
notech_nand2 i_689(.A(n_813), .B(n_714), .Z(n_814));
notech_nand2 i_690(.A(i_psram_sub_axi_araddr[11]), .B(n_810), .Z(n_811)
);
notech_nand2 i_691(.A(n_811), .B(n_814), .Z(n_812));
notech_inv i_692(.A(n_812), .Z(i_psram_sub_function_sub[11]));
notech_inv i_693(.A(n_716), .Z(n_815));
notech_inv i_694(.A(i_psram_sub_axi_araddr[12]), .Z(n_818));
notech_nand2 i_695(.A(n_818), .B(n_716), .Z(n_819));
notech_nand2 i_696(.A(i_psram_sub_axi_araddr[12]), .B(n_815), .Z(n_816)
);
notech_nand2 i_697(.A(n_816), .B(n_819), .Z(n_817));
notech_inv i_698(.A(n_817), .Z(i_psram_sub_function_sub[12]));
notech_inv i_699(.A(n_718), .Z(n_820));
notech_inv i_700(.A(i_psram_sub_axi_araddr[13]), .Z(n_823));
notech_nand2 i_701(.A(n_823), .B(n_718), .Z(n_824));
notech_nand2 i_702(.A(i_psram_sub_axi_araddr[13]), .B(n_820), .Z(n_821)
);
notech_nand2 i_703(.A(n_821), .B(n_824), .Z(n_822));
notech_inv i_704(.A(n_822), .Z(i_psram_sub_function_sub[13]));
notech_inv i_705(.A(n_720), .Z(n_825));
notech_inv i_706(.A(i_psram_sub_axi_araddr[14]), .Z(n_828));
notech_nand2 i_707(.A(n_828), .B(n_720), .Z(n_829));
notech_nand2 i_708(.A(i_psram_sub_axi_araddr[14]), .B(n_825), .Z(n_826)
);
notech_nand2 i_709(.A(n_826), .B(n_829), .Z(n_827));
notech_inv i_710(.A(n_827), .Z(i_psram_sub_function_sub[14]));
notech_inv i_711(.A(n_722), .Z(n_830));
notech_inv i_712(.A(i_psram_sub_axi_araddr[15]), .Z(n_833));
notech_nand2 i_713(.A(n_833), .B(n_722), .Z(n_834));
notech_nand2 i_714(.A(i_psram_sub_axi_araddr[15]), .B(n_830), .Z(n_831)
);
notech_nand2 i_715(.A(n_831), .B(n_834), .Z(n_832));
notech_inv i_716(.A(n_832), .Z(i_psram_sub_function_sub[15]));
notech_inv i_717(.A(n_540), .Z(n_835));
notech_inv i_718(.A(i_psram_sub_axi_araddr[16]), .Z(n_838));
notech_nand2 i_719(.A(n_838), .B(n_540), .Z(n_839));
notech_nand2 i_720(.A(i_psram_sub_axi_araddr[16]), .B(n_835), .Z(n_836)
);
notech_nand2 i_721(.A(n_836), .B(n_839), .Z(n_837));
notech_inv i_722(.A(n_837), .Z(i_psram_sub_function_sub[16]));
notech_inv i_723(.A(n_541), .Z(n_840));
notech_inv i_724(.A(i_psram_sub_axi_araddr[17]), .Z(n_843));
notech_nand2 i_725(.A(n_843), .B(n_541), .Z(n_844));
notech_nand2 i_726(.A(i_psram_sub_axi_araddr[17]), .B(n_840), .Z(n_841)
);
notech_nand2 i_727(.A(n_841), .B(n_844), .Z(n_842));
notech_inv i_728(.A(n_842), .Z(i_psram_sub_function_sub[17]));
notech_inv i_729(.A(n_542), .Z(n_845));
notech_inv i_730(.A(i_psram_sub_axi_araddr[18]), .Z(n_848));
notech_nand2 i_731(.A(n_848), .B(n_542), .Z(n_849));
notech_nand2 i_732(.A(i_psram_sub_axi_araddr[18]), .B(n_845), .Z(n_846)
);
notech_nand2 i_733(.A(n_846), .B(n_849), .Z(n_847));
notech_inv i_734(.A(n_847), .Z(i_psram_sub_function_sub[18]));
notech_inv i_735(.A(n_543), .Z(n_850));
notech_inv i_736(.A(i_psram_sub_axi_araddr[19]), .Z(n_853));
notech_nand2 i_737(.A(n_853), .B(n_543), .Z(n_854));
notech_nand2 i_738(.A(i_psram_sub_axi_araddr[19]), .B(n_850), .Z(n_851)
);
notech_nand2 i_739(.A(n_851), .B(n_854), .Z(n_852));
notech_inv i_740(.A(n_852), .Z(i_psram_sub_function_sub[19]));
notech_inv i_741(.A(n_544), .Z(n_855));
notech_inv i_742(.A(i_psram_sub_axi_araddr[20]), .Z(n_858));
notech_nand2 i_743(.A(n_858), .B(n_544), .Z(n_859));
notech_nand2 i_744(.A(i_psram_sub_axi_araddr[20]), .B(n_855), .Z(n_856)
);
notech_nand2 i_745(.A(n_856), .B(n_859), .Z(n_857));
notech_inv i_746(.A(n_857), .Z(i_psram_sub_function_sub[20]));
notech_inv i_747(.A(n_545), .Z(n_860));
notech_inv i_748(.A(i_psram_sub_axi_araddr[21]), .Z(n_863));
notech_nand2 i_749(.A(n_863), .B(n_545), .Z(n_864));
notech_nand2 i_750(.A(i_psram_sub_axi_araddr[21]), .B(n_860), .Z(n_861)
);
notech_nand2 i_751(.A(n_861), .B(n_864), .Z(n_862));
notech_inv i_752(.A(n_862), .Z(i_psram_sub_function_sub[21]));
notech_inv i_753(.A(n_546), .Z(n_865));
notech_inv i_754(.A(i_psram_sub_axi_araddr[22]), .Z(n_868));
notech_nand2 i_755(.A(n_868), .B(n_546), .Z(n_869));
notech_nand2 i_756(.A(i_psram_sub_axi_araddr[22]), .B(n_865), .Z(n_866)
);
notech_nand2 i_757(.A(n_866), .B(n_869), .Z(n_867));
notech_inv i_758(.A(n_867), .Z(i_psram_sub_function_sub[22]));
notech_inv i_759(.A(n_547), .Z(n_870));
notech_inv i_760(.A(i_psram_sub_axi_araddr[23]), .Z(n_873));
notech_nand2 i_761(.A(n_873), .B(n_547), .Z(n_874));
notech_nand2 i_762(.A(i_psram_sub_axi_araddr[23]), .B(n_870), .Z(n_871)
);
notech_nand2 i_763(.A(n_871), .B(n_874), .Z(n_872));
notech_inv i_764(.A(n_872), .Z(i_psram_sub_function_sub[23]));
notech_inv i_0(.A(i_psram_sub_axi_araddr[2]), .Z(\i_psram_sub_axi_araddr_0[2]
));
notech_nand2 i_1(.A(i_psram_sub_axi_araddr[2]), .B(i_psram_sub_axi_araddr
[3]), .Z(n_133));
notech_nand2 i_2(.A(i_psram_sub_axi_araddr[3]), .B(i_psram_sub_axi_araddr
[4]), .Z(n_134));
notech_nand2 i_3(.A(i_psram_sub_axi_araddr[4]), .B(i_psram_sub_axi_araddr
[5]), .Z(n_135));
notech_nand2 i_4(.A(i_psram_sub_axi_araddr[5]), .B(i_psram_sub_axi_araddr
[6]), .Z(n_136));
notech_nand2 i_5(.A(i_psram_sub_axi_araddr[6]), .B(i_psram_sub_axi_araddr
[7]), .Z(n_137));
notech_nand2 i_6(.A(i_psram_sub_axi_araddr[7]), .B(i_psram_sub_axi_araddr
[8]), .Z(n_138));
notech_nand2 i_7(.A(i_psram_sub_axi_araddr[8]), .B(i_psram_sub_axi_araddr
[9]), .Z(n_139));
notech_nand2 i_8(.A(i_psram_sub_axi_araddr[9]), .B(i_psram_sub_axi_araddr
[10]), .Z(n_140));
notech_nand2 i_9(.A(i_psram_sub_axi_araddr[10]), .B(i_psram_sub_axi_araddr
[11]), .Z(n_141));
notech_nand2 i_10(.A(i_psram_sub_axi_araddr[11]), .B(i_psram_sub_axi_araddr
[12]), .Z(n_142));
notech_nand2 i_11(.A(i_psram_sub_axi_araddr[12]), .B(i_psram_sub_axi_araddr
[13]), .Z(n_143));
notech_nand2 i_12(.A(i_psram_sub_axi_araddr[13]), .B(i_psram_sub_axi_araddr
[14]), .Z(n_144));
notech_nand2 i_13(.A(i_psram_sub_axi_araddr[14]), .B(i_psram_sub_axi_araddr
[15]), .Z(n_145));
notech_nand2 i_14(.A(i_psram_sub_axi_araddr[15]), .B(i_psram_sub_axi_araddr
[16]), .Z(n_146));
notech_nand2 i_15(.A(i_psram_sub_axi_araddr[16]), .B(i_psram_sub_axi_araddr
[17]), .Z(n_147));
notech_nand2 i_16(.A(i_psram_sub_axi_araddr[17]), .B(i_psram_sub_axi_araddr
[18]), .Z(n_148));
notech_nand2 i_17(.A(i_psram_sub_axi_araddr[18]), .B(i_psram_sub_axi_araddr
[19]), .Z(n_149));
notech_nand2 i_18(.A(i_psram_sub_axi_araddr[19]), .B(i_psram_sub_axi_araddr
[20]), .Z(n_150));
notech_nand2 i_19(.A(i_psram_sub_axi_araddr[20]), .B(i_psram_sub_axi_araddr
[21]), .Z(n_151));
notech_nand2 i_20(.A(i_psram_sub_axi_araddr[21]), .B(i_psram_sub_axi_araddr
[22]), .Z(n_152));
notech_inv i_22(.A(\i_psram_sub_axi_araddr_0[2] ), .Z(n_154));
notech_inv i_23(.A(n_133), .Z(n_265));
notech_nor2 i_24(.A(\i_psram_sub_axi_araddr_0[2] ), .B(n_134), .Z(n_156)
);
notech_nor2 i_25(.A(n_133), .B(n_135), .Z(n_157));
notech_nor2 i_26(.A(n_134), .B(n_136), .Z(n_158));
notech_nor2 i_27(.A(n_135), .B(n_137), .Z(n_159));
notech_nor2 i_28(.A(n_136), .B(n_138), .Z(n_160));
notech_nor2 i_29(.A(n_137), .B(n_139), .Z(n_161));
notech_nor2 i_30(.A(n_138), .B(n_140), .Z(n_162));
notech_nor2 i_31(.A(n_139), .B(n_141), .Z(n_163));
notech_nor2 i_32(.A(n_140), .B(n_142), .Z(n_164));
notech_nor2 i_33(.A(n_141), .B(n_143), .Z(n_165));
notech_nor2 i_34(.A(n_142), .B(n_144), .Z(n_166));
notech_nor2 i_35(.A(n_143), .B(n_145), .Z(n_167));
notech_nor2 i_36(.A(n_144), .B(n_146), .Z(n_168));
notech_nor2 i_37(.A(n_145), .B(n_147), .Z(n_169));
notech_nor2 i_38(.A(n_146), .B(n_148), .Z(n_170));
notech_nor2 i_39(.A(n_147), .B(n_149), .Z(n_171));
notech_nor2 i_40(.A(n_148), .B(n_150), .Z(n_172));
notech_nor2 i_41(.A(n_149), .B(n_151), .Z(n_173));
notech_nor2 i_42(.A(n_150), .B(n_152), .Z(n_174));
notech_inv i_44(.A(n_154), .Z(n_176));
notech_inv i_45(.A(n_265), .Z(n_177));
notech_inv i_46(.A(n_156), .Z(n_178));
notech_inv i_47(.A(n_157), .Z(n_266));
notech_nand2 i_48(.A(n_154), .B(n_158), .Z(n_180));
notech_nand2 i_49(.A(n_265), .B(n_159), .Z(n_181));
notech_nand2 i_50(.A(n_156), .B(n_160), .Z(n_182));
notech_nand2 i_51(.A(n_157), .B(n_161), .Z(n_183));
notech_nand2 i_52(.A(n_158), .B(n_162), .Z(n_184));
notech_nand2 i_53(.A(n_159), .B(n_163), .Z(n_185));
notech_nand2 i_54(.A(n_160), .B(n_164), .Z(n_186));
notech_nand2 i_55(.A(n_161), .B(n_165), .Z(n_187));
notech_nand2 i_56(.A(n_162), .B(n_166), .Z(n_188));
notech_nand2 i_57(.A(n_163), .B(n_167), .Z(n_189));
notech_nand2 i_58(.A(n_164), .B(n_168), .Z(n_190));
notech_nand2 i_59(.A(n_165), .B(n_169), .Z(n_191));
notech_nand2 i_60(.A(n_166), .B(n_170), .Z(n_192));
notech_nand2 i_61(.A(n_167), .B(n_171), .Z(n_193));
notech_nand2 i_62(.A(n_168), .B(n_172), .Z(n_194));
notech_nand2 i_63(.A(n_169), .B(n_173), .Z(n_195));
notech_nand2 i_64(.A(n_170), .B(n_174), .Z(n_196));
notech_inv i_66(.A(n_176), .Z(n_198));
notech_inv i_67(.A(n_177), .Z(n_199));
notech_inv i_68(.A(n_178), .Z(n_200));
notech_inv i_69(.A(n_266), .Z(n_201));
notech_inv i_70(.A(n_180), .Z(n_202));
notech_nor2 i_74(.A(n_176), .B(n_184), .Z(n_206));
notech_nor2 i_75(.A(n_177), .B(n_185), .Z(n_207));
notech_nor2 i_76(.A(n_178), .B(n_186), .Z(n_208));
notech_nor2 i_77(.A(n_266), .B(n_187), .Z(n_209));
notech_nor2 i_78(.A(n_180), .B(n_188), .Z(n_210));
notech_nor2 i_79(.A(n_181), .B(n_189), .Z(n_211));
notech_nor2 i_80(.A(n_182), .B(n_190), .Z(n_212));
notech_nor2 i_81(.A(n_183), .B(n_191), .Z(n_213));
notech_nor2 i_82(.A(n_184), .B(n_192), .Z(n_214));
notech_nor2 i_83(.A(n_185), .B(n_193), .Z(n_215));
notech_nor2 i_84(.A(n_186), .B(n_194), .Z(n_216));
notech_nor2 i_85(.A(n_187), .B(n_195), .Z(n_217));
notech_nor2 i_86(.A(n_188), .B(n_196), .Z(n_218));
notech_inv i_88(.A(n_198), .Z(n_220));
notech_inv i_89(.A(n_199), .Z(n_221));
notech_inv i_90(.A(n_200), .Z(n_222));
notech_inv i_91(.A(n_201), .Z(n_223));
notech_inv i_92(.A(n_202), .Z(n_224));
notech_inv i_96(.A(n_206), .Z(n_228));
notech_inv i_97(.A(n_207), .Z(n_229));
notech_inv i_98(.A(n_208), .Z(n_230));
notech_inv i_99(.A(n_209), .Z(n_231));
notech_inv i_100(.A(n_210), .Z(n_232));
notech_inv i_101(.A(n_211), .Z(n_233));
notech_inv i_102(.A(n_212), .Z(n_234));
notech_inv i_103(.A(n_213), .Z(n_272));
notech_nand2 i_104(.A(n_198), .B(n_214), .Z(n_236));
notech_nand2 i_105(.A(n_199), .B(n_215), .Z(n_237));
notech_nand2 i_106(.A(n_200), .B(n_216), .Z(n_238));
notech_nand2 i_107(.A(n_201), .B(n_217), .Z(n_239));
notech_nand2 i_108(.A(n_202), .B(n_218), .Z(n_240));
notech_inv i_132(.A(n_220), .Z(n_276));
notech_inv i_133(.A(i_psram_sub_axi_araddr[3]), .Z(n_279));
notech_nand2 i_134(.A(n_279), .B(n_220), .Z(n_280));
notech_nand2 i_135(.A(i_psram_sub_axi_araddr[3]), .B(n_276), .Z(n_277)
);
notech_nand2 i_136(.A(n_277), .B(n_280), .Z(n_278));
notech_inv i_137(.A(n_278), .Z(\i_psram_sub_axi_araddr_0[3] ));
notech_inv i_138(.A(n_221), .Z(n_281));
notech_inv i_139(.A(i_psram_sub_axi_araddr[4]), .Z(n_284));
notech_nand2 i_140(.A(n_284), .B(n_221), .Z(n_285));
notech_nand2 i_141(.A(i_psram_sub_axi_araddr[4]), .B(n_281), .Z(n_282)
);
notech_nand2 i_142(.A(n_282), .B(n_285), .Z(n_283));
notech_inv i_143(.A(n_283), .Z(\i_psram_sub_axi_araddr_0[4] ));
notech_inv i_144(.A(n_222), .Z(n_286));
notech_inv i_145(.A(i_psram_sub_axi_araddr[5]), .Z(n_289));
notech_nand2 i_146(.A(n_289), .B(n_222), .Z(n_290));
notech_nand2 i_147(.A(i_psram_sub_axi_araddr[5]), .B(n_286), .Z(n_287)
);
notech_nand2 i_148(.A(n_287), .B(n_290), .Z(n_288));
notech_inv i_149(.A(n_288), .Z(\i_psram_sub_axi_araddr_0[5] ));
notech_inv i_150(.A(n_223), .Z(n_291));
notech_inv i_151(.A(i_psram_sub_axi_araddr[6]), .Z(n_294));
notech_nand2 i_152(.A(n_294), .B(n_223), .Z(n_295));
notech_nand2 i_153(.A(i_psram_sub_axi_araddr[6]), .B(n_291), .Z(n_292)
);
notech_nand2 i_154(.A(n_292), .B(n_295), .Z(n_293));
notech_inv i_155(.A(n_293), .Z(\i_psram_sub_axi_araddr_0[6] ));
notech_inv i_156(.A(n_224), .Z(n_296));
notech_inv i_157(.A(i_psram_sub_axi_araddr[7]), .Z(n_299));
notech_nand2 i_158(.A(n_299), .B(n_224), .Z(n_300));
notech_nand2 i_159(.A(i_psram_sub_axi_araddr[7]), .B(n_296), .Z(n_297)
);
notech_nand2 i_160(.A(n_297), .B(n_300), .Z(n_298));
notech_inv i_161(.A(n_298), .Z(\i_psram_sub_axi_araddr_0[7] ));
notech_inv i_162(.A(n_181), .Z(n_301));
notech_inv i_163(.A(i_psram_sub_axi_araddr[8]), .Z(n_304));
notech_nand2 i_164(.A(n_304), .B(n_181), .Z(n_305));
notech_nand2 i_165(.A(i_psram_sub_axi_araddr[8]), .B(n_301), .Z(n_302)
);
notech_nand2 i_166(.A(n_302), .B(n_305), .Z(n_303));
notech_inv i_167(.A(n_303), .Z(\i_psram_sub_axi_araddr_0[8] ));
notech_inv i_168(.A(n_182), .Z(n_306));
notech_inv i_169(.A(i_psram_sub_axi_araddr[9]), .Z(n_309));
notech_nand2 i_170(.A(n_309), .B(n_182), .Z(n_310));
notech_nand2 i_171(.A(i_psram_sub_axi_araddr[9]), .B(n_306), .Z(n_307)
);
notech_nand2 i_172(.A(n_307), .B(n_310), .Z(n_308));
notech_inv i_173(.A(n_308), .Z(\i_psram_sub_axi_araddr_0[9] ));
notech_inv i_174(.A(n_183), .Z(n_311));
notech_inv i_175(.A(i_psram_sub_axi_araddr[10]), .Z(n_314));
notech_nand2 i_176(.A(n_314), .B(n_183), .Z(n_315));
notech_nand2 i_177(.A(i_psram_sub_axi_araddr[10]), .B(n_311), .Z(n_312)
);
notech_nand2 i_178(.A(n_312), .B(n_315), .Z(n_313));
notech_inv i_179(.A(n_313), .Z(\i_psram_sub_axi_araddr_0[10] ));
notech_inv i_180(.A(n_228), .Z(n_316));
notech_inv i_181(.A(i_psram_sub_axi_araddr[11]), .Z(n_319));
notech_nand2 i_182(.A(n_319), .B(n_228), .Z(n_320));
notech_nand2 i_183(.A(i_psram_sub_axi_araddr[11]), .B(n_316), .Z(n_317)
);
notech_nand2 i_184(.A(n_317), .B(n_320), .Z(n_318));
notech_inv i_185(.A(n_318), .Z(\i_psram_sub_axi_araddr_0[11] ));
notech_inv i_186(.A(n_229), .Z(n_321));
notech_inv i_187(.A(i_psram_sub_axi_araddr[12]), .Z(n_324));
notech_nand2 i_188(.A(n_324), .B(n_229), .Z(n_325));
notech_nand2 i_189(.A(i_psram_sub_axi_araddr[12]), .B(n_321), .Z(n_322)
);
notech_nand2 i_190(.A(n_322), .B(n_325), .Z(n_323));
notech_inv i_191(.A(n_323), .Z(\i_psram_sub_axi_araddr_0[12] ));
notech_inv i_192(.A(n_230), .Z(n_326));
notech_inv i_193(.A(i_psram_sub_axi_araddr[13]), .Z(n_329));
notech_nand2 i_194(.A(n_329), .B(n_230), .Z(n_330));
notech_nand2 i_195(.A(i_psram_sub_axi_araddr[13]), .B(n_326), .Z(n_327)
);
notech_nand2 i_196(.A(n_327), .B(n_330), .Z(n_328));
notech_inv i_197(.A(n_328), .Z(\i_psram_sub_axi_araddr_0[13] ));
notech_inv i_198(.A(n_231), .Z(n_331));
notech_inv i_199(.A(i_psram_sub_axi_araddr[14]), .Z(n_334));
notech_nand2 i_200(.A(n_334), .B(n_231), .Z(n_335));
notech_nand2 i_201(.A(i_psram_sub_axi_araddr[14]), .B(n_331), .Z(n_332)
);
notech_nand2 i_202(.A(n_332), .B(n_335), .Z(n_333));
notech_inv i_203(.A(n_333), .Z(\i_psram_sub_axi_araddr_0[14] ));
notech_inv i_204(.A(n_232), .Z(n_336));
notech_inv i_205(.A(i_psram_sub_axi_araddr[15]), .Z(n_339));
notech_nand2 i_206(.A(n_339), .B(n_232), .Z(n_340));
notech_nand2 i_207(.A(i_psram_sub_axi_araddr[15]), .B(n_336), .Z(n_337)
);
notech_nand2 i_208(.A(n_337), .B(n_340), .Z(n_338));
notech_inv i_209(.A(n_338), .Z(\i_psram_sub_axi_araddr_0[15] ));
notech_inv i_210(.A(n_233), .Z(n_341));
notech_inv i_211(.A(i_psram_sub_axi_araddr[16]), .Z(n_344));
notech_nand2 i_212(.A(n_344), .B(n_233), .Z(n_345));
notech_nand2 i_213(.A(i_psram_sub_axi_araddr[16]), .B(n_341), .Z(n_342)
);
notech_nand2 i_214(.A(n_342), .B(n_345), .Z(n_343));
notech_inv i_215(.A(n_343), .Z(\i_psram_sub_axi_araddr_0[16] ));
notech_inv i_216(.A(n_234), .Z(n_346));
notech_inv i_217(.A(i_psram_sub_axi_araddr[17]), .Z(n_349));
notech_nand2 i_218(.A(n_349), .B(n_234), .Z(n_350));
notech_nand2 i_219(.A(i_psram_sub_axi_araddr[17]), .B(n_346), .Z(n_347)
);
notech_nand2 i_220(.A(n_347), .B(n_350), .Z(n_348));
notech_inv i_221(.A(n_348), .Z(\i_psram_sub_axi_araddr_0[17] ));
notech_inv i_222(.A(n_272), .Z(n_351));
notech_inv i_223(.A(i_psram_sub_axi_araddr[18]), .Z(n_354));
notech_nand2 i_224(.A(n_354), .B(n_272), .Z(n_355));
notech_nand2 i_225(.A(i_psram_sub_axi_araddr[18]), .B(n_351), .Z(n_352)
);
notech_nand2 i_226(.A(n_352), .B(n_355), .Z(n_353));
notech_inv i_227(.A(n_353), .Z(\i_psram_sub_axi_araddr_0[18] ));
notech_inv i_228(.A(n_236), .Z(n_356));
notech_inv i_229(.A(i_psram_sub_axi_araddr[19]), .Z(n_359));
notech_nand2 i_230(.A(n_359), .B(n_236), .Z(n_360));
notech_nand2 i_231(.A(i_psram_sub_axi_araddr[19]), .B(n_356), .Z(n_357)
);
notech_nand2 i_232(.A(n_357), .B(n_360), .Z(n_358));
notech_inv i_233(.A(n_358), .Z(\i_psram_sub_axi_araddr_0[19] ));
notech_inv i_234(.A(n_237), .Z(n_361));
notech_inv i_235(.A(i_psram_sub_axi_araddr[20]), .Z(n_364));
notech_nand2 i_236(.A(n_364), .B(n_237), .Z(n_365));
notech_nand2 i_237(.A(i_psram_sub_axi_araddr[20]), .B(n_361), .Z(n_362)
);
notech_nand2 i_238(.A(n_362), .B(n_365), .Z(n_363));
notech_inv i_239(.A(n_363), .Z(\i_psram_sub_axi_araddr_0[20] ));
notech_inv i_240(.A(n_238), .Z(n_366));
notech_inv i_241(.A(i_psram_sub_axi_araddr[21]), .Z(n_369));
notech_nand2 i_242(.A(n_369), .B(n_238), .Z(n_370));
notech_nand2 i_243(.A(i_psram_sub_axi_araddr[21]), .B(n_366), .Z(n_367)
);
notech_nand2 i_244(.A(n_367), .B(n_370), .Z(n_368));
notech_inv i_245(.A(n_368), .Z(\i_psram_sub_axi_araddr_0[21] ));
notech_inv i_246(.A(n_239), .Z(n_371));
notech_inv i_247(.A(i_psram_sub_axi_araddr[22]), .Z(n_374));
notech_nand2 i_248(.A(n_374), .B(n_239), .Z(n_375));
notech_nand2 i_249(.A(i_psram_sub_axi_araddr[22]), .B(n_371), .Z(n_372)
);
notech_nand2 i_250(.A(n_372), .B(n_375), .Z(n_373));
notech_inv i_251(.A(n_373), .Z(\i_psram_sub_axi_araddr_0[22] ));
notech_inv i_252(.A(n_240), .Z(n_376));
notech_inv i_253(.A(i_psram_sub_axi_araddr[23]), .Z(n_379));
notech_nand2 i_254(.A(n_379), .B(n_240), .Z(n_380));
notech_nand2 i_255(.A(i_psram_sub_axi_araddr[23]), .B(n_376), .Z(n_377)
);
notech_nand2 i_256(.A(n_377), .B(n_380), .Z(n_378));
notech_inv i_257(.A(n_378), .Z(\i_psram_sub_axi_araddr_0[23] ));
notech_inv i_psram_sub_i_5222(.A(s00_axi_awready), .Z(i_psram_sub_n_4399
));
notech_inv i_psram_sub_i_5221(.A(i_psram_sub_go), .Z(i_psram_sub_n_4398)
);
notech_inv i_psram_sub_i_5220(.A(\i_psram_sub_axi_rdata_0[16] ), .Z(i_psram_sub_n_4397
));
notech_inv i_psram_sub_i_5219(.A(\i_psram_sub_axi_rdata_0[17] ), .Z(i_psram_sub_n_4396
));
notech_inv i_psram_sub_i_5218(.A(\i_psram_sub_axi_rdata_0[18] ), .Z(i_psram_sub_n_4395
));
notech_inv i_psram_sub_i_5217(.A(\i_psram_sub_axi_rdata_0[19] ), .Z(i_psram_sub_n_4394
));
notech_inv i_psram_sub_i_5216(.A(\i_psram_sub_axi_rdata_0[20] ), .Z(i_psram_sub_n_4393
));
notech_inv i_psram_sub_i_5215(.A(\i_psram_sub_axi_rdata_0[21] ), .Z(i_psram_sub_n_4392
));
notech_inv i_psram_sub_i_5214(.A(\i_psram_sub_axi_rdata_0[22] ), .Z(i_psram_sub_n_4391
));
notech_inv i_psram_sub_i_5213(.A(\i_psram_sub_axi_rdata_0[23] ), .Z(i_psram_sub_n_4390
));
notech_inv i_psram_sub_i_5212(.A(\i_psram_sub_axi_rdata_0[24] ), .Z(i_psram_sub_n_4389
));
notech_inv i_psram_sub_i_5211(.A(\i_psram_sub_axi_rdata_0[25] ), .Z(i_psram_sub_n_4388
));
notech_inv i_psram_sub_i_5210(.A(\i_psram_sub_axi_rdata_0[26] ), .Z(i_psram_sub_n_4387
));
notech_inv i_psram_sub_i_5209(.A(\i_psram_sub_axi_rdata_0[27] ), .Z(i_psram_sub_n_4386
));
notech_inv i_psram_sub_i_5208(.A(\i_psram_sub_axi_rdata_0[28] ), .Z(i_psram_sub_n_4385
));
notech_inv i_psram_sub_i_5207(.A(\i_psram_sub_axi_rdata_0[29] ), .Z(i_psram_sub_n_4384
));
notech_inv i_psram_sub_i_5206(.A(\i_psram_sub_axi_rdata_0[30] ), .Z(i_psram_sub_n_4383
));
notech_inv i_psram_sub_i_5205(.A(\i_psram_sub_axi_rdata_0[31] ), .Z(i_psram_sub_n_4382
));
notech_inv i_psram_sub_i_5204(.A(\i_psram_sub_axi_awaddr_0[2] ), .Z(i_psram_sub_n_4381
));
notech_inv i_psram_sub_i_5203(.A(\i_psram_sub_axi_awaddr_0[3] ), .Z(i_psram_sub_n_4380
));
notech_inv i_psram_sub_i_5202(.A(\i_psram_sub_axi_awaddr_0[4] ), .Z(i_psram_sub_n_4379
));
notech_inv i_psram_sub_i_5201(.A(\i_psram_sub_axi_awaddr_0[5] ), .Z(i_psram_sub_n_4378
));
notech_inv i_psram_sub_i_5200(.A(\i_psram_sub_axi_awaddr_0[6] ), .Z(i_psram_sub_n_4377
));
notech_inv i_psram_sub_i_5199(.A(\i_psram_sub_axi_awaddr_0[7] ), .Z(i_psram_sub_n_4376
));
notech_inv i_psram_sub_i_5198(.A(\i_psram_sub_axi_awaddr_0[8] ), .Z(i_psram_sub_n_4375
));
notech_inv i_psram_sub_i_5197(.A(\i_psram_sub_axi_awaddr_0[9] ), .Z(i_psram_sub_n_4374
));
notech_inv i_psram_sub_i_5196(.A(\i_psram_sub_axi_awaddr_0[10] ), .Z(i_psram_sub_n_4373
));
notech_inv i_psram_sub_i_5195(.A(\i_psram_sub_axi_awaddr_0[11] ), .Z(i_psram_sub_n_4372
));
notech_inv i_psram_sub_i_5194(.A(\i_psram_sub_axi_awaddr_0[12] ), .Z(i_psram_sub_n_4371
));
notech_inv i_psram_sub_i_5193(.A(\i_psram_sub_axi_awaddr_0[13] ), .Z(i_psram_sub_n_4370
));
notech_inv i_psram_sub_i_5192(.A(\i_psram_sub_axi_awaddr_0[14] ), .Z(i_psram_sub_n_4369
));
notech_inv i_psram_sub_i_5191(.A(\i_psram_sub_axi_awaddr_0[15] ), .Z(i_psram_sub_n_4368
));
notech_inv i_psram_sub_i_5190(.A(\i_psram_sub_axi_awaddr_0[16] ), .Z(i_psram_sub_n_4367
));
notech_inv i_psram_sub_i_5189(.A(\i_psram_sub_axi_awaddr_0[17] ), .Z(i_psram_sub_n_4366
));
notech_inv i_psram_sub_i_5188(.A(\i_psram_sub_axi_awaddr_0[18] ), .Z(i_psram_sub_n_4365
));
notech_inv i_psram_sub_i_5187(.A(\i_psram_sub_axi_awaddr_0[19] ), .Z(i_psram_sub_n_4364
));
notech_inv i_psram_sub_i_5186(.A(\i_psram_sub_axi_awaddr_0[20] ), .Z(i_psram_sub_n_4363
));
notech_inv i_psram_sub_i_5185(.A(\i_psram_sub_axi_awaddr_0[21] ), .Z(i_psram_sub_n_4362
));
notech_inv i_psram_sub_i_5184(.A(\i_psram_sub_axi_awaddr_0[22] ), .Z(i_psram_sub_n_4361
));
notech_inv i_psram_sub_i_5183(.A(\i_psram_sub_axi_awaddr_0[23] ), .Z(i_psram_sub_n_4360
));
notech_inv i_psram_sub_i_5182(.A(s00_axi_awlen[0]), .Z(i_psram_sub_n_4359
));
notech_inv i_psram_sub_i_5181(.A(s00_axi_awlen[1]), .Z(i_psram_sub_n_4358
));
notech_inv i_psram_sub_i_5180(.A(s00_axi_awlen[2]), .Z(i_psram_sub_n_4357
));
notech_inv i_psram_sub_i_5179(.A(s00_axi_awlen[3]), .Z(i_psram_sub_n_4356
));
notech_inv i_psram_sub_i_5178(.A(s00_axi_awlen[4]), .Z(i_psram_sub_n_4355
));
notech_inv i_psram_sub_i_5177(.A(s00_axi_awlen[5]), .Z(i_psram_sub_n_4354
));
notech_inv i_psram_sub_i_5176(.A(s00_axi_awlen[6]), .Z(i_psram_sub_n_4353
));
notech_inv i_psram_sub_i_5175(.A(s00_axi_awlen[7]), .Z(i_psram_sub_n_4352
));
notech_inv i_psram_sub_i_5174(.A(\i_psram_sub_axi_araddr_0[2] ), .Z(i_psram_sub_n_4351
));
notech_inv i_psram_sub_i_5173(.A(\i_psram_sub_axi_araddr_0[3] ), .Z(i_psram_sub_n_4350
));
notech_inv i_psram_sub_i_5172(.A(\i_psram_sub_axi_araddr_0[4] ), .Z(i_psram_sub_n_4349
));
notech_inv i_psram_sub_i_5171(.A(\i_psram_sub_axi_araddr_0[5] ), .Z(i_psram_sub_n_4348
));
notech_inv i_psram_sub_i_5170(.A(\i_psram_sub_axi_araddr_0[6] ), .Z(i_psram_sub_n_4347
));
notech_inv i_psram_sub_i_5169(.A(\i_psram_sub_axi_araddr_0[7] ), .Z(i_psram_sub_n_4346
));
notech_inv i_psram_sub_i_5168(.A(\i_psram_sub_axi_araddr_0[8] ), .Z(i_psram_sub_n_4345
));
notech_inv i_psram_sub_i_5167(.A(\i_psram_sub_axi_araddr_0[9] ), .Z(i_psram_sub_n_4344
));
notech_inv i_psram_sub_i_5166(.A(\i_psram_sub_axi_araddr_0[10] ), .Z(i_psram_sub_n_4343
));
notech_inv i_psram_sub_i_5165(.A(\i_psram_sub_axi_araddr_0[11] ), .Z(i_psram_sub_n_4342
));
notech_inv i_psram_sub_i_5164(.A(\i_psram_sub_axi_araddr_0[12] ), .Z(i_psram_sub_n_4341
));
notech_inv i_psram_sub_i_5163(.A(\i_psram_sub_axi_araddr_0[13] ), .Z(i_psram_sub_n_4340
));
notech_inv i_psram_sub_i_5162(.A(\i_psram_sub_axi_araddr_0[14] ), .Z(i_psram_sub_n_4339
));
notech_inv i_psram_sub_i_5161(.A(\i_psram_sub_axi_araddr_0[15] ), .Z(i_psram_sub_n_4338
));
notech_inv i_psram_sub_i_5160(.A(\i_psram_sub_axi_araddr_0[16] ), .Z(i_psram_sub_n_4337
));
notech_inv i_psram_sub_i_5159(.A(\i_psram_sub_axi_araddr_0[17] ), .Z(i_psram_sub_n_4336
));
notech_inv i_psram_sub_i_5158(.A(\i_psram_sub_axi_araddr_0[18] ), .Z(i_psram_sub_n_4335
));
notech_inv i_psram_sub_i_5157(.A(\i_psram_sub_axi_araddr_0[19] ), .Z(i_psram_sub_n_4334
));
notech_inv i_psram_sub_i_5156(.A(\i_psram_sub_axi_araddr_0[20] ), .Z(i_psram_sub_n_4333
));
notech_inv i_psram_sub_i_5155(.A(\i_psram_sub_axi_araddr_0[21] ), .Z(i_psram_sub_n_4332
));
notech_inv i_psram_sub_i_5154(.A(\i_psram_sub_axi_araddr_0[22] ), .Z(i_psram_sub_n_4331
));
notech_inv i_psram_sub_i_5153(.A(\i_psram_sub_axi_araddr_0[23] ), .Z(i_psram_sub_n_4330
));
notech_inv i_psram_sub_i_5152(.A(s00_axi_arlen[0]), .Z(i_psram_sub_n_4329
));
notech_inv i_psram_sub_i_5151(.A(s00_axi_arlen[1]), .Z(i_psram_sub_n_4328
));
notech_inv i_psram_sub_i_5150(.A(s00_axi_arlen[2]), .Z(i_psram_sub_n_4327
));
notech_inv i_psram_sub_i_5149(.A(s00_axi_arlen[3]), .Z(i_psram_sub_n_4326
));
notech_inv i_psram_sub_i_5148(.A(s00_axi_arlen[4]), .Z(i_psram_sub_n_4325
));
notech_inv i_psram_sub_i_5147(.A(s00_axi_arlen[5]), .Z(i_psram_sub_n_4324
));
notech_inv i_psram_sub_i_5146(.A(s00_axi_arlen[6]), .Z(i_psram_sub_n_4323
));
notech_inv i_psram_sub_i_5145(.A(s00_axi_arlen[7]), .Z(i_psram_sub_n_4322
));
notech_inv i_psram_sub_i_5144(.A(s00_axi_wvalid), .Z(i_psram_sub_n_4321)
);
notech_inv i_psram_sub_i_5143(.A(i_psram_sub_mem_idle), .Z(i_psram_sub_n_4320
));
notech_inv i_psram_sub_i_5142(.A(s00_axi_aresetn), .Z(i_psram_sub_n_4319
));
notech_inv i_psram_sub_i_5141(.A(s00_axi_arburst[1]), .Z(i_psram_sub_n_4318
));
notech_inv i_psram_sub_i_5140(.A(s00_axi_awburst[1]), .Z(i_psram_sub_n_4317
));
notech_inv i_psram_sub_i_5139(.A(s00_axi_awburst[0]), .Z(i_psram_sub_n_4316
));
notech_inv i_psram_sub_i_5138(.A(s00_axi_wstrb[3]), .Z(i_psram_sub_n_4315
));
notech_inv i_psram_sub_i_5137(.A(s00_axi_wstrb[2]), .Z(i_psram_sub_n_4314
));
notech_inv i_psram_sub_i_5136(.A(s00_axi_rdata[31]), .Z(i_psram_sub_n_4313
));
notech_inv i_psram_sub_i_5135(.A(s00_axi_rdata[30]), .Z(i_psram_sub_n_4312
));
notech_inv i_psram_sub_i_5134(.A(s00_axi_rdata[29]), .Z(i_psram_sub_n_4311
));
notech_inv i_psram_sub_i_5133(.A(s00_axi_rdata[28]), .Z(i_psram_sub_n_4310
));
notech_inv i_psram_sub_i_5132(.A(s00_axi_rdata[27]), .Z(i_psram_sub_n_4309
));
notech_inv i_psram_sub_i_5131(.A(s00_axi_rdata[26]), .Z(i_psram_sub_n_4308
));
notech_inv i_psram_sub_i_5130(.A(s00_axi_rdata[25]), .Z(i_psram_sub_n_4307
));
notech_inv i_psram_sub_i_5129(.A(s00_axi_rdata[24]), .Z(i_psram_sub_n_4306
));
notech_inv i_psram_sub_i_5128(.A(s00_axi_rdata[23]), .Z(i_psram_sub_n_4305
));
notech_inv i_psram_sub_i_5127(.A(s00_axi_rdata[22]), .Z(i_psram_sub_n_4304
));
notech_inv i_psram_sub_i_5126(.A(s00_axi_rdata[21]), .Z(i_psram_sub_n_4303
));
notech_inv i_psram_sub_i_5125(.A(s00_axi_rdata[20]), .Z(i_psram_sub_n_4302
));
notech_inv i_psram_sub_i_5124(.A(s00_axi_rdata[19]), .Z(i_psram_sub_n_4301
));
notech_inv i_psram_sub_i_5123(.A(s00_axi_rdata[18]), .Z(i_psram_sub_n_4300
));
notech_inv i_psram_sub_i_5122(.A(s00_axi_rdata[17]), .Z(i_psram_sub_n_4299
));
notech_inv i_psram_sub_i_5121(.A(s00_axi_rdata[16]), .Z(i_psram_sub_n_4298
));
notech_inv i_psram_sub_i_5120(.A(s00_axi_rdata[15]), .Z(i_psram_sub_n_4297
));
notech_inv i_psram_sub_i_5119(.A(s00_axi_rdata[14]), .Z(i_psram_sub_n_4296
));
notech_inv i_psram_sub_i_5118(.A(s00_axi_rdata[13]), .Z(i_psram_sub_n_4295
));
notech_inv i_psram_sub_i_5117(.A(s00_axi_rdata[12]), .Z(i_psram_sub_n_4294
));
notech_inv i_psram_sub_i_5116(.A(s00_axi_rdata[11]), .Z(i_psram_sub_n_4293
));
notech_inv i_psram_sub_i_5115(.A(s00_axi_rdata[10]), .Z(i_psram_sub_n_4292
));
notech_inv i_psram_sub_i_5114(.A(s00_axi_rdata[9]), .Z(i_psram_sub_n_4291
));
notech_inv i_psram_sub_i_5113(.A(s00_axi_rdata[8]), .Z(i_psram_sub_n_4290
));
notech_inv i_psram_sub_i_5112(.A(s00_axi_rdata[7]), .Z(i_psram_sub_n_4289
));
notech_inv i_psram_sub_i_5111(.A(s00_axi_rdata[6]), .Z(i_psram_sub_n_4288
));
notech_inv i_psram_sub_i_5110(.A(s00_axi_rdata[5]), .Z(i_psram_sub_n_4287
));
notech_inv i_psram_sub_i_5109(.A(s00_axi_rdata[4]), .Z(i_psram_sub_n_4286
));
notech_inv i_psram_sub_i_5108(.A(s00_axi_rdata[3]), .Z(i_psram_sub_n_4285
));
notech_inv i_psram_sub_i_5107(.A(s00_axi_rdata[2]), .Z(i_psram_sub_n_4284
));
notech_inv i_psram_sub_i_5106(.A(s00_axi_rdata[1]), .Z(i_psram_sub_n_4283
));
notech_inv i_psram_sub_i_5105(.A(s00_axi_rdata[0]), .Z(i_psram_sub_n_4282
));
notech_inv i_psram_sub_i_5104(.A(s00_axi_awaddr[23]), .Z(i_psram_sub_n_4281
));
notech_inv i_psram_sub_i_5103(.A(s00_axi_awaddr[22]), .Z(i_psram_sub_n_4280
));
notech_inv i_psram_sub_i_5102(.A(s00_axi_awaddr[21]), .Z(i_psram_sub_n_4279
));
notech_inv i_psram_sub_i_5101(.A(s00_axi_awaddr[20]), .Z(i_psram_sub_n_4278
));
notech_inv i_psram_sub_i_5100(.A(s00_axi_awaddr[19]), .Z(i_psram_sub_n_4277
));
notech_inv i_psram_sub_i_5099(.A(s00_axi_awaddr[18]), .Z(i_psram_sub_n_4276
));
notech_inv i_psram_sub_i_5098(.A(s00_axi_awaddr[17]), .Z(i_psram_sub_n_4275
));
notech_inv i_psram_sub_i_5097(.A(s00_axi_awaddr[16]), .Z(i_psram_sub_n_4274
));
notech_inv i_psram_sub_i_5096(.A(s00_axi_awaddr[15]), .Z(i_psram_sub_n_4273
));
notech_inv i_psram_sub_i_5095(.A(s00_axi_awaddr[14]), .Z(i_psram_sub_n_4272
));
notech_inv i_psram_sub_i_5094(.A(s00_axi_awaddr[13]), .Z(i_psram_sub_n_4271
));
notech_inv i_psram_sub_i_5093(.A(s00_axi_awaddr[12]), .Z(i_psram_sub_n_4270
));
notech_inv i_psram_sub_i_5092(.A(s00_axi_awaddr[11]), .Z(i_psram_sub_n_4269
));
notech_inv i_psram_sub_i_5091(.A(s00_axi_awaddr[10]), .Z(i_psram_sub_n_4268
));
notech_inv i_psram_sub_i_5090(.A(s00_axi_awaddr[9]), .Z(i_psram_sub_n_4267
));
notech_inv i_psram_sub_i_5089(.A(s00_axi_awaddr[8]), .Z(i_psram_sub_n_4266
));
notech_inv i_psram_sub_i_5088(.A(s00_axi_awaddr[7]), .Z(i_psram_sub_n_4265
));
notech_inv i_psram_sub_i_5087(.A(s00_axi_awaddr[6]), .Z(i_psram_sub_n_4264
));
notech_inv i_psram_sub_i_5086(.A(s00_axi_awaddr[5]), .Z(i_psram_sub_n_4263
));
notech_inv i_psram_sub_i_5085(.A(s00_axi_awaddr[4]), .Z(i_psram_sub_n_4262
));
notech_inv i_psram_sub_i_5084(.A(s00_axi_awaddr[3]), .Z(i_psram_sub_n_4261
));
notech_inv i_psram_sub_i_5083(.A(s00_axi_awaddr[2]), .Z(i_psram_sub_n_4260
));
notech_inv i_psram_sub_i_5082(.A(s00_axi_araddr[23]), .Z(i_psram_sub_n_4259
));
notech_inv i_psram_sub_i_5081(.A(s00_axi_araddr[22]), .Z(i_psram_sub_n_4258
));
notech_inv i_psram_sub_i_5080(.A(s00_axi_araddr[21]), .Z(i_psram_sub_n_4257
));
notech_inv i_psram_sub_i_5079(.A(s00_axi_araddr[20]), .Z(i_psram_sub_n_4256
));
notech_inv i_psram_sub_i_5078(.A(s00_axi_araddr[19]), .Z(i_psram_sub_n_4255
));
notech_inv i_psram_sub_i_5077(.A(s00_axi_araddr[18]), .Z(i_psram_sub_n_4254
));
notech_inv i_psram_sub_i_5076(.A(s00_axi_araddr[17]), .Z(i_psram_sub_n_4253
));
notech_inv i_psram_sub_i_5075(.A(s00_axi_araddr[16]), .Z(i_psram_sub_n_4252
));
notech_inv i_psram_sub_i_5074(.A(s00_axi_araddr[15]), .Z(i_psram_sub_n_4251
));
notech_inv i_psram_sub_i_5073(.A(s00_axi_araddr[14]), .Z(i_psram_sub_n_4250
));
notech_inv i_psram_sub_i_5072(.A(s00_axi_araddr[13]), .Z(i_psram_sub_n_4249
));
notech_inv i_psram_sub_i_5071(.A(s00_axi_araddr[12]), .Z(i_psram_sub_n_4248
));
notech_inv i_psram_sub_i_5070(.A(s00_axi_araddr[11]), .Z(i_psram_sub_n_4247
));
notech_inv i_psram_sub_i_5069(.A(s00_axi_araddr[10]), .Z(i_psram_sub_n_4246
));
notech_inv i_psram_sub_i_5068(.A(s00_axi_araddr[9]), .Z(i_psram_sub_n_4245
));
notech_inv i_psram_sub_i_5067(.A(s00_axi_araddr[8]), .Z(i_psram_sub_n_4244
));
notech_inv i_psram_sub_i_5066(.A(s00_axi_araddr[7]), .Z(i_psram_sub_n_4243
));
notech_inv i_psram_sub_i_5065(.A(s00_axi_araddr[6]), .Z(i_psram_sub_n_4242
));
notech_inv i_psram_sub_i_5064(.A(s00_axi_araddr[5]), .Z(i_psram_sub_n_4241
));
notech_inv i_psram_sub_i_5063(.A(s00_axi_araddr[4]), .Z(i_psram_sub_n_4240
));
notech_inv i_psram_sub_i_5062(.A(s00_axi_araddr[3]), .Z(i_psram_sub_n_4239
));
notech_inv i_psram_sub_i_5061(.A(s00_axi_araddr[2]), .Z(i_psram_sub_n_4238
));
notech_inv i_psram_sub_i_5060(.A(s00_axi_wdata[15]), .Z(i_psram_sub_n_4237
));
notech_inv i_psram_sub_i_5059(.A(s00_axi_wdata[14]), .Z(i_psram_sub_n_4236
));
notech_inv i_psram_sub_i_5058(.A(s00_axi_wdata[13]), .Z(i_psram_sub_n_4235
));
notech_inv i_psram_sub_i_5057(.A(s00_axi_wdata[12]), .Z(i_psram_sub_n_4234
));
notech_inv i_psram_sub_i_5056(.A(s00_axi_wdata[11]), .Z(i_psram_sub_n_4233
));
notech_inv i_psram_sub_i_5055(.A(s00_axi_wdata[10]), .Z(i_psram_sub_n_4232
));
notech_inv i_psram_sub_i_5054(.A(s00_axi_wdata[9]), .Z(i_psram_sub_n_4231
));
notech_inv i_psram_sub_i_5053(.A(s00_axi_wdata[8]), .Z(i_psram_sub_n_4230
));
notech_inv i_psram_sub_i_5052(.A(s00_axi_wdata[7]), .Z(i_psram_sub_n_4229
));
notech_inv i_psram_sub_i_5051(.A(s00_axi_wdata[6]), .Z(i_psram_sub_n_4228
));
notech_inv i_psram_sub_i_5050(.A(s00_axi_wdata[5]), .Z(i_psram_sub_n_4227
));
notech_inv i_psram_sub_i_5049(.A(s00_axi_wdata[4]), .Z(i_psram_sub_n_4226
));
notech_inv i_psram_sub_i_5048(.A(s00_axi_wdata[3]), .Z(i_psram_sub_n_4225
));
notech_inv i_psram_sub_i_5047(.A(s00_axi_wdata[2]), .Z(i_psram_sub_n_4224
));
notech_inv i_psram_sub_i_5046(.A(s00_axi_wdata[1]), .Z(i_psram_sub_n_4223
));
notech_inv i_psram_sub_i_5045(.A(s00_axi_wdata[0]), .Z(i_psram_sub_n_4222
));
notech_inv i_psram_sub_i_5044(.A(i_psram_sub_mem_addr[22]), .Z(i_psram_sub_n_4221
));
notech_inv i_psram_sub_i_5043(.A(i_psram_sub_mem_addr[21]), .Z(i_psram_sub_n_4220
));
notech_inv i_psram_sub_i_5042(.A(i_psram_sub_mem_addr[20]), .Z(i_psram_sub_n_4219
));
notech_inv i_psram_sub_i_5041(.A(i_psram_sub_mem_addr[19]), .Z(i_psram_sub_n_4218
));
notech_inv i_psram_sub_i_5040(.A(i_psram_sub_mem_addr[18]), .Z(i_psram_sub_n_4217
));
notech_inv i_psram_sub_i_5039(.A(i_psram_sub_mem_addr[17]), .Z(i_psram_sub_n_4216
));
notech_inv i_psram_sub_i_5038(.A(i_psram_sub_mem_addr[16]), .Z(i_psram_sub_n_4215
));
notech_inv i_psram_sub_i_5037(.A(i_psram_sub_mem_addr[15]), .Z(i_psram_sub_n_4214
));
notech_inv i_psram_sub_i_5036(.A(i_psram_sub_mem_addr[14]), .Z(i_psram_sub_n_4213
));
notech_inv i_psram_sub_i_5035(.A(i_psram_sub_mem_addr[13]), .Z(i_psram_sub_n_4212
));
notech_inv i_psram_sub_i_5034(.A(i_psram_sub_mem_addr[12]), .Z(i_psram_sub_n_4211
));
notech_inv i_psram_sub_i_5033(.A(i_psram_sub_mem_addr[11]), .Z(i_psram_sub_n_4210
));
notech_inv i_psram_sub_i_5032(.A(i_psram_sub_mem_addr[10]), .Z(i_psram_sub_n_4209
));
notech_inv i_psram_sub_i_5031(.A(i_psram_sub_mem_addr[9]), .Z(i_psram_sub_n_4208
));
notech_inv i_psram_sub_i_5030(.A(i_psram_sub_mem_addr[8]), .Z(i_psram_sub_n_4207
));
notech_inv i_psram_sub_i_5029(.A(i_psram_sub_mem_addr[7]), .Z(i_psram_sub_n_4206
));
notech_inv i_psram_sub_i_5028(.A(i_psram_sub_mem_addr[6]), .Z(i_psram_sub_n_4205
));
notech_inv i_psram_sub_i_5027(.A(i_psram_sub_mem_addr[5]), .Z(i_psram_sub_n_4204
));
notech_inv i_psram_sub_i_5026(.A(i_psram_sub_mem_addr[4]), .Z(i_psram_sub_n_4203
));
notech_inv i_psram_sub_i_5025(.A(i_psram_sub_mem_addr[3]), .Z(i_psram_sub_n_4202
));
notech_inv i_psram_sub_i_5024(.A(i_psram_sub_mem_addr[2]), .Z(i_psram_sub_n_4201
));
notech_inv i_psram_sub_i_5023(.A(i_psram_sub_mem_addr[1]), .Z(i_psram_sub_n_4200
));
notech_inv i_psram_sub_i_5022(.A(i_psram_sub_mem_addr[0]), .Z(i_psram_sub_n_4199
));
notech_inv i_psram_sub_i_5021(.A(i_psram_sub_function_plus_2[22]), .Z(i_psram_sub_n_4198
));
notech_inv i_psram_sub_i_5020(.A(i_psram_sub_function_plus_2[21]), .Z(i_psram_sub_n_4197
));
notech_inv i_psram_sub_i_5019(.A(i_psram_sub_function_plus_2[20]), .Z(i_psram_sub_n_4196
));
notech_inv i_psram_sub_i_5018(.A(i_psram_sub_function_plus_2[19]), .Z(i_psram_sub_n_4195
));
notech_inv i_psram_sub_i_5017(.A(i_psram_sub_function_plus_2[18]), .Z(i_psram_sub_n_4194
));
notech_inv i_psram_sub_i_5016(.A(i_psram_sub_function_plus_2[17]), .Z(i_psram_sub_n_4193
));
notech_inv i_psram_sub_i_5015(.A(i_psram_sub_function_plus_2[16]), .Z(i_psram_sub_n_4192
));
notech_inv i_psram_sub_i_5014(.A(i_psram_sub_function_plus_2[15]), .Z(i_psram_sub_n_4191
));
notech_inv i_psram_sub_i_5013(.A(i_psram_sub_function_plus_2[14]), .Z(i_psram_sub_n_4190
));
notech_inv i_psram_sub_i_5012(.A(i_psram_sub_function_plus_2[13]), .Z(i_psram_sub_n_4189
));
notech_inv i_psram_sub_i_5011(.A(i_psram_sub_function_plus_2[12]), .Z(i_psram_sub_n_4188
));
notech_inv i_psram_sub_i_5010(.A(i_psram_sub_function_plus_2[11]), .Z(i_psram_sub_n_4187
));
notech_inv i_psram_sub_i_5009(.A(i_psram_sub_function_plus_2[10]), .Z(i_psram_sub_n_4186
));
notech_inv i_psram_sub_i_5008(.A(i_psram_sub_function_plus_2[9]), .Z(i_psram_sub_n_4185
));
notech_inv i_psram_sub_i_5007(.A(i_psram_sub_function_plus_2[8]), .Z(i_psram_sub_n_4184
));
notech_inv i_psram_sub_i_5006(.A(i_psram_sub_function_plus_2[7]), .Z(i_psram_sub_n_4183
));
notech_inv i_psram_sub_i_5005(.A(i_psram_sub_function_plus_2[6]), .Z(i_psram_sub_n_4182
));
notech_inv i_psram_sub_i_5004(.A(i_psram_sub_function_plus_2[5]), .Z(i_psram_sub_n_4181
));
notech_inv i_psram_sub_i_5003(.A(i_psram_sub_function_plus_2[4]), .Z(i_psram_sub_n_4180
));
notech_inv i_psram_sub_i_5002(.A(i_psram_sub_function_plus_2[3]), .Z(i_psram_sub_n_4179
));
notech_inv i_psram_sub_i_5001(.A(i_psram_sub_function_plus_2[2]), .Z(i_psram_sub_n_4178
));
notech_inv i_psram_sub_i_5000(.A(i_psram_sub_function_plus_2[1]), .Z(i_psram_sub_n_4177
));
notech_inv i_psram_sub_i_4999(.A(i_psram_sub_function_plus_2[0]), .Z(i_psram_sub_n_4176
));
notech_inv i_psram_sub_i_4998(.A(i_psram_sub_axi_awaddr[23]), .Z(i_psram_sub_n_4175
));
notech_inv i_psram_sub_i_4997(.A(i_psram_sub_axi_awaddr[22]), .Z(i_psram_sub_n_4174
));
notech_inv i_psram_sub_i_4995(.A(i_psram_sub_axi_awaddr[21]), .Z(i_psram_sub_n_4173
));
notech_inv i_psram_sub_i_4994(.A(i_psram_sub_axi_awaddr[20]), .Z(i_psram_sub_n_4172
));
notech_inv i_psram_sub_i_4993(.A(i_psram_sub_axi_awaddr[19]), .Z(i_psram_sub_n_4171
));
notech_inv i_psram_sub_i_4992(.A(i_psram_sub_axi_awaddr[18]), .Z(i_psram_sub_n_4170
));
notech_inv i_psram_sub_i_4991(.A(i_psram_sub_axi_awaddr[17]), .Z(i_psram_sub_n_4169
));
notech_inv i_psram_sub_i_4990(.A(i_psram_sub_axi_awaddr[16]), .Z(i_psram_sub_n_4168
));
notech_inv i_psram_sub_i_4989(.A(i_psram_sub_axi_awaddr[15]), .Z(i_psram_sub_n_4167
));
notech_inv i_psram_sub_i_4988(.A(i_psram_sub_axi_awaddr[14]), .Z(i_psram_sub_n_4166
));
notech_inv i_psram_sub_i_4987(.A(i_psram_sub_axi_awaddr[13]), .Z(i_psram_sub_n_4165
));
notech_inv i_psram_sub_i_4986(.A(i_psram_sub_axi_awaddr[12]), .Z(i_psram_sub_n_4164
));
notech_inv i_psram_sub_i_4985(.A(i_psram_sub_axi_awaddr[11]), .Z(i_psram_sub_n_4163
));
notech_inv i_psram_sub_i_4984(.A(i_psram_sub_axi_awaddr[10]), .Z(i_psram_sub_n_4162
));
notech_inv i_psram_sub_i_4983(.A(i_psram_sub_axi_awaddr[9]), .Z(i_psram_sub_n_4161
));
notech_inv i_psram_sub_i_4982(.A(i_psram_sub_axi_awaddr[8]), .Z(i_psram_sub_n_4160
));
notech_inv i_psram_sub_i_4981(.A(i_psram_sub_axi_awaddr[7]), .Z(i_psram_sub_n_4159
));
notech_inv i_psram_sub_i_4980(.A(i_psram_sub_axi_awaddr[6]), .Z(i_psram_sub_n_4158
));
notech_inv i_psram_sub_i_4979(.A(i_psram_sub_axi_awaddr[5]), .Z(i_psram_sub_n_4157
));
notech_inv i_psram_sub_i_4978(.A(i_psram_sub_axi_awaddr[4]), .Z(i_psram_sub_n_4156
));
notech_inv i_psram_sub_i_4977(.A(i_psram_sub_axi_awaddr[3]), .Z(i_psram_sub_n_4155
));
notech_inv i_psram_sub_i_4976(.A(i_psram_sub_axi_awaddr[2]), .Z(i_psram_sub_n_4154
));
notech_inv i_psram_sub_i_4975(.A(i_psram_sub_axi_awaddr[1]), .Z(i_psram_sub_n_4153
));
notech_inv i_psram_sub_i_4974(.A(i_psram_sub_axi_awaddr[0]), .Z(i_psram_sub_n_4152
));
notech_inv i_psram_sub_i_4973(.A(i_psram_sub_function_sub_0[23]), .Z(i_psram_sub_n_4151
));
notech_inv i_psram_sub_i_4972(.A(i_psram_sub_function_sub_0[22]), .Z(i_psram_sub_n_4150
));
notech_inv i_psram_sub_i_4971(.A(i_psram_sub_function_sub_0[21]), .Z(i_psram_sub_n_4149
));
notech_inv i_psram_sub_i_4970(.A(i_psram_sub_function_sub_0[20]), .Z(i_psram_sub_n_4148
));
notech_inv i_psram_sub_i_4969(.A(i_psram_sub_function_sub_0[19]), .Z(i_psram_sub_n_4147
));
notech_inv i_psram_sub_i_4968(.A(i_psram_sub_function_sub_0[18]), .Z(i_psram_sub_n_4146
));
notech_inv i_psram_sub_i_4967(.A(i_psram_sub_function_sub_0[17]), .Z(i_psram_sub_n_4145
));
notech_inv i_psram_sub_i_4966(.A(i_psram_sub_function_sub_0[16]), .Z(i_psram_sub_n_4144
));
notech_inv i_psram_sub_i_4965(.A(i_psram_sub_function_sub_0[15]), .Z(i_psram_sub_n_4143
));
notech_inv i_psram_sub_i_4964(.A(i_psram_sub_function_sub_0[14]), .Z(i_psram_sub_n_4142
));
notech_inv i_psram_sub_i_4963(.A(i_psram_sub_function_sub_0[13]), .Z(i_psram_sub_n_4141
));
notech_inv i_psram_sub_i_4962(.A(i_psram_sub_function_sub_0[12]), .Z(i_psram_sub_n_4140
));
notech_inv i_psram_sub_i_4961(.A(i_psram_sub_function_sub_0[11]), .Z(i_psram_sub_n_4139
));
notech_inv i_psram_sub_i_4960(.A(i_psram_sub_function_sub_0[10]), .Z(i_psram_sub_n_4138
));
notech_inv i_psram_sub_i_4959(.A(i_psram_sub_function_sub_0[9]), .Z(i_psram_sub_n_4137
));
notech_inv i_psram_sub_i_4958(.A(i_psram_sub_function_sub_0[8]), .Z(i_psram_sub_n_4136
));
notech_inv i_psram_sub_i_4957(.A(i_psram_sub_function_sub_0[7]), .Z(i_psram_sub_n_4135
));
notech_inv i_psram_sub_i_4956(.A(i_psram_sub_function_sub_0[6]), .Z(i_psram_sub_n_4134
));
notech_inv i_psram_sub_i_4955(.A(i_psram_sub_function_sub_0[5]), .Z(i_psram_sub_n_4133
));
notech_inv i_psram_sub_i_4954(.A(i_psram_sub_function_sub_0[4]), .Z(i_psram_sub_n_4132
));
notech_inv i_psram_sub_i_4953(.A(i_psram_sub_function_sub_0[3]), .Z(i_psram_sub_n_4131
));
notech_inv i_psram_sub_i_4952(.A(i_psram_sub_function_sub_0[2]), .Z(i_psram_sub_n_4130
));
notech_inv i_psram_sub_i_4951(.A(i_psram_sub_function_sub_0[1]), .Z(i_psram_sub_n_4129
));
notech_inv i_psram_sub_i_4950(.A(i_psram_sub_function_sub_0[0]), .Z(i_psram_sub_n_4128
));
notech_inv i_psram_sub_i_4949(.A(i_psram_sub_axi_araddr[23]), .Z(i_psram_sub_n_4127
));
notech_inv i_psram_sub_i_4948(.A(i_psram_sub_axi_araddr[22]), .Z(i_psram_sub_n_4126
));
notech_inv i_psram_sub_i_4947(.A(i_psram_sub_axi_araddr[21]), .Z(i_psram_sub_n_4125
));
notech_inv i_psram_sub_i_4946(.A(i_psram_sub_axi_araddr[20]), .Z(i_psram_sub_n_4124
));
notech_inv i_psram_sub_i_4945(.A(i_psram_sub_axi_araddr[19]), .Z(i_psram_sub_n_4123
));
notech_inv i_psram_sub_i_4944(.A(i_psram_sub_axi_araddr[18]), .Z(i_psram_sub_n_4122
));
notech_inv i_psram_sub_i_4943(.A(i_psram_sub_axi_araddr[17]), .Z(i_psram_sub_n_4121
));
notech_inv i_psram_sub_i_4942(.A(i_psram_sub_axi_araddr[16]), .Z(i_psram_sub_n_4120
));
notech_inv i_psram_sub_i_4941(.A(i_psram_sub_axi_araddr[15]), .Z(i_psram_sub_n_4119
));
notech_inv i_psram_sub_i_4940(.A(i_psram_sub_axi_araddr[14]), .Z(i_psram_sub_n_4118
));
notech_inv i_psram_sub_i_4939(.A(i_psram_sub_axi_araddr[13]), .Z(i_psram_sub_n_4117
));
notech_inv i_psram_sub_i_4938(.A(i_psram_sub_axi_araddr[12]), .Z(i_psram_sub_n_4116
));
notech_inv i_psram_sub_i_4937(.A(i_psram_sub_axi_araddr[11]), .Z(i_psram_sub_n_4115
));
notech_inv i_psram_sub_i_4936(.A(i_psram_sub_axi_araddr[10]), .Z(i_psram_sub_n_4114
));
notech_inv i_psram_sub_i_4935(.A(i_psram_sub_axi_araddr[9]), .Z(i_psram_sub_n_4113
));
notech_inv i_psram_sub_i_4934(.A(i_psram_sub_axi_araddr[8]), .Z(i_psram_sub_n_4112
));
notech_inv i_psram_sub_i_4933(.A(i_psram_sub_axi_araddr[7]), .Z(i_psram_sub_n_4111
));
notech_inv i_psram_sub_i_4932(.A(i_psram_sub_axi_araddr[6]), .Z(i_psram_sub_n_4110
));
notech_inv i_psram_sub_i_4931(.A(i_psram_sub_axi_araddr[5]), .Z(i_psram_sub_n_4109
));
notech_inv i_psram_sub_i_4930(.A(i_psram_sub_axi_araddr[4]), .Z(i_psram_sub_n_4108
));
notech_inv i_psram_sub_i_4929(.A(i_psram_sub_axi_araddr[3]), .Z(i_psram_sub_n_4107
));
notech_inv i_psram_sub_i_4928(.A(i_psram_sub_axi_araddr[2]), .Z(i_psram_sub_n_4106
));
notech_inv i_psram_sub_i_4927(.A(i_psram_sub_axi_araddr[1]), .Z(i_psram_sub_n_4105
));
notech_inv i_psram_sub_i_4926(.A(i_psram_sub_axi_araddr[0]), .Z(i_psram_sub_n_4104
));
notech_inv i_psram_sub_i_4925(.A(i_psram_sub_function_sub[23]), .Z(i_psram_sub_n_4103
));
notech_inv i_psram_sub_i_4924(.A(i_psram_sub_function_sub[22]), .Z(i_psram_sub_n_4102
));
notech_inv i_psram_sub_i_4923(.A(i_psram_sub_function_sub[21]), .Z(i_psram_sub_n_4101
));
notech_inv i_psram_sub_i_4922(.A(i_psram_sub_function_sub[20]), .Z(i_psram_sub_n_4100
));
notech_inv i_psram_sub_i_4921(.A(i_psram_sub_function_sub[19]), .Z(i_psram_sub_n_4099
));
notech_inv i_psram_sub_i_4920(.A(i_psram_sub_function_sub[18]), .Z(i_psram_sub_n_4098
));
notech_inv i_psram_sub_i_4919(.A(i_psram_sub_function_sub[17]), .Z(i_psram_sub_n_4097
));
notech_inv i_psram_sub_i_4918(.A(i_psram_sub_function_sub[16]), .Z(i_psram_sub_n_4096
));
notech_inv i_psram_sub_i_4917(.A(i_psram_sub_function_sub[15]), .Z(i_psram_sub_n_4095
));
notech_inv i_psram_sub_i_4916(.A(i_psram_sub_function_sub[14]), .Z(i_psram_sub_n_4094
));
notech_inv i_psram_sub_i_4915(.A(i_psram_sub_function_sub[13]), .Z(i_psram_sub_n_4093
));
notech_inv i_psram_sub_i_4914(.A(i_psram_sub_function_sub[12]), .Z(i_psram_sub_n_4092
));
notech_inv i_psram_sub_i_4913(.A(i_psram_sub_function_sub[11]), .Z(i_psram_sub_n_4091
));
notech_inv i_psram_sub_i_4912(.A(i_psram_sub_function_sub[10]), .Z(i_psram_sub_n_4090
));
notech_inv i_psram_sub_i_4911(.A(i_psram_sub_function_sub[9]), .Z(i_psram_sub_n_4089
));
notech_inv i_psram_sub_i_4910(.A(i_psram_sub_function_sub[8]), .Z(i_psram_sub_n_4088
));
notech_inv i_psram_sub_i_4909(.A(i_psram_sub_function_sub[7]), .Z(i_psram_sub_n_4087
));
notech_inv i_psram_sub_i_4908(.A(i_psram_sub_function_sub[6]), .Z(i_psram_sub_n_4086
));
notech_inv i_psram_sub_i_4907(.A(i_psram_sub_function_sub[5]), .Z(i_psram_sub_n_4085
));
notech_inv i_psram_sub_i_4906(.A(i_psram_sub_function_sub[4]), .Z(i_psram_sub_n_4084
));
notech_inv i_psram_sub_i_4905(.A(i_psram_sub_function_sub[3]), .Z(i_psram_sub_n_4083
));
notech_inv i_psram_sub_i_4904(.A(i_psram_sub_function_sub[2]), .Z(i_psram_sub_n_4082
));
notech_inv i_psram_sub_i_4903(.A(i_psram_sub_function_sub[1]), .Z(i_psram_sub_n_4081
));
notech_inv i_psram_sub_i_4902(.A(i_psram_sub_function_sub[0]), .Z(i_psram_sub_n_4080
));
notech_inv i_psram_sub_i_4901(.A(i_psram_sub_mem_data_wr[15]), .Z(i_psram_sub_n_4079
));
notech_inv i_psram_sub_i_4900(.A(i_psram_sub_mem_data_wr[14]), .Z(i_psram_sub_n_4078
));
notech_inv i_psram_sub_i_4899(.A(i_psram_sub_mem_data_wr[13]), .Z(i_psram_sub_n_4077
));
notech_inv i_psram_sub_i_4898(.A(i_psram_sub_mem_data_wr[12]), .Z(i_psram_sub_n_4076
));
notech_inv i_psram_sub_i_4897(.A(i_psram_sub_mem_data_wr[11]), .Z(i_psram_sub_n_4075
));
notech_inv i_psram_sub_i_4896(.A(i_psram_sub_mem_data_wr[10]), .Z(i_psram_sub_n_4074
));
notech_inv i_psram_sub_i_4895(.A(i_psram_sub_mem_data_wr[9]), .Z(i_psram_sub_n_4073
));
notech_inv i_psram_sub_i_4894(.A(i_psram_sub_mem_data_wr[8]), .Z(i_psram_sub_n_4072
));
notech_inv i_psram_sub_i_4893(.A(i_psram_sub_mem_data_wr[7]), .Z(i_psram_sub_n_4071
));
notech_inv i_psram_sub_i_4892(.A(i_psram_sub_mem_data_wr[6]), .Z(i_psram_sub_n_4070
));
notech_inv i_psram_sub_i_4891(.A(i_psram_sub_mem_data_wr[5]), .Z(i_psram_sub_n_4069
));
notech_inv i_psram_sub_i_4890(.A(i_psram_sub_mem_data_wr[4]), .Z(i_psram_sub_n_4068
));
notech_inv i_psram_sub_i_4889(.A(i_psram_sub_mem_data_wr[3]), .Z(i_psram_sub_n_4067
));
notech_inv i_psram_sub_i_4888(.A(i_psram_sub_mem_data_wr[2]), .Z(i_psram_sub_n_4066
));
notech_inv i_psram_sub_i_4887(.A(i_psram_sub_mem_data_wr[1]), .Z(i_psram_sub_n_4065
));
notech_inv i_psram_sub_i_4886(.A(i_psram_sub_mem_data_wr[0]), .Z(i_psram_sub_n_4064
));
notech_inv i_psram_sub_i_4885(.A(i_psram_sub_n_1521), .Z(i_psram_sub_n_4063
));
notech_inv i_psram_sub_i_4884(.A(i_psram_sub_n_1516), .Z(i_psram_sub_n_4062
));
notech_inv i_psram_sub_i_4883(.A(i_psram_sub_n_951), .Z(i_psram_sub_n_4061
));
notech_inv i_psram_sub_i_4882(.A(i_psram_sub_n_1511), .Z(i_psram_sub_n_4060
));
notech_inv i_psram_sub_i_4881(.A(i_psram_sub_n_1506), .Z(i_psram_sub_n_4059
));
notech_inv i_psram_sub_i_4880(.A(i_psram_sub_n_1501), .Z(i_psram_sub_n_4058
));
notech_inv i_psram_sub_i_4879(.A(i_psram_sub_n_1496), .Z(i_psram_sub_n_4057
));
notech_inv i_psram_sub_i_4878(.A(i_psram_sub_n_1491), .Z(i_psram_sub_n_4056
));
notech_inv i_psram_sub_i_4877(.A(i_psram_sub_n_1486), .Z(i_psram_sub_n_4055
));
notech_inv i_psram_sub_i_4876(.A(i_psram_sub_n_1481), .Z(i_psram_sub_n_4054
));
notech_inv i_psram_sub_i_4875(.A(i_psram_sub_n_1476), .Z(i_psram_sub_n_4053
));
notech_inv i_psram_sub_i_4874(.A(i_psram_sub_n_1471), .Z(i_psram_sub_n_4052
));
notech_inv i_psram_sub_i_4873(.A(i_psram_sub_n_1466), .Z(i_psram_sub_n_4051
));
notech_inv i_psram_sub_i_4872(.A(i_psram_sub_n_1461), .Z(i_psram_sub_n_4050
));
notech_inv i_psram_sub_i_4871(.A(i_psram_sub_n_1456), .Z(i_psram_sub_n_4049
));
notech_inv i_psram_sub_i_4870(.A(i_psram_sub_n_1451), .Z(i_psram_sub_n_4048
));
notech_inv i_psram_sub_i_4869(.A(i_psram_sub_n_1446), .Z(i_psram_sub_n_4047
));
notech_inv i_psram_sub_i_4868(.A(i_psram_sub_n_1441), .Z(i_psram_sub_n_4046
));
notech_inv i_psram_sub_i_4867(.A(i_psram_sub_n_1436), .Z(i_psram_sub_n_4045
));
notech_inv i_psram_sub_i_4866(.A(i_psram_sub_n_1431), .Z(i_psram_sub_n_4044
));
notech_inv i_psram_sub_i_4865(.A(i_psram_sub_n_1426), .Z(i_psram_sub_n_4043
));
notech_inv i_psram_sub_i_4864(.A(i_psram_sub_n_1421), .Z(i_psram_sub_n_4042
));
notech_inv i_psram_sub_i_4863(.A(i_psram_sub_n_1416), .Z(i_psram_sub_n_4041
));
notech_inv i_psram_sub_i_4862(.A(i_psram_sub_n_1411), .Z(i_psram_sub_n_4040
));
notech_inv i_psram_sub_i_4861(.A(i_psram_sub_n_1406), .Z(i_psram_sub_n_4039
));
notech_inv i_psram_sub_i_4860(.A(i_psram_sub_n_1401), .Z(i_psram_sub_n_4038
));
notech_inv i_psram_sub_i_4859(.A(i_psram_sub_n_1396), .Z(i_psram_sub_n_4037
));
notech_inv i_psram_sub_i_4858(.A(i_psram_sub_n_1391), .Z(i_psram_sub_n_4036
));
notech_inv i_psram_sub_i_4857(.A(i_psram_sub_n_1386), .Z(i_psram_sub_n_4035
));
notech_inv i_psram_sub_i_4856(.A(i_psram_sub_n_1381), .Z(i_psram_sub_n_4034
));
notech_inv i_psram_sub_i_4855(.A(i_psram_sub_n_1376), .Z(i_psram_sub_n_4033
));
notech_inv i_psram_sub_i_4854(.A(i_psram_sub_n_1371), .Z(i_psram_sub_n_4032
));
notech_inv i_psram_sub_i_4853(.A(i_psram_sub_n_1366), .Z(i_psram_sub_n_4031
));
notech_inv i_psram_sub_i_4852(.A(i_psram_sub_n_913), .Z(i_psram_sub_n_4030
));
notech_inv i_psram_sub_i_4851(.A(i_psram_sub_axi_awv_awr_flag), .Z(i_psram_sub_n_4029
));
notech_inv i_psram_sub_i_4850(.A(i_psram_sub_n_1639), .Z(i_psram_sub_n_4028
));
notech_inv i_psram_sub_i_4849(.A(i_psram_sub_state[2]), .Z(i_psram_sub_n_4027
));
notech_inv i_psram_sub_i_4848(.A(i_psram_sub_state_5[0]), .Z(i_psram_sub_n_4026
));
notech_inv i_psram_sub_i_4847(.A(i_psram_sub_state[0]), .Z(i_psram_sub_n_4025
));
notech_inv i_psram_sub_i_4846(.A(i_psram_sub_axi_arv_arr_flag), .Z(i_psram_sub_n_4024
));
notech_inv i_psram_sub_i_4845(.A(i_psram_sub_axi_awlen[7]), .Z(i_psram_sub_n_4023
));
notech_inv i_psram_sub_i_4844(.A(i_psram_sub_axi_awlen[6]), .Z(i_psram_sub_n_4022
));
notech_inv i_psram_sub_i_4843(.A(i_psram_sub_axi_awlen[5]), .Z(i_psram_sub_n_4021
));
notech_inv i_psram_sub_i_4842(.A(i_psram_sub_axi_awlen[4]), .Z(i_psram_sub_n_4020
));
notech_inv i_psram_sub_i_4841(.A(i_psram_sub_axi_awlen[0]), .Z(i_psram_sub_n_4019
));
notech_inv i_psram_sub_i_4839(.A(i_psram_sub_axi_awlen_cntr[3]), .Z(i_psram_sub_n_4018
));
notech_inv i_psram_sub_i_4838(.A(i_psram_sub_axi_awlen_cntr[2]), .Z(i_psram_sub_n_4017
));
notech_inv i_psram_sub_i_4837(.A(i_psram_sub_n_1931), .Z(i_psram_sub_n_4016
));
notech_inv i_psram_sub_i_4836(.A(i_psram_sub_axi_awlen_cntr[1]), .Z(i_psram_sub_n_4015
));
notech_inv i_psram_sub_i_4835(.A(i_psram_sub_n_1926), .Z(i_psram_sub_n_4014
));
notech_inv i_psram_sub_i_4834(.A(i_psram_sub_axi_arlen[7]), .Z(i_psram_sub_n_4013
));
notech_inv i_psram_sub_i_4833(.A(i_psram_sub_n_799775), .Z(i_psram_sub_n_4012
));
notech_inv i_psram_sub_i_4832(.A(i_psram_sub_axi_arlen[6]), .Z(i_psram_sub_n_4011
));
notech_inv i_psram_sub_i_4831(.A(i_psram_sub_axi_arlen[5]), .Z(i_psram_sub_n_4010
));
notech_inv i_psram_sub_i_4830(.A(i_psram_sub_axi_arlen[4]), .Z(i_psram_sub_n_4009
));
notech_inv i_psram_sub_i_4829(.A(i_psram_sub_axi_arlen[0]), .Z(i_psram_sub_n_4008
));
notech_inv i_psram_sub_i_4828(.A(i_psram_sub_axi_arlen_cntr[3]), .Z(i_psram_sub_n_4007
));
notech_inv i_psram_sub_i_4827(.A(i_psram_sub_axi_arlen_cntr[2]), .Z(i_psram_sub_n_4006
));
notech_inv i_psram_sub_i_4826(.A(i_psram_sub_n_2072), .Z(i_psram_sub_n_4005
));
notech_inv i_psram_sub_i_4825(.A(i_psram_sub_axi_arlen_cntr[1]), .Z(i_psram_sub_n_4004
));
notech_inv i_psram_sub_i_4824(.A(i_psram_sub_n_2067), .Z(i_psram_sub_n_4003
));
notech_inv i_psram_sub_i_4823(.A(i_psram_sub_go_7), .Z(i_psram_sub_n_4002
));
notech_inv i_psram_sub_i_4822(.A(i_psram_sub_n_1015), .Z(i_psram_sub_n_4001
));
notech_inv i_psram_sub_i_4821(.A(i_psram_sub_n_1086), .Z(i_psram_sub_n_4000
));
notech_inv i_psram_sub_i_4820(.A(i_psram_sub_n_1022), .Z(i_psram_sub_n_3999
));
notech_inv i_psram_sub_i_4819(.A(i_psram_sub_n_1094), .Z(i_psram_sub_n_3998
));
notech_inv i_psram_sub_i_4818(.A(i_psram_sub_n_588), .Z(i_psram_sub_n_3997
));
notech_inv i_psram_sub_i_4817(.A(i_psram_sub_n_965), .Z(i_psram_sub_n_3996
));
notech_inv i_psram_sub_i_4816(.A(i_psram_sub_n_968), .Z(i_psram_sub_n_3995
));
notech_inv i_psram_sub_i_4815(.A(i_psram_sub_n_960), .Z(i_psram_sub_n_3994
));
notech_inv i_psram_sub_i_4814(.A(i_psram_sub_n_458), .Z(i_psram_sub_n_3993
));
notech_inv i_psram_sub_i_4813(.A(i_psram_sub_n_1220), .Z(i_psram_sub_n_3992
));
notech_inv i_psram_sub_i_4812(.A(i_psram_sub_n_1077), .Z(i_psram_sub_n_3991
));
notech_inv i_psram_sub_i_4811(.A(i_psram_sub_n_1006), .Z(i_psram_sub_n_3990
));
notech_mux2 i_psram_sub_i_3952(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[31]), .B(i_psram_sub_n_4063), .Z(i_psram_sub_n_3984));
notech_reg_set i_psram_sub_axi_rdata_reg_31(.CP(s00_axi_aclk), .D(i_psram_sub_n_3984
), .SD(1'b1), .Q(s00_axi_rdata[31]));
notech_mux2 i_psram_sub_i_3944(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[30]), .B(i_psram_sub_n_4062), .Z(i_psram_sub_n_3978));
notech_reg_set i_psram_sub_axi_rdata_reg_30(.CP(s00_axi_aclk), .D(i_psram_sub_n_3978
), .SD(1'b1), .Q(s00_axi_rdata[30]));
notech_ao4 i_psram_sub_i_1993(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4282
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4397), .Z(i_psram_sub_n_1366
));
notech_mux2 i_psram_sub_i_3936(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[29]), .B(i_psram_sub_n_4060), .Z(i_psram_sub_n_3972));
notech_reg_set i_psram_sub_axi_rdata_reg_29(.CP(s00_axi_aclk), .D(i_psram_sub_n_3972
), .SD(1'b1), .Q(s00_axi_rdata[29]));
notech_ao4 i_psram_sub_i_2994(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4283
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4396), .Z(i_psram_sub_n_1371
));
notech_mux2 i_psram_sub_i_3928(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[28]), .B(i_psram_sub_n_4059), .Z(i_psram_sub_n_3966));
notech_reg_set i_psram_sub_axi_rdata_reg_28(.CP(s00_axi_aclk), .D(i_psram_sub_n_3966
), .SD(1'b1), .Q(s00_axi_rdata[28]));
notech_ao4 i_psram_sub_i_3995(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4284
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4395), .Z(i_psram_sub_n_1376
));
notech_mux2 i_psram_sub_i_3920(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[27]), .B(i_psram_sub_n_4058), .Z(i_psram_sub_n_3960));
notech_reg_set i_psram_sub_axi_rdata_reg_27(.CP(s00_axi_aclk), .D(i_psram_sub_n_3960
), .SD(1'b1), .Q(s00_axi_rdata[27]));
notech_ao4 i_psram_sub_i_4996(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4285
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4394), .Z(i_psram_sub_n_1381
));
notech_mux2 i_psram_sub_i_3912(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[26]), .B(i_psram_sub_n_4057), .Z(i_psram_sub_n_3954));
notech_reg_set i_psram_sub_axi_rdata_reg_26(.CP(s00_axi_aclk), .D(i_psram_sub_n_3954
), .SD(1'b1), .Q(s00_axi_rdata[26]));
notech_ao4 i_psram_sub_i_5997(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4286
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4393), .Z(i_psram_sub_n_1386
));
notech_mux2 i_psram_sub_i_3904(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[25]), .B(i_psram_sub_n_4056), .Z(i_psram_sub_n_3948));
notech_reg_set i_psram_sub_axi_rdata_reg_25(.CP(s00_axi_aclk), .D(i_psram_sub_n_3948
), .SD(1'b1), .Q(s00_axi_rdata[25]));
notech_ao4 i_psram_sub_i_6998(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4287
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4392), .Z(i_psram_sub_n_1391
));
notech_mux2 i_psram_sub_i_3895(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[24]), .B(i_psram_sub_n_4055), .Z(i_psram_sub_n_3942));
notech_reg_set i_psram_sub_axi_rdata_reg_24(.CP(s00_axi_aclk), .D(i_psram_sub_n_3942
), .SD(1'b1), .Q(s00_axi_rdata[24]));
notech_ao4 i_psram_sub_i_7999(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4288
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4391), .Z(i_psram_sub_n_1396
));
notech_mux2 i_psram_sub_i_3887(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[23]), .B(i_psram_sub_n_4054), .Z(i_psram_sub_n_3936));
notech_reg_set i_psram_sub_axi_rdata_reg_23(.CP(s00_axi_aclk), .D(i_psram_sub_n_3936
), .SD(1'b1), .Q(s00_axi_rdata[23]));
notech_ao4 i_psram_sub_i_81000(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4289
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4390), .Z(i_psram_sub_n_1401
));
notech_mux2 i_psram_sub_i_3879(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[22]), .B(i_psram_sub_n_4053), .Z(i_psram_sub_n_3930));
notech_reg_set i_psram_sub_axi_rdata_reg_22(.CP(s00_axi_aclk), .D(i_psram_sub_n_3930
), .SD(1'b1), .Q(s00_axi_rdata[22]));
notech_ao4 i_psram_sub_i_91001(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4290
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4389), .Z(i_psram_sub_n_1406
));
notech_mux2 i_psram_sub_i_3871(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[21]), .B(i_psram_sub_n_4052), .Z(i_psram_sub_n_3924));
notech_reg_set i_psram_sub_axi_rdata_reg_21(.CP(s00_axi_aclk), .D(i_psram_sub_n_3924
), .SD(1'b1), .Q(s00_axi_rdata[21]));
notech_ao4 i_psram_sub_i_101002(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4291
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4388), .Z(i_psram_sub_n_1411
));
notech_mux2 i_psram_sub_i_3863(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[20]), .B(i_psram_sub_n_4051), .Z(i_psram_sub_n_3918));
notech_reg_set i_psram_sub_axi_rdata_reg_20(.CP(s00_axi_aclk), .D(i_psram_sub_n_3918
), .SD(1'b1), .Q(s00_axi_rdata[20]));
notech_ao4 i_psram_sub_i_111003(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4292
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4387), .Z(i_psram_sub_n_1416
));
notech_mux2 i_psram_sub_i_3855(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[19]), .B(i_psram_sub_n_4050), .Z(i_psram_sub_n_3912));
notech_reg_set i_psram_sub_axi_rdata_reg_19(.CP(s00_axi_aclk), .D(i_psram_sub_n_3912
), .SD(1'b1), .Q(s00_axi_rdata[19]));
notech_ao4 i_psram_sub_i_121004(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4293
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4386), .Z(i_psram_sub_n_1421
));
notech_mux2 i_psram_sub_i_3847(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[18]), .B(i_psram_sub_n_4049), .Z(i_psram_sub_n_3906));
notech_reg_set i_psram_sub_axi_rdata_reg_18(.CP(s00_axi_aclk), .D(i_psram_sub_n_3906
), .SD(1'b1), .Q(s00_axi_rdata[18]));
notech_ao4 i_psram_sub_i_131005(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4294
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4385), .Z(i_psram_sub_n_1426
));
notech_mux2 i_psram_sub_i_3838(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[17]), .B(i_psram_sub_n_4048), .Z(i_psram_sub_n_3900));
notech_reg_set i_psram_sub_axi_rdata_reg_17(.CP(s00_axi_aclk), .D(i_psram_sub_n_3900
), .SD(1'b1), .Q(s00_axi_rdata[17]));
notech_ao4 i_psram_sub_i_141006(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4295
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4384), .Z(i_psram_sub_n_1431
));
notech_mux2 i_psram_sub_i_3830(.S(\i_psram_sub_nbus_58[16] ), .A(s00_axi_rdata
[16]), .B(i_psram_sub_n_4047), .Z(i_psram_sub_n_3894));
notech_reg_set i_psram_sub_axi_rdata_reg_16(.CP(s00_axi_aclk), .D(i_psram_sub_n_3894
), .SD(1'b1), .Q(s00_axi_rdata[16]));
notech_ao4 i_psram_sub_i_151007(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4296
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4383), .Z(i_psram_sub_n_1436
));
notech_mux2 i_psram_sub_i_3822(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[15]), .B(i_psram_sub_n_4046), .Z(i_psram_sub_n_3888));
notech_reg_set i_psram_sub_axi_rdata_reg_15(.CP(s00_axi_aclk), .D(i_psram_sub_n_3888
), .SD(1'b1), .Q(s00_axi_rdata[15]));
notech_ao4 i_psram_sub_i_161008(.A(i_psram_sub_n_413), .B(i_psram_sub_n_4297
), .C(i_psram_sub_n_976), .D(i_psram_sub_n_4382), .Z(i_psram_sub_n_1441
));
notech_mux2 i_psram_sub_i_3814(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[14]), .B(i_psram_sub_n_4045), .Z(i_psram_sub_n_3882));
notech_reg_set i_psram_sub_axi_rdata_reg_14(.CP(s00_axi_aclk), .D(i_psram_sub_n_3882
), .SD(1'b1), .Q(s00_axi_rdata[14]));
notech_ao4 i_psram_sub_i_171009(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4298
), .C(i_psram_sub_n_4397), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1446
));
notech_mux2 i_psram_sub_i_3806(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[13]), .B(i_psram_sub_n_4044), .Z(i_psram_sub_n_3876));
notech_reg_set i_psram_sub_axi_rdata_reg_13(.CP(s00_axi_aclk), .D(i_psram_sub_n_3876
), .SD(1'b1), .Q(s00_axi_rdata[13]));
notech_ao4 i_psram_sub_i_181010(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4299
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4396), .Z(i_psram_sub_n_1451
));
notech_mux2 i_psram_sub_i_3798(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[12]), .B(i_psram_sub_n_4043), .Z(i_psram_sub_n_3870));
notech_reg_set i_psram_sub_axi_rdata_reg_12(.CP(s00_axi_aclk), .D(i_psram_sub_n_3870
), .SD(1'b1), .Q(s00_axi_rdata[12]));
notech_ao4 i_psram_sub_i_191011(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4300
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4395), .Z(i_psram_sub_n_1456
));
notech_mux2 i_psram_sub_i_3790(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[11]), .B(i_psram_sub_n_4042), .Z(i_psram_sub_n_3864));
notech_reg_set i_psram_sub_axi_rdata_reg_11(.CP(s00_axi_aclk), .D(i_psram_sub_n_3864
), .SD(1'b1), .Q(s00_axi_rdata[11]));
notech_ao4 i_psram_sub_i_201012(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4301
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4394), .Z(i_psram_sub_n_1461
));
notech_mux2 i_psram_sub_i_3782(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[10]), .B(i_psram_sub_n_4041), .Z(i_psram_sub_n_3858));
notech_reg_set i_psram_sub_axi_rdata_reg_10(.CP(s00_axi_aclk), .D(i_psram_sub_n_3858
), .SD(1'b1), .Q(s00_axi_rdata[10]));
notech_ao4 i_psram_sub_i_211013(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4302
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4393), .Z(i_psram_sub_n_1466
));
notech_mux2 i_psram_sub_i_3774(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[9]), .B(i_psram_sub_n_4040), .Z(i_psram_sub_n_3852));
notech_reg_set i_psram_sub_axi_rdata_reg_9(.CP(s00_axi_aclk), .D(i_psram_sub_n_3852
), .SD(1'b1), .Q(s00_axi_rdata[9]));
notech_ao4 i_psram_sub_i_221014(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4303
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4392), .Z(i_psram_sub_n_1471
));
notech_mux2 i_psram_sub_i_3765(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[8]), .B(i_psram_sub_n_4039), .Z(i_psram_sub_n_3846));
notech_reg_set i_psram_sub_axi_rdata_reg_8(.CP(s00_axi_aclk), .D(i_psram_sub_n_3846
), .SD(1'b1), .Q(s00_axi_rdata[8]));
notech_ao4 i_psram_sub_i_231015(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4304
), .C(i_psram_sub_n_951), .D(i_psram_sub_n_4391), .Z(i_psram_sub_n_1476
));
notech_mux2 i_psram_sub_i_3757(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[7]), .B(i_psram_sub_n_4038), .Z(i_psram_sub_n_3840));
notech_reg_set i_psram_sub_axi_rdata_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3840
), .SD(1'b1), .Q(s00_axi_rdata[7]));
notech_ao4 i_psram_sub_i_241016(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4305
), .C(i_psram_sub_n_4390), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1481
));
notech_mux2 i_psram_sub_i_3749(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[6]), .B(i_psram_sub_n_4037), .Z(i_psram_sub_n_3834));
notech_reg_set i_psram_sub_axi_rdata_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3834
), .SD(1'b1), .Q(s00_axi_rdata[6]));
notech_ao4 i_psram_sub_i_251017(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4306
), .C(i_psram_sub_n_4389), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1486
));
notech_mux2 i_psram_sub_i_3741(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[5]), .B(i_psram_sub_n_4036), .Z(i_psram_sub_n_3828));
notech_reg_set i_psram_sub_axi_rdata_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3828
), .SD(1'b1), .Q(s00_axi_rdata[5]));
notech_ao4 i_psram_sub_i_261018(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4307
), .C(i_psram_sub_n_4388), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1491
));
notech_mux2 i_psram_sub_i_3733(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[4]), .B(i_psram_sub_n_4035), .Z(i_psram_sub_n_3822));
notech_reg_set i_psram_sub_axi_rdata_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3822
), .SD(1'b1), .Q(s00_axi_rdata[4]));
notech_ao4 i_psram_sub_i_271019(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4308
), .C(i_psram_sub_n_4387), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1496
));
notech_mux2 i_psram_sub_i_3725(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[3]), .B(i_psram_sub_n_4034), .Z(i_psram_sub_n_3816));
notech_reg_set i_psram_sub_axi_rdata_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3816
), .SD(1'b1), .Q(s00_axi_rdata[3]));
notech_ao4 i_psram_sub_i_281020(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4309
), .C(i_psram_sub_n_4386), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1501
));
notech_mux2 i_psram_sub_i_3717(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[2]), .B(i_psram_sub_n_4033), .Z(i_psram_sub_n_3810));
notech_reg_set i_psram_sub_axi_rdata_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3810
), .SD(1'b1), .Q(s00_axi_rdata[2]));
notech_ao4 i_psram_sub_i_291021(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4310
), .C(i_psram_sub_n_4385), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1506
));
notech_mux2 i_psram_sub_i_3709(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[1]), .B(i_psram_sub_n_4032), .Z(i_psram_sub_n_3804));
notech_reg_set i_psram_sub_axi_rdata_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3804
), .SD(1'b1), .Q(s00_axi_rdata[1]));
notech_ao4 i_psram_sub_i_301022(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4311
), .C(i_psram_sub_n_4384), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1511
));
notech_mux2 i_psram_sub_i_3701(.S(\i_psram_sub_nbus_58[0] ), .A(s00_axi_rdata
[0]), .B(i_psram_sub_n_4031), .Z(i_psram_sub_n_3798));
notech_reg_set i_psram_sub_axi_rdata_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3798
), .SD(1'b1), .Q(s00_axi_rdata[0]));
notech_ao4 i_psram_sub_i_311023(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4312
), .C(i_psram_sub_n_4383), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1516
));
notech_and3 i_psram_sub_i_3694(.A(s00_axi_aresetn), .B(i_psram_sub_n_569
), .C(s00_axi_bresp[1]), .Z(i_psram_sub_n_3795));
notech_reg_set i_psram_sub_axi_bresp_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3795
), .SD(1'b1), .Q(s00_axi_bresp[1]));
notech_ao4 i_psram_sub_i_321024(.A(i_psram_sub_n_448), .B(i_psram_sub_n_4313
), .C(i_psram_sub_n_4382), .D(i_psram_sub_n_951), .Z(i_psram_sub_n_1521
));
notech_and3 i_psram_sub_i_3686(.A(s00_axi_aresetn), .B(s00_axi_bresp[0])
, .C(i_psram_sub_n_569), .Z(i_psram_sub_n_3789));
notech_reg_set i_psram_sub_axi_bresp_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3789
), .SD(1'b1), .Q(s00_axi_bresp[0]));
notech_nand3 i_psram_sub_i_1379(.A(i_psram_sub_n_1198), .B(i_psram_sub_n_1202
), .C(i_psram_sub_n_593), .Z(i_psram_sub_n_2037));
notech_nao3 i_psram_sub_i_3678(.A(s00_axi_bvalid), .B(\i_psram_sub_nbus_68[0]
), .C(s00_axi_bready), .Z(i_psram_sub_n_3783));
notech_nao3 i_psram_sub_i_3677(.A(s00_axi_aresetn), .B(i_psram_sub_n_2024
), .C(s00_axi_bvalid), .Z(i_psram_sub_n_3782));
notech_nand2 i_psram_sub_i_3676(.A(i_psram_sub_n_3782), .B(i_psram_sub_n_3783
), .Z(i_psram_sub_n_3780));
notech_reg_set i_psram_sub_axi_bvalid_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3780
), .SD(1'b1), .Q(s00_axi_bvalid));
notech_nand3 i_psram_sub_i_2380(.A(i_psram_sub_n_1198), .B(i_psram_sub_n_1196
), .C(i_psram_sub_n_597), .Z(i_psram_sub_n_2042));
notech_mux2 i_psram_sub_i_3668(.S(i_psram_sub_n_2173), .A(s00_axi_rlast)
, .B(i_psram_sub_n_579), .Z(i_psram_sub_n_3774));
notech_reg_set i_psram_sub_axi_rlast_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3774
), .SD(1'b1), .Q(s00_axi_rlast));
notech_nand2 i_psram_sub_i_1694(.A(i_psram_sub_n_1194), .B(i_psram_sub_n_1193
), .Z(i_psram_sub_n_1237));
notech_and3 i_psram_sub_i_3662(.A(s00_axi_aresetn), .B(i_psram_sub_n_568
), .C(s00_axi_rresp[1]), .Z(i_psram_sub_n_3771));
notech_reg_set i_psram_sub_axi_rresp_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3771
), .SD(1'b1), .Q(s00_axi_rresp[1]));
notech_nand2 i_psram_sub_i_2695(.A(i_psram_sub_n_1192), .B(i_psram_sub_n_1191
), .Z(i_psram_sub_n_1242));
notech_and3 i_psram_sub_i_3654(.A(s00_axi_aresetn), .B(s00_axi_rresp[0])
, .C(i_psram_sub_n_568), .Z(i_psram_sub_n_3765));
notech_reg_set i_psram_sub_axi_rresp_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3765
), .SD(1'b1), .Q(s00_axi_rresp[0]));
notech_nand2 i_psram_sub_i_3696(.A(i_psram_sub_n_1190), .B(i_psram_sub_n_1189
), .Z(i_psram_sub_n_1247));
notech_mux2 i_psram_sub_i_3644(.S(i_psram_sub_n_2198), .A(s00_axi_awready
), .B(i_psram_sub_n_580), .Z(i_psram_sub_n_3756));
notech_reg_set i_psram_sub_axi_awready_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3756
), .SD(1'b1), .Q(s00_axi_awready));
notech_nand2 i_psram_sub_i_4697(.A(i_psram_sub_n_1188), .B(i_psram_sub_n_1187
), .Z(i_psram_sub_n_1252));
notech_mux2 i_psram_sub_i_3636(.S(i_psram_sub_n_1786), .A(i_psram_sub_axi_awv_awr_flag
), .B(i_psram_sub_n_580), .Z(i_psram_sub_n_3750));
notech_reg_set i_psram_sub_axi_awv_awr_flag_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3750
), .SD(1'b1), .Q(i_psram_sub_axi_awv_awr_flag));
notech_nand2 i_psram_sub_i_5698(.A(i_psram_sub_n_1186), .B(i_psram_sub_n_1185
), .Z(i_psram_sub_n_1257));
notech_mux2 i_psram_sub_i_3628(.S(\i_psram_sub_nbus_56[0] ), .A(s00_axi_wready
), .B(i_psram_sub_n_4028), .Z(i_psram_sub_n_3744));
notech_reg_set i_psram_sub_axi_wready_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3744
), .SD(1'b1), .Q(s00_axi_wready));
notech_reg_set i_psram_sub_state_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_state_5
[2]), .SD(1'b1), .Q(i_psram_sub_state[2]));
notech_reg_set i_psram_sub_state_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_state_5
[1]), .SD(1'b1), .Q(i_psram_sub_state[1]));
notech_reg_set i_psram_sub_state_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_4026
), .SD(1'b1), .Q(i_psram_sub_state[0]));
notech_nand2 i_psram_sub_i_6699(.A(i_psram_sub_n_1184), .B(i_psram_sub_n_1183
), .Z(i_psram_sub_n_1262));
notech_mux2 i_psram_sub_i_3608(.S(i_psram_sub_n_2159), .A(i_psram_sub_axi_arv_arr_flag
), .B(i_psram_sub_n_581), .Z(i_psram_sub_n_3732));
notech_reg_set i_psram_sub_axi_arv_arr_flag_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3732
), .SD(1'b1), .Q(i_psram_sub_axi_arv_arr_flag));
notech_nand2 i_psram_sub_i_7700(.A(i_psram_sub_n_1182), .B(i_psram_sub_n_1181
), .Z(i_psram_sub_n_1267));
notech_mux2 i_psram_sub_i_3600(.S(i_psram_sub_n_1970), .A(s00_axi_arready
), .B(i_psram_sub_n_581), .Z(i_psram_sub_n_3726));
notech_reg_set i_psram_sub_axi_arready_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3726
), .SD(1'b1), .Q(s00_axi_arready));
notech_reg_set i_psram_sub_axi_rvalid_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_4061
), .SD(1'b1), .Q(s00_axi_rvalid));
notech_nand2 i_psram_sub_i_8701(.A(i_psram_sub_n_1180), .B(i_psram_sub_n_1179
), .Z(i_psram_sub_n_1272));
notech_mux2 i_psram_sub_i_3588(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_command
), .B(i_psram_sub_n_2054), .Z(i_psram_sub_n_3718));
notech_reg_set i_psram_sub_command_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_3718
), .SD(1'b1), .Q(i_psram_sub_command));
notech_nand2 i_psram_sub_i_9702(.A(i_psram_sub_n_1178), .B(i_psram_sub_n_1177
), .Z(i_psram_sub_n_1277));
notech_mux2 i_psram_sub_i_3580(.S(\i_psram_sub_nbus_64[0] ), .A(i_psram_sub_mem_byte_en
[1]), .B(i_psram_sub_n_2042), .Z(i_psram_sub_n_3712));
notech_reg_set i_psram_sub_mem_byte_en_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3712
), .SD(1'b1), .Q(i_psram_sub_mem_byte_en[1]));
notech_nand2 i_psram_sub_i_10703(.A(i_psram_sub_n_1176), .B(i_psram_sub_n_1175
), .Z(i_psram_sub_n_1282));
notech_mux2 i_psram_sub_i_3572(.S(\i_psram_sub_nbus_64[0] ), .A(i_psram_sub_mem_byte_en
[0]), .B(i_psram_sub_n_2037), .Z(i_psram_sub_n_3706));
notech_reg_set i_psram_sub_mem_byte_en_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3706
), .SD(1'b1), .Q(i_psram_sub_mem_byte_en[0]));
notech_nand2 i_psram_sub_i_11704(.A(i_psram_sub_n_1174), .B(i_psram_sub_n_1173
), .Z(i_psram_sub_n_1287));
notech_mux2 i_psram_sub_i_3564(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[22]), .B(i_psram_sub_n_1347), .Z(i_psram_sub_n_3700));
notech_reg_set i_psram_sub_mem_addr_reg_22(.CP(s00_axi_aclk), .D(i_psram_sub_n_3700
), .SD(1'b1), .Q(i_psram_sub_mem_addr[22]));
notech_nand2 i_psram_sub_i_12705(.A(i_psram_sub_n_1172), .B(i_psram_sub_n_1171
), .Z(i_psram_sub_n_1292));
notech_mux2 i_psram_sub_i_3556(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[21]), .B(i_psram_sub_n_1342), .Z(i_psram_sub_n_3694));
notech_reg_set i_psram_sub_mem_addr_reg_21(.CP(s00_axi_aclk), .D(i_psram_sub_n_3694
), .SD(1'b1), .Q(i_psram_sub_mem_addr[21]));
notech_nand2 i_psram_sub_i_13706(.A(i_psram_sub_n_1170), .B(i_psram_sub_n_1169
), .Z(i_psram_sub_n_1297));
notech_mux2 i_psram_sub_i_3548(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[20]), .B(i_psram_sub_n_1337), .Z(i_psram_sub_n_3688));
notech_reg_set i_psram_sub_mem_addr_reg_20(.CP(s00_axi_aclk), .D(i_psram_sub_n_3688
), .SD(1'b1), .Q(i_psram_sub_mem_addr[20]));
notech_nand2 i_psram_sub_i_14707(.A(i_psram_sub_n_1168), .B(i_psram_sub_n_1167
), .Z(i_psram_sub_n_1302));
notech_mux2 i_psram_sub_i_3540(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[19]), .B(i_psram_sub_n_1332), .Z(i_psram_sub_n_3682));
notech_reg_set i_psram_sub_mem_addr_reg_19(.CP(s00_axi_aclk), .D(i_psram_sub_n_3682
), .SD(1'b1), .Q(i_psram_sub_mem_addr[19]));
notech_nand2 i_psram_sub_i_15708(.A(i_psram_sub_n_1166), .B(i_psram_sub_n_1165
), .Z(i_psram_sub_n_1307));
notech_mux2 i_psram_sub_i_3532(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[18]), .B(i_psram_sub_n_1327), .Z(i_psram_sub_n_3676));
notech_reg_set i_psram_sub_mem_addr_reg_18(.CP(s00_axi_aclk), .D(i_psram_sub_n_3676
), .SD(1'b1), .Q(i_psram_sub_mem_addr[18]));
notech_nand2 i_psram_sub_i_16709(.A(i_psram_sub_n_1164), .B(i_psram_sub_n_1163
), .Z(i_psram_sub_n_1312));
notech_mux2 i_psram_sub_i_3524(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[17]), .B(i_psram_sub_n_1322), .Z(i_psram_sub_n_3670));
notech_reg_set i_psram_sub_mem_addr_reg_17(.CP(s00_axi_aclk), .D(i_psram_sub_n_3670
), .SD(1'b1), .Q(i_psram_sub_mem_addr[17]));
notech_nand2 i_psram_sub_i_17710(.A(i_psram_sub_n_1162), .B(i_psram_sub_n_1161
), .Z(i_psram_sub_n_1317));
notech_mux2 i_psram_sub_i_3516(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[16]), .B(i_psram_sub_n_1317), .Z(i_psram_sub_n_3664));
notech_reg_set i_psram_sub_mem_addr_reg_16(.CP(s00_axi_aclk), .D(i_psram_sub_n_3664
), .SD(1'b1), .Q(i_psram_sub_mem_addr[16]));
notech_nand2 i_psram_sub_i_18711(.A(i_psram_sub_n_1160), .B(i_psram_sub_n_1159
), .Z(i_psram_sub_n_1322));
notech_mux2 i_psram_sub_i_3508(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[15]), .B(i_psram_sub_n_1312), .Z(i_psram_sub_n_3658));
notech_reg_set i_psram_sub_mem_addr_reg_15(.CP(s00_axi_aclk), .D(i_psram_sub_n_3658
), .SD(1'b1), .Q(i_psram_sub_mem_addr[15]));
notech_nand2 i_psram_sub_i_19712(.A(i_psram_sub_n_1158), .B(i_psram_sub_n_1157
), .Z(i_psram_sub_n_1327));
notech_mux2 i_psram_sub_i_3500(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[14]), .B(i_psram_sub_n_1307), .Z(i_psram_sub_n_3652));
notech_reg_set i_psram_sub_mem_addr_reg_14(.CP(s00_axi_aclk), .D(i_psram_sub_n_3652
), .SD(1'b1), .Q(i_psram_sub_mem_addr[14]));
notech_nand2 i_psram_sub_i_20713(.A(i_psram_sub_n_1156), .B(i_psram_sub_n_1155
), .Z(i_psram_sub_n_1332));
notech_mux2 i_psram_sub_i_3492(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[13]), .B(i_psram_sub_n_1302), .Z(i_psram_sub_n_3646));
notech_reg_set i_psram_sub_mem_addr_reg_13(.CP(s00_axi_aclk), .D(i_psram_sub_n_3646
), .SD(1'b1), .Q(i_psram_sub_mem_addr[13]));
notech_nand2 i_psram_sub_i_21714(.A(i_psram_sub_n_1154), .B(i_psram_sub_n_1153
), .Z(i_psram_sub_n_1337));
notech_mux2 i_psram_sub_i_3484(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[12]), .B(i_psram_sub_n_1297), .Z(i_psram_sub_n_3640));
notech_reg_set i_psram_sub_mem_addr_reg_12(.CP(s00_axi_aclk), .D(i_psram_sub_n_3640
), .SD(1'b1), .Q(i_psram_sub_mem_addr[12]));
notech_nand2 i_psram_sub_i_22715(.A(i_psram_sub_n_1152), .B(i_psram_sub_n_1151
), .Z(i_psram_sub_n_1342));
notech_mux2 i_psram_sub_i_3476(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[11]), .B(i_psram_sub_n_1292), .Z(i_psram_sub_n_3634));
notech_reg_set i_psram_sub_mem_addr_reg_11(.CP(s00_axi_aclk), .D(i_psram_sub_n_3634
), .SD(1'b1), .Q(i_psram_sub_mem_addr[11]));
notech_nand2 i_psram_sub_i_23716(.A(i_psram_sub_n_1150), .B(i_psram_sub_n_1148
), .Z(i_psram_sub_n_1347));
notech_mux2 i_psram_sub_i_3468(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[10]), .B(i_psram_sub_n_1287), .Z(i_psram_sub_n_3628));
notech_reg_set i_psram_sub_mem_addr_reg_10(.CP(s00_axi_aclk), .D(i_psram_sub_n_3628
), .SD(1'b1), .Q(i_psram_sub_mem_addr[10]));
notech_nand2 i_psram_sub_i_1837(.A(i_psram_sub_n_1147), .B(i_psram_sub_n_460
), .Z(i_psram_sub_n_1660));
notech_mux2 i_psram_sub_i_3460(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[9]), .B(i_psram_sub_n_1282), .Z(i_psram_sub_n_3622));
notech_reg_set i_psram_sub_mem_addr_reg_9(.CP(s00_axi_aclk), .D(i_psram_sub_n_3622
), .SD(1'b1), .Q(i_psram_sub_mem_addr[9]));
notech_nand2 i_psram_sub_i_2838(.A(i_psram_sub_n_1146), .B(i_psram_sub_n_461
), .Z(i_psram_sub_n_1665));
notech_mux2 i_psram_sub_i_3452(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[8]), .B(i_psram_sub_n_1277), .Z(i_psram_sub_n_3616));
notech_reg_set i_psram_sub_mem_addr_reg_8(.CP(s00_axi_aclk), .D(i_psram_sub_n_3616
), .SD(1'b1), .Q(i_psram_sub_mem_addr[8]));
notech_nand2 i_psram_sub_i_3839(.A(i_psram_sub_n_1145), .B(i_psram_sub_n_1144
), .Z(i_psram_sub_n_1670));
notech_mux2 i_psram_sub_i_3444(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[7]), .B(i_psram_sub_n_1272), .Z(i_psram_sub_n_3610));
notech_reg_set i_psram_sub_mem_addr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3610
), .SD(1'b1), .Q(i_psram_sub_mem_addr[7]));
notech_nand2 i_psram_sub_i_4840(.A(i_psram_sub_n_1143), .B(i_psram_sub_n_1142
), .Z(i_psram_sub_n_1675));
notech_mux2 i_psram_sub_i_3436(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[6]), .B(i_psram_sub_n_1267), .Z(i_psram_sub_n_3604));
notech_reg_set i_psram_sub_mem_addr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3604
), .SD(1'b1), .Q(i_psram_sub_mem_addr[6]));
notech_nand2 i_psram_sub_i_5841(.A(i_psram_sub_n_1141), .B(i_psram_sub_n_1140
), .Z(i_psram_sub_n_1680));
notech_mux2 i_psram_sub_i_3428(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[5]), .B(i_psram_sub_n_1262), .Z(i_psram_sub_n_3598));
notech_reg_set i_psram_sub_mem_addr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3598
), .SD(1'b1), .Q(i_psram_sub_mem_addr[5]));
notech_nand2 i_psram_sub_i_6842(.A(i_psram_sub_n_1139), .B(i_psram_sub_n_1138
), .Z(i_psram_sub_n_1685));
notech_mux2 i_psram_sub_i_3420(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[4]), .B(i_psram_sub_n_1257), .Z(i_psram_sub_n_3592));
notech_reg_set i_psram_sub_mem_addr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3592
), .SD(1'b1), .Q(i_psram_sub_mem_addr[4]));
notech_nand2 i_psram_sub_i_7843(.A(i_psram_sub_n_1137), .B(i_psram_sub_n_1136
), .Z(i_psram_sub_n_1690));
notech_mux2 i_psram_sub_i_3412(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[3]), .B(i_psram_sub_n_1252), .Z(i_psram_sub_n_3586));
notech_reg_set i_psram_sub_mem_addr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3586
), .SD(1'b1), .Q(i_psram_sub_mem_addr[3]));
notech_nand2 i_psram_sub_i_8844(.A(i_psram_sub_n_1135), .B(i_psram_sub_n_1134
), .Z(i_psram_sub_n_1695));
notech_mux2 i_psram_sub_i_3404(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[2]), .B(i_psram_sub_n_1247), .Z(i_psram_sub_n_3580));
notech_reg_set i_psram_sub_mem_addr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3580
), .SD(1'b1), .Q(i_psram_sub_mem_addr[2]));
notech_nand2 i_psram_sub_i_9845(.A(i_psram_sub_n_1133), .B(i_psram_sub_n_1132
), .Z(i_psram_sub_n_1700));
notech_mux2 i_psram_sub_i_3396(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[1]), .B(i_psram_sub_n_1242), .Z(i_psram_sub_n_3574));
notech_reg_set i_psram_sub_mem_addr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3574
), .SD(1'b1), .Q(i_psram_sub_mem_addr[1]));
notech_nand2 i_psram_sub_i_10846(.A(i_psram_sub_n_1131), .B(i_psram_sub_n_1130
), .Z(i_psram_sub_n_1705));
notech_mux2 i_psram_sub_i_3388(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_addr
[0]), .B(i_psram_sub_n_1237), .Z(i_psram_sub_n_3568));
notech_reg_set i_psram_sub_mem_addr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3568
), .SD(1'b1), .Q(i_psram_sub_mem_addr[0]));
notech_nand2 i_psram_sub_i_11847(.A(i_psram_sub_n_1129), .B(i_psram_sub_n_1128
), .Z(i_psram_sub_n_1710));
notech_mux2 i_psram_sub_i_3380(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[23]), .B(i_psram_sub_n_1775), .Z(i_psram_sub_n_3562));
notech_reg_set i_psram_sub_axi_awaddr_reg_23(.CP(s00_axi_aclk), .D(i_psram_sub_n_3562
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[23]));
notech_nand2 i_psram_sub_i_12848(.A(i_psram_sub_n_1127), .B(i_psram_sub_n_1126
), .Z(i_psram_sub_n_1715));
notech_mux2 i_psram_sub_i_3372(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[22]), .B(i_psram_sub_n_1770), .Z(i_psram_sub_n_3556));
notech_reg_set i_psram_sub_axi_awaddr_reg_22(.CP(s00_axi_aclk), .D(i_psram_sub_n_3556
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[22]));
notech_nand2 i_psram_sub_i_13849(.A(i_psram_sub_n_1125), .B(i_psram_sub_n_1124
), .Z(i_psram_sub_n_1720));
notech_mux2 i_psram_sub_i_3364(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[21]), .B(i_psram_sub_n_1765), .Z(i_psram_sub_n_3550));
notech_reg_set i_psram_sub_axi_awaddr_reg_21(.CP(s00_axi_aclk), .D(i_psram_sub_n_3550
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[21]));
notech_nand2 i_psram_sub_i_14850(.A(i_psram_sub_n_1123), .B(i_psram_sub_n_1122
), .Z(i_psram_sub_n_1725));
notech_mux2 i_psram_sub_i_3356(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[20]), .B(i_psram_sub_n_1760), .Z(i_psram_sub_n_3544));
notech_reg_set i_psram_sub_axi_awaddr_reg_20(.CP(s00_axi_aclk), .D(i_psram_sub_n_3544
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[20]));
notech_nand2 i_psram_sub_i_15851(.A(i_psram_sub_n_1121), .B(i_psram_sub_n_1120
), .Z(i_psram_sub_n_1730));
notech_mux2 i_psram_sub_i_3348(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[19]), .B(i_psram_sub_n_1755), .Z(i_psram_sub_n_3538));
notech_reg_set i_psram_sub_axi_awaddr_reg_19(.CP(s00_axi_aclk), .D(i_psram_sub_n_3538
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[19]));
notech_nand2 i_psram_sub_i_16852(.A(i_psram_sub_n_1119), .B(i_psram_sub_n_1118
), .Z(i_psram_sub_n_1735));
notech_mux2 i_psram_sub_i_3340(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[18]), .B(i_psram_sub_n_1750), .Z(i_psram_sub_n_3532));
notech_reg_set i_psram_sub_axi_awaddr_reg_18(.CP(s00_axi_aclk), .D(i_psram_sub_n_3532
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[18]));
notech_nand2 i_psram_sub_i_17853(.A(i_psram_sub_n_1117), .B(i_psram_sub_n_1116
), .Z(i_psram_sub_n_1740));
notech_mux2 i_psram_sub_i_3332(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[17]), .B(i_psram_sub_n_1745), .Z(i_psram_sub_n_3526));
notech_reg_set i_psram_sub_axi_awaddr_reg_17(.CP(s00_axi_aclk), .D(i_psram_sub_n_3526
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[17]));
notech_nand2 i_psram_sub_i_18854(.A(i_psram_sub_n_1115), .B(i_psram_sub_n_1114
), .Z(i_psram_sub_n_1745));
notech_mux2 i_psram_sub_i_3323(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[16]), .B(i_psram_sub_n_1740), .Z(i_psram_sub_n_3520));
notech_reg_set i_psram_sub_axi_awaddr_reg_16(.CP(s00_axi_aclk), .D(i_psram_sub_n_3520
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[16]));
notech_nand2 i_psram_sub_i_19855(.A(i_psram_sub_n_1113), .B(i_psram_sub_n_1112
), .Z(i_psram_sub_n_1750));
notech_mux2 i_psram_sub_i_3315(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[15]), .B(i_psram_sub_n_1735), .Z(i_psram_sub_n_3514));
notech_reg_set i_psram_sub_axi_awaddr_reg_15(.CP(s00_axi_aclk), .D(i_psram_sub_n_3514
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[15]));
notech_nand2 i_psram_sub_i_20856(.A(i_psram_sub_n_1111), .B(i_psram_sub_n_1110
), .Z(i_psram_sub_n_1755));
notech_mux2 i_psram_sub_i_3307(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[14]), .B(i_psram_sub_n_1730), .Z(i_psram_sub_n_3508));
notech_reg_set i_psram_sub_axi_awaddr_reg_14(.CP(s00_axi_aclk), .D(i_psram_sub_n_3508
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[14]));
notech_nand2 i_psram_sub_i_21857(.A(i_psram_sub_n_1109), .B(i_psram_sub_n_1108
), .Z(i_psram_sub_n_1760));
notech_mux2 i_psram_sub_i_3299(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[13]), .B(i_psram_sub_n_1725), .Z(i_psram_sub_n_3502));
notech_reg_set i_psram_sub_axi_awaddr_reg_13(.CP(s00_axi_aclk), .D(i_psram_sub_n_3502
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[13]));
notech_nand2 i_psram_sub_i_22858(.A(i_psram_sub_n_1107), .B(i_psram_sub_n_1106
), .Z(i_psram_sub_n_1765));
notech_mux2 i_psram_sub_i_3291(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[12]), .B(i_psram_sub_n_1720), .Z(i_psram_sub_n_3496));
notech_reg_set i_psram_sub_axi_awaddr_reg_12(.CP(s00_axi_aclk), .D(i_psram_sub_n_3496
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[12]));
notech_nand2 i_psram_sub_i_23859(.A(i_psram_sub_n_1105), .B(i_psram_sub_n_1104
), .Z(i_psram_sub_n_1770));
notech_mux2 i_psram_sub_i_3283(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[11]), .B(i_psram_sub_n_1715), .Z(i_psram_sub_n_3490));
notech_reg_set i_psram_sub_axi_awaddr_reg_11(.CP(s00_axi_aclk), .D(i_psram_sub_n_3490
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[11]));
notech_nand2 i_psram_sub_i_24860(.A(i_psram_sub_n_1103), .B(i_psram_sub_n_1098
), .Z(i_psram_sub_n_1775));
notech_mux2 i_psram_sub_i_3275(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[10]), .B(i_psram_sub_n_1710), .Z(i_psram_sub_n_3484));
notech_reg_set i_psram_sub_axi_awaddr_reg_10(.CP(s00_axi_aclk), .D(i_psram_sub_n_3484
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[10]));
notech_ao4 i_psram_sub_i_21066(.A(i_psram_sub_n_4015), .B(i_psram_sub_n_799775
), .C(\i_psram_sub_nbus_63[0] ), .D(i_psram_sub_n_1084), .Z(i_psram_sub_n_1926
));
notech_mux2 i_psram_sub_i_3267(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[9]), .B(i_psram_sub_n_1705), .Z(i_psram_sub_n_3478));
notech_reg_set i_psram_sub_axi_awaddr_reg_9(.CP(s00_axi_aclk), .D(i_psram_sub_n_3478
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[9]));
notech_ao4 i_psram_sub_i_31067(.A(i_psram_sub_n_4017), .B(i_psram_sub_n_799775
), .C(\i_psram_sub_nbus_63[0] ), .D(i_psram_sub_n_494), .Z(i_psram_sub_n_1931
));
notech_mux2 i_psram_sub_i_3259(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[8]), .B(i_psram_sub_n_1700), .Z(i_psram_sub_n_3472));
notech_reg_set i_psram_sub_axi_awaddr_reg_8(.CP(s00_axi_aclk), .D(i_psram_sub_n_3472
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[8]));
notech_nand2 i_psram_sub_i_1765(.A(i_psram_sub_n_1075), .B(i_psram_sub_n_508
), .Z(i_psram_sub_n_1797));
notech_mux2 i_psram_sub_i_3251(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[7]), .B(i_psram_sub_n_1695), .Z(i_psram_sub_n_3466));
notech_reg_set i_psram_sub_axi_awaddr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3466
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[7]));
notech_nand2 i_psram_sub_i_2766(.A(i_psram_sub_n_1074), .B(i_psram_sub_n_509
), .Z(i_psram_sub_n_1802));
notech_mux2 i_psram_sub_i_3243(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[6]), .B(i_psram_sub_n_1690), .Z(i_psram_sub_n_3460));
notech_reg_set i_psram_sub_axi_awaddr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3460
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[6]));
notech_nand2 i_psram_sub_i_3767(.A(i_psram_sub_n_1073), .B(i_psram_sub_n_1072
), .Z(i_psram_sub_n_1807));
notech_mux2 i_psram_sub_i_3235(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[5]), .B(i_psram_sub_n_1685), .Z(i_psram_sub_n_3454));
notech_reg_set i_psram_sub_axi_awaddr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3454
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[5]));
notech_nand2 i_psram_sub_i_4768(.A(i_psram_sub_n_1071), .B(i_psram_sub_n_1070
), .Z(i_psram_sub_n_1812));
notech_mux2 i_psram_sub_i_3227(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[4]), .B(i_psram_sub_n_1680), .Z(i_psram_sub_n_3448));
notech_reg_set i_psram_sub_axi_awaddr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3448
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[4]));
notech_nand2 i_psram_sub_i_5769(.A(i_psram_sub_n_1069), .B(i_psram_sub_n_1068
), .Z(i_psram_sub_n_1817));
notech_mux2 i_psram_sub_i_3219(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[3]), .B(i_psram_sub_n_1675), .Z(i_psram_sub_n_3442));
notech_reg_set i_psram_sub_axi_awaddr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3442
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[3]));
notech_nand2 i_psram_sub_i_6770(.A(i_psram_sub_n_1067), .B(i_psram_sub_n_1066
), .Z(i_psram_sub_n_1822));
notech_mux2 i_psram_sub_i_3211(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[2]), .B(i_psram_sub_n_1670), .Z(i_psram_sub_n_3436));
notech_reg_set i_psram_sub_axi_awaddr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3436
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[2]));
notech_nand2 i_psram_sub_i_7771(.A(i_psram_sub_n_1065), .B(i_psram_sub_n_1064
), .Z(i_psram_sub_n_1827));
notech_mux2 i_psram_sub_i_3203(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[1]), .B(i_psram_sub_n_1665), .Z(i_psram_sub_n_3430));
notech_reg_set i_psram_sub_axi_awaddr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3430
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[1]));
notech_nand2 i_psram_sub_i_8772(.A(i_psram_sub_n_1063), .B(i_psram_sub_n_1062
), .Z(i_psram_sub_n_1832));
notech_mux2 i_psram_sub_i_3195(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awaddr
[0]), .B(i_psram_sub_n_1660), .Z(i_psram_sub_n_3424));
notech_reg_set i_psram_sub_axi_awaddr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3424
), .SD(1'b1), .Q(i_psram_sub_axi_awaddr[0]));
notech_nand2 i_psram_sub_i_9773(.A(i_psram_sub_n_1061), .B(i_psram_sub_n_1060
), .Z(i_psram_sub_n_1837));
notech_mux2 i_psram_sub_i_3187(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[7]), .B(i_psram_sub_n_798774), .Z(i_psram_sub_n_3418));
notech_reg_set i_psram_sub_axi_awlen_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3418
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[7]));
notech_nand2 i_psram_sub_i_10774(.A(i_psram_sub_n_1059), .B(i_psram_sub_n_1058
), .Z(i_psram_sub_n_1842));
notech_mux2 i_psram_sub_i_3179(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[6]), .B(i_psram_sub_n_797773), .Z(i_psram_sub_n_3412));
notech_reg_set i_psram_sub_axi_awlen_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3412
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[6]));
notech_nand2 i_psram_sub_i_11775(.A(i_psram_sub_n_1057), .B(i_psram_sub_n_1056
), .Z(i_psram_sub_n_1847));
notech_mux2 i_psram_sub_i_3171(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[5]), .B(i_psram_sub_n_796772), .Z(i_psram_sub_n_3406));
notech_reg_set i_psram_sub_axi_awlen_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3406
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[5]));
notech_nand2 i_psram_sub_i_12776(.A(i_psram_sub_n_1055), .B(i_psram_sub_n_1054
), .Z(i_psram_sub_n_1852));
notech_mux2 i_psram_sub_i_3163(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[4]), .B(i_psram_sub_n_795771), .Z(i_psram_sub_n_3400));
notech_reg_set i_psram_sub_axi_awlen_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3400
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[4]));
notech_nand2 i_psram_sub_i_13777(.A(i_psram_sub_n_1053), .B(i_psram_sub_n_1052
), .Z(i_psram_sub_n_1857));
notech_mux2 i_psram_sub_i_3155(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[3]), .B(i_psram_sub_n_794770), .Z(i_psram_sub_n_3394));
notech_reg_set i_psram_sub_axi_awlen_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3394
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[3]));
notech_nand2 i_psram_sub_i_14778(.A(i_psram_sub_n_1051), .B(i_psram_sub_n_1050
), .Z(i_psram_sub_n_1862));
notech_mux2 i_psram_sub_i_3147(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[2]), .B(i_psram_sub_n_793769), .Z(i_psram_sub_n_3388));
notech_reg_set i_psram_sub_axi_awlen_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3388
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[2]));
notech_nand2 i_psram_sub_i_15779(.A(i_psram_sub_n_1049), .B(i_psram_sub_n_1048
), .Z(i_psram_sub_n_1867));
notech_mux2 i_psram_sub_i_3139(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[1]), .B(i_psram_sub_n_792768), .Z(i_psram_sub_n_3382));
notech_reg_set i_psram_sub_axi_awlen_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3382
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[1]));
notech_nand2 i_psram_sub_i_16780(.A(i_psram_sub_n_1047), .B(i_psram_sub_n_1046
), .Z(i_psram_sub_n_1872));
notech_mux2 i_psram_sub_i_3131(.S(\i_psram_sub_nbus_63[0] ), .A(i_psram_sub_axi_awlen
[0]), .B(i_psram_sub_n_791767), .Z(i_psram_sub_n_3376));
notech_reg_set i_psram_sub_axi_awlen_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3376
), .SD(1'b1), .Q(i_psram_sub_axi_awlen[0]));
notech_nand2 i_psram_sub_i_17781(.A(i_psram_sub_n_1045), .B(i_psram_sub_n_1044
), .Z(i_psram_sub_n_1877));
notech_mux2 i_psram_sub_i_3123(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[7]), .B(i_psram_sub_n_804780), .Z(i_psram_sub_n_3370));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3370
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[7]));
notech_nand2 i_psram_sub_i_18782(.A(i_psram_sub_n_1043), .B(i_psram_sub_n_1042
), .Z(i_psram_sub_n_1882));
notech_mux2 i_psram_sub_i_3115(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[6]), .B(i_psram_sub_n_803779), .Z(i_psram_sub_n_3364));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3364
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[6]));
notech_nand2 i_psram_sub_i_19783(.A(i_psram_sub_n_1041), .B(i_psram_sub_n_1040
), .Z(i_psram_sub_n_1887));
notech_mux2 i_psram_sub_i_3107(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[5]), .B(i_psram_sub_n_802778), .Z(i_psram_sub_n_3358));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3358
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[5]));
notech_nand2 i_psram_sub_i_20784(.A(i_psram_sub_n_1039), .B(i_psram_sub_n_1038
), .Z(i_psram_sub_n_1892));
notech_mux2 i_psram_sub_i_3099(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[4]), .B(i_psram_sub_n_801777), .Z(i_psram_sub_n_3352));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3352
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[4]));
notech_nand2 i_psram_sub_i_21785(.A(i_psram_sub_n_1037), .B(i_psram_sub_n_1036
), .Z(i_psram_sub_n_1897));
notech_mux2 i_psram_sub_i_3091(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[3]), .B(i_psram_sub_n_800776), .Z(i_psram_sub_n_3346));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3346
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[3]));
notech_nand2 i_psram_sub_i_22786(.A(i_psram_sub_n_1035), .B(i_psram_sub_n_1034
), .Z(i_psram_sub_n_1902));
notech_mux2 i_psram_sub_i_3083(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[2]), .B(i_psram_sub_n_4016), .Z(i_psram_sub_n_3340));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3340
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[2]));
notech_nand2 i_psram_sub_i_23787(.A(i_psram_sub_n_1033), .B(i_psram_sub_n_1032
), .Z(i_psram_sub_n_1907));
notech_mux2 i_psram_sub_i_3075(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[1]), .B(i_psram_sub_n_4014), .Z(i_psram_sub_n_3334));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3334
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[1]));
notech_nand2 i_psram_sub_i_24788(.A(i_psram_sub_n_1031), .B(i_psram_sub_n_1026
), .Z(i_psram_sub_n_1912));
notech_mux2 i_psram_sub_i_3067(.S(\i_psram_sub_nbus_60[0] ), .A(i_psram_sub_axi_awlen_cntr
[0]), .B(i_psram_sub_n_4012), .Z(i_psram_sub_n_3328));
notech_reg_set i_psram_sub_axi_awlen_cntr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3328
), .SD(1'b1), .Q(i_psram_sub_axi_awlen_cntr[0]));
notech_ao4 i_psram_sub_i_21050(.A(i_psram_sub_n_913), .B(i_psram_sub_n_4004
), .C(\i_psram_sub_nbus_67[0] ), .D(i_psram_sub_n_1013), .Z(i_psram_sub_n_2067
));
notech_mux2 i_psram_sub_i_3059(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[23]), .B(i_psram_sub_n_1912), .Z(i_psram_sub_n_3322));
notech_reg_set i_psram_sub_axi_araddr_reg_23(.CP(s00_axi_aclk), .D(i_psram_sub_n_3322
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[23]));
notech_ao4 i_psram_sub_i_31051(.A(i_psram_sub_n_4006), .B(i_psram_sub_n_913
), .C(i_psram_sub_n_535), .D(\i_psram_sub_nbus_67[0] ), .Z(i_psram_sub_n_2072
));
notech_mux2 i_psram_sub_i_3051(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[22]), .B(i_psram_sub_n_1907), .Z(i_psram_sub_n_3316));
notech_reg_set i_psram_sub_axi_araddr_reg_22(.CP(s00_axi_aclk), .D(i_psram_sub_n_3316
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[22]));
notech_nand2 i_psram_sub_i_1329(.A(i_psram_sub_n_1004), .B(i_psram_sub_n_549
), .Z(i_psram_sub_n_1553));
notech_mux2 i_psram_sub_i_3043(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[21]), .B(i_psram_sub_n_1902), .Z(i_psram_sub_n_3310));
notech_reg_set i_psram_sub_axi_araddr_reg_21(.CP(s00_axi_aclk), .D(i_psram_sub_n_3310
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[21]));
notech_nand2 i_psram_sub_i_2330(.A(i_psram_sub_n_1001), .B(i_psram_sub_n_550
), .Z(i_psram_sub_n_1558));
notech_mux2 i_psram_sub_i_3035(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[20]), .B(i_psram_sub_n_1897), .Z(i_psram_sub_n_3304));
notech_reg_set i_psram_sub_axi_araddr_reg_20(.CP(s00_axi_aclk), .D(i_psram_sub_n_3304
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[20]));
notech_nand2 i_psram_sub_i_3331(.A(i_psram_sub_n_1000), .B(i_psram_sub_n_551
), .Z(i_psram_sub_n_1563));
notech_mux2 i_psram_sub_i_3027(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[19]), .B(i_psram_sub_n_1892), .Z(i_psram_sub_n_3298));
notech_reg_set i_psram_sub_axi_araddr_reg_19(.CP(s00_axi_aclk), .D(i_psram_sub_n_3298
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[19]));
notech_nand2 i_psram_sub_i_4332(.A(i_psram_sub_n_999), .B(i_psram_sub_n_552
), .Z(i_psram_sub_n_1568));
notech_mux2 i_psram_sub_i_3019(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[18]), .B(i_psram_sub_n_1887), .Z(i_psram_sub_n_3292));
notech_reg_set i_psram_sub_axi_araddr_reg_18(.CP(s00_axi_aclk), .D(i_psram_sub_n_3292
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[18]));
notech_nand2 i_psram_sub_i_5333(.A(i_psram_sub_n_998), .B(i_psram_sub_n_553
), .Z(i_psram_sub_n_1573));
notech_mux2 i_psram_sub_i_3011(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[17]), .B(i_psram_sub_n_1882), .Z(i_psram_sub_n_3286));
notech_reg_set i_psram_sub_axi_araddr_reg_17(.CP(s00_axi_aclk), .D(i_psram_sub_n_3286
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[17]));
notech_nand2 i_psram_sub_i_6334(.A(i_psram_sub_n_997), .B(i_psram_sub_n_554
), .Z(i_psram_sub_n_1578));
notech_mux2 i_psram_sub_i_3003(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[16]), .B(i_psram_sub_n_1877), .Z(i_psram_sub_n_3280));
notech_reg_set i_psram_sub_axi_araddr_reg_16(.CP(s00_axi_aclk), .D(i_psram_sub_n_3280
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[16]));
notech_nand2 i_psram_sub_i_7335(.A(i_psram_sub_n_996), .B(i_psram_sub_n_555
), .Z(i_psram_sub_n_1583));
notech_mux2 i_psram_sub_i_2995(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[15]), .B(i_psram_sub_n_1872), .Z(i_psram_sub_n_3274));
notech_reg_set i_psram_sub_axi_araddr_reg_15(.CP(s00_axi_aclk), .D(i_psram_sub_n_3274
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[15]));
notech_nand2 i_psram_sub_i_8336(.A(i_psram_sub_n_995), .B(i_psram_sub_n_556
), .Z(i_psram_sub_n_1588));
notech_mux2 i_psram_sub_i_2986(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[14]), .B(i_psram_sub_n_1867), .Z(i_psram_sub_n_3268));
notech_reg_set i_psram_sub_axi_araddr_reg_14(.CP(s00_axi_aclk), .D(i_psram_sub_n_3268
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[14]));
notech_nand2 i_psram_sub_i_9337(.A(i_psram_sub_n_994), .B(i_psram_sub_n_557
), .Z(i_psram_sub_n_1593));
notech_mux2 i_psram_sub_i_2978(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[13]), .B(i_psram_sub_n_1862), .Z(i_psram_sub_n_3262));
notech_reg_set i_psram_sub_axi_araddr_reg_13(.CP(s00_axi_aclk), .D(i_psram_sub_n_3262
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[13]));
notech_nand2 i_psram_sub_i_10338(.A(i_psram_sub_n_993), .B(i_psram_sub_n_558
), .Z(i_psram_sub_n_1598));
notech_mux2 i_psram_sub_i_2970(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[12]), .B(i_psram_sub_n_1857), .Z(i_psram_sub_n_3256));
notech_reg_set i_psram_sub_axi_araddr_reg_12(.CP(s00_axi_aclk), .D(i_psram_sub_n_3256
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[12]));
notech_nand2 i_psram_sub_i_11339(.A(i_psram_sub_n_992), .B(i_psram_sub_n_559
), .Z(i_psram_sub_n_1603));
notech_mux2 i_psram_sub_i_2962(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[11]), .B(i_psram_sub_n_1852), .Z(i_psram_sub_n_3250));
notech_reg_set i_psram_sub_axi_araddr_reg_11(.CP(s00_axi_aclk), .D(i_psram_sub_n_3250
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[11]));
notech_nand2 i_psram_sub_i_12340(.A(i_psram_sub_n_991), .B(i_psram_sub_n_560
), .Z(i_psram_sub_n_1608));
notech_mux2 i_psram_sub_i_2954(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[10]), .B(i_psram_sub_n_1847), .Z(i_psram_sub_n_3244));
notech_reg_set i_psram_sub_axi_araddr_reg_10(.CP(s00_axi_aclk), .D(i_psram_sub_n_3244
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[10]));
notech_nand2 i_psram_sub_i_13341(.A(i_psram_sub_n_990), .B(i_psram_sub_n_561
), .Z(i_psram_sub_n_1613));
notech_mux2 i_psram_sub_i_2946(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[9]), .B(i_psram_sub_n_1842), .Z(i_psram_sub_n_3238));
notech_reg_set i_psram_sub_axi_araddr_reg_9(.CP(s00_axi_aclk), .D(i_psram_sub_n_3238
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[9]));
notech_nand2 i_psram_sub_i_14342(.A(i_psram_sub_n_989), .B(i_psram_sub_n_562
), .Z(i_psram_sub_n_1618));
notech_mux2 i_psram_sub_i_2938(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[8]), .B(i_psram_sub_n_1837), .Z(i_psram_sub_n_3232));
notech_reg_set i_psram_sub_axi_araddr_reg_8(.CP(s00_axi_aclk), .D(i_psram_sub_n_3232
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[8]));
notech_nand2 i_psram_sub_i_15343(.A(i_psram_sub_n_988), .B(i_psram_sub_n_563
), .Z(i_psram_sub_n_1623));
notech_mux2 i_psram_sub_i_2930(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[7]), .B(i_psram_sub_n_1832), .Z(i_psram_sub_n_3226));
notech_reg_set i_psram_sub_axi_araddr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3226
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[7]));
notech_nand2 i_psram_sub_i_16344(.A(i_psram_sub_n_987), .B(i_psram_sub_n_565
), .Z(i_psram_sub_n_1628));
notech_mux2 i_psram_sub_i_2922(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[6]), .B(i_psram_sub_n_1827), .Z(i_psram_sub_n_3220));
notech_reg_set i_psram_sub_axi_araddr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3220
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[6]));
notech_ao4 i_psram_sub_i_811(.A(i_psram_sub_n_451), .B(i_psram_sub_n_985
), .C(i_psram_sub_n_961), .D(i_psram_sub_n_984), .Z(i_psram_sub_n_1639
));
notech_mux2 i_psram_sub_i_2914(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[5]), .B(i_psram_sub_n_1822), .Z(i_psram_sub_n_3214));
notech_reg_set i_psram_sub_axi_araddr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3214
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[5]));
notech_nao3 i_psram_sub_i_798(.A(s00_axi_aresetn), .B(i_psram_sub_n_1205
), .C(i_psram_sub_n_975), .Z(i_psram_sub_n_2054));
notech_mux2 i_psram_sub_i_2906(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[4]), .B(i_psram_sub_n_1817), .Z(i_psram_sub_n_3208));
notech_reg_set i_psram_sub_axi_araddr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3208
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[4]));
notech_nao3 i_psram_sub_i_3896(.A(i_psram_sub_n_570), .B(i_psram_sub_n_372
), .C(i_psram_sub_n_571), .Z(i_psram_sub_state_5[2]));
notech_mux2 i_psram_sub_i_2898(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[3]), .B(i_psram_sub_n_1812), .Z(i_psram_sub_n_3202));
notech_reg_set i_psram_sub_axi_araddr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3202
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[3]));
notech_nao3 i_psram_sub_i_2895(.A(i_psram_sub_n_1235), .B(i_psram_sub_n_574
), .C(i_psram_sub_n_573), .Z(i_psram_sub_state_5[1]));
notech_mux2 i_psram_sub_i_2889(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[2]), .B(i_psram_sub_n_1807), .Z(i_psram_sub_n_3196));
notech_reg_set i_psram_sub_axi_araddr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3196
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[2]));
notech_ao4 i_psram_sub_i_1894(.A(i_psram_sub_n_1231), .B(i_psram_sub_axi_araddr
[1]), .C(i_psram_sub_n_377), .D(i_psram_sub_mem_idle), .Z(i_psram_sub_state_5
[0]));
notech_mux2 i_psram_sub_i_2881(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[1]), .B(i_psram_sub_n_1802), .Z(i_psram_sub_n_3190));
notech_reg_set i_psram_sub_axi_araddr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3190
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[1]));
notech_nao3 i_psram_sub_i_860(.A(i_psram_sub_n_954), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_382), .Z(\i_psram_sub_nbus_58[0] ));
notech_mux2 i_psram_sub_i_2873(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_araddr
[0]), .B(i_psram_sub_n_1797), .Z(i_psram_sub_n_3184));
notech_reg_set i_psram_sub_axi_araddr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3184
), .SD(1'b1), .Q(i_psram_sub_axi_araddr[0]));
notech_nand3 i_psram_sub_i_862(.A(i_psram_sub_n_954), .B(s00_axi_aresetn
), .C(i_psram_sub_n_416), .Z(\i_psram_sub_nbus_58[16] ));
notech_mux2 i_psram_sub_i_2865(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[7]), .B(i_psram_sub_n_912), .Z(i_psram_sub_n_3178));
notech_reg_set i_psram_sub_axi_arlen_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3178
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[7]));
notech_nand3 i_psram_sub_i_1021(.A(s00_axi_aresetn), .B(i_psram_sub_n_569
), .C(i_psram_sub_n_449), .Z(i_psram_sub_n_2024));
notech_mux2 i_psram_sub_i_2857(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[6]), .B(i_psram_sub_n_911), .Z(i_psram_sub_n_3172));
notech_reg_set i_psram_sub_axi_arlen_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3172
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[6]));
notech_nand3 i_psram_sub_i_1113(.A(i_psram_sub_n_954), .B(i_psram_sub_n_374
), .C(s00_axi_aresetn), .Z(i_psram_sub_n_2173));
notech_mux2 i_psram_sub_i_2849(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[5]), .B(i_psram_sub_n_910), .Z(i_psram_sub_n_3166));
notech_reg_set i_psram_sub_axi_arlen_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3166
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[5]));
notech_nao3 i_psram_sub_i_1122(.A(s00_axi_aresetn), .B(i_psram_sub_n_1225
), .C(i_psram_sub_n_982), .Z(i_psram_sub_n_2198));
notech_mux2 i_psram_sub_i_2841(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[4]), .B(i_psram_sub_n_909), .Z(i_psram_sub_n_3160));
notech_reg_set i_psram_sub_axi_arlen_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3160
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[4]));
notech_nand3 i_psram_sub_i_957(.A(s00_axi_aresetn), .B(i_psram_sub_n_1225
), .C(i_psram_sub_n_982), .Z(i_psram_sub_n_1786));
notech_mux2 i_psram_sub_i_2832(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[3]), .B(i_psram_sub_n_908), .Z(i_psram_sub_n_3154));
notech_reg_set i_psram_sub_axi_arlen_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3154
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[3]));
notech_or4 i_psram_sub_i_922(.A(i_psram_sub_state[1]), .B(i_psram_sub_n_958
), .C(i_psram_sub_mem_idle), .D(i_psram_sub_state[2]), .Z(\i_psram_sub_nbus_56[0]
));
notech_mux2 i_psram_sub_i_2824(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[2]), .B(i_psram_sub_n_907), .Z(i_psram_sub_n_3148));
notech_reg_set i_psram_sub_axi_arlen_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3148
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[2]));
notech_nao3 i_psram_sub_i_1102(.A(s00_axi_aresetn), .B(i_psram_sub_n_1223
), .C(i_psram_sub_n_1222), .Z(i_psram_sub_n_2159));
notech_mux2 i_psram_sub_i_2816(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[1]), .B(i_psram_sub_n_906), .Z(i_psram_sub_n_3142));
notech_reg_set i_psram_sub_axi_arlen_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3142
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[1]));
notech_nand3 i_psram_sub_i_1002(.A(s00_axi_aresetn), .B(i_psram_sub_n_1222
), .C(i_psram_sub_n_1223), .Z(i_psram_sub_n_1970));
notech_mux2 i_psram_sub_i_2808(.S(\i_psram_sub_nbus_67[0] ), .A(i_psram_sub_axi_arlen
[0]), .B(i_psram_sub_n_905), .Z(i_psram_sub_n_3136));
notech_reg_set i_psram_sub_axi_arlen_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3136
), .SD(1'b1), .Q(i_psram_sub_axi_arlen[0]));
notech_nao3 i_psram_sub_i_1029(.A(i_psram_sub_n_985), .B(i_psram_sub_n_596
), .C(i_psram_sub_n_958), .Z(\i_psram_sub_nbus_64[0] ));
notech_mux2 i_psram_sub_i_2800(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[7]), .B(i_psram_sub_n_918), .Z(i_psram_sub_n_3130));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3130
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[7]));
notech_nand3 i_psram_sub_i_929(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_463), .Z(\i_psram_sub_nbus_60[0] ));
notech_mux2 i_psram_sub_i_2792(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[6]), .B(i_psram_sub_n_917), .Z(i_psram_sub_n_3124));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3124
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[6]));
notech_nand2 i_psram_sub_i_1007(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .Z(\i_psram_sub_nbus_63[0] ));
notech_mux2 i_psram_sub_i_2784(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[5]), .B(i_psram_sub_n_916), .Z(i_psram_sub_n_3118));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3118
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[5]));
notech_nand3 i_psram_sub_i_962(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_511), .Z(\i_psram_sub_nbus_61[0] ));
notech_mux2 i_psram_sub_i_2776(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[4]), .B(i_psram_sub_n_915), .Z(i_psram_sub_n_3112));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3112
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[4]));
notech_nand2 i_psram_sub_i_1085(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .Z(\i_psram_sub_nbus_67[0] ));
notech_mux2 i_psram_sub_i_2768(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[3]), .B(i_psram_sub_n_914), .Z(i_psram_sub_n_3106));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3106
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[3]));
notech_mux2 i_psram_sub_i_2759(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[2]), .B(i_psram_sub_n_4005), .Z(i_psram_sub_n_3100));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3100
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[2]));
notech_and2 i_psram_sub_i_1095(.A(s00_axi_aresetn), .B(i_psram_sub_n_569
), .Z(\i_psram_sub_nbus_68[0] ));
notech_mux2 i_psram_sub_i_2751(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[1]), .B(i_psram_sub_n_4003), .Z(i_psram_sub_n_3094));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_3094
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[1]));
notech_and4 i_psram_sub_i_765(.A(i_psram_sub_n_976), .B(i_psram_sub_n_972
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_952), .Z(i_psram_sub_go_7
));
notech_mux2 i_psram_sub_i_2743(.S(\i_psram_sub_nbus_61[0] ), .A(i_psram_sub_axi_arlen_cntr
[0]), .B(i_psram_sub_n_4030), .Z(i_psram_sub_n_3088));
notech_reg_set i_psram_sub_axi_arlen_cntr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_3088
), .SD(1'b1), .Q(i_psram_sub_axi_arlen_cntr[0]));
notech_mux2 i_psram_sub_i_2735(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[15]), .B(i_psram_sub_n_1628), .Z(i_psram_sub_n_3082));
notech_reg_set i_psram_sub_mem_data_wr_reg_15(.CP(s00_axi_aclk), .D(i_psram_sub_n_3082
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[15]));
notech_ao4 i_psram_sub_i_651(.A(i_psram_sub_mem_idle), .B(i_psram_sub_n_970
), .C(i_psram_sub_n_1231), .D(i_psram_sub_axi_araddr[1]), .Z(i_psram_sub_n_1235
));
notech_mux2 i_psram_sub_i_2727(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[14]), .B(i_psram_sub_n_1623), .Z(i_psram_sub_n_3076));
notech_reg_set i_psram_sub_mem_data_wr_reg_14(.CP(s00_axi_aclk), .D(i_psram_sub_n_3076
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[14]));
notech_mux2 i_psram_sub_i_2719(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[13]), .B(i_psram_sub_n_1618), .Z(i_psram_sub_n_3070));
notech_reg_set i_psram_sub_mem_data_wr_reg_13(.CP(s00_axi_aclk), .D(i_psram_sub_n_3070
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[13]));
notech_mux2 i_psram_sub_i_2711(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[12]), .B(i_psram_sub_n_1613), .Z(i_psram_sub_n_3064));
notech_reg_set i_psram_sub_mem_data_wr_reg_12(.CP(s00_axi_aclk), .D(i_psram_sub_n_3064
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[12]));
notech_mux2 i_psram_sub_i_2703(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[11]), .B(i_psram_sub_n_1608), .Z(i_psram_sub_n_3058));
notech_reg_set i_psram_sub_mem_data_wr_reg_11(.CP(s00_axi_aclk), .D(i_psram_sub_n_3058
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[11]));
notech_or4 i_psram_sub_i_86(.A(i_psram_sub_n_954), .B(i_psram_sub_n_4319
), .C(i_psram_sub_n_4024), .D(i_psram_sub_mem_idle), .Z(i_psram_sub_n_1231
));
notech_mux2 i_psram_sub_i_2694(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[10]), .B(i_psram_sub_n_1603), .Z(i_psram_sub_n_3052));
notech_reg_set i_psram_sub_mem_data_wr_reg_10(.CP(s00_axi_aclk), .D(i_psram_sub_n_3052
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[10]));
notech_mux2 i_psram_sub_i_2686(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[9]), .B(i_psram_sub_n_1598), .Z(i_psram_sub_n_3046));
notech_reg_set i_psram_sub_mem_data_wr_reg_9(.CP(s00_axi_aclk), .D(i_psram_sub_n_3046
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[9]));
notech_mux2 i_psram_sub_i_2678(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[8]), .B(i_psram_sub_n_1593), .Z(i_psram_sub_n_3040));
notech_reg_set i_psram_sub_mem_data_wr_reg_8(.CP(s00_axi_aclk), .D(i_psram_sub_n_3040
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[8]));
notech_ao4 i_psram_sub_i_658(.A(i_psram_sub_n_974), .B(i_psram_sub_n_4319
), .C(i_psram_sub_n_979), .D(i_psram_sub_n_1227), .Z(i_psram_sub_n_1228
));
notech_mux2 i_psram_sub_i_2670(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[7]), .B(i_psram_sub_n_1588), .Z(i_psram_sub_n_3034));
notech_reg_set i_psram_sub_mem_data_wr_reg_7(.CP(s00_axi_aclk), .D(i_psram_sub_n_3034
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[7]));
notech_or4 i_psram_sub_i_85(.A(i_psram_sub_state[1]), .B(i_psram_sub_state
[0]), .C(i_psram_sub_n_4027), .D(i_psram_sub_n_4319), .Z(i_psram_sub_n_1227
));
notech_mux2 i_psram_sub_i_2662(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[6]), .B(i_psram_sub_n_1583), .Z(i_psram_sub_n_3028));
notech_reg_set i_psram_sub_mem_data_wr_reg_6(.CP(s00_axi_aclk), .D(i_psram_sub_n_3028
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[6]));
notech_mux2 i_psram_sub_i_2654(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[5]), .B(i_psram_sub_n_1578), .Z(i_psram_sub_n_3022));
notech_reg_set i_psram_sub_mem_data_wr_reg_5(.CP(s00_axi_aclk), .D(i_psram_sub_n_3022
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[5]));
notech_nand2 i_psram_sub_i_47(.A(i_psram_sub_n_4024), .B(i_psram_sub_n_3991
), .Z(i_psram_sub_n_1225));
notech_mux2 i_psram_sub_i_2646(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[4]), .B(i_psram_sub_n_1573), .Z(i_psram_sub_n_3016));
notech_reg_set i_psram_sub_mem_data_wr_reg_4(.CP(s00_axi_aclk), .D(i_psram_sub_n_3016
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[4]));
notech_mux2 i_psram_sub_i_2638(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[3]), .B(i_psram_sub_n_1568), .Z(i_psram_sub_n_3010));
notech_reg_set i_psram_sub_mem_data_wr_reg_3(.CP(s00_axi_aclk), .D(i_psram_sub_n_3010
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[3]));
notech_or2 i_psram_sub_i_44(.A(i_psram_sub_n_1006), .B(i_psram_sub_axi_awv_awr_flag
), .Z(i_psram_sub_n_1223));
notech_mux2 i_psram_sub_i_2630(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[2]), .B(i_psram_sub_n_1563), .Z(i_psram_sub_n_3004));
notech_reg_set i_psram_sub_mem_data_wr_reg_2(.CP(s00_axi_aclk), .D(i_psram_sub_n_3004
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[2]));
notech_and4 i_psram_sub_i_77(.A(i_psram_sub_n_1213), .B(s00_axi_rvalid),
.C(s00_axi_rready), .D(i_psram_sub_n_3992), .Z(i_psram_sub_n_1222
));
notech_mux2 i_psram_sub_i_2622(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[1]), .B(i_psram_sub_n_1558), .Z(i_psram_sub_n_2998));
notech_reg_set i_psram_sub_mem_data_wr_reg_1(.CP(s00_axi_aclk), .D(i_psram_sub_n_2998
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[1]));
notech_mux2 i_psram_sub_i_2614(.S(\i_psram_sub_nbus_56[0] ), .A(i_psram_sub_mem_data_wr
[0]), .B(i_psram_sub_n_1553), .Z(i_psram_sub_n_2992));
notech_reg_set i_psram_sub_mem_data_wr_reg_0(.CP(s00_axi_aclk), .D(i_psram_sub_n_2992
), .SD(1'b1), .Q(i_psram_sub_mem_data_wr[0]));
notech_reg_set i_psram_sub_go_reg(.CP(s00_axi_aclk), .D(i_psram_sub_n_4002
), .SD(1'b1), .Q(i_psram_sub_go));
notech_or4 i_psram_sub_i_673(.A(i_psram_sub_n_587), .B(i_psram_sub_n_586
), .C(i_psram_sub_n_1219), .D(i_psram_sub_n_1214), .Z(i_psram_sub_n_1220
));
notech_or4 i_psram_sub_i_669(.A(i_psram_sub_n_583), .B(i_psram_sub_n_582
), .C(i_psram_sub_n_585), .D(i_psram_sub_n_584), .Z(i_psram_sub_n_1219
));
notech_nand2 i_psram_sub_i_671(.A(i_psram_sub_n_589), .B(i_psram_sub_n_588
), .Z(i_psram_sub_n_1214));
notech_and4 i_psram_sub_i_680(.A(i_psram_sub_n_1211), .B(i_psram_sub_n_1210
), .C(i_psram_sub_n_1208), .D(i_psram_sub_n_1207), .Z(i_psram_sub_n_1213
));
notech_ao4 i_psram_sub_i_674(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_n_4008
), .C(i_psram_sub_axi_arlen[1]), .D(i_psram_sub_n_4004), .Z(i_psram_sub_n_1211
));
notech_ao4 i_psram_sub_i_675(.A(i_psram_sub_axi_arlen[2]), .B(i_psram_sub_n_4006
), .C(i_psram_sub_axi_arlen[3]), .D(i_psram_sub_n_4007), .Z(i_psram_sub_n_1210
));
notech_ao4 i_psram_sub_i_677(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_n_4009
), .C(i_psram_sub_axi_arlen_cntr[5]), .D(i_psram_sub_n_4010), .Z
(i_psram_sub_n_1208));
notech_ao4 i_psram_sub_i_678(.A(i_psram_sub_axi_arlen_cntr[6]), .B(i_psram_sub_n_4011
), .C(i_psram_sub_axi_arlen_cntr[7]), .D(i_psram_sub_n_4013), .Z
(i_psram_sub_n_1207));
notech_ao4 i_psram_sub_i_682(.A(i_psram_sub_n_3995), .B(i_psram_sub_n_954
), .C(i_psram_sub_n_962), .D(i_psram_sub_n_1204), .Z(i_psram_sub_n_1205
));
notech_nand2 i_psram_sub_i_683(.A(i_psram_sub_command), .B(i_psram_sub_n_954
), .Z(i_psram_sub_n_1204));
notech_ao4 i_psram_sub_i_685(.A(s00_axi_wstrb[0]), .B(i_psram_sub_n_971)
, .C(i_psram_sub_n_962), .D(i_psram_sub_n_1201), .Z(i_psram_sub_n_1202
));
notech_nand3 i_psram_sub_i_686(.A(s00_axi_aresetn), .B(i_psram_sub_n_954
), .C(i_psram_sub_mem_byte_en[0]), .Z(i_psram_sub_n_1201));
notech_ao4 i_psram_sub_i_57(.A(i_psram_sub_n_3994), .B(i_psram_sub_n_980
), .C(i_psram_sub_n_3995), .D(i_psram_sub_n_1197), .Z(i_psram_sub_n_1198
));
notech_nao3 i_psram_sub_i_690(.A(i_psram_sub_n_568), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_954), .Z(i_psram_sub_n_1197));
notech_ao4 i_psram_sub_i_689(.A(s00_axi_wstrb[1]), .B(i_psram_sub_n_971)
, .C(i_psram_sub_n_962), .D(i_psram_sub_n_1195), .Z(i_psram_sub_n_1196
));
notech_nand3 i_psram_sub_i_691(.A(s00_axi_aresetn), .B(i_psram_sub_n_954
), .C(i_psram_sub_mem_byte_en[1]), .Z(i_psram_sub_n_1195));
notech_ao4 i_psram_sub_i_692(.A(i_psram_sub_n_969), .B(i_psram_sub_n_965
), .C(i_psram_sub_n_456), .D(i_psram_sub_n_4199), .Z(i_psram_sub_n_1194
));
notech_ao4 i_psram_sub_i_693(.A(i_psram_sub_n_455), .B(i_psram_sub_n_4176
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4105), .Z(i_psram_sub_n_1193
));
notech_ao4 i_psram_sub_i_694(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4200
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4177), .Z(i_psram_sub_n_1192
));
notech_ao4 i_psram_sub_i_695(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4154
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4106), .Z(i_psram_sub_n_1191
));
notech_ao4 i_psram_sub_i_696(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4201
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4178), .Z(i_psram_sub_n_1190
));
notech_ao4 i_psram_sub_i_697(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4155
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4107), .Z(i_psram_sub_n_1189
));
notech_ao4 i_psram_sub_i_698(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4202
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4179), .Z(i_psram_sub_n_1188
));
notech_ao4 i_psram_sub_i_699(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4156
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4108), .Z(i_psram_sub_n_1187
));
notech_ao4 i_psram_sub_i_700(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4203
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4180), .Z(i_psram_sub_n_1186
));
notech_ao4 i_psram_sub_i_701(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4157
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4109), .Z(i_psram_sub_n_1185
));
notech_ao4 i_psram_sub_i_702(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4204
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4181), .Z(i_psram_sub_n_1184
));
notech_ao4 i_psram_sub_i_703(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4158
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4110), .Z(i_psram_sub_n_1183
));
notech_ao4 i_psram_sub_i_704(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4205
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4182), .Z(i_psram_sub_n_1182
));
notech_ao4 i_psram_sub_i_705(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4159
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4111), .Z(i_psram_sub_n_1181
));
notech_ao4 i_psram_sub_i_706(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4206
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4183), .Z(i_psram_sub_n_1180
));
notech_ao4 i_psram_sub_i_707(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4160
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4112), .Z(i_psram_sub_n_1179
));
notech_ao4 i_psram_sub_i_708(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4207
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4184), .Z(i_psram_sub_n_1178
));
notech_ao4 i_psram_sub_i_709(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4161
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4113), .Z(i_psram_sub_n_1177
));
notech_ao4 i_psram_sub_i_710(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4208
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4185), .Z(i_psram_sub_n_1176
));
notech_ao4 i_psram_sub_i_711(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4162
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4114), .Z(i_psram_sub_n_1175
));
notech_ao4 i_psram_sub_i_712(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4209
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4186), .Z(i_psram_sub_n_1174
));
notech_ao4 i_psram_sub_i_713(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4163
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4115), .Z(i_psram_sub_n_1173
));
notech_ao4 i_psram_sub_i_714(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4210
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4187), .Z(i_psram_sub_n_1172
));
notech_ao4 i_psram_sub_i_715(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4164
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4116), .Z(i_psram_sub_n_1171
));
notech_ao4 i_psram_sub_i_716(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4211
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4188), .Z(i_psram_sub_n_1170
));
notech_ao4 i_psram_sub_i_717(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4165
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4117), .Z(i_psram_sub_n_1169
));
notech_ao4 i_psram_sub_i_718(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4212
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4189), .Z(i_psram_sub_n_1168
));
notech_ao4 i_psram_sub_i_719(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4166
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4118), .Z(i_psram_sub_n_1167
));
notech_ao4 i_psram_sub_i_720(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4213
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4190), .Z(i_psram_sub_n_1166
));
notech_ao4 i_psram_sub_i_721(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4167
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4119), .Z(i_psram_sub_n_1165
));
notech_ao4 i_psram_sub_i_722(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4214
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4191), .Z(i_psram_sub_n_1164
));
notech_ao4 i_psram_sub_i_723(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4168
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4120), .Z(i_psram_sub_n_1163
));
notech_ao4 i_psram_sub_i_724(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4215
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4192), .Z(i_psram_sub_n_1162
));
notech_ao4 i_psram_sub_i_725(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4169
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4121), .Z(i_psram_sub_n_1161
));
notech_ao4 i_psram_sub_i_726(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4216
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4193), .Z(i_psram_sub_n_1160
));
notech_ao4 i_psram_sub_i_727(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4170
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4122), .Z(i_psram_sub_n_1159
));
notech_ao4 i_psram_sub_i_728(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4217
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4194), .Z(i_psram_sub_n_1158
));
notech_ao4 i_psram_sub_i_729(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4171
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4123), .Z(i_psram_sub_n_1157
));
notech_ao4 i_psram_sub_i_730(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4218
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4195), .Z(i_psram_sub_n_1156
));
notech_ao4 i_psram_sub_i_731(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4172
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4124), .Z(i_psram_sub_n_1155
));
notech_ao4 i_psram_sub_i_732(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4219
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4196), .Z(i_psram_sub_n_1154
));
notech_ao4 i_psram_sub_i_733(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4173
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4125), .Z(i_psram_sub_n_1153
));
notech_ao4 i_psram_sub_i_734(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4220
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4197), .Z(i_psram_sub_n_1152
));
notech_ao4 i_psram_sub_i_735(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4174
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4126), .Z(i_psram_sub_n_1151
));
notech_ao4 i_psram_sub_i_736(.A(i_psram_sub_n_456), .B(i_psram_sub_n_4221
), .C(i_psram_sub_n_455), .D(i_psram_sub_n_4198), .Z(i_psram_sub_n_1150
));
notech_and2 i_psram_sub_i_48(.A(i_psram_sub_n_974), .B(i_psram_sub_n_960
), .Z(i_psram_sub_n_1149));
notech_ao4 i_psram_sub_i_737(.A(i_psram_sub_n_972), .B(i_psram_sub_n_4175
), .C(i_psram_sub_n_957), .D(i_psram_sub_n_4127), .Z(i_psram_sub_n_1148
));
notech_ao4 i_psram_sub_i_738(.A(i_psram_sub_n_1101), .B(i_psram_sub_n_4128
), .C(i_psram_sub_n_1097), .D(i_psram_sub_n_4152), .Z(i_psram_sub_n_1147
));
notech_ao4 i_psram_sub_i_739(.A(i_psram_sub_n_4129), .B(i_psram_sub_n_1101
), .C(i_psram_sub_n_1097), .D(i_psram_sub_n_4153), .Z(i_psram_sub_n_1146
));
notech_ao4 i_psram_sub_i_740(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4260
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4130), .Z(i_psram_sub_n_1145
));
notech_ao4 i_psram_sub_i_741(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4154
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4381), .Z(i_psram_sub_n_1144
));
notech_ao4 i_psram_sub_i_742(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4261
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4131), .Z(i_psram_sub_n_1143
));
notech_ao4 i_psram_sub_i_743(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4155
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4380), .Z(i_psram_sub_n_1142
));
notech_ao4 i_psram_sub_i_744(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4262
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4132), .Z(i_psram_sub_n_1141
));
notech_ao4 i_psram_sub_i_745(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4156
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4379), .Z(i_psram_sub_n_1140
));
notech_ao4 i_psram_sub_i_746(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4263
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4133), .Z(i_psram_sub_n_1139
));
notech_ao4 i_psram_sub_i_747(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4157
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4378), .Z(i_psram_sub_n_1138
));
notech_ao4 i_psram_sub_i_749(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4264
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4134), .Z(i_psram_sub_n_1137
));
notech_ao4 i_psram_sub_i_750(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4158
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4377), .Z(i_psram_sub_n_1136
));
notech_ao4 i_psram_sub_i_751(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4265
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4135), .Z(i_psram_sub_n_1135
));
notech_ao4 i_psram_sub_i_752(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4159
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4376), .Z(i_psram_sub_n_1134
));
notech_ao4 i_psram_sub_i_753(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4266
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4136), .Z(i_psram_sub_n_1133
));
notech_ao4 i_psram_sub_i_754(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4160
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4375), .Z(i_psram_sub_n_1132
));
notech_ao4 i_psram_sub_i_755(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4267
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4137), .Z(i_psram_sub_n_1131
));
notech_ao4 i_psram_sub_i_756(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4161
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4374), .Z(i_psram_sub_n_1130
));
notech_ao4 i_psram_sub_i_757(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4268
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4138), .Z(i_psram_sub_n_1129
));
notech_ao4 i_psram_sub_i_758(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4162
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4373), .Z(i_psram_sub_n_1128
));
notech_ao4 i_psram_sub_i_759(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4269
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4139), .Z(i_psram_sub_n_1127
));
notech_ao4 i_psram_sub_i_760(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4163
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4372), .Z(i_psram_sub_n_1126
));
notech_ao4 i_psram_sub_i_761(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4270
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4140), .Z(i_psram_sub_n_1125
));
notech_ao4 i_psram_sub_i_762(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4164
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4371), .Z(i_psram_sub_n_1124
));
notech_ao4 i_psram_sub_i_763(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4271
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4141), .Z(i_psram_sub_n_1123
));
notech_ao4 i_psram_sub_i_764(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4165
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4370), .Z(i_psram_sub_n_1122
));
notech_ao4 i_psram_sub_i_766(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4272
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4142), .Z(i_psram_sub_n_1121
));
notech_ao4 i_psram_sub_i_767(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4166
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4369), .Z(i_psram_sub_n_1120
));
notech_ao4 i_psram_sub_i_768(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4273
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4143), .Z(i_psram_sub_n_1119
));
notech_ao4 i_psram_sub_i_769(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4167
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4368), .Z(i_psram_sub_n_1118
));
notech_ao4 i_psram_sub_i_770(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4274
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4144), .Z(i_psram_sub_n_1117
));
notech_ao4 i_psram_sub_i_771(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4168
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4367), .Z(i_psram_sub_n_1116
));
notech_ao4 i_psram_sub_i_772(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4275
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4145), .Z(i_psram_sub_n_1115
));
notech_ao4 i_psram_sub_i_773(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4169
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4366), .Z(i_psram_sub_n_1114
));
notech_ao4 i_psram_sub_i_774(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4276
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4146), .Z(i_psram_sub_n_1113
));
notech_ao4 i_psram_sub_i_775(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4170
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4365), .Z(i_psram_sub_n_1112
));
notech_ao4 i_psram_sub_i_776(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4277
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4147), .Z(i_psram_sub_n_1111
));
notech_ao4 i_psram_sub_i_777(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4171
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4364), .Z(i_psram_sub_n_1110
));
notech_ao4 i_psram_sub_i_778(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4278
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4148), .Z(i_psram_sub_n_1109
));
notech_ao4 i_psram_sub_i_779(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4172
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4363), .Z(i_psram_sub_n_1108
));
notech_ao4 i_psram_sub_i_780(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4279
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4149), .Z(i_psram_sub_n_1107
));
notech_ao4 i_psram_sub_i_781(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4173
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4362), .Z(i_psram_sub_n_1106
));
notech_ao4 i_psram_sub_i_782(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4280
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4150), .Z(i_psram_sub_n_1105
));
notech_ao4 i_psram_sub_i_783(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4174
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4361), .Z(i_psram_sub_n_1104
));
notech_ao4 i_psram_sub_i_784(.A(i_psram_sub_n_1102), .B(i_psram_sub_n_4281
), .C(i_psram_sub_n_1101), .D(i_psram_sub_n_4151), .Z(i_psram_sub_n_1103
));
notech_nand2 i_psram_sub_i_5(.A(s00_axi_aresetn), .B(i_psram_sub_n_3991)
, .Z(i_psram_sub_n_1102));
notech_or4 i_psram_sub_i_8(.A(\i_psram_sub_nbus_63[0] ), .B(s00_axi_awburst
[0]), .C(i_psram_sub_n_3998), .D(i_psram_sub_n_4317), .Z(i_psram_sub_n_1101
));
notech_ao4 i_psram_sub_i_785(.A(i_psram_sub_n_1097), .B(i_psram_sub_n_4175
), .C(i_psram_sub_n_1095), .D(i_psram_sub_n_4360), .Z(i_psram_sub_n_1098
));
notech_nao3 i_psram_sub_i_9(.A(i_psram_sub_n_4317), .B(i_psram_sub_n_4316
), .C(\i_psram_sub_nbus_63[0] ), .Z(i_psram_sub_n_1097));
notech_nand3 i_psram_sub_i_13(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_370), .Z(i_psram_sub_n_1095));
notech_and4 i_psram_sub_i_491563(.A(i_psram_sub_n_1092), .B(i_psram_sub_n_1091
), .C(i_psram_sub_n_1089), .D(i_psram_sub_n_1088), .Z(i_psram_sub_n_1094
));
notech_ao4 i_psram_sub_i_789(.A(i_psram_sub_axi_awaddr[2]), .B(i_psram_sub_n_4359
), .C(i_psram_sub_axi_awaddr[3]), .D(i_psram_sub_n_4358), .Z(i_psram_sub_n_1092
));
notech_ao4 i_psram_sub_i_790(.A(i_psram_sub_axi_awaddr[4]), .B(i_psram_sub_n_4357
), .C(i_psram_sub_axi_awaddr[5]), .D(i_psram_sub_n_4356), .Z(i_psram_sub_n_1091
));
notech_ao4 i_psram_sub_i_792(.A(i_psram_sub_axi_awaddr[6]), .B(i_psram_sub_n_4355
), .C(i_psram_sub_axi_awaddr[7]), .D(i_psram_sub_n_4354), .Z(i_psram_sub_n_1089
));
notech_ao4 i_psram_sub_i_793(.A(i_psram_sub_axi_awaddr[8]), .B(i_psram_sub_n_4353
), .C(i_psram_sub_axi_awaddr[9]), .D(i_psram_sub_n_4352), .Z(i_psram_sub_n_1088
));
notech_ao4 i_psram_sub_i_22(.A(i_psram_sub_axi_awlen[3]), .B(i_psram_sub_n_4018
), .C(i_psram_sub_n_482), .D(i_psram_sub_n_481), .Z(i_psram_sub_n_1086
));
notech_nand2 i_psram_sub_i_806(.A(i_psram_sub_axi_awlen_cntr[0]), .B(i_psram_sub_n_4019
), .Z(i_psram_sub_n_1085));
notech_nand2 i_psram_sub_i_807(.A(i_psram_sub_axi_awlen_cntr[0]), .B(i_psram_sub_n_4015
), .Z(i_psram_sub_n_1084));
notech_and3 i_psram_sub_i_70(.A(i_psram_sub_axi_awlen_cntr[5]), .B(i_psram_sub_n_1081
), .C(i_psram_sub_axi_awlen_cntr[6]), .Z(i_psram_sub_n_1083));
notech_and3 i_psram_sub_i_53(.A(i_psram_sub_axi_awlen_cntr[4]), .B(i_psram_sub_n_1080
), .C(i_psram_sub_axi_awlen_cntr[5]), .Z(i_psram_sub_n_1082));
notech_ao3 i_psram_sub_i_46(.A(i_psram_sub_axi_awlen_cntr[4]), .B(i_psram_sub_axi_awlen_cntr
[3]), .C(i_psram_sub_n_1079), .Z(i_psram_sub_n_1081));
notech_and4 i_psram_sub_i_40(.A(i_psram_sub_axi_awlen_cntr[0]), .B(i_psram_sub_axi_awlen_cntr
[1]), .C(i_psram_sub_axi_awlen_cntr[2]), .D(i_psram_sub_axi_awlen_cntr
[3]), .Z(i_psram_sub_n_1080));
notech_nand3 i_psram_sub_i_101507(.A(i_psram_sub_axi_awlen_cntr[0]), .B(i_psram_sub_axi_awlen_cntr
[1]), .C(i_psram_sub_axi_awlen_cntr[2]), .Z(i_psram_sub_n_1079)
);
notech_nand2 i_psram_sub_i_818(.A(i_psram_sub_axi_awlen_cntr[0]), .B(i_psram_sub_axi_awlen_cntr
[1]), .Z(i_psram_sub_n_1078));
notech_nao3 i_psram_sub_i_472(.A(s00_axi_awvalid), .B(i_psram_sub_n_4399
), .C(i_psram_sub_axi_awv_awr_flag), .Z(i_psram_sub_n_1077));
notech_ao4 i_psram_sub_i_826(.A(i_psram_sub_n_4080), .B(i_psram_sub_n_1029
), .C(i_psram_sub_n_1025), .D(i_psram_sub_n_4104), .Z(i_psram_sub_n_1075
));
notech_ao4 i_psram_sub_i_827(.A(i_psram_sub_n_1029), .B(i_psram_sub_n_4081
), .C(i_psram_sub_n_1025), .D(i_psram_sub_n_4105), .Z(i_psram_sub_n_1074
));
notech_ao4 i_psram_sub_i_828(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4238
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4082), .Z(i_psram_sub_n_1073
));
notech_ao4 i_psram_sub_i_829(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4106
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4351), .Z(i_psram_sub_n_1072
));
notech_ao4 i_psram_sub_i_830(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4239
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4083), .Z(i_psram_sub_n_1071
));
notech_ao4 i_psram_sub_i_831(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4107
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4350), .Z(i_psram_sub_n_1070
));
notech_ao4 i_psram_sub_i_832(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4240
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4084), .Z(i_psram_sub_n_1069
));
notech_ao4 i_psram_sub_i_833(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4108
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4349), .Z(i_psram_sub_n_1068
));
notech_ao4 i_psram_sub_i_834(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4241
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4085), .Z(i_psram_sub_n_1067
));
notech_ao4 i_psram_sub_i_835(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4109
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4348), .Z(i_psram_sub_n_1066
));
notech_ao4 i_psram_sub_i_836(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4242
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4086), .Z(i_psram_sub_n_1065
));
notech_ao4 i_psram_sub_i_837(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4110
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4347), .Z(i_psram_sub_n_1064
));
notech_ao4 i_psram_sub_i_838(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4243
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4087), .Z(i_psram_sub_n_1063
));
notech_ao4 i_psram_sub_i_839(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4111
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4346), .Z(i_psram_sub_n_1062
));
notech_ao4 i_psram_sub_i_840(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4244
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4088), .Z(i_psram_sub_n_1061
));
notech_ao4 i_psram_sub_i_841(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4112
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4345), .Z(i_psram_sub_n_1060
));
notech_ao4 i_psram_sub_i_842(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4245
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4089), .Z(i_psram_sub_n_1059
));
notech_ao4 i_psram_sub_i_843(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4113
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4344), .Z(i_psram_sub_n_1058
));
notech_ao4 i_psram_sub_i_844(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4246
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4090), .Z(i_psram_sub_n_1057
));
notech_ao4 i_psram_sub_i_845(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4114
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4343), .Z(i_psram_sub_n_1056
));
notech_ao4 i_psram_sub_i_846(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4247
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4091), .Z(i_psram_sub_n_1055
));
notech_ao4 i_psram_sub_i_847(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4115
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4342), .Z(i_psram_sub_n_1054
));
notech_ao4 i_psram_sub_i_848(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4248
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4092), .Z(i_psram_sub_n_1053
));
notech_ao4 i_psram_sub_i_849(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4116
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4341), .Z(i_psram_sub_n_1052
));
notech_ao4 i_psram_sub_i_863(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4249
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4093), .Z(i_psram_sub_n_1051
));
notech_ao4 i_psram_sub_i_864(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4117
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4340), .Z(i_psram_sub_n_1050
));
notech_ao4 i_psram_sub_i_865(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4250
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4094), .Z(i_psram_sub_n_1049
));
notech_ao4 i_psram_sub_i_866(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4118
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4339), .Z(i_psram_sub_n_1048
));
notech_ao4 i_psram_sub_i_867(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4251
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4095), .Z(i_psram_sub_n_1047
));
notech_ao4 i_psram_sub_i_868(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4119
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4338), .Z(i_psram_sub_n_1046
));
notech_ao4 i_psram_sub_i_869(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4252
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4096), .Z(i_psram_sub_n_1045
));
notech_ao4 i_psram_sub_i_870(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4120
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4337), .Z(i_psram_sub_n_1044
));
notech_ao4 i_psram_sub_i_871(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4253
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4097), .Z(i_psram_sub_n_1043
));
notech_ao4 i_psram_sub_i_872(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4121
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4336), .Z(i_psram_sub_n_1042
));
notech_ao4 i_psram_sub_i_873(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4254
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4098), .Z(i_psram_sub_n_1041
));
notech_ao4 i_psram_sub_i_874(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4122
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4335), .Z(i_psram_sub_n_1040
));
notech_ao4 i_psram_sub_i_875(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4255
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4099), .Z(i_psram_sub_n_1039
));
notech_ao4 i_psram_sub_i_876(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4123
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4334), .Z(i_psram_sub_n_1038
));
notech_ao4 i_psram_sub_i_877(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4256
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4100), .Z(i_psram_sub_n_1037
));
notech_ao4 i_psram_sub_i_878(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4124
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4333), .Z(i_psram_sub_n_1036
));
notech_ao4 i_psram_sub_i_879(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4257
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4101), .Z(i_psram_sub_n_1035
));
notech_ao4 i_psram_sub_i_880(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4125
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4332), .Z(i_psram_sub_n_1034
));
notech_ao4 i_psram_sub_i_881(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4258
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4102), .Z(i_psram_sub_n_1033
));
notech_ao4 i_psram_sub_i_882(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4126
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4331), .Z(i_psram_sub_n_1032
));
notech_ao4 i_psram_sub_i_883(.A(i_psram_sub_n_1030), .B(i_psram_sub_n_4259
), .C(i_psram_sub_n_1029), .D(i_psram_sub_n_4103), .Z(i_psram_sub_n_1031
));
notech_nand2 i_psram_sub_i_6(.A(s00_axi_aresetn), .B(i_psram_sub_n_3990)
, .Z(i_psram_sub_n_1030));
notech_or4 i_psram_sub_i_7(.A(\i_psram_sub_nbus_67[0] ), .B(s00_axi_arburst
[0]), .C(i_psram_sub_n_3999), .D(i_psram_sub_n_4318), .Z(i_psram_sub_n_1029
));
notech_ao4 i_psram_sub_i_884(.A(i_psram_sub_n_1025), .B(i_psram_sub_n_4127
), .C(i_psram_sub_n_1023), .D(i_psram_sub_n_4330), .Z(i_psram_sub_n_1026
));
notech_or4 i_psram_sub_i_10(.A(s00_axi_arburst[0]), .B(i_psram_sub_n_4319
), .C(s00_axi_arburst[1]), .D(i_psram_sub_n_3990), .Z(i_psram_sub_n_1025
));
notech_nand3 i_psram_sub_i_15(.A(i_psram_sub_n_1006), .B(s00_axi_aresetn
), .C(i_psram_sub_n_371), .Z(i_psram_sub_n_1023));
notech_and4 i_psram_sub_i_49(.A(i_psram_sub_n_1020), .B(i_psram_sub_n_1019
), .C(i_psram_sub_n_1017), .D(i_psram_sub_n_1016), .Z(i_psram_sub_n_1022
));
notech_ao4 i_psram_sub_i_888(.A(i_psram_sub_axi_araddr[2]), .B(i_psram_sub_n_4329
), .C(i_psram_sub_axi_araddr[3]), .D(i_psram_sub_n_4328), .Z(i_psram_sub_n_1020
));
notech_ao4 i_psram_sub_i_889(.A(i_psram_sub_axi_araddr[4]), .B(i_psram_sub_n_4327
), .C(i_psram_sub_axi_araddr[5]), .D(i_psram_sub_n_4326), .Z(i_psram_sub_n_1019
));
notech_ao4 i_psram_sub_i_891(.A(i_psram_sub_axi_araddr[6]), .B(i_psram_sub_n_4325
), .C(i_psram_sub_axi_araddr[7]), .D(i_psram_sub_n_4324), .Z(i_psram_sub_n_1017
));
notech_ao4 i_psram_sub_i_892(.A(i_psram_sub_axi_araddr[8]), .B(i_psram_sub_n_4323
), .C(i_psram_sub_axi_araddr[9]), .D(i_psram_sub_n_4322), .Z(i_psram_sub_n_1016
));
notech_ao4 i_psram_sub_i_21(.A(i_psram_sub_axi_arlen[3]), .B(i_psram_sub_n_4007
), .C(i_psram_sub_n_525), .D(i_psram_sub_n_584), .Z(i_psram_sub_n_1015
));
notech_nand2 i_psram_sub_i_909(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_n_4004
), .Z(i_psram_sub_n_1013));
notech_and3 i_psram_sub_i_69(.A(i_psram_sub_axi_arlen_cntr[5]), .B(i_psram_sub_n_1010
), .C(i_psram_sub_axi_arlen_cntr[6]), .Z(i_psram_sub_n_1012));
notech_and3 i_psram_sub_i_52(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_n_1009
), .C(i_psram_sub_axi_arlen_cntr[5]), .Z(i_psram_sub_n_1011));
notech_ao3 i_psram_sub_i_45(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_axi_arlen_cntr
[3]), .C(i_psram_sub_n_1008), .Z(i_psram_sub_n_1010));
notech_and4 i_psram_sub_i_36(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_axi_arlen_cntr
[1]), .C(i_psram_sub_axi_arlen_cntr[2]), .D(i_psram_sub_axi_arlen_cntr
[3]), .Z(i_psram_sub_n_1009));
notech_nand3 i_psram_sub_i_101456(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_axi_arlen_cntr
[1]), .C(i_psram_sub_axi_arlen_cntr[2]), .Z(i_psram_sub_n_1008)
);
notech_nand2 i_psram_sub_i_923(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_axi_arlen_cntr
[1]), .Z(i_psram_sub_n_1007));
notech_nao3 i_psram_sub_i_490(.A(s00_axi_arvalid), .B(i_psram_sub_n_4024
), .C(s00_axi_arready), .Z(i_psram_sub_n_1006));
notech_ao4 i_psram_sub_i_925(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4064
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4222), .Z(i_psram_sub_n_1004
));
notech_ao4 i_psram_sub_i_932(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4065
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4223), .Z(i_psram_sub_n_1001
));
notech_ao4 i_psram_sub_i_933(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4066
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4224), .Z(i_psram_sub_n_1000
));
notech_ao4 i_psram_sub_i_934(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4067
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4225), .Z(i_psram_sub_n_999
));
notech_ao4 i_psram_sub_i_935(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4068
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4226), .Z(i_psram_sub_n_998
));
notech_ao4 i_psram_sub_i_936(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4069
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4227), .Z(i_psram_sub_n_997
));
notech_ao4 i_psram_sub_i_937(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4070
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4228), .Z(i_psram_sub_n_996
));
notech_ao4 i_psram_sub_i_938(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4071
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4229), .Z(i_psram_sub_n_995
));
notech_ao4 i_psram_sub_i_939(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4072
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4230), .Z(i_psram_sub_n_994
));
notech_ao4 i_psram_sub_i_940(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4073
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4231), .Z(i_psram_sub_n_993
));
notech_ao4 i_psram_sub_i_941(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4074
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4232), .Z(i_psram_sub_n_992
));
notech_ao4 i_psram_sub_i_942(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4075
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4233), .Z(i_psram_sub_n_991
));
notech_ao4 i_psram_sub_i_943(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4076
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4234), .Z(i_psram_sub_n_990
));
notech_ao4 i_psram_sub_i_944(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4077
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4235), .Z(i_psram_sub_n_989
));
notech_ao4 i_psram_sub_i_945(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4078
), .C(i_psram_sub_n_971), .D(i_psram_sub_n_4236), .Z(i_psram_sub_n_988
));
notech_ao4 i_psram_sub_i_946(.A(i_psram_sub_n_564), .B(i_psram_sub_n_4079
), .C(i_psram_sub_n_4237), .D(i_psram_sub_n_971), .Z(i_psram_sub_n_987
));
notech_nao3 i_psram_sub_i_947(.A(i_psram_sub_n_954), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_985), .Z(i_psram_sub_n_986));
notech_nand2 i_psram_sub_i_61438(.A(i_psram_sub_n_4027), .B(i_psram_sub_n_4025
), .Z(i_psram_sub_n_985));
notech_nand3 i_psram_sub_i_83(.A(i_psram_sub_n_954), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_3994), .Z(i_psram_sub_n_984));
notech_nand2 i_psram_sub_i_68(.A(s00_axi_wready), .B(s00_axi_wlast), .Z(i_psram_sub_n_982
));
notech_nand3 i_psram_sub_i_73(.A(i_psram_sub_n_954), .B(i_psram_sub_n_979
), .C(s00_axi_aresetn), .Z(i_psram_sub_n_980));
notech_and2 i_psram_sub_i_35(.A(i_psram_sub_mem_idle), .B(i_psram_sub_n_4398
), .Z(i_psram_sub_n_979));
notech_nand3 i_psram_sub_i_87(.A(i_psram_sub_n_954), .B(i_psram_sub_n_975
), .C(s00_axi_aresetn), .Z(i_psram_sub_n_976));
notech_and4 i_psram_sub_i_67(.A(i_psram_sub_state[1]), .B(i_psram_sub_n_4027
), .C(i_psram_sub_state[0]), .D(i_psram_sub_mem_idle), .Z(i_psram_sub_n_975
));
notech_nand3 i_psram_sub_i_61441(.A(i_psram_sub_state[1]), .B(i_psram_sub_n_4027
), .C(i_psram_sub_state[0]), .Z(i_psram_sub_n_974));
notech_and2 i_psram_sub_i_14(.A(i_psram_sub_n_971), .B(i_psram_sub_n_970
), .Z(i_psram_sub_n_972));
notech_or4 i_psram_sub_i_75(.A(i_psram_sub_n_954), .B(i_psram_sub_n_4319
), .C(i_psram_sub_n_968), .D(i_psram_sub_n_3996), .Z(i_psram_sub_n_971
));
notech_or4 i_psram_sub_i_65(.A(i_psram_sub_n_954), .B(i_psram_sub_n_4319
), .C(i_psram_sub_n_968), .D(i_psram_sub_n_965), .Z(i_psram_sub_n_970
));
notech_nao3 i_psram_sub_i_51(.A(s00_axi_aresetn), .B(i_psram_sub_n_3995)
, .C(i_psram_sub_n_954), .Z(i_psram_sub_n_969));
notech_or4 i_psram_sub_i_25(.A(s00_axi_wready), .B(i_psram_sub_n_4029),
.C(i_psram_sub_axi_arv_arr_flag), .D(i_psram_sub_n_4321), .Z(i_psram_sub_n_968
));
notech_or2 i_psram_sub_i_71446(.A(s00_axi_wstrb[0]), .B(s00_axi_wstrb[1]
), .Z(i_psram_sub_n_965));
notech_nand3 i_psram_sub_i_88(.A(i_psram_sub_n_954), .B(i_psram_sub_n_962
), .C(s00_axi_aresetn), .Z(i_psram_sub_n_963));
notech_ao3 i_psram_sub_i_20(.A(i_psram_sub_n_961), .B(i_psram_sub_state[
0]), .C(i_psram_sub_n_959), .Z(i_psram_sub_n_962));
notech_nand2 i_psram_sub_i_74(.A(i_psram_sub_n_4314), .B(i_psram_sub_n_4315
), .Z(i_psram_sub_n_961));
notech_nao3 i_psram_sub_i_61435(.A(i_psram_sub_n_4027), .B(i_psram_sub_state
[0]), .C(i_psram_sub_state[1]), .Z(i_psram_sub_n_960));
notech_or2 i_psram_sub_i_965(.A(i_psram_sub_state[1]), .B(i_psram_sub_state
[2]), .Z(i_psram_sub_n_959));
notech_nand2 i_psram_sub_i_0(.A(i_psram_sub_n_954), .B(s00_axi_aresetn),
.Z(i_psram_sub_n_958));
notech_or4 i_psram_sub_i_89(.A(i_psram_sub_n_954), .B(s00_axi_rvalid), .C
(i_psram_sub_n_4319), .D(i_psram_sub_n_4024), .Z(i_psram_sub_n_957
));
notech_or4 i_psram_sub_i_1(.A(i_psram_sub_state[1]), .B(i_psram_sub_state
[0]), .C(i_psram_sub_state[2]), .D(i_psram_sub_n_4319), .Z(i_psram_sub_n_955
));
notech_nao3 i_psram_sub_i_61588(.A(i_psram_sub_n_4025), .B(i_psram_sub_n_4027
), .C(i_psram_sub_state[1]), .Z(i_psram_sub_n_954));
notech_nao3 i_psram_sub_i_649(.A(i_psram_sub_n_962), .B(i_psram_sub_mem_idle
), .C(i_psram_sub_n_958), .Z(i_psram_sub_n_952));
notech_or4 i_psram_sub_i_161596(.A(i_psram_sub_state[1]), .B(i_psram_sub_state
[0]), .C(i_psram_sub_n_980), .D(i_psram_sub_n_4027), .Z(i_psram_sub_n_951
));
notech_and3 i_psram_sub_i_81056(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_360), .Z(i_psram_sub_n_918));
notech_and3 i_psram_sub_i_71055(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_361), .Z(i_psram_sub_n_917));
notech_and3 i_psram_sub_i_61054(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_362), .Z(i_psram_sub_n_916));
notech_and3 i_psram_sub_i_51053(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_363), .Z(i_psram_sub_n_915));
notech_and3 i_psram_sub_i_41052(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_n_364), .Z(i_psram_sub_n_914));
notech_nao3 i_psram_sub_i_11049(.A(s00_axi_aresetn), .B(i_psram_sub_n_1006
), .C(i_psram_sub_axi_arlen_cntr[0]), .Z(i_psram_sub_n_913));
notech_and2 i_psram_sub_i_81032(.A(s00_axi_arlen[7]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_912));
notech_and2 i_psram_sub_i_71031(.A(s00_axi_arlen[6]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_911));
notech_and2 i_psram_sub_i_61030(.A(s00_axi_arlen[5]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_910));
notech_and2 i_psram_sub_i_51029(.A(s00_axi_arlen[4]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_909));
notech_and2 i_psram_sub_i_41028(.A(s00_axi_arlen[3]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_908));
notech_and2 i_psram_sub_i_31027(.A(s00_axi_arlen[2]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_907));
notech_and2 i_psram_sub_i_21026(.A(s00_axi_arlen[1]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_906));
notech_and2 i_psram_sub_i_11025(.A(s00_axi_arlen[0]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_905));
notech_xor2 i_psram_sub_i_93(.A(i_psram_sub_axi_arlen_cntr[7]), .B(i_psram_sub_n_1012
), .Z(i_psram_sub_n_360));
notech_xor2 i_psram_sub_i_94(.A(i_psram_sub_axi_arlen_cntr[6]), .B(i_psram_sub_n_1011
), .Z(i_psram_sub_n_361));
notech_xor2 i_psram_sub_i_95(.A(i_psram_sub_axi_arlen_cntr[5]), .B(i_psram_sub_n_1010
), .Z(i_psram_sub_n_362));
notech_xor2 i_psram_sub_i_96(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_n_1009
), .Z(i_psram_sub_n_363));
notech_xor2 i_psram_sub_i_97(.A(i_psram_sub_n_4007), .B(i_psram_sub_n_1008
), .Z(i_psram_sub_n_364));
notech_xor2 i_psram_sub_i_99(.A(i_psram_sub_axi_awlen_cntr[7]), .B(i_psram_sub_n_1083
), .Z(i_psram_sub_n_365));
notech_xor2 i_psram_sub_i_100(.A(i_psram_sub_axi_awlen_cntr[6]), .B(i_psram_sub_n_1082
), .Z(i_psram_sub_n_366));
notech_xor2 i_psram_sub_i_101(.A(i_psram_sub_axi_awlen_cntr[5]), .B(i_psram_sub_n_1081
), .Z(i_psram_sub_n_367));
notech_xor2 i_psram_sub_i_102(.A(i_psram_sub_axi_awlen_cntr[4]), .B(i_psram_sub_n_1080
), .Z(i_psram_sub_n_368));
notech_xor2 i_psram_sub_i_103(.A(i_psram_sub_n_4018), .B(i_psram_sub_n_1079
), .Z(i_psram_sub_n_369));
notech_or2 i_psram_sub_i_106(.A(s00_axi_awburst[0]), .B(i_psram_sub_n_462
), .Z(i_psram_sub_n_370));
notech_or2 i_psram_sub_i_107(.A(s00_axi_arburst[0]), .B(i_psram_sub_n_510
), .Z(i_psram_sub_n_371));
notech_nao3 i_psram_sub_i_112(.A(i_psram_sub_mem_idle), .B(s00_axi_aresetn
), .C(i_psram_sub_n_974), .Z(i_psram_sub_n_372));
notech_nao3 i_psram_sub_i_62(.A(i_psram_sub_n_974), .B(i_psram_sub_n_985
), .C(i_psram_sub_n_3994), .Z(i_psram_sub_n_374));
notech_or2 i_psram_sub_i_118(.A(i_psram_sub_state[0]), .B(i_psram_sub_n_4398
), .Z(i_psram_sub_n_375));
notech_ao4 i_psram_sub_i_91(.A(i_psram_sub_n_969), .B(i_psram_sub_n_3996
), .C(i_psram_sub_n_4319), .D(i_psram_sub_n_1149), .Z(i_psram_sub_n_377
));
notech_mux2 i_psram_sub_i_124(.S(i_psram_sub_state[0]), .A(i_psram_sub_state
[2]), .B(i_psram_sub_n_959), .Z(i_psram_sub_n_382));
notech_and3 i_psram_sub_i_3(.A(i_psram_sub_n_1227), .B(i_psram_sub_n_955
), .C(i_psram_sub_n_576), .Z(i_psram_sub_n_413));
notech_nao3 i_psram_sub_i_159(.A(i_psram_sub_n_985), .B(i_psram_sub_n_417
), .C(i_psram_sub_n_3994), .Z(i_psram_sub_n_416));
notech_nand2 i_psram_sub_i_76(.A(i_psram_sub_mem_idle), .B(i_psram_sub_n_4027
), .Z(i_psram_sub_n_417));
notech_and2 i_psram_sub_i_4(.A(i_psram_sub_n_1228), .B(i_psram_sub_n_955
), .Z(i_psram_sub_n_448));
notech_nand2 i_psram_sub_i_192(.A(s00_axi_bvalid), .B(s00_axi_bready), .Z
(i_psram_sub_n_449));
notech_and2 i_psram_sub_i_92(.A(i_psram_sub_n_980), .B(i_psram_sub_n_452
), .Z(i_psram_sub_n_451));
notech_nand3 i_psram_sub_i_194(.A(i_psram_sub_n_954), .B(s00_axi_wready)
, .C(s00_axi_aresetn), .Z(i_psram_sub_n_452));
notech_and2 i_psram_sub_i_12(.A(i_psram_sub_n_976), .B(i_psram_sub_n_963
), .Z(i_psram_sub_n_455));
notech_ao4 i_psram_sub_i_11(.A(i_psram_sub_n_958), .B(i_psram_sub_n_3993
), .C(i_psram_sub_n_961), .D(i_psram_sub_n_984), .Z(i_psram_sub_n_456
));
notech_ao4 i_psram_sub_i_105(.A(i_psram_sub_n_959), .B(i_psram_sub_n_4025
), .C(i_psram_sub_n_974), .D(i_psram_sub_n_4320), .Z(i_psram_sub_n_458
));
notech_nao3 i_psram_sub_i_310(.A(s00_axi_aresetn), .B(s00_axi_awaddr[0])
, .C(i_psram_sub_n_1077), .Z(i_psram_sub_n_460));
notech_nao3 i_psram_sub_i_313(.A(s00_axi_aresetn), .B(s00_axi_awaddr[1])
, .C(i_psram_sub_n_1077), .Z(i_psram_sub_n_461));
notech_and2 i_psram_sub_i_402(.A(s00_axi_awburst[1]), .B(i_psram_sub_n_3998
), .Z(i_psram_sub_n_462));
notech_nao3 i_psram_sub_i_416(.A(s00_axi_wvalid), .B(s00_axi_wready), .C
(i_psram_sub_n_464), .Z(i_psram_sub_n_463));
notech_ao4 i_psram_sub_i_82(.A(i_psram_sub_axi_awlen_cntr[7]), .B(i_psram_sub_n_4023
), .C(i_psram_sub_n_467), .D(i_psram_sub_n_466), .Z(i_psram_sub_n_464
));
notech_and2 i_psram_sub_i_27(.A(i_psram_sub_axi_awlen_cntr[7]), .B(i_psram_sub_n_4023
), .Z(i_psram_sub_n_466));
notech_ao4 i_psram_sub_i_72(.A(i_psram_sub_axi_awlen_cntr[6]), .B(i_psram_sub_n_4022
), .C(i_psram_sub_n_471), .D(i_psram_sub_n_470), .Z(i_psram_sub_n_467
));
notech_and2 i_psram_sub_i_29(.A(i_psram_sub_axi_awlen_cntr[6]), .B(i_psram_sub_n_4022
), .Z(i_psram_sub_n_470));
notech_ao4 i_psram_sub_i_64(.A(i_psram_sub_axi_awlen_cntr[5]), .B(i_psram_sub_n_4021
), .C(i_psram_sub_n_475), .D(i_psram_sub_n_474), .Z(i_psram_sub_n_471
));
notech_and2 i_psram_sub_i_33(.A(i_psram_sub_axi_awlen_cntr[5]), .B(i_psram_sub_n_4021
), .Z(i_psram_sub_n_474));
notech_ao4 i_psram_sub_i_59(.A(i_psram_sub_axi_awlen_cntr[4]), .B(i_psram_sub_n_4000
), .C(i_psram_sub_n_478), .D(i_psram_sub_n_4020), .Z(i_psram_sub_n_475
));
notech_and2 i_psram_sub_i_55(.A(i_psram_sub_axi_awlen_cntr[4]), .B(i_psram_sub_n_4000
), .Z(i_psram_sub_n_478));
notech_and2 i_psram_sub_i_31(.A(i_psram_sub_axi_awlen[3]), .B(i_psram_sub_n_4018
), .Z(i_psram_sub_n_481));
notech_ao4 i_psram_sub_i_109(.A(i_psram_sub_axi_awlen[2]), .B(i_psram_sub_n_4017
), .C(i_psram_sub_n_486), .D(i_psram_sub_n_485), .Z(i_psram_sub_n_482
));
notech_and2 i_psram_sub_i_42(.A(i_psram_sub_axi_awlen[2]), .B(i_psram_sub_n_4017
), .Z(i_psram_sub_n_485));
notech_ao4 i_psram_sub_i_79(.A(i_psram_sub_axi_awlen[1]), .B(i_psram_sub_n_4015
), .C(i_psram_sub_n_489), .D(i_psram_sub_n_1085), .Z(i_psram_sub_n_486
));
notech_and2 i_psram_sub_i_61(.A(i_psram_sub_axi_awlen[1]), .B(i_psram_sub_n_4015
), .Z(i_psram_sub_n_489));
notech_mux2 i_psram_sub_i_104(.S(i_psram_sub_axi_awlen_cntr[2]), .A(i_psram_sub_n_1078
), .B(i_psram_sub_axi_awlen_cntr[1]), .Z(i_psram_sub_n_494));
notech_nao3 i_psram_sub_i_457(.A(s00_axi_araddr[0]), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_1006), .Z(i_psram_sub_n_508));
notech_nao3 i_psram_sub_i_460(.A(s00_axi_araddr[1]), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_1006), .Z(i_psram_sub_n_509));
notech_and2 i_psram_sub_i_558(.A(s00_axi_arburst[1]), .B(i_psram_sub_n_3999
), .Z(i_psram_sub_n_510));
notech_nao3 i_psram_sub_i_567(.A(s00_axi_rvalid), .B(s00_axi_rready), .C
(i_psram_sub_n_512), .Z(i_psram_sub_n_511));
notech_ao4 i_psram_sub_i_90(.A(i_psram_sub_axi_arlen_cntr[7]), .B(i_psram_sub_n_4013
), .C(i_psram_sub_n_514), .D(i_psram_sub_n_582), .Z(i_psram_sub_n_512
));
notech_ao4 i_psram_sub_i_81(.A(i_psram_sub_axi_arlen_cntr[6]), .B(i_psram_sub_n_4011
), .C(i_psram_sub_n_517), .D(i_psram_sub_n_583), .Z(i_psram_sub_n_514
));
notech_ao4 i_psram_sub_i_71(.A(i_psram_sub_axi_arlen_cntr[5]), .B(i_psram_sub_n_4010
), .C(i_psram_sub_n_520), .D(i_psram_sub_n_585), .Z(i_psram_sub_n_517
));
notech_ao4 i_psram_sub_i_63(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_n_4009
), .C(i_psram_sub_n_587), .D(i_psram_sub_n_4001), .Z(i_psram_sub_n_520
));
notech_ao4 i_psram_sub_i_108(.A(i_psram_sub_axi_arlen[2]), .B(i_psram_sub_n_4006
), .C(i_psram_sub_n_528), .D(i_psram_sub_n_586), .Z(i_psram_sub_n_525
));
notech_ao4 i_psram_sub_i_78(.A(i_psram_sub_axi_arlen[1]), .B(i_psram_sub_n_4004
), .C(i_psram_sub_n_3997), .D(i_psram_sub_n_589), .Z(i_psram_sub_n_528
));
notech_mux2 i_psram_sub_i_98(.S(i_psram_sub_axi_arlen_cntr[2]), .A(i_psram_sub_n_1007
), .B(i_psram_sub_axi_arlen_cntr[1]), .Z(i_psram_sub_n_535));
notech_nand2 i_psram_sub_i_600(.A(s00_axi_wdata[16]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_549));
notech_nand2 i_psram_sub_i_603(.A(s00_axi_wdata[17]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_550));
notech_nand2 i_psram_sub_i_606(.A(s00_axi_wdata[18]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_551));
notech_nand2 i_psram_sub_i_609(.A(s00_axi_wdata[19]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_552));
notech_nand2 i_psram_sub_i_612(.A(s00_axi_wdata[20]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_553));
notech_nand2 i_psram_sub_i_615(.A(s00_axi_wdata[21]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_554));
notech_nand2 i_psram_sub_i_618(.A(s00_axi_wdata[22]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_555));
notech_nand2 i_psram_sub_i_621(.A(s00_axi_wdata[23]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_556));
notech_nand2 i_psram_sub_i_624(.A(s00_axi_wdata[24]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_557));
notech_nand2 i_psram_sub_i_627(.A(s00_axi_wdata[25]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_558));
notech_nand2 i_psram_sub_i_630(.A(s00_axi_wdata[26]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_559));
notech_nand2 i_psram_sub_i_633(.A(s00_axi_wdata[27]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_560));
notech_nand2 i_psram_sub_i_636(.A(s00_axi_wdata[28]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_561));
notech_nand2 i_psram_sub_i_639(.A(s00_axi_wdata[29]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_562));
notech_nand2 i_psram_sub_i_642(.A(s00_axi_wdata[30]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_563));
notech_ao4 i_psram_sub_i_18(.A(i_psram_sub_n_979), .B(i_psram_sub_n_986)
, .C(i_psram_sub_n_961), .D(i_psram_sub_n_984), .Z(i_psram_sub_n_564
));
notech_nand2 i_psram_sub_i_645(.A(s00_axi_wdata[31]), .B(i_psram_sub_n_566
), .Z(i_psram_sub_n_565));
notech_nand2 i_psram_sub_i_2(.A(i_psram_sub_n_970), .B(i_psram_sub_n_963
), .Z(i_psram_sub_n_566));
notech_or2 i_psram_sub_i_647(.A(s00_axi_rvalid), .B(i_psram_sub_n_4024),
.Z(i_psram_sub_n_568));
notech_or4 i_psram_sub_i_648(.A(s00_axi_bvalid), .B(i_psram_sub_n_982),
.C(i_psram_sub_n_4029), .D(i_psram_sub_n_4321), .Z(i_psram_sub_n_569
));
notech_or4 i_psram_sub_i_110(.A(i_psram_sub_n_955), .B(i_psram_sub_mem_idle
), .C(i_psram_sub_n_4024), .D(i_psram_sub_n_4105), .Z(i_psram_sub_n_570
));
notech_nor2 i_psram_sub_i_111(.A(i_psram_sub_n_979), .B(i_psram_sub_n_1227
), .Z(i_psram_sub_n_571));
notech_and4 i_psram_sub_i_113(.A(i_psram_sub_state[1]), .B(s00_axi_aresetn
), .C(i_psram_sub_n_575), .D(i_psram_sub_n_374), .Z(i_psram_sub_n_573
));
notech_nand3 i_psram_sub_i_114(.A(i_psram_sub_n_962), .B(i_psram_sub_mem_idle
), .C(s00_axi_aresetn), .Z(i_psram_sub_n_574));
notech_nand2 i_psram_sub_i_34(.A(i_psram_sub_mem_idle), .B(i_psram_sub_n_375
), .Z(i_psram_sub_n_575));
notech_nao3 i_psram_sub_i_155(.A(s00_axi_aresetn), .B(i_psram_sub_n_4320
), .C(i_psram_sub_n_974), .Z(i_psram_sub_n_576));
notech_ao3 i_psram_sub_i_748(.A(i_psram_sub_n_1213), .B(i_psram_sub_n_4061
), .C(i_psram_sub_n_1220), .Z(i_psram_sub_n_579));
notech_ao3 i_psram_sub_i_813(.A(s00_axi_aresetn), .B(i_psram_sub_n_4024)
, .C(i_psram_sub_n_1077), .Z(i_psram_sub_n_580));
notech_ao3 i_psram_sub_i_802(.A(i_psram_sub_n_4029), .B(s00_axi_aresetn)
, .C(i_psram_sub_n_1006), .Z(i_psram_sub_n_581));
notech_and2 i_psram_sub_i_26(.A(i_psram_sub_axi_arlen_cntr[7]), .B(i_psram_sub_n_4013
), .Z(i_psram_sub_n_582));
notech_and2 i_psram_sub_i_28(.A(i_psram_sub_axi_arlen_cntr[6]), .B(i_psram_sub_n_4011
), .Z(i_psram_sub_n_583));
notech_and2 i_psram_sub_i_30(.A(i_psram_sub_axi_arlen[3]), .B(i_psram_sub_n_4007
), .Z(i_psram_sub_n_584));
notech_and2 i_psram_sub_i_32(.A(i_psram_sub_axi_arlen_cntr[5]), .B(i_psram_sub_n_4010
), .Z(i_psram_sub_n_585));
notech_and2 i_psram_sub_i_41(.A(i_psram_sub_axi_arlen[2]), .B(i_psram_sub_n_4006
), .Z(i_psram_sub_n_586));
notech_and2 i_psram_sub_i_54(.A(i_psram_sub_axi_arlen_cntr[4]), .B(i_psram_sub_n_4009
), .Z(i_psram_sub_n_587));
notech_nand2 i_psram_sub_i_58(.A(i_psram_sub_axi_arlen[1]), .B(i_psram_sub_n_4004
), .Z(i_psram_sub_n_588));
notech_nand2 i_psram_sub_i_203(.A(i_psram_sub_axi_arlen_cntr[0]), .B(i_psram_sub_n_4008
), .Z(i_psram_sub_n_589));
notech_nand2 i_psram_sub_i_208(.A(i_psram_sub_n_566), .B(i_psram_sub_n_4314
), .Z(i_psram_sub_n_593));
notech_or4 i_psram_sub_i_209(.A(i_psram_sub_state[1]), .B(i_psram_sub_state
[2]), .C(i_psram_sub_n_4025), .D(i_psram_sub_n_4320), .Z(i_psram_sub_n_596
));
notech_nand2 i_psram_sub_i_212(.A(i_psram_sub_n_566), .B(i_psram_sub_n_4315
), .Z(i_psram_sub_n_597));
notech_and2 i_psram_sub_i_11033(.A(s00_axi_awlen[0]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_791767));
notech_and2 i_psram_sub_i_21034(.A(s00_axi_awlen[1]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_792768));
notech_and2 i_psram_sub_i_31035(.A(s00_axi_awlen[2]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_793769));
notech_and2 i_psram_sub_i_41036(.A(s00_axi_awlen[3]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_794770));
notech_and2 i_psram_sub_i_51037(.A(s00_axi_awlen[4]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_795771));
notech_and2 i_psram_sub_i_61038(.A(s00_axi_awlen[5]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_796772));
notech_and2 i_psram_sub_i_71039(.A(s00_axi_awlen[6]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_797773));
notech_and2 i_psram_sub_i_81040(.A(s00_axi_awlen[7]), .B(s00_axi_aresetn
), .Z(i_psram_sub_n_798774));
notech_nao3 i_psram_sub_i_11065(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_axi_awlen_cntr[0]), .Z(i_psram_sub_n_799775)
);
notech_and3 i_psram_sub_i_41068(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_369), .Z(i_psram_sub_n_800776));
notech_and3 i_psram_sub_i_51069(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_368), .Z(i_psram_sub_n_801777));
notech_and3 i_psram_sub_i_61070(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_367), .Z(i_psram_sub_n_802778));
notech_and3 i_psram_sub_i_71071(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_366), .Z(i_psram_sub_n_803779));
notech_and3 i_psram_sub_i_81072(.A(s00_axi_aresetn), .B(i_psram_sub_n_1077
), .C(i_psram_sub_n_365), .Z(i_psram_sub_n_804780));
endmodule
|
module score_counter
(
input wire clk, reset,
input wire d_inc, d_dec, d_clr,
// inc -- increase (hit signal)
// dec -- decrease by 2 (kill signal)
// cle -- simple clear signal
output wire [3:0] dig0, dig1
);
// signal declaration
reg [3:0] dig0_reg, dig1_reg, dig0_next, dig1_next;
// well, common sense, hah?
// simple state machine like textbook
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
dig1_reg <= 0;
dig0_reg <= 0;
end
else
begin
dig1_reg <= dig1_next;
dig0_reg <= dig0_next;
end
// next-state logic
always @*
begin
dig0_next = dig0_reg;
dig1_next = dig1_reg;
if (d_clr)
begin
dig0_next = 0;
dig1_next = 0;
end
else if (d_inc)
if (dig0_reg==9)
begin
dig0_next = 0;
if (dig1_reg==9)
dig1_next = 0;
else
dig1_next = dig1_reg + 1;
end
else // dig0 not 9
dig0_next = dig0_reg + 1;
else if (d_dec)
if((dig1_reg == 0) && (dig0_reg < 2))
begin
dig0_next = 0;
dig1_next = 0;
end
else if((dig1_reg > 0) && (dig0_reg == 1))
begin
dig1_next = dig1_reg - 1;
dig0_next = 9;
end
else if((dig1_reg > 0) && (dig0_reg == 0))
begin
dig1_next = dig1_reg - 1;
dig0_next = 8;
end
else
dig0_next = dig0_reg - 2;
end
// output
assign dig0 = dig0_reg;
assign dig1 = dig1_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Tue Jun 30 18:14:28 2015
// Host : Vangelis-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/About/About_funcsim.v
// Design : About
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.4" *) (* CHECK_LICENSE_TYPE = "About,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "About,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=About.mif,C_INIT_FILE=About.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}" *)
(* NotValidForBitStream *)
module About
(clka,
addra,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [9:0]addra;
output [799:0]douta;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [799:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [799:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "22" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 60.4532 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "About.mem" *)
(* C_INIT_FILE_NAME = "About.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "3" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "600" *)
(* C_READ_DEPTH_B = "600" *)
(* C_READ_WIDTH_A = "800" *)
(* C_READ_WIDTH_B = "800" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "600" *)
(* C_WRITE_DEPTH_B = "600" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "800" *)
(* C_WRITE_WIDTH_B = "800" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
About_blk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[799:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[799:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(1'b0),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module About_blk_mem_gen_generic_cstr
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
About_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[17:0]));
About_blk_mem_gen_prim_width__parameterized9 \ramloop[10].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[377:342]));
About_blk_mem_gen_prim_width__parameterized10 \ramloop[11].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[413:378]));
About_blk_mem_gen_prim_width__parameterized11 \ramloop[12].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[449:414]));
About_blk_mem_gen_prim_width__parameterized12 \ramloop[13].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[485:450]));
About_blk_mem_gen_prim_width__parameterized13 \ramloop[14].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[521:486]));
About_blk_mem_gen_prim_width__parameterized14 \ramloop[15].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[557:522]));
About_blk_mem_gen_prim_width__parameterized15 \ramloop[16].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[593:558]));
About_blk_mem_gen_prim_width__parameterized16 \ramloop[17].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[629:594]));
About_blk_mem_gen_prim_width__parameterized17 \ramloop[18].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[665:630]));
About_blk_mem_gen_prim_width__parameterized18 \ramloop[19].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[701:666]));
About_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[53:18]));
About_blk_mem_gen_prim_width__parameterized19 \ramloop[20].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[737:702]));
About_blk_mem_gen_prim_width__parameterized20 \ramloop[21].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[773:738]));
About_blk_mem_gen_prim_width__parameterized21 \ramloop[22].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[799:774]));
About_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[89:54]));
About_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[125:90]));
About_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[161:126]));
About_blk_mem_gen_prim_width__parameterized4 \ramloop[5].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[197:162]));
About_blk_mem_gen_prim_width__parameterized5 \ramloop[6].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[233:198]));
About_blk_mem_gen_prim_width__parameterized6 \ramloop[7].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[269:234]));
About_blk_mem_gen_prim_width__parameterized7 \ramloop[8].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[305:270]));
About_blk_mem_gen_prim_width__parameterized8 \ramloop[9].ram.r
(.addra(addra),
.clka(clka),
.douta(douta[341:306]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
About_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized10 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized11 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized12 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized13 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized14 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized15 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized16 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized17 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized18 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized19 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized20 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized21
(douta,
clka,
addra);
output [25:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [25:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized21 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized4 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized5 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized6 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized7 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized8 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module About_blk_mem_gen_prim_width__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
About_blk_mem_gen_prim_wrapper_init__parameterized9 \prim_init.ram
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra);
output [17:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [17:0]douta;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP({douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'hF000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000EFFF104444444444444444446666666611FF),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'hFFFFFF0000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'hFFFF7EC0FFFF7EC0FFFF7CC07FFF18C0000000C0000001C0FFFFFFC0FFFFFF80),
.INIT_39(256'h03F000C003F000C003F000C003F000C07FFF00C0FFFF10C0FFFF3CC0FFFF7EC0),
.INIT_3A(256'h03F000C003F000C003F000C003F000C003F000C003F000C003F000C003F000C0),
.INIT_3B(256'h000000C0000000C003F000C003F000C003F000C003F000C003F000C003F000C0),
.INIT_3C(256'h00000000000000000000000000000000FFFFFE00FFFFFF00FFFFFF80FFFFFFC0),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized1
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'hF000000000000000000000000000000008004400080000000000000000000000),
.INITP_07(256'h0000000000000000000CEE2AA2FF4FFF00999999911199BBBB333BBBB99900FF),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'hCCC000008CC00000000000000000000000000000000000000000000000000000),
.INIT_33(256'h000000008CC00000CCC00000CCC00000CCC00000CDC00000CFC00000CEC00000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'hFFFFFFFF00000000000000000000000000000000000000000000000000000000),
.INIT_38(256'hF8FF00FCF8FF00FCF8FF00FCF0FE00FC0000000000000000FFFFFFFFFFFFFFFF),
.INIT_39(256'hF0FFFCFCF0FFF8FC00FFF0FC00FFF0FC00FFE0FCF8FFC0FCF8FFC0FCF8FF80FC),
.INIT_3A(256'hF8FE0FFC00FE1FFC00FE3FFC00FE7FFCF0FE7FFCF0FEFFFCF0FEFEFCF0FFFEFC),
.INIT_3B(256'h0000000000000000F0FE00FCF8FE01FCF8FE03FCF8FE03FCF8FE07FCF8FE0FFC),
.INIT_3C(256'h8E19FE7807390EF8E7F1FEDEE3E1FC8E1C9F0373FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3D(256'h000000000000000000000000E0C00400E3F10E70E7F90E7006391C708E19FC30),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized10
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000002224440002222220004444442220000000000000000000000000),
.INITP_01(256'h0999999DD888899DDDD000000000004400000011111111550000000000000000),
.INITP_02(256'h0000000055555555555555555500000000000440000444400000044000000000),
.INITP_03(256'h9991111990000000000000111155551111115500000000000000000000000000),
.INITP_04(256'h000011004400000000000BB11111111111111BB0000000000000000991111119),
.INITP_05(256'h000000000000000000000000000BB99111133111111330000000000044000000),
.INITP_06(256'h0000000000000000888888888000000000000000000000000000000000000000),
.INITP_07(256'h000000000000000000000006777DDCCCCCCCCCCCC44444444444444557777600),
.INITP_08(256'h000000000000555566666666EEEE666666666666AAAA99990000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h01F0000F01F07E0F01F07E0F01F07E0F007FF00F007FF00F007FF00F00000000),
.INIT_04(256'h000F800F000F800F000F800F007E000F007E000F007E000F01F0000F01F0000F),
.INIT_05(256'h01F07E0101F07E0100007E0100007E0100007E010001F00F0001F00F0001F00F),
.INIT_06(256'h00000000000000000000000000000000007FF001007FF001007FF00101F07E01),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h3C78F0E13C78F0E13C78F0E13C78F0E13C78F0E13C78F0E10FE0FF810FE0FF81),
.INIT_0B(256'h3C78F0013C78F0013C78F0013C78F0013C78F0013C78F0013C78FF813C78FF81),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000FE0F0010FE0F001),
.INIT_0D(256'h0FE0F0E103803F8103803F810000000000000000000000000000000000000000),
.INIT_0E(256'h3FF8F3E13C78F0013C78F0013C78F0013C78F0013C78F0E13C78F0E10FE0F0E1),
.INIT_0F(256'h000000003C783FE13C783FE13C78F0E13C78F0E13C78F0E13C78F0E13FF8F3E1),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0F0000013C0000013C0000013C7800013C7800010FE000010FE0000100000000),
.INIT_12(256'h3C780001007800010078000100E0000100E0000103800001038000010F000001),
.INIT_13(256'h00000000000000000000000000000000000000000FE000010FE000013C780001),
.INIT_14(256'h0FE03F800FE03F80000000000000000000000000000000000000000000000000),
.INIT_15(256'h0380F0E00380F0E00380F0E00380F0E00380F0E10380F0E10380F0E10380F0E1),
.INIT_16(256'h0FE03F800FE03F800380F0E10380F0E10380F0E00380F0E00380F0E00380F0E0),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h3C78F0E03C78F0E03C78F0E03C78F0E03FE0F0E03FE0F0E00000000000000000),
.INIT_1C(256'h3C78F0E03C78F0E03CE0F0E03CE0F0E03FE0F0E03FE0F0E03C78F0E03C78F0E0),
.INIT_1D(256'h000000000000000000000000000000003C780F003C780F003C783F803C783F80),
.INIT_1E(256'hF00000FF00000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'hC00000FF000000E1000000E1000000E1000000E13C0000E13C0000E1F00000FF),
.INIT_20(256'hF00000E03C0000E03C0000E03C0000E03C0000E0F00000E0F00000E0C00000FF),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000F00000E0),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h3C78F0E03C78F0E03C78F0E03C78F0E03C78F0E0F01FC0E0F01FC0E000000000),
.INIT_24(256'h3C78F0E03C78F0E03C78F0E03C78F0E03C78F0E03C78F0E03C78F0E03C78F0E0),
.INIT_25(256'h0000000000000000000000000000000000000000F01FC0FFF01FC0FF3C78F0E0),
.INIT_26(256'h0FE0F0790FE0F079000000000000000000000000000000000000000000000000),
.INIT_27(256'h3C78F3793C78F3793C78F3793C78F3793C78FCF93C78FCF93C78F0793C78F079),
.INIT_28(256'h0FE0F0790FE0F0793C78F0793C78F0793C78F0793C78F0793C78F3793C78F379),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h3C7800E13C7800E13C7800E13C7FF0FF3C7FF0FF000000000000000000000000),
.INIT_2B(256'h3C7800E13C7800E73C7800E73C7FC0FF3C7FC0FF3C7800E13C7800E13C7800E1),
.INIT_2C(256'h000000000000000000000000C07FF0E1C07FF0E1F07800E1F07800E13C7800E1),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'hBF7800F100000000000000000000000000000000000000000000000000000000),
.INIT_35(256'hBF7800F1B06C0061B0660061B0660061BE660061B0660061B0660061B06C0061),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h01E007FE01FFFFFC01FFFFF001FFFFE001FFFF8001FFFE000000000000000000),
.INIT_39(256'h01E0000701E0000701E0000F01E0000F01E0001F01E0003F01E0007F01E000FE),
.INIT_3A(256'h01E0000301E0000301E0000301E0000301E0000301E0000301E0000701E00007),
.INIT_3B(256'hE1E0001FC1E0000FC1E0000781E0000781E0000781E0000701E0000301E00003),
.INIT_3C(256'hFDFFFFC0F9FFFFE0F9FFFFF8F9E00FFCF1E001FEF1E000FEE1E0003FE1E0001F),
.INIT_3D(256'h000000000000000000000000000000000000000000000000000000007DFFFF00),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'hFE00FE03FE00FE03FE00FE03FE00FE03E0001FFFE0001FFFE0001FFFE0001FFF),
.INIT_43(256'h1FC0FE001FC0FE001FC0FE001FC0FE001FC0FE031FC0FE031FC0FE031FC0FE03),
.INIT_44(256'hFFC0FE00FFC0FE00FFC0FE00FFC0FE001FC0FE001FC0FE001FC0FE001FC0FE00),
.INIT_45(256'h1FC0FE031FC0FE031FC0FE031FC0FE031FC0FE031FC0FE031FC0FE031FC0FE03),
.INIT_46(256'h000000000000000000000000000000001FC01FFF1FC01FFF1FC01FFF1FC01FFF),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized11
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000CCCCCCCCCCCCCCCCCCCCCCCCCCC0000000000000000000000000),
.INITP_01(256'h08888888800001188880000000000077CCCCCCCCCCCCCCEE0000000000000000),
.INITP_02(256'h0000000077444444CCCCCCCCFF000000000007777775555777777DD000000000),
.INITP_03(256'h22222222200000000000DDCCCCCCDDEEEEEEDD00000000000000000000000000),
.INITP_04(256'h88888888110000000000022EEEEAAAAAAEEEE220000000000000000222222222),
.INITP_05(256'h000000000000000000000000000EECCCCCCCCCCCCCCEE0000000000011888888),
.INITP_06(256'h0000000000000000FBBBEEBBF000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000CCCCC888833333306666666666675111111111100),
.INITP_08(256'h000000000000DDDD999999999999DDDD999999998888CCCC0000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h81F0000081F0000081F0000081F0000081F0000081F0000081F0000000000000),
.INIT_04(256'hFFF00000FFF00000FFF0000081F0000081F0000081F0000081F0000081F00000),
.INIT_05(256'h81F0000081F0000081F0000081F0000081F0000081F0000081F0000081F00000),
.INIT_06(256'h0000000000000000000000000000000081F0000081F0000081F0000081F00000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'hC3800F00C3800F00C3800F00C3800F00C3800F00C3800F00C3FF0F00C3FF0F00),
.INIT_0B(256'h03800F0003800F00C3800F00C3800F00C3800F00C3800F00C3FE0F00C3FE0F00),
.INIT_0C(256'h00000000000000000000000000000000000000000000000003FF0FFE03FF0FFE),
.INIT_0D(256'hC0000F0700000F0700000F070000000000000000000000000000000000000000),
.INIT_0E(256'h00000F6700000F6700000F6700000F6700000F6700000F9F00000F9FC0000F07),
.INIT_0F(256'h0000000000000F0700000F07C0000F07C0000F07C0000F07C0000F0700000F67),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h038700E0038700E0038700E0038700E0038700E0C3FE03F8C3FE03F800000000),
.INIT_12(256'h038700E0038700E0038700E0039E00E0039E00E003FE00E003FE00E0038700E0),
.INIT_13(256'h0000000000000000000000000000000000000000038703F8038703F8038700E0),
.INIT_14(256'h03FF03F803FF03F8000000000000000000000000000000000000000000000000),
.INIT_15(256'h03FE0F0003FE0F00C3800F00C3800F00C3800F1EC3800F1EC3800F1EC3800F1E),
.INIT_16(256'h03FF03FE03FF03FE03800F1E03800F1E03800F1E03800F1E03800F7E03800F7E),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'hC3870F00C3870F00C3870F00C3870F00C3FE0FFEC3FE0FFE0000000000000000),
.INIT_1C(256'hC3800F00C3800F00C3800F00C3800F00C3FE0FF8C3FE0FF8C3870F00C3870F00),
.INIT_1D(256'h0000000000000000000000000000000003800FFE03800FFEC3800F00C3800F00),
.INIT_1E(256'hFF01FC0700000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h3C070F013C070F073C070F073C070F1E3C070F1E3C070F1E3C070F1EFF01FC07),
.INIT_20(256'hFF01FC073C070F1E3C070F1E3C070F003C070F003C070F003C070F003C070F01),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000FF01FC07),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'hC0070F1EC3870F1EC3870F1EC3870F1EC3870F1EFF070F07FF070F0700000000),
.INIT_24(256'hC3870F1EC3870F1EC3870F1EC0070F1EC0070F1EC007FF1EC007FF1EC0070F1E),
.INIT_25(256'h0000000000000000000000000000000000000000FF070F07FF070F07C3870F1E),
.INIT_26(256'h000003F8000003F8000000000000000000000000000000000000000000000000),
.INIT_27(256'hC0000F00C0000F00C0000F00C0000F00C0000F1EC0000F1E00000F1E00000F1E),
.INIT_28(256'h000003F8000003F800000F1E00000F1EC0000F1EC0000F1EC0000F00C0000F00),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'hF0E0F01EC0E0F01EC0E0F01EC0E1FC1EC0E1FC1E000000000000000000000000),
.INIT_2B(256'hC0E0F01EC3E0F01EC3E0F01ECFE0F01ECFE0F01EFCE0F01EFCE0F01EF0E0F01E),
.INIT_2C(256'h000000000000000000000000C0E1FC01C0E1FC01C0E0F007C0E0F007C0E0F01E),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'hF1C3871800000000000000000000000000000000000000000000000000000000),
.INIT_35(256'hF1C3879803610C9800610C9800C10D99E0810C1B01010C1E03010C9C03610C98),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h007C3FC0007C3FC0003E3F80003E1F80003E1F80003E0F000000000000000000),
.INIT_39(256'h01E0E0F801E0F0F800F0F0F800F0F8F000F0F8F000F8F9E000F87DE0007C7DE0),
.INIT_3A(256'h0F0F001F0707801F0787803F0787803E03C3C03E03C3C07E03C1E07C01E1E0FC),
.INIT_3B(256'h3C7FFFFF3E3FFFFF3E3FFFFF1E3FFFFF1F1FFFFF1F1FFFFF0F0F000F0F0F000F),
.INIT_3C(256'hE1E00000F0F00000F0F00000F8F00000F8F8000078F800017C7C00017C7C0001),
.INIT_3D(256'h00000000000000000000000000000000000000000000000000000000E1E00000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h80FF00FF80FF00FF80FF00FF80FF00FFFFF0000FFFF0000FFFF0000FFFF0000F),
.INIT_43(256'h80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07F0),
.INIT_44(256'h80FF07FF80FF07FF80FF07FF80FF07FFFFF007F0FFF007F0FFF007F0FFF007F0),
.INIT_45(256'h80FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07F080FF07F0),
.INIT_46(256'h00000000000000000000000000000000FFF007F0FFF007F0FFF007F0FFF007F0),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized12
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000AAACCCCCCCCCCCCCCCCCC4442220000000000000000000000000),
.INITP_01(256'h0AA332222222233332200000000000AA00111133111111BB0000000000000000),
.INITP_02(256'h0000000099111111999911119900000000000222222222222AA2233000000000),
.INITP_03(256'hCCCCCDDDD0000000000022111133331111113300000000000000000000000000),
.INITP_04(256'h3333119999000000000001111111100000011110000000000000000DDDDDDDDC),
.INITP_05(256'h0000000000000000000000000001111111111111111110000000000011111199),
.INITP_06(256'h0000000000000000111111111000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000222AAAAAAAAAAAAA2222333333337777776666620),
.INITP_08(256'h00000000000000000088888CCCCCEEEEECCCCC88888000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h81F07E0F01F07E0F01F07E0F01F07E0F007FF00F007FF00F007FF00F00000000),
.INIT_04(256'h81F0000F81F0000F81F0000F81F0000F81F0000F81F0000F81F07E0F81F07E0F),
.INIT_05(256'h81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F0000F81F0000F81F0000F),
.INIT_06(256'h00000000000000000000000000000000807FF00F807FF00F807FF00F81F07E0F),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h3C7800E13C7800E13C7800E13C7800E1F07800E1F07800E1C07FF0E1C07FF0E1),
.INIT_0B(256'hF078007FF078007F3C7800E13C7800E13C7800E13C7800E13C7FC0E13C7FC0E1),
.INIT_0C(256'h000000000000000000000000000000000000000000000000C07FF01EC07FF01E),
.INIT_0D(256'h000700E1001FC07F001FC07F0000000000000000000000000000000000000000),
.INIT_0E(256'h000700070007001E0007001E0007007800070078000700E0000700E0000700E1),
.INIT_0F(256'h00000000FC1FC07FFC1FC07F000700E1000700E1000700010007000100070007),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'hCF07001E3F07001E3F07001E0F07001E0F07001E0F1FC0FF0F1FC0FF00000000),
.INIT_12(256'h0F07001E0F07001E0F07001ECF07001ECF07001ECF07001ECF07001ECF07001E),
.INIT_13(256'h00000000000000000000000000000000000000000F1FC01E0F1FC01E0F07001E),
.INIT_14(256'hF00000FFF00000FF000000000000000000000000000000000000000000000000),
.INIT_15(256'hC00000FFC00000FF000000E1000000E1000000E1000000E13C0000E13C0000E1),
.INIT_16(256'hF00000E0F00000E03C0000E03C0000E03C0000E03C0000E0F00000E0F00000E0),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h007800E1007800E10078F0E10078F0E1001FC0E1001FC0E10000000000000000),
.INIT_1C(256'h0000F0E10000F0E10001C0E10001C0E1000700E1000700E1001E00E1001E00E1),
.INIT_1D(256'h00000000000000000000000000000000001FC07F001FC07F0078F0E10078F0E1),
.INIT_1E(256'h0FE03F8000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h03800F0003803C0003803C000380F0000380F0000380F0E00380F0E00FE03F80),
.INIT_20(256'h0FE03F800380F0E00380F0E0038000E0038000E0038003800380038003800F00),
.INIT_21(256'h000000000000000000000000000000000000000000000000000000000FE03F80),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h00003C010000F0010000F0010000F0E10000F0E100003F8000003F8000000000),
.INIT_24(256'h0000F0E1000000E1000000E1000003810000038100000F0100000F0100003C01),
.INIT_25(256'h000000000000000000000000000000000000000000003F8000003F800000F0E1),
.INIT_26(256'hC0783CFEC0783CFE000000000000000000000000000000000000000000000000),
.INIT_27(256'h3C79FCE13C79FCE13C7F3CE13C7F3CE13C7E3CE13C7E3CE1F0783CE7F0783CE7),
.INIT_28(256'h3C783CFE3C783CFE3C783CE73C783CE73C783CE13C783CE1FC78FCE1FC78FCE1),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000F0E10000F0E10000F0E10000F0E10000F0E1000000000000000000000000),
.INIT_2B(256'h0000F0E10000F0E10000F0E10000F0E10000F0E10000F0E10000F0E10000F0E1),
.INIT_2C(256'h00000000000000000000000000003F8100003F810000F0E10000F0E10000F0E1),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h000000E100000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h000000E1000000B10000009900000099000000990000009900000099000000B1),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h07871F0003C71F0003C71F0003E73F0001E73E0001E73E000007000000000000),
.INIT_39(256'h1F0703E01F0703C01F0703C00F0707C00F0707800F07078007870F8007870F00),
.INIT_3A(256'hF80700F8F80700F8780700F87C0700F07C0700F03E0701F03E0701E03E0701E0),
.INIT_3B(256'hC007001FC007001FE007003EE007003EE007003EF007007CF007007CF007007C),
.INIT_3C(256'h00070003000700030007000700070007800700078007000F8007000F8007000F),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000070003),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'hF000003FC000003F0000003F0000003F0000003F0000003F0000003F0000003F),
.INIT_43(256'hFFFF803FFFFF003FFFFC003FFFF0003FFFE0003FFF80003FFF00003FFC00003F),
.INIT_44(256'hFFE0003FFFF8003FFFFC003FFFFF003FFFFF803FFFFF803FFFFF803FFFFF803F),
.INIT_45(256'h0000003F0000003F0000003FC000003FF000003FFC00003FFF00003FFF80003F),
.INIT_46(256'h000000000000000000000000000000000000003F0000003F0000003F0000003F),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized13
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000CCCCCCCCCDDDCCCCCCCCCDDDDDD0000000000000000000000000),
.INITP_01(256'h066EEEEEEAAAAEEEE22000000000000000000000000000000000000000000000),
.INITP_02(256'h000000002200000000000000EE00000000000AA88CCCCCCCCCC88AA000000000),
.INITP_03(256'h6777766CC0000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h000088CC00000000000000000000000000000000000000000000000CC6666666),
.INITP_05(256'h000000000000000000000000000FFEEEE666666EECC880000000000000CC4400),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000111111111111110000000000222222200),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h81F07E0F81F00FFE81F00FFE81F00FFEFF8001F0FF8001F0FF8001F000000000),
.INIT_04(256'h81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F),
.INIT_05(256'h81F07E0F81F07E0F81F07E0F81F07E0F81F07E0F81F07FFF81F07FFF81F07FFF),
.INIT_06(256'h00000000000000000000000000000000FF807E0FFF807E0FFF807E0F81F07E0F),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000001E0000001E0000001E0000001E0000001E0000001E0000001F0000001F),
.INIT_0B(256'h0000001E0000001E0000001E0000001E0000001E0000001E0000001E0000001E),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000001F0000001F),
.INIT_0D(256'hC387001EFF07FF1EFF07FF1E0000000000000000000000000000000000000000),
.INIT_0E(256'hCF87001EC007FC1EC007FC1EC007001EC007001EC387001EC387001EC387001E),
.INIT_0F(256'h00000000FF87FF1FFF87FF1FC387001EC387001EC387001EC387001ECF87001E),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'hC380F01EC380F01FC380F01FCF00F01ECF00F01EFC01FC1EFC01FC1E00000000),
.INIT_12(256'hCF00F01EC380F01EC380F01EC380F01EC380F01EC380F01EC380F01EC380F01E),
.INIT_13(256'h0000000000000000000000000000000000000000FC01FC1EFC01FC1ECF00F01E),
.INIT_14(256'hFF81FC07FF81FC07000000000000000000000000000000000000000000000000),
.INIT_15(256'h3C00F0013C00F0013C00F0073C00F0073C00F01E3C00F01E3C00F01E3C00F01E),
.INIT_16(256'h3C01FC073C01FC073C00F01E3C00F01E3C00F0003C00F0003C00F0003C00F000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h00FE0F0700000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h03870F7F03870FE703870FE703870F8703870F8703870F0703870F0700FE0F07),
.INIT_20(256'h00FE0F0703870F0703870F0703870F0703870F0703870F1F03870F1F03870F7F),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000FE0F07),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'hFF000001FF000001000000000000000000000000000000000000000000000000),
.INIT_27(256'h3C00001E3C00001EF000001EF000001EC000001EC000001EC3800007C3800007),
.INIT_28(256'hFF00001EFF00001EC380001EC380001E0380001E0380001E0F00001F0F00001F),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'hC3870F00C0FE0F00C0FE0F0000780F0000780F00000000000000000000000000),
.INIT_2B(256'hC3870F0003FF0F0003FF0F0003870F0003870F0003870F0003870F00C3870F00),
.INIT_2C(256'h00000000000000000000000003870FFE03870FFEC3870F00C3870F00C3870F00),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000F0000000F0000001F0000001E0000001E0000001E0000000000000000000),
.INIT_39(256'h00003E0000003E0000007C0000007C0000007C000000F8000000F8000000F800),
.INIT_3A(256'h0000078000000F8000000F0000000F0000001F0000001F0000001F0000003F00),
.INIT_3B(256'h000000F3000001E1000001E1000001E1000003C0000003C0000003C000000780),
.INIT_3C(256'h0000003F0000007F0000007F0000007F000000FF000000FF000000FB000000F3),
.INIT_3D(256'h000000000000000000000000000000000000000000000000000000000000003F),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000007F0000007F0000007F0000007E0000007C000000400000000000000000),
.INIT_43(256'h0000007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F),
.INIT_44(256'h0000007F0000007F0000007F0000007F0000007F0000007F0000007F0000007F),
.INIT_45(256'h0000007C0000007F0000007F0000007F0000007F0000007F0000007F0000007F),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000040),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized14
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000004444444446666664444444446660000000000000000000000000),
.INITP_01(256'h0000000551100004444000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000011111111551111115500000000000000000000000000000000000000),
.INITP_03(256'h0000022220000000000000000000000000000000000000000000000000000000),
.INITP_04(256'hCCCCDDDDDD000000000000000000000000000000000000000000000222200000),
.INITP_05(256'h0000000000000000000000000002233333333BBBB332200000000000DDDDDDCC),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h01F07E0F01F07E0F01F07E0F01F07E0F01FFF00101FFF00101FFF00100000000),
.INIT_04(256'h01FFF00F01FFF00F01FFF00F01F07E0F01F07E0F01F07E0F01F07E0F01F07E0F),
.INIT_05(256'h01F07E0F01F07E0F01F07E0F01F07E0F01F07E0F01F1F00F01F1F00F01F1F00F),
.INIT_06(256'h0000000000000000000000000000000001F07E0101F07E0101F07E0101F07E0F),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0FE0F0790380F0780380F0780000000000000000000000000000000000000000),
.INIT_0E(256'h3FF8F0F93C78F3F93C78F3F93C78FF793C78FF793C78FC793C78FC790FE0F079),
.INIT_0F(256'h000000003C78F0783C78F0783C78F0793C78F0793C78F0793C78F0793FF8F0F9),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000100000001000000010000000100000001000000010000000100000000),
.INIT_12(256'h0000000100000001000000010000000100000001000000010000000100000001),
.INIT_13(256'h0000000000000000000000000000000000000000000000010000000100000001),
.INIT_14(256'h3FF83F813FF83F81000000000000000000000000000000000000000000000000),
.INIT_15(256'h3FE0F0E03FE0F0E03C00F0E03C00F0E03C00F0E03C00F0E03C00F0E03C00F0E0),
.INIT_16(256'h3C003F803C003F803C00F0E03C00F0E03C00F0E03C00F0E03C00F0E03C00F0E0),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h007F007F00000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0078F01E0078F01E0078F01E0078F01E0078F01E0079C01E0079C01E007F007F),
.INIT_20(256'h007F007F0079C01E0079C01E0078F01E0078F01E0078F01E0078F01E0078F01E),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000007F007F),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0FE03F800FE03F80000000000000000000000000000000000000000000000000),
.INIT_27(256'h0380F0000380F0000380F0000380F0000380F0E10380F0E10380F0E10380F0E1),
.INIT_28(256'h0FE03F800FE03F800380F0E10380F0E10380F0E00380F0E00380F0000380F000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0F0700E10F0700E10F0700E10F1FC07F0F1FC07F000000000000000000000000),
.INIT_2B(256'h0F0700E13F0700E03F0700E0FF0700E0FF0700E0CF0700E0CF0700E00F0700E1),
.INIT_2C(256'h0000000000000000000000000F1FC07F0F1FC07F0F0700E10F0700E10F0700E1),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized15
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000001111111110000000000000000000000000000),
.INITP_01(256'h0111100000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h8CCCCCC880000000000000000000000000000000000000000000000000000000),
.INITP_04(256'hEEFFFFEECC000000000000000000000000000000000000000000000CCCCCC888),
.INITP_05(256'h00000000000000000000000000022EEEEAAAAAAEEEE2200000000000CCEEEEEE),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000000000000000000000444C0000000080000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h000001FE000001F0000001F0000001F00000007E0000007E0000007E00000000),
.INIT_04(256'h000000000000000000000000000001FE000001FE000001FE000001FE000001FE),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h00000F1E00000F1E00000F1E0000000000000000000000000000000000000000),
.INIT_0E(256'h00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E),
.INIT_0F(256'h00000000000000E0000000E0000003F8000003F800000F1E00000F1E00000F1E),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'hFF00000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'hFF000000C3800000C3800000C3800000C3800000C3800000C3800000FF000000),
.INIT_20(256'hC380FC00C380FC00C380FC00C3800000C3800000CF000000CF000000FF000000),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000C380FC00),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h00FE0F0700FE0F07000000000000000000000000000000000000000000000000),
.INIT_27(256'h03870F7F03870F7FC3870FE7C3870FE7C3870F87C3870F87C3870F07C3870F07),
.INIT_28(256'hC0FE0F07C0FE0F07C3870F07C3870F07C3870F07C3870F0703870F1F03870F1F),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'hC3870F1FC3870F1EC3870F1EFF070F1EFF070F1E000000000000000000000000),
.INIT_2B(256'hC3870F1EC0070F1EC0070F1EC007FF1EC007FF1EC0070F1FC0070F1FC3870F1F),
.INIT_2C(256'h000000000000000000000000FF070F1EFF070F1EC3870F1EC3870F1EC3870F1E),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000800000000000000000000000),
.INIT_3A(256'h0F00000019000000190000001900000099000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000006000000060000000600000006000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized16
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h1111111000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h33333333BB000000000000000000000000000000000000000000000001111111),
.INITP_05(256'h00000000000000000000000000055444444554444445500000000000BB333333),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h000000000000000000FEEEFEEEF000000000FDDDFFDDF00000000E8898889F00),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000FF0100000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000F0E10000F0E10000F0E10000F0E10000F0E10000F3810000F3810000FF01),
.INIT_20(256'h0000FF010000F3810000F3810000F0E10000F0E10000F0E10000F0E10000F0E1),
.INIT_21(256'h000000000000000000000000000000000000000000000000000000000000FF01),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'hF07FF0FFF07FF0FF000000000000000000000000000000000000000000000000),
.INIT_27(256'h000700FF000700FF000700E1000700E13C0700E13C0700E13C0700E13C0700E1),
.INIT_28(256'hF00700E1F00700E13C0700E13C0700E13C0700E13C0700E1000700E7000700E7),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0380F0010380F0010380F0013FF8FFE03FF8FFE0000000000000000000000000),
.INIT_2B(256'h0380F0010380F0010380F0010380FF810380FF810380F0010380F0010380F001),
.INIT_2C(256'h0000000000000000000000000380FFE00380FFE00380F0010380F0010380F001),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h9CC307CCBCC306CCECC306CCCCC366CC8CC3638C8CE1C10C0000000000000000),
.INIT_39(256'h00000000000000000000000000000000000000008CE1C6CF8CC366CC8CC366CC),
.INIT_3A(256'hF1E08103813101038133010381336103F9E1C38F000000000000000000000000),
.INIT_3B(256'h00000000000000000000000000000000F931C38381336103813061038160C103),
.INIT_3C(256'h9900860099008600F1F3E7C00000000000000000000000000000000000000000),
.INIT_3D(256'h000000000000000099F087C09900860099008600B1008600F1E0878099008600),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized17
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'hAAAAAAAAAA000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h00000000000000000000000000000000000000000000000000000000EEAAAAAA),
.INITP_06(256'h0000000000088888888800000000088888888888000000000000000000000000),
.INITP_07(256'h0000000000000000000444444400000000002666666660000000000000000400),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'hC007FF07C007FF07000000000000000000000000000000000000000000000000),
.INIT_27(256'hC007FC1EC007FC1EC007001EC007001EC007001EC007001EC007001EC007001E),
.INIT_28(256'hFF87FF07FF87FF07C007001EC007001EC007001EC007001EC007001EC007001E),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h40000000C0000000C00000008000000000000000000000000000000000000000),
.INIT_34(256'hC0000000C0000000C0000000C000000040000000400000004000000040000000),
.INIT_35(256'h8000000080000000800000008000000080000000C0000000C0000000C0000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h063060CC063E60FC063060CC063066CC063066CC1F3F3CCC0000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000063F3CCC063066CC063066CC),
.INIT_3A(256'h193718CC193D18CC193918CC193118CC19313CCC000000000000000000000000),
.INIT_3B(256'h000000000000000000000000000000000F313C3019311878193118CC193318CC),
.INIT_3C(256'h193000CC193000CC0F3F00780000000000000000000000000000000000000000),
.INIT_3D(256'h00000000000000000F300078193000CC193000CC193000C0193E00C0193000C0),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized18
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h1100000011000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000EEE000000000000000000000000000000000000000000000011000000),
.INITP_06(256'hBFFFECCCCFFF33000008BB3BBB11110000000000000000001110000000000000),
.INITP_07(256'h000000000000000000EEE44446EEEE440001119998999899999998999899999B),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000FFE10000FFE1000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000FF810000FF810000F0010000F0010000F0010000F0010000F0010000F001),
.INIT_28(256'h0000FFE10000FFE10000F0010000F0010000F0010000F0010000F0010000F001),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'hFFFFFC00FFFFFC00000000000000000000000000000000000000000000000000),
.INIT_2F(256'h00001C0000001C0000001C0000001C0000001C0000001C0000001C00FFFFFC00),
.INIT_30(256'h00001C0000001C0000001C0000001C0000001C0000001C0000001C0000001C00),
.INIT_31(256'h00001BC000001B8000001B8000001300000033000000370000001E0000001E00),
.INIT_32(256'h000033CF000013CE000013CC00001BCC00001BF800001BF800001BF000001BC0),
.INIT_33(256'h000066D9000066D9000062D9000033D9000033C9000033CD000033CD000033CF),
.INIT_34(256'hE0008D3380008CB30000CC930000CC9B0000CE9B0000E69900006699000066D9),
.INIT_35(256'h700666CC6006666EF8033366FC033366FC0333668C0119367C011933F8009933),
.INIT_36(256'hFFE37336FFF33133FFF13933FB19999B07189C990E1C8C9D1C0CCCCD380EE6CD),
.INIT_37(256'hFF0DBF30FF3FFF98FF37F898FFBFACDCFFBDCCCCFFFCC6ECFFE6E666FFE66366),
.INIT_38(256'hF4F000F0FCF003F0FC6003F0FC600DF0FCE48EF0FEC6E7E0FE07F3E0FE033DF0),
.INIT_39(256'hE3700330E37000F0E33001F0F6F000F0F6F000C0F6F000E0F6300070F4E001B0),
.INIT_3A(256'hFE3007C0FE3006C0F63000E0F33003F0F33003B0F3380370F33801F0F37803F0),
.INIT_3B(256'h3F007E003F0006007E0003007EC00700FEE00F00FCE01C80FC600100FEF00780),
.INIT_3C(256'h3FFE1C007BE7DC00E3E7FC00C7C7DC008FC0FC00CF80FC00FF003C007F007C00),
.INIT_3D(256'h0000000000000000FFFFFC00FFFFFC00DFFFFC0005F01C0003F81C000FFC1C00),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized19
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'hFC66AAED5DCAEE6640888CCC44400888888888CCCCCCC4444444000000000000),
.INITP_06(256'h777FFF7B9991AAACDD54011011100444066626FF177677CD9B3759886EEE4DBF),
.INITP_07(256'h000000000000000000FFFFFDCEEFD7766644444667755DD7FFC44554CCCEADDD),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h3C8000000C8000000F0000000700000000000000000000000000000000000000),
.INIT_2A(256'hCC800000CC800000CC800000CC800000C8800000C8800000E880000078800000),
.INIT_2B(256'hB660000066C0000066C0000066C000006CC000006CC000006C800000CC800000),
.INIT_2C(256'h6D180000D9180000D9380000DB300000DB300000B3600000B3600000B7600000),
.INIT_2D(256'hCD630000DB630000DB670000BBC60000B6C6000036CC00006C8C00006C980000),
.INIT_2E(256'hCDB67FFFD9667FFF9B6CC00033CCC00037D880006698800066B10000ED310000),
.INIT_2F(256'h7C9F7F007DBBFF00D936DE00FB6E8C00B36D9C00E6D9180066DB3000CCB33FFF),
.INIT_30(256'hF8DC8770B898E6607939E6607F316EC0CFF3D8C0DFF3D880BFF6F180B6FFF100),
.INIT_31(256'h3878E08C1C77E0DC0F3F81D867FF0118E3FE0198CCE003B8CC8C0330FCCC0330),
.INIT_32(256'hFF8E60D8F7E3F0D8CBFFF8CCDFFFB8CCC1BD788CE08578CCE8DE38CCF8FF70CC),
.INIT_33(256'h236F001806FF001806DF0018068C8018040880D8000780D8898FC0D8FF8FE0D8),
.INIT_34(256'h06007FFF06003FFF0C000FFE0C00000C0C70000C1FF800183FF80018337C0018),
.INIT_35(256'h0080031F008001FF010000FF010000FE03007EFF0F007FBF0F007FBE06006000),
.INIT_36(256'hFE00FFFFFC001FFFF80007FF706001FFE0FFF07FE0FFFC07C0CFFE078080071F),
.INIT_37(256'h7FFFFFFF3FFFFFFF3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF03FFFF),
.INIT_38(256'h01C00E3701C03C3780E0FC33C0F1F833E0FBDC63F8FFEFE3FCFE7FC3FFF4FF83),
.INIT_39(256'hE7FF0F87E7FF0FC7E7FC07C7770006E73E0006E7188006E7088006B700C00637),
.INIT_3A(256'h07EC80C00FED00813FED0081BFE70083F7E70103E7E70103E7E3030307E20303),
.INIT_3B(256'h0FE08E1C0FE0CC180FF0DC300FF078301FF870601FF8E0601FF8C0E00FF880C0),
.INIT_3C(256'hDFF0FC609FF0E0C0DFF180C0DFE300C1DFE30083DFE10187CFE1030E0FE1070C),
.INIT_3D(256'h0000000000000000FFFFFFFFFFFFFFFFFFFFFFFFBFFFC19FFFFF0FBC7FF83F70),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized2
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h88888888CC000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h00000000000000000000000000000000000000000000000000000000CC8888CC),
.INITP_06(256'hF00000000000000000A222200000000006666666660000000000000000000000),
.INITP_07(256'h00000000000000000008991119BB5FFF00FFFFFFFDDDDDDDDDDDDDDDDDDD00FF),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0FE000000FE00000000000000000000000000000000000000000000000000000),
.INIT_27(256'h3C0000003C0000003C0000003C0000003C7800003C7800003C7800003C780000),
.INIT_28(256'h0FF800000FF800003C7800003C7800003C7800003C7800003CF800003CF80000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h30816006FCF9C003000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000030F9C00330816006308130063081300630F130063081300630813006),
.INIT_34(256'h001E3C7C00000000000000000000000000000000000000000000000000000000),
.INIT_35(256'hC01E3C66C01B3666E0193366C019336CC019337CC0193366C0193366001B3666),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'hFFFFFFFF00000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h83F801FF83F801FF83F801FF83F801FF0000000000000000FFFFFFFFFFFFFFFF),
.INIT_39(256'h83F801FF83F801FF83F801F883F801F883F801F883F801FF83F801FF83F801FF),
.INIT_3A(256'h83FFF1FF83F801F883F801F883F801FC83F801FF83F801FF83F801FF83F801FF),
.INIT_3B(256'h000000000000000083FFF1FF83FFF1FF83FFF1FF83FFF1FF83FFF1FF83FFF1FF),
.INIT_3C(256'h60063FCFE0063FCCC03FB0CF803FB08F7FC06F78FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3D(256'h00000000000000000000000000001007C00638CFE00638CFE00630CC60063FCF),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized20
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000011333110111110000000000000000000000000000000000000000000000),
.INITP_06(256'h2333333333310111111000000000000223111111100000000000000000000000),
.INITP_07(256'h0000000000000000003333333333333333323332221112322310002333233132),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000700000003000000010000000100000000000000000000000000000000),
.INIT_2B(256'h0000003600000036000000370000003D0000001D0000000D0000000D00000007),
.INIT_2C(256'h0000007B0000007B0000007B0000007300000033000000360000003600000036),
.INIT_2D(256'h000000FF000000FE000000DE00000076000000FC000000FD000000FD00000079),
.INIT_2E(256'h00FFFF6B00FFFF5B000000DE000000F7000000F7000000BD000000AF000000EB),
.INIT_2F(256'h00C0007D00C0006D00C0007B00C000DB00C000F600C000B600C000BD00FFFFED),
.INIT_30(256'h00C0000300C0000700C0000700C0000D00C0000F00C0001B00C0003E00C00037),
.INIT_31(256'h00C0000100C0000100C0000300C0000300C0000300C0000600C0000700C00003),
.INIT_32(256'h00C000FF00C0003C00C0000000C0000000C0000000C0000000C0000000C00000),
.INIT_33(256'h00C18F0000C0CF0000C0E78000C07BE000C03DFC00C01FFF00C007EF00C001FF),
.INIT_34(256'h00DB780000CF780000CF780000CF780000C6380000C7780000C37C0000C13E00),
.INIT_35(256'h00FC0FFF00FC2FC700FD7F0F00FF7E0F00FF7C0E00FF7C0E00DB581C00DB7838),
.INIT_36(256'h00E7FCFD00E5FFB700E73FFA00E601FF00EE003F00EE01FF00FE03FF00FC07FF),
.INIT_37(256'h00F77E0000EF0F8000FF83FC00FF8CFF00FF0F1F00FCFFEC00E3FFF600E7FFBB),
.INIT_38(256'h00DFE3E700DFF1E300DFF83900DBFC9E00DB6FDF00F807F700F3E3FF00F7F8FF),
.INIT_39(256'h00FFC37F00FF63FF00FE73FF00FC38FE00F4983700F0CC1B00FBCE0000FF6706),
.INIT_3A(256'h00C1F80000C3F91800CF311800DF317B00FF0F7F00F00FFF00E686FF00EFC006),
.INIT_3B(256'h00C7FFBF00C7FF3C00C3FF1800C3FF0000C3FE0000C3FD0000C1FB0000C1E600),
.INIT_3C(256'h00DFFFFF00DFFFFF00CFFFFE00CFFFF900CFFFF100C7FFF600C7FFFF00C7FFCF),
.INIT_3D(256'h000000000000000000FFFFFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF00FFFFFF),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized21
(douta,
clka,
addra);
output [25:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [25:0]douta;
wire \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[25:20],\n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[19:13],\n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[12:7],\n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,douta[6:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,\n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized3
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h88999988CC000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h00000000000000000000000000000000000000000000000000000000CC888888),
.INITP_06(256'hF00000000000000022000666600000000E222622260000000000000000000000),
.INITP_07(256'h00000000000000000000BB333375EFFF006666666602AAAAAA026666666400FF),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h00FE0F0700FE0F07000000000000000000000000000000000000000000000000),
.INIT_27(256'h00780F7F00780F7FC0780FE7C0780FE7C0780F87C0780F87C0780F07C0780F07),
.INIT_28(256'hC0FE0F07C0FE0F07C0780F07C0780F07C0780F07C0780F0700780F1F00780F1F),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0C18B0630F98BF63000000000000000000000000000000000000000000000000),
.INIT_33(256'h00000000CF98BF630C18B0630C18B0630C1AB0670F1ABE6F0C1AB07B0C1DB073),
.INIT_34(256'hCC98E00300000000000000000000000000000000000000000000000000000000),
.INIT_35(256'hCC60E000CC613000CC6030075860600630F0C0033098800368990003CC993003),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'hFFFFFFFF00000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h1FFFF03F0FFFE03F03FF803F00FF001F0000000000000000FFFFFFFFFFFFFFFF),
.INIT_39(256'hFE3FFE3FFE1FFC3FFF00003FFF01C03FFF83F03F7FFFF83F7FFFF83F3FFFF83F),
.INIT_3A(256'h7F83FC3FFF00FC3FFF00FE3FFE3FFE3FFE3FFE3FFE3FFE3FFE3FFE3FFE3FFE3F),
.INIT_3B(256'h000000000038000001FF001F07FFC03F0FFFE03F1FFFF03F3FFFF83F7FFFF83F),
.INIT_3C(256'h1EE09F8C3FF19E8C777F1C8F633F188FDCCCE770FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3D(256'h000000000000000000000000000E00070C3F188F0C7F998F0CE19B8C0CC09B8C),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized4
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h4000000440000000000000000000000000000000000000000000000000000000),
.INITP_04(256'hBB111111BB000000000000000000000000000000000000000000000440000444),
.INITP_05(256'h00000000000000000000000000055444444554444445500000000000BB111111),
.INITP_06(256'hF000000000000000111111111000000002222322230000000000000000000000),
.INITP_07(256'h0000000000000000000022222222FFFF00DDDDDDFFBBBBBBBBBBFDDDDDD900FF),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0FE0000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h038000000F0000000F0000003C0000003C0000003C7800003C7800000FE00000),
.INIT_20(256'h0FE000003C7800003C780000007800000078000000E0000000E0000003800000),
.INIT_21(256'h000000000000000000000000000000000000000000000000000000000FE00000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'hFC7FF0FFFC7FF0FF000000000000000000000000000000000000000000000000),
.INIT_27(256'hF07FC0FFF07FC0FF007800E1007800E1007800E1007800E1007800E1007800E1),
.INIT_28(256'hFC7FF0E1FC7FF0E1007800E1007800E1007800E1007800E1007800E7007800E7),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0380F0000380F0000380F0003FF8FFE03FF8FFE0000000000000000000000000),
.INIT_2B(256'h0380F0000380F0000380F0000380FF800380FF800380F0000380F0000380F000),
.INIT_2C(256'h0000000000000000000000000380FFE00380FFE00380F0000380F0000380F000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h00611B6600F11BC6000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000F11B0700611B0600611B0600615B0600615BC600615B660061BB66),
.INIT_34(256'h0000317E00000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000317E0000316000003160000033600000377C00003D600000396000003160),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'hFFFFFFFF00000000000000000000000000000000000000000000000000000000),
.INIT_38(256'hFFFC07F0FFF807F0FFE007F0FF0003F00000000000000000FFFFFFFFFFFFFFFF),
.INIT_39(256'hF03F87F0F03F87F0F03F87F0F0FF07F0F3FF07F0FFFF07F0FFFF07F0FFFE07F0),
.INIT_3A(256'hFFFF07F0F0FF07F0F07F07F0F03F87F0F03F87F0F03F87F0F03F87F0F03F87F0),
.INIT_3B(256'h0000000000000000FF8003F0FFF007F0FFF807F0FFFC07F0FFFE07F0FFFF07F0),
.INIT_3C(256'h0000FE7E0000FE600000FE7F0000FC7FFFFF0380FFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_3D(256'h0000000000000000000000000000F83F0000FE7F0000FE7F000086600000FE7E),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized5
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000004444444440000000000000000000000000),
.INITP_01(256'h000CC4400000088CC00000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h8888888770000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h3333333333000000000000000000000000000000000000000000000998888888),
.INITP_05(256'h000000000000000000000000000FFEEEE445566EEEEDD0000000000033333333),
.INITP_06(256'h3444CCC880000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h000000000000000000FFF000FFF000EEED11137764CCC88882222666C8800033),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0F8000007F8000007F8000007F8000007F8000007F8000007F80000000000000),
.INIT_04(256'h0000000000000000000000007E0000007E0000007E0000000F8000000F800000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'hC3800000FF000000FF0000000000000000000000000000000000000000000000),
.INIT_0E(256'h0F0000003C0000003C000000F0000000F0000000C0000000C0000000C3800000),
.INIT_0F(256'h00000000FF000000FF000000C3800000C380000003800000038000000F000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h03FF03F800000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'hC0780F1EC0780F1EC0780F1EC0780F1EC0780F1E00780F1E00780F1E03FF03F8),
.INIT_20(256'hC07803F8C0780F1EC0780F1EC0780F1EC0780F1EC0780F1EC0780F1EC0780F1E),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000C07803F8),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'hFF07039FFF07039F000000000000000000000000000000000000000000000000),
.INIT_27(256'h3C073F9F3C073F9F3C07F39E3C07F39E3C07C39E3C07C39E3C07039E3C07039E),
.INIT_28(256'hFF07039FFF07039F3C07039E3C07039E3C07039E3C07039E3C070F9E3C070F9E),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'hC3870F00C3870F00C3870F0003FE0FFE03FE0FFE000000000000000000000000),
.INIT_2B(256'hC3870F00039E0F00039E0F0003FE0FF803FE0FF803870F0003870F00C3870F00),
.INIT_2C(256'h00000000000000000000000003870FFE03870FFEC3870F00C3870F00C3870F00),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'hFF00000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h30FFFFFF70E0000061C00000E1C00000C3800000FF800000FF000000FF000000),
.INIT_38(256'hC30F0003830E0003871E0003063C00030E3C00000C7800001C7FFFFF38FFFFFF),
.INIT_39(256'hFE30F003FC70E003F860C00378E1C00370C3800370C3800361870003E1870003),
.INIT_3A(256'h01C30F0301C30F0303871E0307061C03870E3C038F0C3803CF1C7803DE38F003),
.INIT_3B(256'hFFFFF8F0FFFC70E0003C60E30078E1C300F0C18300F0C38300E0830300E10703),
.INIT_3C(256'hFFFFFFFEFFFFFFFEFFFFFFFE0000001E0000003F0000003FFFFFF07FFFFFF87F),
.INIT_3D(256'h0000000000000000FFFFFFF0FFFFFFF8FFFFFFF80000003C0000001C0000001E),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized6
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000CCC444444666666444444444EEE0000000000000000000000000),
.INITP_01(256'h0551111111111111111000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000044115555111100004400000000000000000000000000000000000000),
.INITP_03(256'hBBBBB88880000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h44441111110000000000000000000000000000000000000000000009999BBBBB),
.INITP_05(256'h0000000000000000000000000000011111199111111880000000000011111111),
.INITP_06(256'h7000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000003330445776655511000022233330000000011111110077),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h01F07E0001F07E0001F07E0001F07E0081FFF00081FFF00081FFF00000000000),
.INIT_04(256'h01FFF00001FFF00001FFF00001F07E0001F07E0001F07E0001F07E0001F07E00),
.INIT_05(256'h01F07E0001F07E0001F07E0001F07E0001F07E0001F1F00001F1F00001F1F000),
.INIT_06(256'h0000000000000000000000000000000081F07E0081F07E0081F07E0001F07E00),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h3C00F0E13C003F803C003F800000000000000000000000000000000000000000),
.INIT_0E(256'h3C00F0E03C00F0E03C00F0E03C00F0E03C00F0E03C00F0E13C00F0E13C00F0E1),
.INIT_0F(256'h000000003FF83F803FF83F803C00F0E13C00F0E13C00F0E03C00F0E03C00F0E0),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h03F83C0003F83C00000000000000000000000000000000000000000000000000),
.INIT_15(256'h0F1E03800F1E03800F7E03800F7E03800F7E0F000F7E0F000F1E0F000F1E0F00),
.INIT_16(256'h03F80F0003F80F000F1E03800F1E03800F9E03800F9E03800F9E03800F9E0380),
.INIT_17(256'h0000000000000000000000000000000000003C0000003C0000000F0000000F00),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'hF078F01E00000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'hC07F00E1C079C0E1C079C0E1C079C0E1C079C0E1C078F07FC078F07FF078F01E),
.INIT_20(256'hF078F0E1C078F0E1C078F0E1C079C0E1C079C0E1C079C0FFC079C0FFC07F00E1),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000F078F0E1),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h3C1E3F803C1E3F80000000000000000000000000000000000000000000000000),
.INIT_27(256'h3CFEF0003CFEF0003F9EF0003F9EF0003F1EF0E03F1EF0E03C1EF0E03C1EF0E0),
.INIT_28(256'h3C1E3FE03C1E3FE03C1EF0E03C1EF0E03C1EF0E03C1EF0E03C7EF3E03C7EF3E0),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h000000E1000000E1000000E1FC00007FFC00007F000000000000000000000000),
.INIT_2B(256'h000000E1000000E0000000E0F00000E0F00000E0000000E0000000E0000000E1),
.INIT_2C(256'h0000000000000000000000000000007F0000007F000000E1000000E1000000E1),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000100000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h07FFFFFC0000003C0000001E0000000F0000000F000000070000000700000003),
.INIT_38(256'h18000383180001C1180001C1180000E01C0000F01E0000F01FFFFFF80FFFFFF8),
.INIT_39(256'h18003C3018003C3818001E1818001E1C18000F0C180007061800070718000383),
.INIT_3A(256'h1803831E1801C10F1801C1871800E0871800E0C31800F0C31800786118007870),
.INIT_3B(256'h1C7C70FF1C3C30FF181E38F0181E1C78180F0C78180F0E3C1807063C1803871E),
.INIT_3C(256'h01C307FF01C30FFF01C10FFF00E1860001E0C70007F0C3000FF0E1FF1FF861FF),
.INIT_3D(256'h0000000000000000007FFFFF007FFFFF00FFFFFF00FE000000E6000001C70000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized7
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000999888888888DDDCCCCCCCCCDDD0000000000000000000000000),
.INITP_01(256'h055666666EEEEEEEECC000000000000000000088888888880000000000000000),
.INITP_02(256'h0000000099990000000044000000000000000FF6666667777664499000000000),
.INITP_03(256'hCCCCC00220000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h9988888899000000000000000000000000000000000000000000000CCCCCCCCC),
.INITP_05(256'h0000000000000000000000000002222222222222222220000000000099888888),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000000000000000000000000000000088888CCCC8880),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h81F07E0081F07E0081F07E0081F07E00FF807FFFFF807FFFFF807FFF00000000),
.INIT_04(256'hFF807FFEFF807FFEFF807FFE81F07E0081F07E0081F07E0081F07E0081F07E00),
.INIT_05(256'h80007E0080007E0080007E0080007E0080007E0080007E0080007E0080007E00),
.INIT_06(256'h0000000000000000000000000000000080007FFF80007FFF80007FFF80007E00),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'hC0000000C0000000C0000000C0000000C0000000C0000000C0000000C0000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'hC3870F1E00FE0F1E00FE0F1E0000000000000000000000000000000000000000),
.INIT_0E(256'h03870F1E03870F1E03870F1EC3870F1EC3870F1EC3870F1EC3870F1EC3870F1E),
.INIT_0F(256'h0000000000FE03F800FE03F803870F1E03870F1E03870F1E03870F1E03870F1E),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0387038003870F0003870F0000FE0F1E00FE0F1E007803F8007803F800000000),
.INIT_12(256'h03870F1E0387001E0387001E03FF007803FF0078038700E0038700E003870380),
.INIT_13(256'h0000000000000000000000000000000000000000038703F8038703F803870F1E),
.INIT_14(256'h001E0000001E0000000000000000000000000000000000000000000000000000),
.INIT_15(256'h001E0000001E0000001E0000001E000003FE000003FE0000007E0000007E0000),
.INIT_16(256'h001E00F8001E00F8001E00F8001E00F8001E0000001E0000001E0000001E0000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h3C07FF0700000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'hC380F001C380F001C380F001C380F001C380F001FF00F001FF00F0013C07FF07),
.INIT_20(256'hC380F007C380F001C380F001C380F001C380F001FF80F001FF80F001C380F001),
.INIT_21(256'h00000000000000000000000000000000000000000000000000000000C380F007),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h00000FFE00000FFE000000000000000000000000000000000000000000000000),
.INIT_27(256'h00000FF800000FF8C0000F00C0000F00C0000F00C0000F00C0000F00C0000F00),
.INIT_28(256'hC0000FFEC0000FFEC0000F00C0000F00C0000F00C0000F0000000F0000000F00),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h00070F1E00070F1E00070F1E0001FC1F0001FC1F000000000000000000000000),
.INIT_2B(256'h00070F1E00070F1E00070F1E00070F1F00070F1F00070F1E00070F1E00070F1E),
.INIT_2C(256'h0000000000000000000000000001FC1E0001FC1E00070F1E00070F1E00070F1E),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'hFF000000FF800000FF800000FF000000FC000000E00000008000000000000000),
.INIT_39(256'h00000000000000000000000080000000E0000000F0000000FC000000FF000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized8
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000EEE444444444666444444444EEE0000000000000000000000000),
.INITP_01(256'h03311111199111111BB000000000002200000022111111330000000000000000),
.INITP_02(256'h00000088AAAA8888888888880000000000000AA0000222200000022000000000),
.INITP_03(256'h000110000000000000008800002222000000AA00000000000000000000000000),
.INITP_04(256'hBB999999BB000000000000000000044000000440000000000000000444400000),
.INITP_05(256'h00000000000000000000000000044444444555555555500000000000BB999999),
.INITP_06(256'h6733333333333333322222200000000000000000000000000000000000000000),
.INITP_07(256'h00000000000000000000000888880008888888888888888CCCCDDD7777777766),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h01F0000F01F0000F01F0000F01F0000F81FFFE0F81FFFE0F81FFFE0F00000000),
.INIT_04(256'h01FFF00F01FFF00F01FFF00F01F0000F01F0000F01F0000F01F0000F01F0000F),
.INIT_05(256'h01F0000F01F0000F01F0000F01F0000F01F0000F01F0000F01F0000F01F0000F),
.INIT_06(256'h0000000000000000000000000000000081FFFE0F81FFFE0F81FFFE0F01F0000F),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0078F0E10078F0E10078F0E10078F0E10078F0E10078F0E1007FC0E1007FC0E1),
.INIT_0B(256'h0078F01E0078F01E0078F01E0078F01E0078F01E0078F01E007FC07F007FC07F),
.INIT_0C(256'h000000000000000000000000000000000000000000000000007FC01E007FC01E),
.INIT_0D(256'h3C78F0E1F01FC0FFF01FC0FF0000000000000000000000000000000000000000),
.INIT_0E(256'hF078F0E0F078F0FFF078F0FF3C78F0E13C78F0E13C78F0E13C78F0E13C78F0E1),
.INIT_0F(256'h000000003C1FC0E03C1FC0E03C78F0E03C78F0E03C78F0E03C78F0E0F078F0E0),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h3C1E001E3C78001E3C78001E3C78F01E3C78F01E3C1FC07F3C1FC07F00000000),
.INIT_12(256'h3C78F01E3C00F01E3C00F01E3C01C01E3C01C01E3C07001E3C07001E3C1E001E),
.INIT_13(256'h0000000000000000000000000000000000000000F01FC07FF01FC07F3C78F01E),
.INIT_14(256'hF0000000F0000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0078F0000078F0000078F0000078F000C078F000C078F000C0000000C0000000),
.INIT_16(256'hC007001FC007001F001FC01F001FC01F0078F0000078F0000078F0000078F000),
.INIT_17(256'h00000000000000000000000000000000F0000000F0000000C0000000C0000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h3C78F0003C78F0003C78F0003C78F000F07FC000F07FC0000000000000000000),
.INIT_1C(256'h3C78F0003C78F0003C79C0003C79C0003C7FC0003C7FC0003C78F0003C78F000),
.INIT_1D(256'h00000000000000000000000000000000F078F000F078F0003C78F0003C78F000),
.INIT_1E(256'h3C78F07800000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h3C78F3793C78F3793C78F3793C78FCF93C78FCF93C78F0783C78F0783C78F078),
.INIT_20(256'h0380F0790FE0F0790FE0F0793C78F0793C78F0793C78F3793C78F3793C78F379),
.INIT_21(256'h000000000000000000000000000000000000000000000000000000000380F079),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h3C0000003C0000003C0000003C0000003C0000003FF800003FF8000000000000),
.INIT_24(256'h3C0000003C0000003C0000003C0000003C0000003FE000003FE000003C000000),
.INIT_25(256'h00000000000000000000000000000000000000003C0000003C0000003C000000),
.INIT_26(256'hFC7FF0FFFC7FF0FF000000000000000000000000000000000000000000000000),
.INIT_27(256'hC07FC0FFC07FC0FFC07800E1C07800E1C07800E1C07800E1C07800E1C07800E1),
.INIT_28(256'hC07FF0E1C07FF0E1C07800E1C07800E1C07800E1C07800E1C07800E7C07800E7),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0380F0E00380F0E00380F0E03FF8F0E03FF8F0E0000000000000000000000000),
.INIT_2B(256'h03800F0003800F0003800F0003803F8003803F800380F0E00380F0E00380F0E0),
.INIT_2C(256'h00000000000000000000000003800F0003800F0003800F0003800F0003800F00),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0003FF800003FF000003FE000003F8000007F0000007C0000007000000070000),
.INIT_36(256'h0001FFE00001FFF00001FFE00001FFE00001FFE00003FFE00003FFE00003FFC0),
.INIT_37(256'h01FF007800FF00F8007F03F8003F07F0001F1FF0000F3FF00007FFF00003FFF0),
.INIT_38(256'h0FFFFFFF0FFF7FFF0FFF1FFF0FFF07FF0FFF03FF0FFF00FF07FF007F03FF001E),
.INIT_39(256'h8F8000008FE0001C8FF000FF8FF801FF0FFC0FFF0FFE7FFF0FFFFFFF0FFFFFFF),
.INIT_3A(256'hC0000000C0000000C0000000C0000000CC000000CE000000CF000000CF000000),
.INIT_3B(256'h00000000800000008000000080000000C0000000C0000000C0000000C0000000),
.INIT_3C(256'hBE000000BE000000FE000000EE00000000000000000000000000000000000000),
.INIT_3D(256'h00000000000000000000000000000000000000000000000000000000FE000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module About_blk_mem_gen_prim_wrapper_init__parameterized9
(douta,
clka,
addra);
output [35:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [35:0]douta;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h000000000000DDDCCCCCC8889998888888889990000000000000000000000000),
.INITP_01(256'h0EE88888888888888EE00000000000EEAAAAAAAAAAAAAAEE0000000000000000),
.INITP_02(256'h0000000000CC4400000088CC0000000000000AAEEEEEEAAEEEEEEAA000000000),
.INITP_03(256'hFEEEEEEFF0000000000022220000002222222200000000000000000000000000),
.INITP_04(256'hAAEEEEEEAA00000000000990000000000000011000000000000000077666666F),
.INITP_05(256'h000000000000000000000000000DDFFBB9999DDDDFFDD00000000000AAAAAAAA),
.INITP_06(256'h0000000000000000888888888000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000033375444CCCCCCCC8888888CCCCCCCC4455733320),
.INITP_08(256'h000000000000AAAAAAAABBBB333333333333BBBBAAAAAAAA0000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h807E7E00807E7E00807E7E00807E7E00807E7FFF807E7FFF807E7FFF00000000),
.INIT_04(256'h8E7E7FFE8E7E7FFE8E7E7FFE8E7E7E008E7E7E008E7E7E00807E7E00807E7E00),
.INIT_05(256'hF1F07E00F1F07E00F1F07E00F1F07E00F1F07E008E7E7E008E7E7E008E7E7E00),
.INIT_06(256'h00000000000000000000000000000000F1F07FFFF1F07FFFF1F07FFFF1F07E00),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'hC0070F00C0070F00C0070F00C0070F00C0073C00C0073C00FF87F000FF87F000),
.INIT_0B(256'hC0073C00C0073C00C0070F00C0070F00C0070F00C0070F00FF070F00FF070F00),
.INIT_0C(256'h000000000000000000000000000000000000000000000000FF87F000FF87F000),
.INIT_0D(256'hC000F01EFF81FC1FFF81FC1F0000000000000000000000000000000000000000),
.INIT_0E(256'hC000F01EFF00F01FFF00F01FC000F01EC000F01EC000F01EC000F01EC000F01E),
.INIT_0F(256'h00000000FF81FC1EFF81FC1EC000F01EC000F01EC000F01EC000F01EC000F01E),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'hC3870F1EC3870F1EC3870F1EC3870F1EC3870F1EFF01FC1EFF01FC1E00000000),
.INIT_12(256'hC3870F1EC3870F1EC3870F1EC3870F1EC3870F1EFF070F1EFF070F1EC3870F1E),
.INIT_13(256'h0000000000000000000000000000000000000000FF01FC07FF01FC07C3870F1E),
.INIT_14(256'hFF000000FF000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h3C0000073C000007F0000007F0000007C0000001C0000001C3800001C3800001),
.INIT_16(256'hFF000001FF000001C3800007C380000703800007038000070F0000070F000007),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000100000001),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h3C07001E3C07001E3C070F1E3C070F1EFF01FC07FF01FC070000000000000000),
.INIT_1C(256'h3C000F1E3C000F1E3C003C1E3C003C1E3C00F01E3C00F01E3C01C01E3C01C01E),
.INIT_1D(256'h00000000000000000000000000000000FF01FC07FF01FC073C070F1E3C070F1E),
.INIT_1E(256'h0381CFFE00000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h039FCFF8C3F9CF00C3F9CF00C3E1CF00C3E1CF00C381CF00C381CF000381CFFE),
.INIT_20(256'h0381CFFE0381CF000381CF000381CF000381CF000387CF000387CF00039FCFF8),
.INIT_21(256'h000000000000000000000000000000000000000000000000000000000381CFFE),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h00000F1E00000F1E00000F1E00000F1E00000F1E000003F8000003F800000000),
.INIT_24(256'h00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E00000F1E),
.INIT_25(256'h0000000000000000000000000000000000000000C00003F8C00003F800000F1E),
.INIT_26(256'hFF070F1FFF070F1F000000000000000000000000000000000000000000000000),
.INIT_27(256'hFF070F01FF070F01C3870F01C3870F01C3870F01C3870F01C3870F01C3870F01),
.INIT_28(256'hC001FC01C001FC01C0070F01C0070F01C0070F01C0070F01C0070F01C0070F01),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'hC38000E0C38700E0C38700E000FE03F800FE03F8000000000000000000000000),
.INIT_2B(256'hC00700E0001E00E0001E00E0007800E0007800E0C0E000E0C0E000E0C38000E0),
.INIT_2C(256'h000000000000000000000000C0FE03F8C0FE03F8C38700E0C38700E0C00700E0),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h1800000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h1800000018000000180000003800000078000000D80000009800000018000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h01FC00FE01FF03FC00FFFFFC00FFFFF0003FFFE0000FFFC00003FF0000000000),
.INIT_39(256'hDF0000078F0000078F80000F8F80000F07C0000F07C0001F07E0003F03F0007F),
.INIT_3A(256'hDF000003DF000003DF000003DF000003DF000003DF000003DF000003DF000007),
.INIT_3B(256'h0780000F8F80000F8F0000078F000007DF000007DF000007DF000003DF000003),
.INIT_3C(256'h003FFFE000FFFFF800FFFFFD01FE01FF01F800FE03E0007F07E0003F07C0001F),
.INIT_3D(256'h00000000000000000000000000000000000000000000000000000000001FFFC0),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'hF83F80FFF83F80FFF83F80FFF83F80FF803F80FF803F80FF803F80FF803F80FF),
.INIT_43(256'h003F87F0003F87F0003F87F0003F87F0F83F87F0F83F87F0F83F87F0F83F87F0),
.INIT_44(256'h003F87F0003F87F0003F87F0003F87F0003FFF00003FFF00003FFF00003FFF00),
.INIT_45(256'hF83F80FFF83F80FFF83F80FFF83F80FFF83F87F0F83F87F0F83F87F0F83F87F0),
.INIT_46(256'h00000000000000000000000000000000803F80FF803F80FF803F80FF803F80FF),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({douta[34:27],douta[25:18],douta[16:9],douta[7:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({douta[35],douta[26],douta[17],douta[8]}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b0,1'b0,1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module About_blk_mem_gen_top
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
About_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "artix7" *) (* C_XDEVICEFAMILY = "artix7" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "3" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "1" *) (* C_INIT_FILE_NAME = "About.mif" *)
(* C_INIT_FILE = "About.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "800" *) (* C_READ_WIDTH_A = "800" *) (* C_WRITE_DEPTH_A = "600" *)
(* C_READ_DEPTH_A = "600" *) (* C_ADDRA_WIDTH = "10" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "800" *)
(* C_READ_WIDTH_B = "800" *) (* C_WRITE_DEPTH_B = "600" *) (* C_READ_DEPTH_B = "600" *)
(* C_ADDRB_WIDTH = "10" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) (* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "22" *)
(* C_COUNT_18K_BRAM = "1" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 60.4532 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module About_blk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [799:0]dina;
output [799:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [799:0]dinb;
output [799:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [799:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [799:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire [9:0]addrb;
wire clka;
wire clkb;
wire [799:0]dina;
wire [799:0]dinb;
wire [799:0]douta;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [799:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign doutb[799] = \<const0> ;
assign doutb[798] = \<const0> ;
assign doutb[797] = \<const0> ;
assign doutb[796] = \<const0> ;
assign doutb[795] = \<const0> ;
assign doutb[794] = \<const0> ;
assign doutb[793] = \<const0> ;
assign doutb[792] = \<const0> ;
assign doutb[791] = \<const0> ;
assign doutb[790] = \<const0> ;
assign doutb[789] = \<const0> ;
assign doutb[788] = \<const0> ;
assign doutb[787] = \<const0> ;
assign doutb[786] = \<const0> ;
assign doutb[785] = \<const0> ;
assign doutb[784] = \<const0> ;
assign doutb[783] = \<const0> ;
assign doutb[782] = \<const0> ;
assign doutb[781] = \<const0> ;
assign doutb[780] = \<const0> ;
assign doutb[779] = \<const0> ;
assign doutb[778] = \<const0> ;
assign doutb[777] = \<const0> ;
assign doutb[776] = \<const0> ;
assign doutb[775] = \<const0> ;
assign doutb[774] = \<const0> ;
assign doutb[773] = \<const0> ;
assign doutb[772] = \<const0> ;
assign doutb[771] = \<const0> ;
assign doutb[770] = \<const0> ;
assign doutb[769] = \<const0> ;
assign doutb[768] = \<const0> ;
assign doutb[767] = \<const0> ;
assign doutb[766] = \<const0> ;
assign doutb[765] = \<const0> ;
assign doutb[764] = \<const0> ;
assign doutb[763] = \<const0> ;
assign doutb[762] = \<const0> ;
assign doutb[761] = \<const0> ;
assign doutb[760] = \<const0> ;
assign doutb[759] = \<const0> ;
assign doutb[758] = \<const0> ;
assign doutb[757] = \<const0> ;
assign doutb[756] = \<const0> ;
assign doutb[755] = \<const0> ;
assign doutb[754] = \<const0> ;
assign doutb[753] = \<const0> ;
assign doutb[752] = \<const0> ;
assign doutb[751] = \<const0> ;
assign doutb[750] = \<const0> ;
assign doutb[749] = \<const0> ;
assign doutb[748] = \<const0> ;
assign doutb[747] = \<const0> ;
assign doutb[746] = \<const0> ;
assign doutb[745] = \<const0> ;
assign doutb[744] = \<const0> ;
assign doutb[743] = \<const0> ;
assign doutb[742] = \<const0> ;
assign doutb[741] = \<const0> ;
assign doutb[740] = \<const0> ;
assign doutb[739] = \<const0> ;
assign doutb[738] = \<const0> ;
assign doutb[737] = \<const0> ;
assign doutb[736] = \<const0> ;
assign doutb[735] = \<const0> ;
assign doutb[734] = \<const0> ;
assign doutb[733] = \<const0> ;
assign doutb[732] = \<const0> ;
assign doutb[731] = \<const0> ;
assign doutb[730] = \<const0> ;
assign doutb[729] = \<const0> ;
assign doutb[728] = \<const0> ;
assign doutb[727] = \<const0> ;
assign doutb[726] = \<const0> ;
assign doutb[725] = \<const0> ;
assign doutb[724] = \<const0> ;
assign doutb[723] = \<const0> ;
assign doutb[722] = \<const0> ;
assign doutb[721] = \<const0> ;
assign doutb[720] = \<const0> ;
assign doutb[719] = \<const0> ;
assign doutb[718] = \<const0> ;
assign doutb[717] = \<const0> ;
assign doutb[716] = \<const0> ;
assign doutb[715] = \<const0> ;
assign doutb[714] = \<const0> ;
assign doutb[713] = \<const0> ;
assign doutb[712] = \<const0> ;
assign doutb[711] = \<const0> ;
assign doutb[710] = \<const0> ;
assign doutb[709] = \<const0> ;
assign doutb[708] = \<const0> ;
assign doutb[707] = \<const0> ;
assign doutb[706] = \<const0> ;
assign doutb[705] = \<const0> ;
assign doutb[704] = \<const0> ;
assign doutb[703] = \<const0> ;
assign doutb[702] = \<const0> ;
assign doutb[701] = \<const0> ;
assign doutb[700] = \<const0> ;
assign doutb[699] = \<const0> ;
assign doutb[698] = \<const0> ;
assign doutb[697] = \<const0> ;
assign doutb[696] = \<const0> ;
assign doutb[695] = \<const0> ;
assign doutb[694] = \<const0> ;
assign doutb[693] = \<const0> ;
assign doutb[692] = \<const0> ;
assign doutb[691] = \<const0> ;
assign doutb[690] = \<const0> ;
assign doutb[689] = \<const0> ;
assign doutb[688] = \<const0> ;
assign doutb[687] = \<const0> ;
assign doutb[686] = \<const0> ;
assign doutb[685] = \<const0> ;
assign doutb[684] = \<const0> ;
assign doutb[683] = \<const0> ;
assign doutb[682] = \<const0> ;
assign doutb[681] = \<const0> ;
assign doutb[680] = \<const0> ;
assign doutb[679] = \<const0> ;
assign doutb[678] = \<const0> ;
assign doutb[677] = \<const0> ;
assign doutb[676] = \<const0> ;
assign doutb[675] = \<const0> ;
assign doutb[674] = \<const0> ;
assign doutb[673] = \<const0> ;
assign doutb[672] = \<const0> ;
assign doutb[671] = \<const0> ;
assign doutb[670] = \<const0> ;
assign doutb[669] = \<const0> ;
assign doutb[668] = \<const0> ;
assign doutb[667] = \<const0> ;
assign doutb[666] = \<const0> ;
assign doutb[665] = \<const0> ;
assign doutb[664] = \<const0> ;
assign doutb[663] = \<const0> ;
assign doutb[662] = \<const0> ;
assign doutb[661] = \<const0> ;
assign doutb[660] = \<const0> ;
assign doutb[659] = \<const0> ;
assign doutb[658] = \<const0> ;
assign doutb[657] = \<const0> ;
assign doutb[656] = \<const0> ;
assign doutb[655] = \<const0> ;
assign doutb[654] = \<const0> ;
assign doutb[653] = \<const0> ;
assign doutb[652] = \<const0> ;
assign doutb[651] = \<const0> ;
assign doutb[650] = \<const0> ;
assign doutb[649] = \<const0> ;
assign doutb[648] = \<const0> ;
assign doutb[647] = \<const0> ;
assign doutb[646] = \<const0> ;
assign doutb[645] = \<const0> ;
assign doutb[644] = \<const0> ;
assign doutb[643] = \<const0> ;
assign doutb[642] = \<const0> ;
assign doutb[641] = \<const0> ;
assign doutb[640] = \<const0> ;
assign doutb[639] = \<const0> ;
assign doutb[638] = \<const0> ;
assign doutb[637] = \<const0> ;
assign doutb[636] = \<const0> ;
assign doutb[635] = \<const0> ;
assign doutb[634] = \<const0> ;
assign doutb[633] = \<const0> ;
assign doutb[632] = \<const0> ;
assign doutb[631] = \<const0> ;
assign doutb[630] = \<const0> ;
assign doutb[629] = \<const0> ;
assign doutb[628] = \<const0> ;
assign doutb[627] = \<const0> ;
assign doutb[626] = \<const0> ;
assign doutb[625] = \<const0> ;
assign doutb[624] = \<const0> ;
assign doutb[623] = \<const0> ;
assign doutb[622] = \<const0> ;
assign doutb[621] = \<const0> ;
assign doutb[620] = \<const0> ;
assign doutb[619] = \<const0> ;
assign doutb[618] = \<const0> ;
assign doutb[617] = \<const0> ;
assign doutb[616] = \<const0> ;
assign doutb[615] = \<const0> ;
assign doutb[614] = \<const0> ;
assign doutb[613] = \<const0> ;
assign doutb[612] = \<const0> ;
assign doutb[611] = \<const0> ;
assign doutb[610] = \<const0> ;
assign doutb[609] = \<const0> ;
assign doutb[608] = \<const0> ;
assign doutb[607] = \<const0> ;
assign doutb[606] = \<const0> ;
assign doutb[605] = \<const0> ;
assign doutb[604] = \<const0> ;
assign doutb[603] = \<const0> ;
assign doutb[602] = \<const0> ;
assign doutb[601] = \<const0> ;
assign doutb[600] = \<const0> ;
assign doutb[599] = \<const0> ;
assign doutb[598] = \<const0> ;
assign doutb[597] = \<const0> ;
assign doutb[596] = \<const0> ;
assign doutb[595] = \<const0> ;
assign doutb[594] = \<const0> ;
assign doutb[593] = \<const0> ;
assign doutb[592] = \<const0> ;
assign doutb[591] = \<const0> ;
assign doutb[590] = \<const0> ;
assign doutb[589] = \<const0> ;
assign doutb[588] = \<const0> ;
assign doutb[587] = \<const0> ;
assign doutb[586] = \<const0> ;
assign doutb[585] = \<const0> ;
assign doutb[584] = \<const0> ;
assign doutb[583] = \<const0> ;
assign doutb[582] = \<const0> ;
assign doutb[581] = \<const0> ;
assign doutb[580] = \<const0> ;
assign doutb[579] = \<const0> ;
assign doutb[578] = \<const0> ;
assign doutb[577] = \<const0> ;
assign doutb[576] = \<const0> ;
assign doutb[575] = \<const0> ;
assign doutb[574] = \<const0> ;
assign doutb[573] = \<const0> ;
assign doutb[572] = \<const0> ;
assign doutb[571] = \<const0> ;
assign doutb[570] = \<const0> ;
assign doutb[569] = \<const0> ;
assign doutb[568] = \<const0> ;
assign doutb[567] = \<const0> ;
assign doutb[566] = \<const0> ;
assign doutb[565] = \<const0> ;
assign doutb[564] = \<const0> ;
assign doutb[563] = \<const0> ;
assign doutb[562] = \<const0> ;
assign doutb[561] = \<const0> ;
assign doutb[560] = \<const0> ;
assign doutb[559] = \<const0> ;
assign doutb[558] = \<const0> ;
assign doutb[557] = \<const0> ;
assign doutb[556] = \<const0> ;
assign doutb[555] = \<const0> ;
assign doutb[554] = \<const0> ;
assign doutb[553] = \<const0> ;
assign doutb[552] = \<const0> ;
assign doutb[551] = \<const0> ;
assign doutb[550] = \<const0> ;
assign doutb[549] = \<const0> ;
assign doutb[548] = \<const0> ;
assign doutb[547] = \<const0> ;
assign doutb[546] = \<const0> ;
assign doutb[545] = \<const0> ;
assign doutb[544] = \<const0> ;
assign doutb[543] = \<const0> ;
assign doutb[542] = \<const0> ;
assign doutb[541] = \<const0> ;
assign doutb[540] = \<const0> ;
assign doutb[539] = \<const0> ;
assign doutb[538] = \<const0> ;
assign doutb[537] = \<const0> ;
assign doutb[536] = \<const0> ;
assign doutb[535] = \<const0> ;
assign doutb[534] = \<const0> ;
assign doutb[533] = \<const0> ;
assign doutb[532] = \<const0> ;
assign doutb[531] = \<const0> ;
assign doutb[530] = \<const0> ;
assign doutb[529] = \<const0> ;
assign doutb[528] = \<const0> ;
assign doutb[527] = \<const0> ;
assign doutb[526] = \<const0> ;
assign doutb[525] = \<const0> ;
assign doutb[524] = \<const0> ;
assign doutb[523] = \<const0> ;
assign doutb[522] = \<const0> ;
assign doutb[521] = \<const0> ;
assign doutb[520] = \<const0> ;
assign doutb[519] = \<const0> ;
assign doutb[518] = \<const0> ;
assign doutb[517] = \<const0> ;
assign doutb[516] = \<const0> ;
assign doutb[515] = \<const0> ;
assign doutb[514] = \<const0> ;
assign doutb[513] = \<const0> ;
assign doutb[512] = \<const0> ;
assign doutb[511] = \<const0> ;
assign doutb[510] = \<const0> ;
assign doutb[509] = \<const0> ;
assign doutb[508] = \<const0> ;
assign doutb[507] = \<const0> ;
assign doutb[506] = \<const0> ;
assign doutb[505] = \<const0> ;
assign doutb[504] = \<const0> ;
assign doutb[503] = \<const0> ;
assign doutb[502] = \<const0> ;
assign doutb[501] = \<const0> ;
assign doutb[500] = \<const0> ;
assign doutb[499] = \<const0> ;
assign doutb[498] = \<const0> ;
assign doutb[497] = \<const0> ;
assign doutb[496] = \<const0> ;
assign doutb[495] = \<const0> ;
assign doutb[494] = \<const0> ;
assign doutb[493] = \<const0> ;
assign doutb[492] = \<const0> ;
assign doutb[491] = \<const0> ;
assign doutb[490] = \<const0> ;
assign doutb[489] = \<const0> ;
assign doutb[488] = \<const0> ;
assign doutb[487] = \<const0> ;
assign doutb[486] = \<const0> ;
assign doutb[485] = \<const0> ;
assign doutb[484] = \<const0> ;
assign doutb[483] = \<const0> ;
assign doutb[482] = \<const0> ;
assign doutb[481] = \<const0> ;
assign doutb[480] = \<const0> ;
assign doutb[479] = \<const0> ;
assign doutb[478] = \<const0> ;
assign doutb[477] = \<const0> ;
assign doutb[476] = \<const0> ;
assign doutb[475] = \<const0> ;
assign doutb[474] = \<const0> ;
assign doutb[473] = \<const0> ;
assign doutb[472] = \<const0> ;
assign doutb[471] = \<const0> ;
assign doutb[470] = \<const0> ;
assign doutb[469] = \<const0> ;
assign doutb[468] = \<const0> ;
assign doutb[467] = \<const0> ;
assign doutb[466] = \<const0> ;
assign doutb[465] = \<const0> ;
assign doutb[464] = \<const0> ;
assign doutb[463] = \<const0> ;
assign doutb[462] = \<const0> ;
assign doutb[461] = \<const0> ;
assign doutb[460] = \<const0> ;
assign doutb[459] = \<const0> ;
assign doutb[458] = \<const0> ;
assign doutb[457] = \<const0> ;
assign doutb[456] = \<const0> ;
assign doutb[455] = \<const0> ;
assign doutb[454] = \<const0> ;
assign doutb[453] = \<const0> ;
assign doutb[452] = \<const0> ;
assign doutb[451] = \<const0> ;
assign doutb[450] = \<const0> ;
assign doutb[449] = \<const0> ;
assign doutb[448] = \<const0> ;
assign doutb[447] = \<const0> ;
assign doutb[446] = \<const0> ;
assign doutb[445] = \<const0> ;
assign doutb[444] = \<const0> ;
assign doutb[443] = \<const0> ;
assign doutb[442] = \<const0> ;
assign doutb[441] = \<const0> ;
assign doutb[440] = \<const0> ;
assign doutb[439] = \<const0> ;
assign doutb[438] = \<const0> ;
assign doutb[437] = \<const0> ;
assign doutb[436] = \<const0> ;
assign doutb[435] = \<const0> ;
assign doutb[434] = \<const0> ;
assign doutb[433] = \<const0> ;
assign doutb[432] = \<const0> ;
assign doutb[431] = \<const0> ;
assign doutb[430] = \<const0> ;
assign doutb[429] = \<const0> ;
assign doutb[428] = \<const0> ;
assign doutb[427] = \<const0> ;
assign doutb[426] = \<const0> ;
assign doutb[425] = \<const0> ;
assign doutb[424] = \<const0> ;
assign doutb[423] = \<const0> ;
assign doutb[422] = \<const0> ;
assign doutb[421] = \<const0> ;
assign doutb[420] = \<const0> ;
assign doutb[419] = \<const0> ;
assign doutb[418] = \<const0> ;
assign doutb[417] = \<const0> ;
assign doutb[416] = \<const0> ;
assign doutb[415] = \<const0> ;
assign doutb[414] = \<const0> ;
assign doutb[413] = \<const0> ;
assign doutb[412] = \<const0> ;
assign doutb[411] = \<const0> ;
assign doutb[410] = \<const0> ;
assign doutb[409] = \<const0> ;
assign doutb[408] = \<const0> ;
assign doutb[407] = \<const0> ;
assign doutb[406] = \<const0> ;
assign doutb[405] = \<const0> ;
assign doutb[404] = \<const0> ;
assign doutb[403] = \<const0> ;
assign doutb[402] = \<const0> ;
assign doutb[401] = \<const0> ;
assign doutb[400] = \<const0> ;
assign doutb[399] = \<const0> ;
assign doutb[398] = \<const0> ;
assign doutb[397] = \<const0> ;
assign doutb[396] = \<const0> ;
assign doutb[395] = \<const0> ;
assign doutb[394] = \<const0> ;
assign doutb[393] = \<const0> ;
assign doutb[392] = \<const0> ;
assign doutb[391] = \<const0> ;
assign doutb[390] = \<const0> ;
assign doutb[389] = \<const0> ;
assign doutb[388] = \<const0> ;
assign doutb[387] = \<const0> ;
assign doutb[386] = \<const0> ;
assign doutb[385] = \<const0> ;
assign doutb[384] = \<const0> ;
assign doutb[383] = \<const0> ;
assign doutb[382] = \<const0> ;
assign doutb[381] = \<const0> ;
assign doutb[380] = \<const0> ;
assign doutb[379] = \<const0> ;
assign doutb[378] = \<const0> ;
assign doutb[377] = \<const0> ;
assign doutb[376] = \<const0> ;
assign doutb[375] = \<const0> ;
assign doutb[374] = \<const0> ;
assign doutb[373] = \<const0> ;
assign doutb[372] = \<const0> ;
assign doutb[371] = \<const0> ;
assign doutb[370] = \<const0> ;
assign doutb[369] = \<const0> ;
assign doutb[368] = \<const0> ;
assign doutb[367] = \<const0> ;
assign doutb[366] = \<const0> ;
assign doutb[365] = \<const0> ;
assign doutb[364] = \<const0> ;
assign doutb[363] = \<const0> ;
assign doutb[362] = \<const0> ;
assign doutb[361] = \<const0> ;
assign doutb[360] = \<const0> ;
assign doutb[359] = \<const0> ;
assign doutb[358] = \<const0> ;
assign doutb[357] = \<const0> ;
assign doutb[356] = \<const0> ;
assign doutb[355] = \<const0> ;
assign doutb[354] = \<const0> ;
assign doutb[353] = \<const0> ;
assign doutb[352] = \<const0> ;
assign doutb[351] = \<const0> ;
assign doutb[350] = \<const0> ;
assign doutb[349] = \<const0> ;
assign doutb[348] = \<const0> ;
assign doutb[347] = \<const0> ;
assign doutb[346] = \<const0> ;
assign doutb[345] = \<const0> ;
assign doutb[344] = \<const0> ;
assign doutb[343] = \<const0> ;
assign doutb[342] = \<const0> ;
assign doutb[341] = \<const0> ;
assign doutb[340] = \<const0> ;
assign doutb[339] = \<const0> ;
assign doutb[338] = \<const0> ;
assign doutb[337] = \<const0> ;
assign doutb[336] = \<const0> ;
assign doutb[335] = \<const0> ;
assign doutb[334] = \<const0> ;
assign doutb[333] = \<const0> ;
assign doutb[332] = \<const0> ;
assign doutb[331] = \<const0> ;
assign doutb[330] = \<const0> ;
assign doutb[329] = \<const0> ;
assign doutb[328] = \<const0> ;
assign doutb[327] = \<const0> ;
assign doutb[326] = \<const0> ;
assign doutb[325] = \<const0> ;
assign doutb[324] = \<const0> ;
assign doutb[323] = \<const0> ;
assign doutb[322] = \<const0> ;
assign doutb[321] = \<const0> ;
assign doutb[320] = \<const0> ;
assign doutb[319] = \<const0> ;
assign doutb[318] = \<const0> ;
assign doutb[317] = \<const0> ;
assign doutb[316] = \<const0> ;
assign doutb[315] = \<const0> ;
assign doutb[314] = \<const0> ;
assign doutb[313] = \<const0> ;
assign doutb[312] = \<const0> ;
assign doutb[311] = \<const0> ;
assign doutb[310] = \<const0> ;
assign doutb[309] = \<const0> ;
assign doutb[308] = \<const0> ;
assign doutb[307] = \<const0> ;
assign doutb[306] = \<const0> ;
assign doutb[305] = \<const0> ;
assign doutb[304] = \<const0> ;
assign doutb[303] = \<const0> ;
assign doutb[302] = \<const0> ;
assign doutb[301] = \<const0> ;
assign doutb[300] = \<const0> ;
assign doutb[299] = \<const0> ;
assign doutb[298] = \<const0> ;
assign doutb[297] = \<const0> ;
assign doutb[296] = \<const0> ;
assign doutb[295] = \<const0> ;
assign doutb[294] = \<const0> ;
assign doutb[293] = \<const0> ;
assign doutb[292] = \<const0> ;
assign doutb[291] = \<const0> ;
assign doutb[290] = \<const0> ;
assign doutb[289] = \<const0> ;
assign doutb[288] = \<const0> ;
assign doutb[287] = \<const0> ;
assign doutb[286] = \<const0> ;
assign doutb[285] = \<const0> ;
assign doutb[284] = \<const0> ;
assign doutb[283] = \<const0> ;
assign doutb[282] = \<const0> ;
assign doutb[281] = \<const0> ;
assign doutb[280] = \<const0> ;
assign doutb[279] = \<const0> ;
assign doutb[278] = \<const0> ;
assign doutb[277] = \<const0> ;
assign doutb[276] = \<const0> ;
assign doutb[275] = \<const0> ;
assign doutb[274] = \<const0> ;
assign doutb[273] = \<const0> ;
assign doutb[272] = \<const0> ;
assign doutb[271] = \<const0> ;
assign doutb[270] = \<const0> ;
assign doutb[269] = \<const0> ;
assign doutb[268] = \<const0> ;
assign doutb[267] = \<const0> ;
assign doutb[266] = \<const0> ;
assign doutb[265] = \<const0> ;
assign doutb[264] = \<const0> ;
assign doutb[263] = \<const0> ;
assign doutb[262] = \<const0> ;
assign doutb[261] = \<const0> ;
assign doutb[260] = \<const0> ;
assign doutb[259] = \<const0> ;
assign doutb[258] = \<const0> ;
assign doutb[257] = \<const0> ;
assign doutb[256] = \<const0> ;
assign doutb[255] = \<const0> ;
assign doutb[254] = \<const0> ;
assign doutb[253] = \<const0> ;
assign doutb[252] = \<const0> ;
assign doutb[251] = \<const0> ;
assign doutb[250] = \<const0> ;
assign doutb[249] = \<const0> ;
assign doutb[248] = \<const0> ;
assign doutb[247] = \<const0> ;
assign doutb[246] = \<const0> ;
assign doutb[245] = \<const0> ;
assign doutb[244] = \<const0> ;
assign doutb[243] = \<const0> ;
assign doutb[242] = \<const0> ;
assign doutb[241] = \<const0> ;
assign doutb[240] = \<const0> ;
assign doutb[239] = \<const0> ;
assign doutb[238] = \<const0> ;
assign doutb[237] = \<const0> ;
assign doutb[236] = \<const0> ;
assign doutb[235] = \<const0> ;
assign doutb[234] = \<const0> ;
assign doutb[233] = \<const0> ;
assign doutb[232] = \<const0> ;
assign doutb[231] = \<const0> ;
assign doutb[230] = \<const0> ;
assign doutb[229] = \<const0> ;
assign doutb[228] = \<const0> ;
assign doutb[227] = \<const0> ;
assign doutb[226] = \<const0> ;
assign doutb[225] = \<const0> ;
assign doutb[224] = \<const0> ;
assign doutb[223] = \<const0> ;
assign doutb[222] = \<const0> ;
assign doutb[221] = \<const0> ;
assign doutb[220] = \<const0> ;
assign doutb[219] = \<const0> ;
assign doutb[218] = \<const0> ;
assign doutb[217] = \<const0> ;
assign doutb[216] = \<const0> ;
assign doutb[215] = \<const0> ;
assign doutb[214] = \<const0> ;
assign doutb[213] = \<const0> ;
assign doutb[212] = \<const0> ;
assign doutb[211] = \<const0> ;
assign doutb[210] = \<const0> ;
assign doutb[209] = \<const0> ;
assign doutb[208] = \<const0> ;
assign doutb[207] = \<const0> ;
assign doutb[206] = \<const0> ;
assign doutb[205] = \<const0> ;
assign doutb[204] = \<const0> ;
assign doutb[203] = \<const0> ;
assign doutb[202] = \<const0> ;
assign doutb[201] = \<const0> ;
assign doutb[200] = \<const0> ;
assign doutb[199] = \<const0> ;
assign doutb[198] = \<const0> ;
assign doutb[197] = \<const0> ;
assign doutb[196] = \<const0> ;
assign doutb[195] = \<const0> ;
assign doutb[194] = \<const0> ;
assign doutb[193] = \<const0> ;
assign doutb[192] = \<const0> ;
assign doutb[191] = \<const0> ;
assign doutb[190] = \<const0> ;
assign doutb[189] = \<const0> ;
assign doutb[188] = \<const0> ;
assign doutb[187] = \<const0> ;
assign doutb[186] = \<const0> ;
assign doutb[185] = \<const0> ;
assign doutb[184] = \<const0> ;
assign doutb[183] = \<const0> ;
assign doutb[182] = \<const0> ;
assign doutb[181] = \<const0> ;
assign doutb[180] = \<const0> ;
assign doutb[179] = \<const0> ;
assign doutb[178] = \<const0> ;
assign doutb[177] = \<const0> ;
assign doutb[176] = \<const0> ;
assign doutb[175] = \<const0> ;
assign doutb[174] = \<const0> ;
assign doutb[173] = \<const0> ;
assign doutb[172] = \<const0> ;
assign doutb[171] = \<const0> ;
assign doutb[170] = \<const0> ;
assign doutb[169] = \<const0> ;
assign doutb[168] = \<const0> ;
assign doutb[167] = \<const0> ;
assign doutb[166] = \<const0> ;
assign doutb[165] = \<const0> ;
assign doutb[164] = \<const0> ;
assign doutb[163] = \<const0> ;
assign doutb[162] = \<const0> ;
assign doutb[161] = \<const0> ;
assign doutb[160] = \<const0> ;
assign doutb[159] = \<const0> ;
assign doutb[158] = \<const0> ;
assign doutb[157] = \<const0> ;
assign doutb[156] = \<const0> ;
assign doutb[155] = \<const0> ;
assign doutb[154] = \<const0> ;
assign doutb[153] = \<const0> ;
assign doutb[152] = \<const0> ;
assign doutb[151] = \<const0> ;
assign doutb[150] = \<const0> ;
assign doutb[149] = \<const0> ;
assign doutb[148] = \<const0> ;
assign doutb[147] = \<const0> ;
assign doutb[146] = \<const0> ;
assign doutb[145] = \<const0> ;
assign doutb[144] = \<const0> ;
assign doutb[143] = \<const0> ;
assign doutb[142] = \<const0> ;
assign doutb[141] = \<const0> ;
assign doutb[140] = \<const0> ;
assign doutb[139] = \<const0> ;
assign doutb[138] = \<const0> ;
assign doutb[137] = \<const0> ;
assign doutb[136] = \<const0> ;
assign doutb[135] = \<const0> ;
assign doutb[134] = \<const0> ;
assign doutb[133] = \<const0> ;
assign doutb[132] = \<const0> ;
assign doutb[131] = \<const0> ;
assign doutb[130] = \<const0> ;
assign doutb[129] = \<const0> ;
assign doutb[128] = \<const0> ;
assign doutb[127] = \<const0> ;
assign doutb[126] = \<const0> ;
assign doutb[125] = \<const0> ;
assign doutb[124] = \<const0> ;
assign doutb[123] = \<const0> ;
assign doutb[122] = \<const0> ;
assign doutb[121] = \<const0> ;
assign doutb[120] = \<const0> ;
assign doutb[119] = \<const0> ;
assign doutb[118] = \<const0> ;
assign doutb[117] = \<const0> ;
assign doutb[116] = \<const0> ;
assign doutb[115] = \<const0> ;
assign doutb[114] = \<const0> ;
assign doutb[113] = \<const0> ;
assign doutb[112] = \<const0> ;
assign doutb[111] = \<const0> ;
assign doutb[110] = \<const0> ;
assign doutb[109] = \<const0> ;
assign doutb[108] = \<const0> ;
assign doutb[107] = \<const0> ;
assign doutb[106] = \<const0> ;
assign doutb[105] = \<const0> ;
assign doutb[104] = \<const0> ;
assign doutb[103] = \<const0> ;
assign doutb[102] = \<const0> ;
assign doutb[101] = \<const0> ;
assign doutb[100] = \<const0> ;
assign doutb[99] = \<const0> ;
assign doutb[98] = \<const0> ;
assign doutb[97] = \<const0> ;
assign doutb[96] = \<const0> ;
assign doutb[95] = \<const0> ;
assign doutb[94] = \<const0> ;
assign doutb[93] = \<const0> ;
assign doutb[92] = \<const0> ;
assign doutb[91] = \<const0> ;
assign doutb[90] = \<const0> ;
assign doutb[89] = \<const0> ;
assign doutb[88] = \<const0> ;
assign doutb[87] = \<const0> ;
assign doutb[86] = \<const0> ;
assign doutb[85] = \<const0> ;
assign doutb[84] = \<const0> ;
assign doutb[83] = \<const0> ;
assign doutb[82] = \<const0> ;
assign doutb[81] = \<const0> ;
assign doutb[80] = \<const0> ;
assign doutb[79] = \<const0> ;
assign doutb[78] = \<const0> ;
assign doutb[77] = \<const0> ;
assign doutb[76] = \<const0> ;
assign doutb[75] = \<const0> ;
assign doutb[74] = \<const0> ;
assign doutb[73] = \<const0> ;
assign doutb[72] = \<const0> ;
assign doutb[71] = \<const0> ;
assign doutb[70] = \<const0> ;
assign doutb[69] = \<const0> ;
assign doutb[68] = \<const0> ;
assign doutb[67] = \<const0> ;
assign doutb[66] = \<const0> ;
assign doutb[65] = \<const0> ;
assign doutb[64] = \<const0> ;
assign doutb[63] = \<const0> ;
assign doutb[62] = \<const0> ;
assign doutb[61] = \<const0> ;
assign doutb[60] = \<const0> ;
assign doutb[59] = \<const0> ;
assign doutb[58] = \<const0> ;
assign doutb[57] = \<const0> ;
assign doutb[56] = \<const0> ;
assign doutb[55] = \<const0> ;
assign doutb[54] = \<const0> ;
assign doutb[53] = \<const0> ;
assign doutb[52] = \<const0> ;
assign doutb[51] = \<const0> ;
assign doutb[50] = \<const0> ;
assign doutb[49] = \<const0> ;
assign doutb[48] = \<const0> ;
assign doutb[47] = \<const0> ;
assign doutb[46] = \<const0> ;
assign doutb[45] = \<const0> ;
assign doutb[44] = \<const0> ;
assign doutb[43] = \<const0> ;
assign doutb[42] = \<const0> ;
assign doutb[41] = \<const0> ;
assign doutb[40] = \<const0> ;
assign doutb[39] = \<const0> ;
assign doutb[38] = \<const0> ;
assign doutb[37] = \<const0> ;
assign doutb[36] = \<const0> ;
assign doutb[35] = \<const0> ;
assign doutb[34] = \<const0> ;
assign doutb[33] = \<const0> ;
assign doutb[32] = \<const0> ;
assign doutb[31] = \<const0> ;
assign doutb[30] = \<const0> ;
assign doutb[29] = \<const0> ;
assign doutb[28] = \<const0> ;
assign doutb[27] = \<const0> ;
assign doutb[26] = \<const0> ;
assign doutb[25] = \<const0> ;
assign doutb[24] = \<const0> ;
assign doutb[23] = \<const0> ;
assign doutb[22] = \<const0> ;
assign doutb[21] = \<const0> ;
assign doutb[20] = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[799] = \<const0> ;
assign s_axi_rdata[798] = \<const0> ;
assign s_axi_rdata[797] = \<const0> ;
assign s_axi_rdata[796] = \<const0> ;
assign s_axi_rdata[795] = \<const0> ;
assign s_axi_rdata[794] = \<const0> ;
assign s_axi_rdata[793] = \<const0> ;
assign s_axi_rdata[792] = \<const0> ;
assign s_axi_rdata[791] = \<const0> ;
assign s_axi_rdata[790] = \<const0> ;
assign s_axi_rdata[789] = \<const0> ;
assign s_axi_rdata[788] = \<const0> ;
assign s_axi_rdata[787] = \<const0> ;
assign s_axi_rdata[786] = \<const0> ;
assign s_axi_rdata[785] = \<const0> ;
assign s_axi_rdata[784] = \<const0> ;
assign s_axi_rdata[783] = \<const0> ;
assign s_axi_rdata[782] = \<const0> ;
assign s_axi_rdata[781] = \<const0> ;
assign s_axi_rdata[780] = \<const0> ;
assign s_axi_rdata[779] = \<const0> ;
assign s_axi_rdata[778] = \<const0> ;
assign s_axi_rdata[777] = \<const0> ;
assign s_axi_rdata[776] = \<const0> ;
assign s_axi_rdata[775] = \<const0> ;
assign s_axi_rdata[774] = \<const0> ;
assign s_axi_rdata[773] = \<const0> ;
assign s_axi_rdata[772] = \<const0> ;
assign s_axi_rdata[771] = \<const0> ;
assign s_axi_rdata[770] = \<const0> ;
assign s_axi_rdata[769] = \<const0> ;
assign s_axi_rdata[768] = \<const0> ;
assign s_axi_rdata[767] = \<const0> ;
assign s_axi_rdata[766] = \<const0> ;
assign s_axi_rdata[765] = \<const0> ;
assign s_axi_rdata[764] = \<const0> ;
assign s_axi_rdata[763] = \<const0> ;
assign s_axi_rdata[762] = \<const0> ;
assign s_axi_rdata[761] = \<const0> ;
assign s_axi_rdata[760] = \<const0> ;
assign s_axi_rdata[759] = \<const0> ;
assign s_axi_rdata[758] = \<const0> ;
assign s_axi_rdata[757] = \<const0> ;
assign s_axi_rdata[756] = \<const0> ;
assign s_axi_rdata[755] = \<const0> ;
assign s_axi_rdata[754] = \<const0> ;
assign s_axi_rdata[753] = \<const0> ;
assign s_axi_rdata[752] = \<const0> ;
assign s_axi_rdata[751] = \<const0> ;
assign s_axi_rdata[750] = \<const0> ;
assign s_axi_rdata[749] = \<const0> ;
assign s_axi_rdata[748] = \<const0> ;
assign s_axi_rdata[747] = \<const0> ;
assign s_axi_rdata[746] = \<const0> ;
assign s_axi_rdata[745] = \<const0> ;
assign s_axi_rdata[744] = \<const0> ;
assign s_axi_rdata[743] = \<const0> ;
assign s_axi_rdata[742] = \<const0> ;
assign s_axi_rdata[741] = \<const0> ;
assign s_axi_rdata[740] = \<const0> ;
assign s_axi_rdata[739] = \<const0> ;
assign s_axi_rdata[738] = \<const0> ;
assign s_axi_rdata[737] = \<const0> ;
assign s_axi_rdata[736] = \<const0> ;
assign s_axi_rdata[735] = \<const0> ;
assign s_axi_rdata[734] = \<const0> ;
assign s_axi_rdata[733] = \<const0> ;
assign s_axi_rdata[732] = \<const0> ;
assign s_axi_rdata[731] = \<const0> ;
assign s_axi_rdata[730] = \<const0> ;
assign s_axi_rdata[729] = \<const0> ;
assign s_axi_rdata[728] = \<const0> ;
assign s_axi_rdata[727] = \<const0> ;
assign s_axi_rdata[726] = \<const0> ;
assign s_axi_rdata[725] = \<const0> ;
assign s_axi_rdata[724] = \<const0> ;
assign s_axi_rdata[723] = \<const0> ;
assign s_axi_rdata[722] = \<const0> ;
assign s_axi_rdata[721] = \<const0> ;
assign s_axi_rdata[720] = \<const0> ;
assign s_axi_rdata[719] = \<const0> ;
assign s_axi_rdata[718] = \<const0> ;
assign s_axi_rdata[717] = \<const0> ;
assign s_axi_rdata[716] = \<const0> ;
assign s_axi_rdata[715] = \<const0> ;
assign s_axi_rdata[714] = \<const0> ;
assign s_axi_rdata[713] = \<const0> ;
assign s_axi_rdata[712] = \<const0> ;
assign s_axi_rdata[711] = \<const0> ;
assign s_axi_rdata[710] = \<const0> ;
assign s_axi_rdata[709] = \<const0> ;
assign s_axi_rdata[708] = \<const0> ;
assign s_axi_rdata[707] = \<const0> ;
assign s_axi_rdata[706] = \<const0> ;
assign s_axi_rdata[705] = \<const0> ;
assign s_axi_rdata[704] = \<const0> ;
assign s_axi_rdata[703] = \<const0> ;
assign s_axi_rdata[702] = \<const0> ;
assign s_axi_rdata[701] = \<const0> ;
assign s_axi_rdata[700] = \<const0> ;
assign s_axi_rdata[699] = \<const0> ;
assign s_axi_rdata[698] = \<const0> ;
assign s_axi_rdata[697] = \<const0> ;
assign s_axi_rdata[696] = \<const0> ;
assign s_axi_rdata[695] = \<const0> ;
assign s_axi_rdata[694] = \<const0> ;
assign s_axi_rdata[693] = \<const0> ;
assign s_axi_rdata[692] = \<const0> ;
assign s_axi_rdata[691] = \<const0> ;
assign s_axi_rdata[690] = \<const0> ;
assign s_axi_rdata[689] = \<const0> ;
assign s_axi_rdata[688] = \<const0> ;
assign s_axi_rdata[687] = \<const0> ;
assign s_axi_rdata[686] = \<const0> ;
assign s_axi_rdata[685] = \<const0> ;
assign s_axi_rdata[684] = \<const0> ;
assign s_axi_rdata[683] = \<const0> ;
assign s_axi_rdata[682] = \<const0> ;
assign s_axi_rdata[681] = \<const0> ;
assign s_axi_rdata[680] = \<const0> ;
assign s_axi_rdata[679] = \<const0> ;
assign s_axi_rdata[678] = \<const0> ;
assign s_axi_rdata[677] = \<const0> ;
assign s_axi_rdata[676] = \<const0> ;
assign s_axi_rdata[675] = \<const0> ;
assign s_axi_rdata[674] = \<const0> ;
assign s_axi_rdata[673] = \<const0> ;
assign s_axi_rdata[672] = \<const0> ;
assign s_axi_rdata[671] = \<const0> ;
assign s_axi_rdata[670] = \<const0> ;
assign s_axi_rdata[669] = \<const0> ;
assign s_axi_rdata[668] = \<const0> ;
assign s_axi_rdata[667] = \<const0> ;
assign s_axi_rdata[666] = \<const0> ;
assign s_axi_rdata[665] = \<const0> ;
assign s_axi_rdata[664] = \<const0> ;
assign s_axi_rdata[663] = \<const0> ;
assign s_axi_rdata[662] = \<const0> ;
assign s_axi_rdata[661] = \<const0> ;
assign s_axi_rdata[660] = \<const0> ;
assign s_axi_rdata[659] = \<const0> ;
assign s_axi_rdata[658] = \<const0> ;
assign s_axi_rdata[657] = \<const0> ;
assign s_axi_rdata[656] = \<const0> ;
assign s_axi_rdata[655] = \<const0> ;
assign s_axi_rdata[654] = \<const0> ;
assign s_axi_rdata[653] = \<const0> ;
assign s_axi_rdata[652] = \<const0> ;
assign s_axi_rdata[651] = \<const0> ;
assign s_axi_rdata[650] = \<const0> ;
assign s_axi_rdata[649] = \<const0> ;
assign s_axi_rdata[648] = \<const0> ;
assign s_axi_rdata[647] = \<const0> ;
assign s_axi_rdata[646] = \<const0> ;
assign s_axi_rdata[645] = \<const0> ;
assign s_axi_rdata[644] = \<const0> ;
assign s_axi_rdata[643] = \<const0> ;
assign s_axi_rdata[642] = \<const0> ;
assign s_axi_rdata[641] = \<const0> ;
assign s_axi_rdata[640] = \<const0> ;
assign s_axi_rdata[639] = \<const0> ;
assign s_axi_rdata[638] = \<const0> ;
assign s_axi_rdata[637] = \<const0> ;
assign s_axi_rdata[636] = \<const0> ;
assign s_axi_rdata[635] = \<const0> ;
assign s_axi_rdata[634] = \<const0> ;
assign s_axi_rdata[633] = \<const0> ;
assign s_axi_rdata[632] = \<const0> ;
assign s_axi_rdata[631] = \<const0> ;
assign s_axi_rdata[630] = \<const0> ;
assign s_axi_rdata[629] = \<const0> ;
assign s_axi_rdata[628] = \<const0> ;
assign s_axi_rdata[627] = \<const0> ;
assign s_axi_rdata[626] = \<const0> ;
assign s_axi_rdata[625] = \<const0> ;
assign s_axi_rdata[624] = \<const0> ;
assign s_axi_rdata[623] = \<const0> ;
assign s_axi_rdata[622] = \<const0> ;
assign s_axi_rdata[621] = \<const0> ;
assign s_axi_rdata[620] = \<const0> ;
assign s_axi_rdata[619] = \<const0> ;
assign s_axi_rdata[618] = \<const0> ;
assign s_axi_rdata[617] = \<const0> ;
assign s_axi_rdata[616] = \<const0> ;
assign s_axi_rdata[615] = \<const0> ;
assign s_axi_rdata[614] = \<const0> ;
assign s_axi_rdata[613] = \<const0> ;
assign s_axi_rdata[612] = \<const0> ;
assign s_axi_rdata[611] = \<const0> ;
assign s_axi_rdata[610] = \<const0> ;
assign s_axi_rdata[609] = \<const0> ;
assign s_axi_rdata[608] = \<const0> ;
assign s_axi_rdata[607] = \<const0> ;
assign s_axi_rdata[606] = \<const0> ;
assign s_axi_rdata[605] = \<const0> ;
assign s_axi_rdata[604] = \<const0> ;
assign s_axi_rdata[603] = \<const0> ;
assign s_axi_rdata[602] = \<const0> ;
assign s_axi_rdata[601] = \<const0> ;
assign s_axi_rdata[600] = \<const0> ;
assign s_axi_rdata[599] = \<const0> ;
assign s_axi_rdata[598] = \<const0> ;
assign s_axi_rdata[597] = \<const0> ;
assign s_axi_rdata[596] = \<const0> ;
assign s_axi_rdata[595] = \<const0> ;
assign s_axi_rdata[594] = \<const0> ;
assign s_axi_rdata[593] = \<const0> ;
assign s_axi_rdata[592] = \<const0> ;
assign s_axi_rdata[591] = \<const0> ;
assign s_axi_rdata[590] = \<const0> ;
assign s_axi_rdata[589] = \<const0> ;
assign s_axi_rdata[588] = \<const0> ;
assign s_axi_rdata[587] = \<const0> ;
assign s_axi_rdata[586] = \<const0> ;
assign s_axi_rdata[585] = \<const0> ;
assign s_axi_rdata[584] = \<const0> ;
assign s_axi_rdata[583] = \<const0> ;
assign s_axi_rdata[582] = \<const0> ;
assign s_axi_rdata[581] = \<const0> ;
assign s_axi_rdata[580] = \<const0> ;
assign s_axi_rdata[579] = \<const0> ;
assign s_axi_rdata[578] = \<const0> ;
assign s_axi_rdata[577] = \<const0> ;
assign s_axi_rdata[576] = \<const0> ;
assign s_axi_rdata[575] = \<const0> ;
assign s_axi_rdata[574] = \<const0> ;
assign s_axi_rdata[573] = \<const0> ;
assign s_axi_rdata[572] = \<const0> ;
assign s_axi_rdata[571] = \<const0> ;
assign s_axi_rdata[570] = \<const0> ;
assign s_axi_rdata[569] = \<const0> ;
assign s_axi_rdata[568] = \<const0> ;
assign s_axi_rdata[567] = \<const0> ;
assign s_axi_rdata[566] = \<const0> ;
assign s_axi_rdata[565] = \<const0> ;
assign s_axi_rdata[564] = \<const0> ;
assign s_axi_rdata[563] = \<const0> ;
assign s_axi_rdata[562] = \<const0> ;
assign s_axi_rdata[561] = \<const0> ;
assign s_axi_rdata[560] = \<const0> ;
assign s_axi_rdata[559] = \<const0> ;
assign s_axi_rdata[558] = \<const0> ;
assign s_axi_rdata[557] = \<const0> ;
assign s_axi_rdata[556] = \<const0> ;
assign s_axi_rdata[555] = \<const0> ;
assign s_axi_rdata[554] = \<const0> ;
assign s_axi_rdata[553] = \<const0> ;
assign s_axi_rdata[552] = \<const0> ;
assign s_axi_rdata[551] = \<const0> ;
assign s_axi_rdata[550] = \<const0> ;
assign s_axi_rdata[549] = \<const0> ;
assign s_axi_rdata[548] = \<const0> ;
assign s_axi_rdata[547] = \<const0> ;
assign s_axi_rdata[546] = \<const0> ;
assign s_axi_rdata[545] = \<const0> ;
assign s_axi_rdata[544] = \<const0> ;
assign s_axi_rdata[543] = \<const0> ;
assign s_axi_rdata[542] = \<const0> ;
assign s_axi_rdata[541] = \<const0> ;
assign s_axi_rdata[540] = \<const0> ;
assign s_axi_rdata[539] = \<const0> ;
assign s_axi_rdata[538] = \<const0> ;
assign s_axi_rdata[537] = \<const0> ;
assign s_axi_rdata[536] = \<const0> ;
assign s_axi_rdata[535] = \<const0> ;
assign s_axi_rdata[534] = \<const0> ;
assign s_axi_rdata[533] = \<const0> ;
assign s_axi_rdata[532] = \<const0> ;
assign s_axi_rdata[531] = \<const0> ;
assign s_axi_rdata[530] = \<const0> ;
assign s_axi_rdata[529] = \<const0> ;
assign s_axi_rdata[528] = \<const0> ;
assign s_axi_rdata[527] = \<const0> ;
assign s_axi_rdata[526] = \<const0> ;
assign s_axi_rdata[525] = \<const0> ;
assign s_axi_rdata[524] = \<const0> ;
assign s_axi_rdata[523] = \<const0> ;
assign s_axi_rdata[522] = \<const0> ;
assign s_axi_rdata[521] = \<const0> ;
assign s_axi_rdata[520] = \<const0> ;
assign s_axi_rdata[519] = \<const0> ;
assign s_axi_rdata[518] = \<const0> ;
assign s_axi_rdata[517] = \<const0> ;
assign s_axi_rdata[516] = \<const0> ;
assign s_axi_rdata[515] = \<const0> ;
assign s_axi_rdata[514] = \<const0> ;
assign s_axi_rdata[513] = \<const0> ;
assign s_axi_rdata[512] = \<const0> ;
assign s_axi_rdata[511] = \<const0> ;
assign s_axi_rdata[510] = \<const0> ;
assign s_axi_rdata[509] = \<const0> ;
assign s_axi_rdata[508] = \<const0> ;
assign s_axi_rdata[507] = \<const0> ;
assign s_axi_rdata[506] = \<const0> ;
assign s_axi_rdata[505] = \<const0> ;
assign s_axi_rdata[504] = \<const0> ;
assign s_axi_rdata[503] = \<const0> ;
assign s_axi_rdata[502] = \<const0> ;
assign s_axi_rdata[501] = \<const0> ;
assign s_axi_rdata[500] = \<const0> ;
assign s_axi_rdata[499] = \<const0> ;
assign s_axi_rdata[498] = \<const0> ;
assign s_axi_rdata[497] = \<const0> ;
assign s_axi_rdata[496] = \<const0> ;
assign s_axi_rdata[495] = \<const0> ;
assign s_axi_rdata[494] = \<const0> ;
assign s_axi_rdata[493] = \<const0> ;
assign s_axi_rdata[492] = \<const0> ;
assign s_axi_rdata[491] = \<const0> ;
assign s_axi_rdata[490] = \<const0> ;
assign s_axi_rdata[489] = \<const0> ;
assign s_axi_rdata[488] = \<const0> ;
assign s_axi_rdata[487] = \<const0> ;
assign s_axi_rdata[486] = \<const0> ;
assign s_axi_rdata[485] = \<const0> ;
assign s_axi_rdata[484] = \<const0> ;
assign s_axi_rdata[483] = \<const0> ;
assign s_axi_rdata[482] = \<const0> ;
assign s_axi_rdata[481] = \<const0> ;
assign s_axi_rdata[480] = \<const0> ;
assign s_axi_rdata[479] = \<const0> ;
assign s_axi_rdata[478] = \<const0> ;
assign s_axi_rdata[477] = \<const0> ;
assign s_axi_rdata[476] = \<const0> ;
assign s_axi_rdata[475] = \<const0> ;
assign s_axi_rdata[474] = \<const0> ;
assign s_axi_rdata[473] = \<const0> ;
assign s_axi_rdata[472] = \<const0> ;
assign s_axi_rdata[471] = \<const0> ;
assign s_axi_rdata[470] = \<const0> ;
assign s_axi_rdata[469] = \<const0> ;
assign s_axi_rdata[468] = \<const0> ;
assign s_axi_rdata[467] = \<const0> ;
assign s_axi_rdata[466] = \<const0> ;
assign s_axi_rdata[465] = \<const0> ;
assign s_axi_rdata[464] = \<const0> ;
assign s_axi_rdata[463] = \<const0> ;
assign s_axi_rdata[462] = \<const0> ;
assign s_axi_rdata[461] = \<const0> ;
assign s_axi_rdata[460] = \<const0> ;
assign s_axi_rdata[459] = \<const0> ;
assign s_axi_rdata[458] = \<const0> ;
assign s_axi_rdata[457] = \<const0> ;
assign s_axi_rdata[456] = \<const0> ;
assign s_axi_rdata[455] = \<const0> ;
assign s_axi_rdata[454] = \<const0> ;
assign s_axi_rdata[453] = \<const0> ;
assign s_axi_rdata[452] = \<const0> ;
assign s_axi_rdata[451] = \<const0> ;
assign s_axi_rdata[450] = \<const0> ;
assign s_axi_rdata[449] = \<const0> ;
assign s_axi_rdata[448] = \<const0> ;
assign s_axi_rdata[447] = \<const0> ;
assign s_axi_rdata[446] = \<const0> ;
assign s_axi_rdata[445] = \<const0> ;
assign s_axi_rdata[444] = \<const0> ;
assign s_axi_rdata[443] = \<const0> ;
assign s_axi_rdata[442] = \<const0> ;
assign s_axi_rdata[441] = \<const0> ;
assign s_axi_rdata[440] = \<const0> ;
assign s_axi_rdata[439] = \<const0> ;
assign s_axi_rdata[438] = \<const0> ;
assign s_axi_rdata[437] = \<const0> ;
assign s_axi_rdata[436] = \<const0> ;
assign s_axi_rdata[435] = \<const0> ;
assign s_axi_rdata[434] = \<const0> ;
assign s_axi_rdata[433] = \<const0> ;
assign s_axi_rdata[432] = \<const0> ;
assign s_axi_rdata[431] = \<const0> ;
assign s_axi_rdata[430] = \<const0> ;
assign s_axi_rdata[429] = \<const0> ;
assign s_axi_rdata[428] = \<const0> ;
assign s_axi_rdata[427] = \<const0> ;
assign s_axi_rdata[426] = \<const0> ;
assign s_axi_rdata[425] = \<const0> ;
assign s_axi_rdata[424] = \<const0> ;
assign s_axi_rdata[423] = \<const0> ;
assign s_axi_rdata[422] = \<const0> ;
assign s_axi_rdata[421] = \<const0> ;
assign s_axi_rdata[420] = \<const0> ;
assign s_axi_rdata[419] = \<const0> ;
assign s_axi_rdata[418] = \<const0> ;
assign s_axi_rdata[417] = \<const0> ;
assign s_axi_rdata[416] = \<const0> ;
assign s_axi_rdata[415] = \<const0> ;
assign s_axi_rdata[414] = \<const0> ;
assign s_axi_rdata[413] = \<const0> ;
assign s_axi_rdata[412] = \<const0> ;
assign s_axi_rdata[411] = \<const0> ;
assign s_axi_rdata[410] = \<const0> ;
assign s_axi_rdata[409] = \<const0> ;
assign s_axi_rdata[408] = \<const0> ;
assign s_axi_rdata[407] = \<const0> ;
assign s_axi_rdata[406] = \<const0> ;
assign s_axi_rdata[405] = \<const0> ;
assign s_axi_rdata[404] = \<const0> ;
assign s_axi_rdata[403] = \<const0> ;
assign s_axi_rdata[402] = \<const0> ;
assign s_axi_rdata[401] = \<const0> ;
assign s_axi_rdata[400] = \<const0> ;
assign s_axi_rdata[399] = \<const0> ;
assign s_axi_rdata[398] = \<const0> ;
assign s_axi_rdata[397] = \<const0> ;
assign s_axi_rdata[396] = \<const0> ;
assign s_axi_rdata[395] = \<const0> ;
assign s_axi_rdata[394] = \<const0> ;
assign s_axi_rdata[393] = \<const0> ;
assign s_axi_rdata[392] = \<const0> ;
assign s_axi_rdata[391] = \<const0> ;
assign s_axi_rdata[390] = \<const0> ;
assign s_axi_rdata[389] = \<const0> ;
assign s_axi_rdata[388] = \<const0> ;
assign s_axi_rdata[387] = \<const0> ;
assign s_axi_rdata[386] = \<const0> ;
assign s_axi_rdata[385] = \<const0> ;
assign s_axi_rdata[384] = \<const0> ;
assign s_axi_rdata[383] = \<const0> ;
assign s_axi_rdata[382] = \<const0> ;
assign s_axi_rdata[381] = \<const0> ;
assign s_axi_rdata[380] = \<const0> ;
assign s_axi_rdata[379] = \<const0> ;
assign s_axi_rdata[378] = \<const0> ;
assign s_axi_rdata[377] = \<const0> ;
assign s_axi_rdata[376] = \<const0> ;
assign s_axi_rdata[375] = \<const0> ;
assign s_axi_rdata[374] = \<const0> ;
assign s_axi_rdata[373] = \<const0> ;
assign s_axi_rdata[372] = \<const0> ;
assign s_axi_rdata[371] = \<const0> ;
assign s_axi_rdata[370] = \<const0> ;
assign s_axi_rdata[369] = \<const0> ;
assign s_axi_rdata[368] = \<const0> ;
assign s_axi_rdata[367] = \<const0> ;
assign s_axi_rdata[366] = \<const0> ;
assign s_axi_rdata[365] = \<const0> ;
assign s_axi_rdata[364] = \<const0> ;
assign s_axi_rdata[363] = \<const0> ;
assign s_axi_rdata[362] = \<const0> ;
assign s_axi_rdata[361] = \<const0> ;
assign s_axi_rdata[360] = \<const0> ;
assign s_axi_rdata[359] = \<const0> ;
assign s_axi_rdata[358] = \<const0> ;
assign s_axi_rdata[357] = \<const0> ;
assign s_axi_rdata[356] = \<const0> ;
assign s_axi_rdata[355] = \<const0> ;
assign s_axi_rdata[354] = \<const0> ;
assign s_axi_rdata[353] = \<const0> ;
assign s_axi_rdata[352] = \<const0> ;
assign s_axi_rdata[351] = \<const0> ;
assign s_axi_rdata[350] = \<const0> ;
assign s_axi_rdata[349] = \<const0> ;
assign s_axi_rdata[348] = \<const0> ;
assign s_axi_rdata[347] = \<const0> ;
assign s_axi_rdata[346] = \<const0> ;
assign s_axi_rdata[345] = \<const0> ;
assign s_axi_rdata[344] = \<const0> ;
assign s_axi_rdata[343] = \<const0> ;
assign s_axi_rdata[342] = \<const0> ;
assign s_axi_rdata[341] = \<const0> ;
assign s_axi_rdata[340] = \<const0> ;
assign s_axi_rdata[339] = \<const0> ;
assign s_axi_rdata[338] = \<const0> ;
assign s_axi_rdata[337] = \<const0> ;
assign s_axi_rdata[336] = \<const0> ;
assign s_axi_rdata[335] = \<const0> ;
assign s_axi_rdata[334] = \<const0> ;
assign s_axi_rdata[333] = \<const0> ;
assign s_axi_rdata[332] = \<const0> ;
assign s_axi_rdata[331] = \<const0> ;
assign s_axi_rdata[330] = \<const0> ;
assign s_axi_rdata[329] = \<const0> ;
assign s_axi_rdata[328] = \<const0> ;
assign s_axi_rdata[327] = \<const0> ;
assign s_axi_rdata[326] = \<const0> ;
assign s_axi_rdata[325] = \<const0> ;
assign s_axi_rdata[324] = \<const0> ;
assign s_axi_rdata[323] = \<const0> ;
assign s_axi_rdata[322] = \<const0> ;
assign s_axi_rdata[321] = \<const0> ;
assign s_axi_rdata[320] = \<const0> ;
assign s_axi_rdata[319] = \<const0> ;
assign s_axi_rdata[318] = \<const0> ;
assign s_axi_rdata[317] = \<const0> ;
assign s_axi_rdata[316] = \<const0> ;
assign s_axi_rdata[315] = \<const0> ;
assign s_axi_rdata[314] = \<const0> ;
assign s_axi_rdata[313] = \<const0> ;
assign s_axi_rdata[312] = \<const0> ;
assign s_axi_rdata[311] = \<const0> ;
assign s_axi_rdata[310] = \<const0> ;
assign s_axi_rdata[309] = \<const0> ;
assign s_axi_rdata[308] = \<const0> ;
assign s_axi_rdata[307] = \<const0> ;
assign s_axi_rdata[306] = \<const0> ;
assign s_axi_rdata[305] = \<const0> ;
assign s_axi_rdata[304] = \<const0> ;
assign s_axi_rdata[303] = \<const0> ;
assign s_axi_rdata[302] = \<const0> ;
assign s_axi_rdata[301] = \<const0> ;
assign s_axi_rdata[300] = \<const0> ;
assign s_axi_rdata[299] = \<const0> ;
assign s_axi_rdata[298] = \<const0> ;
assign s_axi_rdata[297] = \<const0> ;
assign s_axi_rdata[296] = \<const0> ;
assign s_axi_rdata[295] = \<const0> ;
assign s_axi_rdata[294] = \<const0> ;
assign s_axi_rdata[293] = \<const0> ;
assign s_axi_rdata[292] = \<const0> ;
assign s_axi_rdata[291] = \<const0> ;
assign s_axi_rdata[290] = \<const0> ;
assign s_axi_rdata[289] = \<const0> ;
assign s_axi_rdata[288] = \<const0> ;
assign s_axi_rdata[287] = \<const0> ;
assign s_axi_rdata[286] = \<const0> ;
assign s_axi_rdata[285] = \<const0> ;
assign s_axi_rdata[284] = \<const0> ;
assign s_axi_rdata[283] = \<const0> ;
assign s_axi_rdata[282] = \<const0> ;
assign s_axi_rdata[281] = \<const0> ;
assign s_axi_rdata[280] = \<const0> ;
assign s_axi_rdata[279] = \<const0> ;
assign s_axi_rdata[278] = \<const0> ;
assign s_axi_rdata[277] = \<const0> ;
assign s_axi_rdata[276] = \<const0> ;
assign s_axi_rdata[275] = \<const0> ;
assign s_axi_rdata[274] = \<const0> ;
assign s_axi_rdata[273] = \<const0> ;
assign s_axi_rdata[272] = \<const0> ;
assign s_axi_rdata[271] = \<const0> ;
assign s_axi_rdata[270] = \<const0> ;
assign s_axi_rdata[269] = \<const0> ;
assign s_axi_rdata[268] = \<const0> ;
assign s_axi_rdata[267] = \<const0> ;
assign s_axi_rdata[266] = \<const0> ;
assign s_axi_rdata[265] = \<const0> ;
assign s_axi_rdata[264] = \<const0> ;
assign s_axi_rdata[263] = \<const0> ;
assign s_axi_rdata[262] = \<const0> ;
assign s_axi_rdata[261] = \<const0> ;
assign s_axi_rdata[260] = \<const0> ;
assign s_axi_rdata[259] = \<const0> ;
assign s_axi_rdata[258] = \<const0> ;
assign s_axi_rdata[257] = \<const0> ;
assign s_axi_rdata[256] = \<const0> ;
assign s_axi_rdata[255] = \<const0> ;
assign s_axi_rdata[254] = \<const0> ;
assign s_axi_rdata[253] = \<const0> ;
assign s_axi_rdata[252] = \<const0> ;
assign s_axi_rdata[251] = \<const0> ;
assign s_axi_rdata[250] = \<const0> ;
assign s_axi_rdata[249] = \<const0> ;
assign s_axi_rdata[248] = \<const0> ;
assign s_axi_rdata[247] = \<const0> ;
assign s_axi_rdata[246] = \<const0> ;
assign s_axi_rdata[245] = \<const0> ;
assign s_axi_rdata[244] = \<const0> ;
assign s_axi_rdata[243] = \<const0> ;
assign s_axi_rdata[242] = \<const0> ;
assign s_axi_rdata[241] = \<const0> ;
assign s_axi_rdata[240] = \<const0> ;
assign s_axi_rdata[239] = \<const0> ;
assign s_axi_rdata[238] = \<const0> ;
assign s_axi_rdata[237] = \<const0> ;
assign s_axi_rdata[236] = \<const0> ;
assign s_axi_rdata[235] = \<const0> ;
assign s_axi_rdata[234] = \<const0> ;
assign s_axi_rdata[233] = \<const0> ;
assign s_axi_rdata[232] = \<const0> ;
assign s_axi_rdata[231] = \<const0> ;
assign s_axi_rdata[230] = \<const0> ;
assign s_axi_rdata[229] = \<const0> ;
assign s_axi_rdata[228] = \<const0> ;
assign s_axi_rdata[227] = \<const0> ;
assign s_axi_rdata[226] = \<const0> ;
assign s_axi_rdata[225] = \<const0> ;
assign s_axi_rdata[224] = \<const0> ;
assign s_axi_rdata[223] = \<const0> ;
assign s_axi_rdata[222] = \<const0> ;
assign s_axi_rdata[221] = \<const0> ;
assign s_axi_rdata[220] = \<const0> ;
assign s_axi_rdata[219] = \<const0> ;
assign s_axi_rdata[218] = \<const0> ;
assign s_axi_rdata[217] = \<const0> ;
assign s_axi_rdata[216] = \<const0> ;
assign s_axi_rdata[215] = \<const0> ;
assign s_axi_rdata[214] = \<const0> ;
assign s_axi_rdata[213] = \<const0> ;
assign s_axi_rdata[212] = \<const0> ;
assign s_axi_rdata[211] = \<const0> ;
assign s_axi_rdata[210] = \<const0> ;
assign s_axi_rdata[209] = \<const0> ;
assign s_axi_rdata[208] = \<const0> ;
assign s_axi_rdata[207] = \<const0> ;
assign s_axi_rdata[206] = \<const0> ;
assign s_axi_rdata[205] = \<const0> ;
assign s_axi_rdata[204] = \<const0> ;
assign s_axi_rdata[203] = \<const0> ;
assign s_axi_rdata[202] = \<const0> ;
assign s_axi_rdata[201] = \<const0> ;
assign s_axi_rdata[200] = \<const0> ;
assign s_axi_rdata[199] = \<const0> ;
assign s_axi_rdata[198] = \<const0> ;
assign s_axi_rdata[197] = \<const0> ;
assign s_axi_rdata[196] = \<const0> ;
assign s_axi_rdata[195] = \<const0> ;
assign s_axi_rdata[194] = \<const0> ;
assign s_axi_rdata[193] = \<const0> ;
assign s_axi_rdata[192] = \<const0> ;
assign s_axi_rdata[191] = \<const0> ;
assign s_axi_rdata[190] = \<const0> ;
assign s_axi_rdata[189] = \<const0> ;
assign s_axi_rdata[188] = \<const0> ;
assign s_axi_rdata[187] = \<const0> ;
assign s_axi_rdata[186] = \<const0> ;
assign s_axi_rdata[185] = \<const0> ;
assign s_axi_rdata[184] = \<const0> ;
assign s_axi_rdata[183] = \<const0> ;
assign s_axi_rdata[182] = \<const0> ;
assign s_axi_rdata[181] = \<const0> ;
assign s_axi_rdata[180] = \<const0> ;
assign s_axi_rdata[179] = \<const0> ;
assign s_axi_rdata[178] = \<const0> ;
assign s_axi_rdata[177] = \<const0> ;
assign s_axi_rdata[176] = \<const0> ;
assign s_axi_rdata[175] = \<const0> ;
assign s_axi_rdata[174] = \<const0> ;
assign s_axi_rdata[173] = \<const0> ;
assign s_axi_rdata[172] = \<const0> ;
assign s_axi_rdata[171] = \<const0> ;
assign s_axi_rdata[170] = \<const0> ;
assign s_axi_rdata[169] = \<const0> ;
assign s_axi_rdata[168] = \<const0> ;
assign s_axi_rdata[167] = \<const0> ;
assign s_axi_rdata[166] = \<const0> ;
assign s_axi_rdata[165] = \<const0> ;
assign s_axi_rdata[164] = \<const0> ;
assign s_axi_rdata[163] = \<const0> ;
assign s_axi_rdata[162] = \<const0> ;
assign s_axi_rdata[161] = \<const0> ;
assign s_axi_rdata[160] = \<const0> ;
assign s_axi_rdata[159] = \<const0> ;
assign s_axi_rdata[158] = \<const0> ;
assign s_axi_rdata[157] = \<const0> ;
assign s_axi_rdata[156] = \<const0> ;
assign s_axi_rdata[155] = \<const0> ;
assign s_axi_rdata[154] = \<const0> ;
assign s_axi_rdata[153] = \<const0> ;
assign s_axi_rdata[152] = \<const0> ;
assign s_axi_rdata[151] = \<const0> ;
assign s_axi_rdata[150] = \<const0> ;
assign s_axi_rdata[149] = \<const0> ;
assign s_axi_rdata[148] = \<const0> ;
assign s_axi_rdata[147] = \<const0> ;
assign s_axi_rdata[146] = \<const0> ;
assign s_axi_rdata[145] = \<const0> ;
assign s_axi_rdata[144] = \<const0> ;
assign s_axi_rdata[143] = \<const0> ;
assign s_axi_rdata[142] = \<const0> ;
assign s_axi_rdata[141] = \<const0> ;
assign s_axi_rdata[140] = \<const0> ;
assign s_axi_rdata[139] = \<const0> ;
assign s_axi_rdata[138] = \<const0> ;
assign s_axi_rdata[137] = \<const0> ;
assign s_axi_rdata[136] = \<const0> ;
assign s_axi_rdata[135] = \<const0> ;
assign s_axi_rdata[134] = \<const0> ;
assign s_axi_rdata[133] = \<const0> ;
assign s_axi_rdata[132] = \<const0> ;
assign s_axi_rdata[131] = \<const0> ;
assign s_axi_rdata[130] = \<const0> ;
assign s_axi_rdata[129] = \<const0> ;
assign s_axi_rdata[128] = \<const0> ;
assign s_axi_rdata[127] = \<const0> ;
assign s_axi_rdata[126] = \<const0> ;
assign s_axi_rdata[125] = \<const0> ;
assign s_axi_rdata[124] = \<const0> ;
assign s_axi_rdata[123] = \<const0> ;
assign s_axi_rdata[122] = \<const0> ;
assign s_axi_rdata[121] = \<const0> ;
assign s_axi_rdata[120] = \<const0> ;
assign s_axi_rdata[119] = \<const0> ;
assign s_axi_rdata[118] = \<const0> ;
assign s_axi_rdata[117] = \<const0> ;
assign s_axi_rdata[116] = \<const0> ;
assign s_axi_rdata[115] = \<const0> ;
assign s_axi_rdata[114] = \<const0> ;
assign s_axi_rdata[113] = \<const0> ;
assign s_axi_rdata[112] = \<const0> ;
assign s_axi_rdata[111] = \<const0> ;
assign s_axi_rdata[110] = \<const0> ;
assign s_axi_rdata[109] = \<const0> ;
assign s_axi_rdata[108] = \<const0> ;
assign s_axi_rdata[107] = \<const0> ;
assign s_axi_rdata[106] = \<const0> ;
assign s_axi_rdata[105] = \<const0> ;
assign s_axi_rdata[104] = \<const0> ;
assign s_axi_rdata[103] = \<const0> ;
assign s_axi_rdata[102] = \<const0> ;
assign s_axi_rdata[101] = \<const0> ;
assign s_axi_rdata[100] = \<const0> ;
assign s_axi_rdata[99] = \<const0> ;
assign s_axi_rdata[98] = \<const0> ;
assign s_axi_rdata[97] = \<const0> ;
assign s_axi_rdata[96] = \<const0> ;
assign s_axi_rdata[95] = \<const0> ;
assign s_axi_rdata[94] = \<const0> ;
assign s_axi_rdata[93] = \<const0> ;
assign s_axi_rdata[92] = \<const0> ;
assign s_axi_rdata[91] = \<const0> ;
assign s_axi_rdata[90] = \<const0> ;
assign s_axi_rdata[89] = \<const0> ;
assign s_axi_rdata[88] = \<const0> ;
assign s_axi_rdata[87] = \<const0> ;
assign s_axi_rdata[86] = \<const0> ;
assign s_axi_rdata[85] = \<const0> ;
assign s_axi_rdata[84] = \<const0> ;
assign s_axi_rdata[83] = \<const0> ;
assign s_axi_rdata[82] = \<const0> ;
assign s_axi_rdata[81] = \<const0> ;
assign s_axi_rdata[80] = \<const0> ;
assign s_axi_rdata[79] = \<const0> ;
assign s_axi_rdata[78] = \<const0> ;
assign s_axi_rdata[77] = \<const0> ;
assign s_axi_rdata[76] = \<const0> ;
assign s_axi_rdata[75] = \<const0> ;
assign s_axi_rdata[74] = \<const0> ;
assign s_axi_rdata[73] = \<const0> ;
assign s_axi_rdata[72] = \<const0> ;
assign s_axi_rdata[71] = \<const0> ;
assign s_axi_rdata[70] = \<const0> ;
assign s_axi_rdata[69] = \<const0> ;
assign s_axi_rdata[68] = \<const0> ;
assign s_axi_rdata[67] = \<const0> ;
assign s_axi_rdata[66] = \<const0> ;
assign s_axi_rdata[65] = \<const0> ;
assign s_axi_rdata[64] = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
About_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module About_blk_mem_gen_v8_2_synth
(douta,
clka,
addra);
output [799:0]douta;
input clka;
input [9:0]addra;
wire [9:0]addra;
wire clka;
wire [799:0]douta;
About_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.douta(douta));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module CapBoardDriver(clk500kHz,state,fets);
//INPUT:
//clk: Clock - designed to be 500 kHz
input clk500kHz;
//reg [3:0] clkCnt; //Count on clock edges to divide clock.
//state: state of board - which cap numbers are on. Each bit corresponds to
//cap bank (either serial or parallel).
input [3:0] state;
//OUTPUT:
//fets: gets signal that goes into MIC4427 drivers -
//should be a square wave at 500 kHz - divide clk/2^2.
output [7:0] fets;
//Send square wave to MOSFET drivers
//The number outside the curly braces, {4...}, is a repitition multiplier which serves
//to create a vector from the square wave for bitwise AND with the board state.
assign fets[3:0]={4{clk500kHz}} & state;
assign fets[7:4]=(~fets[3:0]) & state; //Invert square wave for 180-degree phase shift for push-pull transformer drive.
endmodule
//CODE GRAVEYARD
// //Initialize clock count variable.
// initial begin
// #0; //Act on zeroth simulation cycle.
// clkCnt=3'b0; //Zero.
// end
//
// //Act on clk positive edges.
// always @(posedge clk) begin
// //Divide clk to get slower square wave for driving transformers,
// //so increment counter.
// clkCnt=clkCnt+4'b1;
// end
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_1_V
`define SKY130_FD_SC_HDLL__DLXTN_1_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlxtn_1 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlxtn_1 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKBUF_BLACKBOX_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_BLACKBOX_V
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module vga(clk, r, g, b, hs, vs, cs_, oe_, we_, addr, data);
input clk;
output reg r;
output reg g;
output reg b;
output reg hs;
output reg vs;
input cs_;
input oe_;
input we_;
input [11:0] addr;
inout [7:0] data;
/* See http://martin.hinner.info/vga/vga.html
The VGA signal is composed of lines and frames. The frame is:
Active video -> front porch -> sync pulse (HS#) -> back porch
The lines are:
Active video (certain number of frames) -> front porch -> sync pulse (VS#) -> back porch
Note that during sync pulses, the green output is equal to HS ^ VS, and all sync pulses are
active low.
The 640x480 mode has the following characteristics:
VRefresh 60 Hz
HRefresh 31.5 kHz
Pixel frequency 25.175 MHz
Line:
Active video 640 pixels
Front porch 16 pixels
Sync pulse 96 pixels
Back porch 48 pixels
Thus a total of 800 pixels
Frame:
Active video 480 lines
Front porch 10 lines
Sync pulse 2 lines
Back porch 33 lines
Total of 525 lines
We assume modern monitors can cope with a slightly different frequency
and use a pixel frequency of 25 MHz instead, with the same 800x525 window.
This means that each pixel is displayed for a total of 2 clock cycles at
a input frequency of 50 MHz. This gives us three states per colour i.e.
11, 10 or 01 (these will be displayed the same) and 00. With 3 colours
(RGB) we can thus output up to 27 different colours. For any more we'd need
to use a PLL to multiply our clock sufficiently.
*/
reg [10:0] counterX = 11'd0; // count up to 1600 (2 counts per pixel)
reg [9:0] counterY = 10'd0; // count up to 525
parameter Width = 640;
parameter Height = 480;
parameter LineFrontPorch = 16;
parameter LineSyncPulse = 96;
parameter LineBackPorch = 48;
parameter FrameFrontPorch = 11;
parameter FrameSyncPulse = 2;
parameter FrameBackPorch = 31;
parameter ClocksPerPixel = 2;
localparam TotalLine = (Width + LineFrontPorch + LineSyncPulse + LineBackPorch) * ClocksPerPixel;
localparam TotalFrame = Height + FrameFrontPorch + FrameSyncPulse + FrameBackPorch;
localparam LWVal = Width * ClocksPerPixel;
localparam LFPVal = (Width + LineFrontPorch) * ClocksPerPixel;
localparam LSPVal = (Width + LineFrontPorch + LineSyncPulse) * ClocksPerPixel;
localparam FFPVal = Height + FrameFrontPorch;
localparam FSPVal = Height + FrameFrontPorch + FrameSyncPulse;
wire counterXMaxed = (counterX == TotalLine);
wire counterYMaxed = (counterY == TotalFrame);
always @(posedge clk)
if(counterXMaxed)
counterX <= 11'd0;
else
counterX <= counterX + 11'd1;
always @(posedge clk)
if(counterXMaxed)
if(counterYMaxed)
counterY <= 10'd0;
else
counterY <= counterY + 10'd1;
/* We implement a simple text based frame buffer with 80 x 25 characters. For 640x480 this means
the characters are 8 pixels across and 16 characters high (we lose the last 80 lines).
The character values in the RAM framebuffer reference a font in the ROM.
We can determine the framebuffer address of a given character by xchar + ychar * 2^charsAcrossLog -
ie round up CharsAcross to a power of 2 then use bit indexes to get the appropriate value
*/
parameter CharsAcross = 80;
parameter CharsAcrossLog = 7;
parameter CharsDown = 25;
parameter CharWidth = 8;
parameter CharHeight = 16;
parameter AllCharWidth = CharsAcross * CharWidth * ClocksPerPixel;
parameter AllCharHeight = CharsDown * CharHeight;
wire [6:0] xchar = (counterX < AllCharWidth) ? counterX[10:4] : 7'h7f;
wire xcharvalid = ~&xchar;
wire [6:0] ychar = (counterY < AllCharHeight) ? { 1'b0, counterY[9:4] } : 7'h7f;
wire ycharvalid = ~&ychar;
wire charvalid = xcharvalid & ycharvalid;
wire [11:0] mem_addr = { ychar[4:0], xchar[6:0] };
// Framebuffer - side A is CPU, side B is video
wire [7:0] fbuf_out;
wire [7:0] fbuf_out_to_cpu;
assign data = (~cs_ & ~oe_) ? fbuf_out_to_cpu : 8'bzzzzzzzz;
vga_ram ram_fb(.address_a(addr), .address_b(mem_addr), .clock_a(clk), .clock_b(clk), .data_a(data), .q_a(fbuf_out_to_cpu), .q_b(fbuf_out), .wren_a(~cs_ & ~we_), .wren_b(1'b0));
// ROM contains fonts
wire [2:0] charxbit = counterX[3:1];
wire [3:0] charybit = counterY[3:0];
wire [7:0] font_out;
// change to wire [11:0] font_addr = { fbuf_out[7:0],... } to support all 256 characters (requires 4 kiB font memory)
wire [11:0] font_addr = { fbuf_out[7:0], charybit };
vga_font_rom font_rom(.clock(clk), .address(font_addr), .q(font_out));
wire font_bit = font_out[charxbit] & charvalid;
always @(posedge clk)
if(counterY < Height)
begin
if(counterX < LWVal)
{ r, g, b, hs, vs } <= { font_bit, font_bit, font_bit, 1'b1, 1'b1 };
else if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
else if(counterY < FFPVal)
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
else if(counterY < FSPVal)
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 }; // note G also high here (VS^HS)
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 };
end
else
begin
if(counterX < LFPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
else if(counterX < LSPVal)
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 };
else
{ r, g, b, hs, vs } <= { 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 };
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/27 21:57:37
// Design Name:
// Module Name: Datapath_with_mux_adder_register_memory_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Datapath_with_mux_adder_register_memory_tb(
);
parameter DATA_WIDTH = 8;
reg Clk, reset, a_sel, next_sel, sum_sel;
reg [(DATA_WIDTH - 1):0] reset_value;
wire [(DATA_WIDTH - 1):0] a_o, next_o, sum_o, ld_next_o, ld_sum_o, add1_o, add2_o, mem_o;
wire next_zero;
integer i, j;
Datapath_with_mux_adder_register_memory #(DATA_WIDTH) DUT (.Clk(Clk), .reset(reset), .reset_value(reset_value), .a_sel(a_sel), .next_sel(next_sel), .sum_sel(sum_sel),
.a_o(a_o), .next_o(next_o), .sum_o(sum_o), .ld_next_o(ld_next_o), .ld_sum_o(ld_sum_o), .add1_o(add1_o), .add2_o(add2_o), .mem_o(mem_o), .next_zero(next_zero));
initial begin
#1000 $finish;
end
initial begin
Clk = 0;
for (i = 0; i < 100; i = i + 1) begin
#10 Clk = ~Clk;
end
end
initial begin
reset_value = {{(DATA_WIDTH/2){1'b0}}, {(DATA_WIDTH/2){1'b1}}};
reset = 1;
{a_sel, next_sel, sum_sel} = 7;
#40 reset = 0;
for (j = 7; j >= 0; j = j - 1) begin
#10 {a_sel, next_sel, sum_sel} = j;
#100;
end
end
endmodule
|
// bsg_front_side_bus_hop_in
//
// this implements the front side bus
// input side. it does *not* have backwards
// flow control, since nodes are supposed
// to have enough buffering to accept
// all incoming packets.
//
`include "bsg_defines.v"
module bsg_front_side_bus_hop_in_no_fc #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
// 0 is to the next switch
// 1 is to the local switch
, output [1:0][width_p-1:0] data_o
, output [1:0] v_o
, input local_accept_i
);
logic [width_p-1:0] data_r;
logic v_r;
// fixme: trade logic/speed for power
// and avoid fake transitions
assign data_o[0] = data_r;
assign v_o[0] = v_r;
// to local node
assign data_o[1] = data_r;
assign v_o[1] = v_r & local_accept_i;
bsg_dff_reset #( .width_p($bits(v_r)) )
v_reg
( .clk_i ( clk_i )
, .reset_i( reset_i )
, .data_i ( v_i )
, .data_o ( v_r )
);
bsg_dff #( .width_p($bits(data_r)) )
data_reg
( .clk_i ( clk_i )
, .data_i( data_i )
, .data_o( data_r )
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_front_side_bus_hop_in_no_fc)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
// single channel dds (dual tone)
module ad_dds #(
parameter DISABLE = 0,
// range 8-24
parameter DDS_DW = 16,
// range 8-16 (FIX ME)
parameter PHASE_DW = 16,
// set 1 for CORDIC or 2 for Polynomial
parameter DDS_TYPE = 1,
// range 8-24
parameter CORDIC_DW = 16,
// range 8-24 (make sure CORDIC_PHASE_DW < CORDIC_DW)
parameter CORDIC_PHASE_DW = 16,
// the clock radtio between the device clock(sample rate) and the dac_core clock
// 2^N, 1<N<6
parameter CLK_RATIO = 1) (
// interface
input clk,
input dac_dds_format,
input dac_data_sync,
input dac_valid,
input [ 15:0] tone_1_scale,
input [ 15:0] tone_2_scale,
input [ 15:0] tone_1_init_offset,
input [ 15:0] tone_2_init_offset,
input [ PHASE_DW-1:0] tone_1_freq_word,
input [ PHASE_DW-1:0] tone_2_freq_word,
output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data
);
wire [DDS_DW*CLK_RATIO-1:0] dac_dds_data_s;
always @(posedge clk) begin
dac_dds_data <= dac_dds_data_s;
end
genvar i;
generate
if (DISABLE == 1) begin
assign dac_dds_data_s = {(DDS_DW*CLK_RATIO-1){1'b0}};
end else begin
// enable dds
reg [PHASE_DW-1:0] dac_dds_phase_0[1:CLK_RATIO];
reg [PHASE_DW-1:0] dac_dds_phase_1[1:CLK_RATIO];
reg [PHASE_DW-1:0] dac_dds_incr_0 = 'd0;
reg [PHASE_DW-1:0] dac_dds_incr_1 = 'd0;
always @(posedge clk) begin
dac_dds_incr_0 <= tone_1_freq_word * CLK_RATIO;
dac_dds_incr_1 <= tone_2_freq_word * CLK_RATIO;
end
// phase accumulator
for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase
always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin
if (i == 1) begin
dac_dds_phase_0[1] <= tone_1_init_offset;
dac_dds_phase_1[1] <= tone_2_init_offset;
end else if (CLK_RATIO > 1)begin
dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
end
end else if (dac_valid == 1'b1) begin
dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
end
end
// phase to amplitude convertor
ad_dds_2 #(
.DDS_DW (DDS_DW),
.PHASE_DW (PHASE_DW),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (CORDIC_DW),
.CORDIC_PHASE_DW (CORDIC_PHASE_DW))
i_dds_2 (
.clk (clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0[i]),
.dds_scale_0 (tone_1_scale),
.dds_phase_1 (dac_dds_phase_1[i]),
.dds_scale_1 (tone_2_scale),
.dds_data (dac_dds_data_s[(DDS_DW*i)-1:DDS_DW*(i-1)]));
end
end
endgenerate
endmodule
|
module ibex_register_file (
clk_i,
rst_ni,
test_en_i,
raddr_a_i,
rdata_a_o,
raddr_b_i,
rdata_b_o,
waddr_a_i,
wdata_a_i,
we_a_i
);
parameter RV32E = 0;
parameter [31:0] DataWidth = 32;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire [4:0] raddr_a_i;
output wire [(DataWidth - 1):0] rdata_a_o;
input wire [4:0] raddr_b_i;
output wire [(DataWidth - 1):0] rdata_b_o;
input wire [4:0] waddr_a_i;
input wire [(DataWidth - 1):0] wdata_a_i;
input wire we_a_i;
localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
localparam [31:0] NUM_WORDS = (2 ** ADDR_WIDTH);
wire [(((NUM_WORDS - 1) >= 0) ? (((DataWidth - 1) >= 0) ? (((((NUM_WORDS - 1) >= 0) ? NUM_WORDS : (2 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + -1) : (((((NUM_WORDS - 1) >= 0) ? NUM_WORDS : (2 - NUM_WORDS)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + ((DataWidth - 1) - 1))) : (((DataWidth - 1) >= 0) ? ((((0 >= (NUM_WORDS - 1)) ? (2 - NUM_WORDS) : NUM_WORDS) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + (((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) - 1)) : ((((0 >= (NUM_WORDS - 1)) ? (2 - NUM_WORDS) : NUM_WORDS) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) - 1)))):(((NUM_WORDS - 1) >= 0) ? (((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) : (((DataWidth - 1) >= 0) ? ((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) : ((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)))))] rf_reg;
reg [(((NUM_WORDS - 1) >= 1) ? (((DataWidth - 1) >= 0) ? (((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + ((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) - 1)) : (((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) - 1))) : (((DataWidth - 1) >= 0) ? ((((1 >= (NUM_WORDS - 1)) ? (3 - NUM_WORDS) : (NUM_WORDS - 1)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + (((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) - 1)) : ((((1 >= (NUM_WORDS - 1)) ? (3 - NUM_WORDS) : (NUM_WORDS - 1)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) - 1)))):(((NUM_WORDS - 1) >= 1) ? (((DataWidth - 1) >= 0) ? (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) : ((DataWidth - 1) + ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) : (((DataWidth - 1) >= 0) ? ((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) : ((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)))))] rf_reg_tmp;
reg [(NUM_WORDS - 1):1] we_a_dec;
always @(*) begin : we_a_decoder
begin : sv2v_autoblock_2
reg [31:0] i;
for (i = 1; (i < NUM_WORDS); i = (i + 1))
we_a_dec[i] = ((waddr_a_i == sv2v_cast_5(i)) ? we_a_i : 1'b0);
end
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rf_reg_tmp <= {(((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) {1'sb0}};
else begin : sv2v_autoblock_3
reg signed [31:0] r;
for (r = 1; (r < NUM_WORDS); r = (r + 1))
if (we_a_dec[r])
rf_reg_tmp[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 1) ? r : (1 - (r - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] <= wdata_a_i;
end
assign rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? 0 : (NUM_WORDS - 1)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] = 1'sb0;
assign rf_reg[(((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) + ((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)))) - 1):(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] = rf_reg_tmp[(((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) + ((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)))) - 1):(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
assign rdata_a_o = rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? raddr_a_i : (0 - (raddr_a_i - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
assign rdata_b_o = rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? raddr_b_i : (0 - (raddr_b_i - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
function automatic [4:0] sv2v_cast_5;
input reg [4:0] inp;
sv2v_cast_5 = inp;
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LP__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222o (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X, and1_out, and0_out, and2_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_FUNCTIONAL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:18:08 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_81 ( CLK, EN, ENCLK, TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_21 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_23 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_26 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_27 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_29 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_32 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch3v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire enab_d_ff4_Zn, enab_d_ff_RB1, enab_RB3, enab_d_ff5_data_out,
d_ff3_sign_out, enab_d_ff4_Yn, enab_d_ff4_Xn, fmtted_Result_63_,
ITER_CONT_net3844161, ITER_CONT_N3, d_ff5_data_out_net3844125,
reg_Z0_net3844125, reg_val_muxZ_2stage_net3844125,
reg_shift_y_net3844125, d_ff4_Xn_net3844125, d_ff4_Yn_net3844125,
d_ff4_Zn_net3844125, n249, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n992, n993, n994, n995, n996, n997, n998, n999, n1000,
n1001, n1002, n1003, intadd_465_CI, intadd_465_n3, intadd_465_n2,
intadd_465_n1, intadd_466_CI, intadd_466_n3, intadd_466_n2,
intadd_466_n1, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] first_mux_X;
wire [63:0] d_ff_Yn;
wire [63:0] first_mux_Y;
wire [63:0] d_ff_Zn;
wire [63:0] first_mux_Z;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [10:0] sh_exp_x;
wire [10:0] sh_exp_y;
wire [54:0] data_out_LUT;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [62:0] mux_sal;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4_81 ITER_CONT_clk_gate_temp_reg (
.CLK(clk), .EN(enab_cont_iter), .ENCLK(ITER_CONT_net3844161), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_21 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3844125),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_32 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff_RB1), .ENCLK(reg_Z0_net3844125), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_29 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
reg_val_muxZ_2stage_net3844125), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_27 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_RB3), .ENCLK(reg_shift_y_net3844125), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_26 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3844125), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_24 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3844125), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_23 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3844125), .TE(1'b0) );
DFFRXLTS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3844125),
.RN(n1442), .QN(n1139) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3844125), .RN(n1427), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n1144) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(data_out_LUT[0]), .CK(reg_shift_y_net3844125),
.RN(n1442), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n968), .CK(reg_shift_y_net3844125), .RN(n1408), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n990), .CK(reg_shift_y_net3844125), .RN(n1437), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(n962), .CK(reg_shift_y_net3844125), .RN(n1417), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n971), .CK(reg_shift_y_net3844125), .RN(n1419), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n994), .CK(reg_shift_y_net3844125), .RN(n1436), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(data_out_LUT[6]), .CK(reg_shift_y_net3844125),
.RN(n249), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n989), .CK(reg_shift_y_net3844125), .RN(n1436), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n993), .CK(reg_shift_y_net3844125), .RN(n1443), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n963), .CK(reg_shift_y_net3844125), .RN(n1426), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n982), .CK(reg_shift_y_net3844125), .RN(
n1410), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n965), .CK(reg_shift_y_net3844125), .RN(
n1443), .Q(d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n999), .CK(reg_shift_y_net3844125), .RN(
n1432), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n969), .CK(reg_shift_y_net3844125), .RN(
n1443), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n987), .CK(reg_shift_y_net3844125), .RN(
n1436), .Q(d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n964), .CK(reg_shift_y_net3844125), .RN(
n1432), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n992), .CK(reg_shift_y_net3844125), .RN(
n1432), .Q(d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n995), .CK(reg_shift_y_net3844125), .RN(
n1441), .Q(d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n973), .CK(reg_shift_y_net3844125), .RN(
n1442), .Q(d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n996), .CK(reg_shift_y_net3844125), .RN(
n1432), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n1000), .CK(reg_shift_y_net3844125), .RN(
n1432), .Q(d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n970), .CK(reg_shift_y_net3844125), .RN(
n1412), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n1003), .CK(reg_shift_y_net3844125), .RN(
n1444), .Q(d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n979), .CK(reg_shift_y_net3844125), .RN(
n1433), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n978), .CK(reg_shift_y_net3844125), .RN(
n1441), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(n984), .CK(reg_shift_y_net3844125), .RN(
n1442), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n980), .CK(reg_shift_y_net3844125), .RN(
n1409), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n966), .CK(reg_shift_y_net3844125), .RN(
n1438), .Q(d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n975), .CK(reg_shift_y_net3844125), .RN(
n1423), .Q(d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n986), .CK(reg_shift_y_net3844125), .RN(
n1444), .Q(d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n981), .CK(reg_shift_y_net3844125), .RN(
n1433), .Q(d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n974), .CK(reg_shift_y_net3844125), .RN(
n1441), .Q(d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n967), .CK(reg_shift_y_net3844125), .RN(
n1442), .Q(d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n976), .CK(reg_shift_y_net3844125), .RN(
n1424), .Q(d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n972), .CK(reg_shift_y_net3844125), .RN(
n1428), .Q(d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n1146), .CK(reg_shift_y_net3844125), .RN(
n1436), .Q(d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(data_out_LUT[39]), .CK(
reg_shift_y_net3844125), .RN(n1444), .Q(d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n977), .CK(reg_shift_y_net3844125), .RN(
n1433), .Q(d_ff3_LUT_out[41]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n998), .CK(reg_shift_y_net3844125), .RN(
n1441), .Q(d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n1002), .CK(reg_shift_y_net3844125), .RN(
n1442), .Q(d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n1001), .CK(reg_shift_y_net3844125), .RN(
n1426), .Q(d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n997), .CK(reg_shift_y_net3844125), .RN(
n1429), .Q(d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n1407), .CK(reg_shift_y_net3844125), .RN(
n1443), .Q(d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n988), .CK(reg_shift_y_net3844125), .RN(
n1444), .Q(d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(data_out_LUT[54]), .CK(
reg_shift_y_net3844125), .RN(n1433), .Q(d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n983), .CK(reg_shift_y_net3844125), .RN(
n1441), .Q(d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n985), .CK(reg_shift_y_net3844125), .RN(
n1442), .Q(d_ff3_LUT_out[56]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3844125), .RN(n1410), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3844125), .RN(n1415), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3844125), .RN(n1421), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3844125), .RN(n1444), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3844125), .RN(n1433), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3844125), .RN(n1441), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3844125), .RN(n1412), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3844125), .RN(n1436), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3844125), .RN(n1412), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3844125), .RN(n1436), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3844125), .RN(
n1432), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3844125), .RN(
n1436), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3844125), .RN(
n1423), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3844125), .RN(
n1443), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3844125), .RN(
n1423), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3844125), .RN(
n1443), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3844125), .RN(
n1408), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3844125), .RN(
n1443), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3844125), .RN(
n1438), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3844125), .RN(
n1437), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3844125), .RN(
n1434), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3844125), .RN(
n1438), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3844125), .RN(
n1434), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3844125), .RN(
n1440), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3844125), .RN(
n1411), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3844125), .RN(
n1416), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3844125), .RN(
n1440), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3844125), .RN(
n1411), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3844125), .RN(
n1440), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3844125), .RN(
n1416), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3844125), .RN(
n1439), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3844125), .RN(
n1431), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(data_in[32]), .CK(reg_Z0_net3844125), .RN(
n1435), .Q(d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(data_in[33]), .CK(reg_Z0_net3844125), .RN(
n1447), .Q(d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(data_in[34]), .CK(reg_Z0_net3844125), .RN(
n1422), .Q(d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(data_in[35]), .CK(reg_Z0_net3844125), .RN(
n1414), .Q(d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(data_in[36]), .CK(reg_Z0_net3844125), .RN(
n1439), .Q(d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(data_in[37]), .CK(reg_Z0_net3844125), .RN(
n1431), .Q(d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(data_in[38]), .CK(reg_Z0_net3844125), .RN(
n1435), .Q(d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(data_in[39]), .CK(reg_Z0_net3844125), .RN(
n1447), .Q(d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(data_in[40]), .CK(reg_Z0_net3844125), .RN(
n1422), .Q(d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(data_in[41]), .CK(reg_Z0_net3844125), .RN(
n1414), .Q(d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(data_in[42]), .CK(reg_Z0_net3844125), .RN(
n1433), .Q(d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(data_in[43]), .CK(reg_Z0_net3844125), .RN(
n1427), .Q(d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(data_in[44]), .CK(reg_Z0_net3844125), .RN(
n1422), .Q(d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(data_in[45]), .CK(reg_Z0_net3844125), .RN(
n1425), .Q(d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(data_in[46]), .CK(reg_Z0_net3844125), .RN(
n1427), .Q(d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(data_in[47]), .CK(reg_Z0_net3844125), .RN(
n1424), .Q(d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(data_in[48]), .CK(reg_Z0_net3844125), .RN(
n1446), .Q(d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(data_in[49]), .CK(reg_Z0_net3844125), .RN(
n1425), .Q(d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(data_in[50]), .CK(reg_Z0_net3844125), .RN(
n1446), .Q(d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(data_in[51]), .CK(reg_Z0_net3844125), .RN(
n1427), .Q(d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(data_in[52]), .CK(reg_Z0_net3844125), .RN(
n1137), .Q(d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(data_in[53]), .CK(reg_Z0_net3844125), .RN(
n1425), .Q(d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(data_in[54]), .CK(reg_Z0_net3844125), .RN(
n1137), .Q(d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(data_in[55]), .CK(reg_Z0_net3844125), .RN(
n1137), .Q(d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(data_in[56]), .CK(reg_Z0_net3844125), .RN(
n1446), .Q(d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(data_in[57]), .CK(reg_Z0_net3844125), .RN(
n1446), .Q(d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(data_in[58]), .CK(reg_Z0_net3844125), .RN(
n1136), .Q(d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(data_in[59]), .CK(reg_Z0_net3844125), .RN(
n1136), .Q(d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(data_in[60]), .CK(reg_Z0_net3844125), .RN(
n1428), .Q(d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(data_in[61]), .CK(reg_Z0_net3844125), .RN(
n1429), .Q(d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(data_in[62]), .CK(reg_Z0_net3844125), .RN(
n1415), .Q(d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(data_in[63]), .CK(reg_Z0_net3844125), .RN(
n1137), .Q(d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3844125), .RN(n1137), .Q(d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3844125), .RN(n1446), .Q(d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3844125), .RN(n1438), .Q(d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3844125), .RN(n1440), .Q(d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3844125), .RN(n1416), .Q(d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3844125), .RN(n1411), .Q(d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(sh_exp_x[8]), .CK(reg_shift_y_net3844125), .RN(n1440), .Q(d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(sh_exp_x[9]), .CK(reg_shift_y_net3844125), .RN(n1411), .Q(d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(sh_exp_x[10]), .CK(
reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3844125), .RN(n1440), .Q(d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3844125), .RN(n1437), .Q(d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3844125), .RN(n1416), .Q(d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3844125), .RN(n1416), .Q(d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3844125), .RN(n1416), .Q(d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3844125), .RN(n1438), .Q(d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(sh_exp_y[8]), .CK(reg_shift_y_net3844125), .RN(n1440), .Q(d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(sh_exp_y[9]), .CK(reg_shift_y_net3844125), .RN(n1437), .Q(d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(sh_exp_y[10]), .CK(
reg_shift_y_net3844125), .RN(n1437), .Q(d_ff3_sh_y_out[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3844125), .RN(n1437), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1440), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3844125),
.RN(n1411), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3844125), .RN(n1434), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1412), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3844125),
.RN(n1412), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3844125), .RN(n1423), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1436), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3844125),
.RN(n1412), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3844125), .RN(n1412), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1423), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3844125),
.RN(n1423), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3844125), .RN(n1412), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1443), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3844125),
.RN(n1423), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3844125), .RN(n1423), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3844125),
.RN(n249), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3844125), .RN(n249), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3844125),
.RN(n249), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3844125), .RN(n1432), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3844125),
.RN(n249), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1420), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3844125),
.RN(n1138), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3844125), .RN(n1445), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1414), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3844125),
.RN(n1439), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3844125), .RN(n1431), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1435), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3844125), .RN(n1447), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3844125), .RN(n1414), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3844125), .RN(n1435), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1447), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3844125), .RN(n1422), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3844125), .RN(n1414), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1411), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3844125), .RN(n1434), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3844125), .RN(n1416), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1416), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3844125), .RN(n1416), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3844125), .RN(n1437), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1438), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3844125), .RN(n1440), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3844125), .RN(n1437), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1437), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3844125), .RN(n1437), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3844125), .RN(n1415), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3844125), .RN(n1137), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3844125), .RN(n1137), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3844125), .RN(n1446), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(d_ff2_X[23]), .CK(reg_shift_y_net3844125), .RN(n1136), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3844125), .RN(n1136), .Q(d_ff_Xn[24]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_X[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(d_ff2_X[24]), .CK(reg_shift_y_net3844125), .RN(n1429), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[25]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1442), .Q(d_ff2_X[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(d_ff2_X[25]), .CK(reg_shift_y_net3844125), .RN(n1433), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3844125), .RN(n1411), .Q(d_ff_Xn[26]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(d_ff2_X[26]), .CK(reg_shift_y_net3844125), .RN(n1444), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3844125), .RN(n1433), .Q(d_ff_Xn[27]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1441), .Q(d_ff2_X[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(d_ff2_X[27]), .CK(reg_shift_y_net3844125), .RN(n1442), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3844125), .RN(n1444), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(d_ff2_X[28]), .CK(reg_shift_y_net3844125), .RN(n249), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3844125), .RN(n1444), .Q(d_ff_Xn[29]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_X[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(d_ff2_X[29]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_X[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(d_ff2_X[30]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[32]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_32_ ( .D(first_mux_X[32]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_X[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(d_ff2_X[32]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_x_out[32]) );
DFFRXLTS d_ff4_Xn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[33]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_33_ ( .D(first_mux_X[33]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1433), .Q(d_ff2_X[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(d_ff2_X[33]), .CK(reg_shift_y_net3844125), .RN(n1441), .Q(d_ff3_sh_x_out[33]) );
DFFRXLTS d_ff4_Xn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Xn_net3844125), .RN(n1442), .Q(d_ff_Xn[34]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_34_ ( .D(first_mux_X[34]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_X[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(d_ff2_X[34]), .CK(reg_shift_y_net3844125), .RN(n1137), .Q(d_ff3_sh_x_out[34]) );
DFFRXLTS d_ff4_Xn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Xn_net3844125), .RN(n249), .Q(d_ff_Xn[35]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_35_ ( .D(first_mux_X[35]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1444), .Q(d_ff2_X[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(d_ff2_X[35]), .CK(reg_shift_y_net3844125), .RN(n1433), .Q(d_ff3_sh_x_out[35]) );
DFFRXLTS d_ff4_Xn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Xn_net3844125), .RN(n1441), .Q(d_ff_Xn[36]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_36_ ( .D(first_mux_X[36]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1442), .Q(d_ff2_X[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(d_ff2_X[36]), .CK(reg_shift_y_net3844125), .RN(n1441), .Q(d_ff3_sh_x_out[36]) );
DFFRXLTS d_ff4_Xn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Xn_net3844125), .RN(n1136), .Q(d_ff_Xn[37]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_37_ ( .D(first_mux_X[37]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(d_ff2_X[37]), .CK(reg_shift_y_net3844125), .RN(n1432), .Q(d_ff3_sh_x_out[37]) );
DFFRXLTS d_ff4_Xn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Xn_net3844125), .RN(n1445), .Q(d_ff_Xn[38]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_38_ ( .D(first_mux_X[38]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(d_ff2_X[38]), .CK(reg_shift_y_net3844125), .RN(n1432), .Q(d_ff3_sh_x_out[38]) );
DFFRXLTS d_ff4_Xn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Xn_net3844125), .RN(n1445), .Q(d_ff_Xn[39]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_39_ ( .D(first_mux_X[39]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(d_ff2_X[39]), .CK(reg_shift_y_net3844125), .RN(n1432), .Q(d_ff3_sh_x_out[39]) );
DFFRXLTS d_ff4_Xn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Xn_net3844125), .RN(n1445), .Q(d_ff_Xn[40]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_40_ ( .D(first_mux_X[40]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n249), .Q(d_ff2_X[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(d_ff2_X[40]), .CK(reg_shift_y_net3844125), .RN(n1432), .Q(d_ff3_sh_x_out[40]) );
DFFRXLTS d_ff4_Xn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Xn_net3844125), .RN(n1445), .Q(d_ff_Xn[41]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_41_ ( .D(first_mux_X[41]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_X[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(d_ff2_X[41]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_x_out[41]) );
DFFRXLTS d_ff4_Xn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Xn_net3844125), .RN(n1435), .Q(d_ff_Xn[42]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_42_ ( .D(first_mux_X[42]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1447), .Q(d_ff2_X[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(d_ff2_X[42]), .CK(reg_shift_y_net3844125), .RN(n1422), .Q(d_ff3_sh_x_out[42]) );
DFFRXLTS d_ff4_Xn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Xn_net3844125), .RN(n1414), .Q(d_ff_Xn[43]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_43_ ( .D(first_mux_X[43]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_X[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(d_ff2_X[43]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_x_out[43]) );
DFFRXLTS d_ff4_Xn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Xn_net3844125), .RN(n1435), .Q(d_ff_Xn[44]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_44_ ( .D(first_mux_X[44]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1447), .Q(d_ff2_X[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(d_ff2_X[44]), .CK(reg_shift_y_net3844125), .RN(n1422), .Q(d_ff3_sh_x_out[44]) );
DFFRXLTS d_ff4_Xn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Xn_net3844125), .RN(n1414), .Q(d_ff_Xn[45]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_45_ ( .D(first_mux_X[45]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_X[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(d_ff2_X[45]), .CK(reg_shift_y_net3844125), .RN(n1412), .Q(d_ff3_sh_x_out[45]) );
DFFRXLTS d_ff4_Xn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Xn_net3844125), .RN(n1408), .Q(d_ff_Xn[46]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_46_ ( .D(first_mux_X[46]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1412), .Q(d_ff2_X[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(d_ff2_X[46]), .CK(reg_shift_y_net3844125), .RN(n1436), .Q(d_ff3_sh_x_out[46]) );
DFFRXLTS d_ff4_Xn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Xn_net3844125), .RN(n1432), .Q(d_ff_Xn[47]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_47_ ( .D(first_mux_X[47]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1432), .Q(d_ff2_X[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(d_ff2_X[47]), .CK(reg_shift_y_net3844125), .RN(n1423), .Q(d_ff3_sh_x_out[47]) );
DFFRXLTS d_ff4_Xn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Xn_net3844125), .RN(n1432), .Q(d_ff_Xn[48]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_48_ ( .D(first_mux_X[48]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1423), .Q(d_ff2_X[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(d_ff2_X[48]), .CK(reg_shift_y_net3844125), .RN(n1443), .Q(d_ff3_sh_x_out[48]) );
DFFRXLTS d_ff4_Xn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Xn_net3844125), .RN(n1438), .Q(d_ff_Xn[49]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_49_ ( .D(first_mux_X[49]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_X[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(d_ff2_X[49]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_x_out[49]) );
DFFRXLTS d_ff4_Xn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Xn_net3844125), .RN(n1429), .Q(d_ff_Xn[50]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_50_ ( .D(first_mux_X[50]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1415), .Q(d_ff2_X[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(d_ff2_X[50]), .CK(reg_shift_y_net3844125), .RN(n1137), .Q(d_ff3_sh_x_out[50]) );
DFFRXLTS d_ff4_Xn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Xn_net3844125), .RN(n1137), .Q(d_ff_Xn[51]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_51_ ( .D(first_mux_X[51]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(d_ff2_X[51]), .CK(reg_shift_y_net3844125), .RN(n1446), .Q(d_ff3_sh_x_out[51]) );
DFFRXLTS d_ff4_Xn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Xn_net3844125), .RN(n1136), .Q(d_ff_Xn[52]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(first_mux_X[52]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_X[52]), .QN(
n1143) );
DFFRXLTS d_ff4_Xn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Xn_net3844125), .RN(n1428), .Q(d_ff_Xn[53]) );
DFFRXLTS d_ff4_Xn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Xn_net3844125), .RN(n1136), .Q(d_ff_Xn[54]) );
DFFRXLTS d_ff4_Xn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Xn_net3844125), .RN(n1136), .Q(d_ff_Xn[55]) );
DFFRXLTS d_ff4_Xn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Xn_net3844125), .RN(n1428), .Q(d_ff_Xn[56]) );
DFFRXLTS d_ff4_Xn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Xn_net3844125), .RN(n1429), .Q(d_ff_Xn[57]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_57_ ( .D(first_mux_X[57]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_X[57]), .QN(
n1405) );
DFFRXLTS d_ff4_Xn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Xn_net3844125), .RN(n1415), .Q(d_ff_Xn[58]) );
DFFRXLTS d_ff4_Xn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Xn_net3844125), .RN(n1446), .Q(d_ff_Xn[59]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_59_ ( .D(first_mux_X[59]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[59]) );
DFFRXLTS d_ff4_Xn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Xn_net3844125), .RN(n1430), .Q(d_ff_Xn[60]) );
DFFRXLTS d_ff4_Xn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Xn_net3844125), .RN(n1430), .Q(d_ff_Xn[61]) );
DFFRXLTS d_ff4_Xn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Xn_net3844125), .RN(n1430), .Q(d_ff_Xn[62]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_62_ ( .D(first_mux_X[62]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1430), .Q(d_ff2_X[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Xn_net3844125), .RN(n1430), .Q(d_ff_Xn[63]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_63_ ( .D(first_mux_X[63]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1430), .Q(d_ff2_X[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(d_ff2_X[63]), .CK(reg_shift_y_net3844125), .RN(n1430), .Q(d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3844125), .RN(n1430), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1430), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3844125),
.RN(n1445), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(mux_sal[0]), .CK(
d_ff5_data_out_net3844125), .RN(n1415), .Q(data_output[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3844125), .RN(n1137), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3844125),
.RN(n1446), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(mux_sal[1]), .CK(
d_ff5_data_out_net3844125), .RN(n1446), .Q(data_output[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3844125), .RN(n1136), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3844125),
.RN(n1428), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(mux_sal[2]), .CK(
d_ff5_data_out_net3844125), .RN(n1429), .Q(data_output[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3844125), .RN(n1415), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3844125),
.RN(n1137), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(mux_sal[3]), .CK(
d_ff5_data_out_net3844125), .RN(n1446), .Q(data_output[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3844125), .RN(n1446), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3844125),
.RN(n1136), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(mux_sal[4]), .CK(
d_ff5_data_out_net3844125), .RN(n1428), .Q(data_output[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3844125), .RN(n1429), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1415), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3844125),
.RN(n1137), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(mux_sal[5]), .CK(
d_ff5_data_out_net3844125), .RN(n1137), .Q(data_output[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3844125), .RN(n1446), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3844125),
.RN(n1136), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(mux_sal[6]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3844125),
.RN(n1427), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(mux_sal[7]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3844125),
.RN(n1427), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(mux_sal[8]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3844125),
.RN(n1427), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(mux_sal[9]), .CK(
d_ff5_data_out_net3844125), .RN(n1419), .Q(data_output[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3844125), .RN(n1446), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3844125), .RN(n1409), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(mux_sal[10]), .CK(
d_ff5_data_out_net3844125), .RN(n1409), .Q(data_output[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3844125), .RN(n1410), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1426), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3844125), .RN(n1424), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(mux_sal[11]), .CK(
d_ff5_data_out_net3844125), .RN(n1410), .Q(data_output[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3844125), .RN(n1426), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3844125), .RN(n1408), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(mux_sal[12]), .CK(
d_ff5_data_out_net3844125), .RN(n1426), .Q(data_output[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3844125), .RN(n1426), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1426), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3844125), .RN(n1426), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(mux_sal[13]), .CK(
d_ff5_data_out_net3844125), .RN(n1426), .Q(data_output[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3844125), .RN(n1426), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1426), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3844125), .RN(n1426), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(mux_sal[14]), .CK(
d_ff5_data_out_net3844125), .RN(n1426), .Q(data_output[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3844125), .RN(n1426), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1426), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3844125), .RN(n1426), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(mux_sal[15]), .CK(
d_ff5_data_out_net3844125), .RN(n1410), .Q(data_output[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3844125), .RN(n1425), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1410), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3844125), .RN(n1425), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(mux_sal[16]), .CK(
d_ff5_data_out_net3844125), .RN(n1410), .Q(data_output[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3844125), .RN(n1425), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1410), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3844125), .RN(n1425), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(mux_sal[17]), .CK(
d_ff5_data_out_net3844125), .RN(n1410), .Q(data_output[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3844125), .RN(n1425), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1410), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3844125), .RN(n1425), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(mux_sal[18]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3844125), .RN(n1427), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(mux_sal[19]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3844125), .RN(n1427), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(mux_sal[20]), .CK(
d_ff5_data_out_net3844125), .RN(n1424), .Q(data_output[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3844125), .RN(n1427), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1424), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3844125), .RN(n1427), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(mux_sal[21]), .CK(
d_ff5_data_out_net3844125), .RN(n1436), .Q(data_output[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3844125), .RN(n1423), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1438), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3844125), .RN(n1428), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(mux_sal[22]), .CK(
d_ff5_data_out_net3844125), .RN(n1436), .Q(data_output[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3844125), .RN(n1436), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1443), .Q(d_ff2_Y[23]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(d_ff2_Y[23]), .CK(reg_shift_y_net3844125), .RN(n1412), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(mux_sal[23]), .CK(
d_ff5_data_out_net3844125), .RN(n1432), .Q(data_output[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3844125), .RN(n1432), .Q(d_ff_Yn[24]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1443), .Q(d_ff2_Y[24]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(d_ff2_Y[24]), .CK(reg_shift_y_net3844125), .RN(n1443), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(mux_sal[24]), .CK(
d_ff5_data_out_net3844125), .RN(n1422), .Q(data_output[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3844125), .RN(n1414), .Q(d_ff_Yn[25]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_Y[25]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(d_ff2_Y[25]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(mux_sal[25]), .CK(
d_ff5_data_out_net3844125), .RN(n1435), .Q(data_output[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3844125), .RN(n1447), .Q(d_ff_Yn[26]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1422), .Q(d_ff2_Y[26]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(d_ff2_Y[26]), .CK(reg_shift_y_net3844125), .RN(n1414), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(mux_sal[26]), .CK(
d_ff5_data_out_net3844125), .RN(n1439), .Q(data_output[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3844125), .RN(n1431), .Q(d_ff_Yn[27]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1435), .Q(d_ff2_Y[27]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(d_ff2_Y[27]), .CK(reg_shift_y_net3844125), .RN(n1447), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(mux_sal[27]), .CK(
d_ff5_data_out_net3844125), .RN(n1445), .Q(data_output[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3844125), .RN(n1439), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1440), .Q(d_ff2_Y[28]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(d_ff2_Y[28]), .CK(reg_shift_y_net3844125), .RN(n1429), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(mux_sal[28]), .CK(
d_ff5_data_out_net3844125), .RN(n1428), .Q(data_output[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3844125), .RN(n1434), .Q(d_ff_Yn[29]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_Y[29]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(d_ff2_Y[29]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(mux_sal[29]), .CK(
d_ff5_data_out_net3844125), .RN(n1438), .Q(data_output[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3844125), .RN(n1414), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1432), .Q(d_ff2_Y[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(d_ff2_Y[30]), .CK(reg_shift_y_net3844125), .RN(n1414), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(mux_sal[30]), .CK(
d_ff5_data_out_net3844125), .RN(n1414), .Q(data_output[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3844125), .RN(n1431), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1416), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(mux_sal[31]), .CK(
d_ff5_data_out_net3844125), .RN(n1439), .Q(data_output[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Yn_net3844125), .RN(n1439), .Q(d_ff_Yn[32]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_32_ ( .D(first_mux_Y[32]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1437), .Q(d_ff2_Y[32]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(d_ff2_Y[32]), .CK(reg_shift_y_net3844125), .RN(n1415), .Q(d_ff3_sh_y_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(mux_sal[32]), .CK(
d_ff5_data_out_net3844125), .RN(n1445), .Q(data_output[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Yn_net3844125), .RN(n1422), .Q(d_ff_Yn[33]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_33_ ( .D(first_mux_Y[33]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1412), .Q(d_ff2_Y[33]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(d_ff2_Y[33]), .CK(reg_shift_y_net3844125), .RN(n1438), .Q(d_ff3_sh_y_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(mux_sal[33]), .CK(
d_ff5_data_out_net3844125), .RN(n1421), .Q(data_output[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Yn_net3844125), .RN(n1138), .Q(d_ff_Yn[34]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_34_ ( .D(first_mux_Y[34]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1415), .Q(d_ff2_Y[34]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(d_ff2_Y[34]), .CK(reg_shift_y_net3844125), .RN(n1429), .Q(d_ff3_sh_y_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(mux_sal[34]), .CK(
d_ff5_data_out_net3844125), .RN(n1428), .Q(data_output[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Yn_net3844125), .RN(n1438), .Q(d_ff_Yn[35]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_35_ ( .D(first_mux_Y[35]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_Y[35]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(d_ff2_Y[35]), .CK(reg_shift_y_net3844125), .RN(n1138), .Q(d_ff3_sh_y_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(mux_sal[35]), .CK(
d_ff5_data_out_net3844125), .RN(n1415), .Q(data_output[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Yn_net3844125), .RN(n1429), .Q(d_ff_Yn[36]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_36_ ( .D(first_mux_Y[36]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_Y[36]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(d_ff2_Y[36]), .CK(reg_shift_y_net3844125), .RN(n1438), .Q(d_ff3_sh_y_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(mux_sal[36]), .CK(
d_ff5_data_out_net3844125), .RN(n1445), .Q(data_output[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Yn_net3844125), .RN(n1446), .Q(d_ff_Yn[37]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_37_ ( .D(first_mux_Y[37]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1422), .Q(d_ff2_Y[37]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(d_ff2_Y[37]), .CK(reg_shift_y_net3844125), .RN(n1439), .Q(d_ff3_sh_y_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(mux_sal[37]), .CK(
d_ff5_data_out_net3844125), .RN(n1445), .Q(data_output[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Yn_net3844125), .RN(n1136), .Q(d_ff_Yn[38]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_38_ ( .D(first_mux_Y[38]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_Y[38]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(d_ff2_Y[38]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_y_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(mux_sal[38]), .CK(
d_ff5_data_out_net3844125), .RN(n1445), .Q(data_output[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Yn_net3844125), .RN(n1136), .Q(d_ff_Yn[39]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_39_ ( .D(first_mux_Y[39]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1434), .Q(d_ff2_Y[39]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(d_ff2_Y[39]), .CK(reg_shift_y_net3844125), .RN(n1435), .Q(d_ff3_sh_y_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(mux_sal[39]), .CK(
d_ff5_data_out_net3844125), .RN(n1432), .Q(data_output[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Yn_net3844125), .RN(n1423), .Q(d_ff_Yn[40]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_40_ ( .D(first_mux_Y[40]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1423), .Q(d_ff2_Y[40]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(d_ff2_Y[40]), .CK(reg_shift_y_net3844125), .RN(n1414), .Q(d_ff3_sh_y_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(mux_sal[40]), .CK(
d_ff5_data_out_net3844125), .RN(n1431), .Q(data_output[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Yn_net3844125), .RN(n1412), .Q(d_ff_Yn[41]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_41_ ( .D(first_mux_Y[41]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1436), .Q(d_ff2_Y[41]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(d_ff2_Y[41]), .CK(reg_shift_y_net3844125), .RN(n1422), .Q(d_ff3_sh_y_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(mux_sal[41]), .CK(
d_ff5_data_out_net3844125), .RN(n1422), .Q(data_output[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Yn_net3844125), .RN(n1440), .Q(d_ff_Yn[42]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_42_ ( .D(first_mux_Y[42]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1443), .Q(d_ff2_Y[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(d_ff2_Y[42]), .CK(reg_shift_y_net3844125), .RN(n1431), .Q(d_ff3_sh_y_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(mux_sal[42]), .CK(
d_ff5_data_out_net3844125), .RN(n1413), .Q(data_output[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Yn_net3844125), .RN(n1418), .Q(d_ff_Yn[43]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_43_ ( .D(first_mux_Y[43]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1413), .Q(d_ff2_Y[43]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(d_ff2_Y[43]), .CK(reg_shift_y_net3844125), .RN(n1419), .Q(d_ff3_sh_y_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(mux_sal[43]), .CK(
d_ff5_data_out_net3844125), .RN(n1420), .Q(data_output[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Yn_net3844125), .RN(n1413), .Q(d_ff_Yn[44]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_44_ ( .D(first_mux_Y[44]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Y[44]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(d_ff2_Y[44]), .CK(reg_shift_y_net3844125), .RN(n1442), .Q(d_ff3_sh_y_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(mux_sal[44]), .CK(
d_ff5_data_out_net3844125), .RN(n1417), .Q(data_output[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Yn_net3844125), .RN(n1419), .Q(d_ff_Yn[45]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_45_ ( .D(first_mux_Y[45]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1420), .Q(d_ff2_Y[45]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(d_ff2_Y[45]), .CK(reg_shift_y_net3844125), .RN(n1413), .Q(d_ff3_sh_y_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(mux_sal[45]), .CK(
d_ff5_data_out_net3844125), .RN(n1417), .Q(data_output[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Yn_net3844125), .RN(n1413), .Q(d_ff_Yn[46]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_46_ ( .D(first_mux_Y[46]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Y[46]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(d_ff2_Y[46]), .CK(reg_shift_y_net3844125), .RN(n1433), .Q(d_ff3_sh_y_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(mux_sal[46]), .CK(
d_ff5_data_out_net3844125), .RN(n1419), .Q(data_output[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Yn_net3844125), .RN(n1420), .Q(d_ff_Yn[47]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_47_ ( .D(first_mux_Y[47]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Y[47]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(d_ff2_Y[47]), .CK(reg_shift_y_net3844125), .RN(n1413), .Q(d_ff3_sh_y_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(mux_sal[47]), .CK(
d_ff5_data_out_net3844125), .RN(n1418), .Q(data_output[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Yn_net3844125), .RN(n1418), .Q(d_ff_Yn[48]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_48_ ( .D(first_mux_Y[48]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1419), .Q(d_ff2_Y[48]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(d_ff2_Y[48]), .CK(reg_shift_y_net3844125), .RN(n1420), .Q(d_ff3_sh_y_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(mux_sal[48]), .CK(
d_ff5_data_out_net3844125), .RN(n1418), .Q(data_output[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Yn_net3844125), .RN(n1442), .Q(d_ff_Yn[49]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_49_ ( .D(first_mux_Y[49]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Y[49]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(d_ff2_Y[49]), .CK(reg_shift_y_net3844125), .RN(n1413), .Q(d_ff3_sh_y_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(mux_sal[49]), .CK(
d_ff5_data_out_net3844125), .RN(n1418), .Q(data_output[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Yn_net3844125), .RN(n1417), .Q(d_ff_Yn[50]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_50_ ( .D(first_mux_Y[50]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Y[50]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(d_ff2_Y[50]), .CK(reg_shift_y_net3844125), .RN(n1419), .Q(d_ff3_sh_y_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(mux_sal[50]), .CK(
d_ff5_data_out_net3844125), .RN(n1420), .Q(data_output[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Yn_net3844125), .RN(n1413), .Q(d_ff_Yn[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_51_ ( .D(first_mux_Y[51]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Y[51]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(d_ff2_Y[51]), .CK(reg_shift_y_net3844125), .RN(n1413), .Q(d_ff3_sh_y_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(mux_sal[51]), .CK(
d_ff5_data_out_net3844125), .RN(n1417), .Q(data_output[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Yn_net3844125), .RN(n1419), .Q(d_ff_Yn[52]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(first_mux_Y[52]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1420), .Q(d_ff2_Y[52]), .QN(
n1142) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(mux_sal[52]), .CK(
d_ff5_data_out_net3844125), .RN(n1413), .Q(data_output[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Yn_net3844125), .RN(n1418), .Q(d_ff_Yn[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(mux_sal[53]), .CK(
d_ff5_data_out_net3844125), .RN(n1433), .Q(data_output[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Yn_net3844125), .RN(n1417), .Q(d_ff_Yn[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(mux_sal[54]), .CK(
d_ff5_data_out_net3844125), .RN(n1419), .Q(data_output[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Yn_net3844125), .RN(n1420), .Q(d_ff_Yn[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(mux_sal[55]), .CK(
d_ff5_data_out_net3844125), .RN(n1417), .Q(data_output[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Yn_net3844125), .RN(n1419), .Q(d_ff_Yn[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(mux_sal[56]), .CK(
d_ff5_data_out_net3844125), .RN(n1420), .Q(data_output[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Yn_net3844125), .RN(n1413), .Q(d_ff_Yn[57]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_57_ ( .D(first_mux_Y[57]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Y[57]), .QN(
n1406) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(mux_sal[57]), .CK(
d_ff5_data_out_net3844125), .RN(n1416), .Q(data_output[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Yn_net3844125), .RN(n1417), .Q(d_ff_Yn[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(mux_sal[58]), .CK(
d_ff5_data_out_net3844125), .RN(n1413), .Q(data_output[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Yn_net3844125), .RN(n1418), .Q(d_ff_Yn[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(mux_sal[59]), .CK(
d_ff5_data_out_net3844125), .RN(n1434), .Q(data_output[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Yn_net3844125), .RN(n1434), .Q(d_ff_Yn[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(mux_sal[60]), .CK(
d_ff5_data_out_net3844125), .RN(n1416), .Q(data_output[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Yn_net3844125), .RN(n1416), .Q(d_ff_Yn[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(mux_sal[61]), .CK(
d_ff5_data_out_net3844125), .RN(n1440), .Q(data_output[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Yn_net3844125), .RN(n1440), .Q(d_ff_Yn[62]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(first_mux_Y[62]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1437), .Q(d_ff2_Y[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(mux_sal[62]), .CK(
d_ff5_data_out_net3844125), .RN(n1437), .Q(data_output[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Yn_net3844125), .RN(n1411), .Q(d_ff_Yn[63]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(fmtted_Result_63_), .CK(
d_ff5_data_out_net3844125), .RN(n1416), .Q(data_output[63]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_63_ ( .D(first_mux_Y[63]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Y[63]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(d_ff2_Y[63]), .CK(reg_shift_y_net3844125), .RN(n1136), .Q(d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3844125), .RN(n1428), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3844125), .RN(n1415), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3844125), .RN(n1446), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3844125), .RN(n1136), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3844125), .RN(n1428), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3844125), .RN(n1447), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1422), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3844125), .RN(n1414), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3844125), .RN(n1431), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1435), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3844125), .RN(n1447), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1422), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3844125), .RN(n1414), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1439), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3844125), .RN(n1431), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1435), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3844125), .RN(n1429), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3844125), .RN(n1438), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1415), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3844125), .RN(n1429), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3844125), .RN(n1438), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1421), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1415), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3844125), .RN(n1413), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3844125), .RN(n1433), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3844125), .RN(n1413), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3844125), .RN(n1434), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3844125), .RN(n1419), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1420), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3844125), .RN(n1413), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3844125), .RN(n1443), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1436), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3844125), .RN(n1436), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1412), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3844125), .RN(n1412), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1412), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3844125), .RN(n1436), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1443), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3844125), .RN(n1443), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1423), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3844125), .RN(n1423), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1423), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3844125), .RN(n1416), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1416), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3844125), .RN(n1438), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1411), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3844125), .RN(n1434), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1437), .Q(d_ff2_Z[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Zn_net3844125), .RN(n1437), .Q(d_ff_Zn[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(first_mux_Z[32]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1437), .Q(d_ff2_Z[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Zn_net3844125), .RN(n1411), .Q(d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(first_mux_Z[33]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1438), .Q(d_ff2_Z[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Zn_net3844125), .RN(n1440), .Q(d_ff_Zn[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(first_mux_Z[34]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1438), .Q(d_ff2_Z[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(first_mux_Z[35]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(first_mux_Z[36]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(first_mux_Z[37]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(first_mux_Z[38]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(first_mux_Z[39]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Zn_net3844125), .RN(n1410), .Q(d_ff_Zn[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(first_mux_Z[40]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1425), .Q(d_ff2_Z[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(first_mux_Z[41]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(first_mux_Z[42]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(first_mux_Z[43]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(first_mux_Z[44]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(first_mux_Z[45]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Zn_net3844125), .RN(n1409), .Q(d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(first_mux_Z[46]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1409), .Q(d_ff2_Z[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(first_mux_Z[47]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(first_mux_Z[48]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(first_mux_Z[49]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(first_mux_Z[50]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(first_mux_Z[51]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Zn_net3844125), .RN(n1408), .Q(d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(first_mux_Z[52]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1408), .Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Zn_net3844125), .RN(n1136), .Q(d_ff_Zn[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(first_mux_Z[53]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_Z[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Zn_net3844125), .RN(n1432), .Q(d_ff_Zn[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(first_mux_Z[54]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_Z[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Zn_net3844125), .RN(n1415), .Q(d_ff_Zn[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(first_mux_Z[55]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Z[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Zn_net3844125), .RN(n1137), .Q(d_ff_Zn[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(first_mux_Z[56]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1429), .Q(d_ff2_Z[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Zn_net3844125), .RN(n1415), .Q(d_ff_Zn[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(first_mux_Z[57]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1136), .Q(d_ff2_Z[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Zn_net3844125), .RN(n1428), .Q(d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(first_mux_Z[58]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(first_mux_Z[59]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_Z[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(first_mux_Z[60]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(first_mux_Z[61]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_Z[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(first_mux_Z[62]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_Z[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Zn_net3844125), .RN(n1138), .Q(d_ff_Zn[63]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_63_ ( .D(first_mux_Z[63]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1138), .Q(d_ff2_Z[63]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[63]), .CK(reg_shift_y_net3844125),
.RN(n1138), .Q(d_ff3_sign_out) );
DFFRXLTS reg_LUT_Q_reg_48_ ( .D(1'b1), .CK(reg_shift_y_net3844125), .RN(
n1425), .Q(d_ff3_LUT_out[48]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n1433), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n1401) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n1441), .Q(
inst_CORDIC_FSM_v3_state_reg[1]), .QN(n1400) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n249), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1398) );
DFFRX1TS VAR_CONT_temp_reg_0_ ( .D(n960), .CK(clk), .RN(n1444), .Q(
cont_var_out[0]), .QN(n1397) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n1399), .CK(ITER_CONT_net3844161), .RN(
n1442), .Q(n1407), .QN(n1399) );
DFFSX4TS ITER_CONT_temp_reg_3_ ( .D(n983), .CK(ITER_CONT_net3844161), .SN(
n1417), .Q(n1402), .QN(cont_iter_out[3]) );
DFFSX4TS ITER_CONT_temp_reg_2_ ( .D(data_out_LUT[54]), .CK(
ITER_CONT_net3844161), .SN(n1428), .Q(n1396), .QN(cont_iter_out[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_59_ ( .D(first_mux_Y[59]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1440), .Q(d_ff2_Y[59]), .QN(
n1403) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n961), .CK(clk), .RN(n1433), .Q(
cont_var_out[1]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n1136), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n1442), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(first_mux_X[56]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_X[56]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_56_ ( .D(first_mux_Y[56]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Y[56]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
inst_CORDIC_FSM_v3_state_next[3]), .CK(clk), .RN(n1137), .Q(
inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(first_mux_X[61]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1430), .Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(first_mux_Y[61]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1434), .Q(d_ff2_Y[61]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3844125), .RN(n1444), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(first_mux_X[58]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[58]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(first_mux_Y[60]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1440), .Q(d_ff2_Y[60]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(first_mux_Y[58]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1428), .Q(d_ff2_Y[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(first_mux_X[55]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(first_mux_X[54]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1446), .Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(first_mux_X[53]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1137), .Q(d_ff2_X[53]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(first_mux_Y[55]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1418), .Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(first_mux_Y[54]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1413), .Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(first_mux_Y[53]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1417), .Q(d_ff2_Y[53]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n1418), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(first_mux_X[60]), .CK(
reg_val_muxZ_2stage_net3844125), .RN(n1430), .Q(d_ff2_X[60]) );
DFFSX1TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n1442), .Q(
inst_CORDIC_FSM_v3_state_reg[0]), .QN(n1404) );
ADDFX1TS intadd_466_U2 ( .A(d_ff2_Y[55]), .B(n1402), .CI(intadd_466_n2),
.CO(intadd_466_n1), .S(sh_exp_y[3]) );
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(ITER_CONT_N3), .CK(ITER_CONT_net3844161),
.RN(n1433), .Q(cont_iter_out[1]), .QN(n1134) );
CMPR32X2TS intadd_466_U4 ( .A(d_ff2_Y[53]), .B(n1134), .C(intadd_466_CI),
.CO(intadd_466_n3), .S(sh_exp_y[1]) );
CMPR32X2TS intadd_465_U4 ( .A(d_ff2_X[53]), .B(n1134), .C(intadd_465_CI),
.CO(intadd_465_n3), .S(sh_exp_x[1]) );
CMPR32X2TS intadd_466_U3 ( .A(d_ff2_Y[54]), .B(n1396), .C(intadd_466_n3),
.CO(intadd_466_n2), .S(sh_exp_y[2]) );
CMPR32X2TS intadd_465_U3 ( .A(d_ff2_X[54]), .B(n1396), .C(intadd_465_n3),
.CO(intadd_465_n2), .S(sh_exp_x[2]) );
CMPR32X2TS intadd_465_U2 ( .A(n1402), .B(d_ff2_X[55]), .C(intadd_465_n2),
.CO(intadd_465_n1), .S(sh_exp_x[3]) );
AOI222X1TS U726 ( .A0(n1348), .A1(d_ff2_X[4]), .B0(n1356), .B1(d_ff2_Y[4]),
.C0(n1290), .C1(d_ff2_Z[4]), .Y(n1208) );
AOI222X1TS U727 ( .A0(n1348), .A1(d_ff2_X[1]), .B0(n1356), .B1(d_ff2_Y[1]),
.C0(n1290), .C1(d_ff2_Z[1]), .Y(n1211) );
AOI222X1TS U728 ( .A0(n1359), .A1(d_ff2_X[5]), .B0(n1259), .B1(d_ff2_Y[5]),
.C0(n1355), .C1(d_ff2_Z[5]), .Y(n1227) );
AOI222X1TS U729 ( .A0(n1256), .A1(d_ff2_X[55]), .B0(n1259), .B1(d_ff2_Y[55]),
.C0(n1258), .C1(d_ff2_Z[55]), .Y(n1245) );
AOI222X1TS U730 ( .A0(n1267), .A1(d_ff2_X[58]), .B0(n1259), .B1(d_ff2_Y[58]),
.C0(n1258), .C1(d_ff2_Z[58]), .Y(n1254) );
AOI222X1TS U731 ( .A0(n1344), .A1(d_ff2_X[42]), .B0(n1216), .B1(d_ff2_Y[42]),
.C0(n1258), .C1(d_ff2_Z[42]), .Y(n1253) );
AOI222X1TS U732 ( .A0(n1272), .A1(d_ff2_X[43]), .B0(n1216), .B1(d_ff2_Y[43]),
.C0(n1258), .C1(d_ff2_Z[43]), .Y(n1248) );
AOI222X1TS U733 ( .A0(n1267), .A1(d_ff2_X[53]), .B0(n1291), .B1(d_ff2_Y[53]),
.C0(n1258), .C1(d_ff2_Z[53]), .Y(n1189) );
AOI222X1TS U734 ( .A0(n1348), .A1(d_ff2_X[12]), .B0(n1251), .B1(d_ff2_Y[12]),
.C0(n1255), .C1(d_ff2_Z[12]), .Y(n1246) );
AOI222X1TS U735 ( .A0(n1348), .A1(d_ff2_X[10]), .B0(n1251), .B1(d_ff2_Y[10]),
.C0(n1255), .C1(d_ff2_Z[10]), .Y(n1244) );
AOI222X1TS U736 ( .A0(n1348), .A1(d_ff2_X[9]), .B0(n1251), .B1(d_ff2_Y[9]),
.C0(n1255), .C1(d_ff2_Z[9]), .Y(n1243) );
AOI222X1TS U737 ( .A0(n1348), .A1(d_ff2_X[13]), .B0(n1251), .B1(d_ff2_Y[13]),
.C0(n1255), .C1(d_ff2_Z[13]), .Y(n1242) );
AOI222X1TS U738 ( .A0(n1359), .A1(d_ff2_X[7]), .B0(n1251), .B1(d_ff2_Y[7]),
.C0(n1255), .C1(d_ff2_Z[7]), .Y(n1241) );
AOI222X1TS U739 ( .A0(n1348), .A1(d_ff2_X[16]), .B0(n1251), .B1(d_ff2_Y[16]),
.C0(n1255), .C1(d_ff2_Z[16]), .Y(n1240) );
AOI222X1TS U740 ( .A0(n1348), .A1(d_ff2_X[18]), .B0(n1251), .B1(d_ff2_Y[18]),
.C0(n1255), .C1(d_ff2_Z[18]), .Y(n1239) );
AOI222X1TS U741 ( .A0(n1344), .A1(d_ff2_X[0]), .B0(n1251), .B1(d_ff2_Y[0]),
.C0(n1258), .C1(d_ff2_Z[0]), .Y(n1236) );
AOI222X1TS U742 ( .A0(n1348), .A1(d_ff2_X[6]), .B0(n1251), .B1(d_ff2_Y[6]),
.C0(n1355), .C1(d_ff2_Z[6]), .Y(n1230) );
AOI222X1TS U743 ( .A0(n1359), .A1(d_ff2_X[3]), .B0(n1251), .B1(d_ff2_Y[3]),
.C0(n1355), .C1(d_ff2_Z[3]), .Y(n1229) );
AOI222X1TS U744 ( .A0(n1359), .A1(d_ff2_X[8]), .B0(n1251), .B1(d_ff2_Y[8]),
.C0(n1355), .C1(d_ff2_Z[8]), .Y(n1228) );
NAND2X6TS U745 ( .A(n1145), .B(n1365), .Y(n997) );
NAND3XLTS U746 ( .A(n1332), .B(n1330), .C(n1298), .Y(n1382) );
INVX6TS U747 ( .A(n1301), .Y(n1318) );
BUFX4TS U748 ( .A(n1358), .Y(n1197) );
OR2X4TS U749 ( .A(n1397), .B(cont_var_out[1]), .Y(n1147) );
INVX4TS U750 ( .A(n1308), .Y(n1135) );
OR2X2TS U751 ( .A(n1167), .B(n1145), .Y(n1369) );
BUFX6TS U752 ( .A(n1414), .Y(n1428) );
BUFX6TS U753 ( .A(n1439), .Y(n1429) );
BUFX6TS U754 ( .A(n1431), .Y(n1415) );
NAND2X2TS U755 ( .A(cont_iter_out[2]), .B(n1402), .Y(n1146) );
INVX4TS U756 ( .A(n1329), .Y(n1358) );
NOR2X4TS U757 ( .A(cont_iter_out[3]), .B(cont_iter_out[2]), .Y(n1145) );
BUFX6TS U758 ( .A(n1422), .Y(n1136) );
BUFX6TS U759 ( .A(n1445), .Y(n1438) );
BUFX6TS U760 ( .A(n1447), .Y(n1137) );
BUFX6TS U761 ( .A(n1411), .Y(n1138) );
BUFX6TS U762 ( .A(n249), .Y(n1432) );
INVX6TS U763 ( .A(rst), .Y(n249) );
AOI222X1TS U764 ( .A0(n1287), .A1(d_ff2_X[34]), .B0(n1259), .B1(d_ff2_Y[34]),
.C0(n1358), .C1(d_ff2_Z[34]), .Y(n1234) );
AOI222X1TS U765 ( .A0(n1256), .A1(d_ff2_X[35]), .B0(n1216), .B1(d_ff2_Y[35]),
.C0(n1358), .C1(d_ff2_Z[35]), .Y(n1235) );
AOI222X1TS U766 ( .A0(n1267), .A1(d_ff2_X[36]), .B0(n1291), .B1(d_ff2_Y[36]),
.C0(n1358), .C1(d_ff2_Z[36]), .Y(n1233) );
NAND2BXLTS U767 ( .AN(n1380), .B(n1379), .Y(n972) );
NAND2BXLTS U768 ( .AN(n1377), .B(n1145), .Y(n999) );
BUFX6TS U769 ( .A(n1148), .Y(n1356) );
NOR2X2TS U770 ( .A(n1298), .B(n1294), .Y(enab_d_ff4_Zn) );
AOI32X1TS U771 ( .A0(n1396), .A1(n1372), .A2(n1371), .B0(n1370), .B1(n1372),
.Y(n982) );
NOR2X2TS U772 ( .A(cont_iter_out[3]), .B(n1134), .Y(n1370) );
BUFX4TS U773 ( .A(n249), .Y(n1414) );
BUFX4TS U774 ( .A(n249), .Y(n1439) );
BUFX4TS U775 ( .A(n249), .Y(n1431) );
BUFX4TS U776 ( .A(n249), .Y(n1422) );
BUFX4TS U777 ( .A(n1432), .Y(n1427) );
BUFX4TS U778 ( .A(n1428), .Y(n1424) );
BUFX4TS U779 ( .A(n1438), .Y(n1425) );
BUFX4TS U780 ( .A(n1415), .Y(n1410) );
BUFX4TS U781 ( .A(n1420), .Y(n1409) );
BUFX4TS U782 ( .A(n1429), .Y(n1426) );
BUFX4TS U783 ( .A(n1432), .Y(n1412) );
BUFX4TS U784 ( .A(n1432), .Y(n1423) );
BUFX4TS U785 ( .A(n1432), .Y(n1436) );
BUFX4TS U786 ( .A(n1432), .Y(n1443) );
BUFX4TS U787 ( .A(n1137), .Y(n1408) );
BUFX4TS U788 ( .A(n1445), .Y(n1416) );
BUFX4TS U789 ( .A(n1445), .Y(n1437) );
BUFX4TS U790 ( .A(n1445), .Y(n1434) );
BUFX4TS U791 ( .A(n1445), .Y(n1440) );
BUFX4TS U792 ( .A(n249), .Y(n1445) );
NOR2X2TS U793 ( .A(n1378), .B(n1365), .Y(ITER_CONT_N3) );
BUFX4TS U794 ( .A(n1438), .Y(n1442) );
BUFX4TS U795 ( .A(n1429), .Y(n1433) );
NOR2X4TS U796 ( .A(cont_iter_out[1]), .B(n1399), .Y(n1377) );
NOR2X4TS U797 ( .A(n1407), .B(n1134), .Y(n1367) );
INVX2TS U798 ( .A(n1369), .Y(n1140) );
INVX6TS U799 ( .A(n1147), .Y(n1256) );
AOI211X2TS U800 ( .A0(n1375), .A1(n1399), .B0(n1297), .C0(cont_iter_out[1]),
.Y(n1380) );
NOR3X2TS U801 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(n1401), .C(n1168),
.Y(ready_cordic) );
NAND2X2TS U802 ( .A(n1402), .B(n1399), .Y(n1371) );
AOI222X1TS U803 ( .A0(n1272), .A1(d_ff2_X[24]), .B0(n1286), .B1(d_ff2_Y[24]),
.C0(n1355), .C1(d_ff2_Z[24]), .Y(n1268) );
AOI222X1TS U804 ( .A0(n1272), .A1(d_ff2_X[30]), .B0(n1356), .B1(d_ff2_Y[30]),
.C0(n1255), .C1(d_ff2_Z[30]), .Y(n1257) );
AOI222X1TS U805 ( .A0(n1256), .A1(d_ff2_X[33]), .B0(n1216), .B1(d_ff2_Y[33]),
.C0(n1255), .C1(d_ff2_Z[33]), .Y(n1238) );
AOI222X1TS U806 ( .A0(n1287), .A1(d_ff2_X[32]), .B0(n1216), .B1(d_ff2_Y[32]),
.C0(n1255), .C1(d_ff2_Z[32]), .Y(n1237) );
AOI222X1TS U807 ( .A0(n1272), .A1(d_ff2_X[37]), .B0(n1286), .B1(d_ff2_Y[37]),
.C0(n1358), .C1(d_ff2_Z[37]), .Y(n1232) );
AOI222X1TS U808 ( .A0(n1267), .A1(d_ff2_X[40]), .B0(n1286), .B1(d_ff2_Y[40]),
.C0(n1355), .C1(d_ff2_Z[40]), .Y(n1231) );
AOI222X1TS U809 ( .A0(n1287), .A1(d_ff2_X[39]), .B0(n1148), .B1(d_ff2_Y[39]),
.C0(n1358), .C1(d_ff2_Z[39]), .Y(n1215) );
AOI222X1TS U810 ( .A0(n1272), .A1(d_ff2_X[38]), .B0(n1148), .B1(d_ff2_Y[38]),
.C0(n1358), .C1(d_ff2_Z[38]), .Y(n1214) );
INVX4TS U811 ( .A(n1294), .Y(n1148) );
NAND2X2TS U812 ( .A(n1399), .B(n1134), .Y(n1364) );
AOI222X1TS U813 ( .A0(n1348), .A1(d_ff2_X[17]), .B0(n1251), .B1(d_ff2_Y[17]),
.C0(n1255), .C1(d_ff2_Z[17]), .Y(n1252) );
AOI222X1TS U814 ( .A0(n1348), .A1(d_ff2_X[15]), .B0(n1251), .B1(d_ff2_Y[15]),
.C0(n1255), .C1(d_ff2_Z[15]), .Y(n1249) );
BUFX4TS U815 ( .A(n1216), .Y(n1259) );
AOI222X1TS U816 ( .A0(n1344), .A1(d_ff3_sh_y_out[22]), .B0(n1291), .B1(
d_ff3_sh_x_out[22]), .C0(n1264), .C1(d_ff3_LUT_out[22]), .Y(n1261) );
AOI222X1TS U817 ( .A0(n1256), .A1(d_ff3_sh_y_out[20]), .B0(n1291), .B1(
d_ff3_sh_x_out[20]), .C0(n1264), .C1(d_ff3_LUT_out[20]), .Y(n1262) );
AOI222X1TS U818 ( .A0(n1256), .A1(d_ff3_sh_y_out[21]), .B0(n1291), .B1(
d_ff3_sh_x_out[21]), .C0(n1264), .C1(d_ff3_LUT_out[21]), .Y(n1263) );
AOI222X1TS U819 ( .A0(n1344), .A1(d_ff3_sh_y_out[19]), .B0(n1291), .B1(
d_ff3_sh_x_out[19]), .C0(n1264), .C1(d_ff3_LUT_out[19]), .Y(n1265) );
BUFX4TS U820 ( .A(n1284), .Y(n1291) );
NOR2X2TS U821 ( .A(d_ff2_X[60]), .B(n1390), .Y(n1394) );
INVX2TS U822 ( .A(n1139), .Y(n1141) );
BUFX4TS U823 ( .A(n1429), .Y(n1418) );
BUFX4TS U824 ( .A(n1415), .Y(n1413) );
BUFX4TS U825 ( .A(n1138), .Y(n1417) );
INVX4TS U826 ( .A(n997), .Y(n1325) );
BUFX6TS U827 ( .A(n1358), .Y(n1290) );
INVX4TS U828 ( .A(n1308), .Y(n1309) );
INVX4TS U829 ( .A(n1308), .Y(n1326) );
INVX4TS U830 ( .A(n1308), .Y(n1323) );
INVX4TS U831 ( .A(n1308), .Y(n1307) );
CLKINVX6TS U832 ( .A(n1147), .Y(n1287) );
CLKINVX6TS U833 ( .A(n1147), .Y(n1272) );
CLKINVX6TS U834 ( .A(n1147), .Y(n1267) );
BUFX4TS U835 ( .A(n1356), .Y(n1216) );
BUFX4TS U836 ( .A(n1356), .Y(n1286) );
NOR3X1TS U837 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1155) );
AOI222X4TS U838 ( .A0(n1267), .A1(d_ff2_X[54]), .B0(n1148), .B1(d_ff2_Y[54]),
.C0(n1258), .C1(d_ff2_Z[54]), .Y(n1250) );
NAND2X2TS U839 ( .A(n1167), .B(n1378), .Y(n985) );
NOR2X2TS U840 ( .A(d_ff2_Y[58]), .B(n1386), .Y(n1385) );
AOI222X1TS U841 ( .A0(n1267), .A1(d_ff2_X[60]), .B0(n1259), .B1(d_ff2_Y[60]),
.C0(n1197), .C1(d_ff2_Z[60]), .Y(n1224) );
NOR2X2TS U842 ( .A(d_ff2_Y[60]), .B(n1384), .Y(n1388) );
NOR2X2TS U843 ( .A(d_ff2_X[58]), .B(n1392), .Y(n1391) );
OAI32X4TS U844 ( .A0(n1144), .A1(d_ff1_shift_region_flag_out[1]), .A2(n1141),
.B0(d_ff1_shift_region_flag_out[0]), .B1(n1302), .Y(n1303) );
AOI222X1TS U845 ( .A0(n1287), .A1(d_ff2_X[61]), .B0(n1259), .B1(d_ff2_Y[61]),
.C0(n1197), .C1(d_ff2_Z[61]), .Y(n1218) );
BUFX6TS U846 ( .A(n1422), .Y(n1446) );
AOI21X2TS U847 ( .A0(n1396), .A1(n1399), .B0(cont_iter_out[3]), .Y(n1299) );
AOI222X1TS U848 ( .A0(n1256), .A1(d_ff2_X[56]), .B0(n1259), .B1(d_ff2_Y[56]),
.C0(n1258), .C1(d_ff2_Z[56]), .Y(n1260) );
NAND4X2TS U849 ( .A(n1153), .B(inst_CORDIC_FSM_v3_state_reg[4]), .C(n1401),
.D(n1398), .Y(n1330) );
NOR4X2TS U850 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(inst_CORDIC_FSM_v3_state_reg[7]),
.D(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1154) );
INVX4TS U851 ( .A(n997), .Y(n1311) );
INVX4TS U852 ( .A(n1318), .Y(n1315) );
OR2X1TS U853 ( .A(d_ff_Xn[60]), .B(n1305), .Y(first_mux_X[60]) );
OR2X1TS U854 ( .A(d_ff_Xn[46]), .B(n1305), .Y(first_mux_X[46]) );
OR2X1TS U855 ( .A(d_ff_Xn[39]), .B(n1324), .Y(first_mux_X[39]) );
OR2X1TS U856 ( .A(d_ff_Xn[26]), .B(n1169), .Y(first_mux_X[26]) );
OR2X1TS U857 ( .A(d_ff_Xn[19]), .B(n1323), .Y(first_mux_X[19]) );
OR2X1TS U858 ( .A(d_ff_Xn[7]), .B(n1307), .Y(first_mux_X[7]) );
OR2X1TS U859 ( .A(d_ff_Xn[3]), .B(n1324), .Y(first_mux_X[3]) );
OAI21XLTS U860 ( .A0(n1387), .A1(n1406), .B0(n1386), .Y(sh_exp_y[5]) );
OAI211XLTS U861 ( .A0(n1146), .A1(n1374), .B0(n1162), .C0(n1362), .Y(n964)
);
OAI211XLTS U862 ( .A0(n1166), .A1(n1134), .B0(n1165), .C0(n1362), .Y(n968)
);
OAI21XLTS U863 ( .A0(n1147), .A1(n1206), .B0(n1205), .Y(add_subt_dataA[59])
);
INVX2TS U864 ( .A(n1364), .Y(n1365) );
NOR2X2TS U865 ( .A(n1402), .B(n1396), .Y(n1167) );
NAND2X2TS U866 ( .A(n1407), .B(cont_iter_out[1]), .Y(n1374) );
INVX2TS U867 ( .A(n1374), .Y(n1378) );
AOI21X1TS U868 ( .A0(n1396), .A1(n1134), .B0(cont_iter_out[3]), .Y(n1161) );
OAI211XLTS U869 ( .A0(n1145), .A1(n1374), .B0(n1161), .C0(n1364), .Y(n980)
);
BUFX3TS U870 ( .A(n249), .Y(n1447) );
OR4X2TS U871 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.D(inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1159) );
NOR2X1TS U872 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(n1159), .Y(n1153) );
NAND2BX1TS U873 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(n1153), .Y(n1168)
);
BUFX3TS U874 ( .A(n1438), .Y(n1441) );
BUFX3TS U875 ( .A(n249), .Y(n1435) );
BUFX3TS U876 ( .A(n1445), .Y(n1411) );
BUFX3TS U877 ( .A(n1138), .Y(n1444) );
BUFX3TS U878 ( .A(n249), .Y(n1430) );
BUFX3TS U879 ( .A(n1432), .Y(n1421) );
BUFX3TS U880 ( .A(n1415), .Y(n1420) );
BUFX3TS U881 ( .A(n1429), .Y(n1419) );
OAI21XLTS U882 ( .A0(n1396), .A1(n1134), .B0(n1402), .Y(n1000) );
OAI2BB1X1TS U883 ( .A0N(n1407), .A1N(n1145), .B0(cont_iter_out[1]), .Y(n1376) );
NAND2X1TS U884 ( .A(n1376), .B(n1299), .Y(n971) );
INVX2TS U885 ( .A(n1371), .Y(n1366) );
OAI21XLTS U886 ( .A0(cont_iter_out[2]), .A1(n1134), .B0(n1366), .Y(n990) );
NAND2X2TS U887 ( .A(n1396), .B(cont_iter_out[3]), .Y(n1363) );
INVX2TS U888 ( .A(n1363), .Y(n1375) );
NAND2X1TS U889 ( .A(n1377), .B(n1369), .Y(n1165) );
NAND3XLTS U890 ( .A(cont_iter_out[1]), .B(n1371), .C(n1146), .Y(n1379) );
OAI211XLTS U891 ( .A0(n1375), .A1(n1364), .B0(n1165), .C0(n1379), .Y(n967)
);
NAND2X1TS U892 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .Y(n1329) );
INVX4TS U893 ( .A(n1147), .Y(n1359) );
NAND2X1TS U894 ( .A(n1397), .B(cont_var_out[1]), .Y(n1294) );
AOI22X1TS U895 ( .A0(n1359), .A1(d_ff3_sh_y_out[4]), .B0(n1356), .B1(
d_ff3_sh_x_out[4]), .Y(n1149) );
OAI2BB1X1TS U896 ( .A0N(n1358), .A1N(d_ff3_LUT_out[4]), .B0(n1149), .Y(
add_subt_dataB[4]) );
AOI22X1TS U897 ( .A0(n1359), .A1(d_ff3_sh_y_out[43]), .B0(n1356), .B1(
d_ff3_sh_x_out[43]), .Y(n1150) );
OAI2BB1X1TS U898 ( .A0N(n1358), .A1N(d_ff3_LUT_out[34]), .B0(n1150), .Y(
add_subt_dataB[43]) );
NOR3BX1TS U899 ( .AN(n1154), .B(inst_CORDIC_FSM_v3_state_reg[2]), .C(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1151) );
NAND3XLTS U900 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(n1151), .C(n1404),
.Y(n1328) );
NAND3X1TS U901 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n1151), .C(n1400),
.Y(n1327) );
NAND2X1TS U902 ( .A(n1328), .B(n1327), .Y(enab_d_ff_RB1) );
NOR2BX1TS U903 ( .AN(n1154), .B(inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1152)
);
AND4X1TS U904 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(n1152), .C(n1404),
.D(n1400), .Y(inst_CORDIC_FSM_v3_state_next[3]) );
NAND3X1TS U905 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1155), .C(n1154),
.Y(n1331) );
NAND2X1TS U906 ( .A(n1330), .B(n1331), .Y(beg_add_subt) );
BUFX3TS U907 ( .A(n1356), .Y(n1284) );
AO22XLTS U908 ( .A0(n1287), .A1(d_ff3_sh_y_out[62]), .B0(n1284), .B1(
d_ff3_sh_x_out[62]), .Y(add_subt_dataB[62]) );
AO22XLTS U909 ( .A0(n1287), .A1(d_ff3_sh_y_out[63]), .B0(n1284), .B1(
d_ff3_sh_x_out[63]), .Y(add_subt_dataB[63]) );
NAND2X1TS U910 ( .A(n1143), .B(n1407), .Y(intadd_465_CI) );
OAI21XLTS U911 ( .A0(n1407), .A1(n1143), .B0(intadd_465_CI), .Y(sh_exp_x[0])
);
NAND2X1TS U912 ( .A(n1142), .B(n1407), .Y(intadd_466_CI) );
OAI21XLTS U913 ( .A0(n1407), .A1(n1142), .B0(intadd_466_CI), .Y(sh_exp_y[0])
);
OR2X1TS U914 ( .A(n1370), .B(n1299), .Y(n970) );
INVX2TS U915 ( .A(n1299), .Y(n1166) );
OAI21XLTS U916 ( .A0(n1167), .A1(cont_iter_out[1]), .B0(n1166), .Y(n969) );
OAI21X1TS U917 ( .A0(cont_iter_out[1]), .A1(n1366), .B0(n1376), .Y(n976) );
OR2X1TS U918 ( .A(n976), .B(cont_iter_out[2]), .Y(n978) );
AOI22X1TS U919 ( .A0(cont_iter_out[2]), .A1(n1377), .B0(n1367), .B1(n1363),
.Y(n1156) );
OAI21XLTS U920 ( .A0(n1140), .A1(n1374), .B0(n1156), .Y(n966) );
NOR2X1TS U921 ( .A(d_ff2_X[56]), .B(intadd_465_n1), .Y(n1393) );
OR3X1TS U922 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_465_n1), .Y(n1392) );
OAI21XLTS U923 ( .A0(n1393), .A1(n1405), .B0(n1392), .Y(sh_exp_x[5]) );
NOR2X1TS U924 ( .A(d_ff2_Y[56]), .B(intadd_466_n1), .Y(n1387) );
OR3X1TS U925 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_466_n1), .Y(n1386) );
NOR2X1TS U926 ( .A(cont_iter_out[3]), .B(n1399), .Y(n1297) );
AOI21X1TS U927 ( .A0(n1140), .A1(n1367), .B0(n1297), .Y(n1157) );
OAI21XLTS U928 ( .A0(cont_iter_out[1]), .A1(n1363), .B0(n1157), .Y(n963) );
OR3X1TS U929 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[7]), .C(inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n1158) );
NOR3BX2TS U930 ( .AN(inst_CORDIC_FSM_v3_state_reg[3]), .B(n1159), .C(n1158),
.Y(enab_RB3) );
BUFX4TS U931 ( .A(n1358), .Y(n1355) );
INVX2TS U932 ( .A(enab_RB3), .Y(n1160) );
OAI21XLTS U933 ( .A0(n1290), .A1(n1330), .B0(n1160), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U934 ( .A(n1161), .Y(n1003) );
AOI22X1TS U935 ( .A0(n1145), .A1(n1367), .B0(n1377), .B1(n1396), .Y(n1162)
);
NAND2X1TS U936 ( .A(n1140), .B(n1365), .Y(n1362) );
AOI22X1TS U937 ( .A0(n1377), .A1(n1396), .B0(n1378), .B1(n1402), .Y(n1163)
);
OAI31X1TS U938 ( .A0(n1167), .A1(n1407), .A2(n1370), .B0(n1163), .Y(n965) );
AOI22X1TS U939 ( .A0(cont_iter_out[2]), .A1(n1367), .B0(n1378), .B1(n1369),
.Y(n1164) );
OAI21XLTS U940 ( .A0(cont_iter_out[1]), .A1(n1146), .B0(n1164), .Y(n984) );
NAND2BXLTS U941 ( .AN(n1167), .B(n1367), .Y(n1296) );
OAI211XLTS U942 ( .A0(ITER_CONT_N3), .A1(n1369), .B0(n1296), .C0(n1363), .Y(
n989) );
NAND2X1TS U943 ( .A(n1403), .B(n1385), .Y(n1384) );
OAI21XLTS U944 ( .A0(n1385), .A1(n1403), .B0(n1384), .Y(sh_exp_y[7]) );
INVX2TS U945 ( .A(d_ff2_X[59]), .Y(n1206) );
NAND2X1TS U946 ( .A(n1206), .B(n1391), .Y(n1390) );
OAI21XLTS U947 ( .A0(n1391), .A1(n1206), .B0(n1390), .Y(sh_exp_x[7]) );
NOR3X2TS U948 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1168), .C(n1398),
.Y(enab_cont_iter) );
INVX2TS U949 ( .A(enab_cont_iter), .Y(n1332) );
INVX2TS U950 ( .A(ready_cordic), .Y(n1333) );
OAI21XLTS U951 ( .A0(n1332), .A1(n985), .B0(n1333), .Y(enab_d_ff5_data_out)
);
INVX4TS U952 ( .A(n997), .Y(n1313) );
OR2X1TS U953 ( .A(d_ff_Xn[41]), .B(n1313), .Y(first_mux_X[41]) );
OR2X1TS U954 ( .A(d_ff_Xn[36]), .B(n1305), .Y(first_mux_X[36]) );
INVX4TS U955 ( .A(n997), .Y(n1305) );
OR2X1TS U956 ( .A(d_ff_Xn[29]), .B(n1324), .Y(first_mux_X[29]) );
INVX4TS U957 ( .A(n997), .Y(n1324) );
OR2X1TS U958 ( .A(d_ff_Xn[6]), .B(n1311), .Y(first_mux_X[6]) );
OR2X1TS U959 ( .A(d_ff_Xn[59]), .B(n1169), .Y(first_mux_X[59]) );
OR2X1TS U960 ( .A(d_ff_Xn[9]), .B(n1313), .Y(first_mux_X[9]) );
OR2X1TS U961 ( .A(d_ff_Xn[32]), .B(n1311), .Y(first_mux_X[32]) );
OR2X1TS U962 ( .A(d_ff_Xn[24]), .B(n1323), .Y(first_mux_X[24]) );
OR2X1TS U963 ( .A(d_ff_Xn[14]), .B(n1305), .Y(first_mux_X[14]) );
INVX4TS U964 ( .A(n997), .Y(n1169) );
OR2X1TS U965 ( .A(d_ff_Xn[49]), .B(n1169), .Y(first_mux_X[49]) );
OR2X1TS U966 ( .A(d_ff_Xn[55]), .B(n1309), .Y(first_mux_X[55]) );
OR2X1TS U967 ( .A(d_ff_Xn[43]), .B(n1313), .Y(first_mux_X[43]) );
OR2X1TS U968 ( .A(d_ff_Xn[58]), .B(n1169), .Y(first_mux_X[58]) );
OR2X1TS U969 ( .A(d_ff_Xn[28]), .B(n1305), .Y(first_mux_X[28]) );
OR2X1TS U970 ( .A(d_ff_Xn[54]), .B(n1307), .Y(first_mux_X[54]) );
OR2X1TS U971 ( .A(d_ff_Xn[34]), .B(n1324), .Y(first_mux_X[34]) );
OR2X1TS U972 ( .A(d_ff_Xn[56]), .B(n1169), .Y(first_mux_X[56]) );
OR2X1TS U973 ( .A(d_ff_Xn[48]), .B(n1311), .Y(first_mux_X[48]) );
OR2X1TS U974 ( .A(d_ff_Xn[57]), .B(n1326), .Y(first_mux_X[57]) );
OR2X1TS U975 ( .A(d_ff_Xn[61]), .B(n1313), .Y(first_mux_X[61]) );
OR2X1TS U976 ( .A(d_ff_Xn[35]), .B(n1169), .Y(first_mux_X[35]) );
OR2X1TS U977 ( .A(d_ff_Xn[45]), .B(n1313), .Y(first_mux_X[45]) );
OR2X1TS U978 ( .A(d_ff_Xn[31]), .B(n1305), .Y(first_mux_X[31]) );
OR2X1TS U979 ( .A(d_ff_Xn[42]), .B(n1324), .Y(first_mux_X[42]) );
OR2X1TS U980 ( .A(d_ff_Xn[53]), .B(n1311), .Y(first_mux_X[53]) );
BUFX3TS U981 ( .A(n997), .Y(n1308) );
OR2X1TS U982 ( .A(d_ff_Xn[11]), .B(n1309), .Y(first_mux_X[11]) );
OR2X1TS U983 ( .A(d_ff_Xn[8]), .B(n1326), .Y(first_mux_X[8]) );
OR2X1TS U984 ( .A(d_ff_Xn[13]), .B(n1307), .Y(first_mux_X[13]) );
OR2X1TS U985 ( .A(d_ff_Xn[0]), .B(n1309), .Y(first_mux_X[0]) );
INVX2TS U986 ( .A(ITER_CONT_N3), .Y(n988) );
NOR4X1TS U987 ( .A(enab_RB3), .B(inst_CORDIC_FSM_v3_state_next[3]), .C(
enab_d_ff_RB1), .D(beg_add_subt), .Y(n1170) );
AOI32X1TS U988 ( .A0(n1170), .A1(n1333), .A2(n1332), .B0(ready_cordic), .B1(
ack_cordic), .Y(n1171) );
OAI21XLTS U989 ( .A0(beg_fsm_cordic), .A1(n1327), .B0(n1171), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
BUFX4TS U990 ( .A(n1358), .Y(n1258) );
AOI222X1TS U991 ( .A0(n1287), .A1(d_ff2_X[41]), .B0(n1286), .B1(d_ff2_Y[41]),
.C0(n1258), .C1(d_ff2_Z[41]), .Y(n1172) );
INVX2TS U992 ( .A(n1172), .Y(add_subt_dataA[41]) );
AOI222X1TS U993 ( .A0(n1256), .A1(d_ff2_X[26]), .B0(n1286), .B1(d_ff2_Y[26]),
.C0(n1197), .C1(d_ff2_Z[26]), .Y(n1173) );
INVX2TS U994 ( .A(n1173), .Y(add_subt_dataA[26]) );
AOI222X1TS U995 ( .A0(n1344), .A1(d_ff2_X[21]), .B0(n1286), .B1(d_ff2_Y[21]),
.C0(n1197), .C1(d_ff2_Z[21]), .Y(n1174) );
INVX2TS U996 ( .A(n1174), .Y(add_subt_dataA[21]) );
BUFX4TS U997 ( .A(n1358), .Y(n1255) );
AOI222X1TS U998 ( .A0(n1256), .A1(d_ff2_X[29]), .B0(n1286), .B1(d_ff2_Y[29]),
.C0(n1255), .C1(d_ff2_Z[29]), .Y(n1175) );
INVX2TS U999 ( .A(n1175), .Y(add_subt_dataA[29]) );
AOI222X1TS U1000 ( .A0(n1256), .A1(d_ff2_X[44]), .B0(n1291), .B1(d_ff2_Y[44]), .C0(n1258), .C1(d_ff2_Z[44]), .Y(n1176) );
INVX2TS U1001 ( .A(n1176), .Y(add_subt_dataA[44]) );
AOI222X1TS U1002 ( .A0(n1272), .A1(d_ff2_X[20]), .B0(n1286), .B1(d_ff2_Y[20]), .C0(n1255), .C1(d_ff2_Z[20]), .Y(n1177) );
INVX2TS U1003 ( .A(n1177), .Y(add_subt_dataA[20]) );
AOI222X1TS U1004 ( .A0(n1256), .A1(d_ff2_X[48]), .B0(n1356), .B1(d_ff2_Y[48]), .C0(n1258), .C1(d_ff2_Z[48]), .Y(n1178) );
INVX2TS U1005 ( .A(n1178), .Y(add_subt_dataA[48]) );
AOI222X1TS U1006 ( .A0(n1344), .A1(d_ff2_X[31]), .B0(n1286), .B1(d_ff2_Y[31]), .C0(n1255), .C1(d_ff2_Z[31]), .Y(n1179) );
INVX2TS U1007 ( .A(n1179), .Y(add_subt_dataA[31]) );
AOI222X1TS U1008 ( .A0(n1256), .A1(d_ff2_X[46]), .B0(n1291), .B1(d_ff2_Y[46]), .C0(n1258), .C1(d_ff2_Z[46]), .Y(n1180) );
INVX2TS U1009 ( .A(n1180), .Y(add_subt_dataA[46]) );
AOI222X1TS U1010 ( .A0(n1267), .A1(d_ff2_X[51]), .B0(n1148), .B1(d_ff2_Y[51]), .C0(n1258), .C1(d_ff2_Z[51]), .Y(n1181) );
INVX2TS U1011 ( .A(n1181), .Y(add_subt_dataA[51]) );
AOI222X1TS U1012 ( .A0(n1256), .A1(d_ff2_X[50]), .B0(n1148), .B1(d_ff2_Y[50]), .C0(n1258), .C1(d_ff2_Z[50]), .Y(n1182) );
INVX2TS U1013 ( .A(n1182), .Y(add_subt_dataA[50]) );
AOI222X1TS U1014 ( .A0(n1267), .A1(d_ff2_X[49]), .B0(n1148), .B1(d_ff2_Y[49]), .C0(n1258), .C1(d_ff2_Z[49]), .Y(n1183) );
INVX2TS U1015 ( .A(n1183), .Y(add_subt_dataA[49]) );
AOI222X1TS U1016 ( .A0(n1344), .A1(d_ff2_X[27]), .B0(n1286), .B1(d_ff2_Y[27]), .C0(n1197), .C1(d_ff2_Z[27]), .Y(n1184) );
INVX2TS U1017 ( .A(n1184), .Y(add_subt_dataA[27]) );
AOI222X1TS U1018 ( .A0(n1287), .A1(d_ff2_X[19]), .B0(n1286), .B1(d_ff2_Y[19]), .C0(n1255), .C1(d_ff2_Z[19]), .Y(n1185) );
INVX2TS U1019 ( .A(n1185), .Y(add_subt_dataA[19]) );
AOI222X1TS U1020 ( .A0(n1256), .A1(d_ff2_X[47]), .B0(n1148), .B1(d_ff2_Y[47]), .C0(n1258), .C1(d_ff2_Z[47]), .Y(n1186) );
INVX2TS U1021 ( .A(n1186), .Y(add_subt_dataA[47]) );
AOI222X1TS U1022 ( .A0(n1344), .A1(d_ff2_X[45]), .B0(n1148), .B1(d_ff2_Y[45]), .C0(n1258), .C1(d_ff2_Z[45]), .Y(n1187) );
INVX2TS U1023 ( .A(n1187), .Y(add_subt_dataA[45]) );
AOI222X1TS U1024 ( .A0(n1267), .A1(d_ff2_X[28]), .B0(n1286), .B1(d_ff2_Y[28]), .C0(n1255), .C1(d_ff2_Z[28]), .Y(n1188) );
INVX2TS U1025 ( .A(n1188), .Y(add_subt_dataA[28]) );
INVX2TS U1026 ( .A(n1189), .Y(add_subt_dataA[53]) );
AOI222X1TS U1027 ( .A0(n1256), .A1(d_ff2_X[52]), .B0(n1148), .B1(d_ff2_Y[52]), .C0(n1258), .C1(d_ff2_Z[52]), .Y(n1190) );
INVX2TS U1028 ( .A(n1190), .Y(add_subt_dataA[52]) );
BUFX3TS U1029 ( .A(n1197), .Y(n1264) );
AOI222X1TS U1030 ( .A0(n1287), .A1(d_ff3_sh_y_out[12]), .B0(n1216), .B1(
d_ff3_sh_x_out[12]), .C0(n1264), .C1(d_ff3_LUT_out[12]), .Y(n1191) );
INVX2TS U1031 ( .A(n1191), .Y(add_subt_dataB[12]) );
AOI222X1TS U1032 ( .A0(n1344), .A1(d_ff3_sh_y_out[13]), .B0(n1216), .B1(
d_ff3_sh_x_out[13]), .C0(n1264), .C1(d_ff3_LUT_out[13]), .Y(n1192) );
INVX2TS U1033 ( .A(n1192), .Y(add_subt_dataB[13]) );
AOI222X1TS U1034 ( .A0(n1256), .A1(d_ff3_sh_y_out[14]), .B0(n1216), .B1(
d_ff3_sh_x_out[14]), .C0(n1264), .C1(d_ff3_LUT_out[14]), .Y(n1193) );
INVX2TS U1035 ( .A(n1193), .Y(add_subt_dataB[14]) );
AOI222X1TS U1036 ( .A0(n1287), .A1(d_ff3_sh_y_out[17]), .B0(n1216), .B1(
d_ff3_sh_x_out[17]), .C0(n1264), .C1(d_ff3_LUT_out[17]), .Y(n1194) );
INVX2TS U1037 ( .A(n1194), .Y(add_subt_dataB[17]) );
AOI222X1TS U1038 ( .A0(n1272), .A1(d_ff3_sh_y_out[11]), .B0(n1216), .B1(
d_ff3_sh_x_out[11]), .C0(n1264), .C1(d_ff3_LUT_out[11]), .Y(n1195) );
INVX2TS U1039 ( .A(n1195), .Y(add_subt_dataB[11]) );
AOI222X1TS U1040 ( .A0(n1272), .A1(d_ff3_sh_y_out[15]), .B0(n1216), .B1(
d_ff3_sh_x_out[15]), .C0(n1264), .C1(d_ff3_LUT_out[15]), .Y(n1196) );
INVX2TS U1041 ( .A(n1196), .Y(add_subt_dataB[15]) );
AOI222X1TS U1042 ( .A0(n1272), .A1(d_ff3_sh_y_out[8]), .B0(n1216), .B1(
d_ff3_sh_x_out[8]), .C0(n1197), .C1(d_ff3_LUT_out[8]), .Y(n1198) );
INVX2TS U1043 ( .A(n1198), .Y(add_subt_dataB[8]) );
AOI222X1TS U1044 ( .A0(n1287), .A1(d_ff3_sh_y_out[9]), .B0(n1216), .B1(
d_ff3_sh_x_out[9]), .C0(n1197), .C1(d_ff3_LUT_out[9]), .Y(n1199) );
INVX2TS U1045 ( .A(n1199), .Y(add_subt_dataB[9]) );
AOI222X1TS U1046 ( .A0(n1272), .A1(d_ff3_sh_y_out[10]), .B0(n1216), .B1(
d_ff3_sh_x_out[10]), .C0(n1264), .C1(d_ff3_LUT_out[10]), .Y(n1200) );
INVX2TS U1047 ( .A(n1200), .Y(add_subt_dataB[10]) );
AOI222X1TS U1048 ( .A0(n1256), .A1(d_ff3_sh_y_out[6]), .B0(n1216), .B1(
d_ff3_sh_x_out[6]), .C0(n1197), .C1(d_ff3_LUT_out[6]), .Y(n1201) );
INVX2TS U1049 ( .A(n1201), .Y(add_subt_dataB[6]) );
AOI222X1TS U1050 ( .A0(n1267), .A1(d_ff3_sh_y_out[16]), .B0(n1216), .B1(
d_ff3_sh_x_out[16]), .C0(n1264), .C1(d_ff3_LUT_out[16]), .Y(n1202) );
INVX2TS U1051 ( .A(n1202), .Y(add_subt_dataB[16]) );
INVX4TS U1052 ( .A(n1147), .Y(n1348) );
AOI222X1TS U1053 ( .A0(n1348), .A1(d_ff2_X[11]), .B0(n1286), .B1(d_ff2_Y[11]), .C0(n1255), .C1(d_ff2_Z[11]), .Y(n1203) );
INVX2TS U1054 ( .A(n1203), .Y(add_subt_dataA[11]) );
AOI222X1TS U1055 ( .A0(n1348), .A1(d_ff2_X[14]), .B0(n1286), .B1(d_ff2_Y[14]), .C0(n1255), .C1(d_ff2_Z[14]), .Y(n1204) );
INVX2TS U1056 ( .A(n1204), .Y(add_subt_dataA[14]) );
AOI22X1TS U1057 ( .A0(n1356), .A1(d_ff2_Y[59]), .B0(n1290), .B1(d_ff2_Z[59]),
.Y(n1205) );
AOI222X1TS U1058 ( .A0(n1256), .A1(d_ff3_sh_y_out[7]), .B0(n1216), .B1(
d_ff3_sh_x_out[7]), .C0(n1197), .C1(d_ff3_LUT_out[7]), .Y(n1207) );
INVX2TS U1059 ( .A(n1207), .Y(add_subt_dataB[7]) );
INVX2TS U1060 ( .A(n1208), .Y(add_subt_dataA[4]) );
AOI222X1TS U1061 ( .A0(n1256), .A1(d_ff3_sh_y_out[41]), .B0(n1284), .B1(
d_ff3_sh_x_out[41]), .C0(n1355), .C1(d_ff3_LUT_out[41]), .Y(n1209) );
INVX2TS U1062 ( .A(n1209), .Y(add_subt_dataB[41]) );
AOI222X1TS U1063 ( .A0(n1272), .A1(d_ff3_sh_y_out[53]), .B0(n1284), .B1(
d_ff3_sh_x_out[53]), .C0(n1355), .C1(d_ff3_LUT_out[53]), .Y(n1210) );
INVX2TS U1064 ( .A(n1210), .Y(add_subt_dataB[53]) );
INVX2TS U1065 ( .A(n1211), .Y(add_subt_dataA[1]) );
AOI222X1TS U1066 ( .A0(n1256), .A1(d_ff3_sh_y_out[55]), .B0(n1284), .B1(
d_ff3_sh_x_out[55]), .C0(n1355), .C1(d_ff3_LUT_out[55]), .Y(n1212) );
INVX2TS U1067 ( .A(n1212), .Y(add_subt_dataB[55]) );
AOI222X1TS U1068 ( .A0(n1359), .A1(d_ff2_X[2]), .B0(n1356), .B1(d_ff2_Y[2]),
.C0(n1355), .C1(d_ff2_Z[2]), .Y(n1213) );
INVX2TS U1069 ( .A(n1213), .Y(add_subt_dataA[2]) );
INVX2TS U1070 ( .A(n1214), .Y(add_subt_dataA[38]) );
INVX2TS U1071 ( .A(n1215), .Y(add_subt_dataA[39]) );
AOI222X1TS U1072 ( .A0(n1344), .A1(d_ff3_sh_y_out[3]), .B0(n1259), .B1(
d_ff3_sh_x_out[3]), .C0(n1197), .C1(d_ff3_LUT_out[3]), .Y(n1217) );
INVX2TS U1073 ( .A(n1217), .Y(add_subt_dataB[3]) );
INVX2TS U1074 ( .A(n1218), .Y(add_subt_dataA[61]) );
AOI222X1TS U1075 ( .A0(n1287), .A1(d_ff3_sh_y_out[2]), .B0(n1259), .B1(
d_ff3_sh_x_out[2]), .C0(n1197), .C1(d_ff3_LUT_out[2]), .Y(n1219) );
INVX2TS U1076 ( .A(n1219), .Y(add_subt_dataB[2]) );
AOI222X1TS U1077 ( .A0(n1344), .A1(d_ff3_sh_y_out[0]), .B0(n1259), .B1(
d_ff3_sh_x_out[0]), .C0(n1197), .C1(d_ff3_LUT_out[0]), .Y(n1220) );
INVX2TS U1078 ( .A(n1220), .Y(add_subt_dataB[0]) );
AOI222X1TS U1079 ( .A0(n1272), .A1(d_ff2_X[63]), .B0(n1259), .B1(d_ff2_Y[63]), .C0(n1197), .C1(d_ff2_Z[63]), .Y(n1221) );
INVX2TS U1080 ( .A(n1221), .Y(add_subt_dataA[63]) );
AOI222X1TS U1081 ( .A0(n1272), .A1(d_ff2_X[62]), .B0(n1259), .B1(d_ff2_Y[62]), .C0(n1197), .C1(d_ff2_Z[62]), .Y(n1222) );
INVX2TS U1082 ( .A(n1222), .Y(add_subt_dataA[62]) );
AOI222X1TS U1083 ( .A0(n1344), .A1(d_ff3_sh_y_out[5]), .B0(n1259), .B1(
d_ff3_sh_x_out[5]), .C0(n1197), .C1(d_ff3_LUT_out[5]), .Y(n1223) );
INVX2TS U1084 ( .A(n1223), .Y(add_subt_dataB[5]) );
INVX2TS U1085 ( .A(n1224), .Y(add_subt_dataA[60]) );
AOI222X1TS U1086 ( .A0(n1287), .A1(d_ff3_sh_y_out[18]), .B0(n1259), .B1(
d_ff3_sh_x_out[18]), .C0(n1264), .C1(d_ff3_LUT_out[18]), .Y(n1225) );
INVX2TS U1087 ( .A(n1225), .Y(add_subt_dataB[18]) );
AOI222X1TS U1088 ( .A0(n1344), .A1(d_ff3_sh_y_out[1]), .B0(n1259), .B1(
d_ff3_sh_x_out[1]), .C0(n1197), .C1(d_ff3_LUT_out[1]), .Y(n1226) );
INVX2TS U1089 ( .A(n1226), .Y(add_subt_dataB[1]) );
BUFX3TS U1090 ( .A(n1286), .Y(n1251) );
INVX2TS U1091 ( .A(n1227), .Y(add_subt_dataA[5]) );
INVX2TS U1092 ( .A(n1228), .Y(add_subt_dataA[8]) );
INVX2TS U1093 ( .A(n1229), .Y(add_subt_dataA[3]) );
INVX2TS U1094 ( .A(n1230), .Y(add_subt_dataA[6]) );
INVX2TS U1095 ( .A(n1231), .Y(add_subt_dataA[40]) );
INVX2TS U1096 ( .A(n1232), .Y(add_subt_dataA[37]) );
INVX2TS U1097 ( .A(n1233), .Y(add_subt_dataA[36]) );
INVX2TS U1098 ( .A(n1234), .Y(add_subt_dataA[34]) );
INVX2TS U1099 ( .A(n1235), .Y(add_subt_dataA[35]) );
INVX2TS U1100 ( .A(n1236), .Y(add_subt_dataA[0]) );
INVX2TS U1101 ( .A(n1237), .Y(add_subt_dataA[32]) );
INVX2TS U1102 ( .A(n1238), .Y(add_subt_dataA[33]) );
INVX2TS U1103 ( .A(n1239), .Y(add_subt_dataA[18]) );
INVX2TS U1104 ( .A(n1240), .Y(add_subt_dataA[16]) );
INVX2TS U1105 ( .A(n1241), .Y(add_subt_dataA[7]) );
INVX2TS U1106 ( .A(n1242), .Y(add_subt_dataA[13]) );
INVX2TS U1107 ( .A(n1243), .Y(add_subt_dataA[9]) );
INVX2TS U1108 ( .A(n1244), .Y(add_subt_dataA[10]) );
INVX2TS U1109 ( .A(n1245), .Y(add_subt_dataA[55]) );
INVX2TS U1110 ( .A(n1246), .Y(add_subt_dataA[12]) );
AOI222X1TS U1111 ( .A0(n1256), .A1(d_ff2_X[57]), .B0(n1259), .B1(d_ff2_Y[57]), .C0(n1258), .C1(d_ff2_Z[57]), .Y(n1247) );
INVX2TS U1112 ( .A(n1247), .Y(add_subt_dataA[57]) );
INVX2TS U1113 ( .A(n1248), .Y(add_subt_dataA[43]) );
INVX2TS U1114 ( .A(n1249), .Y(add_subt_dataA[15]) );
INVX2TS U1115 ( .A(n1250), .Y(add_subt_dataA[54]) );
INVX2TS U1116 ( .A(n1252), .Y(add_subt_dataA[17]) );
INVX2TS U1117 ( .A(n1253), .Y(add_subt_dataA[42]) );
INVX2TS U1118 ( .A(n1254), .Y(add_subt_dataA[58]) );
INVX2TS U1119 ( .A(n1257), .Y(add_subt_dataA[30]) );
INVX2TS U1120 ( .A(n1260), .Y(add_subt_dataA[56]) );
INVX2TS U1121 ( .A(ready_add_subt), .Y(n1298) );
NOR2XLTS U1122 ( .A(n1298), .B(n1147), .Y(enab_d_ff4_Yn) );
INVX4TS U1123 ( .A(n1147), .Y(n1344) );
INVX2TS U1124 ( .A(n1261), .Y(add_subt_dataB[22]) );
INVX2TS U1125 ( .A(n1262), .Y(add_subt_dataB[20]) );
INVX2TS U1126 ( .A(n1263), .Y(add_subt_dataB[21]) );
INVX2TS U1127 ( .A(n1265), .Y(add_subt_dataB[19]) );
AOI222X1TS U1128 ( .A0(n1287), .A1(d_ff3_sh_y_out[56]), .B0(n1291), .B1(
d_ff3_sh_x_out[56]), .C0(n1355), .C1(d_ff3_LUT_out[56]), .Y(n1266) );
INVX2TS U1129 ( .A(n1266), .Y(add_subt_dataB[56]) );
INVX2TS U1130 ( .A(n1268), .Y(add_subt_dataA[24]) );
AOI222X1TS U1131 ( .A0(n1272), .A1(d_ff3_sh_y_out[26]), .B0(n1291), .B1(
d_ff3_sh_x_out[26]), .C0(n1355), .C1(d_ff3_LUT_out[26]), .Y(n1269) );
INVX2TS U1132 ( .A(n1269), .Y(add_subt_dataB[26]) );
AOI222X1TS U1133 ( .A0(n1344), .A1(d_ff3_sh_y_out[52]), .B0(n1284), .B1(
d_ff3_sh_x_out[52]), .C0(n1355), .C1(d_ff3_LUT_out[52]), .Y(n1270) );
INVX2TS U1134 ( .A(n1270), .Y(add_subt_dataB[52]) );
AOI222X1TS U1135 ( .A0(n1267), .A1(d_ff3_sh_y_out[33]), .B0(n1291), .B1(
d_ff3_sh_x_out[33]), .C0(n1355), .C1(d_ff3_LUT_out[33]), .Y(n1271) );
INVX2TS U1136 ( .A(n1271), .Y(add_subt_dataB[33]) );
AOI222X1TS U1137 ( .A0(n1272), .A1(d_ff2_X[22]), .B0(n1286), .B1(d_ff2_Y[22]), .C0(n1290), .C1(d_ff2_Z[22]), .Y(n1273) );
INVX2TS U1138 ( .A(n1273), .Y(add_subt_dataA[22]) );
AOI222X1TS U1139 ( .A0(n1267), .A1(d_ff3_sh_y_out[54]), .B0(n1284), .B1(
d_ff3_sh_x_out[54]), .C0(n1290), .C1(d_ff3_LUT_out[54]), .Y(n1274) );
INVX2TS U1140 ( .A(n1274), .Y(add_subt_dataB[54]) );
AOI222X1TS U1141 ( .A0(n1267), .A1(d_ff3_sh_y_out[37]), .B0(n1284), .B1(
d_ff3_sh_x_out[37]), .C0(n1290), .C1(d_ff3_LUT_out[37]), .Y(n1275) );
INVX2TS U1142 ( .A(n1275), .Y(add_subt_dataB[37]) );
AOI222X1TS U1143 ( .A0(n1256), .A1(d_ff3_sh_y_out[31]), .B0(n1291), .B1(
d_ff3_sh_x_out[31]), .C0(n1290), .C1(d_ff3_LUT_out[31]), .Y(n1276) );
INVX2TS U1144 ( .A(n1276), .Y(add_subt_dataB[31]) );
AOI222X1TS U1145 ( .A0(n1256), .A1(d_ff3_sh_y_out[23]), .B0(n1291), .B1(
d_ff3_sh_x_out[23]), .C0(n1290), .C1(d_ff3_LUT_out[23]), .Y(n1277) );
INVX2TS U1146 ( .A(n1277), .Y(add_subt_dataB[23]) );
AOI222X1TS U1147 ( .A0(n1267), .A1(d_ff3_sh_y_out[45]), .B0(n1284), .B1(
d_ff3_sh_x_out[45]), .C0(n1290), .C1(d_ff3_LUT_out[45]), .Y(n1278) );
INVX2TS U1148 ( .A(n1278), .Y(add_subt_dataB[45]) );
AOI222X1TS U1149 ( .A0(n1256), .A1(d_ff3_sh_y_out[27]), .B0(n1291), .B1(
d_ff3_sh_x_out[27]), .C0(n1290), .C1(d_ff3_LUT_out[27]), .Y(n1279) );
INVX2TS U1150 ( .A(n1279), .Y(add_subt_dataB[27]) );
AOI222X1TS U1151 ( .A0(n1267), .A1(d_ff2_X[23]), .B0(n1286), .B1(d_ff2_Y[23]), .C0(n1290), .C1(d_ff2_Z[23]), .Y(n1280) );
INVX2TS U1152 ( .A(n1280), .Y(add_subt_dataA[23]) );
AOI222X1TS U1153 ( .A0(n1267), .A1(d_ff3_sh_y_out[25]), .B0(n1291), .B1(
d_ff3_sh_x_out[25]), .C0(n1290), .C1(d_ff3_LUT_out[25]), .Y(n1281) );
INVX2TS U1154 ( .A(n1281), .Y(add_subt_dataB[25]) );
AOI222X1TS U1155 ( .A0(n1344), .A1(d_ff3_sh_y_out[39]), .B0(n1284), .B1(
d_ff3_sh_x_out[39]), .C0(n1290), .C1(d_ff3_LUT_out[39]), .Y(n1282) );
INVX2TS U1156 ( .A(n1282), .Y(add_subt_dataB[39]) );
AOI222X1TS U1157 ( .A0(n1287), .A1(d_ff3_sh_y_out[29]), .B0(n1291), .B1(
d_ff3_sh_x_out[29]), .C0(n1290), .C1(d_ff3_LUT_out[29]), .Y(n1283) );
INVX2TS U1158 ( .A(n1283), .Y(add_subt_dataB[29]) );
AOI222X1TS U1159 ( .A0(n1256), .A1(d_ff3_sh_y_out[50]), .B0(n1284), .B1(
d_ff3_sh_x_out[50]), .C0(n1290), .C1(d_ff3_LUT_out[50]), .Y(n1285) );
INVX2TS U1160 ( .A(n1285), .Y(add_subt_dataB[50]) );
AOI222X1TS U1161 ( .A0(n1256), .A1(d_ff2_X[25]), .B0(n1286), .B1(d_ff2_Y[25]), .C0(n1290), .C1(d_ff2_Z[25]), .Y(n1288) );
INVX2TS U1162 ( .A(n1288), .Y(add_subt_dataA[25]) );
AOI222X1TS U1163 ( .A0(n1344), .A1(d_ff3_sh_y_out[24]), .B0(n1291), .B1(
d_ff3_sh_x_out[24]), .C0(n1290), .C1(d_ff3_LUT_out[24]), .Y(n1289) );
INVX2TS U1164 ( .A(n1289), .Y(add_subt_dataB[24]) );
AOI222X1TS U1165 ( .A0(n1287), .A1(d_ff3_sh_y_out[35]), .B0(n1291), .B1(
d_ff3_sh_x_out[35]), .C0(n1290), .C1(d_ff3_LUT_out[35]), .Y(n1292) );
INVX2TS U1166 ( .A(n1292), .Y(add_subt_dataB[35]) );
INVX2TS U1167 ( .A(n1382), .Y(n1383) );
AOI21X1TS U1168 ( .A0(n1383), .A1(cont_var_out[1]), .B0(n1356), .Y(n1293) );
OAI21XLTS U1169 ( .A0(n1147), .A1(n1383), .B0(n1293), .Y(n961) );
NAND2X1TS U1170 ( .A(n1365), .B(n1363), .Y(n1295) );
OAI211XLTS U1171 ( .A0(cont_iter_out[2]), .A1(n1399), .B0(n1296), .C0(n1295),
.Y(n962) );
AOI31XLTS U1172 ( .A0(cont_iter_out[1]), .A1(n1396), .A2(n1371), .B0(n1380),
.Y(data_out_LUT[0]) );
OAI32X1TS U1173 ( .A0(n1134), .A1(cont_iter_out[2]), .A2(n1366), .B0(
cont_iter_out[1]), .B1(n1369), .Y(n994) );
NOR3XLTS U1174 ( .A(cont_var_out[0]), .B(cont_var_out[1]), .C(n1298), .Y(
enab_d_ff4_Xn) );
AOI22X1TS U1176 ( .A0(n1365), .A1(n1396), .B0(n1140), .B1(n1364), .Y(
data_out_LUT[6]) );
AOI22X1TS U1177 ( .A0(cont_iter_out[1]), .A1(n1366), .B0(n1299), .B1(n1134),
.Y(data_out_LUT[39]) );
NAND2X1TS U1178 ( .A(d_ff1_shift_region_flag_out[1]), .B(n1141), .Y(n1302)
);
OAI21XLTS U1179 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n1141), .B0(n1302), .Y(n1300) );
XOR2X1TS U1180 ( .A(n1144), .B(n1300), .Y(n1301) );
AOI22X1TS U1181 ( .A0(n1316), .A1(d_ff_Yn[63]), .B0(d_ff_Xn[63]), .B1(n1318),
.Y(n1304) );
XNOR2X1TS U1182 ( .A(n1304), .B(n1303), .Y(fmtted_Result_63_) );
NAND2X1TS U1183 ( .A(n1366), .B(n1396), .Y(n998) );
NOR2BX1TS U1184 ( .AN(d_ff_Yn[0]), .B(n1325), .Y(first_mux_Y[0]) );
NOR2BX1TS U1185 ( .AN(d_ff_Yn[1]), .B(n1307), .Y(first_mux_Y[1]) );
NOR2BX1TS U1186 ( .AN(d_ff_Yn[2]), .B(n1169), .Y(first_mux_Y[2]) );
NOR2BX1TS U1187 ( .AN(d_ff_Yn[3]), .B(n1313), .Y(first_mux_Y[3]) );
NOR2BX1TS U1188 ( .AN(d_ff_Yn[4]), .B(n1305), .Y(first_mux_Y[4]) );
NOR2BX1TS U1189 ( .AN(d_ff_Yn[5]), .B(n1324), .Y(first_mux_Y[5]) );
NOR2BX1TS U1190 ( .AN(d_ff_Yn[6]), .B(n1311), .Y(first_mux_Y[6]) );
NOR2BX1TS U1191 ( .AN(d_ff_Yn[7]), .B(n1169), .Y(first_mux_Y[7]) );
NOR2BX1TS U1192 ( .AN(d_ff_Yn[8]), .B(n1313), .Y(first_mux_Y[8]) );
NOR2BX1TS U1193 ( .AN(d_ff_Yn[9]), .B(n1323), .Y(first_mux_Y[9]) );
NOR2BX1TS U1194 ( .AN(d_ff_Yn[10]), .B(n1324), .Y(first_mux_Y[10]) );
NOR2BX1TS U1195 ( .AN(d_ff_Yn[11]), .B(n1305), .Y(first_mux_Y[11]) );
NOR2BX1TS U1196 ( .AN(d_ff_Yn[12]), .B(n1307), .Y(first_mux_Y[12]) );
NOR2BX1TS U1197 ( .AN(d_ff_Yn[13]), .B(n1307), .Y(first_mux_Y[13]) );
NOR2BX1TS U1198 ( .AN(d_ff_Yn[14]), .B(n1323), .Y(first_mux_Y[14]) );
NOR2BX1TS U1199 ( .AN(d_ff_Yn[15]), .B(n1325), .Y(first_mux_Y[15]) );
NOR2BX1TS U1200 ( .AN(d_ff_Yn[16]), .B(n1309), .Y(first_mux_Y[16]) );
NOR2BX1TS U1201 ( .AN(d_ff_Yn[17]), .B(n1309), .Y(first_mux_Y[17]) );
NOR2BX1TS U1202 ( .AN(d_ff_Yn[18]), .B(n1307), .Y(first_mux_Y[18]) );
NOR2BX1TS U1203 ( .AN(d_ff_Yn[19]), .B(n1326), .Y(first_mux_Y[19]) );
NOR2BX1TS U1204 ( .AN(d_ff_Yn[20]), .B(n1326), .Y(first_mux_Y[20]) );
NOR2BX1TS U1205 ( .AN(d_ff_Yn[21]), .B(n1305), .Y(first_mux_Y[21]) );
NOR2BX1TS U1206 ( .AN(d_ff_Yn[22]), .B(n1324), .Y(first_mux_Y[22]) );
NOR2BX1TS U1207 ( .AN(d_ff_Yn[23]), .B(n1311), .Y(first_mux_Y[23]) );
NOR2BX1TS U1208 ( .AN(d_ff_Yn[24]), .B(n1169), .Y(first_mux_Y[24]) );
NOR2BX1TS U1209 ( .AN(d_ff_Yn[25]), .B(n1313), .Y(first_mux_Y[25]) );
NOR2BX1TS U1210 ( .AN(d_ff_Yn[26]), .B(n1305), .Y(first_mux_Y[26]) );
NOR2BX1TS U1211 ( .AN(d_ff_Yn[27]), .B(n1324), .Y(first_mux_Y[27]) );
NOR2BX1TS U1212 ( .AN(d_ff_Yn[28]), .B(n1311), .Y(first_mux_Y[28]) );
NOR2BX1TS U1213 ( .AN(d_ff_Yn[29]), .B(n1324), .Y(first_mux_Y[29]) );
NOR2BX1TS U1214 ( .AN(d_ff_Yn[30]), .B(n1311), .Y(first_mux_Y[30]) );
NOR2BX1TS U1215 ( .AN(d_ff_Yn[31]), .B(n1169), .Y(first_mux_Y[31]) );
NOR2BX1TS U1216 ( .AN(d_ff_Yn[32]), .B(n1313), .Y(first_mux_Y[32]) );
NOR2BX1TS U1217 ( .AN(d_ff_Yn[33]), .B(n1135), .Y(first_mux_Y[33]) );
NOR2BX1TS U1218 ( .AN(d_ff_Yn[34]), .B(n1309), .Y(first_mux_Y[34]) );
NOR2BX1TS U1219 ( .AN(d_ff_Yn[35]), .B(n1135), .Y(first_mux_Y[35]) );
NOR2BX1TS U1220 ( .AN(d_ff_Yn[36]), .B(n1307), .Y(first_mux_Y[36]) );
NOR2BX1TS U1221 ( .AN(d_ff_Yn[37]), .B(n1135), .Y(first_mux_Y[37]) );
NOR2BX1TS U1222 ( .AN(d_ff_Yn[38]), .B(n1311), .Y(first_mux_Y[38]) );
NOR2BX1TS U1223 ( .AN(d_ff_Yn[39]), .B(n1135), .Y(first_mux_Y[39]) );
NOR2BX1TS U1224 ( .AN(d_ff_Yn[40]), .B(n1309), .Y(first_mux_Y[40]) );
NOR2BX1TS U1225 ( .AN(d_ff_Yn[41]), .B(n1135), .Y(first_mux_Y[41]) );
NOR2BX1TS U1226 ( .AN(d_ff_Yn[42]), .B(n1135), .Y(first_mux_Y[42]) );
NOR2BX1TS U1227 ( .AN(d_ff_Yn[43]), .B(n1326), .Y(first_mux_Y[43]) );
NOR2BX1TS U1228 ( .AN(d_ff_Yn[44]), .B(n1135), .Y(first_mux_Y[44]) );
NOR2BX1TS U1229 ( .AN(d_ff_Yn[45]), .B(n1323), .Y(first_mux_Y[45]) );
NOR2BX1TS U1230 ( .AN(d_ff_Yn[46]), .B(n1307), .Y(first_mux_Y[46]) );
NOR2BX1TS U1231 ( .AN(d_ff_Yn[47]), .B(n1323), .Y(first_mux_Y[47]) );
NOR2BX1TS U1232 ( .AN(d_ff_Yn[48]), .B(n1323), .Y(first_mux_Y[48]) );
NOR2BX1TS U1233 ( .AN(d_ff_Yn[49]), .B(n1309), .Y(first_mux_Y[49]) );
NOR2BX1TS U1234 ( .AN(d_ff_Yn[50]), .B(n1135), .Y(first_mux_Y[50]) );
NOR2BX1TS U1235 ( .AN(d_ff_Yn[51]), .B(n1309), .Y(first_mux_Y[51]) );
NOR2BX1TS U1236 ( .AN(d_ff_Yn[52]), .B(n1309), .Y(first_mux_Y[52]) );
NOR2BX1TS U1237 ( .AN(d_ff_Yn[53]), .B(n1323), .Y(first_mux_Y[53]) );
NOR2BX1TS U1238 ( .AN(d_ff_Yn[54]), .B(n1309), .Y(first_mux_Y[54]) );
NOR2BX1TS U1239 ( .AN(d_ff_Yn[55]), .B(n1307), .Y(first_mux_Y[55]) );
NOR2BX1TS U1240 ( .AN(d_ff_Yn[56]), .B(n1307), .Y(first_mux_Y[56]) );
NOR2BX1TS U1241 ( .AN(d_ff_Yn[57]), .B(n1326), .Y(first_mux_Y[57]) );
NOR2BX1TS U1242 ( .AN(d_ff_Yn[58]), .B(n1326), .Y(first_mux_Y[58]) );
NOR2BX1TS U1243 ( .AN(d_ff_Yn[59]), .B(n1326), .Y(first_mux_Y[59]) );
NOR2BX1TS U1244 ( .AN(d_ff_Yn[60]), .B(n1323), .Y(first_mux_Y[60]) );
NOR2BX1TS U1245 ( .AN(d_ff_Yn[61]), .B(n1325), .Y(first_mux_Y[61]) );
NOR2BX1TS U1246 ( .AN(d_ff_Yn[62]), .B(n1135), .Y(first_mux_Y[62]) );
NOR2BX1TS U1247 ( .AN(d_ff_Yn[63]), .B(n1326), .Y(first_mux_Y[63]) );
AO22XLTS U1248 ( .A0(n1313), .A1(d_ff1_Z[0]), .B0(n1308), .B1(d_ff_Zn[0]),
.Y(first_mux_Z[0]) );
AO22XLTS U1249 ( .A0(n1135), .A1(d_ff1_Z[1]), .B0(n1308), .B1(d_ff_Zn[1]),
.Y(first_mux_Z[1]) );
AO22XLTS U1250 ( .A0(n1326), .A1(d_ff1_Z[2]), .B0(n997), .B1(d_ff_Zn[2]),
.Y(first_mux_Z[2]) );
AO22XLTS U1251 ( .A0(n1309), .A1(d_ff1_Z[3]), .B0(n997), .B1(d_ff_Zn[3]),
.Y(first_mux_Z[3]) );
AO22XLTS U1252 ( .A0(n1309), .A1(d_ff1_Z[4]), .B0(n997), .B1(d_ff_Zn[4]),
.Y(first_mux_Z[4]) );
AO22XLTS U1253 ( .A0(n1135), .A1(d_ff1_Z[5]), .B0(n997), .B1(d_ff_Zn[5]),
.Y(first_mux_Z[5]) );
AO22XLTS U1254 ( .A0(n1326), .A1(d_ff1_Z[6]), .B0(n997), .B1(d_ff_Zn[6]),
.Y(first_mux_Z[6]) );
AO22XLTS U1255 ( .A0(n1325), .A1(d_ff1_Z[7]), .B0(n1308), .B1(d_ff_Zn[7]),
.Y(first_mux_Z[7]) );
AO22XLTS U1256 ( .A0(n1323), .A1(d_ff1_Z[8]), .B0(n997), .B1(d_ff_Zn[8]),
.Y(first_mux_Z[8]) );
AO22XLTS U1257 ( .A0(n1309), .A1(d_ff1_Z[9]), .B0(n997), .B1(d_ff_Zn[9]),
.Y(first_mux_Z[9]) );
AO22XLTS U1258 ( .A0(n1326), .A1(d_ff1_Z[10]), .B0(n1308), .B1(d_ff_Zn[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U1259 ( .A0(n1307), .A1(d_ff1_Z[11]), .B0(n997), .B1(d_ff_Zn[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U1260 ( .A0(n1307), .A1(d_ff1_Z[12]), .B0(n1308), .B1(d_ff_Zn[12]),
.Y(first_mux_Z[12]) );
BUFX4TS U1261 ( .A(n997), .Y(n1310) );
AO22XLTS U1262 ( .A0(n1326), .A1(d_ff1_Z[13]), .B0(n1310), .B1(d_ff_Zn[13]),
.Y(first_mux_Z[13]) );
BUFX3TS U1263 ( .A(n997), .Y(n1314) );
AO22XLTS U1264 ( .A0(n1325), .A1(d_ff1_Z[14]), .B0(n1314), .B1(d_ff_Zn[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U1265 ( .A0(n1307), .A1(d_ff1_Z[15]), .B0(n1310), .B1(d_ff_Zn[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U1266 ( .A0(n1323), .A1(d_ff1_Z[16]), .B0(n1314), .B1(d_ff_Zn[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U1267 ( .A0(n1307), .A1(d_ff1_Z[17]), .B0(n1310), .B1(d_ff_Zn[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U1268 ( .A0(n1311), .A1(d_ff1_Z[18]), .B0(n1314), .B1(d_ff_Zn[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U1269 ( .A0(n1307), .A1(d_ff1_Z[19]), .B0(n1310), .B1(d_ff_Zn[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U1270 ( .A0(n1323), .A1(d_ff1_Z[20]), .B0(n1310), .B1(d_ff_Zn[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U1271 ( .A0(n1326), .A1(d_ff1_Z[21]), .B0(n1314), .B1(d_ff_Zn[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U1272 ( .A0(n1326), .A1(d_ff1_Z[22]), .B0(n1310), .B1(d_ff_Zn[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U1273 ( .A0(n1135), .A1(d_ff1_Z[23]), .B0(n1310), .B1(d_ff_Zn[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U1274 ( .A0(n1325), .A1(d_ff1_Z[24]), .B0(n1310), .B1(d_ff_Zn[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U1275 ( .A0(n1323), .A1(d_ff1_Z[25]), .B0(n1310), .B1(d_ff_Zn[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U1276 ( .A0(n1309), .A1(d_ff1_Z[26]), .B0(n1310), .B1(d_ff_Zn[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U1277 ( .A0(n1323), .A1(d_ff1_Z[27]), .B0(n1310), .B1(d_ff_Zn[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U1278 ( .A0(n1323), .A1(d_ff1_Z[28]), .B0(n1310), .B1(d_ff_Zn[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U1279 ( .A0(n1135), .A1(d_ff1_Z[29]), .B0(n1310), .B1(d_ff_Zn[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U1280 ( .A0(n1309), .A1(d_ff1_Z[30]), .B0(n1310), .B1(d_ff_Zn[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U1281 ( .A0(n1135), .A1(d_ff1_Z[31]), .B0(n1310), .B1(d_ff_Zn[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U1282 ( .A0(n1135), .A1(d_ff1_Z[32]), .B0(n1310), .B1(d_ff_Zn[32]),
.Y(first_mux_Z[32]) );
AO22XLTS U1283 ( .A0(n1307), .A1(d_ff1_Z[33]), .B0(n1310), .B1(d_ff_Zn[33]),
.Y(first_mux_Z[33]) );
AO22XLTS U1284 ( .A0(n1309), .A1(d_ff1_Z[34]), .B0(n1314), .B1(d_ff_Zn[34]),
.Y(first_mux_Z[34]) );
AO22XLTS U1285 ( .A0(n1313), .A1(d_ff1_Z[35]), .B0(n1310), .B1(d_ff_Zn[35]),
.Y(first_mux_Z[35]) );
AO22XLTS U1286 ( .A0(n1305), .A1(d_ff1_Z[36]), .B0(n997), .B1(d_ff_Zn[36]),
.Y(first_mux_Z[36]) );
BUFX3TS U1287 ( .A(n997), .Y(n1312) );
AO22XLTS U1288 ( .A0(n1324), .A1(d_ff1_Z[37]), .B0(n1312), .B1(d_ff_Zn[37]),
.Y(first_mux_Z[37]) );
AO22XLTS U1289 ( .A0(n1311), .A1(d_ff1_Z[38]), .B0(n1314), .B1(d_ff_Zn[38]),
.Y(first_mux_Z[38]) );
AO22XLTS U1290 ( .A0(n1169), .A1(d_ff1_Z[39]), .B0(n1310), .B1(d_ff_Zn[39]),
.Y(first_mux_Z[39]) );
AO22XLTS U1291 ( .A0(n1324), .A1(d_ff1_Z[40]), .B0(n997), .B1(d_ff_Zn[40]),
.Y(first_mux_Z[40]) );
AO22XLTS U1292 ( .A0(n1313), .A1(d_ff1_Z[41]), .B0(n1312), .B1(d_ff_Zn[41]),
.Y(first_mux_Z[41]) );
AO22XLTS U1293 ( .A0(n1311), .A1(d_ff1_Z[42]), .B0(n1310), .B1(d_ff_Zn[42]),
.Y(first_mux_Z[42]) );
AO22XLTS U1294 ( .A0(n1169), .A1(d_ff1_Z[43]), .B0(n997), .B1(d_ff_Zn[43]),
.Y(first_mux_Z[43]) );
AO22XLTS U1295 ( .A0(n1305), .A1(d_ff1_Z[44]), .B0(n1312), .B1(d_ff_Zn[44]),
.Y(first_mux_Z[44]) );
AO22XLTS U1296 ( .A0(n1324), .A1(d_ff1_Z[45]), .B0(n1312), .B1(d_ff_Zn[45]),
.Y(first_mux_Z[45]) );
AO22XLTS U1297 ( .A0(n1313), .A1(d_ff1_Z[46]), .B0(n1312), .B1(d_ff_Zn[46]),
.Y(first_mux_Z[46]) );
AO22XLTS U1298 ( .A0(n1305), .A1(d_ff1_Z[47]), .B0(n1312), .B1(d_ff_Zn[47]),
.Y(first_mux_Z[47]) );
AO22XLTS U1299 ( .A0(n1169), .A1(d_ff1_Z[48]), .B0(n1312), .B1(d_ff_Zn[48]),
.Y(first_mux_Z[48]) );
AO22XLTS U1300 ( .A0(n1313), .A1(d_ff1_Z[49]), .B0(n1312), .B1(d_ff_Zn[49]),
.Y(first_mux_Z[49]) );
AO22XLTS U1301 ( .A0(n1311), .A1(d_ff1_Z[50]), .B0(n1312), .B1(d_ff_Zn[50]),
.Y(first_mux_Z[50]) );
AO22XLTS U1302 ( .A0(n1305), .A1(d_ff1_Z[51]), .B0(n1312), .B1(d_ff_Zn[51]),
.Y(first_mux_Z[51]) );
AO22XLTS U1303 ( .A0(n1324), .A1(d_ff1_Z[52]), .B0(n1312), .B1(d_ff_Zn[52]),
.Y(first_mux_Z[52]) );
AO22XLTS U1304 ( .A0(n1169), .A1(d_ff1_Z[53]), .B0(n1312), .B1(d_ff_Zn[53]),
.Y(first_mux_Z[53]) );
AO22XLTS U1305 ( .A0(n1313), .A1(d_ff1_Z[54]), .B0(n1312), .B1(d_ff_Zn[54]),
.Y(first_mux_Z[54]) );
AO22XLTS U1306 ( .A0(n1313), .A1(d_ff1_Z[55]), .B0(n1312), .B1(d_ff_Zn[55]),
.Y(first_mux_Z[55]) );
AO22XLTS U1307 ( .A0(n1311), .A1(d_ff1_Z[56]), .B0(n1314), .B1(d_ff_Zn[56]),
.Y(first_mux_Z[56]) );
AO22XLTS U1308 ( .A0(n1305), .A1(d_ff1_Z[57]), .B0(n1314), .B1(d_ff_Zn[57]),
.Y(first_mux_Z[57]) );
AO22XLTS U1309 ( .A0(n1324), .A1(d_ff1_Z[58]), .B0(n1314), .B1(d_ff_Zn[58]),
.Y(first_mux_Z[58]) );
AO22XLTS U1310 ( .A0(n1169), .A1(d_ff1_Z[59]), .B0(n1314), .B1(d_ff_Zn[59]),
.Y(first_mux_Z[59]) );
AO22XLTS U1311 ( .A0(n1311), .A1(d_ff1_Z[60]), .B0(n1314), .B1(d_ff_Zn[60]),
.Y(first_mux_Z[60]) );
AO22XLTS U1312 ( .A0(n1169), .A1(d_ff1_Z[61]), .B0(n1314), .B1(d_ff_Zn[61]),
.Y(first_mux_Z[61]) );
AO22XLTS U1313 ( .A0(n1305), .A1(d_ff1_Z[62]), .B0(n1314), .B1(d_ff_Zn[62]),
.Y(first_mux_Z[62]) );
AO22XLTS U1314 ( .A0(n1324), .A1(d_ff1_Z[63]), .B0(n1314), .B1(d_ff_Zn[63]),
.Y(first_mux_Z[63]) );
AO22XLTS U1315 ( .A0(n1315), .A1(d_ff_Yn[0]), .B0(n1318), .B1(d_ff_Xn[0]),
.Y(mux_sal[0]) );
AO22XLTS U1316 ( .A0(n1315), .A1(d_ff_Yn[1]), .B0(n1318), .B1(d_ff_Xn[1]),
.Y(mux_sal[1]) );
AO22XLTS U1317 ( .A0(n1315), .A1(d_ff_Yn[2]), .B0(n1318), .B1(d_ff_Xn[2]),
.Y(mux_sal[2]) );
AO22XLTS U1318 ( .A0(n1315), .A1(d_ff_Yn[3]), .B0(n1318), .B1(d_ff_Xn[3]),
.Y(mux_sal[3]) );
BUFX4TS U1319 ( .A(n1318), .Y(n1317) );
AO22XLTS U1320 ( .A0(n1315), .A1(d_ff_Yn[4]), .B0(n1317), .B1(d_ff_Xn[4]),
.Y(mux_sal[4]) );
AO22XLTS U1321 ( .A0(n1315), .A1(d_ff_Yn[5]), .B0(n1317), .B1(d_ff_Xn[5]),
.Y(mux_sal[5]) );
AO22XLTS U1322 ( .A0(n1315), .A1(d_ff_Yn[6]), .B0(n1317), .B1(d_ff_Xn[6]),
.Y(mux_sal[6]) );
AO22XLTS U1323 ( .A0(n1315), .A1(d_ff_Yn[7]), .B0(n1317), .B1(d_ff_Xn[7]),
.Y(mux_sal[7]) );
AO22XLTS U1324 ( .A0(n1315), .A1(d_ff_Yn[8]), .B0(n1317), .B1(d_ff_Xn[8]),
.Y(mux_sal[8]) );
AO22XLTS U1325 ( .A0(n1315), .A1(d_ff_Yn[9]), .B0(n1317), .B1(d_ff_Xn[9]),
.Y(mux_sal[9]) );
AO22XLTS U1326 ( .A0(n1315), .A1(d_ff_Yn[10]), .B0(n1317), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U1327 ( .A0(n1315), .A1(d_ff_Yn[11]), .B0(n1317), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U1328 ( .A0(n1315), .A1(d_ff_Yn[12]), .B0(n1317), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
INVX2TS U1329 ( .A(n1318), .Y(n1316) );
AO22XLTS U1330 ( .A0(n1316), .A1(d_ff_Yn[13]), .B0(n1317), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U1331 ( .A0(n1316), .A1(d_ff_Yn[14]), .B0(n1317), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U1332 ( .A0(n1316), .A1(d_ff_Yn[15]), .B0(n1318), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
BUFX3TS U1333 ( .A(n1318), .Y(n1319) );
AO22XLTS U1334 ( .A0(n1316), .A1(d_ff_Yn[16]), .B0(n1319), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U1335 ( .A0(n1316), .A1(d_ff_Yn[17]), .B0(n1317), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U1336 ( .A0(n1316), .A1(d_ff_Yn[18]), .B0(n1318), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U1337 ( .A0(n1316), .A1(d_ff_Yn[19]), .B0(n1317), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U1338 ( .A0(n1316), .A1(d_ff_Yn[20]), .B0(n1319), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U1339 ( .A0(n1316), .A1(d_ff_Yn[21]), .B0(n1317), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U1340 ( .A0(n1315), .A1(d_ff_Yn[22]), .B0(n1317), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U1341 ( .A0(n1315), .A1(d_ff_Yn[23]), .B0(n1317), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U1342 ( .A0(n1315), .A1(d_ff_Yn[24]), .B0(n1317), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U1343 ( .A0(n1315), .A1(d_ff_Yn[25]), .B0(n1317), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U1344 ( .A0(n1315), .A1(d_ff_Yn[26]), .B0(n1318), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
INVX4TS U1345 ( .A(n1318), .Y(n1320) );
AO22XLTS U1346 ( .A0(n1320), .A1(d_ff_Yn[27]), .B0(n1318), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U1347 ( .A0(n1320), .A1(d_ff_Yn[28]), .B0(n1318), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U1348 ( .A0(n1320), .A1(d_ff_Yn[29]), .B0(n1318), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U1349 ( .A0(n1320), .A1(d_ff_Yn[30]), .B0(n1318), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U1350 ( .A0(n1320), .A1(d_ff_Yn[31]), .B0(n1318), .B1(d_ff_Xn[31]),
.Y(mux_sal[31]) );
AO22XLTS U1351 ( .A0(n1320), .A1(d_ff_Yn[32]), .B0(n1318), .B1(d_ff_Xn[32]),
.Y(mux_sal[32]) );
AO22XLTS U1352 ( .A0(n1320), .A1(d_ff_Yn[33]), .B0(n1318), .B1(d_ff_Xn[33]),
.Y(mux_sal[33]) );
AO22XLTS U1353 ( .A0(n1320), .A1(d_ff_Yn[34]), .B0(n1318), .B1(d_ff_Xn[34]),
.Y(mux_sal[34]) );
AO22XLTS U1354 ( .A0(n1320), .A1(d_ff_Yn[35]), .B0(n1318), .B1(d_ff_Xn[35]),
.Y(mux_sal[35]) );
AO22XLTS U1355 ( .A0(n1320), .A1(d_ff_Yn[36]), .B0(n1317), .B1(d_ff_Xn[36]),
.Y(mux_sal[36]) );
BUFX3TS U1356 ( .A(n1318), .Y(n1321) );
AO22XLTS U1357 ( .A0(n1320), .A1(d_ff_Yn[37]), .B0(n1321), .B1(d_ff_Xn[37]),
.Y(mux_sal[37]) );
AO22XLTS U1358 ( .A0(n1320), .A1(d_ff_Yn[38]), .B0(n1321), .B1(d_ff_Xn[38]),
.Y(mux_sal[38]) );
AO22XLTS U1359 ( .A0(n1320), .A1(d_ff_Yn[39]), .B0(n1321), .B1(d_ff_Xn[39]),
.Y(mux_sal[39]) );
AO22XLTS U1360 ( .A0(n1320), .A1(d_ff_Yn[40]), .B0(n1321), .B1(d_ff_Xn[40]),
.Y(mux_sal[40]) );
INVX4TS U1361 ( .A(n1318), .Y(n1322) );
AO22XLTS U1362 ( .A0(n1322), .A1(d_ff_Yn[41]), .B0(n1321), .B1(d_ff_Xn[41]),
.Y(mux_sal[41]) );
AO22XLTS U1363 ( .A0(n1322), .A1(d_ff_Yn[42]), .B0(n1321), .B1(d_ff_Xn[42]),
.Y(mux_sal[42]) );
AO22XLTS U1364 ( .A0(n1322), .A1(d_ff_Yn[43]), .B0(n1321), .B1(d_ff_Xn[43]),
.Y(mux_sal[43]) );
AO22XLTS U1365 ( .A0(n1322), .A1(d_ff_Yn[44]), .B0(n1321), .B1(d_ff_Xn[44]),
.Y(mux_sal[44]) );
AO22XLTS U1366 ( .A0(n1322), .A1(d_ff_Yn[45]), .B0(n1321), .B1(d_ff_Xn[45]),
.Y(mux_sal[45]) );
AO22XLTS U1367 ( .A0(n1322), .A1(d_ff_Yn[46]), .B0(n1321), .B1(d_ff_Xn[46]),
.Y(mux_sal[46]) );
AO22XLTS U1368 ( .A0(n1322), .A1(d_ff_Yn[47]), .B0(n1321), .B1(d_ff_Xn[47]),
.Y(mux_sal[47]) );
AO22XLTS U1369 ( .A0(n1322), .A1(d_ff_Yn[48]), .B0(n1319), .B1(d_ff_Xn[48]),
.Y(mux_sal[48]) );
AO22XLTS U1370 ( .A0(n1322), .A1(d_ff_Yn[49]), .B0(n1319), .B1(d_ff_Xn[49]),
.Y(mux_sal[49]) );
AO22XLTS U1371 ( .A0(n1322), .A1(d_ff_Yn[50]), .B0(n1319), .B1(d_ff_Xn[50]),
.Y(mux_sal[50]) );
AO22XLTS U1372 ( .A0(n1322), .A1(d_ff_Yn[51]), .B0(n1319), .B1(d_ff_Xn[51]),
.Y(mux_sal[51]) );
AO22XLTS U1373 ( .A0(n1322), .A1(d_ff_Yn[52]), .B0(n1319), .B1(d_ff_Xn[52]),
.Y(mux_sal[52]) );
AO22XLTS U1374 ( .A0(n1322), .A1(d_ff_Yn[53]), .B0(n1319), .B1(d_ff_Xn[53]),
.Y(mux_sal[53]) );
AO22XLTS U1375 ( .A0(n1322), .A1(d_ff_Yn[54]), .B0(n1319), .B1(d_ff_Xn[54]),
.Y(mux_sal[54]) );
AO22XLTS U1376 ( .A0(n1320), .A1(d_ff_Yn[55]), .B0(n1319), .B1(d_ff_Xn[55]),
.Y(mux_sal[55]) );
AO22XLTS U1377 ( .A0(n1322), .A1(d_ff_Yn[56]), .B0(n1319), .B1(d_ff_Xn[56]),
.Y(mux_sal[56]) );
AO22XLTS U1378 ( .A0(n1320), .A1(d_ff_Yn[57]), .B0(n1319), .B1(d_ff_Xn[57]),
.Y(mux_sal[57]) );
AO22XLTS U1379 ( .A0(n1322), .A1(d_ff_Yn[58]), .B0(n1319), .B1(d_ff_Xn[58]),
.Y(mux_sal[58]) );
AO22XLTS U1380 ( .A0(n1320), .A1(d_ff_Yn[59]), .B0(n1317), .B1(d_ff_Xn[59]),
.Y(mux_sal[59]) );
AO22XLTS U1381 ( .A0(n1322), .A1(d_ff_Yn[60]), .B0(n1318), .B1(d_ff_Xn[60]),
.Y(mux_sal[60]) );
AO22XLTS U1382 ( .A0(n1320), .A1(d_ff_Yn[61]), .B0(n1319), .B1(d_ff_Xn[61]),
.Y(mux_sal[61]) );
AO22XLTS U1383 ( .A0(n1322), .A1(d_ff_Yn[62]), .B0(n1321), .B1(d_ff_Xn[62]),
.Y(mux_sal[62]) );
NOR2BX1TS U1384 ( .AN(d_ff_Xn[1]), .B(n1326), .Y(first_mux_X[1]) );
NOR2BX1TS U1385 ( .AN(d_ff_Xn[2]), .B(n1323), .Y(first_mux_X[2]) );
NOR2BX1TS U1386 ( .AN(d_ff_Xn[4]), .B(n1135), .Y(first_mux_X[4]) );
NOR2BX1TS U1387 ( .AN(d_ff_Xn[5]), .B(n1323), .Y(first_mux_X[5]) );
NOR2BX1TS U1388 ( .AN(d_ff_Xn[10]), .B(n1311), .Y(first_mux_X[10]) );
NOR2BX1TS U1389 ( .AN(d_ff_Xn[12]), .B(n1169), .Y(first_mux_X[12]) );
NOR2BX1TS U1390 ( .AN(d_ff_Xn[15]), .B(n1313), .Y(first_mux_X[15]) );
NOR2BX1TS U1391 ( .AN(d_ff_Xn[16]), .B(n1305), .Y(first_mux_X[16]) );
NOR2BX1TS U1392 ( .AN(d_ff_Xn[17]), .B(n1324), .Y(first_mux_X[17]) );
NOR2BX1TS U1393 ( .AN(d_ff_Xn[18]), .B(n1311), .Y(first_mux_X[18]) );
NOR2BX1TS U1394 ( .AN(d_ff_Xn[20]), .B(n1135), .Y(first_mux_X[20]) );
NOR2BX1TS U1395 ( .AN(d_ff_Xn[21]), .B(n1169), .Y(first_mux_X[21]) );
NOR2BX1TS U1396 ( .AN(d_ff_Xn[22]), .B(n1313), .Y(first_mux_X[22]) );
NOR2BX1TS U1397 ( .AN(d_ff_Xn[23]), .B(n1305), .Y(first_mux_X[23]) );
NOR2BX1TS U1398 ( .AN(d_ff_Xn[25]), .B(n1324), .Y(first_mux_X[25]) );
NOR2BX1TS U1399 ( .AN(d_ff_Xn[27]), .B(n1311), .Y(first_mux_X[27]) );
NOR2BX1TS U1400 ( .AN(d_ff_Xn[30]), .B(n1325), .Y(first_mux_X[30]) );
NOR2BX1TS U1401 ( .AN(d_ff_Xn[33]), .B(n1325), .Y(first_mux_X[33]) );
NOR2BX1TS U1402 ( .AN(d_ff_Xn[37]), .B(n1325), .Y(first_mux_X[37]) );
NOR2BX1TS U1403 ( .AN(d_ff_Xn[38]), .B(n1325), .Y(first_mux_X[38]) );
NOR2BX1TS U1404 ( .AN(d_ff_Xn[40]), .B(n1325), .Y(first_mux_X[40]) );
NOR2BX1TS U1405 ( .AN(d_ff_Xn[44]), .B(n1325), .Y(first_mux_X[44]) );
NOR2BX1TS U1406 ( .AN(d_ff_Xn[47]), .B(n1325), .Y(first_mux_X[47]) );
NOR2BX1TS U1407 ( .AN(d_ff_Xn[50]), .B(n1325), .Y(first_mux_X[50]) );
NOR2BX1TS U1408 ( .AN(d_ff_Xn[51]), .B(n1325), .Y(first_mux_X[51]) );
NOR2BX1TS U1409 ( .AN(d_ff_Xn[52]), .B(n1325), .Y(first_mux_X[52]) );
NOR2BX1TS U1410 ( .AN(d_ff_Xn[62]), .B(n1325), .Y(first_mux_X[62]) );
NOR2BX1TS U1411 ( .AN(d_ff_Xn[63]), .B(n1326), .Y(first_mux_X[63]) );
NOR2BX1TS U1412 ( .AN(beg_fsm_cordic), .B(n1327), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI2BB1X1TS U1413 ( .A0N(n985), .A1N(enab_cont_iter), .B0(n1328), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U1414 ( .A0(enab_d_ff4_Zn), .A1(n1331), .B0(n1330), .B1(n1329),
.Y(inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U1415 ( .AN(enab_d_ff4_Zn), .B(n1331), .Y(
inst_CORDIC_FSM_v3_state_next[6]) );
OAI22X1TS U1416 ( .A0(ack_cordic), .A1(n1333), .B0(n985), .B1(n1332), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
OAI22X1TS U1417 ( .A0(n1396), .A1(n1374), .B0(n1378), .B1(cont_iter_out[2]),
.Y(data_out_LUT[54]) );
XOR2XLTS U1418 ( .A(d_ff3_sign_out), .B(cont_var_out[0]), .Y(op_add_subt) );
AOI22X1TS U1419 ( .A0(n1359), .A1(d_ff3_sh_y_out[61]), .B0(n1356), .B1(
d_ff3_sh_x_out[61]), .Y(n1334) );
NAND2X2TS U1420 ( .A(n1355), .B(d_ff3_LUT_out[48]), .Y(n1341) );
NAND2X1TS U1421 ( .A(n1334), .B(n1341), .Y(add_subt_dataB[61]) );
AOI22X1TS U1422 ( .A0(n1348), .A1(d_ff3_sh_y_out[60]), .B0(n1356), .B1(
d_ff3_sh_x_out[60]), .Y(n1335) );
NAND2X1TS U1423 ( .A(n1335), .B(n1341), .Y(add_subt_dataB[60]) );
AOI22X1TS U1424 ( .A0(n1287), .A1(d_ff3_sh_y_out[59]), .B0(n1356), .B1(
d_ff3_sh_x_out[59]), .Y(n1336) );
NAND2X1TS U1425 ( .A(n1336), .B(n1341), .Y(add_subt_dataB[59]) );
AOI22X1TS U1426 ( .A0(n1359), .A1(d_ff3_sh_y_out[58]), .B0(n1356), .B1(
d_ff3_sh_x_out[58]), .Y(n1337) );
NAND2X1TS U1427 ( .A(n1337), .B(n1341), .Y(add_subt_dataB[58]) );
AOI22X1TS U1428 ( .A0(n1267), .A1(d_ff3_sh_y_out[57]), .B0(n1356), .B1(
d_ff3_sh_x_out[57]), .Y(n1338) );
NAND2X1TS U1429 ( .A(n1338), .B(n1341), .Y(add_subt_dataB[57]) );
AOI22X1TS U1430 ( .A0(n1287), .A1(d_ff3_sh_y_out[51]), .B0(n1148), .B1(
d_ff3_sh_x_out[51]), .Y(n1339) );
NAND2X1TS U1431 ( .A(n1339), .B(n1341), .Y(add_subt_dataB[51]) );
AOI22X1TS U1432 ( .A0(n1359), .A1(d_ff3_sh_y_out[49]), .B0(n1148), .B1(
d_ff3_sh_x_out[49]), .Y(n1340) );
NAND2X1TS U1433 ( .A(n1355), .B(d_ff3_LUT_out[44]), .Y(n1346) );
NAND2X1TS U1434 ( .A(n1340), .B(n1346), .Y(add_subt_dataB[49]) );
AOI22X1TS U1435 ( .A0(n1348), .A1(d_ff3_sh_y_out[48]), .B0(n1148), .B1(
d_ff3_sh_x_out[48]), .Y(n1342) );
NAND2X1TS U1436 ( .A(n1342), .B(n1341), .Y(add_subt_dataB[48]) );
AOI22X1TS U1437 ( .A0(n1272), .A1(d_ff3_sh_y_out[47]), .B0(n1356), .B1(
d_ff3_sh_x_out[47]), .Y(n1343) );
OAI2BB1X1TS U1438 ( .A0N(n1290), .A1N(d_ff3_LUT_out[42]), .B0(n1343), .Y(
add_subt_dataB[47]) );
AOI22X1TS U1439 ( .A0(n1272), .A1(d_ff3_sh_y_out[46]), .B0(n1148), .B1(
d_ff3_sh_x_out[46]), .Y(n1345) );
NAND2X1TS U1440 ( .A(n1345), .B(n1346), .Y(add_subt_dataB[46]) );
AOI22X1TS U1441 ( .A0(n1348), .A1(d_ff3_sh_y_out[44]), .B0(n1356), .B1(
d_ff3_sh_x_out[44]), .Y(n1347) );
NAND2X1TS U1442 ( .A(n1347), .B(n1346), .Y(add_subt_dataB[44]) );
AOI22X1TS U1443 ( .A0(n1348), .A1(d_ff3_sh_y_out[42]), .B0(n1356), .B1(
d_ff3_sh_x_out[42]), .Y(n1349) );
OAI2BB1X1TS U1444 ( .A0N(n1290), .A1N(d_ff3_LUT_out[42]), .B0(n1349), .Y(
add_subt_dataB[42]) );
AOI22X1TS U1445 ( .A0(n1359), .A1(d_ff3_sh_y_out[40]), .B0(n1356), .B1(
d_ff3_sh_x_out[40]), .Y(n1350) );
NAND2X1TS U1446 ( .A(n1355), .B(d_ff3_LUT_out[28]), .Y(n1360) );
NAND2X1TS U1447 ( .A(n1350), .B(n1360), .Y(add_subt_dataB[40]) );
AOI22X1TS U1448 ( .A0(n1359), .A1(d_ff3_sh_y_out[38]), .B0(n1356), .B1(
d_ff3_sh_x_out[38]), .Y(n1351) );
OAI2BB1X1TS U1449 ( .A0N(n1290), .A1N(d_ff3_LUT_out[32]), .B0(n1351), .Y(
add_subt_dataB[38]) );
AOI22X1TS U1450 ( .A0(n1359), .A1(d_ff3_sh_y_out[36]), .B0(n1148), .B1(
d_ff3_sh_x_out[36]), .Y(n1352) );
NAND2X1TS U1451 ( .A(n1352), .B(n1360), .Y(add_subt_dataB[36]) );
AOI22X1TS U1452 ( .A0(n1359), .A1(d_ff3_sh_y_out[34]), .B0(n1356), .B1(
d_ff3_sh_x_out[34]), .Y(n1353) );
OAI2BB1X1TS U1453 ( .A0N(n1290), .A1N(d_ff3_LUT_out[34]), .B0(n1353), .Y(
add_subt_dataB[34]) );
AOI22X1TS U1454 ( .A0(n1359), .A1(d_ff3_sh_y_out[32]), .B0(n1356), .B1(
d_ff3_sh_x_out[32]), .Y(n1354) );
OAI2BB1X1TS U1455 ( .A0N(n1290), .A1N(d_ff3_LUT_out[32]), .B0(n1354), .Y(
add_subt_dataB[32]) );
AOI22X1TS U1456 ( .A0(n1359), .A1(d_ff3_sh_y_out[30]), .B0(n1356), .B1(
d_ff3_sh_x_out[30]), .Y(n1357) );
OAI2BB1X1TS U1457 ( .A0N(n1358), .A1N(d_ff3_LUT_out[4]), .B0(n1357), .Y(
add_subt_dataB[30]) );
AOI22X1TS U1458 ( .A0(n1359), .A1(d_ff3_sh_y_out[28]), .B0(n1148), .B1(
d_ff3_sh_x_out[28]), .Y(n1361) );
NAND2X1TS U1459 ( .A(n1361), .B(n1360), .Y(add_subt_dataB[28]) );
NAND2X1TS U1460 ( .A(n1362), .B(n1003), .Y(n996) );
OAI22X1TS U1461 ( .A0(n1134), .A1(n1146), .B0(n1364), .B1(n1363), .Y(n995)
);
AO21XLTS U1462 ( .A0(n1371), .A1(n1146), .B0(n1365), .Y(n993) );
AOI22X1TS U1463 ( .A0(cont_iter_out[1]), .A1(n1145), .B0(n1366), .B1(n1134),
.Y(n992) );
OAI22X1TS U1464 ( .A0(n1378), .A1(n1396), .B0(n1402), .B1(n1134), .Y(n987)
);
AOI22X1TS U1465 ( .A0(cont_iter_out[2]), .A1(n1134), .B0(n1367), .B1(n1369),
.Y(n1373) );
NAND2X1TS U1466 ( .A(n1373), .B(n985), .Y(n986) );
NAND2X1TS U1467 ( .A(n1402), .B(n1374), .Y(n1368) );
OAI21X1TS U1468 ( .A0(n1140), .A1(n1374), .B0(n1368), .Y(n983) );
NAND2X1TS U1469 ( .A(n1378), .B(n1146), .Y(n1372) );
NAND2X1TS U1470 ( .A(n1373), .B(n1372), .Y(n981) );
OAI22X1TS U1471 ( .A0(n1375), .A1(n1374), .B0(n1146), .B1(n988), .Y(n979) );
NAND2X1TS U1472 ( .A(n1402), .B(n1376), .Y(n977) );
NAND2X1TS U1473 ( .A(n1145), .B(n1134), .Y(n1002) );
NAND2X1TS U1474 ( .A(n1145), .B(n1377), .Y(n975) );
NAND2X1TS U1475 ( .A(n1378), .B(n1145), .Y(n974) );
AO21XLTS U1476 ( .A0(cont_iter_out[1]), .A1(n1146), .B0(n1380), .Y(n973) );
NAND2X1TS U1477 ( .A(cont_iter_out[1]), .B(n1145), .Y(n1001) );
AOI22X1TS U1478 ( .A0(n1383), .A1(n1397), .B0(cont_var_out[0]), .B1(n1382),
.Y(n960) );
XOR2XLTS U1480 ( .A(d_ff2_Y[61]), .B(n1388), .Y(sh_exp_y[9]) );
AO21XLTS U1481 ( .A0(d_ff2_Y[60]), .A1(n1384), .B0(n1388), .Y(sh_exp_y[8])
);
AO21XLTS U1482 ( .A0(d_ff2_Y[58]), .A1(n1386), .B0(n1385), .Y(sh_exp_y[6])
);
AO21XLTS U1483 ( .A0(intadd_466_n1), .A1(d_ff2_Y[56]), .B0(n1387), .Y(
sh_exp_y[4]) );
NOR2BX1TS U1484 ( .AN(n1388), .B(d_ff2_Y[61]), .Y(n1389) );
XOR2XLTS U1485 ( .A(n1389), .B(d_ff2_Y[62]), .Y(sh_exp_y[10]) );
XOR2XLTS U1486 ( .A(d_ff2_X[61]), .B(n1394), .Y(sh_exp_x[9]) );
AO21XLTS U1487 ( .A0(d_ff2_X[60]), .A1(n1390), .B0(n1394), .Y(sh_exp_x[8])
);
AO21XLTS U1488 ( .A0(d_ff2_X[58]), .A1(n1392), .B0(n1391), .Y(sh_exp_x[6])
);
AO21XLTS U1489 ( .A0(intadd_465_n1), .A1(d_ff2_X[56]), .B0(n1393), .Y(
sh_exp_x[4]) );
NOR2BX1TS U1490 ( .AN(n1394), .B(d_ff2_X[61]), .Y(n1395) );
XOR2XLTS U1491 ( .A(n1395), .B(d_ff2_X[62]), .Y(sh_exp_x[10]) );
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_MES_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_MES_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_MES
);
localparam N = 4; // Para definir el número de bits del contador (hasta 12->4 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 4'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 5)
begin
if (enUP)
begin
if (q_act >= 4'd11) q_next = 4'd0;
else q_next = q_act + 4'd1;
end
else if (enDOWN)
begin
if (q_act == 4'd0) q_next = 4'd11;
else q_next = q_act - 4'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act + 1'b1;//Suma 1 a todas las cuentas de 0->11 a 1->12
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
8'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
8'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
8'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
8'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
8'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
8'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
8'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
8'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
8'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
8'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
8'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
8'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_MES = {digit1,digit0};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:50:22 05/08/2016
// Design Name:
// Module Name: xorshift
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module xorshift(
input clk,
input rst,
input [127:0] seed,
output [31:0] out
);
reg [31:0] x_q, y_q, z_q, w_q, x_d, y_d, z_d, w_d;
assign out = w_q;
always @(*) begin
x_d = y_q;
y_d = z_q;
z_d = w_q;
w_d = w_q ^ (w_q >> 19) ^ (x_q ^ (x_q << 11)) ^ ((x_q ^ (x_q << 11)) >> 8);
end
always @(posedge clk) begin
// Auto-reset if we're in the all-zero state
if (x_q == 0 && y_q == 0 && z_q == 0 && w_q == 0) begin
x_q <= 32'h8de97cc5;
y_q <= 32'h6144a7eb;
z_q <= 32'h653f6dee;
w_q <= 32'h8b49b282;
end else if (rst) begin
x_q <= seed[127:96];
y_q <= seed[95:64];
z_q <= seed[63:32];
w_q <= seed[31:0];
end else begin
x_q <= x_d;
y_q <= y_d;
z_q <= z_d;
w_q <= w_d;
end
end
endmodule
|
// File ifchain.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
// vhd2vl is Free (libre) Software:
// Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
// Verilog for correctness, ideally with a formal verification tool.
//
// You are welcome to redistribute vhd2vl under certain conditions.
// See the license (GPLv2) file included with the source for details.
// The result of translation follows. Its copyright status should be
// considered unchanged from the original VHDL.
// no timescale needed
module test(
clk,
rstn
);
input clk, rstn;
wire clk;
wire rstn;
wire [3:0] a;
wire [3:0] b;
reg status;
reg [31:0] c[3:0];
always @(posedge clk) begin
if({b[1],a[3:2]} == 3'b 001) begin
status <= 1'b 1;
c[0] <= 16'h FFFF;
end
end
endmodule
|
module tx(output wire ALERT_TransmitSOP_MessageFailed,
output wire ALERT_TransmitSuccessful,
output wire MessageID_mismatch,
output wire SOP_mismatch,
output wire MessageID_SOP_match,
output wire [7:0] TRANSMIT_BYTE_COUNT,
output wire [7:0] TRANSMIT_HEADER_LOW,
output wire [7:0] TRANSMIT_HEADER_HIGH,
output wire [7:0] TRANSMIT_DATA_OBJECTS,
output wire Start_CRCReceiveTimer,
output wire Stop_CRCReceiverTimer,
output wire MessageIDCounter,
output wire MessageID,
input wire [2:0] TRANSMIT,
input wire PRL_Rx_Message_Discard,
input wire Hard_Reset_received,
input wire Cable_Reset_received,
input wire RetryCounter,
input wire CRCReceiveTimer_Timeout,
input wire GoodCRC_Response_from_PHY,
input wire Message_discarded_bus_Idle,
input wire [7:0] TX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_FRAME_TYPE,
input wire CLK,
input wire RESET);
wire RetryCounter_bigger;
wire RetryCounter_smaller;
reg [7:0] CurrentState;
reg [7:0] NextState;
reg [8:0] CRCReceive_timer;
localparam Wait_for_Transmit_Request = 8'b00000001;
localparam Reset_RetryCounter = 8'b00000010;
localparam Construct_Message = 8'b00000100;
localparam Wait_for_PHY_response = 8'b00001000;
localparam Match_MessageID = 8'b00010000;
localparam Check_RetryCounter = 8'b00100000;
localparam Report_Failure = 8'b01000000;
localparam Report_Success = 8'b10000000;
localparam nRetryCounter = 2'b10; //definir el valor maximo
// Logica prox estado
always@( * )
begin
NextState = CurrentState;
case(CurrentState)
Wait_for_Transmit_Request:
begin
if(PRL_Rx_Message_Discard || Hard_Reset_received || Cable_Reset_received) begin NextState = Reset_RetryCounter; end
end
Reset_RetryCounter:
begin
NextState = Construct_Message;
end
Construct_Message:
begin
NextState = Wait_for_PHY_response;
end
Wait_for_PHY_response:
begin
if (GoodCRC_Response_from_PHY) NextState = Match_MessageID;
else if(Message_discarded_bus_Idle || CRCReceiveTimer_Timeout) NextState= Check_RetryCounter;
end
Match_MessageID:
begin
if(MessageID_mismatch || SOP_mismatch) NextState = Check_RetryCounter;
else if(MessageID_SOP_match) NextState = Report_Success;
end
Check_RetryCounter:
begin
if(RetryCounter_bigger) NextState = Report_Failure;
else if(RetryCounter_smaller) NextState = Construct_Message;
end
Report_Success:
begin
NextState = Wait_for_Transmit_Request;
end
Report_Failure:
begin
NextState = Wait_for_Transmit_Request;
end
endcase
// if (CurrentState==Reset_RetryCounter) RetryCounter=0;
//else if (CurrentState==Check_RetryCounter) RetryCounter = RetryCounter+1;
end
// Logica de salidas
assign TRANSMIT_BYTE_COUNT = CurrentState==0;
assign TRANSMIT_HEADER_LOW=0;
assign TRANSMIT_HEADER_HIGH=0;
assign TRANSMIT_DATA_OBJECTS=0;
assign Start_CRCReceiveTimer = CurrentState==Wait_for_PHY_response;
assign Stop_CRCReceiverTimer = CurrentState== Match_MessageID;
assign MessageIDCounter = CurrentState==Match_MessageID;
assign MessageID_mismatch = (CurrentState==Match_MessageID) && (TX_BUF_HEADER_BYTE_1 != RX_BUF_HEADER_BYTE_1);
assign SOP_mismatch = (CurrentState==Match_MessageID) && (TRANSMIT[2:0] != RX_BUF_FRAME_TYPE);
assign MessageID_SOP_match = !MessageID_mismatch && !SOP_mismatch;
assign RetryCounter_bigger = RetryCounter>=nRetryCounter && CurrentState==Check_RetryCounter;
assign RetryCounter_smaller = RetryCounter<nRetryCounter && CurrentState==Check_RetryCounter;
assign ALERT_TransmitSOP_MessageFailed= CurrentState==Report_Failure;
assign ALERT_TransmitSuccessful= CurrentState==Report_Success;
// Cambio de estado
always@(posedge CLK)
begin
if(RESET) CurrentState <= Wait_for_Transmit_Request;
else CurrentState <= NextState;
end
endmodule
|
module c7552 (
n94,
n18,
n172,
n61,
n188,
n133,
n53,
n178,
n55,
n213,
n63,
n239,
n220,
n65,
n231,
n208,
n113,
n162,
n184,
n74,
n1,
n3749,
n2230,
n160,
n80,
n4394,
n226,
n210,
n150,
n78,
n109,
n89,
n114,
n176,
n3711,
n180,
n2239,
n141,
n153,
n83,
n2224,
n3729,
n3723,
n124,
n2247,
n103,
n216,
n223,
n157,
n196,
n155,
n69,
n197,
n81,
n4420,
n32,
n202,
n4405,
n190,
n76,
n240,
n4526,
n57,
n9,
n111,
n1486,
n1492,
n151,
n12,
n2236,
n2211,
n205,
n191,
n29,
n234,
n206,
n97,
n177,
n147,
n232,
n47,
n50,
n4437,
n2208,
n159,
n73,
n173,
n62,
n4400,
n228,
n87,
n23,
n193,
n130,
n38,
n4410,
n127,
n2204,
n219,
n4432,
n179,
n227,
n118,
n1469,
n4528,
n238,
n161,
n201,
n88,
n54,
n237,
n169,
n2218,
n75,
n64,
n60,
n82,
n3743,
n1480,
n189,
n1197,
n171,
n134,
n221,
n230,
n175,
n212,
n4427,
n112,
n167,
n35,
n166,
n135,
n154,
n164,
n85,
n4415,
n222,
n1462,
n185,
n203,
n152,
n170,
n199,
n2256,
n181,
n187,
n214,
n3698,
n100,
n211,
n3737,
n1496,
n115,
n207,
n1459,
n217,
n168,
n26,
n195,
n209,
n163,
n198,
n2253,
n183,
n182,
n215,
n218,
n3701,
n86,
n59,
n5,
n4393,
n165,
n110,
n158,
n1455,
n121,
n84,
n58,
n15,
n144,
n79,
n41,
n3705,
n229,
n138,
n66,
n56,
n192,
n194,
n186,
n77,
n3717,
n106,
n235,
n204,
n70,
n224,
n233,
n156,
n174,
n225,
n44,
n236,
n200,
n408,
n399,
n278,
n2,
n370,
n350,
n319,
n522,
n307,
n368,
n556,
n406,
n471,
n436,
n540,
n412,
n304,
n292,
n532,
n528,
n480,
n422,
n404,
n432,
n444,
n333,
n488,
n391,
n276,
n558,
n486,
n258,
n560,
n362,
n281,
n546,
n330,
n448,
n289,
n341,
n324,
n554,
n526,
n264,
n496,
n442,
n410,
n524,
n416,
n538,
n3,
n552,
n469,
n382,
n492,
n414,
n246,
n286,
n295,
n394,
n536,
n249,
n327,
n365,
n453,
n313,
n279,
n379,
n548,
n298,
n356,
n373,
n252,
n446,
n321,
n438,
n284,
n530,
n450,
n550,
n359,
n336,
n534,
n301,
n344,
n397,
n338,
n418,
n490,
n542,
n440,
n388,
n484,
n270,
n385,
n482,
n478,
n347,
n544,
n316,
n310,
n402,
n494,
n419,
n273,
n353,
n376);
// Start PIs
input n94;
input n18;
input n172;
input n61;
input n188;
input n133;
input n53;
input n178;
input n55;
input n213;
input n63;
input n239;
input n220;
input n65;
input n231;
input n208;
input n113;
input n162;
input n184;
input n74;
input n1;
input n3749;
input n2230;
input n160;
input n80;
input n4394;
input n226;
input n210;
input n150;
input n78;
input n109;
input n89;
input n114;
input n176;
input n3711;
input n180;
input n2239;
input n141;
input n153;
input n83;
input n2224;
input n3729;
input n3723;
input n124;
input n2247;
input n103;
input n216;
input n223;
input n157;
input n196;
input n155;
input n69;
input n197;
input n81;
input n4420;
input n32;
input n202;
input n4405;
input n190;
input n76;
input n240;
input n4526;
input n57;
input n9;
input n111;
input n1486;
input n1492;
input n151;
input n12;
input n2236;
input n2211;
input n205;
input n191;
input n29;
input n234;
input n206;
input n97;
input n177;
input n147;
input n232;
input n47;
input n50;
input n4437;
input n2208;
input n159;
input n73;
input n173;
input n62;
input n4400;
input n228;
input n87;
input n23;
input n193;
input n130;
input n38;
input n4410;
input n127;
input n2204;
input n219;
input n4432;
input n179;
input n227;
input n118;
input n1469;
input n4528;
input n238;
input n161;
input n201;
input n88;
input n54;
input n237;
input n169;
input n2218;
input n75;
input n64;
input n60;
input n82;
input n3743;
input n1480;
input n189;
input n1197;
input n171;
input n134;
input n221;
input n230;
input n175;
input n212;
input n4427;
input n112;
input n167;
input n35;
input n166;
input n135;
input n154;
input n164;
input n85;
input n4415;
input n222;
input n1462;
input n185;
input n203;
input n152;
input n170;
input n199;
input n2256;
input n181;
input n187;
input n214;
input n3698;
input n100;
input n211;
input n3737;
input n1496;
input n115;
input n207;
input n1459;
input n217;
input n168;
input n26;
input n195;
input n209;
input n163;
input n198;
input n2253;
input n183;
input n182;
input n215;
input n218;
input n3701;
input n86;
input n59;
input n5;
input n4393;
input n165;
input n110;
input n158;
input n1455;
input n121;
input n84;
input n58;
input n15;
input n144;
input n79;
input n41;
input n3705;
input n229;
input n138;
input n66;
input n56;
input n192;
input n194;
input n186;
input n77;
input n3717;
input n106;
input n235;
input n204;
input n70;
input n224;
input n233;
input n156;
input n174;
input n225;
input n44;
input n236;
input n200;
// Start POs
output n408;
output n399;
output n278;
output n2;
output n370;
output n350;
output n319;
output n522;
output n307;
output n368;
output n556;
output n406;
output n471;
output n436;
output n540;
output n412;
output n304;
output n292;
output n532;
output n528;
output n480;
output n422;
output n404;
output n432;
output n444;
output n333;
output n488;
output n391;
output n276;
output n558;
output n486;
output n258;
output n560;
output n362;
output n281;
output n546;
output n330;
output n448;
output n289;
output n341;
output n324;
output n554;
output n526;
output n264;
output n496;
output n442;
output n410;
output n524;
output n416;
output n538;
output n3;
output n552;
output n469;
output n382;
output n492;
output n414;
output n246;
output n286;
output n295;
output n394;
output n536;
output n249;
output n327;
output n365;
output n453;
output n313;
output n279;
output n379;
output n548;
output n298;
output n356;
output n373;
output n252;
output n446;
output n321;
output n438;
output n284;
output n530;
output n450;
output n550;
output n359;
output n336;
output n534;
output n301;
output n344;
output n397;
output n338;
output n418;
output n490;
output n542;
output n440;
output n388;
output n484;
output n270;
output n385;
output n482;
output n478;
output n347;
output n544;
output n316;
output n310;
output n402;
output n494;
output n419;
output n273;
output n353;
output n376;
// Start wires
wire n408;
wire n319;
wire net_796;
wire net_416;
wire net_215;
wire net_933;
wire net_54;
wire net_526;
wire net_943;
wire n436;
wire net_834;
wire net_429;
wire net_694;
wire net_129;
wire net_648;
wire net_373;
wire net_98;
wire net_739;
wire net_980;
wire net_151;
wire net_356;
wire net_53;
wire net_452;
wire n63;
wire net_974;
wire net_545;
wire net_284;
wire net_560;
wire net_774;
wire net_923;
wire net_826;
wire net_439;
wire net_259;
wire net_548;
wire n333;
wire net_501;
wire n560;
wire n2230;
wire net_187;
wire net_111;
wire net_264;
wire net_225;
wire n150;
wire net_636;
wire n78;
wire net_263;
wire net_252;
wire net_124;
wire net_343;
wire net_160;
wire n141;
wire net_832;
wire net_322;
wire net_511;
wire n3723;
wire net_815;
wire net_901;
wire net_420;
wire net_665;
wire net_447;
wire net_871;
wire net_410;
wire net_508;
wire net_390;
wire n536;
wire net_35;
wire n365;
wire net_586;
wire n453;
wire n313;
wire net_703;
wire net_239;
wire net_193;
wire net_310;
wire n1486;
wire net_120;
wire net_292;
wire net_201;
wire net_109;
wire net_80;
wire n234;
wire n206;
wire net_96;
wire net_167;
wire net_651;
wire net_682;
wire net_989;
wire net_280;
wire net_744;
wire n159;
wire net_495;
wire net_34;
wire net_458;
wire net_108;
wire net_598;
wire net_685;
wire n478;
wire n87;
wire n130;
wire net_789;
wire n38;
wire net_971;
wire n4410;
wire n310;
wire net_593;
wire net_617;
wire net_672;
wire net_777;
wire net_1007;
wire net_554;
wire net_490;
wire net_742;
wire net_1014;
wire net_46;
wire n60;
wire net_584;
wire net_969;
wire n175;
wire net_632;
wire net_538;
wire net_165;
wire net_883;
wire net_843;
wire net_821;
wire net_464;
wire net_366;
wire net_13;
wire n448;
wire net_747;
wire net_446;
wire n554;
wire n1462;
wire n410;
wire n170;
wire n2256;
wire net_248;
wire net_384;
wire n3;
wire net_964;
wire n1496;
wire net_198;
wire n26;
wire n195;
wire net_209;
wire net_3;
wire n163;
wire net_634;
wire net_294;
wire net_802;
wire net_371;
wire n110;
wire n58;
wire n15;
wire net_1004;
wire net_848;
wire net_485;
wire net_997;
wire n194;
wire net_1031;
wire n336;
wire net_503;
wire net_256;
wire net_850;
wire n3717;
wire net_82;
wire net_64;
wire net_996;
wire net_726;
wire net_679;
wire net_1028;
wire net_308;
wire net_75;
wire n347;
wire net_959;
wire net_515;
wire net_600;
wire net_757;
wire net_701;
wire net_206;
wire net_125;
wire net_397;
wire net_808;
wire net_223;
wire net_1009;
wire net_715;
wire net_235;
wire net_890;
wire net_606;
wire net_623;
wire n188;
wire net_663;
wire net_320;
wire net_579;
wire net_250;
wire net_769;
wire n65;
wire net_312;
wire net_986;
wire net_130;
wire net_572;
wire n208;
wire n231;
wire net_286;
wire net_147;
wire net_787;
wire net_481;
wire net_369;
wire n486;
wire net_403;
wire net_32;
wire net_1025;
wire n80;
wire n330;
wire net_935;
wire net_282;
wire net_645;
wire net_426;
wire net_780;
wire net_841;
wire net_609;
wire net_541;
wire net_414;
wire n2224;
wire n83;
wire net_794;
wire n2247;
wire net_799;
wire net_528;
wire n197;
wire n69;
wire net_1012;
wire net_456;
wire net_155;
wire net_705;
wire net_335;
wire net_907;
wire net_506;
wire net_181;
wire n76;
wire net_349;
wire net_39;
wire net_1036;
wire net_245;
wire n446;
wire net_395;
wire net_331;
wire n530;
wire net_493;
wire n2236;
wire net_816;
wire net_386;
wire net_987;
wire net_641;
wire net_277;
wire n50;
wire n344;
wire net_919;
wire n418;
wire net_89;
wire n4437;
wire net_290;
wire net_680;
wire n23;
wire net_931;
wire net_338;
wire net_1039;
wire net_721;
wire net_243;
wire net_400;
wire n399;
wire n179;
wire net_759;
wire net_1018;
wire net_602;
wire net_175;
wire net_657;
wire n2218;
wire net_823;
wire net_106;
wire net_140;
wire net_740;
wire net_247;
wire n1480;
wire net_329;
wire net_279;
wire net_698;
wire net_897;
wire net_25;
wire net_70;
wire net_691;
wire n112;
wire net_194;
wire net_962;
wire net_730;
wire net_615;
wire net_478;
wire net_441;
wire net_596;
wire net_138;
wire net_749;
wire net_1019;
wire net_804;
wire net_333;
wire net_639;
wire net_728;
wire n289;
wire n324;
wire net_957;
wire net_1006;
wire net_719;
wire net_170;
wire net_531;
wire net_471;
wire net_565;
wire net_499;
wire net_77;
wire net_20;
wire n214;
wire n181;
wire net_878;
wire net_1033;
wire net_49;
wire net_518;
wire net_861;
wire net_15;
wire net_57;
wire net_71;
wire net_771;
wire net_929;
wire n3701;
wire net_1;
wire net_708;
wire n5;
wire net_696;
wire n165;
wire net_537;
wire net_180;
wire net_367;
wire net_169;
wire net_51;
wire net_171;
wire net_432;
wire net_513;
wire net_204;
wire net_232;
wire n338;
wire net_604;
wire net_163;
wire net_967;
wire n542;
wire net_67;
wire n224;
wire net_268;
wire n174;
wire net_459;
wire net_483;
wire net_48;
wire net_8;
wire net_737;
wire net_203;
wire net_505;
wire net_176;
wire net_296;
wire net_137;
wire net_992;
wire net_613;
wire net_237;
wire n172;
wire n94;
wire net_782;
wire n53;
wire net_614;
wire net_532;
wire net_93;
wire net_578;
wire n220;
wire net_786;
wire net_302;
wire net_889;
wire n184;
wire net_127;
wire net_984;
wire net_348;
wire net_753;
wire n1;
wire net_626;
wire net_101;
wire net_906;
wire net_388;
wire net_326;
wire net_707;
wire net_589;
wire net_100;
wire net_655;
wire n526;
wire net_686;
wire net_652;
wire net_536;
wire net_455;
wire net_221;
wire net_115;
wire net_689;
wire net_751;
wire net_393;
wire net_442;
wire net_830;
wire net_542;
wire n216;
wire n246;
wire net_575;
wire net_877;
wire net_595;
wire net_378;
wire n223;
wire net_408;
wire net_724;
wire net_1026;
wire net_423;
wire n190;
wire net_328;
wire net_157;
wire net_42;
wire n2211;
wire n191;
wire net_874;
wire net_66;
wire net_466;
wire net_868;
wire net_765;
wire n359;
wire net_675;
wire net_818;
wire net_938;
wire net_443;
wire net_922;
wire net_522;
wire net_270;
wire n385;
wire net_183;
wire net_668;
wire net_150;
wire net_304;
wire net_1011;
wire n278;
wire net_811;
wire net_352;
wire n1469;
wire n350;
wire net_800;
wire n238;
wire net_977;
wire net_644;
wire n307;
wire net_30;
wire net_643;
wire net_852;
wire net_436;
wire n540;
wire net_24;
wire net_622;
wire n304;
wire net_186;
wire net_812;
wire n1197;
wire n167;
wire net_792;
wire n432;
wire net_1000;
wire n488;
wire net_1035;
wire net_1016;
wire net_767;
wire n85;
wire net_825;
wire net_219;
wire net_18;
wire net_309;
wire net_659;
wire net_131;
wire net_196;
wire net_913;
wire net_29;
wire net_358;
wire n203;
wire net_837;
wire n152;
wire net_899;
wire net_1010;
wire net_516;
wire net_31;
wire net_927;
wire n115;
wire n3737;
wire net_956;
wire n1459;
wire net_713;
wire n2253;
wire net_693;
wire net_360;
wire net_213;
wire net_729;
wire n4393;
wire net_863;
wire net_260;
wire net_947;
wire net_438;
wire n321;
wire n284;
wire net_732;
wire net_580;
wire n450;
wire n229;
wire net_314;
wire net_904;
wire net_341;
wire net_952;
wire n397;
wire net_468;
wire net_58;
wire n484;
wire net_970;
wire net_798;
wire net_488;
wire n44;
wire net_73;
wire net_807;
wire net_86;
wire net_945;
wire net_179;
wire net_159;
wire net_61;
wire net_449;
wire net_383;
wire n133;
wire n471;
wire net_62;
wire n178;
wire net_6;
wire net_553;
wire net_534;
wire net_217;
wire n55;
wire net_733;
wire net_887;
wire net_903;
wire n213;
wire net_763;
wire net_427;
wire net_486;
wire net_135;
wire net_915;
wire net_473;
wire net_406;
wire n422;
wire net_633;
wire net_324;
wire net_113;
wire net_710;
wire net_497;
wire n546;
wire net_454;
wire net_462;
wire net_418;
wire net_40;
wire net_872;
wire n264;
wire net_709;
wire n109;
wire net_161;
wire n442;
wire n2239;
wire net_300;
wire n538;
wire net_748;
wire net_677;
wire net_95;
wire n103;
wire net_173;
wire net_78;
wire net_990;
wire net_950;
wire net_1003;
wire net_514;
wire net_376;
wire net_22;
wire net_354;
wire net_524;
wire net_646;
wire net_363;
wire net_445;
wire net_573;
wire n205;
wire net_776;
wire net_866;
wire net_44;
wire net_784;
wire net_520;
wire net_422;
wire n301;
wire net_1032;
wire net_561;
wire net_567;
wire n2208;
wire net_45;
wire net_381;
wire net_591;
wire net_746;
wire n62;
wire net_981;
wire n4400;
wire net_272;
wire n193;
wire net_178;
wire net_845;
wire n127;
wire net_1024;
wire n219;
wire n544;
wire net_762;
wire n227;
wire net_695;
wire net_839;
wire net_814;
wire n88;
wire net_556;
wire net_941;
wire n169;
wire net_893;
wire net_809;
wire net_629;
wire net_55;
wire net_559;
wire net_635;
wire net_255;
wire net_266;
wire net_1037;
wire net_345;
wire net_859;
wire net_620;
wire net_619;
wire net_350;
wire net_398;
wire net_306;
wire net_954;
wire n528;
wire n444;
wire net_500;
wire n276;
wire n154;
wire n164;
wire net_631;
wire net_11;
wire net_123;
wire net_994;
wire net_527;
wire net_362;
wire net_262;
wire net_318;
wire net_68;
wire n211;
wire n469;
wire net_976;
wire n394;
wire net_316;
wire net_865;
wire net_84;
wire net_670;
wire net_611;
wire net_231;
wire n379;
wire net_103;
wire net_226;
wire net_1021;
wire net_228;
wire n252;
wire net_926;
wire n41;
wire n3705;
wire net_966;
wire net_143;
wire n56;
wire net_190;
wire net_391;
wire net_1002;
wire net_533;
wire net_145;
wire net_911;
wire net_37;
wire n233;
wire n156;
wire net_582;
wire net_188;
wire net_755;
wire net_509;
wire n482;
wire net_661;
wire net_881;
wire net_211;
wire net_133;
wire net_568;
wire n2;
wire net_47;
wire net_1008;
wire n522;
wire n556;
wire n61;
wire net_557;
wire net_119;
wire net_210;
wire net_168;
wire net_916;
wire n532;
wire net_741;
wire net_477;
wire net_940;
wire n404;
wire net_385;
wire net_851;
wire net_269;
wire net_469;
wire n160;
wire net_847;
wire net_727;
wire net_90;
wire net_671;
wire net_283;
wire net_85;
wire net_778;
wire net_770;
wire n176;
wire net_404;
wire net_1005;
wire n180;
wire net_240;
wire n124;
wire net_4;
wire net_895;
wire net_295;
wire n196;
wire n81;
wire n32;
wire n4420;
wire net_307;
wire net_344;
wire net_16;
wire n279;
wire net_884;
wire net_712;
wire net_257;
wire n57;
wire net_233;
wire net_474;
wire net_472;
wire net_958;
wire net_65;
wire n550;
wire net_995;
wire net_896;
wire net_484;
wire net_136;
wire net_207;
wire net_944;
wire net_700;
wire net_961;
wire net_126;
wire n173;
wire n73;
wire net_278;
wire net_571;
wire net_63;
wire n494;
wire n4432;
wire net_274;
wire net_601;
wire n118;
wire net_321;
wire net_425;
wire n4528;
wire net_287;
wire net_189;
wire net_930;
wire net_833;
wire net_829;
wire net_720;
wire net_99;
wire n64;
wire net_480;
wire net_216;
wire net_934;
wire net_433;
wire net_836;
wire net_900;
wire net_717;
wire n4427;
wire net_544;
wire net_368;
wire n480;
wire net_224;
wire net_684;
wire net_52;
wire n166;
wire net_608;
wire n258;
wire net_370;
wire net_510;
wire net_413;
wire net_1020;
wire net_716;
wire net_114;
wire net_973;
wire net_1034;
wire net_860;
wire net_36;
wire net_870;
wire n207;
wire net_253;
wire net_637;
wire net_276;
wire net_311;
wire net_760;
wire net_494;
wire net_547;
wire net_873;
wire net_154;
wire net_666;
wire n86;
wire net_507;
wire net_616;
wire n158;
wire net_238;
wire net_817;
wire net_28;
wire net_529;
wire net_704;
wire n79;
wire net_587;
wire net_97;
wire n186;
wire net_192;
wire net_793;
wire net_649;
wire net_460;
wire n204;
wire n235;
wire net_650;
wire net_291;
wire net_457;
wire net_735;
wire net_772;
wire net_857;
wire net_867;
wire net_121;
wire net_200;
wire net_597;
wire net_743;
wire n200;
wire net_396;
wire n316;
wire net_195;
wire net_107;
wire net_166;
wire net_530;
wire n406;
wire net_849;
wire net_594;
wire net_603;
wire net_23;
wire net_271;
wire net_117;
wire net_74;
wire net_673;
wire net_401;
wire net_642;
wire net_205;
wire net_699;
wire net_242;
wire net_359;
wire net_440;
wire n162;
wire net_758;
wire net_26;
wire net_470;
wire net_920;
wire net_334;
wire net_430;
wire net_882;
wire net_718;
wire net_365;
wire net_820;
wire net_380;
wire n496;
wire net_141;
wire n3711;
wire net_467;
wire n524;
wire net_83;
wire net_879;
wire n416;
wire net_372;
wire net_437;
wire n295;
wire net_56;
wire n249;
wire net_566;
wire net_968;
wire n4405;
wire net_336;
wire net_803;
wire n240;
wire net_624;
wire net_555;
wire net_2;
wire net_9;
wire n111;
wire n438;
wire n151;
wire n12;
wire net_298;
wire net_790;
wire net_688;
wire net_697;
wire net_998;
wire net_475;
wire net_563;
wire net_605;
wire net_199;
wire net_502;
wire net_431;
wire net_835;
wire net_924;
wire net_898;
wire net_638;
wire net_909;
wire n370;
wire net_222;
wire net_932;
wire net_152;
wire net_313;
wire n368;
wire net_489;
wire net_714;
wire n237;
wire n75;
wire net_683;
wire net_258;
wire net_607;
wire net_148;
wire net_419;
wire net_251;
wire net_972;
wire net_244;
wire net_664;
wire net_936;
wire net_128;
wire net_585;
wire net_840;
wire net_819;
wire n362;
wire net_827;
wire net_549;
wire net_785;
wire net_374;
wire net_411;
wire net_854;
wire net_788;
wire net_214;
wire n187;
wire net_249;
wire n100;
wire n552;
wire n382;
wire net_979;
wire n168;
wire net_706;
wire n209;
wire net_156;
wire net_1013;
wire net_842;
wire net_810;
wire net_92;
wire net_112;
wire net_394;
wire n59;
wire net_139;
wire net_551;
wire n1455;
wire net_332;
wire net_409;
wire n84;
wire n138;
wire net_463;
wire net_492;
wire net_656;
wire net_88;
wire n77;
wire net_197;
wire net_766;
wire n106;
wire net_81;
wire n388;
wire n440;
wire net_402;
wire net_202;
wire n270;
wire n225;
wire net_110;
wire net_722;
wire net_379;
wire net_33;
wire net_988;
wire net_918;
wire net_949;
wire net_289;
wire net_450;
wire net_621;
wire net_435;
wire net_132;
wire n18;
wire net_105;
wire net_12;
wire net_978;
wire n239;
wire n113;
wire net_569;
wire net_768;
wire net_1017;
wire net_955;
wire n74;
wire net_327;
wire net_357;
wire n391;
wire net_960;
wire net_630;
wire net_999;
wire net_76;
wire net_1029;
wire net_908;
wire n4394;
wire net_353;
wire net_822;
wire net_801;
wire net_519;
wire net_412;
wire net_838;
wire n153;
wire n3729;
wire net_17;
wire net_319;
wire net_453;
wire n286;
wire net_581;
wire net_164;
wire n155;
wire net_731;
wire net_377;
wire net_87;
wire net_0;
wire net_288;
wire net_1038;
wire net_912;
wire n202;
wire net_658;
wire net_805;
wire net_734;
wire n4526;
wire net_540;
wire net_512;
wire net_779;
wire n1492;
wire net_662;
wire net_862;
wire net_951;
wire net_891;
wire net_50;
wire net_806;
wire n97;
wire net_234;
wire net_38;
wire n177;
wire n147;
wire net_342;
wire n47;
wire net_975;
wire net_612;
wire net_19;
wire n490;
wire net_738;
wire net_946;
wire net_892;
wire net_504;
wire net_855;
wire n228;
wire net_674;
wire net_618;
wire n2204;
wire net_303;
wire n273;
wire n161;
wire net_491;
wire net_965;
wire net_681;
wire net_948;
wire net_783;
wire net_392;
wire net_118;
wire n82;
wire n3743;
wire net_754;
wire n189;
wire net_421;
wire net_146;
wire n171;
wire net_921;
wire net_764;
wire net_550;
wire net_876;
wire net_122;
wire net_417;
wire n230;
wire net_7;
wire n35;
wire net_172;
wire n281;
wire net_428;
wire net_94;
wire net_246;
wire net_461;
wire net_640;
wire net_482;
wire n222;
wire net_991;
wire net_905;
wire net_775;
wire net_149;
wire net_142;
wire net_752;
wire n199;
wire net_387;
wire net_654;
wire net_858;
wire net_330;
wire net_888;
wire net_498;
wire net_535;
wire net_158;
wire n414;
wire net_676;
wire net_41;
wire n327;
wire n198;
wire net_577;
wire n183;
wire net_570;
wire n182;
wire n215;
wire net_444;
wire net_525;
wire net_1023;
wire net_844;
wire n548;
wire net_325;
wire net_797;
wire n356;
wire net_301;
wire n121;
wire net_299;
wire n144;
wire net_985;
wire n66;
wire net_182;
wire net_60;
wire net_521;
wire net_337;
wire net_590;
wire net_267;
wire net_273;
wire net_424;
wire net_576;
wire net_690;
wire net_465;
wire n236;
wire net_177;
wire net_523;
wire net_407;
wire net_476;
wire net_564;
wire n376;
wire net_382;
wire net_725;
wire net_583;
wire net_813;
wire net_953;
wire net_351;
wire net_1027;
wire net_894;
wire net_340;
wire net_265;
wire net_517;
wire net_434;
wire net_628;
wire net_791;
wire net_939;
wire net_824;
wire net_14;
wire net_220;
wire n558;
wire net_293;
wire n3749;
wire net_942;
wire n226;
wire n210;
wire n341;
wire net_69;
wire net_543;
wire n114;
wire n89;
wire net_925;
wire net_625;
wire net_339;
wire net_993;
wire n492;
wire net_361;
wire net_864;
wire net_27;
wire n157;
wire net_317;
wire net_856;
wire net_305;
wire net_880;
wire net_191;
wire net_261;
wire net_558;
wire net_660;
wire net_144;
wire net_102;
wire net_227;
wire net_59;
wire n9;
wire net_162;
wire n29;
wire net_1001;
wire net_781;
wire net_230;
wire net_910;
wire n232;
wire net_653;
wire n534;
wire net_134;
wire net_1022;
wire net_678;
wire net_546;
wire net_185;
wire net_702;
wire net_588;
wire net_928;
wire net_667;
wire net_853;
wire n402;
wire net_208;
wire net_236;
wire net_1015;
wire net_212;
wire net_315;
wire net_487;
wire net_552;
wire net_914;
wire net_415;
wire net_116;
wire n201;
wire n54;
wire net_347;
wire net_756;
wire net_91;
wire net_297;
wire net_346;
wire n412;
wire net_875;
wire net_104;
wire net_448;
wire n134;
wire net_72;
wire net_886;
wire n221;
wire n292;
wire net_229;
wire n212;
wire net_627;
wire net_917;
wire net_241;
wire net_687;
wire net_5;
wire net_405;
wire n135;
wire net_983;
wire net_355;
wire net_184;
wire net_711;
wire net_599;
wire net_610;
wire n4415;
wire net_723;
wire n185;
wire net_389;
wire net_831;
wire net_902;
wire net_451;
wire n3698;
wire net_323;
wire net_963;
wire net_846;
wire net_750;
wire net_736;
wire net_275;
wire net_399;
wire net_539;
wire n217;
wire net_692;
wire net_153;
wire net_218;
wire net_174;
wire n218;
wire net_375;
wire net_562;
wire n298;
wire net_364;
wire net_43;
wire n373;
wire net_10;
wire net_592;
wire net_21;
wire net_79;
wire net_647;
wire net_885;
wire net_1030;
wire n192;
wire net_773;
wire net_285;
wire net_281;
wire net_828;
wire net_869;
wire net_669;
wire net_937;
wire net_254;
wire n70;
wire net_761;
wire net_496;
wire net_479;
wire net_574;
wire net_795;
wire net_982;
wire n419;
wire net_745;
wire n353;
// Start cells
NAND2_X1 inst_696 ( .ZN(net_190), .A2(net_146), .A1(net_39) );
NOR2_X1 inst_481 ( .ZN(net_875), .A1(net_768), .A2(net_711) );
XNOR2_X1 inst_228 ( .ZN(net_844), .B(net_842), .A(net_781) );
XNOR2_X1 inst_125 ( .ZN(net_603), .A(net_333), .B(n2211) );
NOR2_X1 inst_486 ( .A2(net_856), .ZN(net_789), .A1(net_602) );
INV_X1 inst_1025 ( .ZN(net_491), .A(net_490) );
NAND2_X1 inst_707 ( .ZN(net_280), .A2(net_154), .A1(net_56) );
NAND2_X1 inst_779 ( .ZN(net_559), .A1(net_533), .A2(net_491) );
NOR2_X1 inst_395 ( .A1(net_164), .ZN(net_158), .A2(net_91) );
NAND2_X1 inst_841 ( .ZN(net_971), .A2(net_936), .A1(net_879) );
XNOR2_X1 inst_244 ( .ZN(net_943), .B(net_854), .A(net_514) );
NOR2_X1 inst_452 ( .A2(net_999), .ZN(net_502), .A1(net_501) );
NAND2_X1 inst_689 ( .ZN(net_265), .A2(net_131), .A1(net_77) );
NOR2_X1 inst_430 ( .ZN(net_433), .A2(net_179), .A1(n4427) );
XNOR2_X1 inst_214 ( .ZN(net_781), .B(net_733), .A(net_732) );
NAND4_X1 inst_548 ( .A4(net_741), .A1(net_706), .A2(net_705), .A3(net_704), .ZN(n412) );
NOR2_X1 inst_515 ( .ZN(net_1011), .A2(net_1007), .A1(net_729) );
NAND2_X1 inst_772 ( .ZN(net_544), .A2(net_422), .A1(net_386) );
NAND2_X1 inst_728 ( .ZN(net_167), .A2(net_132), .A1(net_33) );
INV_X1 inst_944 ( .ZN(net_15), .A(n3705) );
NAND2_X1 inst_642 ( .ZN(net_74), .A2(n238), .A1(n18) );
NOR2_X1 inst_459 ( .ZN(net_805), .A1(net_531), .A2(net_399) );
INV_X1 inst_1018 ( .ZN(net_720), .A(net_432) );
NOR2_X1 inst_445 ( .A2(net_1012), .ZN(net_615), .A1(net_498) );
NAND2_X1 inst_850 ( .ZN(net_988), .A2(net_970), .A1(net_776) );
NAND2_X1 inst_709 ( .ZN(net_157), .A1(net_156), .A2(net_93) );
XNOR2_X1 inst_93 ( .A(net_266), .ZN(net_227), .B(net_114) );
NAND2_X1 inst_700 ( .ZN(net_271), .A2(net_140), .A1(net_48) );
INV_X2 inst_920 ( .A(net_373), .ZN(net_164) );
NAND2_X1 inst_606 ( .ZN(net_39), .A2(n198), .A1(n18) );
NOR2_X1 inst_367 ( .A1(net_191), .ZN(net_91), .A2(n170) );
INV_X1 inst_957 ( .ZN(net_26), .A(n82) );
INV_X1 inst_979 ( .A(net_331), .ZN(net_236) );
NAND2_X1 inst_853 ( .ZN(net_1003), .A2(net_985), .A1(net_766) );
INV_X1 inst_1008 ( .ZN(net_1025), .A(net_623) );
XNOR2_X1 inst_139 ( .ZN(net_422), .A(net_290), .B(n4437) );
NAND2_X1 inst_657 ( .A2(net_191), .ZN(net_145), .A1(n94) );
NAND3_X1 inst_559 ( .ZN(net_477), .A3(net_476), .A1(net_305), .A2(net_304) );
NAND3_X1 inst_584 ( .ZN(net_750), .A1(net_658), .A3(net_657), .A2(net_484) );
NAND4_X1 inst_521 ( .ZN(n404), .A4(n240), .A3(n228), .A2(n184), .A1(n150) );
NOR2_X1 inst_470 ( .A2(net_808), .ZN(net_708), .A1(net_677) );
NAND4_X1 inst_535 ( .A1(net_722), .ZN(net_674), .A3(net_592), .A4(net_591), .A2(net_389) );
NOR2_X1 inst_450 ( .A2(net_956), .A1(net_728), .ZN(net_496) );
NAND2_X1 inst_745 ( .ZN(net_506), .A2(net_352), .A1(net_108) );
NAND4_X1 inst_520 ( .ZN(n410), .A4(n199), .A3(n188), .A2(n172), .A1(n162) );
XNOR2_X1 inst_237 ( .ZN(net_874), .A(net_827), .B(net_774) );
XNOR2_X1 inst_148 ( .ZN(net_597), .A(net_406), .B(net_309) );
NAND4_X1 inst_554 ( .A3(net_986), .A4(net_935), .A1(net_891), .A2(net_836), .ZN(n270) );
XNOR2_X1 inst_191 ( .ZN(net_707), .B(net_636), .A(net_508) );
CLKBUF_X1 inst_1063 ( .Z(n530), .A(n4420) );
NAND2_X1 inst_813 ( .ZN(net_754), .A2(net_753), .A1(n4526) );
XOR2_X1 inst_51 ( .Z(net_344), .A(net_343), .B(net_342) );
OR2_X4 inst_315 ( .ZN(net_677), .A1(net_536), .A2(net_231) );
XOR2_X1 inst_80 ( .Z(net_780), .A(net_779), .B(net_778) );
NAND2_X1 inst_836 ( .ZN(net_962), .A1(net_907), .A2(net_899) );
CLKBUF_X1 inst_1066 ( .Z(n524), .A(n4437) );
INV_X1 inst_974 ( .A(net_333), .ZN(net_240) );
XNOR2_X1 inst_216 ( .ZN(net_788), .A(net_715), .B(net_241) );
CLKBUF_X1 inst_1059 ( .Z(n538), .A(n4400) );
XNOR2_X1 inst_241 ( .ZN(net_930), .A(net_884), .B(net_844) );
CLKBUF_X1 inst_1075 ( .Z(n482), .A(n2253) );
MUX2_X2 inst_862 ( .Z(net_214), .S(net_191), .A(net_8), .B(n62) );
AND2_X4 inst_1116 ( .ZN(net_561), .A1(net_480), .A2(net_467) );
XNOR2_X1 inst_151 ( .ZN(net_445), .A(net_330), .B(net_294) );
XOR2_X1 inst_64 ( .Z(net_377), .A(net_376), .B(net_375) );
INV_X1 inst_1001 ( .ZN(net_1016), .A(net_442) );
NAND2_X1 inst_743 ( .A2(net_293), .ZN(net_201), .A1(net_115) );
NOR2_X1 inst_415 ( .ZN(net_245), .A2(net_172), .A1(n4415) );
NAND2_X1 inst_828 ( .ZN(net_871), .A1(net_867), .A2(net_850) );
AND3_X4 inst_1104 ( .A3(net_608), .ZN(net_602), .A1(net_601), .A2(net_592) );
MUX2_X2 inst_892 ( .S(net_987), .Z(net_830), .A(net_829), .B(net_828) );
XNOR2_X1 inst_223 ( .ZN(net_837), .A(net_788), .B(net_661) );
AND2_X4 inst_1132 ( .ZN(net_550), .A2(net_549), .A1(net_432) );
NOR2_X1 inst_402 ( .ZN(net_351), .A1(net_164), .A2(net_104) );
INV_X1 inst_968 ( .A(net_262), .ZN(net_172) );
NAND2_X1 inst_819 ( .A2(net_987), .ZN(net_809), .A1(net_808) );
OR2_X2 inst_340 ( .A1(net_570), .ZN(net_541), .A2(net_540) );
NOR2_X1 inst_494 ( .A1(net_1020), .ZN(net_986), .A2(net_807) );
OR2_X4 inst_329 ( .ZN(net_685), .A1(net_628), .A2(net_538) );
INV_X1 inst_938 ( .ZN(net_115), .A(n3749) );
NAND3_X1 inst_574 ( .ZN(net_612), .A1(net_611), .A3(net_598), .A2(net_487) );
NOR2_X1 inst_386 ( .A2(net_162), .ZN(net_129), .A1(net_128) );
XNOR2_X1 inst_158 ( .A(net_485), .ZN(net_453), .B(net_452) );
XNOR2_X1 inst_141 ( .ZN(net_535), .B(net_392), .A(net_232) );
INV_X1 inst_936 ( .ZN(net_12), .A(n1496) );
NOR2_X1 inst_507 ( .ZN(net_917), .A2(net_916), .A1(net_747) );
NAND3_X1 inst_571 ( .ZN(net_649), .A3(net_578), .A1(net_519), .A2(net_467) );
MUX2_X2 inst_884 ( .S(net_191), .Z(net_119), .B(net_10), .A(n1459) );
NAND2_X1 inst_711 ( .ZN(net_328), .A2(net_126), .A1(net_54) );
NAND2_X1 inst_827 ( .ZN(net_890), .A1(net_867), .A2(net_834) );
NAND4_X1 inst_552 ( .ZN(net_921), .A1(net_920), .A2(net_895), .A4(net_813), .A3(net_767) );
NAND2_X1 inst_599 ( .ZN(net_373), .A2(n9), .A1(n12) );
INV_X1 inst_1033 ( .A(net_893), .ZN(net_675) );
NOR2_X1 inst_469 ( .ZN(net_692), .A1(net_590), .A2(net_516) );
XOR2_X1 inst_18 ( .Z(net_564), .A(net_259), .B(net_258) );
MUX2_X2 inst_915 ( .Z(net_1036), .B(net_1032), .A(net_1026), .S(n4526) );
NAND2_X1 inst_811 ( .A1(net_762), .ZN(net_755), .A2(net_735) );
NAND4_X1 inst_541 ( .ZN(net_699), .A1(net_579), .A2(net_562), .A4(net_481), .A3(net_194) );
XNOR2_X1 inst_208 ( .ZN(net_770), .B(net_680), .A(net_405) );
XOR2_X1 inst_9 ( .A(net_314), .Z(net_217), .B(net_216) );
XNOR2_X1 inst_113 ( .ZN(net_371), .A(net_157), .B(net_110) );
NOR2_X1 inst_505 ( .ZN(net_936), .A1(net_913), .A2(net_886) );
NOR3_X1 inst_356 ( .ZN(net_977), .A1(net_934), .A3(net_900), .A2(net_825) );
CLKBUF_X1 inst_1058 ( .Z(n540), .A(n4393) );
XNOR2_X1 inst_198 ( .ZN(net_738), .B(net_637), .A(net_509) );
INV_X1 inst_952 ( .ZN(net_22), .A(n1492) );
MUX2_X2 inst_897 ( .Z(net_866), .A(net_865), .B(net_864), .S(net_785) );
NAND2_X1 inst_784 ( .ZN(net_633), .A2(net_526), .A1(net_429) );
NAND2_X1 inst_721 ( .A1(net_191), .ZN(net_168), .A2(net_156) );
MUX2_X2 inst_902 ( .Z(net_949), .B(net_947), .A(net_946), .S(net_907) );
XNOR2_X1 inst_293 ( .B(net_1014), .A(net_1001), .ZN(n310) );
NAND2_X1 inst_778 ( .A1(net_751), .ZN(net_658), .A2(net_551) );
NAND2_X1 inst_636 ( .ZN(net_68), .A2(n206), .A1(n18) );
NAND2_X1 inst_632 ( .ZN(net_64), .A2(n189), .A1(n18) );
XOR2_X1 inst_0 ( .Z(net_381), .B(net_182), .A(n38) );
XNOR2_X1 inst_184 ( .ZN(net_795), .A(net_673), .B(net_659) );
NAND2_X1 inst_690 ( .ZN(net_320), .A2(net_139), .A1(net_60) );
NOR2_X1 inst_433 ( .ZN(net_569), .A2(net_418), .A1(net_366) );
NAND2_X1 inst_781 ( .ZN(net_731), .A2(net_627), .A1(net_524) );
NAND2_X1 inst_732 ( .A1(net_264), .A2(net_211), .ZN(net_192) );
XNOR2_X1 inst_98 ( .A(net_283), .B(net_280), .ZN(net_255) );
XNOR2_X1 inst_263 ( .B(net_962), .A(net_596), .ZN(n356) );
XNOR2_X1 inst_185 ( .ZN(net_701), .B(net_586), .A(net_395) );
INV_X1 inst_959 ( .ZN(net_80), .A(n5) );
XOR2_X1 inst_75 ( .Z(net_803), .A(net_720), .B(net_662) );
OR2_X4 inst_332 ( .ZN(net_824), .A1(net_756), .A2(net_755) );
XNOR2_X1 inst_166 ( .ZN(net_510), .B(net_370), .A(net_357) );
MUX2_X2 inst_868 ( .Z(net_285), .S(net_191), .A(net_112), .B(n75) );
XNOR2_X1 inst_163 ( .ZN(net_507), .B(net_324), .A(net_252) );
NOR2_X1 inst_394 ( .ZN(net_362), .A1(net_164), .A2(net_102) );
XOR2_X1 inst_79 ( .B(net_1025), .A(net_686), .Z(n391) );
XNOR2_X1 inst_106 ( .ZN(net_334), .A(net_333), .B(net_141) );
NOR2_X1 inst_422 ( .ZN(net_248), .A2(net_180), .A1(n2256) );
XNOR2_X1 inst_201 ( .ZN(net_741), .B(net_640), .A(net_445) );
INV_X1 inst_927 ( .ZN(net_4), .A(n3737) );
NAND2_X1 inst_605 ( .ZN(net_38), .A2(n226), .A1(n18) );
CLKBUF_X1 inst_1084 ( .Z(n440), .A(n1492) );
OR4_X1 inst_304 ( .ZN(net_851), .A2(n416), .A4(n414), .A3(n412), .A1(n404) );
NAND2_X1 inst_752 ( .ZN(net_244), .A2(net_240), .A1(n2211) );
INV_X1 inst_1027 ( .A(net_591), .ZN(net_537) );
XOR2_X1 inst_73 ( .Z(net_829), .A(net_536), .B(net_534) );
AND2_X4 inst_1143 ( .ZN(net_991), .A2(net_974), .A1(net_551) );
NOR2_X1 inst_378 ( .A1(net_191), .ZN(net_103), .A2(n167) );
MUX2_X2 inst_890 ( .Z(net_341), .S(net_191), .A(net_122), .B(n112) );
NOR2_X1 inst_361 ( .A1(net_191), .ZN(net_85), .A2(n169) );
INV_X1 inst_1024 ( .ZN(net_594), .A(net_522) );
INV_X1 inst_1016 ( .ZN(net_1004), .A(net_414) );
NAND2_X1 inst_659 ( .A2(net_191), .ZN(net_154), .A1(n29) );
XNOR2_X1 inst_250 ( .B(net_905), .A(net_898), .ZN(n344) );
NAND2_X1 inst_848 ( .ZN(net_985), .A2(net_958), .A1(net_743) );
NAND2_X1 inst_786 ( .ZN(net_660), .A2(net_659), .A1(net_540) );
NOR2_X1 inst_397 ( .ZN(net_358), .A1(net_164), .A2(net_100) );
NOR2_X1 inst_504 ( .ZN(net_906), .A2(net_896), .A1(net_764) );
CLKBUF_X1 inst_1048 ( .Z(n560), .A(n3698) );
NOR2_X1 inst_440 ( .A1(net_1027), .A2(net_963), .ZN(net_608) );
XOR2_X1 inst_2 ( .A(net_341), .Z(net_205), .B(net_204) );
NAND2_X1 inst_644 ( .ZN(net_76), .A2(n220), .A1(n18) );
MUX2_X2 inst_918 ( .Z(net_1039), .B(net_1034), .A(net_1030), .S(net_931) );
CLKBUF_X1 inst_1091 ( .A(n341), .Z(n286) );
NAND3_X1 inst_578 ( .ZN(net_729), .A1(net_620), .A3(net_619), .A2(net_506) );
MUX2_X2 inst_888 ( .Z(net_220), .S(net_191), .A(net_14), .B(n64) );
XOR2_X1 inst_52 ( .Z(net_347), .A(net_346), .B(net_345) );
NAND2_X1 inst_668 ( .A2(net_191), .ZN(net_147), .A1(n32) );
XNOR2_X1 inst_221 ( .ZN(net_826), .A(net_770), .B(net_672) );
NAND3_X1 inst_556 ( .A1(net_80), .ZN(n292), .A3(n134), .A2(n133) );
NAND2_X1 inst_650 ( .A2(net_191), .ZN(net_149), .A1(n103) );
XNOR2_X1 inst_289 ( .ZN(net_1024), .A(net_1012), .B(net_1002) );
INV_X1 inst_987 ( .A(net_277), .ZN(net_186) );
NOR2_X1 inst_432 ( .A1(net_406), .ZN(net_405), .A2(net_404) );
NAND2_X1 inst_679 ( .ZN(net_325), .A2(net_125), .A1(net_57) );
NOR2_X1 inst_420 ( .ZN(net_533), .A2(net_183), .A1(n2247) );
XNOR2_X1 inst_282 ( .ZN(net_1015), .A(net_1004), .B(net_998) );
NOR2_X1 inst_513 ( .ZN(net_994), .A2(net_991), .A1(net_750) );
NAND2_X1 inst_754 ( .ZN(net_460), .A2(net_242), .A1(n2239) );
XOR2_X1 inst_44 ( .Z(net_478), .B(net_320), .A(net_314) );
NOR2_X1 inst_371 ( .ZN(net_182), .A1(net_96), .A2(n2204) );
OR2_X4 inst_314 ( .A1(net_321), .A2(net_216), .ZN(net_196) );
NOR2_X1 inst_435 ( .A2(net_967), .ZN(net_427), .A1(net_426) );
NAND2_X1 inst_597 ( .ZN(net_31), .A2(n18), .A1(n160) );
NAND2_X1 inst_687 ( .ZN(net_323), .A2(net_140), .A1(net_62) );
NAND2_X1 inst_774 ( .ZN(net_668), .A2(net_597), .A1(net_415) );
NAND2_X1 inst_621 ( .ZN(net_124), .A1(n4528), .A2(n1492) );
NAND2_X1 inst_838 ( .A2(net_923), .ZN(net_922), .A1(net_678) );
INV_X1 inst_985 ( .ZN(net_392), .A(net_231) );
NAND2_X1 inst_628 ( .ZN(net_60), .A2(n18), .A1(n179) );
NAND2_X1 inst_815 ( .ZN(net_785), .A2(net_784), .A1(net_736) );
NOR2_X1 inst_472 ( .ZN(net_710), .A1(net_676), .A2(net_653) );
NOR2_X1 inst_447 ( .A1(net_1016), .ZN(net_617), .A2(net_503) );
NOR2_X1 inst_457 ( .ZN(net_709), .A1(net_524), .A2(net_490) );
MUX2_X2 inst_875 ( .Z(net_259), .S(net_191), .A(net_4), .B(n54) );
NAND2_X1 inst_665 ( .ZN(net_406), .A2(net_191), .A1(n3701) );
CLKBUF_X1 inst_1073 ( .Z(n486), .A(n2239) );
AND2_X4 inst_1117 ( .ZN(net_576), .A2(net_412), .A1(net_303) );
AND2_X4 inst_1130 ( .A1(net_603), .A2(net_551), .ZN(net_543) );
XNOR2_X1 inst_127 ( .ZN(net_462), .A(net_367), .B(n2247) );
MUX2_X2 inst_855 ( .S(net_191), .Z(net_107), .A(net_22), .B(n1455) );
NOR2_X1 inst_413 ( .ZN(net_751), .A2(net_240), .A1(n2211) );
XNOR2_X1 inst_146 ( .ZN(net_397), .B(net_229), .A(net_205) );
OR2_X4 inst_334 ( .ZN(net_894), .A2(net_833), .A1(net_757) );
MUX2_X2 inst_859 ( .Z(net_284), .S(net_191), .A(net_109), .B(n76) );
XNOR2_X1 inst_187 ( .ZN(net_703), .B(net_588), .A(net_230) );
XNOR2_X1 inst_206 ( .ZN(net_769), .A(net_683), .B(net_243) );
NAND2_X1 inst_805 ( .ZN(net_889), .A1(net_709), .A2(net_648) );
XNOR2_X1 inst_122 ( .ZN(net_463), .A(net_346), .B(n2253) );
XOR2_X1 inst_25 ( .Z(net_276), .A(net_275), .B(net_274) );
NOR3_X1 inst_354 ( .ZN(net_716), .A1(net_550), .A3(net_434), .A2(net_401) );
NOR2_X1 inst_405 ( .ZN(net_200), .A1(net_164), .A2(net_106) );
AND2_X4 inst_1145 ( .ZN(net_1008), .A2(net_1007), .A1(net_696) );
NOR2_X1 inst_492 ( .ZN(net_825), .A1(net_824), .A2(net_823) );
INV_X1 inst_1042 ( .ZN(net_822), .A(net_821) );
NAND2_X1 inst_817 ( .ZN(net_786), .A2(net_782), .A1(net_719) );
OR2_X4 inst_326 ( .ZN(net_526), .A2(net_525), .A1(net_483) );
NAND4_X1 inst_518 ( .ZN(n408), .A4(n186), .A3(n185), .A1(n183), .A2(n182) );
XOR2_X1 inst_69 ( .Z(net_799), .B(net_596), .A(net_485) );
NOR2_X1 inst_373 ( .A1(net_191), .ZN(net_98), .A2(n212) );
XOR2_X1 inst_82 ( .Z(net_804), .A(net_803), .B(net_802) );
XNOR2_X1 inst_108 ( .ZN(net_418), .A(net_358), .B(net_354) );
NAND2_X1 inst_844 ( .ZN(net_997), .A1(net_950), .A2(net_922) );
NAND3_X1 inst_595 ( .ZN(net_953), .A1(net_951), .A3(net_930), .A2(net_819) );
XOR2_X1 inst_22 ( .Z(net_268), .A(net_267), .B(net_266) );
AND2_X4 inst_1121 ( .A2(net_469), .ZN(net_421), .A1(net_295) );
AND3_X4 inst_1102 ( .ZN(net_679), .A3(net_611), .A2(net_598), .A1(net_597) );
NOR2_X1 inst_460 ( .ZN(net_532), .A2(net_441), .A1(net_248) );
INV_X1 inst_970 ( .A(net_318), .ZN(net_174) );
OR3_X4 inst_307 ( .A2(net_720), .A3(net_596), .ZN(net_520), .A1(net_485) );
NAND2_X1 inst_767 ( .ZN(net_655), .A2(net_592), .A1(net_556) );
NAND2_X1 inst_638 ( .ZN(net_70), .A2(n194), .A1(n18) );
XNOR2_X1 inst_161 ( .ZN(net_457), .A(net_337), .B(net_260) );
NAND3_X1 inst_560 ( .ZN(net_479), .A3(net_471), .A1(net_363), .A2(net_362) );
NAND2_X1 inst_749 ( .ZN(net_241), .A2(net_236), .A1(n4394) );
NAND3_X1 inst_586 ( .ZN(net_840), .A1(net_697), .A3(net_557), .A2(net_504) );
NAND2_X1 inst_702 ( .ZN(net_267), .A2(net_150), .A1(net_53) );
XOR2_X1 inst_16 ( .Z(net_252), .A(net_190), .B(net_167) );
NAND2_X1 inst_717 ( .ZN(net_264), .A2(net_143), .A1(net_58) );
XNOR2_X1 inst_276 ( .ZN(net_1002), .A(net_1001), .B(net_966) );
INV_X1 inst_1030 ( .ZN(net_650), .A(net_649) );
NAND2_X1 inst_718 ( .ZN(net_283), .A2(net_155), .A1(net_68) );
INV_X1 inst_1029 ( .ZN(net_648), .A(net_647) );
XNOR2_X1 inst_156 ( .ZN(net_450), .B(net_374), .A(net_350) );
INV_X1 inst_950 ( .ZN(net_20), .A(n69) );
CLKBUF_X1 inst_1068 ( .Z(n496), .A(n2208) );
MUX2_X2 inst_886 ( .Z(net_378), .S(net_191), .A(net_23), .B(n79) );
NAND2_X1 inst_802 ( .ZN(net_694), .A1(net_625), .A2(net_618) );
XNOR2_X1 inst_296 ( .ZN(net_1034), .B(net_1029), .A(net_1024) );
XNOR2_X1 inst_91 ( .A(net_315), .ZN(net_221), .B(net_220) );
MUX2_X2 inst_905 ( .S(net_962), .B(net_858), .A(net_802), .Z(n347) );
XNOR2_X1 inst_132 ( .ZN(net_673), .A(net_292), .B(n3743) );
OR2_X2 inst_342 ( .A2(net_921), .A1(net_915), .ZN(n264) );
NAND4_X1 inst_526 ( .A2(net_578), .ZN(net_562), .A4(net_561), .A1(net_518), .A3(net_391) );
INV_X1 inst_1006 ( .A(net_911), .ZN(net_882) );
NOR2_X1 inst_463 ( .ZN(net_555), .A2(net_554), .A1(net_498) );
XNOR2_X1 inst_96 ( .ZN(net_253), .A(net_159), .B(net_134) );
XNOR2_X1 inst_101 ( .ZN(net_311), .A(net_310), .B(net_264) );
OR2_X4 inst_319 ( .A2(net_1029), .ZN(net_554), .A1(net_484) );
NOR2_X1 inst_400 ( .ZN(net_360), .A1(net_164), .A2(net_95) );
NAND2_X1 inst_614 ( .ZN(net_47), .A2(n187), .A1(n18) );
NAND2_X1 inst_649 ( .A2(net_191), .ZN(net_148), .A1(n66) );
NAND2_X1 inst_821 ( .A2(net_950), .ZN(net_821), .A1(net_647) );
XNOR2_X1 inst_261 ( .ZN(net_957), .A(net_956), .B(net_912) );
INV_X1 inst_1031 ( .ZN(net_652), .A(net_651) );
INV_X1 inst_980 ( .A(net_345), .ZN(net_180) );
NOR2_X1 inst_500 ( .A2(net_904), .ZN(net_886), .A1(net_768) );
INV_X1 inst_945 ( .ZN(net_16), .A(n1486) );
NOR2_X1 inst_510 ( .ZN(net_961), .A2(net_959), .A1(net_746) );
XNOR2_X1 inst_268 ( .A(net_999), .ZN(net_979), .B(net_940) );
NOR2_X1 inst_369 ( .A1(net_191), .ZN(net_94), .A2(n214) );
INV_X1 inst_995 ( .ZN(net_925), .A(net_415) );
NAND4_X1 inst_550 ( .ZN(net_869), .A4(net_817), .A1(net_584), .A3(net_479), .A2(net_473) );
NAND2_X1 inst_830 ( .ZN(net_878), .A2(net_877), .A1(net_710) );
NAND2_X1 inst_603 ( .ZN(net_36), .A2(n196), .A1(n18) );
OR2_X4 inst_327 ( .A1(net_728), .ZN(net_620), .A2(net_529) );
XOR2_X1 inst_85 ( .B(net_1027), .A(net_961), .Z(n362) );
XNOR2_X1 inst_291 ( .ZN(net_1028), .B(net_1027), .A(net_1010) );
CLKBUF_X1 inst_1060 ( .Z(n536), .A(n4405) );
XNOR2_X1 inst_266 ( .ZN(net_968), .A(net_967), .B(net_926) );
NAND2_X1 inst_776 ( .ZN(net_920), .A2(net_420), .A1(n38) );
MUX2_X2 inst_900 ( .Z(net_945), .B(net_943), .A(net_942), .S(net_761) );
MUX2_X2 inst_866 ( .Z(net_308), .S(net_191), .A(net_111), .B(n59) );
XOR2_X1 inst_77 ( .Z(net_794), .A(net_745), .B(net_713) );
XNOR2_X1 inst_171 ( .ZN(net_586), .B(net_394), .A(net_222) );
NAND3_X1 inst_558 ( .A3(net_567), .ZN(net_475), .A2(net_355), .A1(net_341) );
NAND3_X1 inst_594 ( .ZN(net_952), .A1(net_951), .A2(net_950), .A3(net_928) );
XNOR2_X1 inst_145 ( .ZN(net_396), .B(net_227), .A(net_221) );
XNOR2_X1 inst_290 ( .ZN(net_1026), .B(net_1025), .A(net_1005) );
NOR2_X1 inst_374 ( .A1(net_191), .ZN(net_99), .A2(n173) );
XNOR2_X1 inst_272 ( .B(net_1012), .A(net_954), .ZN(n316) );
NOR2_X1 inst_502 ( .ZN(net_900), .A2(net_890), .A1(net_889) );
XNOR2_X1 inst_103 ( .ZN(net_319), .A(net_318), .B(net_317) );
NAND2_X1 inst_814 ( .ZN(net_767), .A1(net_766), .A2(net_742) );
XNOR2_X1 inst_248 ( .ZN(net_947), .B(net_860), .A(net_452) );
NOR2_X1 inst_389 ( .ZN(net_365), .A1(net_164), .A2(net_85) );
INV_X1 inst_925 ( .ZN(net_112), .A(n3717) );
NAND2_X1 inst_789 ( .A2(net_776), .ZN(net_664), .A1(net_522) );
NOR2_X1 inst_357 ( .A1(net_191), .ZN(net_81), .A2(n177) );
AND2_X4 inst_1120 ( .ZN(net_566), .A2(net_476), .A1(net_417) );
AND2_X4 inst_1141 ( .ZN(net_959), .A2(net_916), .A1(net_548) );
NAND2_X1 inst_809 ( .ZN(net_723), .A1(net_722), .A2(net_666) );
MUX2_X2 inst_881 ( .Z(net_314), .S(net_191), .A(net_117), .B(n84) );
INV_X1 inst_932 ( .ZN(net_8), .A(n4437) );
NAND2_X1 inst_822 ( .ZN(net_816), .A2(net_812), .A1(n89) );
MUX2_X2 inst_913 ( .A(net_1020), .B(net_1019), .S(net_993), .Z(n276) );
XNOR2_X1 inst_180 ( .ZN(net_640), .B(net_444), .A(net_276) );
AND2_X4 inst_1125 ( .A2(net_673), .ZN(net_436), .A1(net_435) );
INV_X1 inst_947 ( .ZN(net_18), .A(n2256) );
MUX2_X2 inst_912 ( .S(net_1018), .A(net_535), .B(net_534), .Z(n469) );
NAND2_X1 inst_731 ( .ZN(net_390), .A1(net_191), .A2(net_190) );
NAND2_X1 inst_609 ( .ZN(net_42), .A2(n217), .A1(n18) );
INV_X1 inst_1022 ( .A(net_630), .ZN(net_487) );
NAND2_X1 inst_795 ( .A2(net_684), .ZN(net_680), .A1(net_539) );
XNOR2_X1 inst_301 ( .B(net_1038), .A(net_984), .ZN(n370) );
NOR2_X1 inst_363 ( .A1(net_191), .ZN(net_87), .A2(n153) );
XOR2_X1 inst_27 ( .Z(net_518), .A(net_281), .B(net_280) );
XNOR2_X1 inst_247 ( .ZN(net_946), .B(net_859), .A(net_454) );
NOR2_X1 inst_403 ( .ZN(net_349), .A1(net_164), .A2(net_92) );
XNOR2_X1 inst_302 ( .A(net_1039), .B(net_981), .ZN(n321) );
OR2_X4 inst_322 ( .A2(net_1027), .ZN(net_552), .A1(net_497) );
NAND2_X1 inst_673 ( .A2(net_191), .ZN(net_151), .A1(n138) );
XNOR2_X1 inst_211 ( .ZN(net_858), .B(net_749), .A(net_717) );
NAND2_X1 inst_619 ( .ZN(net_52), .A2(n190), .A1(n18) );
NAND2_X1 inst_681 ( .ZN(net_258), .A2(net_127), .A1(net_40) );
NAND3_X1 inst_561 ( .ZN(net_481), .A3(net_480), .A2(net_323), .A1(net_285) );
NOR2_X1 inst_412 ( .ZN(net_452), .A2(net_239), .A1(n4420) );
NOR2_X1 inst_449 ( .A2(net_963), .ZN(net_495), .A1(net_383) );
NAND2_X1 inst_639 ( .ZN(net_71), .A2(n201), .A1(n18) );
MUX2_X2 inst_877 ( .Z(net_209), .S(net_191), .A(net_115), .B(n56) );
XNOR2_X1 inst_155 ( .ZN(net_449), .A(net_369), .B(net_347) );
NOR2_X1 inst_464 ( .ZN(net_659), .A2(net_546), .A1(net_435) );
MUX2_X2 inst_871 ( .Z(net_300), .S(net_191), .A(net_113), .B(n81) );
OR2_X2 inst_341 ( .ZN(net_545), .A2(net_544), .A1(net_486) );
INV_X1 inst_962 ( .ZN(net_28), .A(n2211) );
XNOR2_X1 inst_196 ( .A(net_925), .B(net_631), .ZN(n397) );
NAND4_X1 inst_532 ( .ZN(net_580), .A1(net_576), .A4(net_564), .A3(net_376), .A2(net_375) );
XOR2_X1 inst_55 ( .Z(net_357), .A(net_356), .B(net_355) );
NAND2_X1 inst_641 ( .ZN(net_73), .A2(n18), .A1(n158) );
NOR2_X1 inst_498 ( .A1(net_892), .ZN(net_870), .A2(net_849) );
NAND2_X1 inst_684 ( .ZN(net_136), .A2(net_135), .A1(net_43) );
XNOR2_X1 inst_298 ( .B(net_1023), .A(net_989), .ZN(n327) );
AND2_X4 inst_1137 ( .ZN(net_686), .A1(net_685), .A2(net_684) );
XOR2_X1 inst_42 ( .Z(net_413), .A(net_308), .B(net_307) );
OR2_X4 inst_323 ( .A2(net_1031), .ZN(net_557), .A1(net_506) );
NAND3_X1 inst_588 ( .ZN(net_856), .A1(net_723), .A3(net_552), .A2(net_501) );
NOR3_X1 inst_350 ( .ZN(net_766), .A3(net_381), .A2(net_163), .A1(net_129) );
XNOR2_X1 inst_231 ( .ZN(net_855), .A(net_796), .B(net_791) );
AND2_X4 inst_1138 ( .ZN(net_700), .A2(net_646), .A1(net_198) );
AND2_X4 inst_1119 ( .A1(net_572), .A2(net_469), .ZN(net_416) );
INV_X1 inst_1038 ( .ZN(net_743), .A(net_742) );
NAND2_X1 inst_793 ( .A1(net_692), .ZN(net_672), .A2(net_668) );
NAND2_X1 inst_715 ( .ZN(net_379), .A2(net_125), .A1(net_55) );
NOR2_X1 inst_437 ( .ZN(net_546), .A2(net_511), .A1(net_483) );
INV_X1 inst_940 ( .ZN(net_14), .A(n2236) );
INV_X1 inst_1004 ( .ZN(net_733), .A(net_463) );
XNOR2_X1 inst_189 ( .ZN(net_705), .B(net_642), .A(net_449) );
XOR2_X1 inst_14 ( .A(net_373), .B(net_228), .Z(net_225) );
NOR2_X1 inst_475 ( .A1(net_1025), .ZN(net_687), .A2(net_685) );
XOR2_X1 inst_31 ( .B(net_304), .Z(net_287), .A(net_286) );
INV_X1 inst_1045 ( .A(net_898), .ZN(net_872) );
NAND4_X1 inst_528 ( .ZN(net_670), .A1(net_573), .A3(net_572), .A2(net_469), .A4(net_270) );
MUX2_X2 inst_865 ( .Z(net_204), .S(net_191), .A(net_16), .B(n88) );
XNOR2_X1 inst_252 ( .ZN(net_912), .A(net_911), .B(net_874) );
MUX2_X2 inst_903 ( .S(net_962), .B(net_455), .A(net_453), .Z(n353) );
XOR2_X1 inst_62 ( .Z(net_596), .B(net_325), .A(n4420) );
INV_X1 inst_956 ( .ZN(net_25), .A(n4415) );
XNOR2_X1 inst_251 ( .ZN(net_910), .B(net_880), .A(net_873) );
NOR3_X1 inst_352 ( .ZN(net_681), .A1(net_528), .A2(net_440), .A3(net_438) );
NAND3_X1 inst_575 ( .A2(net_747), .ZN(net_614), .A1(net_613), .A3(net_608) );
CLKBUF_X1 inst_1074 ( .Z(n484), .A(n2247) );
NAND2_X1 inst_846 ( .A2(net_971), .ZN(net_970), .A1(net_594) );
XNOR2_X1 inst_286 ( .B(net_1016), .A(net_988), .ZN(n333) );
MUX2_X2 inst_879 ( .Z(net_363), .S(net_191), .A(net_11), .B(n109) );
NOR2_X1 inst_484 ( .A2(net_840), .ZN(net_774), .A1(net_605) );
NAND2_X1 inst_627 ( .ZN(net_59), .A2(n232), .A1(n18) );
XOR2_X1 inst_32 ( .B(net_302), .Z(net_288), .A(net_265) );
NOR4_X1 inst_344 ( .A2(net_1025), .A3(net_1004), .A1(net_967), .ZN(net_735), .A4(net_668) );
NOR2_X1 inst_428 ( .ZN(net_435), .A2(net_184), .A1(n3737) );
INV_X1 inst_969 ( .A(net_351), .ZN(net_173) );
NAND2_X1 inst_629 ( .ZN(net_61), .A2(n229), .A1(n18) );
AND3_X4 inst_1100 ( .ZN(net_644), .A3(net_478), .A1(net_197), .A2(net_196) );
NOR2_X1 inst_407 ( .ZN(net_372), .A1(net_164), .A2(net_82) );
NAND2_X1 inst_791 ( .ZN(net_667), .A2(net_658), .A1(net_657) );
NAND2_X1 inst_623 ( .ZN(net_55), .A2(n192), .A1(n18) );
CLKBUF_X1 inst_1072 ( .Z(n488), .A(n2236) );
INV_X1 inst_1044 ( .ZN(net_983), .A(net_866) );
XNOR2_X1 inst_97 ( .ZN(net_254), .A(net_166), .B(net_130) );
NAND2_X1 inst_616 ( .ZN(net_49), .A2(n239), .A1(n18) );
MUX2_X2 inst_898 ( .Z(net_898), .A(net_865), .B(net_864), .S(net_852) );
NAND2_X1 inst_775 ( .ZN(net_628), .A2(net_597), .A1(n4526) );
NAND4_X1 inst_533 ( .A1(net_645), .ZN(net_582), .A4(net_478), .A3(net_321), .A2(net_216) );
NAND2_X1 inst_620 ( .ZN(net_53), .A2(n18), .A1(n171) );
AND3_X4 inst_1107 ( .ZN(net_607), .A3(net_606), .A2(net_603), .A1(net_437) );
NAND2_X1 inst_652 ( .A2(net_191), .ZN(net_156), .A1(n70) );
XNOR2_X1 inst_137 ( .ZN(net_432), .A(net_289), .B(n4432) );
NAND2_X1 inst_677 ( .ZN(net_121), .A2(net_120), .A1(n38) );
NOR2_X1 inst_425 ( .ZN(net_249), .A2(net_178), .A1(n1486) );
XNOR2_X1 inst_130 ( .ZN(net_389), .A(net_262), .B(n4415) );
NAND2_X1 inst_722 ( .ZN(net_282), .A2(net_149), .A1(net_72) );
XNOR2_X1 inst_227 ( .ZN(net_843), .B(net_842), .A(net_780) );
CLKBUF_X1 inst_1095 ( .A(n264), .Z(n258) );
NAND2_X1 inst_760 ( .ZN(net_538), .A1(net_415), .A2(net_414) );
NAND2_X1 inst_746 ( .ZN(net_309), .A2(net_224), .A1(net_191) );
XNOR2_X1 inst_176 ( .ZN(net_636), .B(net_451), .A(net_257) );
XOR2_X1 inst_58 ( .Z(net_471), .B(net_338), .A(net_202) );
XOR2_X1 inst_87 ( .B(net_1029), .A(net_994), .Z(n313) );
CLKBUF_X1 inst_1054 ( .Z(n548), .A(n3737) );
INV_X1 inst_972 ( .A(net_272), .ZN(net_175) );
INV_X1 inst_983 ( .A(net_367), .ZN(net_183) );
NAND2_X1 inst_800 ( .ZN(net_691), .A1(net_622), .A2(net_616) );
NAND2_X1 inst_780 ( .A2(net_805), .ZN(net_626), .A1(net_492) );
XOR2_X1 inst_10 ( .B(net_361), .Z(net_218), .A(net_199) );
XOR2_X1 inst_4 ( .A(net_375), .B(net_259), .Z(net_208) );
AND2_X4 inst_1110 ( .ZN(net_163), .A2(net_162), .A1(net_128) );
NAND3_X1 inst_581 ( .ZN(net_624), .A1(net_623), .A3(net_611), .A2(net_590) );
NAND2_X1 inst_600 ( .ZN(net_33), .A2(n208), .A1(n18) );
XOR2_X1 inst_28 ( .Z(net_480), .B(net_282), .A(net_206) );
CLKBUF_X1 inst_1089 ( .A(n471), .Z(n419) );
XOR2_X1 inst_49 ( .A(net_360), .Z(net_340), .B(net_200) );
XNOR2_X1 inst_204 ( .ZN(net_800), .B(net_720), .A(net_663) );
NAND3_X1 inst_592 ( .ZN(net_932), .A1(net_931), .A3(net_930), .A2(net_821) );
NAND4_X1 inst_546 ( .A1(net_739), .A2(net_738), .A4(net_737), .A3(net_707), .ZN(n416) );
INV_X1 inst_993 ( .A(net_512), .ZN(net_483) );
MUX2_X2 inst_910 ( .S(net_997), .A(net_779), .B(net_734), .Z(n301) );
NAND2_X1 inst_704 ( .ZN(net_152), .A2(net_137), .A1(net_41) );
NAND2_X1 inst_693 ( .ZN(net_310), .A2(net_144), .A1(net_70) );
NOR2_X1 inst_390 ( .ZN(net_343), .A1(net_164), .A2(net_84) );
CLKBUF_X1 inst_1062 ( .Z(n532), .A(n4415) );
NOR2_X1 inst_359 ( .A1(net_191), .ZN(net_83), .A2(n154) );
CLKBUF_X1 inst_1055 ( .Z(n546), .A(n3743) );
NAND2_X1 inst_765 ( .ZN(net_529), .A2(net_442), .A1(net_411) );
XNOR2_X1 inst_256 ( .B(net_956), .ZN(net_927), .A(net_883) );
NAND2_X1 inst_694 ( .ZN(net_307), .A2(net_145), .A1(net_44) );
NAND2_X1 inst_630 ( .ZN(net_62), .A2(n205), .A1(n18) );
INV_X1 inst_937 ( .ZN(net_111), .A(n4405) );
NOR2_X1 inst_401 ( .ZN(net_346), .A1(net_164), .A2(net_83) );
INV_X1 inst_923 ( .ZN(net_2), .A(n1469) );
NOR2_X1 inst_512 ( .ZN(net_976), .A2(net_960), .A1(net_856) );
MUX2_X2 inst_908 ( .Z(net_984), .S(net_983), .B(net_949), .A(net_948) );
NOR3_X1 inst_355 ( .ZN(net_914), .A1(net_870), .A3(net_869), .A2(net_187) );
NAND2_X1 inst_782 ( .ZN(net_631), .A1(net_630), .A2(net_628) );
XNOR2_X1 inst_218 ( .ZN(net_798), .A(net_797), .B(net_748) );
NAND2_X1 inst_647 ( .ZN(net_78), .A2(n224), .A1(n18) );
XOR2_X1 inst_6 ( .B(net_300), .Z(net_212), .A(net_211) );
XNOR2_X1 inst_194 ( .ZN(net_732), .B(net_731), .A(net_460) );
INV_X1 inst_1014 ( .ZN(net_1027), .A(net_722) );
NAND2_X1 inst_787 ( .A2(net_797), .ZN(net_661), .A1(net_537) );
NAND2_X1 inst_825 ( .ZN(net_877), .A2(net_847), .A1(net_754) );
NAND2_X1 inst_833 ( .ZN(net_899), .A2(net_898), .A1(net_654) );
XNOR2_X1 inst_123 ( .ZN(net_387), .A(net_329), .B(n3737) );
NOR2_X1 inst_509 ( .ZN(net_974), .A1(net_939), .A2(net_909) );
INV_X1 inst_930 ( .ZN(net_6), .A(n4432) );
NAND2_X1 inst_699 ( .ZN(net_286), .A2(net_148), .A1(net_64) );
INV_X1 inst_960 ( .ZN(net_27), .A(n58) );
XNOR2_X1 inst_118 ( .ZN(net_1001), .A(net_343), .B(n2236) );
INV_X1 inst_935 ( .ZN(net_11), .A(n2253) );
XNOR2_X1 inst_153 ( .ZN(net_447), .A(net_327), .B(net_291) );
NOR2_X1 inst_442 ( .A2(net_963), .A1(net_905), .ZN(net_591) );
XOR2_X1 inst_38 ( .Z(net_303), .A(net_302), .B(net_301) );
NOR2_X1 inst_381 ( .ZN(net_162), .A1(net_96), .A2(n1455) );
NAND2_X1 inst_726 ( .ZN(net_292), .A2(net_165), .A1(net_59) );
XNOR2_X1 inst_295 ( .ZN(net_1033), .B(net_1031), .A(net_1017) );
MUX2_X2 inst_883 ( .S(net_191), .Z(net_118), .B(net_27), .A(n4393) );
XNOR2_X1 inst_209 ( .ZN(net_884), .B(net_726), .A(net_682) );
INV_X1 inst_964 ( .ZN(net_169), .A(net_168) );
CLKBUF_X1 inst_1087 ( .Z(n432), .A(n1) );
XOR2_X1 inst_40 ( .Z(net_476), .B(net_286), .A(net_214) );
OR2_X4 inst_320 ( .A1(net_571), .ZN(net_540), .A2(net_511) );
XNOR2_X1 inst_167 ( .ZN(net_513), .A(net_512), .B(net_511) );
NAND2_X1 inst_607 ( .ZN(net_40), .A2(n202), .A1(n18) );
INV_X1 inst_1026 ( .ZN(net_595), .A(net_492) );
NAND2_X1 inst_756 ( .ZN(net_609), .A1(net_590), .A2(net_414) );
XNOR2_X1 inst_95 ( .ZN(net_230), .A(net_123), .B(net_107) );
XOR2_X1 inst_1 ( .A(net_363), .Z(net_203), .B(net_202) );
NOR2_X1 inst_439 ( .A1(net_1031), .A2(net_956), .ZN(net_604) );
OR2_X4 inst_331 ( .A1(net_814), .ZN(net_757), .A2(net_670) );
CLKBUF_X1 inst_1070 ( .Z(n492), .A(n2224) );
XNOR2_X1 inst_235 ( .ZN(net_862), .A(net_861), .B(net_806) );
NAND2_X1 inst_750 ( .ZN(net_243), .A2(net_235), .A1(n1462) );
OR2_X4 inst_317 ( .ZN(net_382), .A2(net_381), .A1(net_162) );
AND2_X4 inst_1123 ( .ZN(net_425), .A2(net_424), .A1(net_379) );
CLKBUF_X1 inst_1082 ( .Z(n444), .A(n1480) );
NAND2_X1 inst_667 ( .A2(net_191), .ZN(net_131), .A1(n100) );
XNOR2_X1 inst_278 ( .A(net_1016), .ZN(net_1006), .B(net_972) );
NOR2_X1 inst_467 ( .ZN(net_558), .A2(net_557), .A1(net_503) );
INV_X1 inst_992 ( .ZN(net_728), .A(net_384) );
XNOR2_X1 inst_105 ( .ZN(net_324), .A(net_323), .B(net_282) );
NOR2_X1 inst_488 ( .A2(net_987), .ZN(net_807), .A1(net_677) );
NOR2_X1 inst_387 ( .A1(net_164), .ZN(net_130), .A2(net_98) );
INV_X1 inst_997 ( .A(net_965), .ZN(net_489) );
MUX2_X2 inst_857 ( .Z(net_228), .S(net_191), .A(net_24), .B(n113) );
XNOR2_X1 inst_254 ( .B(net_939), .ZN(net_919), .A(net_888) );
NAND2_X1 inst_654 ( .A2(net_191), .ZN(net_139), .A1(n144) );
NAND2_X1 inst_625 ( .ZN(net_57), .A2(n222), .A1(n18) );
XNOR2_X1 inst_225 ( .ZN(net_839), .B(net_775), .A(net_772) );
NOR2_X1 inst_508 ( .ZN(net_938), .A2(net_906), .A1(net_814) );
NAND3_X1 inst_568 ( .ZN(net_584), .A3(net_563), .A2(net_361), .A1(net_360) );
NAND4_X1 inst_523 ( .A2(net_568), .A4(net_567), .ZN(net_466), .A1(net_358), .A3(net_354) );
NOR2_X1 inst_365 ( .A1(net_191), .ZN(net_89), .A2(n211) );
XOR2_X1 inst_67 ( .Z(net_967), .B(net_272), .A(n3723) );
INV_X1 inst_954 ( .ZN(net_23), .A(n4420) );
XNOR2_X1 inst_181 ( .ZN(net_641), .B(net_446), .A(net_279) );
AND2_X4 inst_1135 ( .ZN(net_671), .A2(net_574), .A1(net_192) );
NOR2_X1 inst_391 ( .ZN(net_356), .A1(net_164), .A2(net_101) );
NAND2_X1 inst_661 ( .A2(net_191), .ZN(net_144), .A1(n121) );
NAND3_X1 inst_590 ( .ZN(net_813), .A1(net_812), .A3(net_675), .A2(n89) );
NAND2_X1 inst_713 ( .ZN(net_275), .A2(net_154), .A1(net_74) );
XNOR2_X1 inst_202 ( .ZN(net_792), .A(net_660), .B(net_570) );
NAND2_X1 inst_634 ( .ZN(net_66), .A2(n225), .A1(n18) );
NOR2_X1 inst_419 ( .ZN(net_247), .A2(net_171), .A1(n2236) );
AND3_X4 inst_1105 ( .ZN(net_678), .A2(net_615), .A3(net_606), .A1(net_603) );
INV_X1 inst_981 ( .A(net_275), .ZN(net_181) );
NOR2_X1 inst_477 ( .A2(net_750), .ZN(net_718), .A1(net_543) );
NOR2_X1 inst_423 ( .ZN(net_531), .A2(net_174), .A1(n2218) );
CLKBUF_X1 inst_1069 ( .Z(n494), .A(n2218) );
NAND2_X1 inst_835 ( .ZN(net_931), .A1(net_904), .A2(net_871) );
XNOR2_X1 inst_136 ( .ZN(net_696), .A(net_348), .B(n1480) );
XOR2_X1 inst_30 ( .Z(net_467), .B(net_323), .A(net_285) );
OR2_X4 inst_330 ( .A1(net_756), .A2(net_668), .ZN(net_629) );
NAND2_X1 inst_610 ( .ZN(net_43), .A2(n181), .A1(n18) );
AND2_X4 inst_1112 ( .A2(net_965), .A1(net_751), .ZN(net_399) );
INV_X1 inst_1036 ( .ZN(net_845), .A(net_712) );
XNOR2_X1 inst_233 ( .ZN(net_859), .B(net_858), .A(net_801) );
NAND2_X1 inst_710 ( .ZN(net_290), .A2(net_148), .A1(net_37) );
XNOR2_X1 inst_165 ( .ZN(net_509), .B(net_340), .A(net_339) );
INV_X1 inst_941 ( .ZN(net_756), .A(n4526) );
XNOR2_X1 inst_271 ( .ZN(net_990), .A(net_989), .B(net_957) );
XOR2_X1 inst_34 ( .Z(net_294), .A(net_293), .B(net_292) );
XOR2_X1 inst_12 ( .B(net_308), .A(net_297), .Z(net_222) );
INV_X1 inst_1047 ( .ZN(net_951), .A(net_931) );
NAND4_X1 inst_529 ( .ZN(net_574), .A2(net_573), .A4(net_572), .A1(net_421), .A3(net_269) );
XOR2_X1 inst_56 ( .Z(net_567), .B(net_356), .A(net_204) );
XOR2_X1 inst_71 ( .A(net_462), .Z(net_461), .B(net_460) );
OR3_X4 inst_308 ( .A2(net_720), .ZN(net_676), .A1(net_596), .A3(net_544) );
XOR2_X1 inst_60 ( .Z(net_369), .A(net_368), .B(net_367) );
NOR2_X1 inst_455 ( .A2(net_925), .A1(net_630), .ZN(net_516) );
CLKBUF_X1 inst_1064 ( .Z(n528), .A(n4427) );
NAND2_X1 inst_675 ( .A2(net_80), .ZN(n289), .A1(n1197) );
NAND2_X1 inst_758 ( .A1(net_911), .ZN(net_522), .A2(net_411) );
NOR2_X1 inst_496 ( .ZN(net_849), .A1(net_848), .A2(net_815) );
MUX2_X2 inst_860 ( .S(net_191), .Z(net_110), .B(net_20), .A(n3698) );
OR2_X4 inst_336 ( .ZN(net_934), .A1(net_913), .A2(net_885) );
NAND3_X1 inst_563 ( .ZN(net_758), .A3(net_576), .A2(net_564), .A1(net_377) );
NAND3_X1 inst_583 ( .ZN(net_746), .A1(net_656), .A3(net_655), .A2(net_497) );
INV_X1 inst_943 ( .ZN(net_108), .A(n106) );
XNOR2_X1 inst_258 ( .A(net_965), .ZN(net_941), .B(net_903) );
NOR2_X1 inst_376 ( .A1(net_191), .ZN(net_101), .A2(n166) );
XNOR2_X1 inst_143 ( .ZN(net_394), .B(net_226), .A(net_212) );
XNOR2_X1 inst_265 ( .ZN(net_966), .A(net_965), .B(net_919) );
NOR2_X1 inst_482 ( .A2(net_772), .ZN(net_771), .A1(net_599) );
INV_X1 inst_1040 ( .ZN(net_765), .A(net_764) );
NAND2_X1 inst_682 ( .ZN(net_293), .A2(net_131), .A1(net_35) );
NAND2_X1 inst_736 ( .A1(net_321), .A2(net_216), .ZN(net_197) );
NAND4_X1 inst_544 ( .ZN(net_764), .A4(net_671), .A2(net_565), .A1(net_470), .A3(net_408) );
XNOR2_X1 inst_238 ( .ZN(net_881), .B(net_880), .A(net_839) );
CLKBUF_X1 inst_1093 ( .A(n292), .Z(n281) );
NAND4_X1 inst_539 ( .ZN(net_848), .A4(net_581), .A2(net_575), .A3(net_477), .A1(net_195) );
NAND2_X1 inst_724 ( .ZN(net_277), .A2(net_142), .A1(net_38) );
MUX2_X2 inst_895 ( .B(net_853), .S(net_852), .A(net_794), .Z(n376) );
XNOR2_X1 inst_178 ( .ZN(net_638), .B(net_510), .A(net_359) );
XNOR2_X1 inst_111 ( .ZN(net_366), .A(net_365), .B(net_364) );
INV_X1 inst_975 ( .A(net_289), .ZN(net_177) );
NAND2_X1 inst_734 ( .A1(net_282), .A2(net_206), .ZN(net_194) );
CLKBUF_X1 inst_1077 ( .Z(n478), .A(n2211) );
XNOR2_X1 inst_222 ( .ZN(net_827), .A(net_769), .B(net_664) );
XNOR2_X1 inst_284 ( .B(net_1018), .A(net_536), .ZN(n471) );
NAND2_X1 inst_806 ( .ZN(net_714), .A2(net_713), .A1(net_541) );
XNOR2_X1 inst_280 ( .ZN(net_1010), .B(net_1009), .A(net_979) );
NAND2_X1 inst_763 ( .ZN(net_524), .A2(net_462), .A1(net_388) );
NOR4_X1 inst_346 ( .ZN(net_907), .A2(net_690), .A1(net_553), .A4(net_502), .A3(net_245) );
NOR2_X1 inst_491 ( .A1(net_865), .ZN(net_847), .A2(net_763) );
CLKBUF_X1 inst_1052 ( .Z(n552), .A(n3723) );
INV_X1 inst_978 ( .A(net_325), .ZN(net_239) );
CLKBUF_X1 inst_1079 ( .Z(n450), .A(n1459) );
NAND2_X1 inst_842 ( .ZN(net_954), .A2(net_924), .A1(net_805) );
NAND4_X1 inst_537 ( .ZN(net_646), .A1(net_645), .A2(net_644), .A3(net_267), .A4(net_266) );
NAND2_X1 inst_826 ( .ZN(net_850), .A2(net_847), .A1(net_824) );
NAND4_X1 inst_551 ( .ZN(net_913), .A4(net_820), .A3(net_559), .A1(net_532), .A2(net_465) );
CLKBUF_X1 inst_1051 ( .Z(n554), .A(n3717) );
XNOR2_X1 inst_207 ( .B(net_1004), .A(net_693), .ZN(n394) );
NOR3_X1 inst_353 ( .ZN(net_713), .A1(net_547), .A3(net_436), .A2(net_430) );
NOR2_X1 inst_495 ( .A2(net_847), .ZN(net_846), .A1(net_845) );
NOR2_X1 inst_506 ( .ZN(net_915), .A2(net_914), .A1(net_893) );
XNOR2_X1 inst_159 ( .A(net_485), .ZN(net_455), .B(net_454) );
MUX2_X2 inst_872 ( .Z(net_306), .S(net_191), .A(net_29), .B(n60) );
INV_X1 inst_951 ( .ZN(net_21), .A(n3743) );
XNOR2_X1 inst_134 ( .ZN(net_601), .A(net_331), .B(n4394) );
CLKBUF_X1 inst_1085 ( .Z(n438), .A(n1496) );
OR2_X4 inst_333 ( .A2(net_865), .ZN(net_864), .A1(net_762) );
NAND2_X1 inst_712 ( .ZN(net_342), .A2(net_160), .A1(net_73) );
XNOR2_X1 inst_131 ( .ZN(net_592), .A(net_278), .B(n4405) );
NOR2_X1 inst_406 ( .ZN(net_355), .A1(net_164), .A2(net_103) );
XNOR2_X1 inst_160 ( .ZN(net_456), .B(net_288), .A(net_256) );
NOR2_X1 inst_462 ( .A1(net_999), .ZN(net_553), .A2(net_552) );
OR2_X4 inst_328 ( .A1(net_880), .ZN(net_539), .A2(net_538) );
MUX2_X2 inst_869 ( .Z(net_281), .S(net_191), .A(net_15), .B(n74) );
XOR2_X1 inst_19 ( .Z(net_263), .A(net_262), .B(net_261) );
XOR2_X1 inst_47 ( .Z(net_332), .B(net_331), .A(net_138) );
XOR2_X1 inst_8 ( .B(net_305), .Z(net_215), .A(net_214) );
NAND2_X1 inst_818 ( .A2(net_867), .ZN(net_823), .A1(net_744) );
NOR2_X1 inst_370 ( .A1(net_191), .ZN(net_95), .A2(n175) );
NAND2_X1 inst_762 ( .ZN(net_420), .A2(net_382), .A1(net_182) );
NAND3_X1 inst_573 ( .ZN(net_653), .A3(net_613), .A2(net_608), .A1(net_601) );
XNOR2_X1 inst_100 ( .A(net_267), .ZN(net_260), .B(net_136) );
INV_X1 inst_965 ( .A(net_290), .ZN(net_170) );
INV_X1 inst_921 ( .ZN(net_0), .A(n4400) );
XNOR2_X1 inst_279 ( .B(net_975), .A(net_965), .ZN(n319) );
XOR2_X1 inst_81 ( .Z(net_796), .A(net_795), .B(net_794) );
NAND2_X1 inst_612 ( .ZN(net_45), .A2(n18), .A1(n159) );
NAND4_X1 inst_525 ( .ZN(net_473), .A3(net_472), .A4(net_471), .A2(net_400), .A1(net_238) );
INV_X1 inst_1012 ( .ZN(net_1009), .A(net_592) );
MUX2_X2 inst_901 ( .Z(net_948), .A(net_947), .B(net_946), .S(net_811) );
NOR2_X1 inst_434 ( .ZN(net_645), .A2(net_409), .A1(net_316) );
NAND2_X1 inst_790 ( .ZN(net_666), .A2(net_656), .A1(net_655) );
INV_X1 inst_1032 ( .ZN(net_654), .A(net_653) );
INV_X1 inst_1009 ( .ZN(net_956), .A(net_411) );
NAND2_X1 inst_751 ( .ZN(net_514), .A2(net_234), .A1(n3729) );
MUX2_X2 inst_906 ( .Z(net_978), .S(net_977), .A(net_863), .B(net_830) );
NAND2_X1 inst_845 ( .A2(net_971), .ZN(net_969), .A1(net_652) );
NAND2_X1 inst_733 ( .A1(net_356), .A2(net_204), .ZN(net_193) );
NOR2_X1 inst_377 ( .A1(net_191), .ZN(net_102), .A2(n174) );
XNOR2_X1 inst_142 ( .ZN(net_393), .B(net_210), .A(net_208) );
XOR2_X1 inst_78 ( .Z(net_802), .A(net_749), .B(net_716) );
XNOR2_X1 inst_177 ( .ZN(net_637), .B(net_457), .A(net_322) );
NAND2_X1 inst_783 ( .ZN(net_632), .A2(net_610), .A1(net_609) );
MUX2_X2 inst_885 ( .Z(net_216), .S(net_191), .A(net_9), .B(n83) );
XNOR2_X1 inst_183 ( .ZN(net_643), .B(net_450), .A(net_353) );
NAND2_X1 inst_852 ( .ZN(net_996), .A2(net_995), .A1(net_728) );
AND2_X4 inst_1142 ( .ZN(net_960), .A2(net_959), .A1(net_722) );
INV_X1 inst_928 ( .ZN(n341), .A(n15) );
INV_X1 inst_1028 ( .A(net_758), .ZN(net_600) );
XNOR2_X1 inst_107 ( .ZN(net_337), .A(net_336), .B(net_335) );
NOR2_X1 inst_393 ( .ZN(net_336), .A1(net_164), .A2(net_81) );
NAND2_X1 inst_615 ( .ZN(net_48), .A2(n236), .A1(n18) );
INV_X1 inst_990 ( .ZN(net_486), .A(net_452) );
XNOR2_X1 inst_92 ( .A(net_269), .ZN(net_226), .B(net_118) );
NOR4_X1 inst_345 ( .ZN(net_950), .A2(net_691), .A1(net_555), .A4(net_500), .A3(net_247) );
CLKBUF_X1 inst_1050 ( .Z(n556), .A(n3711) );
NAND2_X1 inst_643 ( .ZN(net_75), .A2(n235), .A1(n18) );
NAND2_X1 inst_697 ( .ZN(net_312), .A2(net_147), .A1(net_79) );
NOR2_X1 inst_487 ( .A2(net_861), .ZN(net_790), .A1(net_607) );
XNOR2_X1 inst_200 ( .ZN(net_740), .B(net_639), .A(net_393) );
XOR2_X1 inst_57 ( .Z(net_472), .A(net_361), .B(net_360) );
OR2_X4 inst_338 ( .A2(net_977), .ZN(net_973), .A1(net_808) );
NOR2_X1 inst_417 ( .ZN(net_401), .A2(net_177), .A1(n4432) );
NAND2_X1 inst_671 ( .A2(net_191), .ZN(net_135), .A1(n141) );
INV_X1 inst_1017 ( .ZN(net_1031), .A(net_696) );
XOR2_X1 inst_21 ( .Z(net_412), .B(net_265), .A(net_209) );
NAND3_X1 inst_579 ( .A1(net_722), .ZN(net_621), .A3(net_613), .A2(net_556) );
XNOR2_X1 inst_281 ( .ZN(net_1013), .A(net_1012), .B(net_980) );
CLKBUF_X1 inst_1094 ( .A(n341), .Z(n279) );
NAND3_X1 inst_585 ( .ZN(net_772), .A1(net_689), .A3(net_494), .A2(net_426) );
NAND2_X1 inst_698 ( .ZN(net_261), .A2(net_144), .A1(net_78) );
MUX2_X2 inst_893 ( .S(net_852), .B(net_515), .A(net_513), .Z(n382) );
XOR2_X1 inst_88 ( .B(net_1031), .A(net_1011), .Z(n330) );
NOR2_X1 inst_410 ( .ZN(net_384), .A2(net_235), .A1(n1462) );
OR2_X4 inst_316 ( .ZN(net_233), .A1(net_232), .A2(net_231) );
XNOR2_X1 inst_220 ( .ZN(net_806), .A(net_805), .B(net_752) );
NAND2_X1 inst_851 ( .ZN(net_993), .A1(net_987), .A2(net_973) );
NAND2_X1 inst_831 ( .ZN(net_879), .A2(net_877), .A1(net_875) );
NOR2_X1 inst_360 ( .A1(net_191), .ZN(net_84), .A2(n157) );
NOR2_X1 inst_383 ( .A2(net_124), .ZN(net_116), .A1(n38) );
INV_X1 inst_1023 ( .ZN(net_880), .A(net_597) );
XOR2_X1 inst_50 ( .Z(net_568), .B(net_355), .A(net_341) );
NAND2_X1 inst_773 ( .ZN(net_1019), .A2(net_677), .A1(net_443) );
XNOR2_X1 inst_245 ( .ZN(net_942), .B(net_855), .A(net_512) );
NAND3_X1 inst_569 ( .ZN(net_808), .A2(net_696), .A1(net_617), .A3(net_594) );
CLKBUF_X1 inst_1080 ( .Z(n448), .A(n1469) );
AND2_X4 inst_1124 ( .ZN(net_434), .A1(net_433), .A2(net_432) );
NAND2_X1 inst_678 ( .ZN(net_232), .A2(net_124), .A1(n38) );
NAND2_X1 inst_624 ( .ZN(net_56), .A2(n207), .A1(n18) );
AND3_X4 inst_1103 ( .ZN(net_599), .A3(net_598), .A1(net_597), .A2(net_414) );
XNOR2_X1 inst_260 ( .ZN(net_955), .B(net_925), .A(net_910) );
AND2_X4 inst_1129 ( .A1(net_601), .A2(net_548), .ZN(net_542) );
NAND2_X1 inst_854 ( .A2(net_1003), .A1(net_920), .ZN(n249) );
XNOR2_X1 inst_147 ( .ZN(net_398), .A(net_218), .B(net_203) );
NAND2_X1 inst_837 ( .ZN(net_908), .A2(net_897), .A1(net_797) );
OR2_X4 inst_313 ( .A1(net_200), .A2(net_199), .ZN(net_188) );
NAND2_X1 inst_744 ( .ZN(net_504), .A2(net_348), .A1(net_122) );
NAND4_X1 inst_549 ( .A4(net_875), .ZN(net_818), .A3(net_753), .A2(net_712), .A1(n4526) );
INV_X1 inst_1041 ( .A(net_950), .ZN(net_819) );
XNOR2_X1 inst_234 ( .ZN(net_860), .A(net_804), .B(net_799) );
NAND4_X1 inst_522 ( .ZN(net_465), .A1(net_464), .A3(net_463), .A4(net_462), .A2(net_439) );
XNOR2_X1 inst_236 ( .ZN(net_873), .A(net_826), .B(net_771) );
INV_X1 inst_1002 ( .ZN(net_745), .A(net_428) );
NOR2_X1 inst_478 ( .ZN(net_721), .A1(net_720), .A2(net_665) );
NAND4_X1 inst_553 ( .ZN(net_981), .A3(net_953), .A2(net_952), .A1(net_932), .A4(net_929) );
XOR2_X1 inst_65 ( .Z(net_380), .A(net_379), .B(net_378) );
NAND4_X1 inst_536 ( .ZN(net_593), .A4(net_568), .A1(net_488), .A3(net_365), .A2(net_364) );
XNOR2_X1 inst_242 ( .ZN(net_887), .A(net_837), .B(net_789) );
INV_X1 inst_986 ( .A(net_346), .ZN(net_185) );
NAND2_X1 inst_688 ( .ZN(net_141), .A2(net_135), .A1(net_34) );
NOR2_X1 inst_516 ( .ZN(net_1014), .A2(net_992), .A1(net_861) );
NAND2_X1 inst_804 ( .ZN(net_697), .A1(net_696), .A2(net_634) );
XNOR2_X1 inst_190 ( .ZN(net_706), .B(net_643), .A(net_254) );
XOR2_X1 inst_13 ( .B(net_284), .A(net_281), .Z(net_223) );
INV_X8 inst_919 ( .ZN(net_191), .A(n18) );
XNOR2_X1 inst_116 ( .ZN(net_374), .A(net_373), .B(net_372) );
NOR2_X1 inst_416 ( .ZN(net_556), .A2(net_186), .A1(n4400) );
NAND2_X1 inst_598 ( .ZN(net_32), .A2(n227), .A1(n18) );
AND2_X4 inst_1133 ( .ZN(net_585), .A2(net_475), .A1(net_193) );
NOR2_X1 inst_471 ( .ZN(net_867), .A1(net_676), .A2(net_674) );
NAND2_X1 inst_799 ( .ZN(net_690), .A1(net_621), .A2(net_614) );
XNOR2_X1 inst_219 ( .ZN(net_801), .A(net_800), .B(net_799) );
NAND2_X1 inst_738 ( .ZN(net_237), .A1(net_200), .A2(net_199) );
NAND2_X1 inst_719 ( .ZN(net_289), .A2(net_161), .A1(net_76) );
NAND2_X1 inst_840 ( .ZN(net_935), .A2(net_934), .A1(net_708) );
XNOR2_X1 inst_255 ( .ZN(net_926), .B(net_925), .A(net_881) );
NAND4_X1 inst_542 ( .ZN(net_761), .A3(net_624), .A4(net_612), .A2(net_530), .A1(net_474) );
XNOR2_X1 inst_128 ( .ZN(net_411), .A(net_351), .B(n1469) );
NOR2_X1 inst_453 ( .ZN(net_505), .A1(net_504), .A2(net_503) );
AND2_X4 inst_1134 ( .ZN(net_665), .A2(net_545), .A1(net_423) );
NOR2_X1 inst_493 ( .ZN(net_833), .A1(net_832), .A2(net_783) );
XOR2_X1 inst_23 ( .A(net_295), .Z(net_270), .B(net_269) );
MUX2_X2 inst_896 ( .Z(net_863), .B(net_829), .A(net_828), .S(net_809) );
OR2_X2 inst_339 ( .ZN(n402), .A2(n57), .A1(n5) );
AND2_X4 inst_1113 ( .ZN(net_563), .A2(net_471), .A1(net_400) );
NOR3_X1 inst_351 ( .ZN(net_762), .A1(net_571), .A2(net_570), .A3(net_525) );
NOR2_X1 inst_408 ( .ZN(net_166), .A1(net_164), .A2(net_89) );
INV_X1 inst_973 ( .A(net_292), .ZN(net_176) );
AND2_X4 inst_1144 ( .ZN(net_992), .A2(net_991), .A1(net_724) );
OR2_X4 inst_325 ( .A1(net_630), .ZN(net_610), .A2(net_538) );
NOR2_X1 inst_461 ( .ZN(net_627), .A1(net_533), .A2(net_527) );
NOR2_X1 inst_385 ( .ZN(net_367), .A1(net_164), .A2(net_97) );
NAND2_X1 inst_829 ( .ZN(net_876), .A1(net_875), .A2(net_846) );
NAND2_X1 inst_812 ( .ZN(net_736), .A2(net_735), .A1(n4526) );
XNOR2_X1 inst_197 ( .ZN(net_737), .B(net_635), .A(net_456) );
XNOR2_X1 inst_179 ( .ZN(net_639), .B(net_458), .A(net_223) );
XOR2_X1 inst_24 ( .Z(net_273), .A(net_272), .B(net_271) );
INV_X1 inst_955 ( .ZN(net_24), .A(n1462) );
XNOR2_X1 inst_114 ( .ZN(net_989), .A(net_349), .B(n1486) );
AND2_X4 inst_1122 ( .ZN(net_527), .A1(net_464), .A2(net_462) );
XOR2_X1 inst_76 ( .Z(net_778), .A(net_726), .B(net_681) );
NAND2_X1 inst_617 ( .ZN(net_50), .A2(n237), .A1(n18) );
AND2_X4 inst_1127 ( .ZN(net_441), .A1(net_440), .A2(net_439) );
XNOR2_X1 inst_150 ( .ZN(net_444), .B(net_273), .A(net_251) );
XNOR2_X1 inst_172 ( .ZN(net_587), .B(net_396), .A(net_217) );
NOR2_X1 inst_362 ( .A1(net_191), .ZN(net_86), .A2(n165) );
XNOR2_X1 inst_277 ( .ZN(net_1005), .A(net_1004), .B(net_968) );
XOR2_X1 inst_83 ( .B(net_967), .A(net_773), .Z(n388) );
XNOR2_X1 inst_121 ( .ZN(net_439), .A(net_345), .B(n2256) );
MUX2_X2 inst_887 ( .Z(net_364), .S(net_191), .A(net_2), .B(n111) );
OR3_X4 inst_306 ( .A1(net_1025), .A3(net_967), .A2(net_493), .ZN(net_474) );
NAND4_X1 inst_534 ( .ZN(net_589), .A4(net_569), .A2(net_567), .A3(net_403), .A1(net_228) );
CLKBUF_X1 inst_1065 ( .Z(n526), .A(n4432) );
CLKBUF_X1 inst_1057 ( .Z(n542), .A(n3701) );
NAND2_X1 inst_596 ( .ZN(net_30), .A2(n18), .A1(n178) );
XNOR2_X1 inst_90 ( .ZN(net_536), .A(net_124), .B(n38) );
XNOR2_X1 inst_140 ( .ZN(net_534), .B(net_392), .A(net_116) );
XNOR2_X1 inst_267 ( .A(net_989), .ZN(net_972), .B(net_927) );
NAND2_X1 inst_847 ( .ZN(net_995), .A2(net_971), .A1(net_911) );
NAND2_X1 inst_748 ( .ZN(net_484), .A2(net_317), .A1(net_117) );
AND2_X2 inst_1146 ( .ZN(n278), .A1(n163), .A2(n1) );
NAND2_X1 inst_716 ( .ZN(net_318), .A2(net_151), .A1(net_31) );
NAND2_X1 inst_637 ( .ZN(net_69), .A2(n233), .A1(n18) );
NAND4_X1 inst_530 ( .ZN(net_575), .A2(net_476), .A1(net_425), .A4(net_417), .A3(net_378) );
NAND4_X1 inst_547 ( .A4(net_740), .A1(net_703), .A2(net_702), .A3(net_701), .ZN(n414) );
NAND2_X1 inst_792 ( .ZN(net_893), .A1(net_766), .A2(net_669) );
NAND2_X1 inst_720 ( .ZN(net_329), .A2(net_127), .A1(net_69) );
INV_X1 inst_958 ( .ZN(net_122), .A(n1480) );
NOR2_X1 inst_368 ( .A1(net_191), .ZN(net_92), .A2(n213) );
INV_X1 inst_1010 ( .ZN(net_517), .A(net_388) );
NAND2_X1 inst_803 ( .ZN(net_695), .A1(net_673), .A2(net_633) );
NAND2_X1 inst_769 ( .ZN(net_431), .A1(net_430), .A2(net_428) );
XNOR2_X1 inst_174 ( .B(net_756), .A(net_597), .ZN(n373) );
XNOR2_X1 inst_274 ( .ZN(net_998), .A(net_967), .B(net_955) );
NAND2_X1 inst_662 ( .A2(net_191), .ZN(net_160), .A1(n135) );
NAND2_X1 inst_701 ( .ZN(net_272), .A2(net_149), .A1(net_75) );
XNOR2_X1 inst_164 ( .ZN(net_508), .B(net_313), .A(net_287) );
MUX2_X2 inst_867 ( .Z(net_206), .S(net_191), .A(net_5), .B(n73) );
NAND2_X1 inst_820 ( .A2(net_907), .ZN(net_811), .A1(net_674) );
XOR2_X1 inst_5 ( .B(net_301), .Z(net_210), .A(net_209) );
XNOR2_X1 inst_157 ( .ZN(net_451), .B(net_311), .A(net_296) );
NAND2_X1 inst_729 ( .ZN(net_302), .A2(net_165), .A1(net_71) );
XNOR2_X1 inst_213 ( .ZN(net_777), .A(net_776), .B(net_730) );
XOR2_X1 inst_68 ( .Z(net_571), .B(net_328), .A(n3729) );
NAND2_X1 inst_604 ( .ZN(net_37), .A2(n219), .A1(n18) );
XOR2_X1 inst_53 ( .Z(net_350), .A(net_349), .B(net_348) );
INV_X1 inst_1007 ( .ZN(net_939), .A(net_603) );
XNOR2_X1 inst_205 ( .ZN(net_752), .A(net_751), .B(net_750) );
NAND2_X1 inst_753 ( .ZN(net_454), .A2(net_239), .A1(n4420) );
NOR2_X1 inst_380 ( .A1(net_191), .ZN(net_105), .A2(n164) );
INV_X1 inst_946 ( .ZN(net_17), .A(n85) );
NAND2_X1 inst_651 ( .A2(net_191), .ZN(net_140), .A1(n23) );
XNOR2_X1 inst_292 ( .ZN(net_1030), .B(net_1029), .A(net_1013) );
INV_X1 inst_999 ( .A(net_1001), .ZN(net_498) );
NOR2_X1 inst_379 ( .A1(net_191), .ZN(net_104), .A2(n216) );
INV_X1 inst_926 ( .ZN(net_113), .A(n4410) );
XNOR2_X1 inst_186 ( .ZN(net_702), .B(net_587), .A(net_398) );
XOR2_X1 inst_17 ( .A(net_376), .B(net_258), .Z(net_256) );
NAND2_X1 inst_706 ( .ZN(net_295), .A2(net_153), .A1(net_47) );
NAND2_X1 inst_759 ( .ZN(net_490), .A1(net_463), .A2(net_439) );
XNOR2_X1 inst_249 ( .B(net_939), .ZN(net_903), .A(net_862) );
MUX2_X2 inst_863 ( .Z(net_269), .S(net_191), .A(net_19), .B(n77) );
NAND2_X1 inst_839 ( .ZN(net_924), .A2(net_923), .A1(net_595) );
INV_X1 inst_1015 ( .ZN(net_905), .A(net_601) );
XNOR2_X1 inst_240 ( .ZN(net_928), .B(net_843), .A(net_464) );
XNOR2_X1 inst_110 ( .B(net_365), .ZN(net_359), .A(net_358) );
MUX2_X2 inst_891 ( .S(net_191), .Z(net_123), .A(net_12), .B(n2204) );
XOR2_X1 inst_74 ( .Z(net_779), .A(net_733), .B(net_627) );
XNOR2_X1 inst_288 ( .ZN(net_1022), .B(net_1009), .A(net_1000) );
XNOR2_X1 inst_229 ( .B(net_852), .A(net_571), .ZN(n385) );
NOR2_X1 inst_396 ( .A1(net_164), .ZN(net_159), .A2(net_86) );
XNOR2_X1 inst_99 ( .A(net_307), .B(net_298), .ZN(net_257) );
NAND2_X1 inst_669 ( .A2(net_191), .ZN(net_146), .A1(n41) );
NAND2_X1 inst_664 ( .A2(net_191), .ZN(net_127), .A1(n127) );
XNOR2_X1 inst_283 ( .ZN(net_1017), .A(net_1016), .B(net_990) );
OR3_X2 inst_311 ( .ZN(net_891), .A1(net_890), .A3(net_889), .A2(net_835) );
MUX2_X2 inst_917 ( .Z(net_1038), .A(net_1035), .B(net_1028), .S(net_983) );
NOR2_X1 inst_372 ( .A1(net_191), .ZN(net_97), .A2(n155) );
INV_X1 inst_988 ( .ZN(net_238), .A(net_237) );
XNOR2_X1 inst_215 ( .ZN(net_787), .A(net_718), .B(net_244) );
XNOR2_X1 inst_169 ( .ZN(net_842), .A(net_517), .B(net_462) );
NOR2_X1 inst_421 ( .ZN(net_440), .A2(net_185), .A1(n2253) );
CLKBUF_X1 inst_1092 ( .A(n289), .Z(n284) );
NAND4_X1 inst_555 ( .A3(net_986), .A4(net_937), .A2(net_876), .A1(net_818), .ZN(n246) );
NAND2_X1 inst_849 ( .ZN(net_1018), .A1(net_987), .A2(net_969) );
NAND2_X1 inst_816 ( .ZN(net_852), .A2(net_784), .A1(net_688) );
NOR2_X1 inst_431 ( .ZN(net_391), .A2(net_390), .A1(net_169) );
XOR2_X1 inst_3 ( .B(net_285), .Z(net_207), .A(net_206) );
NOR4_X1 inst_348 ( .A4(net_892), .ZN(net_812), .A1(net_758), .A3(net_757), .A2(net_649) );
CLKBUF_X1 inst_1090 ( .Z(n3), .A(n1) );
MUX2_X2 inst_889 ( .Z(net_375), .S(net_191), .A(net_1), .B(n53) );
NAND3_X1 inst_577 ( .ZN(net_618), .A1(net_617), .A3(net_604), .A2(net_384) );
NAND3_X1 inst_566 ( .ZN(net_581), .A3(net_566), .A2(net_312), .A1(net_306) );
XOR2_X1 inst_36 ( .Z(net_299), .A(net_298), .B(net_297) );
NAND2_X1 inst_656 ( .A2(net_191), .ZN(net_126), .A1(n130) );
NAND2_X1 inst_645 ( .ZN(net_77), .A2(n200), .A1(n18) );
XOR2_X1 inst_45 ( .Z(net_327), .A(net_326), .B(net_325) );
NOR2_X1 inst_503 ( .ZN(net_916), .A1(net_905), .A2(net_872) );
NOR2_X1 inst_451 ( .ZN(net_500), .A1(net_499), .A2(net_498) );
AND3_X4 inst_1108 ( .ZN(net_684), .A1(net_610), .A3(net_609), .A2(net_493) );
XNOR2_X1 inst_269 ( .A(net_1001), .ZN(net_980), .B(net_941) );
NOR2_X1 inst_458 ( .ZN(net_530), .A2(net_427), .A1(net_250) );
NOR2_X1 inst_444 ( .A1(net_1029), .ZN(net_606), .A2(net_489) );
NAND2_X1 inst_797 ( .ZN(net_688), .A2(net_679), .A1(n4526) );
AND4_X1 inst_1097 ( .A2(net_480), .ZN(net_468), .A4(net_467), .A3(net_284), .A1(net_283) );
NAND2_X1 inst_686 ( .ZN(net_317), .A2(net_139), .A1(net_45) );
NAND2_X1 inst_741 ( .ZN(net_497), .A2(net_278), .A1(net_111) );
NOR2_X1 inst_514 ( .ZN(net_1007), .A2(net_995), .A1(net_529) );
INV_X1 inst_967 ( .A(net_372), .ZN(net_235) );
NAND2_X1 inst_685 ( .ZN(net_138), .A2(net_137), .A1(net_32) );
XOR2_X1 inst_63 ( .Z(net_485), .B(net_326), .A(n4427) );
XNOR2_X1 inst_119 ( .ZN(net_442), .A(net_352), .B(n106) );
INV_X1 inst_939 ( .ZN(net_13), .A(n2239) );
NAND2_X1 inst_676 ( .A2(net_191), .ZN(net_125), .A1(n35) );
AND2_X4 inst_1118 ( .ZN(net_573), .A2(net_413), .A1(net_299) );
AND2_X4 inst_1115 ( .A2(net_568), .ZN(net_403), .A1(net_373) );
MUX2_X2 inst_874 ( .S(net_191), .Z(net_114), .B(net_26), .A(n2208) );
INV_X1 inst_1019 ( .ZN(net_1029), .A(net_724) );
INV_X1 inst_1021 ( .A(net_1020), .ZN(net_443) );
NOR2_X1 inst_473 ( .ZN(net_712), .A1(net_677), .A2(net_651) );
AND2_X4 inst_1131 ( .A1(net_673), .ZN(net_547), .A2(net_546) );
CLKBUF_X1 inst_1076 ( .Z(n480), .A(n2256) );
XNOR2_X1 inst_217 ( .ZN(net_793), .A(net_792), .B(net_791) );
NAND3_X1 inst_572 ( .A1(net_911), .ZN(net_651), .A3(net_617), .A2(net_604) );
NAND2_X1 inst_742 ( .ZN(net_426), .A2(net_271), .A1(net_112) );
NAND2_X1 inst_691 ( .ZN(net_298), .A2(net_142), .A1(net_36) );
AND3_X4 inst_1101 ( .ZN(net_519), .A3(net_518), .A2(net_480), .A1(net_407) );
NOR2_X1 inst_427 ( .ZN(net_250), .A2(net_175), .A1(n3723) );
XNOR2_X1 inst_257 ( .A(net_963), .ZN(net_940), .B(net_902) );
NOR2_X1 inst_485 ( .ZN(net_783), .A2(net_782), .A1(net_758) );
NAND2_X1 inst_770 ( .ZN(net_657), .A1(net_531), .A2(net_437) );
NAND3_X1 inst_565 ( .ZN(net_577), .A3(net_576), .A1(net_259), .A2(net_258) );
MUX2_X2 inst_861 ( .Z(net_315), .S(net_191), .B(net_17), .A(n2230) );
NAND2_X1 inst_672 ( .A2(net_191), .ZN(net_150), .A1(n147) );
XNOR2_X1 inst_138 ( .ZN(net_724), .A(net_342), .B(n2230) );
NAND2_X1 inst_622 ( .ZN(net_54), .A2(n234), .A1(n18) );
NOR2_X1 inst_409 ( .ZN(net_512), .A2(net_234), .A1(n3729) );
MUX2_X2 inst_899 ( .Z(net_944), .A(net_943), .B(net_942), .S(net_760) );
XOR2_X1 inst_33 ( .Z(net_291), .A(net_290), .B(net_289) );
NAND2_X1 inst_703 ( .ZN(net_321), .A2(net_151), .A1(net_67) );
OR2_X4 inst_312 ( .A1(net_191), .ZN(net_93), .A2(n3701) );
NAND2_X1 inst_660 ( .A2(net_191), .ZN(net_142), .A1(n97) );
INV_X1 inst_977 ( .A(net_326), .ZN(net_179) );
NOR2_X1 inst_517 ( .ZN(net_1023), .A2(net_1008), .A1(net_840) );
OR3_X4 inst_309 ( .ZN(net_895), .A1(net_894), .A2(net_893), .A3(net_892) );
XNOR2_X1 inst_232 ( .ZN(net_857), .A(net_856), .B(net_798) );
NOR4_X1 inst_347 ( .ZN(net_987), .A2(net_694), .A1(net_558), .A4(net_505), .A3(net_249) );
NAND2_X1 inst_768 ( .A1(net_435), .ZN(net_429), .A2(net_428) );
NAND2_X1 inst_663 ( .A2(net_191), .ZN(net_155), .A1(n26) );
XNOR2_X1 inst_297 ( .ZN(net_1035), .B(net_1027), .A(net_1022) );
NAND2_X1 inst_755 ( .ZN(net_1020), .A2(net_233), .A1(net_121) );
CLKBUF_X1 inst_1067 ( .Z(n522), .A(n4394) );
OR3_X2 inst_310 ( .ZN(net_410), .A1(net_409), .A2(net_335), .A3(net_315) );
INV_X1 inst_1043 ( .A(net_847), .ZN(net_834) );
XNOR2_X1 inst_253 ( .ZN(net_918), .B(net_905), .A(net_887) );
INV_X1 inst_971 ( .A(net_368), .ZN(net_242) );
XNOR2_X1 inst_162 ( .ZN(net_458), .B(net_371), .A(net_207) );
NAND3_X1 inst_589 ( .ZN(net_861), .A1(net_725), .A3(net_554), .A2(net_499) );
NAND2_X1 inst_794 ( .ZN(net_768), .A1(net_709), .A2(net_678) );
INV_X1 inst_1005 ( .ZN(net_511), .A(net_387) );
NAND2_X1 inst_602 ( .ZN(net_35), .A2(n231), .A1(n18) );
XOR2_X1 inst_59 ( .Z(net_400), .A(net_363), .B(net_362) );
XNOR2_X1 inst_135 ( .ZN(net_414), .A(net_274), .B(n3711) );
INV_X1 inst_996 ( .A(net_989), .ZN(net_503) );
XOR2_X1 inst_37 ( .Z(net_469), .B(net_310), .A(net_300) );
AND4_X1 inst_1098 ( .ZN(net_698), .A4(net_563), .A3(net_472), .A1(net_237), .A2(net_188) );
NAND2_X1 inst_740 ( .ZN(net_501), .A2(net_261), .A1(net_113) );
XNOR2_X1 inst_264 ( .ZN(net_964), .A(net_963), .B(net_918) );
XOR2_X1 inst_84 ( .B(net_963), .A(net_917), .Z(n368) );
INV_X1 inst_924 ( .ZN(net_3), .A(n2230) );
OR4_X1 inst_303 ( .ZN(net_836), .A2(net_835), .A4(net_823), .A1(net_756), .A3(net_755) );
XNOR2_X1 inst_173 ( .ZN(net_588), .B(net_397), .A(net_219) );
NAND2_X1 inst_723 ( .ZN(net_304), .A2(net_161), .A1(net_52) );
XNOR2_X1 inst_224 ( .ZN(net_838), .A(net_787), .B(net_626) );
NAND2_X1 inst_611 ( .ZN(net_44), .A2(n195), .A1(n18) );
XNOR2_X1 inst_287 ( .B(net_1031), .ZN(net_1021), .A(net_1006) );
NOR2_X1 inst_426 ( .ZN(net_590), .A2(net_181), .A1(n3705) );
NAND2_X1 inst_618 ( .ZN(net_51), .A2(n221), .A1(n18) );
NAND2_X1 inst_648 ( .ZN(net_79), .A2(n191), .A1(n18) );
CLKBUF_X1 inst_1088 ( .A(n469), .Z(n422) );
XNOR2_X1 inst_270 ( .B(net_971), .A(net_882), .ZN(n324) );
NOR2_X1 inst_474 ( .A2(net_729), .ZN(net_683), .A1(net_523) );
XOR2_X1 inst_26 ( .Z(net_279), .A(net_278), .B(net_277) );
NAND2_X1 inst_766 ( .A1(net_433), .ZN(net_423), .A2(net_422) );
NOR2_X1 inst_490 ( .ZN(net_815), .A1(net_814), .A2(net_765) );
INV_X1 inst_984 ( .A(net_329), .ZN(net_184) );
NAND2_X1 inst_801 ( .ZN(net_693), .A1(net_692), .A2(net_629) );
NAND2_X1 inst_626 ( .ZN(net_58), .A2(n193), .A1(n18) );
NAND2_X1 inst_692 ( .ZN(net_262), .A2(net_143), .A1(net_63) );
XOR2_X1 inst_70 ( .B(net_464), .A(net_462), .Z(net_459) );
XNOR2_X1 inst_129 ( .ZN(net_388), .A(net_368), .B(n2239) );
MUX2_X2 inst_870 ( .Z(net_301), .S(net_191), .A(net_21), .B(n55) );
XOR2_X1 inst_11 ( .B(net_364), .A(net_354), .Z(net_219) );
NAND2_X1 inst_631 ( .ZN(net_63), .A2(n223), .A1(n18) );
CLKBUF_X1 inst_1056 ( .Z(n544), .A(n3749) );
XNOR2_X1 inst_188 ( .ZN(net_704), .B(net_641), .A(net_447) );
NOR2_X1 inst_441 ( .ZN(net_488), .A2(net_418), .A1(net_385) );
NAND2_X1 inst_798 ( .ZN(net_689), .A2(net_632), .A1(net_623) );
NAND2_X1 inst_808 ( .ZN(net_719), .A2(net_650), .A1(n89) );
NAND3_X1 inst_557 ( .A1(net_572), .ZN(net_408), .A2(net_310), .A3(net_300) );
NAND2_X1 inst_777 ( .A1(net_747), .ZN(net_656), .A2(net_548) );
NOR2_X1 inst_398 ( .ZN(net_345), .A1(net_164), .A2(net_87) );
AND2_X4 inst_1128 ( .ZN(net_528), .A2(net_527), .A1(net_463) );
NOR2_X1 inst_436 ( .A1(net_1004), .A2(net_967), .ZN(net_611) );
INV_X1 inst_1037 ( .ZN(net_784), .A(net_761) );
NAND2_X1 inst_823 ( .ZN(net_817), .A2(net_759), .A1(net_698) );
INV_X1 inst_933 ( .ZN(net_9), .A(n2218) );
XNOR2_X1 inst_300 ( .B(net_1037), .A(net_978), .ZN(n338) );
XNOR2_X1 inst_102 ( .A(net_335), .ZN(net_316), .B(net_315) );
INV_X1 inst_1013 ( .A(net_673), .ZN(net_570) );
NOR2_X1 inst_446 ( .A2(net_1009), .A1(net_963), .ZN(net_548) );
NOR2_X1 inst_364 ( .A1(net_191), .ZN(net_88), .A2(n156) );
XNOR2_X1 inst_144 ( .ZN(net_395), .B(net_215), .A(net_213) );
XNOR2_X1 inst_195 ( .ZN(net_734), .B(net_733), .A(net_731) );
NAND2_X1 inst_824 ( .ZN(net_820), .A2(net_819), .A1(net_709) );
NOR2_X1 inst_411 ( .ZN(net_747), .A2(net_236), .A1(n4394) );
XNOR2_X1 inst_124 ( .ZN(net_911), .A(net_372), .B(n1462) );
MUX2_X2 inst_880 ( .Z(net_361), .S(net_191), .A(net_7), .B(n86) );
NAND2_X1 inst_680 ( .ZN(net_376), .A2(net_126), .A1(net_65) );
NAND2_X1 inst_785 ( .ZN(net_634), .A2(net_620), .A1(net_619) );
NAND2_X1 inst_737 ( .A1(net_336), .A2(net_220), .ZN(net_198) );
INV_X1 inst_961 ( .ZN(net_109), .A(n3711) );
MUX2_X2 inst_876 ( .Z(net_305), .S(net_191), .A(net_6), .B(n61) );
NAND4_X1 inst_545 ( .ZN(net_759), .A4(net_700), .A1(net_583), .A2(net_582), .A3(net_410) );
NOR2_X1 inst_399 ( .ZN(net_338), .A1(net_164), .A2(net_99) );
NAND4_X1 inst_527 ( .ZN(net_565), .A1(net_416), .A4(net_413), .A3(net_298), .A2(net_297) );
XNOR2_X1 inst_226 ( .ZN(net_841), .A(net_840), .B(net_777) );
NOR2_X1 inst_414 ( .ZN(net_464), .A2(net_242), .A1(n2239) );
XOR2_X1 inst_61 ( .A(net_373), .Z(net_370), .B(net_158) );
XNOR2_X1 inst_203 ( .ZN(net_748), .A(net_747), .B(net_746) );
NAND4_X1 inst_531 ( .ZN(net_579), .A4(net_578), .A1(net_561), .A2(net_281), .A3(net_280) );
NAND3_X1 inst_562 ( .ZN(net_482), .A3(net_412), .A2(net_302), .A1(net_301) );
XNOR2_X1 inst_212 ( .ZN(net_775), .B(net_727), .A(net_692) );
AND2_X4 inst_1139 ( .ZN(net_763), .A1(net_762), .A2(net_761) );
NOR2_X1 inst_499 ( .A2(net_904), .A1(net_889), .ZN(net_885) );
OR2_X4 inst_335 ( .ZN(net_901), .A2(net_894), .A1(net_892) );
NAND2_X1 inst_674 ( .A2(net_191), .ZN(net_143), .A1(n47) );
NOR2_X1 inst_466 ( .ZN(net_662), .A2(net_549), .A1(net_433) );
NAND2_X1 inst_658 ( .A2(net_191), .ZN(net_153), .A1(n118) );
INV_X1 inst_989 ( .ZN(net_404), .A(net_309) );
NOR2_X1 inst_456 ( .A1(net_1016), .ZN(net_523), .A2(net_522) );
NAND2_X1 inst_832 ( .A2(net_898), .ZN(net_897), .A1(net_591) );
XNOR2_X1 inst_275 ( .ZN(net_1000), .A(net_999), .B(net_964) );
XNOR2_X1 inst_117 ( .ZN(net_437), .A(net_317), .B(n2224) );
MUX2_X2 inst_858 ( .Z(net_354), .S(net_191), .A(net_108), .B(n87) );
NOR2_X1 inst_438 ( .ZN(net_549), .A1(net_486), .A2(net_485) );
AND2_X4 inst_1109 ( .ZN(net_335), .A2(net_160), .A1(net_30) );
NOR2_X1 inst_501 ( .ZN(net_896), .A2(net_868), .A1(net_670) );
NAND3_X1 inst_587 ( .ZN(net_865), .A3(net_695), .A1(net_431), .A2(net_201) );
CLKBUF_X1 inst_1081 ( .Z(n446), .A(n106) );
XNOR2_X1 inst_154 ( .ZN(net_448), .A(net_344), .B(net_334) );
NAND2_X1 inst_666 ( .A2(net_191), .ZN(net_161), .A1(n50) );
OR2_X4 inst_324 ( .A1(net_733), .A2(net_524), .ZN(net_521) );
NOR2_X1 inst_465 ( .ZN(net_797), .A1(net_556), .A2(net_495) );
XOR2_X1 inst_54 ( .Z(net_353), .A(net_352), .B(net_351) );
XNOR2_X1 inst_109 ( .ZN(net_409), .A(net_336), .B(net_220) );
NAND3_X1 inst_570 ( .A2(net_724), .ZN(net_647), .A1(net_615), .A3(net_595) );
NAND2_X1 inst_640 ( .ZN(net_72), .A2(n204), .A1(n18) );
XOR2_X1 inst_43 ( .A(net_379), .Z(net_313), .B(net_312) );
XNOR2_X1 inst_94 ( .ZN(net_229), .A(net_228), .B(net_119) );
AND2_X4 inst_1114 ( .A2(net_422), .ZN(net_402), .A1(net_401) );
NOR2_X1 inst_454 ( .A2(net_1012), .ZN(net_551), .A1(net_489) );
NOR2_X1 inst_375 ( .A1(net_191), .ZN(net_100), .A2(n168) );
INV_X1 inst_942 ( .ZN(net_128), .A(n38) );
MUX2_X2 inst_904 ( .S(net_962), .A(net_803), .B(net_800), .Z(n350) );
XNOR2_X1 inst_262 ( .B(net_1009), .A(net_908), .ZN(n365) );
XNOR2_X1 inst_243 ( .ZN(net_888), .A(net_838), .B(net_790) );
XNOR2_X1 inst_285 ( .A(net_996), .B(net_956), .ZN(n336) );
NOR2_X1 inst_424 ( .ZN(net_560), .A2(net_173), .A1(n1469) );
NAND3_X1 inst_591 ( .A1(net_931), .ZN(net_929), .A3(net_928), .A2(net_822) );
NOR2_X1 inst_497 ( .ZN(net_868), .A1(net_832), .A2(net_831) );
XOR2_X1 inst_15 ( .Z(net_251), .B(net_224), .A(net_133) );
NAND2_X1 inst_757 ( .ZN(net_630), .A1(net_406), .A2(net_404) );
OR2_X2 inst_343 ( .A2(net_938), .A1(net_848), .ZN(n252) );
INV_X1 inst_1035 ( .ZN(net_711), .A(net_710) );
AND3_X4 inst_1106 ( .A2(net_911), .ZN(net_605), .A3(net_604), .A1(net_442) );
OR2_X4 inst_337 ( .ZN(net_937), .A2(net_936), .A1(net_845) );
NAND4_X1 inst_543 ( .ZN(net_742), .A2(net_593), .A4(net_589), .A3(net_585), .A1(net_466) );
INV_X1 inst_929 ( .ZN(net_5), .A(n3723) );
INV_X1 inst_982 ( .A(net_328), .ZN(net_234) );
CLKBUF_X1 inst_1078 ( .Z(n453), .A(n1) );
NAND2_X1 inst_670 ( .A2(net_191), .ZN(net_132), .A1(n44) );
XNOR2_X1 inst_299 ( .B(net_1036), .A(net_982), .ZN(n399) );
INV_X1 inst_1034 ( .ZN(net_835), .A(net_708) );
NOR2_X1 inst_476 ( .A2(net_746), .ZN(net_715), .A1(net_542) );
NOR2_X1 inst_418 ( .ZN(net_246), .A2(net_170), .A1(n4437) );
MUX2_X2 inst_864 ( .Z(net_211), .S(net_191), .A(net_25), .B(n80) );
XOR2_X1 inst_86 ( .B(net_999), .A(net_976), .Z(n359) );
INV_X1 inst_949 ( .ZN(net_19), .A(n4394) );
XOR2_X1 inst_20 ( .Z(net_572), .B(net_264), .A(net_211) );
NAND2_X1 inst_613 ( .ZN(net_46), .A2(n18), .A1(n151) );
INV_X1 inst_1039 ( .A(net_889), .ZN(net_744) );
NAND2_X1 inst_714 ( .ZN(net_326), .A2(net_147), .A1(net_51) );
NOR4_X1 inst_349 ( .ZN(net_904), .A1(net_810), .A2(net_721), .A4(net_402), .A3(net_246) );
NOR2_X1 inst_483 ( .ZN(net_773), .A2(net_772), .A1(net_687) );
NAND3_X1 inst_576 ( .A2(net_751), .ZN(net_616), .A1(net_615), .A3(net_606) );
XNOR2_X1 inst_259 ( .A(net_939), .B(net_923), .ZN(n295) );
INV_X1 inst_1046 ( .A(net_923), .ZN(net_909) );
XNOR2_X1 inst_246 ( .B(net_905), .ZN(net_902), .A(net_857) );
INV_X1 inst_1020 ( .ZN(net_749), .A(net_422) );
CLKBUF_X1 inst_1061 ( .Z(n534), .A(n4410) );
NAND2_X1 inst_635 ( .ZN(net_67), .A2(n180), .A1(n18) );
NAND2_X1 inst_807 ( .ZN(net_717), .A2(net_716), .A1(net_520) );
NAND2_X1 inst_705 ( .ZN(net_333), .A2(net_150), .A1(net_46) );
XOR2_X1 inst_72 ( .Z(net_791), .B(net_571), .A(net_511) );
MUX2_X2 inst_911 ( .S(net_997), .B(net_884), .A(net_778), .Z(n298) );
INV_X1 inst_976 ( .A(net_349), .ZN(net_178) );
NAND4_X1 inst_519 ( .ZN(n406), .A4(n230), .A3(n218), .A1(n210), .A2(n152) );
MUX2_X2 inst_909 ( .S(net_997), .B(net_461), .A(net_459), .Z(n304) );
INV_X1 inst_1003 ( .ZN(net_726), .A(net_439) );
NAND3_X1 inst_582 ( .A1(net_696), .ZN(net_625), .A3(net_617), .A2(net_560) );
CLKBUF_X1 inst_1096 ( .Z(n2), .A(n1) );
NAND2_X1 inst_683 ( .ZN(net_133), .A2(net_132), .A1(net_49) );
NAND2_X1 inst_735 ( .A1(net_286), .A2(net_214), .ZN(net_195) );
CLKBUF_X1 inst_1053 ( .Z(n550), .A(n3729) );
XNOR2_X1 inst_115 ( .ZN(net_965), .A(net_318), .B(n2218) );
XNOR2_X1 inst_210 ( .ZN(net_853), .B(net_745), .A(net_714) );
MUX2_X2 inst_894 ( .S(net_852), .A(net_795), .B(net_792), .Z(n379) );
INV_X1 inst_994 ( .A(net_567), .ZN(net_385) );
NAND2_X1 inst_761 ( .ZN(net_525), .A2(net_428), .A1(net_387) );
XNOR2_X1 inst_239 ( .ZN(net_883), .B(net_882), .A(net_841) );
XNOR2_X1 inst_175 ( .ZN(net_635), .B(net_507), .A(net_255) );
NAND3_X1 inst_593 ( .ZN(net_933), .A1(net_914), .A3(net_901), .A2(net_816) );
NAND2_X1 inst_725 ( .ZN(net_224), .A2(net_146), .A1(net_61) );
NAND2_X1 inst_747 ( .ZN(net_499), .A2(net_342), .A1(net_3) );
NAND2_X1 inst_843 ( .ZN(net_958), .A2(net_933), .A1(net_669) );
NAND2_X1 inst_601 ( .ZN(net_34), .A2(n18), .A1(n161) );
XNOR2_X1 inst_133 ( .ZN(net_722), .A(net_261), .B(n4410) );
XNOR2_X1 inst_112 ( .ZN(net_415), .A(net_275), .B(n3705) );
MUX2_X2 inst_916 ( .Z(net_1037), .A(net_1033), .B(net_1021), .S(net_977) );
NAND2_X1 inst_764 ( .A2(net_965), .A1(net_603), .ZN(net_492) );
NOR2_X1 inst_479 ( .ZN(net_782), .A2(net_699), .A1(net_468) );
OR4_X1 inst_305 ( .A4(net_851), .ZN(n418), .A3(n410), .A2(n408), .A1(n406) );
AND2_X4 inst_1111 ( .A1(net_338), .A2(net_202), .ZN(net_187) );
XOR2_X1 inst_29 ( .Z(net_578), .A(net_284), .B(net_283) );
NAND2_X1 inst_771 ( .ZN(net_619), .A1(net_560), .A2(net_442) );
MUX2_X2 inst_878 ( .Z(net_199), .S(net_191), .A(net_13), .B(n63) );
XNOR2_X1 inst_126 ( .ZN(net_623), .A(net_271), .B(n3717) );
NOR2_X1 inst_480 ( .A2(net_761), .ZN(net_760), .A1(net_735) );
NAND4_X1 inst_538 ( .ZN(net_832), .A2(net_580), .A4(net_577), .A3(net_482), .A1(net_189) );
NAND3_X1 inst_564 ( .ZN(net_814), .A3(net_566), .A2(net_424), .A1(net_380) );
NAND2_X1 inst_646 ( .ZN(net_120), .A1(n4528), .A2(n1496) );
INV_X1 inst_963 ( .ZN(net_29), .A(n4427) );
AND2_X4 inst_1140 ( .ZN(net_831), .A2(net_786), .A1(net_600) );
NOR2_X1 inst_382 ( .A1(net_191), .ZN(net_106), .A2(n176) );
XOR2_X1 inst_35 ( .Z(net_296), .B(net_295), .A(net_152) );
NAND2_X1 inst_739 ( .ZN(net_493), .A2(net_274), .A1(net_109) );
INV_X1 inst_948 ( .ZN(net_117), .A(n2224) );
CLKBUF_X1 inst_1086 ( .Z(n436), .A(n1462) );
NOR2_X1 inst_358 ( .A1(net_191), .ZN(net_82), .A2(n209) );
XOR2_X1 inst_48 ( .B(net_362), .Z(net_339), .A(net_338) );
MUX2_X2 inst_907 ( .Z(net_982), .A(net_945), .B(net_944), .S(n4526) );
XOR2_X1 inst_46 ( .Z(net_330), .A(net_329), .B(net_328) );
INV_X1 inst_934 ( .ZN(net_10), .A(n114) );
INV_X1 inst_922 ( .ZN(net_1), .A(n3729) );
INV_X1 inst_1000 ( .A(net_485), .ZN(net_386) );
AND2_X4 inst_1126 ( .A1(net_533), .A2(net_463), .ZN(net_438) );
NOR2_X1 inst_443 ( .A1(net_1025), .A2(net_925), .ZN(net_598) );
NAND2_X1 inst_796 ( .ZN(net_682), .A2(net_681), .A1(net_521) );
NAND2_X1 inst_633 ( .ZN(net_65), .A2(n203), .A1(n18) );
NAND4_X1 inst_524 ( .A4(net_572), .ZN(net_470), .A2(net_469), .A3(net_308), .A1(net_307) );
NAND2_X1 inst_655 ( .A2(net_191), .ZN(net_137), .A1(n115) );
XNOR2_X1 inst_104 ( .ZN(net_322), .A(net_321), .B(net_320) );
NOR2_X1 inst_448 ( .A1(net_1009), .A2(net_999), .ZN(net_613) );
CLKBUF_X1 inst_1049 ( .Z(n558), .A(n3705) );
XNOR2_X1 inst_168 ( .ZN(net_515), .A(net_514), .B(net_511) );
MUX2_X2 inst_914 ( .A(net_1020), .B(net_1019), .S(net_1018), .Z(n273) );
NAND2_X1 inst_695 ( .ZN(net_278), .A2(net_145), .A1(net_66) );
NAND2_X1 inst_730 ( .A1(net_265), .A2(net_209), .ZN(net_189) );
NOR2_X1 inst_384 ( .ZN(net_368), .A1(net_164), .A2(net_88) );
NAND2_X1 inst_727 ( .ZN(net_331), .A2(net_153), .A1(net_42) );
MUX2_X2 inst_873 ( .Z(net_202), .S(net_191), .A(net_18), .B(n110) );
OR2_X4 inst_321 ( .A2(net_1025), .ZN(net_494), .A1(net_493) );
NAND2_X1 inst_653 ( .A2(net_191), .ZN(net_165), .A1(n124) );
INV_X1 inst_991 ( .A(net_747), .ZN(net_383) );
NAND2_X1 inst_608 ( .ZN(net_41), .A2(n197), .A1(n18) );
NAND2_X1 inst_834 ( .ZN(net_923), .A1(net_904), .A2(net_878) );
MUX2_X2 inst_882 ( .Z(net_266), .S(net_191), .A(net_28), .B(n65) );
XNOR2_X1 inst_170 ( .ZN(net_828), .A(net_536), .B(net_535) );
NAND3_X1 inst_580 ( .A1(net_724), .ZN(net_622), .A3(net_615), .A2(net_531) );
INV_X1 inst_966 ( .A(net_343), .ZN(net_171) );
NOR2_X1 inst_511 ( .ZN(net_975), .A2(net_974), .A1(net_751) );
XOR2_X1 inst_41 ( .Z(net_424), .B(net_312), .A(net_306) );
XNOR2_X1 inst_199 ( .ZN(net_739), .B(net_638), .A(net_253) );
NAND2_X1 inst_708 ( .ZN(net_274), .A2(net_155), .A1(net_50) );
XNOR2_X1 inst_152 ( .ZN(net_446), .B(net_332), .A(net_263) );
INV_X1 inst_953 ( .ZN(net_96), .A(n4528) );
CLKBUF_X1 inst_1071 ( .Z(n490), .A(n2230) );
AND4_X1 inst_1099 ( .ZN(net_669), .A1(net_569), .A2(net_568), .A4(net_567), .A3(net_225) );
NOR2_X1 inst_468 ( .ZN(net_776), .A1(net_560), .A2(net_496) );
INV_X1 inst_1011 ( .ZN(net_999), .A(net_389) );
NOR2_X1 inst_429 ( .ZN(net_430), .A2(net_176), .A1(n3743) );
NAND4_X1 inst_540 ( .ZN(net_892), .A4(net_698), .A2(net_645), .A3(net_644), .A1(net_268) );
NOR2_X1 inst_404 ( .ZN(net_348), .A1(net_164), .A2(net_94) );
INV_X1 inst_998 ( .ZN(net_1012), .A(net_437) );
XNOR2_X1 inst_89 ( .ZN(net_231), .A(net_120), .B(n38) );
NOR2_X1 inst_388 ( .A1(net_164), .ZN(net_134), .A2(net_105) );
XOR2_X1 inst_66 ( .Z(net_963), .B(net_277), .A(n4400) );
XOR2_X1 inst_7 ( .A(net_378), .B(net_306), .Z(net_213) );
NOR2_X1 inst_392 ( .ZN(net_352), .A1(net_164), .A2(net_90) );
XNOR2_X1 inst_182 ( .ZN(net_642), .B(net_448), .A(net_319) );
XNOR2_X1 inst_273 ( .B(net_997), .A(net_517), .ZN(n307) );
XNOR2_X1 inst_120 ( .ZN(net_428), .A(net_293), .B(n3749) );
XNOR2_X1 inst_294 ( .ZN(net_1032), .B(net_1025), .A(net_1015) );
NAND2_X1 inst_788 ( .ZN(net_663), .A2(net_662), .A1(net_419) );
NOR2_X1 inst_489 ( .A2(net_907), .ZN(net_810), .A1(net_676) );
INV_X1 inst_931 ( .ZN(net_7), .A(n2247) );
XNOR2_X1 inst_192 ( .ZN(net_727), .B(net_684), .A(net_630) );
NOR2_X1 inst_366 ( .A1(net_191), .ZN(net_90), .A2(n215) );
CLKBUF_X1 inst_1083 ( .Z(n442), .A(n1486) );
NAND3_X1 inst_567 ( .A3(net_645), .ZN(net_583), .A1(net_320), .A2(net_314) );
XNOR2_X1 inst_149 ( .ZN(net_407), .B(net_390), .A(net_168) );
XNOR2_X1 inst_193 ( .ZN(net_730), .A(net_729), .B(net_728) );
OR2_X4 inst_318 ( .A1(net_596), .A2(net_485), .ZN(net_419) );
NAND2_X1 inst_810 ( .ZN(net_725), .A1(net_724), .A2(net_667) );
AND2_X4 inst_1136 ( .A1(net_762), .ZN(net_753), .A2(net_679) );
XOR2_X1 inst_39 ( .Z(net_417), .A(net_305), .B(net_304) );
XNOR2_X1 inst_230 ( .ZN(net_854), .B(net_853), .A(net_793) );
MUX2_X2 inst_856 ( .Z(net_297), .S(net_191), .A(net_0), .B(n78) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, D, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_FUNCTIONAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_16_V
`define SKY130_FD_SC_LP__CLKINV_16_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_16_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
// Module ports
output Q ;
output Q_N ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_BEHAVIORAL_V
|
/*
###############################################################
# Generated by: Cadence Encounter 13.13-s017_1
# OS: Linux x86_64(Host ID microelnsys)
# Generated on: Wed Sep 14 17:42:50 2016
# Design: DLX
# Command: saveNetlist DLX.v
###############################################################
*/
module mmu_out_dram (
data_ram,
mem_op,
nibble,
unaligned,
data_read);
input [31:0] data_ram;
input [5:0] mem_op;
input [1:0] nibble;
input unaligned;
output [31:0] data_read;
endmodule
module mmu_in_dram (
mem_op,
aligned_address,
data,
unaligned,
nibble,
write_op,
read_op,
mem_address,
mem_data,
write_byte);
input [5:0] mem_op;
input [31:0] aligned_address;
input [31:0] data;
output unaligned;
output [1:0] nibble;
output write_op;
output read_op;
output [31:0] mem_address;
output [31:0] mem_data;
output write_byte;
// Internal wires
wire FE_OFN6_n21;
wire n10;
wire n12;
wire n13;
wire n14;
wire n15;
wire n16;
wire n17;
wire n18;
wire n19;
wire n20;
wire n21;
wire n22;
wire n23;
wire n24;
wire n25;
wire n26;
wire n27;
wire n28;
wire n29;
wire n30;
wire n31;
wire n32;
assign mem_address[31] = 1'b0 ;
assign mem_address[30] = 1'b0 ;
CLKBUF_X1 FE_OFC6_n21 (.Z(FE_OFN6_n21),
.A(n21));
NAND2_X1 U6 (.ZN(n24),
.A2(n20),
.A1(n12));
NOR2_X1 U7 (.ZN(nibble[0]),
.A2(n13),
.A1(n20));
AND3_X1 U8 (.ZN(n20),
.A3(n15),
.A2(n23),
.A1(n16));
AND2_X1 U9 (.ZN(n12),
.A2(n17),
.A1(n10));
AND2_X1 U10 (.ZN(n10),
.A2(n22),
.A1(n18));
OR2_X1 U11 (.ZN(write_op),
.A2(FE_OFN6_n21),
.A1(write_byte));
INV_X1 U14 (.ZN(write_byte),
.A(n23));
NOR3_X1 U15 (.ZN(n25),
.A3(mem_op[0]),
.A2(mem_op[2]),
.A1(mem_op[1]));
NOR3_X1 U16 (.ZN(n29),
.A3(mem_op[3]),
.A2(mem_op[5]),
.A1(mem_op[4]));
NAND4_X1 U19 (.ZN(n17),
.A4(n31),
.A3(n32),
.A2(n29),
.A1(mem_op[1]));
NAND4_X1 U20 (.ZN(n16),
.A4(n31),
.A3(n30),
.A2(n29),
.A1(mem_op[0]));
NAND4_X1 U21 (.ZN(n15),
.A4(n27),
.A3(n26),
.A2(n25),
.A1(mem_op[3]));
NAND4_X1 U22 (.ZN(n18),
.A4(n30),
.A3(n32),
.A2(n29),
.A1(mem_op[2]));
NAND4_X1 U23 (.ZN(n22),
.A4(n27),
.A3(n28),
.A2(n25),
.A1(mem_op[4]));
NAND4_X1 U24 (.ZN(n23),
.A4(n26),
.A3(n28),
.A2(n25),
.A1(mem_op[5]));
AND2_X1 U25 (.ZN(nibble[1]),
.A2(aligned_address[1]),
.A1(n19));
OAI21_X1 U26 (.ZN(n19),
.B2(aligned_address[0]),
.B1(n17),
.A(n20));
INV_X1 U27 (.ZN(n28),
.A(mem_op[3]));
INV_X1 U28 (.ZN(n32),
.A(mem_op[0]));
INV_X1 U29 (.ZN(n31),
.A(mem_op[2]));
INV_X1 U30 (.ZN(n30),
.A(mem_op[1]));
INV_X1 U31 (.ZN(n13),
.A(aligned_address[0]));
INV_X1 U32 (.ZN(n27),
.A(mem_op[5]));
INV_X1 U33 (.ZN(n26),
.A(mem_op[4]));
NOR3_X1 U34 (.ZN(n21),
.A3(n22),
.A2(aligned_address[1]),
.A1(aligned_address[0]));
NAND4_X1 U35 (.ZN(read_op),
.A4(n17),
.A3(n16),
.A2(n15),
.A1(n14));
OR3_X1 U36 (.ZN(n14),
.A3(n18),
.A2(aligned_address[1]),
.A1(aligned_address[0]));
AND2_X1 U37 (.ZN(mem_data[0]),
.A2(write_op),
.A1(data[0]));
AND2_X1 U38 (.ZN(mem_data[1]),
.A2(write_op),
.A1(data[1]));
AND2_X1 U39 (.ZN(mem_data[2]),
.A2(write_op),
.A1(data[2]));
AND2_X1 U40 (.ZN(mem_data[3]),
.A2(write_op),
.A1(data[3]));
AND2_X1 U41 (.ZN(mem_data[4]),
.A2(write_op),
.A1(data[4]));
AND2_X1 U42 (.ZN(mem_data[5]),
.A2(write_op),
.A1(data[5]));
AND2_X1 U43 (.ZN(mem_data[6]),
.A2(write_op),
.A1(data[6]));
AND2_X1 U44 (.ZN(mem_data[7]),
.A2(write_op),
.A1(data[7]));
AND2_X1 U45 (.ZN(mem_data[8]),
.A2(FE_OFN6_n21),
.A1(data[8]));
AND2_X1 U46 (.ZN(mem_data[9]),
.A2(FE_OFN6_n21),
.A1(data[9]));
AND2_X1 U47 (.ZN(mem_data[10]),
.A2(FE_OFN6_n21),
.A1(data[10]));
AND2_X1 U48 (.ZN(mem_data[11]),
.A2(FE_OFN6_n21),
.A1(data[11]));
AND2_X1 U49 (.ZN(mem_data[12]),
.A2(FE_OFN6_n21),
.A1(data[12]));
AND2_X1 U50 (.ZN(mem_data[13]),
.A2(FE_OFN6_n21),
.A1(data[13]));
AND2_X1 U51 (.ZN(mem_data[14]),
.A2(FE_OFN6_n21),
.A1(data[14]));
AND2_X1 U52 (.ZN(mem_data[15]),
.A2(FE_OFN6_n21),
.A1(data[15]));
AND2_X1 U53 (.ZN(mem_data[16]),
.A2(FE_OFN6_n21),
.A1(data[16]));
AND2_X1 U54 (.ZN(mem_data[17]),
.A2(FE_OFN6_n21),
.A1(data[17]));
AND2_X1 U55 (.ZN(mem_data[18]),
.A2(FE_OFN6_n21),
.A1(data[18]));
AND2_X1 U56 (.ZN(mem_data[19]),
.A2(FE_OFN6_n21),
.A1(data[19]));
AND2_X1 U57 (.ZN(mem_data[20]),
.A2(FE_OFN6_n21),
.A1(data[20]));
AND2_X1 U58 (.ZN(mem_data[21]),
.A2(FE_OFN6_n21),
.A1(data[21]));
AND2_X1 U59 (.ZN(mem_data[22]),
.A2(FE_OFN6_n21),
.A1(data[22]));
AND2_X1 U60 (.ZN(mem_data[23]),
.A2(FE_OFN6_n21),
.A1(data[23]));
AND2_X1 U61 (.ZN(mem_data[24]),
.A2(FE_OFN6_n21),
.A1(data[24]));
AND2_X1 U62 (.ZN(mem_data[25]),
.A2(FE_OFN6_n21),
.A1(data[25]));
AND2_X1 U63 (.ZN(mem_data[26]),
.A2(FE_OFN6_n21),
.A1(data[26]));
AND2_X1 U64 (.ZN(mem_data[27]),
.A2(FE_OFN6_n21),
.A1(data[27]));
AND2_X1 U65 (.ZN(mem_data[28]),
.A2(FE_OFN6_n21),
.A1(data[28]));
AND2_X1 U66 (.ZN(mem_data[29]),
.A2(FE_OFN6_n21),
.A1(data[29]));
AND2_X1 U67 (.ZN(mem_data[30]),
.A2(FE_OFN6_n21),
.A1(data[30]));
AND2_X1 U68 (.ZN(mem_data[31]),
.A2(FE_OFN6_n21),
.A1(data[31]));
AND2_X1 U69 (.ZN(mem_address[1]),
.A2(n24),
.A1(aligned_address[3]));
AND2_X1 U70 (.ZN(mem_address[2]),
.A2(n24),
.A1(aligned_address[4]));
AND2_X1 U71 (.ZN(mem_address[3]),
.A2(n24),
.A1(aligned_address[5]));
AND2_X1 U72 (.ZN(mem_address[4]),
.A2(n24),
.A1(aligned_address[6]));
AND2_X1 U73 (.ZN(mem_address[5]),
.A2(n24),
.A1(aligned_address[7]));
AND2_X1 U74 (.ZN(mem_address[6]),
.A2(n24),
.A1(aligned_address[8]));
AND2_X1 U75 (.ZN(mem_address[7]),
.A2(n24),
.A1(aligned_address[9]));
AND2_X1 U76 (.ZN(mem_address[8]),
.A2(n24),
.A1(aligned_address[10]));
AND2_X1 U77 (.ZN(mem_address[9]),
.A2(n24),
.A1(aligned_address[11]));
AND2_X1 U78 (.ZN(mem_address[15]),
.A2(n24),
.A1(aligned_address[17]));
AND2_X1 U79 (.ZN(mem_address[16]),
.A2(n24),
.A1(aligned_address[18]));
AND2_X1 U80 (.ZN(mem_address[17]),
.A2(n24),
.A1(aligned_address[19]));
AND2_X1 U81 (.ZN(mem_address[18]),
.A2(n24),
.A1(aligned_address[20]));
AND2_X1 U82 (.ZN(mem_address[19]),
.A2(n24),
.A1(aligned_address[21]));
AND2_X1 U83 (.ZN(mem_address[20]),
.A2(n24),
.A1(aligned_address[22]));
AND2_X1 U84 (.ZN(mem_address[21]),
.A2(n24),
.A1(aligned_address[23]));
AND2_X1 U85 (.ZN(mem_address[22]),
.A2(n24),
.A1(aligned_address[24]));
AND2_X1 U86 (.ZN(mem_address[23]),
.A2(n24),
.A1(aligned_address[25]));
AND2_X1 U87 (.ZN(mem_address[24]),
.A2(n24),
.A1(aligned_address[26]));
AND2_X1 U88 (.ZN(mem_address[25]),
.A2(n24),
.A1(aligned_address[27]));
AND2_X1 U89 (.ZN(mem_address[26]),
.A2(n24),
.A1(aligned_address[28]));
AND2_X1 U90 (.ZN(mem_address[27]),
.A2(n24),
.A1(aligned_address[29]));
AND2_X1 U91 (.ZN(mem_address[28]),
.A2(n24),
.A1(aligned_address[30]));
AND2_X1 U92 (.ZN(mem_address[29]),
.A2(n24),
.A1(aligned_address[31]));
AND2_X1 U93 (.ZN(mem_address[0]),
.A2(n24),
.A1(aligned_address[2]));
AND2_X1 U94 (.ZN(mem_address[10]),
.A2(n24),
.A1(aligned_address[12]));
AND2_X1 U95 (.ZN(mem_address[11]),
.A2(n24),
.A1(aligned_address[13]));
AND2_X1 U96 (.ZN(mem_address[12]),
.A2(n24),
.A1(aligned_address[14]));
AND2_X1 U97 (.ZN(mem_address[13]),
.A2(n24),
.A1(aligned_address[15]));
AND2_X1 U98 (.ZN(mem_address[14]),
.A2(n24),
.A1(aligned_address[16]));
endmodule
module ALU_DW01_cmp6_1 (
A,
B,
TC,
LT,
GT,
EQ,
LE,
GE,
NE);
input [31:0] A;
input [31:0] B;
input TC;
output LT;
output GT;
output EQ;
output LE;
output GE;
output NE;
// Internal wires
wire n1;
wire n2;
wire n3;
wire n4;
wire n5;
wire n6;
wire n7;
wire n8;
wire n9;
wire n10;
wire n11;
wire n12;
wire n13;
wire n14;
wire n15;
wire n16;
wire n17;
wire n18;
wire n19;
wire n20;
wire n21;
wire n22;
wire n23;
wire n24;
wire n25;
wire n26;
wire n27;
wire n28;
wire n29;
wire n30;
wire n31;
wire n32;
wire n33;
wire n34;
wire n35;
wire n36;
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
XOR2_X1 U55 (.Z(n7),
.B(n111),
.A(A[30]));
NAND3_X1 U149 (.ZN(n185),
.A3(n96),
.A2(n99),
.A1(n189));
NAND3_X1 U153 (.ZN(n189),
.A3(n195),
.A2(n194),
.A1(n193));
INV_X1 U1 (.ZN(n88),
.A(n91));
INV_X1 U2 (.ZN(n74),
.A(n77));
INV_X1 U3 (.ZN(n60),
.A(n63));
INV_X1 U4 (.ZN(n46),
.A(n49));
INV_X1 U5 (.ZN(n32),
.A(n35));
INV_X1 U6 (.ZN(n18),
.A(n21));
INV_X1 U7 (.ZN(NE),
.A(EQ));
NOR2_X1 U8 (.ZN(EQ),
.A2(LT),
.A1(GT));
NOR2_X1 U9 (.ZN(n82),
.A2(n83),
.A1(n179));
NOR2_X1 U10 (.ZN(n68),
.A2(n69),
.A1(n167));
NOR2_X1 U11 (.ZN(n54),
.A2(n55),
.A1(n155));
NOR2_X1 U12 (.ZN(n40),
.A2(n41),
.A1(n143));
NOR2_X1 U13 (.ZN(n26),
.A2(n27),
.A1(n131));
NOR2_X1 U14 (.ZN(n12),
.A2(n13),
.A1(n119));
OAI211_X1 U15 (.ZN(n114),
.C2(n118),
.C1(n117),
.B(n12),
.A(n15));
NAND2_X1 U16 (.ZN(n118),
.A2(n123),
.A1(n122));
AOI211_X1 U17 (.ZN(n117),
.C2(n125),
.C1(n124),
.B(n126),
.A(n21));
INV_X1 U18 (.ZN(n122),
.A(n16));
OAI211_X1 U19 (.ZN(n173),
.C2(n178),
.C1(n177),
.B(n82),
.A(n85));
NAND2_X1 U20 (.ZN(n178),
.A2(n183),
.A1(n182));
AOI211_X1 U21 (.ZN(n177),
.C2(n185),
.C1(n184),
.B(n186),
.A(n91));
INV_X1 U22 (.ZN(n182),
.A(n86));
OAI211_X1 U23 (.ZN(n161),
.C2(n166),
.C1(n165),
.B(n68),
.A(n71));
NAND2_X1 U24 (.ZN(n166),
.A2(n171),
.A1(n170));
AOI211_X1 U25 (.ZN(n165),
.C2(n173),
.C1(n172),
.B(n174),
.A(n77));
INV_X1 U26 (.ZN(n170),
.A(n72));
OAI211_X1 U27 (.ZN(n149),
.C2(n154),
.C1(n153),
.B(n54),
.A(n57));
NAND2_X1 U28 (.ZN(n154),
.A2(n159),
.A1(n158));
AOI211_X1 U29 (.ZN(n153),
.C2(n161),
.C1(n160),
.B(n162),
.A(n63));
INV_X1 U30 (.ZN(n158),
.A(n58));
OAI211_X1 U31 (.ZN(n137),
.C2(n142),
.C1(n141),
.B(n40),
.A(n43));
NAND2_X1 U32 (.ZN(n142),
.A2(n147),
.A1(n146));
AOI211_X1 U33 (.ZN(n141),
.C2(n149),
.C1(n148),
.B(n150),
.A(n49));
INV_X1 U34 (.ZN(n146),
.A(n44));
OAI211_X1 U35 (.ZN(n125),
.C2(n130),
.C1(n129),
.B(n26),
.A(n29));
NAND2_X1 U36 (.ZN(n130),
.A2(n135),
.A1(n134));
AOI211_X1 U37 (.ZN(n129),
.C2(n137),
.C1(n136),
.B(n138),
.A(n35));
INV_X1 U38 (.ZN(n134),
.A(n30));
AOI21_X1 U39 (.ZN(n87),
.B2(n93),
.B1(n92),
.A(n94));
AOI21_X1 U40 (.ZN(n92),
.B2(n96),
.B1(n95),
.A(n97));
AOI21_X1 U41 (.ZN(n95),
.B2(n99),
.B1(n98),
.A(n100));
AOI21_X1 U42 (.ZN(n98),
.B2(n102),
.B1(n101),
.A(n103));
AOI21_X1 U43 (.ZN(n73),
.B2(n79),
.B1(n78),
.A(n80));
AOI21_X1 U44 (.ZN(n78),
.B2(n82),
.B1(n81),
.A(n83));
AOI21_X1 U45 (.ZN(n81),
.B2(n85),
.B1(n84),
.A(n86));
AOI21_X1 U46 (.ZN(n84),
.B2(n88),
.B1(n87),
.A(n89));
AOI21_X1 U47 (.ZN(n59),
.B2(n65),
.B1(n64),
.A(n66));
AOI21_X1 U48 (.ZN(n64),
.B2(n68),
.B1(n67),
.A(n69));
AOI21_X1 U49 (.ZN(n67),
.B2(n71),
.B1(n70),
.A(n72));
AOI21_X1 U50 (.ZN(n70),
.B2(n74),
.B1(n73),
.A(n75));
AOI21_X1 U51 (.ZN(n45),
.B2(n51),
.B1(n50),
.A(n52));
AOI21_X1 U52 (.ZN(n50),
.B2(n54),
.B1(n53),
.A(n55));
AOI21_X1 U53 (.ZN(n53),
.B2(n57),
.B1(n56),
.A(n58));
AOI21_X1 U54 (.ZN(n56),
.B2(n60),
.B1(n59),
.A(n61));
AOI21_X1 U56 (.ZN(n31),
.B2(n37),
.B1(n36),
.A(n38));
AOI21_X1 U57 (.ZN(n36),
.B2(n40),
.B1(n39),
.A(n41));
AOI21_X1 U58 (.ZN(n39),
.B2(n43),
.B1(n42),
.A(n44));
AOI21_X1 U59 (.ZN(n42),
.B2(n46),
.B1(n45),
.A(n47));
AOI21_X1 U60 (.ZN(n17),
.B2(n23),
.B1(n22),
.A(n24));
AOI21_X1 U61 (.ZN(n22),
.B2(n26),
.B1(n25),
.A(n27));
AOI21_X1 U62 (.ZN(n25),
.B2(n29),
.B1(n28),
.A(n30));
AOI21_X1 U63 (.ZN(n28),
.B2(n32),
.B1(n31),
.A(n33));
AOI21_X1 U64 (.ZN(n6),
.B2(n9),
.B1(n8),
.A(n10));
AOI21_X1 U65 (.ZN(n8),
.B2(n12),
.B1(n11),
.A(n13));
AOI21_X1 U66 (.ZN(n11),
.B2(n15),
.B1(n14),
.A(n16));
AOI21_X1 U67 (.ZN(n14),
.B2(n18),
.B1(n17),
.A(n19));
NOR2_X1 U68 (.ZN(n96),
.A2(n97),
.A1(n190));
NOR2_X1 U69 (.ZN(n184),
.A2(n94),
.A1(n190));
NOR2_X1 U70 (.ZN(n172),
.A2(n80),
.A1(n179));
NOR2_X1 U71 (.ZN(n160),
.A2(n66),
.A1(n167));
NOR2_X1 U72 (.ZN(n148),
.A2(n52),
.A1(n155));
NOR2_X1 U73 (.ZN(n136),
.A2(n38),
.A1(n143));
NOR2_X1 U74 (.ZN(n124),
.A2(n24),
.A1(n131));
NOR2_X1 U75 (.ZN(n113),
.A2(n10),
.A1(n119));
NAND2_X1 U76 (.ZN(n91),
.A2(n90),
.A1(n183));
NAND2_X1 U77 (.ZN(n77),
.A2(n76),
.A1(n171));
NAND2_X1 U78 (.ZN(n63),
.A2(n62),
.A1(n159));
NAND2_X1 U79 (.ZN(n49),
.A2(n48),
.A1(n147));
NAND2_X1 U80 (.ZN(n35),
.A2(n34),
.A1(n135));
NAND2_X1 U81 (.ZN(n21),
.A2(n20),
.A1(n123));
AND2_X1 U82 (.ZN(n102),
.A2(n104),
.A1(n194));
INV_X1 U83 (.ZN(LT),
.A(GE));
INV_X1 U84 (.ZN(n186),
.A(n93));
INV_X1 U85 (.ZN(n174),
.A(n79));
INV_X1 U86 (.ZN(n162),
.A(n65));
INV_X1 U87 (.ZN(n150),
.A(n51));
INV_X1 U88 (.ZN(n138),
.A(n37));
INV_X1 U89 (.ZN(n126),
.A(n23));
INV_X1 U90 (.ZN(n89),
.A(n90));
INV_X1 U91 (.ZN(n75),
.A(n76));
INV_X1 U92 (.ZN(n61),
.A(n62));
INV_X1 U93 (.ZN(n47),
.A(n48));
INV_X1 U94 (.ZN(n33),
.A(n34));
INV_X1 U95 (.ZN(n19),
.A(n20));
INV_X1 U96 (.ZN(n103),
.A(n104));
AOI21_X1 U97 (.ZN(GE),
.B2(n2),
.B1(n1),
.A(n3));
INV_X1 U98 (.ZN(n2),
.A(n4));
AOI22_X1 U99 (.ZN(n4),
.B2(n7),
.B1(n6),
.A2(n5),
.A1(B[30]));
INV_X1 U100 (.ZN(n5),
.A(A[30]));
OAI21_X1 U101 (.ZN(GT),
.B2(n109),
.B1(n3),
.A(n1));
AOI22_X1 U102 (.ZN(n109),
.B2(n7),
.B1(n112),
.A2(n111),
.A1(A[30]));
AOI21_X1 U103 (.ZN(n112),
.B2(n114),
.B1(n113),
.A(n115));
INV_X1 U104 (.ZN(n115),
.A(n9));
AOI22_X1 U105 (.ZN(n101),
.B2(n107),
.B1(A[1]),
.A2(n106),
.A1(n105));
OR2_X1 U106 (.ZN(n105),
.A2(A[1]),
.A1(n107));
NAND2_X1 U107 (.ZN(n107),
.A2(n108),
.A1(B[0]));
NOR2_X1 U108 (.ZN(n196),
.A2(B[0]),
.A1(n108));
NOR2_X1 U109 (.ZN(n190),
.A2(B[4]),
.A1(n191));
NOR2_X1 U110 (.ZN(n179),
.A2(B[8]),
.A1(n180));
NOR2_X1 U111 (.ZN(n167),
.A2(B[12]),
.A1(n168));
NOR2_X1 U112 (.ZN(n155),
.A2(B[16]),
.A1(n156));
NOR2_X1 U113 (.ZN(n143),
.A2(B[20]),
.A1(n144));
NOR2_X1 U114 (.ZN(n131),
.A2(B[24]),
.A1(n132));
NOR2_X1 U115 (.ZN(n119),
.A2(B[28]),
.A1(n120));
NOR2_X1 U116 (.ZN(n94),
.A2(B[5]),
.A1(n187));
NOR2_X1 U117 (.ZN(n80),
.A2(B[9]),
.A1(n175));
NOR2_X1 U118 (.ZN(n66),
.A2(B[13]),
.A1(n163));
NOR2_X1 U119 (.ZN(n52),
.A2(B[17]),
.A1(n151));
NOR2_X1 U120 (.ZN(n38),
.A2(B[21]),
.A1(n139));
NOR2_X1 U121 (.ZN(n24),
.A2(B[25]),
.A1(n127));
NOR2_X1 U122 (.ZN(n10),
.A2(B[29]),
.A1(n116));
NOR2_X1 U123 (.ZN(n100),
.A2(B[3]),
.A1(n192));
NOR2_X1 U124 (.ZN(n86),
.A2(B[7]),
.A1(n181));
NOR2_X1 U125 (.ZN(n72),
.A2(B[11]),
.A1(n169));
NOR2_X1 U126 (.ZN(n58),
.A2(B[15]),
.A1(n157));
NOR2_X1 U127 (.ZN(n44),
.A2(B[19]),
.A1(n145));
NOR2_X1 U128 (.ZN(n30),
.A2(B[23]),
.A1(n133));
NOR2_X1 U129 (.ZN(n16),
.A2(B[27]),
.A1(n121));
NOR2_X1 U130 (.ZN(n3),
.A2(A[31]),
.A1(n110));
INV_X1 U131 (.ZN(n193),
.A(n100));
OAI211_X1 U132 (.ZN(n195),
.C2(n196),
.C1(A[1]),
.B(n102),
.A(n197));
NAND2_X1 U133 (.ZN(n85),
.A2(n181),
.A1(B[7]));
NAND2_X1 U134 (.ZN(n71),
.A2(n169),
.A1(B[11]));
NAND2_X1 U135 (.ZN(n57),
.A2(n157),
.A1(B[15]));
NAND2_X1 U136 (.ZN(n43),
.A2(n145),
.A1(B[19]));
NAND2_X1 U137 (.ZN(n29),
.A2(n133),
.A1(B[23]));
NAND2_X1 U138 (.ZN(n15),
.A2(n121),
.A1(B[27]));
NAND2_X1 U139 (.ZN(n93),
.A2(n187),
.A1(B[5]));
NAND2_X1 U140 (.ZN(n79),
.A2(n175),
.A1(B[9]));
NAND2_X1 U141 (.ZN(n65),
.A2(n163),
.A1(B[13]));
NAND2_X1 U142 (.ZN(n51),
.A2(n151),
.A1(B[17]));
NAND2_X1 U143 (.ZN(n37),
.A2(n139),
.A1(B[21]));
NAND2_X1 U144 (.ZN(n23),
.A2(n127),
.A1(B[25]));
NAND2_X1 U145 (.ZN(n9),
.A2(n116),
.A1(B[29]));
NAND2_X1 U146 (.ZN(n90),
.A2(n188),
.A1(B[6]));
NAND2_X1 U147 (.ZN(n76),
.A2(n176),
.A1(B[10]));
NAND2_X1 U148 (.ZN(n62),
.A2(n164),
.A1(B[14]));
NAND2_X1 U150 (.ZN(n48),
.A2(n152),
.A1(B[18]));
NAND2_X1 U151 (.ZN(n34),
.A2(n140),
.A1(B[22]));
NAND2_X1 U152 (.ZN(n20),
.A2(n128),
.A1(B[26]));
NAND2_X1 U154 (.ZN(n1),
.A2(n110),
.A1(A[31]));
AND2_X1 U155 (.ZN(n97),
.A2(n191),
.A1(B[4]));
AND2_X1 U156 (.ZN(n83),
.A2(n180),
.A1(B[8]));
AND2_X1 U157 (.ZN(n69),
.A2(n168),
.A1(B[12]));
AND2_X1 U158 (.ZN(n55),
.A2(n156),
.A1(B[16]));
AND2_X1 U159 (.ZN(n41),
.A2(n144),
.A1(B[20]));
AND2_X1 U160 (.ZN(n27),
.A2(n132),
.A1(B[24]));
AND2_X1 U161 (.ZN(n13),
.A2(n120),
.A1(B[28]));
NAND2_X1 U162 (.ZN(n99),
.A2(n192),
.A1(B[3]));
NAND2_X1 U163 (.ZN(n104),
.A2(n198),
.A1(B[2]));
OR2_X1 U164 (.ZN(n183),
.A2(B[6]),
.A1(n188));
OR2_X1 U165 (.ZN(n171),
.A2(B[10]),
.A1(n176));
OR2_X1 U166 (.ZN(n159),
.A2(B[14]),
.A1(n164));
OR2_X1 U167 (.ZN(n147),
.A2(B[18]),
.A1(n152));
OR2_X1 U168 (.ZN(n135),
.A2(B[22]),
.A1(n140));
OR2_X1 U169 (.ZN(n123),
.A2(B[26]),
.A1(n128));
INV_X1 U170 (.ZN(n108),
.A(A[0]));
INV_X1 U171 (.ZN(n192),
.A(A[3]));
INV_X1 U172 (.ZN(n187),
.A(A[5]));
INV_X1 U173 (.ZN(n181),
.A(A[7]));
INV_X1 U174 (.ZN(n175),
.A(A[9]));
INV_X1 U175 (.ZN(n169),
.A(A[11]));
INV_X1 U176 (.ZN(n163),
.A(A[13]));
INV_X1 U177 (.ZN(n157),
.A(A[15]));
INV_X1 U178 (.ZN(n151),
.A(A[17]));
INV_X1 U179 (.ZN(n145),
.A(A[19]));
INV_X1 U180 (.ZN(n139),
.A(A[21]));
INV_X1 U181 (.ZN(n133),
.A(A[23]));
INV_X1 U182 (.ZN(n127),
.A(A[25]));
INV_X1 U183 (.ZN(n121),
.A(A[27]));
INV_X1 U184 (.ZN(n116),
.A(A[29]));
INV_X1 U185 (.ZN(n110),
.A(B[31]));
INV_X1 U186 (.ZN(n106),
.A(B[1]));
INV_X1 U187 (.ZN(n111),
.A(B[30]));
INV_X1 U188 (.ZN(n198),
.A(A[2]));
INV_X1 U189 (.ZN(n188),
.A(A[6]));
INV_X1 U190 (.ZN(n176),
.A(A[10]));
INV_X1 U191 (.ZN(n164),
.A(A[14]));
INV_X1 U192 (.ZN(n152),
.A(A[18]));
INV_X1 U193 (.ZN(n140),
.A(A[22]));
INV_X1 U194 (.ZN(n128),
.A(A[26]));
OR2_X1 U195 (.ZN(n194),
.A2(B[2]),
.A1(n198));
INV_X1 U196 (.ZN(n191),
.A(A[4]));
INV_X1 U197 (.ZN(n180),
.A(A[8]));
INV_X1 U198 (.ZN(n168),
.A(A[12]));
INV_X1 U199 (.ZN(n156),
.A(A[16]));
INV_X1 U200 (.ZN(n144),
.A(A[20]));
INV_X1 U201 (.ZN(n132),
.A(A[24]));
INV_X1 U202 (.ZN(n120),
.A(A[28]));
INV_X1 U203 (.ZN(n197),
.A(n199));
AOI21_X1 U204 (.ZN(n199),
.B2(n196),
.B1(A[1]),
.A(n106));
endmodule
module ALU_DW01_cmp6_0 (
A,
B,
TC,
LT,
GT,
EQ,
LE,
GE,
NE);
input [31:0] A;
input [31:0] B;
input TC;
output LT;
output GT;
output EQ;
output LE;
output GE;
output NE;
// Internal wires
wire n1;
wire n2;
wire n3;
wire n4;
wire n5;
wire n6;
wire n7;
wire n8;
wire n9;
wire n10;
wire n11;
wire n12;
wire n13;
wire n14;
wire n15;
wire n16;
wire n17;
wire n18;
wire n19;
wire n20;
wire n21;
wire n22;
wire n23;
wire n24;
wire n25;
wire n26;
wire n27;
wire n28;
wire n29;
wire n30;
wire n31;
wire n32;
wire n33;
wire n34;
wire n35;
wire n36;
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
wire n200;
NAND3_X1 U25 (.ZN(n69),
.A3(n74),
.A2(n73),
.A1(n72));
NAND3_X1 U26 (.ZN(n72),
.A3(n77),
.A2(n76),
.A1(n75));
XOR2_X1 U43 (.Z(n8),
.B(B[30]),
.A(n100));
INV_X1 U1 (.ZN(n168),
.A(n60));
INV_X1 U2 (.ZN(n140),
.A(n40));
INV_X1 U3 (.ZN(n112),
.A(n20));
INV_X1 U4 (.ZN(GE),
.A(LT));
AOI211_X1 U5 (.ZN(n62),
.C2(n69),
.C1(n68),
.B(n71),
.A(n70));
NOR2_X1 U6 (.ZN(n68),
.A2(n85),
.A1(n84));
AOI211_X1 U7 (.ZN(n52),
.C2(n59),
.C1(n58),
.B(n61),
.A(n60));
NOR2_X1 U8 (.ZN(n58),
.A2(n87),
.A1(n86));
OAI211_X1 U9 (.ZN(n59),
.C2(n63),
.C1(n62),
.B(n65),
.A(n64));
NAND2_X1 U10 (.ZN(n63),
.A2(n67),
.A1(n66));
AOI211_X1 U11 (.ZN(n42),
.C2(n49),
.C1(n48),
.B(n51),
.A(n50));
NOR2_X1 U12 (.ZN(n48),
.A2(n89),
.A1(n88));
OAI211_X1 U13 (.ZN(n49),
.C2(n53),
.C1(n52),
.B(n55),
.A(n54));
NAND2_X1 U14 (.ZN(n53),
.A2(n57),
.A1(n56));
AOI211_X1 U15 (.ZN(n32),
.C2(n39),
.C1(n38),
.B(n41),
.A(n40));
NOR2_X1 U16 (.ZN(n38),
.A2(n91),
.A1(n90));
OAI211_X1 U17 (.ZN(n39),
.C2(n43),
.C1(n42),
.B(n45),
.A(n44));
NAND2_X1 U18 (.ZN(n43),
.A2(n47),
.A1(n46));
AOI211_X1 U19 (.ZN(n22),
.C2(n29),
.C1(n28),
.B(n31),
.A(n30));
NOR2_X1 U20 (.ZN(n28),
.A2(n93),
.A1(n92));
OAI211_X1 U21 (.ZN(n29),
.C2(n33),
.C1(n32),
.B(n35),
.A(n34));
NAND2_X1 U22 (.ZN(n33),
.A2(n37),
.A1(n36));
AOI211_X1 U23 (.ZN(n12),
.C2(n19),
.C1(n18),
.B(n21),
.A(n20));
NOR2_X1 U24 (.ZN(n18),
.A2(n95),
.A1(n94));
OAI211_X1 U27 (.ZN(n19),
.C2(n23),
.C1(n22),
.B(n25),
.A(n24));
NAND2_X1 U28 (.ZN(n23),
.A2(n27),
.A1(n26));
NOR2_X1 U29 (.ZN(n80),
.A2(n196),
.A1(n195));
INV_X1 U30 (.ZN(n196),
.A(n76));
NOR2_X1 U31 (.ZN(n65),
.A2(n86),
.A1(n176));
NOR2_X1 U32 (.ZN(n55),
.A2(n88),
.A1(n162));
NOR2_X1 U33 (.ZN(n45),
.A2(n90),
.A1(n148));
NOR2_X1 U34 (.ZN(n35),
.A2(n92),
.A1(n134));
NOR2_X1 U35 (.ZN(n25),
.A2(n94),
.A1(n120));
NOR2_X1 U36 (.ZN(n15),
.A2(n96),
.A1(n106));
AOI21_X1 U37 (.ZN(n167),
.B2(n173),
.B1(n172),
.A(n87));
INV_X1 U38 (.ZN(n173),
.A(n61));
AOI21_X1 U39 (.ZN(n172),
.B2(n65),
.B1(n175),
.A(n176));
AOI21_X1 U40 (.ZN(n175),
.B2(n64),
.B1(n178),
.A(n179));
AOI21_X1 U41 (.ZN(n186),
.B2(n74),
.B1(n189),
.A(n190));
AOI21_X1 U42 (.ZN(n189),
.B2(n73),
.B1(n191),
.A(n192));
INV_X1 U44 (.ZN(n192),
.A(n75));
AOI21_X1 U45 (.ZN(n191),
.B2(n80),
.B1(n194),
.A(n195));
AOI21_X1 U46 (.ZN(n178),
.B2(n182),
.B1(n181),
.A(n183));
INV_X1 U47 (.ZN(n182),
.A(n70));
AOI21_X1 U48 (.ZN(n181),
.B2(n187),
.B1(n186),
.A(n85));
INV_X1 U49 (.ZN(n187),
.A(n71));
AOI21_X1 U50 (.ZN(n158),
.B2(n55),
.B1(n161),
.A(n162));
AOI21_X1 U51 (.ZN(n161),
.B2(n54),
.B1(n164),
.A(n165));
INV_X1 U52 (.ZN(n165),
.A(n56));
AOI21_X1 U53 (.ZN(n164),
.B2(n168),
.B1(n167),
.A(n169));
AOI21_X1 U54 (.ZN(n111),
.B2(n117),
.B1(n116),
.A(n95));
INV_X1 U55 (.ZN(n117),
.A(n21));
AOI21_X1 U56 (.ZN(n116),
.B2(n25),
.B1(n119),
.A(n120));
AOI21_X1 U57 (.ZN(n119),
.B2(n24),
.B1(n122),
.A(n123));
AOI21_X1 U58 (.ZN(n150),
.B2(n154),
.B1(n153),
.A(n155));
INV_X1 U59 (.ZN(n154),
.A(n50));
AOI21_X1 U60 (.ZN(n153),
.B2(n159),
.B1(n158),
.A(n89));
INV_X1 U61 (.ZN(n159),
.A(n51));
AOI21_X1 U62 (.ZN(n139),
.B2(n145),
.B1(n144),
.A(n91));
INV_X1 U63 (.ZN(n145),
.A(n41));
AOI21_X1 U64 (.ZN(n144),
.B2(n45),
.B1(n147),
.A(n148));
AOI21_X1 U65 (.ZN(n147),
.B2(n44),
.B1(n150),
.A(n151));
AOI21_X1 U66 (.ZN(n130),
.B2(n35),
.B1(n133),
.A(n134));
AOI21_X1 U67 (.ZN(n133),
.B2(n34),
.B1(n136),
.A(n137));
INV_X1 U68 (.ZN(n137),
.A(n36));
AOI21_X1 U69 (.ZN(n136),
.B2(n140),
.B1(n139),
.A(n141));
AOI21_X1 U70 (.ZN(n122),
.B2(n126),
.B1(n125),
.A(n127));
INV_X1 U71 (.ZN(n126),
.A(n30));
AOI21_X1 U72 (.ZN(n125),
.B2(n131),
.B1(n130),
.A(n93));
INV_X1 U73 (.ZN(n131),
.A(n31));
AOI21_X1 U74 (.ZN(n102),
.B2(n15),
.B1(n105),
.A(n106));
AOI21_X1 U75 (.ZN(n105),
.B2(n14),
.B1(n108),
.A(n109));
INV_X1 U76 (.ZN(n109),
.A(n16));
AOI21_X1 U77 (.ZN(n108),
.B2(n112),
.B1(n111),
.A(n113));
AOI21_X1 U78 (.ZN(n7),
.B2(n10),
.B1(n9),
.A(n11));
NOR2_X1 U79 (.ZN(n9),
.A2(n97),
.A1(n96));
OAI211_X1 U80 (.ZN(n10),
.C2(n13),
.C1(n12),
.B(n15),
.A(n14));
NAND2_X1 U81 (.ZN(n13),
.A2(n17),
.A1(n16));
NOR2_X1 U82 (.ZN(n74),
.A2(n84),
.A1(n190));
NAND2_X1 U83 (.ZN(n70),
.A2(n67),
.A1(n184));
INV_X1 U84 (.ZN(n184),
.A(n183));
NAND2_X1 U85 (.ZN(n60),
.A2(n57),
.A1(n170));
INV_X1 U86 (.ZN(n170),
.A(n169));
NAND2_X1 U87 (.ZN(n50),
.A2(n47),
.A1(n156));
INV_X1 U88 (.ZN(n156),
.A(n155));
NAND2_X1 U89 (.ZN(n40),
.A2(n37),
.A1(n142));
INV_X1 U90 (.ZN(n142),
.A(n141));
NAND2_X1 U91 (.ZN(n30),
.A2(n27),
.A1(n128));
INV_X1 U92 (.ZN(n128),
.A(n127));
NAND2_X1 U93 (.ZN(n20),
.A2(n17),
.A1(n114));
INV_X1 U94 (.ZN(n114),
.A(n113));
INV_X1 U95 (.ZN(GT),
.A(LE));
INV_X1 U96 (.ZN(n179),
.A(n66));
INV_X1 U97 (.ZN(n151),
.A(n46));
INV_X1 U98 (.ZN(n123),
.A(n26));
AOI21_X1 U99 (.ZN(LE),
.B2(n3),
.B1(n2),
.A(n4));
INV_X1 U100 (.ZN(n3),
.A(n5));
AOI22_X1 U101 (.ZN(n5),
.B2(n8),
.B1(n7),
.A2(n6),
.A1(A[30]));
INV_X1 U102 (.ZN(n6),
.A(B[30]));
OAI21_X1 U103 (.ZN(LT),
.B2(n98),
.B1(n4),
.A(n2));
AOI22_X1 U104 (.ZN(n98),
.B2(n8),
.B1(n101),
.A2(n100),
.A1(B[30]));
AOI21_X1 U105 (.ZN(n101),
.B2(n103),
.B1(n102),
.A(n97));
INV_X1 U106 (.ZN(n103),
.A(n11));
NOR2_X1 U107 (.ZN(n71),
.A2(A[5]),
.A1(n188));
NOR2_X1 U108 (.ZN(n61),
.A2(A[9]),
.A1(n174));
NOR2_X1 U109 (.ZN(n51),
.A2(A[13]),
.A1(n160));
NOR2_X1 U110 (.ZN(n41),
.A2(A[17]),
.A1(n146));
NOR2_X1 U111 (.ZN(n31),
.A2(A[21]),
.A1(n132));
NOR2_X1 U112 (.ZN(n21),
.A2(A[25]),
.A1(n118));
NOR2_X1 U113 (.ZN(n195),
.A2(A[2]),
.A1(n197));
NOR2_X1 U114 (.ZN(n190),
.A2(A[4]),
.A1(n1));
NOR2_X1 U115 (.ZN(n176),
.A2(A[8]),
.A1(n177));
NOR2_X1 U116 (.ZN(n162),
.A2(A[12]),
.A1(n163));
NOR2_X1 U117 (.ZN(n148),
.A2(A[16]),
.A1(n149));
NOR2_X1 U118 (.ZN(n134),
.A2(A[20]),
.A1(n135));
NOR2_X1 U119 (.ZN(n120),
.A2(A[24]),
.A1(n121));
NOR2_X1 U120 (.ZN(n106),
.A2(A[28]),
.A1(n107));
NOR2_X1 U121 (.ZN(n183),
.A2(A[6]),
.A1(n185));
NOR2_X1 U122 (.ZN(n169),
.A2(A[10]),
.A1(n171));
NOR2_X1 U123 (.ZN(n155),
.A2(A[14]),
.A1(n157));
NOR2_X1 U124 (.ZN(n141),
.A2(A[18]),
.A1(n143));
NOR2_X1 U125 (.ZN(n127),
.A2(A[22]),
.A1(n129));
NOR2_X1 U126 (.ZN(n113),
.A2(A[26]),
.A1(n115));
NOR2_X1 U127 (.ZN(n11),
.A2(A[29]),
.A1(n104));
NOR2_X1 U128 (.ZN(n4),
.A2(A[31]),
.A1(n99));
OAI211_X1 U129 (.ZN(n77),
.C2(n78),
.C1(A[1]),
.B(n80),
.A(n79));
INV_X1 U130 (.ZN(n78),
.A(n82));
OAI21_X1 U131 (.ZN(n79),
.B2(n82),
.B1(n81),
.A(B[1]));
NAND2_X1 U132 (.ZN(n82),
.A2(n83),
.A1(A[0]));
NAND2_X1 U133 (.ZN(n67),
.A2(n185),
.A1(A[6]));
NAND2_X1 U134 (.ZN(n57),
.A2(n171),
.A1(A[10]));
NAND2_X1 U135 (.ZN(n47),
.A2(n157),
.A1(A[14]));
NAND2_X1 U136 (.ZN(n37),
.A2(n143),
.A1(A[18]));
NAND2_X1 U137 (.ZN(n27),
.A2(n129),
.A1(A[22]));
NAND2_X1 U138 (.ZN(n17),
.A2(n115),
.A1(A[26]));
NAND2_X1 U139 (.ZN(n2),
.A2(n99),
.A1(A[31]));
NAND2_X1 U140 (.ZN(n66),
.A2(n180),
.A1(A[7]));
NAND2_X1 U141 (.ZN(n56),
.A2(n166),
.A1(A[11]));
NAND2_X1 U142 (.ZN(n46),
.A2(n152),
.A1(A[15]));
NAND2_X1 U143 (.ZN(n36),
.A2(n138),
.A1(A[19]));
NAND2_X1 U144 (.ZN(n26),
.A2(n124),
.A1(A[23]));
NAND2_X1 U145 (.ZN(n16),
.A2(n110),
.A1(A[27]));
INV_X1 U146 (.ZN(n81),
.A(A[1]));
AND2_X1 U147 (.ZN(n84),
.A2(n1),
.A1(A[4]));
AND2_X1 U148 (.ZN(n86),
.A2(n177),
.A1(A[8]));
AND2_X1 U149 (.ZN(n88),
.A2(n163),
.A1(A[12]));
AND2_X1 U150 (.ZN(n90),
.A2(n149),
.A1(A[16]));
AND2_X1 U151 (.ZN(n92),
.A2(n135),
.A1(A[20]));
AND2_X1 U152 (.ZN(n94),
.A2(n121),
.A1(A[24]));
AND2_X1 U153 (.ZN(n96),
.A2(n107),
.A1(A[28]));
AND2_X1 U154 (.ZN(n85),
.A2(n188),
.A1(A[5]));
AND2_X1 U155 (.ZN(n87),
.A2(n174),
.A1(A[9]));
AND2_X1 U156 (.ZN(n89),
.A2(n160),
.A1(A[13]));
AND2_X1 U157 (.ZN(n91),
.A2(n146),
.A1(A[17]));
AND2_X1 U158 (.ZN(n93),
.A2(n132),
.A1(A[21]));
AND2_X1 U159 (.ZN(n95),
.A2(n118),
.A1(A[25]));
AND2_X1 U160 (.ZN(n97),
.A2(n104),
.A1(A[29]));
OR2_X1 U161 (.ZN(n64),
.A2(A[7]),
.A1(n180));
OR2_X1 U162 (.ZN(n54),
.A2(A[11]),
.A1(n166));
OR2_X1 U163 (.ZN(n44),
.A2(A[15]),
.A1(n152));
OR2_X1 U164 (.ZN(n34),
.A2(A[19]),
.A1(n138));
OR2_X1 U165 (.ZN(n24),
.A2(A[23]),
.A1(n124));
OR2_X1 U166 (.ZN(n14),
.A2(A[27]),
.A1(n110));
NAND2_X1 U167 (.ZN(n76),
.A2(n197),
.A1(A[2]));
NAND2_X1 U168 (.ZN(n75),
.A2(n193),
.A1(A[3]));
INV_X1 U169 (.ZN(n197),
.A(B[2]));
INV_X1 U170 (.ZN(n185),
.A(B[6]));
INV_X1 U171 (.ZN(n171),
.A(B[10]));
INV_X1 U172 (.ZN(n157),
.A(B[14]));
INV_X1 U173 (.ZN(n83),
.A(B[0]));
INV_X1 U174 (.ZN(n143),
.A(B[18]));
INV_X1 U175 (.ZN(n129),
.A(B[22]));
INV_X1 U176 (.ZN(n115),
.A(B[26]));
INV_X1 U177 (.ZN(n99),
.A(B[31]));
OR2_X1 U178 (.ZN(n73),
.A2(A[3]),
.A1(n193));
INV_X1 U179 (.ZN(n100),
.A(A[30]));
INV_X1 U180 (.ZN(n193),
.A(B[3]));
INV_X1 U181 (.ZN(n180),
.A(B[7]));
INV_X1 U182 (.ZN(n166),
.A(B[11]));
INV_X1 U183 (.ZN(n152),
.A(B[15]));
INV_X1 U184 (.ZN(n138),
.A(B[19]));
INV_X1 U185 (.ZN(n124),
.A(B[23]));
INV_X1 U186 (.ZN(n110),
.A(B[27]));
INV_X1 U187 (.ZN(n1),
.A(B[4]));
INV_X1 U188 (.ZN(n188),
.A(B[5]));
INV_X1 U189 (.ZN(n177),
.A(B[8]));
INV_X1 U190 (.ZN(n174),
.A(B[9]));
INV_X1 U191 (.ZN(n163),
.A(B[12]));
INV_X1 U192 (.ZN(n160),
.A(B[13]));
INV_X1 U193 (.ZN(n149),
.A(B[16]));
INV_X1 U194 (.ZN(n146),
.A(B[17]));
INV_X1 U195 (.ZN(n135),
.A(B[20]));
INV_X1 U196 (.ZN(n132),
.A(B[21]));
INV_X1 U197 (.ZN(n121),
.A(B[24]));
INV_X1 U198 (.ZN(n118),
.A(B[25]));
INV_X1 U199 (.ZN(n107),
.A(B[28]));
INV_X1 U200 (.ZN(n104),
.A(B[29]));
INV_X1 U201 (.ZN(n194),
.A(n198));
OAI22_X1 U202 (.ZN(n198),
.B2(n200),
.B1(n81),
.A2(B[1]),
.A1(n199));
AND2_X1 U203 (.ZN(n199),
.A2(n81),
.A1(n200));
NOR2_X1 U204 (.ZN(n200),
.A2(A[0]),
.A1(n83));
endmodule
module ALU_DW01_add_1 (
A,
B,
CI,
SUM,
CO);
input [31:0] A;
input [31:0] B;
input CI;
output [31:0] SUM;
output CO;
// Internal wires
wire \carry[31] ;
wire \carry[30] ;
wire \carry[29] ;
wire \carry[28] ;
wire \carry[27] ;
wire \carry[26] ;
wire \carry[25] ;
wire \carry[24] ;
wire \carry[23] ;
wire \carry[22] ;
wire \carry[21] ;
wire \carry[20] ;
wire \carry[19] ;
wire \carry[18] ;
wire \carry[17] ;
wire \carry[16] ;
wire \carry[15] ;
wire \carry[14] ;
wire \carry[13] ;
wire \carry[12] ;
wire \carry[11] ;
wire \carry[10] ;
wire \carry[9] ;
wire \carry[8] ;
wire \carry[7] ;
wire \carry[6] ;
wire \carry[5] ;
wire \carry[4] ;
wire \carry[3] ;
wire \carry[2] ;
wire \carry[1] ;
FA_X1 U1_31 (.S(SUM[31]),
.CI(\carry[31] ),
.B(B[31]),
.A(A[31]));
FA_X1 U1_30 (.S(SUM[30]),
.CO(\carry[31] ),
.CI(\carry[30] ),
.B(B[30]),
.A(A[30]));
FA_X1 U1_29 (.S(SUM[29]),
.CO(\carry[30] ),
.CI(\carry[29] ),
.B(B[29]),
.A(A[29]));
FA_X1 U1_28 (.S(SUM[28]),
.CO(\carry[29] ),
.CI(\carry[28] ),
.B(B[28]),
.A(A[28]));
FA_X1 U1_27 (.S(SUM[27]),
.CO(\carry[28] ),
.CI(\carry[27] ),
.B(B[27]),
.A(A[27]));
FA_X1 U1_26 (.S(SUM[26]),
.CO(\carry[27] ),
.CI(\carry[26] ),
.B(B[26]),
.A(A[26]));
FA_X1 U1_25 (.S(SUM[25]),
.CO(\carry[26] ),
.CI(\carry[25] ),
.B(B[25]),
.A(A[25]));
FA_X1 U1_24 (.S(SUM[24]),
.CO(\carry[25] ),
.CI(\carry[24] ),
.B(B[24]),
.A(A[24]));
FA_X1 U1_23 (.S(SUM[23]),
.CO(\carry[24] ),
.CI(\carry[23] ),
.B(B[23]),
.A(A[23]));
FA_X1 U1_22 (.S(SUM[22]),
.CO(\carry[23] ),
.CI(\carry[22] ),
.B(B[22]),
.A(A[22]));
FA_X1 U1_21 (.S(SUM[21]),
.CO(\carry[22] ),
.CI(\carry[21] ),
.B(B[21]),
.A(A[21]));
FA_X1 U1_20 (.S(SUM[20]),
.CO(\carry[21] ),
.CI(\carry[20] ),
.B(B[20]),
.A(A[20]));
FA_X1 U1_19 (.S(SUM[19]),
.CO(\carry[20] ),
.CI(\carry[19] ),
.B(B[19]),
.A(A[19]));
FA_X1 U1_18 (.S(SUM[18]),
.CO(\carry[19] ),
.CI(\carry[18] ),
.B(B[18]),
.A(A[18]));
FA_X1 U1_17 (.S(SUM[17]),
.CO(\carry[18] ),
.CI(\carry[17] ),
.B(B[17]),
.A(A[17]));
FA_X1 U1_16 (.S(SUM[16]),
.CO(\carry[17] ),
.CI(\carry[16] ),
.B(B[16]),
.A(A[16]));
FA_X1 U1_15 (.S(SUM[15]),
.CO(\carry[16] ),
.CI(\carry[15] ),
.B(B[15]),
.A(A[15]));
FA_X1 U1_14 (.S(SUM[14]),
.CO(\carry[15] ),
.CI(\carry[14] ),
.B(B[14]),
.A(A[14]));
FA_X1 U1_13 (.S(SUM[13]),
.CO(\carry[14] ),
.CI(\carry[13] ),
.B(B[13]),
.A(A[13]));
FA_X1 U1_12 (.S(SUM[12]),
.CO(\carry[13] ),
.CI(\carry[12] ),
.B(B[12]),
.A(A[12]));
FA_X1 U1_11 (.S(SUM[11]),
.CO(\carry[12] ),
.CI(\carry[11] ),
.B(B[11]),
.A(A[11]));
FA_X1 U1_10 (.S(SUM[10]),
.CO(\carry[11] ),
.CI(\carry[10] ),
.B(B[10]),
.A(A[10]));
FA_X1 U1_9 (.S(SUM[9]),
.CO(\carry[10] ),
.CI(\carry[9] ),
.B(B[9]),
.A(A[9]));
FA_X1 U1_8 (.S(SUM[8]),
.CO(\carry[9] ),
.CI(\carry[8] ),
.B(B[8]),
.A(A[8]));
FA_X1 U1_7 (.S(SUM[7]),
.CO(\carry[8] ),
.CI(\carry[7] ),
.B(B[7]),
.A(A[7]));
FA_X1 U1_6 (.S(SUM[6]),
.CO(\carry[7] ),
.CI(\carry[6] ),
.B(B[6]),
.A(A[6]));
FA_X1 U1_5 (.S(SUM[5]),
.CO(\carry[6] ),
.CI(\carry[5] ),
.B(B[5]),
.A(A[5]));
FA_X1 U1_4 (.S(SUM[4]),
.CO(\carry[5] ),
.CI(\carry[4] ),
.B(B[4]),
.A(A[4]));
FA_X1 U1_3 (.S(SUM[3]),
.CO(\carry[4] ),
.CI(\carry[3] ),
.B(B[3]),
.A(A[3]));
FA_X1 U1_2 (.S(SUM[2]),
.CO(\carry[3] ),
.CI(\carry[2] ),
.B(B[2]),
.A(A[2]));
FA_X1 U1_1 (.S(SUM[1]),
.CO(\carry[2] ),
.CI(\carry[1] ),
.B(B[1]),
.A(A[1]));
XOR2_X1 U2 (.Z(SUM[0]),
.B(A[0]),
.A(B[0]));
AND2_X1 U1 (.ZN(\carry[1] ),
.A2(B[0]),
.A1(A[0]));
endmodule
module ALU_DW01_add_0 (
A,
B,
CI,
SUM,
CO);
input [31:0] A;
input [31:0] B;
input CI;
output [31:0] SUM;
output CO;
// Internal wires
wire \carry[31] ;
wire \carry[30] ;
wire \carry[29] ;
wire \carry[28] ;
wire \carry[27] ;
wire \carry[26] ;
wire \carry[25] ;
wire \carry[24] ;
wire \carry[23] ;
wire \carry[22] ;
wire \carry[21] ;
wire \carry[20] ;
wire \carry[19] ;
wire \carry[18] ;
wire \carry[17] ;
wire \carry[16] ;
wire \carry[15] ;
wire \carry[14] ;
wire \carry[13] ;
wire \carry[12] ;
wire \carry[11] ;
wire \carry[10] ;
wire \carry[9] ;
wire \carry[8] ;
wire \carry[7] ;
wire \carry[6] ;
wire \carry[5] ;
wire \carry[4] ;
wire \carry[3] ;
wire \carry[2] ;
wire \carry[1] ;
FA_X1 U1_31 (.S(SUM[31]),
.CI(\carry[31] ),
.B(B[31]),
.A(A[31]));
FA_X1 U1_30 (.S(SUM[30]),
.CO(\carry[31] ),
.CI(\carry[30] ),
.B(B[30]),
.A(A[30]));
FA_X1 U1_29 (.S(SUM[29]),
.CO(\carry[30] ),
.CI(\carry[29] ),
.B(B[29]),
.A(A[29]));
FA_X1 U1_28 (.S(SUM[28]),
.CO(\carry[29] ),
.CI(\carry[28] ),
.B(B[28]),
.A(A[28]));
FA_X1 U1_27 (.S(SUM[27]),
.CO(\carry[28] ),
.CI(\carry[27] ),
.B(B[27]),
.A(A[27]));
FA_X1 U1_26 (.S(SUM[26]),
.CO(\carry[27] ),
.CI(\carry[26] ),
.B(B[26]),
.A(A[26]));
FA_X1 U1_25 (.S(SUM[25]),
.CO(\carry[26] ),
.CI(\carry[25] ),
.B(B[25]),
.A(A[25]));
FA_X1 U1_24 (.S(SUM[24]),
.CO(\carry[25] ),
.CI(\carry[24] ),
.B(B[24]),
.A(A[24]));
FA_X1 U1_23 (.S(SUM[23]),
.CO(\carry[24] ),
.CI(\carry[23] ),
.B(B[23]),
.A(A[23]));
FA_X1 U1_22 (.S(SUM[22]),
.CO(\carry[23] ),
.CI(\carry[22] ),
.B(B[22]),
.A(A[22]));
FA_X1 U1_21 (.S(SUM[21]),
.CO(\carry[22] ),
.CI(\carry[21] ),
.B(B[21]),
.A(A[21]));
FA_X1 U1_20 (.S(SUM[20]),
.CO(\carry[21] ),
.CI(\carry[20] ),
.B(B[20]),
.A(A[20]));
FA_X1 U1_19 (.S(SUM[19]),
.CO(\carry[20] ),
.CI(\carry[19] ),
.B(B[19]),
.A(A[19]));
FA_X1 U1_18 (.S(SUM[18]),
.CO(\carry[19] ),
.CI(\carry[18] ),
.B(B[18]),
.A(A[18]));
FA_X1 U1_17 (.S(SUM[17]),
.CO(\carry[18] ),
.CI(\carry[17] ),
.B(B[17]),
.A(A[17]));
FA_X1 U1_16 (.S(SUM[16]),
.CO(\carry[17] ),
.CI(\carry[16] ),
.B(B[16]),
.A(A[16]));
FA_X1 U1_15 (.S(SUM[15]),
.CO(\carry[16] ),
.CI(\carry[15] ),
.B(B[15]),
.A(A[15]));
FA_X1 U1_14 (.S(SUM[14]),
.CO(\carry[15] ),
.CI(\carry[14] ),
.B(B[14]),
.A(A[14]));
FA_X1 U1_13 (.S(SUM[13]),
.CO(\carry[14] ),
.CI(\carry[13] ),
.B(B[13]),
.A(A[13]));
FA_X1 U1_12 (.S(SUM[12]),
.CO(\carry[13] ),
.CI(\carry[12] ),
.B(B[12]),
.A(A[12]));
FA_X1 U1_11 (.S(SUM[11]),
.CO(\carry[12] ),
.CI(\carry[11] ),
.B(B[11]),
.A(A[11]));
FA_X1 U1_10 (.S(SUM[10]),
.CO(\carry[11] ),
.CI(\carry[10] ),
.B(B[10]),
.A(A[10]));
FA_X1 U1_9 (.S(SUM[9]),
.CO(\carry[10] ),
.CI(\carry[9] ),
.B(B[9]),
.A(A[9]));
FA_X1 U1_8 (.S(SUM[8]),
.CO(\carry[9] ),
.CI(\carry[8] ),
.B(B[8]),
.A(A[8]));
FA_X1 U1_7 (.S(SUM[7]),
.CO(\carry[8] ),
.CI(\carry[7] ),
.B(B[7]),
.A(A[7]));
FA_X1 U1_6 (.S(SUM[6]),
.CO(\carry[7] ),
.CI(\carry[6] ),
.B(B[6]),
.A(A[6]));
FA_X1 U1_5 (.S(SUM[5]),
.CO(\carry[6] ),
.CI(\carry[5] ),
.B(B[5]),
.A(A[5]));
FA_X1 U1_4 (.S(SUM[4]),
.CO(\carry[5] ),
.CI(\carry[4] ),
.B(B[4]),
.A(A[4]));
FA_X1 U1_3 (.S(SUM[3]),
.CO(\carry[4] ),
.CI(\carry[3] ),
.B(B[3]),
.A(A[3]));
FA_X1 U1_2 (.S(SUM[2]),
.CO(\carry[3] ),
.CI(\carry[2] ),
.B(B[2]),
.A(A[2]));
FA_X1 U1_1 (.S(SUM[1]),
.CO(\carry[2] ),
.CI(\carry[1] ),
.B(B[1]),
.A(A[1]));
XOR2_X1 U2 (.Z(SUM[0]),
.B(A[0]),
.A(B[0]));
AND2_X1 U1 (.ZN(\carry[1] ),
.A2(B[0]),
.A1(A[0]));
endmodule
module ALU_DW01_sub_1 (
A,
B,
CI,
DIFF,
CO);
input [31:0] A;
input [31:0] B;
input CI;
output [31:0] DIFF;
output CO;
// Internal wires
wire \carry[31] ;
wire \carry[30] ;
wire \carry[29] ;
wire \carry[28] ;
wire \carry[27] ;
wire \carry[26] ;
wire \carry[25] ;
wire \carry[24] ;
wire \carry[23] ;
wire \carry[22] ;
wire \carry[21] ;
wire \carry[20] ;
wire \carry[19] ;
wire \carry[18] ;
wire \carry[17] ;
wire \carry[16] ;
wire \carry[15] ;
wire \carry[14] ;
wire \carry[13] ;
wire \carry[12] ;
wire \carry[11] ;
wire \carry[10] ;
wire \carry[9] ;
wire \carry[8] ;
wire \carry[7] ;
wire \carry[6] ;
wire \carry[5] ;
wire \carry[4] ;
wire \carry[3] ;
wire \carry[2] ;
wire \carry[1] ;
wire \B_not[31] ;
wire \B_not[30] ;
wire \B_not[29] ;
wire \B_not[28] ;
wire \B_not[27] ;
wire \B_not[26] ;
wire \B_not[25] ;
wire \B_not[24] ;
wire \B_not[23] ;
wire \B_not[22] ;
wire \B_not[21] ;
wire \B_not[20] ;
wire \B_not[19] ;
wire \B_not[18] ;
wire \B_not[17] ;
wire \B_not[16] ;
wire \B_not[15] ;
wire \B_not[14] ;
wire \B_not[13] ;
wire \B_not[12] ;
wire \B_not[11] ;
wire \B_not[10] ;
wire \B_not[9] ;
wire \B_not[8] ;
wire \B_not[7] ;
wire \B_not[6] ;
wire \B_not[5] ;
wire \B_not[3] ;
wire \B_not[2] ;
wire \B_not[1] ;
wire \B_not[0] ;
wire n1;
FA_X1 U2_31 (.S(DIFF[31]),
.CI(\carry[31] ),
.B(\B_not[31] ),
.A(A[31]));
FA_X1 U2_30 (.S(DIFF[30]),
.CO(\carry[31] ),
.CI(\carry[30] ),
.B(\B_not[30] ),
.A(A[30]));
FA_X1 U2_29 (.S(DIFF[29]),
.CO(\carry[30] ),
.CI(\carry[29] ),
.B(\B_not[29] ),
.A(A[29]));
FA_X1 U2_28 (.S(DIFF[28]),
.CO(\carry[29] ),
.CI(\carry[28] ),
.B(\B_not[28] ),
.A(A[28]));
FA_X1 U2_27 (.S(DIFF[27]),
.CO(\carry[28] ),
.CI(\carry[27] ),
.B(\B_not[27] ),
.A(A[27]));
FA_X1 U2_26 (.S(DIFF[26]),
.CO(\carry[27] ),
.CI(\carry[26] ),
.B(\B_not[26] ),
.A(A[26]));
FA_X1 U2_25 (.S(DIFF[25]),
.CO(\carry[26] ),
.CI(\carry[25] ),
.B(\B_not[25] ),
.A(A[25]));
FA_X1 U2_24 (.S(DIFF[24]),
.CO(\carry[25] ),
.CI(\carry[24] ),
.B(\B_not[24] ),
.A(A[24]));
FA_X1 U2_23 (.S(DIFF[23]),
.CO(\carry[24] ),
.CI(\carry[23] ),
.B(\B_not[23] ),
.A(A[23]));
FA_X1 U2_22 (.S(DIFF[22]),
.CO(\carry[23] ),
.CI(\carry[22] ),
.B(\B_not[22] ),
.A(A[22]));
FA_X1 U2_21 (.S(DIFF[21]),
.CO(\carry[22] ),
.CI(\carry[21] ),
.B(\B_not[21] ),
.A(A[21]));
FA_X1 U2_20 (.S(DIFF[20]),
.CO(\carry[21] ),
.CI(\carry[20] ),
.B(\B_not[20] ),
.A(A[20]));
FA_X1 U2_19 (.S(DIFF[19]),
.CO(\carry[20] ),
.CI(\carry[19] ),
.B(\B_not[19] ),
.A(A[19]));
FA_X1 U2_18 (.S(DIFF[18]),
.CO(\carry[19] ),
.CI(\carry[18] ),
.B(\B_not[18] ),
.A(A[18]));
FA_X1 U2_17 (.S(DIFF[17]),
.CO(\carry[18] ),
.CI(\carry[17] ),
.B(\B_not[17] ),
.A(A[17]));
FA_X1 U2_16 (.S(DIFF[16]),
.CO(\carry[17] ),
.CI(\carry[16] ),
.B(\B_not[16] ),
.A(A[16]));
FA_X1 U2_15 (.S(DIFF[15]),
.CO(\carry[16] ),
.CI(\carry[15] ),
.B(\B_not[15] ),
.A(A[15]));
FA_X1 U2_14 (.S(DIFF[14]),
.CO(\carry[15] ),
.CI(\carry[14] ),
.B(\B_not[14] ),
.A(A[14]));
FA_X1 U2_13 (.S(DIFF[13]),
.CO(\carry[14] ),
.CI(\carry[13] ),
.B(\B_not[13] ),
.A(A[13]));
FA_X1 U2_12 (.S(DIFF[12]),
.CO(\carry[13] ),
.CI(\carry[12] ),
.B(\B_not[12] ),
.A(A[12]));
FA_X1 U2_11 (.S(DIFF[11]),
.CO(\carry[12] ),
.CI(\carry[11] ),
.B(\B_not[11] ),
.A(A[11]));
FA_X1 U2_10 (.S(DIFF[10]),
.CO(\carry[11] ),
.CI(\carry[10] ),
.B(\B_not[10] ),
.A(A[10]));
FA_X1 U2_9 (.S(DIFF[9]),
.CO(\carry[10] ),
.CI(\carry[9] ),
.B(\B_not[9] ),
.A(A[9]));
FA_X1 U2_8 (.S(DIFF[8]),
.CO(\carry[9] ),
.CI(\carry[8] ),
.B(\B_not[8] ),
.A(A[8]));
FA_X1 U2_7 (.S(DIFF[7]),
.CO(\carry[8] ),
.CI(\carry[7] ),
.B(\B_not[7] ),
.A(A[7]));
FA_X1 U2_6 (.S(DIFF[6]),
.CO(\carry[7] ),
.CI(\carry[6] ),
.B(\B_not[6] ),
.A(A[6]));
FA_X1 U2_5 (.S(DIFF[5]),
.CO(\carry[6] ),
.CI(\carry[5] ),
.B(\B_not[5] ),
.A(A[5]));
FA_X1 U2_4 (.S(DIFF[4]),
.CO(\carry[5] ),
.CI(\carry[4] ),
.B(n1),
.A(A[4]));
FA_X1 U2_3 (.S(DIFF[3]),
.CO(\carry[4] ),
.CI(\carry[3] ),
.B(\B_not[3] ),
.A(A[3]));
FA_X1 U2_2 (.S(DIFF[2]),
.CO(\carry[3] ),
.CI(\carry[2] ),
.B(\B_not[2] ),
.A(A[2]));
FA_X1 U2_1 (.S(DIFF[1]),
.CO(\carry[2] ),
.CI(\carry[1] ),
.B(\B_not[1] ),
.A(A[1]));
XNOR2_X1 U1 (.ZN(DIFF[0]),
.B(\B_not[0] ),
.A(A[0]));
INV_X1 U2 (.ZN(\B_not[1] ),
.A(B[1]));
OR2_X1 U3 (.ZN(\carry[1] ),
.A2(A[0]),
.A1(\B_not[0] ));
INV_X1 U4 (.ZN(\B_not[2] ),
.A(B[2]));
INV_X1 U5 (.ZN(\B_not[3] ),
.A(B[3]));
INV_X1 U6 (.ZN(n1),
.A(B[4]));
INV_X1 U7 (.ZN(\B_not[5] ),
.A(B[5]));
INV_X1 U8 (.ZN(\B_not[6] ),
.A(B[6]));
INV_X1 U9 (.ZN(\B_not[7] ),
.A(B[7]));
INV_X1 U10 (.ZN(\B_not[8] ),
.A(B[8]));
INV_X1 U11 (.ZN(\B_not[9] ),
.A(B[9]));
INV_X1 U12 (.ZN(\B_not[10] ),
.A(B[10]));
INV_X1 U13 (.ZN(\B_not[11] ),
.A(B[11]));
INV_X1 U14 (.ZN(\B_not[12] ),
.A(B[12]));
INV_X1 U15 (.ZN(\B_not[13] ),
.A(B[13]));
INV_X1 U16 (.ZN(\B_not[14] ),
.A(B[14]));
INV_X1 U17 (.ZN(\B_not[15] ),
.A(B[15]));
INV_X1 U18 (.ZN(\B_not[16] ),
.A(B[16]));
INV_X1 U19 (.ZN(\B_not[17] ),
.A(B[17]));
INV_X1 U20 (.ZN(\B_not[18] ),
.A(B[18]));
INV_X1 U21 (.ZN(\B_not[19] ),
.A(B[19]));
INV_X1 U22 (.ZN(\B_not[20] ),
.A(B[20]));
INV_X1 U23 (.ZN(\B_not[21] ),
.A(B[21]));
INV_X1 U24 (.ZN(\B_not[22] ),
.A(B[22]));
INV_X1 U25 (.ZN(\B_not[23] ),
.A(B[23]));
INV_X1 U26 (.ZN(\B_not[24] ),
.A(B[24]));
INV_X1 U27 (.ZN(\B_not[25] ),
.A(B[25]));
INV_X1 U28 (.ZN(\B_not[26] ),
.A(B[26]));
INV_X1 U29 (.ZN(\B_not[27] ),
.A(B[27]));
INV_X1 U30 (.ZN(\B_not[28] ),
.A(B[28]));
INV_X1 U31 (.ZN(\B_not[29] ),
.A(B[29]));
INV_X1 U32 (.ZN(\B_not[30] ),
.A(B[30]));
INV_X1 U33 (.ZN(\B_not[0] ),
.A(B[0]));
INV_X1 U34 (.ZN(\B_not[31] ),
.A(B[31]));
endmodule
module ALU_DW01_sub_0 (
A,
B,
CI,
DIFF,
CO);
input [31:0] A;
input [31:0] B;
input CI;
output [31:0] DIFF;
output CO;
// Internal wires
wire \carry[31] ;
wire \carry[30] ;
wire \carry[29] ;
wire \carry[28] ;
wire \carry[27] ;
wire \carry[26] ;
wire \carry[25] ;
wire \carry[24] ;
wire \carry[23] ;
wire \carry[22] ;
wire \carry[21] ;
wire \carry[20] ;
wire \carry[19] ;
wire \carry[18] ;
wire \carry[17] ;
wire \carry[16] ;
wire \carry[15] ;
wire \carry[14] ;
wire \carry[13] ;
wire \carry[12] ;
wire \carry[11] ;
wire \carry[10] ;
wire \carry[9] ;
wire \carry[8] ;
wire \carry[7] ;
wire \carry[6] ;
wire \carry[5] ;
wire \carry[4] ;
wire \carry[3] ;
wire \carry[2] ;
wire \carry[1] ;
wire \B_not[31] ;
wire \B_not[30] ;
wire \B_not[29] ;
wire \B_not[28] ;
wire \B_not[27] ;
wire \B_not[26] ;
wire \B_not[25] ;
wire \B_not[24] ;
wire \B_not[23] ;
wire \B_not[22] ;
wire \B_not[21] ;
wire \B_not[20] ;
wire \B_not[19] ;
wire \B_not[18] ;
wire \B_not[17] ;
wire \B_not[16] ;
wire \B_not[15] ;
wire \B_not[14] ;
wire \B_not[13] ;
wire \B_not[12] ;
wire \B_not[11] ;
wire \B_not[10] ;
wire \B_not[9] ;
wire \B_not[8] ;
wire \B_not[7] ;
wire \B_not[6] ;
wire \B_not[5] ;
wire \B_not[3] ;
wire \B_not[2] ;
wire \B_not[1] ;
wire \B_not[0] ;
wire n1;
FA_X1 U2_31 (.S(DIFF[31]),
.CI(\carry[31] ),
.B(\B_not[31] ),
.A(A[31]));
FA_X1 U2_30 (.S(DIFF[30]),
.CO(\carry[31] ),
.CI(\carry[30] ),
.B(\B_not[30] ),
.A(A[30]));
FA_X1 U2_29 (.S(DIFF[29]),
.CO(\carry[30] ),
.CI(\carry[29] ),
.B(\B_not[29] ),
.A(A[29]));
FA_X1 U2_28 (.S(DIFF[28]),
.CO(\carry[29] ),
.CI(\carry[28] ),
.B(\B_not[28] ),
.A(A[28]));
FA_X1 U2_27 (.S(DIFF[27]),
.CO(\carry[28] ),
.CI(\carry[27] ),
.B(\B_not[27] ),
.A(A[27]));
FA_X1 U2_26 (.S(DIFF[26]),
.CO(\carry[27] ),
.CI(\carry[26] ),
.B(\B_not[26] ),
.A(A[26]));
FA_X1 U2_25 (.S(DIFF[25]),
.CO(\carry[26] ),
.CI(\carry[25] ),
.B(\B_not[25] ),
.A(A[25]));
FA_X1 U2_24 (.S(DIFF[24]),
.CO(\carry[25] ),
.CI(\carry[24] ),
.B(\B_not[24] ),
.A(A[24]));
FA_X1 U2_23 (.S(DIFF[23]),
.CO(\carry[24] ),
.CI(\carry[23] ),
.B(\B_not[23] ),
.A(A[23]));
FA_X1 U2_22 (.S(DIFF[22]),
.CO(\carry[23] ),
.CI(\carry[22] ),
.B(\B_not[22] ),
.A(A[22]));
FA_X1 U2_21 (.S(DIFF[21]),
.CO(\carry[22] ),
.CI(\carry[21] ),
.B(\B_not[21] ),
.A(A[21]));
FA_X1 U2_20 (.S(DIFF[20]),
.CO(\carry[21] ),
.CI(\carry[20] ),
.B(\B_not[20] ),
.A(A[20]));
FA_X1 U2_19 (.S(DIFF[19]),
.CO(\carry[20] ),
.CI(\carry[19] ),
.B(\B_not[19] ),
.A(A[19]));
FA_X1 U2_18 (.S(DIFF[18]),
.CO(\carry[19] ),
.CI(\carry[18] ),
.B(\B_not[18] ),
.A(A[18]));
FA_X1 U2_17 (.S(DIFF[17]),
.CO(\carry[18] ),
.CI(\carry[17] ),
.B(\B_not[17] ),
.A(A[17]));
FA_X1 U2_16 (.S(DIFF[16]),
.CO(\carry[17] ),
.CI(\carry[16] ),
.B(\B_not[16] ),
.A(A[16]));
FA_X1 U2_15 (.S(DIFF[15]),
.CO(\carry[16] ),
.CI(\carry[15] ),
.B(\B_not[15] ),
.A(A[15]));
FA_X1 U2_14 (.S(DIFF[14]),
.CO(\carry[15] ),
.CI(\carry[14] ),
.B(\B_not[14] ),
.A(A[14]));
FA_X1 U2_13 (.S(DIFF[13]),
.CO(\carry[14] ),
.CI(\carry[13] ),
.B(\B_not[13] ),
.A(A[13]));
FA_X1 U2_12 (.S(DIFF[12]),
.CO(\carry[13] ),
.CI(\carry[12] ),
.B(\B_not[12] ),
.A(A[12]));
FA_X1 U2_11 (.S(DIFF[11]),
.CO(\carry[12] ),
.CI(\carry[11] ),
.B(\B_not[11] ),
.A(A[11]));
FA_X1 U2_10 (.S(DIFF[10]),
.CO(\carry[11] ),
.CI(\carry[10] ),
.B(\B_not[10] ),
.A(A[10]));
FA_X1 U2_9 (.S(DIFF[9]),
.CO(\carry[10] ),
.CI(\carry[9] ),
.B(\B_not[9] ),
.A(A[9]));
FA_X1 U2_8 (.S(DIFF[8]),
.CO(\carry[9] ),
.CI(\carry[8] ),
.B(\B_not[8] ),
.A(A[8]));
FA_X1 U2_7 (.S(DIFF[7]),
.CO(\carry[8] ),
.CI(\carry[7] ),
.B(\B_not[7] ),
.A(A[7]));
FA_X1 U2_6 (.S(DIFF[6]),
.CO(\carry[7] ),
.CI(\carry[6] ),
.B(\B_not[6] ),
.A(A[6]));
FA_X1 U2_5 (.S(DIFF[5]),
.CO(\carry[6] ),
.CI(\carry[5] ),
.B(\B_not[5] ),
.A(A[5]));
FA_X1 U2_4 (.S(DIFF[4]),
.CO(\carry[5] ),
.CI(\carry[4] ),
.B(n1),
.A(A[4]));
FA_X1 U2_3 (.S(DIFF[3]),
.CO(\carry[4] ),
.CI(\carry[3] ),
.B(\B_not[3] ),
.A(A[3]));
FA_X1 U2_2 (.S(DIFF[2]),
.CO(\carry[3] ),
.CI(\carry[2] ),
.B(\B_not[2] ),
.A(A[2]));
FA_X1 U2_1 (.S(DIFF[1]),
.CO(\carry[2] ),
.CI(\carry[1] ),
.B(\B_not[1] ),
.A(A[1]));
XNOR2_X1 U1 (.ZN(DIFF[0]),
.B(\B_not[0] ),
.A(A[0]));
INV_X1 U2 (.ZN(\B_not[13] ),
.A(B[13]));
INV_X1 U3 (.ZN(\B_not[14] ),
.A(B[14]));
INV_X1 U4 (.ZN(\B_not[1] ),
.A(B[1]));
OR2_X1 U5 (.ZN(\carry[1] ),
.A2(A[0]),
.A1(\B_not[0] ));
INV_X1 U6 (.ZN(\B_not[2] ),
.A(B[2]));
INV_X1 U7 (.ZN(\B_not[3] ),
.A(B[3]));
INV_X1 U8 (.ZN(n1),
.A(B[4]));
INV_X1 U9 (.ZN(\B_not[5] ),
.A(B[5]));
INV_X1 U10 (.ZN(\B_not[6] ),
.A(B[6]));
INV_X1 U11 (.ZN(\B_not[7] ),
.A(B[7]));
INV_X1 U12 (.ZN(\B_not[8] ),
.A(B[8]));
INV_X1 U13 (.ZN(\B_not[9] ),
.A(B[9]));
INV_X1 U14 (.ZN(\B_not[10] ),
.A(B[10]));
INV_X1 U15 (.ZN(\B_not[11] ),
.A(B[11]));
INV_X1 U16 (.ZN(\B_not[12] ),
.A(B[12]));
INV_X1 U17 (.ZN(\B_not[15] ),
.A(B[15]));
INV_X1 U18 (.ZN(\B_not[16] ),
.A(B[16]));
INV_X1 U19 (.ZN(\B_not[17] ),
.A(B[17]));
INV_X1 U20 (.ZN(\B_not[18] ),
.A(B[18]));
INV_X1 U21 (.ZN(\B_not[19] ),
.A(B[19]));
INV_X1 U22 (.ZN(\B_not[20] ),
.A(B[20]));
INV_X1 U23 (.ZN(\B_not[21] ),
.A(B[21]));
INV_X1 U24 (.ZN(\B_not[22] ),
.A(B[22]));
INV_X1 U25 (.ZN(\B_not[23] ),
.A(B[23]));
INV_X1 U26 (.ZN(\B_not[24] ),
.A(B[24]));
INV_X1 U27 (.ZN(\B_not[25] ),
.A(B[25]));
INV_X1 U28 (.ZN(\B_not[26] ),
.A(B[26]));
INV_X1 U29 (.ZN(\B_not[27] ),
.A(B[27]));
INV_X1 U30 (.ZN(\B_not[28] ),
.A(B[28]));
INV_X1 U31 (.ZN(\B_not[29] ),
.A(B[29]));
INV_X1 U32 (.ZN(\B_not[30] ),
.A(B[30]));
INV_X1 U33 (.ZN(\B_not[0] ),
.A(B[0]));
INV_X1 U34 (.ZN(\B_not[31] ),
.A(B[31]));
endmodule
module mmu_out_iram (
from_iram,
flush,
to_if_id_reg);
input [31:0] from_iram;
input flush;
output [31:0] to_if_id_reg;
// Internal wires
wire FE_PHN127_iram_data_23_;
wire FE_PHN126_iram_data_29_;
wire FE_PHN125_iram_data_24_;
wire FE_PHN124_iram_data_10_;
wire FE_PHN123_iram_data_31_;
wire FE_PHN122_iram_data_7_;
wire FE_PHN121_iram_data_8_;
wire FE_PHN120_iram_data_6_;
wire FE_PHN119_iram_data_16_;
wire FE_PHN118_iram_data_2_;
wire FE_PHN117_iram_data_21_;
wire FE_PHN116_iram_data_20_;
wire FE_PHN115_iram_data_17_;
wire FE_PHN114_iram_data_22_;
wire FE_PHN113_iram_data_19_;
wire FE_PHN112_iram_data_18_;
wire FE_PHN108_iram_data_3_;
wire FE_PHN107_iram_data_13_;
wire FE_PHN106_iram_data_15_;
wire FE_PHN105_iram_data_5_;
wire FE_PHN104_iram_data_27_;
wire FE_PHN103_iram_data_11_;
wire FE_PHN102_iram_data_0_;
wire FE_PHN101_iram_data_1_;
wire FE_PHN100_iram_data_12_;
wire FE_PHN99_iram_data_14_;
wire FE_PHN98_iram_data_9_;
wire FE_PHN97_iram_data_4_;
wire FE_PHN96_iram_data_23_;
wire FE_PHN95_iram_data_7_;
wire FE_PHN94_iram_data_2_;
wire FE_PHN93_iram_data_22_;
wire FE_PHN92_iram_data_24_;
wire FE_PHN91_iram_data_25_;
wire FE_PHN90_iram_data_10_;
wire FE_PHN89_iram_data_31_;
wire FE_PHN88_iram_data_8_;
wire FE_PHN87_iram_data_6_;
wire FE_PHN86_iram_data_16_;
wire FE_PHN85_iram_data_29_;
wire FE_PHN84_iram_data_20_;
wire FE_PHN83_iram_data_17_;
wire FE_PHN82_iram_data_18_;
wire FE_PHN81_iram_data_21_;
wire FE_PHN80_iram_data_19_;
wire FE_PHN76_iram_data_7_;
wire FE_PHN72_iram_data_8_;
wire FE_PHN71_iram_data_6_;
wire FE_PHN70_iram_data_2_;
wire FE_PHN69_iram_data_24_;
wire FE_PHN68_iram_data_10_;
wire FE_PHN67_iram_data_17_;
wire FE_PHN66_iram_data_20_;
wire FE_PHN65_iram_data_22_;
wire FE_PHN64_iram_data_19_;
wire FE_PHN63_iram_data_31_;
wire FE_PHN62_iram_data_18_;
wire FE_PHN61_iram_data_21_;
wire FE_PHN60_iram_data_16_;
wire FE_PHN59_iram_data_15_;
wire FE_PHN58_iram_data_1_;
wire FE_PHN57_iram_data_4_;
wire FE_PHN56_iram_data_3_;
wire FE_PHN55_iram_data_13_;
wire FE_PHN54_iram_data_0_;
wire FE_PHN53_iram_data_12_;
wire FE_PHN52_iram_data_11_;
wire FE_PHN51_iram_data_5_;
wire FE_PHN50_iram_data_14_;
wire FE_PHN49_iram_data_29_;
wire FE_PHN48_iram_data_9_;
wire FE_PHN47_iram_data_23_;
wire FE_PHN46_iram_data_25_;
wire FE_PHN44_iram_data_27_;
wire FE_PHN41_iram_data_2_;
wire FE_PHN40_iram_data_8_;
wire FE_PHN39_iram_data_6_;
wire FE_PHN23_iram_data_4_;
wire FE_PHN22_iram_data_13_;
wire FE_PHN21_iram_data_11_;
wire FE_PHN20_iram_data_12_;
wire FE_PHN19_iram_data_15_;
wire FE_PHN18_iram_data_3_;
wire FE_PHN17_iram_data_7_;
wire FE_PHN16_iram_data_1_;
wire FE_PHN15_iram_data_0_;
wire FE_PHN14_iram_data_5_;
wire n2;
BUF_X1 FE_PHC127_iram_data_23_ (.Z(FE_PHN127_iram_data_23_),
.A(from_iram[23]));
BUF_X1 FE_PHC126_iram_data_29_ (.Z(FE_PHN126_iram_data_29_),
.A(from_iram[29]));
BUF_X1 FE_PHC125_iram_data_24_ (.Z(FE_PHN125_iram_data_24_),
.A(from_iram[24]));
BUF_X1 FE_PHC124_iram_data_10_ (.Z(FE_PHN124_iram_data_10_),
.A(from_iram[10]));
BUF_X1 FE_PHC123_iram_data_31_ (.Z(FE_PHN123_iram_data_31_),
.A(from_iram[31]));
BUF_X1 FE_PHC122_iram_data_7_ (.Z(FE_PHN122_iram_data_7_),
.A(from_iram[7]));
BUF_X1 FE_PHC121_iram_data_8_ (.Z(FE_PHN121_iram_data_8_),
.A(from_iram[8]));
BUF_X1 FE_PHC120_iram_data_6_ (.Z(FE_PHN120_iram_data_6_),
.A(from_iram[6]));
BUF_X1 FE_PHC119_iram_data_16_ (.Z(FE_PHN119_iram_data_16_),
.A(from_iram[16]));
BUF_X1 FE_PHC118_iram_data_2_ (.Z(FE_PHN118_iram_data_2_),
.A(from_iram[2]));
BUF_X1 FE_PHC117_iram_data_21_ (.Z(FE_PHN117_iram_data_21_),
.A(from_iram[21]));
BUF_X1 FE_PHC116_iram_data_20_ (.Z(FE_PHN116_iram_data_20_),
.A(from_iram[20]));
BUF_X1 FE_PHC115_iram_data_17_ (.Z(FE_PHN115_iram_data_17_),
.A(from_iram[17]));
BUF_X1 FE_PHC114_iram_data_22_ (.Z(FE_PHN114_iram_data_22_),
.A(from_iram[22]));
BUF_X1 FE_PHC113_iram_data_19_ (.Z(FE_PHN113_iram_data_19_),
.A(from_iram[19]));
BUF_X1 FE_PHC112_iram_data_18_ (.Z(FE_PHN112_iram_data_18_),
.A(from_iram[18]));
CLKBUF_X1 FE_PHC108_iram_data_3_ (.Z(FE_PHN108_iram_data_3_),
.A(from_iram[3]));
CLKBUF_X1 FE_PHC107_iram_data_13_ (.Z(FE_PHN107_iram_data_13_),
.A(from_iram[13]));
CLKBUF_X1 FE_PHC106_iram_data_15_ (.Z(FE_PHN106_iram_data_15_),
.A(from_iram[15]));
CLKBUF_X1 FE_PHC105_iram_data_5_ (.Z(FE_PHN105_iram_data_5_),
.A(from_iram[5]));
CLKBUF_X1 FE_PHC104_iram_data_27_ (.Z(FE_PHN104_iram_data_27_),
.A(from_iram[27]));
CLKBUF_X1 FE_PHC103_iram_data_11_ (.Z(FE_PHN103_iram_data_11_),
.A(from_iram[11]));
CLKBUF_X1 FE_PHC102_iram_data_0_ (.Z(FE_PHN102_iram_data_0_),
.A(from_iram[0]));
CLKBUF_X1 FE_PHC101_iram_data_1_ (.Z(FE_PHN101_iram_data_1_),
.A(from_iram[1]));
CLKBUF_X1 FE_PHC100_iram_data_12_ (.Z(FE_PHN100_iram_data_12_),
.A(from_iram[12]));
CLKBUF_X1 FE_PHC99_iram_data_14_ (.Z(FE_PHN99_iram_data_14_),
.A(from_iram[14]));
CLKBUF_X1 FE_PHC98_iram_data_9_ (.Z(FE_PHN98_iram_data_9_),
.A(from_iram[9]));
CLKBUF_X1 FE_PHC97_iram_data_4_ (.Z(FE_PHN97_iram_data_4_),
.A(from_iram[4]));
CLKBUF_X1 FE_PHC96_iram_data_23_ (.Z(FE_PHN96_iram_data_23_),
.A(FE_PHN127_iram_data_23_));
CLKBUF_X1 FE_PHC95_iram_data_7_ (.Z(FE_PHN95_iram_data_7_),
.A(FE_PHN122_iram_data_7_));
CLKBUF_X1 FE_PHC94_iram_data_2_ (.Z(FE_PHN94_iram_data_2_),
.A(FE_PHN118_iram_data_2_));
CLKBUF_X1 FE_PHC93_iram_data_22_ (.Z(FE_PHN93_iram_data_22_),
.A(FE_PHN114_iram_data_22_));
CLKBUF_X1 FE_PHC92_iram_data_24_ (.Z(FE_PHN92_iram_data_24_),
.A(FE_PHN125_iram_data_24_));
CLKBUF_X1 FE_PHC91_iram_data_25_ (.Z(FE_PHN91_iram_data_25_),
.A(from_iram[25]));
CLKBUF_X1 FE_PHC90_iram_data_10_ (.Z(FE_PHN90_iram_data_10_),
.A(FE_PHN124_iram_data_10_));
CLKBUF_X1 FE_PHC89_iram_data_31_ (.Z(FE_PHN89_iram_data_31_),
.A(FE_PHN123_iram_data_31_));
CLKBUF_X1 FE_PHC88_iram_data_8_ (.Z(FE_PHN88_iram_data_8_),
.A(FE_PHN121_iram_data_8_));
CLKBUF_X1 FE_PHC87_iram_data_6_ (.Z(FE_PHN87_iram_data_6_),
.A(FE_PHN120_iram_data_6_));
CLKBUF_X1 FE_PHC86_iram_data_16_ (.Z(FE_PHN86_iram_data_16_),
.A(FE_PHN119_iram_data_16_));
CLKBUF_X1 FE_PHC85_iram_data_29_ (.Z(FE_PHN85_iram_data_29_),
.A(FE_PHN126_iram_data_29_));
CLKBUF_X1 FE_PHC84_iram_data_20_ (.Z(FE_PHN84_iram_data_20_),
.A(FE_PHN116_iram_data_20_));
CLKBUF_X1 FE_PHC83_iram_data_17_ (.Z(FE_PHN83_iram_data_17_),
.A(FE_PHN115_iram_data_17_));
CLKBUF_X1 FE_PHC82_iram_data_18_ (.Z(FE_PHN82_iram_data_18_),
.A(FE_PHN112_iram_data_18_));
CLKBUF_X1 FE_PHC81_iram_data_21_ (.Z(FE_PHN81_iram_data_21_),
.A(FE_PHN117_iram_data_21_));
CLKBUF_X1 FE_PHC80_iram_data_19_ (.Z(FE_PHN80_iram_data_19_),
.A(FE_PHN113_iram_data_19_));
CLKBUF_X1 FE_PHC76_iram_data_7_ (.Z(FE_PHN76_iram_data_7_),
.A(FE_PHN95_iram_data_7_));
CLKBUF_X1 FE_PHC72_iram_data_8_ (.Z(FE_PHN72_iram_data_8_),
.A(FE_PHN88_iram_data_8_));
CLKBUF_X1 FE_PHC71_iram_data_6_ (.Z(FE_PHN71_iram_data_6_),
.A(FE_PHN87_iram_data_6_));
CLKBUF_X1 FE_PHC70_iram_data_2_ (.Z(FE_PHN70_iram_data_2_),
.A(FE_PHN94_iram_data_2_));
CLKBUF_X1 FE_PHC69_iram_data_24_ (.Z(FE_PHN69_iram_data_24_),
.A(FE_PHN92_iram_data_24_));
CLKBUF_X1 FE_PHC68_iram_data_10_ (.Z(FE_PHN68_iram_data_10_),
.A(FE_PHN90_iram_data_10_));
CLKBUF_X1 FE_PHC67_iram_data_17_ (.Z(FE_PHN67_iram_data_17_),
.A(FE_PHN83_iram_data_17_));
CLKBUF_X1 FE_PHC66_iram_data_20_ (.Z(FE_PHN66_iram_data_20_),
.A(FE_PHN84_iram_data_20_));
CLKBUF_X1 FE_PHC65_iram_data_22_ (.Z(FE_PHN65_iram_data_22_),
.A(FE_PHN93_iram_data_22_));
CLKBUF_X1 FE_PHC64_iram_data_19_ (.Z(FE_PHN64_iram_data_19_),
.A(FE_PHN80_iram_data_19_));
CLKBUF_X1 FE_PHC63_iram_data_31_ (.Z(FE_PHN63_iram_data_31_),
.A(FE_PHN89_iram_data_31_));
CLKBUF_X1 FE_PHC62_iram_data_18_ (.Z(FE_PHN62_iram_data_18_),
.A(FE_PHN82_iram_data_18_));
CLKBUF_X1 FE_PHC61_iram_data_21_ (.Z(FE_PHN61_iram_data_21_),
.A(FE_PHN81_iram_data_21_));
CLKBUF_X1 FE_PHC60_iram_data_16_ (.Z(FE_PHN60_iram_data_16_),
.A(FE_PHN86_iram_data_16_));
CLKBUF_X1 FE_PHC59_iram_data_15_ (.Z(FE_PHN59_iram_data_15_),
.A(FE_PHN106_iram_data_15_));
CLKBUF_X1 FE_PHC58_iram_data_1_ (.Z(FE_PHN58_iram_data_1_),
.A(FE_PHN101_iram_data_1_));
CLKBUF_X1 FE_PHC57_iram_data_4_ (.Z(FE_PHN57_iram_data_4_),
.A(FE_PHN97_iram_data_4_));
CLKBUF_X1 FE_PHC56_iram_data_3_ (.Z(FE_PHN56_iram_data_3_),
.A(FE_PHN108_iram_data_3_));
CLKBUF_X1 FE_PHC55_iram_data_13_ (.Z(FE_PHN55_iram_data_13_),
.A(FE_PHN107_iram_data_13_));
CLKBUF_X1 FE_PHC54_iram_data_0_ (.Z(FE_PHN54_iram_data_0_),
.A(FE_PHN102_iram_data_0_));
CLKBUF_X1 FE_PHC53_iram_data_12_ (.Z(FE_PHN53_iram_data_12_),
.A(FE_PHN100_iram_data_12_));
CLKBUF_X1 FE_PHC52_iram_data_11_ (.Z(FE_PHN52_iram_data_11_),
.A(FE_PHN103_iram_data_11_));
CLKBUF_X1 FE_PHC51_iram_data_5_ (.Z(FE_PHN51_iram_data_5_),
.A(FE_PHN105_iram_data_5_));
CLKBUF_X1 FE_PHC50_iram_data_14_ (.Z(FE_PHN50_iram_data_14_),
.A(FE_PHN99_iram_data_14_));
CLKBUF_X1 FE_PHC49_iram_data_29_ (.Z(FE_PHN49_iram_data_29_),
.A(FE_PHN85_iram_data_29_));
CLKBUF_X1 FE_PHC48_iram_data_9_ (.Z(FE_PHN48_iram_data_9_),
.A(FE_PHN98_iram_data_9_));
CLKBUF_X1 FE_PHC47_iram_data_23_ (.Z(FE_PHN47_iram_data_23_),
.A(FE_PHN96_iram_data_23_));
CLKBUF_X1 FE_PHC46_iram_data_25_ (.Z(FE_PHN46_iram_data_25_),
.A(FE_PHN91_iram_data_25_));
CLKBUF_X1 FE_PHC44_iram_data_27_ (.Z(FE_PHN44_iram_data_27_),
.A(FE_PHN104_iram_data_27_));
CLKBUF_X1 FE_PHC41_iram_data_2_ (.Z(FE_PHN41_iram_data_2_),
.A(FE_PHN70_iram_data_2_));
CLKBUF_X1 FE_PHC40_iram_data_8_ (.Z(FE_PHN40_iram_data_8_),
.A(FE_PHN72_iram_data_8_));
CLKBUF_X1 FE_PHC39_iram_data_6_ (.Z(FE_PHN39_iram_data_6_),
.A(FE_PHN71_iram_data_6_));
CLKBUF_X1 FE_PHC23_iram_data_4_ (.Z(FE_PHN23_iram_data_4_),
.A(FE_PHN57_iram_data_4_));
CLKBUF_X1 FE_PHC22_iram_data_13_ (.Z(FE_PHN22_iram_data_13_),
.A(FE_PHN55_iram_data_13_));
CLKBUF_X1 FE_PHC21_iram_data_11_ (.Z(FE_PHN21_iram_data_11_),
.A(FE_PHN52_iram_data_11_));
CLKBUF_X1 FE_PHC20_iram_data_12_ (.Z(FE_PHN20_iram_data_12_),
.A(FE_PHN53_iram_data_12_));
CLKBUF_X1 FE_PHC19_iram_data_15_ (.Z(FE_PHN19_iram_data_15_),
.A(FE_PHN59_iram_data_15_));
CLKBUF_X1 FE_PHC18_iram_data_3_ (.Z(FE_PHN18_iram_data_3_),
.A(FE_PHN56_iram_data_3_));
CLKBUF_X1 FE_PHC17_iram_data_7_ (.Z(FE_PHN17_iram_data_7_),
.A(FE_PHN76_iram_data_7_));
CLKBUF_X1 FE_PHC16_iram_data_1_ (.Z(FE_PHN16_iram_data_1_),
.A(FE_PHN58_iram_data_1_));
CLKBUF_X1 FE_PHC15_iram_data_0_ (.Z(FE_PHN15_iram_data_0_),
.A(FE_PHN54_iram_data_0_));
CLKBUF_X1 FE_PHC14_iram_data_5_ (.Z(FE_PHN14_iram_data_5_),
.A(FE_PHN51_iram_data_5_));
INV_X1 U6 (.ZN(n2),
.A(flush));
AND2_X1 U7 (.ZN(to_if_id_reg[0]),
.A2(n2),
.A1(FE_PHN15_iram_data_0_));
AND2_X1 U8 (.ZN(to_if_id_reg[1]),
.A2(n2),
.A1(FE_PHN16_iram_data_1_));
AND2_X1 U9 (.ZN(to_if_id_reg[2]),
.A2(n2),
.A1(FE_PHN41_iram_data_2_));
AND2_X1 U10 (.ZN(to_if_id_reg[3]),
.A2(n2),
.A1(FE_PHN18_iram_data_3_));
AND2_X1 U11 (.ZN(to_if_id_reg[4]),
.A2(n2),
.A1(FE_PHN23_iram_data_4_));
AND2_X1 U12 (.ZN(to_if_id_reg[5]),
.A2(n2),
.A1(FE_PHN14_iram_data_5_));
AND2_X1 U13 (.ZN(to_if_id_reg[6]),
.A2(n2),
.A1(FE_PHN39_iram_data_6_));
AND2_X1 U14 (.ZN(to_if_id_reg[7]),
.A2(n2),
.A1(FE_PHN17_iram_data_7_));
AND2_X1 U15 (.ZN(to_if_id_reg[8]),
.A2(n2),
.A1(FE_PHN40_iram_data_8_));
AND2_X1 U16 (.ZN(to_if_id_reg[9]),
.A2(n2),
.A1(FE_PHN48_iram_data_9_));
AND2_X1 U17 (.ZN(to_if_id_reg[10]),
.A2(n2),
.A1(FE_PHN68_iram_data_10_));
AND2_X1 U18 (.ZN(to_if_id_reg[11]),
.A2(n2),
.A1(FE_PHN21_iram_data_11_));
AND2_X1 U19 (.ZN(to_if_id_reg[12]),
.A2(n2),
.A1(FE_PHN20_iram_data_12_));
AND2_X1 U20 (.ZN(to_if_id_reg[13]),
.A2(n2),
.A1(FE_PHN22_iram_data_13_));
AND2_X1 U21 (.ZN(to_if_id_reg[14]),
.A2(n2),
.A1(FE_PHN50_iram_data_14_));
AND2_X1 U22 (.ZN(to_if_id_reg[15]),
.A2(n2),
.A1(FE_PHN19_iram_data_15_));
AND2_X1 U23 (.ZN(to_if_id_reg[16]),
.A2(n2),
.A1(FE_PHN60_iram_data_16_));
AND2_X1 U24 (.ZN(to_if_id_reg[17]),
.A2(n2),
.A1(FE_PHN67_iram_data_17_));
AND2_X1 U25 (.ZN(to_if_id_reg[18]),
.A2(n2),
.A1(FE_PHN62_iram_data_18_));
AND2_X1 U26 (.ZN(to_if_id_reg[19]),
.A2(n2),
.A1(FE_PHN64_iram_data_19_));
AND2_X1 U27 (.ZN(to_if_id_reg[20]),
.A2(n2),
.A1(FE_PHN66_iram_data_20_));
AND2_X1 U28 (.ZN(to_if_id_reg[21]),
.A2(n2),
.A1(FE_PHN61_iram_data_21_));
AND2_X1 U29 (.ZN(to_if_id_reg[22]),
.A2(n2),
.A1(FE_PHN65_iram_data_22_));
AND2_X1 U30 (.ZN(to_if_id_reg[23]),
.A2(n2),
.A1(FE_PHN47_iram_data_23_));
AND2_X1 U31 (.ZN(to_if_id_reg[24]),
.A2(n2),
.A1(FE_PHN69_iram_data_24_));
AND2_X1 U32 (.ZN(to_if_id_reg[25]),
.A2(n2),
.A1(FE_PHN46_iram_data_25_));
AND2_X1 U33 (.ZN(to_if_id_reg[27]),
.A2(n2),
.A1(FE_PHN44_iram_data_27_));
AND2_X1 U34 (.ZN(to_if_id_reg[29]),
.A2(n2),
.A1(FE_PHN49_iram_data_29_));
OR2_X1 U35 (.ZN(to_if_id_reg[26]),
.A2(from_iram[26]),
.A1(flush));
OR2_X1 U36 (.ZN(to_if_id_reg[28]),
.A2(from_iram[28]),
.A1(flush));
OR2_X1 U37 (.ZN(to_if_id_reg[30]),
.A2(from_iram[30]),
.A1(flush));
AND2_X1 U38 (.ZN(to_if_id_reg[31]),
.A2(n2),
.A1(FE_PHN63_iram_data_31_));
endmodule
module mmu_in_iram (
from_pc,
to_iram);
input [31:0] from_pc;
output [31:0] to_iram;
// Internal wires
wire \from_pc[31] ;
wire \from_pc[30] ;
wire \from_pc[29] ;
wire \from_pc[28] ;
wire \from_pc[27] ;
wire \from_pc[26] ;
wire \from_pc[25] ;
wire \from_pc[24] ;
wire \from_pc[23] ;
wire \from_pc[22] ;
wire \from_pc[21] ;
wire \from_pc[20] ;
wire \from_pc[19] ;
wire \from_pc[18] ;
wire \from_pc[17] ;
wire \from_pc[16] ;
wire \from_pc[15] ;
wire \from_pc[14] ;
wire \from_pc[13] ;
wire \from_pc[12] ;
wire \from_pc[11] ;
wire \from_pc[10] ;
wire \from_pc[9] ;
wire \from_pc[8] ;
wire \from_pc[7] ;
wire \from_pc[6] ;
wire \from_pc[5] ;
wire \from_pc[4] ;
wire \from_pc[3] ;
wire \from_pc[2] ;
assign to_iram[31] = 1'b0 ;
assign to_iram[30] = 1'b0 ;
assign to_iram[29] = \from_pc[31] ;
assign \from_pc[31] = from_pc[31] ;
assign to_iram[28] = \from_pc[30] ;
assign \from_pc[30] = from_pc[30] ;
assign to_iram[27] = \from_pc[29] ;
assign \from_pc[29] = from_pc[29] ;
assign to_iram[26] = \from_pc[28] ;
assign \from_pc[28] = from_pc[28] ;
assign to_iram[25] = \from_pc[27] ;
assign \from_pc[27] = from_pc[27] ;
assign to_iram[24] = \from_pc[26] ;
assign \from_pc[26] = from_pc[26] ;
assign to_iram[23] = \from_pc[25] ;
assign \from_pc[25] = from_pc[25] ;
assign to_iram[22] = \from_pc[24] ;
assign \from_pc[24] = from_pc[24] ;
assign to_iram[21] = \from_pc[23] ;
assign \from_pc[23] = from_pc[23] ;
assign to_iram[20] = \from_pc[22] ;
assign \from_pc[22] = from_pc[22] ;
assign to_iram[19] = \from_pc[21] ;
assign \from_pc[21] = from_pc[21] ;
assign to_iram[18] = \from_pc[20] ;
assign \from_pc[20] = from_pc[20] ;
assign to_iram[17] = \from_pc[19] ;
assign \from_pc[19] = from_pc[19] ;
assign to_iram[16] = \from_pc[18] ;
assign \from_pc[18] = from_pc[18] ;
assign to_iram[15] = \from_pc[17] ;
assign \from_pc[17] = from_pc[17] ;
assign to_iram[14] = \from_pc[16] ;
assign \from_pc[16] = from_pc[16] ;
assign to_iram[13] = \from_pc[15] ;
assign \from_pc[15] = from_pc[15] ;
assign to_iram[12] = \from_pc[14] ;
assign \from_pc[14] = from_pc[14] ;
assign to_iram[11] = \from_pc[13] ;
assign \from_pc[13] = from_pc[13] ;
assign to_iram[10] = \from_pc[12] ;
assign \from_pc[12] = from_pc[12] ;
assign to_iram[9] = \from_pc[11] ;
assign \from_pc[11] = from_pc[11] ;
assign to_iram[8] = \from_pc[10] ;
assign \from_pc[10] = from_pc[10] ;
assign to_iram[7] = \from_pc[9] ;
assign \from_pc[9] = from_pc[9] ;
assign to_iram[6] = \from_pc[8] ;
assign \from_pc[8] = from_pc[8] ;
assign to_iram[5] = \from_pc[7] ;
assign \from_pc[7] = from_pc[7] ;
assign to_iram[4] = \from_pc[6] ;
assign \from_pc[6] = from_pc[6] ;
assign to_iram[3] = \from_pc[5] ;
assign \from_pc[5] = from_pc[5] ;
assign to_iram[2] = \from_pc[4] ;
assign \from_pc[4] = from_pc[4] ;
assign to_iram[1] = \from_pc[3] ;
assign \from_pc[3] = from_pc[3] ;
assign to_iram[0] = \from_pc[2] ;
assign \from_pc[2] = from_pc[2] ;
endmodule
module increment_pc_DW01_add_0 (
A,
B,
CI,
SUM,
CO);
input [31:0] A;
input [31:0] B;
input CI;
output [31:0] SUM;
output CO;
// Internal wires
wire \A[1] ;
wire \A[0] ;
wire \carry[30] ;
wire \carry[29] ;
wire \carry[28] ;
wire \carry[27] ;
wire \carry[26] ;
wire \carry[25] ;
wire \carry[24] ;
wire \carry[23] ;
wire \carry[22] ;
wire \carry[21] ;
wire \carry[20] ;
wire \carry[19] ;
wire \carry[18] ;
wire \carry[17] ;
wire \carry[16] ;
wire \carry[15] ;
wire \carry[14] ;
wire \carry[13] ;
wire \carry[12] ;
wire \carry[11] ;
wire \carry[10] ;
wire \carry[9] ;
wire \carry[8] ;
wire \carry[7] ;
wire \carry[6] ;
wire \carry[5] ;
wire \carry[4] ;
wire \carry[3] ;
wire n1;
assign SUM[1] = \A[1] ;
assign \A[1] = A[1] ;
assign SUM[0] = \A[0] ;
assign \A[0] = A[0] ;
assign \carry[3] = A[2] ;
XOR2_X1 U3 (.Z(SUM[30]),
.B(\carry[30] ),
.A(A[30]));
XOR2_X1 U5 (.Z(SUM[29]),
.B(\carry[29] ),
.A(A[29]));
XOR2_X1 U7 (.Z(SUM[28]),
.B(\carry[28] ),
.A(A[28]));
XOR2_X1 U9 (.Z(SUM[27]),
.B(\carry[27] ),
.A(A[27]));
XOR2_X1 U11 (.Z(SUM[26]),
.B(\carry[26] ),
.A(A[26]));
XOR2_X1 U13 (.Z(SUM[25]),
.B(\carry[25] ),
.A(A[25]));
XOR2_X1 U15 (.Z(SUM[24]),
.B(\carry[24] ),
.A(A[24]));
XOR2_X1 U17 (.Z(SUM[23]),
.B(\carry[23] ),
.A(A[23]));
XOR2_X1 U19 (.Z(SUM[22]),
.B(\carry[22] ),
.A(A[22]));
XOR2_X1 U21 (.Z(SUM[21]),
.B(\carry[21] ),
.A(A[21]));
XOR2_X1 U23 (.Z(SUM[20]),
.B(\carry[20] ),
.A(A[20]));
XOR2_X1 U25 (.Z(SUM[19]),
.B(\carry[19] ),
.A(A[19]));
XOR2_X1 U27 (.Z(SUM[18]),
.B(\carry[18] ),
.A(A[18]));
XOR2_X1 U29 (.Z(SUM[17]),
.B(\carry[17] ),
.A(A[17]));
XOR2_X1 U31 (.Z(SUM[16]),
.B(\carry[16] ),
.A(A[16]));
XOR2_X1 U33 (.Z(SUM[15]),
.B(\carry[15] ),
.A(A[15]));
XOR2_X1 U35 (.Z(SUM[14]),
.B(\carry[14] ),
.A(A[14]));
XOR2_X1 U37 (.Z(SUM[13]),
.B(\carry[13] ),
.A(A[13]));
XOR2_X1 U39 (.Z(SUM[12]),
.B(\carry[12] ),
.A(A[12]));
XOR2_X1 U41 (.Z(SUM[11]),
.B(\carry[11] ),
.A(A[11]));
XOR2_X1 U43 (.Z(SUM[10]),
.B(\carry[10] ),
.A(A[10]));
XOR2_X1 U45 (.Z(SUM[9]),
.B(\carry[9] ),
.A(A[9]));
XOR2_X1 U47 (.Z(SUM[8]),
.B(\carry[8] ),
.A(A[8]));
XOR2_X1 U49 (.Z(SUM[7]),
.B(\carry[7] ),
.A(A[7]));
XOR2_X1 U51 (.Z(SUM[6]),
.B(\carry[6] ),
.A(A[6]));
XOR2_X1 U53 (.Z(SUM[5]),
.B(\carry[5] ),
.A(A[5]));
XOR2_X1 U55 (.Z(SUM[4]),
.B(\carry[4] ),
.A(A[4]));
XOR2_X1 U57 (.Z(SUM[3]),
.B(\carry[3] ),
.A(A[3]));
XNOR2_X1 U1 (.ZN(SUM[31]),
.B(n1),
.A(A[31]));
NAND2_X1 U2 (.ZN(n1),
.A2(A[30]),
.A1(\carry[30] ));
AND2_X1 U4 (.ZN(\carry[4] ),
.A2(A[3]),
.A1(\carry[3] ));
AND2_X1 U6 (.ZN(\carry[5] ),
.A2(A[4]),
.A1(\carry[4] ));
AND2_X1 U8 (.ZN(\carry[6] ),
.A2(A[5]),
.A1(\carry[5] ));
AND2_X1 U10 (.ZN(\carry[7] ),
.A2(A[6]),
.A1(\carry[6] ));
AND2_X1 U12 (.ZN(\carry[8] ),
.A2(A[7]),
.A1(\carry[7] ));
AND2_X1 U14 (.ZN(\carry[9] ),
.A2(A[8]),
.A1(\carry[8] ));
AND2_X1 U16 (.ZN(\carry[10] ),
.A2(A[9]),
.A1(\carry[9] ));
AND2_X1 U18 (.ZN(\carry[11] ),
.A2(A[10]),
.A1(\carry[10] ));
AND2_X1 U20 (.ZN(\carry[12] ),
.A2(A[11]),
.A1(\carry[11] ));
AND2_X1 U22 (.ZN(\carry[13] ),
.A2(A[12]),
.A1(\carry[12] ));
AND2_X1 U24 (.ZN(\carry[14] ),
.A2(A[13]),
.A1(\carry[13] ));
AND2_X1 U26 (.ZN(\carry[15] ),
.A2(A[14]),
.A1(\carry[14] ));
AND2_X1 U28 (.ZN(\carry[16] ),
.A2(A[15]),
.A1(\carry[15] ));
AND2_X1 U30 (.ZN(\carry[17] ),
.A2(A[16]),
.A1(\carry[16] ));
AND2_X1 U32 (.ZN(\carry[18] ),
.A2(A[17]),
.A1(\carry[17] ));
AND2_X1 U34 (.ZN(\carry[19] ),
.A2(A[18]),
.A1(\carry[18] ));
AND2_X1 U36 (.ZN(\carry[20] ),
.A2(A[19]),
.A1(\carry[19] ));
AND2_X1 U38 (.ZN(\carry[21] ),
.A2(A[20]),
.A1(\carry[20] ));
AND2_X1 U40 (.ZN(\carry[22] ),
.A2(A[21]),
.A1(\carry[21] ));
AND2_X1 U42 (.ZN(\carry[23] ),
.A2(A[22]),
.A1(\carry[22] ));
AND2_X1 U44 (.ZN(\carry[24] ),
.A2(A[23]),
.A1(\carry[23] ));
AND2_X1 U46 (.ZN(\carry[25] ),
.A2(A[24]),
.A1(\carry[24] ));
AND2_X1 U48 (.ZN(\carry[26] ),
.A2(A[25]),
.A1(\carry[25] ));
AND2_X1 U50 (.ZN(\carry[27] ),
.A2(A[26]),
.A1(\carry[26] ));
AND2_X1 U52 (.ZN(\carry[28] ),
.A2(A[27]),
.A1(\carry[27] ));
AND2_X1 U54 (.ZN(\carry[29] ),
.A2(A[28]),
.A1(\carry[28] ));
AND2_X1 U56 (.ZN(\carry[30] ),
.A2(A[29]),
.A1(\carry[29] ));
INV_X1 U58 (.ZN(SUM[2]),
.A(\carry[3] ));
endmodule
module dram_block (
address,
data_write,
mem_op,
Data_out,
unaligned,
data_read,
read_op,
write_op,
nibble,
write_byte,
Address_toRAM,
Data_in);
input [31:0] address;
input [31:0] data_write;
input [5:0] mem_op;
input [31:0] Data_out;
output unaligned;
output [31:0] data_read;
output read_op;
output write_op;
output [1:0] nibble;
output write_byte;
output [31:0] Address_toRAM;
output [31:0] Data_in;
// Internal wires
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
assign Address_toRAM[31] = 1'b0 ;
assign Address_toRAM[30] = 1'b0 ;
mmu_in_dram mmu_in0 (.mem_op(mem_op),
.aligned_address(address),
.data(data_write),
.unaligned(unaligned),
.nibble(nibble),
.write_op(write_op),
.read_op(read_op),
.mem_address({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
Address_toRAM[29],
Address_toRAM[28],
Address_toRAM[27],
Address_toRAM[26],
Address_toRAM[25],
Address_toRAM[24],
Address_toRAM[23],
Address_toRAM[22],
Address_toRAM[21],
Address_toRAM[20],
Address_toRAM[19],
Address_toRAM[18],
Address_toRAM[17],
Address_toRAM[16],
Address_toRAM[15],
Address_toRAM[14],
Address_toRAM[13],
Address_toRAM[12],
Address_toRAM[11],
Address_toRAM[10],
Address_toRAM[9],
Address_toRAM[8],
Address_toRAM[7],
Address_toRAM[6],
Address_toRAM[5],
Address_toRAM[4],
Address_toRAM[3],
Address_toRAM[2],
Address_toRAM[1],
Address_toRAM[0] }),
.mem_data(Data_in),
.write_byte(write_byte));
mmu_out_dram mmu_out0 (.data_ram(Data_out),
.mem_op(mem_op),
.nibble(nibble),
.unaligned(unaligned),
.data_read(data_read));
endmodule
module ALU (
alu_op,
a,
b,
ovf,
zero,
res);
input [4:0] alu_op;
input [31:0] a;
input [31:0] b;
output ovf;
output zero;
output [31:0] res;
// Internal wires
wire FE_OFN9_n274;
wire FE_OFN8_n188;
wire FE_OFN3_n325;
wire FE_OFN2_n322;
wire FE_OFN1_n187;
wire N529;
wire N530;
wire N531;
wire N532;
wire N533;
wire N534;
wire N535;
wire N536;
wire N537;
wire N538;
wire N539;
wire N540;
wire N541;
wire N542;
wire N543;
wire N544;
wire N545;
wire N546;
wire N547;
wire N548;
wire N549;
wire N550;
wire N551;
wire N552;
wire N553;
wire N554;
wire N555;
wire N556;
wire N557;
wire N558;
wire N559;
wire N560;
wire N562;
wire N563;
wire N564;
wire N565;
wire N566;
wire N567;
wire N568;
wire N569;
wire N570;
wire N571;
wire N572;
wire N573;
wire N574;
wire N575;
wire N576;
wire N577;
wire N578;
wire N579;
wire N580;
wire N581;
wire N582;
wire N583;
wire N584;
wire N585;
wire N586;
wire N587;
wire N588;
wire N589;
wire N590;
wire N591;
wire N592;
wire N593;
wire N594;
wire N595;
wire N596;
wire N597;
wire N598;
wire N599;
wire N600;
wire N601;
wire N602;
wire N603;
wire N604;
wire N605;
wire N606;
wire N607;
wire N608;
wire N609;
wire N610;
wire N611;
wire N612;
wire N613;
wire N614;
wire N615;
wire N616;
wire N617;
wire N618;
wire N619;
wire N620;
wire N621;
wire N622;
wire N623;
wire N624;
wire N625;
wire N629;
wire N630;
wire N631;
wire N632;
wire N633;
wire N634;
wire N635;
wire N636;
wire N637;
wire N638;
wire N639;
wire N640;
wire N641;
wire N642;
wire N643;
wire N644;
wire N645;
wire N646;
wire N647;
wire N648;
wire N649;
wire N650;
wire N651;
wire N652;
wire N653;
wire N654;
wire N655;
wire N656;
wire N657;
wire N658;
wire N659;
wire N660;
wire N757;
wire N758;
wire N759;
wire N760;
wire N761;
wire N762;
wire N763;
wire N764;
wire N765;
wire n694;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n196;
wire n197;
wire n198;
wire n199;
wire n200;
wire n202;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n212;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n224;
wire n225;
wire n226;
wire n227;
wire n228;
wire n229;
wire n230;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n253;
wire n254;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
wire n260;
wire n261;
wire n262;
wire n263;
wire n264;
wire n265;
wire n266;
wire n267;
wire n268;
wire n269;
wire n270;
wire n271;
wire n272;
wire n273;
wire n274;
wire n275;
wire n276;
wire n277;
wire n278;
wire n279;
wire n280;
wire n281;
wire n282;
wire n283;
wire n284;
wire n285;
wire n286;
wire n287;
wire n288;
wire n289;
wire n290;
wire n291;
wire n292;
wire n293;
wire n294;
wire n295;
wire n296;
wire n297;
wire n298;
wire n299;
wire n300;
wire n301;
wire n302;
wire n303;
wire n304;
wire n305;
wire n306;
wire n307;
wire n308;
wire n309;
wire n310;
wire n311;
wire n312;
wire n313;
wire n314;
wire n315;
wire n316;
wire n317;
wire n318;
wire n319;
wire n320;
wire n321;
wire n322;
wire n324;
wire n325;
wire n326;
wire n327;
wire n328;
wire n329;
wire n330;
wire n331;
wire n332;
wire n333;
wire n334;
wire n335;
wire n336;
wire n337;
wire n338;
wire n339;
wire n340;
wire n341;
wire n342;
wire n343;
wire n344;
wire n345;
wire n346;
wire n348;
wire n349;
wire n350;
wire n351;
wire n352;
wire n353;
wire n354;
wire n355;
wire n356;
wire n357;
wire n358;
wire n359;
wire n361;
wire n362;
wire n363;
wire n364;
wire n365;
wire n366;
wire n367;
wire n368;
wire n369;
wire n370;
wire n371;
wire n372;
wire n373;
wire n374;
wire n375;
wire n376;
wire n377;
wire n378;
wire n379;
wire n380;
wire n381;
wire n382;
wire n383;
wire n384;
wire n385;
wire n386;
wire n387;
wire n388;
wire n389;
wire n390;
wire n391;
wire n392;
wire n393;
wire n394;
wire n395;
wire n396;
wire n397;
wire n398;
wire n399;
wire n400;
wire n401;
wire n402;
wire n403;
wire n404;
wire n405;
wire n406;
wire n407;
wire n408;
wire n409;
wire n410;
wire n411;
wire n412;
wire n413;
wire n414;
wire n415;
wire n416;
wire n417;
wire n418;
wire n419;
wire n420;
wire n421;
wire n422;
wire n423;
wire n424;
wire n425;
wire n426;
wire n427;
wire n428;
wire n429;
wire n430;
wire n431;
wire n432;
wire n433;
wire n434;
wire n435;
wire n436;
wire n437;
wire n438;
wire n439;
wire n440;
wire n441;
wire n442;
wire n443;
wire n444;
wire n445;
wire n446;
wire n447;
wire n448;
wire n449;
wire n450;
wire n451;
wire n452;
wire n453;
wire n454;
wire n455;
wire n456;
wire n457;
wire n458;
wire n459;
wire n460;
wire n461;
wire n462;
wire n463;
wire n464;
wire n465;
wire n466;
wire n467;
wire n468;
wire n469;
wire n470;
wire n471;
wire n472;
wire n473;
wire n474;
wire n475;
wire n476;
wire n477;
wire n478;
wire n479;
wire n480;
wire n481;
wire n482;
wire n483;
wire n484;
wire n485;
wire n486;
wire n487;
wire n488;
wire n489;
wire n490;
wire n491;
wire n492;
wire n493;
wire n494;
wire n495;
wire n496;
wire n497;
wire n498;
wire n499;
wire n500;
wire n501;
wire n502;
wire n503;
wire n504;
wire n505;
wire n506;
wire n507;
wire n508;
wire n509;
wire n510;
wire n511;
wire n512;
wire n513;
wire n514;
wire n515;
wire n516;
wire n517;
wire n518;
wire n519;
wire n520;
wire n521;
wire n522;
wire n523;
wire n524;
wire n525;
wire n526;
wire n527;
wire n528;
wire n529;
wire n530;
wire n531;
wire n532;
wire n533;
wire n534;
wire n535;
wire n536;
wire n537;
wire n538;
wire n539;
wire n540;
wire n541;
wire n542;
wire n543;
wire n544;
wire n545;
wire n546;
wire n547;
wire n548;
wire n549;
wire n550;
wire n551;
wire n552;
wire n553;
wire n554;
wire n555;
wire n556;
wire n557;
wire n558;
wire n559;
wire n560;
wire n561;
wire n562;
wire n563;
wire n564;
wire n565;
wire n566;
wire n567;
wire n568;
wire n569;
wire n570;
wire n571;
wire n572;
wire n573;
wire n574;
wire n575;
wire n576;
wire n577;
wire n578;
wire n579;
wire n580;
wire n581;
wire n582;
wire n583;
wire n584;
wire n585;
wire n586;
wire n587;
wire n588;
wire n589;
wire n590;
wire n591;
wire n592;
wire n593;
wire n594;
wire n595;
wire n596;
wire n597;
wire n598;
wire n599;
wire n600;
wire n601;
wire n602;
wire n603;
wire n604;
wire n605;
wire n606;
wire n607;
wire n608;
wire n609;
wire n610;
wire n611;
wire n612;
wire n613;
wire n614;
wire n615;
wire n616;
wire n617;
wire n618;
wire n619;
wire n620;
wire n621;
wire n622;
wire n623;
wire n624;
wire n625;
wire n626;
wire n627;
wire n628;
wire n629;
wire n630;
wire n631;
wire n632;
wire n633;
wire n634;
wire n635;
wire n636;
wire n637;
wire n638;
wire n639;
wire n640;
wire n641;
wire n642;
wire n643;
wire n644;
wire n645;
wire n646;
wire n647;
wire n648;
wire n649;
wire n650;
wire n651;
wire n652;
wire n653;
wire n654;
wire n655;
wire n656;
wire n657;
wire n658;
wire n659;
wire n660;
wire n661;
wire n662;
wire n663;
wire n664;
wire n665;
wire n666;
wire n667;
wire n668;
wire n669;
wire n670;
wire n671;
wire n672;
wire n673;
wire n674;
wire n675;
wire n676;
wire n678;
wire n679;
wire n680;
wire n681;
wire n682;
wire n683;
wire n684;
wire n685;
wire n686;
wire n687;
wire n688;
wire n689;
wire n690;
wire n691;
wire n692;
wire n693;
wire n695;
wire n696;
wire n697;
wire n698;
wire n699;
wire n700;
wire n701;
wire n702;
wire n703;
wire n704;
wire n705;
wire n706;
wire n707;
wire n708;
wire n709;
wire n710;
wire n711;
wire n712;
wire n713;
wire n714;
wire n716;
wire n717;
wire n718;
wire n719;
wire n720;
wire n721;
wire n722;
wire n723;
wire n724;
wire n725;
wire n726;
wire n727;
wire n728;
wire n729;
wire n730;
wire n731;
wire n732;
wire n733;
wire n734;
wire n735;
wire n736;
wire n737;
wire n738;
wire n739;
wire n740;
wire n741;
wire n742;
wire n743;
wire n744;
wire n745;
wire n746;
wire n747;
wire n748;
wire n749;
wire n750;
wire n751;
wire n752;
wire n753;
wire n754;
wire n755;
wire n756;
wire n757;
wire n758;
wire n759;
wire n760;
wire n761;
wire n762;
wire n763;
wire n764;
wire n765;
wire n766;
wire n767;
wire n768;
wire n769;
wire n770;
wire n771;
wire n772;
wire n773;
wire n774;
wire n775;
wire n776;
wire n777;
wire n778;
wire n779;
wire n780;
wire n781;
wire n782;
wire n783;
wire n784;
wire n785;
wire n786;
wire n787;
wire n788;
wire n789;
wire n790;
wire n791;
wire n792;
wire n793;
wire n794;
wire n795;
wire n796;
wire n797;
wire n798;
wire n799;
wire n800;
wire n801;
wire n802;
wire n803;
wire n804;
wire n805;
wire n806;
wire n807;
wire n808;
wire n809;
wire n810;
wire n811;
wire n812;
wire n813;
wire n814;
wire n815;
wire n816;
wire n817;
wire n818;
wire n819;
wire n820;
wire n821;
wire n822;
wire n823;
wire n824;
wire n825;
wire n826;
wire n827;
wire n831;
wire n715;
wire n834;
wire n865;
wire n868;
wire n872;
wire n885;
wire n887;
wire n889;
wire n892;
wire n899;
assign n694 = b[4] ;
CLKBUF_X1 FE_OFC9_n274 (.Z(FE_OFN9_n274),
.A(n274));
CLKBUF_X1 FE_OFC8_n188 (.Z(FE_OFN8_n188),
.A(n188));
CLKBUF_X2 FE_OFC3_n325 (.Z(FE_OFN3_n325),
.A(n325));
CLKBUF_X2 FE_OFC2_n322 (.Z(FE_OFN2_n322),
.A(n322));
CLKBUF_X2 FE_OFC1_n187 (.Z(FE_OFN1_n187),
.A(n187));
NOR2_X2 U567 (.ZN(n191),
.A2(n357),
.A1(n306));
NAND3_X1 U713 (.ZN(res[31]),
.A3(n334),
.A2(n333),
.A1(n332));
NAND3_X1 U714 (.ZN(n471),
.A3(n472),
.A2(n359),
.A1(a[31]));
NAND3_X1 U715 (.ZN(n734),
.A3(n439),
.A2(n736),
.A1(n299));
OAI33_X1 U716 (.ZN(n789),
.B3(n794),
.B2(n793),
.B1(n792),
.A3(n791),
.A2(alu_op[4]),
.A1(n790));
ALU_DW01_sub_0 sub_76 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.CI(1'b0),
.DIFF({ N660,
N659,
N658,
N657,
N656,
N655,
N654,
N653,
N652,
N651,
N650,
N649,
N648,
N647,
N646,
N645,
N644,
N643,
N642,
N641,
N640,
N639,
N638,
N637,
N636,
N635,
N634,
N633,
N632,
N631,
N630,
N629 }));
ALU_DW01_sub_1 sub_67 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.CI(1'b0),
.DIFF({ N625,
N624,
N623,
N622,
N621,
N620,
N619,
N618,
N617,
N616,
N615,
N614,
N613,
N612,
N611,
N610,
N609,
N608,
N607,
N606,
N605,
N604,
N603,
N602,
N601,
N600,
N599,
N598,
N597,
N596,
N595,
N594 }));
ALU_DW01_add_0 add_64 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.CI(1'b0),
.SUM({ N593,
N592,
N591,
N590,
N589,
N588,
N587,
N586,
N585,
N584,
N583,
N582,
N581,
N580,
N579,
N578,
N577,
N576,
N575,
N574,
N573,
N572,
N571,
N570,
N569,
N568,
N567,
N566,
N565,
N564,
N563,
N562 }));
ALU_DW01_add_1 add_60 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.CI(1'b0),
.SUM({ N560,
N559,
N558,
N557,
N556,
N555,
N554,
N553,
N552,
N551,
N550,
N549,
N548,
N547,
N546,
N545,
N544,
N543,
N542,
N541,
N540,
N539,
N538,
N537,
N536,
N535,
N534,
N533,
N532,
N531,
N530,
N529 }));
ALU_DW01_cmp6_0 r95 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.TC(1'b1),
.LT(N759),
.GT(N760),
.LE(N761),
.GE(N762));
ALU_DW01_cmp6_1 r94 (.A(a),
.B({ b[31],
b[30],
b[29],
b[28],
b[27],
b[26],
b[25],
b[24],
b[23],
b[22],
b[21],
b[20],
b[19],
b[18],
b[17],
b[16],
b[15],
b[14],
b[13],
b[12],
b[11],
b[10],
b[9],
b[8],
b[7],
b[6],
b[5],
n694,
b[3],
b[2],
b[1],
b[0] }),
.TC(1'b0),
.LT(N763),
.GT(N764),
.EQ(N757),
.GE(N765),
.NE(N758));
AOI221_X1 U6 (.ZN(n521),
.C2(a[25]),
.C1(n865),
.B2(a[26]),
.B1(n344),
.A(n815));
OAI222_X1 U7 (.ZN(n274),
.C2(n401),
.C1(n834),
.B2(n774),
.B1(n326),
.A2(n609),
.A1(FE_OFN3_n325));
OAI221_X1 U8 (.ZN(n275),
.C2(n290),
.C1(FE_OFN3_n325),
.B2(n304),
.B1(n326),
.A(n779));
NOR2_X1 U9 (.ZN(n310),
.A2(n737),
.A1(n624));
NOR2_X1 U10 (.ZN(n472),
.A2(n694),
.A1(n362));
INV_X1 U11 (.ZN(n200),
.A(n321));
INV_X1 U14 (.ZN(n695),
.A(n735));
INV_X1 U20 (.ZN(n230),
.A(n198));
INV_X1 U24 (.ZN(n229),
.A(n191));
NAND2_X1 U25 (.ZN(n321),
.A2(n592),
.A1(n439));
INV_X1 U26 (.ZN(n225),
.A(n208));
NOR2_X1 U27 (.ZN(n682),
.A2(n359),
.A1(n183));
INV_X1 U28 (.ZN(n468),
.A(n487));
INV_X1 U29 (.ZN(n885),
.A(n715));
NOR2_X1 U30 (.ZN(n735),
.A2(n439),
.A1(n470));
INV_X1 U31 (.ZN(n232),
.A(n206));
NAND2_X1 U32 (.ZN(n299),
.A2(n752),
.A1(n183));
INV_X1 U39 (.ZN(n361),
.A(n372));
INV_X1 U40 (.ZN(n359),
.A(n439));
INV_X1 U41 (.ZN(n357),
.A(n351));
NOR2_X1 U47 (.ZN(n487),
.A2(n306),
.A1(n639));
NOR2_X1 U48 (.ZN(n198),
.A2(n461),
.A1(n306));
NAND2_X1 U49 (.ZN(n206),
.A2(n592),
.A1(n351));
INV_X1 U50 (.ZN(n193),
.A(n279));
NOR4_X1 U51 (.ZN(n167),
.A4(res[13]),
.A3(res[14]),
.A2(res[15]),
.A1(res[16]));
NOR2_X1 U52 (.ZN(n369),
.A2(n359),
.A1(n463));
INV_X1 U53 (.ZN(n470),
.A(n309));
NAND2_X1 U54 (.ZN(n208),
.A2(n592),
.A1(n310));
NAND2_X1 U55 (.ZN(n592),
.A2(n458),
.A1(n463));
OAI22_X1 U56 (.ZN(n697),
.B2(n229),
.B1(n387),
.A2(n715),
.A1(n388));
OAI22_X1 U57 (.ZN(n676),
.B2(n229),
.B1(n356),
.A2(n715),
.A1(n358));
OAI22_X1 U58 (.ZN(n227),
.B2(n231),
.B1(n230),
.A2(n229),
.A1(n228));
OAI22_X1 U59 (.ZN(n780),
.B2(n206),
.B1(n278),
.A2(n752),
.A1(n490));
OAI22_X1 U60 (.ZN(n700),
.B2(n206),
.B1(n701),
.A2(n321),
.A1(n278));
OAI22_X1 U61 (.ZN(n656),
.B2(n230),
.B1(n423),
.A2(n468),
.A1(n571));
OAI22_X1 U62 (.ZN(n630),
.B2(n230),
.B1(n356),
.A2(n468),
.A1(n462));
OAI22_X1 U63 (.ZN(n596),
.B2(n230),
.B1(n597),
.A2(n468),
.A1(n519));
OAI22_X1 U64 (.ZN(n489),
.B2(n230),
.B1(n491),
.A2(n463),
.A1(n490));
OAI22_X1 U65 (.ZN(n467),
.B2(n230),
.B1(n469),
.A2(n468),
.A1(n358));
OAI22_X1 U66 (.ZN(n276),
.B2(n279),
.B1(n278),
.A2(n206),
.A1(n277));
OAI22_X1 U67 (.ZN(n775),
.B2(n279),
.B1(n701),
.A2(n321),
.A1(n277));
OAI22_X1 U68 (.ZN(n743),
.B2(n279),
.B1(n593),
.A2(n321),
.A1(n744));
OAI22_X1 U69 (.ZN(n675),
.B2(n230),
.B1(n462),
.A2(n468),
.A1(n460));
OAI22_X1 U70 (.ZN(n292),
.B2(n208),
.B1(n293),
.A2(n279),
.A1(n205));
OAI22_X1 U71 (.ZN(n258),
.B2(n208),
.B1(n260),
.A2(n206),
.A1(n259));
OAI22_X1 U72 (.ZN(n761),
.B2(n321),
.B1(n259),
.A2(n715),
.A1(n356));
INV_X1 U73 (.ZN(n183),
.A(n221));
OR2_X1 U74 (.ZN(n715),
.A2(n359),
.A1(n306));
INV_X1 U75 (.ZN(n752),
.A(n179));
AOI21_X1 U76 (.ZN(n431),
.B2(n361),
.B1(n432),
.A(n433));
INV_X1 U77 (.ZN(n432),
.A(n369));
INV_X1 U78 (.ZN(n532),
.A(n549));
INV_X1 U79 (.ZN(n533),
.A(n548));
NOR2_X1 U80 (.ZN(n372),
.A2(n434),
.A1(n343));
OAI22_X1 U81 (.ZN(n531),
.B2(n533),
.B1(n460),
.A2(n532),
.A1(n462));
NAND2_X1 U86 (.ZN(n693),
.A2(n439),
.A1(n179));
INV_X1 U89 (.ZN(n887),
.A(n190));
INV_X2 U90 (.ZN(n211),
.A(n827));
INV_X2 U91 (.ZN(n209),
.A(n826));
OAI22_X1 U98 (.ZN(n537),
.B2(n359),
.B1(n541),
.A2(n357),
.A1(n540));
INV_X1 U99 (.ZN(n639),
.A(n310));
OAI22_X1 U100 (.ZN(n422),
.B2(n359),
.B1(n424),
.A2(n357),
.A1(n423));
OAI22_X1 U101 (.ZN(n386),
.B2(n359),
.B1(n388),
.A2(n357),
.A1(n387));
OAI22_X1 U102 (.ZN(n355),
.B2(n359),
.B1(n358),
.A2(n357),
.A1(n356));
OAI21_X1 U103 (.ZN(n611),
.B2(n639),
.B1(n576),
.A(n653));
OAI21_X1 U104 (.ZN(n610),
.B2(n639),
.B1(n580),
.A(n653));
OAI21_X1 U105 (.ZN(n284),
.B2(n461),
.B1(n576),
.A(n577));
INV_X1 U106 (.ZN(n580),
.A(n410));
INV_X1 U107 (.ZN(n231),
.A(n661));
INV_X1 U108 (.ZN(n576),
.A(n412));
OR2_X1 U110 (.ZN(n217),
.A2(n503),
.A1(n220));
OR2_X1 U111 (.ZN(n255),
.A2(n503),
.A1(n537));
NOR2_X1 U114 (.ZN(n179),
.A2(n308),
.A1(n362));
NOR2_X1 U115 (.ZN(n221),
.A2(n434),
.A1(n308));
NOR2_X1 U116 (.ZN(n309),
.A2(n712),
.A1(n752));
NOR2_X1 U117 (.ZN(n549),
.A2(n359),
.A1(n478));
AOI222_X1 U118 (.ZN(n282),
.C2(n199),
.C1(n232),
.B2(n291),
.B1(n200),
.A2(n197),
.A1(n191));
AOI222_X1 U119 (.ZN(n297),
.C2(n237),
.C1(n225),
.B2(n310),
.B1(n309),
.A2(n233),
.A1(n193));
AOI222_X1 U120 (.ZN(n599),
.C2(n197),
.C1(n885),
.B2(n294),
.B1(n225),
.A2(n203),
.A1(N563));
NOR4_X1 U121 (.ZN(n173),
.A4(res[6]),
.A3(res[7]),
.A2(res[8]),
.A1(res[9]));
NOR4_X1 U122 (.ZN(n169),
.A4(res[20]),
.A3(res[21]),
.A2(res[22]),
.A1(res[23]));
NOR4_X1 U123 (.ZN(n168),
.A4(res[17]),
.A3(res[18]),
.A2(res[19]),
.A1(res[1]));
AOI221_X1 U124 (.ZN(n513),
.C2(n220),
.C1(n515),
.B2(n514),
.B1(n452),
.A(n516));
OAI222_X1 U125 (.ZN(n514),
.C2(n231),
.C1(n461),
.B2(n357),
.B1(n228),
.A2(n359),
.A1(n519));
OAI21_X1 U126 (.ZN(n516),
.B2(n485),
.B1(n517),
.A(n470));
INV_X1 U127 (.ZN(n517),
.A(n518));
AOI221_X1 U128 (.ZN(n176),
.C2(n194),
.C1(n193),
.B2(n192),
.B1(n191),
.A(n195));
INV_X1 U129 (.ZN(n195),
.A(n196));
AOI22_X1 U130 (.ZN(n196),
.B2(n200),
.B1(n199),
.A2(n198),
.A1(n197));
AOI221_X1 U131 (.ZN(n672),
.C2(n254),
.C1(n200),
.B2(n626),
.B1(n193),
.A(n685));
OAI22_X1 U132 (.ZN(n685),
.B2(n206),
.B1(n260),
.A2(n208),
.A1(n540));
AOI221_X1 U133 (.ZN(n545),
.C2(n203),
.C1(N584),
.B2(n483),
.B1(n487),
.A(n564));
OAI22_X1 U134 (.ZN(n564),
.B2(n229),
.B1(n491),
.A2(n230),
.A1(n388));
AOI221_X1 U135 (.ZN(n566),
.C2(n203),
.C1(N583),
.B2(n202),
.B1(n487),
.A(n582));
OAI22_X1 U136 (.ZN(n582),
.B2(n229),
.B1(n508),
.A2(n230),
.A1(n424));
AOI221_X1 U137 (.ZN(n213),
.C2(n203),
.C1(N570),
.B2(n233),
.B1(n232),
.A(n234));
INV_X1 U138 (.ZN(n234),
.A(n235));
AOI22_X1 U139 (.ZN(n235),
.B2(n193),
.B1(n237),
.A2(n200),
.A1(n236));
AOI221_X1 U140 (.ZN(n527),
.C2(n203),
.C1(N585),
.B2(n542),
.B1(n487),
.A(n543));
OAI22_X1 U141 (.ZN(n543),
.B2(n229),
.B1(n469),
.A2(n230),
.A1(n358));
NOR4_X1 U142 (.ZN(n166),
.A4(res[0]),
.A3(res[10]),
.A2(res[11]),
.A1(res[12]));
AOI21_X1 U143 (.ZN(n188),
.B2(n800),
.B1(n807),
.A(n887));
NAND2_X1 U144 (.ZN(n279),
.A2(n592),
.A1(n353));
OAI22_X1 U145 (.ZN(n507),
.B2(n229),
.B1(n509),
.A2(n230),
.A1(n508));
INV_X1 U146 (.ZN(n509),
.A(n421));
OAI22_X1 U147 (.ZN(n720),
.B2(n206),
.B1(n293),
.A2(n279),
.A1(n207));
OAI22_X1 U148 (.ZN(n204),
.B2(n208),
.B1(n207),
.A2(n206),
.A1(n205));
OAI22_X1 U149 (.ZN(n716),
.B2(n230),
.B1(n571),
.A2(n468),
.A1(n572));
NAND2_X1 U150 (.ZN(n306),
.A2(n308),
.A1(n338));
OAI22_X1 U151 (.ZN(n740),
.B2(n715),
.B1(n597),
.A2(n208),
.A1(n521));
OAI22_X1 U152 (.ZN(n570),
.B2(n533),
.B1(n572),
.A2(n532),
.A1(n571));
INV_X1 U153 (.ZN(n458),
.A(n515));
AND2_X1 U154 (.ZN(n338),
.A2(n795),
.A1(n807));
NOR2_X1 U155 (.ZN(n548),
.A2(n357),
.A1(n478));
NAND2_X1 U156 (.ZN(n187),
.A2(n810),
.A1(n799));
NAND4_X1 U157 (.ZN(res[6]),
.A4(n264),
.A3(n263),
.A2(n262),
.A1(n261));
AOI222_X1 U158 (.ZN(n261),
.C2(n211),
.C1(N600),
.B2(n210),
.B1(N635),
.A2(n209),
.A1(N535));
AOI222_X1 U159 (.ZN(n263),
.C2(FE_OFN9_n274),
.C1(n191),
.B2(n273),
.B1(n179),
.A2(n272),
.A1(n225));
AOI221_X1 U160 (.ZN(n262),
.C2(n203),
.C1(N568),
.B2(n275),
.B1(n885),
.A(n276));
NAND4_X1 U161 (.ZN(res[17]),
.A4(n648),
.A3(n647),
.A2(n646),
.A1(n645));
AOI222_X1 U162 (.ZN(n645),
.C2(n211),
.C1(N611),
.B2(n210),
.B1(N646),
.A2(n209),
.A1(N546));
AOI222_X1 U163 (.ZN(n647),
.C2(n610),
.C1(n472),
.B2(n611),
.B1(n515),
.A2(n419),
.A1(n885));
AOI221_X1 U164 (.ZN(n646),
.C2(n203),
.C1(N579),
.B2(n506),
.B1(n191),
.A(n656));
NAND4_X1 U165 (.ZN(res[10]),
.A4(n769),
.A3(n768),
.A2(n767),
.A1(n766));
AOI222_X1 U166 (.ZN(n766),
.C2(n211),
.C1(N604),
.B2(n210),
.B1(N639),
.A2(n209),
.A1(N539));
AOI221_X1 U167 (.ZN(n768),
.C2(n563),
.C1(n225),
.B2(n275),
.B1(n191),
.A(n775));
AOI221_X1 U168 (.ZN(n767),
.C2(n203),
.C1(N572),
.B2(n483),
.B1(n885),
.A(n780));
NAND4_X1 U169 (.ZN(res[18]),
.A4(n634),
.A3(n633),
.A2(n632),
.A1(n631));
AOI222_X1 U170 (.ZN(n631),
.C2(n211),
.C1(N612),
.B2(n210),
.B1(N647),
.A2(n209),
.A1(N547));
AOI221_X1 U171 (.ZN(n632),
.C2(n203),
.C1(N580),
.B2(n488),
.B1(n191),
.A(n643));
AOI222_X1 U172 (.ZN(n633),
.C2(n404),
.C1(n472),
.B2(n403),
.B1(n515),
.A2(n383),
.A1(n885));
NAND4_X1 U173 (.ZN(res[3]),
.A4(n315),
.A3(n314),
.A2(n313),
.A1(n312));
AOI222_X1 U174 (.ZN(n312),
.C2(n211),
.C1(N597),
.B2(n210),
.B1(N632),
.A2(n209),
.A1(N532));
AOI222_X1 U175 (.ZN(n314),
.C2(n330),
.C1(n179),
.B2(n329),
.B1(n221),
.A2(n254),
.A1(n225));
AOI222_X1 U176 (.ZN(n313),
.C2(n256),
.C1(n885),
.B2(n331),
.B1(n193),
.A2(n203),
.A1(N565));
NAND4_X1 U177 (.ZN(res[7]),
.A4(n241),
.A3(n240),
.A2(n239),
.A1(n238));
AOI222_X1 U178 (.ZN(n238),
.C2(n211),
.C1(N601),
.B2(n210),
.B1(N636),
.A2(n209),
.A1(N536));
AOI222_X1 U179 (.ZN(n240),
.C2(n256),
.C1(n191),
.B2(n255),
.B1(n179),
.A2(n254),
.A1(n193));
AOI221_X1 U180 (.ZN(n239),
.C2(n203),
.C1(N569),
.B2(n257),
.B1(n885),
.A(n258));
NAND4_X1 U181 (.ZN(res[2]),
.A4(n393),
.A3(n392),
.A2(n391),
.A1(n390));
AOI222_X1 U182 (.ZN(n390),
.C2(n211),
.C1(N596),
.B2(n210),
.B1(N631),
.A2(n209),
.A1(N531));
AOI222_X1 U183 (.ZN(n392),
.C2(n404),
.C1(n179),
.B2(n403),
.B1(n221),
.A2(n402),
.A1(n225));
AOI222_X1 U184 (.ZN(n391),
.C2(FE_OFN9_n274),
.C1(n885),
.B2(n405),
.B1(n193),
.A2(n203),
.A1(N564));
NAND4_X1 U185 (.ZN(res[19]),
.A4(n618),
.A3(n617),
.A2(n616),
.A1(n615));
AOI222_X1 U186 (.ZN(n615),
.C2(n211),
.C1(N613),
.B2(n210),
.B1(N648),
.A2(n209),
.A1(N548));
AOI222_X1 U187 (.ZN(n617),
.C2(n330),
.C1(n472),
.B2(n329),
.B1(n515),
.A2(n350),
.A1(n885));
AOI221_X1 U188 (.ZN(n616),
.C2(n203),
.C1(N581),
.B2(n629),
.B1(n191),
.A(n630));
NAND4_X1 U189 (.ZN(res[22]),
.A4(n547),
.A3(n546),
.A2(n545),
.A1(n544));
AOI222_X1 U190 (.ZN(n544),
.C2(n211),
.C1(N616),
.B2(n210),
.B1(N651),
.A2(n209),
.A1(N551));
AOI221_X1 U191 (.ZN(n546),
.C2(n385),
.C1(n885),
.B2(n273),
.B1(n472),
.A(n553));
AOI221_X1 U192 (.ZN(n547),
.C2(n275),
.C1(n549),
.B2(FE_OFN9_n274),
.B1(n548),
.A(n550));
NAND4_X1 U193 (.ZN(res[16]),
.A4(n660),
.A3(n659),
.A2(n658),
.A1(n657));
AOI222_X1 U194 (.ZN(n657),
.C2(n211),
.C1(N610),
.B2(n210),
.B1(N645),
.A2(n209),
.A1(N545));
AOI222_X1 U195 (.ZN(n659),
.C2(n666),
.C1(n487),
.B2(n224),
.B1(n198),
.A2(n445),
.A1(n191));
AOI222_X1 U196 (.ZN(n658),
.C2(n592),
.C1(n667),
.B2(n442),
.B1(n885),
.A2(n203),
.A1(N578));
NAND4_X1 U197 (.ZN(res[5]),
.A4(n283),
.A3(n282),
.A2(n281),
.A1(n280));
AOI222_X1 U198 (.ZN(n280),
.C2(n211),
.C1(N599),
.B2(n210),
.B1(N634),
.A2(n209),
.A1(N534));
AOI221_X1 U199 (.ZN(n283),
.C2(n285),
.C1(n179),
.B2(n284),
.B1(n221),
.A(n286));
AOI221_X1 U200 (.ZN(n281),
.C2(n203),
.C1(N567),
.B2(n192),
.B1(n885),
.A(n292));
NAND4_X1 U201 (.ZN(res[13]),
.A4(n707),
.A3(n706),
.A2(n705),
.A1(n704));
AOI221_X1 U202 (.ZN(n704),
.C2(n209),
.C1(N542),
.B2(n211),
.B1(N607),
.A(n725));
AOI221_X1 U203 (.ZN(n706),
.C2(n500),
.C1(n225),
.B2(n202),
.B1(n191),
.A(n716));
AOI221_X1 U204 (.ZN(n705),
.C2(n506),
.C1(n885),
.B2(n294),
.B1(n200),
.A(n720));
NAND4_X1 U205 (.ZN(res[14]),
.A4(n689),
.A3(n688),
.A2(n687),
.A1(n686));
AOI221_X1 U206 (.ZN(n686),
.C2(n209),
.C1(N543),
.B2(n211),
.B1(N608),
.A(n702));
AOI221_X1 U207 (.ZN(n688),
.C2(FE_OFN9_n274),
.C1(n487),
.B2(n275),
.B1(n198),
.A(n697));
AOI221_X1 U208 (.ZN(n687),
.C2(n563),
.C1(n193),
.B2(n562),
.B1(n225),
.A(n700));
NAND2_X1 U209 (.ZN(n362),
.A2(n807),
.A1(n796));
AOI21_X1 U210 (.ZN(n247),
.B2(n246),
.B1(n899),
.A(n892));
NAND4_X1 U211 (.ZN(n164),
.A4(n173),
.A3(n172),
.A2(n171),
.A1(n170));
NOR4_X1 U212 (.ZN(n171),
.A4(res[28]),
.A3(res[29]),
.A2(res[2]),
.A1(res[30]));
NOR4_X1 U213 (.ZN(n172),
.A4(res[31]),
.A3(res[3]),
.A2(res[4]),
.A1(res[5]));
NOR4_X1 U214 (.ZN(n170),
.A4(res[24]),
.A3(res[25]),
.A2(res[26]),
.A1(res[27]));
NAND2_X1 U215 (.ZN(n434),
.A2(n807),
.A1(n799));
AOI21_X1 U216 (.ZN(n425),
.B2(n209),
.B1(N557),
.A(n389));
AOI21_X1 U217 (.ZN(n365),
.B2(n209),
.B1(N559),
.A(n389));
NAND4_X1 U218 (.ZN(res[11]),
.A4(n748),
.A3(n747),
.A2(n746),
.A1(n745));
AOI22_X1 U219 (.ZN(n746),
.B2(n210),
.B1(N640),
.A2(n203),
.A1(N573));
AOI22_X1 U220 (.ZN(n745),
.B2(n209),
.B1(N540),
.A2(n211),
.A1(N605));
AOI221_X1 U221 (.ZN(n747),
.C2(n625),
.C1(n193),
.B2(n254),
.B1(n232),
.A(n761));
NAND4_X1 U222 (.ZN(res[15]),
.A4(n673),
.A3(n672),
.A2(n671),
.A1(n670));
AOI22_X1 U223 (.ZN(n671),
.B2(n210),
.B1(N644),
.A2(n203),
.A1(N577));
AOI22_X1 U224 (.ZN(n670),
.B2(n209),
.B1(N544),
.A2(n211),
.A1(N609));
NOR3_X1 U225 (.ZN(n673),
.A3(n676),
.A2(n675),
.A1(n674));
NAND2_X2 U226 (.ZN(n189),
.A2(n810),
.A1(n800));
OAI21_X1 U227 (.ZN(n550),
.B2(n522),
.B1(n551),
.A(n470));
AOI21_X1 U228 (.ZN(n551),
.B2(n552),
.B1(n899),
.A(n892));
INV_X1 U229 (.ZN(n463),
.A(n472));
NAND2_X2 U230 (.ZN(n190),
.A2(n810),
.A1(n795));
INV_X1 U231 (.ZN(n796),
.A(n806));
INV_X1 U232 (.ZN(n524),
.A(n525));
AOI22_X1 U233 (.ZN(n525),
.B2(n191),
.B1(n444),
.A2(n198),
.A1(n442));
INV_X1 U234 (.ZN(n643),
.A(n644));
AOI22_X1 U235 (.ZN(n644),
.B2(n198),
.B1(n483),
.A2(n487),
.A1(n275));
AOI221_X1 U236 (.ZN(n793),
.C2(n796),
.C1(N765),
.B2(n795),
.B1(N763),
.A(n797));
INV_X1 U237 (.ZN(n797),
.A(n798));
AOI22_X1 U238 (.ZN(n798),
.B2(n800),
.B1(N762),
.A2(n799),
.A1(N764));
NAND2_X1 U239 (.ZN(n827),
.A2(n799),
.A1(n824));
NAND2_X1 U240 (.ZN(n826),
.A2(n800),
.A1(n824));
AOI21_X1 U241 (.ZN(n803),
.B2(n805),
.B1(n804),
.A(n801));
AOI22_X1 U242 (.ZN(n804),
.B2(n800),
.B1(N758),
.A2(n799),
.A1(N760));
AOI22_X1 U243 (.ZN(n805),
.B2(n796),
.B1(N761),
.A2(n795),
.A1(N759));
INV_X1 U244 (.ZN(n452),
.A(n478));
AND2_X2 U245 (.ZN(n210),
.A2(n796),
.A1(n824));
AND2_X2 U246 (.ZN(n203),
.A2(n795),
.A1(n824));
INV_X1 U247 (.ZN(n335),
.A(n336));
AOI22_X1 U248 (.ZN(n336),
.B2(N625),
.B1(n211),
.A2(N560),
.A1(n209));
INV_X1 U249 (.ZN(n725),
.A(n726));
AOI22_X1 U250 (.ZN(n726),
.B2(n210),
.B1(N642),
.A2(n203),
.A1(N575));
INV_X1 U251 (.ZN(n702),
.A(n703));
AOI22_X1 U252 (.ZN(n703),
.B2(n210),
.B1(N643),
.A2(n203),
.A1(N576));
AOI222_X1 U253 (.ZN(n653),
.C2(n351),
.C1(n581),
.B2(n353),
.B1(n500),
.A2(n439),
.A1(n194));
AOI222_X1 U254 (.ZN(n640),
.C2(n353),
.C1(n562),
.B2(n351),
.B1(n563),
.A2(n439),
.A1(n272));
OAI222_X1 U255 (.ZN(n300),
.C2(n357),
.C1(n521),
.B2(n359),
.B1(n593),
.A2(n461),
.A1(n433));
AOI221_X1 U256 (.ZN(n490),
.C2(n439),
.C1(n562),
.B2(n351),
.B1(n370),
.A(n503));
INV_X1 U257 (.ZN(n461),
.A(n353));
OAI22_X1 U258 (.ZN(n220),
.B2(n359),
.B1(n521),
.A2(n357),
.A1(n433));
OAI221_X1 U259 (.ZN(n667),
.C2(n639),
.C1(n433),
.B2(n461),
.B1(n521),
.A(n811));
AOI22_X1 U260 (.ZN(n811),
.B2(n226),
.B1(n351),
.A2(n237),
.A1(n439));
OAI21_X1 U261 (.ZN(n412),
.B2(n712),
.B1(n326),
.A(n713));
NOR2_X1 U262 (.ZN(n346),
.A2(n834),
.A1(n712));
NOR2_X1 U263 (.ZN(n661),
.A2(n834),
.A1(n774));
OAI221_X1 U264 (.ZN(n808),
.C2(n639),
.C1(n744),
.B2(n461),
.B1(n816),
.A(n817));
INV_X1 U265 (.ZN(n816),
.A(n236));
AOI22_X1 U266 (.ZN(n817),
.B2(n311),
.B1(n351),
.A2(n818),
.A1(n439));
NOR2_X1 U267 (.ZN(n503),
.A2(n712),
.A1(n624));
OAI21_X1 U268 (.ZN(n410),
.B2(n712),
.B1(n711),
.A(n713));
AOI22_X1 U269 (.ZN(n557),
.B2(n439),
.B1(n563),
.A2(n351),
.A1(n562));
AOI22_X1 U270 (.ZN(n623),
.B2(n351),
.B1(n626),
.A2(n439),
.A1(n625));
AOI22_X1 U271 (.ZN(n577),
.B2(n351),
.B1(n500),
.A2(n439),
.A1(n581));
AOI22_X1 U272 (.ZN(n182),
.B2(n351),
.B1(n412),
.A2(n439),
.A1(n500));
AOI22_X1 U273 (.ZN(n480),
.B2(n351),
.B1(n373),
.A2(n439),
.A1(n562));
NOR2_X1 U274 (.ZN(n380),
.A2(n349),
.A1(n834));
OAI22_X1 U275 (.ZN(n440),
.B2(n441),
.B1(n326),
.A2(n381),
.A1(FE_OFN3_n325));
OAI22_X1 U276 (.ZN(n418),
.B2(n381),
.B1(n326),
.A2(n348),
.A1(FE_OFN3_n325));
OAI211_X1 U277 (.ZN(n285),
.C2(n461),
.C1(n580),
.B(n577),
.A(n561));
OAI211_X1 U278 (.ZN(n330),
.C2(n461),
.C1(n540),
.B(n623),
.A(n561));
OAI22_X1 U279 (.ZN(n379),
.B2(n382),
.B1(FE_OFN3_n325),
.A2(n872),
.A1(n381));
OAI22_X1 U280 (.ZN(n345),
.B2(n349),
.B1(FE_OFN3_n325),
.A2(n348),
.A1(n872));
OAI211_X1 U281 (.ZN(n273),
.C2(n461),
.C1(n560),
.B(n557),
.A(n561));
AOI21_X1 U282 (.ZN(n253),
.B2(n346),
.B1(n353),
.A(n537));
INV_X1 U283 (.ZN(n197),
.A(n572));
OAI21_X1 U284 (.ZN(n266),
.B2(n461),
.B1(n556),
.A(n557));
OAI21_X1 U285 (.ZN(n329),
.B2(n624),
.B1(n457),
.A(n623));
OAI21_X1 U286 (.ZN(n403),
.B2(n639),
.B1(n556),
.A(n640));
OAI21_X1 U287 (.ZN(n404),
.B2(n639),
.B1(n560),
.A(n640));
NAND2_X1 U288 (.ZN(n343),
.A2(n308),
.A1(n439));
INV_X1 U289 (.ZN(n462),
.A(n257));
INV_X1 U294 (.ZN(n356),
.A(n542));
INV_X1 U295 (.ZN(n460),
.A(n256));
INV_X1 U296 (.ZN(n540),
.A(n451));
INV_X1 U297 (.ZN(n358),
.A(n629));
INV_X1 U298 (.ZN(n571),
.A(n192));
INV_X1 U299 (.ZN(n433),
.A(n736));
INV_X1 U300 (.ZN(n519),
.A(n224));
INV_X1 U301 (.ZN(n388),
.A(n488));
INV_X1 U302 (.ZN(n423),
.A(n202));
INV_X1 U303 (.ZN(n387),
.A(n483));
INV_X1 U304 (.ZN(n228),
.A(n666));
INV_X1 U305 (.ZN(n278),
.A(n402));
INV_X1 U306 (.ZN(n581),
.A(n207));
INV_X1 U307 (.ZN(n424),
.A(n506));
INV_X1 U308 (.ZN(n597),
.A(n445));
INV_X1 U309 (.ZN(n593),
.A(n226));
INV_X1 U310 (.ZN(n373),
.A(n556));
INV_X1 U311 (.ZN(n293),
.A(n194));
INV_X1 U312 (.ZN(n260),
.A(n625));
INV_X1 U313 (.ZN(n205),
.A(n294));
INV_X1 U314 (.ZN(n491),
.A(n383));
INV_X1 U315 (.ZN(n469),
.A(n350));
INV_X1 U316 (.ZN(n508),
.A(n419));
INV_X1 U317 (.ZN(n701),
.A(n272));
INV_X1 U318 (.ZN(n744),
.A(n233));
INV_X1 U319 (.ZN(n541),
.A(n626));
INV_X1 U320 (.ZN(n180),
.A(n502));
AOI221_X1 U321 (.ZN(n502),
.C2(n351),
.C1(n410),
.B2(n439),
.B1(n500),
.A(n503));
INV_X1 U322 (.ZN(n277),
.A(n405));
INV_X1 U323 (.ZN(n259),
.A(n331));
INV_X1 U324 (.ZN(n370),
.A(n560));
INV_X2 U325 (.ZN(n326),
.A(n344));
INV_X1 U326 (.ZN(n307),
.A(n446));
INV_X1 U327 (.ZN(n319),
.A(n242));
INV_X1 U328 (.ZN(n397),
.A(n265));
NOR3_X1 U329 (.ZN(n807),
.A3(alu_op[2]),
.A2(alu_op[4]),
.A1(alu_op[3]));
NOR2_X1 U330 (.ZN(n515),
.A2(n694),
.A1(n434));
NOR3_X1 U331 (.ZN(n810),
.A3(n790),
.A2(alu_op[4]),
.A1(alu_op[2]));
NOR2_X1 U332 (.ZN(n800),
.A2(alu_op[1]),
.A1(alu_op[0]));
NOR2_X1 U333 (.ZN(n799),
.A2(alu_op[0]),
.A1(n825));
AOI222_X1 U334 (.ZN(n785),
.C2(n203),
.C1(N562),
.B2(n885),
.B1(n661),
.A2(n210),
.A1(N629));
NOR4_X1 U335 (.ZN(n748),
.A4(n751),
.A3(n735),
.A2(n750),
.A1(n749));
NOR3_X1 U336 (.ZN(n751),
.A3(n457),
.A2(b[3]),
.A1(n183));
OAI221_X1 U337 (.ZN(n749),
.C2(n208),
.C1(n541),
.B2(n229),
.B1(n462),
.A(n756));
OAI22_X1 U338 (.ZN(n750),
.B2(n612),
.B1(n753),
.A2(n693),
.A1(n540));
AOI221_X1 U339 (.ZN(n769),
.C2(FE_OFN9_n274),
.C1(n198),
.B2(n770),
.B1(b[10]),
.A(n771));
OAI221_X1 U340 (.ZN(n770),
.C2(FE_OFN1_n187),
.C1(a[10]),
.B2(n613),
.B1(n189),
.A(n190));
OAI22_X1 U341 (.ZN(n771),
.B2(n613),
.B1(n772),
.A2(n183),
.A1(n480));
INV_X1 U342 (.ZN(n772),
.A(n773));
AOI221_X1 U343 (.ZN(n634),
.C2(n635),
.C1(b[18]),
.B2(FE_OFN9_n274),
.B1(n549),
.A(n636));
OAI221_X1 U344 (.ZN(n635),
.C2(FE_OFN1_n187),
.C1(a[18]),
.B2(n594),
.B1(n189),
.A(n190));
OAI21_X1 U345 (.ZN(n636),
.B2(n594),
.B1(n637),
.A(n470));
INV_X1 U346 (.ZN(n637),
.A(n638));
AOI221_X1 U347 (.ZN(n618),
.C2(n619),
.C1(b[19]),
.B2(n256),
.B1(n549),
.A(n620));
OAI221_X1 U348 (.ZN(n619),
.C2(FE_OFN1_n187),
.C1(a[19]),
.B2(n578),
.B1(n189),
.A(n190));
OAI21_X1 U349 (.ZN(n620),
.B2(n578),
.B1(n621),
.A(n470));
INV_X1 U350 (.ZN(n621),
.A(n622));
AOI221_X1 U351 (.ZN(n450),
.C2(n453),
.C1(n452),
.B2(n451),
.B1(n369),
.A(n454));
OAI222_X1 U352 (.ZN(n453),
.C2(n357),
.C1(n462),
.B2(n359),
.B1(n356),
.A2(n461),
.A1(n460));
OAI21_X1 U353 (.ZN(n454),
.B2(n381),
.B1(n455),
.A(n456));
OR3_X1 U354 (.ZN(n456),
.A3(n458),
.A2(b[3]),
.A1(n457));
AOI221_X1 U355 (.ZN(n264),
.C2(n266),
.C1(n221),
.B2(n265),
.B1(n200),
.A(n267));
OAI22_X1 U356 (.ZN(n267),
.B2(n271),
.B1(n270),
.A2(n269),
.A1(n268));
AOI221_X1 U357 (.ZN(n268),
.C2(n889),
.C1(a[6]),
.B2(n271),
.B1(n899),
.A(n887));
AOI21_X1 U358 (.ZN(n270),
.B2(n269),
.B1(n899),
.A(n892));
AOI221_X1 U359 (.ZN(n689),
.C2(n690),
.C1(b[14]),
.B2(n373),
.B1(n682),
.A(n691));
OAI221_X1 U360 (.ZN(n690),
.C2(FE_OFN1_n187),
.C1(a[14]),
.B2(n668),
.B1(n189),
.A(n190));
OAI221_X1 U361 (.ZN(n691),
.C2(n693),
.C1(n560),
.B2(n668),
.B1(n692),
.A(n695));
INV_X1 U362 (.ZN(n692),
.A(n696));
AOI221_X1 U363 (.ZN(n241),
.C2(n243),
.C1(n221),
.B2(n242),
.B1(n200),
.A(n244));
INV_X1 U364 (.ZN(n243),
.A(n253));
OAI22_X1 U365 (.ZN(n244),
.B2(n248),
.B1(n247),
.A2(n246),
.A1(n245));
AOI221_X1 U366 (.ZN(n245),
.C2(n889),
.C1(a[7]),
.B2(n248),
.B1(n899),
.A(n887));
AOI221_X1 U367 (.ZN(n393),
.C2(n395),
.C1(b[2]),
.B2(n394),
.B1(a[2]),
.A(n396));
OAI221_X1 U368 (.ZN(n395),
.C2(FE_OFN1_n187),
.C1(a[2]),
.B2(n401),
.B1(n189),
.A(n190));
OAI21_X1 U369 (.ZN(n394),
.B2(FE_OFN1_n187),
.B1(b[2]),
.A(n188));
OAI22_X1 U370 (.ZN(n396),
.B2(n321),
.B1(n398),
.A2(n206),
.A1(n397));
AOI221_X1 U371 (.ZN(n315),
.C2(n317),
.C1(b[3]),
.B2(n316),
.B1(a[3]),
.A(n318));
OAI221_X1 U372 (.ZN(n317),
.C2(FE_OFN1_n187),
.C1(a[3]),
.B2(n328),
.B1(n189),
.A(n190));
OAI21_X1 U373 (.ZN(n316),
.B2(FE_OFN1_n187),
.B1(b[3]),
.A(n188));
OAI22_X1 U374 (.ZN(n318),
.B2(n321),
.B1(n320),
.A2(n206),
.A1(n319));
AOI221_X1 U375 (.ZN(n730),
.C2(n732),
.C1(a[12]),
.B2(n446),
.B1(n731),
.A(n733));
NOR2_X1 U376 (.ZN(n731),
.A2(n306),
.A1(n624));
OAI21_X1 U377 (.ZN(n732),
.B2(FE_OFN1_n187),
.B1(b[12]),
.A(FE_OFN8_n188));
NAND2_X1 U378 (.ZN(n733),
.A2(n695),
.A1(n734));
AOI221_X1 U379 (.ZN(n707),
.C2(n708),
.C1(b[13]),
.B2(n412),
.B1(n682),
.A(n709));
OAI221_X1 U380 (.ZN(n708),
.C2(FE_OFN1_n187),
.C1(a[13]),
.B2(n678),
.B1(n189),
.A(n190));
OAI221_X1 U381 (.ZN(n709),
.C2(n693),
.C1(n580),
.B2(n678),
.B1(n710),
.A(n695));
INV_X1 U382 (.ZN(n710),
.A(n714));
AOI221_X1 U383 (.ZN(n648),
.C2(n649),
.C1(b[17]),
.B2(n197),
.B1(n549),
.A(n650));
OAI221_X1 U384 (.ZN(n649),
.C2(FE_OFN1_n187),
.C1(a[17]),
.B2(n627),
.B1(n189),
.A(n190));
OAI21_X1 U385 (.ZN(n650),
.B2(n627),
.B1(n651),
.A(n470));
INV_X1 U386 (.ZN(n651),
.A(n652));
AOI221_X1 U387 (.ZN(n660),
.C2(n662),
.C1(b[16]),
.B2(n661),
.B1(n549),
.A(n663));
OAI221_X1 U388 (.ZN(n662),
.C2(FE_OFN1_n187),
.C1(a[16]),
.B2(n641),
.B1(n189),
.A(n190));
OAI21_X1 U389 (.ZN(n663),
.B2(n641),
.B1(n664),
.A(n470));
INV_X1 U390 (.ZN(n664),
.A(n665));
AOI211_X1 U391 (.ZN(n586),
.C2(n452),
.C1(n587),
.B(n309),
.A(n588));
NOR2_X1 U392 (.ZN(n587),
.A2(n307),
.A1(b[3]));
OAI22_X1 U393 (.ZN(n588),
.B2(n558),
.B1(n589),
.A2(n561),
.A1(n463));
INV_X1 U394 (.ZN(n589),
.A(n590));
OAI221_X1 U395 (.ZN(n591),
.C2(FE_OFN1_n187),
.C1(a[20]),
.B2(n558),
.B1(n189),
.A(n190));
OAI221_X1 U396 (.ZN(n520),
.C2(FE_OFN1_n187),
.C1(a[24]),
.B2(n485),
.B1(n189),
.A(n190));
OAI221_X1 U397 (.ZN(n501),
.C2(FE_OFN1_n187),
.C1(a[25]),
.B2(n189),
.B1(n465),
.A(n190));
OAI221_X1 U398 (.ZN(n484),
.C2(FE_OFN1_n187),
.C1(a[26]),
.B2(n189),
.B1(n441),
.A(n190));
OAI221_X1 U399 (.ZN(n809),
.C2(FE_OFN1_n187),
.C1(a[0]),
.B2(n774),
.B1(n189),
.A(n190));
OAI221_X1 U400 (.ZN(n216),
.C2(FE_OFN1_n187),
.C1(a[8]),
.B2(n223),
.B1(n189),
.A(n190));
OAI221_X1 U401 (.ZN(n429),
.C2(FE_OFN1_n187),
.C1(a[28]),
.B2(n189),
.B1(n348),
.A(n190));
OAI22_X1 U402 (.ZN(n604),
.B2(n321),
.B1(n606),
.A2(n206),
.A1(n605));
INV_X1 U403 (.ZN(n605),
.A(n291));
AOI221_X1 U404 (.ZN(n606),
.C2(n868),
.C1(a[1]),
.B2(FE_OFN2_n322),
.B1(a[4]),
.A(n607));
OAI22_X1 U405 (.ZN(n607),
.B2(n328),
.B1(n326),
.A2(n401),
.A1(FE_OFN3_n325));
OAI22_X1 U406 (.ZN(n181),
.B2(n185),
.B1(n184),
.A2(n183),
.A1(n182));
INV_X1 U407 (.ZN(n184),
.A(n186));
OAI21_X1 U408 (.ZN(n186),
.B2(b[9]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
NAND2_X1 U409 (.ZN(n478),
.A2(n694),
.A1(n338));
AOI22_X1 U410 (.ZN(n756),
.B2(n256),
.B1(n198),
.A2(n757),
.A1(b[11]));
OAI221_X1 U411 (.ZN(n757),
.C2(FE_OFN1_n187),
.C1(a[11]),
.B2(n612),
.B1(n189),
.A(n190));
NAND4_X1 U412 (.ZN(res[20]),
.A4(n586),
.A3(n585),
.A2(n584),
.A1(n583));
AOI222_X1 U413 (.ZN(n583),
.C2(n211),
.C1(N614),
.B2(n210),
.B1(N649),
.A2(n209),
.A1(N549));
AOI222_X1 U414 (.ZN(n585),
.C2(n300),
.C1(n592),
.B2(n591),
.B1(b[20]),
.A2(n444),
.A1(n885));
AOI221_X1 U415 (.ZN(n584),
.C2(n203),
.C1(N582),
.B2(n442),
.B1(n191),
.A(n596));
NAND4_X1 U416 (.ZN(res[24]),
.A4(n513),
.A3(n512),
.A2(n511),
.A1(n510));
AOI222_X1 U417 (.ZN(n510),
.C2(n211),
.C1(N618),
.B2(n210),
.B1(N653),
.A2(n209),
.A1(N553));
AOI222_X1 U418 (.ZN(n512),
.C2(n217),
.C1(n472),
.B2(n520),
.B1(b[24]),
.A2(n443),
.A1(n885));
AOI221_X1 U419 (.ZN(n511),
.C2(n203),
.C1(N586),
.B2(n445),
.B1(n487),
.A(n524));
NAND4_X1 U420 (.ZN(res[21]),
.A4(n568),
.A3(n567),
.A2(n566),
.A1(n565));
AOI222_X1 U421 (.ZN(n565),
.C2(n211),
.C1(N615),
.B2(n210),
.B1(N650),
.A2(n209),
.A1(N550));
AOI211_X1 U422 (.ZN(n568),
.C2(n569),
.C1(a[21]),
.B(n309),
.A(n570));
AOI221_X1 U423 (.ZN(n567),
.C2(n421),
.C1(n885),
.B2(n285),
.B1(n472),
.A(n573));
NAND4_X1 U424 (.ZN(res[25]),
.A4(n495),
.A3(n494),
.A2(n493),
.A1(n492));
AOI222_X1 U425 (.ZN(n492),
.C2(n211),
.C1(N619),
.B2(n210),
.B1(N654),
.A2(n209),
.A1(N554));
AOI222_X1 U426 (.ZN(n494),
.C2(n180),
.C1(n472),
.B2(n501),
.B1(b[25]),
.A2(n420),
.A1(n885));
AOI221_X1 U427 (.ZN(n493),
.C2(n203),
.C1(N587),
.B2(n506),
.B1(n487),
.A(n507));
NAND4_X1 U428 (.ZN(res[4]),
.A4(n298),
.A3(n297),
.A2(n296),
.A1(n295));
AOI222_X1 U429 (.ZN(n295),
.C2(n211),
.C1(N598),
.B2(n210),
.B1(N633),
.A2(n209),
.A1(N533));
AOI221_X1 U430 (.ZN(n298),
.C2(n301),
.C1(n694),
.B2(n300),
.B1(n299),
.A(n302));
AOI222_X1 U431 (.ZN(n296),
.C2(n236),
.C1(n232),
.B2(n311),
.B1(n200),
.A2(n203),
.A1(N566));
NAND4_X1 U432 (.ZN(res[8]),
.A4(n215),
.A3(n214),
.A2(n213),
.A1(n212));
AOI222_X1 U433 (.ZN(n212),
.C2(n211),
.C1(N602),
.B2(n210),
.B1(N637),
.A2(n209),
.A1(N537));
AOI221_X1 U434 (.ZN(n215),
.C2(n217),
.C1(n179),
.B2(n216),
.B1(b[8]),
.A(n218));
AOI221_X1 U435 (.ZN(n214),
.C2(n226),
.C1(n225),
.B2(n224),
.B1(n885),
.A(n227));
NAND4_X1 U436 (.ZN(res[26]),
.A4(n476),
.A3(n475),
.A2(n474),
.A1(n473));
AOI222_X1 U437 (.ZN(n473),
.C2(n211),
.C1(N620),
.B2(n210),
.B1(N655),
.A2(n209),
.A1(N555));
AOI222_X1 U438 (.ZN(n475),
.C2(n384),
.C1(n885),
.B2(n484),
.B1(b[26]),
.A2(n385),
.A1(n191));
AOI221_X1 U439 (.ZN(n474),
.C2(n203),
.C1(N588),
.B2(n488),
.B1(n487),
.A(n489));
NAND4_X1 U440 (.ZN(res[1]),
.A4(n601),
.A3(n600),
.A2(n599),
.A1(n598));
AOI222_X1 U441 (.ZN(n598),
.C2(n211),
.C1(N595),
.B2(n210),
.B1(N630),
.A2(n209),
.A1(N530));
AOI222_X1 U442 (.ZN(n600),
.C2(n611),
.C1(n221),
.B2(n199),
.B1(n193),
.A2(n610),
.A1(n179));
AOI221_X1 U443 (.ZN(n601),
.C2(n603),
.C1(b[1]),
.B2(n602),
.B1(a[1]),
.A(n604));
NAND4_X1 U444 (.ZN(res[12]),
.A4(n730),
.A3(n729),
.A2(n728),
.A1(n727));
AOI222_X1 U445 (.ZN(n727),
.C2(n211),
.C1(N606),
.B2(n210),
.B1(N641),
.A2(n209),
.A1(N541));
AOI221_X1 U446 (.ZN(n729),
.C2(n224),
.C1(n191),
.B2(n739),
.B1(b[12]),
.A(n740));
AOI221_X1 U447 (.ZN(n728),
.C2(n203),
.C1(N574),
.B2(n237),
.B1(n232),
.A(n743));
NAND4_X1 U448 (.ZN(res[9]),
.A4(n177),
.A3(n176),
.A2(n175),
.A1(n174));
AOI222_X1 U449 (.ZN(n174),
.C2(n211),
.C1(N603),
.B2(n210),
.B1(N638),
.A2(n209),
.A1(N538));
AOI221_X1 U450 (.ZN(n177),
.C2(n180),
.C1(n179),
.B2(n178),
.B1(b[9]),
.A(n181));
AOI221_X1 U451 (.ZN(n175),
.C2(n203),
.C1(N571),
.B2(n202),
.B1(n885),
.A(n204));
NAND4_X1 U452 (.ZN(res[23]),
.A4(n529),
.A3(n528),
.A2(n527),
.A1(n526));
AOI222_X1 U453 (.ZN(n526),
.C2(n211),
.C1(N617),
.B2(n210),
.B1(N652),
.A2(n209),
.A1(N552));
AOI221_X1 U454 (.ZN(n528),
.C2(n354),
.C1(n885),
.B2(n255),
.B1(n472),
.A(n534));
AOI211_X1 U455 (.ZN(n529),
.C2(n530),
.C1(a[23]),
.B(n309),
.A(n531));
NAND2_X1 U456 (.ZN(n389),
.A2(n471),
.A1(n470));
OAI211_X1 U457 (.ZN(n337),
.C2(n361),
.C1(n834),
.B(n363),
.A(n362));
AOI21_X1 U458 (.ZN(n363),
.B2(n889),
.B1(b[31]),
.A(n892));
NAND4_X1 U459 (.ZN(res[27]),
.A4(n450),
.A3(n449),
.A2(n448),
.A1(n447));
AOI222_X1 U460 (.ZN(n449),
.C2(n352),
.C1(n885),
.B2(n464),
.B1(b[27]),
.A2(n354),
.A1(n191));
AOI221_X1 U461 (.ZN(n448),
.C2(n210),
.C1(N656),
.B2(n203),
.B1(N589),
.A(n467));
AOI221_X1 U462 (.ZN(n447),
.C2(n209),
.C1(N556),
.B2(n211),
.B1(N621),
.A(n389));
NAND4_X1 U463 (.ZN(res[0]),
.A4(n787),
.A3(n786),
.A2(n785),
.A1(n784));
AOI22_X1 U464 (.ZN(n784),
.B2(n209),
.B1(N529),
.A2(n211),
.A1(N594));
AOI222_X1 U465 (.ZN(n786),
.C2(n809),
.C1(b[0]),
.B2(n299),
.B1(n667),
.A2(n592),
.A1(n808));
AOI21_X1 U466 (.ZN(n787),
.B2(n788),
.B1(a[0]),
.A(n789));
NAND4_X1 U467 (.ZN(res[29]),
.A4(n409),
.A3(n408),
.A2(n407),
.A1(n406));
AOI222_X1 U468 (.ZN(n407),
.C2(n210),
.C1(N658),
.B2(n203),
.B1(N591),
.A2(n211),
.A1(N623));
AOI22_X1 U469 (.ZN(n408),
.B2(n414),
.B1(n338),
.A2(n413),
.A1(b[29]));
AOI21_X1 U470 (.ZN(n406),
.B2(n209),
.B1(N558),
.A(n389));
OAI22_X1 U471 (.ZN(n286),
.B2(n290),
.B1(n289),
.A2(n288),
.A1(n287));
AOI221_X1 U472 (.ZN(n287),
.C2(n889),
.C1(a[5]),
.B2(n290),
.B1(n899),
.A(n887));
AOI21_X1 U473 (.ZN(n289),
.B2(n288),
.B1(n899),
.A(n892));
INV_X1 U474 (.ZN(n288),
.A(b[5]));
OAI21_X1 U475 (.ZN(n302),
.B2(n304),
.B1(n303),
.A(n305));
OR3_X1 U476 (.ZN(n305),
.A3(n307),
.A2(b[3]),
.A1(n306));
AOI21_X1 U477 (.ZN(n303),
.B2(n308),
.B1(n899),
.A(n892));
NAND4_X1 U478 (.ZN(res[30]),
.A4(n368),
.A3(n367),
.A2(n366),
.A1(n365));
AOI222_X1 U479 (.ZN(n366),
.C2(n210),
.C1(N659),
.B2(n203),
.B1(N592),
.A2(n211),
.A1(N624));
AOI22_X1 U480 (.ZN(n367),
.B2(n375),
.B1(n338),
.A2(n374),
.A1(b[30]));
AOI222_X1 U481 (.ZN(n368),
.C2(n373),
.C1(n372),
.B2(n371),
.B1(a[30]),
.A2(n370),
.A1(n369));
AOI22_X1 U482 (.ZN(n332),
.B2(n364),
.B1(n899),
.A2(b[31]),
.A1(n887));
AOI221_X1 U483 (.ZN(n334),
.C2(n210),
.C1(N660),
.B2(n203),
.B1(N593),
.A(n335));
AOI22_X1 U484 (.ZN(n333),
.B2(n339),
.B1(n338),
.A2(n337),
.A1(a[31]));
AND2_X1 U485 (.ZN(n795),
.A2(n825),
.A1(alu_op[0]));
OAI21_X1 U486 (.ZN(n518),
.B2(b[24]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U487 (.ZN(n773),
.B2(b[10]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U488 (.ZN(n714),
.B2(b[13]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U489 (.ZN(n696),
.B2(b[14]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U490 (.ZN(n684),
.B2(b[15]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U491 (.ZN(n665),
.B2(b[16]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U492 (.ZN(n652),
.B2(b[17]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U493 (.ZN(n638),
.B2(b[18]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U494 (.ZN(n622),
.B2(b[19]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U495 (.ZN(n590),
.B2(b[20]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U496 (.ZN(n499),
.B2(b[25]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U497 (.ZN(n482),
.B2(b[26]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI21_X1 U498 (.ZN(n430),
.B2(FE_OFN1_n187),
.B1(b[28]),
.A(FE_OFN8_n188));
OAI21_X1 U499 (.ZN(n788),
.B2(FE_OFN1_n187),
.B1(b[0]),
.A(n188));
OAI21_X1 U500 (.ZN(n569),
.B2(FE_OFN1_n187),
.B1(b[21]),
.A(FE_OFN8_n188));
OAI21_X1 U501 (.ZN(n530),
.B2(FE_OFN1_n187),
.B1(b[23]),
.A(FE_OFN8_n188));
OAI21_X1 U502 (.ZN(n371),
.B2(FE_OFN1_n187),
.B1(b[30]),
.A(n188));
AOI222_X1 U503 (.ZN(n409),
.C2(n412),
.C1(n372),
.B2(n411),
.B1(a[29]),
.A2(n410),
.A1(n369));
OAI21_X1 U504 (.ZN(n411),
.B2(FE_OFN1_n187),
.B1(b[29]),
.A(n188));
OAI21_X1 U505 (.ZN(n602),
.B2(FE_OFN1_n187),
.B1(b[1]),
.A(n188));
NAND4_X1 U506 (.ZN(res[28]),
.A4(n428),
.A3(n427),
.A2(n426),
.A1(n425));
AOI22_X1 U507 (.ZN(n427),
.B2(n203),
.B1(N590),
.A2(n435),
.A1(n338));
AOI22_X1 U508 (.ZN(n426),
.B2(n211),
.B1(N622),
.A2(n210),
.A1(N657));
AOI221_X1 U509 (.ZN(n428),
.C2(n430),
.C1(a[28]),
.B2(n429),
.B1(b[28]),
.A(n431));
INV_X1 U510 (.ZN(n790),
.A(alu_op[3]));
NAND2_X1 U511 (.ZN(n806),
.A2(alu_op[0]),
.A1(alu_op[1]));
INV_X1 U512 (.ZN(n825),
.A(alu_op[1]));
INV_X1 U513 (.ZN(n476),
.A(n477));
OAI221_X1 U514 (.ZN(n477),
.C2(n480),
.C1(n458),
.B2(n479),
.B1(n478),
.A(n481));
AOI222_X1 U515 (.ZN(n479),
.C2(n351),
.C1(n275),
.B2(n439),
.B1(n483),
.A2(n353),
.A1(FE_OFN9_n274));
AOI21_X1 U516 (.ZN(n481),
.B2(a[26]),
.B1(n482),
.A(n309));
INV_X1 U517 (.ZN(n495),
.A(n496));
OAI221_X1 U518 (.ZN(n496),
.C2(n182),
.C1(n458),
.B2(n497),
.B1(n478),
.A(n498));
AOI222_X1 U519 (.ZN(n497),
.C2(n439),
.C1(n202),
.B2(n351),
.B1(n192),
.A2(n353),
.A1(n197));
AOI21_X1 U520 (.ZN(n498),
.B2(a[25]),
.B1(n499),
.A(n309));
INV_X1 U521 (.ZN(n218),
.A(n219));
AOI22_X1 U522 (.ZN(n219),
.B2(a[8]),
.B1(n222),
.A2(n221),
.A1(n220));
OAI21_X1 U523 (.ZN(n222),
.B2(b[8]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
INV_X1 U524 (.ZN(n573),
.A(n574));
AOI22_X1 U525 (.ZN(n574),
.B2(b[21]),
.B1(n575),
.A2(n515),
.A1(n284));
OAI221_X1 U526 (.ZN(n575),
.C2(n189),
.C1(n538),
.B2(a[21]),
.B1(FE_OFN1_n187),
.A(n190));
INV_X1 U527 (.ZN(n753),
.A(n754));
OAI21_X1 U528 (.ZN(n754),
.B2(b[11]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
INV_X1 U529 (.ZN(n455),
.A(n459));
OAI21_X1 U530 (.ZN(n459),
.B2(b[27]),
.B1(FE_OFN1_n187),
.A(FE_OFN8_n188));
OAI211_X1 U531 (.ZN(n674),
.C2(n654),
.C1(n680),
.B(n681),
.A(n470));
AOI22_X1 U532 (.ZN(n681),
.B2(n683),
.B1(b[15]),
.A2(n346),
.A1(n682));
INV_X1 U533 (.ZN(n680),
.A(n684));
OAI221_X1 U534 (.ZN(n683),
.C2(FE_OFN1_n187),
.C1(a[15]),
.B2(n654),
.B1(n189),
.A(n190));
NOR2_X1 U535 (.ZN(zero),
.A2(n165),
.A1(n164));
NAND4_X1 U536 (.ZN(n165),
.A4(n169),
.A3(n168),
.A2(n167),
.A1(n166));
INV_X1 U537 (.ZN(n794),
.A(alu_op[4]));
NAND2_X1 U538 (.ZN(n792),
.A2(n790),
.A1(n801));
AOI21_X1 U539 (.ZN(n791),
.B2(N757),
.B1(n802),
.A(n803));
NOR3_X1 U540 (.ZN(n824),
.A3(n801),
.A2(alu_op[4]),
.A1(alu_op[3]));
OAI221_X1 U541 (.ZN(n603),
.C2(FE_OFN1_n187),
.C1(a[1]),
.B2(n609),
.B1(n189),
.A(n190));
OAI221_X1 U542 (.ZN(n301),
.C2(FE_OFN1_n187),
.C1(a[4]),
.B2(n304),
.B1(n189),
.A(n190));
OAI221_X1 U543 (.ZN(n413),
.C2(FE_OFN1_n187),
.C1(a[29]),
.B2(n189),
.B1(n382),
.A(n190));
OAI221_X1 U544 (.ZN(n374),
.C2(FE_OFN1_n187),
.C1(a[30]),
.B2(n189),
.B1(n349),
.A(n190));
OAI221_X1 U545 (.ZN(n464),
.C2(FE_OFN1_n187),
.C1(a[27]),
.B2(n189),
.B1(n381),
.A(n190));
OAI221_X1 U546 (.ZN(n739),
.C2(FE_OFN1_n187),
.C1(a[12]),
.B2(n698),
.B1(n189),
.A(n190));
OAI221_X1 U547 (.ZN(n178),
.C2(FE_OFN1_n187),
.C1(a[9]),
.B2(n189),
.B1(n185),
.A(n190));
OAI22_X1 U548 (.ZN(n553),
.B2(n552),
.B1(n555),
.A2(n458),
.A1(n554));
INV_X1 U549 (.ZN(n554),
.A(n266));
AOI221_X1 U550 (.ZN(n555),
.C2(n889),
.C1(a[22]),
.B2(n522),
.B1(n899),
.A(n887));
OAI22_X1 U551 (.ZN(n534),
.B2(n536),
.B1(n535),
.A2(n458),
.A1(n253));
INV_X1 U552 (.ZN(n536),
.A(b[23]));
AOI221_X1 U553 (.ZN(n535),
.C2(n889),
.C1(a[23]),
.B2(n504),
.B1(n899),
.A(n887));
NOR2_X1 U554 (.ZN(n802),
.A2(n806),
.A1(alu_op[2]));
INV_X1 U555 (.ZN(n801),
.A(alu_op[2]));
AOI22_X1 U556 (.ZN(n779),
.B2(n868),
.B1(a[6]),
.A2(FE_OFN2_n322),
.A1(a[3]));
OAI22_X1 U557 (.ZN(n815),
.B2(n834),
.B1(n485),
.A2(n381),
.A1(n872));
OAI221_X1 U558 (.ZN(n256),
.C2(n401),
.C1(FE_OFN3_n325),
.B2(n609),
.B1(n326),
.A(n758));
AOI22_X1 U559 (.ZN(n758),
.B2(n868),
.B1(a[3]),
.A2(FE_OFN2_n322),
.A1(a[0]));
OAI221_X1 U560 (.ZN(n224),
.C2(n248),
.C1(FE_OFN3_n325),
.B2(n271),
.B1(n326),
.A(n742));
AOI22_X1 U561 (.ZN(n742),
.B2(n868),
.B1(a[8]),
.A2(FE_OFN2_n322),
.A1(a[5]));
OAI221_X1 U562 (.ZN(n500),
.C2(n441),
.C1(FE_OFN3_n325),
.B2(n381),
.B1(n326),
.A(n718));
AOI22_X1 U563 (.ZN(n718),
.B2(n868),
.B1(a[25]),
.A2(FE_OFN2_n322),
.A1(a[28]));
OAI221_X1 U565 (.ZN(n192),
.C2(n304),
.C1(FE_OFN3_n325),
.B2(n328),
.B1(n326),
.A(n717));
AOI22_X1 U566 (.ZN(n717),
.B2(n868),
.B1(a[5]),
.A2(FE_OFN2_n322),
.A1(a[2]));
OAI221_X1 U568 (.ZN(n202),
.C2(n223),
.C1(FE_OFN3_n325),
.B2(n248),
.B1(n326),
.A(n719));
AOI22_X1 U569 (.ZN(n719),
.B2(a[9]),
.B1(n868),
.A2(FE_OFN2_n322),
.A1(a[6]));
OAI221_X1 U570 (.ZN(n562),
.C2(n381),
.C1(FE_OFN3_n325),
.B2(n348),
.B1(n326),
.A(n782));
AOI22_X1 U571 (.ZN(n782),
.B2(n868),
.B1(a[26]),
.A2(a[29]),
.A1(FE_OFN2_n322));
OAI221_X1 U572 (.ZN(n483),
.C2(FE_OFN3_n325),
.C1(n185),
.B2(n223),
.B1(n326),
.A(n783));
AOI22_X1 U573 (.ZN(n783),
.B2(n868),
.B1(a[10]),
.A2(FE_OFN2_n322),
.A1(a[7]));
AOI221_X1 U574 (.ZN(n207),
.C2(a[22]),
.C1(n865),
.B2(a[23]),
.B1(n344),
.A(n722));
OAI22_X1 U575 (.ZN(n722),
.B2(n834),
.B1(n538),
.A2(n872),
.A1(n485));
NOR2_X2 U576 (.ZN(n353),
.A2(b[2]),
.A1(n624));
OAI221_X1 U577 (.ZN(n254),
.C2(n641),
.C1(FE_OFN3_n325),
.B2(n627),
.B1(n326),
.A(n765));
AOI22_X1 U578 (.ZN(n765),
.B2(n868),
.B1(a[15]),
.A2(FE_OFN2_n322),
.A1(a[18]));
OAI221_X1 U579 (.ZN(n506),
.C2(n698),
.C1(FE_OFN3_n325),
.B2(n612),
.B1(n326),
.A(n723));
AOI22_X1 U580 (.ZN(n723),
.B2(n868),
.B1(a[13]),
.A2(FE_OFN2_n322),
.A1(a[10]));
OAI221_X1 U581 (.ZN(n563),
.C2(n504),
.C1(FE_OFN3_n325),
.B2(n485),
.B1(n326),
.A(n778));
AOI22_X1 U582 (.ZN(n778),
.B2(n868),
.B1(a[22]),
.A2(FE_OFN2_n322),
.A1(a[25]));
OAI221_X1 U583 (.ZN(n237),
.C2(n627),
.C1(FE_OFN3_n325),
.B2(n594),
.B1(n326),
.A(n813));
AOI22_X1 U584 (.ZN(n813),
.B2(n868),
.B1(a[16]),
.A2(FE_OFN2_n322),
.A1(a[19]));
OAI221_X1 U585 (.ZN(n442),
.C2(n654),
.C1(FE_OFN3_n325),
.B2(n668),
.B1(n326),
.A(n669));
AOI22_X1 U586 (.ZN(n669),
.B2(n868),
.B1(a[16]),
.A2(FE_OFN2_n322),
.A1(a[13]));
OAI221_X1 U587 (.ZN(n445),
.C2(n612),
.C1(FE_OFN3_n325),
.B2(n613),
.B1(n326),
.A(n741));
AOI22_X1 U588 (.ZN(n741),
.B2(n868),
.B1(a[12]),
.A2(a[9]),
.A1(FE_OFN2_n322));
NOR2_X1 U589 (.ZN(n344),
.A2(b[0]),
.A1(n711));
OAI221_X1 U590 (.ZN(n226),
.C2(n538),
.C1(FE_OFN3_n325),
.B2(n522),
.B1(n326),
.A(n812));
AOI22_X1 U591 (.ZN(n812),
.B2(n868),
.B1(a[20]),
.A2(FE_OFN2_n322),
.A1(a[23]));
OAI221_X1 U592 (.ZN(n421),
.C2(n558),
.C1(FE_OFN3_n325),
.B2(n578),
.B1(n326),
.A(n579));
AOI22_X1 U593 (.ZN(n579),
.B2(n868),
.B1(a[21]),
.A2(FE_OFN2_n322),
.A1(a[18]));
OAI221_X1 U594 (.ZN(n385),
.C2(n538),
.C1(FE_OFN3_n325),
.B2(n558),
.B1(n326),
.A(n559));
AOI22_X1 U595 (.ZN(n559),
.B2(n868),
.B1(a[22]),
.A2(FE_OFN2_n322),
.A1(a[19]));
OAI221_X1 U596 (.ZN(n354),
.C2(n522),
.C1(FE_OFN3_n325),
.B2(n538),
.B1(n326),
.A(n539));
AOI22_X1 U597 (.ZN(n539),
.B2(n868),
.B1(a[23]),
.A2(FE_OFN2_n322),
.A1(a[20]));
OAI221_X1 U598 (.ZN(n194),
.C2(n594),
.C1(FE_OFN3_n325),
.B2(n578),
.B1(n326),
.A(n721));
AOI22_X1 U599 (.ZN(n721),
.B2(n868),
.B1(a[17]),
.A2(FE_OFN2_n322),
.A1(a[20]));
OAI221_X1 U600 (.ZN(n625),
.C2(n558),
.C1(FE_OFN3_n325),
.B2(n538),
.B1(n326),
.A(n764));
AOI22_X1 U601 (.ZN(n764),
.B2(n868),
.B1(a[19]),
.A2(FE_OFN2_n322),
.A1(a[22]));
OAI221_X1 U602 (.ZN(n257),
.C2(n271),
.C1(FE_OFN3_n325),
.B2(n290),
.B1(n326),
.A(n760));
AOI22_X1 U603 (.ZN(n760),
.B2(n868),
.B1(a[7]),
.A2(FE_OFN2_n322),
.A1(a[4]));
OAI221_X1 U604 (.ZN(n451),
.C2(n348),
.C1(FE_OFN3_n325),
.B2(n326),
.B1(n382),
.A(n755));
AOI22_X1 U605 (.ZN(n755),
.B2(n868),
.B1(a[27]),
.A2(a[30]),
.A1(FE_OFN2_n322));
OAI221_X1 U606 (.ZN(n294),
.C2(n668),
.C1(FE_OFN3_n325),
.B2(n654),
.B1(n326),
.A(n724));
AOI22_X1 U607 (.ZN(n724),
.B2(n868),
.B1(a[13]),
.A2(FE_OFN2_n322),
.A1(a[16]));
OAI221_X1 U608 (.ZN(n236),
.C2(FE_OFN3_n325),
.C1(n185),
.B2(n613),
.B1(n326),
.A(n822));
AOI22_X1 U609 (.ZN(n822),
.B2(n868),
.B1(a[8]),
.A2(FE_OFN2_n322),
.A1(a[11]));
OAI221_X1 U610 (.ZN(n199),
.C2(n613),
.C1(FE_OFN3_n325),
.B2(n612),
.B1(n326),
.A(n614));
AOI22_X1 U611 (.ZN(n614),
.B2(a[9]),
.B1(n868),
.A2(FE_OFN2_n322),
.A1(a[12]));
OAI221_X1 U612 (.ZN(n419),
.C2(n641),
.C1(FE_OFN3_n325),
.B2(n654),
.B1(n326),
.A(n655));
AOI22_X1 U613 (.ZN(n655),
.B2(n868),
.B1(a[17]),
.A2(FE_OFN2_n322),
.A1(a[14]));
OAI221_X1 U614 (.ZN(n383),
.C2(n627),
.C1(FE_OFN3_n325),
.B2(n641),
.B1(n326),
.A(n642));
AOI22_X1 U615 (.ZN(n642),
.B2(n868),
.B1(a[18]),
.A2(FE_OFN2_n322),
.A1(a[15]));
OAI221_X1 U616 (.ZN(n350),
.C2(n594),
.C1(FE_OFN3_n325),
.B2(n627),
.B1(n326),
.A(n628));
AOI22_X1 U617 (.ZN(n628),
.B2(n868),
.B1(a[19]),
.A2(FE_OFN2_n322),
.A1(a[16]));
OAI221_X1 U618 (.ZN(n272),
.C2(n578),
.C1(FE_OFN3_n325),
.B2(n558),
.B1(n326),
.A(n776));
AOI22_X1 U619 (.ZN(n776),
.B2(n868),
.B1(a[18]),
.A2(FE_OFN2_n322),
.A1(a[21]));
OAI221_X1 U620 (.ZN(n233),
.C2(n678),
.C1(FE_OFN3_n325),
.B2(n668),
.B1(n326),
.A(n821));
AOI22_X1 U621 (.ZN(n821),
.B2(n868),
.B1(a[12]),
.A2(FE_OFN2_n322),
.A1(a[15]));
OAI221_X1 U622 (.ZN(n488),
.C2(n678),
.C1(FE_OFN3_n325),
.B2(n698),
.B1(n326),
.A(n699));
AOI22_X1 U623 (.ZN(n699),
.B2(n868),
.B1(a[14]),
.A2(FE_OFN2_n322),
.A1(a[11]));
OAI221_X1 U624 (.ZN(n444),
.C2(n578),
.C1(FE_OFN3_n325),
.B2(n594),
.B1(n326),
.A(n595));
AOI22_X1 U625 (.ZN(n595),
.B2(n868),
.B1(a[20]),
.A2(FE_OFN2_n322),
.A1(a[17]));
OAI221_X1 U626 (.ZN(n626),
.C2(n485),
.C1(FE_OFN3_n325),
.B2(n465),
.B1(n326),
.A(n759));
AOI22_X1 U627 (.ZN(n759),
.B2(n868),
.B1(a[23]),
.A2(a[26]),
.A1(FE_OFN2_n322));
OAI222_X1 U628 (.ZN(n435),
.C2(n343),
.C1(n438),
.B2(n437),
.B1(n694),
.A2(n308),
.A1(n436));
AOI221_X1 U629 (.ZN(n438),
.C2(n868),
.C1(a[28]),
.B2(FE_OFN2_n322),
.B1(a[25]),
.A(n440));
AOI222_X1 U630 (.ZN(n437),
.C2(n444),
.C1(n353),
.B2(n443),
.B1(n351),
.A2(n442),
.A1(n310));
AOI222_X1 U631 (.ZN(n436),
.C2(n224),
.C1(n351),
.B2(b[3]),
.B1(n446),
.A2(n445),
.A1(n439));
OAI222_X1 U632 (.ZN(n414),
.C2(n343),
.C1(n417),
.B2(n416),
.B1(n694),
.A2(n308),
.A1(n415));
AOI221_X1 U633 (.ZN(n415),
.C2(n197),
.C1(n310),
.B2(n192),
.B1(n353),
.A(n422));
AOI221_X1 U634 (.ZN(n417),
.C2(n868),
.C1(a[29]),
.B2(a[26]),
.B1(FE_OFN2_n322),
.A(n418));
AOI222_X1 U635 (.ZN(n416),
.C2(n421),
.C1(n353),
.B2(n420),
.B1(n351),
.A2(n419),
.A1(n310));
OAI222_X1 U636 (.ZN(n375),
.C2(n343),
.C1(n378),
.B2(n377),
.B1(n694),
.A2(n308),
.A1(n376));
AOI211_X1 U637 (.ZN(n378),
.C2(n344),
.C1(a[28]),
.B(n380),
.A(n379));
AOI221_X1 U638 (.ZN(n376),
.C2(n275),
.C1(n353),
.B2(FE_OFN9_n274),
.B1(n310),
.A(n386));
AOI222_X1 U639 (.ZN(n377),
.C2(n385),
.C1(n353),
.B2(n384),
.B1(n351),
.A2(n383),
.A1(n310));
OAI222_X1 U640 (.ZN(n339),
.C2(n343),
.C1(n342),
.B2(n341),
.B1(n694),
.A2(n308),
.A1(n340));
AOI211_X1 U641 (.ZN(n342),
.C2(a[29]),
.C1(n344),
.B(n346),
.A(n345));
AOI221_X1 U642 (.ZN(n340),
.C2(n257),
.C1(n353),
.B2(n256),
.B1(n310),
.A(n355));
AOI222_X1 U643 (.ZN(n341),
.C2(n354),
.C1(n353),
.B2(n352),
.B1(n351),
.A2(n350),
.A1(n310));
OAI221_X1 U644 (.ZN(n311),
.C2(n290),
.C1(FE_OFN3_n325),
.B2(n271),
.B1(n326),
.A(n819));
AOI22_X1 U645 (.ZN(n819),
.B2(n868),
.B1(a[4]),
.A2(FE_OFN2_n322),
.A1(a[7]));
AOI21_X1 U646 (.ZN(n560),
.B2(a[31]),
.B1(n834),
.A(n380));
OAI221_X1 U647 (.ZN(n384),
.C2(n465),
.C1(FE_OFN3_n325),
.B2(n485),
.B1(n326),
.A(n486));
AOI22_X1 U648 (.ZN(n486),
.B2(n868),
.B1(a[26]),
.A2(FE_OFN2_n322),
.A1(a[23]));
OAI221_X1 U649 (.ZN(n352),
.C2(n441),
.C1(FE_OFN3_n325),
.B2(n465),
.B1(n326),
.A(n466));
AOI22_X1 U650 (.ZN(n466),
.B2(n868),
.B1(a[27]),
.A2(FE_OFN2_n322),
.A1(a[24]));
OAI221_X1 U651 (.ZN(n291),
.C2(n271),
.C1(FE_OFN3_n325),
.B2(n248),
.B1(n326),
.A(n608));
AOI22_X1 U652 (.ZN(n608),
.B2(n868),
.B1(a[5]),
.A2(FE_OFN2_n322),
.A1(a[8]));
OAI221_X1 U653 (.ZN(n405),
.C2(n612),
.C1(FE_OFN3_n325),
.B2(n698),
.B1(n326),
.A(n777));
AOI22_X1 U654 (.ZN(n777),
.B2(n868),
.B1(a[10]),
.A2(FE_OFN2_n322),
.A1(a[13]));
OAI221_X1 U655 (.ZN(n331),
.C2(n698),
.C1(FE_OFN3_n325),
.B2(n678),
.B1(n326),
.A(n762));
AOI22_X1 U656 (.ZN(n762),
.B2(n868),
.B1(a[11]),
.A2(FE_OFN2_n322),
.A1(a[14]));
OAI221_X1 U657 (.ZN(n443),
.C2(n504),
.C1(FE_OFN3_n325),
.B2(n522),
.B1(n326),
.A(n523));
AOI22_X1 U658 (.ZN(n523),
.B2(n868),
.B1(a[24]),
.A2(FE_OFN2_n322),
.A1(a[21]));
OAI221_X1 U659 (.ZN(n420),
.C2(n485),
.C1(FE_OFN3_n325),
.B2(n504),
.B1(n326),
.A(n505));
AOI22_X1 U660 (.ZN(n505),
.B2(n868),
.B1(a[25]),
.A2(FE_OFN2_n322),
.A1(a[22]));
OAI221_X1 U661 (.ZN(n666),
.C2(n328),
.C1(FE_OFN3_n325),
.B2(n401),
.B1(n326),
.A(n738));
AOI22_X1 U662 (.ZN(n738),
.B2(n868),
.B1(a[4]),
.A2(FE_OFN2_n322),
.A1(a[1]));
OAI221_X1 U663 (.ZN(n402),
.C2(n654),
.C1(FE_OFN3_n325),
.B2(n641),
.B1(n326),
.A(n781));
AOI22_X1 U664 (.ZN(n781),
.B2(n868),
.B1(a[14]),
.A2(FE_OFN2_n322),
.A1(a[17]));
OAI221_X1 U665 (.ZN(n242),
.C2(n223),
.C1(FE_OFN3_n325),
.B2(n326),
.B1(n185),
.A(n327));
AOI22_X1 U666 (.ZN(n327),
.B2(n868),
.B1(a[7]),
.A2(FE_OFN2_n322),
.A1(a[10]));
OAI221_X1 U667 (.ZN(n542),
.C2(n613),
.C1(FE_OFN3_n325),
.B2(n326),
.B1(n185),
.A(n763));
AOI22_X1 U668 (.ZN(n763),
.B2(n868),
.B1(a[11]),
.A2(FE_OFN2_n322),
.A1(a[8]));
OAI221_X1 U669 (.ZN(n265),
.C2(n248),
.C1(FE_OFN3_n325),
.B2(n223),
.B1(n326),
.A(n400));
AOI22_X1 U670 (.ZN(n400),
.B2(n868),
.B1(a[6]),
.A2(a[9]),
.A1(FE_OFN2_n322));
OAI221_X1 U671 (.ZN(n629),
.C2(n668),
.C1(FE_OFN3_n325),
.B2(n678),
.B1(n326),
.A(n679));
AOI22_X1 U672 (.ZN(n679),
.B2(n868),
.B1(a[15]),
.A2(FE_OFN2_n322),
.A1(a[12]));
AOI22_X1 U673 (.ZN(n457),
.B2(n346),
.B1(b[2]),
.A2(n451),
.A1(n737));
AOI221_X1 U674 (.ZN(n398),
.C2(n868),
.C1(a[2]),
.B2(FE_OFN2_n322),
.B1(a[5]),
.A(n399));
OAI22_X1 U675 (.ZN(n399),
.B2(n304),
.B1(n326),
.A2(n328),
.A1(FE_OFN3_n325));
AOI221_X1 U676 (.ZN(n320),
.C2(n868),
.C1(a[3]),
.B2(FE_OFN2_n322),
.B1(a[6]),
.A(n324));
OAI22_X1 U677 (.ZN(n324),
.B2(n290),
.B1(n326),
.A2(n304),
.A1(FE_OFN3_n325));
AOI22_X1 U678 (.ZN(n572),
.B2(a[0]),
.B1(n865),
.A2(a[1]),
.A1(n868));
OAI221_X1 U679 (.ZN(n736),
.C2(n382),
.C1(FE_OFN3_n325),
.B2(n326),
.B1(n349),
.A(n814));
AOI22_X1 U680 (.ZN(n814),
.B2(n868),
.B1(a[28]),
.A2(a[31]),
.A1(FE_OFN2_n322));
AOI22_X1 U681 (.ZN(n446),
.B2(n228),
.B1(n737),
.A2(b[2]),
.A1(n231));
INV_X1 U682 (.ZN(n308),
.A(n694));
AOI21_X1 U683 (.ZN(n556),
.B2(a[31]),
.B1(n865),
.A(n380));
OAI221_X1 U684 (.ZN(n818),
.C2(n328),
.C1(n872),
.B2(n609),
.B1(FE_OFN3_n325),
.A(n820));
AOI21_X1 U685 (.ZN(n820),
.B2(n344),
.B1(a[2]),
.A(n661));
INV_X1 U686 (.ZN(n381),
.A(a[27]));
INV_X1 U687 (.ZN(n485),
.A(a[24]));
AOI22_X1 U688 (.ZN(n713),
.B2(a[30]),
.B1(n865),
.A2(a[29]),
.A1(n868));
INV_X1 U689 (.ZN(n624),
.A(b[3]));
INV_X1 U690 (.ZN(n712),
.A(a[31]));
XNOR2_X1 U691 (.ZN(n364),
.B(a[31]),
.A(n831));
INV_X1 U692 (.ZN(n185),
.A(a[9]));
INV_X1 U693 (.ZN(n304),
.A(a[4]));
INV_X1 U694 (.ZN(n328),
.A(a[3]));
INV_X1 U695 (.ZN(n290),
.A(a[5]));
INV_X1 U696 (.ZN(n271),
.A(a[6]));
INV_X1 U697 (.ZN(n248),
.A(a[7]));
INV_X1 U698 (.ZN(n613),
.A(a[10]));
INV_X1 U699 (.ZN(n612),
.A(a[11]));
INV_X1 U700 (.ZN(n558),
.A(a[20]));
INV_X1 U701 (.ZN(n641),
.A(a[16]));
INV_X1 U702 (.ZN(n627),
.A(a[17]));
INV_X1 U703 (.ZN(n594),
.A(a[18]));
INV_X1 U704 (.ZN(n578),
.A(a[19]));
INV_X1 U705 (.ZN(n654),
.A(a[15]));
INV_X1 U706 (.ZN(n678),
.A(a[13]));
INV_X1 U707 (.ZN(n668),
.A(a[14]));
NOR2_X1 U708 (.ZN(n322),
.A2(n823),
.A1(n711));
INV_X1 U709 (.ZN(n823),
.A(b[0]));
INV_X1 U710 (.ZN(n538),
.A(a[21]));
NAND2_X1 U711 (.ZN(n561),
.A2(a[31]),
.A1(n310));
INV_X1 U712 (.ZN(n348),
.A(a[28]));
INV_X1 U718 (.ZN(n401),
.A(a[2]));
INV_X1 U719 (.ZN(n522),
.A(a[22]));
INV_X1 U720 (.ZN(n223),
.A(a[8]));
INV_X1 U721 (.ZN(n698),
.A(a[12]));
INV_X1 U722 (.ZN(n737),
.A(b[2]));
NOR2_X2 U723 (.ZN(n351),
.A2(b[3]),
.A1(n737));
NOR2_X2 U724 (.ZN(n439),
.A2(b[2]),
.A1(b[3]));
INV_X1 U725 (.ZN(n349),
.A(a[30]));
INV_X1 U726 (.ZN(n382),
.A(a[29]));
INV_X1 U727 (.ZN(n441),
.A(a[26]));
INV_X1 U728 (.ZN(n711),
.A(b[1]));
INV_X1 U729 (.ZN(n465),
.A(a[25]));
INV_X1 U730 (.ZN(n504),
.A(a[23]));
INV_X1 U731 (.ZN(n609),
.A(a[1]));
NAND2_X1 U732 (.ZN(n325),
.A2(n711),
.A1(b[0]));
INV_X1 U733 (.ZN(n774),
.A(a[0]));
OR2_X1 U734 (.ZN(n834),
.A2(b[1]),
.A1(b[0]));
INV_X1 U735 (.ZN(n269),
.A(b[6]));
INV_X1 U736 (.ZN(n246),
.A(b[7]));
INV_X1 U737 (.ZN(n552),
.A(b[22]));
INV_X1 U738 (.ZN(n831),
.A(b[31]));
INV_X1 U759 (.ZN(n865),
.A(FE_OFN3_n325));
INV_X2 U762 (.ZN(n868),
.A(n834));
INV_X1 U763 (.ZN(n872),
.A(FE_OFN2_n322));
INV_X1 U764 (.ZN(n889),
.A(n189));
INV_X1 U765 (.ZN(n892),
.A(n188));
INV_X1 U768 (.ZN(n899),
.A(FE_OFN1_n187));
endmodule
module PSWreg (
rst,
clk,
unaligned,
ovf,
status);
input rst;
input clk;
input unaligned;
input ovf;
output [31:0] status;
assign status[31] = 1'b0 ;
assign status[30] = 1'b0 ;
assign status[29] = 1'b0 ;
assign status[28] = 1'b0 ;
assign status[27] = 1'b0 ;
assign status[26] = 1'b0 ;
assign status[25] = 1'b0 ;
assign status[24] = 1'b0 ;
assign status[23] = 1'b0 ;
assign status[22] = 1'b0 ;
assign status[21] = 1'b0 ;
assign status[20] = 1'b0 ;
assign status[19] = 1'b0 ;
assign status[18] = 1'b0 ;
assign status[17] = 1'b0 ;
assign status[16] = 1'b0 ;
assign status[15] = 1'b0 ;
assign status[14] = 1'b0 ;
assign status[13] = 1'b0 ;
assign status[12] = 1'b0 ;
assign status[11] = 1'b0 ;
assign status[10] = 1'b0 ;
assign status[9] = 1'b0 ;
assign status[8] = 1'b0 ;
assign status[7] = 1'b0 ;
assign status[6] = 1'b0 ;
assign status[5] = 1'b0 ;
assign status[4] = 1'b0 ;
assign status[3] = 1'b0 ;
assign status[2] = 1'b0 ;
endmodule
module branch_circ (
branch_type,
zero,
branch_taken);
input branch_type;
input zero;
output branch_taken;
XOR2_X1 U1 (.Z(branch_taken),
.B(branch_type),
.A(zero));
endmodule
module forward (
rt_addr_IDEX,
rs_addr_IDEX,
rd_addr_EXMEM,
rd_addr_MEMWB,
regwrite_EXMEM,
regwrite_MEMWB,
forwardA,
forwardB);
input [4:0] rt_addr_IDEX;
input [4:0] rs_addr_IDEX;
input [4:0] rd_addr_EXMEM;
input [4:0] rd_addr_MEMWB;
input regwrite_EXMEM;
input regwrite_MEMWB;
output [1:0] forwardA;
output [1:0] forwardB;
endmodule
module concat16 (
string16,
string32);
input [15:0] string16;
output [31:0] string32;
// Internal wires
wire \string16[15] ;
wire \string16[14] ;
wire \string16[13] ;
wire \string16[12] ;
wire \string16[11] ;
wire \string16[10] ;
wire \string16[9] ;
wire \string16[8] ;
wire \string16[7] ;
wire \string16[6] ;
wire \string16[5] ;
wire \string16[4] ;
wire \string16[3] ;
wire \string16[2] ;
wire \string16[1] ;
wire \string16[0] ;
assign string32[15] = 1'b0 ;
assign string32[14] = 1'b0 ;
assign string32[13] = 1'b0 ;
assign string32[12] = 1'b0 ;
assign string32[11] = 1'b0 ;
assign string32[10] = 1'b0 ;
assign string32[9] = 1'b0 ;
assign string32[8] = 1'b0 ;
assign string32[7] = 1'b0 ;
assign string32[6] = 1'b0 ;
assign string32[5] = 1'b0 ;
assign string32[4] = 1'b0 ;
assign string32[3] = 1'b0 ;
assign string32[2] = 1'b0 ;
assign string32[1] = 1'b0 ;
assign string32[0] = 1'b0 ;
assign string32[31] = \string16[15] ;
assign \string16[15] = string16[15] ;
assign string32[30] = \string16[14] ;
assign \string16[14] = string16[14] ;
assign string32[29] = \string16[13] ;
assign \string16[13] = string16[13] ;
assign string32[28] = \string16[12] ;
assign \string16[12] = string16[12] ;
assign string32[27] = \string16[11] ;
assign \string16[11] = string16[11] ;
assign string32[26] = \string16[10] ;
assign \string16[10] = string16[10] ;
assign string32[25] = \string16[9] ;
assign \string16[9] = string16[9] ;
assign string32[24] = \string16[8] ;
assign \string16[8] = string16[8] ;
assign string32[23] = \string16[7] ;
assign \string16[7] = string16[7] ;
assign string32[22] = \string16[6] ;
assign \string16[6] = string16[6] ;
assign string32[21] = \string16[5] ;
assign \string16[5] = string16[5] ;
assign string32[20] = \string16[4] ;
assign \string16[4] = string16[4] ;
assign string32[19] = \string16[3] ;
assign \string16[3] = string16[3] ;
assign string32[18] = \string16[2] ;
assign \string16[2] = string16[2] ;
assign string32[17] = \string16[1] ;
assign \string16[1] = string16[1] ;
assign string32[16] = \string16[0] ;
assign \string16[0] = string16[0] ;
endmodule
module reg_file (
read_address_1,
read_address_2,
write_address,
write_data,
reg_write,
rst,
data_reg_1,
data_reg_2);
input [4:0] read_address_1;
input [4:0] read_address_2;
input [4:0] write_address;
input [31:0] write_data;
input reg_write;
input rst;
output [31:0] data_reg_1;
output [31:0] data_reg_2;
// Internal wires
wire N4144;
assign N4144 = rst ;
endmodule
module extender (
immediate,
unsigned_value,
extended);
input [15:0] immediate;
input unsigned_value;
output [31:0] extended;
// Internal wires
wire \extended[16] ;
wire \immediate[15] ;
wire \immediate[14] ;
wire \immediate[13] ;
wire \immediate[12] ;
wire \immediate[11] ;
wire \immediate[10] ;
wire \immediate[9] ;
wire \immediate[8] ;
wire \immediate[7] ;
wire \immediate[6] ;
wire \immediate[5] ;
wire \immediate[4] ;
wire \immediate[3] ;
wire \immediate[2] ;
wire \immediate[1] ;
wire \immediate[0] ;
wire n2;
assign extended[31] = \extended[16] ;
assign extended[30] = \extended[16] ;
assign extended[29] = \extended[16] ;
assign extended[28] = \extended[16] ;
assign extended[27] = \extended[16] ;
assign extended[26] = \extended[16] ;
assign extended[25] = \extended[16] ;
assign extended[24] = \extended[16] ;
assign extended[23] = \extended[16] ;
assign extended[22] = \extended[16] ;
assign extended[21] = \extended[16] ;
assign extended[20] = \extended[16] ;
assign extended[19] = \extended[16] ;
assign extended[18] = \extended[16] ;
assign extended[17] = \extended[16] ;
assign extended[16] = \extended[16] ;
assign extended[15] = \immediate[15] ;
assign \immediate[15] = immediate[15] ;
assign extended[14] = \immediate[14] ;
assign \immediate[14] = immediate[14] ;
assign extended[13] = \immediate[13] ;
assign \immediate[13] = immediate[13] ;
assign extended[12] = \immediate[12] ;
assign \immediate[12] = immediate[12] ;
assign extended[11] = \immediate[11] ;
assign \immediate[11] = immediate[11] ;
assign extended[10] = \immediate[10] ;
assign \immediate[10] = immediate[10] ;
assign extended[9] = \immediate[9] ;
assign \immediate[9] = immediate[9] ;
assign extended[8] = \immediate[8] ;
assign \immediate[8] = immediate[8] ;
assign extended[7] = \immediate[7] ;
assign \immediate[7] = immediate[7] ;
assign extended[6] = \immediate[6] ;
assign \immediate[6] = immediate[6] ;
assign extended[5] = \immediate[5] ;
assign \immediate[5] = immediate[5] ;
assign extended[4] = \immediate[4] ;
assign \immediate[4] = immediate[4] ;
assign extended[3] = \immediate[3] ;
assign \immediate[3] = immediate[3] ;
assign extended[2] = \immediate[2] ;
assign \immediate[2] = immediate[2] ;
assign extended[1] = \immediate[1] ;
assign \immediate[1] = immediate[1] ;
assign extended[0] = \immediate[0] ;
assign \immediate[0] = immediate[0] ;
NOR2_X1 U2 (.ZN(\extended[16] ),
.A2(n2),
.A1(unsigned_value));
INV_X1 U3 (.ZN(n2),
.A(\immediate[15] ));
endmodule
module sign_extender (
immediate_jump,
extended_jump);
input [25:0] immediate_jump;
output [31:0] extended_jump;
// Internal wires
wire extended_jump_31;
assign extended_jump[31] = extended_jump_31 ;
assign extended_jump[30] = extended_jump_31 ;
assign extended_jump[29] = extended_jump_31 ;
assign extended_jump[28] = extended_jump_31 ;
assign extended_jump[27] = extended_jump_31 ;
assign extended_jump[26] = extended_jump_31 ;
assign extended_jump[25] = extended_jump_31 ;
assign extended_jump_31 = immediate_jump[25] ;
assign extended_jump[24] = immediate_jump[24] ;
assign extended_jump[23] = immediate_jump[23] ;
assign extended_jump[22] = immediate_jump[22] ;
assign extended_jump[21] = immediate_jump[21] ;
assign extended_jump[20] = immediate_jump[20] ;
assign extended_jump[19] = immediate_jump[19] ;
assign extended_jump[18] = immediate_jump[18] ;
assign extended_jump[17] = immediate_jump[17] ;
assign extended_jump[16] = immediate_jump[16] ;
assign extended_jump[15] = immediate_jump[15] ;
assign extended_jump[14] = immediate_jump[14] ;
assign extended_jump[13] = immediate_jump[13] ;
assign extended_jump[12] = immediate_jump[12] ;
assign extended_jump[11] = immediate_jump[11] ;
assign extended_jump[10] = immediate_jump[10] ;
assign extended_jump[9] = immediate_jump[9] ;
assign extended_jump[8] = immediate_jump[8] ;
assign extended_jump[7] = immediate_jump[7] ;
assign extended_jump[6] = immediate_jump[6] ;
assign extended_jump[5] = immediate_jump[5] ;
assign extended_jump[4] = immediate_jump[4] ;
assign extended_jump[3] = immediate_jump[3] ;
assign extended_jump[2] = immediate_jump[2] ;
assign extended_jump[1] = immediate_jump[1] ;
assign extended_jump[0] = immediate_jump[0] ;
endmodule
module mux_stall (
cw_from_cu,
mux_op,
cw_from_mux);
input [22:0] cw_from_cu;
input mux_op;
output [22:0] cw_from_mux;
// Internal wires
wire n2;
AND2_X1 U2 (.ZN(cw_from_mux[7]),
.A2(n2),
.A1(cw_from_cu[7]));
AND2_X1 U3 (.ZN(cw_from_mux[12]),
.A2(n2),
.A1(cw_from_cu[12]));
AND2_X1 U4 (.ZN(cw_from_mux[16]),
.A2(n2),
.A1(cw_from_cu[16]));
AND2_X1 U5 (.ZN(cw_from_mux[18]),
.A2(n2),
.A1(cw_from_cu[18]));
INV_X1 U6 (.ZN(n2),
.A(mux_op));
AND2_X1 U7 (.ZN(cw_from_mux[0]),
.A2(n2),
.A1(cw_from_cu[0]));
AND2_X1 U8 (.ZN(cw_from_mux[1]),
.A2(n2),
.A1(cw_from_cu[1]));
AND2_X1 U9 (.ZN(cw_from_mux[5]),
.A2(n2),
.A1(cw_from_cu[5]));
AND2_X1 U10 (.ZN(cw_from_mux[6]),
.A2(n2),
.A1(cw_from_cu[6]));
AND2_X1 U11 (.ZN(cw_from_mux[8]),
.A2(n2),
.A1(cw_from_cu[8]));
AND2_X1 U12 (.ZN(cw_from_mux[9]),
.A2(n2),
.A1(cw_from_cu[9]));
AND2_X1 U13 (.ZN(cw_from_mux[10]),
.A2(n2),
.A1(cw_from_cu[10]));
AND2_X1 U14 (.ZN(cw_from_mux[13]),
.A2(n2),
.A1(cw_from_cu[13]));
AND2_X1 U15 (.ZN(cw_from_mux[17]),
.A2(n2),
.A1(cw_from_cu[17]));
AND2_X1 U16 (.ZN(cw_from_mux[20]),
.A2(n2),
.A1(cw_from_cu[20]));
AND2_X1 U17 (.ZN(cw_from_mux[22]),
.A2(n2),
.A1(cw_from_cu[22]));
AND2_X1 U18 (.ZN(cw_from_mux[21]),
.A2(n2),
.A1(cw_from_cu[21]));
AND2_X1 U19 (.ZN(cw_from_mux[2]),
.A2(n2),
.A1(cw_from_cu[2]));
AND2_X1 U20 (.ZN(cw_from_mux[3]),
.A2(n2),
.A1(cw_from_cu[3]));
AND2_X1 U21 (.ZN(cw_from_mux[4]),
.A2(n2),
.A1(cw_from_cu[4]));
AND2_X1 U22 (.ZN(cw_from_mux[11]),
.A2(n2),
.A1(cw_from_cu[11]));
AND2_X1 U23 (.ZN(cw_from_mux[14]),
.A2(n2),
.A1(cw_from_cu[14]));
AND2_X1 U24 (.ZN(cw_from_mux[15]),
.A2(n2),
.A1(cw_from_cu[15]));
AND2_X1 U25 (.ZN(cw_from_mux[19]),
.A2(n2),
.A1(cw_from_cu[19]));
endmodule
module hdu (
clk,
rst,
idex_mem_read,
idex_rt,
rs,
rt,
pcwrite,
ifidwrite,
mux_op);
input clk;
input rst;
input [3:0] idex_mem_read;
input [4:0] idex_rt;
input [4:0] rs;
input [4:0] rt;
output pcwrite;
output ifidwrite;
output mux_op;
// Internal wires
wire N7;
wire N8;
wire n6;
wire net41391;
wire n7;
wire n8;
wire n9;
wire n11;
wire n12;
wire n13;
wire n14;
wire n15;
wire n16;
wire n17;
wire n18;
wire n19;
wire n20;
wire n21;
wire n22;
wire n23;
wire n24;
wire n25;
assign pcwrite = ifidwrite ;
DFF_X1 \current_state_reg[0] (.QN(net41391),
.D(N7),
.CK(clk));
DFF_X1 \current_state_reg[1] (.QN(n25),
.Q(n6),
.D(N8),
.CK(clk));
OAI33_X1 U18 (.ZN(n11),
.B3(n18),
.B2(n17),
.B1(n16),
.A3(n15),
.A2(n14),
.A1(n13));
XOR2_X1 U19 (.Z(n18),
.B(idex_rt[4]),
.A(rt[4]));
XOR2_X1 U20 (.Z(n17),
.B(idex_rt[2]),
.A(rt[2]));
NAND3_X1 U21 (.ZN(n16),
.A3(n21),
.A2(n20),
.A1(n19));
XOR2_X1 U22 (.Z(n15),
.B(idex_rt[4]),
.A(rs[4]));
XOR2_X1 U23 (.Z(n14),
.B(idex_rt[3]),
.A(rs[3]));
NAND3_X1 U24 (.ZN(n13),
.A3(n24),
.A2(n23),
.A1(n22));
INV_X1 U3 (.ZN(ifidwrite),
.A(n7));
NOR3_X1 U4 (.ZN(mux_op),
.A3(n9),
.A2(net41391),
.A1(n6));
AOI21_X1 U5 (.ZN(n7),
.B2(n9),
.B1(n25),
.A(net41391));
NAND2_X1 U6 (.ZN(n9),
.A2(n12),
.A1(n11));
OR4_X1 U7 (.ZN(n12),
.A4(idex_mem_read[2]),
.A3(idex_mem_read[3]),
.A2(idex_mem_read[0]),
.A1(idex_mem_read[1]));
XNOR2_X1 U8 (.ZN(n22),
.B(rs[0]),
.A(idex_rt[0]));
XNOR2_X1 U9 (.ZN(n23),
.B(rs[1]),
.A(idex_rt[1]));
XNOR2_X1 U10 (.ZN(n24),
.B(rs[2]),
.A(idex_rt[2]));
XNOR2_X1 U11 (.ZN(n20),
.B(rt[0]),
.A(idex_rt[0]));
XNOR2_X1 U12 (.ZN(n19),
.B(rt[3]),
.A(idex_rt[3]));
XNOR2_X1 U13 (.ZN(n21),
.B(rt[1]),
.A(idex_rt[1]));
NOR2_X1 U14 (.ZN(N7),
.A2(n7),
.A1(rst));
NOR2_X1 U15 (.ZN(N8),
.A2(n8),
.A1(rst));
INV_X1 U16 (.ZN(n8),
.A(mux_op));
endmodule
module iram_block (
from_pc,
flush,
from_iram,
to_iram,
to_if_id_reg);
input [31:0] from_pc;
input flush;
input [31:0] from_iram;
output [31:0] to_iram;
output [31:0] to_if_id_reg;
// Internal wires
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
assign to_iram[31] = 1'b0 ;
assign to_iram[30] = 1'b0 ;
mmu_in_iram mmu_in (.from_pc(from_pc),
.to_iram({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
to_iram[29],
to_iram[28],
to_iram[27],
to_iram[26],
to_iram[25],
to_iram[24],
to_iram[23],
to_iram[22],
to_iram[21],
to_iram[20],
to_iram[19],
to_iram[18],
to_iram[17],
to_iram[16],
to_iram[15],
to_iram[14],
to_iram[13],
to_iram[12],
to_iram[11],
to_iram[10],
to_iram[9],
to_iram[8],
to_iram[7],
to_iram[6],
to_iram[5],
to_iram[4],
to_iram[3],
to_iram[2],
to_iram[1],
to_iram[0] }));
mmu_out_iram mmu_out (.from_iram(from_iram),
.flush(flush),
.to_if_id_reg(to_if_id_reg));
endmodule
module increment_pc (
from_pc,
to_mux_branch);
input [31:0] from_pc;
output [31:0] to_mux_branch;
increment_pc_DW01_add_0 add_33 (.A(from_pc),
.B({ 1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b1,
1'b0,
1'b0 }),
.CI(1'b0),
.SUM(to_mux_branch));
endmodule
module pc (
from_mux_jump,
pcwrite,
clk,
rst,
to_iram_block,
clk__L2_N1,
clk__L2_N2,
clk__L2_N3,
clk__L2_N4);
input [31:0] from_mux_jump;
input pcwrite;
input clk;
input rst;
output [31:0] to_iram_block;
input clk__L2_N1;
input clk__L2_N2;
input clk__L2_N3;
input clk__L2_N4;
// Internal wires
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n34;
wire n35;
wire n132;
DFF_X1 \to_iram_block_reg[31] (.QN(n37),
.Q(to_iram_block[31]),
.D(n100),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[30] (.QN(n38),
.Q(to_iram_block[30]),
.D(n99),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[29] (.QN(n39),
.Q(to_iram_block[29]),
.D(n98),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[28] (.QN(n40),
.Q(to_iram_block[28]),
.D(n97),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[27] (.QN(n41),
.Q(to_iram_block[27]),
.D(n96),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[26] (.QN(n42),
.Q(to_iram_block[26]),
.D(n95),
.CK(clk__L2_N2));
DFF_X1 \to_iram_block_reg[25] (.QN(n43),
.Q(to_iram_block[25]),
.D(n94),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[24] (.QN(n44),
.Q(to_iram_block[24]),
.D(n93),
.CK(clk));
DFF_X1 \to_iram_block_reg[23] (.QN(n45),
.Q(to_iram_block[23]),
.D(n92),
.CK(clk));
DFF_X1 \to_iram_block_reg[22] (.QN(n46),
.Q(to_iram_block[22]),
.D(n91),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[21] (.QN(n47),
.Q(to_iram_block[21]),
.D(n90),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[20] (.QN(n48),
.Q(to_iram_block[20]),
.D(n89),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[19] (.QN(n49),
.Q(to_iram_block[19]),
.D(n88),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[18] (.QN(n50),
.Q(to_iram_block[18]),
.D(n87),
.CK(clk));
DFF_X1 \to_iram_block_reg[17] (.QN(n51),
.Q(to_iram_block[17]),
.D(n86),
.CK(clk));
DFF_X1 \to_iram_block_reg[16] (.QN(n52),
.Q(to_iram_block[16]),
.D(n85),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[15] (.QN(n53),
.Q(to_iram_block[15]),
.D(n84),
.CK(clk));
DFF_X1 \to_iram_block_reg[14] (.QN(n54),
.Q(to_iram_block[14]),
.D(n83),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[13] (.QN(n55),
.Q(to_iram_block[13]),
.D(n82),
.CK(clk__L2_N4));
DFF_X1 \to_iram_block_reg[12] (.QN(n56),
.Q(to_iram_block[12]),
.D(n81),
.CK(clk__L2_N2));
DFF_X1 \to_iram_block_reg[11] (.QN(n57),
.Q(to_iram_block[11]),
.D(n80),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[10] (.QN(n58),
.Q(to_iram_block[10]),
.D(n79),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[9] (.QN(n59),
.Q(to_iram_block[9]),
.D(n78),
.CK(clk__L2_N2));
DFF_X1 \to_iram_block_reg[8] (.QN(n60),
.Q(to_iram_block[8]),
.D(n77),
.CK(clk__L2_N4));
DFF_X1 \to_iram_block_reg[7] (.QN(n61),
.Q(to_iram_block[7]),
.D(n76),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[6] (.QN(n62),
.Q(to_iram_block[6]),
.D(n75),
.CK(clk__L2_N2));
DFF_X1 \to_iram_block_reg[5] (.QN(n63),
.Q(to_iram_block[5]),
.D(n74),
.CK(clk__L2_N3));
DFF_X1 \to_iram_block_reg[4] (.QN(n64),
.Q(to_iram_block[4]),
.D(n73),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[3] (.QN(n65),
.Q(to_iram_block[3]),
.D(n72),
.CK(clk));
DFF_X1 \to_iram_block_reg[2] (.QN(n66),
.Q(to_iram_block[2]),
.D(n71),
.CK(clk));
DFF_X1 \to_iram_block_reg[1] (.QN(n67),
.Q(to_iram_block[1]),
.D(n70),
.CK(clk__L2_N1));
DFF_X1 \to_iram_block_reg[0] (.QN(n68),
.Q(to_iram_block[0]),
.D(n69),
.CK(clk));
OAI22_X1 U9 (.ZN(n92),
.B2(from_mux_jump[23]),
.B1(n35),
.A2(n45),
.A1(n34));
OAI22_X1 U11 (.ZN(n93),
.B2(from_mux_jump[24]),
.B1(n35),
.A2(n44),
.A1(n34));
OAI22_X1 U13 (.ZN(n96),
.B2(from_mux_jump[27]),
.B1(n35),
.A2(n41),
.A1(n34));
OAI22_X1 U15 (.ZN(n97),
.B2(from_mux_jump[28]),
.B1(n35),
.A2(n40),
.A1(n34));
OAI22_X1 U17 (.ZN(n84),
.B2(from_mux_jump[15]),
.B1(n35),
.A2(n53),
.A1(n34));
OAI22_X1 U19 (.ZN(n85),
.B2(from_mux_jump[16]),
.B1(n35),
.A2(n52),
.A1(n34));
OAI22_X1 U21 (.ZN(n88),
.B2(from_mux_jump[19]),
.B1(n35),
.A2(n49),
.A1(n34));
OAI22_X1 U23 (.ZN(n100),
.B2(from_mux_jump[31]),
.B1(n35),
.A2(n37),
.A1(n34));
OAI22_X1 U25 (.ZN(n83),
.B2(from_mux_jump[14]),
.B1(n35),
.A2(n54),
.A1(n34));
OAI22_X1 U27 (.ZN(n86),
.B2(from_mux_jump[17]),
.B1(n35),
.A2(n51),
.A1(n34));
OAI22_X1 U29 (.ZN(n87),
.B2(from_mux_jump[18]),
.B1(n35),
.A2(n50),
.A1(n34));
OAI22_X1 U31 (.ZN(n89),
.B2(from_mux_jump[20]),
.B1(n35),
.A2(n48),
.A1(n34));
OAI22_X1 U33 (.ZN(n90),
.B2(from_mux_jump[21]),
.B1(n35),
.A2(n47),
.A1(n34));
OAI22_X1 U35 (.ZN(n91),
.B2(from_mux_jump[22]),
.B1(n35),
.A2(n46),
.A1(n34));
OAI22_X1 U37 (.ZN(n94),
.B2(from_mux_jump[25]),
.B1(n35),
.A2(n43),
.A1(n34));
OAI22_X1 U39 (.ZN(n95),
.B2(from_mux_jump[26]),
.B1(n35),
.A2(n42),
.A1(n34));
OAI22_X1 U41 (.ZN(n98),
.B2(from_mux_jump[29]),
.B1(n35),
.A2(n39),
.A1(n34));
OAI22_X1 U43 (.ZN(n99),
.B2(from_mux_jump[30]),
.B1(n35),
.A2(n38),
.A1(n34));
OAI22_X1 U45 (.ZN(n69),
.B2(from_mux_jump[0]),
.B1(n35),
.A2(n68),
.A1(n34));
OAI22_X1 U47 (.ZN(n70),
.B2(from_mux_jump[1]),
.B1(n35),
.A2(n67),
.A1(n34));
OAI22_X1 U49 (.ZN(n71),
.B2(from_mux_jump[2]),
.B1(n35),
.A2(n66),
.A1(n34));
OAI22_X1 U51 (.ZN(n72),
.B2(from_mux_jump[3]),
.B1(n35),
.A2(n65),
.A1(n34));
OAI22_X1 U53 (.ZN(n73),
.B2(from_mux_jump[4]),
.B1(n35),
.A2(n64),
.A1(n34));
OAI22_X1 U55 (.ZN(n74),
.B2(from_mux_jump[5]),
.B1(n35),
.A2(n63),
.A1(n34));
OAI22_X1 U57 (.ZN(n75),
.B2(from_mux_jump[6]),
.B1(n35),
.A2(n62),
.A1(n34));
OAI22_X1 U59 (.ZN(n76),
.B2(from_mux_jump[7]),
.B1(n35),
.A2(n61),
.A1(n34));
OAI22_X1 U61 (.ZN(n77),
.B2(from_mux_jump[8]),
.B1(n35),
.A2(n60),
.A1(n34));
OAI22_X1 U63 (.ZN(n78),
.B2(from_mux_jump[9]),
.B1(n35),
.A2(n59),
.A1(n34));
OAI22_X1 U65 (.ZN(n79),
.B2(from_mux_jump[10]),
.B1(n35),
.A2(n58),
.A1(n34));
OAI22_X1 U67 (.ZN(n80),
.B2(from_mux_jump[11]),
.B1(n35),
.A2(n57),
.A1(n34));
OAI22_X1 U69 (.ZN(n81),
.B2(from_mux_jump[12]),
.B1(n35),
.A2(n56),
.A1(n34));
NAND2_X2 U71 (.ZN(n35),
.A2(n34),
.A1(n132));
INV_X1 U72 (.ZN(n132),
.A(rst));
OR2_X2 U73 (.ZN(n34),
.A2(rst),
.A1(pcwrite));
OAI22_X1 U74 (.ZN(n82),
.B2(from_mux_jump[13]),
.B1(n35),
.A2(n55),
.A1(n34));
endmodule
module mux_jump (
jump_address,
from_mux_branch,
jump,
to_pc);
input [31:0] jump_address;
input [31:0] from_mux_branch;
input jump;
output [31:0] to_pc;
// Internal wires
wire n15;
wire n16;
wire n17;
wire n18;
INV_X2 U1 (.ZN(n18),
.A(n17));
AOI22_X1 U13 (.ZN(to_pc[23]),
.B2(n16),
.B1(jump_address[23]),
.A2(n18),
.A1(from_mux_branch[23]));
AOI22_X1 U15 (.ZN(to_pc[24]),
.B2(n16),
.B1(jump_address[24]),
.A2(n18),
.A1(from_mux_branch[24]));
AOI22_X1 U17 (.ZN(to_pc[27]),
.B2(n16),
.B1(jump_address[27]),
.A2(n18),
.A1(from_mux_branch[27]));
AOI22_X1 U19 (.ZN(to_pc[28]),
.B2(n15),
.B1(jump_address[28]),
.A2(n18),
.A1(from_mux_branch[28]));
AOI22_X1 U21 (.ZN(to_pc[15]),
.B2(n17),
.B1(jump_address[15]),
.A2(n18),
.A1(from_mux_branch[15]));
AOI22_X1 U23 (.ZN(to_pc[16]),
.B2(n17),
.B1(jump_address[16]),
.A2(n18),
.A1(from_mux_branch[16]));
AOI22_X1 U25 (.ZN(to_pc[19]),
.B2(n16),
.B1(jump_address[19]),
.A2(n18),
.A1(from_mux_branch[19]));
AOI22_X1 U27 (.ZN(to_pc[31]),
.B2(n15),
.B1(jump_address[31]),
.A2(n18),
.A1(from_mux_branch[31]));
AOI22_X1 U29 (.ZN(to_pc[14]),
.B2(n17),
.B1(jump_address[14]),
.A2(n18),
.A1(from_mux_branch[14]));
AOI22_X1 U31 (.ZN(to_pc[17]),
.B2(n16),
.B1(jump_address[17]),
.A2(n18),
.A1(from_mux_branch[17]));
AOI22_X1 U33 (.ZN(to_pc[18]),
.B2(n16),
.B1(jump_address[18]),
.A2(n18),
.A1(from_mux_branch[18]));
AOI22_X1 U35 (.ZN(to_pc[20]),
.B2(n16),
.B1(jump_address[20]),
.A2(n18),
.A1(from_mux_branch[20]));
AOI22_X1 U37 (.ZN(to_pc[21]),
.B2(n16),
.B1(jump_address[21]),
.A2(n18),
.A1(from_mux_branch[21]));
AOI22_X1 U39 (.ZN(to_pc[22]),
.B2(n16),
.B1(jump_address[22]),
.A2(n18),
.A1(from_mux_branch[22]));
AOI22_X1 U41 (.ZN(to_pc[25]),
.B2(n16),
.B1(jump_address[25]),
.A2(n18),
.A1(from_mux_branch[25]));
AOI22_X1 U43 (.ZN(to_pc[26]),
.B2(n16),
.B1(jump_address[26]),
.A2(n18),
.A1(from_mux_branch[26]));
AOI22_X1 U45 (.ZN(to_pc[29]),
.B2(n15),
.B1(jump_address[29]),
.A2(n18),
.A1(from_mux_branch[29]));
AOI22_X1 U47 (.ZN(to_pc[30]),
.B2(n15),
.B1(jump_address[30]),
.A2(n18),
.A1(from_mux_branch[30]));
AOI22_X1 U49 (.ZN(to_pc[0]),
.B2(n17),
.B1(jump_address[0]),
.A2(n18),
.A1(from_mux_branch[0]));
AOI22_X1 U51 (.ZN(to_pc[1]),
.B2(n16),
.B1(jump_address[1]),
.A2(n18),
.A1(from_mux_branch[1]));
AOI22_X1 U53 (.ZN(to_pc[2]),
.B2(n15),
.B1(jump_address[2]),
.A2(n18),
.A1(from_mux_branch[2]));
AOI22_X1 U55 (.ZN(to_pc[3]),
.B2(n15),
.B1(jump_address[3]),
.A2(n18),
.A1(from_mux_branch[3]));
AOI22_X1 U57 (.ZN(to_pc[4]),
.B2(n15),
.B1(jump_address[4]),
.A2(n18),
.A1(from_mux_branch[4]));
AOI22_X1 U59 (.ZN(to_pc[5]),
.B2(n15),
.B1(jump_address[5]),
.A2(n18),
.A1(from_mux_branch[5]));
AOI22_X1 U61 (.ZN(to_pc[6]),
.B2(n15),
.B1(jump_address[6]),
.A2(n18),
.A1(from_mux_branch[6]));
AOI22_X1 U63 (.ZN(to_pc[7]),
.B2(n15),
.B1(jump_address[7]),
.A2(n18),
.A1(from_mux_branch[7]));
AOI22_X1 U65 (.ZN(to_pc[8]),
.B2(n15),
.B1(jump_address[8]),
.A2(n18),
.A1(from_mux_branch[8]));
AOI22_X1 U67 (.ZN(to_pc[9]),
.B2(n15),
.B1(jump_address[9]),
.A2(n18),
.A1(from_mux_branch[9]));
AOI22_X1 U69 (.ZN(to_pc[10]),
.B2(n17),
.B1(jump_address[10]),
.A2(n18),
.A1(from_mux_branch[10]));
AOI22_X1 U71 (.ZN(to_pc[11]),
.B2(n17),
.B1(jump_address[11]),
.A2(n18),
.A1(from_mux_branch[11]));
AOI22_X1 U73 (.ZN(to_pc[12]),
.B2(n17),
.B1(jump_address[12]),
.A2(n18),
.A1(from_mux_branch[12]));
BUF_X1 U74 (.Z(n17),
.A(jump));
BUF_X1 U75 (.Z(n16),
.A(jump));
BUF_X1 U76 (.Z(n15),
.A(jump));
AOI22_X1 U78 (.ZN(to_pc[13]),
.B2(n17),
.B1(jump_address[13]),
.A2(n18),
.A1(from_mux_branch[13]));
endmodule
module mux_branch (
from_increment_pc,
branch_target,
pcsrc,
to_mux_jump);
input [31:0] from_increment_pc;
input [31:0] branch_target;
input pcsrc;
output [31:0] to_mux_jump;
// Internal wires
wire n34;
wire n36;
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n22;
INV_X2 U11 (.ZN(n22),
.A(pcsrc));
INV_X1 U12 (.ZN(to_mux_jump[14]),
.A(n61));
AOI22_X1 U13 (.ZN(n61),
.B2(n22),
.B1(from_increment_pc[14]),
.A2(pcsrc),
.A1(branch_target[14]));
INV_X1 U14 (.ZN(to_mux_jump[15]),
.A(n60));
AOI22_X1 U15 (.ZN(n60),
.B2(n22),
.B1(from_increment_pc[15]),
.A2(pcsrc),
.A1(branch_target[15]));
INV_X1 U16 (.ZN(to_mux_jump[16]),
.A(n59));
AOI22_X1 U17 (.ZN(n59),
.B2(n22),
.B1(from_increment_pc[16]),
.A2(pcsrc),
.A1(branch_target[16]));
INV_X1 U18 (.ZN(to_mux_jump[17]),
.A(n58));
AOI22_X1 U19 (.ZN(n58),
.B2(n22),
.B1(from_increment_pc[17]),
.A2(pcsrc),
.A1(branch_target[17]));
INV_X1 U20 (.ZN(to_mux_jump[18]),
.A(n57));
AOI22_X1 U21 (.ZN(n57),
.B2(n22),
.B1(from_increment_pc[18]),
.A2(pcsrc),
.A1(branch_target[18]));
INV_X1 U22 (.ZN(to_mux_jump[19]),
.A(n56));
AOI22_X1 U23 (.ZN(n56),
.B2(n22),
.B1(from_increment_pc[19]),
.A2(pcsrc),
.A1(branch_target[19]));
INV_X1 U24 (.ZN(to_mux_jump[20]),
.A(n54));
AOI22_X1 U25 (.ZN(n54),
.B2(n22),
.B1(from_increment_pc[20]),
.A2(pcsrc),
.A1(branch_target[20]));
INV_X1 U26 (.ZN(to_mux_jump[21]),
.A(n53));
AOI22_X1 U27 (.ZN(n53),
.B2(n22),
.B1(from_increment_pc[21]),
.A2(pcsrc),
.A1(branch_target[21]));
INV_X1 U28 (.ZN(to_mux_jump[22]),
.A(n52));
AOI22_X1 U29 (.ZN(n52),
.B2(n22),
.B1(from_increment_pc[22]),
.A2(pcsrc),
.A1(branch_target[22]));
INV_X1 U30 (.ZN(to_mux_jump[23]),
.A(n51));
AOI22_X1 U31 (.ZN(n51),
.B2(n22),
.B1(from_increment_pc[23]),
.A2(pcsrc),
.A1(branch_target[23]));
INV_X1 U32 (.ZN(to_mux_jump[24]),
.A(n50));
AOI22_X1 U33 (.ZN(n50),
.B2(n22),
.B1(from_increment_pc[24]),
.A2(pcsrc),
.A1(branch_target[24]));
INV_X1 U34 (.ZN(to_mux_jump[25]),
.A(n49));
AOI22_X1 U35 (.ZN(n49),
.B2(n22),
.B1(from_increment_pc[25]),
.A2(pcsrc),
.A1(branch_target[25]));
INV_X1 U36 (.ZN(to_mux_jump[26]),
.A(n48));
AOI22_X1 U37 (.ZN(n48),
.B2(n22),
.B1(from_increment_pc[26]),
.A2(pcsrc),
.A1(branch_target[26]));
INV_X1 U38 (.ZN(to_mux_jump[27]),
.A(n47));
AOI22_X1 U39 (.ZN(n47),
.B2(n22),
.B1(from_increment_pc[27]),
.A2(pcsrc),
.A1(branch_target[27]));
INV_X1 U40 (.ZN(to_mux_jump[28]),
.A(n46));
AOI22_X1 U41 (.ZN(n46),
.B2(n22),
.B1(from_increment_pc[28]),
.A2(pcsrc),
.A1(branch_target[28]));
INV_X1 U42 (.ZN(to_mux_jump[29]),
.A(n45));
AOI22_X1 U43 (.ZN(n45),
.B2(n22),
.B1(from_increment_pc[29]),
.A2(pcsrc),
.A1(branch_target[29]));
INV_X1 U44 (.ZN(to_mux_jump[30]),
.A(n43));
AOI22_X1 U45 (.ZN(n43),
.B2(n22),
.B1(from_increment_pc[30]),
.A2(pcsrc),
.A1(branch_target[30]));
INV_X1 U46 (.ZN(to_mux_jump[31]),
.A(n42));
AOI22_X1 U47 (.ZN(n42),
.B2(n22),
.B1(from_increment_pc[31]),
.A2(pcsrc),
.A1(branch_target[31]));
INV_X1 U48 (.ZN(to_mux_jump[9]),
.A(n34));
AOI22_X1 U49 (.ZN(n34),
.B2(n22),
.B1(from_increment_pc[9]),
.A2(branch_target[9]),
.A1(pcsrc));
INV_X1 U50 (.ZN(to_mux_jump[3]),
.A(n41));
AOI22_X1 U51 (.ZN(n41),
.B2(n22),
.B1(from_increment_pc[3]),
.A2(pcsrc),
.A1(branch_target[3]));
INV_X1 U52 (.ZN(to_mux_jump[4]),
.A(n40));
AOI22_X1 U53 (.ZN(n40),
.B2(n22),
.B1(from_increment_pc[4]),
.A2(pcsrc),
.A1(branch_target[4]));
INV_X1 U54 (.ZN(to_mux_jump[5]),
.A(n39));
AOI22_X1 U55 (.ZN(n39),
.B2(n22),
.B1(from_increment_pc[5]),
.A2(pcsrc),
.A1(branch_target[5]));
INV_X1 U56 (.ZN(to_mux_jump[6]),
.A(n38));
AOI22_X1 U57 (.ZN(n38),
.B2(n22),
.B1(from_increment_pc[6]),
.A2(pcsrc),
.A1(branch_target[6]));
INV_X1 U58 (.ZN(to_mux_jump[7]),
.A(n37));
AOI22_X1 U59 (.ZN(n37),
.B2(n22),
.B1(from_increment_pc[7]),
.A2(pcsrc),
.A1(branch_target[7]));
INV_X1 U60 (.ZN(to_mux_jump[8]),
.A(n36));
AOI22_X1 U61 (.ZN(n36),
.B2(n22),
.B1(from_increment_pc[8]),
.A2(pcsrc),
.A1(branch_target[8]));
INV_X1 U62 (.ZN(to_mux_jump[10]),
.A(n65));
AOI22_X1 U63 (.ZN(n65),
.B2(n22),
.B1(from_increment_pc[10]),
.A2(pcsrc),
.A1(branch_target[10]));
INV_X1 U64 (.ZN(to_mux_jump[11]),
.A(n64));
AOI22_X1 U65 (.ZN(n64),
.B2(n22),
.B1(from_increment_pc[11]),
.A2(pcsrc),
.A1(branch_target[11]));
INV_X1 U66 (.ZN(to_mux_jump[12]),
.A(n63));
AOI22_X1 U67 (.ZN(n63),
.B2(n22),
.B1(from_increment_pc[12]),
.A2(pcsrc),
.A1(branch_target[12]));
INV_X1 U68 (.ZN(to_mux_jump[13]),
.A(n62));
AOI22_X1 U69 (.ZN(n62),
.B2(n22),
.B1(from_increment_pc[13]),
.A2(pcsrc),
.A1(branch_target[13]));
INV_X1 U70 (.ZN(to_mux_jump[0]),
.A(n66));
AOI22_X1 U71 (.ZN(n66),
.B2(n22),
.B1(from_increment_pc[0]),
.A2(pcsrc),
.A1(branch_target[0]));
INV_X1 U72 (.ZN(to_mux_jump[1]),
.A(n55));
AOI22_X1 U73 (.ZN(n55),
.B2(n22),
.B1(from_increment_pc[1]),
.A2(pcsrc),
.A1(branch_target[1]));
INV_X1 U74 (.ZN(to_mux_jump[2]),
.A(n44));
AOI22_X1 U75 (.ZN(n44),
.B2(n22),
.B1(from_increment_pc[2]),
.A2(pcsrc),
.A1(branch_target[2]));
endmodule
module writeback (
from_mem_data,
from_alu_data,
regfile_addr_in,
regwrite_in,
link,
memtoreg,
regwrite_out,
regfile_data,
regfile_addr_out);
input [31:0] from_mem_data;
input [31:0] from_alu_data;
input [4:0] regfile_addr_in;
input regwrite_in;
input link;
input memtoreg;
output regwrite_out;
output [31:0] regfile_data;
output [4:0] regfile_addr_out;
assign regwrite_out = regwrite_in ;
mux21_NBIT32_1 memtoreg_mux21 (.A(from_mem_data),
.B(from_alu_data),
.S(memtoreg),
.Y(regfile_data));
mux21_NBIT5_1 link_mux21 (.A({ 1'b1,
1'b1,
1'b1,
1'b1,
1'b1 }),
.B(regfile_addr_in),
.S(link),
.Y(regfile_addr_out));
endmodule
module MEM_WB_Reg (
clk,
rst,
controls_in,
from_mem_data_in,
from_alu_data_in,
regfile_addr_in,
controls_out,
from_mem_data_out,
from_alu_data_out,
regfile_addr_out);
input clk;
input rst;
input [2:0] controls_in;
input [31:0] from_mem_data_in;
input [31:0] from_alu_data_in;
input [4:0] regfile_addr_in;
output [2:0] controls_out;
output [31:0] from_mem_data_out;
output [31:0] from_alu_data_out;
output [4:0] regfile_addr_out;
// Internal wires
wire N3;
wire N4;
wire N5;
wire N70;
wire N71;
wire N72;
wire N73;
wire N74;
wire n74;
DFF_X1 \controls_out_reg[2] (.Q(controls_out[2]),
.D(N5),
.CK(clk));
INV_X1 U19 (.ZN(n74),
.A(rst));
AND2_X1 U30 (.ZN(N70),
.A2(n74),
.A1(regfile_addr_in[0]));
AND2_X1 U31 (.ZN(N71),
.A2(n74),
.A1(regfile_addr_in[1]));
AND2_X1 U32 (.ZN(N72),
.A2(n74),
.A1(regfile_addr_in[2]));
AND2_X1 U33 (.ZN(N74),
.A2(n74),
.A1(regfile_addr_in[4]));
AND2_X1 U34 (.ZN(N73),
.A2(n74),
.A1(regfile_addr_in[3]));
AND2_X1 U79 (.ZN(N3),
.A2(n74),
.A1(controls_in[0]));
AND2_X1 U80 (.ZN(N4),
.A2(n74),
.A1(controls_in[1]));
AND2_X1 U81 (.ZN(N5),
.A2(n74),
.A1(controls_in[2]));
endmodule
module memory (
controls_in,
PC1_in,
PC2_in,
takeBranch,
addrMem,
writeData,
RFaddr_in,
Data_out_fromRAM,
controls_out,
dataOut_mem,
dataOut_exe,
RFaddr_out,
unaligned,
PCsrc,
flush,
jump,
PC1_out,
PC2_out,
regwrite_MEM,
RFaddr_MEM,
forw_addr_MEM,
read_op,
write_op,
nibble,
write_byte,
Address_toRAM,
Data_in);
input [10:0] controls_in;
input [31:0] PC1_in;
input [31:0] PC2_in;
input takeBranch;
input [31:0] addrMem;
input [31:0] writeData;
input [4:0] RFaddr_in;
input [31:0] Data_out_fromRAM;
output [2:0] controls_out;
output [31:0] dataOut_mem;
output [31:0] dataOut_exe;
output [4:0] RFaddr_out;
output unaligned;
output PCsrc;
output flush;
output jump;
output [31:0] PC1_out;
output [31:0] PC2_out;
output regwrite_MEM;
output [4:0] RFaddr_MEM;
output [31:0] forw_addr_MEM;
output read_op;
output write_op;
output [1:0] nibble;
output write_byte;
output [31:0] Address_toRAM;
output [31:0] Data_in;
// Internal wires
wire controls_in_1;
wire controls_in_0;
wire \controls_in[10] ;
wire \controls_in[9] ;
wire \controls_in[2] ;
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
assign jump = controls_in_1 ;
assign controls_in_1 = controls_in[1] ;
assign controls_in_0 = controls_in[0] ;
assign controls_out[2] = \controls_in[10] ;
assign regwrite_MEM = \controls_in[10] ;
assign \controls_in[10] = controls_in[10] ;
assign controls_out[1] = \controls_in[9] ;
assign \controls_in[9] = controls_in[9] ;
assign controls_out[0] = \controls_in[2] ;
assign \controls_in[2] = controls_in[2] ;
assign PC1_out[31] = PC1_in[31] ;
assign PC1_out[30] = PC1_in[30] ;
assign PC1_out[29] = PC1_in[29] ;
assign PC1_out[28] = PC1_in[28] ;
assign PC1_out[27] = PC1_in[27] ;
assign PC1_out[26] = PC1_in[26] ;
assign PC1_out[25] = PC1_in[25] ;
assign PC1_out[24] = PC1_in[24] ;
assign PC1_out[23] = PC1_in[23] ;
assign PC1_out[22] = PC1_in[22] ;
assign PC1_out[21] = PC1_in[21] ;
assign PC1_out[20] = PC1_in[20] ;
assign PC1_out[19] = PC1_in[19] ;
assign PC1_out[18] = PC1_in[18] ;
assign PC1_out[17] = PC1_in[17] ;
assign PC1_out[16] = PC1_in[16] ;
assign PC1_out[15] = PC1_in[15] ;
assign PC1_out[14] = PC1_in[14] ;
assign PC1_out[13] = PC1_in[13] ;
assign PC1_out[12] = PC1_in[12] ;
assign PC1_out[11] = PC1_in[11] ;
assign PC1_out[10] = PC1_in[10] ;
assign PC1_out[9] = PC1_in[9] ;
assign PC1_out[8] = PC1_in[8] ;
assign PC1_out[7] = PC1_in[7] ;
assign PC1_out[6] = PC1_in[6] ;
assign PC1_out[5] = PC1_in[5] ;
assign PC1_out[4] = PC1_in[4] ;
assign PC1_out[3] = PC1_in[3] ;
assign PC1_out[2] = PC1_in[2] ;
assign PC1_out[1] = PC1_in[1] ;
assign PC1_out[0] = PC1_in[0] ;
assign PC2_out[31] = PC2_in[31] ;
assign PC2_out[30] = PC2_in[30] ;
assign PC2_out[29] = PC2_in[29] ;
assign PC2_out[28] = PC2_in[28] ;
assign PC2_out[27] = PC2_in[27] ;
assign PC2_out[26] = PC2_in[26] ;
assign PC2_out[25] = PC2_in[25] ;
assign PC2_out[24] = PC2_in[24] ;
assign PC2_out[23] = PC2_in[23] ;
assign PC2_out[22] = PC2_in[22] ;
assign PC2_out[21] = PC2_in[21] ;
assign PC2_out[20] = PC2_in[20] ;
assign PC2_out[19] = PC2_in[19] ;
assign PC2_out[18] = PC2_in[18] ;
assign PC2_out[17] = PC2_in[17] ;
assign PC2_out[16] = PC2_in[16] ;
assign PC2_out[15] = PC2_in[15] ;
assign PC2_out[14] = PC2_in[14] ;
assign PC2_out[13] = PC2_in[13] ;
assign PC2_out[12] = PC2_in[12] ;
assign PC2_out[11] = PC2_in[11] ;
assign PC2_out[10] = PC2_in[10] ;
assign PC2_out[9] = PC2_in[9] ;
assign PC2_out[8] = PC2_in[8] ;
assign PC2_out[7] = PC2_in[7] ;
assign PC2_out[6] = PC2_in[6] ;
assign PC2_out[5] = PC2_in[5] ;
assign PC2_out[4] = PC2_in[4] ;
assign PC2_out[3] = PC2_in[3] ;
assign PC2_out[2] = PC2_in[2] ;
assign PC2_out[1] = PC2_in[1] ;
assign PC2_out[0] = PC2_in[0] ;
assign RFaddr_out[4] = RFaddr_in[4] ;
assign RFaddr_MEM[4] = RFaddr_in[4] ;
assign RFaddr_out[3] = RFaddr_in[3] ;
assign RFaddr_MEM[3] = RFaddr_in[3] ;
assign RFaddr_out[2] = RFaddr_in[2] ;
assign RFaddr_MEM[2] = RFaddr_in[2] ;
assign RFaddr_out[1] = RFaddr_in[1] ;
assign RFaddr_MEM[1] = RFaddr_in[1] ;
assign RFaddr_out[0] = RFaddr_in[0] ;
assign RFaddr_MEM[0] = RFaddr_in[0] ;
assign dataOut_exe[31] = addrMem[31] ;
assign forw_addr_MEM[31] = addrMem[31] ;
assign dataOut_exe[30] = addrMem[30] ;
assign forw_addr_MEM[30] = addrMem[30] ;
assign dataOut_exe[29] = addrMem[29] ;
assign forw_addr_MEM[29] = addrMem[29] ;
assign dataOut_exe[28] = addrMem[28] ;
assign forw_addr_MEM[28] = addrMem[28] ;
assign dataOut_exe[27] = addrMem[27] ;
assign forw_addr_MEM[27] = addrMem[27] ;
assign dataOut_exe[26] = addrMem[26] ;
assign forw_addr_MEM[26] = addrMem[26] ;
assign dataOut_exe[25] = addrMem[25] ;
assign forw_addr_MEM[25] = addrMem[25] ;
assign dataOut_exe[24] = addrMem[24] ;
assign forw_addr_MEM[24] = addrMem[24] ;
assign dataOut_exe[23] = addrMem[23] ;
assign forw_addr_MEM[23] = addrMem[23] ;
assign dataOut_exe[22] = addrMem[22] ;
assign forw_addr_MEM[22] = addrMem[22] ;
assign dataOut_exe[21] = addrMem[21] ;
assign forw_addr_MEM[21] = addrMem[21] ;
assign dataOut_exe[20] = addrMem[20] ;
assign forw_addr_MEM[20] = addrMem[20] ;
assign dataOut_exe[19] = addrMem[19] ;
assign forw_addr_MEM[19] = addrMem[19] ;
assign dataOut_exe[18] = addrMem[18] ;
assign forw_addr_MEM[18] = addrMem[18] ;
assign dataOut_exe[17] = addrMem[17] ;
assign forw_addr_MEM[17] = addrMem[17] ;
assign dataOut_exe[16] = addrMem[16] ;
assign forw_addr_MEM[16] = addrMem[16] ;
assign dataOut_exe[15] = addrMem[15] ;
assign forw_addr_MEM[15] = addrMem[15] ;
assign dataOut_exe[14] = addrMem[14] ;
assign forw_addr_MEM[14] = addrMem[14] ;
assign dataOut_exe[13] = addrMem[13] ;
assign forw_addr_MEM[13] = addrMem[13] ;
assign dataOut_exe[12] = addrMem[12] ;
assign forw_addr_MEM[12] = addrMem[12] ;
assign dataOut_exe[11] = addrMem[11] ;
assign forw_addr_MEM[11] = addrMem[11] ;
assign dataOut_exe[10] = addrMem[10] ;
assign forw_addr_MEM[10] = addrMem[10] ;
assign dataOut_exe[9] = addrMem[9] ;
assign forw_addr_MEM[9] = addrMem[9] ;
assign dataOut_exe[8] = addrMem[8] ;
assign forw_addr_MEM[8] = addrMem[8] ;
assign dataOut_exe[7] = addrMem[7] ;
assign forw_addr_MEM[7] = addrMem[7] ;
assign dataOut_exe[6] = addrMem[6] ;
assign forw_addr_MEM[6] = addrMem[6] ;
assign dataOut_exe[5] = addrMem[5] ;
assign forw_addr_MEM[5] = addrMem[5] ;
assign dataOut_exe[4] = addrMem[4] ;
assign forw_addr_MEM[4] = addrMem[4] ;
assign dataOut_exe[3] = addrMem[3] ;
assign forw_addr_MEM[3] = addrMem[3] ;
assign dataOut_exe[2] = addrMem[2] ;
assign forw_addr_MEM[2] = addrMem[2] ;
assign dataOut_exe[1] = addrMem[1] ;
assign forw_addr_MEM[1] = addrMem[1] ;
assign dataOut_exe[0] = addrMem[0] ;
assign forw_addr_MEM[0] = addrMem[0] ;
assign Address_toRAM[31] = 1'b0 ;
assign Address_toRAM[30] = 1'b0 ;
dram_block dram (.address(addrMem),
.data_write(writeData),
.mem_op({ controls_in[8],
controls_in[7],
controls_in[6],
controls_in[5],
controls_in[4],
controls_in[3] }),
.Data_out(Data_out_fromRAM),
.unaligned(unaligned),
.data_read(dataOut_mem),
.read_op(read_op),
.write_op(write_op),
.nibble(nibble),
.write_byte(write_byte),
.Address_toRAM({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
Address_toRAM[29],
Address_toRAM[28],
Address_toRAM[27],
Address_toRAM[26],
Address_toRAM[25],
Address_toRAM[24],
Address_toRAM[23],
Address_toRAM[22],
Address_toRAM[21],
Address_toRAM[20],
Address_toRAM[19],
Address_toRAM[18],
Address_toRAM[17],
Address_toRAM[16],
Address_toRAM[15],
Address_toRAM[14],
Address_toRAM[13],
Address_toRAM[12],
Address_toRAM[11],
Address_toRAM[10],
Address_toRAM[9],
Address_toRAM[8],
Address_toRAM[7],
Address_toRAM[6],
Address_toRAM[5],
Address_toRAM[4],
Address_toRAM[3],
Address_toRAM[2],
Address_toRAM[1],
Address_toRAM[0] }),
.Data_in(Data_in));
OR2_X1 U1 (.ZN(flush),
.A2(controls_in_1),
.A1(PCsrc));
AND2_X2 U2 (.ZN(PCsrc),
.A2(controls_in_0),
.A1(takeBranch));
endmodule
module EX_MEM_Reg (
clk,
rst,
controls_in,
toPC1_in,
toPC2_in,
takeBranch_in,
mem_addr_in,
mem_writedata_in,
regfile_addr_in,
controls_out,
toPC1_out,
toPC2_out,
takeBranch_out,
mem_addr_out,
mem_writedata_out,
regfile_addr_out,
clk__L2_N1,
clk__L2_N10,
clk__L2_N11,
clk__L2_N12,
clk__L2_N2,
clk__L2_N3,
clk__L2_N4,
clk__L2_N5,
clk__L2_N6,
clk__L2_N7,
clk__L2_N9);
input clk;
input rst;
input [10:0] controls_in;
input [31:0] toPC1_in;
input [31:0] toPC2_in;
input takeBranch_in;
input [31:0] mem_addr_in;
input [31:0] mem_writedata_in;
input [4:0] regfile_addr_in;
output [10:0] controls_out;
output [31:0] toPC1_out;
output [31:0] toPC2_out;
output takeBranch_out;
output [31:0] mem_addr_out;
output [31:0] mem_writedata_out;
output [4:0] regfile_addr_out;
input clk__L2_N1;
input clk__L2_N10;
input clk__L2_N11;
input clk__L2_N12;
input clk__L2_N2;
input clk__L2_N3;
input clk__L2_N4;
input clk__L2_N5;
input clk__L2_N6;
input clk__L2_N7;
input clk__L2_N9;
// Internal wires
wire FE_OFN5_n147;
wire FE_OFN4_n147;
wire N3;
wire N4;
wire N5;
wire N6;
wire N7;
wire N8;
wire N9;
wire N10;
wire N11;
wire N12;
wire N13;
wire N14;
wire N15;
wire N16;
wire N17;
wire N18;
wire N19;
wire N20;
wire N21;
wire N22;
wire N23;
wire N24;
wire N25;
wire N26;
wire N27;
wire N28;
wire N29;
wire N30;
wire N31;
wire N32;
wire N33;
wire N34;
wire N35;
wire N36;
wire N37;
wire N38;
wire N39;
wire N40;
wire N41;
wire N42;
wire N43;
wire N44;
wire N45;
wire N46;
wire N47;
wire N48;
wire N49;
wire N50;
wire N51;
wire N52;
wire N53;
wire N54;
wire N55;
wire N56;
wire N57;
wire N58;
wire N59;
wire N60;
wire N61;
wire N62;
wire N63;
wire N64;
wire N65;
wire N66;
wire N67;
wire N68;
wire N69;
wire N70;
wire N71;
wire N72;
wire N73;
wire N74;
wire N75;
wire N76;
wire N77;
wire N78;
wire N79;
wire N80;
wire N81;
wire N82;
wire N83;
wire N84;
wire N85;
wire N86;
wire N87;
wire N88;
wire N89;
wire N90;
wire N91;
wire N92;
wire N93;
wire N94;
wire N95;
wire N96;
wire N97;
wire N98;
wire N99;
wire N100;
wire N101;
wire N102;
wire N103;
wire N104;
wire N105;
wire N106;
wire N107;
wire N108;
wire N109;
wire N110;
wire N111;
wire N112;
wire N113;
wire N114;
wire N115;
wire N116;
wire N117;
wire N118;
wire N119;
wire N120;
wire N121;
wire N122;
wire N123;
wire N124;
wire N125;
wire N126;
wire N127;
wire N128;
wire N129;
wire N130;
wire N131;
wire N132;
wire N133;
wire N134;
wire N135;
wire N136;
wire N137;
wire N138;
wire N139;
wire N140;
wire N141;
wire N142;
wire N143;
wire N144;
wire N145;
wire N146;
wire N147;
wire n147;
CLKBUF_X1 FE_OFC5_n147 (.Z(FE_OFN5_n147),
.A(FE_OFN4_n147));
CLKBUF_X2 FE_OFC4_n147 (.Z(FE_OFN4_n147),
.A(n147));
DFF_X1 \regfile_addr_out_reg[4] (.Q(regfile_addr_out[4]),
.D(N147),
.CK(clk__L2_N6));
DFF_X1 \regfile_addr_out_reg[3] (.Q(regfile_addr_out[3]),
.D(N146),
.CK(clk__L2_N6));
DFF_X1 \regfile_addr_out_reg[2] (.Q(regfile_addr_out[2]),
.D(N145),
.CK(clk__L2_N6));
DFF_X1 \regfile_addr_out_reg[1] (.Q(regfile_addr_out[1]),
.D(N144),
.CK(clk__L2_N6));
DFF_X1 \regfile_addr_out_reg[0] (.Q(regfile_addr_out[0]),
.D(N143),
.CK(clk__L2_N6));
DFF_X1 \controls_out_reg[10] (.Q(controls_out[10]),
.D(N13),
.CK(clk__L2_N6));
DFF_X1 \controls_out_reg[9] (.Q(controls_out[9]),
.D(N12),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[8] (.Q(controls_out[8]),
.D(N11),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[7] (.Q(controls_out[7]),
.D(N10),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[6] (.Q(controls_out[6]),
.D(N9),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[5] (.Q(controls_out[5]),
.D(N8),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[4] (.Q(controls_out[4]),
.D(N7),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[3] (.Q(controls_out[3]),
.D(N6),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[2] (.Q(controls_out[2]),
.D(N5),
.CK(clk__L2_N9));
DFF_X1 \controls_out_reg[1] (.Q(controls_out[1]),
.D(N4),
.CK(clk__L2_N7));
DFF_X1 \controls_out_reg[0] (.Q(controls_out[0]),
.D(N3),
.CK(clk__L2_N7));
DFF_X1 \toPC1_out_reg[31] (.Q(toPC1_out[31]),
.D(N45),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[30] (.Q(toPC1_out[30]),
.D(N44),
.CK(clk__L2_N5));
DFF_X1 \toPC1_out_reg[29] (.Q(toPC1_out[29]),
.D(N43),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[28] (.Q(toPC1_out[28]),
.D(N42),
.CK(clk__L2_N5));
DFF_X1 \toPC1_out_reg[27] (.Q(toPC1_out[27]),
.D(N41),
.CK(clk__L2_N3));
DFF_X1 \toPC1_out_reg[26] (.Q(toPC1_out[26]),
.D(N40),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[25] (.Q(toPC1_out[25]),
.D(N39),
.CK(clk));
DFF_X1 \toPC1_out_reg[24] (.Q(toPC1_out[24]),
.D(N38),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[23] (.Q(toPC1_out[23]),
.D(N37),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[22] (.Q(toPC1_out[22]),
.D(N36),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[21] (.Q(toPC1_out[21]),
.D(N35),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[20] (.Q(toPC1_out[20]),
.D(N34),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[19] (.Q(toPC1_out[19]),
.D(N33),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[18] (.Q(toPC1_out[18]),
.D(N32),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[17] (.Q(toPC1_out[17]),
.D(N31),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[16] (.Q(toPC1_out[16]),
.D(N30),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[15] (.Q(toPC1_out[15]),
.D(N29),
.CK(clk__L2_N1));
DFF_X1 \toPC1_out_reg[14] (.Q(toPC1_out[14]),
.D(N28),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[13] (.Q(toPC1_out[13]),
.D(N27),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[12] (.Q(toPC1_out[12]),
.D(N26),
.CK(clk__L2_N3));
DFF_X1 \toPC1_out_reg[11] (.Q(toPC1_out[11]),
.D(N25),
.CK(clk__L2_N1));
DFF_X1 \toPC1_out_reg[10] (.Q(toPC1_out[10]),
.D(N24),
.CK(clk__L2_N3));
DFF_X1 \toPC1_out_reg[9] (.Q(toPC1_out[9]),
.D(N23),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[8] (.Q(toPC1_out[8]),
.D(N22),
.CK(clk__L2_N5));
DFF_X1 \toPC1_out_reg[7] (.Q(toPC1_out[7]),
.D(N21),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[6] (.Q(toPC1_out[6]),
.D(N20),
.CK(clk__L2_N3));
DFF_X1 \toPC1_out_reg[5] (.Q(toPC1_out[5]),
.D(N19),
.CK(clk__L2_N4));
DFF_X1 \toPC1_out_reg[4] (.Q(toPC1_out[4]),
.D(N18),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[3] (.Q(toPC1_out[3]),
.D(N17),
.CK(clk__L2_N2));
DFF_X1 \toPC1_out_reg[2] (.Q(toPC1_out[2]),
.D(N16),
.CK(clk__L2_N1));
DFF_X1 \toPC1_out_reg[1] (.Q(toPC1_out[1]),
.D(N15),
.CK(clk__L2_N1));
DFF_X1 \toPC1_out_reg[0] (.Q(toPC1_out[0]),
.D(N14),
.CK(clk));
DFF_X1 \toPC2_out_reg[31] (.Q(toPC2_out[31]),
.D(N77),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[30] (.Q(toPC2_out[30]),
.D(N76),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[29] (.Q(toPC2_out[29]),
.D(N75),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[28] (.Q(toPC2_out[28]),
.D(N74),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[27] (.Q(toPC2_out[27]),
.D(N73),
.CK(clk__L2_N3));
DFF_X1 \toPC2_out_reg[26] (.Q(toPC2_out[26]),
.D(N72),
.CK(clk__L2_N3));
DFF_X1 \toPC2_out_reg[25] (.Q(toPC2_out[25]),
.D(N71),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[24] (.Q(toPC2_out[24]),
.D(N70),
.CK(clk));
DFF_X1 \toPC2_out_reg[23] (.Q(toPC2_out[23]),
.D(N69),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[22] (.Q(toPC2_out[22]),
.D(N68),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[21] (.Q(toPC2_out[21]),
.D(N67),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[20] (.Q(toPC2_out[20]),
.D(N66),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[19] (.Q(toPC2_out[19]),
.D(N65),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[18] (.Q(toPC2_out[18]),
.D(N64),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[17] (.Q(toPC2_out[17]),
.D(N63),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[16] (.Q(toPC2_out[16]),
.D(N62),
.CK(clk__L2_N3));
DFF_X1 \toPC2_out_reg[15] (.Q(toPC2_out[15]),
.D(N61),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[14] (.Q(toPC2_out[14]),
.D(N60),
.CK(clk__L2_N3));
DFF_X1 \toPC2_out_reg[13] (.Q(toPC2_out[13]),
.D(N59),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[12] (.Q(toPC2_out[12]),
.D(N58),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[11] (.Q(toPC2_out[11]),
.D(N57),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[10] (.Q(toPC2_out[10]),
.D(N56),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[9] (.Q(toPC2_out[9]),
.D(N55),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[8] (.Q(toPC2_out[8]),
.D(N54),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[7] (.Q(toPC2_out[7]),
.D(N53),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[6] (.Q(toPC2_out[6]),
.D(N52),
.CK(clk__L2_N5));
DFF_X1 \toPC2_out_reg[5] (.Q(toPC2_out[5]),
.D(N51),
.CK(clk__L2_N4));
DFF_X1 \toPC2_out_reg[4] (.Q(toPC2_out[4]),
.D(N50),
.CK(clk__L2_N2));
DFF_X1 \toPC2_out_reg[3] (.Q(toPC2_out[3]),
.D(N49),
.CK(clk));
DFF_X1 \toPC2_out_reg[2] (.Q(toPC2_out[2]),
.D(N48),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[1] (.Q(toPC2_out[1]),
.D(N47),
.CK(clk__L2_N1));
DFF_X1 \toPC2_out_reg[0] (.Q(toPC2_out[0]),
.D(N46),
.CK(clk));
DFF_X1 takeBranch_out_reg (.Q(takeBranch_out),
.D(N78),
.CK(clk__L2_N7));
DFF_X1 \mem_addr_out_reg[31] (.Q(mem_addr_out[31]),
.D(N110),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[30] (.Q(mem_addr_out[30]),
.D(N109),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[29] (.Q(mem_addr_out[29]),
.D(N108),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[28] (.Q(mem_addr_out[28]),
.D(N107),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[27] (.Q(mem_addr_out[27]),
.D(N106),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[26] (.Q(mem_addr_out[26]),
.D(N105),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[25] (.Q(mem_addr_out[25]),
.D(N104),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[24] (.Q(mem_addr_out[24]),
.D(N103),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[23] (.Q(mem_addr_out[23]),
.D(N102),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[22] (.Q(mem_addr_out[22]),
.D(N101),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[21] (.Q(mem_addr_out[21]),
.D(N100),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[20] (.Q(mem_addr_out[20]),
.D(N99),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[19] (.Q(mem_addr_out[19]),
.D(N98),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[18] (.Q(mem_addr_out[18]),
.D(N97),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[17] (.Q(mem_addr_out[17]),
.D(N96),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[16] (.Q(mem_addr_out[16]),
.D(N95),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[15] (.Q(mem_addr_out[15]),
.D(N94),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[14] (.Q(mem_addr_out[14]),
.D(N93),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[13] (.Q(mem_addr_out[13]),
.D(N92),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[12] (.Q(mem_addr_out[12]),
.D(N91),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[11] (.Q(mem_addr_out[11]),
.D(N90),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[10] (.Q(mem_addr_out[10]),
.D(N89),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[9] (.Q(mem_addr_out[9]),
.D(N88),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[8] (.Q(mem_addr_out[8]),
.D(N87),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[7] (.Q(mem_addr_out[7]),
.D(N86),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[6] (.Q(mem_addr_out[6]),
.D(N85),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[5] (.Q(mem_addr_out[5]),
.D(N84),
.CK(clk__L2_N12));
DFF_X1 \mem_addr_out_reg[4] (.Q(mem_addr_out[4]),
.D(N83),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[3] (.Q(mem_addr_out[3]),
.D(N82),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[2] (.Q(mem_addr_out[2]),
.D(N81),
.CK(clk__L2_N11));
DFF_X1 \mem_addr_out_reg[1] (.Q(mem_addr_out[1]),
.D(N80),
.CK(clk__L2_N10));
DFF_X1 \mem_addr_out_reg[0] (.Q(mem_addr_out[0]),
.D(N79),
.CK(clk__L2_N9));
DFF_X1 \mem_writedata_out_reg[31] (.Q(mem_writedata_out[31]),
.D(N142),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[30] (.Q(mem_writedata_out[30]),
.D(N141),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[29] (.Q(mem_writedata_out[29]),
.D(N140),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[28] (.Q(mem_writedata_out[28]),
.D(N139),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[27] (.Q(mem_writedata_out[27]),
.D(N138),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[26] (.Q(mem_writedata_out[26]),
.D(N137),
.CK(clk__L2_N10));
DFF_X1 \mem_writedata_out_reg[25] (.Q(mem_writedata_out[25]),
.D(N136),
.CK(clk__L2_N10));
DFF_X1 \mem_writedata_out_reg[24] (.Q(mem_writedata_out[24]),
.D(N135),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[23] (.Q(mem_writedata_out[23]),
.D(N134),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[22] (.Q(mem_writedata_out[22]),
.D(N133),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[21] (.Q(mem_writedata_out[21]),
.D(N132),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[20] (.Q(mem_writedata_out[20]),
.D(N131),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[19] (.Q(mem_writedata_out[19]),
.D(N130),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[18] (.Q(mem_writedata_out[18]),
.D(N129),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[17] (.Q(mem_writedata_out[17]),
.D(N128),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[16] (.Q(mem_writedata_out[16]),
.D(N127),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[15] (.Q(mem_writedata_out[15]),
.D(N126),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[14] (.Q(mem_writedata_out[14]),
.D(N125),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[13] (.Q(mem_writedata_out[13]),
.D(N124),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[12] (.Q(mem_writedata_out[12]),
.D(N123),
.CK(clk__L2_N10));
DFF_X1 \mem_writedata_out_reg[11] (.Q(mem_writedata_out[11]),
.D(N122),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[10] (.Q(mem_writedata_out[10]),
.D(N121),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[9] (.Q(mem_writedata_out[9]),
.D(N120),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[8] (.Q(mem_writedata_out[8]),
.D(N119),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[7] (.Q(mem_writedata_out[7]),
.D(N118),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[6] (.Q(mem_writedata_out[6]),
.D(N117),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[5] (.Q(mem_writedata_out[5]),
.D(N116),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[4] (.Q(mem_writedata_out[4]),
.D(N115),
.CK(clk__L2_N10));
DFF_X1 \mem_writedata_out_reg[3] (.Q(mem_writedata_out[3]),
.D(N114),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[2] (.Q(mem_writedata_out[2]),
.D(N113),
.CK(clk__L2_N11));
DFF_X1 \mem_writedata_out_reg[1] (.Q(mem_writedata_out[1]),
.D(N112),
.CK(clk__L2_N12));
DFF_X1 \mem_writedata_out_reg[0] (.Q(mem_writedata_out[0]),
.D(N111),
.CK(clk__L2_N12));
AND2_X1 U18 (.ZN(N78),
.A2(n147),
.A1(takeBranch_in));
INV_X2 U19 (.ZN(n147),
.A(rst));
AND2_X1 U20 (.ZN(N111),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[0]));
AND2_X1 U21 (.ZN(N112),
.A2(n147),
.A1(mem_writedata_in[1]));
AND2_X1 U22 (.ZN(N113),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[2]));
AND2_X1 U23 (.ZN(N114),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[3]));
AND2_X1 U24 (.ZN(N115),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[4]));
AND2_X1 U25 (.ZN(N116),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[5]));
AND2_X1 U26 (.ZN(N117),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[6]));
AND2_X1 U27 (.ZN(N118),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[7]));
AND2_X1 U28 (.ZN(N119),
.A2(n147),
.A1(mem_writedata_in[8]));
AND2_X1 U29 (.ZN(N120),
.A2(n147),
.A1(mem_writedata_in[9]));
AND2_X1 U30 (.ZN(N121),
.A2(n147),
.A1(mem_writedata_in[10]));
AND2_X1 U31 (.ZN(N122),
.A2(n147),
.A1(mem_writedata_in[11]));
AND2_X1 U32 (.ZN(N123),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[12]));
AND2_X1 U33 (.ZN(N124),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[13]));
AND2_X1 U34 (.ZN(N125),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[14]));
AND2_X1 U35 (.ZN(N126),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[15]));
AND2_X1 U36 (.ZN(N127),
.A2(n147),
.A1(mem_writedata_in[16]));
AND2_X1 U37 (.ZN(N128),
.A2(n147),
.A1(mem_writedata_in[17]));
AND2_X1 U38 (.ZN(N129),
.A2(n147),
.A1(mem_writedata_in[18]));
AND2_X1 U39 (.ZN(N130),
.A2(FE_OFN4_n147),
.A1(mem_writedata_in[19]));
AND2_X1 U40 (.ZN(N131),
.A2(n147),
.A1(mem_writedata_in[20]));
AND2_X1 U41 (.ZN(N132),
.A2(n147),
.A1(mem_writedata_in[21]));
AND2_X1 U42 (.ZN(N133),
.A2(n147),
.A1(mem_writedata_in[22]));
AND2_X1 U43 (.ZN(N134),
.A2(n147),
.A1(mem_writedata_in[23]));
AND2_X1 U44 (.ZN(N135),
.A2(n147),
.A1(mem_writedata_in[24]));
AND2_X1 U45 (.ZN(N136),
.A2(n147),
.A1(mem_writedata_in[25]));
AND2_X1 U46 (.ZN(N137),
.A2(n147),
.A1(mem_writedata_in[26]));
AND2_X1 U47 (.ZN(N138),
.A2(n147),
.A1(mem_writedata_in[27]));
AND2_X1 U48 (.ZN(N139),
.A2(n147),
.A1(mem_writedata_in[28]));
AND2_X1 U49 (.ZN(N140),
.A2(n147),
.A1(mem_writedata_in[29]));
AND2_X1 U50 (.ZN(N141),
.A2(n147),
.A1(mem_writedata_in[30]));
AND2_X1 U51 (.ZN(N142),
.A2(n147),
.A1(mem_writedata_in[31]));
AND2_X1 U52 (.ZN(N79),
.A2(n147),
.A1(mem_addr_in[0]));
AND2_X1 U53 (.ZN(N80),
.A2(n147),
.A1(mem_addr_in[1]));
AND2_X1 U54 (.ZN(N81),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[2]));
AND2_X1 U55 (.ZN(N82),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[3]));
AND2_X1 U56 (.ZN(N83),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[4]));
AND2_X1 U57 (.ZN(N84),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[5]));
AND2_X1 U58 (.ZN(N85),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[6]));
AND2_X1 U59 (.ZN(N86),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[7]));
AND2_X1 U60 (.ZN(N87),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[8]));
AND2_X1 U61 (.ZN(N100),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[21]));
AND2_X1 U62 (.ZN(N101),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[22]));
AND2_X1 U63 (.ZN(N102),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[23]));
AND2_X1 U64 (.ZN(N103),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[24]));
AND2_X1 U65 (.ZN(N104),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[25]));
AND2_X1 U66 (.ZN(N105),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[26]));
AND2_X1 U67 (.ZN(N106),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[27]));
AND2_X1 U68 (.ZN(N107),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[28]));
AND2_X1 U69 (.ZN(N108),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[29]));
AND2_X1 U70 (.ZN(N109),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[30]));
AND2_X1 U71 (.ZN(N110),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[31]));
AND2_X1 U72 (.ZN(N46),
.A2(n147),
.A1(toPC2_in[0]));
AND2_X1 U73 (.ZN(N47),
.A2(FE_OFN4_n147),
.A1(toPC2_in[1]));
AND2_X1 U74 (.ZN(N48),
.A2(FE_OFN5_n147),
.A1(toPC2_in[2]));
AND2_X1 U75 (.ZN(N49),
.A2(FE_OFN5_n147),
.A1(toPC2_in[3]));
AND2_X1 U76 (.ZN(N50),
.A2(FE_OFN4_n147),
.A1(toPC2_in[4]));
AND2_X1 U77 (.ZN(N51),
.A2(FE_OFN4_n147),
.A1(toPC2_in[5]));
AND2_X1 U78 (.ZN(N52),
.A2(FE_OFN4_n147),
.A1(toPC2_in[6]));
AND2_X1 U79 (.ZN(N53),
.A2(FE_OFN4_n147),
.A1(toPC2_in[7]));
AND2_X1 U80 (.ZN(N54),
.A2(n147),
.A1(toPC2_in[8]));
AND2_X1 U81 (.ZN(N55),
.A2(n147),
.A1(toPC2_in[9]));
AND2_X1 U82 (.ZN(N56),
.A2(n147),
.A1(toPC2_in[10]));
AND2_X1 U83 (.ZN(N57),
.A2(n147),
.A1(toPC2_in[11]));
AND2_X1 U84 (.ZN(N58),
.A2(n147),
.A1(toPC2_in[12]));
AND2_X1 U85 (.ZN(N59),
.A2(n147),
.A1(toPC2_in[13]));
AND2_X1 U86 (.ZN(N60),
.A2(n147),
.A1(toPC2_in[14]));
AND2_X1 U87 (.ZN(N61),
.A2(n147),
.A1(toPC2_in[15]));
AND2_X1 U88 (.ZN(N62),
.A2(n147),
.A1(toPC2_in[16]));
AND2_X1 U89 (.ZN(N63),
.A2(n147),
.A1(toPC2_in[17]));
AND2_X1 U90 (.ZN(N64),
.A2(n147),
.A1(toPC2_in[18]));
AND2_X1 U91 (.ZN(N65),
.A2(n147),
.A1(toPC2_in[19]));
AND2_X1 U92 (.ZN(N66),
.A2(FE_OFN4_n147),
.A1(toPC2_in[20]));
AND2_X1 U93 (.ZN(N67),
.A2(FE_OFN4_n147),
.A1(toPC2_in[21]));
AND2_X1 U94 (.ZN(N68),
.A2(FE_OFN4_n147),
.A1(toPC2_in[22]));
AND2_X1 U95 (.ZN(N69),
.A2(FE_OFN5_n147),
.A1(toPC2_in[23]));
AND2_X1 U96 (.ZN(N70),
.A2(FE_OFN5_n147),
.A1(toPC2_in[24]));
AND2_X1 U97 (.ZN(N71),
.A2(FE_OFN5_n147),
.A1(toPC2_in[25]));
AND2_X1 U98 (.ZN(N72),
.A2(FE_OFN5_n147),
.A1(toPC2_in[26]));
AND2_X1 U99 (.ZN(N73),
.A2(FE_OFN5_n147),
.A1(toPC2_in[27]));
AND2_X1 U100 (.ZN(N74),
.A2(FE_OFN5_n147),
.A1(toPC2_in[28]));
AND2_X1 U101 (.ZN(N75),
.A2(FE_OFN5_n147),
.A1(toPC2_in[29]));
AND2_X1 U102 (.ZN(N76),
.A2(FE_OFN4_n147),
.A1(toPC2_in[30]));
AND2_X1 U103 (.ZN(N77),
.A2(FE_OFN5_n147),
.A1(toPC2_in[31]));
AND2_X1 U104 (.ZN(N14),
.A2(n147),
.A1(toPC1_in[0]));
AND2_X1 U105 (.ZN(N15),
.A2(FE_OFN4_n147),
.A1(toPC1_in[1]));
AND2_X1 U106 (.ZN(N16),
.A2(FE_OFN5_n147),
.A1(toPC1_in[2]));
AND2_X1 U107 (.ZN(N17),
.A2(FE_OFN5_n147),
.A1(toPC1_in[3]));
AND2_X1 U108 (.ZN(N18),
.A2(FE_OFN4_n147),
.A1(toPC1_in[4]));
AND2_X1 U109 (.ZN(N19),
.A2(FE_OFN5_n147),
.A1(toPC1_in[5]));
AND2_X1 U110 (.ZN(N20),
.A2(FE_OFN4_n147),
.A1(toPC1_in[6]));
AND2_X1 U111 (.ZN(N21),
.A2(FE_OFN4_n147),
.A1(toPC1_in[7]));
AND2_X1 U112 (.ZN(N22),
.A2(n147),
.A1(toPC1_in[8]));
AND2_X1 U113 (.ZN(N23),
.A2(n147),
.A1(toPC1_in[9]));
AND2_X1 U114 (.ZN(N24),
.A2(n147),
.A1(toPC1_in[10]));
AND2_X1 U115 (.ZN(N25),
.A2(n147),
.A1(toPC1_in[11]));
AND2_X1 U116 (.ZN(N26),
.A2(n147),
.A1(toPC1_in[12]));
AND2_X1 U117 (.ZN(N27),
.A2(n147),
.A1(toPC1_in[13]));
AND2_X1 U118 (.ZN(N28),
.A2(n147),
.A1(toPC1_in[14]));
AND2_X1 U119 (.ZN(N29),
.A2(n147),
.A1(toPC1_in[15]));
AND2_X1 U120 (.ZN(N30),
.A2(n147),
.A1(toPC1_in[16]));
AND2_X1 U121 (.ZN(N31),
.A2(n147),
.A1(toPC1_in[17]));
AND2_X1 U122 (.ZN(N32),
.A2(FE_OFN4_n147),
.A1(toPC1_in[18]));
AND2_X1 U123 (.ZN(N33),
.A2(FE_OFN4_n147),
.A1(toPC1_in[19]));
AND2_X1 U124 (.ZN(N34),
.A2(FE_OFN4_n147),
.A1(toPC1_in[20]));
AND2_X1 U125 (.ZN(N35),
.A2(FE_OFN4_n147),
.A1(toPC1_in[21]));
AND2_X1 U126 (.ZN(N36),
.A2(FE_OFN4_n147),
.A1(toPC1_in[22]));
AND2_X1 U127 (.ZN(N37),
.A2(FE_OFN5_n147),
.A1(toPC1_in[23]));
AND2_X1 U128 (.ZN(N38),
.A2(FE_OFN5_n147),
.A1(toPC1_in[24]));
AND2_X1 U129 (.ZN(N39),
.A2(FE_OFN5_n147),
.A1(toPC1_in[25]));
AND2_X1 U130 (.ZN(N40),
.A2(FE_OFN5_n147),
.A1(toPC1_in[26]));
AND2_X1 U131 (.ZN(N41),
.A2(FE_OFN5_n147),
.A1(toPC1_in[27]));
AND2_X1 U132 (.ZN(N42),
.A2(FE_OFN5_n147),
.A1(toPC1_in[28]));
AND2_X1 U133 (.ZN(N43),
.A2(FE_OFN5_n147),
.A1(toPC1_in[29]));
AND2_X1 U134 (.ZN(N44),
.A2(FE_OFN4_n147),
.A1(toPC1_in[30]));
AND2_X1 U135 (.ZN(N45),
.A2(FE_OFN4_n147),
.A1(toPC1_in[31]));
AND2_X1 U136 (.ZN(N3),
.A2(n147),
.A1(controls_in[0]));
AND2_X1 U137 (.ZN(N4),
.A2(n147),
.A1(controls_in[1]));
AND2_X1 U138 (.ZN(N5),
.A2(n147),
.A1(controls_in[2]));
AND2_X1 U139 (.ZN(N6),
.A2(n147),
.A1(controls_in[3]));
AND2_X1 U140 (.ZN(N7),
.A2(n147),
.A1(controls_in[4]));
AND2_X1 U141 (.ZN(N8),
.A2(n147),
.A1(controls_in[5]));
AND2_X1 U142 (.ZN(N10),
.A2(n147),
.A1(controls_in[7]));
AND2_X1 U143 (.ZN(N11),
.A2(n147),
.A1(controls_in[8]));
AND2_X1 U144 (.ZN(N12),
.A2(n147),
.A1(controls_in[9]));
AND2_X1 U145 (.ZN(N13),
.A2(n147),
.A1(controls_in[10]));
AND2_X1 U146 (.ZN(N143),
.A2(n147),
.A1(regfile_addr_in[0]));
AND2_X1 U147 (.ZN(N144),
.A2(n147),
.A1(regfile_addr_in[1]));
AND2_X1 U148 (.ZN(N145),
.A2(n147),
.A1(regfile_addr_in[2]));
AND2_X1 U149 (.ZN(N146),
.A2(n147),
.A1(regfile_addr_in[3]));
AND2_X1 U150 (.ZN(N147),
.A2(n147),
.A1(regfile_addr_in[4]));
AND2_X1 U151 (.ZN(N88),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[9]));
AND2_X1 U152 (.ZN(N89),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[10]));
AND2_X1 U153 (.ZN(N90),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[11]));
AND2_X1 U154 (.ZN(N91),
.A2(n147),
.A1(mem_addr_in[12]));
AND2_X1 U155 (.ZN(N92),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[13]));
AND2_X1 U156 (.ZN(N93),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[14]));
AND2_X1 U157 (.ZN(N94),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[15]));
AND2_X1 U158 (.ZN(N95),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[16]));
AND2_X1 U159 (.ZN(N96),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[17]));
AND2_X1 U160 (.ZN(N97),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[18]));
AND2_X1 U161 (.ZN(N98),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[19]));
AND2_X1 U162 (.ZN(N9),
.A2(n147),
.A1(controls_in[6]));
AND2_X1 U163 (.ZN(N99),
.A2(FE_OFN4_n147),
.A1(mem_addr_in[20]));
endmodule
module execute (
clk,
rst,
controls_in,
ext25_0,
nextPC,
op_A,
op_B,
ext15_0,
inst15_0,
rt_inst,
rd_inst,
rs_inst,
unaligned,
forw_dataWB,
forw_dataMEM,
RFaddr_WB,
RFaddr_MEM,
regwriteWB,
regwriteMEM,
controls_out,
toPC1,
toPC2,
branchTaken,
addrMem,
writeData,
addrRF,
IDEX_rt,
IDEX_memread);
input clk;
input rst;
input [21:0] controls_in;
input [31:0] ext25_0;
input [31:0] nextPC;
input [31:0] op_A;
input [31:0] op_B;
input [31:0] ext15_0;
input [15:0] inst15_0;
input [4:0] rt_inst;
input [4:0] rd_inst;
input [4:0] rs_inst;
input unaligned;
input [31:0] forw_dataWB;
input [31:0] forw_dataMEM;
input [4:0] RFaddr_WB;
input [4:0] RFaddr_MEM;
input regwriteWB;
input regwriteMEM;
output [10:0] controls_out;
output [31:0] toPC1;
output [31:0] toPC2;
output branchTaken;
output [31:0] addrMem;
output [31:0] writeData;
output [4:0] addrRF;
output [4:0] IDEX_rt;
output [3:0] IDEX_memread;
// Internal wires
wire FE_UNCONNECTED_0;
wire controls_in_20;
wire controls_in_19;
wire controls_in_17;
wire controls_in_16;
wire controls_in_15;
wire controls_in_14;
wire \controls_in[21] ;
wire \controls_in[18] ;
wire \controls_in[13] ;
wire \controls_in[12] ;
wire \controls_in[11] ;
wire \controls_in[10] ;
wire \controls_in[9] ;
wire \controls_in[8] ;
wire \controls_in[7] ;
wire \controls_in[6] ;
wire \controls_in[5] ;
wire zero_i;
wire \resAdd1_i[9] ;
wire \resAdd1_i[8] ;
wire \resAdd1_i[7] ;
wire \resAdd1_i[6] ;
wire \resAdd1_i[5] ;
wire \resAdd1_i[4] ;
wire \resAdd1_i[3] ;
wire \resAdd1_i[31] ;
wire \resAdd1_i[30] ;
wire \resAdd1_i[2] ;
wire \resAdd1_i[29] ;
wire \resAdd1_i[28] ;
wire \resAdd1_i[27] ;
wire \resAdd1_i[26] ;
wire \resAdd1_i[25] ;
wire \resAdd1_i[24] ;
wire \resAdd1_i[23] ;
wire \resAdd1_i[22] ;
wire \resAdd1_i[21] ;
wire \resAdd1_i[20] ;
wire \resAdd1_i[1] ;
wire \resAdd1_i[19] ;
wire \resAdd1_i[18] ;
wire \resAdd1_i[17] ;
wire \resAdd1_i[16] ;
wire \resAdd1_i[15] ;
wire \resAdd1_i[14] ;
wire \resAdd1_i[13] ;
wire \resAdd1_i[12] ;
wire \resAdd1_i[11] ;
wire \resAdd1_i[10] ;
wire \resAdd1_i[0] ;
wire \link_value_i[9] ;
wire \link_value_i[8] ;
wire \link_value_i[7] ;
wire \link_value_i[6] ;
wire \link_value_i[5] ;
wire \link_value_i[4] ;
wire \link_value_i[3] ;
wire \link_value_i[31] ;
wire \link_value_i[30] ;
wire \link_value_i[2] ;
wire \link_value_i[29] ;
wire \link_value_i[28] ;
wire \link_value_i[27] ;
wire \link_value_i[26] ;
wire \link_value_i[25] ;
wire \link_value_i[24] ;
wire \link_value_i[23] ;
wire \link_value_i[22] ;
wire \link_value_i[21] ;
wire \link_value_i[20] ;
wire \link_value_i[1] ;
wire \link_value_i[19] ;
wire \link_value_i[18] ;
wire \link_value_i[17] ;
wire \link_value_i[16] ;
wire \link_value_i[15] ;
wire \link_value_i[14] ;
wire \link_value_i[13] ;
wire \link_value_i[12] ;
wire \link_value_i[11] ;
wire \link_value_i[10] ;
wire \link_value_i[0] ;
wire \link2lhi_wire_i[9] ;
wire \link2lhi_wire_i[8] ;
wire \link2lhi_wire_i[7] ;
wire \link2lhi_wire_i[6] ;
wire \link2lhi_wire_i[5] ;
wire \link2lhi_wire_i[4] ;
wire \link2lhi_wire_i[3] ;
wire \link2lhi_wire_i[31] ;
wire \link2lhi_wire_i[30] ;
wire \link2lhi_wire_i[2] ;
wire \link2lhi_wire_i[29] ;
wire \link2lhi_wire_i[28] ;
wire \link2lhi_wire_i[27] ;
wire \link2lhi_wire_i[26] ;
wire \link2lhi_wire_i[25] ;
wire \link2lhi_wire_i[24] ;
wire \link2lhi_wire_i[23] ;
wire \link2lhi_wire_i[22] ;
wire \link2lhi_wire_i[21] ;
wire \link2lhi_wire_i[20] ;
wire \link2lhi_wire_i[1] ;
wire \link2lhi_wire_i[19] ;
wire \link2lhi_wire_i[18] ;
wire \link2lhi_wire_i[17] ;
wire \link2lhi_wire_i[16] ;
wire \link2lhi_wire_i[15] ;
wire \link2lhi_wire_i[14] ;
wire \link2lhi_wire_i[13] ;
wire \link2lhi_wire_i[12] ;
wire \link2lhi_wire_i[11] ;
wire \link2lhi_wire_i[10] ;
wire \link2lhi_wire_i[0] ;
wire \lhi2mov_wire_i[9] ;
wire \lhi2mov_wire_i[8] ;
wire \lhi2mov_wire_i[7] ;
wire \lhi2mov_wire_i[6] ;
wire \lhi2mov_wire_i[5] ;
wire \lhi2mov_wire_i[4] ;
wire \lhi2mov_wire_i[3] ;
wire \lhi2mov_wire_i[31] ;
wire \lhi2mov_wire_i[30] ;
wire \lhi2mov_wire_i[2] ;
wire \lhi2mov_wire_i[29] ;
wire \lhi2mov_wire_i[28] ;
wire \lhi2mov_wire_i[27] ;
wire \lhi2mov_wire_i[26] ;
wire \lhi2mov_wire_i[25] ;
wire \lhi2mov_wire_i[24] ;
wire \lhi2mov_wire_i[23] ;
wire \lhi2mov_wire_i[22] ;
wire \lhi2mov_wire_i[21] ;
wire \lhi2mov_wire_i[20] ;
wire \lhi2mov_wire_i[1] ;
wire \lhi2mov_wire_i[19] ;
wire \lhi2mov_wire_i[18] ;
wire \lhi2mov_wire_i[17] ;
wire \lhi2mov_wire_i[16] ;
wire \lhi2mov_wire_i[15] ;
wire \lhi2mov_wire_i[14] ;
wire \lhi2mov_wire_i[13] ;
wire \lhi2mov_wire_i[12] ;
wire \lhi2mov_wire_i[11] ;
wire \lhi2mov_wire_i[10] ;
wire \lhi2mov_wire_i[0] ;
wire [31:0] A_inALU_i;
wire [31:0] res_outALU_i;
wire [31:0] lhi_value_i;
wire [31:0] psw_status_i;
wire [31:0] B_inALU_i;
wire [1:0] forwardA_i;
wire [1:0] forwardB_i;
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
wire SYNOPSYS_UNCONNECTED__2;
wire SYNOPSYS_UNCONNECTED__3;
wire SYNOPSYS_UNCONNECTED__4;
wire SYNOPSYS_UNCONNECTED__5;
wire SYNOPSYS_UNCONNECTED__6;
wire SYNOPSYS_UNCONNECTED__7;
wire SYNOPSYS_UNCONNECTED__8;
wire SYNOPSYS_UNCONNECTED__9;
wire SYNOPSYS_UNCONNECTED__10;
wire SYNOPSYS_UNCONNECTED__11;
wire SYNOPSYS_UNCONNECTED__12;
wire SYNOPSYS_UNCONNECTED__13;
wire SYNOPSYS_UNCONNECTED__14;
wire SYNOPSYS_UNCONNECTED__15;
wire SYNOPSYS_UNCONNECTED__16;
wire SYNOPSYS_UNCONNECTED__17;
wire SYNOPSYS_UNCONNECTED__18;
wire SYNOPSYS_UNCONNECTED__19;
wire SYNOPSYS_UNCONNECTED__20;
wire SYNOPSYS_UNCONNECTED__21;
wire SYNOPSYS_UNCONNECTED__22;
wire SYNOPSYS_UNCONNECTED__23;
wire SYNOPSYS_UNCONNECTED__24;
wire SYNOPSYS_UNCONNECTED__25;
wire SYNOPSYS_UNCONNECTED__26;
wire SYNOPSYS_UNCONNECTED__27;
wire SYNOPSYS_UNCONNECTED__28;
wire SYNOPSYS_UNCONNECTED__29;
wire SYNOPSYS_UNCONNECTED__30;
wire SYNOPSYS_UNCONNECTED__31;
wire SYNOPSYS_UNCONNECTED__32;
wire SYNOPSYS_UNCONNECTED__33;
wire SYNOPSYS_UNCONNECTED__34;
wire SYNOPSYS_UNCONNECTED__35;
wire SYNOPSYS_UNCONNECTED__36;
wire SYNOPSYS_UNCONNECTED__37;
wire SYNOPSYS_UNCONNECTED__38;
wire SYNOPSYS_UNCONNECTED__39;
wire SYNOPSYS_UNCONNECTED__40;
wire SYNOPSYS_UNCONNECTED__41;
wire SYNOPSYS_UNCONNECTED__42;
wire SYNOPSYS_UNCONNECTED__43;
wire SYNOPSYS_UNCONNECTED__44;
wire SYNOPSYS_UNCONNECTED__45;
assign controls_in_20 = controls_in[20] ;
assign controls_in_19 = controls_in[19] ;
assign controls_in_17 = controls_in[17] ;
assign controls_in_16 = controls_in[16] ;
assign controls_in_15 = controls_in[15] ;
assign controls_in_14 = controls_in[14] ;
assign controls_out[10] = \controls_in[21] ;
assign \controls_in[21] = controls_in[21] ;
assign controls_out[9] = \controls_in[18] ;
assign \controls_in[18] = controls_in[18] ;
assign controls_out[8] = \controls_in[13] ;
assign \controls_in[13] = controls_in[13] ;
assign controls_out[7] = \controls_in[12] ;
assign \controls_in[12] = controls_in[12] ;
assign controls_out[6] = \controls_in[11] ;
assign IDEX_memread[3] = \controls_in[11] ;
assign \controls_in[11] = controls_in[11] ;
assign controls_out[5] = \controls_in[10] ;
assign IDEX_memread[2] = \controls_in[10] ;
assign \controls_in[10] = controls_in[10] ;
assign controls_out[4] = \controls_in[9] ;
assign IDEX_memread[1] = \controls_in[9] ;
assign \controls_in[9] = controls_in[9] ;
assign controls_out[3] = \controls_in[8] ;
assign IDEX_memread[0] = \controls_in[8] ;
assign \controls_in[8] = controls_in[8] ;
assign controls_out[2] = \controls_in[7] ;
assign \controls_in[7] = controls_in[7] ;
assign controls_out[1] = \controls_in[6] ;
assign \controls_in[6] = controls_in[6] ;
assign controls_out[0] = \controls_in[5] ;
assign \controls_in[5] = controls_in[5] ;
assign IDEX_rt[4] = rt_inst[4] ;
assign IDEX_rt[3] = rt_inst[3] ;
assign IDEX_rt[2] = rt_inst[2] ;
assign IDEX_rt[1] = rt_inst[1] ;
assign IDEX_rt[0] = rt_inst[0] ;
adder_0 adder1 (.a(ext25_0),
.b(nextPC),
.res({ \resAdd1_i[31] ,
\resAdd1_i[30] ,
\resAdd1_i[29] ,
\resAdd1_i[28] ,
\resAdd1_i[27] ,
\resAdd1_i[26] ,
\resAdd1_i[25] ,
\resAdd1_i[24] ,
\resAdd1_i[23] ,
\resAdd1_i[22] ,
\resAdd1_i[21] ,
\resAdd1_i[20] ,
\resAdd1_i[19] ,
\resAdd1_i[18] ,
\resAdd1_i[17] ,
\resAdd1_i[16] ,
\resAdd1_i[15] ,
\resAdd1_i[14] ,
\resAdd1_i[13] ,
\resAdd1_i[12] ,
\resAdd1_i[11] ,
\resAdd1_i[10] ,
\resAdd1_i[9] ,
\resAdd1_i[8] ,
\resAdd1_i[7] ,
\resAdd1_i[6] ,
\resAdd1_i[5] ,
\resAdd1_i[4] ,
\resAdd1_i[3] ,
\resAdd1_i[2] ,
\resAdd1_i[1] ,
\resAdd1_i[0] }));
adder_2 adder2 (.a(nextPC),
.b(ext15_0),
.res(toPC2));
adder_1 plus4_adder (.a(nextPC),
.b({ 1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b1,
1'b0,
1'b0 }),
.res({ \link_value_i[31] ,
\link_value_i[30] ,
\link_value_i[29] ,
\link_value_i[28] ,
\link_value_i[27] ,
\link_value_i[26] ,
\link_value_i[25] ,
\link_value_i[24] ,
\link_value_i[23] ,
\link_value_i[22] ,
\link_value_i[21] ,
\link_value_i[20] ,
\link_value_i[19] ,
\link_value_i[18] ,
\link_value_i[17] ,
\link_value_i[16] ,
\link_value_i[15] ,
\link_value_i[14] ,
\link_value_i[13] ,
\link_value_i[12] ,
\link_value_i[11] ,
\link_value_i[10] ,
\link_value_i[9] ,
\link_value_i[8] ,
\link_value_i[7] ,
\link_value_i[6] ,
\link_value_i[5] ,
\link_value_i[4] ,
\link_value_i[3] ,
\link_value_i[2] ,
\link_value_i[1] ,
\link_value_i[0] }));
mux21_NBIT32_0 jreg_mux21 (.A(A_inALU_i),
.B({ \resAdd1_i[31] ,
\resAdd1_i[30] ,
\resAdd1_i[29] ,
\resAdd1_i[28] ,
\resAdd1_i[27] ,
\resAdd1_i[26] ,
\resAdd1_i[25] ,
\resAdd1_i[24] ,
\resAdd1_i[23] ,
\resAdd1_i[22] ,
\resAdd1_i[21] ,
\resAdd1_i[20] ,
\resAdd1_i[19] ,
\resAdd1_i[18] ,
\resAdd1_i[17] ,
\resAdd1_i[16] ,
\resAdd1_i[15] ,
\resAdd1_i[14] ,
\resAdd1_i[13] ,
\resAdd1_i[12] ,
\resAdd1_i[11] ,
\resAdd1_i[10] ,
\resAdd1_i[9] ,
\resAdd1_i[8] ,
\resAdd1_i[7] ,
\resAdd1_i[6] ,
\resAdd1_i[5] ,
\resAdd1_i[4] ,
\resAdd1_i[3] ,
\resAdd1_i[2] ,
\resAdd1_i[1] ,
\resAdd1_i[0] }),
.S(controls_in_20),
.Y(toPC1));
mux21_NBIT32_5 link_mux21 (.A({ \link_value_i[31] ,
\link_value_i[30] ,
\link_value_i[29] ,
\link_value_i[28] ,
\link_value_i[27] ,
\link_value_i[26] ,
\link_value_i[25] ,
\link_value_i[24] ,
\link_value_i[23] ,
\link_value_i[22] ,
\link_value_i[21] ,
\link_value_i[20] ,
\link_value_i[19] ,
\link_value_i[18] ,
\link_value_i[17] ,
\link_value_i[16] ,
\link_value_i[15] ,
\link_value_i[14] ,
\link_value_i[13] ,
\link_value_i[12] ,
\link_value_i[11] ,
\link_value_i[10] ,
\link_value_i[9] ,
\link_value_i[8] ,
\link_value_i[7] ,
\link_value_i[6] ,
\link_value_i[5] ,
\link_value_i[4] ,
\link_value_i[3] ,
\link_value_i[2] ,
\link_value_i[1] ,
\link_value_i[0] }),
.B(res_outALU_i),
.S(\controls_in[18] ),
.Y({ \link2lhi_wire_i[31] ,
\link2lhi_wire_i[30] ,
\link2lhi_wire_i[29] ,
\link2lhi_wire_i[28] ,
\link2lhi_wire_i[27] ,
\link2lhi_wire_i[26] ,
\link2lhi_wire_i[25] ,
\link2lhi_wire_i[24] ,
\link2lhi_wire_i[23] ,
\link2lhi_wire_i[22] ,
\link2lhi_wire_i[21] ,
\link2lhi_wire_i[20] ,
\link2lhi_wire_i[19] ,
\link2lhi_wire_i[18] ,
\link2lhi_wire_i[17] ,
\link2lhi_wire_i[16] ,
\link2lhi_wire_i[15] ,
\link2lhi_wire_i[14] ,
\link2lhi_wire_i[13] ,
\link2lhi_wire_i[12] ,
\link2lhi_wire_i[11] ,
\link2lhi_wire_i[10] ,
\link2lhi_wire_i[9] ,
\link2lhi_wire_i[8] ,
\link2lhi_wire_i[7] ,
\link2lhi_wire_i[6] ,
\link2lhi_wire_i[5] ,
\link2lhi_wire_i[4] ,
\link2lhi_wire_i[3] ,
\link2lhi_wire_i[2] ,
\link2lhi_wire_i[1] ,
\link2lhi_wire_i[0] }));
mux21_NBIT32_4 lhi_mux21 (.A({ lhi_value_i[31],
lhi_value_i[30],
lhi_value_i[29],
lhi_value_i[28],
lhi_value_i[27],
lhi_value_i[26],
lhi_value_i[25],
lhi_value_i[24],
lhi_value_i[23],
lhi_value_i[22],
lhi_value_i[21],
lhi_value_i[20],
lhi_value_i[19],
lhi_value_i[18],
lhi_value_i[17],
lhi_value_i[16],
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0 }),
.B({ \link2lhi_wire_i[31] ,
\link2lhi_wire_i[30] ,
\link2lhi_wire_i[29] ,
\link2lhi_wire_i[28] ,
\link2lhi_wire_i[27] ,
\link2lhi_wire_i[26] ,
\link2lhi_wire_i[25] ,
\link2lhi_wire_i[24] ,
\link2lhi_wire_i[23] ,
\link2lhi_wire_i[22] ,
\link2lhi_wire_i[21] ,
\link2lhi_wire_i[20] ,
\link2lhi_wire_i[19] ,
\link2lhi_wire_i[18] ,
\link2lhi_wire_i[17] ,
\link2lhi_wire_i[16] ,
\link2lhi_wire_i[15] ,
\link2lhi_wire_i[14] ,
\link2lhi_wire_i[13] ,
\link2lhi_wire_i[12] ,
\link2lhi_wire_i[11] ,
\link2lhi_wire_i[10] ,
\link2lhi_wire_i[9] ,
\link2lhi_wire_i[8] ,
\link2lhi_wire_i[7] ,
\link2lhi_wire_i[6] ,
\link2lhi_wire_i[5] ,
\link2lhi_wire_i[4] ,
\link2lhi_wire_i[3] ,
\link2lhi_wire_i[2] ,
\link2lhi_wire_i[1] ,
\link2lhi_wire_i[0] }),
.S(controls_in_17),
.Y({ \lhi2mov_wire_i[31] ,
\lhi2mov_wire_i[30] ,
\lhi2mov_wire_i[29] ,
\lhi2mov_wire_i[28] ,
\lhi2mov_wire_i[27] ,
\lhi2mov_wire_i[26] ,
\lhi2mov_wire_i[25] ,
\lhi2mov_wire_i[24] ,
\lhi2mov_wire_i[23] ,
\lhi2mov_wire_i[22] ,
\lhi2mov_wire_i[21] ,
\lhi2mov_wire_i[20] ,
\lhi2mov_wire_i[19] ,
\lhi2mov_wire_i[18] ,
\lhi2mov_wire_i[17] ,
\lhi2mov_wire_i[16] ,
\lhi2mov_wire_i[15] ,
\lhi2mov_wire_i[14] ,
\lhi2mov_wire_i[13] ,
\lhi2mov_wire_i[12] ,
\lhi2mov_wire_i[11] ,
\lhi2mov_wire_i[10] ,
\lhi2mov_wire_i[9] ,
\lhi2mov_wire_i[8] ,
\lhi2mov_wire_i[7] ,
\lhi2mov_wire_i[6] ,
\lhi2mov_wire_i[5] ,
\lhi2mov_wire_i[4] ,
\lhi2mov_wire_i[3] ,
\lhi2mov_wire_i[2] ,
\lhi2mov_wire_i[1] ,
\lhi2mov_wire_i[0] }));
mux21_NBIT5_0 regaddr_mux21 (.A(rd_inst),
.B(rt_inst),
.S(controls_in_16),
.Y(addrRF));
mux21_NBIT32_3 movs2i_mux21 (.A({ 1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
psw_status_i[1],
psw_status_i[0] }),
.B({ \lhi2mov_wire_i[31] ,
\lhi2mov_wire_i[30] ,
\lhi2mov_wire_i[29] ,
\lhi2mov_wire_i[28] ,
\lhi2mov_wire_i[27] ,
\lhi2mov_wire_i[26] ,
\lhi2mov_wire_i[25] ,
\lhi2mov_wire_i[24] ,
\lhi2mov_wire_i[23] ,
\lhi2mov_wire_i[22] ,
\lhi2mov_wire_i[21] ,
\lhi2mov_wire_i[20] ,
\lhi2mov_wire_i[19] ,
\lhi2mov_wire_i[18] ,
\lhi2mov_wire_i[17] ,
\lhi2mov_wire_i[16] ,
\lhi2mov_wire_i[15] ,
\lhi2mov_wire_i[14] ,
\lhi2mov_wire_i[13] ,
\lhi2mov_wire_i[12] ,
\lhi2mov_wire_i[11] ,
\lhi2mov_wire_i[10] ,
\lhi2mov_wire_i[9] ,
\lhi2mov_wire_i[8] ,
\lhi2mov_wire_i[7] ,
\lhi2mov_wire_i[6] ,
\lhi2mov_wire_i[5] ,
\lhi2mov_wire_i[4] ,
\lhi2mov_wire_i[3] ,
\lhi2mov_wire_i[2] ,
\lhi2mov_wire_i[1] ,
\lhi2mov_wire_i[0] }),
.S(controls_in_15),
.Y(addrMem));
mux21_NBIT32_2 alusrc_mux21 (.A(ext15_0),
.B(writeData),
.S(controls_in_14),
.Y(B_inALU_i));
mux41_NBIT32_0 oprnd1_mux41 (.a(op_A),
.b(forw_dataWB),
.c(forw_dataMEM),
.s(forwardA_i),
.y(A_inALU_i));
mux41_NBIT32_1 oprnd2_mux41 (.a(op_B),
.b(forw_dataWB),
.c(forw_dataMEM),
.s(forwardB_i),
.y(writeData));
concat16 concatenate16 (.string16(inst15_0),
.string32({ lhi_value_i[31],
lhi_value_i[30],
lhi_value_i[29],
lhi_value_i[28],
lhi_value_i[27],
lhi_value_i[26],
lhi_value_i[25],
lhi_value_i[24],
lhi_value_i[23],
lhi_value_i[22],
lhi_value_i[21],
lhi_value_i[20],
lhi_value_i[19],
lhi_value_i[18],
lhi_value_i[17],
lhi_value_i[16],
SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
SYNOPSYS_UNCONNECTED__2,
SYNOPSYS_UNCONNECTED__3,
SYNOPSYS_UNCONNECTED__4,
SYNOPSYS_UNCONNECTED__5,
SYNOPSYS_UNCONNECTED__6,
SYNOPSYS_UNCONNECTED__7,
SYNOPSYS_UNCONNECTED__8,
SYNOPSYS_UNCONNECTED__9,
SYNOPSYS_UNCONNECTED__10,
SYNOPSYS_UNCONNECTED__11,
SYNOPSYS_UNCONNECTED__12,
SYNOPSYS_UNCONNECTED__13,
SYNOPSYS_UNCONNECTED__14,
SYNOPSYS_UNCONNECTED__15 }));
forward forwarding_unit (.rt_addr_IDEX(rt_inst),
.rs_addr_IDEX(rs_inst),
.rd_addr_EXMEM(RFaddr_MEM),
.rd_addr_MEMWB(RFaddr_WB),
.regwrite_EXMEM(regwriteMEM),
.regwrite_MEMWB(regwriteWB),
.forwardA(forwardA_i),
.forwardB(forwardB_i));
branch_circ branch_circuit (.branch_type(controls_in_19),
.zero(zero_i),
.branch_taken(branchTaken));
PSWreg PSW (.rst(rst),
.clk(clk),
.unaligned(unaligned),
.ovf(FE_UNCONNECTED_0),
.status({ SYNOPSYS_UNCONNECTED__16,
SYNOPSYS_UNCONNECTED__17,
SYNOPSYS_UNCONNECTED__18,
SYNOPSYS_UNCONNECTED__19,
SYNOPSYS_UNCONNECTED__20,
SYNOPSYS_UNCONNECTED__21,
SYNOPSYS_UNCONNECTED__22,
SYNOPSYS_UNCONNECTED__23,
SYNOPSYS_UNCONNECTED__24,
SYNOPSYS_UNCONNECTED__25,
SYNOPSYS_UNCONNECTED__26,
SYNOPSYS_UNCONNECTED__27,
SYNOPSYS_UNCONNECTED__28,
SYNOPSYS_UNCONNECTED__29,
SYNOPSYS_UNCONNECTED__30,
SYNOPSYS_UNCONNECTED__31,
SYNOPSYS_UNCONNECTED__32,
SYNOPSYS_UNCONNECTED__33,
SYNOPSYS_UNCONNECTED__34,
SYNOPSYS_UNCONNECTED__35,
SYNOPSYS_UNCONNECTED__36,
SYNOPSYS_UNCONNECTED__37,
SYNOPSYS_UNCONNECTED__38,
SYNOPSYS_UNCONNECTED__39,
SYNOPSYS_UNCONNECTED__40,
SYNOPSYS_UNCONNECTED__41,
SYNOPSYS_UNCONNECTED__42,
SYNOPSYS_UNCONNECTED__43,
SYNOPSYS_UNCONNECTED__44,
SYNOPSYS_UNCONNECTED__45,
psw_status_i[1],
psw_status_i[0] }));
ALU EXALU (.alu_op({ controls_in[4],
controls_in[3],
controls_in[2],
controls_in[1],
controls_in[0] }),
.a(A_inALU_i),
.b(B_inALU_i),
.ovf(FE_UNCONNECTED_0),
.zero(zero_i),
.res(res_outALU_i));
endmodule
module idex_reg (
cw_to_ex_dec,
jump_address_dec,
pc_4_dec,
read_data_1_dec,
read_data_2_dec,
immediate_ext_dec,
immediate_dec,
rt_dec,
rd_dec,
rs_dec,
clk,
rst,
cw_to_ex,
jump_address,
pc_4,
read_data_1,
read_data_2,
immediate_ext,
immediate,
rt,
rd,
rs,
clk__L2_N5,
clk__L2_N6,
clk__L2_N7,
clk__L2_N8,
clk__L2_N9);
input [21:0] cw_to_ex_dec;
input [31:0] jump_address_dec;
input [31:0] pc_4_dec;
input [31:0] read_data_1_dec;
input [31:0] read_data_2_dec;
input [31:0] immediate_ext_dec;
input [15:0] immediate_dec;
input [4:0] rt_dec;
input [4:0] rd_dec;
input [4:0] rs_dec;
input clk;
input rst;
output [21:0] cw_to_ex;
output [31:0] jump_address;
output [31:0] pc_4;
output [31:0] read_data_1;
output [31:0] read_data_2;
output [31:0] immediate_ext;
output [15:0] immediate;
output [4:0] rt;
output [4:0] rd;
output [4:0] rs;
input clk__L2_N5;
input clk__L2_N6;
input clk__L2_N7;
input clk__L2_N8;
input clk__L2_N9;
// Internal wires
wire FE_OFN0_n215;
wire N3;
wire N4;
wire N5;
wire N6;
wire N7;
wire N8;
wire N9;
wire N10;
wire N11;
wire N12;
wire N13;
wire N14;
wire N15;
wire N16;
wire N17;
wire N18;
wire N19;
wire N20;
wire N21;
wire N22;
wire N23;
wire N24;
wire N57;
wire N58;
wire N59;
wire N60;
wire N61;
wire N62;
wire N63;
wire N64;
wire N65;
wire N66;
wire N67;
wire N68;
wire N69;
wire N70;
wire N71;
wire N72;
wire N73;
wire N74;
wire N75;
wire N76;
wire N77;
wire N78;
wire N79;
wire N80;
wire N81;
wire N82;
wire N83;
wire N84;
wire N85;
wire N86;
wire N87;
wire N88;
wire N185;
wire N186;
wire N187;
wire N188;
wire N189;
wire N190;
wire N191;
wire N192;
wire N193;
wire N194;
wire N195;
wire N196;
wire N197;
wire N198;
wire N199;
wire N200;
wire N201;
wire N202;
wire N203;
wire N204;
wire N205;
wire n215;
CLKBUF_X1 FE_OFC0_n215 (.Z(FE_OFN0_n215),
.A(n215));
DFF_X1 \cw_to_ex_reg[21] (.Q(cw_to_ex[21]),
.D(N24),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[20] (.Q(cw_to_ex[20]),
.D(N23),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[19] (.Q(cw_to_ex[19]),
.D(N22),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[18] (.Q(cw_to_ex[18]),
.D(N21),
.CK(clk__L2_N9));
DFF_X1 \cw_to_ex_reg[17] (.Q(cw_to_ex[17]),
.D(N20),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[16] (.Q(cw_to_ex[16]),
.D(N19),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[15] (.Q(cw_to_ex[15]),
.D(N18),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[14] (.Q(cw_to_ex[14]),
.D(N17),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[13] (.Q(cw_to_ex[13]),
.D(N16),
.CK(clk__L2_N9));
DFF_X1 \cw_to_ex_reg[12] (.Q(cw_to_ex[12]),
.D(N15),
.CK(clk__L2_N9));
DFF_X1 \cw_to_ex_reg[11] (.Q(cw_to_ex[11]),
.D(N14),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[10] (.Q(cw_to_ex[10]),
.D(N13),
.CK(clk__L2_N9));
DFF_X1 \cw_to_ex_reg[9] (.Q(cw_to_ex[9]),
.D(N12),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[8] (.Q(cw_to_ex[8]),
.D(N11),
.CK(clk__L2_N8));
DFF_X1 \cw_to_ex_reg[7] (.Q(cw_to_ex[7]),
.D(N10),
.CK(clk__L2_N9));
DFF_X1 \cw_to_ex_reg[6] (.Q(cw_to_ex[6]),
.D(N9),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[5] (.Q(cw_to_ex[5]),
.D(N8),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[4] (.Q(cw_to_ex[4]),
.D(N7),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[3] (.Q(cw_to_ex[3]),
.D(N6),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[2] (.Q(cw_to_ex[2]),
.D(N5),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[1] (.Q(cw_to_ex[1]),
.D(N4),
.CK(clk__L2_N7));
DFF_X1 \cw_to_ex_reg[0] (.Q(cw_to_ex[0]),
.D(N3),
.CK(clk__L2_N7));
DFF_X1 \immediate_reg[15] (.Q(immediate[15]),
.D(N200),
.CK(clk__L2_N7));
DFF_X1 \immediate_reg[14] (.Q(immediate[14]),
.D(N199),
.CK(clk__L2_N5));
DFF_X1 \immediate_reg[13] (.Q(immediate[13]),
.D(N198),
.CK(clk__L2_N6));
DFF_X1 \immediate_reg[12] (.Q(immediate[12]),
.D(N197),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[11] (.Q(immediate[11]),
.D(N196),
.CK(clk__L2_N7));
DFF_X1 \immediate_reg[10] (.Q(immediate[10]),
.D(N195),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[9] (.Q(immediate[9]),
.D(N194),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[8] (.Q(immediate[8]),
.D(N193),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[7] (.Q(immediate[7]),
.D(N192),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[6] (.Q(immediate[6]),
.D(N191),
.CK(clk__L2_N8));
DFF_X1 \immediate_reg[5] (.Q(immediate[5]),
.D(N190),
.CK(clk));
DFF_X1 \immediate_reg[4] (.Q(immediate[4]),
.D(N189),
.CK(clk));
DFF_X1 \immediate_reg[3] (.Q(immediate[3]),
.D(N188),
.CK(clk__L2_N9));
DFF_X1 \immediate_reg[2] (.Q(immediate[2]),
.D(N187),
.CK(clk__L2_N9));
DFF_X1 \immediate_reg[1] (.Q(immediate[1]),
.D(N186),
.CK(clk__L2_N9));
DFF_X1 \immediate_reg[0] (.Q(immediate[0]),
.D(N185),
.CK(clk));
DFF_X1 \rt_reg[4] (.Q(rt[4]),
.D(N205),
.CK(clk__L2_N6));
DFF_X1 \rt_reg[3] (.Q(rt[3]),
.D(N204),
.CK(clk__L2_N6));
DFF_X1 \rt_reg[2] (.Q(rt[2]),
.D(N203),
.CK(clk__L2_N6));
DFF_X1 \rt_reg[1] (.Q(rt[1]),
.D(N202),
.CK(clk__L2_N6));
DFF_X1 \rt_reg[0] (.Q(rt[0]),
.D(N201),
.CK(clk__L2_N6));
AND2_X1 U21 (.ZN(N10),
.A2(n215),
.A1(cw_to_ex_dec[7]));
AND2_X1 U22 (.ZN(N15),
.A2(n215),
.A1(cw_to_ex_dec[12]));
AND2_X1 U23 (.ZN(N19),
.A2(n215),
.A1(cw_to_ex_dec[16]));
AND2_X1 U24 (.ZN(N21),
.A2(n215),
.A1(cw_to_ex_dec[18]));
AND2_X1 U76 (.ZN(N3),
.A2(n215),
.A1(cw_to_ex_dec[0]));
AND2_X1 U77 (.ZN(N4),
.A2(n215),
.A1(cw_to_ex_dec[1]));
AND2_X1 U78 (.ZN(N8),
.A2(n215),
.A1(cw_to_ex_dec[5]));
AND2_X1 U79 (.ZN(N9),
.A2(n215),
.A1(cw_to_ex_dec[6]));
AND2_X1 U80 (.ZN(N11),
.A2(n215),
.A1(cw_to_ex_dec[8]));
AND2_X1 U81 (.ZN(N12),
.A2(n215),
.A1(cw_to_ex_dec[9]));
AND2_X1 U82 (.ZN(N13),
.A2(n215),
.A1(cw_to_ex_dec[10]));
AND2_X1 U83 (.ZN(N16),
.A2(n215),
.A1(cw_to_ex_dec[13]));
AND2_X1 U84 (.ZN(N20),
.A2(n215),
.A1(cw_to_ex_dec[17]));
AND2_X1 U85 (.ZN(N23),
.A2(n215),
.A1(cw_to_ex_dec[20]));
AND2_X1 U86 (.ZN(N24),
.A2(n215),
.A1(cw_to_ex_dec[21]));
AND2_X1 U87 (.ZN(N187),
.A2(n215),
.A1(immediate_dec[2]));
INV_X2 U90 (.ZN(n215),
.A(rst));
AND2_X1 U99 (.ZN(N203),
.A2(n215),
.A1(rt_dec[2]));
AND2_X1 U101 (.ZN(N188),
.A2(n215),
.A1(immediate_dec[3]));
AND2_X1 U104 (.ZN(N185),
.A2(n215),
.A1(immediate_dec[0]));
AND2_X1 U109 (.ZN(N186),
.A2(n215),
.A1(immediate_dec[1]));
AND2_X1 U112 (.ZN(N190),
.A2(n215),
.A1(immediate_dec[5]));
AND2_X1 U117 (.ZN(N205),
.A2(n215),
.A1(rt_dec[4]));
AND2_X1 U119 (.ZN(N202),
.A2(n215),
.A1(rt_dec[1]));
AND2_X1 U120 (.ZN(N204),
.A2(n215),
.A1(rt_dec[3]));
AND2_X1 U127 (.ZN(N189),
.A2(n215),
.A1(immediate_dec[4]));
AND2_X1 U130 (.ZN(N201),
.A2(n215),
.A1(rt_dec[0]));
AND2_X1 U133 (.ZN(N200),
.A2(n215),
.A1(immediate_dec[15]));
AND2_X1 U136 (.ZN(N191),
.A2(n215),
.A1(immediate_dec[6]));
AND2_X1 U139 (.ZN(N192),
.A2(n215),
.A1(immediate_dec[7]));
AND2_X1 U142 (.ZN(N193),
.A2(n215),
.A1(immediate_dec[8]));
AND2_X1 U145 (.ZN(N194),
.A2(n215),
.A1(immediate_dec[9]));
AND2_X1 U148 (.ZN(N195),
.A2(n215),
.A1(immediate_dec[10]));
AND2_X1 U155 (.ZN(N196),
.A2(n215),
.A1(immediate_dec[11]));
AND2_X1 U156 (.ZN(N197),
.A2(n215),
.A1(immediate_dec[12]));
AND2_X1 U157 (.ZN(N198),
.A2(n215),
.A1(immediate_dec[13]));
AND2_X1 U158 (.ZN(N199),
.A2(n215),
.A1(immediate_dec[14]));
AND2_X1 U186 (.ZN(N57),
.A2(n215),
.A1(pc_4_dec[0]));
AND2_X1 U187 (.ZN(N58),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[1]));
AND2_X1 U188 (.ZN(N59),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[2]));
AND2_X1 U189 (.ZN(N60),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[3]));
AND2_X1 U190 (.ZN(N61),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[4]));
AND2_X1 U191 (.ZN(N62),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[5]));
AND2_X1 U192 (.ZN(N63),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[6]));
AND2_X1 U193 (.ZN(N64),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[7]));
AND2_X1 U194 (.ZN(N65),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[8]));
AND2_X1 U195 (.ZN(N66),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[9]));
AND2_X1 U196 (.ZN(N67),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[10]));
AND2_X1 U197 (.ZN(N68),
.A2(n215),
.A1(pc_4_dec[11]));
AND2_X1 U198 (.ZN(N69),
.A2(n215),
.A1(pc_4_dec[12]));
AND2_X1 U199 (.ZN(N70),
.A2(n215),
.A1(pc_4_dec[13]));
AND2_X1 U200 (.ZN(N71),
.A2(n215),
.A1(pc_4_dec[14]));
AND2_X1 U201 (.ZN(N72),
.A2(n215),
.A1(pc_4_dec[15]));
AND2_X1 U202 (.ZN(N73),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[16]));
AND2_X1 U203 (.ZN(N74),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[17]));
AND2_X1 U204 (.ZN(N75),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[18]));
AND2_X1 U205 (.ZN(N76),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[19]));
AND2_X1 U206 (.ZN(N77),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[20]));
AND2_X1 U207 (.ZN(N78),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[21]));
AND2_X1 U208 (.ZN(N79),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[22]));
AND2_X1 U209 (.ZN(N80),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[23]));
AND2_X1 U210 (.ZN(N81),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[24]));
AND2_X1 U211 (.ZN(N82),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[25]));
AND2_X1 U212 (.ZN(N83),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[26]));
AND2_X1 U213 (.ZN(N84),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[27]));
AND2_X1 U214 (.ZN(N85),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[28]));
AND2_X1 U215 (.ZN(N86),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[29]));
AND2_X1 U216 (.ZN(N87),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[30]));
AND2_X1 U217 (.ZN(N88),
.A2(FE_OFN0_n215),
.A1(pc_4_dec[31]));
AND2_X1 U222 (.ZN(N5),
.A2(n215),
.A1(cw_to_ex_dec[2]));
AND2_X1 U223 (.ZN(N6),
.A2(n215),
.A1(cw_to_ex_dec[3]));
AND2_X1 U224 (.ZN(N7),
.A2(n215),
.A1(cw_to_ex_dec[4]));
AND2_X1 U225 (.ZN(N14),
.A2(n215),
.A1(cw_to_ex_dec[11]));
AND2_X1 U226 (.ZN(N17),
.A2(n215),
.A1(cw_to_ex_dec[14]));
AND2_X1 U227 (.ZN(N18),
.A2(n215),
.A1(cw_to_ex_dec[15]));
AND2_X1 U228 (.ZN(N22),
.A2(n215),
.A1(cw_to_ex_dec[19]));
endmodule
module decode_unit (
address_write,
data_write,
pc_4_from_dec,
instruction,
idex_rt,
clk,
rst,
reg_write,
idex_mem_read,
cw,
cw_to_ex,
jump_address,
pc_4_to_ex,
data_read_1,
data_read_2,
immediate_ext,
immediate,
rt,
rd,
rs,
opcode,
func,
pcwrite,
ifid_write);
input [4:0] address_write;
input [31:0] data_write;
input [31:0] pc_4_from_dec;
input [31:0] instruction;
input [4:0] idex_rt;
input clk;
input rst;
input reg_write;
input [3:0] idex_mem_read;
input [22:0] cw;
output [21:0] cw_to_ex;
output [31:0] jump_address;
output [31:0] pc_4_to_ex;
output [31:0] data_read_1;
output [31:0] data_read_2;
output [31:0] immediate_ext;
output [15:0] immediate;
output [4:0] rt;
output [4:0] rd;
output [4:0] rs;
output [5:0] opcode;
output [10:0] func;
output pcwrite;
output ifid_write;
// Internal wires
wire \instruction[15] ;
wire \instruction[14] ;
wire \instruction[13] ;
wire \instruction[12] ;
wire \instruction[11] ;
wire \instruction[20] ;
wire \instruction[19] ;
wire \instruction[18] ;
wire \instruction[17] ;
wire \instruction[16] ;
wire \instruction[25] ;
wire \instruction[24] ;
wire \instruction[23] ;
wire \instruction[22] ;
wire \instruction[21] ;
wire \instruction[31] ;
wire \instruction[30] ;
wire \instruction[29] ;
wire \instruction[28] ;
wire \instruction[27] ;
wire \instruction[26] ;
wire \instruction[10] ;
wire \instruction[9] ;
wire \instruction[8] ;
wire \instruction[7] ;
wire \instruction[6] ;
wire \instruction[5] ;
wire \instruction[4] ;
wire \instruction[3] ;
wire \instruction[2] ;
wire \instruction[1] ;
wire \instruction[0] ;
wire \cw_i[21] ;
wire mux_op_i;
assign pc_4_to_ex[31] = pc_4_from_dec[31] ;
assign pc_4_to_ex[30] = pc_4_from_dec[30] ;
assign pc_4_to_ex[29] = pc_4_from_dec[29] ;
assign pc_4_to_ex[28] = pc_4_from_dec[28] ;
assign pc_4_to_ex[27] = pc_4_from_dec[27] ;
assign pc_4_to_ex[26] = pc_4_from_dec[26] ;
assign pc_4_to_ex[25] = pc_4_from_dec[25] ;
assign pc_4_to_ex[24] = pc_4_from_dec[24] ;
assign pc_4_to_ex[23] = pc_4_from_dec[23] ;
assign pc_4_to_ex[22] = pc_4_from_dec[22] ;
assign pc_4_to_ex[21] = pc_4_from_dec[21] ;
assign pc_4_to_ex[20] = pc_4_from_dec[20] ;
assign pc_4_to_ex[19] = pc_4_from_dec[19] ;
assign pc_4_to_ex[18] = pc_4_from_dec[18] ;
assign pc_4_to_ex[17] = pc_4_from_dec[17] ;
assign pc_4_to_ex[16] = pc_4_from_dec[16] ;
assign pc_4_to_ex[15] = pc_4_from_dec[15] ;
assign pc_4_to_ex[14] = pc_4_from_dec[14] ;
assign pc_4_to_ex[13] = pc_4_from_dec[13] ;
assign pc_4_to_ex[12] = pc_4_from_dec[12] ;
assign pc_4_to_ex[11] = pc_4_from_dec[11] ;
assign pc_4_to_ex[10] = pc_4_from_dec[10] ;
assign pc_4_to_ex[9] = pc_4_from_dec[9] ;
assign pc_4_to_ex[8] = pc_4_from_dec[8] ;
assign pc_4_to_ex[7] = pc_4_from_dec[7] ;
assign pc_4_to_ex[6] = pc_4_from_dec[6] ;
assign pc_4_to_ex[5] = pc_4_from_dec[5] ;
assign pc_4_to_ex[4] = pc_4_from_dec[4] ;
assign pc_4_to_ex[3] = pc_4_from_dec[3] ;
assign pc_4_to_ex[2] = pc_4_from_dec[2] ;
assign pc_4_to_ex[1] = pc_4_from_dec[1] ;
assign pc_4_to_ex[0] = pc_4_from_dec[0] ;
assign immediate[15] = \instruction[15] ;
assign rd[4] = \instruction[15] ;
assign \instruction[15] = instruction[15] ;
assign immediate[14] = \instruction[14] ;
assign rd[3] = \instruction[14] ;
assign \instruction[14] = instruction[14] ;
assign immediate[13] = \instruction[13] ;
assign rd[2] = \instruction[13] ;
assign \instruction[13] = instruction[13] ;
assign immediate[12] = \instruction[12] ;
assign rd[1] = \instruction[12] ;
assign \instruction[12] = instruction[12] ;
assign immediate[11] = \instruction[11] ;
assign rd[0] = \instruction[11] ;
assign \instruction[11] = instruction[11] ;
assign rt[4] = \instruction[20] ;
assign \instruction[20] = instruction[20] ;
assign rt[3] = \instruction[19] ;
assign \instruction[19] = instruction[19] ;
assign rt[2] = \instruction[18] ;
assign \instruction[18] = instruction[18] ;
assign rt[1] = \instruction[17] ;
assign \instruction[17] = instruction[17] ;
assign rt[0] = \instruction[16] ;
assign \instruction[16] = instruction[16] ;
assign rs[4] = \instruction[25] ;
assign \instruction[25] = instruction[25] ;
assign rs[3] = \instruction[24] ;
assign \instruction[24] = instruction[24] ;
assign rs[2] = \instruction[23] ;
assign \instruction[23] = instruction[23] ;
assign rs[1] = \instruction[22] ;
assign \instruction[22] = instruction[22] ;
assign rs[0] = \instruction[21] ;
assign \instruction[21] = instruction[21] ;
assign opcode[5] = \instruction[31] ;
assign \instruction[31] = instruction[31] ;
assign opcode[4] = \instruction[30] ;
assign \instruction[30] = instruction[30] ;
assign opcode[3] = \instruction[29] ;
assign \instruction[29] = instruction[29] ;
assign opcode[2] = \instruction[28] ;
assign \instruction[28] = instruction[28] ;
assign opcode[1] = \instruction[27] ;
assign \instruction[27] = instruction[27] ;
assign opcode[0] = \instruction[26] ;
assign \instruction[26] = instruction[26] ;
assign immediate[10] = \instruction[10] ;
assign func[10] = \instruction[10] ;
assign \instruction[10] = instruction[10] ;
assign immediate[9] = \instruction[9] ;
assign func[9] = \instruction[9] ;
assign \instruction[9] = instruction[9] ;
assign immediate[8] = \instruction[8] ;
assign func[8] = \instruction[8] ;
assign \instruction[8] = instruction[8] ;
assign immediate[7] = \instruction[7] ;
assign func[7] = \instruction[7] ;
assign \instruction[7] = instruction[7] ;
assign immediate[6] = \instruction[6] ;
assign func[6] = \instruction[6] ;
assign \instruction[6] = instruction[6] ;
assign immediate[5] = \instruction[5] ;
assign func[5] = \instruction[5] ;
assign \instruction[5] = instruction[5] ;
assign immediate[4] = \instruction[4] ;
assign func[4] = \instruction[4] ;
assign \instruction[4] = instruction[4] ;
assign immediate[3] = \instruction[3] ;
assign func[3] = \instruction[3] ;
assign \instruction[3] = instruction[3] ;
assign immediate[2] = \instruction[2] ;
assign func[2] = \instruction[2] ;
assign \instruction[2] = instruction[2] ;
assign immediate[1] = \instruction[1] ;
assign func[1] = \instruction[1] ;
assign \instruction[1] = instruction[1] ;
assign immediate[0] = \instruction[0] ;
assign func[0] = \instruction[0] ;
assign \instruction[0] = instruction[0] ;
hdu hdu_0 (.clk(clk),
.rst(rst),
.idex_mem_read(idex_mem_read),
.idex_rt(idex_rt),
.rs({ \instruction[25] ,
\instruction[24] ,
\instruction[23] ,
\instruction[22] ,
\instruction[21] }),
.rt({ \instruction[20] ,
\instruction[19] ,
\instruction[18] ,
\instruction[17] ,
\instruction[16] }),
.pcwrite(pcwrite),
.ifidwrite(ifid_write),
.mux_op(mux_op_i));
mux_stall mux_stall0 (.cw_from_cu(cw),
.mux_op(mux_op_i),
.cw_from_mux({ cw_to_ex[21],
\cw_i[21] ,
cw_to_ex[20],
cw_to_ex[19],
cw_to_ex[18],
cw_to_ex[17],
cw_to_ex[16],
cw_to_ex[15],
cw_to_ex[14],
cw_to_ex[13],
cw_to_ex[12],
cw_to_ex[11],
cw_to_ex[10],
cw_to_ex[9],
cw_to_ex[8],
cw_to_ex[7],
cw_to_ex[6],
cw_to_ex[5],
cw_to_ex[4],
cw_to_ex[3],
cw_to_ex[2],
cw_to_ex[1],
cw_to_ex[0] }));
sign_extender sign_extender0 (.immediate_jump({ \instruction[25] ,
\instruction[24] ,
\instruction[23] ,
\instruction[22] ,
\instruction[21] ,
\instruction[20] ,
\instruction[19] ,
\instruction[18] ,
\instruction[17] ,
\instruction[16] ,
\instruction[15] ,
\instruction[14] ,
\instruction[13] ,
\instruction[12] ,
\instruction[11] ,
\instruction[10] ,
\instruction[9] ,
\instruction[8] ,
\instruction[7] ,
\instruction[6] ,
\instruction[5] ,
\instruction[4] ,
\instruction[3] ,
\instruction[2] ,
\instruction[1] ,
\instruction[0] }),
.extended_jump(jump_address));
extender extender0 (.immediate({ \instruction[15] ,
\instruction[14] ,
\instruction[13] ,
\instruction[12] ,
\instruction[11] ,
\instruction[10] ,
\instruction[9] ,
\instruction[8] ,
\instruction[7] ,
\instruction[6] ,
\instruction[5] ,
\instruction[4] ,
\instruction[3] ,
\instruction[2] ,
\instruction[1] ,
\instruction[0] }),
.unsigned_value(\cw_i[21] ),
.extended(immediate_ext));
reg_file reg_file0 (.read_address_1({ \instruction[25] ,
\instruction[24] ,
\instruction[23] ,
\instruction[22] ,
\instruction[21] }),
.read_address_2({ \instruction[20] ,
\instruction[19] ,
\instruction[18] ,
\instruction[17] ,
\instruction[16] }),
.write_address(address_write),
.write_data(data_write),
.reg_write(reg_write),
.rst(rst),
.data_reg_1(data_read_1),
.data_reg_2(data_read_2));
endmodule
module ifid_reg (
pc_4,
instruction_fetch,
flush,
ifid_write,
clk,
rst,
instruction_decode,
new_pc,
clk__L2_N1,
clk__L2_N2,
clk__L2_N3,
clk__L2_N4,
clk__L2_N5,
clk__L2_N6,
clk__L2_N7,
clk__L2_N8,
clk__L2_N9);
input [31:0] pc_4;
input [31:0] instruction_fetch;
input flush;
input ifid_write;
input clk;
input rst;
output [31:0] instruction_decode;
output [31:0] new_pc;
input clk__L2_N1;
input clk__L2_N2;
input clk__L2_N3;
input clk__L2_N4;
input clk__L2_N5;
input clk__L2_N6;
input clk__L2_N7;
input clk__L2_N8;
input clk__L2_N9;
// Internal wires
wire FE_PHN111_n191;
wire FE_PHN110_n193;
wire FE_PHN109_n195;
wire FE_PHN79_n191;
wire FE_PHN78_n193;
wire FE_PHN77_n195;
wire FE_PHN75_n191;
wire FE_PHN74_n193;
wire FE_PHN73_n195;
wire FE_PHN45_flush_i;
wire FE_PHN43_n184;
wire FE_PHN42_n183;
wire FE_PHN38_n175;
wire FE_PHN37_n185;
wire FE_PHN36_n194;
wire FE_PHN35_n189;
wire FE_PHN34_n179;
wire FE_PHN33_n181;
wire FE_PHN32_n186;
wire FE_PHN31_n187;
wire FE_PHN30_n182;
wire FE_PHN29_n174;
wire FE_PHN28_n192;
wire FE_PHN27_n190;
wire FE_PHN26_n191;
wire FE_PHN25_n193;
wire FE_PHN24_n195;
wire FE_PHN13_n188;
wire FE_PHN12_n197;
wire FE_PHN11_flush_i;
wire FE_OFN7_n65;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
wire n128;
wire n129;
wire n130;
wire n131;
wire n132;
wire n133;
wire n134;
wire n135;
wire n136;
wire n137;
wire n138;
wire n139;
wire n140;
wire n141;
wire n142;
wire n143;
wire n144;
wire n145;
wire n146;
wire n147;
wire n148;
wire n149;
wire n150;
wire n151;
wire n152;
wire n153;
wire n154;
wire n155;
wire n156;
wire n157;
wire n158;
wire n159;
wire n160;
wire n161;
wire n162;
wire n163;
wire n164;
wire n165;
wire n166;
wire n167;
wire n168;
wire n169;
wire n170;
wire n171;
wire n172;
wire n173;
wire n174;
wire n175;
wire n176;
wire n177;
wire n178;
wire n179;
wire n180;
wire n181;
wire n182;
wire n183;
wire n184;
wire n185;
wire n186;
wire n187;
wire n188;
wire n189;
wire n190;
wire n191;
wire n192;
wire n193;
wire n194;
wire n195;
wire n197;
wire n202;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n196;
wire n198;
wire n199;
wire n200;
wire n201;
wire n203;
wire n204;
wire n205;
wire n206;
wire n207;
wire n208;
wire n209;
wire n210;
wire n211;
wire n212;
wire n213;
wire n214;
wire n215;
wire n216;
wire n217;
wire n218;
wire n219;
wire n220;
wire n221;
wire n222;
wire n223;
wire n224;
wire n225;
wire n226;
wire n227;
wire n228;
wire n229;
wire n230;
wire n231;
wire n232;
wire n233;
wire n234;
wire n235;
wire n236;
wire n237;
wire n238;
wire n239;
wire n240;
wire n241;
wire n242;
wire n243;
wire n244;
wire n245;
wire n246;
wire n247;
wire n248;
wire n249;
wire n250;
wire n251;
wire n252;
wire n253;
wire n254;
wire n255;
wire n256;
wire n257;
wire n258;
wire n259;
CLKBUF_X1 FE_PHC111_n191 (.Z(FE_PHN111_n191),
.A(FE_PHN79_n191));
CLKBUF_X1 FE_PHC110_n193 (.Z(FE_PHN110_n193),
.A(FE_PHN78_n193));
CLKBUF_X1 FE_PHC109_n195 (.Z(FE_PHN109_n195),
.A(FE_PHN77_n195));
CLKBUF_X1 FE_PHC79_n191 (.Z(FE_PHN79_n191),
.A(FE_PHN26_n191));
CLKBUF_X1 FE_PHC78_n193 (.Z(FE_PHN78_n193),
.A(FE_PHN25_n193));
CLKBUF_X1 FE_PHC77_n195 (.Z(FE_PHN77_n195),
.A(FE_PHN24_n195));
CLKBUF_X1 FE_PHC75_n191 (.Z(FE_PHN75_n191),
.A(FE_PHN111_n191));
CLKBUF_X1 FE_PHC74_n193 (.Z(FE_PHN74_n193),
.A(FE_PHN110_n193));
CLKBUF_X1 FE_PHC73_n195 (.Z(FE_PHN73_n195),
.A(FE_PHN109_n195));
CLKBUF_X1 FE_PHC45_flush_i (.Z(FE_PHN45_flush_i),
.A(FE_PHN11_flush_i));
CLKBUF_X3 FE_PHC43_n184 (.Z(FE_PHN43_n184),
.A(n184));
CLKBUF_X3 FE_PHC42_n183 (.Z(FE_PHN42_n183),
.A(n183));
CLKBUF_X3 FE_PHC38_n175 (.Z(FE_PHN38_n175),
.A(n175));
CLKBUF_X3 FE_PHC37_n185 (.Z(FE_PHN37_n185),
.A(n185));
CLKBUF_X1 FE_PHC36_n194 (.Z(FE_PHN36_n194),
.A(n194));
CLKBUF_X1 FE_PHC35_n189 (.Z(FE_PHN35_n189),
.A(n189));
CLKBUF_X3 FE_PHC34_n179 (.Z(FE_PHN34_n179),
.A(n179));
CLKBUF_X3 FE_PHC33_n181 (.Z(FE_PHN33_n181),
.A(n181));
CLKBUF_X3 FE_PHC32_n186 (.Z(FE_PHN32_n186),
.A(n186));
CLKBUF_X3 FE_PHC31_n187 (.Z(FE_PHN31_n187),
.A(n187));
CLKBUF_X3 FE_PHC30_n182 (.Z(FE_PHN30_n182),
.A(n182));
CLKBUF_X3 FE_PHC29_n174 (.Z(FE_PHN29_n174),
.A(n174));
CLKBUF_X3 FE_PHC28_n192 (.Z(FE_PHN28_n192),
.A(n192));
CLKBUF_X3 FE_PHC27_n190 (.Z(FE_PHN27_n190),
.A(n190));
CLKBUF_X1 FE_PHC26_n191 (.Z(FE_PHN26_n191),
.A(n191));
CLKBUF_X1 FE_PHC25_n193 (.Z(FE_PHN25_n193),
.A(n193));
CLKBUF_X1 FE_PHC24_n195 (.Z(FE_PHN24_n195),
.A(n195));
CLKBUF_X1 FE_PHC13_n188 (.Z(FE_PHN13_n188),
.A(n188));
CLKBUF_X1 FE_PHC12_n197 (.Z(FE_PHN12_n197),
.A(n197));
CLKBUF_X1 FE_PHC11_flush_i (.Z(FE_PHN11_flush_i),
.A(flush));
CLKBUF_X2 FE_OFC7_n65 (.Z(FE_OFN7_n65),
.A(n65));
DFFR_X1 \instruction_decode_reg[31] (.RN(n202),
.QN(n132),
.Q(instruction_decode[31]),
.D(FE_PHN12_n197),
.CK(clk__L2_N8));
DFFS_X1 \instruction_decode_reg[30] (.SN(n202),
.QN(n131),
.Q(instruction_decode[30]),
.D(FE_PHN73_n195),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[29] (.RN(n202),
.QN(n130),
.Q(instruction_decode[29]),
.D(FE_PHN36_n194),
.CK(clk__L2_N8));
DFFS_X1 \instruction_decode_reg[28] (.SN(n202),
.QN(n129),
.Q(instruction_decode[28]),
.D(FE_PHN74_n193),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[27] (.RN(n202),
.QN(n128),
.Q(instruction_decode[27]),
.D(FE_PHN28_n192),
.CK(clk__L2_N8));
DFFS_X1 \instruction_decode_reg[26] (.SN(n202),
.QN(n127),
.Q(instruction_decode[26]),
.D(FE_PHN75_n191),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[25] (.RN(n202),
.QN(n126),
.Q(instruction_decode[25]),
.D(FE_PHN27_n190),
.CK(clk__L2_N4));
DFFR_X1 \instruction_decode_reg[24] (.RN(n202),
.QN(n125),
.Q(instruction_decode[24]),
.D(FE_PHN35_n189),
.CK(clk__L2_N5));
DFFR_X1 \instruction_decode_reg[23] (.RN(n202),
.QN(n124),
.Q(instruction_decode[23]),
.D(FE_PHN13_n188),
.CK(clk__L2_N5));
DFFR_X1 \instruction_decode_reg[22] (.RN(n202),
.QN(n123),
.Q(instruction_decode[22]),
.D(FE_PHN31_n187),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[21] (.RN(n202),
.QN(n122),
.Q(instruction_decode[21]),
.D(FE_PHN32_n186),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[20] (.RN(n202),
.QN(n121),
.Q(instruction_decode[20]),
.D(FE_PHN37_n185),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[19] (.RN(n202),
.QN(n120),
.Q(instruction_decode[19]),
.D(FE_PHN43_n184),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[18] (.RN(n202),
.QN(n119),
.Q(instruction_decode[18]),
.D(FE_PHN42_n183),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[17] (.RN(n202),
.QN(n118),
.Q(instruction_decode[17]),
.D(FE_PHN30_n182),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[16] (.RN(n202),
.QN(n117),
.Q(instruction_decode[16]),
.D(FE_PHN33_n181),
.CK(clk__L2_N6));
DFFR_X1 \instruction_decode_reg[15] (.RN(n202),
.QN(n116),
.Q(instruction_decode[15]),
.D(n180),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[14] (.RN(n202),
.QN(n115),
.Q(instruction_decode[14]),
.D(FE_PHN34_n179),
.CK(clk__L2_N5));
DFFR_X1 \instruction_decode_reg[13] (.RN(n202),
.QN(n114),
.Q(instruction_decode[13]),
.D(n178),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[12] (.RN(n202),
.QN(n113),
.Q(instruction_decode[12]),
.D(n177),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[11] (.RN(n202),
.QN(n112),
.Q(instruction_decode[11]),
.D(n176),
.CK(clk__L2_N7));
DFFR_X1 \instruction_decode_reg[10] (.RN(n202),
.QN(n111),
.Q(instruction_decode[10]),
.D(FE_PHN38_n175),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[9] (.RN(n202),
.QN(n110),
.Q(instruction_decode[9]),
.D(FE_PHN29_n174),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[8] (.RN(n202),
.QN(n109),
.Q(instruction_decode[8]),
.D(n173),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[7] (.RN(n202),
.QN(n108),
.Q(instruction_decode[7]),
.D(n172),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[6] (.RN(n202),
.QN(n107),
.Q(instruction_decode[6]),
.D(n171),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[5] (.RN(n202),
.QN(n106),
.Q(instruction_decode[5]),
.D(n170),
.CK(clk__L2_N9));
DFFR_X1 \instruction_decode_reg[4] (.RN(n202),
.QN(n105),
.Q(instruction_decode[4]),
.D(n169),
.CK(clk__L2_N9));
DFFR_X1 \instruction_decode_reg[3] (.RN(n202),
.QN(n104),
.Q(instruction_decode[3]),
.D(n168),
.CK(clk__L2_N9));
DFFR_X1 \instruction_decode_reg[2] (.RN(n202),
.QN(n103),
.Q(instruction_decode[2]),
.D(n167),
.CK(clk__L2_N8));
DFFR_X1 \instruction_decode_reg[1] (.RN(n202),
.QN(n102),
.Q(instruction_decode[1]),
.D(n166),
.CK(clk__L2_N9));
DFFR_X1 \instruction_decode_reg[0] (.RN(n202),
.QN(n101),
.Q(instruction_decode[0]),
.D(n165),
.CK(clk__L2_N9));
DFFR_X1 \new_pc_reg[31] (.RN(n202),
.QN(n69),
.Q(new_pc[31]),
.D(n164),
.CK(clk__L2_N3));
DFFR_X1 \new_pc_reg[30] (.RN(n202),
.QN(n70),
.Q(new_pc[30]),
.D(n163),
.CK(clk__L2_N4));
DFFR_X1 \new_pc_reg[29] (.RN(n202),
.QN(n71),
.Q(new_pc[29]),
.D(n162),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[28] (.RN(n202),
.QN(n72),
.Q(new_pc[28]),
.D(n161),
.CK(clk__L2_N4));
DFFR_X1 \new_pc_reg[27] (.RN(n202),
.QN(n73),
.Q(new_pc[27]),
.D(n160),
.CK(clk__L2_N2));
DFFR_X1 \new_pc_reg[26] (.RN(n202),
.QN(n74),
.Q(new_pc[26]),
.D(n159),
.CK(clk__L2_N2));
DFFR_X1 \new_pc_reg[25] (.RN(n202),
.QN(n75),
.Q(new_pc[25]),
.D(n158),
.CK(clk__L2_N1));
DFFR_X1 \new_pc_reg[24] (.RN(n202),
.QN(n76),
.Q(new_pc[24]),
.D(n157),
.CK(clk__L2_N1));
DFFR_X1 \new_pc_reg[23] (.RN(n202),
.QN(n77),
.Q(new_pc[23]),
.D(n156),
.CK(clk));
DFFR_X1 \new_pc_reg[22] (.RN(n202),
.QN(n78),
.Q(new_pc[22]),
.D(n155),
.CK(clk));
DFFR_X1 \new_pc_reg[21] (.RN(n202),
.QN(n79),
.Q(new_pc[21]),
.D(n154),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[20] (.RN(n202),
.QN(n80),
.Q(new_pc[20]),
.D(n153),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[19] (.RN(n202),
.QN(n81),
.Q(new_pc[19]),
.D(n152),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[18] (.RN(n202),
.QN(n82),
.Q(new_pc[18]),
.D(n151),
.CK(clk__L2_N1));
DFFR_X1 \new_pc_reg[17] (.RN(n202),
.QN(n83),
.Q(new_pc[17]),
.D(n150),
.CK(clk));
DFFR_X1 \new_pc_reg[16] (.RN(n202),
.QN(n84),
.Q(new_pc[16]),
.D(n149),
.CK(clk));
DFFR_X1 \new_pc_reg[15] (.RN(n202),
.QN(n85),
.Q(new_pc[15]),
.D(n148),
.CK(clk));
DFFR_X1 \new_pc_reg[14] (.RN(n202),
.QN(n86),
.Q(new_pc[14]),
.D(n147),
.CK(clk__L2_N3));
DFFR_X1 \new_pc_reg[13] (.RN(n202),
.QN(n87),
.Q(new_pc[13]),
.D(n146),
.CK(clk__L2_N4));
DFFR_X1 \new_pc_reg[12] (.RN(n202),
.QN(n88),
.Q(new_pc[12]),
.D(n145),
.CK(clk__L2_N2));
DFFR_X1 \new_pc_reg[11] (.RN(n202),
.QN(n89),
.Q(new_pc[11]),
.D(n144),
.CK(clk__L2_N1));
DFFR_X1 \new_pc_reg[10] (.RN(n202),
.QN(n90),
.Q(new_pc[10]),
.D(n143),
.CK(clk));
DFFR_X1 \new_pc_reg[9] (.RN(n202),
.QN(n91),
.Q(new_pc[9]),
.D(n142),
.CK(clk__L2_N3));
DFFR_X1 \new_pc_reg[8] (.RN(n202),
.QN(n92),
.Q(new_pc[8]),
.D(n141),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[7] (.RN(n202),
.QN(n93),
.Q(new_pc[7]),
.D(n140),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[6] (.RN(n202),
.QN(n94),
.Q(new_pc[6]),
.D(n139),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[5] (.RN(n202),
.QN(n95),
.Q(new_pc[5]),
.D(n138),
.CK(clk__L2_N5));
DFFR_X1 \new_pc_reg[4] (.RN(n202),
.QN(n96),
.Q(new_pc[4]),
.D(n137),
.CK(clk));
DFFR_X1 \new_pc_reg[3] (.RN(n202),
.QN(n97),
.Q(new_pc[3]),
.D(n136),
.CK(clk));
DFFR_X1 \new_pc_reg[2] (.RN(n202),
.QN(n98),
.Q(new_pc[2]),
.D(n135),
.CK(clk__L2_N1));
DFFR_X1 \new_pc_reg[1] (.RN(n202),
.QN(n99),
.Q(new_pc[1]),
.D(n134),
.CK(clk));
DFFR_X1 \new_pc_reg[0] (.RN(n202),
.QN(n100),
.Q(new_pc[0]),
.D(n133),
.CK(clk));
NAND2_X1 U13 (.ZN(n65),
.A2(n64),
.A1(n67));
INV_X4 U14 (.ZN(n202),
.A(FE_PHN45_flush_i));
OAI22_X1 U15 (.ZN(n153),
.B2(n239),
.B1(FE_OFN7_n65),
.A2(n80),
.A1(n64));
INV_X1 U16 (.ZN(n239),
.A(pc_4[20]));
OAI22_X1 U17 (.ZN(n156),
.B2(n236),
.B1(FE_OFN7_n65),
.A2(n77),
.A1(n64));
INV_X1 U18 (.ZN(n236),
.A(pc_4[23]));
OAI22_X1 U19 (.ZN(n157),
.B2(n235),
.B1(FE_OFN7_n65),
.A2(n76),
.A1(n64));
INV_X1 U20 (.ZN(n235),
.A(pc_4[24]));
OAI22_X1 U21 (.ZN(n160),
.B2(n232),
.B1(FE_OFN7_n65),
.A2(n73),
.A1(n64));
INV_X1 U22 (.ZN(n232),
.A(pc_4[27]));
OAI22_X1 U23 (.ZN(n161),
.B2(n231),
.B1(FE_OFN7_n65),
.A2(n72),
.A1(n64));
INV_X1 U24 (.ZN(n231),
.A(pc_4[28]));
OAI22_X1 U25 (.ZN(n151),
.B2(n241),
.B1(FE_OFN7_n65),
.A2(n82),
.A1(n64));
INV_X1 U26 (.ZN(n241),
.A(pc_4[18]));
OAI22_X1 U27 (.ZN(n152),
.B2(n240),
.B1(FE_OFN7_n65),
.A2(n81),
.A1(n64));
INV_X1 U28 (.ZN(n240),
.A(pc_4[19]));
OAI22_X1 U29 (.ZN(n154),
.B2(n238),
.B1(FE_OFN7_n65),
.A2(n79),
.A1(n64));
INV_X1 U30 (.ZN(n238),
.A(pc_4[21]));
OAI22_X1 U31 (.ZN(n155),
.B2(n237),
.B1(FE_OFN7_n65),
.A2(n78),
.A1(n64));
INV_X1 U32 (.ZN(n237),
.A(pc_4[22]));
OAI22_X1 U33 (.ZN(n158),
.B2(n234),
.B1(FE_OFN7_n65),
.A2(n75),
.A1(n64));
INV_X1 U34 (.ZN(n234),
.A(pc_4[25]));
OAI22_X1 U35 (.ZN(n159),
.B2(n233),
.B1(FE_OFN7_n65),
.A2(n74),
.A1(n64));
INV_X1 U36 (.ZN(n233),
.A(pc_4[26]));
OAI22_X1 U37 (.ZN(n162),
.B2(n230),
.B1(FE_OFN7_n65),
.A2(n71),
.A1(n64));
INV_X1 U38 (.ZN(n230),
.A(pc_4[29]));
OAI22_X1 U39 (.ZN(n163),
.B2(n229),
.B1(FE_OFN7_n65),
.A2(n70),
.A1(n64));
INV_X1 U40 (.ZN(n229),
.A(pc_4[30]));
OAI22_X1 U41 (.ZN(n164),
.B2(n228),
.B1(FE_OFN7_n65),
.A2(n69),
.A1(n64));
INV_X1 U42 (.ZN(n228),
.A(pc_4[31]));
OAI22_X1 U43 (.ZN(n133),
.B2(n259),
.B1(FE_OFN7_n65),
.A2(n100),
.A1(n64));
INV_X1 U44 (.ZN(n259),
.A(pc_4[0]));
OAI22_X1 U45 (.ZN(n134),
.B2(n258),
.B1(FE_OFN7_n65),
.A2(n99),
.A1(n64));
INV_X1 U46 (.ZN(n258),
.A(pc_4[1]));
OAI22_X1 U47 (.ZN(n135),
.B2(n257),
.B1(FE_OFN7_n65),
.A2(n98),
.A1(n64));
INV_X1 U48 (.ZN(n257),
.A(pc_4[2]));
OAI22_X1 U49 (.ZN(n136),
.B2(n256),
.B1(FE_OFN7_n65),
.A2(n97),
.A1(n64));
INV_X1 U50 (.ZN(n256),
.A(pc_4[3]));
OAI22_X1 U51 (.ZN(n137),
.B2(n255),
.B1(FE_OFN7_n65),
.A2(n96),
.A1(n64));
INV_X1 U52 (.ZN(n255),
.A(pc_4[4]));
OAI22_X1 U53 (.ZN(n138),
.B2(n254),
.B1(FE_OFN7_n65),
.A2(n95),
.A1(n64));
INV_X1 U54 (.ZN(n254),
.A(pc_4[5]));
OAI22_X1 U55 (.ZN(n145),
.B2(n247),
.B1(FE_OFN7_n65),
.A2(n88),
.A1(n64));
INV_X1 U56 (.ZN(n247),
.A(pc_4[12]));
OAI22_X1 U57 (.ZN(n146),
.B2(n246),
.B1(FE_OFN7_n65),
.A2(n87),
.A1(n64));
INV_X1 U58 (.ZN(n246),
.A(pc_4[13]));
OAI22_X1 U59 (.ZN(n147),
.B2(n245),
.B1(FE_OFN7_n65),
.A2(n86),
.A1(n64));
INV_X1 U60 (.ZN(n245),
.A(pc_4[14]));
OAI22_X1 U61 (.ZN(n148),
.B2(n244),
.B1(FE_OFN7_n65),
.A2(n85),
.A1(n64));
INV_X1 U62 (.ZN(n244),
.A(pc_4[15]));
OAI22_X1 U63 (.ZN(n149),
.B2(n243),
.B1(FE_OFN7_n65),
.A2(n84),
.A1(n64));
INV_X1 U64 (.ZN(n243),
.A(pc_4[16]));
OAI22_X1 U65 (.ZN(n165),
.B2(n227),
.B1(n65),
.A2(n64),
.A1(n101));
INV_X1 U66 (.ZN(n227),
.A(instruction_fetch[0]));
OAI22_X1 U67 (.ZN(n166),
.B2(n226),
.B1(n65),
.A2(n64),
.A1(n102));
INV_X1 U68 (.ZN(n226),
.A(instruction_fetch[1]));
OAI22_X1 U69 (.ZN(n167),
.B2(n225),
.B1(n65),
.A2(n64),
.A1(n103));
INV_X1 U70 (.ZN(n225),
.A(instruction_fetch[2]));
OAI22_X1 U71 (.ZN(n168),
.B2(n224),
.B1(n65),
.A2(n64),
.A1(n104));
INV_X1 U72 (.ZN(n224),
.A(instruction_fetch[3]));
OAI22_X1 U73 (.ZN(n169),
.B2(n223),
.B1(n65),
.A2(n64),
.A1(n105));
INV_X1 U74 (.ZN(n223),
.A(instruction_fetch[4]));
OAI22_X1 U75 (.ZN(n170),
.B2(n222),
.B1(n65),
.A2(n64),
.A1(n106));
INV_X1 U76 (.ZN(n222),
.A(instruction_fetch[5]));
OAI22_X1 U77 (.ZN(n171),
.B2(n221),
.B1(n65),
.A2(n64),
.A1(n107));
INV_X1 U78 (.ZN(n221),
.A(instruction_fetch[6]));
OAI22_X1 U79 (.ZN(n172),
.B2(n220),
.B1(n65),
.A2(n64),
.A1(n108));
INV_X1 U80 (.ZN(n220),
.A(instruction_fetch[7]));
OAI22_X1 U81 (.ZN(n173),
.B2(n219),
.B1(n65),
.A2(n64),
.A1(n109));
INV_X1 U82 (.ZN(n219),
.A(instruction_fetch[8]));
OAI22_X1 U83 (.ZN(n174),
.B2(n218),
.B1(n65),
.A2(n64),
.A1(n110));
INV_X1 U84 (.ZN(n218),
.A(instruction_fetch[9]));
OAI22_X1 U85 (.ZN(n175),
.B2(n217),
.B1(n65),
.A2(n64),
.A1(n111));
INV_X1 U86 (.ZN(n217),
.A(instruction_fetch[10]));
OAI22_X1 U87 (.ZN(n176),
.B2(n216),
.B1(n65),
.A2(n64),
.A1(n112));
INV_X1 U88 (.ZN(n216),
.A(instruction_fetch[11]));
OAI22_X1 U89 (.ZN(n177),
.B2(n215),
.B1(n65),
.A2(n64),
.A1(n113));
INV_X1 U90 (.ZN(n215),
.A(instruction_fetch[12]));
OAI22_X1 U91 (.ZN(n178),
.B2(n214),
.B1(n65),
.A2(n64),
.A1(n114));
INV_X1 U92 (.ZN(n214),
.A(instruction_fetch[13]));
OAI22_X1 U93 (.ZN(n179),
.B2(n213),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n115));
INV_X1 U94 (.ZN(n213),
.A(instruction_fetch[14]));
OAI22_X1 U95 (.ZN(n180),
.B2(n212),
.B1(n65),
.A2(n64),
.A1(n116));
INV_X1 U96 (.ZN(n212),
.A(instruction_fetch[15]));
OAI22_X1 U97 (.ZN(n181),
.B2(n211),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n117));
INV_X1 U98 (.ZN(n211),
.A(instruction_fetch[16]));
OAI22_X1 U99 (.ZN(n182),
.B2(n210),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n118));
INV_X1 U100 (.ZN(n210),
.A(instruction_fetch[17]));
OAI22_X1 U101 (.ZN(n183),
.B2(n209),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n119));
INV_X1 U102 (.ZN(n209),
.A(instruction_fetch[18]));
OAI22_X1 U103 (.ZN(n184),
.B2(n208),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n120));
INV_X1 U104 (.ZN(n208),
.A(instruction_fetch[19]));
OAI22_X1 U105 (.ZN(n185),
.B2(n207),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n121));
INV_X1 U106 (.ZN(n207),
.A(instruction_fetch[20]));
OAI22_X1 U107 (.ZN(n186),
.B2(n206),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n122));
INV_X1 U108 (.ZN(n206),
.A(instruction_fetch[21]));
OAI22_X1 U109 (.ZN(n187),
.B2(n205),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n123));
INV_X1 U110 (.ZN(n205),
.A(instruction_fetch[22]));
OAI22_X1 U111 (.ZN(n188),
.B2(n204),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n124));
INV_X1 U112 (.ZN(n204),
.A(instruction_fetch[23]));
OAI22_X1 U113 (.ZN(n189),
.B2(n203),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n125));
INV_X1 U114 (.ZN(n203),
.A(instruction_fetch[24]));
OAI22_X1 U115 (.ZN(n190),
.B2(n201),
.B1(FE_OFN7_n65),
.A2(n64),
.A1(n126));
INV_X1 U116 (.ZN(n201),
.A(instruction_fetch[25]));
OAI22_X1 U117 (.ZN(n192),
.B2(n199),
.B1(n65),
.A2(n64),
.A1(n128));
INV_X1 U118 (.ZN(n199),
.A(instruction_fetch[27]));
OAI22_X1 U119 (.ZN(n194),
.B2(n196),
.B1(n65),
.A2(n64),
.A1(n130));
INV_X1 U120 (.ZN(n196),
.A(instruction_fetch[29]));
OAI22_X1 U121 (.ZN(n139),
.B2(n253),
.B1(FE_OFN7_n65),
.A2(n94),
.A1(n64));
INV_X1 U122 (.ZN(n253),
.A(pc_4[6]));
OAI22_X1 U123 (.ZN(n140),
.B2(n252),
.B1(FE_OFN7_n65),
.A2(n93),
.A1(n64));
INV_X1 U124 (.ZN(n252),
.A(pc_4[7]));
OAI22_X1 U125 (.ZN(n141),
.B2(n251),
.B1(FE_OFN7_n65),
.A2(n92),
.A1(n64));
INV_X1 U126 (.ZN(n251),
.A(pc_4[8]));
OAI22_X1 U127 (.ZN(n142),
.B2(n250),
.B1(FE_OFN7_n65),
.A2(n91),
.A1(n64));
INV_X1 U128 (.ZN(n250),
.A(pc_4[9]));
OAI22_X1 U129 (.ZN(n143),
.B2(n249),
.B1(FE_OFN7_n65),
.A2(n90),
.A1(n64));
INV_X1 U130 (.ZN(n249),
.A(pc_4[10]));
OAI22_X1 U131 (.ZN(n144),
.B2(n248),
.B1(FE_OFN7_n65),
.A2(n89),
.A1(n64));
INV_X1 U132 (.ZN(n248),
.A(pc_4[11]));
OAI211_X1 U133 (.ZN(n191),
.C2(n64),
.C1(n127),
.B(n200),
.A(n67));
NAND2_X1 U134 (.ZN(n200),
.A2(n64),
.A1(instruction_fetch[26]));
OAI211_X1 U135 (.ZN(n193),
.C2(n64),
.C1(n129),
.B(n198),
.A(n67));
NAND2_X1 U136 (.ZN(n198),
.A2(n64),
.A1(instruction_fetch[28]));
OAI211_X1 U137 (.ZN(n195),
.C2(n64),
.C1(n131),
.B(n68),
.A(n67));
NAND2_X1 U138 (.ZN(n68),
.A2(n64),
.A1(instruction_fetch[30]));
INV_X1 U139 (.ZN(n67),
.A(rst));
OR2_X4 U140 (.ZN(n64),
.A2(rst),
.A1(ifid_write));
OAI22_X1 U141 (.ZN(n197),
.B2(n66),
.B1(n65),
.A2(n64),
.A1(n132));
INV_X1 U142 (.ZN(n66),
.A(instruction_fetch[31]));
OAI22_X1 U143 (.ZN(n150),
.B2(n242),
.B1(FE_OFN7_n65),
.A2(n83),
.A1(n64));
INV_X1 U144 (.ZN(n242),
.A(pc_4[17]));
endmodule
module fetch (
jump_address,
branch_target,
from_iram,
flush,
clk,
rst,
pcsrc,
jump,
pcwrite,
to_iram,
pc_4,
instruction_fetch,
clk__L2_N1,
clk__L2_N2,
clk__L2_N3,
clk__L2_N4);
input [31:0] jump_address;
input [31:0] branch_target;
input [31:0] from_iram;
input flush;
input clk;
input rst;
input pcsrc;
input jump;
input pcwrite;
output [31:0] to_iram;
output [31:0] pc_4;
output [31:0] instruction_fetch;
input clk__L2_N1;
input clk__L2_N2;
input clk__L2_N3;
input clk__L2_N4;
// Internal wires
wire [31:0] data_mux_branch_i;
wire [31:0] data_mux_jump_i;
wire [31:0] data_pc_i;
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
assign to_iram[31] = 1'b0 ;
assign to_iram[30] = 1'b0 ;
mux_branch mux_branch1 (.from_increment_pc(pc_4),
.branch_target(branch_target),
.pcsrc(pcsrc),
.to_mux_jump(data_mux_branch_i));
mux_jump mux_jump1 (.jump_address(jump_address),
.from_mux_branch(data_mux_branch_i),
.jump(jump),
.to_pc(data_mux_jump_i));
pc pc1 (.from_mux_jump(data_mux_jump_i),
.pcwrite(pcwrite),
.clk(clk),
.rst(rst),
.to_iram_block(data_pc_i),
.clk__L2_N1(clk__L2_N1),
.clk__L2_N2(clk__L2_N2),
.clk__L2_N3(clk__L2_N3),
.clk__L2_N4(clk__L2_N4));
increment_pc inc_pc1 (.from_pc(data_pc_i),
.to_mux_branch(pc_4));
iram_block iram_block1 (.from_pc(data_pc_i),
.flush(flush),
.from_iram(from_iram),
.to_iram({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
to_iram[29],
to_iram[28],
to_iram[27],
to_iram[26],
to_iram[25],
to_iram[24],
to_iram[23],
to_iram[22],
to_iram[21],
to_iram[20],
to_iram[19],
to_iram[18],
to_iram[17],
to_iram[16],
to_iram[15],
to_iram[14],
to_iram[13],
to_iram[12],
to_iram[11],
to_iram[10],
to_iram[9],
to_iram[8],
to_iram[7],
to_iram[6],
to_iram[5],
to_iram[4],
to_iram[3],
to_iram[2],
to_iram[1],
to_iram[0] }),
.to_if_id_reg(instruction_fetch));
endmodule
module DataPath (
clk,
rst,
fromIRAM,
cw,
Data_out_fromRAM,
opcode,
func,
Addr,
read_op,
write_op,
nibble,
write_byte,
Address_toRAM,
Data_in,
clk__L2_N1,
clk__L2_N10,
clk__L2_N11,
clk__L2_N12,
clk__L2_N2,
clk__L2_N3,
clk__L2_N4,
clk__L2_N5,
clk__L2_N6,
clk__L2_N7,
clk__L2_N8,
clk__L2_N9);
input clk;
input rst;
input [31:0] fromIRAM;
input [22:0] cw;
input [31:0] Data_out_fromRAM;
output [5:0] opcode;
output [10:0] func;
output [31:0] Addr;
output read_op;
output write_op;
output [1:0] nibble;
output write_byte;
output [31:0] Address_toRAM;
output [31:0] Data_in;
input clk__L2_N1;
input clk__L2_N10;
input clk__L2_N11;
input clk__L2_N12;
input clk__L2_N2;
input clk__L2_N3;
input clk__L2_N4;
input clk__L2_N5;
input clk__L2_N6;
input clk__L2_N7;
input clk__L2_N8;
input clk__L2_N9;
// Internal wires
wire FE_UNCONNECTED_0;
wire flush_i;
wire pcsrc_i;
wire jump_i;
wire pcwrite_i;
wire ifid_write_i;
wire reg_write_i;
wire regwriteMEM_i;
wire branchTaken_i;
wire takeBranch_out_i;
wire [31:0] jump_address_i;
wire [31:0] branch_target_i;
wire [31:0] pc_4_i;
wire [31:0] instruction_fetch_i;
wire [31:0] instruction_decode_i;
wire [31:0] new_pc_i;
wire [4:0] address_write_i;
wire [31:0] data_write_i;
wire [4:0] idex_rt_i;
wire [3:0] idex_mem_read_i;
wire [21:0] cw_to_idex_i;
wire [31:0] jaddr_i;
wire [31:0] pc4_to_idexreg_i;
wire [31:0] data_read_dec_1_i;
wire [31:0] data_read_dec_2_i;
wire [31:0] immediate_ext_dec_i;
wire [15:0] immediate_dec_i;
wire [4:0] rt_dec_i;
wire [4:0] rd_dec_i;
wire [4:0] rs_dec_i;
wire [21:0] cw_to_ex_i;
wire [31:0] jump_address_toex_i;
wire [31:0] pc_4_to_ex_i;
wire [31:0] data_read_ex_1_i;
wire [31:0] data_read_ex_2_i;
wire [31:0] immediate_ext_ex_i;
wire [15:0] immediate_ex_i;
wire [4:0] rt_ex_i;
wire [4:0] rd_ex_i;
wire [4:0] rs_ex_i;
wire [31:0] forw_dataMEM_i;
wire [4:0] RFaddr_MEM_i;
wire [10:0] cw_exmem_i;
wire [31:0] toPC1_i;
wire [31:0] toPC2_i;
wire [31:0] addrMem_exmem_i;
wire [31:0] writeData_exmem_i;
wire [4:0] addrRF_exmem_i;
wire [10:0] cw_tomem_i;
wire [31:0] PC1_tomem_i;
wire [31:0] PC2_tomem_i;
wire [31:0] mem_addr_out_i;
wire [31:0] mem_writedata_out_i;
wire [4:0] regfile_addr_out_tomem_i;
wire [2:0] cw_memwb_i;
wire [31:0] dataOut_mem_i;
wire [31:0] dataOut_exe_i;
wire [4:0] RFaddr_out_memwb_i;
wire [2:0] cw_towb_i;
wire [31:0] from_mem_data_out_i;
wire [31:0] from_alu_data_out_i;
wire [4:0] regfile_addr_out_towb_i;
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
wire SYNOPSYS_UNCONNECTED__2;
wire SYNOPSYS_UNCONNECTED__3;
assign Addr[31] = 1'b0 ;
assign Addr[30] = 1'b0 ;
assign Address_toRAM[31] = 1'b0 ;
assign Address_toRAM[30] = 1'b0 ;
fetch u_fetch (.jump_address(jump_address_i),
.branch_target(branch_target_i),
.from_iram(fromIRAM),
.flush(flush_i),
.clk(clk),
.rst(rst),
.pcsrc(pcsrc_i),
.jump(jump_i),
.pcwrite(pcwrite_i),
.to_iram({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
Addr[29],
Addr[28],
Addr[27],
Addr[26],
Addr[25],
Addr[24],
Addr[23],
Addr[22],
Addr[21],
Addr[20],
Addr[19],
Addr[18],
Addr[17],
Addr[16],
Addr[15],
Addr[14],
Addr[13],
Addr[12],
Addr[11],
Addr[10],
Addr[9],
Addr[8],
Addr[7],
Addr[6],
Addr[5],
Addr[4],
Addr[3],
Addr[2],
Addr[1],
Addr[0] }),
.pc_4(pc_4_i),
.instruction_fetch(instruction_fetch_i),
.clk__L2_N1(clk__L2_N1),
.clk__L2_N2(clk__L2_N2),
.clk__L2_N3(clk__L2_N3),
.clk__L2_N4(clk__L2_N4));
ifid_reg u_ifidreg (.pc_4(pc_4_i),
.instruction_fetch(instruction_fetch_i),
.flush(flush_i),
.ifid_write(ifid_write_i),
.clk(clk),
.rst(rst),
.instruction_decode(instruction_decode_i),
.new_pc(new_pc_i),
.clk__L2_N1(clk__L2_N1),
.clk__L2_N2(clk__L2_N2),
.clk__L2_N3(clk__L2_N3),
.clk__L2_N4(clk__L2_N4),
.clk__L2_N5(clk__L2_N5),
.clk__L2_N6(clk__L2_N6),
.clk__L2_N7(clk__L2_N7),
.clk__L2_N8(clk__L2_N8),
.clk__L2_N9(clk__L2_N9));
decode_unit u_decode_unit (.address_write(address_write_i),
.data_write(data_write_i),
.pc_4_from_dec(new_pc_i),
.instruction(instruction_decode_i),
.idex_rt(idex_rt_i),
.clk(clk__L2_N6),
.rst(rst),
.reg_write(reg_write_i),
.idex_mem_read(idex_mem_read_i),
.cw(cw),
.cw_to_ex(cw_to_idex_i),
.jump_address(jaddr_i),
.pc_4_to_ex(pc4_to_idexreg_i),
.data_read_1(data_read_dec_1_i),
.data_read_2(data_read_dec_2_i),
.immediate_ext(immediate_ext_dec_i),
.immediate(immediate_dec_i),
.rt(rt_dec_i),
.rd(rd_dec_i),
.rs(rs_dec_i),
.opcode(opcode),
.func(func),
.pcwrite(pcwrite_i),
.ifid_write(ifid_write_i));
idex_reg u_idexreg (.cw_to_ex_dec(cw_to_idex_i),
.jump_address_dec(jaddr_i),
.pc_4_dec(pc4_to_idexreg_i),
.read_data_1_dec(data_read_dec_1_i),
.read_data_2_dec(data_read_dec_2_i),
.immediate_ext_dec(immediate_ext_dec_i),
.immediate_dec(immediate_dec_i),
.rt_dec(rt_dec_i),
.rd_dec(rd_dec_i),
.rs_dec(rs_dec_i),
.clk(clk__L2_N10),
.rst(rst),
.cw_to_ex(cw_to_ex_i),
.jump_address(jump_address_toex_i),
.pc_4(pc_4_to_ex_i),
.read_data_1(data_read_ex_1_i),
.read_data_2(data_read_ex_2_i),
.immediate_ext(immediate_ext_ex_i),
.immediate(immediate_ex_i),
.rt(rt_ex_i),
.rd(rd_ex_i),
.rs(rs_ex_i),
.clk__L2_N5(clk__L2_N5),
.clk__L2_N6(clk__L2_N6),
.clk__L2_N7(clk__L2_N7),
.clk__L2_N8(clk__L2_N8),
.clk__L2_N9(clk__L2_N9));
execute u_execute (.clk(clk),
.rst(rst),
.controls_in(cw_to_ex_i),
.ext25_0(jump_address_toex_i),
.nextPC(pc_4_to_ex_i),
.op_A(data_read_ex_1_i),
.op_B(data_read_ex_2_i),
.ext15_0(immediate_ext_ex_i),
.inst15_0(immediate_ex_i),
.rt_inst(rt_ex_i),
.rd_inst(rd_ex_i),
.rs_inst(rs_ex_i),
.unaligned(FE_UNCONNECTED_0),
.forw_dataWB(data_write_i),
.forw_dataMEM(forw_dataMEM_i),
.RFaddr_WB(address_write_i),
.RFaddr_MEM(RFaddr_MEM_i),
.regwriteWB(reg_write_i),
.regwriteMEM(regwriteMEM_i),
.controls_out(cw_exmem_i),
.toPC1(toPC1_i),
.toPC2(toPC2_i),
.branchTaken(branchTaken_i),
.addrMem(addrMem_exmem_i),
.writeData(writeData_exmem_i),
.addrRF(addrRF_exmem_i),
.IDEX_rt(idex_rt_i),
.IDEX_memread(idex_mem_read_i));
EX_MEM_Reg u_exmemreg (.clk(clk),
.rst(rst),
.controls_in(cw_exmem_i),
.toPC1_in(toPC1_i),
.toPC2_in(toPC2_i),
.takeBranch_in(branchTaken_i),
.mem_addr_in(addrMem_exmem_i),
.mem_writedata_in(writeData_exmem_i),
.regfile_addr_in(addrRF_exmem_i),
.controls_out(cw_tomem_i),
.toPC1_out(PC1_tomem_i),
.toPC2_out(PC2_tomem_i),
.takeBranch_out(takeBranch_out_i),
.mem_addr_out(mem_addr_out_i),
.mem_writedata_out(mem_writedata_out_i),
.regfile_addr_out(regfile_addr_out_tomem_i),
.clk__L2_N1(clk__L2_N1),
.clk__L2_N10(clk__L2_N10),
.clk__L2_N11(clk__L2_N11),
.clk__L2_N12(clk__L2_N12),
.clk__L2_N2(clk__L2_N2),
.clk__L2_N3(clk__L2_N3),
.clk__L2_N4(clk__L2_N4),
.clk__L2_N5(clk__L2_N5),
.clk__L2_N6(clk__L2_N6),
.clk__L2_N7(clk__L2_N7),
.clk__L2_N9(clk__L2_N9));
memory u_memory (.controls_in(cw_tomem_i),
.PC1_in(PC1_tomem_i),
.PC2_in(PC2_tomem_i),
.takeBranch(takeBranch_out_i),
.addrMem(mem_addr_out_i),
.writeData(mem_writedata_out_i),
.RFaddr_in(regfile_addr_out_tomem_i),
.Data_out_fromRAM(Data_out_fromRAM),
.controls_out(cw_memwb_i),
.dataOut_mem(dataOut_mem_i),
.dataOut_exe(dataOut_exe_i),
.RFaddr_out(RFaddr_out_memwb_i),
.unaligned(FE_UNCONNECTED_0),
.PCsrc(pcsrc_i),
.flush(flush_i),
.jump(jump_i),
.PC1_out(jump_address_i),
.PC2_out(branch_target_i),
.regwrite_MEM(regwriteMEM_i),
.RFaddr_MEM(RFaddr_MEM_i),
.forw_addr_MEM(forw_dataMEM_i),
.read_op(read_op),
.write_op(write_op),
.nibble(nibble),
.write_byte(write_byte),
.Address_toRAM({ SYNOPSYS_UNCONNECTED__2,
SYNOPSYS_UNCONNECTED__3,
Address_toRAM[29],
Address_toRAM[28],
Address_toRAM[27],
Address_toRAM[26],
Address_toRAM[25],
Address_toRAM[24],
Address_toRAM[23],
Address_toRAM[22],
Address_toRAM[21],
Address_toRAM[20],
Address_toRAM[19],
Address_toRAM[18],
Address_toRAM[17],
Address_toRAM[16],
Address_toRAM[15],
Address_toRAM[14],
Address_toRAM[13],
Address_toRAM[12],
Address_toRAM[11],
Address_toRAM[10],
Address_toRAM[9],
Address_toRAM[8],
Address_toRAM[7],
Address_toRAM[6],
Address_toRAM[5],
Address_toRAM[4],
Address_toRAM[3],
Address_toRAM[2],
Address_toRAM[1],
Address_toRAM[0] }),
.Data_in(Data_in));
MEM_WB_Reg u_memwbreg (.clk(clk__L2_N6),
.rst(rst),
.controls_in(cw_memwb_i),
.from_mem_data_in(dataOut_mem_i),
.from_alu_data_in(dataOut_exe_i),
.regfile_addr_in(RFaddr_out_memwb_i),
.controls_out(cw_towb_i),
.from_mem_data_out(from_mem_data_out_i),
.from_alu_data_out(from_alu_data_out_i),
.regfile_addr_out(regfile_addr_out_towb_i));
writeback u_writeback (.from_mem_data(from_mem_data_out_i),
.from_alu_data(from_alu_data_out_i),
.regfile_addr_in(regfile_addr_out_towb_i),
.regwrite_in(cw_towb_i[2]),
.link(cw_towb_i[1]),
.memtoreg(cw_towb_i[0]),
.regwrite_out(reg_write_i),
.regfile_data(data_write_i),
.regfile_addr_out(address_write_i));
endmodule
module cu (
opcode,
func,
cw);
input [5:0] opcode;
input [10:0] func;
output [22:0] cw;
// Internal wires
wire n29;
wire n30;
wire n31;
wire n32;
wire n33;
wire n34;
wire n35;
wire n36;
wire n37;
wire n38;
wire n39;
wire n40;
wire n41;
wire n42;
wire n43;
wire n44;
wire n45;
wire n46;
wire n47;
wire n48;
wire n49;
wire n50;
wire n51;
wire n52;
wire n53;
wire n54;
wire n55;
wire n56;
wire n57;
wire n58;
wire n59;
wire n60;
wire n61;
wire n62;
wire n63;
wire n64;
wire n65;
wire n66;
wire n67;
wire n68;
wire n69;
wire n70;
wire n71;
wire n72;
wire n73;
wire n74;
wire n75;
wire n76;
wire n77;
wire n78;
wire n79;
wire n80;
wire n81;
wire n82;
wire n83;
wire n84;
wire n85;
wire n86;
wire n87;
wire n88;
wire n89;
wire n90;
wire n91;
wire n92;
wire n93;
wire n94;
wire n95;
wire n96;
wire n97;
wire n98;
wire n99;
wire n100;
wire n101;
wire n102;
wire n103;
wire n104;
wire n105;
wire n106;
wire n107;
wire n108;
wire n109;
wire n110;
wire n111;
wire n112;
wire n113;
wire n114;
wire n115;
wire n116;
wire n117;
wire n118;
wire n119;
wire n120;
wire n121;
wire n122;
wire n123;
wire n124;
wire n125;
wire n126;
wire n127;
NAND3_X1 U115 (.ZN(n36),
.A3(func[3]),
.A2(n40),
.A1(cw[16]));
NAND3_X1 U116 (.ZN(n35),
.A3(n46),
.A2(n45),
.A1(opcode[1]));
NAND3_X1 U117 (.ZN(cw[1]),
.A3(n83),
.A2(n82),
.A1(n81));
XOR2_X1 U118 (.Z(n117),
.B(n118),
.A(func[1]));
NAND3_X1 U119 (.ZN(n48),
.A3(n38),
.A2(n45),
.A1(opcode[4]));
NAND3_X1 U120 (.ZN(n32),
.A3(opcode[1]),
.A2(n45),
.A1(n30));
NAND3_X1 U121 (.ZN(n79),
.A3(opcode[1]),
.A2(n45),
.A1(opcode[0]));
NAND3_X1 U122 (.ZN(n42),
.A3(func[1]),
.A2(n43),
.A1(func[5]));
NAND3_X1 U123 (.ZN(n107),
.A3(n46),
.A2(n39),
.A1(opcode[0]));
NAND3_X1 U124 (.ZN(n56),
.A3(n59),
.A2(n118),
.A1(func[3]));
INV_X1 U3 (.ZN(n52),
.A(n76));
INV_X1 U4 (.ZN(n77),
.A(n101));
INV_X1 U5 (.ZN(n120),
.A(cw[16]));
INV_X1 U6 (.ZN(n80),
.A(n109));
INV_X1 U7 (.ZN(n33),
.A(cw[18]));
INV_X1 U8 (.ZN(n87),
.A(n98));
INV_X1 U9 (.ZN(n29),
.A(n110));
INV_X1 U10 (.ZN(n53),
.A(n90));
INV_X1 U11 (.ZN(n100),
.A(cw[12]));
NOR2_X1 U12 (.ZN(cw[16]),
.A2(n101),
.A1(n31));
NOR3_X1 U13 (.ZN(n73),
.A3(n42),
.A2(n120),
.A1(n60));
AOI211_X1 U14 (.ZN(n82),
.C2(n124),
.C1(cw[16]),
.B(n66),
.A(n47));
NAND4_X1 U15 (.ZN(n101),
.A4(n123),
.A3(n45),
.A2(n91),
.A1(n30));
OAI22_X1 U16 (.ZN(n92),
.B2(n94),
.B1(n80),
.A2(n108),
.A1(n79));
INV_X1 U17 (.ZN(n108),
.A(n46));
OAI22_X1 U18 (.ZN(cw[18]),
.B2(n31),
.B1(n93),
.A2(n80),
.A1(n79));
NOR2_X1 U19 (.ZN(n46),
.A2(n123),
.A1(n111));
NOR2_X1 U20 (.ZN(n110),
.A2(n62),
.A1(n78));
NAND2_X1 U21 (.ZN(n76),
.A2(n123),
.A1(n38));
INV_X1 U22 (.ZN(n38),
.A(n85));
NOR2_X1 U23 (.ZN(n109),
.A2(n31),
.A1(n123));
INV_X1 U24 (.ZN(n39),
.A(n119));
NAND2_X1 U25 (.ZN(n98),
.A2(n60),
.A1(cw[16]));
NOR2_X1 U26 (.ZN(cw[12]),
.A2(n93),
.A1(n111));
NAND2_X1 U27 (.ZN(n68),
.A2(n93),
.A1(n101));
NAND2_X1 U28 (.ZN(n50),
.A2(n41),
.A1(n73));
NAND2_X1 U29 (.ZN(n90),
.A2(n30),
.A1(n52));
INV_X1 U30 (.ZN(n124),
.A(n56));
OR3_X1 U31 (.ZN(cw[7]),
.A3(n110),
.A2(cw[8]),
.A1(cw[10]));
NAND4_X1 U32 (.ZN(cw[21]),
.A4(n107),
.A3(n106),
.A2(n105),
.A1(n104));
INV_X1 U33 (.ZN(n104),
.A(n92));
NAND2_X1 U34 (.ZN(n106),
.A2(n69),
.A1(n52));
AOI211_X1 U35 (.ZN(n74),
.C2(n38),
.C1(n39),
.B(n103),
.A(n102));
INV_X1 U36 (.ZN(n102),
.A(n48));
OR2_X1 U37 (.ZN(n103),
.A2(cw[21]),
.A1(cw[7]));
INV_X1 U38 (.ZN(n34),
.A(n47));
NAND4_X1 U39 (.ZN(cw[0]),
.A4(n113),
.A3(n112),
.A2(n105),
.A1(n82));
NOR4_X1 U40 (.ZN(n113),
.A4(n115),
.A3(n114),
.A2(n71),
.A1(n110));
AOI21_X1 U41 (.ZN(n81),
.B2(n91),
.B1(n71),
.A(n92));
OAI21_X1 U42 (.ZN(cw[6]),
.B2(n32),
.B1(n31),
.A(n33));
NOR2_X1 U43 (.ZN(cw[9]),
.A2(n30),
.A1(n29));
NOR2_X1 U44 (.ZN(cw[13]),
.A2(n111),
.A1(n101));
NOR3_X1 U45 (.ZN(cw[17]),
.A3(n76),
.A2(n30),
.A1(n94));
AOI21_X1 U46 (.ZN(cw[20]),
.B2(n32),
.B1(n79),
.A(n80));
NAND4_X1 U47 (.ZN(cw[22]),
.A4(n33),
.A3(n76),
.A2(n75),
.A1(n74));
NAND2_X1 U48 (.ZN(n75),
.A2(n78),
.A1(n77));
NOR4_X1 U49 (.ZN(n95),
.A4(func[1]),
.A3(n118),
.A2(n41),
.A1(n89));
OAI221_X1 U50 (.ZN(n66),
.C2(n76),
.C1(n79),
.B2(n120),
.B1(n125),
.A(n49));
AOI21_X1 U51 (.ZN(n125),
.B2(func[2]),
.B1(n124),
.A(n126));
NOR4_X1 U52 (.ZN(n126),
.A4(n42),
.A3(n118),
.A2(func[3]),
.A1(func[4]));
NOR4_X1 U53 (.ZN(n97),
.A4(func[6]),
.A3(func[7]),
.A2(func[8]),
.A1(func[9]));
INV_X1 U54 (.ZN(n30),
.A(opcode[0]));
AOI211_X1 U55 (.ZN(n64),
.C2(n45),
.C1(n52),
.B(n66),
.A(n65));
INV_X1 U56 (.ZN(n65),
.A(n67));
AOI22_X1 U57 (.ZN(n67),
.B2(n38),
.B1(n69),
.A2(opcode[5]),
.A1(n68));
NOR3_X1 U58 (.ZN(cw[8]),
.A3(n101),
.A2(opcode[3]),
.A1(n78));
NOR3_X1 U59 (.ZN(cw[10]),
.A3(n93),
.A2(opcode[3]),
.A1(n78));
NOR2_X1 U60 (.ZN(n71),
.A2(opcode[0]),
.A1(n48));
AOI22_X1 U61 (.ZN(n105),
.B2(n109),
.B1(n122),
.A2(n46),
.A1(n121));
INV_X1 U62 (.ZN(n121),
.A(n32));
OAI22_X1 U63 (.ZN(n122),
.B2(opcode[0]),
.B1(n119),
.A2(n30),
.A1(n94));
NOR3_X1 U64 (.ZN(n114),
.A3(n30),
.A2(opcode[1]),
.A1(n76));
INV_X1 U65 (.ZN(n41),
.A(func[4]));
NOR2_X1 U66 (.ZN(n59),
.A2(func[1]),
.A1(n61));
OAI22_X1 U67 (.ZN(n40),
.B2(n44),
.B1(n43),
.A2(n42),
.A1(n41));
NAND4_X1 U68 (.ZN(n49),
.A4(n30),
.A3(n39),
.A2(opcode[4]),
.A1(n38));
AOI22_X1 U69 (.ZN(n112),
.B2(n68),
.B1(opcode[5]),
.A2(n118),
.A1(n73));
NOR2_X1 U70 (.ZN(n69),
.A2(opcode[2]),
.A1(n30));
INV_X1 U71 (.ZN(n78),
.A(opcode[5]));
NAND2_X1 U72 (.ZN(n94),
.A2(opcode[2]),
.A1(opcode[1]));
INV_X1 U73 (.ZN(n118),
.A(func[0]));
AOI21_X1 U74 (.ZN(n115),
.B2(n116),
.B1(n44),
.A(n98));
NAND4_X1 U75 (.ZN(n116),
.A4(n89),
.A3(n41),
.A2(func[2]),
.A1(n117));
NAND2_X1 U76 (.ZN(n44),
.A2(func[0]),
.A1(n59));
NAND2_X1 U77 (.ZN(n111),
.A2(opcode[5]),
.A1(opcode[3]));
INV_X1 U78 (.ZN(n43),
.A(func[2]));
AOI21_X1 U79 (.ZN(n70),
.B2(n72),
.B1(n44),
.A(func[2]));
OR2_X1 U80 (.ZN(n72),
.A2(func[3]),
.A1(n61));
OAI211_X1 U81 (.ZN(n54),
.C2(n55),
.C1(n44),
.B(n57),
.A(n56));
NAND2_X1 U82 (.ZN(n55),
.A2(n43),
.A1(func[3]));
OAI211_X1 U83 (.ZN(n57),
.C2(n59),
.C1(n58),
.B(func[2]),
.A(n60));
NOR2_X1 U84 (.ZN(n58),
.A2(n61),
.A1(func[0]));
INV_X1 U85 (.ZN(n45),
.A(opcode[2]));
AOI221_X1 U86 (.ZN(n83),
.C2(opcode[1]),
.C1(n53),
.B2(func[0]),
.B1(n73),
.A(n84));
OAI21_X1 U87 (.ZN(n84),
.B2(n85),
.B1(n79),
.A(n86));
NAND4_X1 U88 (.ZN(n86),
.A4(n41),
.A3(n88),
.A2(func[1]),
.A1(n87));
OAI22_X1 U89 (.ZN(n88),
.B2(n89),
.B1(func[0]),
.A2(n43),
.A1(func[5]));
NAND4_X1 U90 (.ZN(n37),
.A4(n39),
.A3(opcode[0]),
.A2(opcode[4]),
.A1(n38));
INV_X1 U91 (.ZN(n123),
.A(opcode[4]));
OR2_X1 U92 (.ZN(n93),
.A2(opcode[4]),
.A1(n79));
OR2_X1 U93 (.ZN(n31),
.A2(opcode[5]),
.A1(opcode[3]));
NAND2_X1 U94 (.ZN(n85),
.A2(n78),
.A1(opcode[3]));
NAND2_X1 U95 (.ZN(n119),
.A2(n91),
.A1(opcode[2]));
NAND2_X1 U96 (.ZN(n61),
.A2(n41),
.A1(func[5]));
INV_X1 U97 (.ZN(n60),
.A(func[3]));
INV_X1 U98 (.ZN(n91),
.A(opcode[1]));
NOR2_X1 U99 (.ZN(cw[5]),
.A2(opcode[5]),
.A1(n62));
INV_X1 U100 (.ZN(n89),
.A(func[5]));
NAND2_X1 U101 (.ZN(n47),
.A2(n127),
.A1(n107));
NAND4_X1 U102 (.ZN(n127),
.A4(n95),
.A3(cw[16]),
.A2(func[2]),
.A1(func[3]));
OR3_X1 U103 (.ZN(n62),
.A3(n119),
.A2(opcode[4]),
.A1(opcode[3]));
NAND4_X1 U104 (.ZN(cw[2]),
.A4(n64),
.A3(n63),
.A2(n62),
.A1(n50));
AOI22_X1 U105 (.ZN(n63),
.B2(opcode[1]),
.B1(n71),
.A2(cw[16]),
.A1(n70));
NAND4_X1 U106 (.ZN(cw[3]),
.A4(n51),
.A3(n50),
.A2(n49),
.A1(n48));
AOI222_X1 U107 (.ZN(n51),
.C2(n54),
.C1(cw[16]),
.B2(opcode[2]),
.B1(n53),
.A2(n39),
.A1(n52));
NAND4_X1 U108 (.ZN(cw[4]),
.A4(n37),
.A3(n36),
.A2(n35),
.A1(n34));
NOR2_X1 U109 (.ZN(cw[11]),
.A2(n29),
.A1(opcode[0]));
NAND4_X1 U110 (.ZN(cw[14]),
.A4(n100),
.A3(n90),
.A2(n99),
.A1(n74));
NAND2_X1 U111 (.ZN(n99),
.A2(n77),
.A1(opcode[3]));
AND4_X1 U112 (.ZN(cw[15]),
.A4(n97),
.A3(n96),
.A2(n95),
.A1(n87));
NOR2_X1 U113 (.ZN(n96),
.A2(func[10]),
.A1(func[2]));
AND2_X1 U114 (.ZN(cw[19]),
.A2(cw[5]),
.A1(opcode[0]));
endmodule
module DLX (
clk,
rst,
iram_data,
Data_out_fromRAM,
addr_to_iram,
read_op,
write_op,
nibble,
write_byte,
Address_toRAM,
Data_in);
input clk;
input rst;
input [31:0] iram_data;
input [31:0] Data_out_fromRAM;
output [31:0] addr_to_iram;
output read_op;
output write_op;
output [1:0] nibble;
output write_byte;
output [31:0] Address_toRAM;
output [31:0] Data_in;
// Internal wires
wire clk__L2_N12;
wire clk__L2_N11;
wire clk__L2_N10;
wire clk__L2_N9;
wire clk__L2_N8;
wire clk__L2_N7;
wire clk__L2_N6;
wire clk__L2_N5;
wire clk__L2_N4;
wire clk__L2_N3;
wire clk__L2_N2;
wire clk__L2_N1;
wire clk__L2_N0;
wire clk__L1_N0;
wire [5:0] opcode_i;
wire [10:0] func_i;
wire [22:0] cw_i;
wire SYNOPSYS_UNCONNECTED__0;
wire SYNOPSYS_UNCONNECTED__1;
wire SYNOPSYS_UNCONNECTED__2;
wire SYNOPSYS_UNCONNECTED__3;
assign addr_to_iram[31] = 1'b0 ;
assign addr_to_iram[30] = 1'b0 ;
assign Address_toRAM[31] = 1'b0 ;
assign Address_toRAM[30] = 1'b0 ;
CLKBUF_X3 clk__L2_I12 (.Z(clk__L2_N12),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I11 (.Z(clk__L2_N11),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I10 (.Z(clk__L2_N10),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I9 (.Z(clk__L2_N9),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I8 (.Z(clk__L2_N8),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I7 (.Z(clk__L2_N7),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I6 (.Z(clk__L2_N6),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I5 (.Z(clk__L2_N5),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I4 (.Z(clk__L2_N4),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I3 (.Z(clk__L2_N3),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I2 (.Z(clk__L2_N2),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I1 (.Z(clk__L2_N1),
.A(clk__L1_N0));
CLKBUF_X3 clk__L2_I0 (.Z(clk__L2_N0),
.A(clk__L1_N0));
CLKBUF_X3 clk__L1_I0 (.Z(clk__L1_N0),
.A(clk));
cu u_cu (.opcode(opcode_i),
.func(func_i),
.cw(cw_i));
DataPath u_DataPath (.clk(clk__L2_N0),
.rst(rst),
.fromIRAM(iram_data),
.cw(cw_i),
.Data_out_fromRAM(Data_out_fromRAM),
.opcode(opcode_i),
.func(func_i),
.Addr({ SYNOPSYS_UNCONNECTED__0,
SYNOPSYS_UNCONNECTED__1,
addr_to_iram[29],
addr_to_iram[28],
addr_to_iram[27],
addr_to_iram[26],
addr_to_iram[25],
addr_to_iram[24],
addr_to_iram[23],
addr_to_iram[22],
addr_to_iram[21],
addr_to_iram[20],
addr_to_iram[19],
addr_to_iram[18],
addr_to_iram[17],
addr_to_iram[16],
addr_to_iram[15],
addr_to_iram[14],
addr_to_iram[13],
addr_to_iram[12],
addr_to_iram[11],
addr_to_iram[10],
addr_to_iram[9],
addr_to_iram[8],
addr_to_iram[7],
addr_to_iram[6],
addr_to_iram[5],
addr_to_iram[4],
addr_to_iram[3],
addr_to_iram[2],
addr_to_iram[1],
addr_to_iram[0] }),
.read_op(read_op),
.write_op(write_op),
.nibble(nibble),
.write_byte(write_byte),
.Address_toRAM({ SYNOPSYS_UNCONNECTED__2,
SYNOPSYS_UNCONNECTED__3,
Address_toRAM[29],
Address_toRAM[28],
Address_toRAM[27],
Address_toRAM[26],
Address_toRAM[25],
Address_toRAM[24],
Address_toRAM[23],
Address_toRAM[22],
Address_toRAM[21],
Address_toRAM[20],
Address_toRAM[19],
Address_toRAM[18],
Address_toRAM[17],
Address_toRAM[16],
Address_toRAM[15],
Address_toRAM[14],
Address_toRAM[13],
Address_toRAM[12],
Address_toRAM[11],
Address_toRAM[10],
Address_toRAM[9],
Address_toRAM[8],
Address_toRAM[7],
Address_toRAM[6],
Address_toRAM[5],
Address_toRAM[4],
Address_toRAM[3],
Address_toRAM[2],
Address_toRAM[1],
Address_toRAM[0] }),
.Data_in(Data_in),
.clk__L2_N1(clk__L2_N1),
.clk__L2_N10(clk__L2_N10),
.clk__L2_N11(clk__L2_N11),
.clk__L2_N12(clk__L2_N12),
.clk__L2_N2(clk__L2_N2),
.clk__L2_N3(clk__L2_N3),
.clk__L2_N4(clk__L2_N4),
.clk__L2_N5(clk__L2_N5),
.clk__L2_N6(clk__L2_N6),
.clk__L2_N7(clk__L2_N7),
.clk__L2_N8(clk__L2_N8),
.clk__L2_N9(clk__L2_N9));
endmodule
|
/*******************************************************************************
*
* FILENAME: B_DMA_UART_v0_1.v
* COMPONENT NAME: B_DMA_UART_v0_1
* Version `$CY_MAJOR_VERSION`.`$CY_MINOR_VERSION`
*
* Description:
* This file provides a top level model of the Base UART user module
* defining the controller and datapath instances and all of the necessary
* interconnect, for the RX and TX components individually. This allows
* for a lot of flexibility in how big the design can be and puts all of
* the code in a single file for easy maintenance.
*
********************************************************************************
* Control and Status Register definitions
********************************************************************************
* Control Register Definition
* +======+------+------+------+-------+-------+------+----------+--------+
* | Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* +======+------+------+------+-------+-------+------+----------+--------+
* | Desc |ADDRM2|ADDRM1|ADDRM0|PARITY1|PARITY0| MARK |SEND_BREAK| HD_SEND|
* +======+------+------+------+-------+-------+------+----------+--------+
*
* HD_SEND => Used for dynamically reconfiguration RX or TX operation in
* Half Duplex mode.
* 0 = RX operation HD mode
* 1 = TX operation HD mode
* SEND_BREAK => 1 = Sends Break signal in HD mode and release Parity bit
* for Break signal in TX mode.
* MARK => 0 = sets space(0) in Parity bit location.
* 1 = sets mark(1) in Parity bit location.
* PARITY0/1 => 0 = NONE
* 1 = EVEN
* 2 = ODD
* 3 = MRKSPC
* ADDRM0/1/2 => The RX address mode control is a 3-bit field used to define
* the expected hardware addressing operation.
* 0 = NONE
* 1 = SW_BYTE_BYTE
* 2 = SW_DET_BUFFER
* 3 = HW_BYTE_BYTE
* 4 = HW_DET_BUFFER
*
********************************************************************************
* TX Data Path register definitions
********************************************************************************
*
* INSTANCE NAME: dpTXShifter
*
* DESCRIPTION:
* Data Shifter for the TX portion of the UART.
*
* REGISTER USAGE:
* F0 => Data to be sent
* F1 => Unused
* D0 => Unused
* D1 => Unused
* A0 => Data as it is shifted out
* A1 => Unused
*
* Data Path States
* (0bit generated on Count7/DP clock divider, 1,2Bit from Sate Machine)
* 0 0 0 0 Idle
* 0 0 1 1 Idle
* 0 1 0 2 Idle
* 0 1 1 3 Send Start Bit (F0 -> A0)
* 1 0 0 4 Idle
* 1 0 1 5 Send Data Bits (A0>>)
* 1 1 0 6 Idle
* 1 1 1 7 Idle (Send Parity/Stop Bits)
*
********************************************************************************
*
* INSTANCE NAME: dpTXBitClkGen
*
* DESCRIPTION:
* Bit Enable Generator for the TX implemented on Data Path.
*
* REGISTER USAGE:
* F0 => Unused
* F1 => Unused
* D0 => Bit length
* D1 => Period
* A0 => Counter
* A1 => Unused
*
* Data Path States
* 0 0 0 0 Counter load (A0 = 0)
* 0 0 1 1 Count (A0++)
*
********************************************************************************
* TX 7-Bit Counter Implementation Description
********************************************************************************
*
* INSTANCE NAME: TXBitCounter
*
* DESCRIPTION:
* Bit Enable Generator and Bit Counter rolled into a 7-Bit Counter. Requires
* a period of the number of bits (+1 for the start bit) times the oversample
* rate of 8 or 16-bits. It is required to use 8 or 16-bit oversampling
* because the lower 3 or 4 bits of the counter are masked and compared to zero
* to generate the bit enable. Terminal count of the counter defines the end
* of a packet before Parity and Stop Bits are sent.
*
* REGISTER USAGE:
* PERIOD => ((NumBits + 1) * (OverSample Rate)) - 1
*
********************************************************************************
* RX Data Path register definitions
********************************************************************************
*
* INSTANCE NAME: dpRXShifter
*
* DESCRIPTION:
* Data Shifter for the RX portion of the UART. Half Duplex mode is
* implemented on this Data Path.
*
* REGISTER USAGE:
* F0 => Data just received
* F1 => Data to be sent(Half duplex send)
* D0 => Address 1
* D1 => Address 2
* A0 => Data as it is shifted in
* A1 => Data as it is shifted out (Half duplex send)
*
* Data Path States
* (0bit generated on RXBitCounter clock divider, 1,2Bit from Sate Machine)
* ADD 2 1 0 Bits cs_addr
* 0 0 0 0 X Idle
* RX Stages:
* 0 1 0 0 X Check Start
* 0 0 0 1 0 Idle
* 0 0 0 1 1 Get Data Bits (A0>>)
* 1 0 0 0 X Get Parity Bit
* 1 1 0 0 X Check Stop Bit (A0 -> F0)
* 0 1 1 1 X Check Break Signal (A1>> - does not take effect in RX mode)
* TX Stage for Half Duplex mode(HD_SEND = 1):
* 0 0 1 0 0 Idle
* 0 0 1 0 1 Send Start Bit (F1 -> A1)
* 0 0 1 1 0 Idle
* 0 0 1 1 1 Send Data Bits (A1>>)
* 1 0 0 0 X Send Parity Bit
* 0 1 1 1 X Send Stop 1 Bit
* 0 1 0 0 X Send Stop 2 Bit
*
********************************************************************************
* RX 7-Bit Counter Implementation Description
********************************************************************************
*
* INSTANCE NAME: RXBitCounter
*
* DESCRIPTION:
* Bit Enable Generator and Bit Counter rolled into a 7-Bit Counter.
*
* REGISTER USAGE:
*
********************************************************************************
* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
`include "cypress.v"
`ifdef B_DMA_UART_v0_1_V_ALREADY_INCLUDED
`else
`define B_DMA_UART_v0_1_V_ALREADY_INCLUDED
module B_DMA_UART_v0_1
(
input wire clock, /* User Supplied Clock = 8x or 16x the bit-rate depends on OverSampleCount parameter */
input wire reset, /* System Global Reset */
input wire rx, /* Receive: Serial Data Input */
output wire tx, /* Transmit: Serial Data Output */
output wire rx_interrupt, /* Interrupt output from the RX section */
output wire tx_interrupt, /* Interrupt output from the TX section */
output wire rx_drq, /* DMA request output */
output wire tx_drq, /* DMA request output */
output wire rx_break, /* Receive Break Signal output */
output wire tx_complete, /* Transmit Complete Signal output */
output wire rts_n, /* Request to send output for Flow control */
input wire cts_n, /* Clear to send input for Flow control */
output reg tx_en, /* Transmit Enable: Hardware control line output */
output reg tx_data, /* Transmit Data: shift out the TX data to a CRC component or other logic */
output reg tx_clk, /* Transmit Clock: Provides clock edge used to shift out the TX data */
output reg rx_data, /* Receive Data: shift out the RX data to a CRC component or other logic */
output reg rx_clk /* Receive Clock: Provides clock edge used to shift out the RX data */
);
/*************************************************************************
* Parameters *
*************************************************************************/
/* Constants for NumStopBits parameter */
localparam UART_NUM_STOP_BITS_1 = 2'd1;
localparam UART_NUM_STOP_BITS_2 = 2'd2;
/* Constants for OverSampleCount parameter */
localparam UART_OVER_SAMPLE_8 = 7'd8;
localparam UART_OVER_SAMPLE_16 = 7'd16;
/* Constants for ParityType parameter */
localparam UART_PARITY_TYPE_NONE = 2'd0;
localparam UART_PARITY_TYPE_EVEN = 2'd1;
localparam UART_PARITY_TYPE_ODD = 2'd2;
localparam UART_PARITY_TYPE_MRKSPC = 2'd3;
/* Constants for RXAddressMode parameter */
localparam UART_RX_ADDR_MODE_NONE = 3'd0;
localparam UART_RX_ADDR_MODE_SW_BYTE_BYTE = 3'd1;
localparam UART_RX_ADDR_MODE_SW_DET_BUFFER = 3'd2;
localparam UART_RX_ADDR_MODE_HW_BYTE_BYTE = 3'd3;
localparam UART_RX_ADDR_MODE_HW_DET_BUFFER = 3'd4;
localparam NUM_START_BITS = 4'd1; /* UART alwas uses one start bit */
localparam NUM_C7_MAX_BITS_O16 = 4'd8; /* max count for count7 at 16x oversample */
/* These parameters will set by the software */
parameter ParityType = UART_PARITY_TYPE_NONE; /* Set the Parity Type as Odd, Even or Mark/Space */
parameter ParityTypeSw = 1'b0; /* Makes Parity Type changeable by Control Register */
parameter FlowControl = 1'b0; /* Enable Flow Control Signals */
parameter HwTXEnSignal = 1'b0; /* Enable the external TX Enable Signal output */
parameter RXEnable = 1'b1; /* Enable RX portion of the UART */
parameter TXEnable = 1'b1; /* Enable TX portion of the UART */
parameter HalfDuplexEn = 1'b0; /* Enable Half Duplex mode: RX+TX portions on the RX only hardware */
parameter CRCoutputsEn = 1'b0; /* Enable CRC outputs */
parameter RXStatusIntEnable = 1'b0; /* Enable Interrupts from status register: not used */
parameter RXAddressMode = UART_RX_ADDR_MODE_NONE; /* Configure RX Hardware Address Detection Scheme */
parameter Address1 = 8'd0; /* RX Hardware Address #1 */
parameter Address2 = 8'd0; /* RX Hardware Address #2 */
parameter NumDataBits = 4'd8; /* Define the Number of Data Bits 5-9 */
parameter NumStopBits = UART_NUM_STOP_BITS_1; /* Define the Number of Stop Bits 1-2*/
parameter OverSampleCount = UART_OVER_SAMPLE_8; /* Allows Oversampling of 8 or 16 */
parameter Use23Polling = 1'b1; /* Use 2 of 3 polling on the RX UART sampler */
parameter TXBitClkGenDP = 1'b1; /* Use datapath for clock generation if enabled, otherwise Count7 */
parameter BreakDetect = 1'b0; /* Enable Break Signal generation and detection */
parameter BreakBitsTX = 7'd13; /* Set Break signal length in bits for TX */
parameter BreakBitsRX = 7'd13; /* Set Break signal length in bits for RX */
/* Polling require to start sampling on 1 bits before */
localparam [3:0] HalfBitCounts = ((OverSampleCount / 4'd2) + (Use23Polling * 4'd1) - 4'd2);
/* Truncating NumDataBits. UART shifts max 8 bits, Mark/Space functionality working if 9 bits selected */
localparam [3:0] FinalNumDataBits = (NumDataBits > 8) ? 4'd8 : NumDataBits;
/* TX Count7 period: calculated always for oversample 8, enable input used for oversample 16 */
localparam [6:0] txperiod_init = ((FinalNumDataBits + NUM_START_BITS) * UART_OVER_SAMPLE_8) - 7'd1;
/* Init RX counter for break detect time, rewritten @ HD mode by LoadRx(Tx) Cofig API */
/* This parameter is increased on the 2 in 2 out of 3 mode to sample voting in the middle */
localparam [6:0] rxperiod_init = (OverSampleCount == UART_OVER_SAMPLE_8) ?
((BreakBitsRX + NUM_START_BITS) * OverSampleCount) + (HalfBitCounts - 1) :
/* 7bit counter need one more bit for OverSampleCount=16 */
((NUM_C7_MAX_BITS_O16 - 1) * OverSampleCount) + (HalfBitCounts - 1);
/* need to use additional bit for count7 at 16x oversample*/
localparam rxperiod_cmp_need_one_bit = ((OverSampleCount == UART_OVER_SAMPLE_16) && (FinalNumDataBits > 6)) ?
1'd1 : 1'd0;
/* This parameter used in RX State machine to define that all predefined data bits received */
localparam [6:0] rxperiod_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ?
BreakBitsRX + NUM_START_BITS - FinalNumDataBits :
/* for 16 OverSample*/
rxperiod_cmp_need_one_bit ? (NUM_C7_MAX_BITS_O16 - 1) * 2 - FinalNumDataBits
: (NUM_C7_MAX_BITS_O16 - 1) - FinalNumDataBits;
/* This parameter used in RX State machine to define that all predefined break bits detected */
localparam [6:0] rxbreak_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? NUM_START_BITS :
/* Break at 16 OverSample always needs one more bit*/
(NUM_C7_MAX_BITS_O16 - 1) * 2 - BreakBitsRX + NUM_START_BITS;
/* This parameter used in TX State machine in HD mode to define that all predefined data bits received */
localparam [6:0] hd_txperiod_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? BreakBitsTX - FinalNumDataBits :
/* for 16 OverSample*/
rxperiod_cmp_need_one_bit ? NUM_C7_MAX_BITS_O16 * 2 - FinalNumDataBits - NUM_START_BITS
: NUM_C7_MAX_BITS_O16 - FinalNumDataBits - NUM_START_BITS;
/* This parameter used in TX State machine in HD mode to define that all predefined break bits detected */
localparam [6:0] hd_tx_break_cmp = (OverSampleCount == UART_OVER_SAMPLE_8) ? NUM_START_BITS :
/* Break at 16 OverSample always needs one more bit*/
NUM_C7_MAX_BITS_O16 * 2 - BreakBitsTX;
/* Counter low position for compare */
localparam cl = (OverSampleCount == UART_OVER_SAMPLE_8) ? 3'd3 : 3'd4;
/* Control Register bit locations */
localparam UART_CTRL_HD_SEND = 3'd0;
localparam UART_CTRL_HD_SEND_BREAK = 3'd1; /* HD_SEND_BREAK - sends break bits in HD mode*/
/* HD_SEND_BREAK - skip to send parity bit @ Break signal in Full Duplex mode*/
localparam UART_CTRL_MARK = 3'd2; /* 1 sets mark, 0 sets space */
localparam UART_CTRL_PARITYTYPE0 = 3'd3; /* Defines the type of parity implemented */
localparam UART_CTRL_PARITYTYPE1 = 3'd4; /* Defines the type of parity implemented */
localparam UART_CTRL_RXADDR_MODE0 = 3'd5;
localparam UART_CTRL_RXADDR_MODE1 = 3'd6;
localparam UART_CTRL_RXADDR_MODE2 = 3'd7;
localparam UART_RX_CTRL_ADDR_MODE_NONE = 3'd0;
localparam UART_RX_CTRL_ADDR_MODE_SW_BYTE_BYTE = 3'd1;
localparam UART_RX_CTRL_ADDR_MODE_SW_DET_BUFFER = 3'd2;
localparam UART_RX_CTRL_ADDR_MODE_HW_BYTE_BYTE = 3'd3;
localparam UART_RX_CTRL_ADDR_MODE_HW_DET_BUFFER = 3'd4;
/***************************************************************************
* Instantiation of udb_clock_enable primitive
****************************************************************************
* The udb_clock_enable primitive component allows to support clock enable
* mechanism and specify the intended synchronization behaviour for the clock
* result (operational clock).
* There is no need to reset or enable this component. In this case the
* udb_clock_enable is used only for synchronization. The resulted clock is
* always enabled.
*/
wire clock_op; /* internal clock to drive the component */
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync
(
/* input */ .clock_in(clock),
/* input */ .enable(1'b1),
/* output */ .clock_out(clock_op)
);
/**************************************************************************
* Control Register Implementation
**************************************************************************/
wire [7:0] control; /* UART Control Register */
generate
if( ((ParityType == UART_PARITY_TYPE_MRKSPC) && TXEnable) ||
((ParityType != UART_PARITY_TYPE_NONE) && TXEnable && BreakDetect) || ParityTypeSw ||
((RXAddressMode != UART_RX_ADDR_MODE_NONE) && RXEnable) || HalfDuplexEn )
begin : sCR_SyncCtl
cy_psoc3_control #(.cy_force_order(1), .cy_ctrl_mode_1(8'h0), .cy_ctrl_mode_0(8'hFF)) CtrlReg
(
/* input */ .clock(clock_op),
/* output [07:00] */ .control(control)
);
end /* sCR_SyncCtl */
endgenerate
/**************************************************************************/
/* Reset signal synchronization for Count7 usage */
/**************************************************************************/
reg reset_reg;
always @(posedge clock_op)
begin
reset_reg <= reset;
end
wire tx_hd_send_break =
((((ParityType != UART_PARITY_TYPE_NONE) || ParityTypeSw) && TXEnable && BreakDetect) || HalfDuplexEn) ?
control[UART_CTRL_HD_SEND_BREAK] : 1'b0;
wire HalfDuplexSend = HalfDuplexEn ? control[UART_CTRL_HD_SEND] : 1'b0;
wire [1:0] FinalParityType = ParityTypeSw ?
{control[UART_CTRL_PARITYTYPE1], control[UART_CTRL_PARITYTYPE0]} : ParityType;
wire [2:0] FinalAddrMode = (RXAddressMode != UART_RX_ADDR_MODE_NONE) ?
{control[UART_CTRL_RXADDR_MODE2], control[UART_CTRL_RXADDR_MODE1], control[UART_CTRL_RXADDR_MODE0]} :
RXAddressMode;
reg tx_mark;
reg tx_ctrl_mark_last;
wire tx_ctrl_mark = ((ParityType == UART_PARITY_TYPE_MRKSPC) || ParityTypeSw) ? control[UART_CTRL_MARK] : 1'b0;
/**************************************************************************/
/* Reset signal for DP and Status Register is available from ES3 silicon */
/* It is required to clear SR when direction changed in HD mode */
/**************************************************************************/
reg HalfDuplexSend_last;
wire reset_sr = (HalfDuplexSend ^ HalfDuplexSend_last) | reset_reg;
if(HalfDuplexEn)
begin
always @(posedge clock_op)
begin
HalfDuplexSend_last <= HalfDuplexSend;
end
end
/**************************************************************************
* txn is the inverted version of tx. The default output for a UART should
* be one. In order to get a one value out at time zero when all flip-flops
* are initialized to zero, txn is registered and then inverted when driven
* to the pin.
**************************************************************************/
reg txn;
assign tx = ~txn;
/* interrupts implementation */
wire tx_interrupt_out;
wire rx_interrupt_out;
assign tx_interrupt = TXEnable ? tx_interrupt_out : 1'b0;
assign rx_interrupt = (RXEnable || HalfDuplexEn) ? rx_interrupt_out : 1'b0;
/* DMA implementation */
wire tx_drq_out;
wire rx_drq_out;
assign tx_drq = TXEnable ? tx_drq_out : 1'b0;
assign rx_drq = (RXEnable || HalfDuplexEn) ? rx_drq_out : 1'b0;
/* Status Signal implementation */
wire tx_complete_out;
wire rx_break_out;
assign tx_complete = TXEnable ? tx_complete_out : 1'b0;
assign rx_break = (RXEnable || HalfDuplexEn) ? rx_break_out : 1'b0;
/**************************************************************************
* UART TX Implementation *
**************************************************************************/
generate
if (TXEnable == 1) begin : sTX
wire [6:0] tx_status; /* Transmit portion of the UART Status Register */
wire tx_fifo_empty; /* Transmitter FIFO Empty status line from FIFO -
used for flow control of data ready to send */
wire tx_fifo_notfull; /* Transmitter FIFO not full status line from FIFO -
Firmware should check the status bit FIFO_FULL before writing more data */
reg tx_parity_bit; /* Transmitter Parity Bit container (sent on TX during parity bit state) */
reg tx_bitclk; /* 1/8 or 1/16 of system clock */
wire tx_bitclk_dp;
wire tx_counter_tc; /* End of data shifting */
wire tx_counter_dp;
wire tx_bitclk_enable_pre; /* Transmitter Enable (1/8 or 1/16 system clock) used for cs_addr[0]*/
reg [2:0] tx_state; /* Transmit State Machine State Container */
/* TX State Machine States: */
localparam UART_TX_STATE_IDLE = 3'd0;
localparam UART_TX_STATE_SEND_START = 3'd1;
localparam UART_TX_STATE_SEND_DATA = 3'd2;
localparam UART_TX_STATE_SEND_PARITY = 3'd3;
localparam UART_TX_STATE_SEND_STOP1 = 3'd4;
localparam UART_TX_STATE_SEND_STOP2 = 3'd7;
localparam UART_TX_STATE_SEND_STOP = (NumStopBits == UART_NUM_STOP_BITS_1) ?
UART_TX_STATE_SEND_STOP1 : UART_TX_STATE_SEND_STOP2;
/* TX Shifter Datapath Configuration */
localparam UART_TX_SHIFTER_DP_CONFIG =
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: SEND START */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: SEND DATA (SR) */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: SEND LAST BIT(PARITY/STOP1/2) */
8'hFF, 8'h00, /*CFG9: */
8'hFF, 8'hFF, /*CFG11-10: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SR, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0_BUS,
`SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* TX Shifter Datapath */
cy_psoc3_dp8 #(.cy_dpconfig_a(UART_TX_SHIFTER_DP_CONFIG)) TxShifter
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({tx_state[1],tx_state[0],tx_bitclk_enable_pre}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(tx_shift_out),
/* output */ .f0_bus_stat(tx_fifo_notfull), /*FIFO is not full when bus_stat = 1;*/
/* output */ .f0_blk_stat(tx_fifo_empty), /*FIFO is empty when blk_stat = 1;*/
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
wire [6:0] txbitcount;
wire tx_bitclk_half;
wire tx_count7_enable;
reg clock2; /* 1/2 system clock for oversample*16 */
/* 8x or 16x clock divider implemented on Count7 */
if(TXBitClkGenDP == 0)
begin : sCLOCK
wire counter_load = (tx_state == UART_TX_STATE_IDLE) || (tx_bitclk && (tx_state == UART_TX_STATE_SEND_STOP));
if( (OverSampleCount == UART_OVER_SAMPLE_16) )
begin
/* Count7 enable implementation to work on 1/2 system clock */
always @(posedge clock_op)
begin
if(counter_load)
begin
clock2 <= 1'b0;
end
else
begin
clock2 <= !clock2;
end
end
assign tx_count7_enable = clock2 | counter_load; /* EN must be high for LD effect */
/* Generate tx_bitclk one clock cycle sooner in STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
assign tx_bitclk_enable_pre = (txbitcount[2:0] == 3'd0) && ((tx_state == UART_TX_STATE_SEND_STOP) ?
(!tx_count7_enable) : (tx_count7_enable));
end
else
begin
assign tx_count7_enable = 1'b1;
assign tx_bitclk_enable_pre = ((tx_state == UART_TX_STATE_SEND_STOP) ?
(txbitcount[2:0] == 3'd1) : (txbitcount[2:0] == 3'd0));
end
cy_psoc3_count7 #(.cy_period(txperiod_init),.cy_route_ld(1),.cy_route_en(1)) TxBitCounter
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input */ .load(counter_load),
/* input */ .enable(tx_count7_enable),
/* output [06:00] */ .count(txbitcount),
/* output */ .tc(tx_counter_tc)
);
if(CRCoutputsEn)
begin
assign tx_bitclk_half = !txbitcount[2]; /* txbitcount[2:0] == 3'd2;*/
end
end
/* 8x or 16x clock divider implemented on Datapath */
else
begin : sCLOCK
wire [7:0] sc_out;
wire counter_load_not = !((tx_state == UART_TX_STATE_IDLE) || (tx_bitclk_enable_pre &&
(tx_state == UART_TX_STATE_SEND_STOP)));
localparam [7:0] dpTXBitClkGenCmask0 = OverSampleCount - 1;
/* TX Bit Clk Datapath Configuration */
localparam UART_TX_BIT_CLK_DP_CONFIG =
{
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_A0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: Counter load (A0 = 0)*/
`CS_ALU_OP__INC, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: Count (A0++)*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: */
8'hFF, 8'h00, /*CFG9: */
8'hFF, dpTXBitClkGenCmask0, /*CFG11-10: dpTXBitClkGenCmask0 = OverSampleCount-1 */
`SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_ENBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_DEFSI, /*CFG13-12: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'h0,
1'h0, `SC_FIFO1__A0, `SC_FIFO0__A0,
`SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
/* TX Bit Clk Datapath */
cy_psoc3_dp #(.cy_dpconfig(UART_TX_BIT_CLK_DP_CONFIG)) TxBitClkGen
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({2'b0,counter_load_not}),
/* input */ .route_si(1'b0),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0_reg(tx_bitclk_dp),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1_reg(tx_counter_dp),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0), /* Carry in from previous stage */
/* output */ .co(), /* Carry out to next stage */
/* input */ .sir(1'b0), /* Shift in from right side */
/* output */ .sor(), /* Shift out to right side */
/* input */ .sil(1'b0), /* Shift in from left side */
/* output */ .sol(), /* Shift out to left side */
/* input */ .msbi(1'b0), /* MSB chain in */
/* output */ .msbo(), /* MSB chain out */
/* input [01:00] */ .cei(2'b0), /* Compare equal in from prev stage */
/* output [01:00] */ .ceo(), /* Compare equal out to next stage */
/* input [01:00] */ .cli(2'b0), /* Compare less than in from prv stage */
/* output [01:00] */ .clo(), /* Compare less than out to next stage */
/* input [01:00] */ .zi(2'b0), /* Zero detect in from previous stage */
/* output [01:00] */ .zo(), /* Zero detect out to next stage */
/* input [01:00] */ .fi(2'b0), /* 0xFF detect in from previous stage */
/* output [01:00] */ .fo(), /* 0xFF detect out to next stage */
/* input [01:00] */ .capi(2'b0), /* Software capture from previous stage */
/* output [01:00] */ .capo(), /* Software capture to next stage */
/* input */ .cfbi(1'b0), /* CRC Feedback in from previous stage */
/* output */ .cfbo(), /* CRC Feedback out to next stage */
/* input [07:00] */ .pi(8'b0), /* Parallel data port */
/* output [07:00] */ .po(sc_out[7:0]) /* Parallel data port */
);
assign tx_counter_tc = tx_counter_dp;
assign tx_bitclk_enable_pre = tx_bitclk_dp;
if(CRCoutputsEn)
begin
assign tx_bitclk_half = sc_out[cl-1];
end
end
/* TX Status Register bit locations */
localparam UART_TX_STS_TX_COMPLETE = 3'h0;
localparam UART_TX_STS_TX_BUFF_EMPTY = 3'h1;
localparam UART_TX_STS_TX_FIFO_FULL = 3'h2;
localparam UART_TX_STS_TX_FIFO_NOT_FULL = 3'h3;
assign tx_status[6:4] = 3'b0;
if(TXBitClkGenDP == 0)
begin
assign tx_status[UART_TX_STS_TX_COMPLETE] = tx_fifo_empty & tx_bitclk & (tx_state == UART_TX_STATE_SEND_STOP);
end
else
begin
assign tx_status[UART_TX_STS_TX_COMPLETE] = tx_fifo_empty & tx_bitclk_enable_pre &
(tx_state == UART_TX_STATE_SEND_STOP);
end
assign tx_status[UART_TX_STS_TX_BUFF_EMPTY] = tx_fifo_empty;
assign tx_status[UART_TX_STS_TX_FIFO_FULL] = !tx_fifo_notfull;
assign tx_status[UART_TX_STS_TX_FIFO_NOT_FULL] = tx_fifo_notfull;
/* Instantiate the status register and interrupt hook*/
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h01), .cy_int_mask(7'h7F)) TxSts
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input [06:00] */ .status(tx_status),
/* output */ .interrupt(tx_interrupt_out)
);
assign tx_drq_out = tx_status[UART_TX_STS_TX_FIFO_NOT_FULL];
assign tx_complete_out = tx_status[UART_TX_STS_TX_COMPLETE];
/**************************************************************************/
/* Registering tx_en for removing possible glitches */
/**************************************************************************/
always @(posedge clock_op)
begin
if(reset_reg)
begin
tx_en <= 1'b0;
end
else
begin
tx_en <= (HwTXEnSignal & (tx_state != UART_TX_STATE_IDLE)) ? 1'b1 : 1'b0;
end
end
/* CRC outputs implementation
* tx_clk and tx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((tx_state == UART_TX_STATE_SEND_DATA) & !reset_reg)
begin
tx_clk <= tx_bitclk_half;
tx_data <= ~txn;
end
else
begin
tx_clk <= 1'b0;
tx_data <= 1'b0;
end
end
end
always @(posedge clock_op)
begin
if(TXBitClkGenDP == 0)
begin
tx_bitclk <= tx_bitclk_enable_pre;
end
else
/* Do not generate tx_bitclk in last STOP state. Use tx_bitclk_pre instead
* to change state to START without time overhead
*/
begin
tx_bitclk <= tx_bitclk_enable_pre && (tx_state != UART_TX_STATE_SEND_STOP);
end
end
/* TX State machine*/
always @(posedge clock_op)
begin
if(FinalParityType == UART_PARITY_TYPE_MRKSPC)
begin
tx_ctrl_mark_last <= tx_ctrl_mark;
if(tx_ctrl_mark && !tx_ctrl_mark_last) /* Edge detector */
begin
tx_mark <= 1'b1;
end
end
if(reset_reg)
begin
tx_state <= UART_TX_STATE_IDLE;
txn <= 1'b0;
tx_mark <= 1'b0;
end
else
begin
case(tx_state)
UART_TX_STATE_IDLE:
begin
txn <= 1'b0;
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
end
UART_TX_STATE_SEND_START:
begin
txn <= 1'b1;
if(tx_bitclk)
begin
txn <= ~tx_shift_out;
if( (FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD) )
begin
tx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
end
tx_state <= UART_TX_STATE_SEND_DATA;
end
end
UART_TX_STATE_SEND_DATA:
begin
if(tx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD) )
begin
tx_parity_bit <= (tx_parity_bit ^ ~txn);
end
if(tx_counter_tc)
begin
if( ((FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD)) && !tx_hd_send_break )
begin
tx_state <= UART_TX_STATE_SEND_PARITY;
txn <= ~(tx_parity_bit ^ ~txn); /* +last bit */
end
else if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) && !tx_hd_send_break )
begin
tx_state <= UART_TX_STATE_SEND_PARITY;
txn <= ~tx_mark;
if(tx_mark)
begin
tx_mark <= 1'b0;
end
end
else
begin
tx_state <= UART_TX_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
else
begin
txn <= ~tx_shift_out;
end
end
end
UART_TX_STATE_SEND_PARITY:
begin
if(tx_bitclk)
begin
tx_state <= UART_TX_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
UART_TX_STATE_SEND_STOP1:
begin
/* Check tx_bitclk one clock cycle sooner in STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
if((TXBitClkGenDP == 0) ? tx_bitclk : tx_bitclk_enable_pre)
begin
if(NumStopBits == UART_NUM_STOP_BITS_1)
begin
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
else
begin
tx_state <= UART_TX_STATE_IDLE;
end
end
else
begin
tx_state <= UART_TX_STATE_SEND_STOP2;
end
end
end
UART_TX_STATE_SEND_STOP2:
begin
if((TXBitClkGenDP == 0) ? tx_bitclk : tx_bitclk_enable_pre)
begin
if(!(cts_n && FlowControl) && !tx_fifo_empty)
begin
tx_state <= UART_TX_STATE_SEND_START;
end
else
begin
tx_state <= UART_TX_STATE_IDLE;
end
end
end
endcase
end /* end of else statement */
end /* End of always block */
end /* End of TXEnable Generate Statement */
endgenerate /* sTX */
/**************************************************************
* UART RX Implementation *
* HALF DUPLEX mode implemented within RX *
**************************************************************/
/* RX Controller Logic */
generate
if (RXEnable || HalfDuplexEn)
begin:sRX
wire [6:0] rx_status; /* Receive portion of the UART Status Register */
reg [3:0] rx_state; /* Receive State Machine State Container */
reg rx_parity_bit;
reg rx_markspace_pre;
reg rx_markspace_status;
reg rx_address_detected; /* used in ADDR_MODE_HW_ mode for skip not addressed data */
reg rx_parity_error_pre; /* need for delay parity error to byte received interrupt */
reg rx_parity_error_status;
reg rx_break_status;
reg rx_addr_match_status;
reg rx_stop_bit_error;
reg rx_break_detect;
reg rx_last; /* used for start bit falling edge detection */
wire rx_postpoll;
reg rx_load_fifo;
wire rx_fifofull;
wire rx_fifonotempty;
wire rx_addressmatch1;
wire rx_addressmatch2;
wire [6:0] rx_count;
wire rx_counter_load;
wire rx_bitclk_pre;
reg rx_bitclk;
reg rx_state_stop1_reg;
/* Additional bit for count7 at 16xOverSample */
wire rx_count7_tc;
reg rx_count7_bit8;
wire rx_count7_bit8_wire;
wire rx_bitclk_pre16x;
wire rx_bitclk_enable;
wire rx_poll_bit1;
wire rx_poll_bit2;
/* One address supported in Half duplex mode */
wire rx_addressmatch = HalfDuplexEn ? rx_addressmatch1 : (rx_addressmatch1 | rx_addressmatch2);
/* RX State Machine States: */
/* Two low bits go to DP cs_addr[2,1] */
localparam UART_RX_STATE_IDLE = 4'h00;
localparam UART_RX_STATE_CHECK_START = 4'h04;
localparam UART_RX_STATE_GET_DATA = 4'h01;
localparam UART_RX_STATE_GET_PARITY = 4'h08;
localparam UART_RX_STATE_CHECK_STOP1 = 4'h0C;
localparam UART_RX_STATE_CHECK_BREAK = 4'h07;
localparam UART_HD_STATE_SEND_START = 4'h02;
localparam UART_HD_STATE_SEND_DATA = 4'h03;
localparam UART_HD_STATE_SEND_PARITY = UART_RX_STATE_GET_PARITY;
localparam UART_HD_STATE_SEND_STOP1 = UART_RX_STATE_CHECK_BREAK;
localparam UART_HD_STATE_SEND_STOP2 = UART_RX_STATE_CHECK_START;
localparam UART_HD_STATE_SEND_STOP = (NumStopBits == UART_NUM_STOP_BITS_1) ?
UART_HD_STATE_SEND_STOP1 : UART_HD_STATE_SEND_STOP2;
localparam [2:0] rxmsbsel = (FinalNumDataBits == 8) ? 3'd7 :
(FinalNumDataBits == 7) ? 3'd6 :
(FinalNumDataBits == 6) ? 3'd5 :
/*(FinalNumDataBits == 5)*/ 3'd4;
localparam [7:0] addressMask = (FinalNumDataBits == 8) ? 8'hFF :
(FinalNumDataBits == 7) ? 8'h7F :
(FinalNumDataBits == 6) ? 8'h3F :
/*(FinalNumDataBits == 5)*/ 8'h1F;
localparam [7:0] dataMask = (FinalNumDataBits == 8) ? 8'hFF :
(FinalNumDataBits == 7) ? 8'h7F :
(FinalNumDataBits == 6) ? 8'h3F :
/*(FinalNumDataBits == 5)*/ 8'h1F;
/* RX Shifter Datapath Configuration */
localparam UART_RX_SHIFTER_DP_CONFIG =
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM1: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM2: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM3: GET DATA (SR) */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM4: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM5: SEND START */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM6: IDLE */
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D0,
`CS_SHFT_OP___SR, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CFGRAM7: SEND DATA (SR) */
dataMask, 8'h00, /*CFG9: */
8'hFF, addressMask, /*CFG11-10: */
`SC_CMPB_A0_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_ENBL,
`SC_A_MASK_ENBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*CFG13-12: CMP A0 -D1 */
`SC_A0_SRC_ACC, `SC_SHIFT_SR, 1'h0,
1'h0, `SC_FIFO1_BUS, `SC_FIFO0__A0,
`SC_MSB_ENBL, rxmsbsel, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*CFG15-14: */
3'h00, `SC_FIFO_SYNC_NONE, 6'h00,
`SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO__EDGE,`SC_FIFO_ASYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*CFG17-16: */
};
cy_psoc3_dp8 #(.cy_dpconfig_a(UART_RX_SHIFTER_DP_CONFIG)) RxShifter
(
/* input */ .clk(clock_op),
/* input */ .reset(reset_reg),
/* input [02:00] */ .cs_addr({rx_state[1],rx_state[0],rx_bitclk_enable}),
/* input */ .route_si(rx_postpoll),
/* input */ .route_ci(1'b0),
/* input */ .f0_load(rx_load_fifo),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(rx_addressmatch1),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(rx_addressmatch2),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(hd_shift_out),
/* output */ .f0_bus_stat(rx_fifonotempty), /* FIFO is not EMPTY */
/* output */ .f0_blk_stat(rx_fifofull), /* FIFO is FULL */
/* output */ .f1_bus_stat(hd_tx_fifo_notfull), /* FIFO is not full when bus_stat = 1; */
/* output */ .f1_blk_stat(hd_tx_fifo_empty) /* FIFO is empty when blk_stat = 1; */
);
if(HalfDuplexEn)
begin
assign rx_counter_load = (rx_state == UART_RX_STATE_IDLE) ||
(HalfDuplexSend & rx_bitclk & (rx_state == UART_HD_STATE_SEND_STOP));
/* Generate rx_bitclk one clock cycle sooner in HD STOP bit state.
* This one clock cycle required to change state to START without time overhead
*/
assign rx_bitclk_pre = ((rx_state == UART_HD_STATE_SEND_STOP) & HalfDuplexSend) ? (rx_count[cl-1:0] == 4'd1) :
(rx_count[cl-1:0] == 4'd0);
end
else
begin
assign rx_counter_load = (rx_state == UART_RX_STATE_IDLE);
assign rx_bitclk_pre = (rx_count[cl-1:0] == 4'd0);
end
assign rx_bitclk_pre16x = (rx_count[cl-1:0] == (HalfBitCounts)) ? 1'b1 : 1'b0;
cy_psoc3_count7 #(.cy_period(rxperiod_init),.cy_route_ld(1),.cy_route_en(1)) RxBitCounter
(
/* input */ .clock(clock_op),
/* input */ .reset(reset_reg),
/* input */ .load(rx_counter_load),
/* input */ .enable(1),
/* output [06:00] */ .count(rx_count),
/* output */ .tc(rx_count7_tc)
);
assign rx_count7_bit8_wire = (OverSampleCount == UART_OVER_SAMPLE_16) ? rx_count7_bit8 : 1'd0;
assign rx_bitclk_enable = !HalfDuplexSend ? rx_bitclk : rx_bitclk_pre;
always @(posedge clock_op)
begin
if( (OverSampleCount == UART_OVER_SAMPLE_16) && rx_count7_bit8 && !HalfDuplexSend)
begin
rx_bitclk <= rx_bitclk_pre16x; /* Count7 reloaded to start value and we don't need to skip half bit*/
end
else
begin
rx_bitclk <= rx_bitclk_pre;
end
rx_state_stop1_reg <= (rx_state != UART_RX_STATE_CHECK_STOP1);
end
/* This state machine counts only first two voting, the third goes directly from rx line */
if(Use23Polling)
begin : s23Poll
reg [1:0] pollcount;
wire pollingrange;
assign rx_poll_bit1 = rx_count7_bit8_wire ?
((rx_count[cl-1:0] == (HalfBitCounts + 4'd1)) ? 1'b1 : 1'b0) :
((rx_count[cl-1:0] == 4'd1) ? 1'b1 : 1'b0);
assign rx_poll_bit2 = rx_count7_bit8_wire ? rx_bitclk_pre16x : rx_bitclk_pre;
assign pollingrange = rx_poll_bit1 | rx_poll_bit2;
always @(posedge clock_op)
begin
if(reset_reg)
begin
pollcount <= 2'd0;
end
else
begin
if(pollingrange)
begin
if(rx)
begin
pollcount <= pollcount + 2'd1;
end
end
else
begin
pollcount <= 2'd0;
end
end
end
assign rx_postpoll = (pollcount < 2'd1) ? 1'b0 : ((pollcount < 2'd2) ? rx : 1'b1);
end
else
begin
assign rx_postpoll = rx;
end /* Use23Polling */
/* RX Status Register bit locations */
localparam UART_RX_STS_MRKSPC = 3'd0;
localparam UART_RX_STS_BREAK = 3'd1;
localparam UART_RX_STS_PAR_ERROR = 3'd2;
localparam UART_RX_STS_STOP_ERROR = 3'd3;
localparam UART_RX_STS_OVERRUN = 3'd4;
localparam UART_RX_STS_FIFO_NOTEMPTY = 3'd5;
localparam UART_RX_STS_ADDR_MATCH = 3'd6;
/* Address Modes define when this bit is set */
/* Address Mode 00 = Software Byte by Byte - Generate Interrupt when address byte detected */
/* Address Mode 01 = Software Address To Buffer - Generate Interrupt when Address byte detected */
/* Address mode 10 = Hardware Byte by Byte - Generate Interrupt when address byte is detected and matches
one of the addresses */
/* Address mode 10 = Hardware Address To Buffer - Generate Interrupt when address byte is detected and matches
one of the addresses */
/* BE NOTE: Adress2 not used in Half duplex mode as 6 only outputs per DP available */
if(HalfDuplexEn)
begin
/*UART_RX_STS_MRKSPC for RX or
UART_TX_STS_TX_COMPLETE for TX - generated at the end of Stop Bit */
assign rx_status[UART_RX_STS_MRKSPC] = HalfDuplexSend ? hd_tx_fifo_empty & rx_bitclk &
((NumStopBits == UART_NUM_STOP_BITS_1) ? (rx_state == UART_HD_STATE_SEND_STOP1) :
(rx_state == UART_HD_STATE_SEND_STOP2)) :
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? (1'b0) : rx_markspace_status;
/*UART_RX_STS_BREAK for RX or Break detect
UART_TX_STS_TX_BUFF_EMPTY for TX*/
assign rx_status[UART_RX_STS_BREAK] = HalfDuplexSend ? hd_tx_fifo_empty : BreakDetect ? rx_break_status : 1'b0 ;
/*UART_RX_STS_PAR_ERROR for RX Parity Error */
assign rx_status[UART_RX_STS_PAR_ERROR] = rx_parity_error_status;
/*UART_RX_STS_STOP_ERROR for RX or Framing error
UART_TX_STS_TX_FIFO_NOT_FULL for TX*/
assign rx_status[UART_RX_STS_STOP_ERROR] = rx_stop_bit_error;
assign rx_status[UART_RX_STS_OVERRUN] = rx_fifofull & rx_load_fifo;
/* FIFO_NOTEMPTY delayed to synchronize with errors for RX
UART_TX_STS_TX_FIFO_FULL for TX*/
assign rx_status[UART_RX_STS_FIFO_NOTEMPTY] = HalfDuplexSend ? !hd_tx_fifo_notfull :
rx_fifonotempty & rx_state_stop1_reg;
assign rx_status[UART_RX_STS_ADDR_MATCH] =
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? 1'b0 : rx_addr_match_status;
/**************************************************************************/
/* Registering tx_en for removing possible glitches */
/**************************************************************************/
always @(posedge clock_op)
begin
if(reset_reg)
begin
tx_en <= 1'b0;
end
else
begin
tx_en <= ( HwTXEnSignal && HalfDuplexSend && (rx_state != UART_RX_STATE_IDLE)) ? 1'b1 : 1'b0;
end
end
/* TX CRC outputs implementation
* tx_clk and tx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((rx_state == UART_HD_STATE_SEND_DATA) & !reset_reg)
begin
tx_clk <= (rx_count[cl-1:0] == ((OverSampleCount / 4'd2) - 4'd2));
tx_data <= ~txn;
end
else
begin
tx_clk <= 1'b0;
tx_data <= 1'b0;
end
end
end
end
else
begin
assign rx_status[UART_RX_STS_MRKSPC] = (FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? (1'b0) :
rx_markspace_status;
assign rx_status[UART_RX_STS_BREAK] = BreakDetect ? rx_break_status : 1'b0 ;/* Break detect */
assign rx_status[UART_RX_STS_PAR_ERROR] = rx_parity_error_status; /* Parity Error */
assign rx_status[UART_RX_STS_STOP_ERROR] = rx_stop_bit_error; /* Framing Error */
assign rx_status[UART_RX_STS_OVERRUN] = rx_fifofull & rx_load_fifo;
/* FIFO_NOTEMPTY delayed to synchronize with errors*/
assign rx_status[UART_RX_STS_FIFO_NOTEMPTY] = rx_fifonotempty & rx_state_stop1_reg;
assign rx_status[UART_RX_STS_ADDR_MATCH] =
(FinalAddrMode == UART_RX_ADDR_MODE_NONE) ? 1'b0 : rx_addr_match_status;
end
assign rts_n = rx_fifofull;
/* RX CRC outputs implementation
* rx_clk and rx_data are synchronized to clock
*/
if(CRCoutputsEn)
begin
always @(posedge clock_op)
begin
if((rx_state == UART_RX_STATE_GET_DATA) & !reset_reg)
begin
rx_clk <= Use23Polling ? rx_poll_bit2 : rx_bitclk;
rx_data <= rx;
end
else
begin
rx_clk <= 1'b0;
rx_data <= 1'b0;
end
end
end
/* Instantiate the status register and interrupt hook */
cy_psoc3_statusi #(.cy_force_order(1), .cy_md_select(7'h5F), .cy_int_mask(7'h7F)) RxSts
(
/* input */ .clock(clock_op),
/* input */ .reset(HalfDuplexEn ? reset_sr : reset_reg),
/* input [06:00] */ .status(rx_status),
/* output */ .interrupt(rx_interrupt_out)
);
assign rx_drq_out = rx_status[UART_RX_STS_FIFO_NOTEMPTY];
assign rx_break_out = rx_status[UART_RX_STS_BREAK];
/* RX State Machine */
always @(posedge clock_op)
begin
if(HalfDuplexEn && (FinalParityType == UART_PARITY_TYPE_MRKSPC))
begin
tx_ctrl_mark_last <= tx_ctrl_mark;
if(tx_ctrl_mark && !tx_ctrl_mark_last) /* Edge detector */
begin
tx_mark <= 1'b1;
end
end
rx_addr_match_status <= 1'b0;
rx_stop_bit_error <= 1'b0;
rx_markspace_status <= 1'b0;
rx_parity_error_status <= 1'b0;
rx_break_status <= 1'b0;
rx_load_fifo <= 1'b0;
if(reset_reg)
begin
rx_state <= UART_RX_STATE_IDLE;
rx_last <= 1'b0;
rx_address_detected <= 1'b0;
if(HalfDuplexEn)
begin
tx_mark <= 1'b0;
txn <= 1'b0;
end
if(OverSampleCount==UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 1'b0;
end
end
else
begin
rx_last <= rx;
if( (OverSampleCount == UART_OVER_SAMPLE_16) && !rx_count7_bit8 )
begin
if(rx_count7_tc)
begin
rx_count7_bit8 <= 1;
end
end
case(rx_state)
UART_RX_STATE_IDLE:
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
if(HalfDuplexEn)
begin
txn <= 1'b0;
end
if(HalfDuplexSend && HalfDuplexEn)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
rx_state <= UART_HD_STATE_SEND_START;
end
end
else if(~rx & rx_last) /* RX falling edge detection */
begin
rx_state <= UART_RX_STATE_CHECK_START;
end
end
UART_RX_STATE_CHECK_START: /* Check the start bit after 4 cycles */
begin
/*UART_HD_STATE_SEND_STOP2 in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
rx_state <= UART_HD_STATE_SEND_START;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end
else if(rx_bitclk)
begin
if(rx_postpoll)
begin
rx_state <= UART_RX_STATE_IDLE;
end
else
begin
rx_state <= UART_RX_STATE_GET_DATA;
/* init status*/
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
rx_parity_error_pre <= 1'b0;
end
if(BreakDetect)
begin
rx_break_detect <= 1'b0;
rx_break_status <= 1'b0;
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_pre <= 1'b0;
end
rx_stop_bit_error <= 1'b0;
end
end
end
UART_RX_STATE_GET_DATA: /* Get the data bits */
begin
if(rx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= rx_parity_bit ^ rx_postpoll;
end
if(BreakDetect)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
end
end
if( rxperiod_cmp_need_one_bit && !rx_count7_bit8_wire )
begin
rx_state <= UART_RX_STATE_GET_DATA; /* wait on next count7 turn */
end
else if(rx_count[6:cl] < rxperiod_cmp)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) ||
(FinalParityType == UART_PARITY_TYPE_MRKSPC) )
begin
rx_state <= UART_RX_STATE_GET_PARITY;
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
end
UART_RX_STATE_GET_PARITY:
begin
/*UART_HD_STATE_SEND_PARITY in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
txn <= 1'b0;
rx_state <= UART_HD_STATE_SEND_STOP1;
end
end
else if(rx_bitclk)
begin
if(BreakDetect)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
end
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
if(rx_postpoll != rx_parity_bit)
begin
rx_parity_error_pre <= 1'b1;
end
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_pre <= rx_postpoll;
if( (FinalAddrMode == UART_RX_ADDR_MODE_HW_DET_BUFFER) ||
(FinalAddrMode == UART_RX_ADDR_MODE_HW_BYTE_BYTE) )
begin
if(rx_postpoll) /* Address byte received */
begin
rx_address_detected <= rx_addressmatch;
if( (FinalAddrMode == UART_RX_ADDR_MODE_HW_BYTE_BYTE) & rx_addressmatch)
begin /* Address is correct - store it for Byte_Byte mode*/
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
else /* Skip not correct address byte or in DET_BUFFER mode*/
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else /* Data byte received*/
begin
if(rx_address_detected) /* Store data only when correct Addres received */
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
else /* Skip not addresed data */
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
else
begin
rx_state <= UART_RX_STATE_CHECK_STOP1;
rx_load_fifo <= 1'b1;
end
end
end /* UART_RX_STATE_GET_PARITY*/
UART_RX_STATE_CHECK_STOP1:
begin
/* prepare clear on read errors one clock ahead */
if(rx_bitclk)
begin
if(FinalAddrMode != UART_RX_ADDR_MODE_NONE)
begin
rx_addr_match_status <= rx_addressmatch;
end
if((FinalParityType == UART_PARITY_TYPE_EVEN) || (FinalParityType == UART_PARITY_TYPE_ODD))
begin
rx_parity_error_status <= rx_parity_error_pre;
end
if( (FinalParityType == UART_PARITY_TYPE_MRKSPC) ||
(FinalAddrMode != UART_RX_ADDR_MODE_NONE) )
begin
rx_markspace_status <= rx_markspace_pre;
end
if(~rx_postpoll)
begin /* Stop bit = 0 */
rx_stop_bit_error <= 1'b1; /* Set Error Flag */
if( BreakDetect && !rx_break_detect) /* Break detection*/
begin
rx_state <= UART_RX_STATE_CHECK_BREAK;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end /*UART_RX_STATE_CHECK_STOP1 */
UART_RX_STATE_CHECK_BREAK:
begin
/*UART_HD_STATE_SEND_STOP1 in Half duplex mode*/
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if(NumStopBits == UART_NUM_STOP_BITS_1)
begin
if(!(cts_n && FlowControl) && !hd_tx_fifo_empty)
begin
if(OverSampleCount == UART_OVER_SAMPLE_16)
begin
rx_count7_bit8 <= 0;
end
rx_state <= UART_HD_STATE_SEND_START;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
else
begin
rx_state <= UART_HD_STATE_SEND_STOP2;
end
end
end
else if(BreakDetect)
begin
if(rx_bitclk)
begin
rx_break_detect <= rx_break_detect | rx_postpoll;
/* always need one more bit at 16x oversample */
if( ( ((OverSampleCount==UART_OVER_SAMPLE_16) && rx_count7_bit8_wire) ||
(OverSampleCount==UART_OVER_SAMPLE_8) ) && (rx_count[6:cl] < rxbreak_cmp) )
begin
if(~rx_break_detect) /* Break detected*/
begin
rx_break_status <= 1'b1; /* Set set BREAK Flag */
end
rx_break_detect <= 1; /* protect from double detect */
end
if(~rx_break_detect && ~rx_postpoll)
begin /* wait till BREAK release, it can be longer */
rx_state <= UART_RX_STATE_CHECK_BREAK;
end
else
begin
rx_state <= UART_RX_STATE_IDLE;
end
end
end /*BreakDetect*/
end /*UART_RX_STATE_CHECK_BREAK */
UART_HD_STATE_SEND_START:
begin
if(HalfDuplexSend && HalfDuplexEn)
begin
txn <= 1'b1;
if(rx_bitclk)
begin
txn <= ~hd_shift_out;
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (FinalParityType == UART_PARITY_TYPE_ODD) ? 1 : 0;
end
rx_state <= UART_HD_STATE_SEND_DATA;
end
else
begin
rx_state <= UART_HD_STATE_SEND_START;
end
end
end
UART_HD_STATE_SEND_DATA:
begin
if(HalfDuplexSend && HalfDuplexEn)
begin
if(rx_bitclk)
begin
if( (FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD) )
begin
rx_parity_bit <= (rx_parity_bit ^ ~txn);
end
/* SendBreak always need one more bit */
if((rx_count7_bit8_wire || /* counter second turn */
rx_count7_tc || /* last bit, but rx_count already reloaded*/
(!rxperiod_cmp_need_one_bit && /*data <= 6 bits*/
!(tx_hd_send_break && (OverSampleCount == UART_OVER_SAMPLE_16)))) && /*Break@16x*/
(((rx_count[6:cl] < hd_txperiod_cmp) && !tx_hd_send_break) ||
((rx_count[6:cl] < hd_tx_break_cmp) && tx_hd_send_break)))
begin
if((FinalParityType == UART_PARITY_TYPE_EVEN) ||
(FinalParityType == UART_PARITY_TYPE_ODD))
begin
rx_state <= UART_HD_STATE_SEND_PARITY;
txn <= ~(rx_parity_bit ^ ~txn); /*+last bit*/
end
else if (FinalParityType == UART_PARITY_TYPE_MRKSPC)
begin
rx_state <= UART_HD_STATE_SEND_PARITY;
txn <= ~tx_mark;
if(tx_mark)
begin
tx_mark <= 1'b0;
end
end
else
begin
rx_state <= UART_HD_STATE_SEND_STOP1;
txn <= 1'b0;
end
end
else
begin
if(tx_hd_send_break)
begin
txn <= 1'b1;
end
else
begin
txn <= ~hd_shift_out;
end
end
end
end
end
endcase
end /* End of Else Statement */
end /* End of Always Block */
end /* End of RXEnable Generate Statement begin*/
endgenerate /* sRX */
endmodule /* B_DMA_UART_v0_1 */
`endif /* B_DMA_UART_v0_1_V_ALREADY_INCLUDED */
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The 1cyc_sram_ctrl module control the 1 Cycle SRAM access requests
//
// ====================================================================
module sirv_1cyc_sram_ctrl #(
parameter DW = 32,
parameter MW = 4,
parameter AW = 32,
parameter AW_LSB = 3,
parameter USR_W = 3
)(
output sram_ctrl_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// ITCM SRAM clock gating for debugging purpose
input tcm_cgstop,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// * Cmd channel
input uop_cmd_valid, // Handshake valid
output uop_cmd_ready, // Handshake ready
input uop_cmd_read, // Read or write
input [AW-1:0] uop_cmd_addr,
input [DW-1:0] uop_cmd_wdata,
input [MW-1:0] uop_cmd_wmask,
input [USR_W-1:0] uop_cmd_usr,
// * RSP channel
output uop_rsp_valid, // Response valid
input uop_rsp_ready, // Response ready
output [DW-1:0] uop_rsp_rdata,
output [USR_W-1:0] uop_rsp_usr,
output ram_cs,
output ram_we,
output [AW-AW_LSB-1:0] ram_addr,
output [MW-1:0] ram_wem,
output [DW-1:0] ram_din,
input [DW-1:0] ram_dout,
output clk_ram,
input test_mode,
input clk,
input rst_n
);
sirv_gnrl_pipe_stage # (
.CUT_READY(0),
.DP(1),
.DW(USR_W)
) u_e1_stage (
.i_vld(uop_cmd_valid),
.i_rdy(uop_cmd_ready),
.i_dat(uop_cmd_usr),
.o_vld(uop_rsp_valid),
.o_rdy(uop_rsp_ready),
.o_dat(uop_rsp_usr),
.clk (clk ),
.rst_n(rst_n)
);
assign ram_cs = uop_cmd_valid & uop_cmd_ready;
assign ram_we = (~uop_cmd_read);
assign ram_addr= uop_cmd_addr [AW-1:AW_LSB];
assign ram_wem = uop_cmd_wmask[MW-1:0];
assign ram_din = uop_cmd_wdata[DW-1:0];
wire ram_clk_en = ram_cs | tcm_cgstop;
e203_clkgate u_ram_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (ram_clk_en),
.clk_out (clk_ram)
);
assign uop_rsp_rdata = ram_dout;
assign sram_ctrl_active = uop_cmd_valid | uop_rsp_valid;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:29:53 10/26/2015
// Design Name: UART_tx
// Module Name: C:/Users/Ariel/Xilinx/Workspace/UART/TXTest.v
// Project Name: UART
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TXTest;
// Inputs
reg clock;
reg reset;
reg s_tick;
reg tx_start;
reg [7:0] data_in;
// Outputs
wire tx;
wire tx_done;
wire baud_rate_clock;
// Instantiate the Unit Under Test (UUT)
UART_tx uut (
.clock(clock),
.reset(reset),
.s_tick(baud_rate_clock),
.tx_start(tx_start),
.data_in(data_in),
.tx(tx),
.tx_done(tx_done)
);
// Instantiate the Unit Under Test (UUT)
UART_baud_rate_generator #(.COUNT(2608)) baud_rate (
.clock(clock),
.baud_rate_clock(baud_rate_clock)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
s_tick = 0;
tx_start = 1;
data_in = 48;
// Wait 100 ns for global reset to finish
#100;
reset=1;
#100;
reset=0;
// Add stimulus here
end
always begin
clock = ~clock;
#3;
end
always begin
#1000;
tx_start=0;
#1000;
tx_start=1;
#500000;
data_in=data_in+5;
#100;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_LP2_V
`define SKY130_FD_SC_LP__ISO0N_LP2_V
/**
* iso0n: ????.
*
* Verilog wrapper for iso0n with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0n.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp2 (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B),
.VPWR(VPWR),
.KAGND(KAGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__iso0n_lp2 (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__iso0n base (
.X(X),
.A(A),
.SLEEP_B(SLEEP_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_LP2_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10230 10036
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_tbp
#( parameter
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
CFG_ENABLE_SHADOW_TBP = 0,
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary encoded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_DATA_ID_WIDTH = 10,
CFG_REG_REQ = 0,
CFG_REG_GRANT = 0,
CFG_DATA_REORDERING_TYPE = "INTER_BANK",
CFG_DISABLE_READ_REODERING = 0,
CFG_DISABLE_PRIORITY = 0,
CFG_PORT_WIDTH_REORDER_DATA = 1,
CFG_PORT_WIDTH_STARVE_LIMIT = 6,
CFG_PORT_WIDTH_TYPE = 3,
T_PARAM_ACT_TO_RDWR_WIDTH = 4,
T_PARAM_ACT_TO_ACT_WIDTH = 4,
T_PARAM_ACT_TO_PCH_WIDTH = 4,
T_PARAM_RD_TO_PCH_WIDTH = 4,
T_PARAM_WR_TO_PCH_WIDTH = 4,
T_PARAM_PCH_TO_VALID_WIDTH = 4,
T_PARAM_RD_AP_TO_VALID_WIDTH = 4,
T_PARAM_WR_AP_TO_VALID_WIDTH = 4
)
(
ctl_clk,
ctl_reset_n,
// Cmd gen interface
tbp_full,
tbp_empty,
cmd_gen_load,
cmd_gen_waiting_to_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// Arbiter interface
row_req,
act_req,
pch_req,
row_grant,
act_grant,
pch_grant,
col_req,
rd_req,
wr_req,
col_grant,
rd_grant,
wr_grant,
log2_row_grant,
log2_col_grant,
log2_act_grant,
log2_pch_grant,
log2_rd_grant,
log2_wr_grant,
or_row_grant,
or_col_grant,
tbp_read,
tbp_write,
tbp_precharge,
tbp_activate,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
tbp_size,
tbp_localid,
tbp_dataid,
tbp_ap,
tbp_burst_chop,
tbp_age,
tbp_priority,
tbp_rmw_correct,
tbp_rmw_partial,
sb_tbp_precharge_all,
sb_do_precharge_all,
// Timer value
t_param_act_to_rdwr,
t_param_act_to_act,
t_param_act_to_pch,
t_param_rd_to_pch,
t_param_wr_to_pch,
t_param_pch_to_valid,
t_param_rd_ap_to_valid,
t_param_wr_ap_to_valid,
// Misc interface
tbp_bank_closed,
tbp_timer_ready,
tbp_load,
data_complete,
data_rmw_complete,
data_rmw_fetch,
// Config interface
cfg_reorder_data,
cfg_starve_limit,
cfg_type,
cfg_enable_ecc,
cfg_enable_no_dm
);
localparam integer CFG_MEM_IF_BA_WIDTH_SQRD = 2**CFG_MEM_IF_BA_WIDTH;
localparam TBP_COUNTER_OFFSET = (CFG_REG_GRANT) ? 2 : 1;
localparam RDWR_AP_TO_VALID_WIDTH = (T_PARAM_RD_AP_TO_VALID_WIDTH > T_PARAM_WR_AP_TO_VALID_WIDTH) ? T_PARAM_RD_AP_TO_VALID_WIDTH : T_PARAM_WR_AP_TO_VALID_WIDTH;
localparam COL_TIMER_WIDTH = T_PARAM_ACT_TO_RDWR_WIDTH;
localparam ROW_TIMER_WIDTH = (T_PARAM_ACT_TO_ACT_WIDTH > RDWR_AP_TO_VALID_WIDTH) ? T_PARAM_ACT_TO_ACT_WIDTH : RDWR_AP_TO_VALID_WIDTH;
localparam TRC_TIMER_WIDTH = T_PARAM_ACT_TO_ACT_WIDTH;
localparam COMBINED_TIMER_WIDTH = (ROW_TIMER_WIDTH > TRC_TIMER_WIDTH) ? ROW_TIMER_WIDTH : TRC_TIMER_WIDTH;
// Start of port declaration
input ctl_clk;
input ctl_reset_n;
output tbp_full;
output tbp_empty;
input cmd_gen_load;
input cmd_gen_waiting_to_load;
input [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
input cmd_gen_write;
input cmd_gen_read;
input [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
input [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
input cmd_gen_priority;
input cmd_gen_rmw_correct;
input cmd_gen_rmw_partial;
input cmd_gen_autopch;
input cmd_gen_complete;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
input [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
input [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output [CFG_CTL_TBP_NUM-1:0] row_req;
output [CFG_CTL_TBP_NUM-1:0] act_req;
output [CFG_CTL_TBP_NUM-1:0] pch_req;
input [CFG_CTL_TBP_NUM-1:0] row_grant;
input [CFG_CTL_TBP_NUM-1:0] act_grant;
input [CFG_CTL_TBP_NUM-1:0] pch_grant;
output [CFG_CTL_TBP_NUM-1:0] col_req;
output [CFG_CTL_TBP_NUM-1:0] rd_req;
output [CFG_CTL_TBP_NUM-1:0] wr_req;
input [CFG_CTL_TBP_NUM-1:0] col_grant;
input [CFG_CTL_TBP_NUM-1:0] rd_grant;
input [CFG_CTL_TBP_NUM-1:0] wr_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_row_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_col_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_act_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_pch_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_rd_grant;
input [log2(CFG_CTL_TBP_NUM)-1:0] log2_wr_grant;
input or_row_grant;
input or_col_grant;
output [CFG_CTL_TBP_NUM-1:0] tbp_read;
output [CFG_CTL_TBP_NUM-1:0] tbp_write;
output [CFG_CTL_TBP_NUM-1:0] tbp_precharge;
output [CFG_CTL_TBP_NUM-1:0] tbp_activate;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
output [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
output [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
output [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
output [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_ap;
output [CFG_CTL_TBP_NUM-1:0] tbp_burst_chop;
output [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
output [CFG_CTL_TBP_NUM-1:0] tbp_priority;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
output [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
input [CFG_CTL_TBP_NUM-1:0] sb_tbp_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] sb_do_precharge_all;
input [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] t_param_act_to_rdwr;
input [T_PARAM_ACT_TO_ACT_WIDTH-1:0] t_param_act_to_act;
input [T_PARAM_ACT_TO_PCH_WIDTH-1:0] t_param_act_to_pch;
input [T_PARAM_RD_TO_PCH_WIDTH-1:0] t_param_rd_to_pch;
input [T_PARAM_WR_TO_PCH_WIDTH-1:0] t_param_wr_to_pch;
input [T_PARAM_PCH_TO_VALID_WIDTH-1:0] t_param_pch_to_valid;
input [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] t_param_rd_ap_to_valid;
input [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] t_param_wr_ap_to_valid;
output [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
output [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
output [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output data_rmw_fetch;
input [CFG_PORT_WIDTH_REORDER_DATA-1:0] cfg_reorder_data;
input [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] cfg_starve_limit;
input [CFG_PORT_WIDTH_TYPE-1:0] cfg_type;
input cfg_enable_ecc;
input cfg_enable_no_dm;
// End of port declaration
// Logic operators
wire tbp_full;
wire tbp_empty;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp;
wire [CFG_CTL_TBP_NUM-1:0] load_tbp_index;
wire [CFG_CTL_TBP_NUM-1:0] flush_tbp;
reg [CFG_CTL_TBP_NUM-1:0] precharge_tbp;
reg [CFG_CTL_TBP_NUM-1:0] row_req;
reg [CFG_CTL_TBP_NUM-1:0] act_req;
reg [CFG_CTL_TBP_NUM-1:0] pch_req;
reg [CFG_CTL_TBP_NUM-1:0] col_req;
reg [CFG_CTL_TBP_NUM-1:0] rd_req;
reg [CFG_CTL_TBP_NUM-1:0] wr_req;
wire cfg_enable_rmw;
wire int_tbp_full;
wire int_tbp_empty;
reg [CFG_CTL_TBP_NUM-1:0] valid;
reg [CFG_CTL_TBP_NUM-1:0] valid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] write;
reg [CFG_CTL_TBP_NUM-1:0] read;
wire [CFG_CTL_TBP_NUM-1:0] precharge;
wire [CFG_CTL_TBP_NUM-1:0] activate;
reg [CFG_INT_SIZE_WIDTH-1:0] size [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] autopch;
reg [CFG_LOCAL_ID_WIDTH-1:0] localid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_DATA_ID_WIDTH-1:0] dataid [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] priority_a;
reg [CFG_CTL_TBP_NUM-1:0] activated;
reg [CFG_CTL_TBP_NUM-1:0] activated_p;
reg [CFG_CTL_TBP_NUM-1:0] activated_combi;
reg [CFG_CTL_TBP_NUM-1:0] precharged;
reg [CFG_CTL_TBP_NUM-1:0] precharged_combi;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] not_done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] done_tbp_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_r;
reg [CFG_CTL_TBP_NUM-1:0] open_row_passed;
wire [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush;
reg [CFG_CTL_TBP_NUM-1:0] open_row_pass_flush_r;
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] log2_open_row_pass_flush_r [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] done;
reg [CFG_CTL_TBP_NUM-1:0] done_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete;
reg [CFG_CTL_TBP_NUM-1:0] complete_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_wr;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_rd;
reg [CFG_CTL_TBP_NUM-1:0] complete_combi_wr;
reg [CFG_CTL_TBP_NUM-1:0] wst_p;
reg [CFG_CTL_TBP_NUM-1:0] ssb;
reg [CFG_CTL_TBP_NUM-1:0] ssbr;
reg [CFG_CTL_TBP_NUM-1:0] ap;
reg [CFG_CTL_TBP_NUM-1:0] real_ap;
reg [CFG_CTL_TBP_NUM-1:0] rmw_correct;
reg [CFG_CTL_TBP_NUM-1:0] rmw_partial;
reg [CFG_CTL_TBP_NUM-1:0] rmw;
reg [CFG_CTL_TBP_NUM-1:0] require_flush;
reg [CFG_CTL_TBP_NUM-1:0] require_flush_calc;
reg [CFG_CTL_TBP_NUM-1:0] require_pch_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] require_pch;
reg [CFG_CTL_TBP_NUM-1:0] burst_chop;
reg [CFG_CTL_TBP_NUM-1:0] age [CFG_CTL_TBP_NUM-1:0];
reg [CFG_PORT_WIDTH_STARVE_LIMIT-1:0] starvation [CFG_CTL_TBP_NUM-1:0];
// bit vectors
reg [CFG_CTL_TBP_NUM-1:0] apvo_combi; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvo; // vector for smart autopch open page
reg [CFG_CTL_TBP_NUM-1:0] apvc_combi; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] apvc; // vector for smart autopch close page
reg [CFG_CTL_TBP_NUM-1:0] rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] cpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] wrt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_rpv [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_sbvt [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] or_wrt;
reg [CFG_CTL_TBP_NUM-1:0] nor_rpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_cpv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbv;
reg [CFG_CTL_TBP_NUM-1:0] nor_sbvt;
wire [CFG_CTL_TBP_NUM-1:0] tbp_read;
wire [CFG_CTL_TBP_NUM-1:0] tbp_write;
wire [CFG_CTL_TBP_NUM-1:0] tbp_ap;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
wire [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
wire [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
wire [(CFG_CTL_TBP_NUM*CFG_INT_SIZE_WIDTH)-1:0] tbp_size;
wire [(CFG_CTL_TBP_NUM*CFG_LOCAL_ID_WIDTH)-1:0] tbp_localid;
wire [(CFG_CTL_TBP_NUM*CFG_DATA_ID_WIDTH)-1:0] tbp_dataid;
wire [(CFG_CTL_TBP_NUM*CFG_CTL_TBP_NUM)-1:0] tbp_age;
wire [CFG_CTL_TBP_NUM-1:0] tbp_priority;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_correct;
wire [CFG_CTL_TBP_NUM-1:0] tbp_rmw_partial;
wire [CFG_MEM_IF_CHIP-1:0] tbp_bank_closed;
wire [CFG_MEM_IF_CHIP-1:0] tbp_timer_ready;
reg [CFG_MEM_IF_CHIP-1:0] bank_closed;
reg [CFG_MEM_IF_CHIP-1:0] timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] int_bank_closed [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] int_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_shadow_timer_ready [CFG_MEM_IF_CHIP-1:0];
reg [CFG_CTL_TBP_NUM-1:0] same_command_read;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank_diff_row;
reg [CFG_CTL_TBP_NUM-1:0] same_chip_bank;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_command_read;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank_diff_row;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chip_bank;
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_diff_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank_row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] pre_calculated_same_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] pre_calculated_same_shadow_chip_bank [CFG_CTL_TBP_NUM-1:0];
reg [COL_TIMER_WIDTH-1:0] col_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] col_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] col_timer_pre_ready;
reg [COMBINED_TIMER_WIDTH-1:0] combined_timer [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer_combi [CFG_CTL_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] row_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] row_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] row_timer_pre_ready;
reg [TRC_TIMER_WIDTH-1:0] trc_timer [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready;
reg [CFG_CTL_TBP_NUM-1:0] trc_timer_pre_ready_combi;
reg [CFG_CTL_TBP_NUM-1:0] pch_ready;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_rd_to_pch_greater_than_row_timer;
reg [CFG_CTL_TBP_NUM-1:0] compare_t_param_wr_to_pch_greater_than_row_timer;
reg compare_t_param_act_to_rdwr_less_than_offset;
reg compare_t_param_act_to_act_less_than_offset;
reg compare_t_param_act_to_pch_less_than_offset;
reg compare_t_param_rd_to_pch_less_than_offset;
reg compare_t_param_wr_to_pch_less_than_offset;
reg compare_t_param_pch_to_valid_less_than_offset;
reg compare_t_param_rd_ap_to_valid_less_than_offset;
reg compare_t_param_wr_ap_to_valid_less_than_offset;
reg compare_offset_t_param_act_to_rdwr_less_than_0;
reg compare_offset_t_param_act_to_rdwr_less_than_1;
reg [T_PARAM_ACT_TO_RDWR_WIDTH-1:0] offset_t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_ACT_WIDTH-1:0] offset_t_param_act_to_act;
reg [T_PARAM_ACT_TO_PCH_WIDTH-1:0] offset_t_param_act_to_pch;
reg [T_PARAM_RD_TO_PCH_WIDTH-1:0] offset_t_param_rd_to_pch;
reg [T_PARAM_WR_TO_PCH_WIDTH-1:0] offset_t_param_wr_to_pch;
reg [T_PARAM_PCH_TO_VALID_WIDTH-1:0] offset_t_param_pch_to_valid;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH-1:0] offset_t_param_rd_ap_to_valid;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH-1:0] offset_t_param_wr_ap_to_valid;
reg [CFG_CTL_TBP_NUM-1:0] can_act;
reg [CFG_CTL_TBP_NUM-1:0] can_pch;
reg [CFG_CTL_TBP_NUM-1:0] can_rd;
reg [CFG_CTL_TBP_NUM-1:0] can_wr;
reg [CFG_CTL_TBP_NUM-1:0] finish_tbp;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] flush_shadow_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp_combi;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] ready_to_push_tbp;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [ROW_TIMER_WIDTH-1:0] shadow_row_timer [CFG_CTL_SHADOW_TBP_NUM-1:0];
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_pre_ready;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] shadow_row_timer_ready;
wire one = 1'b1;
wire zero = 1'b0;
integer i;
integer j;
genvar k;
//----------------------------------------------------------------------------------------------------
// Output port assignments
//----------------------------------------------------------------------------------------------------
assign tbp_read = read;
assign tbp_write = write;
assign tbp_ap = real_ap;
assign tbp_burst_chop = burst_chop;
assign tbp_precharge = precharge;
assign tbp_activate = activate;
assign tbp_priority = priority_a;
assign tbp_rmw_correct = rmw_correct;
assign tbp_rmw_partial = rmw_partial;
generate
begin
for(k=0; k<CFG_CTL_TBP_NUM; k=k+1)
begin : tbp_name
assign tbp_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = chipsel[k];
assign tbp_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = bank [k];
assign tbp_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = row [k];
assign tbp_col [(k*CFG_MEM_IF_COL_WIDTH)+CFG_MEM_IF_COL_WIDTH-1:k*CFG_MEM_IF_COL_WIDTH] = col [k];
assign tbp_localid[(k*CFG_LOCAL_ID_WIDTH)+CFG_LOCAL_ID_WIDTH-1:k*CFG_LOCAL_ID_WIDTH] = localid[k];
assign tbp_dataid [(k*CFG_DATA_ID_WIDTH)+CFG_DATA_ID_WIDTH-1:k*CFG_DATA_ID_WIDTH] = dataid [k];
assign tbp_age [(k*CFG_CTL_TBP_NUM)+CFG_CTL_TBP_NUM-1:k*CFG_CTL_TBP_NUM] = age [k];
assign tbp_size [(k*CFG_INT_SIZE_WIDTH)+CFG_INT_SIZE_WIDTH-1:k*CFG_INT_SIZE_WIDTH] = size [k];
end
for(k=0; k<CFG_CTL_SHADOW_TBP_NUM; k=k+1)
begin : tbp_shadow_name
if (CFG_ENABLE_SHADOW_TBP)
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = shadow_chipsel[k];
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = shadow_bank [k];
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = shadow_row [k];
end
else
begin
assign tbp_shadow_chipsel[(k*CFG_MEM_IF_CS_WIDTH)+CFG_MEM_IF_CS_WIDTH-1:k*CFG_MEM_IF_CS_WIDTH] = 0;
assign tbp_shadow_bank [(k*CFG_MEM_IF_BA_WIDTH)+CFG_MEM_IF_BA_WIDTH-1:k*CFG_MEM_IF_BA_WIDTH] = 0;
assign tbp_shadow_row [(k*CFG_MEM_IF_ROW_WIDTH)+CFG_MEM_IF_ROW_WIDTH-1:k*CFG_MEM_IF_ROW_WIDTH] = 0;
end
end
end
endgenerate
assign tbp_full = int_tbp_full;
assign tbp_empty = int_tbp_empty;
assign int_tbp_empty = &(valid ^~ done); // empty if valid and done are the same
assign load_tbp = (~int_tbp_full & cmd_gen_load) ? load_tbp_index : 0;
assign flush_tbp = open_row_pass_flush_r | finish_tbp | (done & precharge_tbp);
assign tbp_load = load_tbp;
assign tbp_bank_closed = bank_closed;
assign tbp_timer_ready = timer_ready;
assign precharge = activated;
assign activate = ~activated;
//----------------------------------------------------------------------------------------------------
// TBP General Functions
//----------------------------------------------------------------------------------------------------
assign cfg_enable_rmw = cfg_enable_ecc | cfg_enable_no_dm;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
valid_combi <= 0;
end
else
begin
valid_combi <= (valid | load_tbp) & ~flush_tbp;
end
end
assign load_tbp_index = ~valid_combi & (valid_combi + 1);
assign int_tbp_full = &valid_combi;
//----------------------------------------------------------------------------------------------------
// Finish TBP
//----------------------------------------------------------------------------------------------------
// Logic to determine when can we flush a done TBP
// in non-shadow TBP case, we can only flush once the timer finished counting
// in shadow TBP case, we can flush once it is pushed into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
finish_tbp[i] = push_tbp[i] | (done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i]);
end
else
begin
finish_tbp[i] = done[i] & precharged[i] & row_timer_pre_ready[i] & trc_timer_pre_ready[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Shadow TBP Logic
//----------------------------------------------------------------------------------------------------
// Determine when can we flush TBP
assign flush_shadow_tbp = shadow_valid & shadow_row_timer_pre_ready;
// Determine when it's ready to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_tbp[i]) // TBP might flush before shadow TBP is still allocated
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
ready_to_push_tbp_combi[i] = 1'b0;
end
else if ((col_grant[i] && real_ap[i]) || (pch_grant[i] && done[i])) // indicate ready to push TBP once TBP is done
begin
ready_to_push_tbp_combi[i] = 1'b1;
end
else
begin
ready_to_push_tbp_combi[i] = ready_to_push_tbp[i];
end
end
else
begin
ready_to_push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
ready_to_push_tbp[i] <= ready_to_push_tbp_combi[i];
end
end
end
// Determine when to push into shadow TBP
always @ (*)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i]) // we want push_tbp to pulse for one clock cycle only
begin
push_tbp_combi[i] = 1'b0;
end
else if (ready_to_push_tbp_combi[i] && shadow_row_timer_pre_ready[i]) // prevent pushing into an allocated shadow TBP
begin
push_tbp_combi[i] = 1'b1;
end
else
begin
push_tbp_combi[i] = push_tbp[i];
end
end
else
begin
push_tbp_combi[i] = zero;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
push_tbp[i] <= push_tbp_combi[i];
end
end
end
// Shadow TBP information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp_combi[i])
begin
shadow_chipsel[i] <= chipsel[i];
shadow_bank [i] <= bank [i];
shadow_row [i] <= row [i];
end
end
else
begin
shadow_chipsel[i] <= 0;
shadow_bank [i] <= 0;
shadow_row [i] <= 0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (flush_shadow_tbp[i])
begin
shadow_valid[i] <= 1'b0;
end
else if (push_tbp[i])
begin
shadow_valid[i] <= 1'b1;
end
end
else
begin
shadow_valid[i] <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_SHADOW_TBP_NUM; i=i+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (push_tbp[i])
begin
if (!row_timer_pre_ready[i] || !trc_timer_pre_ready[i])
begin
// Decide to take the larger timer value between row/trc timer
if (row_timer[i] > trc_timer[i])
begin
shadow_row_timer[i] <= row_timer[i] - 1'b1;
end
else
begin
shadow_row_timer[i] <= trc_timer[i] - 1'b1;
end
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b1;
shadow_row_timer_ready [i] <= 1'b1;
end
end
else
begin
if (shadow_row_timer[i] != 0)
begin
shadow_row_timer[i] <= shadow_row_timer[i] - 1'b1;
end
if (shadow_row_timer[i] <= 1)
begin
shadow_row_timer_ready[i] <= 1'b1;
end
if (shadow_row_timer[i] <= 2)
begin
shadow_row_timer_pre_ready[i] <= 1'b1;
end
end
end
else
begin
shadow_row_timer [i] <= 0;
shadow_row_timer_pre_ready[i] <= 1'b0;
shadow_row_timer_ready [i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Request logic
//----------------------------------------------------------------------------------------------------
// Can_* logic for request logic, indicate whether TBP can request now
// Can activate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_act[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (activated_combi[i]) // activated, so there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (col_grant[i]) //done, there is no need to enable activate again
begin
can_act[i] <= 1'b0;
end
else if (load_tbp[i]) // new TBP command, assume no open-row-pass (handled by statement above)
begin
can_act[i] <= 1'b1;
end
else if
(
!done[i] && valid[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
)
// precharge or precharge all command, re-enable since it is not done
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_act[i] <= 1'b1;
end
end
end
end
// Can precharge
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_pch[i] <= one; // there is no logic required for precharge, keeping this for future use
end
end
end
// Can read
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_rd[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_rd[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't read since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_rd[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_rd[i] <= 1'b1;
end
end
end
end
// Can write
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
can_wr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (col_grant[i] || done[i]) // done, there is no need to enable read again
begin
can_wr[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && (precharge_tbp[i] || pch_grant[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && (precharge_tbp[i] )) ||
(!cfg_reorder_data && precharge_tbp[i])
)
// precharge or precharge all command, can't write since bank is not active
// (INTER_ROW) we need to validate pch_grant because precharge might happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
begin
can_wr[i] <= 1'b0;
end
else if (((act_grant[i] && compare_t_param_act_to_rdwr_less_than_offset) || open_row_pass[i] || activated[i]) && col_timer_pre_ready[i]) // activated and timer is ready
begin
can_wr[i] <= 1'b1;
end
end
end
end
// Row request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_req[i] = act_req[i] | pch_req[i];
end
end
// Column request
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_req[i] = rd_req[i] | wr_req[i];
end
end
// Individual activate, precharge, read and write request logic
always @ (*)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
act_req[i] = nor_rpv[i] & nor_sbv[i] & nor_sbvt[i] & ~or_wrt[i] & can_act[i];
pch_req[i] = require_pch[i] & pch_ready[i] & can_pch[i];
rd_req [i] = nor_cpv[i] & can_rd[i] & complete_rd[i];
wr_req [i] = nor_cpv[i] & can_wr[i] & complete_wr[i];
end
end
//----------------------------------------------------------------------------------------------------
// Valid logic
//----------------------------------------------------------------------------------------------------
// Indicates that current TBP is valid after load an invalid after flush
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
valid[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
valid[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
valid[i] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// TBP information
//----------------------------------------------------------------------------------------------------
// Keeps information from cmd_gen after load
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
chipsel [i] <= 0;
bank [i] <= 0;
row [i] <= 0;
col [i] <= 0;
write [i] <= 0;
read [i] <= 0;
size [i] <= 0;
autopch [i] <= 0;
localid [i] <= 0;
dataid [i] <= 0;
rmw_correct[i] <= 0;
rmw_partial[i] <= 0;
rmw [i] <= 0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
chipsel [i] <= cmd_gen_chipsel;
bank [i] <= cmd_gen_bank;
row [i] <= cmd_gen_row;
col [i] <= cmd_gen_col;
write [i] <= cmd_gen_write;
read [i] <= cmd_gen_read;
size [i] <= cmd_gen_size;
autopch [i] <= cmd_gen_autopch;
localid [i] <= cmd_gen_localid;
dataid [i] <= cmd_gen_dataid;
rmw_correct[i] <= cmd_gen_rmw_correct;
rmw_partial[i] <= cmd_gen_rmw_partial;
rmw [i] <= cmd_gen_rmw_partial | cmd_gen_rmw_correct;
end
end
end
// Priority information
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
priority_a[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_DISABLE_PRIORITY == 1)
begin
priority_a[i] <= zero;
end
else
begin
if (load_tbp[i])
begin
if (cfg_reorder_data) // priority will be ignored when data reordering is OFF
begin
priority_a[i] <= cmd_gen_priority;
end
else
begin
priority_a[i] <= 1'b0;
end
end
else if (starvation[i] == cfg_starve_limit) // assert priority when starvation limit is reached
begin
priority_a[i] <= 1'b1;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Row dependency vector
//----------------------------------------------------------------------------------------------------
// RPV, TBP is only allowed to request row command when RPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !push_tbp[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && (same_chip_bank_row[j] || (same_chip_bank[j] && (rmw_partial[j] || rmw_correct[j])))) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && same_chip_bank[j]) ||
(!cfg_reorder_data && valid[j] && same_chip_bank[j])
)
)
// (INTER_ROW) Set RPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set RPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// This is to prevent activate going to the later RMW commands
// (INTER_BANK) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (NON_REORDER) Set RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs, to allow command reordering
begin
rpv_combi[i][j] = 1'b1;
end
else
begin
rpv_combi[i][j] = 1'b0;
end
end
else if (flush_tbp[j] || push_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
rpv_combi[i][j] = 1'b0;
end
else
begin
rpv_combi[i][j] = rpv[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (load_tbp[i])
begin
if (!flush_shadow_tbp[j] && ((shadow_valid[j] && same_shadow_chip_bank[j]) || (push_tbp[j] && same_chip_bank[j])))
// Set Shadow RPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else
begin
shadow_rpv_combi[i][j] = 1'b0;
end
end
else if (push_tbp[j] && rpv[i][j])
// If there is a push_tbp and RPV is set to '1'
// We need to shift RPV to Shadow RPV
begin
shadow_rpv_combi[i][j] = 1'b1;
end
else if (flush_shadow_tbp[j])
// (INTER_ROW) Set RPV to '0' after flush
// (INTER_BANK) Set RPV to '0' after flush
begin
shadow_rpv_combi[i][j] = 1'b0;
end
else
begin
shadow_rpv_combi[i][j] = shadow_rpv[i][j];
end
end
else
begin
shadow_rpv_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_rpv[i] <= ~|{shadow_rpv_combi[i], rpv_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
rpv[i][j] <= 1'b0;
end
else
begin
rpv[i][j] <= rpv_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_rpv[i][j] <= shadow_rpv_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Column dependency vector
//----------------------------------------------------------------------------------------------------
// CPV, TBP is only allowed to request column command when CPV is all zero, meaning no dependencies on other TBPs
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i])
begin
if
(
!flush_tbp[j] && !col_grant[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank_row[j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && valid[j] && !done[j] && (priority_a[j] || same_chip_bank [j] || (rmw[j] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct)) || same_command_read[j])) ||
(!cfg_reorder_data && valid[j] && !done[j])
)
)
// (INTER_ROW) Set CPV to '1' when a new TBP has same-chip-bank-row address with any other existing TBPs
// (INTER_ROW) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_ROW) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (INTER_BANK) Set CPV to '1' when a new TBP has same-chip-bank address with any other existing TBPs
// (INTER_BANK) Set CPV to '1' when existing TBP is a RMW command, we don't allow reordering between RMW commands
// (INTER_BANK) Set CPV to '1' when existing TBP is a priority command, we don't want new TBP to take over priority command
// (NON_REORDER) Set CPV to '1' when a new TBP is loaded, all column command must be executed in order
begin
cpv_combi[i][j] = 1'b1;
end
else
begin
cpv_combi[i][j] = 1'b0;
end
end
else if (col_grant[j])
// (INTER_ROW) Set CPV to '0' after col_grant
// (INTER_BANK) Set CPV to '0' after col_grant
begin
cpv_combi[i][j] = 1'b0;
end
else
begin
cpv_combi[i][j] = cpv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
cpv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_cpv[i] <= ~|cpv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
cpv[i][j] <= 1'b0;
end
else
begin
cpv[i][j] <= cpv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Activate related logic
//----------------------------------------------------------------------------------------------------
// Open-row-pass flush logic
// after a granted command and WST (open row pass to another TBP with same page from just granted command) OR
// after a done command and WST (open row pass to another TBP with same page from a done command with page open)
// Logic to determine which not-done TBP should be flushed to perform open-row-pass
always @ (*)
begin
not_done_tbp_row_pass_flush = col_grant & wst_p;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
not_done_tbp_row_pass_flush_r[i] <= not_done_tbp_row_pass_flush[i];
end
end
end
// Logic to determine which done TBP should be flushed to perform open-row-pass
always @ (*)
begin
done_tbp_row_pass_flush = done & wst_p & ~row_grant & ~precharge_tbp;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (done_tbp_row_pass_flush_r[i])
begin
done_tbp_row_pass_flush_r[i] <= 1'b0;
end
else
begin
done_tbp_row_pass_flush_r[i] <= done_tbp_row_pass_flush[i];
end
end
end
end
// Using done_tbp_row_pass_flush_r to improve timing
// it's acceptable to add one clock cycle latency when performing open-row-pass from a done command
// [REMARK] there is potential to optimize the flush logic (for done-open-row-pass case), because flush_tbp depends on open_row_pass_flush logic
assign open_row_pass_flush = not_done_tbp_row_pass_flush | done_tbp_row_pass_flush;
// Open-row-pass logic, TBP will pass related information to same page command (increase efficiency)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass[i] = |open_row_pass_flush && or_wrt[i] && |(wrt[i] & open_row_pass_flush);
end
end
// Open-row-passed logic, keep signal high once there is a open-row-pass to current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_passed[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i])
begin
open_row_passed[i] <= 1'b1;
end
else if (flush_tbp[i])
begin
open_row_passed[i] <= 1'b0;
end
end
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= 1'b0;
open_row_pass_flush_r[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
open_row_pass_r [i] <= open_row_pass [i];
open_row_pass_flush_r[i] <= open_row_pass_flush[i];
end
end
end
// Activated logic
// indicate that current TBP is activated by activate command or open-row-pass
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (act_grant[i] || open_row_pass[i])
begin
activated_combi[i] = 1'b1;
end
else
begin
activated_combi[i] = 1'b0;
end
end
end
// activated need not to be validated with valid
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated [i] <= 1'b0;
activated_p[i] <= 1'b0;
end
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
activated_p[i] <= activated_combi[i]; // activated pulse
if (flush_tbp[i] || pch_grant[i])
begin
activated[i] <= 1'b0;
end
else if (precharge_tbp[i])
begin
activated[i] <= 1'b0;
end
else if (activated_combi[i])
begin
activated[i] <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Precharge related logic
//----------------------------------------------------------------------------------------------------
// Precharge all logic
// indicate which TBP is precharged cause of sideband precharge all command
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharge_tbp[i] = sb_tbp_precharge_all[i];
end
end
// Precharge logic
// indicate which TBP is precharged
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
precharged_combi[i] = 1'b0;
end
else if (activated_combi[i] && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW")
// Only required in INTER-ROW reordering case since TBP might request precharge after TBP load
// due to TBP interlock case
begin
precharged_combi[i] = 1'b0;
end
else if (col_grant[i] && real_ap[i])
begin
precharged_combi[i] = 1'b1;
end
else if (pch_grant[i])
begin
precharged_combi[i] = 1'b1;
end
else
begin
precharged_combi[i] = precharged[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
precharged[i] <= precharged_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Auto-precharge related logic
//----------------------------------------------------------------------------------------------------
// Auto precharge related logic, to determine which TBP should be closed or kept open
// OPP - autoprecharge when there is another command to same chip-bank different row
// CPP - do not autoprecharge when there is another command to the same chip-bank-row
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
apvo_combi[i] = 1'b0;
apvc_combi[i] = 1'b0;
end
else if
(
(load_tbp[i] && CFG_DATA_REORDERING_TYPE == "INTER_ROW") || // load self
(
(|load_tbp && !load_tbp[i]) && // load other TBP
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb[i]) ||
(!cfg_reorder_data && !ssb[i])
)
)
)
// (INTER_ROW) update multiple times whenever there is a load so that it'll get the latest AP info
// (INTER_BANK) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
// (NON_REORDER) only update this once after same chip-bank command is loaded, masked by SSB (seen same bank)
begin
if
(
(load_tbp[i] && |(valid & same_chip_bank_diff_row) && cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW") ||
((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_diff_row[i])
)
// (INTER_ROW) on self load, set to '1' if other valid TBP is same-chip-bank-diff-row with self
// set to '1' if there is a new command with same-chip-bank-diff-row with current TBP
begin
apvo_combi[i] = 1'b1;
end
else
begin
apvo_combi[i] = apvo[i];
end
if ((|load_tbp && !load_tbp[i]) && valid[i] && same_chip_bank_row[i])
// set to '1' if there is a new command with same-chip-bank-row with current TBP
begin
apvc_combi[i] = 1'b1;
end
else
begin
apvc_combi[i] = apvc[i];
end
end
else
begin
apvo_combi[i] = apvo[i];
apvc_combi[i] = apvc[i];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= 1'b0;
apvc[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
apvo[i] <= apvo_combi[i];
apvc[i] <= apvc_combi[i];
end
end
end
// Auto precharge
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (apvc[i]) // keeping a page open have higher priority that keeping a close page (improve efficiency)
begin
ap[i] = 1'b0;
end
else if (apvo[i])
begin
ap[i] = 1'b1;
end
else
begin
ap[i] = autopch[i] | require_flush[i];
end
end
end
// Real auto-precharge
// purpose is to make pipelining easier in the future (if needed)
always @ (*)
begin
real_ap = ap;
end
//----------------------------------------------------------------------------------------------------
// Done logic
//----------------------------------------------------------------------------------------------------
// Indicate that current TBP has finished issuing column command
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (flush_tbp[i])
begin
done_combi[i] = 1'b0;
end
else if (col_grant[i])
begin
done_combi[i] = 1'b1;
end
else
begin
done_combi[i] = done[i];
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
done[i] <= done_combi[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Complete logic
//----------------------------------------------------------------------------------------------------
reg [CFG_CTL_TBP_NUM-1:0] partial_vector_combi [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] partial_vector [CFG_CTL_TBP_NUM-1:0];
reg [CFG_CTL_TBP_NUM-1:0] load_rmw_data;
reg [CFG_CTL_TBP_NUM-1:0] all_complete_vector;
reg all_complete;
wire data_rmw_fetch = data_rmw_complete && !all_complete;
// Partial information, to indicate which partial command should receive the current data_rmw_complete
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
partial_vector_combi[i][j] = zero;
end
else
begin
if (load_tbp[i] && (cmd_gen_rmw_partial || cmd_gen_rmw_correct) && cmd_gen_write) // only required for partial write commands
begin
if (!done[j] && valid[j] && rmw[j] && write[j] && !load_rmw_data[j] && !complete_wr[j]) // compare with current valid and not done RMW commands
begin
partial_vector_combi[i][j] = 1'b1;
end
else
begin
partial_vector_combi[i][j] = 1'b0;
end
end
else if (load_rmw_data[j])
begin
partial_vector_combi[i][j] = 1'b0;
end
else
begin
partial_vector_combi[i][j] = partial_vector[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
partial_vector[i][j] <= partial_vector_combi[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
load_rmw_data[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (~|partial_vector_combi[i] && data_rmw_complete)
begin
load_rmw_data[i] <= 1'b1;
end
else
begin
load_rmw_data[i] <= 1'b0;
end
end
end
end
// Indicate that the data for current TBP is complete and ready to be issued
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i])
begin
if (cmd_gen_read)
begin
complete_combi_rd[i] = cmd_gen_complete;
complete_combi_wr[i] = 1'b0;
end
else
begin
complete_combi_rd[i] = 1'b0;
complete_combi_wr[i] = cmd_gen_complete;
end
end
else if (write[i] && !complete[i])
begin
complete_combi_rd[i] = complete_rd[i];
if (cfg_enable_rmw)
begin
complete_combi_wr[i] = load_rmw_data[i];
end
else
begin
complete_combi_wr[i] = data_complete[i];
end
end
else
begin
complete_combi_rd[i] = complete_rd[i];
complete_combi_wr[i] = complete_wr[i];
end
end
end
always @ (*)
begin
complete_combi = complete_combi_rd | complete_combi_wr;
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
complete <= 0;
complete_rd <= 0;
complete_wr <= 0;
end
else
begin
complete <= complete_combi;
complete_rd <= complete_combi_rd;
complete_wr <= complete_combi_wr;
end
end
// To indicate that all TBP has completed, expect non-valid TBP
always @ (*)
begin
all_complete = &all_complete_vector;
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (!valid[i])
begin
all_complete_vector[i] = 1'b1;
end
else
begin
all_complete_vector[i] = complete[i];
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank vector logic
//----------------------------------------------------------------------------------------------------
// This bit vector (same bank vector) is to stop a TBP from requesting activate when another row in the same chip-bank was granted
// SBV stops TBP from requesting activate when there is another same-chip-bank-diff-row was granted
// prevents activate to and activated bank
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
// There is no need to SBV in INTER_BANK case
sbv_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if
(
(load_tbp[i] && !flush_tbp[j] && (activated[j] || activated_combi[j]) && same_chip_bank_diff_row[j]) ||
(activated_combi[j] && valid[i] && pre_calculated_same_chip_bank_diff_row [i][j])
)
// Set SBV to '1' if new TBP is same-chip-bank-diff-row with other existing TBP
// Set SBV to '1' if there is a row_grant or open-row-pass to other existing TBP with same-chip-bank-diff-row
begin
sbv_combi[i][j] = 1'b1;
end
else if (flush_tbp[j] || pch_grant[j] || precharge_tbp[j])
// Set SBV to '0' if there is a flush to other TBP
// Set SBV to '0' if there is a precharge to other TBP
// Set SBV to '0' if there is a precharge all command from sideband
begin
sbv_combi[i][j] = 1'b0;
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
else
begin
sbv_combi[i][j] = sbv[i][j];
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbv[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbv[i] <= ~|sbv_combi[i];
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbv[i][j] <= 1'b0;
end
else
begin
sbv[i][j] <= sbv_combi[i][j];
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Same bank timer vector logic
//----------------------------------------------------------------------------------------------------
// SBTV stops TBP from requesting activate when the timer for same-chip-bank is still running
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_tbp[i])
begin
sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j])
begin
sbvt_combi[i][j] = 1'b0;
end
else if
(
(pch_grant[j] || (col_grant[j] && real_ap[j])) &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when there is a precharge/auto-precharge to same-chip-bank address
begin
sbvt_combi[i][j] = 1'b1;
end
else if
(
precharged[j] && valid[j] &&
(
(load_tbp[i] && same_chip_bank[j]) ||
(valid[i] && pre_calculated_same_chip_bank[i][j])
)
)
// Set to '1' when same-chip-bank address TBP is still in precharge state
begin
sbvt_combi[i][j] = ~row_timer_pre_ready[j];
end
else
begin
sbvt_combi[i][j] = zero;
end
end
else
begin
sbvt_combi[i][j] = sbvt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
shadow_sbvt_combi[i][j] = zero;
end
else if (CFG_DATA_REORDERING_TYPE == "INTER_ROW")
begin
if (flush_shadow_tbp[j])
begin
shadow_sbvt_combi[i][j] = 1'b0;
end
else if (push_tbp[j] && sbvt[i][j])
begin
shadow_sbvt_combi[i][j] = 1'b1;
end
else if (valid[i] && shadow_valid[j] && pre_calculated_same_shadow_chip_bank[i][j])
// Set to 'timer-pre-ready' when own TBP is valid, shadow TBP is valid and same chip-bank address
begin
shadow_sbvt_combi[i][j] = ~shadow_row_timer_pre_ready[j];
end
else
begin
shadow_sbvt_combi[i][j] = shadow_sbvt[i][j];
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
else
begin
shadow_sbvt_combi[i][j] = zero;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= 1'b0;
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
nor_sbvt[i] <= ~|{shadow_sbvt_combi[i], sbvt_combi[i]};
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j) // Hard-coded to '0' for own vector bit, since we only need to know the dependencies for other TBPs not ourself
begin
sbvt[i][j] <= 1'b0;
end
else
begin
sbvt[i][j] <= sbvt_combi[i][j];
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
shadow_sbvt[i][j] <= shadow_sbvt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssb[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssb[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank[i])
begin
ssb[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Seen same bank row logic
//----------------------------------------------------------------------------------------------------
// Indicate that it sees a new TBP which is same-chip-bank-row with current TBP
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
ssbr[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (flush_tbp[i])
begin
ssbr[i] <= 1'b0;
end
else if (load_tbp[j] && valid[i] && same_chip_bank_row[i])
begin
ssbr[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will send transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will pass current TBP information (timing/page) over to other TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
wst_p[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (load_tbp[i]) // Reset back to '0'
begin
wst_p[i] <= 1'b0;
end
else if
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && precharged_combi[i] && done_combi[i]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && precharged_combi[i] ) ||
(!cfg_reorder_data && precharged_combi[i])
)
// Set to '0' when there is a precharge to current TBP, after a precharge, it's not possible to perform open-row-pass anymore
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
begin
wst_p[i] <= 1'b0;
end
else if (open_row_pass_flush[i]) // make sure open-row-pass only asserts for one clock cycle
begin
wst_p[i] <= 1'b0;
end
else if
(
load_tbp[j] && same_chip_bank_row[i] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[i] && !(precharged_combi[i] && done_combi[i])) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [i] && !(precharged_combi[i] )) ||
(!cfg_reorder_data && !ssb[i] && !precharged_combi[i])
)
)
// Set to '1' when there is a new TBP being loaded, with same-chip-bank-row with current TBP
// make sure current TBP is not precharged so that information can be pass over to same-chip-bank-row TBP
// (INTER_ROW) included done_combi because precharge can happen to a newly loaded TBP due to TBP interlock case (see require_pch logic)
// to make sure we're able to open-row-pass a not-done precharged command
// (INTER_BANK) make sure SSB is not set (only set WST once)
// (NON_REORDER) make sure SSB is not set (only set WST once)
begin
wst_p[i] <= 1'b1;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Will receive transfer logic
//----------------------------------------------------------------------------------------------------
// Indicate that it will receive TBP information (timing/page) from other TBP (also tells which TBP it is receiving from)
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if
(
load_tbp[i] && !flush_tbp[j] && valid[j] && same_chip_bank_row[j] &&
(
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_ROW" && !ssbr[j]) ||
( cfg_reorder_data && CFG_DATA_REORDERING_TYPE == "INTER_BANK" && !ssb [j]) ||
(!cfg_reorder_data && !ssb[j])
)
)
// Set to '1' when there is a new TBp being loaded, with same-chip-bank-row with other existing TBP
// provided other TBP is valid and not precharged
// (INTER_BANK) make sure SSB of other TBP is not set, to handle row interrupt case
begin
wrt_combi[i][j] = 1'b1;
end
else if (flush_tbp[j])
begin
wrt_combi[i][j] = 1'b0;
end
else
begin
wrt_combi[i][j] = wrt[i][j];
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
or_wrt [i] = |wrt[i];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
wrt [i] <= 0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
for (j = 0;j < CFG_CTL_TBP_NUM;j = j + 1)
begin
if (i == j)
wrt[i][j] <= 1'b0;
else
wrt[i][j] <= wrt_combi[i][j];
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require flush logic
//----------------------------------------------------------------------------------------------------
// On demand flush selection, command with same chip-bank-diff-row first, we dont want to precharge twice
// if there are none, flush cmd to diff chip-bank, we might have cmd to the same row in tbp already
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_flush[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_CTL_TBP_NUM == 1)
begin
require_flush[i] <= cmd_gen_load | cmd_gen_waiting_to_load;
end
else
begin
if (|flush_tbp) // tbp will not be full on the next clock cycle
begin
require_flush[i] <= 1'b0;
end
else if (int_tbp_full && (cmd_gen_load | cmd_gen_waiting_to_load))
begin
if (same_chip_bank_row[i])
require_flush[i] <= 1'b0;
else
require_flush[i] <= 1'b1;
end
else
begin
require_flush[i] <= 1'b0;
end
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Require precharge logic
//----------------------------------------------------------------------------------------------------
// Precharge request logic, to clear up lockup state in TBP
always @(*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (CFG_DATA_REORDERING_TYPE == "INTER_BANK")
begin
require_pch_combi[i][j] = zero;
end
else
begin
if (i == j)
begin
require_pch_combi[i][j] = 1'b0;
end
else if (activated[i] && !done[i])
begin
if (cpv[i][j] && sbv[j][i])
begin
require_pch_combi[i][j] = 1'b1;
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
else
begin
require_pch_combi[i][j] = 1'b0;
end
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
require_pch[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (flush_tbp[i])
begin
require_pch[i] <= 1'b0;
end
else
begin
// included real_ap since real_ap is part of precharge request (!apvc so that it will deassert pch_req when not needed)
require_pch[i] <= |require_pch_combi[i] | (done[i] & real_ap[i] & !apvc_combi[i]);
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Address/command comparison logic
//----------------------------------------------------------------------------------------------------
// Command comparator
always @ (*)
begin
if (CFG_DISABLE_READ_REODERING) // logic only enabled when parameter is set to '1'
begin
same_command_read = cmd_gen_same_read_cmd;
end
else
begin
same_command_read = {CFG_CTL_TBP_NUM{zero}};
end
end
always @ (*)
begin
same_shadow_command_read = {CFG_CTL_SHADOW_TBP_NUM{zero}};
end
// Address comparator
always @(*)
begin
same_chip_bank = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr;
same_chip_bank_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & cmd_gen_same_row_addr;
same_chip_bank_diff_row = cmd_gen_same_chipsel_addr & cmd_gen_same_bank_addr & ~cmd_gen_same_row_addr;
end
always @ (*)
begin
same_shadow_chip_bank = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr;
same_shadow_chip_bank_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & cmd_gen_same_shadow_row_addr;
same_shadow_chip_bank_diff_row = cmd_gen_same_shadow_chipsel_addr & cmd_gen_same_shadow_bank_addr & ~cmd_gen_same_shadow_row_addr;
end
// Registered version, to improve fMAX
generate
begin
genvar i_tbp;
genvar j_tbp;
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop
for (j_tbp = 0;j_tbp < CFG_CTL_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= same_chip_bank_diff_row [j_tbp];
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= same_chip_bank_row [j_tbp];
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
end
else if (load_tbp [j_tbp])
begin
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] != cmd_gen_row)
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank && row [i_tbp] == cmd_gen_row)
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
if (chipsel [i_tbp] == cmd_gen_chipsel && bank [i_tbp] == cmd_gen_bank)
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
begin
if (row [i_tbp] != row [j_tbp])
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b1;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b1;
end
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_chip_bank_diff_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank_row [i_tbp][j_tbp] <= 1'b0;
pre_calculated_same_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
for (i_tbp = 0;i_tbp < CFG_CTL_TBP_NUM;i_tbp = i_tbp + 1)
begin : i_compare_loop_shadow
for (j_tbp = 0;j_tbp < CFG_CTL_SHADOW_TBP_NUM;j_tbp = j_tbp + 1)
begin : j_compare_loop_shadow
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else
begin
if (load_tbp [i_tbp])
begin
if (push_tbp [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_chip_bank [j_tbp];
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= same_shadow_chip_bank [j_tbp];
end
else if (push_tbp [j_tbp])
begin
if (chipsel [i_tbp] == chipsel [j_tbp] && bank [i_tbp] == bank [j_tbp])
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
else
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
else if (chipsel [i_tbp] == shadow_chipsel [j_tbp] && bank [i_tbp] == shadow_bank [j_tbp])
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b1;
end
else
begin
pre_calculated_same_shadow_chip_bank [i_tbp][j_tbp] <= 1'b0;
end
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------
// Bank specific timer related logic
//----------------------------------------------------------------------------------------------------
// Offset timing paramter to achieve accurate timing gap between commands
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 0;
compare_t_param_act_to_act_less_than_offset <= 0;
compare_t_param_act_to_pch_less_than_offset <= 0;
compare_t_param_rd_to_pch_less_than_offset <= 0;
compare_t_param_wr_to_pch_less_than_offset <= 0;
compare_t_param_pch_to_valid_less_than_offset <= 0;
compare_t_param_rd_ap_to_valid_less_than_offset <= 0;
compare_t_param_wr_ap_to_valid_less_than_offset <= 0;
compare_offset_t_param_act_to_rdwr_less_than_0 <= 0;
compare_offset_t_param_act_to_rdwr_less_than_1 <= 0;
end
else
begin
if (t_param_act_to_rdwr > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_rdwr_less_than_offset <= 1'b1;
end
if (t_param_act_to_act > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_act_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_act_less_than_offset <= 1'b1;
end
if (t_param_act_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_act_to_pch_less_than_offset <= 1'b1;
end
if (t_param_rd_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_to_pch_less_than_offset <= 1'b1;
end
if (t_param_wr_to_pch > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_to_pch_less_than_offset <= 1'b1;
end
if (t_param_pch_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_pch_to_valid_less_than_offset <= 1'b1;
end
if (t_param_rd_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_rd_ap_to_valid_less_than_offset <= 1'b1;
end
if (t_param_wr_ap_to_valid > TBP_COUNTER_OFFSET)
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b0;
end
else
begin
compare_t_param_wr_ap_to_valid_less_than_offset <= 1'b1;
end
if (offset_t_param_act_to_rdwr <= 0)
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_0 <= 1'b0;
end
if (offset_t_param_act_to_rdwr <= 1)
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b1;
end
else
begin
compare_offset_t_param_act_to_rdwr_less_than_1 <= 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
offset_t_param_act_to_rdwr <= 0;
offset_t_param_act_to_act <= 0;
offset_t_param_act_to_pch <= 0;
offset_t_param_rd_to_pch <= 0;
offset_t_param_wr_to_pch <= 0;
offset_t_param_pch_to_valid <= 0;
offset_t_param_rd_ap_to_valid <= 0;
offset_t_param_wr_ap_to_valid <= 0;
end
else
begin
if (!compare_t_param_act_to_rdwr_less_than_offset)
begin
offset_t_param_act_to_rdwr <= t_param_act_to_rdwr - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_rdwr <= 0;
end
if (!compare_t_param_act_to_act_less_than_offset)
begin
offset_t_param_act_to_act <= t_param_act_to_act - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_act <= 0;
end
if (!compare_t_param_act_to_pch_less_than_offset)
begin
offset_t_param_act_to_pch <= t_param_act_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_act_to_pch <= 0;
end
if (!compare_t_param_rd_to_pch_less_than_offset)
begin
offset_t_param_rd_to_pch <= t_param_rd_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_to_pch <= 0;
end
if (!compare_t_param_wr_to_pch_less_than_offset)
begin
offset_t_param_wr_to_pch <= t_param_wr_to_pch - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_to_pch <= 0;
end
if (!compare_t_param_pch_to_valid_less_than_offset)
begin
offset_t_param_pch_to_valid <= t_param_pch_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_pch_to_valid <= 0;
end
if (!compare_t_param_rd_ap_to_valid_less_than_offset)
begin
offset_t_param_rd_ap_to_valid <= t_param_rd_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_rd_ap_to_valid <= 0;
end
if (!compare_t_param_wr_ap_to_valid_less_than_offset)
begin
offset_t_param_wr_ap_to_valid <= t_param_wr_ap_to_valid - TBP_COUNTER_OFFSET;
end
else
begin
offset_t_param_wr_ap_to_valid <= 0;
end
end
end
// Pre-calculated logic to improve timing, for row_timer and trc_timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
compare_t_param_rd_to_pch_greater_than_row_timer [i] <= 1'b0;
compare_t_param_wr_to_pch_greater_than_row_timer [i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (t_param_rd_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_rd_to_pch_greater_than_row_timer[i] <= 1'b0;
end
if (t_param_wr_to_pch > ((row_timer[i] > 1) ? (row_timer[i] - 1'b1) : 0))
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b1;
end
else
begin
compare_t_param_wr_to_pch_greater_than_row_timer[i] <= 1'b0;
end
end
end
end
// Column timer logic
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b0;
col_timer_pre_ready[i] <= 1'b0;
end
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (row_grant[i])
begin
if (compare_t_param_act_to_rdwr_less_than_offset)
begin
col_timer [i] <= 0;
col_timer_ready [i] <= 1'b1;
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer [i] <= offset_t_param_act_to_rdwr;
if (compare_offset_t_param_act_to_rdwr_less_than_0)
begin
col_timer_ready [i] <= 1'b1;
end
else
begin
col_timer_ready [i] <= 1'b0;
end
if (compare_offset_t_param_act_to_rdwr_less_than_1)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
else
begin
if (col_timer[i] != 0)
begin
col_timer[i] <= col_timer[i] - 1'b1;
end
if (col_timer[i] <= 1)
begin
col_timer_ready[i] <= 1'b1;
end
else
begin
col_timer_ready[i] <= 1'b0;
end
if (col_timer[i] <= 2)
begin
col_timer_pre_ready[i] <= 1'b1;
end
else
begin
col_timer_pre_ready[i] <= 1'b0;
end
end
end
end
// log2 result of open-row-pass-flush, to be used during timer information pass
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush[i] = log2(open_row_pass_flush & wrt[i]);
end
end
// Registered version
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
log2_open_row_pass_flush_r[i] <= log2_open_row_pass_flush[i];
end
end
end
// Combined timer logic
// compare between row_timer and trc_timer and take the largest value
// to be used in open_row_pass only
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
combined_timer[i] <= 0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (CFG_REG_GRANT == 0 && open_row_pass_r[i]) // for QR controller only
begin
if (col_grant[i])
begin
if (row_timer_combi[i] > combined_timer[log2_open_row_pass_flush_r[i]])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
combined_timer[i] <= (combined_timer[log2_open_row_pass_flush_r[i]] > 1'b1) ? (combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1) : 1'b1;
end
end
else
begin
if (row_timer_combi[i] > trc_timer[i])
begin
combined_timer[i] <= row_timer_combi[i];
end
else
begin
combined_timer[i] <= (trc_timer[i] > 1'b1) ? (trc_timer[i] - 1'b1) : 1'b1;
end
end
end
end
end
// Row timer logic
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (trc_timer[i] <= 1)
begin
trc_timer_pre_ready_combi[i] = 1'b1;
end
else
begin
trc_timer_pre_ready_combi[i] = 1'b0;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
trc_timer [i] <= 0;
trc_timer_ready [i] <= 1'b1;
trc_timer_pre_ready[i] <= 1'b1;
end
// We need to update the timer as soon as possible when CFG_REG_GRANT == 0
// because after open-row-pass, row grant can happen on the next clock cycle
else if (CFG_REG_GRANT == 0 && open_row_pass[i])
begin
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if
(open_row_pass_r[i])
begin
trc_timer [i] <= combined_timer[log2_open_row_pass_flush_r[i]] - 1'b1;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else if (act_grant[i])
begin
trc_timer [i] <= offset_t_param_act_to_act;
trc_timer_ready [i] <= 1'b0;
trc_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (trc_timer[i] != 0)
begin
trc_timer[i] <= trc_timer[i] - 1'b1;
end
if (trc_timer[i] <= 1)
begin
trc_timer_ready[i] <= 1'b1;
end
if (trc_timer[i] <= 2)
begin
trc_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (rd_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_rd_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_rd_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_rd_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_rd_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else if (wr_grant[i])
begin
if (real_ap[i])
begin
row_timer_combi[i] = offset_t_param_wr_ap_to_valid;
end
else
begin
if
(
(CFG_REG_GRANT == 1 && compare_t_param_wr_to_pch_greater_than_row_timer[i]) ||
(CFG_REG_GRANT == 0 && t_param_wr_to_pch > row_timer[i])
)
begin
row_timer_combi[i] = offset_t_param_wr_to_pch;
end
else
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
end
end
else
begin
if (row_timer[i] != 0)
begin
row_timer_combi[i] = row_timer[i] - 1'b1;
end
else
begin
row_timer_combi[i] = 0;
end
end
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
// Reset row_timer after push
if (push_tbp[i])
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else if (act_grant[i])
begin
if (compare_t_param_act_to_pch_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRAS after precharge command
row_timer [i] <= offset_t_param_act_to_pch;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (pch_grant[i])
begin
if (compare_t_param_pch_to_valid_less_than_offset)
begin
row_timer [i] <= 0;
row_timer_ready [i] <= 1'b1;
row_timer_pre_ready[i] <= 1'b1;
end
else
begin
// Load tRP after precharge command
row_timer [i] <= offset_t_param_pch_to_valid;
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
end
else if (col_grant[i])
begin
row_timer [i] <= row_timer_combi[i];
row_timer_ready [i] <= 1'b0;
row_timer_pre_ready[i] <= 1'b0;
end
else
begin
if (row_timer[i] != 0)
begin
row_timer[i] <= row_timer[i] - 1'b1;
end
if (row_timer[i] <= 1)
begin
row_timer_ready[i] <= 1'b1;
end
if (row_timer[i] <= 2)
begin
row_timer_pre_ready[i] <= 1'b1;
end
end
end
end
end
// Logic to let precharge request logic that it is ready to request now
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
pch_ready[i] <= 1'b0;
end
end
else
begin
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (open_row_pass[i] || open_row_pass_r[i] || pch_grant[i] || col_grant[i])
// disable pch_ready after open-row-pass and grant
// since precharge is not needed immediately after TBP is loaded
begin
pch_ready[i] <= 1'b0;
end
else if (row_timer_pre_ready[i] && ((trc_timer_pre_ready[i] && open_row_passed[i]) || !open_row_passed[i]) && !precharged[i])
// disable pch_ready if current TBP is precharged
// only compare with trc_timer if TBP is an open_row_pass command
begin
pch_ready[i] <= 1'b1;
end
else
begin
pch_ready[i] <= 1'b0;
end
end
end
end
// Logic to let sideband know which chip contains active banks
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_bank_closed[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i && valid[j])
begin
if (sb_tbp_precharge_all[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (precharged_combi[j])
begin
int_bank_closed[i][j] <= 1'b1;
end
else if (activated_combi[j])
begin
int_bank_closed[i][j] <= 1'b0;
end
end
else
begin
int_bank_closed[i][j] <= 1'b1; // else default to '0'
end
end
end
end
end
// Logic to let sideband know which chip contains running timer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (chipsel[j] == i)
begin
if (col_grant[j] || row_grant[j])
begin
int_timer_ready[i][j] <= 1'b0;
end
else if (trc_timer_pre_ready[j] && row_timer_pre_ready[j])
begin
int_timer_ready[i][j] <= 1'b1;
end
else
begin
int_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
end
else
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
for (j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (CFG_ENABLE_SHADOW_TBP)
begin
if (shadow_chipsel[j] == i)
begin
if (push_tbp[j])
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
else if (shadow_row_timer_pre_ready[j])
begin
int_shadow_timer_ready[i][j] <= 1'b1;
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b0;
end
end
else
begin
int_shadow_timer_ready[i][j] <= 1'b1; // else default to '1'
end
end
else
begin
int_shadow_timer_ready[i][j] <= one;
end
end
end
end
end
always @ (*)
begin
for (i=0; i<CFG_MEM_IF_CHIP; i=i+1)
begin
bank_closed[i] = &int_bank_closed[i];
timer_ready[i] = &{int_shadow_timer_ready[i], int_timer_ready[i]};
end
end
//----------------------------------------------------------------------------------------------------
// Age logic
//----------------------------------------------------------------------------------------------------
// To tell the current age of each TBP entry
// so that arbiter will be able to grant the oldest entry (if there is a tie-break)
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
age[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
for (j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
if (i == j)
begin
age[i][j] <= 1'b0;
end
else
begin
if (load_tbp[i])
if (!flush_tbp[j] && (valid[j]))
age[i][j] <= 1'b1;
else
age[i][j] <= 1'b0;
else if (flush_tbp[j])
age[i][j] <= 1'b0;
end
end
end
end
//----------------------------------------------------------------------------------------------------
// Starvation logic
//----------------------------------------------------------------------------------------------------
// Logic will increments when there is a col_grant to other TBP
// will cause priority to be asserted when the count reaches starvation threshold
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
starvation[i] <= 0;
else
for (i=0; i<CFG_CTL_TBP_NUM; i=i+1)
begin
if (load_tbp[i] || done[i]) // stop starvation count when the current TBP is done
starvation[i] <= 0;
else if (|col_grant && starvation[i] < cfg_starve_limit)
starvation[i] <= starvation[i]+1'b1;
end
end
//----------------------------------------------------------------------------------------------------
// Burst chop logic
//----------------------------------------------------------------------------------------------------
// Logic to determine whether we will issue burst chop in DDR3 mode only
generate
begin
if (CFG_DWIDTH_RATIO == 2)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size <= 2'd2 && cmd_gen_col [(CFG_DWIDTH_RATIO / 2)] == 1'b0)
burst_chop [i] <= 1'b1;
else if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 4)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
if (cfg_type == `MMR_TYPE_DDR3)
begin
if (load_tbp [i])
begin
if (cmd_gen_size == 1'b1)
burst_chop [i] <= 1'b1;
else
burst_chop [i] <= 1'b0;
end
end
else
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
else if (CFG_DWIDTH_RATIO == 8)
begin
// Burst chop is not available in quarter rate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
else
begin
for (i = 0;i < CFG_CTL_TBP_NUM;i = i + 1)
begin
burst_chop [i] <= 1'b0;
end
end
end
end
end
endgenerate
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
begin
log2 = i + 1;
end
end
endfunction
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: Mux_8x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_8x1(
//INPUTS
input wire [2:0] select,
input wire [7:0] ch_0,
input wire [7:0] ch_1,
input wire [7:0] ch_2,
input wire [7:0] ch_3,
input wire [7:0] ch_4,
input wire [7:0] ch_5,
input wire [7:0] ch_6,
input wire [7:0] ch_7,
//OUTPUTS
output reg [7:0] data_out
);
always @*
begin
case(select)
3'b111: data_out = ch_0;
3'b110: data_out = ch_1;
3'b101: data_out = ch_2;
3'b100: data_out = ch_3;
3'b011: data_out = ch_4;
3'b010: data_out = ch_5;
3'b001: data_out = ch_6;
3'b000: data_out = ch_7;
default : data_out = ch_0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
`define SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_SYMBOL_V
`define SKY130_FD_SC_LP__ISO0N_SYMBOL_V
/**
* iso0n: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_SYMBOL_V
|
module arbiter (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock,reset,req_0,req_1;
//-------------Output Ports----------------------------
output gnt_0,gnt_1;
//-------------Input ports Data Type-------------------
wire clock,reset,req_0,req_1;
//-------------Output Ports Data Type------------------
reg gnt_0,gnt_1;
//-------------Internal Constants--------------------------
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//-------------Internal Variables---------------------------
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//----------Code startes Here------------------------
always @ (state or req_0 or req_1)
begin : FSM_COMBO
next_state = 3'b000;
case(state)
IDLE : if (req_0 == 1'b1) begin
next_state = GNT0;
end else if (req_1 == 1'b1) begin
next_state= GNT1;
end else begin
next_state = IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
next_state = GNT0;
end else begin
next_state = IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
next_state = GNT1;
end else begin
next_state = IDLE;
end
default : next_state = IDLE;
endcase
end
//----------Seq Logic-----------------------------
always @ (posedge clock)
begin : FSM_SEQ
if (reset == 1'b1) begin
state <= IDLE;
end else begin
state <= next_state;
end
end
//----------Output Logic-----------------------------
always @ (state)
begin : OUTPUT_LOGIC
case(state)
IDLE : begin
gnt_0 = 1'b0;
gnt_1 = 1'b0;
end
GNT0 : begin
gnt_0 = 1'b1;
gnt_1 = 1'b0;
end
GNT1 : begin
gnt_0 = 1'b0;
gnt_1 = 1'b1;
end
default : begin
gnt_0 = 1'b0;
gnt_1 = 1'b0;
end
endcase
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module arbiter
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Resistor to VCC
// /___/ /\ Filename : PULLUP.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:32 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
`celldefine
module PULLUP (O);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
wire A;
pullup (A);
buf (weak0,weak1) #(100,100) (O,A);
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__MUX2I_PP_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_PP_BLACKBOX_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.