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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_hvl__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hvl__sdfxbp (
Q ,
Q_N,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hvl__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign cond1 = ( SCE_delayed === 1'b0 );
assign cond2 = ( SCE_delayed === 1'b1 );
assign cond3 = ( D_delayed !== SCD_delayed );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXBP_BEHAVIORAL_V
|
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// ============================================================================
//
// Major Functions: SoCKit_Default
//
// ============================================================================
// Revision History :
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| xinxian :| 04/02/13 :| Initial Revision
// ============================================================================
//`define ENABLE_DDR3
//`define ENABLE_HPS
//`define ENABLE_HSMC_XCVR
module SoCKit_top(
///////////AUD/////////////
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_I2C_SCLK,
AUD_I2C_SDAT,
AUD_MUTE,
AUD_XCK,
`ifdef ENABLE_DDR3
/////////DDR3/////////
DDR3_A,
DDR3_BA,
DDR3_CAS_n,
DDR3_CKE,
DDR3_CK_n,
DDR3_CK_p,
DDR3_CS_n,
DDR3_DM,
DDR3_DQ,
DDR3_DQS_n,
DDR3_DQS_p,
DDR3_ODT,
DDR3_RAS_n,
DDR3_RESET_n,
DDR3_RZQ,
DDR3_WE_n,
`endif /*ENABLE_DDR3*/
/////////FAN/////////
FAN_CTRL,
`ifdef ENABLE_HPS
/////////HPS/////////
HPS_CLOCK_25,
HPS_CLOCK_50,
HPS_CONV_USB_n,
HPS_DDR3_A,
HPS_DDR3_BA,
HPS_DDR3_CAS_n,
HPS_DDR3_CKE,
HPS_DDR3_CK_n,
HPS_DDR3_CK_p,
HPS_DDR3_CS_n,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_n,
HPS_DDR3_DQS_p,
HPS_DDR3_ODT,
HPS_DDR3_RAS_n,
HPS_DDR3_RESET_n,
HPS_DDR3_RZQ,
HPS_DDR3_WE_n,
HPS_ENET_GTX_CLK,
HPS_ENET_INT_n,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RESET_n,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
HPS_GSENSOR_INT,
HPS_I2C_CLK,
HPS_I2C_SDA,
HPS_KEY,
HPS_LCM_D_C,
HPS_LCM_RST_N,
HPS_LCM_SPIM_CLK,
HPS_LCM_SPIM_MISO,
HPS_LCM_SPIM_MOSI,
HPS_LCM_SPIM_SS,
HPS_LED,
HPS_LTC_GPIO,
HPS_RESET_n,
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
HPS_SW,
HPS_UART_RX,
HPS_UART_TX,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_RESET_PHY,
HPS_USB_STP,
HPS_WARM_RST_n,
`endif /*ENABLE_HPS*/
/////////HSMC/////////
HSMC_CLKIN_n,
HSMC_CLKIN_p,
HSMC_CLKOUT_n,
HSMC_CLKOUT_p,
HSMC_CLK_IN0,
HSMC_CLK_OUT0,
HSMC_D,
`ifdef ENABLE_HSMC_XCVR
HSMC_GXB_RX_p,
HSMC_GXB_TX_p,
HSMC_REF_CLK_p,
`endif
HSMC_RX_n,
HSMC_RX_p,
HSMC_SCL,
HSMC_SDA,
HSMC_TX_n,
HSMC_TX_p,
/////////IRDA/////////
IRDA_RXD,
/////////KEY/////////
KEY,
/////////LED/////////
LED,
/////////OSC/////////
OSC_50_B3B,
OSC_50_B4A,
OSC_50_B5B,
OSC_50_B8A,
/////////PCIE/////////
PCIE_PERST_n,
PCIE_WAKE_n,
/////////RESET/////////
RESET_n,
/////////SI5338/////////
SI5338_SCL,
SI5338_SDA,
/////////SW/////////
SW,
/////////TEMP/////////
TEMP_CS_n,
TEMP_DIN,
TEMP_DOUT,
TEMP_SCLK,
/////////USB/////////
USB_B2_CLK,
USB_B2_DATA,
USB_EMPTY,
USB_FULL,
USB_OE_n,
USB_RD_n,
USB_RESET_n,
USB_SCL,
USB_SDA,
USB_WR_n,
/////////VGA/////////
VGA_B,
VGA_BLANK_n,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_n,
VGA_VS,
///////////hps//////////
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_qspi_inst_IO0,
hps_io_hps_io_qspi_inst_IO1,
hps_io_hps_io_qspi_inst_IO2,
hps_io_hps_io_qspi_inst_IO3,
hps_io_hps_io_qspi_inst_SS0,
hps_io_hps_io_qspi_inst_CLK,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_spim0_inst_CLK,
hps_io_hps_io_spim0_inst_MOSI,
hps_io_hps_io_spim0_inst_MISO,
hps_io_hps_io_spim0_inst_SS0,
hps_io_hps_io_spim1_inst_CLK,
hps_io_hps_io_spim1_inst_MOSI,
hps_io_hps_io_spim1_inst_MISO,
hps_io_hps_io_spim1_inst_SS0,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
hps_io_hps_io_i2c1_inst_SDA,
hps_io_hps_io_i2c1_inst_SCL,
hps_io_hps_io_gpio_inst_GPIO00
);
//=======================================================
// PORT declarations
//=======================================================
///////// AUD /////////
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_I2C_SCLK;
inout AUD_I2C_SDAT;
output AUD_MUTE;
output AUD_XCK;
`ifdef ENABLE_DDR3
///////// DDR3 /////////
output [14:0] DDR3_A;
output [2:0] DDR3_BA;
output DDR3_CAS_n;
output DDR3_CKE;
output DDR3_CK_n;
output DDR3_CK_p;
output DDR3_CS_n;
output [3:0] DDR3_DM;
inout [31:0] DDR3_DQ;
inout [3:0] DDR3_DQS_n;
inout [3:0] DDR3_DQS_p;
output DDR3_ODT;
output DDR3_RAS_n;
output DDR3_RESET_n;
input DDR3_RZQ;
output DDR3_WE_n;
`endif /*ENABLE_DDR3*/
///////// FAN /////////
output FAN_CTRL;
`ifdef ENABLE_HPS
///////// HPS /////////
input HPS_CLOCK_25;
input HPS_CLOCK_50;
input HPS_CONV_USB_n;
output [14:0] HPS_DDR3_A;
output [2:0] HPS_DDR3_BA;
output HPS_DDR3_CAS_n;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_n;
output HPS_DDR3_CK_p;
output HPS_DDR3_CS_n;
output [3:0] HPS_DDR3_DM;
inout [31:0] HPS_DDR3_DQ;
inout [3:0] HPS_DDR3_DQS_n;
inout [3:0] HPS_DDR3_DQS_p;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_n;
output HPS_DDR3_RESET_n;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_n;
input HPS_ENET_GTX_CLK;
input HPS_ENET_INT_n;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
output HPS_ENET_RESET_n;
input HPS_ENET_RX_CLK;
input [3:0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [3:0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
inout [3:0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
input HPS_GSENSOR_INT;
inout HPS_I2C_CLK;
inout HPS_I2C_SDA;
inout [3:0] HPS_KEY;
output HPS_LCM_D_C;
output HPS_LCM_RST_N;
input HPS_LCM_SPIM_CLK;
inout HPS_LCM_SPIM_MISO;
output HPS_LCM_SPIM_MOSI;
output HPS_LCM_SPIM_SS;
output [3:0] HPS_LED;
inout HPS_LTC_GPIO;
input HPS_RESET_n;
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [3:0] HPS_SD_DATA;
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
output HPS_SPIM_SS;
input [3:0] HPS_SW;
input HPS_UART_RX;
output HPS_UART_TX;
input HPS_USB_CLKOUT;
inout [7:0] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_RESET_PHY;
output HPS_USB_STP;
input HPS_WARM_RST_n;
`endif /*ENABLE_HPS*/
///////// HSMC /////////
input [2:1] HSMC_CLKIN_n;
input [2:1] HSMC_CLKIN_p;
output [2:1] HSMC_CLKOUT_n;
output [2:1] HSMC_CLKOUT_p;
input HSMC_CLK_IN0;
output HSMC_CLK_OUT0;
inout [3:0] HSMC_D;
`ifdef ENABLE_HSMC_XCVR
input [7:0] HSMC_GXB_RX_p;
output [7:0] HSMC_GXB_TX_p;
input HSMC_REF_CLK_p;
`endif
inout [16:0] HSMC_RX_n;
inout [16:0] HSMC_RX_p;
output HSMC_SCL;
inout HSMC_SDA;
inout [16:0] HSMC_TX_n;
inout [16:0] HSMC_TX_p;
///////// IRDA /////////
input IRDA_RXD;
///////// KEY /////////
input [3:0] KEY;
///////// LED /////////
output [3:0] LED;
///////// OSC /////////
input OSC_50_B3B;
input OSC_50_B4A;
input OSC_50_B5B;
input OSC_50_B8A;
///////// PCIE /////////
input PCIE_PERST_n;
input PCIE_WAKE_n;
///////// RESET /////////
input RESET_n;
///////// SI5338 /////////
inout SI5338_SCL;
inout SI5338_SDA;
///////// SW /////////
input [3:0] SW;
///////// TEMP /////////
output TEMP_CS_n;
output TEMP_DIN;
input TEMP_DOUT;
output TEMP_SCLK;
///////// USB /////////
input USB_B2_CLK;
inout [7:0] USB_B2_DATA;
output USB_EMPTY;
output USB_FULL;
input USB_OE_n;
input USB_RD_n;
input USB_RESET_n;
inout USB_SCL;
inout USB_SDA;
input USB_WR_n;
///////// VGA /////////
output [7:0] VGA_B;
output VGA_BLANK_n;
output VGA_CLK;
output [7:0] VGA_G;
output VGA_HS;
output [7:0] VGA_R;
output VGA_SYNC_n;
output VGA_VS;
/////////hps pin///////
output wire [14:0] memory_mem_a;
output wire [2:0] memory_mem_ba;
output wire memory_mem_ck;
output wire memory_mem_ck_n;
output wire memory_mem_cke;
output wire memory_mem_cs_n;
output wire memory_mem_ras_n;
output wire memory_mem_cas_n;
output wire memory_mem_we_n;
output wire memory_mem_reset_n;
inout wire [31:0] memory_mem_dq;
inout wire [3:0] memory_mem_dqs;
inout wire [3:0] memory_mem_dqs_n;
output wire memory_mem_odt;
output wire [3:0] memory_mem_dm;
input wire memory_oct_rzqin;
output wire hps_io_hps_io_emac1_inst_TX_CLK;
output wire hps_io_hps_io_emac1_inst_TXD0;
output wire hps_io_hps_io_emac1_inst_TXD1;
output wire hps_io_hps_io_emac1_inst_TXD2;
output wire hps_io_hps_io_emac1_inst_TXD3;
input wire hps_io_hps_io_emac1_inst_RXD0;
inout wire hps_io_hps_io_emac1_inst_MDIO;
output wire hps_io_hps_io_emac1_inst_MDC;
input wire hps_io_hps_io_emac1_inst_RX_CTL;
output wire hps_io_hps_io_emac1_inst_TX_CTL;
input wire hps_io_hps_io_emac1_inst_RX_CLK;
input wire hps_io_hps_io_emac1_inst_RXD1;
input wire hps_io_hps_io_emac1_inst_RXD2;
input wire hps_io_hps_io_emac1_inst_RXD3;
inout wire hps_io_hps_io_qspi_inst_IO0;
inout wire hps_io_hps_io_qspi_inst_IO1;
inout wire hps_io_hps_io_qspi_inst_IO2;
inout wire hps_io_hps_io_qspi_inst_IO3;
output wire hps_io_hps_io_qspi_inst_SS0;
output wire hps_io_hps_io_qspi_inst_CLK;
inout wire hps_io_hps_io_sdio_inst_CMD;
inout wire hps_io_hps_io_sdio_inst_D0;
inout wire hps_io_hps_io_sdio_inst_D1;
output wire hps_io_hps_io_sdio_inst_CLK;
inout wire hps_io_hps_io_sdio_inst_D2;
inout wire hps_io_hps_io_sdio_inst_D3;
inout wire hps_io_hps_io_usb1_inst_D0;
inout wire hps_io_hps_io_usb1_inst_D1;
inout wire hps_io_hps_io_usb1_inst_D2;
inout wire hps_io_hps_io_usb1_inst_D3;
inout wire hps_io_hps_io_usb1_inst_D4;
inout wire hps_io_hps_io_usb1_inst_D5;
inout wire hps_io_hps_io_usb1_inst_D6;
inout wire hps_io_hps_io_usb1_inst_D7;
input wire hps_io_hps_io_usb1_inst_CLK;
output wire hps_io_hps_io_usb1_inst_STP;
input wire hps_io_hps_io_usb1_inst_DIR;
input wire hps_io_hps_io_usb1_inst_NXT;
output wire hps_io_hps_io_spim0_inst_CLK;
output wire hps_io_hps_io_spim0_inst_MOSI;
input wire hps_io_hps_io_spim0_inst_MISO;
output wire hps_io_hps_io_spim0_inst_SS0;
output wire hps_io_hps_io_spim1_inst_CLK;
output wire hps_io_hps_io_spim1_inst_MOSI;
input wire hps_io_hps_io_spim1_inst_MISO;
output wire hps_io_hps_io_spim1_inst_SS0;
input wire hps_io_hps_io_uart0_inst_RX;
output wire hps_io_hps_io_uart0_inst_TX;
inout wire hps_io_hps_io_i2c1_inst_SDA;
inout wire hps_io_hps_io_i2c1_inst_SCL;
inout wire hps_io_hps_io_gpio_inst_GPIO00;
//=======================================================
// REG/WIRE declarations
//=======================================================
// For Audio CODEC
wire AUD_CTRL_CLK; // For Audio Controller
reg [31:0] Cont;
wire VGA_CTRL_CLK;
wire [9:0] mVGA_R;
wire [9:0] mVGA_G;
wire [9:0] mVGA_B;
wire [19:0] mVGA_ADDR;
wire DLY_RST;
// For VGA Controller
wire mVGA_CLK;
wire [9:0] mRed;
wire [9:0] mGreen;
wire [9:0] mBlue;
wire VGA_Read; // VGA data request
wire [9:0] recon_VGA_R;
wire [9:0] recon_VGA_G;
wire [9:0] recon_VGA_B;
// For Down Sample
wire [3:0] Remain;
wire [9:0] Quotient;
wire AUD_MUTE;
// Drive the LEDs with the switches
assign LED = SW;
// Make the FPGA reset cause an HPS reset
reg [19:0] hps_reset_counter = 20'h0;
reg hps_fpga_reset_n = 0;
always @(posedge OSC_50_B4A) begin
if (hps_reset_counter == 20'h ffffff) hps_fpga_reset_n <= 1;
hps_reset_counter <= hps_reset_counter + 1;
end
ik_swift_hps u0 (
.clk_clk (OSC_50_B4A), // clk.clk
.reset_reset_n (hps_fpga_reset_n), // reset.reset_n
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ba (memory_mem_ba), // .mem_ba
.memory_mem_ck (memory_mem_ck), // .mem_ck
.memory_mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.memory_mem_cke (memory_mem_cke), // .mem_cke
.memory_mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.memory_mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.memory_mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.memory_mem_we_n (memory_mem_we_n), // .mem_we_n
.memory_mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.memory_mem_dq (memory_mem_dq), // .mem_dq
.memory_mem_dqs (memory_mem_dqs), // .mem_dqs
.memory_mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.memory_mem_odt (memory_mem_odt), // .mem_odt
.memory_mem_dm (memory_mem_dm), // .mem_dm
.memory_oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_hps_io_emac1_inst_TX_CLK (hps_io_hps_io_emac1_inst_TX_CLK), // .hps_0_hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_hps_io_emac1_inst_TXD0 (hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_hps_io_emac1_inst_TXD1 (hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_hps_io_emac1_inst_TXD2 (hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_hps_io_emac1_inst_TXD3 (hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_hps_io_emac1_inst_RXD0 (hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_hps_io_emac1_inst_MDIO (hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_hps_io_emac1_inst_MDC (hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_hps_io_emac1_inst_RX_CTL (hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_hps_io_emac1_inst_TX_CTL (hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_hps_io_emac1_inst_RX_CLK (hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_hps_io_emac1_inst_RXD1 (hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_hps_io_emac1_inst_RXD2 (hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_hps_io_emac1_inst_RXD3 (hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_hps_io_qspi_inst_IO0 (hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_hps_io_qspi_inst_IO1 (hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_hps_io_qspi_inst_IO2 (hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_hps_io_qspi_inst_IO3 (hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_hps_io_qspi_inst_SS0 (hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_hps_io_qspi_inst_CLK (hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_hps_io_sdio_inst_CMD (hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_hps_io_sdio_inst_D0 (hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_hps_io_sdio_inst_D1 (hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_hps_io_sdio_inst_CLK (hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_hps_io_sdio_inst_D2 (hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_hps_io_sdio_inst_D3 (hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_hps_io_usb1_inst_D0 (hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_hps_io_usb1_inst_D1 (hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_hps_io_usb1_inst_D2 (hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_hps_io_usb1_inst_D3 (hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_hps_io_usb1_inst_D4 (hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_hps_io_usb1_inst_D5 (hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_hps_io_usb1_inst_D6 (hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_hps_io_usb1_inst_D7 (hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_hps_io_usb1_inst_CLK (hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_hps_io_usb1_inst_STP (hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_hps_io_usb1_inst_DIR (hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_hps_io_usb1_inst_NXT (hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_hps_io_spim0_inst_CLK (hps_io_hps_io_spim0_inst_CLK), // .hps_io_spim0_inst_CLK
.hps_io_hps_io_spim0_inst_MOSI (hps_io_hps_io_spim0_inst_MOSI), // .hps_io_spim0_inst_MOSI
.hps_io_hps_io_spim0_inst_MISO (hps_io_hps_io_spim0_inst_MISO), // .hps_io_spim0_inst_MISO
.hps_io_hps_io_spim0_inst_SS0 (hps_io_hps_io_spim0_inst_SS0), // .hps_io_spim0_inst_SS0
.hps_io_hps_io_spim1_inst_CLK (hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_hps_io_spim1_inst_MOSI (hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_hps_io_spim1_inst_MISO (hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_hps_io_spim1_inst_SS0 (hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_hps_io_uart0_inst_RX (hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_hps_io_uart0_inst_TX (hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_hps_io_i2c1_inst_SDA (hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_hps_io_i2c1_inst_SCL (hps_io_hps_io_i2c1_inst_SCL) // .hps_io_i2c1_inst_SCL
);
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Router for RPC network, protocol version 3
High level architecture: grid of stars.
Each router peers with other routers to the north/south/east/west, and
has up to 256 IP cores attached to its crossbar.
All networks must a router at (0,0).
The network must be convex (no internal cutouts allowed).
*/
module RPCv3Router
#(
//Data width (must be one of 16, 32, 64, 128).
parameter CORE_DATA_WIDTH = 32,
//Configuration of this router's child port(s)
//1: one child interface with 256 addresses, goes to a debug bridge / soft CPU etc
//0: up to 256 child interfaces with one address each, goes to IP cores
parameter CHILD_IS_TRUNK = 1'b0,
//Number of child ports (must be 1 for CHILD_IS_TRUNK = 1)
//Must be <= 256.
parameter CHILD_COUNT = 4,
//Width of the bus going to each child node.
//8 bits per link, must be 16/32/64/128.
parameter CHILD_DATA_WIDTH = 32'h20202020,
//Bit indicating if we have a neighbor in each direction. The transceiver is optimized out.
//TODO: Return RPC_TYPE_HOST_UNREACH to any traffic sent in that direction
//Concatenated {north, south, east, west}
parameter NEIGHBOR_PRESENT = {4'b1111},
//Width of the bus going to each router, or zero if no router in that direction.
//8 bits per link, must be 16/32/64/128.
//Concatenated {north, south, east, west}
parameter NEIGHBOR_DATA_WIDTH = 32'h20202020,
//Coordinates of this router in the grid.
//The base address of this router is {X_POS, Y_POS, 8'h00}.
//North = positive Y
//East = positive X
parameter X_POS = 4'h0,
parameter Y_POS = 4'h0
)
(
//Internal clock (also used for all links, for now)
input wire clk,
//Interfaces to neighboring routers. Concatenated {north, south, east, west}
//Declare all links 128 bits wide and let unused bits get optimized out
output wire[3:0] neighbor_tx_en,
output wire[511:0] neighbor_tx_data,
input wire[3:0] neighbor_tx_ready,
input wire[3:0] neighbor_rx_en,
input wire[511:0] neighbor_rx_data,
output wire[3:0] neighbor_rx_ready,
//Interfaces to child nodes.
//Declare all links 128 bits wide and let unused bits get optimized out
output wire[CHILD_COUNT-1 : 0] child_tx_en,
output wire[CHILD_COUNT*128 - 1 : 0] child_tx_data,
input wire[CHILD_COUNT-1 : 0] child_tx_ready,
input wire[CHILD_COUNT-1 : 0] child_rx_en,
input wire[CHILD_COUNT*128 - 1 : 0] child_rx_data,
output wire[CHILD_COUNT-1 : 0] child_rx_ready
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Compute a few useful constants
//Number of clocks in one message through the core
localparam CORE_WORD_COUNT = 128 / CORE_DATA_WIDTH;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Synthesis-time sanity checking
initial begin
//Must have exactly 1 child if we're a trunk
if(CHILD_IS_TRUNK) begin
if(CHILD_COUNT != 1) begin
$display("ERROR: RPCv3Router: must have only one child if CHILD_IS_TRUNK is set");
$finish;
end
end
//Must have <256 children otherwise
else if(CHILD_COUNT > 256) begin
$display("ERROR: RPCv3Router: must have <256 children");
$finish;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receivers and FIFOs for neighbor ports
wire[3:0] neighbor_fifo_rd;
wire[3:0] neighbor_fifo_empty;
wire[CORE_DATA_WIDTH*4 - 1:0] neighbor_fifo_dout;
wire[23:0] neighbor_fifo_rsize;
genvar i;
generate
for(i=0; i<4; i=i+1) begin : neighbor_rxs
if(NEIGHBOR_PRESENT[i]) begin
//Bus from receiver to FIFO
wire fifo_space_available;
wire[5:0] fifo_wr_size;
wire fifo_wr_en;
wire[CORE_DATA_WIDTH-1:0] fifo_wr_data;
//True if there is enough room in the FIFO for one entire packet
assign fifo_space_available = (fifo_wr_size >= CORE_WORD_COUNT);
//Receiver pushes data directly to FIFO.
//Ignore packet start/done signals, we only care about the data bus.
//Receiver is proven to never send partial packets, so we can't lose sync!
RPCv3RouterReceiver #(
.IN_DATA_WIDTH(NEIGHBOR_DATA_WIDTH[i*8 +: 8]),
.OUT_DATA_WIDTH(CORE_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(neighbor_rx_en[i]),
.rpc_rx_data(neighbor_rx_data[i*128 +: NEIGHBOR_DATA_WIDTH[i*8 +: 8] ] ),
.rpc_rx_ready(neighbor_rx_ready[i]),
.rpc_fab_rx_space_available(fifo_space_available),
.rpc_fab_rx_packet_start(),
.rpc_fab_rx_data_valid(fifo_wr_en),
.rpc_fab_rx_data(fifo_wr_data),
.rpc_fab_rx_packet_done()
);
SingleClockShiftRegisterFifo #(
.WIDTH(CORE_DATA_WIDTH),
.DEPTH(32),
.OUT_REG(1)
) rx_fifo (
.clk(clk),
.wr(fifo_wr_en),
.din(fifo_wr_data),
.rd(neighbor_fifo_rd[i]),
.dout(neighbor_fifo_dout[i*CORE_DATA_WIDTH +: CORE_DATA_WIDTH]),
.overflow(), //ignored, can never under/overflow b/c of receiver flow control
.underflow(),
.empty(neighbor_fifo_empty[i]),
.full(),
.rsize(neighbor_fifo_rsize[6*i +: 6]),
.wsize(fifo_wr_size),
.reset(1'b0) //never reset the fifo
);
end
//No neighbor? Tie everything off to zero
else begin
assign neighbor_fifo_empty[i] = 1;
assign neighbor_fifo_rsize[i*6 +: 6] = 0;
assign neighbor_fifo_dout[i*CORE_DATA_WIDTH +: CORE_DATA_WIDTH] = 0;
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receivers and FIFOs for child ports
wire[CHILD_COUNT-1:0] child_fifo_rd;
wire[CHILD_COUNT-1:0] child_fifo_empty;
wire[CHILD_COUNT*CORE_DATA_WIDTH - 1:0] child_fifo_dout;
wire[CHILD_COUNT*6-1:0] child_fifo_rsize;
generate
for(i=0; i<CHILD_COUNT; i=i+1) begin : child_rxs
//Bus from receiver to FIFO
wire fifo_space_available;
wire[5:0] fifo_wr_size;
wire fifo_wr_en;
wire[CORE_DATA_WIDTH-1:0] fifo_wr_data;
//True if there is enough room in the FIFO for one entire packet
assign fifo_space_available = (fifo_wr_size >= CHILD_DATA_WIDTH[i*8 +: 8]);
//Receiver pushes data directly to FIFO.
//Ignore packet start/done signals, we only care about the data bus.
//Receiver is proven to never send partial packets, so we can't lose sync!
RPCv3RouterReceiver #(
.IN_DATA_WIDTH(CHILD_DATA_WIDTH[i*8 +: 8]),
.OUT_DATA_WIDTH(CORE_DATA_WIDTH)
) rxvr (
.clk(clk),
.rpc_rx_en(child_rx_en[i]),
.rpc_rx_data(child_rx_data[i*128 +: CHILD_DATA_WIDTH[i*8 +: 8] ] ),
.rpc_rx_ready(child_rx_ready[i]),
.rpc_fab_rx_space_available(fifo_space_available),
.rpc_fab_rx_packet_start(),
.rpc_fab_rx_data_valid(fifo_wr_en),
.rpc_fab_rx_data(fifo_wr_data),
.rpc_fab_rx_packet_done()
);
SingleClockShiftRegisterFifo #(
.WIDTH(CORE_DATA_WIDTH),
.DEPTH(32),
.OUT_REG(1)
) rx_fifo (
.clk(clk),
.wr(fifo_wr_en),
.din(fifo_wr_data),
.rd(child_fifo_rd[i]),
.dout(child_fifo_dout[i*CORE_DATA_WIDTH +: CORE_DATA_WIDTH]),
.overflow(), //ignored, can never under/overflow b/c of receiver flow control
.underflow(),
.empty(child_fifo_empty[i]),
.full(),
.rsize(child_fifo_rsize[6*i +: 6]),
.wsize(fifo_wr_size),
.reset(1'b0) //never reset the fifo
);
end
endgenerate
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmitters for neighbor ports
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmitters for child ports
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual switch crossbar
RPCv3RouterCrossbar #(
.CORE_DATA_WIDTH(CORE_DATA_WIDTH),
.CHILD_IS_TRUNK(CHILD_IS_TRUNK),
.CHILD_COUNT(CHILD_COUNT),
.CHILD_DATA_WIDTH(CHILD_DATA_WIDTH),
.NEIGHBOR_PRESENT(NEIGHBOR_PRESENT),
.NEIGHBOR_DATA_WIDTH(NEIGHBOR_DATA_WIDTH),
.X_POS(X_POS),
.Y_POS(Y_POS)
) crossbar (
.clk(clk),
.rx_fifo_rd({child_fifo_rd, neighbor_fifo_rd}),
.rx_fifo_empty({child_fifo_empty, neighbor_fifo_empty}),
.rx_fifo_dout({child_fifo_dout, neighbor_fifo_dout}),
.rx_fifo_rsize({child_fifo_rsize, neighbor_fifo_rsize})
);
endmodule
|
`include "hrfp_defs.vh"
module hrfp_mult_normalize
(output reg expdiff,
output reg [53:0] normalized_mantissa,
input wire clk,
input wire [53:0] mantissa4, mantissa5);
parameter EARLY_EXPDIFF = 1;
parameter EARLY_NORMALIZE = 0;
generate
// IDEA: In case of emergency: Can check only one bit of expdiff
// here and the remaining bits beforehand!
if(EARLY_EXPDIFF) begin : CHECK_EXPDIFF_EARLY
always @(posedge clk) begin
expdiff <= 1;
if(!mantissa4[53:50]) begin
expdiff <= 0;
end
end
end else begin : CHECK_EXPDIFF_LATE
always @* begin
expdiff = 1;
if(!mantissa5[53:50]) begin
expdiff = 0;
end
end
end
endgenerate
generate // Needed for non parallell rounding
if(EARLY_NORMALIZE) begin : CHECK_NORMALIZATION_EARLY
always @(posedge clk) begin
normalized_mantissa <= mantissa4[53:0];
if(!mantissa4[53:50]) begin
normalized_mantissa <= {mantissa4[49:0], 4'b0000};
end
end
end else begin : CHECK_NORMALIZATION_LATE
always @* begin
normalized_mantissa = mantissa5[53:0];
if(!expdiff) begin
normalized_mantissa = {mantissa5[49:0], 4'b0000};
end
end
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_clkgn_ddiv.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
//
// Module Name: clk_ddiv
//
// Description: clock divider based on Johnson counter
//
// - supports odd/even divisors from 2 to 24 (12 stages of Jons. cnt)
// - supports clock stretch for duration of sig "stretch"
//
// - positive clock counter have sigs *joa*
// - negative clock counter have sigs *job*
//
// - outputs joa_q_2, joa_q_1, joa_q_0 might be used for synchronization
//
// - the last stages of counters "joa_q[0]" and "job_q[0]"
// are registered into "joa_q_0_reg" and "job_q_0_reg"
//
// - the "joa_q_0_reg" and "job_q_0_reg" are ORed into "out_gclk".
//
//
//
// Mimi 7/8/03 : Added input stretch_b,rst_b_l
module ctu_clsp_clkgn_ddiv (/*AUTOARG*/
// Outputs
dom_div0, align_edge, align_edge_b, dom_div1, so,
// Inputs
pll_clk_out, pll_clk_out_l, rst_l, rst_b_l, div_dec, stretch_l,
stretch_b_l, se, si
);
// Globals
input pll_clk_out;
input pll_clk_out_l;
input rst_l;
input rst_b_l;
// Divisor
input [14:0] div_dec ;
// The "stretch" is expected synced with pll_clk_out
input stretch_l;
input stretch_b_l;
// Clock outputs
output dom_div0;
output align_edge;
output align_edge_b;
output dom_div1;
input si;
input se;
output so;
/*
output out_gclk;
output out_gclk_l;
*/
ctu_clsp_clkgn_1div pos(
// Outputs
.dom_div (dom_div0),
.align_edge (align_edge),
.align_edge_b (align_edge_b),
.so (),
// Inputs
.pll_clk (pll_clk_out),
.pll_clk_l (pll_clk_out_l),
.init_l (rst_l),
.div_dec (div_dec[14:0]),
.stretch_l (stretch_l),
.se (se),
.si ());
ctu_clsp_clkgn_1div neg(
// Outputs
.dom_div (dom_div1),
.align_edge (),
.align_edge_b (),
.so (),
// Inputs
.pll_clk (pll_clk_out_l),
.pll_clk_l (pll_clk_out),
.init_l (rst_b_l),
.div_dec (div_dec[14:0]),
.stretch_l (stretch_b_l),
.se (se),
.si ());
endmodule // clk_ddiv
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_1_V
`define SKY130_FD_SC_MS__OR4B_1_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_1 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4b_1 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_1_V
|
`timescale 1 ns / 1 ps
module hapara_axis_id_generator_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input wire Finish,
output wire En,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] orgX,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] orgY,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] lengthX,
// output wire [C_S_AXI_DATA_WIDTH - 1 : 0] lengthY,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] org,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] len,
output wire [C_S_AXI_DATA_WIDTH - 1 : 0] numOfSlv,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 || curr_state == counting)
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
// slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
// 2'h3:
// for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
// if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
// slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
// end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
// slv_reg3 <= slv_reg3;
end
endcase
end
end
end
//logic for writing slv_reg3;
always @(posedge S_AXI_ACLK) begin
if (!S_AXI_ARESETN || curr_state == reset || curr_state == counting) begin
slv_reg3 <= 0;
end
else if (curr_state == finish) begin
slv_reg3 <= 1;
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// X: vertical
// Y: horizontal
// slv_reg0: orgX, orgY
// slv_reg1: lenX, lenY
// slv_reg2: num of slaves
// slv_reg3: isFinish?
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_orgX; //slv_reg0
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_orgY; //slv_reg1
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_lengthX; //slv_reg2
// reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_lengthY; //slv_reg3
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_org;
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_len;
reg [C_S_AXI_DATA_WIDTH - 1 : 0] reg_numOfSlv;
localparam LENGTH = C_S_AXI_DATA_WIDTH / 2;
localparam reset = 3'b001;
localparam counting = 3'b010;
localparam finish = 3'b100;
reg [2 : 0] next_state;
reg [2 : 0] curr_state;
// logic for reg_*
always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
if (!S_AXI_ARESETN) begin
reg_org <= 0;
reg_len <= 0;
reg_numOfSlv <= 0;
end
else begin
if (curr_state == reset) begin
reg_org <= slv_reg0;
reg_len <= slv_reg1;
reg_numOfSlv <= slv_reg2;
end
else begin
reg_org <= reg_org;
reg_len <= reg_len;
reg_numOfSlv <= reg_numOfSlv;
end
end
end
// logic for curr_state;
always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
if (!S_AXI_ARESETN) begin
// reset
curr_state <= reset;
end
else begin
curr_state <= next_state;
end
end
wire data_ready;
assign data_ready =
(slv_reg1[C_S_AXI_DATA_WIDTH - 1 : LENGTH] != {LENGTH{1'b0}}) &&
(slv_reg1[LENGTH - 1 : 0] != {LENGTH{1'b0}});
always @(curr_state or data_ready or Finish) begin
case(curr_state)
reset:
if (data_ready) begin
next_state = counting;
end
else begin
next_state = reset;
end
counting:
if (Finish) begin
next_state = finish;
end
else begin
next_state = counting;
end
finish:
if (data_ready) begin
next_state = reset;
end
else begin
next_state = finish;
end
default :
next_state = 3'bxxx;
endcase
end
assign En = curr_state == counting;
// assign orgX = reg_orgX;
// assign orgY = reg_orgY;
// assign lengthX = reg_lengthX;
// assign lengthY = reg_lengthY;
assign org = reg_org;
assign len = reg_len;
assign numOfSlv = reg_numOfSlv;
// User logic ends
endmodule
|
`timescale 1ns / 1ps
module Print(
input clk, // ʱÖÓÐźÅ
input [15:0] num, // ÒªÏÔʾµÄ4λÊý
input [3:0] flash, // 4λ, ÊÇ·ñÉÁ˸, 1 => true, 0 => false
output reg [7:0] display, // Êä³ö, 8λ¶ÎÑ¡¶Ë(CA, CB, CC, CD, CE, CF, CG, DP)
output reg [3:0] an // Êä³ö, 4λλѡ¶Ë
);
reg flash_state; // µ±Ç°ÉÁ˸״̬, 1 => ´¦ÓÚÉÁ˸״̬
reg [3:0] tmp;
reg [15:0] counter;
reg [31:0] flash_counter;
reg [3:0] an_tmp;
parameter [15:0] MAX_COUNTER = 16'D5_0000;
parameter [31:0] MAX_FLASH_COUNTER = 32'D5000_0000;
initial begin
an_tmp = 4'B0111;
counter = 0;
flash_counter = 0;
flash_state = 0;
end
always@(an_tmp) begin
case(an_tmp)
4'B0111: tmp = num[15:12];
4'B1011: tmp = num[11:8];
4'B1101: tmp = num[7:4];
4'B1110: tmp = num[3:0];
endcase
case(tmp)
4'H0: display = 8'B0000_0011;
4'H1: display = 8'B1001_1111;
4'H2: display = 8'B0010_0101;
4'H3: display = 8'B0000_1101;
4'H4: display = 8'B1001_1001;
4'H5: display = 8'B0100_1001;
4'H6: display = 8'B0100_0001;
4'H7: display = 8'B0001_1111;
4'H8: display = 8'B0000_0001;
4'H9: display = 8'B0000_1001;
endcase
end
always@(posedge clk) begin
// ÏÔʾɨÃè
counter = counter + 1;
if(counter == MAX_COUNTER) begin
an_tmp = (an_tmp >> 1) + 4'B1000;
counter = 0;
end
if(an_tmp == 4'B1111) begin
an_tmp = 4'B0111;
end
// ÉÁ˸ɨÃè
flash_counter = flash_counter + 1;
if(flash_counter == MAX_FLASH_COUNTER) begin
flash_counter = 0;
flash_state = ~flash_state;
end
// »ñµÃ×îÖÕanÖµ
if(flash_state) an = an_tmp | flash;
else an = an_tmp;
end
endmodule
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
// Module handles updating the loopy scroll register
module LoopyGen(input clk, input ce,
input is_rendering,
input [2:0] ain, // input address from CPU
input [7:0] din, // data input
input read, // read
input write, // write
input is_pre_render, // Is this the pre-render scanline
input [8:0] cycle,
output [14:0] loopy,
output [2:0] fine_x_scroll); // Current loopy value
// Controls how much to increment on each write
reg ppu_incr; // 0 = 1, 1 = 32
// Current VRAM address
reg [14:0] loopy_v;
// Temporary VRAM address
reg [14:0] loopy_t;
// Fine X scroll (3 bits)
reg [2:0] loopy_x;
// Latch
reg ppu_address_latch;
initial begin
ppu_incr = 0;
loopy_v = 0;
loopy_t = 0;
loopy_x = 0;
ppu_address_latch = 0;
end
// Handle updating loopy_t and loopy_v
always @(posedge clk) if (ce) begin
if (is_rendering) begin
// Increment course X scroll right after attribute table byte was fetched.
if (cycle[2:0] == 3 && (cycle < 256 || cycle >= 320 && cycle < 336)) begin
loopy_v[4:0] <= loopy_v[4:0] + 1;
loopy_v[10] <= loopy_v[10] ^ (loopy_v[4:0] == 31);
end
// Vertical Increment
if (cycle == 251) begin
loopy_v[14:12] <= loopy_v[14:12] + 1;
if (loopy_v[14:12] == 7) begin
if (loopy_v[9:5] == 29) begin
loopy_v[9:5] <= 0;
loopy_v[11] <= !loopy_v[11];
end else begin
loopy_v[9:5] <= loopy_v[9:5] + 1;
end
end
end
// Horizontal Reset at cycle 257
if (cycle == 256)
{loopy_v[10], loopy_v[4:0]} <= {loopy_t[10], loopy_t[4:0]};
// On cycle 256 of each scanline, copy horizontal bits from loopy_t into loopy_v
// On cycle 304 of the pre-render scanline, copy loopy_t into loopy_v
if (cycle == 304 && is_pre_render) begin
loopy_v <= loopy_t;
end
end
if (write && ain == 0) begin
loopy_t[10] <= din[0];
loopy_t[11] <= din[1];
ppu_incr <= din[2];
end else if (write && ain == 5) begin
if (!ppu_address_latch) begin
loopy_t[4:0] <= din[7:3];
loopy_x <= din[2:0];
end else begin
loopy_t[9:5] <= din[7:3];
loopy_t[14:12] <= din[2:0];
end
ppu_address_latch <= !ppu_address_latch;
end else if (write && ain == 6) begin
if (!ppu_address_latch) begin
loopy_t[13:8] <= din[5:0];
loopy_t[14] <= 0;
end else begin
loopy_t[7:0] <= din;
loopy_v <= {loopy_t[14:8], din};
end
ppu_address_latch <= !ppu_address_latch;
end else if (read && ain == 2) begin
ppu_address_latch <= 0; //Reset PPU address latch
end else if ((read || write) && ain == 7 && !is_rendering) begin
// Increment address every time we accessed a reg
loopy_v <= loopy_v + (ppu_incr ? 32 : 1);
end
end
assign loopy = loopy_v;
assign fine_x_scroll = loopy_x;
endmodule
// Generates the current scanline / cycle counters
module ClockGen(input clk, input ce, input reset,
input is_rendering,
output reg [8:0] scanline,
output reg [8:0] cycle,
output reg is_in_vblank,
output end_of_line,
output at_last_cycle_group,
output exiting_vblank,
output entering_vblank,
output reg is_pre_render);
reg second_frame;
// Scanline 0..239 = picture scan lines
// Scanline 240 = dummy scan line
// Scanline 241..260 = VBLANK
// Scanline -1 = Pre render scanline (Fetches objects for next line)
assign at_last_cycle_group = (cycle[8:3] == 42);
// Every second pre-render frame is only 340 cycles instead of 341.
assign end_of_line = at_last_cycle_group && cycle[3:0] == (is_pre_render && second_frame && is_rendering ? 3 : 4);
// Set the clock right before vblank begins
assign entering_vblank = end_of_line && scanline == 240;
// Set the clock right before vblank ends
assign exiting_vblank = end_of_line && scanline == 260;
// New value for is_in_vblank flag
wire new_is_in_vblank = entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank;
// Set if the current line is line 0..239
always @(posedge clk) if (reset) begin
cycle <= 0;
is_in_vblank <= 1;
end else if (ce) begin
cycle <= end_of_line ? 0 : cycle + 1;
is_in_vblank <= new_is_in_vblank;
end
// always @(posedge clk) if (ce) begin
// $write("%x %x %x %x %x\n", new_is_in_vblank, entering_vblank, exiting_vblank, is_in_vblank, entering_vblank ? 1'b1 : exiting_vblank ? 1'b0 : is_in_vblank);
// end
always @(posedge clk) if (reset) begin
scanline <= 0;
is_pre_render <= 0;
second_frame <= 0;
end else if (ce && end_of_line) begin
// Once the scanline counter reaches end of 260, it gets reset to -1.
scanline <= exiting_vblank ? 9'b111111111 : scanline + 1;
// The pre render flag is set while we're on scanline -1.
is_pre_render <= exiting_vblank;
if (exiting_vblank)
second_frame <= !second_frame;
end
endmodule // ClockGen
// 8 of these exist, they are used to output sprites.
module Sprite(input clk, input ce,
input enable,
input [3:0] load,
input [26:0] load_in,
output [26:0] load_out,
output [4:0] bits); // Low 4 bits = pixel, high bit = prio
reg [1:0] upper_color; // Upper 2 bits of color
reg [7:0] x_coord; // X coordinate where we want things
reg [7:0] pix1, pix2; // Shift registers, output when x_coord == 0
reg aprio; // Current prio
wire active = (x_coord == 0);
always @(posedge clk) if (ce) begin
if (enable) begin
if (!active) begin
// Decrease until x_coord is zero.
x_coord <= x_coord - 8'h01;
end else begin
pix1 <= pix1 >> 1;
pix2 <= pix2 >> 1;
end
end
if (load[3]) pix1 <= load_in[26:19];
if (load[2]) pix2 <= load_in[18:11];
if (load[1]) x_coord <= load_in[10:3];
if (load[0]) {upper_color, aprio} <= load_in[2:0];
end
assign bits = {aprio, upper_color, active && pix2[0], active && pix1[0]};
assign load_out = {pix1, pix2, x_coord, upper_color, aprio};
endmodule // SpriteGen
// This contains all 8 sprites. Will return the pixel value of the highest prioritized sprite.
// When load is set, and clocked, load_in is loaded into sprite 7 and all others are shifted down.
// Sprite 0 has highest prio.
// 226 LUTs, 68 Slices
module SpriteSet(input clk, input ce, // Input clock
input enable, // Enable pixel generation
input [3:0] load, // Which parts of the state to load/shift.
input [26:0] load_in, // State to load with
output [4:0] bits, // Output bits
output is_sprite0); // Set to true if sprite #0 was output
wire [26:0] load_out7, load_out6, load_out5, load_out4, load_out3, load_out2, load_out1, load_out0;
wire [4:0] bits7, bits6, bits5, bits4, bits3, bits2, bits1, bits0;
Sprite sprite7(clk, ce, enable, load, load_in, load_out7, bits7);
Sprite sprite6(clk, ce, enable, load, load_out7, load_out6, bits6);
Sprite sprite5(clk, ce, enable, load, load_out6, load_out5, bits5);
Sprite sprite4(clk, ce, enable, load, load_out5, load_out4, bits4);
Sprite sprite3(clk, ce, enable, load, load_out4, load_out3, bits3);
Sprite sprite2(clk, ce, enable, load, load_out3, load_out2, bits2);
Sprite sprite1(clk, ce, enable, load, load_out2, load_out1, bits1);
Sprite sprite0(clk, ce, enable, load, load_out1, load_out0, bits0);
// Determine which sprite is visible on this pixel.
assign bits = bits0[1:0] != 0 ? bits0 :
bits1[1:0] != 0 ? bits1 :
bits2[1:0] != 0 ? bits2 :
bits3[1:0] != 0 ? bits3 :
bits4[1:0] != 0 ? bits4 :
bits5[1:0] != 0 ? bits5 :
bits6[1:0] != 0 ? bits6 :
bits7;
assign is_sprite0 = bits0[1:0] != 0;
endmodule // SpriteSet
module SpriteRAM(input clk, input ce,
input reset_line, // OAM evaluator needs to be reset before processing is started.
input sprites_enabled, // Set to 1 if evaluations are enabled
input exiting_vblank, // Set to 1 when exiting vblank so spr_overflow can be reset
input obj_size, // Set to 1 if objects are 16 pixels.
input [8:0] scanline, // Current scan line (compared against Y)
input [8:0] cycle, // Current cycle.
output reg [7:0] oam_bus, // Current value on the OAM bus, returned to NES through $2004.
input oam_ptr_load, // Load oam with specified value, when writing to NES $2003.
input oam_load, // Load oam_ptr with specified value, when writing to NES $2004.
input [7:0] data_in, // New value for oam or oam_ptr
output reg spr_overflow, // Set to true if we had more than 8 objects on a scan line. Reset when exiting vblank.
output reg sprite0); // True if sprite#0 is included on the scan line currently being painted.
reg [7:0] sprtemp[0:31]; // Sprite Temporary Memory. 32 bytes.
reg [7:0] oam[0:255]; // Sprite OAM. 256 bytes.
reg [7:0] oam_ptr; // Pointer into oam_ptr.
reg [2:0] p; // Upper 3 bits of pointer into temp, the lower bits are oam_ptr[1:0].
reg [1:0] state; // Current state machine state
wire [7:0] oam_data = oam[oam_ptr];
// Compute the current address we read/write in sprtemp.
reg [4:0] sprtemp_ptr;
// Check if the current Y coordinate is inside.
wire [8:0] spr_y_coord = scanline - {1'b0, oam_data};
wire spr_is_inside = (spr_y_coord[8:4] == 0) && (obj_size || spr_y_coord[3] == 0);
reg [7:0] new_oam_ptr; // [wire] New value for oam ptr
reg [1:0] oam_inc; // [wire] How much to increment oam ptr
reg sprite0_curr; // If sprite0 is included on the line being processed.
reg oam_wrapped; // [wire] if new_oam or new_p wrapped.
wire [7:0] sprtemp_data = sprtemp[sprtemp_ptr];
always @* begin
// Compute address to read/write in temp sprite ram
case({cycle[8], cycle[2]})
2'b0_?: sprtemp_ptr = {p, oam_ptr[1:0]};
2'b1_0: sprtemp_ptr = {cycle[5:3], cycle[1:0]}; // 1-4. Read Y, Tile, Attribs
2'b1_1: sprtemp_ptr = {cycle[5:3], 2'b11}; // 5-8. Keep reading X.
endcase
end
always @* begin
/* verilator lint_off CASEOVERLAP */
// Compute value to return to cpu through $2004. And also the value that gets written to temp sprite ram.
case({sprites_enabled, cycle[8], cycle[6], state, oam_ptr[1:0]})
7'b1_10_??_??: oam_bus = sprtemp_data; // At cycle 256-319 we output what's in sprite temp ram
7'b1_??_00_??: oam_bus = 8'b11111111; // On the first 64 cycles (while inside state 0), we output 0xFF.
7'b1_??_01_00: oam_bus = {4'b0000, spr_y_coord[3:0]}; // Y coord that will get written to temp ram.
7'b?_??_??_10: oam_bus = {oam_data[7:5], 3'b000, oam_data[1:0]}; // Bits 2-4 of attrib are always zero when reading oam.
default: oam_bus = oam_data; // Default to outputting from oam.
endcase
end
always @* begin
// Compute incremented oam counters
case ({oam_load, state, oam_ptr[1:0]})
5'b1_??_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // Always increment by 1 when writing to oam.
5'b0_00_??: oam_inc = 2'b01; // State 0: On the the first 64 cycles we fill temp ram with 0xFF, increment low bits.
5'b0_01_00: oam_inc = {!spr_is_inside, spr_is_inside}; // State 1: Copy Y coordinate and increment oam by 1 if it's inside, otherwise 4.
5'b0_01_??: oam_inc = {oam_ptr[1:0] == 3, 1'b1}; // State 1: Copy remaining 3 bytes of the oam.
// State 3: We've had more than 8 sprites. Set overflow flag if we found a sprite that overflowed.
// NES BUG: It increments both low and high counters.
5'b0_11_??: oam_inc = 2'b11;
// While in the final state, keep incrementing the low bits only until they're zero.
5'b0_10_??: oam_inc = {1'b0, oam_ptr[1:0] != 0};
endcase
/* verilator lint_on CASEOVERLAP */
new_oam_ptr[1:0] = oam_ptr[1:0] + {1'b0, oam_inc[0]};
{oam_wrapped, new_oam_ptr[7:2]} = {1'b0, oam_ptr[7:2]} + {6'b0, oam_inc[1]};
end
always @(posedge clk) if (ce) begin
// Some bits of the OAM are hardwired to zero.
if (oam_load)
oam[oam_ptr] <= (oam_ptr & 3) == 2 ? data_in & 8'hE3: data_in;
if (cycle[0] && sprites_enabled || oam_load || oam_ptr_load) begin
oam_ptr <= oam_ptr_load ? data_in : new_oam_ptr;
end
// Set overflow flag?
if (sprites_enabled && state == 2'b11 && spr_is_inside)
spr_overflow <= 1;
// Remember if sprite0 is included on the scanline, needed for hit test later.
sprite0_curr <= (state == 2'b01 && oam_ptr[7:2] == 0 && spr_is_inside || sprite0_curr);
// if (scanline == 0 && cycle[0] && (state == 2'b01 || state == 2'b00))
// $write("Drawing sprite %d/%d. bus=%d oam_ptr=%X->%X oam_data=%X p=%d (%d %d %d)\n", scanline, cycle, oam_bus, oam_ptr, new_oam_ptr, oam_data, p,
// cycle[0] && sprites_enabled, oam_load, oam_ptr_load);
// Always writing to temp ram while we're in state 0 or 1.
if (!state[1]) sprtemp[sprtemp_ptr] <= oam_bus;
// Update state machine on every second cycle.
if (cycle[0]) begin
// Increment p whenever oam_ptr carries in state 0 or 1.
if (!state[1] && oam_ptr[1:0] == 2'b11) p <= p + 1;
// Set sprite0 if sprite1 was included on the scan line
case({state, (p == 7) && (oam_ptr[1:0] == 2'b11), oam_wrapped})
4'b00_0_?: state <= 2'b00; // State #0: Keep filling
4'b00_1_?: state <= 2'b01; // State #0: Until we filled 64 items.
4'b01_?_1: state <= 2'b10; // State #1: Goto State 2 if processed all OAM
4'b01_1_0: state <= 2'b11; // State #1: Goto State 3 if we found 8 sprites
4'b01_0_0: state <= 2'b01; // State #1: Keep comparing Y coordinates.
4'b11_?_1: state <= 2'b10; // State #3: Goto State 2 if processed all OAM
4'b11_?_0: state <= 2'b11; // State #3: Keep comparing Y coordinates
4'b10_?_?: state <= 2'b10; // Stuck in state 2.
endcase
end
if (reset_line) begin
state <= 0;
p <= 0;
oam_ptr <= 0;
sprite0_curr <= 0;
sprite0 <= sprite0_curr;
end
if (exiting_vblank)
spr_overflow <= 0;
end
endmodule // SpriteRAM
// Generates addresses in VRAM where we'll fetch sprite graphics from,
// and populates load, load_in so the SpriteGen can be loaded.
// 10 LUT, 4 Slices
module SpriteAddressGen(input clk, input ce,
input enabled, // If unset, |load| will be all zeros.
input obj_size, // 0: Sprite Height 8, 1: Sprite Height 16.
input obj_patt, // Object pattern table selection
input [2:0] cycle, // Current load cycle. At #4, first bitmap byte is loaded. At #6, second bitmap byte is.
input [7:0] temp, // Input temp data from SpriteTemp. #0 = Y Coord, #1 = Tile, #2 = Attribs, #3 = X Coord
output [12:0] vram_addr,// Low bits of address in VRAM that we'd like to read.
input [7:0] vram_data, // Byte of VRAM in the specified address
output [3:0] load, // Which subset of load_in that is now valid, will be loaded into SpritesGen.
output [26:0] load_in); // Bits to load into SpritesGen.
reg [7:0] temp_tile; // Holds the tile that we will get
reg [3:0] temp_y; // Holds the Y coord (will be swapped based on FlipY).
reg flip_x, flip_y; // If incoming bitmap data needs to be flipped in the X or Y direction.
wire load_y = (cycle == 0);
wire load_tile = (cycle == 1);
wire load_attr = (cycle == 2) && enabled;
wire load_x = (cycle == 3) && enabled;
wire load_pix1 = (cycle == 5) && enabled;
wire load_pix2 = (cycle == 7) && enabled;
reg dummy_sprite; // Set if attrib indicates the sprite is invalid.
// Flip incoming vram data based on flipx. Zero out the sprite if it's invalid. The bits are already flipped once.
wire [7:0] vram_f = dummy_sprite ? 0 :
!flip_x ? {vram_data[0], vram_data[1], vram_data[2], vram_data[3], vram_data[4], vram_data[5], vram_data[6], vram_data[7]} :
vram_data;
wire [3:0] y_f = temp_y ^ {flip_y, flip_y, flip_y, flip_y};
assign load = {load_pix1, load_pix2, load_x, load_attr};
assign load_in = {vram_f, vram_f, temp, temp[1:0], temp[5]};
// If $2000.5 = 0, the tile index data is used as usual, and $2000.3
// selects the pattern table to use. If $2000.5 = 1, the MSB of the range
// result value become the LSB of the indexed tile, and the LSB of the tile
// index value determines pattern table selection. The lower 3 bits of the
// range result value are always used as the fine vertical offset into the
// selected pattern.
assign vram_addr = {obj_size ? temp_tile[0] : obj_patt,
temp_tile[7:1], obj_size ? y_f[3] : temp_tile[0], cycle[1], y_f[2:0] };
always @(posedge clk) if (ce) begin
if (load_y) temp_y <= temp[3:0];
if (load_tile) temp_tile <= temp;
if (load_attr) {flip_y, flip_x, dummy_sprite} <= {temp[7:6], temp[4]};
end
// always @(posedge clk) begin
// if (load[3]) $write("Loading pix1: %x\n", load_in[26:19]);
// if (load[2]) $write("Loading pix2: %x\n", load_in[18:11]);
// if (load[1]) $write("Loading x: %x\n", load_in[10:3]);
//
// if (valid_sprite && enabled)
// $write("%d. Found %d. Flip:%d%d, Addr: %x, Vram: %x!\n", cycle, temp, flip_x, flip_y, vram_addr, vram_data);
// end
endmodule // SpriteAddressGen
module BgPainter(input clk, input ce,
input enable, // Shift registers activated
input [2:0] cycle,
input [2:0] fine_x_scroll,
input [14:0] loopy,
output [7:0] name_table, // VRAM name table to read next.
input [7:0] vram_data,
output [3:0] pixel);
reg [15:0] playfield_pipe_1; // Name table pixel pipeline #1
reg [15:0] playfield_pipe_2; // Name table pixel pipeline #2
reg [8:0] playfield_pipe_3; // Attribute table pixel pipe #1
reg [8:0] playfield_pipe_4; // Attribute table pixel pipe #2
reg [7:0] current_name_table; // Holds the current name table byte
reg [1:0] current_attribute_table; // Holds the 2 current attribute table bits
reg [7:0] bg0; // Pixel data for last loaded background
wire [7:0] bg1 = vram_data;
initial begin
playfield_pipe_1 = 0;
playfield_pipe_2 = 0;
playfield_pipe_3 = 0;
playfield_pipe_4 = 0;
current_name_table = 0;
current_attribute_table = 0;
bg0 = 0;
end
always @(posedge clk) if (ce) begin
case (cycle[2:0])
1: current_name_table <= vram_data;
3: current_attribute_table <= (!loopy[1] && !loopy[6]) ? vram_data[1:0] :
( loopy[1] && !loopy[6]) ? vram_data[3:2] :
(!loopy[1] && loopy[6]) ? vram_data[5:4] :
vram_data[7:6];
5: bg0 <= vram_data; // Pattern table bitmap #0
// 7: bg1 <= vram_data; // Pattern table bitmap #1
endcase
if (enable) begin
playfield_pipe_1[14:0] <= playfield_pipe_1[15:1];
playfield_pipe_2[14:0] <= playfield_pipe_2[15:1];
playfield_pipe_3[7:0] <= playfield_pipe_3[8:1];
playfield_pipe_4[7:0] <= playfield_pipe_4[8:1];
// Load the new values into the shift registers at the last pixel.
if (cycle[2:0] == 7) begin
playfield_pipe_1[15:8] <= {bg0[0], bg0[1], bg0[2], bg0[3], bg0[4], bg0[5], bg0[6], bg0[7]};
playfield_pipe_2[15:8] <= {bg1[0], bg1[1], bg1[2], bg1[3], bg1[4], bg1[5], bg1[6], bg1[7]};
playfield_pipe_3[8] <= current_attribute_table[0];
playfield_pipe_4[8] <= current_attribute_table[1];
end
end
end
assign name_table = current_name_table;
wire [3:0] i = {1'b0, fine_x_scroll};
assign pixel = {playfield_pipe_4[i], playfield_pipe_3[i],
playfield_pipe_2[i], playfield_pipe_1[i]};
endmodule // BgPainter
module PixelMuxer(input [3:0] bg, input [3:0] obj, input obj_prio, output [3:0] out, output is_obj);
wire bg_flag = bg[0] | bg[1];
wire obj_flag = obj[0] | obj[1];
assign is_obj = !(obj_prio && bg_flag) && obj_flag;
assign out = is_obj ? obj : bg;
endmodule
module PaletteRam(input clk, input ce, input [4:0] addr, input [5:0] din, output [5:0] dout, input write);
reg [5:0] palette [0:31];
initial begin
//$readmemh("oam_palette.txt", palette);
end
// Force read from backdrop channel if reading from any addr 0.
wire [4:0] addr2 = (addr[1:0] == 0) ? 0 : addr;
assign dout = palette[addr2];
always @(posedge clk) if (ce && write) begin
// Allow writing only to x0
if (!(addr[3:2] != 0 && addr[1:0] == 0))
palette[addr2] <= din;
end
endmodule // PaletteRam
module PPU(input clk, input ce, input reset, // input clock 21.48 MHz / 4. 1 clock cycle = 1 pixel
output [5:0] color, // output color value, one pixel outputted every clock
input [7:0] din, // input data from bus
output [7:0] dout, // output data to CPU
input [2:0] ain, // input address from CPU
input read, // read
input write, // write
output nmi, // one while inside vblank
output vram_r, // read from vram active
output vram_w, // write to vram active
output [13:0] vram_a, // vram address
input [7:0] vram_din, // vram input
output [7:0] vram_dout,
output [8:0] scanline,
output [8:0] cycle,
output [19:0] mapper_ppu_flags);
// These are stored in control register 0
reg obj_patt; // Object pattern table
reg bg_patt; // Background pattern table
reg obj_size; // 1 if sprites are 16 pixels high, else 0.
reg vbl_enable; // Enable VBL flag
// These are stored in control register 1
reg grayscale; // Disable color burst
reg playfield_clip; // 0: Left side 8 pixels playfield clipping
reg object_clip; // 0: Left side 8 pixels object clipping
reg enable_playfield; // Enable playfield display
reg enable_objects; // Enable objects display
reg [2:0] color_intensity; // Color intensity
initial begin
obj_patt = 0;
bg_patt = 0;
obj_size = 0;
vbl_enable = 0;
grayscale = 0;
playfield_clip = 0;
object_clip = 0;
enable_playfield = 0;
enable_objects = 0;
color_intensity = 0;
end
reg nmi_occured; // True if NMI has occured but not cleared.
reg [7:0] vram_latch;
// Clock generator
wire is_in_vblank; // True if we're in VBLANK
//wire [8:0] scanline; // Current scanline
//wire [8:0] cycle; // Current cycle inside of the line
wire end_of_line; // At the last pixel of a line
wire at_last_cycle_group; // At the very last cycle group of the scan line.
wire exiting_vblank; // At the very last cycle of the vblank
wire entering_vblank; //
wire is_pre_render_line; // True while we're on the pre render scanline
wire is_rendering = (enable_playfield || enable_objects) && !is_in_vblank && scanline != 240;
ClockGen clock(clk, ce, reset, is_rendering, scanline, cycle, is_in_vblank, end_of_line, at_last_cycle_group,
exiting_vblank, entering_vblank, is_pre_render_line);
// The loopy module handles updating of the loopy address
wire [14:0] loopy;
wire [2:0] fine_x_scroll;
LoopyGen loopy0(clk, ce, is_rendering, ain, din, read, write, is_pre_render_line, cycle, loopy, fine_x_scroll);
// Set to true if the current ppu_addr pointer points into
// palette ram.
wire is_pal_address = (loopy[13:8] == 6'b111111);
// Paints background
wire [7:0] bg_name_table;
wire [3:0] bg_pixel_noblank;
BgPainter bg_painter(clk, ce, !at_last_cycle_group, cycle[2:0], fine_x_scroll, loopy, bg_name_table, vram_din, bg_pixel_noblank);
// Blank out BG in the leftmost 8 pixels?
wire show_bg_on_pixel = (playfield_clip || (cycle[7:3] != 0)) && enable_playfield;
wire [3:0] bg_pixel = {bg_pixel_noblank[3:2], show_bg_on_pixel ? bg_pixel_noblank[1:0] : 2'b00};
// This will set oam_ptr to 0 right before the scanline 240 and keep it there throughout vblank.
wire before_line = (enable_playfield || enable_objects) && (exiting_vblank || end_of_line && !is_in_vblank);
wire [7:0] oam_bus;
wire sprite_overflow;
wire obj0_on_line; // True if sprite#0 is included on the current line
SpriteRAM sprite_ram(clk, ce,
before_line, // Condition for resetting the sprite line state.
is_rendering, // Condition for enabling sprite ram logic. Check so we're not on
exiting_vblank,
obj_size,
scanline, cycle,
oam_bus,
write && (ain == 3), // Write to oam_ptr
write && (ain == 4), // Write to oam[oam_ptr]
din,
sprite_overflow,
obj0_on_line);
wire [4:0] obj_pixel_noblank;
wire [12:0] sprite_vram_addr;
wire is_obj0_pixel; // True if obj_pixel originates from sprite0.
wire [3:0] spriteset_load; // Which subset of the |load_in| to load into SpriteSet
wire [26:0] spriteset_load_in; // Bits to load into SpriteSet
// Between 256..319 (64 cycles), fetches bitmap data for the 8 sprites and fills in the SpriteSet
// so that it can start drawing on the next frame.
SpriteAddressGen address_gen(clk, ce,
cycle[8] && !cycle[6], // Load sprites between 256..319
obj_size, obj_patt, // Object size and pattern table
cycle[2:0], // Cycle counter
oam_bus, // Info from temp buffer.
sprite_vram_addr, // [out] VRAM Address that we want data from
vram_din, // [in] Data at the specified address
spriteset_load,
spriteset_load_in); // Which parts of SpriteGen to load
// Between 0..255 (256 cycles), draws pixels.
// Between 256..319 (64 cycles), will be populated for next line
SpriteSet sprite_gen(clk, ce, !cycle[8], spriteset_load, spriteset_load_in, obj_pixel_noblank, is_obj0_pixel);
// Blank out obj in the leftmost 8 pixels?
wire show_obj_on_pixel = (object_clip || (cycle[7:3] != 0)) && enable_objects;
wire [4:0] obj_pixel = {obj_pixel_noblank[4:2], show_obj_on_pixel ? obj_pixel_noblank[1:0] : 2'b00};
reg sprite0_hit_bg; // True if sprite#0 has collided with the BG in the last frame.
always @(posedge clk) if (ce) begin
if (exiting_vblank)
sprite0_hit_bg <= 0;
else if (is_rendering && // Object rendering is enabled
!cycle[8] && // X Pixel 0..255
cycle[7:0] != 255 && // X pixel != 255
!is_pre_render_line && // Y Pixel 0..239
obj0_on_line && // True if sprite#0 is included on the scan line.
is_obj0_pixel && // True if the pixel came from tempram #0.
show_obj_on_pixel &&
bg_pixel[1:0] != 0) begin // Background pixel nonzero.
sprite0_hit_bg <= 1;
end
// if (!cycle[8] && is_visible_line && obj0_on_line && is_obj0_pixel)
// $write("Sprite0 hit bg scan %d!!\n", scanline);
// if (is_obj0_pixel)
// $write("drawing obj0 pixel %d/%d\n", scanline, cycle);
end
wire [3:0] pixel;
wire pixel_is_obj;
PixelMuxer pixel_muxer(bg_pixel, obj_pixel[3:0], obj_pixel[4], pixel, pixel_is_obj);
// Compute the value to put on the VRAM address bus
assign vram_a = !is_rendering ? loopy[13:0] : // VRAM
(cycle[2:1] == 0) ? {2'b10, loopy[11:0]} : // Name table
(cycle[2:1] == 1) ? {2'b10, loopy[11:10], 4'b1111, loopy[9:7], loopy[4:2]} : // Attribute table
cycle[8] && !cycle[6] ? {1'b0, sprite_vram_addr} :
{1'b0, bg_patt, bg_name_table, cycle[1], loopy[14:12]}; // Pattern table bitmap #0, #1
// Read from VRAM, either when user requested a manual read, or when we're generating pixels.
assign vram_r = read && (ain == 7) ||
is_rendering && cycle[0] == 0 && !end_of_line;
// Write to VRAM?
assign vram_w = write && (ain == 7) && !is_pal_address && !is_rendering;
wire [5:0] color2;
PaletteRam palette_ram(clk, ce,
is_rendering ? {pixel_is_obj, pixel[3:0]} : (is_pal_address ? loopy[4:0] : 5'b0000), // Read addr
din[5:0], // Value to write
color2, // Output color
write && (ain == 7) && is_pal_address); // Condition for writing
assign color = grayscale ? {color2[5:4], 4'b0} : color2;
// always @(posedge clk)
// if (scanline == 194 && cycle < 8 && color == 15) begin
// $write("Pixel black %x %x %x %x %x\n", bg_pixel,obj_pixel,pixel,pixel_is_obj,color);
// end
always @(posedge clk) if (ce) begin
// if (!is_in_vblank && write)
// $write("%d/%d: $200%d <= %x\n", scanline, cycle, ain, din);
if (write) begin
case (ain)
0: begin // PPU Control Register 1
// t:....BA.. ........ = d:......BA
obj_patt <= din[3];
bg_patt <= din[4];
obj_size <= din[5];
vbl_enable <= din[7];
//$write("PPU Control #0 <= %X\n", din);
end
1: begin // PPU Control Register 2
grayscale <= din[0];
playfield_clip <= din[1];
object_clip <= din[2];
enable_playfield <= din[3];
enable_objects <= din[4];
color_intensity <= din[7:5];
if (!din[3] && scanline == 59)
$write("Disabling playfield at cycle %d\n", cycle);
end
endcase
end
// Reset frame specific counters upon exiting vblank
if (exiting_vblank)
nmi_occured <= 0;
// Set the
if (entering_vblank)
nmi_occured <= 1;
// Reset NMI register when reading from Status
if (read && ain == 2)
nmi_occured <= 0;
end
// If we're triggering a VBLANK NMI
assign nmi = nmi_occured && vbl_enable;
// One cycle after vram_r was asserted, the value
// is available on the bus.
reg vram_read_delayed;
always @(posedge clk) if (ce) begin
if (vram_read_delayed)
vram_latch <= vram_din;
vram_read_delayed = vram_r;
end
// Value currently being written to video ram
assign vram_dout = din;
reg [7:0] latched_dout;
always @* begin
case (ain)
2: latched_dout = {nmi_occured,
sprite0_hit_bg,
sprite_overflow,
5'b00000};
4: latched_dout = oam_bus;
default: if (is_pal_address) begin
latched_dout = {2'b00, color};
end else begin
latched_dout = vram_latch;
end
endcase
end
assign dout = latched_dout;
assign mapper_ppu_flags = {scanline, cycle, obj_size, is_rendering};
endmodule // PPU
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_TB_V
`define SKY130_FD_SC_LP__DLRBP_TB_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_lp__dlrbp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_TB_V
|
// ======================================================================
// YAB Observer PSoC.v generated from TopDesign.cysch
// 03/26/2016 at 16:40
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 5
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 6
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 7
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 8
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 9
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 10
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 11
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4F 12
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4M 13
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 14
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 15
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 16
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 17
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 18
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 11
`define CYDEV_CHIP_REVISION_USED 0
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v3_0(ApplySbClockParam=false, BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=false, DBGW_SCB_IP_V1=false, DBGW_SCB_IP_V2=true, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cBusVoltage=3.3, EzI2cByteModeEnable=false, EzI2cClkFreqDes=1550, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSlewRate=0, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cAcceptGeneralCall=false, I2cBusVoltage=3.3, I2cBusVoltageLevel=, I2cByteModeEnable=false, I2cClkFreqDes=1550, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cManualOversampleControl=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cSlewRate=0, I2cSlewRateSettings=0, I2cWakeEnable=false, PinLocationP4A=false, PinName0Unconfig=uart_rx_i2c_sda_spi_mosi, PinName0UnconfigWake=uart_rx_wake_i2c_sda_spi_mosi, PinName1Unconfig=uart_tx_i2c_scl_spi_miso, PinName2Unconfig=uart_cts_spi_sclk, PinName3Unconfig=uart_rts_spi_ss0, Pn0Unconfig=RX_SDA_MOSI, Pn0UnconfigWake=RX_WAKE_SDA_MOSI, Pn1Unconfig=TX_SCL_MISO, Pn2Unconfig=CTS_SCLK, Pn3Unconfig=RTS_SS0, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterMiso=true, RemoveSpiMasterMosi=true, RemoveSpiMasterPins=true, RemoveSpiMasterSclk=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlaveMiso=true, RemoveSpiSlaveMosi=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartCtsPin=true, RemoveUartRtsPin=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, RxTriggerOutputEnable=false, ScbClkFreqDes=1497.6, ScbClkMinusTolerance=5, ScbClkPlusTolerance=5, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiByteModeEnable=false, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiFreeRunningSclk=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiManualOversampleControl=true, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRemoveMiso=false, SpiRemoveMosi=false, SpiRemoveSclk=false, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxOutputEnable=false, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSs0Polarity=0, SpiSs1Polarity=0, SpiSs2Polarity=0, SpiSs3Polarity=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxOutputEnable=false, SpiTxTriggerLevel=0, SpiWakeEnable=false, TermMode_clock=0, TermMode_interrupt=0, TermVisibility_clock=false, TermVisibility_interrupt=false, TriggerOutputEnable=false, TxTriggerOutputEnable=false, UartByteModeEnable=false, UartClkFreqDes=1497.6, UartClockFromTerm=false, UartCtsEnable=false, UartCtsPolarity=0, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=13, UartParityType=2, UartRtsEnable=false, UartRtsPolarity=0, UartRtsTriggerLevel=4, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxOutputEnable=false, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxOutputEnable=false, UartTxTriggerLevel=0, UartWakeEnable=false, CY_API_CALLBACK_HEADER_INCLUDE=, CY_COMPONENT_NAME=SCB_P4_v3_0, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=UART, CY_INSTANCE_SHORT_NAME=UART, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP1, INSTANCE_NAME=UART, )
module SCB_P4_v3_0_0 (
interrupt,
clock,
rx_tr_out,
tx_tr_out);
output interrupt;
input clock;
output rx_tr_out;
output tx_tr_out;
wire uncfg_rx_irq;
wire Net_1191;
wire Net_1258;
wire Net_1099;
wire rx_irq;
wire [3:0] ss;
wire Net_1257;
wire Net_1197;
wire Net_1196;
wire Net_1195;
wire Net_1194;
wire Net_1193;
wire Net_1263;
wire Net_663;
wire Net_547;
wire Net_467;
wire Net_1090;
wire Net_1091;
wire Net_1172;
wire Net_1089;
wire Net_1088;
wire Net_387;
wire Net_252;
wire Net_1087;
wire Net_1086;
wire Net_1000;
wire Net_915;
wire Net_916;
wire Net_1175;
wire Net_654;
wire Net_990;
wire Net_652;
wire Net_459;
wire Net_580;
wire Net_581;
wire Net_452;
wire Net_909;
wire Net_1001;
wire Net_899;
wire Net_747;
wire Net_891;
wire Net_1028;
wire Net_1170;
wire Net_1061;
wire Net_1053;
wire Net_1055;
wire Net_1062;
wire Net_1059;
wire Net_847;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/2dc2d7a8-ce2b-43c7-af4a-821c8cd73ccf"),
.source_clock_id(""),
.divisor(0),
.period("667735042.735043"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_847));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_1194));
ZeroTerminal ZeroTerminal_2 (
.z(Net_1195));
ZeroTerminal ZeroTerminal_1 (
.z(Net_1196));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_1197;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_1257 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_1170 = Net_847;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_990 = Net_1196;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_909 = Net_1194;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_1195;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
tx
(.oe(tmpOE__tx_net),
.y({Net_1062}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_1099));
assign Net_1258 = Net_847 | Net_1099;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_1197}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// cts_VM (cy_virtualmux_v1_0)
assign Net_1175 = Net_747;
cy_m0s8_scb_v2_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.select_m(ss[3:0]),
.sclk_m(Net_1059),
.mosi_s(Net_909),
.select_s(Net_652),
.sclk_s(Net_990),
.mosi_m(Net_1061),
.scl(Net_580),
.sda(Net_581),
.tx(Net_1062),
.miso_s(Net_1055),
.interrupt(interrupt),
.cts(Net_1175),
.rts(Net_1053),
.tx_req(tx_tr_out),
.rx_req(rx_tr_out),
.clock(Net_1170));
defparam SCB.scb_mode = 2;
ZeroTerminal ZeroTerminal_6 (
.z(Net_747));
// Device_VM1 (cy_virtualmux_v1_0)
assign Net_547 = Net_1090;
// Device_VM5 (cy_virtualmux_v1_0)
assign Net_891 = Net_1089;
// Device_VM2 (cy_virtualmux_v1_0)
assign Net_1001 = Net_1086;
// Device_VM3 (cy_virtualmux_v1_0)
assign Net_899 = Net_916;
// Device_VM4 (cy_virtualmux_v1_0)
assign uncfg_rx_irq = Net_1000;
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v2_30(GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A500000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>3</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>3</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <IOCapability>DISPLAY</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>BOND</Bonding>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>100</Minimum>\r\n <Maximum>150</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>10240</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>NON_DISCOVERABLE</AdvDiscoveryMode>\r\n <AdvType>SCANNABLE</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>30</AdvFastTimeout>\r\n <AdvReducedTimeout>150</AdvReducedTimeout>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>0</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>65535</ScanReducedTimeout>\r\n <EnableReducedScan>false</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>true</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>04</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>10</ADType>\r\n <ADData>03</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>33</ADType>\r\n <ADData>FB:34:9B:5F:80:00:00:80:00:10:00:00:00:00:00:00</ADData>\r\n </CyADStructure>\r\n </Items>\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="36" DisplayName="Client" Name="Client">\r\n <CyService ID="37" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="38" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>0</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="39" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="41" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="42" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="43" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="44" DisplayName="Custom Service" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="45" DisplayName="Custom Characteristic" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="46" DisplayName="Custom Descriptor" Name="Custom Descriptor" Type="org.bluetooth.descriptor.custom" UUID="0000000000001000800000805F9B34FB">\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="false" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>1</ProfileRoleIndex>\r\n <RoleType>CLIENT</RoleType>\r\n </CyProfileRole>\r\n <CyProfileRole ID="47" DisplayName="Server" Name="Server">\r\n <CyService ID="14" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="15" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>7</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>YAB_OBS</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="16" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="52" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="53" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="54" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="55" DisplayName="Custom Service" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="56" DisplayName="Custom Characteristic" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="57" DisplayName="Custom Descriptor" Name="Custom Descriptor" Type="org.bluetooth.descriptor.custom" UUID="0000000000001000800000805F9B34FB">\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="New field">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="false" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="false" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>OBSERVER</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, UseDeepSleep=false, CY_API_CALLBACK_HEADER_INCLUDE=, CY_COMPONENT_NAME=BLE_v2_30, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v2_30.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=30, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP1, INSTANCE_NAME=BLE, )
module BLE_v2_30_1 (
clk);
output clk;
wire Net_53;
wire Net_64;
wire Net_63;
wire Net_37;
wire Net_15;
wire Net_14;
wire Net_60;
wire Net_55;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("7926b0c4-24d0-41e9-9cd3-d62a85d7b9c1/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
// top
module top ;
wire Net_3187;
wire Net_3192;
wire Net_3191;
wire Net_3189;
wire Net_3188;
SCB_P4_v3_0_0 UART (
.interrupt(Net_3188),
.clock(1'b0),
.rx_tr_out(Net_3191),
.tx_tr_out(Net_3192));
BLE_v2_30_1 BLE (
.clk(Net_3187));
endmodule
|
/**
Based on: https://github.com/dirjud/Nitro-Parts-lib-Xilinx
*/
`timescale 1ps/1ps
`default_nettype none
module clock_divider_sim #(
parameter DIVISOR = 2
) (
input wire CLK,
output reg CLOCK
);
integer cnt;
initial cnt = 0;
wire [31:0] DIV;
assign DIV = DIVISOR;
always @(posedge CLK)
if(cnt == DIVISOR -1)
cnt <= 0;
else
cnt <= cnt + 1;
initial CLOCK = 0;
always @(posedge CLK or negedge CLK) begin
if(cnt == DIVISOR-1 && CLK == 1'b1) // posedge
CLOCK <= 1;
else if (cnt == DIVISOR/2-1 && DIV[0] == 0 && CLK == 1'b1) // posedge
CLOCK <= 0;
else if (cnt == DIVISOR/2 && DIV[0] == 1 && CLK == 1'b0) // negedge
CLOCK <= 0;
end
endmodule
module DCM #(
parameter CLKFX_MULTIPLY = 4,
parameter CLKFX_DIVIDE = 1,
parameter CLKDV_DIVIDE = 2,
parameter CLKIN_PERIOD = 10,
parameter CLK_FEEDBACK = 0,
parameter CLKOUT_PHASE_SHIFT = 0,
parameter CLKIN_DIVIDE_BY_2 = "FALSE",
parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS",
parameter DFS_FREQUENCY_MODE = "LOW",
parameter DLL_FREQUENCY_MODE = "LOW",
parameter DUTY_CYCLE_CORRECTION = "TRUE",
parameter FACTORY_JF = 16'hC080,
parameter PHASE_SHIFT = 0,
parameter STARTUP_WAIT = "TRUE"
) (
CLK0,
CLK180,
CLK270,
CLK2X,
CLK2X180,
CLK90,
CLKDV,
CLKFX,
CLKFX180,
LOCKED,
PSDONE,
STATUS,
CLKFB,
CLKIN,
DSSEN,
PSCLK,
PSEN,
PSINCDEC,
RST
);
input wire CLKFB, CLKIN, DSSEN;
input wire PSCLK, PSEN, PSINCDEC, RST;
output wire CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
output wire CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
output wire [7:0] STATUS;
assign STATUS = 0;
assign CLK0 = CLKIN;
assign CLK180 = ~CLKIN;
assign CLK270 = ~CLK90;
assign CLK2X180 = ~CLK2X;
assign CLKFX180 = ~CLKFX;
wire resetb = ~RST;
wire clk2x;
clock_multiplier #(
.MULTIPLIER(2)
) i_clock_multiplier_two(
.CLK(CLKIN),
.CLOCK(clk2x)
);
reg clk90;
reg [1:0] cnt;
always @(posedge clk2x or negedge clk2x or negedge resetb) begin
if (!resetb) begin
clk90 <= 0;
cnt <= 0;
end else begin
cnt <= cnt + 1;
if (!cnt[0]) clk90 <= ~clk90;
end
end
assign CLK2X = clk2x;
assign CLK90 = clk90;
generate
if (CLKFX_MULTIPLY==2 && CLKFX_DIVIDE==1) begin
assign CLKFX = clk2x;
end else begin
wire CLKINM;
clock_multiplier #( .MULTIPLIER(CLKFX_MULTIPLY) ) i_clock_multiplier(.CLK(CLKIN),.CLOCK(CLKINM));
clock_divider_sim #(.DIVISOR(CLKFX_DIVIDE)) i_clock_divisor_rx (.CLK(CLKINM), .CLOCK(CLKFX));
end
endgenerate
clock_divider_sim #(
.DIVISOR(CLKDV_DIVIDE)
) i_clock_divisor_dv (
.CLK(CLKIN),
.CLOCK(CLKDV)
);
assign LOCKED = 1'b1;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// PCM Request Controller ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_prc.v,v 1.4 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.4 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_prc.v,v $
// Revision 1.4 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.3 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.2 2001/08/10 08:09:42 rudi
//
// - Removed RTY_O output.
// - Added Clock and Reset Inputs to documentation.
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:17 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_prc(clk, rst,
// SR Slot Interface
valid, in_valid, out_slt0,
in_slt0, in_slt1,
// Codec Register Access
crac_valid, crac_wr,
// Channel Configuration
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
// FIFO Status
o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
o9_empty, i3_full, i4_full, i6_full,
// FIFO Control
o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
i3_we, i4_we, i6_we
);
input clk, rst;
input valid;
input [2:0] in_valid;
output [15:0] out_slt0;
input [15:0] in_slt0;
input [19:0] in_slt1;
input crac_valid;
input crac_wr;
input [7:0] oc0_cfg;
input [7:0] oc1_cfg;
input [7:0] oc2_cfg;
input [7:0] oc3_cfg;
input [7:0] oc4_cfg;
input [7:0] oc5_cfg;
input [7:0] ic0_cfg;
input [7:0] ic1_cfg;
input [7:0] ic2_cfg;
input o3_empty;
input o4_empty;
input o6_empty;
input o7_empty;
input o8_empty;
input o9_empty;
input i3_full;
input i4_full;
input i6_full;
output o3_re;
output o4_re;
output o6_re;
output o7_re;
output o8_re;
output o9_re;
output i3_we;
output i4_we;
output i6_we;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire o3_re_l;
wire o4_re_l;
wire o6_re_l;
wire o7_re_l;
wire o8_re_l;
wire o9_re_l;
reg crac_valid_r;
reg crac_wr_r;
////////////////////////////////////////////////////////////////////
//
// Output Tag Assembly
//
assign out_slt0[15] = |out_slt0[14:6];
assign out_slt0[14] = crac_valid_r;
assign out_slt0[13] = crac_wr_r;
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 1'b0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
assign out_slt0[06] = o9_re_l;
assign out_slt0[5:0] = 6'h0;
////////////////////////////////////////////////////////////////////
//
// FIFO Control
//
always @(posedge clk)
if(valid) crac_valid_r <= #1 crac_valid;
always @(posedge clk)
if(valid) crac_wr_r <= #1 crac_valid & crac_wr;
// Output Channel 0 (Out Slot 3)
ac97_fifo_ctrl u0(
.clk( clk ),
.valid( valid ),
.ch_en( oc0_cfg[0] ),
.srs( oc0_cfg[1] ),
.full_empty( o3_empty ),
.req( ~in_slt1[11] ),
.crdy( in_slt0[15] ),
.en_out( o3_re ),
.en_out_l( o3_re_l )
);
// Output Channel 1 (Out Slot 4)
ac97_fifo_ctrl u1(
.clk( clk ),
.valid( valid ),
.ch_en( oc1_cfg[0] ),
.srs( oc1_cfg[1] ),
.full_empty( o4_empty ),
.req( ~in_slt1[10] ),
.crdy( in_slt0[15] ),
.en_out( o4_re ),
.en_out_l( o4_re_l )
);
`ifdef AC97_CENTER
// Output Channel 2 (Out Slot 6)
ac97_fifo_ctrl u2(
.clk( clk ),
.valid( valid ),
.ch_en( oc2_cfg[0] ),
.srs( oc2_cfg[1] ),
.full_empty( o6_empty ),
.req( ~in_slt1[8] ),
.crdy( in_slt0[15] ),
.en_out( o6_re ),
.en_out_l( o6_re_l )
);
`else
assign o6_re = 1'b0;
assign o6_re_l = 1'b0;
`endif
`ifdef AC97_SURROUND
// Output Channel 3 (Out Slot 7)
ac97_fifo_ctrl u3(
.clk( clk ),
.valid( valid ),
.ch_en( oc3_cfg[0] ),
.srs( oc3_cfg[1] ),
.full_empty( o7_empty ),
.req( ~in_slt1[7] ),
.crdy( in_slt0[15] ),
.en_out( o7_re ),
.en_out_l( o7_re_l )
);
// Output Channel 4 (Out Slot 8)
ac97_fifo_ctrl u4(
.clk( clk ),
.valid( valid ),
.ch_en( oc4_cfg[0] ),
.srs( oc4_cfg[1] ),
.full_empty( o8_empty ),
.req( ~in_slt1[6] ),
.crdy( in_slt0[15] ),
.en_out( o8_re ),
.en_out_l( o8_re_l )
);
`else
assign o7_re = 1'b0;
assign o7_re_l = 1'b0;
assign o8_re = 1'b0;
assign o8_re_l = 1'b0;
`endif
`ifdef AC97_LFE
// Output Channel 5 (Out Slot 9)
ac97_fifo_ctrl u5(
.clk( clk ),
.valid( valid ),
.ch_en( oc5_cfg[0] ),
.srs( oc5_cfg[1] ),
.full_empty( o9_empty ),
.req( ~in_slt1[5] ),
.crdy( in_slt0[15] ),
.en_out( o9_re ),
.en_out_l( o9_re_l )
);
`else
assign o9_re = 1'b0;
assign o9_re_l = 1'b0;
`endif
`ifdef AC97_SIN
// Input Channel 0 (In Slot 3)
ac97_fifo_ctrl u6(
.clk( clk ),
.valid( in_valid[0] ),
.ch_en( ic0_cfg[0] ),
.srs( ic0_cfg[1] ),
.full_empty( i3_full ),
.req( in_slt0[12] ),
.crdy( in_slt0[15] ),
.en_out( i3_we ),
.en_out_l( )
);
// Input Channel 1 (In Slot 4)
ac97_fifo_ctrl u7(
.clk( clk ),
.valid( in_valid[1] ),
.ch_en( ic1_cfg[0] ),
.srs( ic1_cfg[1] ),
.full_empty( i4_full ),
.req( in_slt0[11] ),
.crdy( in_slt0[15] ),
.en_out( i4_we ),
.en_out_l( )
);
`else
assign i3_we = 1'b0;
assign i4_we = 1'b0;
`endif
`ifdef AC97_MICIN
// Input Channel 2 (In Slot 6)
ac97_fifo_ctrl u8(
.clk( clk ),
.valid( in_valid[2] ),
.ch_en( ic2_cfg[0] ),
.srs( ic2_cfg[1] ),
.full_empty( i6_full ),
.req( in_slt0[9] ),
.crdy( in_slt0[15] ),
.en_out( i6_we ),
.en_out_l( )
);
`else
assign i6_we = 1'b0;
`endif
endmodule
|
/*
* Copyright (C)2005-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module aq_func_ctl(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output FUNC_START,
input FUNC_READY,
input FUNC_DONE
);
localparam A_FUNC_START = 8'h00;
localparam A_FUNC_STATUS = 8'h04;
localparam A_FUNC_ARGS_00 = 8'h10;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg reg_func_start, reg_func_start_d;
reg [31:0] reg_func_args_00;
reg [31:0] reg_rdata;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
// Write Register
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
reg_func_start <= 1'b0;
reg_func_start_d <= 1'b0;
reg_func_args_00 <= 32'd0;
end else begin
if(wr_ena & ((LOCAL_ADDR[7:0] & 8'hFC) == A_FUNC_START)) begin
reg_func_start <= 1'b1;
end else begin
reg_func_start <= 1'b0;
end
reg_func_start_d <= reg_func_start;
if(wr_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_FUNC_ARGS_00: begin
reg_func_args_00[31:0] <= LOCAL_WDATA[31:0];
end
default: begin
end
endcase
end
end
end
// Read Register
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
reg_rdata[31:0] <= 32'd0;
rd_ack <= 1'b0;
end else begin
rd_ack <= rd_ena;
if(rd_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_FUNC_START: begin
reg_rdata[31:0] <= 32'd0;
end
A_FUNC_STATUS: begin
reg_rdata[31:0] <= {30'd0, FUNC_READY, FUNC_DONE};
end
A_FUNC_ARGS_00: begin
reg_rdata[31:0] <= reg_func_args_00[31:0];
end
default: begin
reg_rdata[31:0] <= 32'd0;
end
endcase
end else begin
reg_rdata[31:0] <= 32'd0;
end
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign FUNC_START = (reg_func_start & ~reg_func_start_d)?1'b1:1'b0;
assign FUNC_ARGS_00 = reg_func_args_00;
endmodule
|
module fsa_stream #(
parameter integer C_TEST = 0,
parameter integer C_OUT_DW = 1,
parameter integer C_OUT_DV = 1,
parameter integer C_IMG_HW = 12,
parameter integer C_IMG_WW = 12,
parameter integer BR_AW = 12 /// same as C_IMG_WW
)(
input clk,
input resetn,
input wire [C_IMG_HW-1:0] height ,
input wire [C_IMG_WW-1:0] width ,
output wire rd_sof ,
output reg rd_en ,
output wire [BR_AW-1:0] rd_addr ,
input wire rd_black,
input wire rd_val_outer,
input wire [C_IMG_HW-1:0] rd_top_outer,
input wire [C_IMG_HW-1:0] rd_bot_outer,
input wire rd_val_inner,
input wire [C_IMG_HW-1:0] rd_top_inner,
input wire [C_IMG_HW-1:0] rd_bot_inner,
input wire lft_valid ,
input wire [C_IMG_WW-1:0] lft_edge ,
input wire rt_valid ,
input wire [C_IMG_WW-1:0] rt_edge ,
input wire lft_header_outer_valid,
input wire [C_IMG_WW-1:0] lft_header_outer_x ,
input wire lft_corner_valid,
input wire [C_IMG_WW-1:0] lft_corner_top_x,
input wire [C_IMG_HW-1:0] lft_corner_top_y,
input wire [C_IMG_WW-1:0] lft_corner_bot_x,
input wire [C_IMG_HW-1:0] lft_corner_bot_y,
input wire rt_header_outer_valid,
input wire [C_IMG_WW-1:0] rt_header_outer_x ,
input wire rt_corner_valid,
input wire [C_IMG_WW-1:0] rt_corner_top_x,
input wire [C_IMG_HW-1:0] rt_corner_top_y,
input wire [C_IMG_WW-1:0] rt_corner_bot_x,
input wire [C_IMG_HW-1:0] rt_corner_bot_y,
input wire fsync,
output wire m_axis_tvalid,
output wire [C_TEST+C_OUT_DW-1:0] m_axis_tdata,
output wire m_axis_tuser,
output wire m_axis_tlast,
input wire m_axis_tready
);
localparam integer FIFO_DW = 2 + C_OUT_DW + C_TEST;
localparam integer FD_SOF = 0;
localparam integer FD_LAST = 1;
localparam integer FD_DATA = 2;
localparam integer FD_TEST = 2 + C_OUT_DW;
assign rd_sof = fsync;
/// store fsa result
reg r_lft_valid ;
reg [C_IMG_WW-1:0] r_lft_edge ;
reg r_rt_valid ;
reg [C_IMG_WW-1:0] r_rt_edge ;
reg r_lft_header_outer_valid;
reg [C_IMG_WW-1:0] r_lft_header_outer_x ;
reg r_lft_corner_valid;
reg [C_IMG_WW-1:0] r_lft_corner_top_x;
reg [C_IMG_HW-1:0] r_lft_corner_top_y;
reg [C_IMG_WW-1:0] r_lft_corner_bot_x;
reg [C_IMG_HW-1:0] r_lft_corner_bot_y;
reg r_rt_header_outer_valid ;
reg [C_IMG_WW-1:0] r_rt_header_outer_x ;
reg r_rt_corner_valid ;
reg [C_IMG_WW-1:0] r_rt_corner_top_x ;
reg [C_IMG_HW-1:0] r_rt_corner_top_y ;
reg [C_IMG_WW-1:0] r_rt_corner_bot_x ;
reg [C_IMG_HW-1:0] r_rt_corner_bot_y ;
always @ (posedge clk) begin
if (fsync) begin
r_lft_valid <= lft_valid ;
r_lft_edge <= lft_edge ;
r_rt_valid <= rt_valid ;
r_rt_edge <= rt_edge ;
r_lft_header_outer_valid <= lft_header_outer_valid;
r_lft_header_outer_x <= lft_header_outer_x ;
r_lft_corner_valid <= lft_corner_valid;
r_lft_corner_top_x <= lft_corner_top_x;
r_lft_corner_top_y <= lft_corner_top_y;
r_lft_corner_bot_x <= lft_corner_bot_x;
r_lft_corner_bot_y <= lft_corner_bot_y;
r_rt_header_outer_valid <= rt_header_outer_valid ;
r_rt_header_outer_x <= rt_header_outer_x ;
r_rt_corner_valid <= rt_corner_valid ;
r_rt_corner_top_x <= rt_corner_top_x ;
r_rt_corner_top_y <= rt_corner_top_y ;
r_rt_corner_bot_x <= rt_corner_bot_x ;
r_rt_corner_bot_y <= rt_corner_bot_y ;
end
end
reg fw_en;
reg [FIFO_DW-1:0] fw_data;
wire fw_af;
wire fr_en;
wire[FIFO_DW-1:0] fr_data;
wire fr_empty;
simple_fifo # (
.DEPTH_WIDTH(3),
.DATA_WIDTH(FIFO_DW),
.ALMOST_FULL_TH(6),
.ALMOST_EMPTY_TH(1)
) fifo_inst (
.clk(clk),
.rst(~resetn),
.wr_data(fw_data),
.wr_en (fw_en ),
.rd_data(fr_data),
.rd_en (fr_en ),
.full(),
.empty(fr_empty),
.almost_full(fw_af),
.almost_empty()
);
reg working;
reg[C_IMG_WW-1:0] px;
reg[C_IMG_HW-1:0] py;
reg pfirst;
wire plast;
reg xlast;
reg ylast;
assign rd_addr = px;
assign plast = (xlast && ylast);
always @ (posedge clk) begin
if (resetn == 1'b0) begin
px <= 0;
py <= 0;
pfirst <= 1'b1;
xlast <= 0;
ylast <= 0;
end
else if (rd_en) begin
if (xlast)
px <= 0;
else
px <= px + 1;
xlast <= (px == width - 2);
if (xlast) begin
if (ylast)
py <= 0;
else
py <= py + 1;
ylast <= (py == height - 2);
end
if (plast)
pfirst <= 1;
else
pfirst <= 0;
end
end
always @ (posedge clk) begin
if (resetn == 1'b0)
working <= 1'b0;
else if (fsync)
working <= 1'b1;
else if (rd_en && plast)
working <= 1'b0;
end
always @ (posedge clk) begin
if (resetn == 1'b0)
rd_en <= 0;
else if ((working && ~fw_af)
&& ~(plast && rd_en))
rd_en <= 1;
else
rd_en <= 0;
end
reg rd_en_d1;
reg pfirst_d1;
reg xlast_d1;
reg [C_IMG_HW-1:0] py_d1;
reg [C_IMG_WW-1:0] px_d1;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d1 <= 0;
py_d1 <= 0;
px_d1 <= 0;
pfirst_d1 <= 0;
xlast_d1 <= 0;
end
else begin
rd_en_d1 <= rd_en;
px_d1 <= px;
py_d1 <= py;
pfirst_d1 <= pfirst;
xlast_d1 <= xlast;
end
end
reg rd_en_d2;
reg pfirst_d2;
reg xlast_d2;
reg [C_IMG_HW-1:0] py_d2;
reg [C_IMG_WW-1:0] px_d2;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d2 <= 0;
py_d2 <= 0;
px_d2 <= 0;
pfirst_d2 <= 0;
xlast_d2 <= 0;
end
else begin
rd_en_d2 <= rd_en_d1;
px_d2 <= px_d1;
py_d2 <= py_d1;
pfirst_d2 <= pfirst_d1;
xlast_d2 <= xlast_d1;
end
end
reg rd_en_d3;
reg pfirst_d3;
reg xlast_d3;
reg [C_IMG_HW-1:0] py_d3;
reg [C_IMG_WW-1:0] px_d3;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d3 <= 0;
py_d3 <= 0;
px_d3 <= 0;
pfirst_d3 <= 0;
xlast_d3 <= 0;
end
else begin
rd_en_d3 <= rd_en_d2;
py_d3 <= py_d2;
px_d3 <= px_d2;
pfirst_d3 <= pfirst_d2;
xlast_d3 <= xlast_d2;
end
end
/// rd_data is valid
reg rd_en_d4;
reg pfirst_d4;
reg xlast_d4;
//reg [C_IMG_HW-1:0] py_d4;
/// corner
reg lc_t;
reg lc_b;
reg rc_t;
reg rc_b;
/// body
reg lb;
reg lb_t;
reg lb_b;
reg rb;
reg rb_t;
reg rb_b;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
rd_en_d4 <= 0;
//py_d4 <= 0;
pfirst_d4 <= 0;
xlast_d4 <= 0;
lc_t <= 0;
lc_b <= 0;
rc_t <= 0;
rc_b <= 0;
lb <= 0;
lb_t <= 0;
lb_b <= 0;
rb <= 0;
rb_t <= 0;
rb_b <= 0;
end
else begin
rd_en_d4 <= rd_en_d3;
//py_d4 <= py_d3;
pfirst_d4 <= pfirst_d3;
xlast_d4 <= xlast_d3;
lc_t <= r_lft_corner_valid && ((r_lft_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (r_lft_corner_top_x < px_d3 && px_d3 <= r_lft_edge));
lc_b <= r_lft_corner_valid && ((r_lft_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (r_lft_corner_bot_x < px_d3 && px_d3 <= r_lft_edge));
rc_t <= r_rt_corner_valid && ((r_rt_corner_top_y <= py_d3 && py_d3 < rd_top_outer)
&& (r_rt_edge <= px_d3 && px_d3 < r_rt_corner_top_x));
rc_b <= r_rt_corner_valid && ((r_rt_corner_bot_y >= py_d3 && py_d3 > rd_bot_outer)
&& (r_rt_edge <= px_d3 && px_d3 < r_rt_corner_bot_x));
lb <= r_lft_header_outer_valid && (px_d3 <= r_lft_header_outer_x);
rb <= r_rt_header_outer_valid && (px_d3 >= r_rt_header_outer_x);
lb_t <= r_lft_corner_valid && ((px_d3 <= r_lft_corner_top_x) && (py_d3 < rd_top_outer));
lb_b <= r_lft_corner_valid && ((px_d3 <= r_lft_corner_bot_x) && (py_d3 > rd_bot_outer));
rb_t <= r_rt_corner_valid && ((px_d3 >= r_rt_corner_top_x) && (py_d3 < rd_top_outer));
rb_b <= r_rt_corner_valid && ((px_d3 >= r_rt_corner_bot_x) && (py_d3 > rd_bot_outer));
end
end
/// @NOTE: delay 5, the almost_full for blockram must be 6
/// if you add delay, don't forget to change blockram config.
always @ (posedge clk) begin
if (resetn == 1'b0) begin
fw_en <= 0;
fw_data <= 0;
end
else if (rd_en_d4) begin
fw_en <= 1'b1;
fw_data[FD_SOF] <= pfirst_d4;
fw_data[FD_LAST] <= xlast_d4;
if (1) begin
if ((r_lft_valid && (lc_t | lc_b))
|| (r_rt_valid && (rc_t | rc_b))) begin
fw_data[FD_DATA+C_OUT_DW-1:FD_DATA] <= C_OUT_DV;
end
else begin
fw_data[FD_DATA+C_OUT_DW-1:FD_DATA] <= 1'b0;
end
end
else begin
if (rd_val_outer && py_d4 >= rd_top_outer && py_d4 <= rd_bot_outer)
fw_data[FD_DATA+C_OUT_DW-1:FD_DATA] <= C_OUT_DV;
else
fw_data[FD_DATA+C_OUT_DW-1:FD_DATA] <= 1'b0;
end
end
else begin
fw_en <= 0;
end
end
generate
if (C_TEST > 0) begin
reg[C_TEST-1:0] test_d1;
reg[C_TEST-1:0] test_d2;
reg[C_TEST-1:0] test_d3;
always @ (posedge clk) begin
test_d1 <= px;
test_d2 <= test_d1;
test_d3 <= test_d2;
fw_data[FIFO_DW-1:FD_TEST] <= test_d3;
end
end
endgenerate
/////////////////////////////////// read side //////////////////////////
reg r_tvalid;
wire [FIFO_DW-FD_DATA-1:0] r_tdata;
wire r_tuser;
wire r_tlast;
wire r_tready;
assign fr_en = (~r_tvalid || r_tready) && ~fr_empty;
always @ (posedge clk) begin
if (resetn == 1'b0)
r_tvalid <= 0;
else if (fr_en)
r_tvalid <= 1;
else if (r_tready)
r_tvalid <= 0;
end
assign r_tdata = fr_data[FIFO_DW-1:FD_DATA];
assign r_tuser = fr_data[FD_SOF];
assign r_tlast = fr_data[FD_LAST];
axis_relay # (
.C_PIXEL_WIDTH(C_OUT_DW + C_TEST)
) relay_inst (
.clk(clk),
.resetn(resetn),
.s_axis_tvalid(r_tvalid),
.s_axis_tdata (r_tdata ),
.s_axis_tuser (r_tuser ),
.s_axis_tlast (r_tlast ),
.s_axis_tready(r_tready),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tdata (m_axis_tdata ),
.m_axis_tuser (m_axis_tuser ),
.m_axis_tlast (m_axis_tlast ),
.m_axis_tready(m_axis_tready)
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dds data to samples conversion
module cf_ddsv_vdma (
// vdma interface
vdma_clk,
vdma_fs,
vdma_valid,
vdma_data,
vdma_ready,
vdma_ovf,
vdma_unf,
// dac side (interpolator default) interface
dac_div3_clk,
dds_master_enable,
dds_rd,
dds_rdata,
// frame count (for vdma fs)
up_vdma_fscnt,
// debug data (chipscope)
vdma_dbg_data,
vdma_dbg_trigger,
// debug data (chipscope)
dac_dbg_data,
dac_dbg_trigger);
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
output vdma_ovf;
output vdma_unf;
// dac side (interpolator default) interface
input dac_div3_clk;
input dds_master_enable;
input dds_rd;
output [95:0] dds_rdata;
// frame count (for vdma fs)
input [15:0] up_vdma_fscnt;
// debug data (chipscope)
output [198:0] vdma_dbg_data;
output [ 7:0] vdma_dbg_trigger;
// debug data (chipscope)
output [107:0] dac_dbg_data;
output [ 7:0] dac_dbg_trigger;
reg dds_start_m1 = 'd0;
reg dds_start = 'd0;
reg [ 7:0] dds_raddr = 'd0;
reg [ 7:0] dds_raddr_g = 'd0;
reg [95:0] dds_rdata = 'd0;
reg vdma_master_enable_m1 = 'd0;
reg vdma_master_enable = 'd0;
reg vdma_master_enable_d = 'd0;
reg [15:0] vdma_fscnt = 'd0;
reg [15:0] vdma_rdcnt = 'd0;
reg vdma_fs = 'd0;
reg vdma_start = 'd0;
reg [ 1:0] vdma_dcnt = 'd0;
reg [63:0] vdma_data_d = 'd0;
reg vdma_wr = 'd0;
reg [ 7:0] vdma_waddr = 'd0;
reg [95:0] vdma_wdata = 'd0;
reg [ 7:0] vdma_raddr_g_m1 = 'd0;
reg [ 7:0] vdma_raddr_g_m2 = 'd0;
reg [ 7:0] vdma_raddr = 'd0;
reg [ 7:0] vdma_addr_diff = 'd0;
reg vdma_ready = 'd0;
reg vdma_almost_full = 'd0;
reg vdma_almost_empty = 'd0;
reg [ 4:0] vdma_ovf_count = 'd0;
reg vdma_ovf = 'd0;
reg [ 4:0] vdma_unf_count = 'd0;
reg vdma_unf = 'd0;
wire vdma_we_s;
wire [ 8:0] vdma_addr_diff_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [95:0] dds_rdata_s;
// binary to grey coversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// debug signals
assign vdma_dbg_trigger[7:7] = vdma_valid;
assign vdma_dbg_trigger[6:6] = vdma_ready;
assign vdma_dbg_trigger[5:5] = vdma_master_enable;
assign vdma_dbg_trigger[4:4] = vdma_start;
assign vdma_dbg_trigger[3:3] = vdma_wr;
assign vdma_dbg_trigger[2:2] = vdma_fs;
assign vdma_dbg_trigger[1:1] = vdma_ovf_s;
assign vdma_dbg_trigger[0:0] = vdma_unf_s;
assign vdma_dbg_data[198:198] = vdma_valid;
assign vdma_dbg_data[197:197] = vdma_ready;
assign vdma_dbg_data[196:196] = vdma_ovf;
assign vdma_dbg_data[195:195] = vdma_unf;
assign vdma_dbg_data[194:194] = vdma_fs;
assign vdma_dbg_data[193:193] = vdma_master_enable;
assign vdma_dbg_data[192:192] = vdma_start;
assign vdma_dbg_data[191:191] = vdma_wr;
assign vdma_dbg_data[190:190] = vdma_almost_full;
assign vdma_dbg_data[189:189] = vdma_almost_empty;
assign vdma_dbg_data[188:188] = vdma_we_s;
assign vdma_dbg_data[187:187] = vdma_ovf_s;
assign vdma_dbg_data[186:186] = vdma_unf_s;
assign vdma_dbg_data[185:184] = vdma_dcnt;
assign vdma_dbg_data[183:176] = vdma_waddr;
assign vdma_dbg_data[175:168] = vdma_raddr;
assign vdma_dbg_data[167:160] = vdma_addr_diff;
assign vdma_dbg_data[159: 96] = vdma_data;
assign vdma_dbg_data[ 95: 80] = vdma_rdcnt;
assign vdma_dbg_data[ 79: 64] = vdma_fscnt;
assign vdma_dbg_data[ 63: 0] = vdma_wdata[63:0];
assign dac_dbg_trigger[7:4] = 'd0;
assign dac_dbg_trigger[3:3] = dds_master_enable;
assign dac_dbg_trigger[2:2] = dds_rd;
assign dac_dbg_trigger[1:1] = dds_start_m1;
assign dac_dbg_trigger[0:0] = dds_start;
assign dac_dbg_data[107:107] = dds_master_enable;
assign dac_dbg_data[106:106] = dds_rd;
assign dac_dbg_data[105:105] = dds_start_m1;
assign dac_dbg_data[104:104] = dds_start;
assign dac_dbg_data[103: 96] = dds_raddr;
assign dac_dbg_data[ 95: 0] = dds_rdata;
// dds read and data output (nothing special)
always @(posedge dac_div3_clk) begin
dds_start_m1 <= vdma_start;
dds_start <= dds_start_m1;
if (dds_start == 1'b0) begin
dds_raddr <= 8'h80;
end else if (dds_rd == 1'b1) begin
dds_raddr <= dds_raddr + 1'b1;
end
dds_raddr_g <= b2g(dds_raddr);
dds_rdata <= dds_rdata_s;
end
// a free running counter is used to generate frame sync for vdma- it is up to the software
// to set it's value. the only thing is that it should be greater than the frame size.
always @(posedge vdma_clk) begin
vdma_master_enable_m1 <= dds_master_enable;
vdma_master_enable <= vdma_master_enable_m1;
vdma_master_enable_d <= vdma_master_enable;
if ((vdma_master_enable == 1'b1) && (vdma_master_enable_d == 1'b0)) begin
vdma_fscnt <= up_vdma_fscnt;
end
if (((vdma_master_enable == 1'b1) && (vdma_master_enable_d == 1'b0)) ||
(vdma_rdcnt >= vdma_fscnt)) begin
vdma_rdcnt <= 16'd0;
end else if (vdma_we_s == 1'b1) begin
vdma_rdcnt <= vdma_rdcnt + 1'b1;
end
if (((vdma_master_enable == 1'b1) && (vdma_master_enable_d == 1'b0)) ||
((vdma_rdcnt >= vdma_fscnt) && (vdma_master_enable_d == 1'b1))) begin
vdma_fs <= 1'b1;
end else begin
vdma_fs <= 1'b0;
end
end
// vdma write, the incoming data is 4 samples (64bits), in order to interface seamlessly to the
// OSERDES 3:1 ratio, the dac is set to read 3 (or 6) samples. So data is written to the
// memory as 6 samples (96bits).
assign vdma_we_s = vdma_valid & vdma_ready;
always @(posedge vdma_clk) begin
if (vdma_master_enable == 1'b0) begin
vdma_start <= 1'b0;
vdma_dcnt <= 2'd0;
vdma_data_d <= 64'd0;
vdma_wr <= 1'b0;
vdma_waddr <= 8'd0;
vdma_wdata <= 96'd0;
end else if (vdma_we_s == 1'b1) begin
vdma_start <= 1'b1;
if (vdma_dcnt >= 2'd2) begin
vdma_dcnt <= 2'd0;
end else begin
vdma_dcnt <= vdma_dcnt + 1'b1;
end
vdma_data_d <= vdma_data;
vdma_wr <= vdma_dcnt[0] | vdma_dcnt[1];
if (vdma_wr == 1'b1) begin
vdma_waddr <= vdma_waddr + 1'b1;
end
if (vdma_dcnt == 2'd1) begin
vdma_wdata[95:80] <= vdma_data_d[15: 0];
vdma_wdata[79:64] <= vdma_data_d[31:16];
vdma_wdata[63:48] <= vdma_data_d[47:32];
vdma_wdata[47:32] <= vdma_data_d[63:48];
vdma_wdata[31:16] <= vdma_data[15: 0];
vdma_wdata[15: 0] <= vdma_data[31:16];
end else begin
vdma_wdata[95:80] <= vdma_data_d[47:32];
vdma_wdata[79:64] <= vdma_data_d[63:48];
vdma_wdata[63:48] <= vdma_data[15: 0];
vdma_wdata[47:32] <= vdma_data[31:16];
vdma_wdata[31:16] <= vdma_data[47:32];
vdma_wdata[15: 0] <= vdma_data[63:48];
end
end
end
// overflow or underflow status
assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
assign vdma_ovf_s = (vdma_addr_diff < 3) ? vdma_almost_full : 1'b0;
assign vdma_unf_s = (vdma_addr_diff > 250) ? vdma_almost_empty : 1'b0;
always @(posedge vdma_clk) begin
vdma_raddr_g_m1 <= dds_raddr_g;
vdma_raddr_g_m2 <= vdma_raddr_g_m1;
vdma_raddr <= g2b(vdma_raddr_g_m2);
vdma_addr_diff <= vdma_addr_diff_s[7:0];
if (vdma_addr_diff >= 250) begin
vdma_ready <= ~vdma_master_enable;
end else if (vdma_addr_diff <= 200) begin
vdma_ready <= 1'b1;
end
vdma_almost_full = (vdma_addr_diff > 250) ? 1'b1 : 1'b0;
vdma_almost_empty = (vdma_addr_diff < 3) ? 1'b1 : 1'b0;
if (vdma_ovf_s == 1'b1) begin
vdma_ovf_count <= 5'h10;
end else if (vdma_ovf_count[4] == 1'b1) begin
vdma_ovf_count <= vdma_ovf_count + 1'b1;
end
vdma_ovf <= vdma_ovf_count[4];
if (vdma_unf_s == 1'b1) begin
vdma_unf_count <= 5'h10;
end else if (vdma_unf_count[4] == 1'b1) begin
vdma_unf_count <= vdma_unf_count + 1'b1;
end
vdma_unf <= vdma_unf_count[4];
end
// memory
cf_mem #(.DW(96), .AW(8)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (dac_div3_clk),
.addrb (dds_raddr),
.doutb (dds_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Controller ////
//// Serial Output Controller ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: ac97_soc.v,v 1.3 2002/09/19 06:30:56 rudi Exp $
//
// $Date: 2002/09/19 06:30:56 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: ac97_soc.v,v $
// Revision 1.3 2002/09/19 06:30:56 rudi
// Fixed a bug reported by Igor. Apparently this bug only shows up when
// the WB clock is very low (2x bit_clk). Updated Copyright header.
//
// Revision 1.2 2002/03/05 04:44:05 rudi
//
// - Fixed the order of the thrash hold bits to match the spec.
// - Many minor synthesis cleanup items ...
//
// Revision 1.1 2001/08/03 06:54:50 rudi
//
//
// - Changed to new directory structure
//
// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
// Initial Checkin
//
//
//
//
`include "ac97_defines.v"
module ac97_soc(clk, wclk, rst,
ps_ce, resume, suspended,
sync, out_le, in_valid, ld, valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] cnt;
reg sync_beat;
reg sync_resume;
reg [5:0] out_le;
reg ld;
reg valid;
reg [2:0] in_valid;
reg bit_clk_capture;
reg bit_clk_capture_r;
//reg bit_clk_r;
//reg bit_clk_r1;
reg bit_clk_e;
reg suspended;
wire to;
reg [5:0] to_cnt;
reg [3:0] res_cnt;
wire resume_done;
assign sync = sync_beat | sync_resume;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 8'hff;
else
if(suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 8'h1;
always @(posedge clk)
ld <= #1 (cnt == 8'h00);
always @(posedge clk)
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
always @(posedge clk)
valid <= #1 (cnt > 8'h39);
always @(posedge clk)
out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
always @(posedge clk)
out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
always @(posedge clk)
out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
always @(posedge clk)
out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
always @(posedge clk)
out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
always @(posedge clk)
out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
always @(posedge clk)
in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
always @(posedge clk)
in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
always @(posedge clk)
in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
always @(clk or bit_clk_e)
if(clk) bit_clk_capture <= #1 1'b1;
else
if(bit_clk_e) bit_clk_capture <= #1 1'b0;
//always @(posedge wclk)
// bit_clk_r <= #1 clk;
//
//always @(posedge wclk)
// bit_clk_r1 <= #1 bit_clk_r;
//
//always @(posedge wclk)
// bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
always @(posedge wclk)
bit_clk_capture_r <= #1 bit_clk_capture;
always @(posedge wclk)
bit_clk_e <= #1 bit_clk_capture_r;
always @(posedge wclk)
suspended <= #1 to;
assign to = (to_cnt == `AC97_SUSP_DET);
always @(posedge wclk or negedge rst)
if(!rst) to_cnt <= #1 6'h0;
else
if(bit_clk_e) to_cnt <= #1 6'h0;
else
if(!to) to_cnt <= #1 to_cnt + 6'h1;
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
always @(posedge wclk or negedge rst)
if(!rst) sync_resume <= #1 1'b0;
else
if(resume_done) sync_resume <= #1 1'b0;
else
if(suspended & resume) sync_resume <= #1 1'b1;
assign resume_done = (res_cnt == `AC97_RES_SIG);
always @(posedge wclk)
if(!sync_resume) res_cnt <= #1 4'h0;
else
if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC16 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* Last two bytes of the data
* CCCCCCCCCCCCCCCC
* C = CRC bit
*
* Hold in reset when not using
*
* Online documentation is way to fucking complicated
* x^16 + x^12 + x^5 + 1
* To find the polynomial remove the top x^16 then add 2^12 + 2^5 + 1 = 0x1021
*
*
* Changes:
* 2015.08.08: Initial Add
*
*/
module crc16 #(
parameter POLYNOMIAL = 16'h1021,
parameter SEED = 16'h0000
)(
input clk,
input rst,
input bit,
output reg [15:0] crc
);
//local parameters
//registes/wires
//submodules
//asynchronous logic
//synchronous logic
//XXX: Does this need to be asynchronous?
always @ (posedge clk) begin
if (rst) begin
crc <= SEED;
end
else begin
//Shift the output value
crc <= bit ? ({crc[14:0], 1'b0} ^ POLYNOMIAL) : {crc[14:0], 1'b0};
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:21:06 10/15/2013
// Design Name: Logica_Barra
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab4/lab_pong/Test_Logica_Barra.v
// Project Name: lab_pong
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Logica_Barra
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_Logica_Barra;
// Inputs
reg clock;
reg reset;
reg actualizar_posicion;
reg revisar_bordes;
reg up_sync;
reg down_sync;
// Outputs
wire [8:0] barra_y;
// Instantiate the Unit Under Test (UUT)
Logica_Barra uut (
.clock(clock),
.reset(reset),
.actualizar_posicion(actualizar_posicion),
.revisar_bordes(revisar_bordes),
.up_sync(up_sync),
.down_sync(down_sync),
.barra_y(barra_y)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
actualizar_posicion = 0;
revisar_bordes = 0;
up_sync = 0;
down_sync = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company: RMIT University
// Engineer: Matthew Myungha Kim
// [email protected], [email protected]
//
// Create Date: 14:32:00 18/03/2014
// Design Name: stimulus_gen
// Module Name: stimulus_gen
// Project Name: Streaming Media on Null Convention Logic
// Description: Stimulus signal generation for gates test - for Testbench
// Used .txt file read function
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module stimulus_gen(clk, rst, req, stm_value, rsb, gnt);
parameter INPUT_PORTS = 3;
parameter RESET_PORT = 1; // 0: no reset, 1: has reset
parameter RESET_SENS = 0; // 0: Active Low, 1: Active High
input clk;
input rst;
input req;
output [INPUT_PORTS-1: 0] stm_value;
output rsb;
output gnt;
reg rsb;
reg gnt;
reg [INPUT_PORTS-1:0] data;
integer fd;
integer code, dummy;
reg [(INPUT_PORTS)*8-1:0] str;
assign stm_value = data;
initial begin
rsb = 1'b0;
gnt = 1'b0;
@(posedge clk);
#100;
@(posedge clk);
wait (req == 1'b1);
@(posedge clk);
//@(posedge clk);
if(RESET_PORT == 0) begin
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added because of <CR><LF> of .txt file
rsb = 1'b0;
$monitor("data = %b", data);
@(posedge clk);
end
end
else if(RESET_PORT == 1) begin
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added because of <CR><LF> of .txt file
rsb = 1'b0; // Reset generation to 0
$monitor("data = %b", data);
@(posedge clk);
end
// close the file for next file open
$fclose(fd);
// select stimulus input text file
if(INPUT_PORTS == 1)
fd = $fopen("ncl_stimul_1input.txt","r");
else if(INPUT_PORTS == 2)
fd = $fopen("ncl_stimul_2input.txt","r");
else if(INPUT_PORTS == 3)
fd = $fopen("ncl_stimul_3input.txt","r");
else if(INPUT_PORTS == 4)
fd = $fopen("ncl_stimul_4input.txt","r");
data = {INPUT_PORTS-1{1'b0}};
code = 1;
while (code) begin
code = $fgets(str, fd);
dummy = $sscanf(str, "%b", data);
code = $fgets(str, fd); // added to remove <CR><LF> of .txt file
rsb = 1'b1; // Reset generation to 1
$monitor("data = %b", data);
@(posedge clk);
end
$fclose(fd);
end
@(posedge clk);
gnt = 1'b1;
@(posedge clk);
gnt = 1'b0;
#100;
end
endmodule
//////////////////////////////////////////////////////////
// Example
//////////////////////////////////////////////////////////
// 3-input stimulus example
// Null to Data sequence
// 000
// ->
// 001 010 100
// -> -> ->
// 011 101 011 110 101 110
// -> -> -> -> -> ->
// 111 111 111 111 111 111
// 000
// 001
// 011
// 111
// 000
// 001
// 101
// 111
// 000
// 010
// 011
// 111
// 000
// 010
// 110
// 111
// 000
// 100
// 101
// 111
// 000
// 100
// 110
// 111
// Alse we need to check more than two value change cases
// 000
// 011
// 111
// 000
// 110
// 111
// 000
// 101
// 111
// 000
// 111
// Data to Null sequence
// 111
// ->
// 110 101 011
// -> -> ->
// 100 010 100 001 010 001
// -> -> -> -> -> ->
// 000 000 000 000 000 000
// 111
// 110
// 100
// 000
// 111
// 110
// 010
// 000
// 111
// 101
// 100
// 000
// 111
// 101
// 001
// 000
// 111
// 011
// 010
// 000
// 111
// 011
// 001
// 000
// Alse we need to check more than two value change cases
// 111
// 100
// 000
// 111
// 001
// 000
// 111
// 010
// 000
// 111
// 000
// NCL doesn't allow these type of signal changes
// 0000
// 0100
// 0010 -> This is illegal
// 0011
// 1100 -> This is illegal
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Tue Jul 4 08:52:39 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.2 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_b.v,v $
// Revision 1.2 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No user `defines in this module
module ent_b
//
// Generated Module inst_b
//
(
port_b_1, // Will create p_mix_sig_1_go port
port_b_3, // Interhierachy link, will create p_mix_sig_3_go
port_b_4, // Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1, // Bus, single bits go to outside, will create p_mix_sig_5_2_2_go
port_b_5_2, // Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO
port_b_6i, // Conflicting definition
port_b_6o, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08 // VHDL intermediate needed (port name)
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
`ifdef exclude_inst_ba
`else
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
`endif
`ifdef exclude_inst_bb
`else
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
`endif
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFINV_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
fan_pwm,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_oen,
linear_flash_wen,
linear_flash_dq_io,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
adc_clk_in_p,
adc_clk_in_n,
adc_or_in_p,
adc_or_in_n,
adc_data_in_p,
adc_data_in_n,
ref_clk_out_p,
ref_clk_out_n );
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output fan_pwm;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
output linear_flash_oen;
output linear_flash_wen;
inout [15:0] linear_flash_dq_io;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
input adc_clk_in_p;
input adc_clk_in_n;
input adc_or_in_p;
input adc_or_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
output ref_clk_out_p;
output ref_clk_out_n;
// internal registers
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg dac_dma_rd = 'd0;
reg adc_data_cnt = 'd0;
reg adc_dma_wr = 'd0;
reg [31:0] adc_dma_wdata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire dac_clk;
wire dac_valid_0;
wire dac_enable_0;
wire dac_valid_1;
wire dac_enable_1;
wire [63:0] dac_dma_rdata;
wire adc_clk;
wire adc_valid_0;
wire adc_enable_0;
wire [15:0] adc_data_0;
wire adc_valid_1;
wire adc_enable_1;
wire [15:0] adc_data_1;
wire ref_clk;
wire oddr_ref_clk;
// assignments
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
i_oddr_ref_clk (
.S (1'b0),
.CE (1'b1),
.R (1'b0),
.C (ref_clk),
.D1 (1'b1),
.D2 (1'b0),
.Q (oddr_ref_clk));
OBUFDS i_obufds_ref_clk (
.I (oddr_ref_clk),
.O (ref_clk_out_p),
.OB (ref_clk_out_n));
always @(posedge dac_clk) begin
dac_dma_rd <= dac_valid_0 & dac_enable_0;
dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
end
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_1, adc_enable_0})
2'b10: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
end
2'b01: begin
adc_dma_wr <= adc_data_cnt;
adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
end
default: begin
adc_dma_wr <= 1'b1;
adc_dma_wdata <= {adc_data_1, adc_data_0};
end
endcase
end
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.linear_flash_dq_io(linear_flash_dq_io),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.adc_clk (adc_clk),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_dma_wdata (adc_dma_wdata),
.adc_dma_wr (adc_dma_wr),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_or_in_n (adc_or_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_valid_0 (adc_valid_0),
.adc_valid_1 (adc_valid_1),
.dac_clk (dac_clk),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_dma_rd (dac_dma_rd),
.dac_dma_rdata (dac_dma_rdata),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_frame_out_n (dac_frame_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_valid_0 (dac_valid_0),
.dac_valid_1 (dac_valid_1),
.ref_clk (ref_clk),
.mb_intr_06 (1'b0),
.mb_intr_07 (1'b0),
.mb_intr_08 (1'b0),
.mb_intr_14 (1'b0),
.mb_intr_15 (1'b0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (8'hff),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 7
(* X_CORE_INFO = "axi_protocol_converter_v2_1_7_axi_protocol_converter,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_auto_pc_0,axi_protocol_converter_v2_1_7_axi_protocol_converter,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_7_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
//
// This module implements a 16 bit SPI slave.
// The main module name is spi.
//
// A parallel output shift register clocked on rising edge
module spirdshft(
output [7:0] dout,
input din,
input clk,
input en);
reg [7:0] doutregister = 8'h00;
assign dout = doutregister;
always @(posedge clk) begin
if(en) begin
doutregister[7:1] <= doutregister[6:0];
doutregister[0] <= din; // Clocked into LSB first
end
end
endmodule
// A parallel input shift register clocked on falling edge
module spiwrshft(
output out,
input [7:0] parallelin,
input rdld,
input clk);
reg [7:0] dinregister = 8'h00;
assign out = dinregister[7];
always @(negedge clk) begin
if(rdld)
dinregister <= parallelin;
else begin
dinregister[7:1] <= dinregister[6:0];
end
end
endmodule
// Clock counter
module spiclkcounter(
output [3:0] clkcount,
input clk,
input en);
reg [3:0] countreg = 0;
assign clkcount = countreg;
// en is async
always @(posedge clk, negedge en) begin
if(en)
countreg <= countreg + 1;
else
countreg <= 4'h0;
end
endmodule
// Address register
module addrregister(
output [3:0] addr,
input clk,
input din,
input en);
reg [3:0] addrreg = 0;
assign addr = addrreg;
always @(posedge clk) begin
if(en) begin
addrreg[3:1] <= addrreg[2:0];
addrreg[0] <= din; // Clocked into MSB first
end
end
endmodule
// Mode register (Stores first bit shifted out as read/~write in a 16 bit transaction)
module moderegister(
output mode,
input clk,
input modet,
input in);
reg modereg = 0;
assign mode = modereg;
always@(posedge clk) begin
if(modet)
modereg = in; // Save the state of the input bit
end
endmodule
// Decode SPI counter counts into transactions
module spiseq(
input [3:0] spiclkcounter,
input spien,
input mode,
output addrt,
output spioe,
output rdt,
output rdld,
output wrt,
output modet);
reg modetreg;
reg addrtreg;
reg rdtreg;
reg wrtreg;
reg rdldreg;
reg spioereg;
assign modet = modetreg;
assign addrt = addrtreg;
assign rdt = rdtreg;
assign wrt = wrtreg;
assign rdld = rdldreg;
assign spioe = spioereg;
always @(*) begin
modetreg = 0;
rdtreg = 0;
addrtreg = 0;
wrtreg = 0;
rdldreg = 0;
spioereg = spien & mode;
case(spiclkcounter)
4'h0:
modetreg <= 1; // Signal to load mode register
4'h1, 4'h2, 4'h3, 4'h4:
addrtreg <= spien; // Signal to load address register
4'h5, 4'h6, 4'h7:
rdtreg <= (mode & spien); // Signal to indicate read transaction
4'h8:
begin
rdtreg <= (mode & spien); // Signal to indicate read transaction
rdldreg <= (mode & spien); // Load shift register
wrtreg <= (~mode & spien); // Signal to indicate write transaction
end
4'h9, 4'ha, 4'hb,
4'hc, 4'hd, 4'he, 4'hf:
wrtreg <= (~mode & spien); // Signal to indicate write transaction
default:
begin
rdtreg <= 1'bx;
wrtreg <= 1'bx;
addrtreg <= 1'bx;
modetreg <= 1'bx;
rdldreg <= 1'bx;
end
endcase
end
endmodule
// Main interface
module spi(
output spidout, // Data to master (MISO)
output rdt, // Indicates a read transaction
output wrt, // Indicates a write transaction
output spioe, // MISO 3 state enable
output [7:0] wrtdata, // Parallel write data out
output [3:0] addr, // Parallel address out
input spien, // SPI enable (SS)
input spiclk, // SPI clock (SCLK)
input spidin, // SPIDIN (MOSI)
input [7:0] rddata); // Parallel read data in
wire mode;
wire rdld;
wire modet;
wire addrt;
wire [3:0] clkcount;
spiclkcounter scc (
.clk(spiclk),
.en(spien),
.clkcount(clkcount));
moderegister mreg (
.clk(spiclk),
.modet(modet),
.in(spidin),
.mode(mode));
addrregister areg (
.clk(spiclk),
.en(addrt),
.din(spidin),
.addr(addr));
spirdshft srs (
.clk(spiclk),
.din(spidin),
.en(wrt),
.dout(wrtdata));
spiwrshft sws (
.clk(spiclk),
.parallelin(rddata),
.rdld(rdld),
.out(spidout));
spiseq ssq (
.spiclkcounter(clkcount),
.spien(spien),
.mode(mode),
.modet(modet),
.spioe(spioe),
.addrt(addrt),
.rdt(rdt),
.rdld(rdld),
.wrt(wrt));
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 12 11:09:14 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/dds/dds_funcsim.v
// Design : dds
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "dds,dds_compiler_v6_0,{}" *)
(* core_generation_info = "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=22,C_CHANNELS=1,C_HAS_PHASE_OUT=1,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=24,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=1,C_M_PHASE_TDATA_WIDTH=24,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}" *)
(* NotValidForBitStream *)
module dds
(aclk,
s_axis_phase_tvalid,
s_axis_phase_tdata,
m_axis_data_tvalid,
m_axis_data_tdata,
m_axis_phase_tvalid,
m_axis_phase_tdata);
(* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID" *) input s_axis_phase_tvalid;
input [23:0]s_axis_phase_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID" *) output m_axis_phase_tvalid;
output [23:0]m_axis_phase_tdata;
wire aclk;
wire [31:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
wire [23:0]m_axis_phase_tdata;
wire m_axis_phase_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tvalid;
wire NLW_U0_debug_axi_resync_in_UNCONNECTED;
wire NLW_U0_debug_core_nd_UNCONNECTED;
wire NLW_U0_debug_phase_nd_UNCONNECTED;
wire NLW_U0_event_phase_in_invalid_UNCONNECTED;
wire NLW_U0_event_pinc_invalid_UNCONNECTED;
wire NLW_U0_event_poff_invalid_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_missing_UNCONNECTED;
wire NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_U0_m_axis_data_tlast_UNCONNECTED;
wire NLW_U0_m_axis_phase_tlast_UNCONNECTED;
wire NLW_U0_s_axis_config_tready_UNCONNECTED;
wire NLW_U0_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_U0_debug_axi_chan_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_pinc_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_axi_poff_in_UNCONNECTED;
wire [21:0]NLW_U0_debug_phase_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_phase_tuser_UNCONNECTED;
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "0" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "1" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "1" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "7" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "9" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "32" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "24" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "2" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "16" *)
(* C_PHASE_ANGLE_WIDTH = "16" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
ddsdds_compiler_v6_0__parameterized0 U0
(.aclk(aclk),
.aclken(1'b1),
.aresetn(1'b1),
.debug_axi_chan_in(NLW_U0_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_U0_debug_axi_pinc_in_UNCONNECTED[21:0]),
.debug_axi_poff_in(NLW_U0_debug_axi_poff_in_UNCONNECTED[21:0]),
.debug_axi_resync_in(NLW_U0_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_U0_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_U0_debug_phase_UNCONNECTED[21:0]),
.debug_phase_nd(NLW_U0_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_U0_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_U0_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_U0_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_U0_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(NLW_U0_event_s_phase_tlast_missing_UNCONNECTED),
.event_s_phase_tlast_unexpected(NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(m_axis_phase_tdata),
.m_axis_phase_tlast(NLW_U0_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(1'b0),
.m_axis_phase_tuser(NLW_U0_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(m_axis_phase_tvalid),
.s_axis_config_tdata(1'b0),
.s_axis_config_tlast(1'b0),
.s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_phase_tdata(s_axis_phase_tdata),
.s_axis_phase_tlast(1'b0),
.s_axis_phase_tready(NLW_U0_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(1'b0),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
(* ORIG_REF_NAME = "dds_compiler_v6_0" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "9" *) (* C_ACCUMULATOR_WIDTH = "22" *) (* C_CHANNELS = "1" *)
(* C_HAS_PHASE_OUT = "1" *) (* C_HAS_PHASEGEN = "1" *) (* C_HAS_SINCOS = "1" *)
(* C_LATENCY = "7" *) (* C_MEM_TYPE = "1" *) (* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "0" *) (* C_OUTPUTS_REQUIRED = "2" *)
(* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "16" *) (* C_PHASE_ANGLE_WIDTH = "16" *)
(* C_PHASE_INCREMENT = "3" *) (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_RESYNC = "0" *)
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_OPTIMISE_GOAL = "0" *)
(* C_USE_DSP48 = "0" *) (* C_POR_MODE = "0" *) (* C_AMPLITUDE = "0" *)
(* C_HAS_ACLKEN = "0" *) (* C_HAS_ARESETN = "0" *) (* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *) (* C_HAS_S_PHASE = "1" *) (* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TUSER_WIDTH = "1" *) (* C_HAS_S_CONFIG = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *) (* C_HAS_M_DATA = "1" *)
(* C_M_DATA_TDATA_WIDTH = "32" *) (* C_M_DATA_HAS_TUSER = "0" *) (* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_HAS_M_PHASE = "1" *) (* C_M_PHASE_TDATA_WIDTH = "24" *) (* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_CHAN_WIDTH = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
module ddsdds_compiler_v6_0__parameterized0
(aclk,
aclken,
aresetn,
s_axis_phase_tvalid,
s_axis_phase_tready,
s_axis_phase_tdata,
s_axis_phase_tlast,
s_axis_phase_tuser,
s_axis_config_tvalid,
s_axis_config_tready,
s_axis_config_tdata,
s_axis_config_tlast,
m_axis_data_tvalid,
m_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tlast,
m_axis_data_tuser,
m_axis_phase_tvalid,
m_axis_phase_tready,
m_axis_phase_tdata,
m_axis_phase_tlast,
m_axis_phase_tuser,
event_pinc_invalid,
event_poff_invalid,
event_phase_in_invalid,
event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected,
event_s_phase_chanid_incorrect,
event_s_config_tlast_missing,
event_s_config_tlast_unexpected,
debug_axi_pinc_in,
debug_axi_poff_in,
debug_axi_resync_in,
debug_axi_chan_in,
debug_core_nd,
debug_phase,
debug_phase_nd);
input aclk;
input aclken;
input aresetn;
input s_axis_phase_tvalid;
output s_axis_phase_tready;
input [23:0]s_axis_phase_tdata;
input s_axis_phase_tlast;
input [0:0]s_axis_phase_tuser;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [0:0]s_axis_config_tdata;
input s_axis_config_tlast;
output m_axis_data_tvalid;
input m_axis_data_tready;
output [31:0]m_axis_data_tdata;
output m_axis_data_tlast;
output [0:0]m_axis_data_tuser;
output m_axis_phase_tvalid;
input m_axis_phase_tready;
output [23:0]m_axis_phase_tdata;
output m_axis_phase_tlast;
output [0:0]m_axis_phase_tuser;
output event_pinc_invalid;
output event_poff_invalid;
output event_phase_in_invalid;
output event_s_phase_tlast_missing;
output event_s_phase_tlast_unexpected;
output event_s_phase_chanid_incorrect;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output [21:0]debug_axi_pinc_in;
output [21:0]debug_axi_poff_in;
output debug_axi_resync_in;
output [0:0]debug_axi_chan_in;
output debug_core_nd;
output [21:0]debug_phase;
output debug_phase_nd;
wire \<const0> ;
wire aclk;
wire aclken;
wire aresetn;
wire [0:0]debug_axi_chan_in;
wire [21:0]debug_axi_pinc_in;
wire [21:0]debug_axi_poff_in;
wire debug_core_nd;
wire [21:0]debug_phase;
wire debug_phase_nd;
wire event_phase_in_invalid;
wire event_pinc_invalid;
wire event_poff_invalid;
wire event_s_config_tlast_missing;
wire event_s_config_tlast_unexpected;
wire event_s_phase_chanid_incorrect;
wire event_s_phase_tlast_missing;
wire event_s_phase_tlast_unexpected;
wire [31:0]m_axis_data_tdata;
wire m_axis_data_tlast;
wire m_axis_data_tready;
wire [0:0]m_axis_data_tuser;
wire m_axis_data_tvalid;
wire [23:0]m_axis_phase_tdata;
wire m_axis_phase_tlast;
wire m_axis_phase_tready;
wire [0:0]m_axis_phase_tuser;
wire m_axis_phase_tvalid;
wire [0:0]s_axis_config_tdata;
wire s_axis_config_tlast;
wire s_axis_config_tready;
wire s_axis_config_tvalid;
wire [23:0]s_axis_phase_tdata;
wire s_axis_phase_tlast;
wire s_axis_phase_tready;
wire [0:0]s_axis_phase_tuser;
wire s_axis_phase_tvalid;
wire NLW_i_synth_debug_axi_resync_in_UNCONNECTED;
assign debug_axi_resync_in = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ACCUMULATOR_WIDTH = "22" *)
(* C_AMPLITUDE = "0" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "1" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "1" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "1" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "7" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "9" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "32" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "24" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "2" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "16" *)
(* C_PHASE_ANGLE_WIDTH = "16" *)
(* C_PHASE_INCREMENT = "3" *)
(* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "24" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* secure_extras = "A" *)
ddsdds_compiler_v6_0_viv__parameterized0 i_synth
(.aclk(aclk),
.aclken(aclken),
.aresetn(aresetn),
.debug_axi_chan_in(debug_axi_chan_in),
.debug_axi_pinc_in(debug_axi_pinc_in),
.debug_axi_poff_in(debug_axi_poff_in),
.debug_axi_resync_in(NLW_i_synth_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(debug_core_nd),
.debug_phase(debug_phase),
.debug_phase_nd(debug_phase_nd),
.event_phase_in_invalid(event_phase_in_invalid),
.event_pinc_invalid(event_pinc_invalid),
.event_poff_invalid(event_poff_invalid),
.event_s_config_tlast_missing(event_s_config_tlast_missing),
.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected),
.event_s_phase_chanid_incorrect(event_s_phase_chanid_incorrect),
.event_s_phase_tlast_missing(event_s_phase_tlast_missing),
.event_s_phase_tlast_unexpected(event_s_phase_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tuser(m_axis_data_tuser),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(m_axis_phase_tdata),
.m_axis_phase_tlast(m_axis_phase_tlast),
.m_axis_phase_tready(m_axis_phase_tready),
.m_axis_phase_tuser(m_axis_phase_tuser),
.m_axis_phase_tvalid(m_axis_phase_tvalid),
.s_axis_config_tdata(s_axis_config_tdata),
.s_axis_config_tlast(s_axis_config_tlast),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_phase_tdata(s_axis_phase_tdata),
.s_axis_phase_tlast(s_axis_phase_tlast),
.s_axis_phase_tready(s_axis_phase_tready),
.s_axis_phase_tuser(s_axis_phase_tuser),
.s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
d8xvwbfVVOwe18UXp6OIppOfMlqR2kjI/C6xX05FTHU8t5J1FuCayg1b8DV73j0+lrSU5NbPke7J
wKyKo6vZmQ==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
eHeURXmQty7NeAv3XUoO5qZy5wiWI4KdVxtm2GsoWgcVxvm19Vpj0GV1w7gFqCWnA4FOQTZuRczj
Ij8Zgd4djaP+0m+uF1VB+55mfNaKcPG2LmiRY6n1d+6aXiDzlcGYYizcbBz72kRf3eOIqxpeA4D2
3Z2PIkm8MwLtPGSJ/Po=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
qH9+GhW8bT+j42lWyvygK5/6l4trt1BCmWOpQcKA/HZx2kAGsb+FDG/Xy6w33wIiMr/qkXwfaeaz
zlfzzUtccPjNghsznvMRED7lhG+MVvWZ9dxb/eJgA8z59jDK+8wSykzMrx433vlospEmnUeHAQ+H
4dfYGCJl9cTzNC+uQlFaZQsxHSBPlOlJ0GYkyCUnHQQjAEI62DNG0kEkyaiojOK+3cvYSaF6wa2m
I1Cx0Gw1ktdWILhOWUSpxci92nn54fp2GViAZYTlm0DB4uFKOskBdOQytDP2f2b1yNgPb5maNLgm
+O1ey7vhDLFg2yHH9hL6wSCP3onvhEE46TJLQA==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 323440)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module stopwatch(CLOCK_50, KEY, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input CLOCK_50;
input [1:0] KEY;
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
wire ms_clk;
wire tenths_in, ones_in, tens_in;
wire [3:0] hundredths_bcd, tenths_bcd, ones_bcd, tens_bcd;
ms_clock ms_clock1(CLOCK_50, clk);
ms_clock_switched ms_clock_switched1(clk, KEY[0], ms_clk);
bcd_counter bcd_counter_hundredths(ms_clk, KEY[1], hundredths_bcd[3:0], tenths_in);
bcd_counter bcd_counter_tenths(tenths_in, KEY[1], tenths_bcd[3:0], ones_in);
bcd_counter bcd_counter_ones(ones_in, KEY[1], ones_bcd[3:0], tens_in);
bcd_counter bcd_counter_tens(tens_in, KEY[1], tens_bcd[3:0], );
seven_segment_decoder seven_segment_decoder_hundredths(hundredths_bcd[3:0], HEX4[0:6]);
seven_segment_decoder seven_segment_decoder_tenths(tenths_bcd[3:0], HEX5[0:6]);
seven_segment_decoder seven_segment_decoder_ones(ones_bcd[3:0], HEX6[0:6]);
seven_segment_decoder seven_segment_decoder_tens(tens_bcd[3:0], HEX7[0:6]);
//Turn the unused displays off
assign HEX3[0:6] = 7'b0100100;
assign HEX2[0:6] = 7'b0110000;
assign HEX1[0:6] = 7'b0110001;
assign HEX0[0:6] = 7'b0100100;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 10.1.03
// \ \ Application : xaw2verilog
// / / Filename : FB_MULT_ADD.v
// /___/ /\ Timestamp : 06/27/2012 17:04:17
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle H:/Firmware_archive/Ben/stopped40MHz/FONT5_9Chan/FB_MULT_ADD.xaw -st FB_MULT_ADD.v
//Design Name: FB_MULT_ADD
//Device: xc5vlx50t-3ff1136
//
// Module FB_MULT_ADD
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module FB_MULT_ADD(A_IN,
B_IN,
CEMULTCARRYIN_IN,
CLK_IN,
C_IN,
P_OUT);
input [20:0] A_IN;
input [12:0] B_IN;
input CEMULTCARRYIN_IN;
input CLK_IN;
input [47:0] C_IN;
output [47:0] P_OUT;
wire GND_ALUMODE;
wire [2:0] GND_BUS_3;
wire [17:0] GND_BUS_18;
wire [29:0] GND_BUS_30;
wire [47:0] GND_BUS_48;
wire GND_OPMODE;
wire VCC_OPMODE;
assign GND_ALUMODE = 0;
assign GND_BUS_3 = 3'b000;
assign GND_BUS_18 = 18'b000000000000000000;
assign GND_BUS_30 = 30'b000000000000000000000000000000;
assign GND_BUS_48 = 48'b000000000000000000000000000000000000000000000000;
assign GND_OPMODE = 0;
assign VCC_OPMODE = 1;
DSP48E DSP48E_INST (.A({A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20],
A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20], A_IN[20:20],
A_IN[20:0]}),
.ACIN(GND_BUS_30[29:0]),
.ALUMODE({GND_ALUMODE, GND_ALUMODE, GND_ALUMODE,
GND_ALUMODE}),
.B({B_IN[12:12], B_IN[12:12], B_IN[12:12], B_IN[12:12],
B_IN[12:12], B_IN[12:0]}),
.BCIN(GND_BUS_18[17:0]),
.C(C_IN[47:0]),
.CARRYCASCIN(GND_ALUMODE),
.CARRYIN(GND_ALUMODE),
.CARRYINSEL(GND_BUS_3[2:0]),
.CEALUMODE(VCC_OPMODE),
.CEA1(VCC_OPMODE),
.CEA2(VCC_OPMODE),
.CEB1(VCC_OPMODE),
.CEB2(VCC_OPMODE),
.CEC(VCC_OPMODE),
.CECARRYIN(VCC_OPMODE),
.CECTRL(VCC_OPMODE),
.CEM(VCC_OPMODE),
.CEMULTCARRYIN(CEMULTCARRYIN_IN),
.CEP(VCC_OPMODE),
.CLK(CLK_IN),
.MULTSIGNIN(GND_ALUMODE),
.OPMODE({GND_OPMODE, VCC_OPMODE, VCC_OPMODE, GND_OPMODE,
VCC_OPMODE, GND_OPMODE, VCC_OPMODE}),
.PCIN(GND_BUS_48[47:0]),
.RSTA(GND_ALUMODE),
.RSTALLCARRYIN(GND_ALUMODE),
.RSTALUMODE(GND_ALUMODE),
.RSTB(GND_ALUMODE),
.RSTC(GND_ALUMODE),
.RSTCTRL(GND_ALUMODE),
.RSTM(GND_ALUMODE),
.RSTP(GND_ALUMODE),
.ACOUT(),
.BCOUT(),
.CARRYCASCOUT(),
.CARRYOUT(),
.MULTSIGNOUT(),
.OVERFLOW(),
.P(P_OUT[47:0]),
.PATTERNBDETECT(),
.PATTERNDETECT(),
.PCOUT(),
.UNDERFLOW());
defparam DSP48E_INST.ACASCREG = 1;
defparam DSP48E_INST.ALUMODEREG = 0;
defparam DSP48E_INST.AREG = 1;
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT = "FALSE";
defparam DSP48E_INST.AUTORESET_PATTERN_DETECT_OPTINV = "MATCH";
defparam DSP48E_INST.A_INPUT = "DIRECT";
defparam DSP48E_INST.BCASCREG = 1;
defparam DSP48E_INST.BREG = 1;
defparam DSP48E_INST.B_INPUT = "DIRECT";
defparam DSP48E_INST.CARRYINREG = 0;
defparam DSP48E_INST.CARRYINSELREG = 0;
defparam DSP48E_INST.CREG = 1;
defparam DSP48E_INST.MASK = 48'h3FFFFFFFFFFF;
defparam DSP48E_INST.MREG = 1;
defparam DSP48E_INST.MULTCARRYINREG = 1;
defparam DSP48E_INST.OPMODEREG = 0;
defparam DSP48E_INST.PATTERN = 48'h000000000000;
defparam DSP48E_INST.PREG = 1;
defparam DSP48E_INST.SEL_MASK = "MASK";
defparam DSP48E_INST.SEL_PATTERN = "PATTERN";
defparam DSP48E_INST.SEL_ROUNDING_MASK = "SEL_MASK";
defparam DSP48E_INST.USE_MULT = "MULT_S";
defparam DSP48E_INST.USE_PATTERN_DETECT = "NO_PATDET";
defparam DSP48E_INST.USE_SIMD = "ONE48";
endmodule
|
module PLLE2_BASE (/*AUTOARG*/
// Outputs
LOCKED, CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5,
CLKFBOUT,
// Inputs
CLKIN1, RST, PWRDWN, CLKFBIN
);
parameter BANDWIDTH = 0;
parameter CLKFBOUT_MULT = 0;
parameter CLKFBOUT_PHASE = 0;
parameter CLKIN1_PERIOD = 0;
parameter CLKOUT0_DIVIDE = 0;
parameter CLKOUT0_DUTY_CYCLE = 0;
parameter CLKOUT0_PHASE = 0;
parameter CLKOUT1_DIVIDE = 0;
parameter CLKOUT1_DUTY_CYCLE = 0;
parameter CLKOUT1_PHASE = 0;
parameter CLKOUT2_DIVIDE = 0;
parameter CLKOUT2_DUTY_CYCLE = 0;
parameter CLKOUT2_PHASE = 0;
parameter CLKOUT3_DIVIDE = 0;
parameter CLKOUT3_DUTY_CYCLE = 0;
parameter CLKOUT3_PHASE = 0;
parameter CLKOUT4_DIVIDE = 0;
parameter CLKOUT4_DUTY_CYCLE = 0;
parameter CLKOUT4_PHASE = 0;
parameter CLKOUT5_DIVIDE = 0;
parameter CLKOUT5_DUTY_CYCLE = 0;
parameter CLKOUT5_PHASE = 0;
parameter DIVCLK_DIVIDE = 0;
parameter REF_JITTER1 = 0;
parameter STARTUP_WAIT = 0;
parameter IOSTANDARD = 0;
//inputs
input CLKIN1;
input RST;
input PWRDWN;
input CLKFBIN;
//outputs
output LOCKED;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output CLKFBOUT;
//Not a correct model
assign CLKFBOUT=CLKIN1;
assign LOCKED=1'b0;
assign CLKOUT0=CLKIN1;
assign CLKOUT1=CLKIN1;
assign CLKOUT2=CLKIN1;
assign CLKOUT3=CLKIN1;
assign CLKOUT4=CLKIN1;
assign CLKOUT5=CLKIN1;
assign CLKFBOUT=CLKIN1;
endmodule // PLLE2_BASE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:33:35 12/02/2013
// Design Name:
// Module Name: tetris
// Project Name: EE201 Final Project
// Target Devices: Diligent Spartan-6
// Tool versions:
// Description:
//
// Dependencies: Food
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// COLLISION: The implementation of the full row clearing may cause problems in the top row.
//
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 100 ps
module tetris( Reset, Clk, Start, Ack, Left, Right, Down, Rotate,
q_I, q_Gen, q_Rot, q_Col, q_Lose, blocks, score, orientation, location, next_block
);
input Reset, Clk;
input Start, Ack;
input Left, Right, Down;
input Rotate;
output q_I, q_Gen;
output q_Rot, q_Col, q_Lose;
output reg [159:0] blocks;
output reg [7:0] score;
reg [7:0] state;
// Current Block Information
output reg [7:0] location;
integer i;
reg [2:0] block_type;
output reg [1:0] orientation;
output reg [2:0] next_block;
// Number of Loops for Rotate and Move
reg [24:0] loop;
reg [2:0] random_count;
wire [19:0] full_rows;
//assign full_rows[0] = blocks[0] && blocks[1] && blocks[2] && blocks[3] && blocks[4] && blocks[5] && blocks[6] && blocks[7] && blocks[8];
// for(integer i = 0; i<20; i=i+1)
// begin
// assign full_rows[i] = blocks[0 + 8*i] && blocks[1+ 8*i] && blocks[2+ 8*i] && blocks[3+ 8*i] && blocks[4+ 8*i] && blocks[5+ 8*i] && blocks[6+ 8*i] && blocks[7+ 8*i] && blocks[8+ 8*i];
// end
// Check if space is avaliable for a rotate or move down Wire
// Square
wire square_l, square_r, square_d;
assign square_l = !blocks[location-2] && !blocks[location -10] && ((location-1)%8);
assign square_r = !blocks[location+1] && !blocks[location-7] && ((location+1)%8);
assign square_d = !blocks[location-16] && !blocks[location-17] && (location > 15) ;
//Bar
wire bar0_l, bar0_r, bar0_d, bar0_rot, bar1_l, bar1_r, bar1_d, bar1_rot; // Two orientations
assign bar0_l = !blocks[location-3] && ((location-2)%8);
assign bar0_r = !blocks[location+2] && ((location+2)%8);
assign bar0_d = !blocks[location-7] && !blocks[location-8] && !blocks[location-9] && !blocks[location-10] && location > 7;
assign bar0_rot = (location/8 != 19) && !blocks[location+8] && !blocks[location-8] && !blocks[location-16] && (location >15);
assign bar1_l = !blocks[location-1] && !blocks[location-9] && !blocks[location-17] && !blocks[location+7] && location%8;
assign bar1_r = !blocks[location+1] && !blocks[location+9] && !blocks[location-7] && !blocks[location -15] && (location+1)%8;
assign bar1_d = !blocks[location-24] && (location > 23);
assign bar1_rot = !blocks[location +1] && !blocks[location-1] && !blocks[location-2] && (location+1)%8 && location%8;
wire s0_l, s0_r, s0_d, s0_rot;
assign s0_l = !blocks[location-1] && !blocks[location-10] && ((location-1)%8);
assign s0_r = !blocks[location-2] && !blocks[location-7] && ((location+2)%8);
assign s0_d = !blocks[location-7] && !blocks[location-16] && !blocks[location-17] && (location>16);
assign s0_rot = (location/8 != 19) && !blocks[location+8] && !blocks[location-7];
wire s1_l, s1_r, s1_d, s1_rot;
assign s1_l = !blocks[location-1] && !blocks[location+7] && !blocks[location-8] && ((location)%8);
assign s1_r = !blocks[location+9] && !blocks[location+2] && !blocks[location-6] && ((location+2)%8);
assign s1_d = !blocks[location-15] && !blocks[location-8] && (location>16);
assign s1_rot = !blocks[location-8] && !blocks[location-9];
wire z0_l, z0_r, z0_d, z0_rot;
assign z0_l = !blocks[location-9] && !blocks[location-2] && ((location-1)%8);
assign z0_r = !blocks[location+1] && !blocks[location-6] && ((location+2)%8);
assign z0_d = !blocks[location-9] && !blocks[location-16] && !blocks[location-15] && (location>16);
assign z0_rot = (location/8 != 19) && !blocks[location+1] && !blocks[location+9];
wire z1_l, z1_r, z1_d, z1_rot;
assign z1_l = !blocks[location-1] && !blocks[location+8] && !blocks[location-9] && ((location)%8);
assign z1_r = !blocks[location+10] && !blocks[location+2] && !blocks[location-7] && ((location+2)%8);
assign z1_d = !blocks[location-16] && !blocks[location-7] && (location>16);
assign z1_rot = !blocks[location-1] && !blocks[location-7];
//for Row clear condition
wire above_row, location_row, below_row, double_below_row;
assign above_row = blocks[(location/8 +1)*8] && blocks[(location/8+1)*8 + 1]
&& blocks[(location/8+1)*8 + 2]&& blocks[(location/8+1)*8 + 3]
&& blocks[(location/8+1)*8 + 4]&& blocks[(location/8+1)*8 + 5]
&& blocks[(location/8+1)*8 + 6]&& blocks[(location/8+1)*8 + 7];
assign location_row = blocks[(location/8)*8] && blocks[(location/8)*8 + 1]
&& blocks[(location/8)*8 + 2]&& blocks[(location/8)*8 + 3]
&& blocks[(location/8)*8 + 4]&& blocks[(location/8)*8 + 5]
&& blocks[(location/8)*8 + 6]&& blocks[(location/8)*8 + 7];
assign below_row = blocks[(location/8-1)*8] && blocks[(location/8-1)*8 + 1]
&& blocks[(location/8-1)*8 + 2]&& blocks[(location/8-1)*8 + 3]
&& blocks[(location/8-1)*8 + 4]&& blocks[(location/8-1)*8 + 5]
&& blocks[(location/8-1)*8 + 6]&& blocks[(location/8-1)*8 + 7];
assign double_below_row = blocks[(location/8-2)*8] && blocks[(location/8-2)*8 + 1]
&& blocks[(location/8-2)*8 + 2]&& blocks[(location/8-2)*8 + 3]
&& blocks[(location/8-2)*8 + 4]&& blocks[(location/8-2)*8 + 5]
&& blocks[(location/8-2)*8 + 6]&& blocks[(location/8-2)*8 + 7];
assign { q_Lose, q_Col, q_Rot, q_Gen, q_I} = state[4:0] ;
localparam
INITIAL = 8'b0000_0001,
GENERATE_PIECE = 8'b0000_0010,
ROTATE_PIECE = 8'b0000_0100,
COLLISION = 8'b0000_1000,
LOSE = 8'b0001_0000,
CLEAR_ROW = 8'b0010_0000,
UNKNOWN = 8'bxxxx_xxxx;
//temp
localparam
empty_row = 8'b0000_0000,
full_row = 8'b1111_1111,
loop_max = 25'd1, //25'b11111_11111_11111_11111_11111, //25'd1,
bottom = 8'b1110_1101;
//pieces
localparam
SQUARE = 3'b000,
BAR = 3'b001,
S = 3'b010,
Z = 3'b011,
L = 3'b100,
J = 3'b101,
T = 3'b110;
initial begin
random_count = $random;
end
always @ (posedge Clk )
begin: RANDOM_NUMBER_GENERATOR
if(random_count >= 0'b110)
random_count <= 0;
else
random_count <= random_count+ 1'b1;
end
always @ (posedge Clk, posedge Reset)
begin
if(Reset)
begin
state <= INITIAL;
loop <= 25'd0;
for(i=0; i<160; i = i+1)
begin
blocks[i] <= 0;
end
score <= 0;
location <= 0;
end
else
begin
(* full_case, parallel_case *)
case(state)
INITIAL :
begin
if(Start)
state <= GENERATE_PIECE;
else
state <= INITIAL;
loop <= 25'd0;
for(i=0; i<160; i = i+1)
begin
blocks[i] <= 0;
end
score <= 0;
location <= 0;
block_type <= random_count %2;
next_block <= random_count %2;
orientation <= 2'b00;
end
GENERATE_PIECE :
begin
(* full_case, parallel_case *)
case(next_block)
SQUARE :
begin
if(blocks[154] || blocks[153] || blocks[146] || blocks[145] )
state <= LOSE;
else
state <= ROTATE_PIECE;
end
BAR :
begin
if(blocks[152] || blocks[153] || blocks[154] || blocks[155])
state <= LOSE;
else
state <= ROTATE_PIECE;
end
S:
begin
if(blocks[154] || blocks[155] || blocks[146] || blocks[145] )
state <= LOSE;
else
state <= ROTATE_PIECE;
end
Z :
begin
if( blocks[154] || blocks[153] || blocks[146] || blocks[147] )
state <= LOSE;
else
state <= ROTATE_PIECE;
end
L:
begin
if( blocks[154] || blocks[155] || blocks[153] || blocks[145])
state <= LOSE;
else
state <= ROTATE_PIECE;
end
J :
begin
if( blocks[154] || blocks[153] || blocks[155] || blocks[147])
state <= LOSE;
else
state <= ROTATE_PIECE;
end
T :
begin
if(blocks[154] || blocks[153] || blocks[155] || blocks[146])
state <= LOSE;
else
state <= ROTATE_PIECE;
end
endcase
//State Actions
block_type <= next_block;
next_block <= random_count %2; //change for all blocks
orientation <= 2'b00;
location <= 8'd154;
loop <= 25'b0;
(* full_case, parallel_case *)
case( next_block)
SQUARE:
begin
blocks [154] <= 1;
blocks[153] <= 1;
blocks[146]<= 1;
blocks[145] <= 1;
end
BAR:
begin
blocks[152] <= 1;
blocks[153] <= 1;
blocks[154] <= 1;
blocks[155] <= 1;
end
S:
begin
blocks[154] <=
1;
blocks[155] <= 1;
blocks[146] <= 1;
blocks[145] <= 1;
end
Z:
begin
blocks[154] <= 1;
blocks[153] <= 1;
blocks[146] <= 1;
blocks[147] <= 1;
end
L:
begin
blocks[154] <= 1;
blocks[155] <= 1;
blocks[153] <= 1;
blocks[145] <= 1;
end
J:
begin
blocks[154] <= 1;
blocks[153] <= 1;
blocks[155] <= 1;
blocks[147] <= 1;
end
T:
begin
blocks[154] <= 1;
blocks[153] <= 1;
blocks[155] <= 1;
blocks[146] <= 1;
end
endcase
end
ROTATE_PIECE :
begin
if( loop < loop_max)
state <= ROTATE_PIECE;
else if(loop == loop_max)
state <= COLLISION;
loop<= loop+ 1'b1;
if(block_type == SQUARE)
begin
if(Left && square_l )
begin
blocks[location] <= 0;
blocks[location-8] <= 0;
blocks[location-10] <= 1;
blocks[location -2] <= 1;
location <= location - 1'b1;
end
else if( Right && square_r)
begin
blocks[location-1] <= 0;
blocks[location-9] <=0;
blocks[location +1] <= 1;
blocks[location - 7] <= 1;
location <= location + 1'b1;
end
else if( Down && square_d)
begin
blocks[location] <= 0;
blocks[location-1] <= 0;
blocks[location-16] <= 1;
blocks[location-17] <= 1;
location <= location - 4'd8;
loop<= 25'd0;
end
end
else if(block_type == BAR)
begin
if(Left && !orientation[0] && bar0_l)
begin
blocks[location +1] <= 0;
blocks[location -3] <= 1;
location <= location - 1'b1;
end
else if(Right && !orientation && bar0_r)
begin
blocks[location +2] <= 1;
blocks[location -2] <= 0;
location <= location+1'b1;
end
else if(Down && !orientation && bar0_d)
begin
blocks[location] <= 0;
blocks[location+1] <= 0;
blocks[location-1] <= 0;
blocks[location-2] <= 0;
blocks[location-7] <= 1;
blocks[location-8] <= 1;
blocks[location-9] <= 1;
blocks[location-10] <= 1;
location <= location -4'd8;
loop<= 25'd0;
end
else if(Rotate && !orientation && bar0_rot)
begin
blocks[location+8] <= 1;
blocks[location-8] <= 1;
blocks[location-16] <= 1;
blocks[location-2] <= 0;
blocks[location-1] <= 0;
blocks[location +1] <= 0;
orientation <= 2'b01;
end
else if(Left && orientation[0] && bar1_l)
begin
blocks[location +8] <= 0;
blocks[location] <= 0;
blocks[location -8] <= 0;
blocks[location -16] <= 0;
blocks[location +7] <= 1;
blocks[location-1] <= 1;
blocks[location -9] <= 1;
blocks[location -17] <= 1;
location <= location - 1'b1;
end
else if(Right && orientation[0] && bar1_r)
begin
blocks[location +8] <= 0;
blocks[location] <= 0;
blocks[location -8] <= 0;
blocks[location -16] <= 0;
blocks[location +9] <= 1;
blocks[location+1] <= 1;
blocks[location -7] <= 1;
blocks[location -15] <= 1;
location <= location +1'b1;
end
else if(Down && orientation[0] && bar1_d)
begin
blocks[location +8] <= 0;
blocks[location -24] <= 1;
location <= location -4'd8;
loop<= 25'd0;
end
else if(Rotate && orientation[0] && bar1_rot)
begin
blocks[location+8] <= 0;
blocks[location-8] <= 0;
blocks[location-16] <= 0;
blocks[location+1] <= 1;
blocks[location-1] <= 1;
blocks[location-2] <= 1;
orientation <= 2'b00;
end
end
else if( block_type == S)
begin
if(!orientation[0])
begin
end
else if(orientation[0])
begin
end
end
else if( block_type == Z)
begin
if(!orientation[0])
begin
end
else if(orientation[0])
begin
end
end
else if( block_type == L)
begin
if(!orientation[0])
begin
end
else if(orientation[0])
begin
end
else if(orientation == 2'b10)
begin
end
else if(orientation == 2'b11)
begin
end
end
else if( block_type == J)
begin
if(!orientation[0])
begin
end
else if(orientation[0])
begin
end
else if(orientation == 2'b10)
begin
end
else if(orientation == 2'b11)
begin
end
end
else if( block_type == T)
begin
if(!orientation[0])
begin
end
else if(orientation[0])
begin
end
else if(orientation == 2'b10)
begin
end
else if(orientation == 2'b11)
begin
end
end
end
COLLISION :
begin
if( (block_type == SQUARE && !square_d && (location_row + below_row) ==2 )
|| (block_type == BAR && !(orientation[0] ? bar1_d : bar0_d) &&
(orientation[0] ? (above_row + location_row + below_row + double_below_row) >1 : location_row)))
state <= CLEAR_ROW;
else if( (block_type == SQUARE && !square_d)
|| block_type == BAR && !(orientation[0] ? bar1_d : bar0_d))
state <= GENERATE_PIECE;
else
state <= ROTATE_PIECE;
// Start of RTL
if(block_type == SQUARE)
begin
if(square_d)
begin
blocks[location] <= 0;
blocks[location-1] <= 0;
blocks[location-16] <= 1;
blocks[location-17] <= 1;
location <= location - 4'd8;
loop<= 25'd0;
end
end
else if(block_type == BAR)
begin
if( !orientation[0])
begin
if(bar0_d)
begin
blocks[location] <= 0;
blocks[location+1] <= 0;
blocks[location-1] <= 0;
blocks[location-2] <= 0;
blocks[location-7] <= 1;
blocks[location-8] <= 1;
blocks[location-9] <= 1;
blocks[location-10] <= 1;
location <= location -4'd8;
loop <= 25'd0;
end
end
else if(orientation[0])
begin
if(bar1_d)
begin
blocks[location+8] <= 0;
blocks[location-24] <= 1;
location <= location - 4'd8;
loop <= 25'd0;
end
end
end // end of RTL
end // end of the Collision State
CLEAR_ROW:
begin
if( (block_type == SQUARE && !square_d && (location_row + below_row) ==2 )
|| (block_type == BAR && !(orientation[0] ? bar1_d : bar0_d) &&
(orientation[0] ? (above_row + location_row + below_row + double_below_row) >1 : location_row)))
state <= CLEAR_ROW;
else
state <= GENERATE_PIECE;
end
LOSE:
begin
if(Ack)
state<= INITIAL;
else
state<= LOSE;
end
default : state <= UNKNOWN;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlymetal6s6s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
module harness();
parameter CYCLE = 100,
Tsetup = 15,
Thold = 5;
// -- Señales de interconexion ----------------------------------- >>>>>
reg clk;
reg reset;
// -- input -------------------------------------------------- >>>>>
wire start_strobe_din;
wire [0:63] plaintext_din;
wire [0:63] key_din;
// -- output ------------------------------------------------- >>>>>
wire done_strobe_dout;
wire active_des_engine_dout;
wire [0:63] ciphertext_dout;
// -- DUT -------------------------------------------------------- >>>>>
des_core des_engine
(
.clk(clk),
.reset(reset),
// -- input -------------------------------------------------- >>>>>
.start_strobe_din (start_strobe_din),
.plaintext_din (plaintext_din),
.key_din (key_din),
// -- output ------------------------------------------------- >>>>>
.done_strobe_dout (done_strobe_dout),
.active_des_engine_dout (active_des_engine_dout),
.ciphertext_dout (ciphertext_dout)
);
// -- Bus Behaivoral Model --------------------------------------- >>>>>
source
#(
.Thold(Thold)
)
source
(
.clk(clk),
// -- input ------------------------------------------ >>>>>
.active_des_engine_din(active_des_engine_dout),
// -- output ----------------------------------------- >>>>>
.start_strobe_dout(start_strobe_din),
.plaintext_dout(plaintext_din),
.key_dout(key_din)
);
sink
#(
.Thold(Thold)
)
sink
(
.clk(clk),
// -- inputs ------------------------------------------------- >>>>>
.done_strobe_din(done_strobe_dout),
.ciphertext_din(ciphertext_dout)
);
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule // harness
|
module game_graph_simple
(
input wire clk, reset,
input wire video_on,
// control the bar
input wire [2:0] sw,
// control the gun
input wire [9:0] pix_x, pix_y,
output reg [2:0] graph_rgb
);
// constant and signal declaration
// x, y coordinates (0,0) to (639,479)
localparam MAX_X = 640;
localparam MAX_Y = 480;
wire refr_tick;
// refr_tick is the refreshment rate
//--------------------------------------------
// vertical stripe as a wall
//--------------------------------------------
// wall left, right boundary
localparam WALL_X_L = 20;
localparam WALL_X_R = 25;
// decrease it if you want more space
//--------------------------------------------
// Let us define the gunner
// just think about the death gun from Sword Art Online
//--------------------------------------------
localparam GUN_X_L = 50;
localparam GUN_X_R = 53;
wire [9:0] gun_y_t;
wire [9:0] gun_y_b;
// register to track the gun
reg [9:0] gun_y_reg;
reg [9:0] gun_y_next;
// gun should move slower than bar
localparam GUN_V = 2;
localparam GUN_Y_SIZE = 62;
//--------------------------------------------
// Now bullet (without silver, pity)
//--------------------------------------------
localparam BULLET_SIZE = 9;
localparam BULLET_V = 5;
// should be able to run in all directions
// however, one direction is locked with the gun (emitter)
wire [9:0] bullet_x_l, bullet_x_r;
wire [9:0] bullet_y_t, bullet_y_b;
// speed shall be registered
reg [9:0] bullet_x_reg;
reg [9:0] bullet_y_reg;
reg [9:0] bullet_x_next;
reg [9:0] bullet_y_next;
//--------------------------------------------
// right vertical bar
//--------------------------------------------
// bar left, right boundary
localparam BAR_X_L = 600;
localparam BAR_X_R = 603;
// bar top, bottom boundary
wire [9:0] bar_y_t, bar_y_b;
localparam BAR_Y_SIZE = 72;
// register to track top boundary (x position is fixed)
reg [9:0] bar_y_reg, bar_y_next;
// bar moving velocity when a button is pressed
localparam BAR_V = 4;
//--------------------------------------------
// square ball (this part can be deleted, test purpose only)
//--------------------------------------------
localparam BALL_SIZE = 8;
// ball left, right boundary
wire [9:0] ball_x_l, ball_x_r;
// ball top, bottom boundary
wire [9:0] ball_y_t, ball_y_b;
// reg to track left, top position
reg [9:0] ball_x_reg, ball_y_reg;
wire [9:0] ball_x_next, ball_y_next;
// reg to track ball speed
reg [9:0] x_delta_reg, x_delta_next;
reg [9:0] y_delta_reg, y_delta_next;
// ball velocity can be pos or neg)
localparam BALL_V_P = 2;
localparam BALL_V_N = -2;
//--------------------------------------------
// round ball (we use this ball actually)
//--------------------------------------------
wire [2:0] rom_addr, rom_col;
reg [7:0] rom_data;
wire rom_bit;
//--------------------------------------------
// object output signals
//--------------------------------------------
wire wall_on, bar_on, gun_on, bullet_on, sq_ball_on, rd_ball_on;
wire [2:0] wall_rgb, gun_rgb, bullet_rgb, bar_rgb, ball_rgb;
// body
//--------------------------------------------
// round ball image ROM
//--------------------------------------------
always @*
case (rom_addr)
// right side is the shape of the ball (at least we think it shall be)
3'h0: rom_data = 8'b00111100; // ****
3'h1: rom_data = 8'b01111110; // ******
3'h2: rom_data = 8'b11111111; // ********
3'h3: rom_data = 8'b11111111; // ********
3'h4: rom_data = 8'b11111111; // ********
3'h5: rom_data = 8'b11111111; // ********
3'h6: rom_data = 8'b01111110; // ******
3'h7: rom_data = 8'b00111100; // ****
endcase
// registers
always @(posedge clk, posedge reset)
if (reset)
begin
bar_y_reg <= 0;
// well, this line is added for visual effect
gun_y_reg <= 0;
// and so is that line
ball_x_reg <= 0;
ball_y_reg <= 0;
bullet_x_reg <= GUN_X_R;
bullet_y_reg <= 0+GUN_Y_SIZE/2;
// 0 should actually be gun_y_reg
// (which shall be zero after resetting op)
// different from the ball
// since at the beginning of the game, bullet should lie
// still on the gun (or gunner)
x_delta_reg <= 10'h004;
y_delta_reg <= 10'h004;
end
else
begin
bar_y_reg <= bar_y_next;
// updating with reg (one time pad loss, same with sync)
gun_y_reg <= gun_y_next;
ball_x_reg <= ball_x_next;
ball_y_reg <= ball_y_next;
x_delta_reg <= x_delta_next;
y_delta_reg <= y_delta_next;
bullet_x_reg <= bullet_x_next; // changed from y to x
bullet_y_reg <= bullet_y_next;
// a little easy than the ball
end
// refr_tick: 1-clock tick asserted at start of v-sync
assign refr_tick = (pix_y==481) && (pix_x==0);
//--------------------------------------------
// (wall) left vertical strip
//--------------------------------------------
// pixel within wall
assign wall_on = (WALL_X_L<=pix_x) && (pix_x<=WALL_X_R);
// wall rgb output
assign wall_rgb = 3'b001; // blue
//--------------------------------------------
// right vertical bar
//--------------------------------------------
// boundary
assign bar_y_t = bar_y_reg;
assign bar_y_b = bar_y_t + BAR_Y_SIZE - 1;
// pixel within bar
assign bar_on = (BAR_X_L<=pix_x) && (pix_x<=BAR_X_R) &&
(bar_y_t<=pix_y) && (pix_y<=bar_y_b);
// bar rgb output
assign bar_rgb = 3'b010; // green
// new bar y-position
always @*
begin
bar_y_next = bar_y_reg; // no move
if (refr_tick)
if (~sw[2] & (bar_y_b < (MAX_Y-1-BAR_V)))
bar_y_next = bar_y_reg + BAR_V; // move down
else if (sw[2] & (bar_y_t > BAR_V))
bar_y_next = bar_y_reg - BAR_V; // move up
end
//--------------------------------------------
// gun (well ... interesting)
//--------------------------------------------
// gun in the left
assign gun_y_t = gun_y_reg;
assign gun_y_b = gun_y_t + GUN_Y_SIZE -1;
// pixels within gun
assign gun_on = (GUN_X_L<=pix_x) && (pix_x<=GUN_X_R) && (gun_y_t<=pix_y) && (pix_y<=gun_y_b);
// gun_y_t should change timely based.
assign gun_rgb = 3'b000;
// changed from white to black
// black gun, the name was taken after the famous boss in the SWORT ART ONLINE
always @*
begin
gun_y_next = gun_y_reg;
if (refr_tick)
if (sw[0] & (gun_y_b < (MAX_Y-1-GUN_V)))
gun_y_next = gun_y_reg + GUN_V; // move up (minor changed)
else if ( (~sw[0]) & (gun_y_t > GUN_V) )
gun_y_next = gun_y_reg - GUN_V; // move down
end
// gun is controlled by switch
//--------------------------------------------
// you can not use a gun without bullet
//--------------------------------------------
// Let us define the bullet
assign bullet_x_l = bullet_x_reg;
assign bullet_x_r = bullet_x_l + BULLET_SIZE -1;
assign bullet_y_t = bullet_y_reg;
// the word size b is a little larger I assume
// right?
assign bullet_y_b = bullet_y_t + BULLET_SIZE -1;
// pixel within bullet
assign bullet_on =
(bullet_x_l<=pix_x) && (pix_x<=bullet_x_r) &&
(bullet_y_t<=pix_y) && (pix_y<=bullet_y_b);
// Now pixels within the bullet are defined with color
assign bullet_rgb = 3'b000; //black bullet
// Well, silver bullet is prefered, but I don't know how to represent it with rgb values.
// the board should be blamed, not me (laugh)
always @*
begin
bullet_x_next = bullet_x_reg;
bullet_y_next = bullet_y_reg;
if (refr_tick)
if ((BAR_X_L<=bullet_x_r) && (bullet_x_r<=BAR_X_R) &&
(bar_y_t<=bullet_y_b) && (bullet_y_t<=bar_y_b))
// now you hit it
begin
bullet_x_next = GUN_X_R;
// bullet_x_next is the left side of the bullet (should be held at the right side of the gun)
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
// emission of bullet is controlled by sw not button
// actually, this should be done with a de-bounced switch (written by cpp)
else if ( sw[1] || (bullet_x_l >= GUN_X_R+5) )
bullet_x_next = bullet_x_reg + BULLET_V;
// y doesn't change, fly along the trajectory (not very physical I assume)
else if ( (bullet_x_reg<=(GUN_X_L-1)) || (bullet_x_reg>=(MAX_X-BULLET_SIZE-1)) )
// correspond to initialization, over, less than
// to make it clearer, over the right boarder of the screen, or less than the left side of the gun
begin
bullet_x_next = GUN_X_R;
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
else
begin
bullet_x_next = GUN_X_R;
bullet_y_next = gun_y_reg+GUN_Y_SIZE/2;
end
end
// please don't delete it
// may be used in some test case
//--------------------------------------------
// ball
//--------------------------------------------
// boundary
assign ball_x_l = ball_x_reg;
assign ball_y_t = ball_y_reg;
assign ball_x_r = ball_x_l + BALL_SIZE - 1;
assign ball_y_b = ball_y_t + BALL_SIZE - 1;
// pixel within ball
assign sq_ball_on =
(ball_x_l<=pix_x) && (pix_x<=ball_x_r) &&
(ball_y_t<=pix_y) && (pix_y<=ball_y_b);
// map current pixel location to ROM addr/col
assign rom_addr = pix_y[2:0] - ball_y_t[2:0];
assign rom_col = pix_x[2:0] - ball_x_l[2:0];
assign rom_bit = rom_data[rom_col];
// pixel within ball
assign rd_ball_on = sq_ball_on & rom_bit;
// ball rgb output
assign ball_rgb = 3'b100; // red
// new ball position
assign ball_x_next = (refr_tick) ? ball_x_reg+x_delta_reg :
ball_x_reg ;
assign ball_y_next = (refr_tick) ? ball_y_reg+y_delta_reg :
ball_y_reg ;
// new ball velocity
always @*
begin
x_delta_next = x_delta_reg;
y_delta_next = y_delta_reg;
if (ball_y_t < 1) // reach top
y_delta_next = BALL_V_P;
else if (ball_y_b > (MAX_Y-1)) // reach bottom
y_delta_next = BALL_V_N;
else if (ball_x_l <= WALL_X_R) // reach wall
x_delta_next = BALL_V_P; // bounce back
else if ((BAR_X_L<=ball_x_r) && (ball_x_r<=BAR_X_R) &&
(bar_y_t<=ball_y_b) && (ball_y_t<=bar_y_b))
// reach x of right bar and hit, ball bounce back
x_delta_next = BALL_V_N;
end
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @*
if (~video_on)
graph_rgb = 3'b000; // blank
else
if (wall_on)
graph_rgb = wall_rgb;
else if (bullet_on)
graph_rgb = bullet_rgb;
// bullet is higher that bar (since it can get through it)
else if (bar_on)
graph_rgb = bar_rgb;
else if (gun_on)
graph_rgb = gun_rgb;
else if (rd_ball_on)
// this stands for the round ball (well...)
// you could also use the sqaure ball which is not yet deleted for the test purpose only
graph_rgb = ball_rgb;
else
graph_rgb = 3'b110; // yellow background
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_rd_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface read buffer. Re orders read data returned from the
// memory controller back to the request order.
//
// Consists of a large buffer for the data, a status RAM and two counters.
//
// The large buffer is implemented with distributed RAM in 6 bit wide,
// 1 read, 1 write mode. The status RAM is implemented with a distributed
// RAM configured as 2 bits wide 1 read/write, 1 read mode.
//
// As read requests are received from the application, the data_buf_addr
// counter supplies the data_buf_addr sent into the memory controller.
// With each read request, the counter is incremented, eventually rolling
// over. This mechanism labels each read request with an incrementing number.
//
// When the memory controller returns read data, it echos the original
// data_buf_addr with the read data.
//
// The status RAM is indexed with the same address as the data buffer
// RAM. Each word of the data buffer RAM has an associated status bit
// and "end" bit. Requests of size 1 return a data burst on two consecutive
// states. Requests of size zero return with a single assertion of rd_data_en.
//
// Upon returning data, the status and end bits are updated for each
// corresponding location in the status RAM indexed by the data_buf_addr
// echoed on the rd_data_addr field.
//
// The other side of the status and data RAMs is indexed by the rd_buf_indx.
// The rd_buf_indx constantly monitors the status bit it is currently
// pointing to. When the status becomes set to the proper state (more on
// this later) read data is returned to the application, and the rd_buf_indx
// is incremented.
//
// At rst the rd_buf_indx is initialized to zero. Data will not have been
// returned from the memory controller yet, so there is nothing to return
// to the application. Evenutally, read requests will be made, and the
// memory controller will return the corresponding data. The memory
// controller may not return this data in the request order. In which
// case, the status bit at location zero, will not indicate
// the data for request zero is ready. Eventually, the memory controller
// will return data for request zero. The data is forwarded on to the
// application, and rd_buf_indx is incremented to point to the next status
// bits and data in the buffers. The status bit will be examined, and if
// data is valid, this data will be returned as well. This process
// continues until the status bit indexed by rd_buf_indx indicates data
// is not ready. This may be because the rd_data_buf
// is empty, or that some data was returned out of order. Since rd_buf_indx
// always increments sequentially, data is always returned to the application
// in request order.
//
// Some further discussion of the status bit is in order. The rd_data_buf
// is a circular buffer. The status bit is a single bit. Distributed RAM
// supports only a single write port. The write port is consumed by
// memory controller read data updates. If a simple '1' were used to
// indicate the status, when rd_data_indx rolled over it would immediately
// encounter a one for a request that may not be ready.
//
// This problem is solved by causing read data returns to flip the
// status bit, and adding hi order bit beyond the size required to
// index the rd_data_buf. Data is considered ready when the status bit
// and this hi order bit are equal.
//
// The status RAM needs to be initialized to zero after reset. This is
// accomplished by cycling through all rd_buf_indx valus and writing a
// zero to the status bits directly following deassertion of reset. This
// mechanism is used for similar purposes
// for the wr_data_buf.
//
// When ORDERING == "STRICT", read data reordering is unnecessary. For thi
// case, most of the logic in the block is not generated.
`timescale 1 ps / 1 ps
// User interface read data.
module mig_7series_v2_0_ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,
// Inputs
rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,
rd_data, ecc_multiple, rd_accepted
);
input rst;
input clk;
output wire ram_init_done_r;
output wire [3:0] ram_init_addr;
// rd_buf_indx points to the status and data storage rams for
// reading data out to the app.
reg [5:0] rd_buf_indx_r;
reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */;
assign ram_init_done_r = ram_init_done_r_lcl;
wire app_rd_data_valid_ns;
wire single_data;
reg [5:0] rd_buf_indx_ns;
generate begin : rd_buf_indx
wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;
// Loop through all status write addresses once after rst. Initializes
// the status and pointer RAMs.
wire ram_init_done_ns =
~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));
always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;
always @(/*AS*/rd_buf_indx_r or rst or single_data
or upd_rd_buf_indx) begin
rd_buf_indx_ns = rd_buf_indx_r;
if (rst) rd_buf_indx_ns = 6'b0;
else if (upd_rd_buf_indx) rd_buf_indx_ns =
// need to use every slot of RAMB32 if all address bits are used
rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data);
end
always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;
end
endgenerate
assign ram_init_addr = rd_buf_indx_r[3:0];
input rd_data_en;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input rd_data_offset;
input rd_data_end;
input [APP_DATA_WIDTH-1:0] rd_data;
output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */;
output reg app_rd_data_end;
output reg [APP_DATA_WIDTH-1:0] app_rd_data;
input [3:0] ecc_multiple;
reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;
output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;
assign app_ecc_multiple_err = app_ecc_multiple_err_r;
input rd_accepted;
output wire rd_buf_full;
output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
// Compute dimensions of read data buffer. Depending on width of
// DQ bus and DRAM CK
// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
// single write, single read, 6 bit wide mode.
localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);
localparam REMAINDER = RD_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
if (ORDERING == "STRICT") begin : strict_mode
assign app_rd_data_valid_ns = 1'b0;
assign single_data = 1'b0;
assign rd_buf_full = 1'b0;
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns =
rst
? 0
: rd_data_buf_addr_r_lcl + rd_accepted;
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
assign rd_data_buf_addr_r = rd_data_buf_addr_ns;
// app_* signals required to be registered.
if (ECC == "OFF") begin : ecc_off
always @(/*AS*/rd_data) app_rd_data = rd_data;
always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;
always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;
end
else begin : ecc_on
always @(posedge clk) app_rd_data <= #TCQ rd_data;
always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;
always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;
always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;
end
end
else begin : not_strict_mode
wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */;
// In configurations where read data is returned in a single fabric cycle
// the offset is always zero and we can use the bit to get a deeper
// FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH
// is set to use them all, discard the offset. Otherwise, include the
// offset.
wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ?
rd_data_addr :
{rd_data_addr, rd_data_offset};
wire [1:0] rd_status;
// Instantiate status RAM. One bit for status and one for "end".
begin : status_ram
// Turns out read to write back status is a timing path. Update
// the status in the ram on the state following the read. Bypass
// the write data into the status read path.
wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl
? rd_buf_wr_addr
: rd_buf_indx_r[4:0];
reg [4:0] status_ram_wr_addr_r;
always @(posedge clk) status_ram_wr_addr_r <=
#TCQ status_ram_wr_addr_ns;
wire [1:0] wr_status;
// Not guaranteed to write second status bit. If it is written, always
// copy in the first status bit.
reg wr_status_r1;
always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];
wire [1:0] status_ram_wr_data_ns =
ram_init_done_r_lcl
? {rd_data_end, ~(rd_data_offset
? wr_status_r1
: wr_status[0])}
: 2'b0;
reg [1:0] status_ram_wr_data_r;
always @(posedge clk) status_ram_wr_data_r <=
#TCQ status_ram_wr_data_ns;
reg rd_buf_we_r1;
always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_status),
.DOB(),
.DOC(wr_status),
.DOD(),
.DIA(status_ram_wr_data_r),
.DIB(2'b0),
.DIC(status_ram_wr_data_r),
.DID(status_ram_wr_data_r),
.ADDRA(rd_buf_indx_r[4:0]),
.ADDRB(5'b0),
.ADDRC(status_ram_wr_addr_ns),
.ADDRD(status_ram_wr_addr_r),
.WE(rd_buf_we_r1),
.WCLK(clk)
);
end // block: status_ram
wire [RAM_WIDTH-1:0] rd_buf_out_data;
begin : rd_buf
wire [RAM_WIDTH-1:0] rd_buf_in_data;
if (REMAINDER == 0)
if (ECC == "OFF")
assign rd_buf_in_data = rd_data;
else
assign rd_buf_in_data = {ecc_multiple, rd_data};
else
if (ECC == "OFF")
assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};
else
assign rd_buf_in_data =
{{6-REMAINDER{1'b0}}, ecc_multiple, rd_data};
// Dedicated copy for driving distributed RAM.
(* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */;
always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_buf_out_data[((i*6)+4)+:2]),
.DOB(rd_buf_out_data[((i*6)+2)+:2]),
.DOC(rd_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(rd_buf_in_data[((i*6)+4)+:2]),
.DIB(rd_buf_in_data[((i*6)+2)+:2]),
.DIC(rd_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_buf_indx_copy_r[4:0]),
.ADDRB(rd_buf_indx_copy_r[4:0]),
.ADDRC(rd_buf_indx_copy_r[4:0]),
.ADDRD(rd_buf_wr_addr),
.WE(rd_buf_we),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]);
wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */;
assign app_rd_data_valid_ns =
ram_init_done_r_lcl && (bypass || rd_data_rdy);
wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1];
always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns;
always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns;
assign single_data =
app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0];
wire [APP_DATA_WIDTH-1:0] app_rd_data_ns =
bypass
? rd_data
: rd_buf_out_data[APP_DATA_WIDTH-1:0];
always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns;
if (ECC != "OFF") begin : assign_app_ecc_multiple
wire [3:0] app_ecc_multiple_err_ns =
bypass
? ecc_multiple
: rd_buf_out_data[APP_DATA_WIDTH+:4];
always @(posedge clk) app_ecc_multiple_err_r <=
#TCQ app_ecc_multiple_err_ns;
end
//Added to fix timing. The signal app_rd_data_valid has
//a very high fanout. So making a dedicated copy for usage
//with the occ_cnt counter.
(* equivalent_register_removal = "no" *)
reg app_rd_data_valid_copy;
always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns;
// Keep track of how many entries in the queue hold data.
wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version
//of the signals in ordered to fix timing
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r;
wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1;
wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1;
begin : occupied_counter
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns;
always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin
occ_cnt_ns = occ_cnt_r;
if (rst) occ_cnt_ns = 0;
else case ({rd_accepted, free_rd_buf})
2'b01 : occ_cnt_ns = occ_minus_one;
2'b10 : occ_cnt_ns = occ_plus_one;
endcase // case ({wr_data_end, new_rd_data})
end
always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH];
`ifdef MC_SVA
rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full));
rd_data_buffer_inc_dec_15: cover property (@(posedge clk)
(~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf)));
rd_data_underflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f))));
rd_data_overflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11))));
`endif
end // block: occupied_counter
// Generate the data_buf_address written into the memory controller
// for reads. Increment with each accepted read, and rollover at 0xf.
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl;
begin : data_buf_addr
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns;
always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin
rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl;
if (rst) rd_data_buf_addr_ns = 0;
else if (rd_accepted) rd_data_buf_addr_ns =
rd_data_buf_addr_r_lcl + 1;
end
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
end // block: data_buf_addr
end // block: not_strict_mode
endgenerate
endmodule // ui_rd_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.06.2015 14:58:39
// Design Name:
// Module Name: harness
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////
`include "system.vh"
module harness();
parameter CYCLE = 100,
Tsetup = 15,
Thold = 5;
// -- Señales de interconexion ----------------------------------- >>>>>
reg clk;
reg reset;
// -- input port --------------------------------------------- >>>>>
wire credit_out_dout;
wire [`CHANNEL_WIDTH-1:0] input_channel_din;
// -- output port -------------------------------------------- >>>>>
wire credit_in_din;
wire [`CHANNEL_WIDTH-1:0] output_channel_dout;
// -- interfaz :: processing node ---------------------------- >>>>>
wire start_strobe;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordA;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordB;
wire done_strobe;
wire active_test_engine;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordC;
wire [(2 * `CHANNEL_WIDTH)-1:0] wordD;
// -- DUT -------------------------------------------------------- >>>>>
test_engine_network_interface DUT
(
.clk (clk),
.reset (reset),
// -- input port ----------------------------------------- >>>>>
.credit_out_dout (credit_out_dout),
.input_channel_din (input_channel_din),
// -- output port ---------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout),
// -- interfaz :: processing node ------------------------ >>>>>
.start_strobe_dout (start_strobe),
.wordA_dout (wordA),
.wordB_dout (wordB),
.done_strobe_din (done_strobe),
.active_test_engine_din (active_test_engine),
.wordC_din (wordC),
.wordD_din (wordD)
);
// -- PE dummy --------------------------------------------------- >>>>>
test_engine_dummy
#(
.Thold(Thold)
)
test_engine_dummy
(
.clk(clk),
// -- inputs --------------------------------------------- >>>>>
.start_strobe_din(start_strobe),
.wordA_din(wordA),
.wordB_din(wordB),
// -- outputs -------------------------------------------- >>>>>
.done_strobe_dout(done_strobe),
.active_test_engine_dout(active_test_engine),
.wordC_dout(wordC),
.wordD_dout(wordD)
);
// -- Canal IO ----------------------------------------------- >>>>>
source
#(
.Thold(Thold),
.CREDITS(1)
)
input_channel
(
.clk (clk),
.credit_in (credit_out_dout),
.channel_out(input_channel_din)
);
sink
#(
.Thold(Thold)
)
output_channel
(
.clk (clk),
.channel_in (output_channel_dout),
.credit_out (credit_in_din)
);
// -- Clock Generator -------------------------------------------- >>>>>
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
// -- Sync Reset Generator --------------------------------------- >>>>>
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule // harness
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the pipe
module pipeline_buffer (in,out,clock,reset);
// Output signal for the design module
output out; // Output data signal
// Input signals for the design module
input in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg out;
reg o1; // Output of flip-flop #1
reg o2; // Output of flip-flop #2
reg o3; // Output of flip-flop #3
reg o4; // Output of flip-flop #4
reg o5; // Output of flip-flop #5
reg o6; // Output of flip-flop #6
reg o7; // Output of flip-flop #7
reg o8; // Output of flip-flop #8
reg o9; // Output of flip-flop #9
reg o10; // Output of flip-flop #10
reg o11; // Output of flip-flop #11
reg o12; // Output of flip-flop #12
reg o13; // Output of flip-flop #13
reg o14; // Output of flip-flop #14
reg o15; // Output of flip-flop #15
reg o16; // Output of flip-flop #16
reg o17; // Output of flip-flop #17
reg o18; // Output of flip-flop #18
reg o19; // Output of flip-flop #19
reg o20; // Output of flip-flop #20
reg o21; // Output of flip-flop #21
reg o22; // Output of flip-flop #22
reg o23; // Output of flip-flop #23
reg o24; // Output of flip-flop #24
reg o25; // Output of flip-flop #25
reg o26; // Output of flip-flop #26
reg o27; // Output of flip-flop #27
reg o28; // Output of flip-flop #28
reg o29; // Output of flip-flop #29
reg o30; // Output of flip-flop #30
reg o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 1'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 1'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 1'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 1'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 1'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 1'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 1'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 1'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 1'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 1'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 1'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 1'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 1'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 1'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 1'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 1'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 1'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 1'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 1'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 1'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 1'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 1'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 1'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 1'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 1'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 1'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 1'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 1'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 1'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 1'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 1'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 1'd0;
else
out = o31;
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_padder;
// Inputs
reg clk;
reg reset;
reg [31:0] in;
reg in_ready;
reg is_last;
reg [1:0] byte_num;
reg f_ack;
// Outputs
wire buffer_full;
wire [575:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
padder uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready),
.f_ack(f_ack)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
f_ack = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// pad an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
if (buffer_full !== 0) error;
in_ready = 1;
is_last = 1;
#(`P);
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check({8'h1, 560'h0, 8'h80});
f_ack = 1; #(`P); f_ack = 0;
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should be 0
end
// pad an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1; is_last = 0;
byte_num = 3; /* should have no effect */
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; is_last = 1; #(`P);
in_ready = 0;
is_last = 0;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890ABCD81 });
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1; is_last = 0;
byte_num = 1; /* should have no effect */
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
#(`P);
check({ {8{64'h1234567890ABCDEF}}, 64'h0100000000000080 });
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
if (out_ready !== 1) error;
check({9{64'h1234567890ABCDEF}});
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 64'h999; // should not eat this
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
f_ack = 1; #(`P); f_ack = 0;
if (out_ready !== 0) error;
// feed next (576-16) bit
for (i=0; i<8; i=i+1)
begin
in = 32'h12345678; #(`P);
in = 32'h90ABCDEF; #(`P);
end
in = 32'h12345678; #(`P);
byte_num = 2;
is_last = 1;
in = 32'h90ABCDEF; #(`P);
if (out_ready !== 1) error;
check({ {8{64'h1234567890ABCDEF}}, 64'h1234567890AB0180 });
is_last = 0;
// eat these bits
f_ack = 1; #(`P); f_ack = 0;
// should not provide any more bits, if user provides nothing
in_ready = 0;
is_last = 0;
for (i=0; i<10; i=i+1)
begin
if (out_ready === 1) error;
#(`P);
end
in_ready = 0;
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [575:0] wish;
begin
if (out !== wish)
begin
$display("out:%h wish:%h", out, wish);
error;
end
end
endtask
endmodule
`undef P
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : forward_unit.v
// KEYWORDS : dlx, forwarding, hazzard
// -----------------------------------------------------------------------------
// PURPOSE : Provide forwarding functionality to uDLX core
// -----------------------------------------------------------------------------
module forward_unit
#(
parameter DATA_WIDTH = 32,
parameter REG_ADDR_WIDTH = 5
)
(
input [DATA_WIDTH-1:0] data_alu_a_in,
input [DATA_WIDTH-1:0] data_alu_b_in,
input [REG_ADDR_WIDTH-1:0] addr_alu_a_in,
input [REG_ADDR_WIDTH-1:0] addr_alu_b_in,
input [DATA_WIDTH-1:0] ex_mem_reg_a_data_in,
input [DATA_WIDTH-1:0] ex_mem_reg_b_data_in,
input [REG_ADDR_WIDTH-1:0] ex_mem_reg_a_addr_in,
input [REG_ADDR_WIDTH-1:0] ex_mem_reg_b_addr_in,
input ex_mem_reg_a_wr_ena_in,
input ex_mem_reg_b_wr_ena_in,
input [DATA_WIDTH-1:0] wb_reg_a_data_in,
input [DATA_WIDTH-1:0] wb_reg_b_data_in,
input [REG_ADDR_WIDTH-1:0] wb_reg_a_addr_in,
input [REG_ADDR_WIDTH-1:0] wb_reg_b_addr_in,
input wb_reg_a_wr_ena_in,
input wb_reg_b_wr_ena_in,
output reg [DATA_WIDTH-1:0] alu_a_mux_sel_out,
output reg [DATA_WIDTH-1:0] alu_b_mux_sel_out
);
// Port-A ALU input
always@(*)begin
// Forwarding data from MEM -> EXE
if((addr_alu_a_in == ex_mem_reg_a_addr_in) & ex_mem_reg_a_wr_ena_in)begin
alu_a_mux_sel_out <= ex_mem_reg_a_data_in;
end
else if((addr_alu_a_in == ex_mem_reg_b_addr_in) & ex_mem_reg_b_wr_ena_in)begin
alu_a_mux_sel_out <= ex_mem_reg_b_data_in;
end
// Forwarding data from WB -> EXE
else if((addr_alu_a_in == wb_reg_a_addr_in) & wb_reg_a_wr_ena_in)begin
alu_a_mux_sel_out <= wb_reg_a_data_in;
end
else if((addr_alu_a_in == wb_reg_b_addr_in) & wb_reg_b_wr_ena_in)begin
alu_a_mux_sel_out <= wb_reg_b_data_in;
end
// No forwarding
else begin
alu_a_mux_sel_out <= data_alu_a_in;
end
end
// Port-B ALU input
always@(*)begin
// Forwarding data from MEM -> EXE
if((addr_alu_b_in == ex_mem_reg_a_addr_in) & ex_mem_reg_a_wr_ena_in)begin
alu_b_mux_sel_out <= ex_mem_reg_a_data_in;
end
else if((addr_alu_b_in == ex_mem_reg_b_addr_in) & ex_mem_reg_b_wr_ena_in)begin
alu_b_mux_sel_out <= ex_mem_reg_b_data_in;
end
// Forwarding data from WB -> EXE
else if((addr_alu_b_in == wb_reg_a_addr_in) & wb_reg_a_wr_ena_in)begin
alu_b_mux_sel_out <= wb_reg_a_data_in;
end
else if((addr_alu_b_in == wb_reg_b_addr_in) & wb_reg_b_wr_ena_in)begin
alu_b_mux_sel_out <= wb_reg_b_data_in;
end
// No forwarding
else begin
alu_b_mux_sel_out <= data_alu_b_in;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311OI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__A311OI_PP_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311OI_PP_SYMBOL_V
|
(** * UseAuto: Theory and Practice of Automation in Coq Proofs *)
(* $Date: 2011-04-20 14:26:52 -0400 (Wed, 20 Apr 2011) $ *)
(* Chapter maintained by Arthur Chargueraud *)
(** In a machine-checked proof, every single detail has to be
justified. This can result in huge proof scripts. Fortunately,
Coq comes with a proof-search mechanism and decision procedures
that enable the system to automatically synthetizes simple pieces
of proof. Automation is very powerful when set up
appropriately. The purpose of this chapter is to explain the
basics of working of automation.
The chapter is organized in two parts. The first part focuses on a
general mechanism called "proof search." In short, proof search
consists in naively trying to apply lemmas and assumptions in all
possible ways until proving the goal. The second part describes
"decision procedures," which are tactics that are very good at
solving proof obligations that fall in some particular fragment of
the logic of Coq.
The examples from this chapter include small lemmas made up to
illustrate particular aspects of automation as well as larger
examples taken from the rest of the Software Foundations
development. For the larger examples, tactics from the library
[LibTactics.v] are used. Those tactics are described in the
chapter [UseTactics.v]. (You will need to read that chapter to
understand the later parts of this one, but the earlier parts can
be read on their own.) *)
Require Import LibTactics.
(* ####################################################### *)
(** * Basic Features of Proof Search *)
(** The idea of proof search is to replace a sequence of tactics
applying lemmas and assumptions with a call to a single tactic,
for example [auto]. This form of proof automation saves a lot of
effort. It typically leads to much shorter proof scripts, and to
scripts that are typically more robust to change. If one makes a
little change to a definition, a proof that exploits automation
probably won't need to be modified at all. Of course, using too
much automation is a bad idea. When a proof script no longer
records the main arguments of a proof, it becomes difficult to fix
it when it gets broken after a change in a definition. Overall, a
reasonable use of automation is generally a big win, as it saves a
lot of time both in building proof scripts and in subsequently
maintaining those proof scripts. *)
(* ####################################################### *)
(** ** Strength of Proof Search *)
(** We are going to study four proof-search tactics: [auto], [eauto],
[iauto] and [jauto]. The tactics [auto] and [eauto] are builtin
in Coq. The tactic [iauto] is a shorthand for the builtin tactic
[try solve [intuition eauto]]. The tactic [jauto] is defined in
the library [LibTactics], and simply performs some preprocessing
of the goal before calling [eauto]. The goal of this chapter is
to explain the general principles of proof search and to give
rule of thumbs for guessing which of the four tactics mentioned
above is best suited for solving a given goal.
Proof search is a compromise between efficiency and
expressiveness, that is, a tradeoff between how complex goals the
tactic can solve and how much time the tactic requires for
terminating. The tactic [auto] builds proofs only by using the
basic tactics [reflexivity], [assumption], and [apply]. The tactic
[eauto] can also exploit [eapply]. The tactic [jauto] extends
[eauto] by being able to open conjunctions and existentials that
occur in the context. The tactic [iauto] is able to deal with
conjunctions, disjunctions, and negation in a quite clever way;
however it is not able to open existentials from the
context. Also, [iauto] usually gets very slow when the goal
involves several disjunctions.
Note that proof search tactics never perform any rewriting
step (tactics [rewrite], [subst]), nor any case analysis on an
arbitrary data structure or predicate (tactics [destruct] and
[inversion]), nor any proof by induction (tactic [induction]). So,
proof search is really intended to automate the final steps from
the various branches of a proof. It is not able to discover the
overall structure of a proof. *)
(* ####################################################### *)
(** ** Basics *)
(** The tactic [auto] is able to solve a goal that can be proved
using a sequence of [intros], [apply], [assumption], and [reflexivity].
Two examples follow. The first one shows the ability for
[auto] to call [reflexivity] at any time. In fact, calling
[reflexivity] is always the first thing that [auto] tries to do. *)
Lemma solving_by_reflexivity :
2 + 3 = 5.
Proof. auto. Qed.
(** The second example illustrates a proof where a sequence of
two calls to [apply] are needed. The goal is to prove that
if [Q n] implies [P n] for any [n] and if [Q n] holds for any [n],
then [P 2] holds. *)
Lemma solving_by_apply : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. auto. Qed.
(** We can ask [auto] to tell us what proof it came up with,
by invoking [info auto] in place of [auto]. *)
Lemma solving_by_apply' : forall (P Q : nat->Prop),
(forall n, Q n -> P n) ->
(forall n, Q n) ->
P 2.
Proof. info auto. Qed.
(* The output is: *)
(* [intro P; intro Q; intro H; intro H0; simple apply H; simple apply H0]. *)
(* which can be reformulated as [intros P Q H H0; apply H; apply H0]. *)
(** The tactic [auto] can invoke [apply] but not [eapply]. So, [auto]
cannot exploit lemmas whose instantiation cannot be directly
deduced from the proof goal. To exploit such lemmas, one needs to
invoke the tactic [eauto], which is able to call [eapply].
In the following example, the first hypothesis asserts that [P n]
is true when [Q m] is true for some [m], and the goal is to prove
that [Q 1] implies [P 2]. This implication follows direction from
the hypothesis by instantiating [m] as the value [1]. The
following proof script shows that [eauto] successfully solves the
goal, whereas [auto] is not able to do so. *)
Lemma solving_by_eapply : forall (P Q : nat->Prop),
(forall n m, Q m -> P n) ->
Q 1 -> P 2.
Proof. auto. eauto. Qed.
(** Remark: Again, we can use [info eauto] to see what proof [eauto]
comes up with. *)
(* ####################################################### *)
(** ** Conjunctions *)
(** So far, we've seen that [eauto] is stronger than [auto] in the
sense that it can deal with [eapply]. In the same way, we are going
to see how [jauto] and [iauto] are stronger than [auto] and [eauto]
in the sense that they provide better support for conjunctions. *)
(** The tactics [auto] and [eauto] can prove a goal of the form
[F /\ F'], where [F] and [F'] are two propositions, as soon as
both [F] and [F'] can be proved in the current context.
An example follows. *)
Lemma solving_conj_goal : forall (P : nat->Prop) (F : Prop),
(forall n, P n) -> F -> F /\ P 2.
Proof. auto. Qed.
(** However, when an assumption is a conjunction, [auto] and [eauto]
are not able to exploit this conjunction. It can be quite
surprising at first that [eauto] can prove very complex goals but
that it fails to prove that [F /\ F'] implies [F]. The tactics
[iauto] and [jauto] are able to decompose conjunctions from the context.
Here is an example. *)
Lemma solving_conj_hyp : forall (F F' : Prop),
F /\ F' -> F.
Proof. auto. eauto. jauto. (* or [iauto] *) Qed.
(** The tactic [jauto] is implemented by first calling a
pre-processing tactic called [jauto_set], and then calling
[eauto]. So, to understand how [jauto] works, one can directly
call the tactic [jauto_set]. *)
Lemma solving_conj_hyp' : forall (F F' : Prop),
F /\ F' -> F.
Proof. intros. jauto_set. eauto. Qed.
(** Next is a more involved goal that can be solved by [iauto] and
[jauto]. *)
Lemma solving_conj_more : forall (P Q R : nat->Prop) (F : Prop),
(F /\ (forall n m, (Q m /\ R n) -> P n)) ->
(F -> R 2) ->
Q 1 ->
P 2 /\ F.
Proof. jauto. (* or [iauto] *) Qed.
(** The strategy of [iauto] and [jauto] is to run a global analysis of
the top-level conjunctions, and then call [eauto]. For this
reason, those tactics are not good at dealing with conjunctions
that occur as the conclusion of some universally quantified
hypothesis. The following example illustrates a general weakness
of Coq proof search mechanisms. *)
Lemma solving_conj_hyp_forall : forall (P Q : nat->Prop),
(forall n, P n /\ Q n) -> P 2.
Proof.
auto. eauto. iauto. jauto.
(* Nothing works, so we have to do some of the work by hand *)
intros. destruct (H 2). auto.
Qed.
(** This situation is slightly disappointing, since automation is
able to prove the following goal, which is very similar. The
only difference is that the universal quantification has been
distributed over the conjunction. *)
Lemma solved_by_jauto : forall (P Q : nat->Prop) (F : Prop),
(forall n, P n) /\ (forall n, Q n) -> P 2.
Proof. jauto. (* or [iauto] *) Qed.
(* ####################################################### *)
(** ** Disjunctions *)
(** The tactics [auto] and [eauto] can handle disjunctions that
occur in the goal. *)
Lemma solving_disj_goal : forall (F F' : Prop),
F -> F \/ F'.
Proof. auto. Qed.
(** However, only [iauto] is able to automate reasoning on the
disjunctions that appear in the context. For example, [iauto] can
prove that [F \/ F'] entails [F' \/ F]. *)
Lemma solving_disj_hyp : forall (F F' : Prop),
F \/ F' -> F' \/ F.
Proof. auto. eauto. jauto. iauto. Qed.
(** More generally, [iauto] can deal with complex combinations of
conjunctions, disjunctions, and negations. Here is an example. *)
Lemma solving_tauto : forall (F1 F2 F3 : Prop),
((~F1 /\ F3) \/ (F2 /\ ~F3)) ->
(F2 -> F1) ->
(F2 -> F3) ->
~F2.
Proof. iauto. Qed.
(** However, the ability of [iauto] to automatically perform a case
analysis on disjunctions comes with a downside: [iauto] can get
very slow. If the context involves several hypotheses with
disjunctions, [iauto] typically generates an exponential number of
subgoals on which [eauto] is called. One advantage of [jauto]
compared with [iauto] is that it never spends time performing this
kind of case analyses. *)
(* ####################################################### *)
(** ** Existentials *)
(** The tactics [eauto], [iauto], and [jauto] can prove goals whose
conclusion is an existential. For example, if the goal is [exists
x, f x], the tactic [eauto] introduces an existential variable,
say [?25], in place of [x]. The remaining goal is [f ?25], and
[eauto] tries to solve this goal, allowing itself to instantiate
[?25] with any appropriate value. For example, if an assumption [f
2] is available, then the variable [?25] gets instantiated with
[2] and the goal is solved, as shown below. *)
Lemma solving_exists_goal : forall (f : nat->Prop),
f 2 -> exists x, f x.
Proof.
auto. (* [auto] does not deal with existentials *)
eauto. (* [eauto], [iauto] and [jauto] solve the goal *)
Qed.
(** A major strength of [jauto] over the other proof search tactics is
that it is able to exploit the existentially quantified
_hypotheses_, i.e., those of the form [exists x, P]. *)
Lemma solving_exists_hyp : forall (f g : nat->Prop),
(forall x, f x -> g x) ->
(exists a, f a) ->
(exists a, g a).
Proof.
auto. eauto. iauto. (* All of these tactics fail, *)
jauto. (* whereas [jauto] succeeds. *)
(* For the details, run [intros. jauto_set. eauto] *)
Qed.
(* ####################################################### *)
(** ** Negation *)
(** The tactics [auto] and [eauto] suffer from some limitations with
respect to the manipulation of negations, mostly related to the
fact that negation, written [~ P], is defined as [P -> False] but
that the unfolding of this definition is not performed
automatically. Consider the following example. *)
Lemma negation_study_1 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof.
intros P H0 HX.
eauto. (* It fails to see that [HX] applies, *)
unfold not in *. eauto. (* unless the negation is unfolded *)
Qed.
(** For this reason, the tactics [iauto] and [jauto] systematically
invoke [unfold not in *] as part of their pre-processing. So,
they are able to solve the previous goal right away. *)
Lemma negation_study_2 : forall (P : nat->Prop),
P 0 -> (forall x, ~ P x) -> False.
Proof. jauto. (* or [iauto] *) Qed.
(** (We will come back later to the behavior of proof search with
respect to the unfolding of definitions.) *)
(* ####################################################### *)
(** ** Equalities *)
(** Coq's proof-search feature is not good at exploiting equalities.
It can do very basic operations, like exploiting reflexivity
and symmetry, but that's about it. Here is a simple example
that [auto] can solve, by first calling [symmetry] and then
applying the hypothesis. *)
Lemma equality_by_auto : forall (f g : nat->Prop),
(forall x, f x = g x) -> g 2 = f 2.
Proof. auto. Qed.
(** To automate more advanced reasoning on equalities, one should
rather try to use the tactic [congruence], which is presented at
the end of this chapter in the "Decision Procedures" section. *)
(* ####################################################### *)
(** * How Proof Search Works *)
(* ####################################################### *)
(** ** Search Depth *)
(** The tactic [auto] works as follows. It first tries to call
[reflexivity] and [assumption]. If one of these calls solves the
goal, the job is done. Otherwise [auto] tries to apply the most
recently introduced assumption that can be applied to the goal
without producing and error. This application produces
subgoals. There are two possible cases. If the sugboals produced
can be solved by a recursive call to [auto], then the job is done.
Otherwise, if this application produces at least one subgoal that
[auto] cannot solve, then [auto] starts over by trying to apply
the second most recently introduced assumption. It continues in a
similar fashion until it finds a proof or until no assumption
remains to be tried.
It is very important to have a clear idea of the backtracking
process involved in the execution of the [auto] tactic; otherwise
its behavior can be quite puzzling. For example, [auto] is not
able to solve the following triviality. *)
Lemma search_depth_0 :
True /\ True /\ True /\ True /\ True /\ True.
Proof.
auto.
Admitted.
(** The reason [auto] fails to solve the goal is because there are
too many conjunctions. If there had been only five of them, [auto]
would have successfully solved the proof, but six is too many.
The tactic [auto] limits the number of lemmas and hypotheses
that can be applied in a proof, so as to ensure that the proof
search eventually terminates. By default, the maximal number
of steps is five. One can specify a different bound, writing
for example [auto 6] to search for a proof involving at most
six steps. For example, [auto 6] would solve the previous lemma.
(Similarly, one can invoke [eauto 6] or [intuition eauto 6].)
The argument [n] of [auto n] is called the "search depth."
The tactic [auto] is simply defined as a shorthand for [auto 5].
The behavior of [auto n] can be summarized as follows. It first
tries to solve the goal using [reflexivity] and [assumption]. If
this fails, it tries to apply a hypothesis (or a lemma that has
been registered in the hint database), and this application
produces a number of sugoals. The tactic [auto (n-1)] is then
called on each of those subgoals. If all the subgoals are solved,
the job is completed, otherwise [auto n] tries to apply a
different hypothesis.
During the process, [auto n] calls [auto (n-1)], which in turn
might call [auto (n-2)], and so on. The tactic [auto 0] only
tries [reflexivity] and [assumption], and does not try to apply
any lemma. Overall, this means that when the maximal number of
steps allowed has been exceeded, the [auto] tactic stops searching
and backtracks to try and investigate other paths. *)
(** The following lemma admits a unique proof that involves exactly
three steps. So, [auto n] proves this goal iff [n] is greater than
three. *)
Lemma search_depth_1 : forall (P : nat->Prop),
P 0 ->
(P 0 -> P 1) ->
(P 1 -> P 2) ->
(P 2).
Proof.
auto 0. (* does not find the proof *)
auto 1. (* does not find the proof *)
auto 2. (* does not find the proof *)
auto 3. (* finds the proof *)
(* more generally, [auto n] solves the goal if [n >= 3] *)
Qed.
(** We can generalize the example by introducing an assumption
asserting that [P k] is derivable from [P (k-1)] for all [k],
and keep the assumption [P 0]. The tactic [auto], which is the
same as [auto 5], is able to derive [P k] for all values of [k]
less than 5. For example, it can prove [P 4]. *)
Lemma search_depth_3 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4).
Proof. auto. Qed.
(** However, to prove [P 5], one needs to call at least [auto 6]. *)
Lemma search_depth_4 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 5).
Proof. auto. auto 6. Qed.
(** Because [auto] looks for proofs at a limited depth, there are
cases where [auto] can prove a goal [F] and can prove a goal
[F'] but cannot prove [F /\ F']. In the following example,
[auto] can prove [P 4] but it is not able to prove [P 4 /\ P 4],
because the splitting of the conjunction consumes one proof step.
To prove the conjunction, one needs to increase the search depth,
using at least [auto 6]. *)
Lemma search_depth_5 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 4 /\ P 4).
Proof. auto. auto 6. Qed.
(* ####################################################### *)
(** ** Backtracking *)
(** In the previous section, we have considered proofs where
at each step there was a unique assumption that [auto]
could apply. In general, [auto] can have several choices
at every step. The strategy of [auto] consists of trying all
of the possibilities (using a depth-first search exploration).
To illustrate how automation works, we are going to extend the
previous example with an additional assumption asserting that
[P k] is also derivable from [P (k+1)]. Adding this hypothesis
offers a new possibility that [auto] could consider at every step.
There exists a special command that one can use for tracing
all the steps that proof-search considers. To view such a
trace, one should write [debug eauto]. (For some reason, the
command [debug auto] does not exist, so we have to use the
command [debug eauto] instead.) *)
Lemma working_of_auto_1 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Goal: *) (P 2).
(* Uncomment "debug" in the following line to see the debug trace: *)
Proof. intros P H1 H2 H3. (* debug *) eauto. Qed.
(** The output message produced by [debug eauto] is as follows.
<<
depth=5
depth=4 apply H3
depth=3 apply H3
depth=3 exact H1
>>
The depth indicates the value of [n] with which [eauto n] is
called. The tactics shown in the message indicate that the first
thing that [eauto] has tried to do is to apply [H3]. The effect of
applying [H3] is to replace the goal [P 2] with the goal [P 1].
Then, again, [H3] has been applied, changing the goal [P 1] into
[P 0]. At that point, the goal was exactly the hypothesis [H1].
It seems that [eauto] was quite lucky there, as it never even
tried to use the hypothesis [H2] at any time. The reason is that
[auto] always tries to use the most recently introduced hypothesis
first, and [H3] is a more recent hypothesis than [H2] in the goal.
So, let's permute the hypotheses [H2] and [H3] and see what
happens. *)
Lemma working_of_auto_2 : forall (P : nat->Prop),
(* Hypothesis H1: *) (P 0) ->
(* Hypothesis H3: *) (forall k, P (k-1) -> P k) ->
(* Hypothesis H2: *) (forall k, P (k+1) -> P k) ->
(* Goal: *) (P 2).
Proof. intros P H1 H3 H2. (* debug *) eauto. Qed.
(** This time, the output message suggests that the proof search
investigates many possibilities. Replacing [debug eauto] with
[info eauto], we observe that the proof that [eauto] comes up
with is actually not the simplest one.
[apply H2; apply H3; apply H3; apply H3; exact H1]
This proof goes through the proof obligation [P 3], even though
it is not any useful. The following tree drawing describes
all the goals that automation has been through.
<<
|5||4||3||2||1||0| -- below, tabulation indicates the depth
[P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 6]
-> [P 7]
-> [P 5]
-> [P 4]
-> [P 5]
-> [P 3]
--> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 4]
-> [P 5]
-> [P 3]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 1]
-> [P 2]
-> [P 3]
-> [P 1]
-> [P 0]
-> !! Done !!
>>
The first few lines read as follows. To prove [P 2], [eauto 5]
has first tried to apply [H2], producing the subgoal [P 3].
To solve it, [eauto 4] has tried again to apply [H2], producing
the goal [P 4]. Similarly, the search goes through [P 5], [P 6]
and [P 7]. When reaching [P 7], the tactic [eauto 0] is called
but as it is not allowed to try and apply any lemma, it fails.
So, we come back to the goal [P 6], and try this time to apply
hypothesis [H3], producing the subgoal [P 5]. Here again,
[eauto 0] fails to solve this goal.
The process goes on and on, until backtracking to [P 3] and trying
to apply [H2] three times in a row, going through [P 2] and [P 1]
and [P 0]. This search tree explains why [eauto] came up with a
proof starting with [apply H2]. *)
(* ####################################################### *)
(** ** Adding Hints *)
(** By default, [auto] (and [eauto]) only tries to apply the
hypotheses that appear in the proof context. There are two
possibilities for telling [auto] to exploit a lemma that have
been proved previously: either adding the lemma as an assumption
just before calling [auto], or adding the lemma as a hint, so
that it can be used by every calls to [auto].
The first possibility is useful to have [auto] exploit a lemma
that only serves at this particular point. To add the lemma as
hypothesis, one can type [generalize mylemma; intros], or simply
[lets: mylemma] (the latter requires [LibTactics.v]).
The second possibility is useful for lemmas that needs to be
exploited several times. The syntax for adding a lemma as a hint
is [Hint Resolve mylemma]. For example, the lemma asserting than
any number is less than or equal to itself, [forall x, x <= x],
called [Le.le_refl] in the Coq standard library, can be added as a
hint as follows. *)
Hint Resolve Le.le_refl.
(** A convenient shorthand for adding all the constructors of an
inductive datatype as hints is the command [Hint Constructors
mydatatype].
Warning: some lemmas, such as transitivity results, should
not be added as hints as they would very badly affect the
performance of proof search. The description of this problem
and the presentation of a general work-around for transitivity
lemmas appear further on. *)
(* ####################################################### *)
(** ** Integration of Automation in Tactics *)
(** The library "LibTactics" introduces a convenient feature for
invoking automation after calling a tactic. In short, it suffices
to add the symbol star ([*]) to the name of a tactic. For example,
[apply* H] is equivalent to [apply H; auto_star], where [auto_star]
is a tactic that can be defined as needed. By default, [auto_star]
first tries to solve the goal using [auto], and if this does not
succeed then it tries to call [jauto]. Even though [jauto] is
strictly stronger than [auto], it makes sense to call [auto] first:
when [auto] succeeds it may save a lot of time, and when [auto]
fails to prove the goal, it fails very quickly.
The definition of [auto_star], which determines the meaning of the
star symbol, can be modified whenever needed. Simply write:
[[
Ltac auto_star ::= a_new_definition.
]]
Observe the use of [::=] instead of [:=], which indicates that the
tactic is being rebound to a new definition. So, the default
definition is as follows. *)
Ltac auto_star ::= try solve [ auto | jauto ].
(** Nearly all standard Coq tactics and all the tactics from
"LibTactics" can be called with a star symbol. For example, one
can invoke [subst*], [destruct* H], [inverts* H], [lets* I: H x],
[specializes* H x], and so on... There are two notable exceptions.
The tactic [auto*] is just another name for the tactic
[auto_star]. And the tactic [apply* H] calls [eapply H] (or the
more powerful [applys H] if needed), and then calls [auto_star].
Note that there is no [eapply* H] tactic, use [apply* H]
instead. *)
(** In large developments, it can be convenient to use two degrees of
automation. Typically, one would use a fast tactic, like [auto],
and a slower but more powerful tactic, like [jauto]. To allow for
a smooth coexistence of the two form of automation, [LibTactics.v[
also defines a "tilde" version of tactics, like [apply~ H],
[destruct~ H], [subst~], [auto~] and so on. The meaning of the
tilde symbol is described by the [auto_tilde] tactic, whose
default implementation is [auto]. *)
Ltac auto_tilde ::= auto.
(** In the examples that follow, only [auto_star] is needed. *)
(* ####################################################### *)
(** * Examples of Use of Automation *)
(** Let's see how to use proof search in practice on the main theorems
of the "Software Foundations" course, proving in particular
results such as determinacy, preservation and progress... *)
(* ####################################################### *)
(** ** Determinacy *)
Module DeterministicImp.
Require Import Imp.
(** Recall the original proof of the determinacy lemma for the IMP
language, shown below. *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2.
generalize dependent st2.
(ceval_cases (induction E1) Case); intros st2 E2; inversion E2; subst.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b1 evaluates to true".
apply IHE1. assumption.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b1 evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b1 evaluates to true".
reflexivity.
SCase "b1 evaluates to false (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b1 evaluates to true (contradiction)".
rewrite H in H4. inversion H4.
SCase "b1 evaluates to false".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Qed.
(** Exercise: rewrite this proof using [auto] whenever possible. *)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** In fact, using automation is not just a matter of calling [auto]
in place of one or two other tactics. Using automation is about
rethinking the organization of sequences of tactics so as to
minimize the effort involved in writing and maintaining the proof.
This process is eased by the use of the tactics from
[LibTactics.v]. So, before trying to optimize the way automation
is used, let's first rewrite the proof of determinacy:
- use [introv H] instead of [intros x H],
- use [gen x] instead of [generalize dependent x],
- use [inverts H] instead of [inversion H; subst],
- use [tryfalse] to handle contradictions, and get rid of
the cases where [beval st b1 = true] and [beval st b1 = false]
both appear in the context,
- stop using [ceval_cases] to label subcases. *)
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
auto.
auto.
auto.
assert (st' = st'0). auto. subst. auto.
Qed.
(** To obtain a nice clean proof script, we have to remove the calls
[assert (st' = st'0)]. Such a tactic invokation is not nice
because it refers to some variables whose name has been
automatically generated. This kind of tactics tend to be very
brittle. The tactic [assert (st' = st'0)] is used to assert the
conclusion that we want to derive from the induction
hypothesis. So, rather than stating this conclusion explicitly, we
are going to ask Coq to instantiate the induction hypothesis,
using automation to figure out how to instantiate it. The tactic
[forwards], described in [LibTactics.v] precisely helps with
instantiating a fact. So, let's see how it works out on our
example. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
(* Let's replay the proof up to the [assert] tactic. *)
introv E1 E2. gen st2.
induction E1; intros; inverts E2; tryfalse.
auto. auto.
(* Let's duplicate the goal to compare the old proof with the new one *)
dup 4.
(* The old proof: *)
assert (st' = st'0). apply IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, without automation: *)
forwards: IHE1_1. apply H1.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with automation: *)
forwards: IHE1_1. eauto.
(* produces [H: st' = st'0]. *) skip.
(* The new proof, with integrated automation: *)
forwards*: IHE1_1.
(* produces [H: st' = st'0]. *) skip.
Admitted.
(** To polish the proof script, it remains to factorize the calls
to [auto], using the star symbol. The proof of determinacy can then
be rewritten in only four lines, including no more than 10 tactics. *)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
introv E1 E2. gen st2.
induction E1; intros; inverts* E2; tryfalse.
forwards*: IHE1_1. subst*.
forwards*: IHE1_1. subst*.
Qed.
End DeterministicImp.
(* ####################################################### *)
(** ** Preservation for STLC *)
Module PreservationProgressStlc.
Require Import Stlc.
Import STLC.
(** Recall the proof of perservation of STLC, shown next.
This proof already uses [eauto] through the triple-dot
mechanism. *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
(has_type_cases (induction HT) Case); intros t' HE; subst Gamma.
Case "T_Var".
inversion HE.
Case "T_Abs".
inversion HE.
Case "T_App".
inversion HE; subst...
(* (step_cases (inversion HE) SCase); subst...*)
(* The ST_App1 and ST_App2 cases are immediate by induction, and
auto takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Case "T_True".
inversion HE.
Case "T_False".
inversion HE.
Case "T_If".
inversion HE; subst...
Qed.
(** Exercise: rewrite this proof using tactics from [LibTactics]
and calling automation using the star symbol rather than the
triple-dot notation. More precisely, make use of the tactics
[inverts*] and [applys*] to call [auto*] after a call to
[inverts] or to [applys]. The solution is three lines long.*)
Theorem preservation' : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof.
(* FILL IN HERE *) admit.
Qed.
(* ####################################################### *)
(** ** Progress for STLC *)
(** Recall the proof of the progress theorem. *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
(has_type_cases (induction Ht) Case); subst Gamma...
Case "T_Var".
inversion H.
Case "T_App".
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
exists (subst t2 x t)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tm_app t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tm_app t1' t2)...
Case "T_If".
right. destruct IHHt1...
destruct t1; try solve by inversion...
inversion H. exists (tm_if x t2 t3)...
Qed.
(** Exercise: optimize the proof of the progress theorem.
Hint: make use of [destruct*] and [inverts*].
The solution is 10 lines long (short lines). *)
Theorem progress' : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof.
(* FILL IN HERE *) admit.
Qed.
End PreservationProgressStlc.
(* ####################################################### *)
(** ** BigStep and SmallStep *)
Module Semantics.
Require Import Smallstep.
(** Recall the proof relating a small-step reduction judgment
to a big-step reduction judgment. *)
Theorem stepmany__eval : forall t v,
normal_form_of t v -> t || v.
Proof.
intros t v Hnorm.
unfold normal_form_of in Hnorm.
inversion Hnorm as [Hs Hnf]; clear Hnorm.
apply nf_is_value in Hnf. inversion Hnf. clear Hnf.
(rsc_cases (induction Hs) Case); subst.
Case "rsc_refl".
apply E_Const.
Case "rsc_step".
eapply step__eval. eassumption. apply IHHs. reflexivity.
Qed.
(** Exercise: optimize the above proof, using [introv],
[invert], and [applys*]. The solution is 4 lines long. *)
Theorem stepmany__eval' : forall t v,
normal_form_of t v -> t || v.
Proof.
(* FILL IN HERE *) admit.
Qed.
End Semantics.
(* ####################################################### *)
(** ** Preservation for STLCRef *)
Module PreservationProgressReferences.
Require Import References.
Import STLCRef.
Hint Resolve store_weakening extends_refl.
(** The proof of preservation for [STLCRef] can be found
in the file [References.v]. It contains 58 lines (not
counting the labelling of cases). The optimized proof
script is more than twice shorter. The following material
explains how to build the optimized proof script.
The resulting optimized proof script for the preservation
theorem appears afterwards. *)
Theorem preservation : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
(* old: [Proof. with eauto using store_weakening, extends_refl.]
new: [Proof.], and the two lemmas are registered as hints
before the proof of the lemma, possibly inside a section in
order to restrict the scope of the hints. *)
remember (@empty ty) as Gamma. introv Ht. gen t'.
(has_type_cases (induction Ht) Case); introv HST Hstep;
(* old: [subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl)]
new: [subst Gamma; inverts Hstep; eauto.]
We want to be more precise on what exactly we substitute,
and we do not want to call [try (solve by inversion)] which
is way to slow. *)
subst Gamma; inverts Hstep; eauto.
Case "T_App".
SCase "ST_AppAbs".
(* old:
exists ST. inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing... *)
(* new: we use [inverts] in place of [inversion] and [splits] to
split the conjunction, and [applys*] in place of [eapply...] *)
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
SCase "ST_App1".
(* old:
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: The tactic [eapply IHHt1 in H0...] applies [IHHt1] to [H0].
But [H0] is only thing that [IHHt1] could be applied to, so
there [eauto] can figure this out on its own. The tactic
[forwards] is used to instantiate all the arguments of [IHHt1],
creating existential variables and producing subgoals when needed. *)
forwards: IHHt1. eauto. eauto. eauto.
(* At this point, we need to decompose the hypothesis [H] that has
just been created by [forwards]. This is done by the first part
of the preprocessing phase of [jauto]. *)
jauto_set_hyps; intros.
(* It remains to decompose the goal, which is done by the second part
of the preprocessing phase of [jauto]. *)
jauto_set_goal; intros.
(* All the subgoals produced can then be solved by [eauto]. *)
eauto. eauto. eauto.
SCase "ST_App2".
(* old:
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'... *)
(* new: this time, we need to call [forwards] on [IHHt2],
and we call [jauto] right away, by writing [forwards*],
proving the goal in a single tactic! *)
forwards*: IHHt2.
(* The same trick works for many of the other subgoals. *)
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
Case "T_Ref".
SCase "ST_RefValue".
(* old:
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (ty_Ref T1) with (ty_Ref (store_ty_lookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_ty_lookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption. *)
(* new: in this proof case, we need to perform an inversion without
removing the hypothesis. The tactic [inverts keep] serves that purpose. *)
exists (snoc ST T1). inverts keep HST. splits.
(* The proof of the first subgoal needs not be changed *)
apply extends_snoc.
(* For the second subgoal, we use the tactic [applys_eq] to avoid
a manual [replace] before [T_loc] can be applied. *)
applys_eq T_Loc 1.
(* To justify the inequality, there is no need to call [rewrite <- H],
because the tactic [omega] is able to exploit [H] on its own.
So, only the rewriting of [lenght_snoc] and the call to [omega] remain. *)
rewrite length_snoc. omega.
(* The next proof case is hard to polish because it relies on the
lemma [nth_eq_snoc] whose statement is not automation-friendly.
We'll come back to this proof case further on. *)
unfold store_ty_lookup. rewrite <- H. rewrite* nth_eq_snoc.
(* Last, we replace [apply ..; assumption] with [apply* ..] *)
apply* store_well_typed_snoc.
forwards*: IHHt.
Case "T_Deref".
SCase "ST_DerefLoc".
(* old:
exists ST. split; try split...
destruct HST as [_ Hsty].
replace T11 with (store_ty_lookup l ST).
apply Hsty...
inversion Ht; subst... *)
(* new: we start by calling [exists ST] and [splits*]. *)
exists ST. splits*.
(* new: we replace [destruct HST as [_ Hsty]] by the following *)
lets [_ Hsty]: HST.
(* new: then we use the tactic [applys_eq] to avoid the need to
perform a manual [replace] before applying [Hsty]. *)
applys_eq* Hsty 1.
(* new: finally, we can call [inverts] in place of [inversion;subst] *)
inverts* Ht.
forwards*: IHHt.
Case "T_Assign".
SCase "ST_Assign".
(* old:
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst... *)
(* new: simply using nicer tactics *)
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(** Let's come back to the proof case that was hard to optimize.
The difficulty comes from the statement of [nth_eq_snoc], which
takes the form [nth (length l) (snoc l x) d = x]. This lemma is
hard to exploit because its first argument, [length l], mentions
a list [l] that has to be exactly the same as the [l] occuring in
[snoc l x]. In practice, the first argument is often a natural
number [n] that is provably equal to [length l] yet that is not
syntactically equal to [length l]. There is a simple fix for
making [nth_eq_snoc] easy to apply: introduce the intermediate
variable [n] explicitly, so that the goal becomes
[nth n (snoc l x) d = x], with a premise asserting [n = length l]. *)
Lemma nth_eq_snoc' : forall (A : Type) (l : list A) (x d : A) (n : nat),
n = length l -> nth n (snoc l x) d = x.
Proof. intros. subst. apply nth_eq_snoc. Qed.
(** The proof case for [ref] from the preservation theorem then
becomes much easier to prove, because [rewrite nth_eq_snoc']
now succeeds. *)
Lemma preservation_ref : forall (st:store) (ST : store_ty) T1,
length ST = length st ->
ty_Ref T1 = ty_Ref (store_ty_lookup (length st) (snoc ST T1)).
Proof.
intros. dup.
(* A first proof, with an explicit [unfold] *)
unfold store_ty_lookup. rewrite* nth_eq_snoc'.
(* A second proof, with a call to [fequal] *)
fequal. symmetry. apply* nth_eq_snoc'.
Qed.
(** The optimized proof of preservation is summarized next. *)
Theorem preservation' : forall ST t t' T st st',
has_type empty ST t T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
has_type empty ST' t' T /\
store_well_typed ST' st').
Proof.
remember (@empty ty) as Gamma. introv Ht. gen t'.
induction Ht; introv HST Hstep; subst Gamma; inverts Hstep; eauto.
exists ST. inverts Ht1. splits*. applys* substitution_preserves_typing.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt.
forwards*: IHHt.
forwards*: IHHt1.
forwards*: IHHt2.
forwards*: IHHt1.
exists (snoc ST T1). inverts keep HST. splits.
apply extends_snoc.
applys_eq T_Loc 1.
rewrite length_snoc. omega.
unfold store_ty_lookup. rewrite* nth_eq_snoc'.
apply* store_well_typed_snoc.
forwards*: IHHt.
exists ST. splits*. lets [_ Hsty]: HST.
applys_eq* Hsty 1. inverts* Ht.
forwards*: IHHt.
exists ST. splits*. applys* assign_pres_store_typing. inverts* Ht1.
forwards*: IHHt1.
forwards*: IHHt2.
Qed.
(* ####################################################### *)
(** ** Progress for STLCRef *)
(** The proof of progress for [STLCRef] can be found in
the file [References.v]. It contains 53 lines and the
optimized proof script is, here again, twice shorter. *)
Theorem progress : forall ST t T st,
has_type empty ST t T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof.
introv Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst Gamma; tryfalse; try solve [left*].
right. destruct* IHHt1 as [K|].
inverts K; inverts Ht1.
destruct* IHHt2.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt as [K|].
inverts K; try solve [inverts Ht]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1].
destruct* IHHt2 as [M|].
inverts M; try solve [inverts Ht2]. eauto.
right. destruct* IHHt1 as [K|].
inverts K; try solve [inverts Ht1]. destruct* n.
right. destruct* IHHt.
right. destruct* IHHt as [K|].
inverts K; inverts Ht as M.
inverts HST as N. rewrite* N in M.
right. destruct* IHHt1 as [K|].
destruct* IHHt2.
inverts K; inverts Ht1 as M.
inverts HST as N. rewrite* N in M.
Qed.
End PreservationProgressReferences.
(* ####################################################### *)
(** ** Subtyping *)
Module SubtypingInversion.
Require Import Subtyping.
(** Recall the inversion lemma for typing judgment
of abstractions in a type system with subtyping. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tm_abs x S1 s2) (ty_arrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst...
Qed.
(** Exercise: optimize the proof script, using
[introv], [lets] and [inverts*]. In particular,
you will find it useful to replace the pattern
[apply K in H. destruct H as I] with [lets I: K H].
The solution is 4 lines. *)
Lemma abs_arrow' : forall x S1 s2 T1 T2,
has_type empty (tm_abs x S1 s2) (ty_arrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof.
(* FILL IN HERE *) admit.
Qed.
(** The lemma [substitution_preserves_typing] has already been
used to illustrate the working of [lets] and [applys] in
the file [UseTactics.v]. Optimize further this proof using
automation (with the star symbol), and using the tactic
[cases_if']. The solution is 33 lines, including the
[Case] instructions. *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma (subst v x t) S.
Proof.
(* FILL IN HERE *) admit.
Qed.
End SubtypingInversion.
(* ####################################################### *)
(** * Advanced Topics in Proof Search *)
(* ####################################################### *)
(** ** Stating Lemmas in the Right Way *)
(** Due to its depth-first strategy, [eauto] can get exponentially
slower as the depth search increases, even when a short proof
exists. In general, to make proof search run reasonably fast, one
should avoid using a depth search greater than 5 or 6. Moreover,
one should try to minimize the number of applicable lemmas, and
usually put first the hypotheses whose proof usefully instantiates
the existential variables.
In fact, the ability for [eauto] to solve certain goals actually
depends on the order in which the hypotheses are stated. This point
is illustrated through the following example, in which [P] is
a predicate on natural numbers. This predicate is such that
[P n] holds for any [n] as soon as [P m] holds for at least one [m]
different from zero. The goal is to prove that [P 2] implies [P 1].
When the hypothesis about [P] is stated in the form
[forall n m, P m -> m <> 0 -> P n], then [eauto] works. However, with
[forall n m, m <> 0 -> P m -> P n], the tactic [eauto] fails. *)
Lemma order_matters_1 : forall (P : nat->Prop),
(forall n m, P m -> m <> 0 -> P n) -> P 2 -> P 1.
Proof.
eauto. (* Success *)
(* The proof: [intros P H K. eapply H. apply K. auto.] *)
Qed.
Lemma order_matters_2 : forall (P : nat->Prop),
(forall n m, m <> 0 -> P m -> P n) -> P 5 -> P 1.
Proof.
eauto. (* Failure *)
(* To understand why, let us replay the previous proof *)
intros P H K.
eapply H.
(* The application of [eapply] has left two subgoals,
[?X <> 0] and [P ?X], where [?X] is an existential variable. *)
(* Solving the first subgoal is easy for [eauto]: it suffices
to instantiate [?X] as the value [1], which is the simplest
value that satisfies [?X <> 0]. *)
eauto.
(* But then the second goal becomes [P 1], which is where we
started from. So, [eauto] gets stuck at this point. *)
Admitted.
(** What is important to understand is that the hypothesis [forall n
m, P m -> m <> 0 -> P n] is eauto-friendly, whereas [forall n m, m
<> 0 -> P m -> P n] really isn't. Guessing a value of [m] for
which [P m] holds and then checking that [m <> 0] holds works well
because there are few values of [m] for which [P m] holds. So, it
is likely that [eauto] comes up with the right one. On the other
hand, guessing a value of [m] for which [m <> 0] and then checking
that [P m] holds does not work well, because there are many values
of [m] that satisfy [m <> 0] but not [P m]. *)
(* ####################################################### *)
(** ** Unfolding of Definitions During Proof-Search *)
(** The use of intermediate definitions is generally encouraged in a
formal development as it usually leads to more concise and more
readable statements. Yet, definitions can make it a little harder
to automate proofs. The problem is that it is not obvious for a
proof search mechanism to know when definitions need to be
unfolded. Note that a naive strategy that consists of unfolding
all definitions before calling proof search does not scale up to
large proofs, so we avoid it. This section introduces a few
techniques for avoiding to manually unfold definitions before
calling proof search. *)
(** To illustrate the treatment of definitions, let [P] be an abstract
predicate on natural numbers, and let [myFact] be a definition
denoting the proposition [P x] holds for any [x] less than or
equal to 3. *)
Axiom P : nat -> Prop.
Definition myFact := forall x, x <= 3 -> P x.
(** Proving that [myFact] under the assumption that [P x] holds for
any [x] should be trivial. Yet, [auto] fails to prove it unless we
unfold the definition of [myFact] explicitly. *)
Lemma demo_hint_unfold_goal_1 :
(forall x, P x) -> myFact.
Proof.
auto. (* Proof search doesn't know what to do, *)
unfold myFact. auto. (* unless we unfold the definition. *)
Qed.
(** To automate the unfolding of definitions that appear as proof
obligation, one can use the command [Hint Unfold myFact] to tell
Coq that it should always try to unfold [myFact] when [myFact]
appears in the goal. *)
Hint Unfold myFact.
(** This time, automation is able to see through the definition
of [myFact]. *)
Lemma demo_hint_unfold_goal_2 :
(forall x, P x) -> myFact.
Proof. auto. Qed.
(** However, the [Hint Unfold] mechanism only works for unfolding
definitions that appear in the goal. In general, proof search does
not unfold definitions from the context. For example, assume we
want to prove that [P 3] holds under the assumption that [True ->
myFact]. *)
Lemma demo_hint_unfold_context_1 :
(True -> myFact) -> P 3.
Proof.
intros.
auto. (* fails *)
unfold myFact in *. auto. (* succeeds *)
Qed.
(** Note: there is one exception to the previous rule: a constant from
the context is automatically unfolded when it directly applies to
the goal. For example, if the assumption is [myFact] instead of
[True -> myFact], then [auto] solves the proof. *)
(* ####################################################### *)
(** ** Automation for Proving Absurd Goals *)
(** In this section, we'll see that lemmas concluding on a negation
are generally not useful as hints, and that lemmas whose
conclusion is [False] can be useful hints but having too many of
them makes proof search inefficient. We'll also see a practical
work-around to the efficiency issue. *)
(** Consider the following lemma, which asserts that a number
less than or equal to 3 is not greater than 3. *)
Parameter le_not_gt : forall x,
(x <= 3) -> ~ (x > 3).
(** Equivalently, one could state that a number greater than three is
not less than or equal to 3. *)
Parameter gt_not_le : forall x,
(x > 3) -> ~ (x <= 3).
(** In fact, both statements are equivalent to a third one stating
that [x <= 3] and [x > 3] are contradictory, in the sense that
they imply [False]. *)
Parameter le_gt_false : forall x,
(x <= 3) -> (x > 3) -> False.
(** The following investigation aim at figuring out which of the three
statments is the most convenient with respect to proof
automation. The following material is enclosed inside a [Section],
so as to restrict the scope of the hints that we are adding. In
other words, after the end of the section, the hints added within
the section will no longer be active.*)
Section DemoAbsurd1.
(** Let's try to add the first lemma, [le_not_gt], as hint,
and see whether we can prove that the proposition
[exists x, x <= 3 /\ x > 3] is absurd. *)
Hint Resolve le_not_gt.
Lemma demo_auto_absurd_1 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
intros. jauto_set. (* decomposes the assumption *)
(* debug *) eauto. (* does not see that [le_not_gt] could apply *)
eapply le_not_gt. eauto. eauto.
Qed.
(** The lemma [gt_not_le] is symmetric to [le_not_gt], so it will not
be any better. The third lemma, [le_gt_false], is a more useful
hint, because it concludes on [False], so proof search will try to
apply it when the current goal is [False]. *)
Hint Resolve le_gt_false.
Lemma demo_auto_absurd_2 :
(exists x, x <= 3 /\ x > 3) -> False.
Proof.
dup.
(* detailed version: *)
intros. jauto_set. (* debug *) eauto.
(* short version: *)
jauto.
Qed.
(** In summary, a lemma of the form [H1 -> H2 -> False] is a much more
effective hint than [H1 -> ~ H2], even though the two statments
are equivalent up to the definition of the negation symbol [~]. *)
(** That said, one should be careful with adding lemmas whose
conclusion is [False] as hint. The reason is that whenever
reaching the goal [False], the proof search mechanism will
potentially try to apply all the hints whose conclusion is [False]
before applying the appropriate one. *)
End DemoAbsurd1.
(** Adding lemmas whose conclusion is [False] as hint can be, locally,
a very effective solution. However, this approach does not scale
up for global hints. For most practical applications, it is
reasonable to give the name of the lemmas to be exploited for
deriving a contradiction. The tactic [false H] is useful for that
purpose: it replaces the goal with [False] and calls [eapply
H]. Its behavior is described next. Observe that any of the three
statements [le_not_gt], [gt_not_le] or [le_gt_false] can be
used. *)
Lemma demo_false : forall x,
(x <= 3) -> (x > 3) -> 4 = 5.
Proof.
intros. dup 4.
(* A failed proof: *)
false. eapply le_gt_false.
auto. (* [auto] does not prove [?x <= 3] using [H], but instead
using the lemma [le_refl : forall x, x <= x]. *)
(* The second subgoal becomes [3 > 3], which is not provable. *)
skip.
(* A correct proof: *)
false. eapply le_gt_false.
eauto. (* [eauto] uses [H], as expected, to prove [?x <= 3] *)
eauto. (* so the second subgoal becomes [x > 3] *)
(* The same proof using [false]: *)
false le_gt_false. eauto. eauto.
(* The lemmas [le_not_gt] and [gt_not_le] work as well *)
false le_not_gt. eauto. eauto.
Qed.
(** In the above example, [false le_gt_false; eauto] proves the goal,
but [false le_gt_false; auto] does not, because [auto] does not
correctly instantiate the existential variable. Note that [false*
le_gt_false] would not work either, because the [*] symbol tries
to call [auto] first. So, there are two possibilities for
completing the proof: either call [false le_gt_false; eauto], or
call [false* (le_gt_false 3)]. *)
(* ####################################################### *)
(** ** Automation for Transitivity Lemmas *)
(** Some lemmas should never be added as hints, because they would
very badly slow down proof search. The typical example is that of
transitivity results. This section describes the problem and
presents a general workaround.
Consider a subtyping relation, written [subtype S T], that relates
two object [S] and [T] of type [typ]. Assume that this relation
has been proved reflexive and transitive. The corresponding lemmas
are named [subtype_refl] and [subtype_trans]. *)
Parameter typ : Type.
Parameter subtype : typ -> typ -> Prop.
Parameter subtype_refl : forall T,
subtype T T.
Parameter subtype_trans : forall S T U,
subtype S T -> subtype T U -> subtype S U.
(** Adding reflexivity as hint is generally a good idea,
so let's add reflexivity of subtyping as hint. *)
Hint Resolve subtype_refl.
(** Adding transitivity as hint is generally a bad idea. To
understand why, let's add it as hint and see what happens.
Because we cannot remove hints once we've added them, we are going
to open a "Section," so as to restrict the scope of the
transitivity hint to that section. *)
Section HintsTransitivity.
Hint Resolve subtype_trans.
(** Now, consider the goal [forall S T, subtype S T], which clearly has
no hope of being solved. Let's call [eauto] on this goal. *)
Lemma transitivity_bad_hint_1 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 106 applications... *)
Admitted.
(** Note that after closing the section, the hint [subtype_trans]
is no longer active. *)
End HintsTransitivity.
(** In the previous example, the proof search has spent a lot of time
trying to apply transitivity and reflexivity in every possible
way. Its process can be summarized as follows. The first goal is
[subtype S T]. Since reflexivity does not apply, [eauto] invokes
transitivity, which produces two subgoals, [subtype S ?X] and
[subtype ?X T]. Solving the first subgoal, [subtype S ?X], is
straightforward, it suffices to apply reflexivity. This unifies
[?X] with [S]. So, the second sugoal, [subtype ?X T], becomes
becomes [subtype S T], which is exactly what we started from...
The problem with the transitivity lemma is that it is applicable
to any goal concluding on a subtyping relation. Because of this,
[eauto] keeps trying to apply it even though it most often doesn't
help to solve the goal. So, one should never add a transitivity
lemma as a hint for proof search. *)
(** There is a general workaround for having automation to exploit
transitivity lemmas without giving up on efficiency. This workaround
relies on a powerful mechanism called "external hint." This
mechanism allows to manually describe the condition under which
a particular lemma should be tried out during proof search.
For the case of transitivity of subtyping, we are going to tell
Coq to try and apply the transitivity lemma on a goal of the form
[subtype S U] only when the proof context already contains an
assumption either of the form [subtype S T] or of the form
[subtype T U]. In other words, we only apply the transitivity
lemma when there is some evidence that this application might
help. To set up this "external hint," one has to write the
following. *)
Hint Extern 1 (subtype ?S ?U) =>
match goal with
| H: subtype S ?T |- _ => apply (@subtype_trans S T U)
| H: subtype ?T U |- _ => apply (@subtype_trans S T U)
end.
(** This hint declaration can be understood as follows.
- "Hint Extern" introduces the hint.
- The number "1" corresponds to a priority for proof search.
It doesn't matter so much what priority is used in practice.
- The pattern [subtype ?S ?U] describes the kind of goal on
which the pattern should apply. The question marks are used
to indicate that the variables [?S] and [?U] should be bound
to some value in the rest of the hint description.
- The construction [match goal with ... end] tries to recognize
patterns in the goal, or in the proof context, or both.
- The first pattern is [H: subtype S ?T |- _]. It indices that
the context should contain an hypothesis [H] of type
[subtype S ?T], where [S] has to be the same as in the goal,
and where [?T] can have any value.
- The symbol [|- _] at the end of [H: subtype S ?T |- _] indicates
that we do not impose further condition on how the proof
obligation has to look like.
- The branch [=> apply subtype_trans with (T:=T)] that follows
indicate that if the goal has the form [subtype S U] and if
there exists an hypothesis of the form [subtype S T], then
we should try and apply transitivity lemma instantiated on
the arguments [S], [T] and [U]. (Note: the symbol [@] in front of
[subtype_trans] is only actually needed when the "Implicit Arguments"
feature is activated.)
- The other branch, which corresponds to an hypothesis of the form
[H: subtype ?T U] is symmetrical.
Note: the same external hint can be reused for any other transitive
relation, simply by renaming [subtype] into the name of that relation. *)
(** Let us see an example illustrating how the hint works. *)
Lemma transitivity_workaround_1 : forall T1 T2 T3 T4,
subtype T1 T2 -> subtype T2 T3 -> subtype T3 T4 -> subtype T1 T4.
Proof.
intros. (* debug *) eauto. (* The trace shows the external hint being used *)
Qed.
(** We may also check that the new external hint does not suffer from the
complexity blow up. *)
Lemma transitivity_workaround_2 : forall S T,
subtype S T.
Proof.
intros. (* debug *) eauto. (* Investigates 0 applications *)
Admitted.
(* ####################################################### *)
(** * Decision Procedures *)
(** A decision procedure is able to solve proof obligations whose
statement admits a particular form. This section describes three
useful decision procedures. The tactic [omega] handles goals
involving arithmetic and inequalities, but not general
multiplications. The tactic [ring] handles goals involving
arithmetic, including multiplications, but does not support
inequalities. The tactic [congruence] is able to prove equalities
and inequalities by exploiting equalities available in the proof
context. *)
(* ####################################################### *)
(** ** Omega *)
(** The tactic [omega] supports natural numbers (type [nat]) as well as
integers (type [Z], available by including the module [ZArith]).
It supports addition, substraction, equalities and inequalities.
Before using [omega], one needs to import the module [Omega],
as follows. *)
Require Import Omega.
(** Here is an example. Let [x] and [y] be two natural numbers
(they cannot be negative). Assume [y] is less than 4, assume
[x+x+1] is less than [y], and assume [x] is not zero. Then,
it must be the case that [x] is equal to one. *)
Lemma omega_demo_1 : forall (x y : nat),
(y <= 4) -> (x + x + 1 <= y) -> (x <> 0) -> (x = 1).
Proof. intros. omega. Qed.
(** Another example: if [z] is the mean of [x] and [y], and if the
difference between [x] and [y] is at most [4], then the difference
between [x] and [z] is at most 2. *)
Lemma omega_demo_2 : forall (x y z : nat),
(x + y = z + z) -> (x - y <= 4) -> (x - z <= 2).
Proof. intros. omega. Qed.
(** One can proof [False] using [omega] if the mathematical facts
from the context are contradictory. In the following example,
the constraints on the values [x] and [y] cannot be all
satisfied in the same time. *)
Lemma omega_demo_3 : forall (x y : nat),
(x + 5 <= y) -> (y - x < 3) -> False.
Proof. intros. omega. Qed.
(** Note: [omega] can prove a goal by contradiction only if its
conclusion is reduced [False]. The tactic [omega] always fails
when the conclusion is an arbitrary proposition [P], even though
[False] implies any proposition [P] (by [ex_falso_quodlibet]). *)
Lemma omega_demo_4 : forall (x y : nat) (P : Prop),
(x + 5 <= y) -> (y - x < 3) -> P.
Proof.
intros.
(* Calling [omega] at this point fails with the message:
"Omega: Can't solve a goal with proposition variables" *)
(* So, one needs to replace the goal by [False] first. *)
false. omega.
Qed.
(* ####################################################### *)
(** ** Ring *)
(** Compared with [omega], the tactic [ring] adds support for
multiplications, however it gives up the ability to reason on
inequations. Moreover, it supports only integers (type [Z]) and
not natural numbers (type [Z]). Here is an example showing how to
use [ring]. *)
Module RingDemo.
Require Import ZArith.
Open Scope Z_scope. (* "+" and "-" and "*" should be interpreted in [Z] *)
Lemma ring_demo : forall (x y z : Z),
x * (y + z) - z * 3 * x
= x * y - 2 * x * z.
Proof. intros. ring. Qed.
End RingDemo.
(* ####################################################### *)
(** ** Congruence *)
(** The tactic [congruence] is able to exploit equalities from the
proof context in order to automatically perform the rewriting
operations necessary to establish a goal. It is slightly more
powerful than the tactic [subst], which can only handle equalities
of the form [x = e] where [x] is a variable and [e] an
expression. *)
Lemma congruence_demo_1 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
f (g x) (g y) = z ->
2 = g x ->
g y = h z ->
f 2 (h z) = z.
Proof. intros. congruence. Qed.
(** Moreover, [congruence] is able to exploit universally quantified
equalities, for example [forall a, g a = h a]. *)
Lemma congruence_demo_2 :
forall (f : nat->nat->nat) (g h : nat->nat) (x y z : nat),
(forall a, g a = h a) ->
f (g x) (g y) = z ->
g x = 2 ->
f 2 (h y) = z.
Proof. congruence. Qed.
(** Next is an example where [congruence] is very useful. *)
Lemma congruence_demo_4 : forall (f g : nat->nat),
(forall a, f a = g a) ->
f (g (g 2)) = g (f (f 2)).
Proof. congruence. Qed.
(** The tactic [congruence] is able to prove a contradiction if the
goal entails an equality that contradicts an inequality available
in the proof context. *)
Lemma congruence_demo_3 :
forall (f g h : nat->nat) (x : nat),
(forall a, f a = h a) ->
g x = f x ->
g x <> h x ->
False.
Proof. congruence. Qed.
(** One of the strengths of [congruence] is that it is a very fast
tactic. So, one should not hesitate to invoke it wherever it might
help. *)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fifoRTL.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
//// parameterized dual clock domain fifo.
//// fifo depth is restricted to 2^ADDR_WIDTH
//// No protection against over runs and under runs.
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//`include "timescale.v"
module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn,
dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
parameter FIFO_WIDTH = 8;
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
// Two clock domains within this module
// These ports are within 'wrClk' domain
input wrClk;
input rstSyncToWrClk;
input [FIFO_WIDTH-1:0] dataIn;
input fifoWEn;
input forceEmptySyncToWrClk;
output fifoFull;
// These ports are within 'rdClk' domain
input rdClk;
input rstSyncToRdClk;
output [FIFO_WIDTH-1:0] dataOut;
input fifoREn;
input forceEmptySyncToRdClk;
output fifoEmpty;
output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
wire wrClk;
wire rdClk;
wire rstSyncToWrClk;
wire rstSyncToRdClk;
wire [FIFO_WIDTH-1:0] dataIn;
reg [FIFO_WIDTH-1:0] dataOut;
wire fifoWEn;
wire fifoREn;
reg fifoFull;
reg fifoEmpty;
wire forceEmpty;
reg [15:0]numElementsInFifo;
// local registers
reg [ADDR_WIDTH:0]bufferInIndex;
reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
reg [ADDR_WIDTH:0]bufferOutIndex;
reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
reg [ADDR_WIDTH-1:0]bufferInIndexToMem;
reg [ADDR_WIDTH-1:0]bufferOutIndexToMem;
reg [ADDR_WIDTH:0]bufferCnt;
reg fifoREnDelayed;
wire [FIFO_WIDTH-1:0] dataFromMem;
always @(posedge wrClk)
begin
bufferOutIndexSyncToWrClk <= bufferOutIndex;
if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
begin
fifoFull <= 1'b0;
bufferInIndex <= 0;
end
else
begin
if (fifoWEn == 1'b1) begin
bufferInIndex <= bufferInIndex + 1'b1;
end
if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
(bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
fifoFull <= 1'b1;
else
fifoFull <= 1'b0;
end
end
always @(bufferInIndexSyncToRdClk or bufferOutIndex)
bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
always @(posedge rdClk)
begin
numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
bufferInIndexSyncToRdClk <= bufferInIndex;
if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
begin
fifoEmpty <= 1'b1;
bufferOutIndex <= 0;
fifoREnDelayed <= 1'b0;
end
else
begin
fifoREnDelayed <= fifoREn;
if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
dataOut <= dataFromMem;
bufferOutIndex <= bufferOutIndex + 1'b1;
end
if (bufferInIndexSyncToRdClk == bufferOutIndex)
fifoEmpty <= 1'b1;
else
fifoEmpty <= 1'b0;
end
end
always @(bufferInIndex or bufferOutIndex) begin
bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
end
dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc (
.addrIn(bufferInIndexToMem),
.addrOut(bufferOutIndexToMem),
.wrClk(wrClk),
.rdClk(rdClk),
.dataIn(dataIn),
.writeEn(fifoWEn),
.readEn(fifoREn),
.dataOut(dataFromMem));
endmodule
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone II" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" port_signa="PORT_UNUSED" port_signb="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEII" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=32 aclr0 clock0 dataa datab result
//VERSION_BEGIN 13.0 cbx_altera_mult_add 2013:06:12:18:03:43:SJ cbx_altera_mult_add_rtl 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_mpt2
(
aclr0,
clock0,
dataa,
datab,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena0(1'b1),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
altera_mult_add_rtl1.addnsub_multiplier_pipeline_register3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.selected_device_family = "Cyclone II",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_pipeline_aclr_a = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_aclr_b = "ACLR0",
altera_mult_add_rtl1.signed_pipeline_register_a = "CLOCK0",
altera_mult_add_rtl1.signed_pipeline_register_b = "CLOCK0",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_mpt2
//VALID FILE
|
`default_netype none
module memory_resource_controller #(
parameter P_MEM_ADDR_N = 22
)(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//IF0
input wire iIF0_ARBIT_REQ,
output wire oIF0_ARBIT_ACK,
input wire iIF0_ARBIT_FINISH,
input wire iIF0_ENA,
output wire oIF0_BUSY,
input wire iIF0_RW,
input wire [P_MEM_ADDR_N-1:0] iIF0_ADDR,
input wire [31:0] iIF0_DATA,
output wire oIF0_VALID,
input wire iIF0_BUSY,
output wire [31:0] oIF0_DATA,
//IF1
input wire iIF1_ARBIT_REQ,
output wire oIF1_ARBIT_ACK,
input wire iIF1_ARBIT_FINISH,
input wire iIF1_ENA,
output wire oIF1_BUSY,
input wire iIF1_RW,
input wire [P_MEM_ADDR_N-1:0] iIF1_ADDR,
input wire [31:0] iIF1_DATA,
output wire oIF1_VALID,
input wire iIF1_BUSY,
output wire [31:0] oIF1_DATA,
//Memory Controller
output wire oMEM_ENA,
input wire iMEM_BUSY,
output wire oMEM_RW,
output wire [P_MEM_ADDR_N-1:0] oMEM_ADDR,
output wire [31:0] oMEM_DATA,
input wire iMEM_VALID,
output wire oMEM_BUSY,
input wire [31:0] iMEM_DATA
);
localparam L_PARAM_STT_IDLE = 2'h0;
localparam L_PARAM_STT_ACK = 2'h1;
localparam L_PARAM_STT_WORK = 2'h2;
reg [1:0] b_state;
reg b_authority;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_STT_IDLE;
end
else begin
case(b_state)
L_PARAM_STT_IDLE:
begin
if(iIF0_ARBIT_REQ || iIF1_ARBIT_REQ)begin
b_state <= L_PARAM_STT_ACK;
end
end
L_PARAM_STT_ACK:
begin
b_state <= L_PARAM_STT_WORK;
end
L_PARAM_STT_WORK:
begin
if(func_if_finish_check(b_authority, iIF0_ARBIT_FINISH, iIF1_ARBIT_FINISH))begin
b_state <= L_PARAM_STT_IDLE;
end
end
default:
begin
b_state <= L_PARAM_STT_IDLE;
end
endcase
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_authority <= 1'b0;
end
else if(iRESET_SYNC)begin
b_authority <= 1'b0;
end
else begin
if(b_state == L_PARAM_STT_IDLE)begin
b_authority <= func_priority_encoder(b_authority, iIF0_ARBIT_REQ, iIF1_ARBIT_REQ);
end
end
end
function func_if_finish_check;
input func_now;
input func_if0_finish;
input func_if1_finish;
begin
if(!func_now && func_if0_finish)begin
func_if_finish_check = 1'b1;
end
else if(func_now && func_if1_finish)begin
func_if_finish_check = 1'b1;
end
else begin
func_if_finish_check = 1'b0;
end
end
endfunction
//Interface
function func_priority_encoder;
input func_now;
input func_if0_req;
input func_if1_req;
begin
case(func_now)
1'b0:
begin
if(func_if1_req)begin
func_priority_encoder = 1'b1;
end
else if(func_if0_req)begin
func_priority_encoder = 1'b0;
end
else begin
func_priority_encoder = 1'b0;
end
end
1'b1:
begin
if(func_if0_req)begin
func_priority_encoder = 1'b0;
end
else if(func_if1_req)begin
func_priority_encoder = 1'b1;
end
else begin
func_priority_encoder = 1'b0;
end
end
endcase
end
endfunction
reg b_if2mem_ena;
reg b_if2mem_rw;
reg [P_MEM_ADDR_N-1:0] b_if2mem_addr;
reg [31:0] b_if2mem_data;
reg b_mem2if0_valid;
reg [31:0] b_mem2if0_data;
reg b_mem2if1_valid;
reg [31:0] b_mem2if1_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_if2mem_ena <= 1'b0;
b_if2mem_rw <= 1'b0;
b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2mem_data <= 32'h0;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
else if(b_state != L_PARAM_STT_WORK || iRESET_SYNC)begin
b_if2mem_ena <= 1'b0;
b_if2mem_rw <= 1'b0;
b_if2mem_addr <= {P_MEM_ADDR_N{1'b0}};
b_if2mem_data <= 32'h0;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
else begin
case(b_authority)
1'b0:
begin
b_if2mem_ena <= iIF0_ENA;
b_if2mem_rw <= iIF0_RW;
b_if2mem_addr <= iIF0_ADDR;
b_if2mem_data <= iIF0_DATA;
b_mem2if0_valid <= iMEM_VALID;
b_mem2if0_data <= iMEM_DATA;
b_mem2if1_valid <= 1'b0;
b_mem2if1_data <= 32'h0;
end
1'b1:
begin
b_if2mem_ena <= iIF1_ENA;
b_if2mem_rw <= iIF1_RW;
b_if2mem_addr <= iIF1_ADDR;
b_if2mem_data <= iIF1_DATA;
b_mem2if0_valid <= 1'b0;
b_mem2if0_data <= 32'h0;
b_mem2if1_valid <= iMEM_VALID;
b_mem2if1_data <= iMEM_DATA;
end
endcase
end
end
assign oIF0_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && !b_authority;
assign oIF1_ARBIT_ACK = (b_state == L_PARAM_STT_ACK) && b_authority;
assign oIF0_VALID = b_mem2if0_valid;
assign oIF0_DATA = b_mem2if0_data;
assign oIF1_VALID = b_mem2if1_valid;
assign oIF1_DATA = b_mem2if1_data;
assign oMEM_ENA = b_if2mem_ena;
assign oMEM_RW = b_if2mem_rw;
assign oMEM_ADDR = b_if2mem_addr;
assign oMEM_DATA = b_if2mem_data;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:33 09/09/2014
// Design Name:
// Module Name: sevensegdecoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sevensegdecoder(
input [3:0] nIn,
output reg [6:0] ssOut
);
always @(nIn)
case (nIn)
4'h0: ssOut = 7'b1000000;
4'h1: ssOut = 7'b1111001;
4'h2: ssOut = 7'b0100100;
4'h3: ssOut = 7'b0110000;
4'h4: ssOut = 7'b0011001;
4'h5: ssOut = 7'b0010010;
4'h6: ssOut = 7'b0000010;
4'h7: ssOut = 7'b1111000;
4'h8: ssOut = 7'b0000000;
4'h9: ssOut = 7'b0011000;
4'hA: ssOut = 7'b0001000;
4'hB: ssOut = 7'b0000011;
4'hC: ssOut = 7'b1000110;
4'hD: ssOut = 7'b0100001;
4'hE: ssOut = 7'b0000110;
4'hF: ssOut = 7'b0001110;
default: ssOut = 7'b1001001;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
/**
* udp_dff$PS_pp$PKG$sN: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B ,
input KAPWR ,
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PKG_SN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVN_SYMBOL_V
`define SKY130_FD_SC_LP__EINVN_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDLCLKP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdlclkp (
GCLK,
GATE,
CLK ,
SCE
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_BLACKBOX_V
|
module RegisterFileTestBench_nogenerate;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] Rd,Mem,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
RegisterFile_nogenerate RF(Rd,Mem,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 0 ; Pcin = 32'bz ; Rd = 32'bz ; Mem = 32'bz ; LOADPC = 0 ; LOAD = 0 ; IR_CU = 0 ; RSLCT = 0 ;
//Clk 1 (Rising Edge)
#1 Pcin = 32'bz ; #1 Rd = 1 ; #1 Mem = 32'bz ; #1 LOADPC = 0 ; #1 LOAD = 1 ; #1 IR_CU = 0 ; #1 RSLCT = 0 ;
//Clk 0 (Falling Edge)
#2 Pcin = 32'bz ; #2 Rd = 1 ; #2 Mem = 32'bz ; #2 LOADPC = 0 ; #2 LOAD = 1 ; #2 IR_CU = 0 ; #2 RSLCT = 0 ;
//Clk 1 (Rising Edge)
#3 Pcin = 32'bz ; #3 Rd = 1 ; #3 Mem = 32'bz ; #3 LOADPC = 0 ; #3 LOAD = 1 ; #3 IR_CU = 0 ; #3 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#4 Pcin = 32'bz ; #4 Rd = 1 ; #4 Mem = 32'bz ; #4 LOADPC = 0 ; #4 LOAD = 1 ; #4 IR_CU = 0 ; #4 RSLCT = 2 ;
//Clk 1 (Rising Edge)
#5 Pcin = 32'bz ; #5 Rd = 1 ; #5 Mem = 32'bz ; #5 LOADPC = 0 ; #5 LOAD = 1 ; #5 IR_CU = 0 ; #5 RSLCT = 2 ;
//Clk 0 (Falling Edge)
#6 Pcin = 32'bz ; #6 Rd = 1 ; #6 Mem = 32'bz ; #6 LOADPC = 0 ; #6 LOAD = 1 ; #6 IR_CU = 0 ; #6 RSLCT = 2 ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench_nogenerate.vcd");
$dumpvars(0,RegisterFileTestBench_nogenerate);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , Rd = %3d , Mem = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, Rd, Mem, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile_nogenerate.v RegisterFileTestBench_nogenerate.v
|
// --------------------------------------------------------------------
// ng_ALU - Arithmetic Logic Unit Module
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_ALU(
input CLK2, // Clock Pulse 2
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Write input bus
output [ 15:0] ALU_OUT // ALU output
);
// --------------------------------------------------------------------
// Control signal definitions
// --------------------------------------------------------------------
wire WB = CP[`CPX(`WB)]; // Write B
wire WX = CP[`CPX(`WX)]; // Write X
wire WY = CP[`CPX(`WY)]; // Write Y
wire WYX = CP[`CPX(`WYX)]; // Write Y (do not reset)
wire CI = CP[`CPX(`CI)]; // Carry in
wire RB = CP[`CPX(`RB)]; // Read B
wire RC = CP[`CPX(`RC)]; // Read C
wire RU = CP[`CPX(`RU)]; // Read SUM
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg [15:0] B; // A Register
reg [15:0] X; // Q Register
reg [15:0] Y; // Z Register
reg C; // C Register
// --------------------------------------------------------------------
// Instantiate Registers: B, X, Y and CI
// --------------------------------------------------------------------
always @(posedge CLK2)
if(!WB) B <= WRITE_BUS; // Load reg B on WB assertion
always @(posedge CLK2)
if(!WY | !WYX) Y <= WRITE_BUS; // Load reg Y on either assertion
always @(posedge CLK2)
if(!WY) X <= 16'h0000; // Clear reg X on WY assertion
else if(!WX) X <= WRITE_BUS; // Load reg X on WX assertion
always @(posedge CLK2)
if(CI & !WY) C <= 1'b0; // Clear CI register
else if(!CI) C <= 1'b1; // Set CI register
// --------------------------------------------------------------------
// 16 bit adder function
//
// 111 1100 0000 0000
// 432 1098 7654 3210
// 111 1111 1111 1111
// --------------------------------------------------------------------
wire C_In = EOC | C; // Carry in is from last time
wire C_Out = SUM[16]; // Carry bit is the 17th bit
wire [16:0] SUM = {1'b0,X} + {1'b0,Y} + {16'h0,C_In}; // B side of ALU
// --------------------------------------------------------------------
// Carry out register
// NOTE: A JK FF instantiated as equivalent D Reg
// always@(negedge CLK) Q <= ~Q & D | Q & D;
// --------------------------------------------------------------------
reg EOC; // Register
reg EOC_Q; // Register
always@(posedge CLK2) EOC_Q <= C_Out;
always@(negedge CLK2) EOC <= EOC_Q;
// --------------------------------------------------------------------
// ALU Function generator:
// A and B are 16 bit inputs. Result in F.
// Slection is as follows:
//
// RB RC RU Func
// 0 0 0 A
// 0 0 1 A
// 0 1 0 A
// 0 1 1 A
// 1 0 0 !A + B
// 1 0 1 !A
// 1 1 0 B
// 1 1 1 Logic 0
// --------------------------------------------------------------------
wire [15:0] A_in = B; // A side of ALU is B reg
wire [15:0] B_in = SUM[15:0]; // B side of ALU is sum
reg [15:0] Func; // Function Output
wire [2:0] sel_cntl = {RB, RC, RU}; // Function selection bits
always @(A_in or B_in or sel_cntl) begin
case(sel_cntl)
3'b000: Func = A_in; // 0 - Identity A, F outputs whatever is on A
3'b001: Func = A_in; // 1 - Identity A
3'b010: Func = A_in; // 2 - Identity A
3'b011: Func = A_in; // 3 - Identity A
3'b100: Func = ~A_in | B_in; // 4 - Compliment A and Add to B, no carry out
3'b101: Func = ~A_in; // 5 - Bitwise complinebt if A
3'b110: Func = B_in; // 6 - Identity B, F outputs whatever is on B
3'b111: Func = 16'h0000; // 7 - Output is zero
endcase
end
assign ALU_OUT = Func; // Make output assignment
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_1.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_1 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_1 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_1 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_1 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_1 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_1
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_1 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_1 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_1 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_1 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_1 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_1 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_1 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_1 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_1 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_1 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_1 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_1
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_1 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_1
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_1
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_1
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_1) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_1_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_1_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_1_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_1",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_1" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_1_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 2000; // 2 ns
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtex8"?"virtex7":(C_FAMILY=="kintex8" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
BLK_MEM_GEN_v8_1_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN (1'b0),
.DBITERR_IN (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN ({C_ADDRB_WIDTH{1'b0}}),
.RDADDRECC ()
);
// Port B
BLK_MEM_GEN_v8_1_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN (sbiterr_in),
.DBITERR_IN (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN (rdaddrecc_in),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_1_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision <= 0;
end
end else begin
is_collision <= 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision <= 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision <= 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a <= 0;
end
end else begin
is_collision_a <= 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a <= collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a <= 0;
end
end else begin
is_collision_delay_a <= 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b <= collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b <= 0;
end
end else begin
is_collision_b <= 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b <= collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b <= 0;
end
end else begin
is_collision_delay_b <= 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_1
#(parameter C_CORENAME = "blk_mem_gen_v8_1",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_1_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_1_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_1_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_1_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_1
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_1
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_1
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_1_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE (C_RST_TYPE),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_1_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// Virtex 6 and Series 7 block RAM mapping.
module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [71:0] A1DATA;
input A1EN;
input [8:0] B1ADDR;
input [71:0] B1DATA;
input [7:0] B1EN;
wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0};
wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0};
wire [7:0] DIP, DOP;
wire [63:0] DI, DO;
assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32],
DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB36E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(72),
.WRITE_WIDTH_B(72),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_36.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[63:32]),
.DOADO(DO[31:0]),
.DOPBDOP(DOP[7:4]),
.DOPADOP(DOP[3:0]),
.DIBDI(DI[63:32]),
.DIADI(DI[31:0]),
.DIPBDIP(DIP[7:4]),
.DIPADIP(DIP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [8:0] A1ADDR;
output [35:0] A1DATA;
input A1EN;
input [8:0] B1ADDR;
input [35:0] B1DATA;
input [3:0] B1EN;
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB18E1 #(
.RAM_MODE("SDP"),
.READ_WIDTH_A(36),
.WRITE_WIDTH_B(36),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_18.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DOBDO(DO[31:16]),
.DOADO(DO[15:0]),
.DOPBDOP(DOP[3:2]),
.DOPADOP(DOP[1:0]),
.DIBDI(DI[31:16]),
.DIADI(DI[15:0]),
.DIPBDIP(DIP[3:2]),
.DIPADIP(DIP[1:0]),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [36863:0] INIT = 36864'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS);
wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS);
wire [7:0] B1EN_8 = B1EN;
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOBDO;
wire [3:0] DOPBDOP;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB36E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_36.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(32'd0),
.DIPADIP(4'd0),
.DOADO(DO[31:0]),
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_8)
);
end else begin
RAMB36E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_32.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(32'd0),
.DIPADIP(4'd0),
.DOADO(DO[31:0]),
.DOPADOP(DOP[3:0]),
.ADDRARDADDR(A1ADDR_16),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(4'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_16),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_8)
);
end endgenerate
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
wire [3:0] B1EN_4 = B1EN;
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB18E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_18.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_4)
);
end else begin
RAMB18E1 #(
.RAM_MODE("TDP"),
.READ_WIDTH_A(CFG_DBITS),
.READ_WIDTH_B(CFG_DBITS),
.WRITE_WIDTH_A(CFG_DBITS),
.WRITE_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.IS_CLKARDCLK_INVERTED(!CLKPOL2),
.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
`include "brams_init_16.vh"
.SIM_DEVICE("7SERIES")
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRARDADDR(A1ADDR_14),
.CLKARDCLK(CLK2),
.ENARDEN(A1EN),
.REGCEAREGCE(|1),
.RSTRAMARSTRAM(|0),
.RSTREGARSTREG(|0),
.WEA(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBWRADDR(B1ADDR_14),
.CLKBWRCLK(CLK3),
.ENBWREN(|1),
.REGCEB(|0),
.RSTRAMB(|0),
.RSTREGB(|0),
.WEBWE(B1EN_4)
);
end endgenerate
endmodule
|
module jfulladdertb;
wire y, carryout;
reg a,b,carryin;
jfulladder jfa(y,carryout,a,b,carryin);
initial
begin
$display("RSLT\tA\tB\tCYIN\t\tCYOUT\tSUM");
a = 0; b = 0; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 0; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 1; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 0; b = 1; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 0; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 0 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 0; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 1; carryin = 0; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 0))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
a = 1; b = 1; carryin = 1; #50; // Set inputs and add delay
if ( (carryout == 1 ) && (y === 1))
$display("PASS\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
else
$display("FAIL\t%d\t%d\t%d\t=\t%d\t%d",a,b,carryin,carryout,y);
end
endmodule
|
module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
// Outputs
.pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
// Inouts
.pin (MD[31]), // Templated
// Inputs
.clk (data_strobeH), // Templated
.pin_out (SDRAM_DQ_out[31]), // Templated
.pin_outen (SDRAM_DQ_outen)); // Templated
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[1]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[2]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
endmodule
|
// bsg_nonsynth_dpi_clock_gen is a drop-in replacement for
// bsg_nonsynth_clock_gen when using verilator, where delay statements
// (e.g. #1) are not valid.
//
// One of the frustrating parts of Verilator is that it "breaks" how
// we normally build testbenches. Our traditional approach is to use
// the bsg_nonsynth_clock_gen module and specify the clock period as a
// parameter. In Verilator, this is not possible because the module
// uses an unsupported delay statement. It's also more challenging
// (though not impossible) to have multiple clock domains.
//
// What I've done is create a drop-in replacement that is backed by a
// C++ API, called bsg_nonsynth_dpi_clock_gen . The user doesn't need
// to know the difference, they just use a different module name with
// the same parameters and include bsg_nonsynth_clock_gen_dpi.hpp
//
// The C++ API is callback based; When each clock-generator module is
// instantiated, it registers itself with the C++ object via an
// imported DPI function -- bsg_nonsynth_clock_gen_register. The
// bsg_timekeeper class tracks the global time (no different than
// normal verilator) and uses a priority queue to track when the next
// clock generator toggles. To advance time, the users calls
// bsg_timekeeper::next()
//
// This drop-in replacement supports multiple clock generators and
// can be embedded anywhere in the hierarchy.
`include "bsg_defines.v"
module bsg_nonsynth_dpi_clock_gen
#(parameter `BSG_INV_PARAM(longint cycle_time_p)
)
(
output bit o
);
int id;
string hierarchy;
import "DPI-C" function int bsg_dpi_clock_gen_register(input longint cycle_time_p, input string hierarchy);
localparam longint cycle_time_lp = {32'b0, cycle_time_p[31:0]};
if(cycle_time_p % 2 != 0)
$fatal(1, "BSG ERROR (%M): cycle_time_p must be divisible by 2");
if(cycle_time_p <= 0)
$fatal(1, "BSG ERROR (%M): cycle_time_p must be greater than 0");
initial begin
$display("BSG INFO: bsg_nonsynth_dpi_clock_gen (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: cycle_time_p = %d", cycle_time_p);
hierarchy = $sformatf("%m");
id = bsg_dpi_clock_gen_register(cycle_time_lp, hierarchy);
end
export "DPI-C" function bsg_dpi_clock_gen_set_level;
function bit bsg_dpi_clock_gen_set_level(bit clkval);
o = clkval;
return o;
endfunction;
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_dpi_clock_gen)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
/**
* clkdlybuf4s25: Clock Delay Buffer 4-stage 0.25um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s25 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__clkdlybuf4s25.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S25_1_V
|
/* Read memory, dump to UART on trigger */
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module top(input clk,
output TXD, // UART TX
input RXD, // UART RX
input resetq
);
localparam MHZ = 12;
// ###### UART ##########################################
//
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data_in;
wire [7:0] uart0_data_out;
wire uart0_wr;
wire uart0_rd;
reg uart0_reset = 1'b0;
buart _uart0 (
.clk(clk),
.resetq(uart0_reset),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(uart0_data_out),
.rx_data(uart0_data_in));
// ###### ROM ##########################################
//
wire [15:0] rom_rd;
wire [7:0] rom_rdb;
wire [8:0] rom_raddr; // 512x8
SB_RAM40_4KNRNW #(
.WRITE_MODE(1), // 8 bit
.READ_MODE(1), // 8 bit
.INIT_0(256'h0000000000400105005501400044504015400014008828bb28a028b028362895),
.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) _rom (
.RDATA(rom_rd),
.RADDR({2'b00, rom_raddr}),
.RCLKN(clk), .RCLKE(1'b1), .RE(1'b1),
.WCLKN(1'b0), .WCLKE(1'b0), .WE(1'b0),
.WADDR(11'h0),
.MASK(16'h0000), .WDATA(16'h0));
assign rom_rdb = {rom_rd[14],rom_rd[12],rom_rd[10],rom_rd[8],rom_rd[6],rom_rd[4],rom_rd[2],rom_rd[0]}; // read byte
// ###### CPU ##########################################
//
// States
localparam S_IDLE =3'b000,
S_OP =3'b001,
S_IMM8 =3'b010,
S_UART_WAIT=3'b011,
S_UART_END =3'b100,
S_MEM_LOAD =3'b101;
reg [8:0] ptr;
wire [8:0] ptr_plus_one = ptr + 9'h1;
assign rom_raddr = ptr;
reg [8:0] ptr_saved;
reg [7:0] outb;
reg outf;
reg [2:0] state;
reg [7:0] opcode;
reg [7:0] cpuregs [3:0];
always @(posedge clk) begin
case (state)
S_IDLE: begin
// "a" to start
if (uart0_valid && uart0_data_in == "a") begin
ptr <= 9'h0;
state <= S_OP;
end
end
S_OP: begin
opcode <= rom_rdb;
ptr <= ptr_plus_one;
casez (rom_rdb)
8'b00000001, // 0x01 JUMP
8'b000001zz, // 0x04-0x07 MOV IMM r0-r3
8'b000100zz: begin // 0x10-0x13 JNZ
state <= S_IMM8;
end
8'b000010zz: begin // 0x08-0x0B SEND r0-r3
state <= S_UART_WAIT;
outb <= cpuregs[rom_rdb[1:0]];
end
// ALU (single reg)
8'b000011zz: begin // 0x0C-0x0F DEC r0-r3
cpuregs[rom_rdb[1:0]] <= cpuregs[rom_rdb[1:0]] - 8'h1;
end
8'b000110zz: begin // 0x18-0x1B INC r0-r3
cpuregs[rom_rdb[1:0]] <= cpuregs[rom_rdb[1:0]] + 8'h1;
end
// ALU (dual reg)
8'b1000zzzz: begin // 0x80-0x8F ADD rx, ry
cpuregs[rom_rdb[3:2]] <= cpuregs[rom_rdb[3:2]] + cpuregs[rom_rdb[1:0]];
end
// Load from memory (page 2)
8'b1100zzzz: begin // 0xC0-0xCF LD rx,[{ry+1,ry}]
state <= S_MEM_LOAD;
ptr_saved <= ptr_plus_one;
//ptr <= {1'b1, cpuregs[{rom_rdb[1],1'b0}]}; // wrong
//ptr <= {1'b1, cpuregs[rom_rdb[1]<<1]}; // wrong
//ptr <= {1'b1, cpuregs[rom_rdb&2'h2]}; // wrong
ptr <= {1'b1, cpuregs[rom_rdb[1:0]]}; // ok
end
default: begin // Invalid instruction, back to IDLE state
state <= S_IDLE;
end
endcase
end
S_IMM8: begin
ptr <= ptr_plus_one;
state <= S_OP;
casez (opcode)
8'b00000001: begin // JUMP
ptr <= rom_rdb;
end
8'b000100zz: begin // 0x10-0x13 JNZ
if (|cpuregs[opcode[1:0]]) begin
ptr <= rom_rdb;
end
end
8'b000001zz: begin // MOV IMM
cpuregs[opcode[1:0]] <= rom_rdb;
end
endcase
end
S_UART_WAIT: begin
if (!uart0_busy) begin // Send byte when UART ready
state <= S_UART_END;
outf <= 1;
end
end
S_UART_END: begin // Clear outf flag after sending to UART
outf <= 0;
state <= S_OP;
end
S_MEM_LOAD: begin // Load from memory
cpuregs[opcode[3:2]] <= rom_rdb;
ptr <= ptr_saved;
state <= S_OP;
end
endcase
// Reset logic
if (!uart0_reset) begin // Reset UART only for one clock
uart0_reset <= 1;
state <= S_IDLE;
end
end
assign uart0_wr = outf;
assign uart0_rd = (state == S_IDLE);
assign uart0_data_out = outb;
endmodule // top
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_nios2_qsys_0_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write_nxt,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
d_write,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output d_write;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 18: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 55: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 18: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write_nxt;
input [ 18: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
reg d_write;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: SoC_nios2_qsys_0_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: SoC_nios2_qsys_0_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: SoC_nios2_qsys_0_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
`include "bsg_nonsynth_dramsim3.svh"
`ifndef dram_pkg
`define dram_pkg bsg_nonsynth_dramsim3_hbm2_8gb_x128_pkg
`endif
module testbench ();
// clock
logic clk;
bsg_nonsynth_clock_gen
#(.cycle_time_p(`dram_pkg::tck_ps))
clkgen
(.o(clk));
// reset
logic reset;
bsg_nonsynth_reset_gen
#(.reset_cycles_lo_p(0)
,.reset_cycles_hi_p(20))
resetgen
(.clk_i(clk)
,.async_reset_o(reset));
// dramsim3
import `dram_pkg::*;
logic [num_channels_p-1:0] dramsim3_v_li;
logic [num_channels_p-1:0] dramsim3_write_not_read_li;
logic [num_channels_p-1:0] [channel_addr_width_p-1:0] dramsim3_ch_addr_li;
logic [num_channels_p-1:0] dramsim3_yumi_lo;
logic [num_channels_p-1:0] dramsim3_data_v_li;
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_li;
logic [num_channels_p-1:0] dramsim3_data_yumi_lo;
logic [num_channels_p-1:0] dramsim3_data_v_lo;
logic [num_channels_p-1:0] [data_width_p-1:0] dramsim3_data_lo;
`dram_pkg::dram_ch_addr_s dramsim3_ch_addr_li_cast;
assign dramsim3_ch_addr_li_cast = dramsim3_ch_addr_li[0];
bsg_nonsynth_dramsim3
#(.channel_addr_width_p(`dram_pkg::channel_addr_width_p)
,.data_width_p(`dram_pkg::data_width_p)
,.num_channels_p(`dram_pkg::num_channels_p)
,.num_columns_p(`dram_pkg::num_columns_p)
,.num_rows_p(`dram_pkg::num_rows_p)
,.num_ba_p(`dram_pkg::num_ba_p)
,.num_bg_p(`dram_pkg::num_bg_p)
,.num_ranks_p(`dram_pkg::num_ranks_p)
,.size_in_bits_p(`dram_pkg::size_in_bits_p)
,.address_mapping_p(`dram_pkg::address_mapping_p)
,.config_p(`dram_pkg::config_p)
,.masked_p(0)
,.trace_file_p(`BSG_STRINGIFY(`trace_file))
,.debug_p(1))
mem
(.clk_i(clk)
,.reset_i(reset)
,.v_i(dramsim3_v_li)
,.write_not_read_i(dramsim3_write_not_read_li)
,.ch_addr_i(dramsim3_ch_addr_li)
,.yumi_o(dramsim3_yumi_lo)
,.data_v_i(dramsim3_data_v_li)
,.data_i(dramsim3_data_li)
,.mask_i('0)
,.data_yumi_o(dramsim3_data_yumi_lo)
,.data_v_o(dramsim3_data_v_lo)
,.data_o(dramsim3_data_lo)
,.read_done_ch_addr_o()
,.write_done_o()
,.write_done_ch_addr_o()
);
// trace replay
//
typedef struct packed {
logic write_not_read;
logic [channel_addr_width_p-1:0] ch_addr;
} dramsim3_trace_s;
localparam ring_width_p = $bits(dramsim3_trace_s);
localparam rom_addr_width_p=20;
dramsim3_trace_s [num_channels_p-1:0] tr_data_lo;
logic [num_channels_p-1:0] tr_v_lo;
logic [num_channels_p-1:0] tr_yumi_li;
logic [num_channels_p-1:0][4+ring_width_p-1:0] rom_data;
logic [num_channels_p-1:0][rom_addr_width_p-1:0] rom_addr;
logic [num_channels_p-1:0] ch_done;
for (genvar i = 0; i < num_channels_p; i++) begin
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
//,.en_i(i == '0)
,.v_i(1'b0)
,.data_i('0)
,.ready_o()
,.v_o(tr_v_lo[i])
,.data_o(tr_data_lo[i])
,.yumi_i(tr_yumi_li[i])
,.rom_addr_o(rom_addr[i])
,.rom_data_i(rom_data[i])
,.done_o(ch_done[i])
,.error_o()
);
bsg_nonsynth_test_rom #(
.data_width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
,.filename_p(`BSG_STRINGIFY(`rom_file))
) rom0 (
.addr_i(rom_addr[i])
,.data_o(rom_data[i])
);
assign dramsim3_write_not_read_li[i] = tr_data_lo[i].write_not_read;
assign dramsim3_ch_addr_li[i] = tr_data_lo[i].ch_addr;
assign dramsim3_v_li[i] = tr_v_lo[i];
assign tr_yumi_li[i] = dramsim3_yumi_lo[i];
end
initial begin
# 10000000 $finish;
end
always_ff @(posedge clk) begin
if (~reset & dramsim3_v_li[0]) begin
if (dramsim3_write_not_read_li[0])
$display("write: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
dramsim3_ch_addr_li[0],
dramsim3_ch_addr_li_cast.ro,
dramsim3_ch_addr_li_cast.ba,
dramsim3_ch_addr_li_cast.bg,
dramsim3_ch_addr_li_cast.co,
dramsim3_ch_addr_li_cast.byte_offset);
else
$display("read: 0x%08x {ro: %d, ba: %d, bg: %d, co: %d, byte: %d}",
dramsim3_ch_addr_li[0],
dramsim3_ch_addr_li_cast.ro,
dramsim3_ch_addr_li_cast.ba,
dramsim3_ch_addr_li_cast.bg,
dramsim3_ch_addr_li_cast.co,
dramsim3_ch_addr_li_cast.byte_offset);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A211OI_BEHAVIORAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_TB_V
`define SKY130_FD_SC_LP__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_TB_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 6
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module XEVIOUS_BROM (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [14 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("XEVIOUS_BROM.mif"),
.C_INIT_FILE("XEVIOUS_BROM.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(32768),
.C_READ_DEPTH_A(32768),
.C_ADDRA_WIDTH(15),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(32768),
.C_READ_DEPTH_B(32768),
.C_ADDRB_WIDTH(15),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("8"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.326399 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(8'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(15'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:27:33 05/29/2015
// Design Name:
// Module Name: shiftRows
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shiftRows(
output [127:0] shftOut, // Data Out
input [127:0] shftIn, // Data In
input inv // If 1, do decryption, else do encryption.
);
// assign shftOut[127:96] = shftIn[127:96];
// assign shftOut[95:64] = (inv)?({shftIn[71:64], shftIn[95:72]}) : ({shftIn[87:64], shftIn[95:88]});
// assign shftOut[63:32] = {shftIn[47:32], shftIn[63:48]};
// assign shftOut[31:0] = (inv)?({shftIn[23:0], shftIn[31:24]}) : ({shftIn[7:0], shftIn[31:8]});
// First Row
assign shftOut[127:120] = shftIn[127:120];
assign shftOut[95:88] = shftIn[95:88];
assign shftOut[63:56] = shftIn[63:56];
assign shftOut[31:24] = shftIn[31:24];
// Second Row
assign shftOut[119:112] = (inv)?(shftIn[23:16]):(shftIn[87:80]);
assign shftOut[87:80] = (inv)?(shftIn[119:112]):(shftIn[55:48]);
assign shftOut[55:48] = (inv)?(shftIn[87:80]):(shftIn[23:16]);
assign shftOut[23:16] = (inv)?(shftIn[55:48]):(shftIn[119:112]);
// Third Row
assign shftOut[111:104] = shftIn[47:40];
assign shftOut[79:72] = shftIn[15:8];
assign shftOut[47:40] = shftIn[111:104];
assign shftOut[15:8] = shftIn[79:72];
// Fourth Row
assign shftOut[103:96] = (inv)?(shftIn[71:64]):(shftIn[7:0]);
assign shftOut[71:64] = (inv)?(shftIn[39:32]):(shftIn[103:96]);
assign shftOut[39:32] = (inv)?(shftIn[7:0]):(shftIn[71:64]);
assign shftOut[7:0] = (inv)?(shftIn[103:96]):(shftIn[39:32]);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9434_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_rst,
adc_data,
adc_or,
adc_status,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
localparam PCORE_DEVICE_7SERIES = 0;
localparam PCORE_DEVICE_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
input adc_rst;
output [47:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
reg [47:0] adc_data = 'd0;
reg adc_or = 'd0;
reg adc_status = 'd0;
// internal clocks and resets
wire adc_clk_in;
// internal signals
wire [11:0] adc_data_ibuf_s;
wire [ 3:0] adc_data_serdes_s[11:0];
wire adc_or_ibuf_s;
wire [ 3:0] adc_or_serdes_s;
wire adc_clk_ibuf_s;
// delay elements are not used
assign delay_ack_t = 1'b0;
assign delay_rdata = 5'd0;
assign delay_locked = 1'b0;
// de-multiplex the adc data
always @(posedge adc_clk) begin
adc_data <= {adc_data_serdes_s[11][3], adc_data_serdes_s[10][3],
adc_data_serdes_s[ 9][3], adc_data_serdes_s[ 8][3],
adc_data_serdes_s[ 7][3], adc_data_serdes_s[ 6][3],
adc_data_serdes_s[ 5][3], adc_data_serdes_s[ 4][3],
adc_data_serdes_s[ 3][3], adc_data_serdes_s[ 2][3],
adc_data_serdes_s[ 1][3], adc_data_serdes_s[ 0][3],
adc_data_serdes_s[11][2], adc_data_serdes_s[10][2],
adc_data_serdes_s[ 9][2], adc_data_serdes_s[ 8][2],
adc_data_serdes_s[ 7][2], adc_data_serdes_s[ 6][2],
adc_data_serdes_s[ 5][2], adc_data_serdes_s[ 4][2],
adc_data_serdes_s[ 3][2], adc_data_serdes_s[ 2][2],
adc_data_serdes_s[ 1][2], adc_data_serdes_s[ 0][2],
adc_data_serdes_s[11][1], adc_data_serdes_s[10][1],
adc_data_serdes_s[ 9][1], adc_data_serdes_s[ 8][1],
adc_data_serdes_s[ 7][1], adc_data_serdes_s[ 6][1],
adc_data_serdes_s[ 5][1], adc_data_serdes_s[ 4][1],
adc_data_serdes_s[ 3][1], adc_data_serdes_s[ 2][1],
adc_data_serdes_s[ 1][1], adc_data_serdes_s[ 0][1],
adc_data_serdes_s[11][0], adc_data_serdes_s[10][0],
adc_data_serdes_s[ 9][0], adc_data_serdes_s[ 8][0],
adc_data_serdes_s[ 7][0], adc_data_serdes_s[ 6][0],
adc_data_serdes_s[ 5][0], adc_data_serdes_s[ 4][0],
adc_data_serdes_s[ 3][0], adc_data_serdes_s[ 2][0],
adc_data_serdes_s[ 1][0], adc_data_serdes_s[ 0][0]};
if (adc_or_serdes_s == 4'd0) begin
adc_or <= 1'b0;
end else begin
adc_or <= 1'b1;
end
adc_status <= 1'b1;
end
// data path - input-buffer - input-serdes (4:1)
genvar l_inst;
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
IBUFDS i_data_ibuf (
.I (adc_data_in_p[l_inst]),
.IB (adc_data_in_n[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
ISERDESE1 #(
.DATA_RATE ("SDR"),
.DATA_WIDTH (4),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"),
.SERDES_MODE ("MASTER"))
i_data_serdes (
.Q1 (adc_data_serdes_s[l_inst][3]),
.Q2 (adc_data_serdes_s[l_inst][2]),
.Q3 (adc_data_serdes_s[l_inst][1]),
.Q4 (adc_data_serdes_s[l_inst][0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (adc_clk_in),
.CLKB (~adc_clk_in),
.CLKDIV (adc_clk),
.D (adc_data_ibuf_s[l_inst]),
.DDLY (1'b0),
.RST (adc_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.O ());
end
endgenerate
// over-range - input-buffer - input-serdes (4:1)
IBUFDS i_or_ibuf (
.I (adc_or_in_p),
.IB (adc_or_in_n),
.O (adc_or_ibuf_s));
ISERDESE1 #(
.DATA_RATE ("SDR"),
.DATA_WIDTH (4),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"),
.SERDES_MODE ("MASTER"))
i_or_serdes (
.Q1 (adc_or_serdes_s[3]),
.Q2 (adc_or_serdes_s[2]),
.Q3 (adc_or_serdes_s[1]),
.Q4 (adc_or_serdes_s[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (adc_clk_in),
.CLKB (~adc_clk_in),
.CLKDIV (adc_clk),
.D (adc_or_ibuf_s),
.DDLY (1'b0),
.RST (adc_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.O ());
// clock - input-buffer ---> bufio & bufr combination (4:1)
IBUFGDS i_clk_ibuf (
.I (adc_clk_in_p),
.IB (adc_clk_in_n),
.O (adc_clk_ibuf_s));
BUFIO i_clk_hs_buf (
.I (adc_clk_ibuf_s),
.O (adc_clk_in));
BUFR #(.BUFR_DIVIDE("4")) i_clk_buf (
.CLR(1'b0),
.CE(1'b1),
.I (adc_clk_ibuf_s),
.O (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// pg_sequencer.v
`timescale 1ns / 1ps
module pg_sequencer
(
input clk,
input sync,
input reset,
input enable,
input start,
output reg running,
output reg [5:0]pgout,
output reg [7:0]ip, // command index pointer
input [15:0]cmd
);
/* command word structure
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
| | pgout | delay |
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*/
wire [5:0]cmd_sig = cmd[13:8];
wire [7:0]cmd_del = cmd[7:0];
wire stop = cmd_del == 0; // stop command
reg [7:0]delay; // delay counter
wire next = delay == 0;
// start/stop
always @(posedge clk or posedge reset)
begin
if (reset) running <= 0;
else if (enable)
begin
if (sync)
begin
if (start) running <= 1;
else if (stop && next) running <= 0;
end
end
else running <= 0;
end
// set index pointer
always @(posedge clk or posedge reset)
begin
if (reset) ip <= 0;
else if (sync)
begin
if (!running) ip <= 0;
else if (next) ip <= ip + 8'd1;
end
end
// command execution
always @(posedge clk or posedge reset)
begin
if (reset)
begin
delay <= 0;
pgout <= 0;
end
else if (sync)
begin
if (!running)
begin
delay <= 0;
pgout <= 0;
end
else if (next)
begin
delay <= cmd_del;
pgout <= cmd_sig;
end
else
begin
delay <= delay - 8'd1;
pgout <= 5'b00000;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:29:56 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_d_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_a_o = ctrl_d_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
NOR3BX1TS U67 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NOR2X1TS U68 ( .A(n16), .B(state_reg[3]), .Y(n51) );
NAND3X1TS U69 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U70 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U71 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND3X1TS U72 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NAND2X1TS U73 ( .A(n43), .B(n27), .Y(load_5_o) );
INVX2TS U74 ( .A(n43), .Y(ctrl_c_o) );
OAI21X1TS U75 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
OAI21X1TS U76 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
INVX2TS U77 ( .A(n28), .Y(ctrl_d_o) );
INVX2TS U78 ( .A(n22), .Y(n10) );
NOR3X1TS U79 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NAND2X1TS U80 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U81 ( .A(n50), .B(n51), .Y(n27) );
NAND2X1TS U82 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND2X1TS U83 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U84 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
INVX2TS U85 ( .A(n40), .Y(load_2_o) );
INVX2TS U86 ( .A(n41), .Y(n4) );
INVX2TS U87 ( .A(n39), .Y(rst_int) );
INVX2TS U88 ( .A(n44), .Y(load_6_o) );
INVX2TS U89 ( .A(n20), .Y(ready) );
INVX2TS U90 ( .A(n32), .Y(n8) );
INVX2TS U91 ( .A(n29), .Y(n7) );
NAND2X1TS U92 ( .A(round_i), .B(n25), .Y(n28) );
NAND4X1TS U93 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
NOR4XLTS U94 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
AOI211X1TS U95 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND3X1TS U96 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
INVX2TS U97 ( .A(norm_iteration_i), .Y(n18) );
NOR2BX1TS U98 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U99 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
OAI2BB1X1TS U100 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U101 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
AOI21X1TS U102 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
OAI22X1TS U103 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U104 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U105 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U106 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35)
);
INVX2TS U107 ( .A(round_i), .Y(n19) );
NAND4X1TS U108 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U109 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U110 ( .A(n31), .Y(n11) );
AOI31X1TS U111 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
NOR3X1TS U112 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AOI2BB1X1TS U113 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
INVX2TS U114 ( .A(n36), .Y(n2) );
NOR2X1TS U115 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NOR2X1TS U116 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U117 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U118 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52) );
NAND3X1TS U119 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U120 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND3X1TS U121 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U122 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U123 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U124 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U125 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U126 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U127 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U128 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
AND2X2TS U129 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
endmodule
|
module node(clk, rst, textfile, keyword, data_wr, key_en);
parameter data_size = 32;
input clk;
input rst;
input [data_size-1:0] textfile; // Input textfile from Scheduler for mapper submodule
input [data_size-1:0] keyword; // Input keyword from Scheduler for mapper submodule
input data_wr; // Informs that whether there are text sent from scheduler now(pulse).
input key_en; // Inform that whether there are keyword sent from scheduler now(keep high).
// Inter-submodule signal
wire [data_size-1:0] pair; // Output (keyword) from mapper to reducer
wire pair_out; // Output keyword notation from mapper to reducer
wire write_in; // Input of reducer pair_out @^#& write_in
// The width of pair_out doesn't meet the requirement of write_in.
// Must do sth to add 1 cycle to the width of pair_out.
reg pair_out_reg;
wire pair_out_ext;
always@(posedge clk or rst)
if(!rst)
pair_out_reg <= 1'b0;
else
pair_out_reg <= pair_out;
assign pair_out_ext = pair_out|pair_out_reg;
assign write_in = pair_out_ext;
wire write_free;
// Instantiation
mapper mapper0(
.clk(clk),
.rst(rst),
.data_in_1(textfile),
.keyword(keyword),
.key_en(key_en),
.data_wr(data_wr),
// Indicates that scheduler can send data to the mapper now.
// Temporarily not connected
.write_free(write_free),
.pair(pair),
.pair_out(pair_out)
);
reducer reducer0(
.clk(clk),
.rst(rst),
.write_in(write_in),
.pair_in(pair),
.result()
);
endmodule
|
//==================================================================================================
// Filename : musoc.v
// Created On : 2015-01-10 21:18:59
// Last Modified : 2015-05-31 21:23:11
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Implementation of the SoC:
// - Core
// - XBAR
// - RAM
// - GPIO
// - UART/Bootloader
//==================================================================================================
module musoc#(
parameter SIM_MODE = "NONE", // Simulation Mode. "SIM" = simulation. "NONE": synthesis mode.
// Core configuration
parameter ENABLE_HW_MULT = 1, // Implement the multiplier
parameter ENABLE_HW_DIV = 1, // Implement the divider
parameter ENABLE_HW_CLO_Z = 1, // Enable CLO/CLZ instructions
// UARTboot
parameter BUS_FREQ = 50, // Bus frequency
// Memory
parameter MEM_ADDR_WIDTH = 12 // 16 KB/4 KW of internal memory
)(
input clk,
input rst,
output halted,
// GPIO
inout [31:0] gpio_a_inout,
// UART
input uart_rx,
output uart_tx
);
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
// master
wire [31:0] master0_address;
wire [3:0] master0_wr;
wire master0_enable;
wire master0_ready;
wire master0_error;
wire [31:0] master1_address;
wire [31:0] master1_data_i;
wire [3:0] master1_wr;
wire master1_enable;
wire master1_ready;
wire master1_error;
wire [31:0] master2_address;
wire [31:0] master2_data_i;
wire [3:0] master2_wr;
wire master2_enable;
wire master2_ready;
wire master2_error; // unused (Bootloader)
wire [31:0] master_data_o;
// slaves
wire [31:0] slave0_data_i;
wire [31:0] slave1_data_i;
wire [31:0] slave2_data_i;
wire slave0_enable;
wire slave1_enable;
wire slave2_enable;
wire slave0_ready;
wire slave1_ready;
wire slave2_ready;
wire [31:0] slave_address;
wire [31:0] slave_data_o;
wire [3:0] slave_wr;
wire [31:0] ms_address;
wire [31:0] ms_data_oi;
wire [31:0] ms_data_io;
wire [3:0] ms_wr;
wire ms_enable;
wire ms_ready;
wire ms_error;
wire [3:0] gpio_interrupt;
wire uart_rx_ready_int;
wire bootloader_reset_core;
wire rst_module;
wire clk_core;
wire clk_bus;
//--------------------------------------------------------------------------
// Clock frequency generator.
//--------------------------------------------------------------------------
clk_generator clock_manager(
.clk_i ( clk ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus )
);
//--------------------------------------------------------------------------
// Reset Manager
// Hold reset for 8 cycles
//--------------------------------------------------------------------------
rst_generator reset_manager(
.clk ( clk_core ),
.rst_i ( rst ),
.rst_o ( rst_module )
);
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
musb_core #(
.ENABLE_HW_MULT ( ENABLE_HW_MULT ),
.ENABLE_HW_DIV ( ENABLE_HW_DIV ),
.ENABLE_HW_CLO_Z ( ENABLE_HW_CLO_Z )
)
musb_core0(/*AUTOINST*/
.halted ( halted ),
.iport_address ( master0_address[31:0] ),
.iport_wr ( master0_wr[3:0] ),
.iport_enable ( master0_enable ),
.dport_address ( master1_address[31:0] ),
.dport_data_o ( master1_data_i[31:0] ),
.dport_wr ( master1_wr[3:0] ),
.dport_enable ( master1_enable ),
.clk ( clk_core ),
.rst_i ( rst_module | bootloader_reset_core ),
.interrupts ( {uart_rx_ready_int, gpio_interrupt[3:0]} ),
.nmi ( 1'b0 ),
.iport_data_i ( master_data_o[31:0] ),
.iport_ready ( master0_ready ),
.iport_error ( master0_error ),
.dport_data_i ( master_data_o[31:0] ),
.dport_ready ( master1_ready ),
.dport_error ( master1_error )
);
//--------------------------------------------------------------------------
// XBAR
//--------------------------------------------------------------------------
arbiter #(
.nmasters(3)
)
arbiter0(/*autoinst*/
.clk ( clk_bus ),
.rst ( rst_module ),
.master_address ( {master2_address[31:0], master1_address[31:0], master0_address[31:0]} ),
.master_data_i ( {master2_data_i[31:0], master1_data_i[31:0], 32'hDEAD_C0DE} ),
.master_wr ( {master2_wr[3:0], master1_wr[3:0], master0_wr[3:0]} ),
.master_enable ( {master2_enable, master1_enable ,master0_enable} ),
.master_data_o ( master_data_o[31:0] ),
.master_ready ( {master2_ready, master1_ready, master0_ready} ),
.master_error ( {master2_error, master1_error, master0_error} ),
.slave_data_i ( ms_data_io[31:0] ),
.slave_ready ( ms_ready ),
.slave_error ( ms_error ),
.slave_address ( ms_address[31:0] ),
.slave_data_o ( ms_data_oi[31:0] ),
.slave_wr ( ms_wr[3:0] ),
.slave_enable ( ms_enable )
);
mux_switch #(
.nslaves (3),
// Slaves
// To generate the mask (easy way): (32'hFFFF_FFFF << N-bits).
// TODO: find a way to get "N-bits" (non-magical way).
// UART GPIO Internal Memory
// 3-bits 5-bits (MEM_ADDR_WIDTH)-bits
.MATCH_ADDR ({32'h1100_0000, 32'h1000_0000, 32'h0000_0000}), // Adjust the mask to avoid address aliasing.
.MATCH_MASK ({32'hFFFF_FFF8, 32'hFFFF_FFE0, 32'hFFFF_0000}) // Adjust the mask to avoid address aliasing.
)
mux_switch0(
.clk ( clk_bus ),
.master_address ( ms_address[31:0] ),
.master_data_i ( ms_data_oi[31:0] ),
.master_wr ( ms_wr[3:0] ),
.master_enable ( ms_enable ),
.master_data_o ( ms_data_io[31:0] ),
.master_ready ( ms_ready ),
.master_error ( ms_error ),
.slave_data_i ( {slave2_data_i[31:0], slave1_data_i[31:0], slave0_data_i[31:0]} ),
.slave_ready ( {slave2_ready, slave1_ready, slave0_ready} ),
.slave_address ( slave_address[31:0] ),
.slave_data_o ( slave_data_o[31:0] ),
.slave_wr ( slave_wr[3:0] ),
.slave_enable ( {slave2_enable, slave1_enable, slave0_enable} )
);
//--------------------------------------------------------------------------
// Internal memory
//--------------------------------------------------------------------------
memory #(
.addr_size( MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst_module ),
.a_addr ( slave_address[2 +: MEM_ADDR_WIDTH] ), // MEM_ADDR_WIDTH bits address.
.a_din ( slave_data_o[31:0] ),
.a_wr ( slave_wr[3:0] ),
.a_enable ( slave0_enable ),
.a_dout ( slave0_data_i[31:0] ),
.a_ready ( slave0_ready ),
.b_addr ( ), // DO NOT CONNECT
.b_din ( ), // DO NOT CONNECT
.b_wr ( ), // DO NOT CONNECT
.b_enable ( ), // DO NOT CONNECT
.b_dout ( ), // DO NOT CONNECT
.b_ready ( ) // DO NOT CONNECT
);
//--------------------------------------------------------------------------
// I/O
//--------------------------------------------------------------------------
gpio gpio0(/*autoinst*/
.gpio_inout ( gpio_a_inout[31:0] ),
.gpio_data_o ( slave1_data_i[31:0] ),
.gpio_ready ( slave1_ready ),
.gpio_interrupt ( gpio_interrupt[3:0] ),
.clk ( clk_bus ),
.rst ( rst_module ),
.gpio_address ( slave_address[4:0] ),
.gpio_data_i ( slave_data_o[31:0] ),
.gpio_wr ( slave_wr[3:0] ),
.gpio_enable ( slave1_enable )
);
uart_bootloader #(
.SIM_MODE ( SIM_MODE ), // Simulation Mode
.BUS_FREQ ( BUS_FREQ ) // Bus frequency
)
uart_bootloader0(
.clk ( clk_bus ),
.rst ( rst_module ),
.uart_address ( slave_address[2:0] ),
.uart_data_i ( slave_data_o[7:0] ),
.uart_wr ( slave_wr[0] ),
.uart_enable ( slave2_enable ),
.uart_data_o ( slave2_data_i[31:0] ),
.uart_ready ( slave2_ready ),
.boot_master_data_i ( master_data_o[31:0] ),
.boot_master_ready ( master2_ready ),
.boot_master_address ( master2_address[31:0] ),
.boot_master_data_o ( master2_data_i[31:0] ),
.boot_master_wr ( master2_wr[3:0] ),
.boot_master_enable ( master2_enable ),
.uart_rx_ready_int ( uart_rx_ready_int ), // unused.
.uart_rx_full_int ( ), // unused.
.bootloader_reset_core ( bootloader_reset_core ),
.uart_rx ( uart_rx ),
.uart_tx ( uart_tx )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_FUNCTIONAL_PP_V
|
`include "../CPU/cpu.v"
module cpu_test;
reg clk;
reg [31:0] addr;
wire [31:0] alu_output, data;
wire [31:0] pc_4;
cpu c(.clk(clk), .alu_output(alu_output), .data(data), .nxt_pc(pc_4));
reg [31:0] regVal;
integer i;
always #1 clk = ~clk;
initial begin
$dumpfile("cpu.vcd");
$dumpvars(0, cpu_test);
clk = 0;
// for(i = 0; i < 223; i = i + 1) begin
// #2; $display("pc_4 = %h, data = %h", pc_4, data);
// if($isunknown(data)) begin
// break;
// end
//end
i = 0;
while (i < 233) begin
#2 ;//$display("pc_4 = %h, data = %b", pc_4, data);
i = i + 1;
end
//for(i = 0; i < 32; i = i + 1) begin
// regVal = c.rf.regs[i];
// #2 $display("pc_4 = %h, data = %h, $s%d = %h", pc_4, data, i,regVal);
//end
//#2; $display("Final value of PC = %h", pc_4 );
#2; $display("$0 = %h", c.rf.regs[0 ] );
#2; $display("$at = %h", c.rf.regs[1 ] );
#2; $display("$v0 = %h", c.rf.regs[2 ] );
#2; $display("$v1 = %h", c.rf.regs[3 ] );
#2; $display("$a0 = %h", c.rf.regs[4 ] );
#2; $display("$a1 = %h", c.rf.regs[5 ] );
#2; $display("$a2 = %h", c.rf.regs[6 ] );
#2; $display("$a3 = %h", c.rf.regs[7 ] );
#2; $display("$t0 = %h", c.rf.regs[8 ] );
#2; $display("$t1 = %h", c.rf.regs[9 ] );
#2; $display("$t2 = %h", c.rf.regs[10] );
#2; $display("$t3 = %h", c.rf.regs[11] );
#2; $display("$t4 = %h", c.rf.regs[12] );
#2; $display("$t5 = %h", c.rf.regs[13] );
#2; $display("$t6 = %h", c.rf.regs[14] );
#2; $display("$t7 = %h", c.rf.regs[15] );
#2; $display("$s0 = %h", c.rf.regs[16] );
#2; $display("$s1 = %h", c.rf.regs[17] );
#2; $display("$s2 = %h", c.rf.regs[18] );
#2; $display("$s3 = %h", c.rf.regs[19] );
#2; $display("$s4 = %h", c.rf.regs[20] );
#2; $display("$s5 = %h", c.rf.regs[21] );
#2; $display("$s6 = %h", c.rf.regs[22] );
#2; $display("$s7 = %h", c.rf.regs[23] );
#2; $display("$t8 = %h", c.rf.regs[24] );
#2; $display("$t9 = %h", c.rf.regs[25] );
#2; $display("$k0 = %h", c.rf.regs[26] );
#2; $display("$k1 = %h", c.rf.regs[27] );
#2; $display("$gp = %h", c.rf.regs[28] );
#2; $display("$sp = %h", c.rf.regs[29] );
#2; $display("$fp = %h", c.rf.regs[30] );
#2; $display("$ra = %h", c.rf.regs[31] );
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:58:06 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20,
n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360;
NAND2X1TS U41 ( .A(n228), .B(n227), .Y(n229) );
NAND2X1TS U42 ( .A(n240), .B(n239), .Y(n241) );
NOR2X1TS U43 ( .A(n53), .B(n51), .Y(n320) );
NAND2XLTS U44 ( .A(n73), .B(n299), .Y(n300) );
NAND2X1TS U45 ( .A(n64), .B(n216), .Y(n211) );
NAND2XLTS U46 ( .A(n67), .B(n292), .Y(n293) );
NAND2XLTS U47 ( .A(n220), .B(n219), .Y(n221) );
NAND2X1TS U48 ( .A(n256), .B(n255), .Y(n257) );
NAND2X1TS U49 ( .A(n263), .B(n262), .Y(n264) );
NAND2X1TS U50 ( .A(n270), .B(n269), .Y(n271) );
NAND2XLTS U51 ( .A(n285), .B(n284), .Y(n287) );
NAND2XLTS U52 ( .A(n274), .B(n273), .Y(n275) );
NAND2XLTS U53 ( .A(n280), .B(n279), .Y(n281) );
NAND2X1TS U54 ( .A(n66), .B(n235), .Y(n236) );
CLKMX2X2TS U55 ( .A(in2[31]), .B(n209), .S0(add_sub), .Y(n210) );
INVX2TS U56 ( .A(n21), .Y(n327) );
NAND2X6TS U57 ( .A(n72), .B(n220), .Y(n206) );
NOR2X1TS U58 ( .A(n207), .B(in2[30]), .Y(n208) );
OR2X6TS U59 ( .A(n203), .B(in1[30]), .Y(n72) );
INVX2TS U60 ( .A(n235), .Y(n193) );
NOR2X2TS U61 ( .A(n283), .B(n278), .Y(n152) );
NAND2X2TS U62 ( .A(n231), .B(n66), .Y(n225) );
MX2X2TS U63 ( .A(in2[29]), .B(n201), .S0(add_sub), .Y(n202) );
MX2X2TS U64 ( .A(in2[28]), .B(n190), .S0(add_sub), .Y(n194) );
NAND2X2TS U65 ( .A(n18), .B(in1[26]), .Y(n239) );
NAND2X2TS U66 ( .A(n170), .B(in1[22]), .Y(n269) );
NAND2X2TS U67 ( .A(n150), .B(in1[20]), .Y(n279) );
OR2X4TS U68 ( .A(n192), .B(in1[27]), .Y(n66) );
NOR2X2TS U69 ( .A(n169), .B(in1[21]), .Y(n266) );
NAND2X2TS U70 ( .A(n171), .B(in1[23]), .Y(n262) );
NOR2X4TS U71 ( .A(n243), .B(n238), .Y(n231) );
NAND2X1TS U72 ( .A(n131), .B(in1[16]), .Y(n295) );
MX2X2TS U73 ( .A(in2[23]), .B(n154), .S0(n182), .Y(n171) );
OR2X4TS U74 ( .A(n138), .B(in1[18]), .Y(n70) );
OR2X4TS U75 ( .A(n137), .B(in1[17]), .Y(n67) );
NAND2X2TS U76 ( .A(n138), .B(in1[18]), .Y(n289) );
XNOR2X1TS U77 ( .A(n143), .B(in2[19]), .Y(n144) );
XOR2X2TS U78 ( .A(n161), .B(in2[22]), .Y(n162) );
NAND2X4TS U79 ( .A(n302), .B(n303), .Y(n37) );
OR2X2TS U80 ( .A(n188), .B(in2[27]), .Y(n197) );
NOR2X2TS U81 ( .A(n164), .B(in2[20]), .Y(n165) );
NOR2X2TS U82 ( .A(n142), .B(in2[18]), .Y(n143) );
CLKMX2X4TS U83 ( .A(in2[15]), .B(n124), .S0(n166), .Y(n125) );
NAND2X1TS U84 ( .A(n185), .B(n184), .Y(n188) );
NOR2X6TS U85 ( .A(n120), .B(in1[14]), .Y(n302) );
NOR2X4TS U86 ( .A(n198), .B(in2[24]), .Y(n177) );
NAND2X2TS U87 ( .A(n115), .B(in1[12]), .Y(n313) );
INVX2TS U88 ( .A(in2[26]), .Y(n184) );
NOR2X2TS U89 ( .A(n134), .B(in2[16]), .Y(n135) );
NOR2X2TS U90 ( .A(in2[25]), .B(in2[24]), .Y(n185) );
INVX2TS U91 ( .A(n157), .Y(n134) );
BUFX16TS U92 ( .A(n128), .Y(n157) );
OR2X6TS U93 ( .A(in1[9]), .B(n100), .Y(n49) );
NAND2X2TS U94 ( .A(n65), .B(n114), .Y(n111) );
OR2X4TS U95 ( .A(n98), .B(in1[8]), .Y(n68) );
OR2X2TS U96 ( .A(in2[21]), .B(in2[20]), .Y(n160) );
NAND2X6TS U97 ( .A(n100), .B(in1[9]), .Y(n326) );
NOR2X1TS U98 ( .A(in2[19]), .B(in2[18]), .Y(n145) );
NOR2X2TS U99 ( .A(in2[17]), .B(in2[16]), .Y(n146) );
NOR2X4TS U100 ( .A(n110), .B(n10), .Y(n106) );
NOR2X2TS U101 ( .A(in2[13]), .B(in2[12]), .Y(n122) );
AND2X6TS U102 ( .A(n45), .B(n44), .Y(n344) );
CLKINVX2TS U103 ( .A(n348), .Y(n79) );
INVX2TS U104 ( .A(in2[8]), .Y(n102) );
OR2X2TS U105 ( .A(in2[10]), .B(n9), .Y(n10) );
AND2X6TS U106 ( .A(n41), .B(n19), .Y(n11) );
INVX3TS U107 ( .A(n45), .Y(n43) );
CLKINVX6TS U108 ( .A(n9), .Y(n19) );
INVX2TS U109 ( .A(add_sub), .Y(n75) );
INVX12TS U110 ( .A(in2[4]), .Y(n23) );
NOR2X4TS U111 ( .A(in2[2]), .B(in2[1]), .Y(n87) );
AOI21X2TS U112 ( .A0(n88), .A1(n87), .B0(n75), .Y(n89) );
CLKINVX6TS U113 ( .A(in2[10]), .Y(n40) );
OAI21X2TS U114 ( .A0(n284), .A1(n278), .B0(n279), .Y(n151) );
INVX12TS U115 ( .A(in2[1]), .Y(n33) );
NAND2X6TS U116 ( .A(n69), .B(n29), .Y(n28) );
MXI2X2TS U117 ( .A(n130), .B(n129), .S0(n182), .Y(n131) );
NOR2X4TS U118 ( .A(n150), .B(in1[20]), .Y(n278) );
NOR2X4TS U119 ( .A(n171), .B(in1[23]), .Y(n261) );
NOR2X2TS U120 ( .A(n307), .B(n312), .Y(n118) );
INVX6TS U121 ( .A(n166), .Y(n85) );
OAI21XLTS U122 ( .A0(n327), .A1(n325), .B0(n326), .Y(n322) );
NAND2X1TS U123 ( .A(n70), .B(n289), .Y(n290) );
AND2X4TS U124 ( .A(n37), .B(n73), .Y(n7) );
NAND2X2TS U125 ( .A(n98), .B(in1[8]), .Y(n329) );
NAND2X2TS U126 ( .A(n104), .B(in1[10]), .Y(n323) );
NAND2X8TS U127 ( .A(n301), .B(n303), .Y(n38) );
NAND2X4TS U128 ( .A(n194), .B(in1[28]), .Y(n227) );
OR2X4TS U129 ( .A(n131), .B(in1[16]), .Y(n71) );
INVX4TS U130 ( .A(n11), .Y(n105) );
INVX2TS U131 ( .A(in1[5]), .Y(n44) );
BUFX12TS U132 ( .A(add_sub), .Y(n182) );
INVX2TS U133 ( .A(in2[7]), .Y(n82) );
INVX2TS U134 ( .A(in2[18]), .Y(n133) );
NAND2X4TS U135 ( .A(n39), .B(n233), .Y(n237) );
INVX2TS U136 ( .A(n268), .Y(n270) );
INVX2TS U137 ( .A(n261), .Y(n263) );
NAND2X4TS U138 ( .A(n191), .B(in1[25]), .Y(n244) );
NAND2X4TS U139 ( .A(n149), .B(in1[19]), .Y(n284) );
NOR2X4TS U140 ( .A(n191), .B(in1[25]), .Y(n243) );
NOR2X4TS U141 ( .A(n149), .B(in1[19]), .Y(n283) );
INVX4TS U142 ( .A(n289), .Y(n139) );
NAND2X4TS U143 ( .A(n116), .B(in1[13]), .Y(n308) );
NAND2X4TS U144 ( .A(n43), .B(in1[5]), .Y(n345) );
NOR4X2TS U145 ( .A(n155), .B(n160), .C(in2[23]), .D(in2[22]), .Y(n156) );
NAND2X2TS U146 ( .A(n146), .B(n145), .Y(n155) );
NOR2X4TS U147 ( .A(n57), .B(n54), .Y(n218) );
INVX6TS U148 ( .A(n249), .Y(n276) );
XOR2X1TS U149 ( .A(n291), .B(n290), .Y(res[18]) );
NAND2X4TS U150 ( .A(n56), .B(n196), .Y(n55) );
INVX4TS U151 ( .A(n196), .Y(n8) );
NAND2X2TS U152 ( .A(n210), .B(in1[31]), .Y(n216) );
OAI21X1TS U153 ( .A0(n316), .A1(n312), .B0(n313), .Y(n311) );
XOR2X1TS U154 ( .A(n321), .B(n320), .Y(res[11]) );
XOR2X1TS U155 ( .A(n316), .B(n315), .Y(res[12]) );
INVX4TS U156 ( .A(n292), .Y(n288) );
XOR2X1TS U157 ( .A(n328), .B(n327), .Y(res[9]) );
NAND2X4TS U158 ( .A(n169), .B(in1[21]), .Y(n273) );
MX2X4TS U159 ( .A(in2[19]), .B(n144), .S0(n182), .Y(n149) );
XOR2X2TS U160 ( .A(n165), .B(in2[21]), .Y(n168) );
XNOR2X2TS U161 ( .A(n135), .B(in2[17]), .Y(n136) );
OR2X6TS U162 ( .A(n125), .B(in1[15]), .Y(n73) );
NAND2X4TS U163 ( .A(n125), .B(in1[15]), .Y(n299) );
INVX4TS U164 ( .A(n317), .Y(n319) );
NAND2X6TS U165 ( .A(n120), .B(in1[14]), .Y(n303) );
INVX6TS U166 ( .A(n326), .Y(n29) );
XOR2XLTS U167 ( .A(n343), .B(n342), .Y(res[6]) );
XOR2X1TS U168 ( .A(n339), .B(n338), .Y(res[7]) );
NOR2X6TS U169 ( .A(n108), .B(in1[11]), .Y(n317) );
OAI21XLTS U170 ( .A0(n354), .A1(n75), .B0(n353), .Y(res[3]) );
OAI21XLTS U171 ( .A0(n357), .A1(n85), .B0(n356), .Y(res[4]) );
OAI21XLTS U172 ( .A0(n350), .A1(n75), .B0(n349), .Y(res[2]) );
OAI21XLTS U173 ( .A0(n360), .A1(n85), .B0(n359), .Y(res[1]) );
OR2X1TS U174 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
AND2X2TS U175 ( .A(in2[4]), .B(add_sub), .Y(n17) );
OA21X2TS U176 ( .A0(add_sub), .A1(in2[4]), .B0(in1[4]), .Y(n77) );
INVX2TS U177 ( .A(n232), .Y(n233) );
NOR2X8TS U178 ( .A(n116), .B(in1[13]), .Y(n307) );
NAND3X6TS U179 ( .A(n77), .B(n76), .C(n46), .Y(n45) );
INVX4TS U180 ( .A(n212), .Y(n220) );
AND2X6TS U181 ( .A(n358), .B(n33), .Y(n12) );
OAI21X2TS U182 ( .A0(n262), .A1(n254), .B0(n255), .Y(n173) );
NOR2X4TS U183 ( .A(n172), .B(in1[24]), .Y(n254) );
XNOR2X2TS U184 ( .A(n215), .B(n214), .Y(res[30]) );
NAND3X8TS U185 ( .A(n30), .B(n27), .C(n318), .Y(n306) );
NAND2X8TS U186 ( .A(n52), .B(n31), .Y(n30) );
MXI2X8TS U187 ( .A(n184), .B(n183), .S0(n182), .Y(n18) );
XNOR2X1TS U188 ( .A(n142), .B(in2[18]), .Y(n132) );
NAND2X4TS U189 ( .A(n157), .B(n146), .Y(n142) );
XOR2X2TS U190 ( .A(n65), .B(in2[12]), .Y(n113) );
NOR2X4TS U191 ( .A(n115), .B(in1[12]), .Y(n312) );
NOR2X4TS U192 ( .A(n202), .B(in1[29]), .Y(n212) );
XNOR2X2TS U193 ( .A(n200), .B(in2[29]), .Y(n201) );
NOR3X6TS U194 ( .A(n198), .B(in2[28]), .C(n197), .Y(n200) );
XNOR2X1TS U195 ( .A(n222), .B(n221), .Y(res[29]) );
NAND2X4TS U196 ( .A(n137), .B(in1[17]), .Y(n292) );
XOR2X4TS U197 ( .A(n207), .B(in2[30]), .Y(n199) );
NAND2X6TS U198 ( .A(n24), .B(n23), .Y(n95) );
NOR2X4TS U199 ( .A(n32), .B(n317), .Y(n31) );
NAND2X6TS U200 ( .A(n61), .B(n59), .Y(n217) );
AO21X2TS U201 ( .A0(n72), .A1(n205), .B0(n204), .Y(n14) );
AND3X8TS U202 ( .A(n36), .B(n295), .C(n35), .Y(n13) );
NAND2X8TS U203 ( .A(n53), .B(n319), .Y(n27) );
MXI2X4TS U204 ( .A(n40), .B(n103), .S0(n182), .Y(n104) );
NAND2X8TS U205 ( .A(n223), .B(n62), .Y(n61) );
OR2X4TS U206 ( .A(n210), .B(in1[31]), .Y(n64) );
NAND2BX4TS U207 ( .AN(in2[29]), .B(n200), .Y(n207) );
XNOR2X2TS U208 ( .A(n217), .B(n211), .Y(res[31]) );
OAI21X4TS U209 ( .A0(n307), .A1(n313), .B0(n308), .Y(n117) );
MXI2X4TS U210 ( .A(n114), .B(n113), .S0(n166), .Y(n115) );
NOR2X4TS U211 ( .A(n206), .B(n8), .Y(n62) );
AOI21X4TS U212 ( .A0(n306), .A1(n118), .B0(n117), .Y(n301) );
NAND2X6TS U213 ( .A(n49), .B(n69), .Y(n32) );
NAND2X2TS U214 ( .A(n71), .B(n126), .Y(n35) );
NAND2X4TS U215 ( .A(n70), .B(n67), .Y(n141) );
NAND2X4TS U216 ( .A(n174), .B(n260), .Y(n176) );
NAND2X2TS U217 ( .A(n85), .B(in2[7]), .Y(n84) );
MXI2X4TS U218 ( .A(n101), .B(n99), .S0(n166), .Y(n100) );
INVX2TS U219 ( .A(in2[9]), .Y(n101) );
MX2X4TS U220 ( .A(in2[13]), .B(n112), .S0(n182), .Y(n116) );
INVX2TS U221 ( .A(in2[16]), .Y(n130) );
MX2X4TS U222 ( .A(in2[17]), .B(n136), .S0(n182), .Y(n137) );
INVX2TS U223 ( .A(n332), .Y(n341) );
INVX2TS U224 ( .A(n333), .Y(n334) );
NAND2X4TS U225 ( .A(n92), .B(in1[7]), .Y(n336) );
INVX2TS U226 ( .A(n69), .Y(n48) );
CLKBUFX2TS U227 ( .A(n52), .Y(n21) );
INVX2TS U228 ( .A(n306), .Y(n316) );
NOR2X4TS U229 ( .A(n170), .B(in1[22]), .Y(n268) );
NAND2X6TS U230 ( .A(n202), .B(in1[29]), .Y(n219) );
INVX2TS U231 ( .A(n12), .Y(n47) );
CLKINVX6TS U232 ( .A(in2[5]), .Y(n24) );
NOR2X4TS U233 ( .A(in2[5]), .B(in2[6]), .Y(n80) );
INVX2TS U234 ( .A(in2[12]), .Y(n114) );
NAND2BX2TS U235 ( .AN(n109), .B(n19), .Y(n26) );
NOR2X4TS U236 ( .A(n261), .B(n254), .Y(n174) );
NOR2X4TS U237 ( .A(in2[3]), .B(in2[4]), .Y(n81) );
XNOR2X1TS U238 ( .A(n198), .B(in2[24]), .Y(n158) );
INVX2TS U239 ( .A(n176), .Y(n56) );
NOR2X4TS U240 ( .A(n225), .B(n226), .Y(n196) );
INVX2TS U241 ( .A(n195), .Y(n58) );
INVX2TS U242 ( .A(n219), .Y(n205) );
INVX2TS U243 ( .A(n213), .Y(n204) );
INVX2TS U244 ( .A(n266), .Y(n274) );
INVX2TS U245 ( .A(n273), .Y(n267) );
NOR2X4TS U246 ( .A(n268), .B(n266), .Y(n260) );
OAI21X1TS U247 ( .A0(n251), .A1(n261), .B0(n262), .Y(n252) );
NOR2X1TS U248 ( .A(n250), .B(n261), .Y(n253) );
INVX2TS U249 ( .A(n260), .Y(n250) );
NAND2X2TS U250 ( .A(n172), .B(in1[24]), .Y(n255) );
CLKBUFX2TS U251 ( .A(n248), .Y(n249) );
NAND2X2TS U252 ( .A(n192), .B(in1[27]), .Y(n235) );
INVX2TS U253 ( .A(n231), .Y(n234) );
AOI21X1TS U254 ( .A0(n195), .A1(n60), .B0(n14), .Y(n59) );
INVX2TS U255 ( .A(n206), .Y(n60) );
NAND2X1TS U256 ( .A(n346), .B(n345), .Y(n347) );
NAND2X1TS U257 ( .A(n341), .B(n333), .Y(n342) );
INVX2TS U258 ( .A(n340), .Y(n343) );
NAND2X1TS U259 ( .A(n337), .B(n336), .Y(n338) );
INVX2TS U260 ( .A(n335), .Y(n337) );
NAND2X1TS U261 ( .A(n68), .B(n329), .Y(n330) );
NAND2X1TS U262 ( .A(n49), .B(n326), .Y(n328) );
NAND2X1TS U263 ( .A(n69), .B(n323), .Y(n324) );
NAND2X1TS U264 ( .A(n319), .B(n318), .Y(n321) );
NOR3X1TS U265 ( .A(n327), .B(n325), .C(n48), .Y(n51) );
NAND2X1TS U266 ( .A(n314), .B(n313), .Y(n315) );
INVX2TS U267 ( .A(n312), .Y(n314) );
NAND2X1TS U268 ( .A(n309), .B(n308), .Y(n310) );
INVX2TS U269 ( .A(n307), .Y(n309) );
NAND2X1TS U270 ( .A(n304), .B(n303), .Y(n305) );
INVX2TS U271 ( .A(n302), .Y(n304) );
NAND2X1TS U272 ( .A(n34), .B(n299), .Y(n297) );
NAND2X1TS U273 ( .A(n71), .B(n295), .Y(n296) );
NAND2X1TS U274 ( .A(n38), .B(n7), .Y(n34) );
XOR2X1TS U275 ( .A(n287), .B(n286), .Y(res[19]) );
INVX2TS U276 ( .A(n283), .Y(n285) );
XNOR2X1TS U277 ( .A(n282), .B(n281), .Y(res[20]) );
OAI21X2TS U278 ( .A0(n286), .A1(n283), .B0(n284), .Y(n282) );
XNOR2X1TS U279 ( .A(n276), .B(n275), .Y(res[21]) );
XOR2X1TS U280 ( .A(n247), .B(n246), .Y(res[25]) );
NAND2X1TS U281 ( .A(n245), .B(n244), .Y(n246) );
INVX2TS U282 ( .A(n243), .Y(n245) );
INVX2TS U283 ( .A(n238), .Y(n240) );
INVX2TS U284 ( .A(n226), .Y(n228) );
NAND2X1TS U285 ( .A(n72), .B(n213), .Y(n214) );
NAND2X2TS U286 ( .A(n63), .B(n216), .Y(res[32]) );
NAND2X4TS U287 ( .A(n217), .B(n64), .Y(n63) );
NAND2BX2TS U288 ( .AN(in2[11]), .B(n40), .Y(n109) );
CLKINVX6TS U289 ( .A(n198), .Y(n180) );
NAND2X8TS U290 ( .A(n157), .B(n156), .Y(n198) );
CLKINVX1TS U291 ( .A(n13), .Y(n294) );
CLKINVX1TS U292 ( .A(n277), .Y(n286) );
XNOR2X1TS U293 ( .A(n294), .B(n293), .Y(res[17]) );
AOI21X1TS U294 ( .A0(n294), .A1(n67), .B0(n288), .Y(n291) );
NAND2X2TS U295 ( .A(n108), .B(in1[11]), .Y(n318) );
XOR2X2TS U296 ( .A(n110), .B(n102), .Y(n97) );
NOR2X4TS U297 ( .A(n110), .B(in2[8]), .Y(n22) );
AND2X8TS U298 ( .A(n358), .B(n33), .Y(n20) );
OR2X4TS U299 ( .A(in2[8]), .B(in2[9]), .Y(n9) );
CLKINVX12TS U300 ( .A(n95), .Y(n42) );
NOR2X8TS U301 ( .A(n92), .B(in1[7]), .Y(n335) );
OA21X4TS U302 ( .A0(n335), .A1(n333), .B0(n336), .Y(n16) );
INVX16TS U303 ( .A(in2[0]), .Y(n358) );
NAND2X4TS U304 ( .A(n91), .B(in1[6]), .Y(n333) );
BUFX12TS U305 ( .A(add_sub), .Y(n166) );
NOR2X4TS U306 ( .A(n335), .B(n332), .Y(n90) );
INVX8TS U307 ( .A(n15), .Y(n223) );
OR2X4TS U308 ( .A(n234), .B(n15), .Y(n39) );
OA21X4TS U309 ( .A0(n248), .A1(n176), .B0(n175), .Y(n15) );
OAI21XLTS U310 ( .A0(n301), .A1(n302), .B0(n303), .Y(n298) );
INVX2TS U311 ( .A(n299), .Y(n126) );
INVX2TS U312 ( .A(n49), .Y(n325) );
OAI21X4TS U313 ( .A0(n238), .A1(n244), .B0(n239), .Y(n232) );
XOR2X4TS U314 ( .A(n22), .B(in2[9]), .Y(n99) );
NOR2X8TS U315 ( .A(n25), .B(n355), .Y(n41) );
NAND2X8TS U316 ( .A(n42), .B(n96), .Y(n25) );
NOR2X8TS U317 ( .A(n110), .B(n26), .Y(n65) );
OAI21X4TS U318 ( .A0(n268), .A1(n273), .B0(n269), .Y(n259) );
NAND2X8TS U319 ( .A(n323), .B(n28), .Y(n53) );
NAND3X8TS U320 ( .A(n71), .B(n38), .C(n7), .Y(n36) );
INVX12TS U321 ( .A(n223), .Y(n247) );
INVX12TS U322 ( .A(n41), .Y(n110) );
XOR2X4TS U323 ( .A(n105), .B(n40), .Y(n103) );
NAND2X8TS U324 ( .A(n20), .B(n94), .Y(n355) );
XOR2X4TS U325 ( .A(n111), .B(in2[13]), .Y(n112) );
MXI2X4TS U326 ( .A(n121), .B(n119), .S0(n166), .Y(n120) );
XNOR2X4TS U327 ( .A(n181), .B(in2[26]), .Y(n183) );
OAI21X4TS U328 ( .A0(n218), .A1(n212), .B0(n219), .Y(n215) );
NAND2BX4TS U329 ( .AN(n155), .B(n157), .Y(n164) );
MXI2X4TS U330 ( .A(n148), .B(n147), .S0(n166), .Y(n150) );
OAI21X4TS U331 ( .A0(n79), .A1(n344), .B0(n345), .Y(n340) );
OAI21X4TS U332 ( .A0(n78), .A1(n47), .B0(n17), .Y(n46) );
NAND2X8TS U333 ( .A(n50), .B(n329), .Y(n52) );
NAND2X8TS U334 ( .A(n331), .B(n68), .Y(n50) );
NOR2X4TS U335 ( .A(n248), .B(n55), .Y(n54) );
OAI21X4TS U336 ( .A0(n175), .A1(n8), .B0(n58), .Y(n57) );
XOR2X2TS U337 ( .A(n265), .B(n264), .Y(res[23]) );
XOR2X2TS U338 ( .A(n258), .B(n257), .Y(res[24]) );
XOR2X2TS U339 ( .A(n272), .B(n271), .Y(res[22]) );
XNOR2X1TS U340 ( .A(n331), .B(n330), .Y(res[8]) );
XNOR2X1TS U341 ( .A(n297), .B(n296), .Y(res[16]) );
NOR2X8TS U342 ( .A(in2[3]), .B(in2[2]), .Y(n94) );
XOR2X4TS U343 ( .A(n74), .B(in2[5]), .Y(n348) );
NAND2X6TS U344 ( .A(n340), .B(n90), .Y(n93) );
AOI21X1TS U345 ( .A0(n341), .A1(n340), .B0(n334), .Y(n339) );
OR2X8TS U346 ( .A(n104), .B(in1[10]), .Y(n69) );
NOR2X4TS U347 ( .A(in2[7]), .B(in2[6]), .Y(n96) );
NOR2X2TS U348 ( .A(n164), .B(n160), .Y(n161) );
NOR2X4TS U349 ( .A(n91), .B(in1[6]), .Y(n332) );
MX2X4TS U350 ( .A(in2[11]), .B(n107), .S0(n182), .Y(n108) );
INVX2TS U351 ( .A(n259), .Y(n251) );
INVX2TS U352 ( .A(n344), .Y(n346) );
INVX2TS U353 ( .A(in2[2]), .Y(n351) );
AOI31X2TS U354 ( .A0(n12), .A1(n81), .A2(n351), .B0(n75), .Y(n74) );
INVX2TS U355 ( .A(n94), .Y(n78) );
NAND3X2TS U356 ( .A(n94), .B(n12), .C(n23), .Y(n76) );
NAND4X2TS U357 ( .A(n81), .B(n87), .C(n358), .D(n80), .Y(n83) );
XOR2X4TS U358 ( .A(n83), .B(n82), .Y(n86) );
OAI21X4TS U359 ( .A0(n86), .A1(n85), .B0(n84), .Y(n92) );
NOR3X4TS U360 ( .A(n95), .B(in2[3]), .C(in2[0]), .Y(n88) );
XOR2X4TS U361 ( .A(n89), .B(in2[6]), .Y(n91) );
NAND2X8TS U362 ( .A(n93), .B(n16), .Y(n331) );
MXI2X4TS U363 ( .A(n102), .B(n97), .S0(n166), .Y(n98) );
XNOR2X4TS U364 ( .A(n106), .B(in2[11]), .Y(n107) );
INVX2TS U365 ( .A(in2[14]), .Y(n121) );
NAND2X8TS U366 ( .A(n65), .B(n122), .Y(n127) );
XNOR2X1TS U367 ( .A(in2[14]), .B(n127), .Y(n119) );
NAND3X1TS U368 ( .A(n65), .B(n122), .C(n121), .Y(n123) );
XOR2X1TS U369 ( .A(n123), .B(in2[15]), .Y(n124) );
NOR3X8TS U370 ( .A(n127), .B(in2[15]), .C(in2[14]), .Y(n128) );
XOR2X4TS U371 ( .A(n157), .B(in2[16]), .Y(n129) );
MXI2X4TS U372 ( .A(n133), .B(n132), .S0(n182), .Y(n138) );
AOI21X4TS U373 ( .A0(n288), .A1(n70), .B0(n139), .Y(n140) );
OAI21X4TS U374 ( .A0(n13), .A1(n141), .B0(n140), .Y(n277) );
INVX2TS U375 ( .A(in2[20]), .Y(n148) );
XNOR2X1TS U376 ( .A(n164), .B(in2[20]), .Y(n147) );
AOI21X4TS U377 ( .A0(n277), .A1(n152), .B0(n151), .Y(n248) );
NOR3X4TS U378 ( .A(n164), .B(in2[22]), .C(n160), .Y(n153) );
XNOR2X2TS U379 ( .A(n153), .B(in2[23]), .Y(n154) );
INVX2TS U380 ( .A(in2[24]), .Y(n159) );
MXI2X2TS U381 ( .A(n159), .B(n158), .S0(n166), .Y(n172) );
INVX2TS U382 ( .A(in2[22]), .Y(n163) );
MXI2X4TS U383 ( .A(n163), .B(n162), .S0(n182), .Y(n170) );
INVX2TS U384 ( .A(in2[21]), .Y(n167) );
MXI2X4TS U385 ( .A(n168), .B(n167), .S0(n85), .Y(n169) );
AOI21X4TS U386 ( .A0(n259), .A1(n174), .B0(n173), .Y(n175) );
XOR2X4TS U387 ( .A(n177), .B(in2[25]), .Y(n179) );
INVX2TS U388 ( .A(in2[25]), .Y(n178) );
MXI2X4TS U389 ( .A(n179), .B(n178), .S0(n85), .Y(n191) );
NAND2X4TS U390 ( .A(n180), .B(n185), .Y(n181) );
NOR2X8TS U391 ( .A(n18), .B(in1[26]), .Y(n238) );
NOR2X4TS U392 ( .A(n198), .B(n188), .Y(n186) );
XNOR2X4TS U393 ( .A(n186), .B(in2[27]), .Y(n187) );
MX2X4TS U394 ( .A(in2[27]), .B(n187), .S0(add_sub), .Y(n192) );
NOR2X1TS U395 ( .A(n198), .B(n197), .Y(n189) );
XNOR2X1TS U396 ( .A(n189), .B(in2[28]), .Y(n190) );
NOR2X8TS U397 ( .A(n194), .B(in1[28]), .Y(n226) );
AOI21X4TS U398 ( .A0(n66), .A1(n232), .B0(n193), .Y(n224) );
OAI21X4TS U399 ( .A0(n224), .A1(n226), .B0(n227), .Y(n195) );
MX2X4TS U400 ( .A(in2[30]), .B(n199), .S0(add_sub), .Y(n203) );
NAND2X4TS U401 ( .A(n203), .B(in1[30]), .Y(n213) );
XNOR2X1TS U402 ( .A(n208), .B(in2[31]), .Y(n209) );
INVX2TS U403 ( .A(n218), .Y(n222) );
OAI21X4TS U404 ( .A0(n247), .A1(n225), .B0(n224), .Y(n230) );
XNOR2X4TS U405 ( .A(n230), .B(n229), .Y(res[28]) );
XNOR2X2TS U406 ( .A(n237), .B(n236), .Y(res[27]) );
OAI21X4TS U407 ( .A0(n247), .A1(n243), .B0(n244), .Y(n242) );
XNOR2X4TS U408 ( .A(n242), .B(n241), .Y(res[26]) );
AOI21X4TS U409 ( .A0(n276), .A1(n253), .B0(n252), .Y(n258) );
INVX2TS U410 ( .A(n254), .Y(n256) );
AOI21X4TS U411 ( .A0(n276), .A1(n260), .B0(n259), .Y(n265) );
AOI21X4TS U412 ( .A0(n276), .A1(n274), .B0(n267), .Y(n272) );
INVX2TS U413 ( .A(n278), .Y(n280) );
XNOR2X1TS U414 ( .A(n298), .B(n300), .Y(res[15]) );
XOR2XLTS U415 ( .A(n301), .B(n305), .Y(res[14]) );
XNOR2X1TS U416 ( .A(n311), .B(n310), .Y(res[13]) );
XNOR2X1TS U417 ( .A(n322), .B(n324), .Y(res[10]) );
XNOR2X1TS U418 ( .A(n348), .B(n347), .Y(res[5]) );
XNOR2X1TS U419 ( .A(n12), .B(n351), .Y(n350) );
AOI21X1TS U420 ( .A0(n85), .A1(in2[2]), .B0(in1[2]), .Y(n349) );
NAND2X1TS U421 ( .A(n12), .B(n351), .Y(n352) );
XNOR2X1TS U422 ( .A(n352), .B(in2[3]), .Y(n354) );
AOI21X1TS U423 ( .A0(n85), .A1(in2[3]), .B0(in1[3]), .Y(n353) );
XNOR2X1TS U424 ( .A(in2[4]), .B(n355), .Y(n357) );
AOI21X1TS U425 ( .A0(n85), .A1(in2[4]), .B0(in1[4]), .Y(n356) );
XOR2X1TS U426 ( .A(n358), .B(in2[1]), .Y(n360) );
AOI21X1TS U427 ( .A0(n85), .A1(in2[1]), .B0(in1[1]), .Y(n359) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL5_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_4_V
`define SKY130_FD_SC_HD__O2111AI_4_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o2111ai_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_4_V
|
`include "../module/controller.v"
// Controller testbench: Supplies test vectors and dumps the results to file and
// standard output. Do not modify!
module controller_tb;
reg ph1, ph2, reset;
reg [5:0] opcode;
reg zero;
wire memread;
wire memwrite;
wire [3:0] irwrite;
wire pcen;
wire regwrite;
wire [1:0] aluop;
wire alusrca;
wire [1:0] alusrcb;
wire [1:0] pcsource;
wire iord;
wire memtoreg;
wire regdst;
wire pcwritecond;
wire pcwrite;
// instatiate device under test and connect the signals
controller U0(
// inputs
.ph1 (ph1),
.ph2 (ph2),
.reset (reset),
.op5 (opcode[5]), .op4 (opcode[4]), .op3 (opcode[3]),
.op2 (opcode[2]), .op1 (opcode[1]), .op0 (opcode[0]),
.zero (zero),
// ouputs
.memread (memread),
.memwrite (memwrite),
.irwrite3 (irwrite[3]), .irwrite2 (irwrite[2]),
.irwrite1 (irwrite[1]), .irwrite0 (irwrite[0]),
.pcen (pcen),
.regwrite (regwrite),
.aluop1 (aluop[1]), .aluop0 (aluop[0]),
.alusrca (alusrca),
.alusrcb1 (alusrcb[1]), .alusrcb0 (alusrcb[0]),
.pcsource1 (pcsource[1]), .pcsource0 (pcsource[0]),
.iord (iord),
.memtoreg (memtoreg),
.regdst (regdst));
// initialization (reset is high)
initial
begin
ph1 <= 0;
ph2 <= 0;
reset <= 1;
zero = 0;
end
// generate a two-phase non-overlapping clock (period is 8 units)
always begin
#2 ph1 = 1;
#2 ph1 = 0;
#4 ph1 = 0;
end
always begin
#6 ph2 = 1;
#2 ph2 = 0;
end
// dump all the signals info file. use with a waveform viewer to see the signals
initial begin
$dumpfile("controller.vcd");
$dumpvars;
end
initial begin
// bring out of reset and supply the first opcode lb
#2 reset = 0; opcode = 6'b100000;
$display("%s %s %s %s %s %s %s %s %s %s %s %s", "memread", "alusrca", "iord", "irwrite",
"alusrcb", "aluop", "pcen", "pcsource", "regdst", "regwrite",
"memtoreg", "memwrite");
$display("opcode = %b", opcode);
// sb
#72 opcode = 6'b101000;
$display("opcode = %b", opcode);
// r-type instructions
#56 opcode = 6'b000000;
$display("opcode = %b", opcode);
// beq
#56 opcode = 6'b000100;
$display("opcode = %b", opcode);
#40 zero = 1'b1; // check that zero works in BEQEX
// jump
#8 opcode = 6'b000010;
$display("opcode = %b", opcode);
// addi
#48 opcode = 6'b001000;
$display("opcode = %b", opcode);
// terminate simulation
#56 $finish;
end
// print the values of all relevant signals every clock period
always
#8 $display("%5b %6b %6b %6b %7b %5b %4b %8b %7b %6b %8b %7b", memread, alusrca, iord, irwrite, alusrcb, aluop,
pcen, pcsource, regdst, regwrite, memtoreg, memwrite);
endmodule
|
`timescale 1ns/1ns
module usb_tx_sie
(input c,
input c_48,
input rst,
input [7:0] d,
input dv,
output done,
output oe_n,
inout vp,
inout vm);
wire txf_q, txf_read, txf_empty;
usb_tx_fifo usb_tx_fifo_inst
(.c(c), .c_48(c_48),
.d(d), .dv(dv), // at 125 mhz
.q(txf_q), .read(txf_read),
.empty(txf_empty)); // at 48 mhz
/////////////////////////////////////////////////////////////////////////
// everything below here is in the 48 MHz clock domain
wire stuff_q, stuff_q_empty; // bit-stuffed output data and output data-valid
wire stuff_q_req; // read request from bit-stuffed data stream
usb_tx_stuff usb_tx_stuff_inst
(.c(c_48), .d(txf_q), .d_empty(txf_empty), .d_req(txf_read),
.q(stuff_q), .q_req(stuff_q_req), .q_empty(stuff_q_empty));
localparam ST_IDLE = 4'd0;
localparam ST_OE = 4'd1;
localparam ST_DATA_BIT = 4'd2;
localparam ST_LAST_BIT = 4'd3;
localparam ST_EOP_SE0_0 = 4'd4;
localparam ST_EOP_SE0_1 = 4'd5;
localparam ST_EOP_J = 4'd6;
localparam ST_IPG = 4'd7; // let's do inter-packet gap of 6 bit times
localparam ST_DONE = 4'd8;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(rst), .en(1'b1), .d(next_state), .q(state));
wire [2:0] ones_count;
wire ones_count_rst, ones_count_en;
r #(3) ones_count_r
(.c(c_48), .rst(ones_count_rst), .en(ones_count_en),
.d(ones_count + 1'b1), .q(ones_count));
wire [1:0] bit_timer;
r #(2) bit_timer_r
(.c(c_48), .rst(1'b0), .en(1'b1), .d(bit_timer+1'b1), .q(bit_timer));
wire advance = bit_timer == 2'b00;
//wire t1 = bit_timer == 2'b01;
assign stuff_q_req = ctrl[0];
// inter-packet gap timer
wire ipg_cnt_rst;
wire [4:0] ipg_cnt;
r #(5) ipg_cnt_r
(.c(c_48), .rst(ipg_cnt_rst), .en(1'b1), .d(ipg_cnt+1'b1), .q(ipg_cnt));
always @* begin
case (state)
ST_IDLE:
if (~stuff_q_empty) ctrl = { ST_OE , 5'b11110 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_OE:
if (advance /*& ipg_cnt > 5'd20*/) ctrl = { ST_DATA_BIT , 5'b01110 };
else ctrl = { ST_OE , 5'b01110 };
ST_DATA_BIT:
if (advance & stuff_q_empty) ctrl = { ST_EOP_SE0_0, 5'b00010 };
else if (advance) ctrl = { ST_DATA_BIT , 5'b00011 };
else ctrl = { ST_DATA_BIT , 5'b00010 };
/*
ST_LAST_BIT:
if (advance) ctrl = { ST_EOP_SE0_0, 5'b00010 };
else ctrl = { ST_LAST_BIT , 5'b00010 };
*/
ST_EOP_SE0_0:
if (advance) ctrl = { ST_EOP_SE0_1, 5'b00110 };
else ctrl = { ST_EOP_SE0_0, 5'b00110 };
ST_EOP_SE0_1:
if (advance) ctrl = { ST_EOP_J , 5'b10110 };
else ctrl = { ST_EOP_SE0_1, 5'b00110 };
ST_EOP_J:
if (advance /*& ipg_cnt > 5'd20*/) ctrl = { ST_IPG , 5'b11110 };
else ctrl = { ST_EOP_J , 5'b01110 };
ST_IPG:
if (ipg_cnt == 5'd3) ctrl = { ST_DONE , 5'b00000 };
else ctrl = { ST_IPG , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
wire bit_hardcoded_en = ctrl[2];
wire bit_hardcoded_vp = ctrl[3];
wire bit_hardcoded_vm = 1'b0;
assign ipg_cnt_rst = ctrl[4];
wire oe_n_i = ~(ctrl[1] | rst);
d1 oe_d1_r(.c(c_48), .d(oe_n_i), .q(oe_n));
wire vp_out = rst ? 1'b0 : (bit_hardcoded_en ? bit_hardcoded_vp : stuff_q);
wire vm_out = rst ? 1'b0 : (bit_hardcoded_en ? bit_hardcoded_vm : ~stuff_q);
wire vp_out_d1, vm_out_d1;
d1 vp_out_d1_r(.c(c_48), .d(vp_out), .q(vp_out_d1));
d1 vm_out_d1_r(.c(c_48), .d(vm_out), .q(vm_out_d1));
assign vp = ~oe_n ? vp_out_d1 : 1'bz;
assign vm = ~oe_n ? vm_out_d1 : 1'bz;
wire done_c48 = state == ST_DONE;
sync done_s(.in(done_c48), .clk(c), .out(done));
endmodule
|
(** * RecordSub: Subtyping with Records *)
Require Export MoreStlc.
(* ###################################################### *)
(** * Core Definitions *)
(* ################################### *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
(* ################################### *)
(** *** Well-Formedness *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' => if eq_id_dec i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' => if eq_id_dec i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ###################################################################### *)
(** * Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(* ################################### *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we
sketched in the motivating discussion, but we need to add
well-formedness side conditions to some of the rules. *)
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
well_formed_ty S ->
subtype S TTop
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (TArrow S1 S2) (TArrow T1 T2)
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
subtype (TRCons i T1 T2) TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
subtype S1 T1 ->
subtype Sr2 Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
subtype (TRCons i S1 Sr2) (TRCons i T1 Tr2)
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
subtype (TRCons i1 T1 (TRCons i2 T2 Tr3))
(TRCons i2 T2 (TRCons i1 T1 Tr3)).
Hint Constructors subtype.
(* ############################################### *)
(** ** Subtyping Examples and Exercises *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 2 stars *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
End Examples.
(* ###################################################################### *)
(** ** Properties of Subtyping *)
(** *** Well-Formedness *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
induction Hsub;
intros; try (destruct IHHsub1; destruct IHHsub2)...
- (* S_RcdPerm *)
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
induction T; intros; try solve by inversion.
- (* TRCons *)
inversion H. subst. unfold Tlookup in H0.
destruct (eq_id_dec i i0)... inversion H0; subst... Qed.
(** *** Field Lookup *)
(** Our record matching lemmas get a little more complicated in
the presence of subtyping for two reasons: First, record
types no longer necessarily describe the exact structure of
corresponding terms. Second, reasoning by induction on
[has_type] derivations becomes harder in general, because
[has_type] is no longer syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
induction Hsub; intros Ti Hget;
try solve by inversion.
- (* S_Refl *)
exists Ti...
- (* S_Trans *)
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
- (* S_RcdDepth *)
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i k)...
+ (* i = k -- we're looking up the first field *)
inversion Hget. subst. exists S1...
- (* S_RcdPerm *)
exists Ti. split.
+ (* lookup *)
unfold Tlookup. unfold Tlookup in Hget.
destruct (eq_id_dec i i1)...
* (* i = i1 -- we're looking up the first field *)
destruct (eq_id_dec i i2)...
(* i = i2 -- contradictory *)
destruct H0.
subst...
+ (* subtype *)
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Typing *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
| T_Proj : forall Gamma i t T Ti,
has_type Gamma t T ->
Tlookup i T = Some Ti ->
has_type Gamma (tproj t i) Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T
(* Rules for record terms *)
| T_RNil : forall Gamma,
has_type Gamma trnil TRNil
| T_RCons : forall Gamma i t T tr Tr,
has_type Gamma t T ->
has_type Gamma tr Tr ->
record_ty Tr ->
record_tm tr ->
has_type Gamma (trcons i t tr) (TRCons i T Tr)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ############################################### *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star *)
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j) {k=(\z:A.z), j=(\z:B.z)} : B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
induction Htyp...
- (* T_App *)
inversion IHHtyp1...
- (* T_Proj *)
eapply wf_rcd_lookup...
- (* T_Sub *)
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
induction Htyp; intros; subst; try solve by inversion.
- (* T_Sub *)
apply (rcd_types_match S) in H0... destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
- (* T_RCons *)
simpl in H0. simpl. simpl in H1.
destruct (eq_id_dec i i0).
+ (* i is first *)
inversion H1. subst. exists t...
+ (* i in tail *)
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ########################################## *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_Proj *)
right. destruct IHHt...
+ (* rcd is value *)
destruct (lookup_field_in_value t T i Ti) as [t' [Hget Ht']]...
+ (* rcd_steps *)
destruct H0 as [t' Hstp]. exists (tproj t' i)...
- (* T_RCons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
+ (* head steps *)
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** Informal proof of progress:
Theorem : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
Proof : Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the typing derivation. Cases [T_Abs] and
[T_RNil] are immediate because abstractions and [{}] are always
values. Case [T_Var] is vacuous because variables cannot be
typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and
[empty |- t2 : T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[t1 t2 ==> t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then
[t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for some
[x], [S1], and [s2]. And [(\x:S1.s2) t2 ==> [x:=t2]s2] by
[ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing subderivation gives us that either [tr]
is a value or it steps. If [tr ==> tr'] for some term [tr'],
then [tr.i ==> tr'.i] by rule [ST_Proj1].
Otherwise, [tr] is a value. In this case, lemma
[lookup_field_in_value] yields that there is a term [ti] such
that [tlookup i tr = Some ti]. It follows that [tr.i ==> ti]
by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then
[{i=t1, tr} ==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then
[{i=t1, tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail],
since [t1] is a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ########################################## *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Abs *)
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Proj *)
assert (well_formed_ty Ti) as Hwf.
{ (* pf of assertion *)
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H... }
exists T. exists Ti...
- (* T_Sub *)
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
induction Hty;
inversion Heqt; subst...
- (* T_Sub *)
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
- (* T_RCons *)
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
{ (* pf of assertion *)
apply has_type__wf in Hty1.
apply has_type__wf in Hty2... }
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. destruct (eq_id_dec x x0)...
- (* T_App *)
apply T_App with T1...
- (* T_RCons *)
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold extend in Hctx. rewrite neq_id in Hctx... Qed.
(* ########################################## *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold extend in Hctx.
destruct (eq_id_dec x y)...
+ (* x=y *)
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
destruct (subtype__wf _ _ Hsub)...
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt) as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (eq_id_dec x y).
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
- (* tproj *)
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
- (* trnil *)
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
- (* trcons *)
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
+ (* record_ty Tr *)
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
+ (* record_tm ([x:=v]t2) *)
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
- (* T_Proj *)
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
- (* T_RCons *)
eauto using step_preserves_record_tm. Qed.
(** Informal proof of [preservation]:
Theorem: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
Proof: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and {} don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(* ###################################################### *)
(** ** Exercises on Typing *)
(** **** Exercise: 2 stars, optional (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with records and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
- Suppose we add the following reduction rule:
------------------ (ST_Funny21)
{} ==> (\x:Top. x)
- Suppose we add the following subtyping rule:
-------------- (S_Funny3)
{} <: Top->Top
- Suppose we add the following subtyping rule:
-------------- (S_Funny4)
Top->Top <: {}
- Suppose we add the following evaluation rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
- Suppose we add the same evaluation rule *and* a new typing rule:
----------------- (ST_Funny5)
({} t) ==> (t {})
---------------------- (T_Funny6)
empty |- {} : Top->Top
- Suppose we *change* the arrow subtyping rule to:
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
(** [] *)
*)
(** $Date$ *)
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//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_auto_us_df_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_7_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(1),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// encodes a one hot signal into an address
// 0001 --> 0, v=1
// 0010 --> 1, v=1
// 0100 --> 2, v=1
// 1000 --> 3, v=1
// 0000 --> 0, v=0
// O*1O*1O* --> undefined
`include "bsg_defines.v"
// we implement at this as a parallel prefix computation
// it is basically a big, clever tree of OR's with a
// certain structure (see sample debug output).
module bsg_encode_one_hot #(parameter width_p=8, parameter lo_to_hi_p=1, parameter debug_p=0)
(input [width_p-1:0] i
,output [`BSG_SAFE_CLOG2(width_p)-1:0] addr_o
,output v_o // whether any bits are set
);
localparam levels_lp = $clog2(width_p);
// adjust for non-power of two input
localparam aligned_width_lp = 1 << $clog2(width_p);
genvar level;
genvar segment;
wire [levels_lp:0][aligned_width_lp-1:0] addr;
wire [levels_lp:0][aligned_width_lp-1:0] v;
// base case, also handle padding for non-power of two inputs
assign v [0] = lo_to_hi_p ? ((aligned_width_lp) ' (i)) : i << (aligned_width_lp - width_p);
assign addr[0] = (width_p == 1) ? '0 : `BSG_UNDEFINED_IN_SIM('0);
for (level = 1; level < levels_lp+1; level=level+1)
begin : rof
localparam segments_lp = 2**(levels_lp-level);
localparam segment_slot_lp = aligned_width_lp/segments_lp;
localparam segment_width_lp = level; // how many bits are needed at each level
for (segment = 0; segment < segments_lp; segment=segment+1)
begin : rof1
wire [1:0] vs = {
v[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)]
, v[level-1][segment*segment_slot_lp]
};
assign v[level][segment*segment_slot_lp] = | vs;
if (level == 1)
assign addr[level][(segment*segment_slot_lp)+:segment_width_lp] = { vs[lo_to_hi_p] };
else
begin : fi
assign addr[level][(segment*segment_slot_lp)+:segment_width_lp]
= { vs[lo_to_hi_p]
, addr[level-1][segment*segment_slot_lp+:segment_width_lp-1]
| addr[level-1][segment*segment_slot_lp+(segment_slot_lp >> 1)+:segment_width_lp-1]
};
end
end
end
assign v_o = v[levels_lp][0];
// BSG_SAFE_CLOG2 handles width_p = 1 case
`ifdef SYNTHESIS
assign addr_o = addr[levels_lp][`BSG_SAFE_CLOG2(width_p)-1:0];
`else
assign addr_o = (((i-1) & i) == '0)
? addr[levels_lp][`BSG_SAFE_CLOG2(width_p)-1:0]
: { `BSG_SAFE_CLOG2(width_p){1'bx}};
// generates debug output that looks like this:
// (addr) (v)
// xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 00000000000000000000000000000100
// z0z0z0z0z0z0z0z0z0z0z0z0z0z0z0z0 z0z0z0z0z0z0z0z0z0z0z0z0z0z0z1z0
// zz00zz00zz00zz00zz00zz00zz00zz10 zzz0zzz0zzz0zzz0zzz0zzz0zzz0zzz1
// zzzzz000zzzzz000zzzzz000zzzzz010 zzzzzzz0zzzzzzz0zzzzzzz0zzzzzzz1
// zzzzzzzzzzzz0000zzzzzzzzzzzz0010 zzzzzzzzzzzzzzz0zzzzzzzzzzzzzzz1
// zzzzzzzzzzzzzzzzzzzzzzzzzzz00010 zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz1
// addr_o=00010 v_o=1
if (debug_p)
always @(addr_o or v_o)
begin
`BSG_HIDE_FROM_VERILATOR(#1)
for (integer k = 0; k <= $clog2(width_p); k=k+1)
$display("%b %b",addr[k], v[k]);
$display("addr_o=%b v_o=%b", addr_o, v_o);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_PP_SYMBOL_V
|
/*
-- ============================================================================
-- FILE NAME : id_stage.v
-- DESCRIPTION : ID¥¹¥Æ©`¥¸
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module id_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] gpr_rd_data_0, // Õi¤ß³ö¤·¥Ç©`¥¿ 0
input wire [`WordDataBus] gpr_rd_data_1, // Õi¤ß³ö¤·¥Ç©`¥¿ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
output wire [`RegAddrBus] gpr_rd_addr_1, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`WordDataBus] ex_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
input wire [`RegAddrBus] ex_dst_addr, // ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire ex_gpr_we_, // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
input wire [`WordDataBus] mem_fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`CpuExeModeBus] exe_mode, // gÐÐ¥â©`¥É
input wire [`WordDataBus] creg_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`RegAddrBus] creg_rd_addr, // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
output wire [`WordAddrBus] br_addr, // ·Ö᪥¢¥É¥ì¥¹
output wire br_taken, // ·Ö᪤γÉÁ¢
output wire ld_hazard, // ¥í©`¥É¥Ï¥¶©`¥É
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] if_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire [`WordDataBus] if_insn, // ÃüÁî
input wire if_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] id_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
output wire id_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output wire [`AluOpBus] id_alu_op, // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] id_alu_in_0, // ALUÈëÁ¦ 0
output wire [`WordDataBus] id_alu_in_1, // ALUÈëÁ¦ 1
output wire id_br_flag, // ·Ö᪥ե饰
output wire [`MemOpBus] id_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`WordDataBus] id_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
output wire [`CtrlOpBus] id_ctrl_op, // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`RegAddrBus] id_dst_addr, // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
output wire id_gpr_we_, // GPRø¤Þz¤ßÓп
output wire [`IsaExpBus] id_exp_code // ÀýÍ⥳©`¥É
);
/********** ¥Ç¥³©`¥ÉÐźŠ**********/
wire [`AluOpBus] alu_op; // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] alu_in_0; // ALUÈëÁ¦ 0
wire [`WordDataBus] alu_in_1; // ALUÈëÁ¦ 1
wire br_flag; // ·Ö᪥ե饰
wire [`MemOpBus] mem_op; // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`WordDataBus] mem_wr_data; // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
wire [`CtrlOpBus] ctrl_op; // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
wire [`RegAddrBus] dst_addr; // GPRø¤Þz¤ß¥¢¥É¥ì¥¹
wire gpr_we_; // GPRø¤Þz¤ßÓп
wire [`IsaExpBus] exp_code; // ÀýÍ⥳©`¥É
/********** ¥Ç¥³©`¥À **********/
decoder decoder (
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_insn (if_insn), // ÃüÁî
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** GPR¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.gpr_rd_data_0 (gpr_rd_data_0), // Õi¤ß³ö¤·¥Ç©`¥¿ 0
.gpr_rd_data_1 (gpr_rd_data_1), // Õi¤ß³ö¤·¥Ç©`¥¿ 1
.gpr_rd_addr_0 (gpr_rd_addr_0), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 0
.gpr_rd_addr_1 (gpr_rd_addr_1), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹ 1
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
// ID¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_dst_addr (id_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // ø¤Þz¤ßÓп
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
// EX¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_fwd_data (ex_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
.ex_dst_addr (ex_dst_addr), // ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // ø¤Þz¤ßÓп
// MEM¥¹¥Æ©`¥¸¤«¤é¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥°
.mem_fwd_data (mem_fwd_data), // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** ÖÆÓù¥ì¥¸¥¹¥¿¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.exe_mode (exe_mode), // gÐÐ¥â©`¥É
.creg_rd_data (creg_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.creg_rd_addr (creg_rd_addr), // Õi¤ß³ö¤·¥¢¥É¥ì¥¹
/********** ¥Ç¥³©`¥ÉÐźŠ**********/
.alu_op (alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.alu_in_0 (alu_in_0), // ALUÈëÁ¦ 0
.alu_in_1 (alu_in_1), // ALUÈëÁ¦ 1
.br_addr (br_addr), // ·Ö᪥¢¥É¥ì¥¹
.br_taken (br_taken), // ·Ö᪤γÉÁ¢
.br_flag (br_flag), // ·Ö᪥ե饰
.mem_op (mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_wr_data (mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ctrl_op (ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.dst_addr (dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.gpr_we_ (gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.exp_code (exp_code), // ÀýÍ⥳©`¥É
.ld_hazard (ld_hazard) // ¥í©`¥É¥Ï¥¶©`¥É
);
/********** ¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
id_reg id_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ç¥³©`¥É½Y¹û **********/
.alu_op (alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.alu_in_0 (alu_in_0), // ALUÈëÁ¦ 0
.alu_in_1 (alu_in_1), // ALUÈëÁ¦ 1
.br_flag (br_flag), // ·Ö᪥ե饰
.mem_op (mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_wr_data (mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ctrl_op (ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.dst_addr (dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.gpr_we_ (gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.exp_code (exp_code), // ÀýÍ⥳©`¥É
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
/********** IF/ID¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.if_pc (if_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.if_en (if_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
/********** ID/EX¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.id_pc (id_pc), // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
.id_en (id_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.id_alu_op (id_alu_op), // ALU¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_alu_in_0 (id_alu_in_0), // ALUÈëÁ¦ 0
.id_alu_in_1 (id_alu_in_1), // ALUÈëÁ¦ 1
.id_br_flag (id_br_flag), // ·Ö᪥ե饰
.id_mem_op (id_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_mem_wr_data (id_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.id_ctrl_op (id_ctrl_op), // ÖÆÓù¥ª¥Ú¥ì©`¥·¥ç¥ó
.id_dst_addr (id_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.id_gpr_we_ (id_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.id_exp_code (id_exp_code) // ÀýÍ⥳©`¥É
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:19 02/21/2016
// Design Name: parityChecker
// Module Name: F:/VLSI Lab/parityChecker/parityCheckerTest.v
// Project Name: parityChecker
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: parityChecker
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module parityCheckerTest;
// Inputs
reg [3:0] data;
reg parity;
// Outputs
wire parity_result;
// Instantiate the Unit Under Test (UUT)
parityChecker uut (
.data(data),
.parity(parity),
.parity_result(parity_result)
);
initial begin
// Initialize Inputs
data = 4'b0101;
parity = 0;
#10;
data = 4'b1101;
parity = 0;
#10;
data = 4'b0101;
parity = 1;
#10;
data = 4'b1101;
parity = 1;
#10;
$stop;
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_174x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_174x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [173:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [173:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "174"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "174"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "174"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 174 0 INPUT NODEFVAL data[173..0]
// Retrieval info: USED_PORT: q 0 0 174 0 OUTPUT NODEFVAL q[173..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 174 0 data 0 0 174 0
// Retrieval info: CONNECT: q 0 0 174 0 @q 0 0 174 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_174x128_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S2S_FUNCTIONAL_PP_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: rgmii_io.v
// Project: NetFPGA
// Description: Instantiate the IO flops for the rgmii interface for one TEMAC.
//
// See the Xilinx TriMode Ethernet MAC USer Guide (UG138) for details
//
///////////////////////////////////////////////////////////////////////////////
module rgmii_io (
//-----------------------------------------------------------------------
//-- Pad side signals
//-----------------------------------------------------------------------
output wire [3:0] rgmii_txd ,
output wire rgmii_tx_ctl ,
output wire rgmii_txc ,
input wire [3:0] rgmii_rxd ,
input wire rgmii_rx_ctl ,
//-----------------------------------------------------------------------
//-- Core side signals
//-----------------------------------------------------------------------
input wire [7:0] gmii_txd_int , // Internal gmii_txd signal.
input wire gmii_tx_en_int ,
input wire gmii_tx_er_int ,
output wire gmii_col_int ,
output wire gmii_crs_int ,
output reg [7:0] gmii_rxd_reg , // RGMII double data rate data valid.
output reg gmii_rx_dv_reg , // gmii_rx_dv_ibuf registered in IOBs.
output reg gmii_rx_er_reg , // gmii_rx_er_ibuf registered in IOBs.
//-----------------------------------------------------------------------
//-- Clocks and misc
//-----------------------------------------------------------------------
output reg eth_link_status ,
output reg [1:0] eth_clock_speed ,
output reg eth_duplex_status ,
// Following are generated by DCMs
input wire tx_rgmii_clk_int , // Internal RGMII transmitter clock.
input wire tx_rgmii_clk90_int, // Internal RGMII transmitter clock w/ 90 deg phase
input wire rx_rgmii_clk_int , // Internal RGMII receiver clock
input wire reset
);
reg [7:0] gmii_txd_rising; // gmii_txd signal registered on the rising edge of tx_rgmii_clk_int.
reg gmii_tx_en_rising; // gmii_tx_en signal registered on the rising edge of tx_rgmii_clk_int.
reg rgmii_tx_ctl_rising; // RGMII control signal registered on the rising edge of tx_rgmii_clk_int.
reg [3:0] gmii_txd_falling; // gmii_txd signal registered on the falling edge of tx_rgmii_clk_int
reg rgmii_tx_ctl_falling;// RGMII control signal registered on the falling edge of tx_rgmii_clk_int.
wire [3:0] rgmii_txd_obuf; // RGMII transmit data output.
//(* IOB="FORCE" *)
wire [3:0] rgmii_rxd_ibuf; // RGMII receiver data input.
//(* IOB="FORCE" *)
wire rgmii_rx_ctl_ibuf;
reg [7:0] rgmii_rxd_ddr;
reg rgmii_rx_dv_ddr; // Inverted version of the rx_rgmii_clk_int signal.
reg rgmii_rx_ctl_ddr; // RGMII double data rate data.
reg [7:0] rgmii_rxd_reg; // RGMII double data rate data valid.
reg rgmii_rx_dv_reg; // RGMII double data rate control signal.
reg rgmii_rx_ctl_reg; // RGMII data. gmii_tx_en signal.
//----------------------------------------------------------------
// Transmit interface
//----------------------------------------------------------------
//----------------------------------------------------------------
// Tx clock.
// Instantiate a DDR output register. This is a good way to drive
// RGMII_TXC since the clock-to-PAD delay will be the same as that
// for data driven from IOB Ouput flip-flops eg rgmii_rxd[3:0].
// This is set to produce a 90 degree phase shifted clock w.r.t.
// gtx_clk_bufg so that the clock edges are centralised within the
// rgmii_txd[3:0] valid window.
//----------------------------------------------------------------
wire rgmii_txc_obuf;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_inst (
.Q(rgmii_txc_obuf),
.C(tx_rgmii_clk90_int),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(1'b0),
.S(1'b0)
);
// drive clock through Output Buffers and onto PADS.
OBUF drive_rgmii_txc (.I(rgmii_txc_obuf), .O(rgmii_txc));
//-------------------------------------------------------------------
// RGMII Transmitter Logic :
// drive TX signals through IOBs onto RGMII interface
//-------------------------------------------------------------------
// Encode rgmii ctl signal
wire rgmii_tx_ctl_int;
assign rgmii_tx_ctl_int = gmii_tx_en_int ^ gmii_tx_er_int;
// Register all output signals on rising edge of gtx_clk_bufg
always @(posedge tx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_txd_rising <= 8'b0;
gmii_tx_en_rising <= 1'b0;
rgmii_tx_ctl_rising <= 1'b0;
end
else
begin
gmii_txd_rising <= gmii_txd_int;
gmii_tx_en_rising <= gmii_tx_en_int;
rgmii_tx_ctl_rising <= rgmii_tx_ctl_int;
end
end
wire not_tx_rgmii_clk_int;
assign not_tx_rgmii_clk_int = ~(tx_rgmii_clk_int);
// Register falling edge RGMII output signals on rising edge of not_gtx_clk_bufg
always @(posedge not_tx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_txd_falling <= 4'b0;
rgmii_tx_ctl_falling <= 1'b0;
end
else
begin
gmii_txd_falling <= gmii_txd_rising[7:4];
rgmii_tx_ctl_falling <= rgmii_tx_ctl_rising;
end
end
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out3 (
.Q(rgmii_txd_obuf[3]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[3]),
.D2(gmii_txd_falling[3]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out2 (
.Q(rgmii_txd_obuf[2]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[2]),
.D2(gmii_txd_falling[2]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out1 (
.Q(rgmii_txd_obuf[1]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[1]),
.D2(gmii_txd_falling[1]),
.R(reset),
.S(1'b0)
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_out0 (
.Q(rgmii_txd_obuf[0]),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_txd_rising[0]),
.D2(gmii_txd_falling[0]),
.R(reset),
.S(1'b0)
);
wire rgmii_tx_ctl_obuf;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR_rgmii_txd_ctl
(
.Q(rgmii_tx_ctl_obuf),
.C(tx_rgmii_clk_int),
.CE(1'b1),
.D1(gmii_tx_en_rising),
.D2(rgmii_tx_ctl_falling),
.R(reset),
.S(1'b0)
);
// Drive RGMII Tx signals through Output Buffers and onto PADS.
OBUF drive_rgmii_tx_ctl (.I(rgmii_tx_ctl_obuf), .O(rgmii_tx_ctl));
OBUF drive_rgmii_txd3 (.I(rgmii_txd_obuf[3]), .O(rgmii_txd[3]));
OBUF drive_rgmii_txd2 (.I(rgmii_txd_obuf[2]), .O(rgmii_txd[2]));
OBUF drive_rgmii_txd1 (.I(rgmii_txd_obuf[1]), .O(rgmii_txd[1]));
OBUF drive_rgmii_txd0 (.I(rgmii_txd_obuf[0]), .O(rgmii_txd[0]));
//----------------------------------------------------------------
// Receive interface
//----------------------------------------------------------------
//-------------------------------------------------------------------
// RGMII Receiver Logic : receive RGMII_RX signals through IOBs from
// RGMII interface and convert to gmii_rx signals.
//-------------------------------------------------------------------
// Drive input RGMII Rx signals from PADS through Input Buffers.
IBUF drive_rgmii_rx_ctl (.I(rgmii_rx_ctl), .O(rgmii_rx_ctl_ibuf));
IBUF drive_rgmii_rxd3 (.I(rgmii_rxd[3]), .O(rgmii_rxd_ibuf[3]));
IBUF drive_rgmii_rxd2 (.I(rgmii_rxd[2]), .O(rgmii_rxd_ibuf[2]));
IBUF drive_rgmii_rxd1 (.I(rgmii_rxd[1]), .O(rgmii_rxd_ibuf[1]));
IBUF drive_rgmii_rxd0 (.I(rgmii_rxd[0]), .O(rgmii_rxd_ibuf[0]));
// Infer Double Data Rate Input flip-flops.
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_ddr[3:0] <= 4'b0;
rgmii_rx_dv_ddr <= 1'b0;
end
else
begin
rgmii_rxd_ddr[3:0] <= rgmii_rxd_ibuf;
rgmii_rx_dv_ddr <= rgmii_rx_ctl_ibuf;
end
end
wire not_rx_rgmii_clk_int;
assign not_rx_rgmii_clk_int = ~(rx_rgmii_clk_int);
always @(posedge not_rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_ddr[7:4] <= 4'b0;
rgmii_rx_ctl_ddr <= 1'b0;
end
else
begin
rgmii_rxd_ddr[7:4] <= rgmii_rxd_ibuf;
rgmii_rx_ctl_ddr <= rgmii_rx_ctl_ibuf;
end
end
// Register DDR signals internally to FPGA fabric
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_reg[3:0] <= 4'b0;
rgmii_rx_dv_reg <= 1'b0;
end
else
begin
rgmii_rxd_reg[3:0] <= rgmii_rxd_ddr[3:0];
rgmii_rx_dv_reg <= rgmii_rx_dv_ddr;
end
end // always @(posedge rx_rgmii_clk_int or posedge reset)
always @(posedge not_rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
rgmii_rxd_reg[7:4] <= 4'b0;
rgmii_rx_ctl_reg <= 1'b0;
end
else
begin
rgmii_rxd_reg[7:4] <= rgmii_rxd_ddr[7:4];
rgmii_rx_ctl_reg <= rgmii_rx_ctl_ddr;
end
end
// Register all input signals on rising edge of gmii_rx_clk_bufg to syncronise.
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
gmii_rxd_reg[7:0] <= 8'b0;
gmii_rx_dv_reg <= 1'b0;
gmii_rx_er_reg <= 1'b0;
end
else
begin
gmii_rxd_reg[7:0] <= rgmii_rxd_reg[7:0];
gmii_rx_dv_reg <= rgmii_rx_dv_reg;
gmii_rx_er_reg <= rgmii_rx_ctl_reg ^ rgmii_rx_dv_reg;
end
end
//--------------------------------------------------------------------
// RGMII Inband Status Registers
// extract the inband status from received rgmii data
//--------------------------------------------------------------------
// Enable inband status registers during Interframe Gap
wire inband_ce;
assign inband_ce = !(gmii_rx_dv_reg || gmii_rx_er_reg);
always @(posedge rx_rgmii_clk_int or posedge reset)
begin
if (reset)
begin
eth_link_status <= 1'b0;
eth_clock_speed[1:0] <= 2'b0;
eth_duplex_status <= 1'b0;
end
else
if (inband_ce)
begin
eth_link_status <= gmii_rxd_reg[0];
eth_clock_speed[1:0] <= gmii_rxd_reg[2:1];
eth_duplex_status <= gmii_rxd_reg[3];
end
end
assign gmii_col_int = (gmii_tx_en_int | gmii_tx_er_int) & (gmii_rx_dv_reg | gmii_rx_er_reg);
assign gmii_crs_int = (gmii_tx_en_int | gmii_tx_er_int) | (gmii_rx_dv_reg | gmii_rx_er_reg);
endmodule // rgmii_io
|
module stream_asyn_fifo_xlx #(
parameter FWFTEN = 1,
parameter ADDRWIDTH = 6,
parameter DATAWIDTH = 8,
parameter [ADDRWIDTH:0] FIFODEPTH = 44,
parameter [ADDRWIDTH:0] HEADSIZE = 0
) (
input w_rst_n ,
input w_clk ,
input [ 2:0] w_ctrl ,
output w_full ,
output w_error ,
output [ADDRWIDTH:0] w_counter ,
input [DATAWIDTH-1:0] w_data ,
// read-side
input r_rst_n ,
input r_clk ,
input r_en ,
output r_valid ,
output r_error ,
output [ADDRWIDTH:0] r_counter ,
output [DATAWIDTH-1:0] r_data
);
wire [ADDRWIDTH-1:0] w_ram_addr;
wire w_ram_en;
wire [ADDRWIDTH-1:0] r_ram_addr;
wire r_ram_en;
stream_asyn_fifo_controller #(
.FWFTEN ( FWFTEN ),
.ADDRWIDTH ( ADDRWIDTH ),
.FIFODEPTH ( FIFODEPTH ),
.HEADSIZE ( HEADSIZE )
) fifo_controller_inst (
.w_rst_n ( w_rst_n ), // I
.w_clk ( w_clk ), // I
.w_ctrl ( w_ctrl ), // I
.w_full ( w_full ), // O
.w_error ( w_error ), // O
.w_counter ( w_counter ), // O [ADDRSIZE:0]
.r_rst_n ( r_rst_n ), // I
.r_clk ( r_clk ), // I
.r_en ( r_en ), // I
.r_valid ( r_valid ), // O
.r_error ( r_error ), // O
.r_counter ( r_counter ), // O [ADDRSIZE:0]
.w_ram_addr ( w_ram_addr ), // O [ADDRSIZE-1:0]
.w_ram_en ( w_ram_en ), // O
.r_ram_addr ( r_ram_addr ), // O [ADDRSIZE-1:0]
.r_ram_en ( r_ram_en ) // O
); // instantiation of stream_asyn_fifo_controller
dpram_xlx #(
.ADDRWIDTH ( ADDRWIDTH ),
.DATAWIDTH ( DATAWIDTH ),
.DEPTH ( FIFODEPTH )
) dpram_xlx_inst (
.clka (w_clk ),
.ena (w_ram_en ),
.wea (w_ram_en ),
.addra (w_ram_addr ), // Bus [13 : 0]
.dina (w_data ), // Bus [8 : 0]
.douta ( ), // Bus [8 : 0]
.clkb (r_clk ),
.enb (r_ram_en ),
.web (1'b0 ),
.addrb (r_ram_addr ), // Bus [13 : 0]
.dinb ( { DATAWIDTH {1'b0} } ), // Bus [8 : 0]
.doutb (r_data ) // Bus [8 : 0]
);
//
endmodule
|
//======================================================================
//
// gcm_core.v
// ----------
// Galois Counter Mode core for AES.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module gcm_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire done,
input wire enc_dec,
input wire keylen,
input wire [1 : 0] taglen,
output wire ready,
output wire valid,
output wire tag_correct,
input wire [255 : 0] key,
input wire [127 : 0] nonce,
input wire [127 : 0] block_in,
output wire [127 : 0] block_out,
input wire [127 : 0] tag_in,
output wire [127 : 0] tag_out
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] ctr_reg;
reg [127 : 0] ctr_new;
reg ctr_we;
reg [2 : 0] gcm_ctrl_reg;
reg [2 : 0] gcm_ctrl_new;
reg gcm_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg aes_init;
reg aes_next;
wire aes_encdec;
wire aes_ready;
wire aes_valid;
reg ctr_init;
reg ctr_next;
reg ghash_init;
reg ghash_next;
wire ghash_ready;
reg [127 : 0] ghash_h0;
reg [127 : 0] ghash_x;
wire [127 : 0] ghash_y;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
// We will only use the AES core for encryption. We hardwire
// the operation. This will allow the synthesis tool to remove
// the decryption datapath.
assign aes_encdec = 1;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
aes_core aes(
.clk(clk),
.reset_n(reset_n),
.encdec(aes_encdec),
.init(aes_init),
.next(aes_next),
.ready(aes_ready),
.key(key),
.keylen(keylen),
.block(block_in),
.result(block_out),
.result_valid(aes_valid)
);
gcm_ghash ghash(
.clk(clk),
.reset_n(reset_n),
.init(ghash_init),
.next(ghash_next),
.ready(ghash_ready),
.h0(ghash_h0),
.x(ghash_x),
.y(ghash_y)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
ctr_reg <= 64'h0;
gcm_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ctr_we)
ctr_reg <= ctr_new;
if (gcm_ctrl_we)
gcm_ctrl_reg <= gcm_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// ctr_logic
//----------------------------------------------------------------
always @*
begin : ctr_logic
ctr_new = 128'h0;
ctr_we = 0;
if (ctr_init)
begin
ctr_new = nonce;
ctr_we = 1;
end
if (ctr_next)
begin
ctr_new = {ctr_reg[127 : 64], ctr_reg[63 : 0] + 1'b1};
ctr_we = 1;
end
end // ctr_logic
//----------------------------------------------------------------
// gcm_core_ctrl_fsm
//----------------------------------------------------------------
always @*
begin : gcm_core_ctrl_fsm
aes_init = 0;
aes_next = 0;
ctr_init = 0;
ctr_next = 0;
gcm_ctrl_new = CTRL_IDLE;
gcm_ctrl_we = 0;
case (gcm_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
gcm_ctrl_new = CTRL_INIT;
gcm_ctrl_we = 1;
end
end
CTRL_INIT:
begin
gcm_ctrl_new = CTRL_IDLE;
gcm_ctrl_we = 1;
end
default:
begin
end
endcase // case (gcm_ctrl_reg)
end // gcm_core_ctrl_fsm
endmodule // gcm_core
//======================================================================
// EOF gcm_core.v
//======================================================================
|
// --------------------------------------------------------------------------------
//| Avalon ST Packets to Bytes Component
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_packets_to_bytes
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0)
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST in with packets
output reg in_ready,
input in_valid,
input [7: 0] in_data,
input [CHANNEL_WIDTH-1: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
localparam CHN_COUNT = CHANNEL_WIDTH/7;
reg sent_esc, sent_sop, sent_eop;
reg sent_channel_char, channel_escaped, sent_channel;
reg [CHANNEL_WIDTH:0] stored_channel;
reg [4:0] channel_count;
reg [((CHANNEL_WIDTH/7+1)*7)-1:0] stored_varchannel;
reg channel_needs_esc;
wire need_sop, need_eop, need_esc, need_channel;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign need_esc = (in_data === 8'h7a |
in_data === 8'h7b |
in_data === 8'h7c |
in_data === 8'h7d );
assign need_eop = (in_endofpacket);
assign need_sop = (in_startofpacket);
generate
if( CHANNEL_WIDTH > 0) begin
wire channel_changed;
assign channel_changed = (in_channel != stored_channel);
assign need_channel = (need_sop | channel_changed);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
out_data <= 0;
out_valid <= 0;
channel_count <= 0;
channel_needs_esc <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin
sent_channel_char <= 1;
out_data <= 8'h7c;
channel_count <= CHN_COUNT[4:0];
stored_varchannel <= in_channel;
if (ENCODING == 0) begin
channel_needs_esc <= (in_channel == 8'h7a |
in_channel == 8'h7b |
in_channel == 8'h7c |
in_channel == 8'h7d );
end
end else if (channel_needs_esc & ~channel_escaped) begin
out_data <= 8'h7d;
channel_escaped <= 1;
end else if (~sent_channel) begin
if (ENCODING) begin
// Sending out MSB=1, while not last 7 bits of Channel
if (channel_count > 0) begin
if (channel_needs_esc) out_data <= {1'b1, stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-1:((CHANNEL_WIDTH/7+1)*7)-7]} ^ 8'h20;
else out_data <= {1'b1, stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-1:((CHANNEL_WIDTH/7+1)*7)-7]};
stored_varchannel <= stored_varchannel<<7;
channel_count <= channel_count - 1'b1;
// check whether the last 7 bits need escape or not
if (channel_count ==1 & CHANNEL_WIDTH > 7) begin
channel_needs_esc <=
((stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-8:((CHANNEL_WIDTH/7+1)*7)-14] == 7'h7a)|
(stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-8:((CHANNEL_WIDTH/7+1)*7)-14] == 7'h7b) |
(stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-8:((CHANNEL_WIDTH/7+1)*7)-14] == 7'h7c) |
(stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-8:((CHANNEL_WIDTH/7+1)*7)-14] == 7'h7d) );
end
end else begin
// Sending out MSB=0, last 7 bits of Channel
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= {1'b0, stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-1:((CHANNEL_WIDTH/7+1)*7)-7]} ^ 8'h20;
end else out_data <= {1'b0, stored_varchannel[((CHANNEL_WIDTH/7+1)*7)-1:((CHANNEL_WIDTH/7+1)*7)-7]};
sent_channel <= 1;
end
end else begin
if (channel_needs_esc) begin
channel_needs_esc <= 0;
out_data <= in_channel ^ 8'h20;
end else out_data <= in_channel;
sent_channel <= 1;
end
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
sent_channel <= 0;
channel_escaped <= 0;
sent_channel_char <= 0;
end
end
end
end
//channel related signals
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
//extra bit in stored_channel to force reset
stored_channel <= {CHANNEL_WIDTH{1'b1}};
end else begin
//update stored_channel only when it is sent out
if (sent_channel) stored_channel <= in_channel;
end
end
always @* begin
// in_ready. Low when:
// back pressured, or when
// we are outputting a control character, which means that one of
// {escape_char, start of packet, end of packet, channel}
// needs to be, but has not yet, been handled.
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end else begin
assign need_channel = (need_sop);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
out_data <= 0;
out_valid <= 0;
sent_channel <= 0;
sent_channel_char <= 0;
end else begin
if (out_ready )
out_valid <= 0;
if ((out_ready | ~out_valid) && in_valid )
out_valid <= 1;
if ((out_ready | ~out_valid) && in_valid) begin
if (need_channel & ~sent_channel) begin
if (~sent_channel_char) begin //Added sent channel 0 before the 1st SOP
sent_channel_char <= 1;
out_data <= 8'h7c;
end else if (~sent_channel) begin
out_data <= 'h0;
sent_channel <= 1;
end
end else if (need_sop & ~sent_sop) begin
sent_sop <= 1;
out_data <= 8'h7a;
end else if (need_eop & ~sent_eop) begin
sent_eop <= 1;
out_data <= 8'h7b;
end else if (need_esc & ~sent_esc) begin
sent_esc <= 1;
out_data <= 8'h7d;
end else begin
if (sent_esc) out_data <= in_data ^ 8'h20;
else out_data <= in_data;
sent_esc <= 0;
sent_sop <= 0;
sent_eop <= 0;
end
end
end
end
always @* begin
in_ready = (out_ready | !out_valid) & in_valid & (~need_esc | sent_esc)
& (~need_sop | sent_sop)
& (~need_eop | sent_eop)
& (~need_channel | sent_channel);
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_1_V
`define SKY130_FD_SC_LS__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_1_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BMSTU
// Engineer: Oleg Odintsov
//
// Create Date: 15:09:47 01/19/2012
// Design Name:
// Module Name: ag_main
// Project Name: Agat Hardware Project
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM2kx8(input CLK, input[10:0] AB, input CS, output[7:0] DO);
reg[7:0] mem[0:2047];
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) R <= mem[AB];
initial begin
`include "monitor7.v"
end
endmodule
module ag_main(
input clk50x,
input[3:0] btns,
input[3:0] switches,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
input[1:0] ps2_bus_in
);
// assign leds = 0;
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk1x, clk10, clk50;
reg turbo = 0;
BUFG bg1(clk50, clk50x);
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1x);
BUFGMUX bgm1(clk1, clk1x, clk10, turbo);
// assign clk1 = turbo?clk10:clk1x;
wire clk_vram;
wire[13:0] AB2;
wire[15:0] DI2;
wire [15:0] AB; // address bus
wire [7:0] DI; // data in, read bus
wire [7:0] DO; // data out, write bus
wire read;
wire rom_cs, ram_cs;
wire phi_1, phi_2;
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
ROM2kx8 rom1(phi_2, AB[10:0], rom_cs, DI);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
wire [3:0] AB_LH = AB[7:4];
wire [3:0] AB_LL = AB[3:0];
wire [7:0] AB_H = AB[15:8];
wire [7:0] AB_L = AB[7:0];
wire AB_CXXX = (AB_HH == 4'hC);
wire AB_FXXX = (AB_HH == 4'hF);
wire AB_C0XX = AB_CXXX && !AB_HL;
wire AB_C00X = AB_C0XX && (AB_LH == 4'h0);
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
reg timer_ints = 0;
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
reg reset_auto = 1;
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
wire NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
assign NMI = timer_ints & vga_bus[0];
reg[7:0] vmode = 0;
wire[7:0] key_reg;
wire key_rus;
reg key_clear = 0;
wire key_rst, key_pause;
reg beep_reg = 0, tape_out_reg = 0;
assign reset = btns[0];
assign leds = AB[11:4];
assign controls = {1'b0, beep_reg ^ tape_out_reg, tape_out_reg, beep_reg};
ag_video video(clk50, vmode, clk_vram, AB2, DI2, vga_bus);
wire[1:0] ps2_bus;
signal_filter sf1(clk1, ps2_bus_in[0], ps2_bus[0]);
signal_filter sf2(clk1, ps2_bus_in[1], ps2_bus[1]);
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
wire reset_all = reset | reset_auto | key_rst;
always @(posedge phi_2) begin
turbo <= switches[0];
key_clear <= AB_C01X;
if (AB_C04X) timer_ints <= 1;
else if (AB_C05X || reset_all) timer_ints <= 0;
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
end
always @(posedge vga_bus[0]) begin
reset_auto <= 0;
end
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~reset_all, ~IRQ, ~NMI, SO, SYNC);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:43:14 03/25/2015
// Design Name: fifo_top
// Module Name: S:/Xilinx/assignment5/fifo_top_tb.v
// Project Name: assignment5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fifo_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module fifo_tb;
// Inputs
reg [6:0] vector_in;
reg reset;
reg clk;
// Outputs
wire [3:0] data_out;
wire empty_flag;
wire full_flag;
reg [3:0]data[3:0];
reg [3:0]count;
// Instantiate the Unit Under Test (UUT)
fifo fifo (
.data_out(data_out),
.empty_flag(empty_flag),
.full_flag(full_flag),
.vector_in(vector_in),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
vector_in = 0;
clk = 1;
reset = 1;
count = 0;
// Wait 100 ns for global reset to finish
// #100;
data[0]=4'b1111;
data[1]=4'b1110;
data[2]=4'b1101;
data[3]=4'b1001;
// Add stimulus here
// 4 writes
#2 reset = 0;
// vector_in = 6'b10_1111;
// #2 vector_in = 6'b10_1110;
// #2 vector_in = 6'b10_1101;
// #2 vector_in = 6'b10_1001;
// #2 vector_in = 6'b00_1001;
// 4 reads
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b01_1001;
// #2 vector_in = 6'b00_1001;
// 4 writes
// #2 vector_in = 6'b10_0000;
// #2 vector_in = 6'b10_0001;
// #2 vector_in = 6'b10_0111;
// #2 vector_in = 6'b10_0110;
// #2 vector_in = 6'b00_1001;
// 4 more writes
// #2 vector_in = 6'b10_0000;
// #2 vector_in = 6'b10_0001;
// #2 vector_in = 6'b10_0111;
// #2 vector_in = 6'b10_0110;
// #2 vector_in = 6'b00_1001;
// 2 writes
// #2 vector_in = 6'b10_1101;
// #2 vector_in = 6'b10_1001;
// #2 vector_in = 6'b00_1000;
// #2 $finish;
end
always@(posedge clk)
begin
if(full_flag)begin
$display("HALT:%d",full_flag);
#2 vector_in = 7'b00_0000_1;
end else begin
$display("FETCHING:%d",full_flag);
#2 vector_in = {2'b10,data[count],1'b0};
count = count + 1;
end
end
always
#1 clk = ~clk;
endmodule
|
/*
* DSI Core
* Copyright (C) 2013-2014 twl <[email protected]>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* dsi_core.v - top level of the DSI core */
`include "dsi_defs.vh"
`timescale 1ns/1ps
module dsi_core
(
// system/FIFO clock
clk_sys_i,
// DSI interface byte clock (=PHY clock/8)
clk_dsi_i,
// DSI HS clock
clk_phy_i,
// Shifted version of DSI/PHY clocks (for clock-data lane alignment)
clk_dsi_shifted_i,
clk_phy_shifted_i,
rst_n_i,
pll_locked_i,
// Pixel FIFO interface
// 1 indicates the core is in LP mode, waiting for the start of the next frame
pix_next_frame_o,
// when pix_next_frame is asserted, 1 on pix_vsync_i starts outputting next frame
pix_vsync_i,
// FIFO almost full
pix_almost_full_o,
// FIFO pixel(s) input
pix_i,
// FIFO write
pix_wr_i,
// DSI high speed output
dsi_hs_p_o,
dsi_hs_n_o,
// DSI low power output
dsi_lp_p_o,
dsi_lp_n_o,
// Low power output enable
dsi_lp_oe_o,
// DSI clock lane output
dsi_clk_p_o,
dsi_clk_n_o,
// DSI clock lane LP signals + output enable
dsi_clk_lp_p_o,
dsi_clk_lp_n_o,
dsi_clk_lp_oe_o,
// Displat Reset pin
dsi_reset_n_o,
// Display Avdd power enable pin/user-defined GPIO
dsi_gpio_o,
// Host control registers (WBv4 pipelined, clk_sys_i clock domain)
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_sel_i,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_ack_o,
wb_stall_o
);
// number of pixels processed in each clk_dsi_i cycle
parameter g_pixels_per_clock = 1;
// max number of DSI lanes
parameter g_lanes = 3;
// image FIFO size (holds g_pixels_per_clock * g_fifo_size pixels)
parameter g_fifo_size = 1024;
// ineverted lane polarity mask (0 = lane 0, 0x4 = lane 2, etc)
parameter g_invert_lanes = 0;
// invert DSI clock when true
parameter g_invert_clock = 0;
parameter g_use_external_dsi_clock = 0;
// PHY clock period, in picoseconds. Used to set clock-to-data shift.
parameter g_clock_period_ps = 3600;
// picoseconds per ODELAY2 tap. Used to set clock-to-data shift.
parameter g_ps_per_delay_tap = 50;
localparam g_data_delay = (g_clock_period_ps / 2) / g_ps_per_delay_tap;
localparam g_pixel_width = 24 * g_pixels_per_clock;
input [31:0] wb_adr_i;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [3:0] wb_sel_i;
input wb_cyc_i, wb_stb_i, wb_we_i;
output wb_ack_o, wb_stall_o;
input clk_sys_i, clk_phy_i, clk_dsi_i, rst_n_i;
input clk_phy_shifted_i, clk_dsi_shifted_i;
input pll_locked_i;
output pix_next_frame_o;
input pix_vsync_i;
output pix_almost_full_o;
input [g_pixel_width - 1 : 0 ] pix_i;
input pix_wr_i;
output dsi_clk_p_o, dsi_clk_n_o;
output [g_lanes-1:0] dsi_hs_p_o, dsi_hs_n_o;
output [g_lanes-1:0] dsi_lp_p_o, dsi_lp_n_o;
output [g_lanes-1:0] dsi_lp_oe_o;
output dsi_clk_lp_p_o, dsi_clk_lp_n_o;
output dsi_clk_lp_oe_o;
output reg dsi_reset_n_o;
output reg [2:0] dsi_gpio_o;
wire [5:0] host_a;
wire [31:0] host_d_in;
wire [31:0] host_d_out;
wire host_wr;
reg [7:0] r_lane_mux;
reg [3:0] r_lane_invert;
reg r_clock_invert;
dsi_wishbone_async_bridge #(
.g_csr_addr_bits(6)
) U_CsrBridge (
.clk_wb_i (clk_sys_i),
.clk_csr_i (clk_dsi_i),
.rst_n_i(rst_n_i),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_sel_i(wb_sel_i),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_ack_o(wb_ack_o),
.wb_stall_o(wb_stall_o),
.wb_dat_o(wb_dat_o),
.csr_adr_o(host_a),
.csr_dat_o(host_d_in),
.csr_wr_o(host_wr),
.csr_dat_i(host_d_out)
);
///////////////////
// PHY/Serdes layer
///////////////////
reg tick = 0;
wire [g_lanes-1:0] phy_hs_ready_lane, lp_ready_lane, lp_readback_lane;
wire [g_lanes:0] serdes_oe_lane;
wire [g_lanes-1:0] lp_txp, lp_txn, lp_oe;
wire lp_ready;
wire phy_hs_ready;
assign lp_ready = lp_ready_lane[0];
assign phy_hs_ready = phy_hs_ready_lane[0];
wire phy_hs_request;
wire [g_lanes * 8 -1 :0] phy_hs_data;
wire [g_lanes-1:0] phy_hs_valid;
wire [(g_lanes + 1) * 8 - 1: 0] serdes_data;
reg r_dsi_clk_en = 0;
reg lp_request = 0;
reg lp_valid = 0;
reg [7:0] lp_data = 0;
reg [2:0] num_lanes;
dsi_sync_chain #(2) Sync3 (clk_dsi_i, 1'b0, rst_n_i, rst_n_dsi);
generate
genvar i;
for(i=0;i<g_lanes;i=i+1)
begin
dphy_lane
// #(
// .g_invert(g_invert_lanes&(1<<i)?1:0)
// )
U_LaneX
(
.clk_i(clk_dsi_i),
.rst_n_i(rst_n_dsi),
.tick_i(tick),
.hs_request_i (phy_hs_request),
.hs_data_i (phy_hs_data),
.hs_ready_o (phy_hs_ready_lane[i]),
.hs_valid_i(phy_hs_valid),
.lp_request_i (lp_request),
.lp_data_i (lp_data),
.lp_valid_i (r_lane_mux[ i*2 +: 2] == 0 ? lp_valid : 1'b0),
.lp_ready_o (lp_ready_lane[i]),
.serdes_data_o(serdes_data[ i*8 +: 8]),
.lane_sel_i( r_lane_mux[ i*2 +: 2] ),
.lane_invert_i( r_lane_invert[i] ), //g_invert_lanes&(1<<i)?1:0),
.lp_txp_o(lp_txp[i]),
.lp_txn_o(lp_txn[i]),
.lp_oe_o(lp_oe[i])
);
assign dsi_lp_p_o[i] = lp_txp[i];
assign dsi_lp_n_o[i] = lp_txn[i];
assign dsi_lp_oe_o[i] = lp_oe[0];
assign serdes_oe_lane[i] = lp_oe[0];
end // for (i=0;i<g_lanes;i=i+1)
endgenerate
wire clk_lane_ready;
wire dsi_clk_lp_oe;
dphy_lane
// #(
// .g_invert(g_invert_clock)
// )
U_ClockLane (
.clk_i(clk_dsi_i),
.rst_n_i(rst_n_dsi),
.tick_i(tick),
.hs_request_i (r_dsi_clk_en),
.hs_data_i ({24'h000000, clk_lane_ready ? 8'haa : 8'h00}),
.hs_ready_o (clk_lane_ready),
.hs_valid_i(1'b1),
.lp_request_i (1'b0),
.lp_data_i(8'h00),
.lp_valid_i(1'b0),
.lp_ready_o(),
.serdes_data_o(serdes_data[g_lanes*8 +: 8]),
.lane_sel_i(2'b00),
.lane_invert_i( r_clock_invert ), //g_invert_clock ? 1'b1: 1'b0),
.lp_txp_o(dsi_clk_lp_p_o),
.lp_txn_o(dsi_clk_lp_n_o),
.lp_oe_o(dsi_clk_lp_oe)
);
assign serdes_oe_lane [g_lanes] = dsi_clk_lp_oe;
assign dsi_clk_lp_oe_o = dsi_clk_lp_oe;
wire clk_serdes, serdes_strobe;
wire clk_serdes_shifted, serdes_strobe_shifted;
dphy_serdes_plla U_BufPLL
(
.clk_phy_i(clk_phy_i),
.clk_dsi_i(clk_dsi_i),
.rst_n_a_i(rst_n_i),
.locked_i (pll_locked_i),
.clk_serdes_o(clk_serdes),
.serdes_strobe_o(serdes_strobe)
);
dphy_serdes_pllb U_BufPLL_Clk
(
.clk_phy_i(clk_phy_shifted_i),
.clk_dsi_i(clk_dsi_i),
.rst_n_a_i(rst_n_i),
.locked_i (pll_locked_i),
.clk_serdes_o(clk_serdes_shifted),
.serdes_strobe_o(serdes_strobe_shifted)
);
wire [g_lanes:0] tx_p, tx_n;
generate
for(i=0;i<g_lanes;i=i+1)
begin
dphy_serdes
#( .g_delay ( g_data_delay ) )
U_Serdes_LaneX (
.clk_serdes_i(clk_serdes),
.clk_word_i(clk_dsi_i),
.rst_n_a_i(rst_n_i),
.strobe_i(serdes_strobe),
.oe_i(serdes_oe_lane[i]),
.d_i(serdes_data[i*8 +: 8]),
.q_p_o(tx_p[i]),
.q_n_o(tx_n[i])
);
if( i < g_lanes ) begin
assign dsi_hs_p_o[i] = tx_p[i];
assign dsi_hs_n_o[i] = tx_n[i];
end
end // for (i=0;i<=g_lanes;i+=1)
endgenerate
dphy_serdes
#( .g_delay ( 0 ) )
U_Serdes_ClkLane (
.clk_serdes_i(clk_serdes_shifted),
.clk_word_i(clk_dsi_i),
.rst_n_a_i(rst_n_i),
.strobe_i(serdes_strobe_shifted),
.oe_i(serdes_oe_lane[g_lanes]),
.d_i(serdes_data[g_lanes*8 +: 8]),
.q_p_o(tx_p[g_lanes]),
.q_n_o(tx_n[g_lanes])
);
assign dsi_clk_p_o = tx_p[g_lanes];
assign dsi_clk_n_o = tx_n[g_lanes];
////////////////
// Packet layer
///////////////
wire p_req, p_islong, p_dreq, p_last;
wire [5:0] p_type;
wire [15:0] p_command, p_wcount;
wire [g_pixel_width-1:0] p_payload;
dsi_packet_assembler
#(
.g_num_lanes(g_lanes),
.g_pixels_per_clock(g_pixels_per_clock)
) U_PktAsm (
.clk_i(clk_dsi_i),
.rst_n_i(rst_n_dsi),
.p_req_i(p_req),
.p_islong_i(p_islong),
.p_type_i(p_type),
.p_wcount_i(p_wcount),
.p_command_i(p_command),
.p_dreq_o(p_dreq),
.p_dlast_o(p_dlast),
.p_payload_i(p_payload),
.p_last_i(p_last),
.phy_d_o(phy_hs_data),
.phy_hs_request_o(phy_hs_request),
.phy_hs_dreq_i(phy_hs_ready_lane[0]),
.phy_dvalid_o(phy_hs_valid),
.num_lanes_i(num_lanes)
);
////////////////
// Test Screen generator
///////////////
wire fifo_empty, fifo_rd;
wire [g_pixel_width-1:0] fifo_dout;
///////////////
// Image timing
///////////////
wire pix_vsync_dsi, pix_next_frame_dsi;
dsi_sync_chain #(2) Sync1 (clk_dsi_i, rst_n_dsi, pix_vsync_i, pix_vsync_dsi);
dsi_sync_chain #(2) Sync2 (clk_sys_i, rst_n_i, pix_next_frame_dsi, pix_next_frame_o);
dsi_timing_gen
#( .g_pixels_per_clock(g_pixels_per_clock) )
U_TimingGen (
.clk_i(clk_dsi_i),
.rst_n_i(rst_n_dsi),
.fifo_empty_i(fifo_empty),
.fifo_rd_o(fifo_rd),
.fifo_pixels_i(fifo_dout),
.pix_vsync_i(pix_vsync_dsi),
.pix_next_frame_o(pix_next_frame_dsi),
.p_req_o(p_req),
.p_islong_o(p_islong),
.p_type_o(p_type),
.p_wcount_o(p_wcount),
.p_command_o(p_command),
.p_payload_o(p_payload),
.p_dreq_i(p_dreq),
.p_last_o(p_last),
.host_a_i(host_a),
.host_d_i(host_d_in),
// .host_d_o(host_d_o),
.host_wr_i(host_wr)
);
////////////////
/// Pixel Buffer
////////////////
generic_async_fifo
#(
.g_data_width(g_pixel_width),
.g_size(g_fifo_size),
.g_almost_full_threshold(g_fifo_size-20),
.g_almost_empty_threshold(10),
.g_with_wr_almost_full(1)
)
U_PixFifo
(
.rst_n_i(rst_n_i),
.clk_wr_i(clk_sys_i),
.d_i(pix_i),
.wr_almost_full_o(pix_almost_full_o),
.we_i(pix_wr_i),
.clk_rd_i(clk_dsi_i),
.rd_i(fifo_rd),
.rd_empty_o(fifo_empty),
.q_o(fifo_dout)
);
////////////////
// Host regs
////////////////
reg [11:0] r_tick_div, tick_count;
always@(posedge clk_dsi_i)
begin
if (!rst_n_dsi)
tick_count <= 0;
else begin
if(tick_count == r_tick_div)
begin
tick <= 1;
tick_count <= 0;
end else begin
tick <= 0;
tick_count <= tick_count + 1;
end
end // else: !if(!rst_n_i)
end // always@ (posedge clk_sys_i)
reg [31:0] host_d_self;
always@(posedge clk_dsi_i)
if(!rst_n_dsi)
begin
r_tick_div <= 0;
r_dsi_clk_en <= 0;
lp_request <= 0;
host_d_self <= 0;
dsi_reset_n_o <= 0;
dsi_gpio_o <= 0;
r_lane_mux <= 0;
r_lane_invert <= 0;
r_clock_invert <= 0;
end else if(host_wr) begin
case(host_a)
`REG_TICK_DIV: r_tick_div <= host_d_in;
`REG_DSI_CTL: begin
r_dsi_clk_en <= host_d_in[0];
lp_request <= host_d_in[1];
num_lanes <= host_d_in[10:8];
end
`REG_LP_TX:
if(lp_ready) begin
lp_valid <= host_d_in[8];
lp_data <= host_d_in[7:0];
end
`REG_GPIO: begin
dsi_reset_n_o <= host_d_in[0];
dsi_gpio_o <= host_d_in[3:1];
end
`REG_LANE_CTRL: begin
r_lane_mux <= host_d_in[7:0];
r_lane_invert <= host_d_in[11:8];
r_clock_invert <= host_d_in[12];
end
endcase // case (host_a_i)
end else begin
lp_valid <= 0;
case(host_a)
`REG_DSI_CTL: begin
host_d_self[7:2] <= 0;
host_d_self[31:11] <= 0;
host_d_self[0] <= r_dsi_clk_en;
host_d_self[1] <= lp_ready;
host_d_self[10:8] <= num_lanes;
end
`REG_GPIO: begin
host_d_self <= 'hdeadbeef;
end
default:
host_d_self <= 0;
endcase // case (host_a)
end // else: !if(host_wr_i)
assign host_d_out = host_d_self;
endmodule // dsi_core
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module Top_Muliti_IOBUS(
sys_clk,
BTN, // I/O:
SW,
LED,
SEGMENT,
AN_SEL,
cellram_dq_io,
cellram_adr_o,
cellram_adv_n_o,
cellram_ce_n_o,
cellram_clk_o,
cellram_oe_n_o,
cellram_wait_i,
cellram_we_n_o,
cellram_cre_o,
cellram_lb_n_o,
cellram_ub_n_o,
vsync, rgb, hsync,
ps2_clk,ps2_dat
);
parameter cellram_dq_width = 16;
parameter cellram_adr_width = 23;
parameter cellram_write_cycles = 4; // wlwh/Tclk = 50ns / 15 ns (66Mhz)
parameter cellram_read_cycles = 4; // elqv/Tclk = 95 / 15 ns (66MHz)
input sys_clk;
input [4:0] BTN;
input [7:0] SW;
output [7:0] LED,SEGMENT;
output [3:0] AN_SEL;
inout [cellram_dq_width-1:0] cellram_dq_io;
output [cellram_adr_width-1:0] cellram_adr_o;
output cellram_adv_n_o;
output cellram_ce_n_o;
output cellram_clk_o;
output cellram_oe_n_o;
input cellram_wait_i;
output cellram_we_n_o;
output cellram_cre_o;
output cellram_ub_n_o;
output cellram_lb_n_o;
wire clk_50mhz;
wire vga_clk, txt_clk;
wire Clk_CPU, rst,clk_m, mem_w,data_ram_we,GPIOf0000000_we,GPIOe0000000_we,counter_we;
wire counter_OUT0,counter_OUT1,counter_OUT2;
wire [1:0]Counter_set;
wire [4:0] state;
wire [3:0] digit_anode,blinke;
wire [4:0] button_out;
wire [7:0] SW_OK,SW,led_out,LED,SEGMENT; //led_out is current LED light
wire [9:0] rom_addr,ram_addr;
wire [21:0]GPIOf0;
wire [31:0] pc,Inst,addr_bus,Cpu_data2bus,ram_data_out,disp_num;
wire [31:0]clkdiv,Cpu_data4bus,counter_out,ram_data_in,Peripheral_in;
wire [3:0] dpdot;
wire BIU_ready, MIO_ready, BIU_req;
wire CPU_MIO;
wire sys_rst=button_out[3];
wire sys_locked;
reg Ireq;
reg Ireq_hold;
wire Iack;
clkgen clkgen0
(// Clock in ports
.CLK_IN1(sys_clk), // IN
// Clock out ports
.CLK_OUT1(clk_50mhz), // OUT
.CLK_OUT2(vga_clk), // OUT
.CLK_OUT3(txt_clk),
// Status and control signals
.RESET(1'b0),// IN
.LOCKED(sys_locked)); // OUT
assign MIO_ready=~button_out[1];
assign rst=~sys_locked;
assign SW2=SW_OK[2];
assign LED=led_out;
assign clk_m=~clk_50mhz;
assign rom_addr=pc[11:2];
assign AN_SEL=digit_anode;
assign clk_io=~Clk_CPU;
seven_seg seven_seg(
.disp_num(disp_num),
.clk(clk_50mhz),
.clr(rst),
.SW(SW_OK[1:0]),
.Scanning(clkdiv[19:18]),
.dpdot(dpdot),
.SEGMENT(SEGMENT),
.AN(digit_anode)
);
BTN_Anti_jitter BTN_OK (clk_50mhz, BTN,SW, button_out,SW_OK);
clk_div div_clk(clk_50mhz,
rst,
SW2,
clkdiv,
Clk_CPU
); // Clock divider-
//++++++++++++++++++single_cycle_Cpu+++++++++++++++++++++++++++++++++++++++++++++++
/* single_cycle_Cpu_9_mux
// simple_cpu_more
// simple_cpu_more_int
single_cycle_cpu(
.clk(Clk_CPU),
.reset(rst),
// Internal signals:
.pc_out(pc),
.inst_in(Inst),
.mem_w(mem_w),
.Addr_out(addr_bus),
.Cpudata_out(Cpu_data2bus),
.Cpudata_in(Cpu_data4bus)
// .INT(counter_OUT0)
);
ROM_B IRom(
.clka(clk_m),
.addra(rom_addr),
.douta(Inst)
);
RAM_B D_Ram (.clka(clk_m),
.wea(data_ram_we),
.addra(ram_addr),
.dina(ram_data_in),
.douta(ram_data_out)
); // Addre_Bus [9 : 0] ,Data_Bus [31 : 0]
*/
//++++++++++++++++++++++muliti_cycle_cpu+++++++++++++++++++++++++++++++++++++++++++
Muliti_cycle_Cpu muliti_cycle_cpu(
.clk(Clk_CPU),
.reset(rst),
.MIO_ready(BIU_ready), //MIO_ready
// Internal signals:
.pc_out(pc), //Test
.Inst(Inst), //Test
.mem_w(mem_w),
.breq_o(BIU_req),
.Addr_out(addr_bus),
.data_out(Cpu_data2bus),
.data_in(Cpu_data4bus),
.CPU_MIO(CPU_MIO),
.Ireq(Ireq),
.Iack(Iack),
.state(state), //Test
.Enable_i(&clkdiv[27:0] | SW2)
);
Mem_B RAM_I_D(.clka(clk_m),
.wea(data_ram_we),
.addra(ram_addr),
.dina(ram_data_in),
.douta(ram_data_out)
); // Addre_Bus [9 : 0] ,Data_Bus [31 : 0]
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
wire [31:0] MIO_data2bus, MIO_data4bus;
wire [31:0] MIO_addr_bus;
wire MIO_mem_w;
wire txt_ena;
wire txt_wea;
wire [12:0] txt_addra;
wire [15:0] txt_dina;
wire [15:0] txt_douta;
wire [31:0] gpu_status;
wire [31:0] cellram_wb_adr_i;
wire [31:0] cellram_wb_dat_i;
wire [31:0] cellram_wb_dat_o;
wire [3:0] cellram_wb_sel_i;
wire cellram_wb_cyc_i;
wire cellram_wb_stb_i;
wire cellram_wb_we_i;
wire cellram_wb_ack_o;
wire [31:0] wb_m0_vcache_adr_i;
wire [31:0] wb_m0_vcache_dat_i;
wire [3:0] wb_m0_vcache_sel_i;
wire wb_m0_vcache_cyc_i;
wire wb_m0_vcache_stb_i;
wire wb_m0_vcache_we_i;
wire [31:0] wb_m0_vcache_dat_o;
wire wb_m0_vcache_ack_o;
wire [31:0] wb_m1_cpu_adr_i;
wire [31:0] wb_m1_cpu_dat_i;
wire [3:0] wb_m1_cpu_sel_i;
wire wb_m1_cpu_cyc_i;
wire wb_m1_cpu_stb_i;
wire wb_m1_cpu_we_i;
wire [31:0] wb_m1_cpu_dat_o;
wire wb_m1_cpu_ack_o;
wire wb_m1_cpu_gnt;
wire wb_m0_vcache_gnt;
wire [7:0] ps2_wb_dat_i;
wire [7:0] ps2_wb_dat_o;
wire [0:0] ps2_wb_adr_i;
wire ps2_wb_stb_i;
wire ps2_wb_we_i;
wire ps2_wb_ack_o;
BIU biu0(
.clk(clk_50mhz),
.rst(rst),
.Cpu_mem_w_i(mem_w),
.Cpu_req_i(BIU_req),
.Cpu_data2bus_i(Cpu_data2bus), //data from CPU
.Cpu_addr_bus_i(addr_bus),
.Cpu_data4bus_o(Cpu_data4bus), //write to CPU
.Cpu_ready_o(BIU_ready),
.MIO_mem_w_o(MIO_mem_w),
.MIO_data2bus_o(MIO_data2bus), //data from CPU
.MIO_addr_bus_o(MIO_addr_bus),
.MIO_data4bus_i(MIO_data4bus), //write to CPU
.MIO_ready_i(MIO_ready),
.wb_d_adr_o(wb_m1_cpu_adr_i),
.wb_d_dat_o(wb_m1_cpu_dat_i),
.wb_d_sel_o(wb_m1_cpu_sel_i),
.wb_d_cyc_o(wb_m1_cpu_cyc_i),
.wb_d_stb_o(wb_m1_cpu_stb_i),
.wb_d_we_o (wb_m1_cpu_we_i ),
.wb_d_dat_i(wb_m1_cpu_dat_o),
.wb_d_ack_i(wb_m1_cpu_ack_o),
.wb_c_adr_o(ps2_wb_adr_i),
.wb_c_dat_o(ps2_wb_dat_i),
.wb_c_stb_o(ps2_wb_stb_i),
.wb_c_we_o (ps2_wb_we_i ),
.wb_c_dat_i(ps2_wb_dat_o),
.wb_c_ack_i(ps2_wb_ack_o),
.txt_ena(txt_ena),
.txt_wea(txt_wea),
.txt_addra(txt_addra),
.txt_dina(txt_douta),
.txt_douta(txt_dina),
.gpu_status(gpu_status)
);
output hsync; // From vchache0 of vcache.v
output [7:0] rgb; // From vchache0 of vcache.v
output vsync; // From vchache0 of vcache.v
assign hsync = gpu_status[0] ? hsync_vc : hsync_tx;
assign vsync = gpu_status[0] ? vsync_vc : vsync_tx;
assign rgb = gpu_status[0] ? rgb_vc : rgb_tx;
wire [7:0] rgb_vc;
wire hsync_vc;
wire vsync_vc;
vcache
#(
.vram_adr_base('hf80000)
)
vchache0
(
.wb_clk_i(clk_50mhz),
.wb_rst_i(rst),
//.wb_m0_vcache_gnt(wb_m0_vcache_gnt),
.wb_adr_o(wb_m0_vcache_adr_i),
.wb_dat_o(wb_m0_vcache_dat_i),
.wb_sel_o(wb_m0_vcache_sel_i),
.wb_cyc_o(wb_m0_vcache_cyc_i),
.wb_stb_o(wb_m0_vcache_stb_i),
.wb_we_o (wb_m0_vcache_we_i ),
.wb_dat_i(wb_m0_vcache_dat_o),
.wb_ack_i(wb_m0_vcache_ack_o),
//vga
// Outputs
.rgb (rgb_vc[7:0]),
.hsync (hsync_vc),
.vsync (vsync_vc),
// Inputs
.vga_clk (vga_clk)
);
wire [7:0] rgb_tx;
wire hsync_tx;
wire vsync_tx;
gpu gpu0 (
.clr(rst),
.clka(clk_50mhz),
.clkb(txt_clk),
.ena(txt_ena),
.wea(txt_wea),
.addra(txt_addra),
.dina(txt_dina),
.douta(txt_douta),
.vgaRed(rgb_tx[2:0]),
.vgaGreen(rgb_tx[5:3]),
.vgaBlue(rgb_tx[7:6]),
.Hsync(hsync_tx),
.Vsync(vsync_tx)
);
wire [1:0] cellram_mst_sel;
arbiter arbiter0(
.wb_clk(clk_50mhz),
.wb_rst(rst),
.cellram_mst_sel(cellram_mst_sel),
.wb_s0_cellram_wb_adr_o(cellram_wb_adr_i),
.wb_s0_cellram_wb_dat_o(cellram_wb_dat_i),
.wb_s0_cellram_wb_sel_o(cellram_wb_sel_i),
.wb_s0_cellram_wb_stb_o(cellram_wb_stb_i),
.wb_s0_cellram_wb_cyc_o(cellram_wb_cyc_i),
.wb_s0_cellram_wb_we_o (cellram_wb_we_i ),
.wb_s0_cellram_wb_dat_i(cellram_wb_dat_o),
.wb_s0_cellram_wb_ack_i(cellram_wb_ack_o),
.wb_m0_vcache_dat_o (wb_m0_vcache_dat_o[31:0]),
.wb_m0_vcache_ack_o (wb_m0_vcache_ack_o),
.wb_m0_vcache_adr_i (wb_m0_vcache_adr_i[31:0]),
.wb_m0_vcache_dat_i (wb_m0_vcache_dat_i[31:0]),
.wb_m0_vcache_sel_i (wb_m0_vcache_sel_i[3:0]),
.wb_m0_vcache_cyc_i (wb_m0_vcache_cyc_i),
.wb_m0_vcache_stb_i (wb_m0_vcache_stb_i),
.wb_m0_vcache_we_i (wb_m0_vcache_we_i),
.wb_m1_cpu_dat_o (wb_m1_cpu_dat_o[31:0]),
.wb_m1_cpu_ack_o (wb_m1_cpu_ack_o),
.wb_m1_cpu_adr_i (wb_m1_cpu_adr_i[31:0]),
.wb_m1_cpu_dat_i (wb_m1_cpu_dat_i[31:0]),
.wb_m1_cpu_sel_i (wb_m1_cpu_sel_i[3:0]),
.wb_m1_cpu_cyc_i (wb_m1_cpu_cyc_i),
.wb_m1_cpu_stb_i (wb_m1_cpu_stb_i),
.wb_m1_cpu_we_i (wb_m1_cpu_we_i)
//.wb_m1_cpu_gnt (wb_m1_cpu_gnt),
//.wb_m0_vcache_gnt (wb_m0_vcache_gnt)
);
cellram_ctrl
/* Use the simple flash interface */
#(
.cellram_read_cycles(4), // 70ns in cycles, at 50MHz 4=80ns
.cellram_write_cycles(4)) // 70ns in cycles, at 50Mhz 4=80ns
cellram_ctrl0
(
.wb_clk_i(clk_50mhz),
.wb_rst_i(rst),
.wb_adr_i(cellram_wb_adr_i),
.wb_dat_i(cellram_wb_dat_i),
.wb_stb_i(cellram_wb_stb_i),
.wb_cyc_i(cellram_wb_cyc_i),
.wb_we_i (cellram_wb_we_i ),
.wb_sel_i(cellram_wb_sel_i),
.wb_dat_o(cellram_wb_dat_o),
.wb_ack_o(cellram_wb_ack_o),
.wb_err_o(),
.wb_rty_o(),
.cellram_dq_io(cellram_dq_io),
.cellram_adr_o(cellram_adr_o),
.cellram_adv_n_o(cellram_adv_n_o),
.cellram_ce_n_o(cellram_ce_n_o),
.cellram_clk_o(cellram_clk_o),
.cellram_oe_n_o(cellram_oe_n_o),
.cellram_rst_n_o(),
.cellram_wait_i(cellram_wait_i),
.cellram_we_n_o(cellram_we_n_o),
.cellram_wp_n_o(),
.cellram_lb_n_o(cellram_lb_n_o),
.cellram_ub_n_o(cellram_ub_n_o),
.cellram_cre_o(cellram_cre_o)
);
MIO_BUS MIO_interface( .clk(clk_50mhz),
.rst(rst),
.BTN(botton_out),
.SW(SW_OK),
.mem_w(MIO_mem_w),
.Cpu_data2bus(MIO_data2bus), //data from CPU
.addr_bus(MIO_addr_bus),
.ram_data_out(ram_data_out),
.led_out(led_out),
.counter_out(counter_out),
.counter0_out(counter_OUT0),
.counter1_out(counter_OUT1),
.counter2_out(counter_OUT2),
.Cpu_data4bus(MIO_data4bus), //write to CPU
.ram_data_in(ram_data_in), //from CPU write to Memory
.ram_addr(ram_addr), //Memory Address signals
.data_ram_we(data_ram_we),
.GPIOf0000000_we(GPIOf0000000_we),
.GPIOe0000000_we(GPIOe0000000_we),
.counter_we(counter_we),
.Peripheral_in(Peripheral_in)
);
inout ps2_clk, ps2_dat;
wire ps2_clk, ps2_dat;
wire ps2_irq_o;
reg ps2_clk_trig, ps2_dat_trig;
always @(posedge clk_50mhz or posedge rst) begin
if(rst) begin
ps2_clk_trig <= 0;
ps2_dat_trig <= 0;
end else if(&clkdiv[20:0]) begin
ps2_clk_trig <= ~ps2_clk;
ps2_dat_trig <= ~ps2_dat;
end else begin
ps2_clk_trig <= ps2_clk_trig | ~ps2_clk;
ps2_dat_trig <= ps2_dat_trig | ~ps2_dat;
end
end
ps2_wb ps2_wb0 (
.wb_clk_i(clk_50mhz),
.wb_rst_i(rst),
.wb_dat_i(ps2_wb_dat_i),
.wb_dat_o(ps2_wb_dat_o),
.wb_adr_i(ps2_wb_adr_i),
.wb_stb_i(ps2_wb_stb_i),
.wb_we_i (ps2_wb_we_i),
.wb_ack_o(ps2_wb_ack_o),
.irq_o(ps2_irq_o),
.ps2_clk(ps2_clk),
.ps2_dat(ps2_dat)
);
//------Peripheral Driver-----------------------------------
/* GPIO out use on LEDs & Counter-Controler read and write addre=f0000000-ffffffff0
*/
led_Dev_IO Device_led( clk_io,
rst,
GPIOf0000000_we,
Peripheral_in,
Counter_set,
led_out,
GPIOf0
);
/* GPIO out use on 7-seg display & CPU state display addre=e0000000-efffffff */
seven_seg_Dev_IO Device_7seg( .clk(clk_io),
.rst(rst),
.GPIOe0000000_we(GPIOe0000000_we),
.Test(SW_OK[7:5]),
.disp_cpudata(Peripheral_in), //CPU data output
.Test_data0({2'b00,pc[31:2]}), //pc[31:2]
.Test_data1(counter_out), //counter
.Test_data2(Inst), //Inst
.Test_data3(addr_bus), //addr_bus
.Test_data4(Cpu_data2bus), //Cpu_data2bus;
.Test_data5(Cpu_data4bus), //Cpu_data4bus;
.Test_data6(pc), //pc;
.disp_num(disp_num)
);
Counter_x Counter_xx(.clk(clk_io),
.rst(rst),
.clk0(clkdiv[9]),
.clk1(clkdiv[10]),
.clk2(clkdiv[10]),
.counter_we(counter_we),
.counter_val(Peripheral_in),
.counter_ch(Counter_set),
.counter0_OUT(counter_OUT0),
.counter1_OUT(counter_OUT1),
.counter2_OUT(counter_OUT2),
.counter_out(counter_out)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// assign AN_SEL=(SW_OK[3]) ? digit_anode : digit_anode|(blinke&{clkdiv[24],clkdiv[24],clkdiv[24],clkdiv[24]});
always @(posedge Clk_CPU or posedge rst) begin : proc_
if(rst) begin
Ireq <= 0;
end else if(Iack) begin
Ireq <= 0;
end else begin
Ireq_hold <= ps2_irq_o;
if(!Ireq_hold && ps2_irq_o) Ireq <= 1;
end
end
//assign dpdot = {MIO_ready, BIU_req, mem_w, BIU_ready};
//assign dpdot = {cellram_mst_sel, mem_w, BIU_ready};//vga_gnt, cpu_gnt
assign dpdot = {Ireq, Iack | ps2_irq_o, mem_w | ps2_clk_trig, BIU_ready | ps2_dat_trig};
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_physical(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_202_0;
wire T_206;
wire T_207;
wire T_208;
wire T_209;
reg done;
reg [31:0] GEN_83;
wire T_212;
wire T_213;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
wire T_219;
wire T_220;
wire T_221;
wire [1:0] T_222;
wire [1:0] T_223;
wire [3:0] T_224;
wire [1:0] T_225;
wire [1:0] T_226;
wire [3:0] T_227;
wire [7:0] T_228;
wire [7:0] T_229;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_234;
wire T_236;
wire T_237;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_243;
wire T_244;
wire T_245;
wire T_248;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_251;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_256;
wire T_259;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_208;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_209;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = T_202_0;
assign io_op_ready = T_251;
assign io_rx_valid = done;
assign io_rx_bits = T_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_202_0 = 1'h1;
assign T_206 = txd[0];
assign T_207 = txd[1];
assign T_208 = txd[2];
assign T_209 = txd[3];
assign T_212 = done | last_d;
assign T_213 = ctrl_fmt_endian == 1'h0;
assign T_215 = buffer[1];
assign T_216 = buffer[2];
assign T_217 = buffer[3];
assign T_218 = buffer[4];
assign T_219 = buffer[5];
assign T_220 = buffer[6];
assign T_221 = buffer[7];
assign T_222 = {T_220,T_221};
assign T_223 = {T_218,T_219};
assign T_224 = {T_223,T_222};
assign T_225 = {T_216,T_217};
assign T_226 = {T_155,T_215};
assign T_227 = {T_226,T_225};
assign T_228 = {T_227,T_224};
assign T_229 = T_213 ? buffer : T_228;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_234 = stop == 1'h0;
assign T_236 = cref == 1'h0;
assign T_237 = cref ^ cinv;
assign GEN_3 = xfr ? T_237 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_236 : 1'h0;
assign GEN_6 = T_236 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_236 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_234 ? GEN_7 : cref;
assign GEN_13 = T_234 ? GEN_8 : sck;
assign GEN_14 = T_234 ? GEN_9 : 1'h0;
assign GEN_15 = T_234 ? GEN_10 : 1'h0;
assign GEN_16 = T_234 ? GEN_11 : {{4'd0}, scnt};
assign T_243 = scnt == 8'h1;
assign T_244 = beat & cref;
assign T_245 = T_244 & xfr;
assign T_248 = beat & T_236;
assign GEN_17 = T_248 ? 1'h1 : stop;
assign GEN_18 = T_248 ? 1'h0 : GEN_15;
assign GEN_19 = T_248 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_243 ? T_245 : 1'h0;
assign GEN_21 = T_243 ? GEN_17 : stop;
assign GEN_22 = T_243 ? GEN_18 : GEN_15;
assign GEN_23 = T_243 ? GEN_19 : GEN_13;
assign T_251 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_256 = 1'h0 == io_op_bits_fn;
assign T_259 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_256 ? buffer_in : T_180;
assign GEN_28 = T_256 ? cinv : GEN_23;
assign GEN_29 = T_256 ? 1'h1 : GEN_22;
assign GEN_30 = T_256 ? T_259 : T_212;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_256 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_212;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_251 ? GEN_40 : GEN_16;
assign GEN_54 = T_251 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_251 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_251 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_251 ? GEN_44 : xfr;
assign GEN_58 = T_251 ? GEN_45 : T_180;
assign GEN_59 = T_251 ? GEN_46 : GEN_23;
assign GEN_60 = T_251 ? GEN_47 : GEN_22;
assign GEN_61 = T_251 ? GEN_48 : T_212;
assign GEN_62 = T_251 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_251 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_251 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_256) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_256) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_251) begin
if (io_op_valid) begin
if (T_256) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_251) begin
if (io_op_valid) begin
xfr <= T_256;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_234) begin
if (beat) begin
cref <= T_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_251) begin
if (io_op_valid) begin
if (T_256) begin
done <= T_259;
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
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