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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_FUNCTIONAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:33:50 11/11/2015
// Design Name:
// Module Name: GameWithSound
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GameWithSound(input clk25, input Reset,
input [9:0] xpos,
input [9:0] ypos,
input rota,
input rotb,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output Speaker);
reg PlayAgain;
reg PlayAgain1;
reg [1:0] Choice, Choice1;
// paddle movement
reg [8:0] paddlePosition;
reg [2:0] quadAr, quadBr;
reg [3:0] score;
wire [3:0] scoreOnesDigit;
wire [3:0] scoreTensDigit;
assign scoreOnesDigit = score % 10;
assign scoreTensDigit = score / 10;
wire tensDigit;
wire onesDigit;
wire digitPixel;
assign digitPixel = tensDigit || onesDigit; // 76
VGA7SegDisplay VGA7SegDisplayTens(9'd100,9'd300,xpos,ypos,scoreTensDigit,tensDigit);
VGA7SegDisplay VGA7SegDisplayOnes(9'd130,9'd300,xpos,ypos,scoreOnesDigit,onesDigit);
always @(posedge clk25) quadAr <= {quadAr[1:0], rota};
always @(posedge clk25) quadBr <= {quadBr[1:0], rotb};
always @(posedge clk25)
if(quadAr[2] ^ quadAr[1] ^ quadBr[2] ^ quadBr[1])
begin
if(quadAr[2] ^ quadBr[1]) begin
if(paddlePosition < 508) // make sure the value doesn't overflow
begin
paddlePosition <= paddlePosition + 3'd4;
Choice <= 2'b00;
PlayAgain <= 1;
end
else
PlayAgain <= 0;
end
else begin
if(paddlePosition > 2'd3) // make sure the value doesn't underflow
begin
paddlePosition <= paddlePosition - 3'd4;
Choice <= 2'b01;
PlayAgain <= 1;
end
else
PlayAgain <= 0;
end
end
// ball movement
reg [9:0] ballX;
reg [8:0] ballY;
reg ballXdir, ballYdir;
reg bounceX, bounceY;
wire endOfFrame = (xpos == 0 && ypos == 480);
always @(posedge clk25) begin
if (endOfFrame) begin // update ball position at end of each frame
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballX <= 480;
ballY <= 300;
end
else begin
if (ballXdir ^ bounceX)
ballX <= ballX + 2'd2;
else
ballX <= ballX - 2'd2;
if (ballYdir ^ bounceY)
ballY <= ballY + 2'd2;
else
ballY <= ballY - 2'd2;
end
end
end
// pixel color
reg [5:0] missTimer;
wire visible = (xpos < 640 && ypos < 480);
wire top = (visible && ypos <= 3);
wire bottom = (visible && ypos >= 476);
wire left = (visible && xpos <= 3);
wire right = (visible && xpos >= 636);
wire border = (visible && (left || right || top));
wire paddle = (xpos >= paddlePosition+4 && xpos <= paddlePosition+124 && ypos >= 440 && ypos <= 447);
wire ball = (xpos >= ballX && xpos <= ballX+7 && ypos >= ballY && ypos <= ballY+7);
wire background = (visible && !(border || paddle || ball));
wire checkerboard = (xpos[5] ^ ypos[5]);
wire missed = visible && missTimer != 0;
assign red = { missed || border || paddle, 2'b0 };
assign green = { !missed && (border || paddle || ball), digitPixel, digitPixel };
assign blue = { !missed && (border || ball) || digitPixel, background && checkerboard || digitPixel};
// ball collision
always @(posedge clk25) begin
if (!endOfFrame) begin
PlayAgain1 <= 0;
if (ball && (left || right))
bounceX <= 1;
if (ball && (top || bottom || (paddle && ballYdir)))
bounceY <= 1;
if (ball && bottom)
begin
missTimer <= 63;
score <= -1;
end
end
else begin
if (ballX == 0 && ballY == 0) begin // cheesy reset handling, assumes initial value of 0
ballXdir <= 1;
ballYdir <= 1;
bounceX <= 0;
bounceY <= 0;
score <= -1;
PlayAgain1 <= 0;
end
else begin
if (bounceX)
ballXdir <= ~ballXdir;
if (bounceY)
if(ballYdir) begin
score <= score + 1;
//Choice1 <= 2'b10;
PlayAgain1 <= 1;
ballYdir <= ~ballYdir;
end
else
begin
ballYdir <= ~ballYdir;
PlayAgain1 <= 0;
end
bounceX <= 0;
bounceY <= 0;
if (missTimer != 0)
missTimer <= missTimer - 1'b1;
end
end
end
PlaySound PlayMusic(PlayAgain|PlayAgain1, Speaker, Reset, clk25, Choice);
endmodule
|
`timescale 1ns/1ps
`include "alu.pkg"
module simple_alu(clk, reset_n, opcode_valid, opcode, data, done, result, overflow);
input clk;
input reset_n;
input opcode_valid;
input opcode;
input [DATA_WIDTH-1:0] data;
output done;
output [DATA_WIDTH-1:0] result;
output overflow;
logic overflow;
logic overflow_buf;
logic done;
logic [DATA_WIDTH-1:0] result;
parameter
RESET = 4'b0000,
IDLE = 4'b0001,
DATA_A = 4'b0010,
DATA_B = 4'b0011,
S_ADD = 4'b0100,
S_SUB = 4'b0101,
S_PAR = 4'b0110,
S_COMP = 4'b0111,
DONE = 4'b1000;
logic [3:0] State, NextState;
logic [DATA_WIDTH-1:0] A_Data, B_Data;
ALU_OPCODES opcode_def;
logic store_a_def, store_b_def;
logic [DATA_WIDTH-1:0] result_def;
logic [1:0] opcode_buf;
logic store_a, store_b;
logic start;
logic alu_done;
logic first;
always_ff @(posedge clk or reset_n)
begin
if(!reset_n)
begin
State = RESET;
end
else
begin
State = NextState;
end
end
always_comb
begin
case(State)
RESET:
begin
if(reset_n)
begin
NextState = IDLE;
end
else
begin
NextState = RESET;
end
end
IDLE:
begin
if(opcode_valid)
begin
NextState = DATA_A;
end
else
begin
NextState = IDLE;
end
end
DATA_A:
begin
if(opcode_valid)
begin
NextState = DATA_B;
opcode_buf[0] = opcode;
end
else
begin
NextState = IDLE;
end
end
DATA_B:
begin
opcode_buf[1] = opcode;
if(opcode_valid)
begin
case(opcode_buf)
ADD:
begin
NextState = S_ADD;
end
SUB:
begin
NextState = S_SUB;
end
PAR:
begin
NextState = S_PAR;
end
COMP:
begin
NextState = S_COMP;
end
endcase
end
else
begin
NextState = IDLE;
end
end
S_ADD:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = S_ADD;
end
end
S_SUB:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = S_SUB;
end
end
S_PAR:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = S_PAR;
end
end
S_COMP:
begin
if(alu_done)
begin
NextState = DONE;
end
else
begin
NextState = S_COMP;
end
end
DONE:
begin
NextState = IDLE;
end
endcase
//$display("done: %h \t opcode: %h \t opcode_valid: %h \t data: %h \t State: %h \t opcode_buf: %h \t result: %h \t overflow: %h",done, opcode, opcode_valid, data, State, opcode_buf, result, overflow);
end
always_comb
begin
case(State)
RESET:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
IDLE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_A:
begin
store_a_def = ON;
store_b_def = OFF;
opcode_def = OPCODE_ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
DATA_B:
begin
store_a_def = OFF;
store_b_def = ON;
opcode_def = OPCODE_ADD;
start = OFF;
result = 0;
done = OFF;
overflow = OFF;
end
S_ADD:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_ADD;
start = 1'b1;
result = 0;
done = OFF;
overflow = OFF;
end
S_SUB:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_SUB;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
S_PAR:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_PAR;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
S_COMP:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_COMP;
start = ON;
result = 0;
done = OFF;
overflow = OFF;
end
DONE:
begin
store_a_def = OFF;
store_b_def = OFF;
opcode_def = OPCODE_ADD;
start = OFF;
result = result_def;
done = ON;
overflow = overflow_buf;
end
endcase
end
alu_datapath alu_datapath (
.clk(clk),
.alu_data(data),
.opcode_value(opcode_def),
.store_a(store_a_def),
.store_b(store_b_def),
.start(start),
.alu_done(alu_done),
.result(result_def),
.overflow_def(overflow_buf)
);
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
//Date : Fri Jun 23 10:19:08 2017
//Host : dshwdev running 64-bit Ubuntu 16.04.2 LTS
//Command : generate_target fmrv32im_artya7.bd
//Design : fmrv32im_artya7
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "fmrv32im_artya7,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=fmrv32im_artya7,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=10,numReposBlks=9,numNonXlnxBlks=7,numHierBlks=1,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_bram_cntlr_cnt=1,synth_mode=OOC_per_BD}" *) (* HW_HANDOFF = "fmrv32im_artya7.hwdef" *)
module fmrv32im_artya7
(CLK100MHZ,
GPIO_i,
GPIO_o,
GPIO_ot,
UART_rx,
UART_tx);
input CLK100MHZ;
input [31:0]GPIO_i;
output [31:0]GPIO_o;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
wire CLK_1;
wire [0:0]High_dout;
wire [31:0]axilm_M_AXI_ARADDR;
wire [3:0]axilm_M_AXI_ARCACHE;
wire [2:0]axilm_M_AXI_ARPROT;
wire axilm_M_AXI_ARREADY;
wire axilm_M_AXI_ARVALID;
wire [31:0]axilm_M_AXI_AWADDR;
wire [3:0]axilm_M_AXI_AWCACHE;
wire [2:0]axilm_M_AXI_AWPROT;
wire axilm_M_AXI_AWREADY;
wire axilm_M_AXI_AWVALID;
wire axilm_M_AXI_BREADY;
wire [1:0]axilm_M_AXI_BRESP;
wire axilm_M_AXI_BVALID;
wire [31:0]axilm_M_AXI_RDATA;
wire axilm_M_AXI_RREADY;
wire [1:0]axilm_M_AXI_RRESP;
wire axilm_M_AXI_RVALID;
wire [31:0]axilm_M_AXI_WDATA;
wire axilm_M_AXI_WREADY;
wire [3:0]axilm_M_AXI_WSTRB;
wire axilm_M_AXI_WVALID;
wire [0:0]concat_dout;
wire [31:0]fmrv32im_axis_uart_0_GPIO_I;
wire [31:0]fmrv32im_axis_uart_0_GPIO_O;
wire [31:0]fmrv32im_axis_uart_0_GPIO_OT;
wire fmrv32im_axis_uart_0_INTERRUPT;
wire fmrv32im_axis_uart_0_UART_RX;
wire fmrv32im_axis_uart_0_UART_TX;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_ADDR;
wire fmrv32im_core_PERIPHERAL_BUS_ENA;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_RDATA;
wire fmrv32im_core_PERIPHERAL_BUS_WAIT;
wire [31:0]fmrv32im_core_PERIPHERAL_BUS_WDATA;
wire [3:0]fmrv32im_core_PERIPHERAL_BUS_WSTB;
assign CLK_1 = CLK100MHZ;
assign GPIO_o[31:0] = fmrv32im_axis_uart_0_GPIO_O;
assign GPIO_ot[31:0] = fmrv32im_axis_uart_0_GPIO_OT;
assign UART_tx = fmrv32im_axis_uart_0_UART_TX;
assign fmrv32im_axis_uart_0_GPIO_I = GPIO_i[31:0];
assign fmrv32im_axis_uart_0_UART_RX = UART_rx;
fmrv32im_artya7_xlconstant_0_0 High
(.dout(High_dout));
fmrv32im_artya7_fmrv32im_axilm_0_0 axi_lite_master
(.BUS_ADDR(fmrv32im_core_PERIPHERAL_BUS_ADDR),
.BUS_ENA(fmrv32im_core_PERIPHERAL_BUS_ENA),
.BUS_RDATA(fmrv32im_core_PERIPHERAL_BUS_RDATA),
.BUS_WAIT(fmrv32im_core_PERIPHERAL_BUS_WAIT),
.BUS_WDATA(fmrv32im_core_PERIPHERAL_BUS_WDATA),
.BUS_WSTB(fmrv32im_core_PERIPHERAL_BUS_WSTB),
.CLK(CLK_1),
.M_AXI_ARADDR(axilm_M_AXI_ARADDR),
.M_AXI_ARCACHE(axilm_M_AXI_ARCACHE),
.M_AXI_ARPROT(axilm_M_AXI_ARPROT),
.M_AXI_ARREADY(axilm_M_AXI_ARREADY),
.M_AXI_ARVALID(axilm_M_AXI_ARVALID),
.M_AXI_AWADDR(axilm_M_AXI_AWADDR),
.M_AXI_AWCACHE(axilm_M_AXI_AWCACHE),
.M_AXI_AWPROT(axilm_M_AXI_AWPROT),
.M_AXI_AWREADY(axilm_M_AXI_AWREADY),
.M_AXI_AWVALID(axilm_M_AXI_AWVALID),
.M_AXI_BREADY(axilm_M_AXI_BREADY),
.M_AXI_BRESP(axilm_M_AXI_BRESP),
.M_AXI_BVALID(axilm_M_AXI_BVALID),
.M_AXI_RDATA(axilm_M_AXI_RDATA),
.M_AXI_RREADY(axilm_M_AXI_RREADY),
.M_AXI_RRESP(axilm_M_AXI_RRESP),
.M_AXI_RVALID(axilm_M_AXI_RVALID),
.M_AXI_WDATA(axilm_M_AXI_WDATA),
.M_AXI_WREADY(axilm_M_AXI_WREADY),
.M_AXI_WSTRB(axilm_M_AXI_WSTRB),
.M_AXI_WVALID(axilm_M_AXI_WVALID),
.RST_N(High_dout));
fmrv32im_artya7_xlconcat_0_0 concat
(.In0(fmrv32im_axis_uart_0_INTERRUPT),
.dout(concat_dout));
fmrv32im_core_imp_14DVYUT fmrv32im_core
(.CLK(CLK_1),
.INT_IN(concat_dout),
.PERIPHERAL_bus_addr(fmrv32im_core_PERIPHERAL_BUS_ADDR),
.PERIPHERAL_bus_ena(fmrv32im_core_PERIPHERAL_BUS_ENA),
.PERIPHERAL_bus_rdata(fmrv32im_core_PERIPHERAL_BUS_RDATA),
.PERIPHERAL_bus_wait(fmrv32im_core_PERIPHERAL_BUS_WAIT),
.PERIPHERAL_bus_wdata(fmrv32im_core_PERIPHERAL_BUS_WDATA),
.PERIPHERAL_bus_wstb(fmrv32im_core_PERIPHERAL_BUS_WSTB),
.RD_REQ_req_mem_addr(1'b0),
.RD_REQ_req_mem_rdata(1'b0),
.RD_REQ_req_mem_we(1'b0),
.RD_REQ_req_ready(1'b0),
.RST_N(High_dout),
.WR_REQ_req_mem_addr(1'b0),
.WR_REQ_req_ready(1'b0));
fmrv32im_artya7_fmrv32im_axis_uart_0_1 uart
(.CLK(CLK_1),
.GPIO_I(fmrv32im_axis_uart_0_GPIO_I),
.GPIO_O(fmrv32im_axis_uart_0_GPIO_O),
.GPIO_OT(fmrv32im_axis_uart_0_GPIO_OT),
.INTERRUPT(fmrv32im_axis_uart_0_INTERRUPT),
.RST_N(High_dout),
.RXD(fmrv32im_axis_uart_0_UART_RX),
.S_AXI_ARADDR(axilm_M_AXI_ARADDR[15:0]),
.S_AXI_ARCACHE(axilm_M_AXI_ARCACHE),
.S_AXI_ARPROT(axilm_M_AXI_ARPROT),
.S_AXI_ARREADY(axilm_M_AXI_ARREADY),
.S_AXI_ARVALID(axilm_M_AXI_ARVALID),
.S_AXI_AWADDR(axilm_M_AXI_AWADDR[15:0]),
.S_AXI_AWCACHE(axilm_M_AXI_AWCACHE),
.S_AXI_AWPROT(axilm_M_AXI_AWPROT),
.S_AXI_AWREADY(axilm_M_AXI_AWREADY),
.S_AXI_AWVALID(axilm_M_AXI_AWVALID),
.S_AXI_BREADY(axilm_M_AXI_BREADY),
.S_AXI_BRESP(axilm_M_AXI_BRESP),
.S_AXI_BVALID(axilm_M_AXI_BVALID),
.S_AXI_RDATA(axilm_M_AXI_RDATA),
.S_AXI_RREADY(axilm_M_AXI_RREADY),
.S_AXI_RRESP(axilm_M_AXI_RRESP),
.S_AXI_RVALID(axilm_M_AXI_RVALID),
.S_AXI_WDATA(axilm_M_AXI_WDATA),
.S_AXI_WREADY(axilm_M_AXI_WREADY),
.S_AXI_WSTRB(axilm_M_AXI_WSTRB),
.S_AXI_WVALID(axilm_M_AXI_WVALID),
.TXD(fmrv32im_axis_uart_0_UART_TX));
endmodule
module fmrv32im_core_imp_14DVYUT
(CLK,
INT_IN,
PERIPHERAL_bus_addr,
PERIPHERAL_bus_ena,
PERIPHERAL_bus_rdata,
PERIPHERAL_bus_wait,
PERIPHERAL_bus_wdata,
PERIPHERAL_bus_wstb,
RD_REQ_req_addr,
RD_REQ_req_len,
RD_REQ_req_mem_addr,
RD_REQ_req_mem_rdata,
RD_REQ_req_mem_we,
RD_REQ_req_ready,
RD_REQ_req_start,
RST_N,
WR_REQ_req_addr,
WR_REQ_req_len,
WR_REQ_req_mem_addr,
WR_REQ_req_mem_wdata,
WR_REQ_req_ready,
WR_REQ_req_start);
input CLK;
input [0:0]INT_IN;
output [31:0]PERIPHERAL_bus_addr;
output PERIPHERAL_bus_ena;
input [31:0]PERIPHERAL_bus_rdata;
input PERIPHERAL_bus_wait;
output [31:0]PERIPHERAL_bus_wdata;
output [3:0]PERIPHERAL_bus_wstb;
output RD_REQ_req_addr;
output RD_REQ_req_len;
input RD_REQ_req_mem_addr;
input RD_REQ_req_mem_rdata;
input RD_REQ_req_mem_we;
input RD_REQ_req_ready;
output RD_REQ_req_start;
input RST_N;
output WR_REQ_req_addr;
output WR_REQ_req_len;
input WR_REQ_req_mem_addr;
output WR_REQ_req_mem_wdata;
input WR_REQ_req_ready;
output WR_REQ_req_start;
wire CLK_1;
wire [31:0]Conn1_REQ_ADDR;
wire [15:0]Conn1_REQ_LEN;
wire Conn1_REQ_MEM_ADDR;
wire Conn1_REQ_MEM_RDATA;
wire Conn1_REQ_MEM_WE;
wire Conn1_REQ_READY;
wire Conn1_REQ_START;
wire [31:0]Conn2_REQ_ADDR;
wire [15:0]Conn2_REQ_LEN;
wire Conn2_REQ_MEM_ADDR;
wire [31:0]Conn2_REQ_MEM_WDATA;
wire Conn2_REQ_READY;
wire Conn2_REQ_START;
wire [31:0]Conn3_BUS_ADDR;
wire Conn3_BUS_ENA;
wire [31:0]Conn3_BUS_RDATA;
wire Conn3_BUS_WAIT;
wire [31:0]Conn3_BUS_WDATA;
wire [3:0]Conn3_BUS_WSTB;
wire [0:0]INT_IN_1;
wire RST_N_1;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA;
wire dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT;
wire [31:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA;
wire [3:0]dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB;
wire [3:0]dbussel_upgraded_ipi_PLIC_BUS_ADDR;
wire [31:0]dbussel_upgraded_ipi_PLIC_BUS_RDATA;
wire [31:0]dbussel_upgraded_ipi_PLIC_BUS_WDATA;
wire dbussel_upgraded_ipi_PLIC_BUS_WE;
wire [3:0]dbussel_upgraded_ipi_TIMER_BUS_ADDR;
wire [31:0]dbussel_upgraded_ipi_TIMER_BUS_RDATA;
wire [31:0]dbussel_upgraded_ipi_TIMER_BUS_WDATA;
wire dbussel_upgraded_ipi_TIMER_BUS_WE;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_ADDR;
wire fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT;
wire fmrv32im_D_MEM_BUS_MEM_ENA;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_RDATA;
wire fmrv32im_D_MEM_BUS_MEM_WAIT;
wire [31:0]fmrv32im_D_MEM_BUS_MEM_WDATA;
wire [3:0]fmrv32im_D_MEM_BUS_MEM_WSTB;
wire [31:0]fmrv32im_I_MEM_BUS_MEM_ADDR;
wire fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT;
wire fmrv32im_I_MEM_BUS_MEM_ENA;
wire [31:0]fmrv32im_I_MEM_BUS_MEM_RDATA;
wire fmrv32im_I_MEM_BUS_MEM_WAIT;
wire fmrv32im_plic_0_INT_OUT;
wire timer_EXPIRED;
assign CLK_1 = CLK;
assign Conn1_REQ_MEM_ADDR = RD_REQ_req_mem_addr;
assign Conn1_REQ_MEM_RDATA = RD_REQ_req_mem_rdata;
assign Conn1_REQ_MEM_WE = RD_REQ_req_mem_we;
assign Conn1_REQ_READY = RD_REQ_req_ready;
assign Conn2_REQ_MEM_ADDR = WR_REQ_req_mem_addr;
assign Conn2_REQ_READY = WR_REQ_req_ready;
assign Conn3_BUS_RDATA = PERIPHERAL_bus_rdata[31:0];
assign Conn3_BUS_WAIT = PERIPHERAL_bus_wait;
assign INT_IN_1 = INT_IN[0];
assign PERIPHERAL_bus_addr[31:0] = Conn3_BUS_ADDR;
assign PERIPHERAL_bus_ena = Conn3_BUS_ENA;
assign PERIPHERAL_bus_wdata[31:0] = Conn3_BUS_WDATA;
assign PERIPHERAL_bus_wstb[3:0] = Conn3_BUS_WSTB;
assign RD_REQ_req_addr = Conn1_REQ_ADDR[0];
assign RD_REQ_req_len = Conn1_REQ_LEN[0];
assign RD_REQ_req_start = Conn1_REQ_START;
assign RST_N_1 = RST_N;
assign WR_REQ_req_addr = Conn2_REQ_ADDR[0];
assign WR_REQ_req_len = Conn2_REQ_LEN[0];
assign WR_REQ_req_mem_wdata = Conn2_REQ_MEM_WDATA[0];
assign WR_REQ_req_start = Conn2_REQ_START;
fmrv32im_artya7_fmrv32im_cache_0_0 cache
(.CLK(CLK_1),
.D_MEM_ADDR(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB),
.I_MEM_ADDR(fmrv32im_I_MEM_BUS_MEM_ADDR),
.I_MEM_BADMEM_EXCPT(fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT),
.I_MEM_ENA(fmrv32im_I_MEM_BUS_MEM_ENA),
.I_MEM_RDATA(fmrv32im_I_MEM_BUS_MEM_RDATA),
.I_MEM_WAIT(fmrv32im_I_MEM_BUS_MEM_WAIT),
.RD_REQ_ADDR(Conn1_REQ_ADDR),
.RD_REQ_LEN(Conn1_REQ_LEN),
.RD_REQ_MEM_ADDR({Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR,Conn1_REQ_MEM_ADDR}),
.RD_REQ_MEM_RDATA({Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA,Conn1_REQ_MEM_RDATA}),
.RD_REQ_MEM_WE(Conn1_REQ_MEM_WE),
.RD_REQ_READY(Conn1_REQ_READY),
.RD_REQ_START(Conn1_REQ_START),
.RST_N(RST_N_1),
.WR_REQ_ADDR(Conn2_REQ_ADDR),
.WR_REQ_LEN(Conn2_REQ_LEN),
.WR_REQ_MEM_ADDR({Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR,Conn2_REQ_MEM_ADDR}),
.WR_REQ_MEM_WDATA(Conn2_REQ_MEM_WDATA),
.WR_REQ_READY(Conn2_REQ_READY),
.WR_REQ_START(Conn2_REQ_START));
fmrv32im_artya7_dbussel_upgraded_ipi_0 dbussel
(.C_MEM_ADDR(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ADDR),
.C_MEM_BADMEM_EXCPT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_BADMEM_EXCPT),
.C_MEM_ENA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_ENA),
.C_MEM_RDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_RDATA),
.C_MEM_WAIT(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WAIT),
.C_MEM_WDATA(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WDATA),
.C_MEM_WSTB(dbussel_upgraded_ipi_C_MEM_BUS_MEM_WSTB),
.D_MEM_ADDR(fmrv32im_D_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(fmrv32im_D_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(fmrv32im_D_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(fmrv32im_D_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(fmrv32im_D_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(fmrv32im_D_MEM_BUS_MEM_WSTB),
.PERIPHERAL_BUS_ADDR(Conn3_BUS_ADDR),
.PERIPHERAL_BUS_ENA(Conn3_BUS_ENA),
.PERIPHERAL_BUS_RDATA(Conn3_BUS_RDATA),
.PERIPHERAL_BUS_WAIT(Conn3_BUS_WAIT),
.PERIPHERAL_BUS_WDATA(Conn3_BUS_WDATA),
.PERIPHERAL_BUS_WSTB(Conn3_BUS_WSTB),
.PLIC_BUS_ADDR(dbussel_upgraded_ipi_PLIC_BUS_ADDR),
.PLIC_BUS_RDATA(dbussel_upgraded_ipi_PLIC_BUS_RDATA),
.PLIC_BUS_WDATA(dbussel_upgraded_ipi_PLIC_BUS_WDATA),
.PLIC_BUS_WE(dbussel_upgraded_ipi_PLIC_BUS_WE),
.TIMER_BUS_ADDR(dbussel_upgraded_ipi_TIMER_BUS_ADDR),
.TIMER_BUS_RDATA(dbussel_upgraded_ipi_TIMER_BUS_RDATA),
.TIMER_BUS_WDATA(dbussel_upgraded_ipi_TIMER_BUS_WDATA),
.TIMER_BUS_WE(dbussel_upgraded_ipi_TIMER_BUS_WE));
fmrv32im_artya7_fmrv32im_0 fmrv32im
(.CLK(CLK_1),
.D_MEM_ADDR(fmrv32im_D_MEM_BUS_MEM_ADDR),
.D_MEM_BADMEM_EXCPT(fmrv32im_D_MEM_BUS_MEM_BADMEM_EXCPT),
.D_MEM_ENA(fmrv32im_D_MEM_BUS_MEM_ENA),
.D_MEM_RDATA(fmrv32im_D_MEM_BUS_MEM_RDATA),
.D_MEM_WAIT(fmrv32im_D_MEM_BUS_MEM_WAIT),
.D_MEM_WDATA(fmrv32im_D_MEM_BUS_MEM_WDATA),
.D_MEM_WSTB(fmrv32im_D_MEM_BUS_MEM_WSTB),
.EXT_INTERRUPT(fmrv32im_plic_0_INT_OUT),
.I_MEM_ADDR(fmrv32im_I_MEM_BUS_MEM_ADDR),
.I_MEM_BADMEM_EXCPT(fmrv32im_I_MEM_BUS_MEM_BADMEM_EXCPT),
.I_MEM_ENA(fmrv32im_I_MEM_BUS_MEM_ENA),
.I_MEM_RDATA(fmrv32im_I_MEM_BUS_MEM_RDATA),
.I_MEM_WAIT(fmrv32im_I_MEM_BUS_MEM_WAIT),
.RST_N(RST_N_1),
.TIMER_EXPIRED(timer_EXPIRED));
fmrv32im_artya7_fmrv32im_plic_0_1 plic
(.BUS_ADDR(dbussel_upgraded_ipi_PLIC_BUS_ADDR),
.BUS_RDATA(dbussel_upgraded_ipi_PLIC_BUS_RDATA),
.BUS_WDATA(dbussel_upgraded_ipi_PLIC_BUS_WDATA),
.BUS_WE(dbussel_upgraded_ipi_PLIC_BUS_WE),
.CLK(CLK_1),
.INT_IN(INT_IN_1),
.INT_OUT(fmrv32im_plic_0_INT_OUT),
.RST_N(RST_N_1));
fmrv32im_artya7_fmrv32im_timer_0_0 timer
(.BUS_ADDR(dbussel_upgraded_ipi_TIMER_BUS_ADDR),
.BUS_RDATA(dbussel_upgraded_ipi_TIMER_BUS_RDATA),
.BUS_WDATA(dbussel_upgraded_ipi_TIMER_BUS_WDATA),
.BUS_WE(dbussel_upgraded_ipi_TIMER_BUS_WE),
.CLK(CLK_1),
.EXPIRED(timer_EXPIRED),
.RST_N(RST_N_1));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_FUNCTIONAL_PP_V
|
/**
* @module instruction_typer
* @author sabertazimi
* @email [email protected]
* @brief instruction typer
* @input op op code
* @input funct funct code
* @output add instruction signal
* @output addi instruction signal
* @output addiu instruction signal
* @output addu instruction signal
* @output s_and instruction signal
* @output andi instruction signal
* @output sll instruction signal
* @output sra instruction signal
* @output srl instruction signal
* @output sub instruction signal
* @output s_or instruction signal
* @output ori instruction signal
* @output s_nor instruction signal
* @output lw instruction signal
* @output sw instruction signal
* @output beq instruction signal
* @output bne instruction signal
* @output slt instruction signal
* @output slti instruction signal
* @output sltu instruction signal
* @output j instruction signal
* @output jal instruction signal
* @output jr instruction signal
* @output syscall instruction signal
* @output divu instruction signal
* @output mflo instruction signal
* @output lb instruction signal
* @output bgtz instruction signal
*/
module instruction_typer
(
input [5:0] op,
input [5:0] funct,
output add,
output addi,
output addiu,
output addu,
output s_and,
output andi,
output sll,
output sra,
output srl,
output sub,
output s_or,
output ori,
output s_nor,
output lw,
output sw,
output beq,
output bne,
output slt,
output slti,
output sltu,
output j,
output jal,
output jr,
output syscall,
output divu,
output mflo,
output lb,
output bgtz
);
`include "defines.vh"
assign add = (op == 0 && funct == `ADD) ? 1 : 0;
assign addi = (op == `ADDI) ? 1 : 0;
assign addiu = (op == `ADDIU) ? 1 : 0;
assign addu = (op == 0 && funct == `ADDU) ? 1 : 0;
assign s_and = (op == 0 && funct == `AND) ? 1 : 0;
assign andi = (op == `ANDI) ? 1 : 0;
assign sll = (op == 0 && funct == `SLL) ? 1 : 0;
assign sra = (op == 0 && funct == `SRA) ? 1 : 0;
assign srl = (op == 0 && funct == `SRL) ? 1 : 0;
assign sub = (op == 0 && funct == `SUB) ? 1 : 0;
assign s_or = (op == 0 && funct == `OR) ? 1 : 0;
assign ori = (op == `ORI) ? 1 : 0;
assign s_nor = (op == 0 && funct == `NOR) ? 1 : 0;
assign lw = (op == `LW) ? 1 : 0;
assign sw = (op == `SW) ? 1 : 0;
assign beq = (op == `BEQ) ? 1 : 0;
assign bne = (op == `BNE) ? 1 : 0;
assign slt = (op == 0 && funct == `SLT) ? 1 : 0;
assign slti = (op == `SLTI) ? 1 : 0;
assign sltu = (op == 0 && funct == `SLTU) ? 1 : 0;
assign j = (op == `J) ? 1 : 0;
assign jal = (op == `JAL) ? 1 : 0;
assign jr = (op == 0 && funct == `JR) ? 1 : 0;
assign syscall = (op == 0 && funct == `SYSCALL) ? 1 : 0;
assign divu = (op == 0 && funct == `DIVU) ? 1 : 0;
assign mflo = (op == 0 && funct == `MFLO) ? 1 : 0;
assign lb = (op == `LB) ? 1 : 0;
assign bgtz = (op == `BGTZ) ? 1 : 0;
endmodule // instruction_typer
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_FUNCTIONAL_PP_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
// Parameters used for fsm states
parameter WIN_UNCHANGE_START = 1'b0;
parameter WIN_UNCHANGE_CHECK = 1'b1;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_test_expr;
reg r_state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
r_state <= WIN_UNCHANGE_START;
// r_test_expr deliberately not reset
end
else begin
r_test_expr <= test_expr;
case (r_state)
WIN_UNCHANGE_START: if (start_event == 1'b1) begin
r_state <= WIN_UNCHANGE_CHECK;
end
WIN_UNCHANGE_CHECK: if (end_event == 1'b1) begin
r_state <= WIN_UNCHANGE_START;
end
endcase
end
end
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression has changed value before the event window closes");
end
end
end
assign fire_2state_1 = ((r_state == WIN_UNCHANGE_CHECK) && (r_test_expr != test_expr));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
end
end
wire valid_start_event = ((start_event ^ start_event) == 1'b0);
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
wire valid_end_event = ((end_event ^ end_event) == 1'b0);
always @ (valid_start_event or r_state) begin
if (valid_start_event || (r_state != WIN_UNCHANGE_START)) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1; // start_event X when r_state is WIN_UNCHANGE_START
end
end
always @ (valid_test_expr or r_state or start_event) begin
if (valid_test_expr || !((r_state == WIN_UNCHANGE_CHECK) || start_event)) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // test_expr X when r_state is CHECK or start_event high
end
end
always @ (valid_end_event or r_state) begin
if (valid_end_event || (r_state != WIN_UNCHANGE_CHECK)) begin
fire_xcheck_3 = 1'b0;
end
else begin
fire_xcheck_3 = 1'b1; // end_event X when r_state is WIN_UNCHANGE_CHECK
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_cover_1) begin
ovl_cover_t("window_open covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("window covered"); // basic
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (start_event == 1'b1) && (r_state == WIN_UNCHANGE_START));
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && (end_event == 1'b1) && (r_state == WIN_UNCHANGE_CHECK));
`endif // OVL_COVER_ON
|
/*
########################################################################
########################################################################
*/
module ecfg_if (/*AUTOARG*/
// Outputs
mi_mmu_en, mi_dma_en, mi_cfg_en, mi_we, mi_addr, mi_din,
access_out, packet_out,
// Inputs
clk, access_in, packet_in, mi_dout0, mi_dout1, mi_dout2, mi_dout3,
wait_in
);
parameter RX = 0; //0,1
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h810;
/********************************/
/*Clocks/reset */
/********************************/
input clk;
/********************************/
/*Incoming Packet */
/********************************/
input access_in;
input [PW-1:0] packet_in;
/********************************/
/* Register Interface */
/********************************/
output mi_mmu_en;
output mi_dma_en;
output mi_cfg_en;
output mi_we;
output [14:0] mi_addr;
output [63:0] mi_din;
input [63:0] mi_dout0;
input [63:0] mi_dout1;
input [63:0] mi_dout2;
input [63:0] mi_dout3;
/********************************/
/* Outgoing Packet */
/********************************/
output access_out;
output [PW-1:0] packet_out;
input wait_in; //incoming wait
//wires
wire [31:0] dstaddr;
wire [31:0] data;
wire [31:0] srcaddr;
wire [1:0] datamode;
wire [3:0] ctrlmode;
wire [63:0] mi_dout_mux;
wire mi_rd;
wire access_forward;
wire rxsel;
wire mi_en;
//regs;
reg access_out;
reg [31:0] dstaddr_reg;
reg [31:0] srcaddr_reg;
reg [1:0] datamode_reg;
reg [3:0] ctrlmode_reg;
reg write_reg;
reg readback_reg;
reg [31:0] data_reg;
wire [31:0] data_out;
//parameter didn't seem to work
assign rxsel = RX;
//splicing packet
packet2emesh p2e (.access_out (),
.write_out (write),
.datamode_out (datamode[1:0] ),
.ctrlmode_out (ctrlmode[3:0]),
.dstaddr_out (dstaddr[31:0]),
.data_out (data[31:0]),
.srcaddr_out (srcaddr[31:0]),
.packet_in (packet_in[PW-1:0])
);
//ENABLE SIGNALS
assign mi_match = access_in & (dstaddr[31:20]==ID);
//config select (group 2 and 3)
assign mi_cfg_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]=={2'b01,rxsel});
//dma select (group 5)
assign mi_dma_en = mi_match &
(dstaddr[19:16]==4'hF) &
(dstaddr[10:8]==3'h5) &
(dstaddr[5]==rxsel);
//mmu select
assign mi_mmu_en = mi_match &
(dstaddr[19:16]==4'hE) &
(dstaddr[15]==rxsel);
//read/write indicator
assign mi_en = (mi_mmu_en | mi_cfg_en | mi_dma_en);
assign mi_rd = ~write & mi_en;
assign mi_we = write & mi_en;
//signal to carry transaction from ETX to ERX block through fifo_cdc
assign mi_rx_en = mi_match &
((dstaddr[19:16]==4'hE) | (dstaddr[19:16]==4'hF)) &
~mi_en;
//ADDR
assign mi_addr[14:0] = dstaddr[14:0];
//DIN
assign mi_din[63:0] = {srcaddr[31:0], data[31:0]};
//READBACK MUX (inputs should be zero if not used)
assign mi_dout_mux[63:0] = mi_dout0[63:0] |
mi_dout1[63:0] |
mi_dout2[63:0] |
mi_dout3[63:0];
//Access out packet
assign access_forward = (mi_rx_en | mi_rd);
always @ (posedge clk)
if(~wait_in)
access_out <= access_forward;
always @ (posedge clk)
if(~wait_in)
begin
readback_reg <= mi_rd;
write_reg <= (mi_rx_en & write) | mi_rd;
datamode_reg[1:0] <= datamode[1:0];
ctrlmode_reg[3:0] <= ctrlmode[3:0];
dstaddr_reg[31:0] <= mi_rx_en ? dstaddr[31:0] : srcaddr[31:0];
data_reg[31:0] <= data[31:0];
srcaddr_reg[31:0] <= mi_rx_en ? srcaddr[31:0] : mi_dout_mux[63:32];
end
assign data_out[31:0] = readback_reg ? mi_dout_mux[31:0] : data_reg[31:0];
//Create packet
emesh2packet e2p (.packet_out (packet_out[PW-1:0]),
.access_in (1'b1),
.write_in (write_reg),
.datamode_in (datamode_reg[1:0]),
.ctrlmode_in (ctrlmode_reg[3:0]),
.dstaddr_in (dstaddr_reg[AW-1:0]),
.data_in (data_out[31:0]),
.srcaddr_in (srcaddr_reg[AW-1:0])
);
endmodule // ecfg_if
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Ultrascale) takes a single stream of
// AXI packets and provides the completion packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "ultrascale.vh"
module rxr_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: CQ
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
// Interface: RXR Engine
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP
);
// Width of the Byte Enable Shift register
localparam C_RX_BE_W = (`SIG_FBE_W + `SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 0;
localparam C_RX_OUTPUT_STAGES = 2; // Should always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// CYCLE = LOW ORDER BIT (INDEX) / C_PCI_DATA_WIDTH
localparam C_RX_ADDRDW0_CYCLE = (`UPKT_RXR_ADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW1_CYCLE = (`UPKT_RXR_ADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_CYCLE = (`UPKT_RXR_METADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`UPKT_RXR_METADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_PAYLOAD_CYCLE = (`UPKT_RXR_PAYLOAD_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_BE_CYCLE = C_RX_INPUT_STAGES; // Available on the first cycle (as per the spec)
localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_ADDRDW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`UPKT_RXR_METADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_BE_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES;
// Mask width of the calculated SOF/EOF fields
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
wire wMAxisCqSop;
wire wMAxisCqTlast;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrEop;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrDataValid;
wire [(C_RX_PIPELINE_DEPTH+1)*C_RX_BE_W-1:0] wRxSrBe;
wire [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] wRxSrData;
wire wRxrDataValid;
wire wRxrDataReady; // Pinned High
wire wRxrDataEndFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
wire wRxrDataStartFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire [127:0] wRxrHdr;
wire [`SIG_TYPE_W-1:0] wRxrType;
wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe;
wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe;
wire [C_RX_BE_W-1:0] wRxrBe;
wire [`SIG_BARDECODE_W-1:0] wRxrBarDecoded;
wire [127:0] wHdr;
wire wEndFlag;
wire wEndFlagLastCycle;
wire _wEndFlag;
wire [C_OFFSET_WIDTH-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wStartFlag;
wire wStartFlag;
wire [1:0] wStartFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [C_OFFSET_WIDTH-1:0] wStartOffset;
wire [C_RX_BE_W-1:0] wByteEnables;
wire [`SIG_BARDECODE_W-1:0] wBarDecoded;
wire wHasPayload;
wire [`SIG_TYPE_W-1:0] wType;
reg rValid,_rValid;
assign wMAxisCqSop = M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_SOP_R];
assign wMAxisCqTlast = M_AXIS_CQ_TLAST;
assign wBarDecoded = (8'b0000_0001 << wHdr[`UPKT_RXR_BARID_R]);
// We assert the end flag on the last cycle of a packet, however on single
// cycle packets we need to check that there wasn't an end flag last cycle
// (because wStartFlag will take priority when setting rValid) so we can
// deassert rValid if necessary.
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES];
assign wEndFlagLastCycle = wRxSrEop[C_RX_INPUT_STAGES + C_RX_COMPUTATION_STAGES + 1];
/* verilator lint_off WIDTH */
assign wStartOffset = 4;
assign wEndOffset = wHdr[`UPKT_RXR_LENGTH_I +: C_OFFSET_WIDTH] + ((`UPKT_RXR_MAXHDR_W-32)/32);
/* verilator lint_on WIDTH */
// Output assignments. See the header file derived from the user
// guide for indices.
assign RXR_META_EP = wRxrHdr[`UPKT_RXR_EP_R];
assign RXR_META_LENGTH = wRxrHdr[`UPKT_RXR_LENGTH_I+:`SIG_LEN_W];// The top three bits are ignored (fine)
assign RXR_META_ATTR = wRxrHdr[`UPKT_RXR_ATTR_R];
assign RXR_META_TC = wRxrHdr[`UPKT_RXR_TC_R];
assign RXR_META_TYPE = wRxrType;
assign RXR_META_REQUESTER_ID = wRxrHdr[`UPKT_RXR_REQID_R];
assign RXR_META_TAG = wRxrHdr[`UPKT_RXR_TAG_R];
assign RXR_META_FDWBE = wRxrMetaFdwbe;
assign RXR_META_LDWBE = wRxrMetaLdwbe;
assign RXR_META_ADDR = {wRxrHdr[`UPKT_RXR_ADDR_R],2'b0};
assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
assign RXR_DATA_START_OFFSET = 0;
assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
assign RXR_DATA_END_OFFSET = wEndOffset;
assign RXR_META_BAR_DECODED = wRxrBarDecoded;
assign RXR_DATA_VALID = wRxrDataValid;
assign RXR_DATA = wRxSrData[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign M_AXIS_CQ_TREADY = 1'b1;
assign wType = upkt_to_trellis_type({wHdr[`UPKT_RXR_TYPE_R], wHdr[`UPKT_RXR_LENGTH_R] != 0});
assign _wEndFlag = wRxSrEop[C_RX_INPUT_STAGES];
assign wEndFlag = wRxSrEop[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
assign wHasPayload = ~wType[`TRLS_TYPE_PAY_I];
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
generate
if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~rValid;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~rValid;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & wRxSrEop[C_RX_INPUT_STAGES]; // No Payload
end else begin // 256
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(RST_IN) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
register
#(
// Parameters
.C_WIDTH (32))
meta_DW1_register
(
// Outputs
.RD_DATA (wHdr[127:96]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (wRxSrData[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]));
register
#(
// Parameters
.C_WIDTH (32))
metadata_DW0_register
(
// Outputs
.RD_DATA (wHdr[95:64]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (wRxSrData[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]));
register
#(
// Parameters
.C_WIDTH (32))
addr_DW1_register
(
// Outputs
.RD_DATA (wHdr[63:32]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (wRxSrData[C_RX_ADDRDW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]));
register
#(
// Parameters
.C_WIDTH (32))
addr_DW0_register
(
// Outputs
.RD_DATA (wHdr[31:0]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (wRxSrData[C_RX_ADDRDW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]));
register
#(
// Parameters
.C_WIDTH (C_RX_BE_W))
be_register
(
// Outputs
.RD_DATA (wByteEnables),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (wRxSrBe[C_RX_BE_INDEX +: C_RX_BE_W]),
.WR_EN (wRxSrSop[C_RX_BE_CYCLE]));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_PCI_DATA_WIDTH)
/*AUTOINSTPARAM*/)
data_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrData),
// Inputs
.WR_DATA (M_AXIS_CQ_TDATA),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (wMAxisCqSop & M_AXIS_CQ_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// End Flag Shift Register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
eop_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrEop),
// Inputs
.WR_DATA (wMAxisCqTlast),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Data Valid Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1)
/*AUTOINSTPARAM*/)
valid_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (M_AXIS_CQ_TVALID),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// Shift register for input data with output taps for each delayed
// cycle.
shiftreg
#(
// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (C_RX_BE_W)
/*AUTOINSTPARAM*/)
be_shiftreg_inst
(
// Outputs
.RD_DATA (wRxSrBe),
// Inputs
.WR_DATA (M_AXIS_CQ_TUSER[`UPKT_CQ_TUSER_BE_R]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
register
#(
// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(
// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | wHasPayload}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxrDataWordEnable),
// Inputs
.RST_IN (~rValid | wHasPayload),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXR_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxrDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end
endgenerate
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`UPKT_RXR_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH) + `SIG_LBE_W + `SIG_FBE_W + `SIG_BARDECODE_W + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(
// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxrHdr,wRxrBarDecoded,wRxrType,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset,wRxrMetaLdwbe,wRxrMetaFdwbe}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({wHdr,wBarDecoded,wType,wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0],wByteEnables}),
.WR_DATA_VALID (rValid),
.RD_DATA_READY (1'b1),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/")
// End:
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_mult2(
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output [25:0] p
);
DSP48 #(
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
.B_INPUT("DIRECT"), // B input DIRECT from fabric or CASCADE from another DSP48
.CARRYINREG(0), // Number of pipeline registers for the CARRYIN input, 0 or 1
.CARRYINSELREG(0), // Number of pipeline registers for the CARRYINSEL, 0 or 1
.CREG(0), // Number of pipeline registers on the C input, 0 or 1
.LEGACY_MODE("MULT18X18"), // Backward compatibility, NONE, MULT18X18 or MULT18X18S
.MREG(0), // Number of multiplier pipeline registers, 0 or 1
.OPMODEREG(0), // Number of pipeline regsiters on OPMODE input, 0 or 1
.PREG(1), // Number of pipeline registers on the P output, 0 or 1
.SUBTRACTREG(0) // Number of pipeline registers on the SUBTRACT input, 0 or 1
) DSP48_inst (
.BCOUT(), // 18-bit B cascade output
.P(p), // 48-bit product output
.PCOUT(), // 48-bit cascade output
.A(a), // 18-bit A data input
.B(b), // 18-bit B data input
.BCIN(18'd0), // 18-bit B cascade input
.C(48'd0), // 48-bit cascade input
.CARRYIN(1'b0), // Carry input signal
.CARRYINSEL(2'd0), // 2-bit carry input select
.CEA(ce), // A data clock enable input
.CEB(ce), // B data clock enable input
.CEC(1'b1), // C data clock enable input
.CECARRYIN(1'b1), // CARRYIN clock enable input
.CECINSUB(1'b1), // CINSUB clock enable input
.CECTRL(1'b1), // Clock Enable input for CTRL regsiters
.CEM(1'b1), // Clock Enable input for multiplier regsiters
.CEP(ce), // Clock Enable input for P regsiters
.CLK(sys_clk), // Clock input
.OPMODE(7'h35), // 7-bit operation mode input
.PCIN(48'd0), // 48-bit PCIN input
.RSTA(1'b0), // Reset input for A pipeline registers
.RSTB(1'b0), // Reset input for B pipeline registers
.RSTC(1'b0), // Reset input for C pipeline registers
.RSTCARRYIN(1'b0), // Reset input for CARRYIN registers
.RSTCTRL(1'b0), // Reset input for CTRL registers
.RSTM(1'b0), // Reset input for multiplier registers
.RSTP(1'b0), // Reset input for P pipeline registers
.SUBTRACT(1'b0) // SUBTRACT input
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_1_V
`define SKY130_FD_SC_MS__O211AI_1_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_1 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_1_V
|
// megafunction wizard: %DDR2 High Performance Controller v16.0%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// ram_controller_controller_phy
// ============================================================
// Generated by DDR2 High Performance Controller 16.0 [Altera, IP Toolbench 1.3.0 Build 211]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ram_controller (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs);
input [24:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [31:0] local_wdata;
input [3:0] local_be;
input [2:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [31:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [1:0] mem_dm;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [15:0] mem_dq;
inout [1:0] mem_dqs;
wire signal_wire0 = 1'b0;
wire [13:0] signal_wire1 = 14'b0;
wire [13:0] signal_wire2 = 14'b0;
wire [5:0] signal_wire3 = 6'b0;
wire [5:0] signal_wire4 = 6'b0;
wire signal_wire5 = 1'b0;
wire [15:0] signal_wire6 = 16'b0;
wire [1:0] signal_wire7 = 2'b0;
wire [1:0] signal_wire8 = 2'b0;
wire [1:0] signal_wire9 = 2'b0;
wire [1:0] signal_wire10 = 2'b0;
wire [1:0] signal_wire11 = 2'b0;
wire signal_wire12 = 1'b0;
wire signal_wire13 = 1'b0;
wire signal_wire14 = 1'b0;
wire signal_wire15 = 1'b0;
wire [3:0] signal_wire16 = 4'b0;
wire [2:0] signal_wire17 = 3'b0;
wire signal_wire18 = 1'b0;
wire [8:0] signal_wire19 = 9'b0;
wire [3:0] signal_wire20 = 4'b0;
wire signal_wire21 = 1'b0;
wire signal_wire22 = 1'b0;
wire signal_wire23 = 1'b0;
wire signal_wire24 = 1'b0;
wire signal_wire25 = 1'b0;
wire signal_wire26 = 1'b0;
wire signal_wire27 = 1'b0;
wire signal_wire28 = 1'b0;
ram_controller_controller_phy ram_controller_controller_phy_inst(
.local_address(local_address),
.local_write_req(local_write_req),
.local_read_req(local_read_req),
.local_burstbegin(local_burstbegin),
.local_wdata(local_wdata),
.local_be(local_be),
.local_size(local_size),
.local_refresh_req(signal_wire0),
.oct_ctl_rs_value(signal_wire1),
.oct_ctl_rt_value(signal_wire2),
.dqs_delay_ctrl_import(signal_wire3),
.dqs_offset_delay_ctrl(signal_wire4),
.hc_scan_enable_access(signal_wire5),
.hc_scan_enable_dq(signal_wire6),
.hc_scan_enable_dm(signal_wire7),
.hc_scan_enable_dqs(signal_wire8),
.hc_scan_enable_dqs_config(signal_wire9),
.hc_scan_din(signal_wire10),
.hc_scan_update(signal_wire11),
.hc_scan_ck(signal_wire12),
.pll_reconfig_write_param(signal_wire13),
.pll_reconfig_read_param(signal_wire14),
.pll_reconfig(signal_wire15),
.pll_reconfig_counter_type(signal_wire16),
.pll_reconfig_counter_param(signal_wire17),
.pll_reconfig_soft_reset_en_n(signal_wire18),
.pll_reconfig_data_in(signal_wire19),
.pll_phasecounterselect(signal_wire20),
.pll_phaseupdown(signal_wire21),
.pll_phasestep(signal_wire22),
.pll_reconfig_enable(signal_wire23),
.local_autopch_req(signal_wire24),
.local_self_rfsh_req(signal_wire25),
.local_self_rfsh_chip(signal_wire26),
.local_multicast_req(signal_wire27),
.local_refresh_chip(signal_wire28),
.global_reset_n(global_reset_n),
.pll_ref_clk(pll_ref_clk),
.soft_reset_n(soft_reset_n),
.local_ready(local_ready),
.local_rdata(local_rdata),
.local_rdata_valid(local_rdata_valid),
.local_refresh_ack(local_refresh_ack),
.local_init_done(local_init_done),
.reset_phy_clk_n(reset_phy_clk_n),
.dll_reference_clk(),
.dqs_delay_ctrl_export(),
.hc_scan_dout(),
.pll_reconfig_busy(),
.pll_reconfig_clk(),
.pll_reconfig_reset(),
.pll_reconfig_data_out(),
.pll_phase_done(),
.aux_scan_clk_reset_n(),
.aux_scan_clk(),
.local_self_rfsh_ack(),
.local_power_down_ack(),
.mem_odt(mem_odt),
.mem_cs_n(mem_cs_n),
.mem_cke(mem_cke),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_ras_n(mem_ras_n),
.mem_cas_n(mem_cas_n),
.mem_we_n(mem_we_n),
.mem_dm(mem_dm),
.mem_reset_n(),
.phy_clk(phy_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.aux_half_rate_clk(aux_half_rate_clk),
.reset_request_n(reset_request_n),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqsn(),
.ecc_interrupt()
);
endmodule
// =========================================================
// DDR2 High Performance Controller Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, DDR2 High Performance Controller Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="DDR2 SDRAM Controller with ALTMEMPHY" version="16.0" build="211" iptb_version="1.3.0 Build 211" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRControllerMVCModel" active_core="ram_controller_controller_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="133.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(20000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="50.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="133.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Full" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(7519 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR2 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="16" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="Micron" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="Custom (Micron MT47H64M8CB-3)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="13" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="40.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="105.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="37.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="240" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="340" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.36" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="8.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="450" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="8.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="50" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="266.667" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ngv110_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_num" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_data_reordering_type" value="INTER_BANK" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_starve_limit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "cfg_reorder_data" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="ODT Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast Exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="5.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="1.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="2.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="ram_controller_alt_mem_ddrx_controller_top" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "nativelink_excludes" value="ram_controller_phy_alt_mem_phy_seq.vhd,ram_controller_phy_alt_mem_phy_seq_wrapper.vhd,ram_controller_phy_alt_mem_phy_seq_wrapper.v" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="ram_controller_alt_mem_ddrx_controller_top.vo" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "native" value="verilog" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+ram_controller_alt_mem_phy_seq_wrapper;+ram_controller_alt_mem_phy_reconfig;+ram_controller_alt_mem_phy_pll;+ram_controller_phy_alt_mem_phy_delay --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/home/caleb/Sources/Telescope_Project/VFPIX-telescope-Code/DAQ_Firmware/ram_controller_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="ram_controller_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP4CE55F23C8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Cyclone IV E" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
// IPFS_FILES: ram_controller_alt_mem_ddrx_controller_top.v, alt_mem_ddrx_controller.v, alt_mem_ddrx_addr_cmd.v, alt_mem_ddrx_addr_cmd_wrap.v, alt_mem_ddrx_controller_st_top.v, alt_mem_ddrx_ddr2_odt_gen.v, alt_mem_ddrx_ddr3_odt_gen.v, alt_mem_ddrx_lpddr2_addr_cmd.v, alt_mem_ddrx_odt_gen.v, alt_mem_ddrx_rdwr_data_tmg.v, alt_mem_ddrx_arbiter.v, alt_mem_ddrx_burst_gen.v, alt_mem_ddrx_cmd_gen.v, alt_mem_ddrx_csr.v, alt_mem_ddrx_buffer.v, alt_mem_ddrx_buffer_manager.v, alt_mem_ddrx_burst_tracking.v, alt_mem_ddrx_dataid_manager.v, alt_mem_ddrx_fifo.v, alt_mem_ddrx_list.v, alt_mem_ddrx_rdata_path.v, alt_mem_ddrx_wdata_path.v, alt_mem_ddrx_define.iv, alt_mem_ddrx_ecc_decoder.v, alt_mem_ddrx_ecc_decoder_32_syn.v, alt_mem_ddrx_ecc_decoder_64_syn.v, alt_mem_ddrx_ecc_encoder.v, alt_mem_ddrx_ecc_encoder_32_syn.v, alt_mem_ddrx_ecc_encoder_64_syn.v, alt_mem_ddrx_ecc_encoder_decoder_wrapper.v, alt_mem_ddrx_input_if.v, alt_mem_ddrx_mm_st_converter.v, alt_mem_ddrx_rank_timer.v, alt_mem_ddrx_sideband.v, alt_mem_ddrx_tbp.v, alt_mem_ddrx_timing_param.v;
// RELATED_FILES: ram_controller_phy_alt_mem_phy_seq.vhd,ram_controller_phy_alt_mem_phy_seq_wrapper.vhd,ram_controller_phy_alt_mem_phy_seq_wrapper.v;
// =========================================================
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4b (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D_N ;
// Local signals
wire DN not0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_FUNCTIONAL_V
|
module MEM_WB (
input clk,
input rst,
input is_hold,
input[`RegAddrWidth-1:0] target_MEM,
input[`RegDataWidth-1:0] ALU_data_MEM,
input[`RegDataWidth-1:0] MEM_data_MEM,
input we_hi_MEM,
input we_lo_MEM,
input[`RegDataWidth-1:0] hi_MEM,
input[`RegDataWidth-1:0] lo_MEM,
input WriteReg_MEM,
input MemOrAlu_MEM,
output[`RegAddrWidth-1:0] target_WB,
output[`RegDataWidth-1:0] ALU_data_WB,
output[`RegDataWidth-1:0] MEM_data_WB,
output we_hi_WB,
output we_lo_WB,
output[`RegDataWidth-1:0] hi_WB,
output[`RegDataWidth-1:0] lo_WB,
output WriteReg_WB,
output MemOrAlu_WB
);
dffe #(.data_width(`RegAddrWidth)) target_holder(clk, rst, is_hold, target_MEM, target_WB);
dffe #(.data_width(`RegDataWidth)) ALU_data_holder(clk, rst, is_hold, ALU_data_MEM, ALU_data_WB);
dffe #(.data_width(`RegDataWidth)) MEM_data_out_holder(clk, rst, is_hold, MEM_data_MEM, MEM_data_WB);
dffe we_hi_holder(clk, rst, is_hold, we_hi_MEM, we_hi_WB);
dffe we_lo_holder(clk, rst, is_hold, we_lo_MEM, we_lo_WB);
dffe #(.data_width(`RegDataWidth)) hi_holder(clk, rst, is_hold, hi_MEM, hi_WB);
dffe #(.data_width(`RegDataWidth)) lo_holder(clk, rst, is_hold, lo_MEM, lo_WB);
dffe WriteReg_holder(clk, rst, is_hold, WriteReg_MEM, WriteReg_WB);
dffe MemOrAlu_holder(clk, rst, is_hold, MemOrAlu_MEM, MemOrAlu_WB);
endmodule
|
// This is a wrapper that maps the module ports from what mkCTop wants to see (as of 6/29/2010) into
// what the automation tools want to see, which is WIP compliance.
module mkOCApp(RST_N_rst_0,
RST_N_rst_1,
RST_N_rst_2,
RST_N_rst_3,
RST_N_rst_4,
RST_N_rst_5,
RST_N_rst_6,
RST_N_rst_7,
CLK,
RST_N,
wci_s_0_MCmd,
wci_s_0_MAddrSpace,
wci_s_0_MByteEn,
wci_s_0_MAddr,
wci_s_0_MData,
wci_s_0_SResp,
wci_s_0_SData,
wci_s_0_SThreadBusy,
wci_s_0_SFlag,
wci_s_0_MFlag,
wci_s_1_MCmd,
wci_s_1_MAddrSpace,
wci_s_1_MByteEn,
wci_s_1_MAddr,
wci_s_1_MData,
wci_s_1_SResp,
wci_s_1_SData,
wci_s_1_SThreadBusy,
wci_s_1_SFlag,
wci_s_1_MFlag,
wci_s_2_MCmd,
wci_s_2_MAddrSpace,
wci_s_2_MByteEn,
wci_s_2_MAddr,
wci_s_2_MData,
wci_s_2_SResp,
wci_s_2_SData,
wci_s_2_SThreadBusy,
wci_s_2_SFlag,
wci_s_2_MFlag,
wci_s_3_MCmd,
wci_s_3_MAddrSpace,
wci_s_3_MByteEn,
wci_s_3_MAddr,
wci_s_3_MData,
wci_s_3_SResp,
wci_s_3_SData,
wci_s_3_SThreadBusy,
wci_s_3_SFlag,
wci_s_3_MFlag,
wci_s_4_MCmd,
wci_s_4_MAddrSpace,
wci_s_4_MByteEn,
wci_s_4_MAddr,
wci_s_4_MData,
wci_s_4_SResp,
wci_s_4_SData,
wci_s_4_SThreadBusy,
wci_s_4_SFlag,
wci_s_4_MFlag,
wci_s_5_MCmd,
wci_s_5_MAddrSpace,
wci_s_5_MByteEn,
wci_s_5_MAddr,
wci_s_5_MData,
wci_s_5_SResp,
wci_s_5_SData,
wci_s_5_SThreadBusy,
wci_s_5_SFlag,
wci_s_5_MFlag,
wci_s_6_MCmd,
wci_s_6_MAddrSpace,
wci_s_6_MByteEn,
wci_s_6_MAddr,
wci_s_6_MData,
wci_s_6_SResp,
wci_s_6_SData,
wci_s_6_SThreadBusy,
wci_s_6_SFlag,
wci_s_6_MFlag,
wci_s_7_MCmd,
wci_s_7_MAddrSpace,
wci_s_7_MByteEn,
wci_s_7_MAddr,
wci_s_7_MData,
wci_s_7_SResp,
wci_s_7_SData,
wci_s_7_SThreadBusy,
wci_s_7_SFlag,
wci_s_7_MFlag,
wmiM0_MCmd,
wmiM0_MReqLast,
wmiM0_MReqInfo,
wmiM0_MAddrSpace,
wmiM0_MAddr,
wmiM0_MBurstLength,
wmiM0_MDataValid,
wmiM0_MDataLast,
wmiM0_MData,
wmiM0_MDataByteEn,
wmiM0_SResp,
wmiM0_SData,
wmiM0_SThreadBusy,
wmiM0_SDataThreadBusy,
wmiM0_SRespLast,
wmiM0_SFlag,
wmiM0_MFlag,
wmiM0_MReset_n,
wmiM0_SReset_n,
wmiM1_MCmd,
wmiM1_MReqLast,
wmiM1_MReqInfo,
wmiM1_MAddrSpace,
wmiM1_MAddr,
wmiM1_MBurstLength,
wmiM1_MDataValid,
wmiM1_MDataLast,
wmiM1_MData,
wmiM1_MDataByteEn,
wmiM1_SResp,
wmiM1_SData,
wmiM1_SThreadBusy,
wmiM1_SDataThreadBusy,
wmiM1_SRespLast,
wmiM1_SFlag,
wmiM1_MFlag,
wmiM1_MReset_n,
wmiM1_SReset_n,
wmemiM_MCmd,
wmemiM_MReqLast,
wmemiM_MAddr,
wmemiM_MBurstLength,
wmemiM_MDataValid,
wmemiM_MDataLast,
wmemiM_MData,
wmemiM_MDataByteEn,
wmemiM_SResp,
wmemiM_SRespLast,
wmemiM_SData,
wmemiM_SCmdAccept,
wmemiM_SDataAccept,
wmemiM_MReset_n,
wsi_s_adc_MCmd,
wsi_s_adc_MReqLast,
wsi_s_adc_MBurstPrecise,
wsi_s_adc_MBurstLength,
wsi_s_adc_MData,
wsi_s_adc_MByteEn,
wsi_s_adc_MReqInfo,
wsi_s_adc_SThreadBusy,
wsi_s_adc_SReset_n,
wsi_s_adc_MReset_n,
wsi_m_dac_MCmd,
wsi_m_dac_MReqLast,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MBurstLength,
wsi_m_dac_MData,
wsi_m_dac_MByteEn,
wsi_m_dac_MReqInfo,
wsi_m_dac_SThreadBusy,
wsi_m_dac_MReset_n,
wsi_m_dac_SReset_n);
parameter [0 : 0] hasDebugLogic = 1'b0;
input RST_N_rst_0;
input RST_N_rst_1;
input RST_N_rst_2;
input RST_N_rst_3;
input RST_N_rst_4;
input RST_N_rst_5;
input RST_N_rst_6;
input RST_N_rst_7;
input CLK;
input RST_N;
// action method wci_s_0_mCmd
input [2 : 0] wci_s_0_MCmd;
// action method wci_s_0_mAddrSpace
input wci_s_0_MAddrSpace;
// action method wci_s_0_mByteEn
input [3 : 0] wci_s_0_MByteEn;
// action method wci_s_0_mAddr
input [19 : 0] wci_s_0_MAddr;
// action method wci_s_0_mData
input [31 : 0] wci_s_0_MData;
// value method wci_s_0_sResp
output [1 : 0] wci_s_0_SResp;
// value method wci_s_0_sData
output [31 : 0] wci_s_0_SData;
// value method wci_s_0_sThreadBusy
output wci_s_0_SThreadBusy;
// value method wci_s_0_sFlag
output [1 : 0] wci_s_0_SFlag;
// action method wci_s_0_mFlag
input [1 : 0] wci_s_0_MFlag;
// action method wci_s_1_mCmd
input [2 : 0] wci_s_1_MCmd;
// action method wci_s_1_mAddrSpace
input wci_s_1_MAddrSpace;
// action method wci_s_1_mByteEn
input [3 : 0] wci_s_1_MByteEn;
// action method wci_s_1_mAddr
input [19 : 0] wci_s_1_MAddr;
// action method wci_s_1_mData
input [31 : 0] wci_s_1_MData;
// value method wci_s_1_sResp
output [1 : 0] wci_s_1_SResp;
// value method wci_s_1_sData
output [31 : 0] wci_s_1_SData;
// value method wci_s_1_sThreadBusy
output wci_s_1_SThreadBusy;
// value method wci_s_1_sFlag
output [1 : 0] wci_s_1_SFlag;
// action method wci_s_1_mFlag
input [1 : 0] wci_s_1_MFlag;
// action method wci_s_2_mCmd
input [2 : 0] wci_s_2_MCmd;
// action method wci_s_2_mAddrSpace
input wci_s_2_MAddrSpace;
// action method wci_s_2_mByteEn
input [3 : 0] wci_s_2_MByteEn;
// action method wci_s_2_mAddr
input [19 : 0] wci_s_2_MAddr;
// action method wci_s_2_mData
input [31 : 0] wci_s_2_MData;
// value method wci_s_2_sResp
output [1 : 0] wci_s_2_SResp;
// value method wci_s_2_sData
output [31 : 0] wci_s_2_SData;
// value method wci_s_2_sThreadBusy
output wci_s_2_SThreadBusy;
// value method wci_s_2_sFlag
output [1 : 0] wci_s_2_SFlag;
// action method wci_s_2_mFlag
input [1 : 0] wci_s_2_MFlag;
// action method wci_s_3_mCmd
input [2 : 0] wci_s_3_MCmd;
// action method wci_s_3_mAddrSpace
input wci_s_3_MAddrSpace;
// action method wci_s_3_mByteEn
input [3 : 0] wci_s_3_MByteEn;
// action method wci_s_3_mAddr
input [19 : 0] wci_s_3_MAddr;
// action method wci_s_3_mData
input [31 : 0] wci_s_3_MData;
// value method wci_s_3_sResp
output [1 : 0] wci_s_3_SResp;
// value method wci_s_3_sData
output [31 : 0] wci_s_3_SData;
// value method wci_s_3_sThreadBusy
output wci_s_3_SThreadBusy;
// value method wci_s_3_sFlag
output [1 : 0] wci_s_3_SFlag;
// action method wci_s_3_mFlag
input [1 : 0] wci_s_3_MFlag;
// action method wci_s_4_mCmd
input [2 : 0] wci_s_4_MCmd;
// action method wci_s_4_mAddrSpace
input wci_s_4_MAddrSpace;
// action method wci_s_4_mByteEn
input [3 : 0] wci_s_4_MByteEn;
// action method wci_s_4_mAddr
input [19 : 0] wci_s_4_MAddr;
// action method wci_s_4_mData
input [31 : 0] wci_s_4_MData;
// value method wci_s_4_sResp
output [1 : 0] wci_s_4_SResp;
// value method wci_s_4_sData
output [31 : 0] wci_s_4_SData;
// value method wci_s_4_sThreadBusy
output wci_s_4_SThreadBusy;
// value method wci_s_4_sFlag
output [1 : 0] wci_s_4_SFlag;
// action method wci_s_4_mFlag
input [1 : 0] wci_s_4_MFlag;
// action method wci_s_5_mCmd
input [2 : 0] wci_s_5_MCmd;
// action method wci_s_5_mAddrSpace
input wci_s_5_MAddrSpace;
// action method wci_s_5_mByteEn
input [3 : 0] wci_s_5_MByteEn;
// action method wci_s_5_mAddr
input [19 : 0] wci_s_5_MAddr;
// action method wci_s_5_mData
input [31 : 0] wci_s_5_MData;
// value method wci_s_5_sResp
output [1 : 0] wci_s_5_SResp;
// value method wci_s_5_sData
output [31 : 0] wci_s_5_SData;
// value method wci_s_5_sThreadBusy
output wci_s_5_SThreadBusy;
// value method wci_s_5_sFlag
output [1 : 0] wci_s_5_SFlag;
// action method wci_s_5_mFlag
input [1 : 0] wci_s_5_MFlag;
// action method wci_s_6_mCmd
input [2 : 0] wci_s_6_MCmd;
// action method wci_s_6_mAddrSpace
input wci_s_6_MAddrSpace;
// action method wci_s_6_mByteEn
input [3 : 0] wci_s_6_MByteEn;
// action method wci_s_6_mAddr
input [19 : 0] wci_s_6_MAddr;
// action method wci_s_6_mData
input [31 : 0] wci_s_6_MData;
// value method wci_s_6_sResp
output [1 : 0] wci_s_6_SResp;
// value method wci_s_6_sData
output [31 : 0] wci_s_6_SData;
// value method wci_s_6_sThreadBusy
output wci_s_6_SThreadBusy;
// value method wci_s_6_sFlag
output [1 : 0] wci_s_6_SFlag;
// action method wci_s_6_mFlag
input [1 : 0] wci_s_6_MFlag;
// action method wci_s_7_mCmd
input [2 : 0] wci_s_7_MCmd;
// action method wci_s_7_mAddrSpace
input wci_s_7_MAddrSpace;
// action method wci_s_7_mByteEn
input [3 : 0] wci_s_7_MByteEn;
// action method wci_s_7_mAddr
input [19 : 0] wci_s_7_MAddr;
// action method wci_s_7_mData
input [31 : 0] wci_s_7_MData;
// value method wci_s_7_sResp
output [1 : 0] wci_s_7_SResp;
// value method wci_s_7_sData
output [31 : 0] wci_s_7_SData;
// value method wci_s_7_sThreadBusy
output wci_s_7_SThreadBusy;
// value method wci_s_7_sFlag
output [1 : 0] wci_s_7_SFlag;
// action method wci_s_7_mFlag
input [1 : 0] wci_s_7_MFlag;
// value method wmiM0_mCmd
output [2 : 0] wmiM0_MCmd;
// value method wmiM0_mReqLast
output wmiM0_MReqLast;
// value method wmiM0_mReqInfo
output wmiM0_MReqInfo;
// value method wmiM0_mAddrSpace
output wmiM0_MAddrSpace;
// value method wmiM0_mAddr
output [13 : 0] wmiM0_MAddr;
// value method wmiM0_mBurstLength
output [11 : 0] wmiM0_MBurstLength;
// value method wmiM0_mDataValid
output wmiM0_MDataValid;
// value method wmiM0_mDataLast
output wmiM0_MDataLast;
// value method wmiM0_mData
output [31 : 0] wmiM0_MData;
// value method wmiM0_mDataInfo
// value method wmiM0_mDataByteEn
output [3 : 0] wmiM0_MDataByteEn;
// action method wmiM0_sResp
input [1 : 0] wmiM0_SResp;
// action method wmiM0_sData
input [31 : 0] wmiM0_SData;
// action method wmiM0_sThreadBusy
input wmiM0_SThreadBusy;
// action method wmiM0_sDataThreadBusy
input wmiM0_SDataThreadBusy;
// action method wmiM0_sRespLast
input wmiM0_SRespLast;
// action method wmiM0_sFlag
input [31 : 0] wmiM0_SFlag;
// value method wmiM0_mFlag
output [31 : 0] wmiM0_MFlag;
// value method wmiM0_mReset_n
output wmiM0_MReset_n;
// action method wmiM0_sReset_n
input wmiM0_SReset_n;
// value method wmiM1_mCmd
output [2 : 0] wmiM1_MCmd;
// value method wmiM1_mReqLast
output wmiM1_MReqLast;
// value method wmiM1_mReqInfo
output wmiM1_MReqInfo;
// value method wmiM1_mAddrSpace
output wmiM1_MAddrSpace;
// value method wmiM1_mAddr
output [13 : 0] wmiM1_MAddr;
// value method wmiM1_mBurstLength
output [11 : 0] wmiM1_MBurstLength;
// value method wmiM1_mDataValid
output wmiM1_MDataValid;
// value method wmiM1_mDataLast
output wmiM1_MDataLast;
// value method wmiM1_mData
output [31 : 0] wmiM1_MData;
// value method wmiM1_mDataInfo
// value method wmiM1_mDataByteEn
output [3 : 0] wmiM1_MDataByteEn;
// action method wmiM1_sResp
input [1 : 0] wmiM1_SResp;
// action method wmiM1_sData
input [31 : 0] wmiM1_SData;
// action method wmiM1_sThreadBusy
input wmiM1_SThreadBusy;
// action method wmiM1_sDataThreadBusy
input wmiM1_SDataThreadBusy;
// action method wmiM1_sRespLast
input wmiM1_SRespLast;
// action method wmiM1_sFlag
input [31 : 0] wmiM1_SFlag;
// value method wmiM1_mFlag
output [31 : 0] wmiM1_MFlag;
// value method wmiM1_mReset_n
output wmiM1_MReset_n;
// action method wmiM1_sReset_n
input wmiM1_SReset_n;
// value method wmemiM_mCmd
output [2 : 0] wmemiM_MCmd;
// value method wmemiM_mReqLast
output wmemiM_MReqLast;
// value method wmemiM_mAddr
output [35 : 0] wmemiM_MAddr;
// value method wmemiM_mBurstLength
output [11 : 0] wmemiM_MBurstLength;
// value method wmemiM_mDataValid
output wmemiM_MDataValid;
// value method wmemiM_mDataLast
output wmemiM_MDataLast;
// value method wmemiM_mData
output [127 : 0] wmemiM_MData;
// value method wmemiM_mDataByteEn
output [15 : 0] wmemiM_MDataByteEn;
// action method wmemiM_sResp
input [1 : 0] wmemiM_SResp;
// action method wmemiM_sRespLast
input wmemiM_SRespLast;
// action method wmemiM_sData
input [127 : 0] wmemiM_SData;
// action method wmemiM_sCmdAccept
input wmemiM_SCmdAccept;
// action method wmemiM_sDataAccept
input wmemiM_SDataAccept;
// value method wmemiM_mReset_n
output wmemiM_MReset_n;
// action method wsi_s_adc_mCmd
input [2 : 0] wsi_s_adc_MCmd;
// action method wsi_s_adc_mReqLast
input wsi_s_adc_MReqLast;
// action method wsi_s_adc_mBurstPrecise
input wsi_s_adc_MBurstPrecise;
// action method wsi_s_adc_mBurstLength
input [11 : 0] wsi_s_adc_MBurstLength;
// action method wsi_s_adc_mData
input [31 : 0] wsi_s_adc_MData;
// action method wsi_s_adc_mByteEn
input [3 : 0] wsi_s_adc_MByteEn;
// action method wsi_s_adc_mReqInfo
input [7 : 0] wsi_s_adc_MReqInfo;
// action method wsi_s_adc_mDataInfo
// value method wsi_s_adc_sThreadBusy
output wsi_s_adc_SThreadBusy;
// value method wsi_s_adc_sReset_n
output wsi_s_adc_SReset_n;
// action method wsi_s_adc_mReset_n
input wsi_s_adc_MReset_n;
// value method wsi_m_dac_mCmd
output [2 : 0] wsi_m_dac_MCmd;
// value method wsi_m_dac_mReqLast
output wsi_m_dac_MReqLast;
// value method wsi_m_dac_mBurstPrecise
output wsi_m_dac_MBurstPrecise;
// value method wsi_m_dac_mBurstLength
output [11 : 0] wsi_m_dac_MBurstLength;
// value method wsi_m_dac_mData
output [31 : 0] wsi_m_dac_MData;
// value method wsi_m_dac_mByteEn
output [3 : 0] wsi_m_dac_MByteEn;
// value method wsi_m_dac_mReqInfo
output [7 : 0] wsi_m_dac_MReqInfo;
// value method wsi_m_dac_mDataInfo
// action method wsi_m_dac_sThreadBusy
input wsi_m_dac_SThreadBusy;
// value method wsi_m_dac_mReset_n
output wsi_m_dac_MReset_n;
// action method wsi_m_dac_sReset_n
input wsi_m_dac_SReset_n;
// signals for module outputs
wire [127 : 0] wmemiM_MData;
wire [35 : 0] wmemiM_MAddr;
wire [31 : 0] wci_s_0_SData,
wci_s_1_SData,
wci_s_2_SData,
wci_s_3_SData,
wci_s_4_SData,
wci_s_5_SData,
wci_s_6_SData,
wci_s_7_SData,
wmiM0_MData,
wmiM0_MFlag,
wmiM1_MData,
wmiM1_MFlag,
wsi_m_dac_MData;
wire [15 : 0] wmemiM_MDataByteEn;
wire [13 : 0] wmiM0_MAddr, wmiM1_MAddr;
wire [11 : 0] wmemiM_MBurstLength,
wmiM0_MBurstLength,
wmiM1_MBurstLength,
wsi_m_dac_MBurstLength;
wire [7 : 0] wsi_m_dac_MReqInfo;
wire [3 : 0] wmiM0_MDataByteEn, wmiM1_MDataByteEn, wsi_m_dac_MByteEn;
wire [2 : 0] wmemiM_MCmd, wmiM0_MCmd, wmiM1_MCmd, wsi_m_dac_MCmd;
wire [1 : 0] wci_s_0_SFlag,
wci_s_0_SResp,
wci_s_1_SFlag,
wci_s_1_SResp,
wci_s_2_SFlag,
wci_s_2_SResp,
wci_s_3_SFlag,
wci_s_3_SResp,
wci_s_4_SFlag,
wci_s_4_SResp,
wci_s_5_SFlag,
wci_s_5_SResp,
wci_s_6_SFlag,
wci_s_6_SResp,
wci_s_7_SFlag,
wci_s_7_SResp;
wire wci_s_0_SThreadBusy,
wci_s_1_SThreadBusy,
wci_s_2_SThreadBusy,
wci_s_3_SThreadBusy,
wci_s_4_SThreadBusy,
wci_s_5_SThreadBusy,
wci_s_6_SThreadBusy,
wci_s_7_SThreadBusy,
wmemiM_MDataLast,
wmemiM_MDataValid,
wmemiM_MReqLast,
wmemiM_MReset_n,
wmiM0_MAddrSpace,
wmiM0_MDataLast,
wmiM0_MDataValid,
wmiM0_MReqInfo,
wmiM0_MReqLast,
wmiM0_MReset_n,
wmiM1_MAddrSpace,
wmiM1_MDataLast,
wmiM1_MDataValid,
wmiM1_MReqInfo,
wmiM1_MReqLast,
wmiM1_MReset_n,
wsi_m_dac_MBurstPrecise,
wsi_m_dac_MReqLast,
wsi_m_dac_MReset_n,
wsi_s_adc_SReset_n,
wsi_s_adc_SThreadBusy;
// Instantiate the wip-compliant app
ocpi_app #(.hasDebugLogic(hasDebugLogic)) app(
.wci0_MReset_n(RST_N_rst_2),
.wci1_MReset_n(RST_N_rst_3),
.wci2_MReset_n(RST_N_rst_4),
.wci_Clk(CLK),
.wci0_MAddr(wci_s_2_MAddr),
.wci0_MAddrSpace(wci_s_2_MAddrSpace),
.wci0_MByteEn(wci_s_2_MByteEn),
.wci0_MCmd(wci_s_2_MCmd),
.wci0_MData(wci_s_2_MData),
.wci0_MFlag(wci_s_2_MFlag),
.wci1_MAddr(wci_s_3_MAddr),
.wci1_MAddrSpace(wci_s_3_MAddrSpace),
.wci1_MByteEn(wci_s_3_MByteEn),
.wci1_MCmd(wci_s_3_MCmd),
.wci1_MData(wci_s_3_MData),
.wci1_MFlag(wci_s_3_MFlag),
.wci2_MAddr(wci_s_4_MAddr),
.wci2_MAddrSpace(wci_s_4_MAddrSpace),
.wci2_MByteEn(wci_s_4_MByteEn),
.wci2_MCmd(wci_s_4_MCmd),
.wci2_MData(wci_s_4_MData),
.wci2_MFlag(wci_s_4_MFlag),
`ifdef NOTHERE
.wmemi0_SData(wmemiM_SData),
.wmemi0_SResp(wmemiM_SResp),
`endif
.FC_SData(wmiM0_SData),
.FC_SFlag(wmiM0_SFlag),
.FC_SResp(wmiM0_SResp),
.FP_SData(wmiM1_SData),
.FP_SFlag(wmiM1_SFlag),
.FP_SResp(wmiM1_SResp),
`ifdef NOTHERE
.adc_MBurstLength(wsi_s_adc_MBurstLength),
.adc_MByteEn(wsi_s_adc_MByteEn),
.adc_MCmd(wsi_s_adc_MCmd),
.adc_MData(wsi_s_adc_MData),
.adc_MReqInfo(wsi_s_adc_MReqInfo),
`endif
.FC_SThreadBusy(wmiM0_SThreadBusy),
.FC_SDataThreadBusy(wmiM0_SDataThreadBusy),
.FC_SRespLast(wmiM0_SRespLast),
.FC_SReset_n(wmiM0_SReset_n),
.FP_SThreadBusy(wmiM1_SThreadBusy),
.FP_SDataThreadBusy(wmiM1_SDataThreadBusy),
.FP_SRespLast(wmiM1_SRespLast),
.FP_SReset_n(wmiM1_SReset_n),
`ifdef NOTHERE
.wmemi0_SRespLast(wmemiM_SRespLast),
.wmemi0_SCmdAccept(wmemiM_SCmdAccept),
.wmemi0_SDataAccept(wmemiM_SDataAccept),
.adc_MReqLast(wsi_s_adc_MReqLast),
.adc_MBurstPrecise(wsi_s_adc_MBurstPrecise),
.adc_MReset_n(wsi_s_adc_MReset_n),
.dac_SThreadBusy(wsi_m_dac_SThreadBusy),
.dac_SReset_n(wsi_m_dac_SReset_n),
`endif
.wci0_SResp(wci_s_2_SResp),
.wci0_SData(wci_s_2_SData),
.wci0_SThreadBusy(wci_s_2_SThreadBusy),
.wci0_SFlag(wci_s_2_SFlag),
.wci1_SResp(wci_s_3_SResp),
.wci1_SData(wci_s_3_SData),
.wci1_SThreadBusy(wci_s_3_SThreadBusy),
.wci1_SFlag(wci_s_3_SFlag),
.wci2_SResp(wci_s_4_SResp),
.wci2_SData(wci_s_4_SData),
.wci2_SThreadBusy(wci_s_4_SThreadBusy),
.wci2_SFlag(wci_s_4_SFlag),
.FC_MCmd(wmiM0_MCmd),
.FC_MReqLast(wmiM0_MReqLast),
.FC_MReqInfo(wmiM0_MReqInfo),
.FC_MAddrSpace(wmiM0_MAddrSpace),
.FC_MAddr(wmiM0_MAddr),
.FC_MBurstLength(wmiM0_MBurstLength),
.FC_MDataValid(wmiM0_MDataValid),
.FC_MDataLast(wmiM0_MDataLast),
.FC_MData(wmiM0_MData),
.FC_MDataByteEn(wmiM0_MDataByteEn),
.FC_MFlag(wmiM0_MFlag),
.FC_MReset_n(wmiM0_MReset_n),
.FP_MCmd(wmiM1_MCmd),
.FP_MReqLast(wmiM1_MReqLast),
.FP_MReqInfo(wmiM1_MReqInfo),
.FP_MAddrSpace(wmiM1_MAddrSpace),
.FP_MAddr(wmiM1_MAddr),
.FP_MBurstLength(wmiM1_MBurstLength),
.FP_MDataValid(wmiM1_MDataValid),
.FP_MDataLast(wmiM1_MDataLast),
.FP_MData(wmiM1_MData),
.FP_MDataByteEn(wmiM1_MDataByteEn),
.FP_MFlag(wmiM1_MFlag),
.FP_MReset_n(wmiM1_MReset_n)
`ifdef NOTTHERE
.wmemi0_MCmd(wmemiM_MCmd),
.wmemi0_MReqLast(wmemiM_MReqLast),
.wmemi0_MAddr(wmemiM_MAddr),
.wmemi0_MBurstLength(wmemiM_MBurstLength),
.wmemi0_MDataValid(wmemiM_MDataValid),
.wmemi0_MDataLast(wmemiM_MDataLast),
.wmemi0_MData(wmemiM_MData),
.wmemi0_MDataByteEn(wmemiM_MDataByteEn),
.wmemi0_MReset_n(wmemiM_MReset_n)
`endif
);
// .adc_SThreadBusy(wsi_s_adc_SThreadBusy),
// .adc_SReset_n(wsi_s_adc_SReset_n),
// .dac_MCmd(wsi_m_dac_MCmd),
// .dac_MReqLast(wsi_m_dac_MReqLast),
// .dac_MBurstPrecise(wsi_m_dac_MBurstPrecise),
// .dac_MBurstLength(wsi_m_dac_MBurstLength),
// .dac_MData(wsi_m_dac_MData),
// .dac_MByteEn(wsi_m_dac_MByteEn),
// .dac_MReqInfo(wsi_m_dac_MReqInfo),
// .dac_MReset_n(wsi_m_dac_MReset_n));
endmodule // mkOCApp
|
`timescale 1ns / 1ps
module clock_tb();
parameter DELAY = 10;
parameter TIME = 1000;
reg clk_src, power, enable, reset;
reg [2:0] add_time, sub_time;
reg timing_clock_switch;
wire alarm, timing_clock_alarm;
wire [7:0] anodes, cnodes;
clock #(32, 0, 5, 4, 3, 5, 5) DUT (
.clk_src(clk_src),
.power(power),
.enable(enable),
.reset(reset),
.add_time(add_time),
.sub_time(sub_time),
.timing_clock_switch(timing_clock_switch),
.alarm(alarm),
.timing_clock_alarm(timing_clock_alarm),
.anodes(anodes),
.cnodes(cnodes)
);
initial begin
clk_src <= 0;
power <= 0;
enable <= 0;
reset <= 0;
add_time <= 3'b000;
sub_time <= 3'b000;
timing_clock_switch <= 0;
#TIME $finish;
end
always begin
#DELAY clk_src <= ~clk_src;
end
always begin
// power = 0, enable = 0
// all buttons don't work
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 0, enable = 1
// all buttons don't work
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 1, enable = 1
// reset works, add_time/sub_time doesn't work
// feat: reset && count
#(DELAY) power = 1;
#(DELAY) enable = 1;
#(DELAY/2);
#(DELAY) add_time = 3'b111;
#(DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
#(5*DELAY) reset = 1;
#(DELAY) reset = 0;
// power = 1, enable = 0
// reset works, add_time/sub_time works
// feat: add time && sub time
#(10*DELAY) enable = 0;
#(10*DELAY); // pause
#(DELAY) add_time = 3'b111;
#(2*DELAY) add_time = 0;
#(DELAY) sub_time = 3'b111;
#(DELAY) sub_time = 0;
// power = 0
// when power off, automatically reset all clock
#(DELAY) power = 0;
// test timing clock feature
#(DELAY) power = 1;
#(DELAY) timing_clock_switch = 1;
#(DELAY) add_time[0] = 1;
#(5*DELAY) add_time[1] = 0;
#(DELAY) timing_clock_switch = 0;
#(DELAY) enable = 1;
end
endmodule
|
/*
* BCH Encode/Decoder Modules
*
* Copyright 2015 - Russ Dill <[email protected]>
* Distributed under 2-clause BSD license as contained in COPYING file.
*/
`timescale 1ns / 1ps
`include "config.vh"
`include "bch_defs.vh"
/* Reduced chien search for cases with only 1 bit error */
module bch_error_one #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_M(P)*2-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam SKIP = `BCH_DATA_BITS(P) - `BCH_K(P) + `BCH_N(P);
wire [BITS-1:0] err_raw;
wire [M-1:0] chien;
if (`BCH_T(P) == 1)
one_does_not_support_sec u_odnss();
bch_chien_reg #(M, 1, 0, BITS) u_chien_reg(
.clk(clk),
.start(start),
.in(sigma[M+:M]),
.out(chien)
);
genvar b;
generate
for (b = 0; b < BITS; b = b + 1) begin : BIT
assign err_raw[b] = chien == lpow(M, SKIP + b);
end
endgenerate
pipeline #(2 + PIPELINE_STAGES) u_first_pipeline (
.clk(clk),
.i(start),
.o(first)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline [BITS-1:0] (
.clk(clk),
.i(err_raw),
.o(err)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:55:09 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top DemoInterconnect_ila_0_0 -prefix
// DemoInterconnect_ila_0_0_ DemoInterconnect_ila_0_0_stub.v
// Design : DemoInterconnect_ila_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ila,Vivado 2017.3" *)
module DemoInterconnect_ila_0_0(clk, probe0, probe1, probe2, probe3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[7:0],probe2[0:0],probe3[7:0]" */;
input clk;
input [0:0]probe0;
input [7:0]probe1;
input [0:0]probe2;
input [7:0]probe3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_FUNCTIONAL_PP_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_e_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_e_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_e_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_e_e
//
// No `defines in this module
module inst_e_e
//
// Generated Module inst_e
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ea
inst_ea_e inst_ea (
);
// End of Generated Instance Port Map for inst_ea
endmodule
//
// End of Generated Module rtl of inst_e_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//----------------------------------------------------------------------------
// Wishbone Tube controller
//----------------------------------------------------------------------------
module wb_tube #(
parameter latency = 0 // 0 .. 7
) (
input clk,
input reset,
// Wishbone interface
input wb_stb_i,
input wb_cyc_i,
input wb_tga_i,
output reg wb_ack_o,
input wb_we_i,
input [2:0] wb_adr_i,
input [1:0] wb_sel_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
// TUBE connection
output reg [2:0] tube_adr,
inout [7:0] tube_dat,
output reg tube_cs_n, // Chip Select
output reg tube_rd_n, // Read
output reg tube_wr_n // Write
);
//----------------------------------------------------------------------------
//
//----------------------------------------------------------------------------
// Wishbone handling
wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
// Tri-State-Driver
reg [7:0] wdat;
reg wdat_oe;
assign tube_dat = wdat_oe ? wdat : 8'bz;
// Latency countdown
reg [2:0] lcount;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
parameter s_idle = 0;
parameter s_read = 1;
parameter s_write = 2;
reg [2:0] state;
always @(posedge clk)
begin
if (reset) begin
state <= s_idle;
lcount <= 0;
wb_ack_o <= 0;
end else begin
case (state)
s_idle: begin
wb_ack_o <= 0;
if (wb_rd) begin
tube_cs_n <= 0;
tube_rd_n <= 0;
tube_wr_n <= 1;
tube_adr <= wb_adr_i;
wdat_oe <= 0;
lcount <= latency;
state <= s_read;
end else if (wb_wr) begin
tube_cs_n <= 0;
tube_rd_n <= 1;
tube_wr_n <= 0;
tube_adr <= wb_adr_i;
wdat <= wb_dat_i[7:0];
wdat_oe <= 1;
lcount <= latency;
state <= s_write;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wdat_oe <= 0;
end
end
s_read: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wb_dat_o <= tube_dat;
wb_ack_o <= 1;
state <= s_idle;
end
end
s_write: begin
if (lcount != 0) begin
lcount <= lcount - 1;
end else begin
tube_cs_n <= 1;
tube_rd_n <= 1;
tube_wr_n <= 1;
wb_ack_o <= 1; // XXX We could acknoledge write XXX
state <= s_idle; // XXX requests 1 cycle ahead XXX
end
end
endcase
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_wakeup_cell.v
//
// *Module Description:
// Generic Wakeup cell
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_wakeup_cell (
// OUTPUTs
wkup_out, // Wakup signal (asynchronous)
// INPUTs
scan_clk, // Scan clock
scan_mode, // Scan mode
scan_rst, // Scan reset
wkup_clear, // Glitch free wakeup event clear
wkup_event // Glitch free asynchronous wakeup event
);
// OUTPUTs
//=========
output wkup_out; // Wakup signal (asynchronous)
// INPUTs
//=========
input scan_clk; // Scan clock
input scan_mode; // Scan mode
input scan_rst; // Scan reset
input wkup_clear; // Glitch free wakeup event clear
input wkup_event; // Glitch free asynchronous wakeup event
//=============================================================================
// 1) AND GATE
//=============================================================================
// Scan stuff for the ASIC mode
`ifdef ASIC
wire wkup_rst;
omsp_scan_mux scan_mux_rst (
.scan_mode (scan_mode),
.data_in_scan (scan_rst),
.data_in_func (wkup_clear),
.data_out (wkup_rst)
);
wire wkup_clk;
omsp_scan_mux scan_mux_clk (
.scan_mode (scan_mode),
.data_in_scan (scan_clk),
.data_in_func (wkup_event),
.data_out (wkup_clk)
);
`else
wire wkup_rst = wkup_clear;
wire wkup_clk = wkup_event;
`endif
// Wakeup capture
reg wkup_out;
always @(posedge wkup_clk or posedge wkup_rst)
if (wkup_rst) wkup_out <= 1'b0;
else wkup_out <= 1'b1;
endmodule // omsp_wakeup_cell
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
`timescale 1ns / 1ps
`default_nettype none
module Freq_Divider#(
parameter sys_clk = 50000000, // 50 MHz system clock
clk_out = 1 // 1 Hz clock output
)
(Clk_in, Clk_out);
// input ports
input wire Clk_in;
// output ports
output reg Clk_out;
// initial begin // Initialize Clk_out for simulation purposes
// Clk_out=1'b0;
// end
// counter size calculation according to input and output frequencies
parameter max = sys_clk / (2*clk_out); // max-counter size. clk_out has 50% duty cycle
localparam N=log2(max); // numbers of bits needed in the counter
reg [N-1:0]counter = 0; // N-bit counter size
always@(posedge Clk_in) begin
if (counter == max-1)
begin
counter <= 0;
Clk_out <= ~Clk_out;
end
else
begin
counter <= counter + 1'd1;
end
end
//function to calculate the bits for the counter according to the size of M
function integer log2(input integer n);
integer i;
begin
log2=1;
for (i=0; 2**i < n; i=i+1)
log2=i+1;
end
endfunction
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:37:09 04/26/2012
// Design Name: joypad_snes_adapter
// Module Name: G:/Projects/s6atlystest/joypad_snes_adapter_tb.v
// Project Name: s6atlystest
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: joypad_snes_adapter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module joypad_snes_adapter_tb;
// Inputs
reg clock;
reg reset;
wire [1:0] button_sel;
wire controller_data;
// Outputs
wire [3:0] button_data;
wire controller_latch;
wire controller_clock;
// Instantiate the Unit Under Test (UUT)
joypad_snes_adapter uut (
.clock(clock),
.reset(reset),
.button_sel(button_sel),
.button_data(button_data),
.controller_data(controller_data),
.controller_latch(controller_latch),
.controller_clock(controller_clock)
);
assign button_sel = 2'b0;
assign controller_data = 1'b0;
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
// Wait 100 ns for module reset to finish
#100 reset = 0;
end
always begin
#10 clock = !clock;
end
endmodule
|
// A register file module. 32 registers, each of it has 32 bit
// Supports 2 reading ports, 1 writing port
// ADDA: reading address of A, ADDB: reading addr of B
// ADDC: writing address of C
// clk: clock signal
// clr: clear signal
// WE: Write Enable
module registerfile(ADDA, DATAA, ADDB, DATAB, ADDC, DATAC, clk, clr, WE);
input [4:0] ADDA, ADDB, ADDC;
input [31:0] DATAC;
input clk, clr, WE;
output [31:0] DATAA, DATAB;
reg [31:0] register [31:0];
integer i;
//clear all the registers in the register file
initial begin
for (i=0; i<32; i=i+1)
register[i] = 0;
$readmemh("reg.dat", register);
end
//only when a positive(rising) edge occurs
always @(posedge clk or posedge clr)
begin
// clear signal will reset all register as well
if (clr)
for (i=0; i<32; i=i+1)
register[i] = 0;
else
// only when WE is 1, we write the register file
if (WE == 1)
begin
register[ADDC] = DATAC;
register[0] = 0;
end
end
// we always reading content of A and B
assign DATAA = register[ADDA];
assign DATAB = register[ADDB];
endmodule
module RegFileTestbench;
reg [31:0] data;
reg [4:0] addrA, addrB, addrC;
wire [31:0] outA;
wire [31:0] outB;
reg clks, clr, WE;
integer ctr;
registerfile UUT(addrA, outA, addrB, outB, addrC, data, clks, clr, WE);
initial begin
clks = 0;
#10 clr = 0;
WE = 0;
for (ctr=0; ctr<31; ctr = ctr+1)
begin
#25 addrA <= ctr;
addrB = ctr+1;
end
addrA = 2;
addrB = 3;
addrC = 3;
WE = 1;
for (ctr=0; ctr<10; ctr = ctr+1)
begin
#25 data <= ctr;
end
WE = 0;
end
initial
forever #20 clks = ~clks;
initial
#1100 $stop;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_M_V
`define SKY130_FD_SC_LP__NAND4B_M_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4b_m (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand4b_m (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_M_V
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Primary control registers.
// Access to registers is asynchronous. It is only controlled by the memory bus
// signals, and not by the system clock.
`include "registers.vh"
`include "tile_registers.vh"
module Register(reset, clk, en, be, d, q, value_in);
parameter WIDTH=16; // Number of bits in the register.
parameter BUS_WIDTH=16; // Width of data bus used to access register.
parameter TYPE=`REG_RW; // Register type: read/write, read-only, etc.
input clk; // System clock
input reset; // System reset
input en; // Access enable
input [1:0] be; // Byte enable
input [BUS_WIDTH-1:0] d; // Input and output ports.
output [BUS_WIDTH-1:0] q;
input [BUS_WIDTH-1:0] value_in; // Read value for read-only registers.
wire byte_lo_en = be[0];
wire byte_hi_en = be[1];
genvar i;
generate
if (TYPE == `REG_RW) begin
for (i = 0; i < BUS_WIDTH; i = i + 1) begin: REG
if (i < WIDTH) begin
CC_DFlipFlop #(1) dff(.clk(clk),
.reset(reset),
.en(en & ((i < 8) ? byte_lo_en : byte_hi_en)),
.d(d[i]),
.q(q[i]));
end else begin
// Unused bits default to zero.
assign q[i] = 1'b0;
end
end
end else begin // if (TYPE == `REG_RO)
// Read only register uses the |value_in| port.
assign q = value_in;
end
endgenerate
endmodule
module Registers(clk, reset, en, rd, wr, be, addr, data_in, data_out,
values_in, values_out);
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=16;
parameter NUM_REGS=(1 << ADDR_WIDTH);
parameter IS_GENERIC=1;
input clk; // System clock
input reset; // System reset
input en; // Access enable
input rd; // Read enable
input wr; // Write enable
input [1:0] be; // Byte enable
input [ADDR_WIDTH-1:0] addr; // Address bus
input [DATA_WIDTH-1:0] data_in; // Data in bus
output reg [DATA_WIDTH-1:0] data_out; // Data out bus
// Port for obtaining read-only register values.
input [DATA_WIDTH * NUM_REGS - 1 : 0] values_in;
// Port for exposing all read/write register values.
output [DATA_WIDTH * NUM_REGS - 1 : 0] values_out;
// This function returns the register type, given a register address.
function integer register_type;
input [31:0] address;
begin
case (address)
`ID: register_type = `REG_RO;
`OUTPUT_STATUS: register_type = `REG_RO;
`SCAN_X: register_type = `REG_RO;
`SCAN_Y: register_type = `REG_RO;
`SYS_CTRL: register_type = `REG_RW;
`MEM_BANK: register_type = `REG_RW;
`OUTPUT_CTRL: register_type = `REG_RW;
`MODE_CTRL: register_type = `REG_RW;
`SPRITE_Z: register_type = `REG_RW;
`SCROLL_X: register_type = `REG_RW;
`SCROLL_Y: register_type = `REG_RW;
default: register_type = `REG_RO;
endcase
end
endfunction
function integer tile_reg_type;
input [31:0] address;
begin
case (address)
`TILE_CTRL0: tile_reg_type = `REG_RW;
`TILE_DATA_OFFSET: tile_reg_type = `REG_RW;
`TILE_NOP_VALUE: tile_reg_type = `REG_RW;
`TILE_COLOR_KEY: tile_reg_type = `REG_RW;
`TILE_OFFSET_X: tile_reg_type = `REG_RW;
`TILE_OFFSET_Y: tile_reg_type = `REG_RW;
default: tile_reg_type = `REG_RO;
endcase
end
endfunction
// Generate the registers.
wire [DATA_WIDTH-1:0] q_array [NUM_REGS - 1:0];
genvar i;
generate
for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS
Register #(.WIDTH(DATA_WIDTH),
.TYPE(IS_GENERIC ? register_type(i) : tile_reg_type(i)))
register(.clk(~wr),
.en(en & ~rd & (i == addr)),
.reset(reset),
.be(be),
.d(data_in),
.q(q_array[i]),
.value_in(values_in[DATA_WIDTH * (i + 1) - 1 :
DATA_WIDTH * i]));
assign values_out[DATA_WIDTH * (i + 1) - 1 : DATA_WIDTH * i] = q_array[i];
end
endgenerate
// Memory bus data read.
always @ (posedge clk)
if (en & rd)
data_out <= q_array[addr];
endmodule
|
// simulate fpga top-level with external dram, rom, z80
// (c) 2010-2016 NedoPC
`include "../include/tune.v"
//`define ZLOG 1
`define HALF_CLK_PERIOD (17.8)
`define ZCLK_DELAY (9.5)
// toshibo
//`define Z80_DELAY_DOWN (17.0)
//`define Z80_DELAY_UP (22.0)
// z0840008
`define Z80_DELAY_DOWN 34
`define Z80_DELAY_UP 30
module tb;
reg fclk;
wire clkz_out,clkz_in;
reg iorq_n,mreq_n,rd_n,wr_n; // has some delays relative to z*_n (below)
reg m1_n,rfsh_n; //
wire res; //
tri1 ziorq_n,zmreq_n,zrd_n,zwr_n,zm1_n,zrfsh_n; // connected to Z80
tri1 int_n,wait_n,nmi_n;
wire zint_n,zwait_n,znmi_n;
wire [15:0] #((`Z80_DELAY_DOWN+`Z80_DELAY_UP)/2) za;
wire [ 7:0] #((`Z80_DELAY_DOWN+`Z80_DELAY_UP)/2) zd;
tri1 [ 7:0] zd_dut_to_z80;
reg [15:0] reset_pc = 16'h0000;
reg [15:0] reset_sp = 16'hFFFF;
wire csrom, romoe_n, romwe_n;
wire rompg0_n, dos_n;
wire rompg2,rompg3,rompg4;
wire [15:0] rd;
wire [9:0] ra;
wire rwe_n,rucas_n,rlcas_n,rras0_n,rras1_n;
tri1 [15:0] ide_d;
wire hsync,vsync;
wire [1:0] red,grn,blu;
// sdcard
wire sdcs_n, sddo, sddi, sdclk;
// avr
wire spick, spidi, spido, spics_n;
assign zwait_n = (wait_n==1'b0) ? 1'b0 : 1'b1;
assign znmi_n = (nmi_n==1'b0) ? 1'b0 : 1'b1;
assign zint_n = (int_n==1'b0) ? 1'b0 : 1'b1;
initial
begin
fclk = 1'b0;
forever #`HALF_CLK_PERIOD fclk = ~fclk;
end
assign #`ZCLK_DELAY clkz_in = ~clkz_out;
top DUT( .fclk(fclk),
.clkz_out(clkz_out),
.clkz_in(clkz_in),
// z80
.iorq_n(iorq_n),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.m1_n(m1_n),
.rfsh_n(rfsh_n),
.int_n(int_n),
.nmi_n(nmi_n),
.wait_n(wait_n),
.res(res),
//
.d(zd),
.a(za),
// ROM
.csrom(csrom),
.romoe_n(romoe_n),
.romwe_n(romwe_n),
.rompg0_n(rompg0_n),
.dos_n(dos_n),
.rompg2(rompg2),
.rompg3(rompg3),
.rompg4(rompg4),
// DRAM
.rd(rd),
.ra(ra),
.rwe_n(rwe_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n),
// ZX-bus
.iorqge1(1'b0),
.iorqge2(1'b0),
// IDE
.ide_d(ide_d),
.ide_rdy(1'b1),
// VG93
.step(1'b0),
.vg_sl(1'b0),
.vg_sr(1'b0),
.vg_tr43(1'b0),
.rdat_b_n(1'b1),
.vg_wf_de(1'b0),
.vg_drq(1'b1),
.vg_irq(1'b1),
.vg_wd(1'b0),
// SDcard SPI
.sddi(sddi),
.sddo(sddo),
.sdcs_n(sdcs_n),
.sdclk(sdclk),
// ATmega SPI
.spics_n(spics_n),
.spick(spick),
.spido(spido),
.spidi(spidi),
.vhsync(hsync),
.vvsync(vsync),
.vred(red),
.vgrn(grn),
.vblu(blu)
);
// assign zd_dut_to_z80 = tb.DUT.ena_ram ? tb.DUT.dout_ram : ( tb.DUT.ena_ports ? tb.DUT.dout_ports : ( tb.DUT.drive_ff ? 8'hFF : 8'bZZZZZZZZ ) );
assign zd_dut_to_z80 = tb.DUT.d_ena ? tb.DUT.d_pre_out : 8'bZZZZ_ZZZZ;
wire zrst_n = ~res;
T80a z80( .RESET_n(zrst_n),
.CLK_n(clkz_in),
.WAIT_n(zwait_n),
.INT_n(zint_n),
.NMI_n(znmi_n),
.M1_n(zm1_n),
.RFSH_n(zrfsh_n),
.MREQ_n(zmreq_n),
.IORQ_n(ziorq_n),
.RD_n(zrd_n),
.WR_n(zwr_n),
.BUSRQ_n(1'b1),
.A(za),
.D_I(zd_dut_to_z80),
.D_O(zd),
.ResetPC(reset_pc),
.ResetSP(reset_sp)
);
// now make delayed versions of signals
//
reg mreq_wr_n;
wire iorq_wr_n, full_wr_n;
//
// first, assure there is no X's at the start
//
initial
begin
m1_n = 1'b1;
rfsh_n = 1'b1;
mreq_n = 1'b1;
iorq_n = 1'b1;
rd_n = 1'b1;
wr_n = 1'b1;
mreq_wr_n = 1'b1;
end
//
always @(zm1_n)
if( zm1_n )
m1_n <= #`Z80_DELAY_UP zm1_n;
else
m1_n <= #`Z80_DELAY_DOWN zm1_n;
//
always @(zrfsh_n)
if( zrfsh_n )
rfsh_n <= #`Z80_DELAY_UP zrfsh_n;
else
rfsh_n <= #`Z80_DELAY_DOWN zrfsh_n;
//
always @(zmreq_n)
if( zmreq_n )
mreq_n <= #`Z80_DELAY_UP zmreq_n;
else
mreq_n <= #`Z80_DELAY_DOWN zmreq_n;
//
always @(ziorq_n)
if( ziorq_n )
iorq_n <= #`Z80_DELAY_UP ziorq_n;
else
iorq_n <= #`Z80_DELAY_DOWN ziorq_n;
//
always @(zrd_n)
if( zrd_n )
rd_n <= #`Z80_DELAY_UP zrd_n;
else
rd_n <= #`Z80_DELAY_DOWN zrd_n;
//
//
// special handling for broken T80 WR_n
//
always @(negedge clkz_in)
mreq_wr_n <= zwr_n;
//
assign iorq_wr_n = ziorq_n | (~zrd_n) | (~zm1_n);
//
assign full_wr_n = mreq_wr_n & iorq_wr_n;
//
// this way glitches won't affect state of wr_n
always @(full_wr_n)
if( !full_wr_n )
#`Z80_DELAY_DOWN wr_n <= full_wr_n;
else
#`Z80_DELAY_UP wr_n <= full_wr_n;
// ROM model
rom romko(
.addr( {rompg4,rompg3,rompg2,dos_n, (~rompg0_n), za[13:0]} ),
.data(zd_dut_to_z80),
.ce_n( romoe_n | (~csrom) )
);
// DRAM model
drammem dramko1(
.ma(ra),
.d(rd),
.ras_n(rras0_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n)
);
//
drammem dramko2(
.ma(ra),
.d(rd),
.ras_n(rras1_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n)
);
defparam dramko1._verbose_ = 0;
defparam dramko2._verbose_ = 0;
defparam dramko1._init_ = 0;
defparam dramko2._init_ = 0;
`ifndef GATE
// trace rom page
wire rma14,rma15;
assign rma14 = DUT.page[0][0];
assign rma15 = DUT.page[0][1];
always @(rma14 or rma15)
begin
// $display("at time %t us",$time/1000000);
// case( {rma15, rma14} )
// 2'b00: $display("BASIC 48");
// 2'b01: $display("TR-DOS");
// 2'b10: $display("BASIC 128");
// 2'b11: $display("GLUKROM");
// default: $display("unknown");
// endcase
// $display("");
end
// trace ram page
wire [5:0] rpag;
assign rpag=DUT.page[3][5:0];
always @(rpag)
begin
// $display("at time %t us",$time/1000000);
// $display("RAM page is %d",rpag);
// $display("");
end
// key presses/nmi/whatsoever
initial
begin
#1;
tb.DUT.zkbdmus.kbd = 40'd0;
tb.DUT.zkbdmus.kbd[36] = 1'b1;
@(negedge int_n);
@(negedge int_n);
tb.DUT.zkbdmus.kbd[36] = 1'b0;
end
`endif
`ifdef ZLOG
reg [ 7:0] old_opcode;
reg [15:0] old_opcode_addr;
wire [7:0] zdd = zd_dut_to_z80;
reg was_m1;
always @(zm1_n)
if( zm1_n )
was_m1 <= 1'b0;
else
was_m1 = 1'b1;
always @(posedge (zmreq_n | zrd_n | zm1_n | (~zrfsh_n)) )
if( was_m1 )
begin
if( (zdd!==old_opcode) || (za!==old_opcode_addr) )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80OPROM: addr %x, opcode %x, time %t",za,zdd,$time);
$display("Z80OPROM: addr %x, opcode %x",za,zdd);
else
// $display("Z80OPRAM: addr %x, opcode %x, time %t",za,zdd,$time);
$display("Z80OPRAM: addr %x, opcode %x",za,zdd);
end
old_opcode = zdd;
old_opcode_addr = za;
end
always @(posedge (zmreq_n | zrd_n | (~zm1_n) | (~zrfsh_n)) )
if( !was_m1 )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80RDROM: addr %x, rddata %x, time %t",za,zdd,$time);
$display("Z80RDROM: addr %x, rddata %x",za,zdd);
else
// $display("Z80RDRAM: addr %x, rddata %x, time %t",za,zdd,$time);
$display("Z80RDRAM: addr %x, rddata %x",za,zdd);
end
always @(posedge (zmreq_n | zwr_n | (~zm1_n) | (~zrfsh_n)) )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80WRROM: addr %x, wrdata %x, time %t",za,zd,$time);
$display("Z80WRROM: addr %x, wrdata %x",za,zd);
else
// $display("Z80WRRAM: addr %x, wrdata %x, time %t",za,zd,$time);
$display("Z80WRRAM: addr %x, wrdata %x",za,zd);
end
`endif
// turbo
`ifdef C7MHZ
initial
force tb.DUT.zclock.turbo = 2'b01;
`else
`ifdef C35MHZ
initial
force tb.DUT.zclock.turbo = 2'b00;
`endif
`endif
// raster type
`ifdef CCONTEND
initial
force tb.DUT.modes_raster = 2'b10;
`endif
`ifdef NMITEST2
`define M48K
initial
begin
int i,fd;
logic [7:0] ldbyte;
reset_pc=16'h8000;
reset_sp=16'h8000;
fd = $fopen("dimkanmi.bin","rb");
if( !fd )
begin
$display("Can't open 'dimkanmi.bin'!");
$stop;
end
i='h8000;
begin : load_loop
while(1)
begin
if( 1!=$fread(ldbyte,fd) ) disable load_loop;
put_byte_48k(i,ldbyte);
i=i+1;
end
end
$fclose(fd);
wait(res===1'b0);
#(0.2);
tb.DUT.zports.atm_turbo = 1'b1;
tb.DUT.zports.peff7_int[4] = 1'b0;
#(100000); // 100 us
//force nmi_n = 1'b0;
@(posedge fclk);
force tb.DUT.imm_nmi = 1'b1;
@(posedge fclk);
release tb.DUT.imm_nmi;
end
`endif
`ifdef NMITEST3
`define M48K
initial
begin
int i,fd;
logic [7:0] ldbyte;
reset_pc=16'h0068;
reset_sp=16'h8000;
#(0.1); // let M48K rom load execute
fd = $fopen("dimkarom.bin","rb");
if( !fd )
begin
$display("Can't open 'dimkarom.bin'!");
$stop;
end
i='h0066;
begin : load_loop
while(1)
begin
if( 1!=$fread(ldbyte,fd) ) disable load_loop;
tb.romko.zxevo_rom.mem[i]=ldbyte;
i=i+1;
end
end
$fclose(fd);
wait(res===1'b0);
#(0.2);
tb.DUT.zports.atm_turbo = 1'b1;
tb.DUT.zports.peff7_int[4] = 1'b0;
#(1000000); // 1 ms
//force nmi_n = 1'b0;
@(posedge fclk);
force tb.DUT.imm_nmi = 1'b1;
@(posedge fclk);
release tb.DUT.imm_nmi;
end
`endif
// port #FE monitor
wire fe_write;
assign fe_write = (za[7:0]==8'hFE) && !wr_n && !iorq_n;
always @(negedge fe_write)
$display("port #FE monitor: border is %d at %t",zd[2:0],$time());
always @(negedge nmi_n)
$display("nmi monitor: negative edge at %t",$time());
// start in 48k mode
`ifdef M48K
initial
begin : force_48k_mode
int i;
int fd;
fd = $fopen("48.rom","rb");
if( 16384!=$fread(tb.romko.zxevo_rom.mem,fd) )
begin
$display("Couldn't load 48k ROM!\n");
$stop;
end
$fclose(fd);
wait(res===1'b0);
#(0.1);
tb.DUT.zports.atm_turbo = 1'b0;
tb.DUT.zports.atm_pen = 1'b0;
tb.DUT.zports.atm_cpm_n = 1'b1;
tb.DUT.zports.atm_pen2 = 1'b0;
tb.DUT.zdos.dos = 1'b0;
tb.DUT.instantiate_atm_pagers[0].atm_pager.pages[0] = 'd0;
tb.DUT.instantiate_atm_pagers[1].atm_pager.pages[0] = 'd5;
tb.DUT.instantiate_atm_pagers[2].atm_pager.pages[0] = 'd2;
tb.DUT.instantiate_atm_pagers[3].atm_pager.pages[0] = 'd0;
tb.DUT.instantiate_atm_pagers[0].atm_pager.pages[1] = 'd0;
tb.DUT.instantiate_atm_pagers[1].atm_pager.pages[1] = 'd5;
tb.DUT.instantiate_atm_pagers[2].atm_pager.pages[1] = 'd2;
tb.DUT.instantiate_atm_pagers[3].atm_pager.pages[1] = 'd0;
tb.DUT.instantiate_atm_pagers[0].atm_pager.ramnrom[0] = 'd0;
tb.DUT.instantiate_atm_pagers[1].atm_pager.ramnrom[0] = 'd1;
tb.DUT.instantiate_atm_pagers[2].atm_pager.ramnrom[0] = 'd1;
tb.DUT.instantiate_atm_pagers[3].atm_pager.ramnrom[0] = 'd1;
tb.DUT.instantiate_atm_pagers[0].atm_pager.ramnrom[1] = 'd0;
tb.DUT.instantiate_atm_pagers[1].atm_pager.ramnrom[1] = 'd1;
tb.DUT.instantiate_atm_pagers[2].atm_pager.ramnrom[1] = 'd1;
tb.DUT.instantiate_atm_pagers[3].atm_pager.ramnrom[1] = 'd1;
tb.DUT.zports.atm_scr_mode = 3'b011;
tb.DUT.zports.peff7_int = 8'h14;
tb.DUT.zports.p7ffd_int = 8'h30;
for(i=0;i<512;i=i+1)
begin : set_palette // R G B
tb.DUT.video_top.video_palframe.palette[i] = { (i[1]?{1'b1,i[3]}:2'b00), 1'b0, (i[2]?{1'b1,i[3]}:2'b00), 1'b0, (i[0]?{1'b1,i[3]}:2'b00) };
end
end
`endif
// load and start some code after we've reached "1982 Sinclair research ltd"
`ifdef START_LOAD
initial
begin
int i,fd;
logic [7:0] ldbyte;
wait( za==16'h15e0 && zmreq_n==1'b0 && zrd_n == 1'b0 );
$display("loading and starting...");
fd = $fopen(`START_NAME,"rb");
for(i=`START_ADDR;i<`START_ADDR+`START_LEN;i=i+1)
begin
if( 1!=$fread(ldbyte,fd) )
begin
$display("can't read byte from input file!");
$stop;
end
put_byte_48k(i,ldbyte);
end
$fclose(fd);
$display("load ok!");
reset_pc = 16'h9718;
reset_sp = 16'h6000;
@(posedge clkz_in);
force tb.zrst_n = 1'b0;
repeat(3) @(posedge clkz_in);
release tb.zrst_n;
@(posedge clkz_in);
reset_pc = 16'h0000;
reset_sp = 16'hFFFF;
end
`endif
`ifndef NO_PIXER
// picture out
pixer pixer
(
.clk(fclk),
.vsync(vsync),
.hsync(hsync),
.red(red),
.grn(grn),
.blu(blu)
);
`endif
/*
// time ticks
always
begin : timemark
integer ms;
ms = ($time/1000000);
// $display("timemark %d ms",ms);
#10000000.0; // 1 ms
end
*/
// init dram
`ifndef NMITEST2
initial
begin : init_dram
integer i;
integer page;
integer offset;
reg [7:0] trd [0:655359];
integer fd;
integer size;
for(i=0;i<4*1024*1024;i=i+1)
begin
put_byte(i,(i%257));
end
// load TRD
fd = $fopen("boot.trd","rb");
size=$fread(trd,fd);
if( size>655360 || size<=0 )
begin
$display("Couldn't load or wrong boot.trd!\n");
$stop;
end
$fclose(fd);
// copy TRD to RAM
page = 32'h0F4;
offset = 0;
for(i=0;i<size;i=i+1)
begin
put_byte( .addr(page*16384+offset), .data(trd[i]) );
offset = offset + 1;
if( offset>=16384 )
begin
offset = 0;
page = page - 1;
end
end
$display("boot.trd loaded!\n");
end
`endif
// cmos simulation
wire [7:0] cmos_addr;
wire [7:0] cmos_read;
wire [7:0] cmos_write;
wire cmos_rnw;
wire cmos_req;
cmosemu cmosemu
(
.zclk(clkz_in),
.cmos_req (cmos_req ),
.cmos_addr (cmos_addr ),
.cmos_rnw (cmos_rnw ),
.cmos_read (cmos_read ),
.cmos_write(cmos_write)
);
assign cmos_req = tb.DUT.wait_start_gluclock;
assign cmos_rnw = tb.DUT.wait_rnw;
assign cmos_addr = tb.DUT.gluclock_addr;
assign cmos_write = tb.DUT.wait_write;
always @*
force tb.DUT.wait_read = cmos_read;
`ifdef SPITEST
// spitest printing module
// does not hurt at any time (yet), so attached forever
spitest_print spitest_print(
.sdclk (sdclk ),
.sddi (sddi ),
.sddo (sddo ),
.sdcs_n(sdcs_n)
);
// spitest AVR imitator
spitest_avr spitest_avr(
.spick (spick ),
.spics_n(spics_n),
.spido (spido ),
.spidi (spidi )
);
`else
assign sddi = 1'b1;
assign spics_n = 1'b1;
assign spick = 1'b0;
assign spido = 1'b1;
`endif
// set up breakpoint
/*
wire bpt = za===16'h3FEC && zmreq_n===1'b0 && zrd_n===1'b0 && zm1_n===1'b0;
initial
begin
#(1_800_000_000);
@(posedge fclk);
forever
begin
@(posedge bpt);
$display("Stop at breakpoint");
$stop;
end
end
*/
// log INI command
wire [15:0] #(0.1) dza;
wire [ 7:0] #(0.1) dzw;
wire [ 7:0] #(0.1) dzr;
typedef enum {FETCH,MRD,MWR,IORD,IOWR,IACK} cycle_t;
cycle_t curr_cycle;
cycle_t cycles[0:3];
logic [15:0] addrs[0:3];
logic [ 7:0] wdata[0:3];
logic [ 7:0] rdata[0:3];
wire is_fetch, is_mrd, is_mwr, is_iord, is_iowr, is_iack;
wire is_any;
assign dza = za;
assign dzw = zd;
assign dzr = zd_dut_to_z80;
assign is_fetch = zm1_n===1'b0 && zmreq_n===1'b0 && zrd_n===1'b0;
assign is_mrd = zm1_n===1'b1 && zmreq_n===1'b0 && zrd_n===1'b0;
assign is_mwr = zmreq_n===1'b0 && zwr_n===1'b0;
assign is_iord = ziorq_n===1'b0 && zrd_n===1'b0;
assign is_iowr = ziorq_n===1'b0 && zwr_n===1'b0;
assign is_iack = zm1_n===1'b0 && ziorq_n===1'b0;
assign is_any = is_fetch || is_mrd || is_mwr || is_iord || is_iowr || is_iack;
always @(negedge is_any)
begin : remember
int i;
for(i=1;i<4;i++)
begin
addrs [i] <= addrs [i-1];
cycles[i] <= cycles[i-1];
wdata [i] <= wdata [i-1];
rdata [i] <= rdata [i-1];
end
addrs[0] <= dza;
cycles[0] <= curr_cycle;
wdata[0] <= dzw;
rdata[0] <= dzr;
end
always @(posedge is_any)
if( is_fetch ) curr_cycle <= FETCH;
else if( is_mrd ) curr_cycle <= MRD;
else if( is_mwr ) curr_cycle <= MWR;
else if( is_iord ) curr_cycle <= IORD;
else if( is_iowr ) curr_cycle <= IOWR;
else if( is_iack ) curr_cycle <= IACK;
else
begin
$display("Spurious cycle detect!");
$stop;
end
// actual break
always @(negedge is_any)
begin
if( cycles[3]==FETCH && addrs[3][15:0 ]==16'h3FEC && rdata[3]==8'hED &&
cycles[2]==FETCH && rdata[2]==8'hA2 &&
cycles[1]==IORD &&
cycles[0]==MWR && addrs[0][15:14]== 2'd0
)
begin
$display("trd INI caught! port=%04x, wraddr=%04x, time=%t",addrs[1],addrs[0],$time());
end
end
// timestamps
always
begin
$display("Running for %t ms",$time()/1000000000.0);
#1000000.0;
end
// generate nmi after 2s
initial
begin
#2000000000.0;
force DUT.set_nmi[0] = 1'b1;
#1000000.0;
release DUT.set_nmi[0];
end
task put_byte;
input [21:0] addr;
input [ 7:0] data;
reg [19:0] arraddr;
begin
arraddr = { addr[21:12], addr[11:2] };
case( addr[1:0] ) // chipsel, bytesel
2'b00: tb.dramko1.array[arraddr][15:8] = data;
2'b01: tb.dramko1.array[arraddr][ 7:0] = data;
2'b10: tb.dramko2.array[arraddr][15:8] = data;
2'b11: tb.dramko2.array[arraddr][ 7:0] = data;
endcase
end
endtask
task put_byte_48k
(
input [15:0] addr,
input [ 7:0] data
);
case( addr[15:14] )
2'b01: put_byte(addr-16'h4000 + 22'h14000,data);
2'b10: put_byte(addr-16'h8000 + 22'h08000,data);
2'b11: put_byte(addr-16'hc000 + 22'h00000,data);
endcase
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
/**
* udp_dff$PE_pp$PG$N: Positive edge triggered enabled D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pe_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg DATA_EN;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DATA_EN = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DATA_EN = 1'b0;
#60 NOTIFIER = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 DATA_EN = 1'b1;
#160 NOTIFIER = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 DATA_EN = 1'b0;
#260 NOTIFIER = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 NOTIFIER = 1'b1;
#380 DATA_EN = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 NOTIFIER = 1'bx;
#480 DATA_EN = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PE_pp$PG$N dut (.D(D), .DATA_EN(DATA_EN), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PE_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_1_V
`define SKY130_FD_SC_HD__A41OI_1_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_1_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_idelay16(
input [15:0] IDATAIN,
output [15:0] DATAOUT,
input INC,
input CE,
input RST,
input CAL,
input CLK,
input IOCLK0,
input IOCLK1
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay0 (
.IDATAIN(IDATAIN[0]),
.DATAOUT(DATAOUT[0]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay1 (
.IDATAIN(IDATAIN[1]),
.DATAOUT(DATAOUT[1]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay2 (
.IDATAIN(IDATAIN[2]),
.DATAOUT(DATAOUT[2]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay3 (
.IDATAIN(IDATAIN[3]),
.DATAOUT(DATAOUT[3]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay4 (
.IDATAIN(IDATAIN[4]),
.DATAOUT(DATAOUT[4]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay5 (
.IDATAIN(IDATAIN[5]),
.DATAOUT(DATAOUT[5]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay6 (
.IDATAIN(IDATAIN[6]),
.DATAOUT(DATAOUT[6]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay7 (
.IDATAIN(IDATAIN[7]),
.DATAOUT(DATAOUT[7]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay8 (
.IDATAIN(IDATAIN[8]),
.DATAOUT(DATAOUT[8]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay9 (
.IDATAIN(IDATAIN[9]),
.DATAOUT(DATAOUT[9]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay10 (
.IDATAIN(IDATAIN[10]),
.DATAOUT(DATAOUT[10]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay11 (
.IDATAIN(IDATAIN[11]),
.DATAOUT(DATAOUT[11]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay12 (
.IDATAIN(IDATAIN[12]),
.DATAOUT(DATAOUT[12]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay13 (
.IDATAIN(IDATAIN[13]),
.DATAOUT(DATAOUT[13]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay14 (
.IDATAIN(IDATAIN[14]),
.DATAOUT(DATAOUT[14]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
IODELAY2 #(
.DELAY_SRC("IDATAIN"),
.IDELAY_TYPE("VARIABLE_FROM_ZERO"),
.DATA_RATE("DDR")
) idelay15 (
.IDATAIN(IDATAIN[15]),
.DATAOUT(DATAOUT[15]),
.INC(INC),
.CE(CE),
.RST(RST),
.CLK(CLK),
.IOCLK0(IOCLK0),
.IOCLK1(IOCLK1),
.ODATAIN(1'b0),
.CAL(CAL),
.T(1'b1)
);
endmodule
|
//======================================================================
//
// sha512_w_mem_regs.v
// -------------------
// The W memory for the SHA-512 core. This version uses 16
// 32-bit registers as a sliding window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module sha512_w_mem(
input wire clk,
input wire reset_n,
input wire [1023 : 0] block,
input wire init,
input wire next,
output wire [63 : 0] w
);
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] w_mem [0 : 15];
reg [63 : 0] w_mem00_new;
reg [63 : 0] w_mem01_new;
reg [63 : 0] w_mem02_new;
reg [63 : 0] w_mem03_new;
reg [63 : 0] w_mem04_new;
reg [63 : 0] w_mem05_new;
reg [63 : 0] w_mem06_new;
reg [63 : 0] w_mem07_new;
reg [63 : 0] w_mem08_new;
reg [63 : 0] w_mem09_new;
reg [63 : 0] w_mem10_new;
reg [63 : 0] w_mem11_new;
reg [63 : 0] w_mem12_new;
reg [63 : 0] w_mem13_new;
reg [63 : 0] w_mem14_new;
reg [63 : 0] w_mem15_new;
reg w_mem_we;
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] w_tmp;
reg [63 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
integer i;
if (!reset_n)
begin
for (i = 0; i < 16; i = i + 1)
w_mem[i] <= 64'h0;
w_ctr_reg <= 7'h0;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
w_tmp = w_mem[w_ctr_reg[3 : 0]];
else
w_tmp = w_new;
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [63 : 0] w_0;
reg [63 : 0] w_1;
reg [63 : 0] w_9;
reg [63 : 0] w_14;
reg [63 : 0] d0;
reg [63 : 0] d1;
w_mem00_new = 64'h0;
w_mem01_new = 64'h0;
w_mem02_new = 64'h0;
w_mem03_new = 64'h0;
w_mem04_new = 64'h0;
w_mem05_new = 64'h0;
w_mem06_new = 64'h0;
w_mem07_new = 64'h0;
w_mem08_new = 64'h0;
w_mem09_new = 64'h0;
w_mem10_new = 64'h0;
w_mem11_new = 64'h0;
w_mem12_new = 64'h0;
w_mem13_new = 64'h0;
w_mem14_new = 64'h0;
w_mem15_new = 64'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[0], w_1[63 : 1]} ^ // ROTR1
{w_1[7 : 0], w_1[63 : 8]} ^ // ROTR8
{7'b0000000, w_1[63 : 7]}; // SHR7
d1 = {w_14[18 : 0], w_14[63 : 19]} ^ // ROTR19
{w_14[60 : 0], w_14[63 : 61]} ^ // ROTR61
{6'b000000, w_14[63 : 6]}; // SHR6
w_new = w_0 + d0 + w_9 + d1;
if (init)
begin
w_mem00_new = block[1023 : 960];
w_mem01_new = block[959 : 896];
w_mem02_new = block[895 : 832];
w_mem03_new = block[831 : 768];
w_mem04_new = block[767 : 704];
w_mem05_new = block[703 : 640];
w_mem06_new = block[639 : 576];
w_mem07_new = block[575 : 512];
w_mem08_new = block[511 : 448];
w_mem09_new = block[447 : 384];
w_mem10_new = block[383 : 320];
w_mem11_new = block[319 : 256];
w_mem12_new = block[255 : 192];
w_mem13_new = block[191 : 128];
w_mem14_new = block[127 : 64];
w_mem15_new = block[63 : 0];
w_mem_we = 1;
end
if (next && (w_ctr_reg > 15))
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 7'h0;
w_ctr_we = 1'h0;
if (init)
begin
w_ctr_new = 7'h00;
w_ctr_we = 1'h1;
end
if (next)
begin
w_ctr_new = w_ctr_reg + 7'h01;
w_ctr_we = 1'h1;
end
end // w_ctr
endmodule // sha512_w_mem
//======================================================================
// sha512_w_mem.v
//======================================================================
|
(** * MoreStlc: More on the Simply Typed Lambda-Calculus *)
Require Export Stlc.
(* ###################################################################### *)
(** * Simple Extensions to STLC *)
(** The simply typed lambda-calculus has enough structure to make its
theoretical properties interesting, but it is not much of a
programming language. In this chapter, we begin to close the gap
with real-world languages by introducing a number of familiar
features that have straightforward treatments at the level of
typing. *)
(** ** Numbers *)
(** Adding types, constants, and primitive operations for numbers is
easy -- just a matter of combining the [Types] and [Stlc]
chapters. *)
(** ** Unit *)
(** Another handy base type, found especially in languages in
the ML family, is the singleton type [Unit]. *)
(** It has a single element -- the term constant [unit] (with a small
[u]) -- and a typing rule making [unit] an element of [Unit]. We
also add [unit] to the set of possible result values of
computations -- indeed, [unit] is the _only_ possible result of
evaluating an expression of type [Unit]. *)
(** Syntax:
<<
t ::= Terms
| ...
| unit unit value
v ::= Values
| ...
| unit unit
T ::= Types
| ...
| Unit Unit type
>>
Typing:
-------------------- (T_Unit)
Gamma |- unit : Unit
*)
(** It may seem a little strange to bother defining a type that
has just one element -- after all, wouldn't every computation
living in such a type be trivial?
This is a fair question, and indeed in the STLC the [Unit] type is
not especially critical (though we'll see two uses for it below).
Where [Unit] really comes in handy is in richer languages with
various sorts of _side effects_ -- e.g., assignment statements
that mutate variables or pointers, exceptions and other sorts of
nonlocal control structures, etc. In such languages, it is
convenient to have a type for the (trivial) result of an
expression that is evaluated only for its effect. *)
(** ** Pairs *)
(** Our functional programming examples in Coq have made
frequent use of _pairs_ of values. The type of such pairs is
called a _product type_.
The formalization of pairs is almost too simple to be worth
discussing. However, let's look briefly at the various parts of
the definition to emphasize the common pattern. *)
(** In Coq, the primitive way of extracting the components of a pair
is _pattern matching_. An alternative style is to take [fst] and
[snd] -- the first- and second-projection operators -- as
primitives. Just for fun, let's do our products this way. For
example, here's how we'd write a function that takes a pair of
numbers and returns the pair of their sum and difference:
<<
\x:Nat*Nat.
let sum = x.fst + x.snd in
let diff = x.fst - x.snd in
(sum,diff)
>>
*)
(** Adding pairs to the simply typed lambda-calculus, then, involves
adding two new forms of term -- pairing, written [(t1,t2)], and
projection, written [t.fst] for the first projection from [t] and
[t.snd] for the second projection -- plus one new type constructor,
[T1*T2], called the _product_ of [T1] and [T2]. *)
(** Syntax:
<<
t ::= Terms
| ...
| (t,t) pair
| t.fst first projection
| t.snd second projection
v ::= Values
| ...
| (v,v) pair value
T ::= Types
| ...
| T * T product type
>>
*)
(** For evaluation, we need several new rules specifying how pairs and
projection behave.
t1 ==> t1'
-------------------- (ST_Pair1)
(t1,t2) ==> (t1',t2)
t2 ==> t2'
-------------------- (ST_Pair2)
(v1,t2) ==> (v1,t2')
t1 ==> t1'
------------------ (ST_Fst1)
t1.fst ==> t1'.fst
------------------ (ST_FstPair)
(v1,v2).fst ==> v1
t1 ==> t1'
------------------ (ST_Snd1)
t1.snd ==> t1'.snd
------------------ (ST_SndPair)
(v1,v2).snd ==> v2
*)
(**
Rules [ST_FstPair] and [ST_SndPair] specify that, when a fully
evaluated pair meets a first or second projection, the result is
the appropriate component. The congruence rules [ST_Fst1] and
[ST_Snd1] allow reduction to proceed under projections, when the
term being projected from has not yet been fully evaluated.
[ST_Pair1] and [ST_Pair2] evaluate the parts of pairs: first the
left part, and then -- when a value appears on the left -- the right
part. The ordering arising from the use of the metavariables [v]
and [t] in these rules enforces a left-to-right evaluation
strategy for pairs. (Note the implicit convention that
metavariables like [v] and [v1] can only denote values.) We've
also added a clause to the definition of values, above, specifying
that [(v1,v2)] is a value. The fact that the components of a pair
value must themselves be values ensures that a pair passed as an
argument to a function will be fully evaluated before the function
body starts executing. *)
(** The typing rules for pairs and projections are straightforward.
Gamma |- t1 : T1 Gamma |- t2 : T2
--------------------------------------- (T_Pair)
Gamma |- (t1,t2) : T1*T2
Gamma |- t1 : T11*T12
--------------------- (T_Fst)
Gamma |- t1.fst : T11
Gamma |- t1 : T11*T12
--------------------- (T_Snd)
Gamma |- t1.snd : T12
*)
(** The rule [T_Pair] says that [(t1,t2)] has type [T1*T2] if [t1] has
type [T1] and [t2] has type [T2]. Conversely, the rules [T_Fst]
and [T_Snd] tell us that, if [t1] has a product type
[T11*T12] (i.e., if it will evaluate to a pair), then the types of
the projections from this pair are [T11] and [T12]. *)
(* ###################################################################### *)
(** ** Records *)
(** Now let's look briefly at how to define _records_ and their types.
Intuitively, records can be obtained from pairs by two kinds of
generalization: they are n-ary products (rather than just binary) and
their fields are accessed by _label_ (rather than position).
Conceptually, this extension is a straightforward generalization
of pairs and product types, but notationally it becomes a little
heavier; for this reason, we postpone its formal treatment to a
separate chapter ([Records]). *)
(** Records are not included in the extended exercise below, but
they will be useful to motivate the [Sub] chapter. *)
(** Syntax:
<<
t ::= Terms
| ...
| {i1=t1, ..., in=tn} record
| t.i projection
v ::= Values
| ...
| {i1=v1, ..., in=vn} record value
T ::= Types
| ...
| {i1:T1, ..., in:Tn} record type
>>
Intuitively, the generalization is pretty obvious. But it's worth
noticing that what we've actually written is rather informal: in
particular, we've written "[...]" in several places to mean "any
number of these," and we've omitted explicit mention of the usual
side-condition that the labels of a record should not contain
repetitions. *)
(** It is possible to devise informal notations that are
more precise, but these tend to be quite heavy and to obscure the
main points of the definitions. So we'll leave these a bit loose
here (they are informal anyway, after all) and do the work of
tightening things up elsewhere (in chapter [Records]). *)
(**
Reduction:
ti ==> ti'
------------------------------------ (ST_Rcd)
{i1=v1, ..., im=vm, in=ti, ...}
==> {i1=v1, ..., im=vm, in=ti', ...}
t1 ==> t1'
-------------- (ST_Proj1)
t1.i ==> t1'.i
------------------------- (ST_ProjRcd)
{..., i=vi, ...}.i ==> vi
Again, these rules are a bit informal. For example, the first rule
is intended to be read "if [ti] is the leftmost field that is not a
value and if [ti] steps to [ti'], then the whole record steps..."
In the last rule, the intention is that there should only be one
field called i, and that all the other fields must contain values. *)
(**
Typing:
Gamma |- t1 : T1 ... Gamma |- tn : Tn
-------------------------------------------------- (T_Rcd)
Gamma |- {i1=t1, ..., in=tn} : {i1:T1, ..., in:Tn}
Gamma |- t : {..., i:Ti, ...}
----------------------------- (T_Proj)
Gamma |- t.i : Ti
*)
(* ###################################################################### *)
(** *** Encoding Records (Optional) *)
(** There are several ways to make the above definitions precise.
- We can directly formalize the syntactic forms and inference
rules, staying as close as possible to the form we've given
them above. This is conceptually straightforward, and it's
probably what we'd want to do if we were building a real
compiler -- in particular, it will allow is to print error
messages in the form that programmers will find easy to
understand. But the formal versions of the rules will not be
pretty at all!
- We could look for a smoother way of presenting records -- for
example, a binary presentation with one constructor for the
empty record and another constructor for adding a single field
to an existing record, instead of a single monolithic
constructor that builds a whole record at once. This is the
right way to go if we are primarily interested in studying the
metatheory of the calculi with records, since it leads to
clean and elegant definitions and proofs. Chapter [Records]
shows how this can be done.
- Alternatively, if we like, we can avoid formalizing records
altogether, by stipulating that record notations are just
informal shorthands for more complex expressions involving
pairs and product types. We sketch this approach here.
First, observe that we can encode arbitrary-size tuples using
nested pairs and the [unit] value. To avoid overloading the pair
notation [(t1,t2)], we'll use curly braces without labels to write
down tuples, so [{}] is the empty tuple, [{5}] is a singleton
tuple, [{5,6}] is a 2-tuple (morally the same as a pair),
[{5,6,7}] is a triple, etc.
<<
{} ----> unit
{t1, t2, ..., tn} ----> (t1, trest)
where {t2, ..., tn} ----> trest
>>
Similarly, we can encode tuple types using nested product types:
<<
{} ----> Unit
{T1, T2, ..., Tn} ----> T1 * TRest
where {T2, ..., Tn} ----> TRest
>>
The operation of projecting a field from a tuple can be encoded
using a sequence of second projections followed by a first projection:
<<
t.0 ----> t.fst
t.(n+1) ----> (t.snd).n
>>
Next, suppose that there is some total ordering on record labels,
so that we can associate each label with a unique natural number.
This number is called the _position_ of the label. For example,
we might assign positions like this:
<<
LABEL POSITION
a 0
b 1
c 2
... ...
foo 1004
... ...
bar 10562
... ...
>>
We use these positions to encode record values as tuples (i.e., as
nested pairs) by sorting the fields according to their positions.
For example:
<<
{a=5, b=6} ----> {5,6}
{a=5, c=7} ----> {5,unit,7}
{c=7, a=5} ----> {5,unit,7}
{c=5, b=3} ----> {unit,3,5}
{f=8,c=5,a=7} ----> {7,unit,5,unit,unit,8}
{f=8,c=5} ----> {unit,unit,5,unit,unit,8}
>>
Note that each field appears in the position associated with its
label, that the size of the tuple is determined by the label with
the highest position, and that we fill in unused positions with
[unit].
We do exactly the same thing with record types:
<<
{a:Nat, b:Nat} ----> {Nat,Nat}
{c:Nat, a:Nat} ----> {Nat,Unit,Nat}
{f:Nat,c:Nat} ----> {Unit,Unit,Nat,Unit,Unit,Nat}
>>
Finally, record projection is encoded as a tuple projection from
the appropriate position:
<<
t.l ----> t.(position of l)
>>
It is not hard to check that all the typing rules for the original
"direct" presentation of records are validated by this
encoding. (The reduction rules are "almost validated" -- not
quite, because the encoding reorders fields.) *)
(** Of course, this encoding will not be very efficient if we
happen to use a record with label [bar]! But things are not
actually as bad as they might seem: for example, if we assume that
our compiler can see the whole program at the same time, we can
_choose_ the numbering of labels so that we assign small positions
to the most frequently used labels. Indeed, there are industrial
compilers that essentially do this! *)
(** ** [let]-bindings *)
(** When writing a complex expression, it is often useful to give
names to some of its subexpressions: this avoids repetition and
often increases readability. Most languages provide one or more
ways of doing this. In OCaml (and Coq), for example, we can write
[let x=t1 in t2] to mean ``evaluate the expression [t1] and bind
the name [x] to the resulting value while evaluating [t2].''
Our [let]-binder follows OCaml's in choosing a call-by-value
evaluation order, where the [let]-bound term must be fully
evaluated before evaluation of the [let]-body can begin. The
typing rule [T_Let] tells us that the type of a [let] can be
calculated by calculating the type of the [let]-bound term,
extending the context with a binding with this type, and in this
enriched context calculating the type of the body, which is then
the type of the whole [let] expression.
At this point in the course, it's probably easier simply to look
at the rules defining this new feature as to wade through a lot of
english text conveying the same information. Here they are: *)
(** Syntax:
<<
t ::= Terms
| ... (other terms same as before)
| let x=t in t let-binding
>>
*)
(**
Reduction:
t1 ==> t1'
---------------------------------- (ST_Let1)
let x=t1 in t2 ==> let x=t1' in t2
---------------------------- (ST_LetValue)
let x=v1 in t2 ==> [x:=v1]t2
Typing:
Gamma |- t1 : T1 Gamma , x:T1 |- t2 : T2
-------------------------------------------- (T_Let)
Gamma |- let x=t1 in t2 : T2
*)
(** ** Sums *)
(** Many programs need to deal with values that can take two distinct
forms. For example, we might identify employees in an accounting
application using using _either_ their name _or_ their id number.
A search function might return _either_ a matching value _or_ an
error code.
These are specific examples of a binary _sum type_,
which describes a set of values drawn from exactly two given types, e.g.
<<
Nat + Bool
>>
*)
(** We create elements of these types by _tagging_ elements of
the component types. For example, if [n] is a [Nat] then [inl v]
is an element of [Nat+Bool]; similarly, if [b] is a [Bool] then
[inr b] is a [Nat+Bool]. The names of the tags [inl] and [inr]
arise from thinking of them as functions
<<
inl : Nat -> Nat + Bool
inr : Bool -> Nat + Bool
>>
that "inject" elements of [Nat] or [Bool] into the left and right
components of the sum type [Nat+Bool]. (But note that we don't
actually treat them as functions in the way we formalize them:
[inl] and [inr] are keywords, and [inl t] and [inr t] are primitive
syntactic forms, not function applications. This allows us to give
them their own special typing rules.) *)
(** In general, the elements of a type [T1 + T2] consist of the
elements of [T1] tagged with the token [inl], plus the elements of
[T2] tagged with [inr]. *)
(** One important usage of sums is signaling errors:
<<
div : Nat -> Nat -> (Nat + Unit) =
div =
\x:Nat. \y:Nat.
if iszero y then
inr unit
else
inl ...
>>
The type [Nat + Unit] above is in fact isomorphic to [option nat]
in Coq, and we've already seen how to signal errors with options. *)
(** To _use_ elements of sum types, we introduce a [case]
construct (a very simplified form of Coq's [match]) to destruct
them. For example, the following procedure converts a [Nat+Bool]
into a [Nat]: *)
(**
<<
getNat =
\x:Nat+Bool.
case x of
inl n => n
| inr b => if b then 1 else 0
>>
*)
(** More formally... *)
(** Syntax:
<<
t ::= Terms
| ...
| inl T t tagging (left)
| inr T t tagging (right)
| case t of case
inl x => t
| inr x => t
v ::= Values
| ...
| inl T v tagged value (left)
| inr T v tagged value (right)
T ::= Types
| ...
| T + T sum type
>>
*)
(** Evaluation:
t1 ==> t1'
---------------------- (ST_Inl)
inl T t1 ==> inl T t1'
t1 ==> t1'
---------------------- (ST_Inr)
inr T t1 ==> inr T t1'
t0 ==> t0'
------------------------------------------- (ST_Case)
case t0 of inl x1 => t1 | inr x2 => t2 ==>
case t0' of inl x1 => t1 | inr x2 => t2
---------------------------------------------- (ST_CaseInl)
case (inl T v0) of inl x1 => t1 | inr x2 => t2
==> [x1:=v0]t1
---------------------------------------------- (ST_CaseInr)
case (inr T v0) of inl x1 => t1 | inr x2 => t2
==> [x2:=v0]t2
*)
(** Typing:
Gamma |- t1 : T1
---------------------------- (T_Inl)
Gamma |- inl T2 t1 : T1 + T2
Gamma |- t1 : T2
---------------------------- (T_Inr)
Gamma |- inr T1 t1 : T1 + T2
Gamma |- t0 : T1+T2
Gamma , x1:T1 |- t1 : T
Gamma , x2:T2 |- t2 : T
--------------------------------------------------- (T_Case)
Gamma |- case t0 of inl x1 => t1 | inr x2 => t2 : T
We use the type annotation in [inl] and [inr] to make the typing
simpler, similarly to what we did for functions. *)
(** Without this extra
information, the typing rule [T_Inl], for example, would have to
say that, once we have shown that [t1] is an element of type [T1],
we can derive that [inl t1] is an element of [T1 + T2] for _any_
type T2. For example, we could derive both [inl 5 : Nat + Nat]
and [inl 5 : Nat + Bool] (and infinitely many other types).
This failure of uniqueness of types would mean that we cannot
build a typechecking algorithm simply by "reading the rules from
bottom to top" as we could for all the other features seen so far.
There are various ways to deal with this difficulty. One simple
one -- which we've adopted here -- forces the programmer to
explicitly annotate the "other side" of a sum type when performing
an injection. This is rather heavyweight for programmers (and so
real languages adopt other solutions), but it is easy to
understand and formalize. *)
(** ** Lists *)
(** The typing features we have seen can be classified into _base
types_ like [Bool], and _type constructors_ like [->] and [*] that
build new types from old ones. Another useful type constructor is
[List]. For every type [T], the type [List T] describes
finite-length lists whose elements are drawn from [T].
In principle, we could encode lists using pairs, sums and
_recursive_ types. But giving semantics to recursive types is
non-trivial. Instead, we'll just discuss the special case of lists
directly.
Below we give the syntax, semantics, and typing rules for lists.
Except for the fact that explicit type annotations are mandatory
on [nil] and cannot appear on [cons], these lists are essentially
identical to those we built in Coq. We use [lcase] to destruct
lists, to avoid dealing with questions like "what is the [head] of
the empty list?" *)
(** For example, here is a function that calculates the sum of
the first two elements of a list of numbers:
<<
\x:List Nat.
lcase x of nil -> 0
| a::x' -> lcase x' of nil -> a
| b::x'' -> a+b
>>
*)
(**
Syntax:
<<
t ::= Terms
| ...
| nil T
| cons t t
| lcase t of nil -> t | x::x -> t
v ::= Values
| ...
| nil T nil value
| cons v v cons value
T ::= Types
| ...
| List T list of Ts
>>
*)
(** Reduction:
t1 ==> t1'
-------------------------- (ST_Cons1)
cons t1 t2 ==> cons t1' t2
t2 ==> t2'
-------------------------- (ST_Cons2)
cons v1 t2 ==> cons v1 t2'
t1 ==> t1'
---------------------------------------- (ST_Lcase1)
(lcase t1 of nil -> t2 | xh::xt -> t3) ==>
(lcase t1' of nil -> t2 | xh::xt -> t3)
----------------------------------------- (ST_LcaseNil)
(lcase nil T of nil -> t2 | xh::xt -> t3)
==> t2
----------------------------------------------- (ST_LcaseCons)
(lcase (cons vh vt) of nil -> t2 | xh::xt -> t3)
==> [xh:=vh,xt:=vt]t3
*)
(** Typing:
----------------------- (T_Nil)
Gamma |- nil T : List T
Gamma |- t1 : T Gamma |- t2 : List T
----------------------------------------- (T_Cons)
Gamma |- cons t1 t2: List T
Gamma |- t1 : List T1
Gamma |- t2 : T
Gamma , h:T1, t:List T1 |- t3 : T
------------------------------------------------- (T_Lcase)
Gamma |- (lcase t1 of nil -> t2 | h::t -> t3) : T
*)
(** ** General Recursion *)
(** Another facility found in most programming languages (including
Coq) is the ability to define recursive functions. For example,
we might like to be able to define the factorial function like
this:
<<
fact = \x:Nat.
if x=0 then 1 else x * (fact (pred x)))
>>
But this would require quite a bit of work to formalize: we'd have
to introduce a notion of "function definitions" and carry around an
"environment" of such definitions in the definition of the [step]
relation. *)
(** Here is another way that is straightforward to formalize: instead
of writing recursive definitions where the right-hand side can
contain the identifier being defined, we can define a _fixed-point
operator_ that performs the "unfolding" of the recursive definition
in the right-hand side lazily during reduction.
<<
fact =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 1 else x * (f (pred x)))
>>
*)
(** The intuition is that the higher-order function [f] passed
to [fix] is a _generator_ for the [fact] function: if [fact] is
applied to a function that approximates the desired behavior of
[fact] up to some number [n] (that is, a function that returns
correct results on inputs less than or equal to [n]), then it
returns a better approximation to [fact] -- a function that returns
correct results for inputs up to [n+1]. Applying [fix] to this
generator returns its _fixed point_ -- a function that gives the
desired behavior for all inputs [n].
(The term "fixed point" has exactly the same sense as in ordinary
mathematics, where a fixed point of a function [f] is an input [x]
such that [f(x) = x]. Here, a fixed point of a function [F] of
type (say) [(Nat->Nat)->(Nat->Nat)] is a function [f] such that [F
f] is behaviorally equivalent to [f].) *)
(** Syntax:
<<
t ::= Terms
| ...
| fix t fixed-point operator
>>
Reduction:
t1 ==> t1'
------------------ (ST_Fix1)
fix t1 ==> fix t1'
F = \xf:T1.t2
----------------------- (ST_FixAbs)
fix F ==> [xf:=fix F]t2
Typing:
Gamma |- t1 : T1->T1
-------------------- (T_Fix)
Gamma |- fix t1 : T1
*)
(** Let's see how [ST_FixAbs] works by reducing [fact 3 = fix F 3],
where [F = (\f. \x. if x=0 then 1 else x * (f (pred x)))] (we are
omitting type annotations for brevity here).
<<
fix F 3
>>
[==>] [ST_FixAbs]
<<
(\x. if x=0 then 1 else x * (fix F (pred x))) 3
>>
[==>] [ST_AppAbs]
<<
if 3=0 then 1 else 3 * (fix F (pred 3))
>>
[==>] [ST_If0_Nonzero]
<<
3 * (fix F (pred 3))
>>
[==>] [ST_FixAbs + ST_Mult2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 3))
>>
[==>] [ST_PredNat + ST_Mult2 + ST_App2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 2)
>>
[==>] [ST_AppAbs + ST_Mult2]
<<
3 * (if 2=0 then 1 else 2 * (fix F (pred 2)))
>>
[==>] [ST_If0_Nonzero + ST_Mult2]
<<
3 * (2 * (fix F (pred 2)))
>>
[==>] [ST_FixAbs + 2 x ST_Mult2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 2)))
>>
[==>] [ST_PredNat + 2 x ST_Mult2 + ST_App2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 1))
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
3 * (2 * (if 1=0 then 1 else 1 * (fix F (pred 1))))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
3 * (2 * (1 * (fix F (pred 1))))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)))
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
3 * (2 * (1 * 1))
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
3 * (2 * 1)
>>
[==>] [ST_MultNats + ST_Mult2]
<<
3 * 2
>>
[==>] [ST_MultNats]
<<
6
>>
*)
(** **** Exercise: 1 star, optional (halve_fix) *)
(** Translate this informal recursive definition into one using [fix]:
<<
halve =
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (halve (pred (pred x)))
>>
halve =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (f (pred (pred x))))
[]
*)
(** **** Exercise: 1 star, optional (fact_steps) *)
(** Write down the sequence of steps that the term [fact 1] goes
through to reduce to a normal form (assuming the usual reduction
rules for arithmetic operations).
fix F 1
>>
(\x. if x=0 then 1 else x * (fix F (pred x))) 1
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
if 1=0 then 1 else 1 * (fix F (pred 1))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
1 * (fix F (pred 1))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
1 * 1
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
1
[]
*)
(** The ability to form the fixed point of a function of type [T->T]
for any [T] has some surprising consequences. In particular, it
implies that _every_ type is inhabited by some term. To see this,
observe that, for every type [T], we can define the term
fix (\x:T.x)
By [T_Fix] and [T_Abs], this term has type [T]. By [ST_FixAbs]
it reduces to itself, over and over again. Thus it is an
_undefined element_ of [T].
More usefully, here's an example using [fix] to define a
two-argument recursive function:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
And finally, here is an example where [fix] is used to define a
_pair_ of recursive functions (illustrating the fact that the type
[T1] in the rule [T_Fix] need not be a function type):
<<
evenodd =
fix
(\eo: (Nat->Bool * Nat->Bool).
let e = \n:Nat. if n=0 then true else eo.snd (pred n) in
let o = \n:Nat. if n=0 then false else eo.fst (pred n) in
(e,o))
even = evenodd.fst
odd = evenodd.snd
>>
*)
(** *** Variants (Optional Reading) *)
(** Just as products can be generalized to records, sums can be
generalized to n-ary labeled types called _variants_. Instead of
[T1+T2], we can write something like [<l1:T1,l2:T2,...ln:Tn>]
where [l1],[l2],... are field labels which are used both to build
instances and as case arm labels.
These n-ary variants give us almost enough mechanism to build
arbitrary inductive data types like lists and trees from
scratch -- the only thing missing is a way to allow _recursion_ in
type definitions. We won't cover this here, but detailed
treatments can be found in many textbooks -- e.g., Types and
Programming Languages. *)
(* ###################################################################### *)
(** * Exercise: Formalizing the Extensions *)
(** **** Exercise: 4 stars, optional (STLC_extensions) *)
(** In this problem you will formalize a couple of the extensions
described above. We've provided the necessary additions to the
syntax of terms and types, and we've included a few examples that
you can test your definitions with to make sure they are working
as expected. You'll fill in the rest of the definitions and
extend all the proofs accordingly.
To get you started, we've provided implementations for:
- numbers
- pairs and units
- sums
- lists
You need to complete the implementations for:
- let (which involves binding)
- [fix]
A good strategy is to work on the extensions one at a time, in
multiple passes, rather than trying to work through the file from
start to finish in a single pass. For each definition or proof,
begin by reading carefully through the parts that are provided for
you, referring to the text in the [Stlc] chapter for high-level
intuitions and the embedded comments for detailed mechanics.
*)
Module STLCExtended.
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty
| TUnit : ty
| TProd : ty -> ty -> ty
| TSum : ty -> ty -> ty
| TList : ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TArrow" | Case_aux c "TNat"
| Case_aux c "TProd" | Case_aux c "TUnit"
| Case_aux c "TSum" | Case_aux c "TList" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* numbers *)
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* units *)
| tunit : tm
(* let *)
| tlet : id -> tm -> tm -> tm
(* i.e., [let x = t1 in t2] *)
(* sums *)
| tinl : ty -> tm -> tm
| tinr : ty -> tm -> tm
| tcase : tm -> id -> tm -> id -> tm -> tm
(* i.e., [case t0 of inl x1 => t1 | inr x2 => t2] *)
(* lists *)
| tnil : ty -> tm
| tcons : tm -> tm -> tm
| tlcase : tm -> tm -> id -> id -> tm -> tm
(* i.e., [lcase t1 of | nil -> t2 | x::y -> t3] *)
(* fix *)
| tfix : tm -> tm.
(** Note that, for brevity, we've omitted booleans and instead
provided a single [if0] form combining a zero test and a
conditional. That is, instead of writing
<<
if x = 0 then ... else ...
>>
we'll write this:
<<
if0 x then ... else ...
>>
*)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tnat" | Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "tunit" | Case_aux c "tlet"
| Case_aux c "tinl" | Case_aux c "tinr" | Case_aux c "tcase"
| Case_aux c "tnil" | Case_aux c "tcons" | Case_aux c "tlcase"
| Case_aux c "tfix" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tpair t1 t2 =>
tpair (subst x s t1) (subst x s t2)
| tfst t1 =>
tfst (subst x s t1)
| tsnd t1 =>
tsnd (subst x s t1)
| tunit => tunit
(* FILL IN HERE BEGIN *)
| tlet y t1 t2 =>
tlet y (subst x s t1) (if eq_id_dec x y then t2 else (subst x s t2))
(* FILL IN HERE END *)
| tinl T t1 =>
tinl T (subst x s t1)
| tinr T t1 =>
tinr T (subst x s t1)
| tcase t0 y1 t1 y2 t2 =>
tcase (subst x s t0)
y1 (if eq_id_dec x y1 then t1 else (subst x s t1))
y2 (if eq_id_dec x y2 then t2 else (subst x s t2))
| tnil T =>
tnil T
| tcons t1 t2 =>
tcons (subst x s t1) (subst x s t2)
| tlcase t1 t2 y1 y2 t3 =>
tlcase (subst x s t1) (subst x s t2) y1 y2
(if eq_id_dec x y1 then
t3
else if eq_id_dec x y2 then t3
else (subst x s t3))
(* FILL IN HERE BEGIN *)
| tfix t => tfix (subst x s t)
(* FILL IN HERE END *)
(* | _ => t (* ... and delete this line *) *)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
(** Next we define the values of our language. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
(* Numbers are values: *)
| v_nat : forall n1,
value (tnat n1)
(* A pair is a value if both components are: *)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
(* A unit is always a value *)
| v_unit : value tunit
(* A tagged value is a value: *)
| v_inl : forall v T,
value v ->
value (tinl T v)
| v_inr : forall v T,
value v ->
value (tinr T v)
(* A list is a value iff its head and tail are values: *)
| v_lnil : forall T, value (tnil T)
| v_lcons : forall v1 vl,
value v1 ->
value vl ->
value (tcons v1 vl)
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* nats *)
| ST_Succ1 : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_SuccNat : forall n1,
(tsucc (tnat n1)) ==> (tnat (S n1))
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_PredNat : forall n1,
(tpred (tnat n1)) ==> (tnat (pred n1))
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tmult v1 t2) ==> (tmult v1 t2')
| ST_MultNats : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (mult n1 n2))
| ST_If01 : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_If0Zero : forall t2 t3,
(tif0 (tnat 0) t2 t3) ==> t2
| ST_If0Nonzero : forall n t2 t3,
(tif0 (tnat (S n)) t2 t3) ==> t3
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst1 : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd1 : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* let *)
(* FILL IN HERE BEGIN *)
| ST_Let1 : forall x t1 t2 t1',
t1 ==> t1' -> tlet x t1 t2 ==> tlet x t1' t2
| ST_LetValue : forall x t1 t2,
value t1 -> tlet x t1 t2 ==> [x:=t1]t2
(* FILL IN HERE END *)
(* sums *)
| ST_Inl : forall t1 t1' T,
t1 ==> t1' ->
(tinl T t1) ==> (tinl T t1')
| ST_Inr : forall t1 t1' T,
t1 ==> t1' ->
(tinr T t1) ==> (tinr T t1')
| ST_Case : forall t0 t0' x1 t1 x2 t2,
t0 ==> t0' ->
(tcase t0 x1 t1 x2 t2) ==> (tcase t0' x1 t1 x2 t2)
| ST_CaseInl : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinl T v0) x1 t1 x2 t2) ==> [x1:=v0]t1
| ST_CaseInr : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinr T v0) x1 t1 x2 t2) ==> [x2:=v0]t2
(* lists *)
| ST_Cons1 : forall t1 t1' t2,
t1 ==> t1' ->
(tcons t1 t2) ==> (tcons t1' t2)
| ST_Cons2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tcons v1 t2) ==> (tcons v1 t2')
| ST_Lcase1 : forall t1 t1' t2 x1 x2 t3,
t1 ==> t1' ->
(tlcase t1 t2 x1 x2 t3) ==> (tlcase t1' t2 x1 x2 t3)
| ST_LcaseNil : forall T t2 x1 x2 t3,
(tlcase (tnil T) t2 x1 x2 t3) ==> t2
| ST_LcaseCons : forall v1 vl t2 x1 x2 t3,
value v1 ->
value vl ->
(tlcase (tcons v1 vl) t2 x1 x2 t3) ==> (subst x2 vl (subst x1 v1 t3))
(* fix *)
(* FILL IN HERE BEGIN *)
| ST_Fix1 : forall t1 t1',
t1 ==> t1' -> tfix t1 ==> tfix t1'
| ST_FixAbs : forall xf T1 t2,
tfix (tabs xf T1 t2) ==> [xf:=tfix (tabs xf T1 t2)]t2
(* FILL IN HERE END *)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Succ1" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Pred1" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_MultNats" | Case_aux c "ST_If01"
| Case_aux c "ST_If0Zero" | Case_aux c "ST_If0Nonzero"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst1" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd1" | Case_aux c "ST_SndPair"
(* FILL IN HERE BEGIN *)
| Case_aux c "ST_Let1" | Case_aux c "ST_LetValue"
(* FILL IN HERE END *)
| Case_aux c "ST_Inl" | Case_aux c "ST_Inr" | Case_aux c "ST_Case"
| Case_aux c "ST_CaseInl" | Case_aux c "ST_CaseInr"
| Case_aux c "ST_Cons1" | Case_aux c "ST_Cons2" | Case_aux c "ST_Lcase1"
| Case_aux c "ST_LcaseNil" | Case_aux c "ST_LcaseCons"
(* FILL IN HERE BEGIN *)
| Case_aux c "ST_Fix1" | Case_aux c "ST_FixAbs"
(* FILL IN HERE END *)
].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
(** Next we define the typing rules. These are nearly direct
transcriptions of the inference rules shown above. *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
(* nats *)
| T_Nat : forall Gamma n1,
Gamma |- (tnat n1) \in TNat
| T_Succ : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tsucc t1) \in TNat
| T_Pred : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tpred t1) \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma t1 t2 t3 T1,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- (tif0 t1 t2 t3) \in T1
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in T2 ->
Gamma |- (tpair t1 t2) \in (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tfst t) \in T1
| T_Snd : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tsnd t) \in T2
(* unit *)
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* let *)
(* FILL IN HERE BEGIN *)
| T_Let : forall Gamma x t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
(extend Gamma x T1) |- t2 \in T2 ->
Gamma |- (tlet x t1 t2) \in T2
(* FILL IN HERE END *)
(* sums *)
| T_Inl : forall Gamma t1 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- (tinl T2 t1) \in (TSum T1 T2)
| T_Inr : forall Gamma t2 T1 T2,
Gamma |- t2 \in T2 ->
Gamma |- (tinr T1 t2) \in (TSum T1 T2)
| T_Case : forall Gamma t0 x1 T1 t1 x2 T2 t2 T,
Gamma |- t0 \in (TSum T1 T2) ->
(extend Gamma x1 T1) |- t1 \in T ->
(extend Gamma x2 T2) |- t2 \in T ->
Gamma |- (tcase t0 x1 t1 x2 t2) \in T
(* lists *)
| T_Nil : forall Gamma T,
Gamma |- (tnil T) \in (TList T)
| T_Cons : forall Gamma t1 t2 T1,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in (TList T1) ->
Gamma |- (tcons t1 t2) \in (TList T1)
| T_Lcase : forall Gamma t1 T1 t2 x1 x2 t3 T2,
Gamma |- t1 \in (TList T1) ->
Gamma |- t2 \in T2 ->
(extend (extend Gamma x2 (TList T1)) x1 T1) |- t3 \in T2 ->
Gamma |- (tlcase t1 t2 x1 x2 t3) \in T2
(* fix *)
(* FILL IN HERE BEGIN *)
| T_Fix : forall Gamma t1 T1,
Gamma |- t1 \in (TArrow T1 T1) ->
Gamma |- (tfix t1) \in T1
(* FILL IN HERE END *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_Unit"
(* let *)
(* FILL IN HERE BEGIN *)
| Case_aux c "T_Let"
(* FILL IN HERE END *)
| Case_aux c "T_Inl" | Case_aux c "T_Inr" | Case_aux c "T_Case"
| Case_aux c "T_Nil" | Case_aux c "T_Cons" | Case_aux c "T_Lcase"
(* fix *)
(* FILL IN HERE BEGIN *)
| Case_aux c "T_Fix"
(* FILL IN HERE END *)
].
(* ###################################################################### *)
(** ** Examples *)
(** This section presents formalized versions of the examples from
above (plus several more). The ones at the beginning focus on
specific features; you can use these to make sure your definition
of a given feature is reasonable before moving on to extending the
proofs later in the file with the cases relating to this feature.
The later examples require all the features together, so you'll
need to come back to these when you've got all the definitions
filled in. *)
Module Examples.
(** *** Preliminaries *)
(** First, let's define a few variable names: *)
Notation a := (Id 0).
Notation f := (Id 1).
Notation g := (Id 2).
Notation l := (Id 3).
Notation k := (Id 6).
Notation i1 := (Id 7).
Notation i2 := (Id 8).
Notation x := (Id 9).
Notation y := (Id 10).
Notation processSum := (Id 11).
Notation n := (Id 12).
Notation eq := (Id 13).
Notation m := (Id 14).
Notation evenodd := (Id 15).
Notation even := (Id 16).
Notation odd := (Id 17).
Notation eo := (Id 18).
(** Next, a bit of Coq hackery to automate searching for typing
derivations. You don't need to understand this bit in detail --
just have a look over it so that you'll know what to look for if
you ever find yourself needing to make custom extensions to
[auto].
The following [Hint] declarations say that, whenever [auto]
arrives at a goal of the form [(Gamma |- (tapp e1 e1) \in T)], it
should consider [eapply T_App], leaving an existential variable
for the middle type T1, and similar for [lcase]. That variable
will then be filled in during the search for type derivations for
[e1] and [e2]. We also include a hint to "try harder" when
solving equality goals; this is useful to automate uses of
[T_Var] (which includes an equality as a precondition). *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
(* You'll want to uncomment the following line once
you've defined the [T_Lcase] constructor for the typing
relation: *)
Hint Extern 2 (has_type _ (tlcase _ _ _ _ _) _) =>
eapply T_Lcase; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(** *** Numbers *)
Module Numtest.
(* if0 (pred (succ (pred (2 * 0))) then 5 else 6 *)
Definition test :=
tif0
(tpred
(tsucc
(tpred
(tmult
(tnat 2)
(tnat 0)))))
(tnat 5)
(tnat 6).
(** Remove the comment braces once you've implemented enough of the
definitions that you think this should work. *)
Example typechecks :
(@empty ty) |- test \in TNat.
Proof.
unfold test.
(* This typing derivation is quite deep, so we need to increase the
max search depth of [auto] from the default 5 to 10. *)
auto 10.
Qed.
Example numtest_reduces :
test ==>* tnat 5.
Proof.
unfold test. normalize.
Qed.
End Numtest.
(** *** Products *)
Module Prodtest.
(* ((5,6),7).fst.snd *)
Definition test :=
tsnd
(tfst
(tpair
(tpair
(tnat 5)
(tnat 6))
(tnat 7))).
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
End Prodtest.
(** *** [let] *)
Module LetTest.
(* let x = pred 6 in succ x *)
Definition test :=
tlet
x
(tpred (tnat 6))
(tsucc (tvar x)).
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
End LetTest.
(** *** Sums *)
Module Sumtest1.
(* case (inl Nat 5) of
inl x => x
| inr y => y *)
Definition test :=
tcase (tinl TNat (tnat 5))
x (tvar x)
y (tvar y).
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tnat 5).
Proof. unfold test. normalize. Qed.
End Sumtest1.
Module Sumtest2.
(* let processSum =
\x:Nat+Nat.
case x of
inl n => n
inr n => if0 n then 1 else 0 in
(processSum (inl Nat 5), processSum (inr Nat 5)) *)
Definition test :=
tlet
processSum
(tabs x (TSum TNat TNat)
(tcase (tvar x)
n (tvar n)
n (tif0 (tvar n) (tnat 1) (tnat 0))))
(tpair
(tapp (tvar processSum) (tinl TNat (tnat 5)))
(tapp (tvar processSum) (tinr TNat (tnat 5)))).
Example typechecks :
(@empty ty) |- test \in (TProd TNat TNat).
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tpair (tnat 5) (tnat 0)).
Proof. unfold test. normalize. Qed.
End Sumtest2.
(** *** Lists *)
Module ListTest.
(* let l = cons 5 (cons 6 (nil Nat)) in
lcase l of
nil => 0
| x::y => x*x *)
Definition test :=
tlet l
(tcons (tnat 5) (tcons (tnat 6) (tnil TNat)))
(tlcase (tvar l)
(tnat 0)
x y (tmult (tvar x) (tvar x))).
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 20. Qed.
Example reduces :
test ==>* (tnat 25).
Proof. unfold test. normalize. Qed.
End ListTest.
(** *** [fix] *)
Module FixTest1.
(* fact := fix
(\f:nat->nat.
\a:nat.
if a=0 then 1 else a * (f (pred a))) *)
Definition fact :=
tfix
(tabs f (TArrow TNat TNat)
(tabs a TNat
(tif0
(tvar a)
(tnat 1)
(tmult
(tvar a)
(tapp (tvar f) (tpred (tvar a))))))).
(** (Warning: you may be able to typecheck [fact] but still have some
rules wrong!) *)
Example fact_typechecks :
(@empty ty) |- fact \in (TArrow TNat TNat).
Proof. unfold fact. auto 10.
Qed.
Example fact_example:
(tapp fact (tnat 4)) ==>* (tnat 24).
Proof. unfold fact. normalize. Qed.
End FixTest1.
Module FixTest2.
(* map :=
\g:nat->nat.
fix
(\f:[nat]->[nat].
\l:[nat].
case l of
| [] -> []
| x::l -> (g x)::(f l)) *)
Definition map :=
tabs g (TArrow TNat TNat)
(tfix
(tabs f (TArrow (TList TNat) (TList TNat))
(tabs l (TList TNat)
(tlcase (tvar l)
(tnil TNat)
a l (tcons (tapp (tvar g) (tvar a))
(tapp (tvar f) (tvar l))))))).
(* Make sure you've uncommented the last [Hint Extern] above... *)
Example map_typechecks :
empty |- map \in
(TArrow (TArrow TNat TNat)
(TArrow (TList TNat)
(TList TNat))).
Proof. unfold map. auto 10. Qed.
Example map_example :
tapp (tapp map (tabs a TNat (tsucc (tvar a))))
(tcons (tnat 1) (tcons (tnat 2) (tnil TNat)))
==>* (tcons (tnat 2) (tcons (tnat 3) (tnil TNat))).
Proof. unfold map. normalize. Qed.
End FixTest2.
Module FixTest3.
(* equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if0 m then (if0 n then 1 else 0)
else if0 n then 0
else eq (pred m) (pred n)) *)
Definition equal :=
tfix
(tabs eq (TArrow TNat (TArrow TNat TNat))
(tabs m TNat
(tabs n TNat
(tif0 (tvar m)
(tif0 (tvar n) (tnat 1) (tnat 0))
(tif0 (tvar n)
(tnat 0)
(tapp (tapp (tvar eq)
(tpred (tvar m)))
(tpred (tvar n)))))))).
Example equal_typechecks :
(@empty ty) |- equal \in (TArrow TNat (TArrow TNat TNat)).
Proof. unfold equal. auto 10.
Qed.
Example equal_example1:
(tapp (tapp equal (tnat 4)) (tnat 4)) ==>* (tnat 1).
Proof. unfold equal. normalize. Qed.
Example equal_example2:
(tapp (tapp equal (tnat 4)) (tnat 5)) ==>* (tnat 0).
Proof. unfold equal. normalize. Qed.
End FixTest3.
Module FixTest4.
(* let evenodd =
fix
(\eo: (Nat->Nat * Nat->Nat).
let e = \n:Nat. if0 n then 1 else eo.snd (pred n) in
let o = \n:Nat. if0 n then 0 else eo.fst (pred n) in
(e,o)) in
let even = evenodd.fst in
let odd = evenodd.snd in
(even 3, even 4)
*)
Definition eotest :=
tlet evenodd
(tfix
(tabs eo (TProd (TArrow TNat TNat) (TArrow TNat TNat))
(tpair
(tabs n TNat
(tif0 (tvar n)
(tnat 1)
(tapp (tsnd (tvar eo)) (tpred (tvar n)))))
(tabs n TNat
(tif0 (tvar n)
(tnat 0)
(tapp (tfst (tvar eo)) (tpred (tvar n))))))))
(tlet even (tfst (tvar evenodd))
(tlet odd (tsnd (tvar evenodd))
(tpair
(tapp (tvar even) (tnat 3))
(tapp (tvar even) (tnat 4))))).
Example eotest_typechecks :
(@empty ty) |- eotest \in (TProd TNat TNat).
Proof. unfold eotest. eauto 30.
Qed.
Example eotest_example1:
eotest ==>* (tpair (tnat 0) (tnat 1)).
Proof. unfold eotest. normalize. Qed.
End FixTest4.
End Examples.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** The proofs of progress and preservation for this system are
essentially the same (though of course somewhat longer) as for the
pure simply typed lambda-calculus. *)
(* ###################################################################### *)
(** *** Progress *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
(* Theorem: Suppose empty |- t : T. Then either
1. t is a value, or
2. t ==> t' for some t'.
Proof: By induction on the given typing derivation. *)
intros t T Ht.
remember (@empty ty) as Gamma.
generalize dependent HeqGamma.
has_type_cases (induction Ht) Case; intros HeqGamma; subst.
Case "T_Var".
(* The final rule in the given typing derivation cannot be [T_Var],
since it can never be the case that [empty |- x : T] (since the
context is empty). *)
inversion H.
Case "T_Abs".
(* If the [T_Abs] rule was the last used, then [t = tabs x T11 t12],
which is a value. *)
left...
Case "T_App".
(* If the last rule applied was T_App, then [t = t1 t2], and we know
from the form of the rule that
[empty |- t1 : T1 -> T2]
[empty |- t2 : T1]
By the induction hypothesis, each of t1 and t2 either is a value
or can take a step. *)
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
(* If both [t1] and [t2] are values, then we know that
[t1 = tabs x T11 t12], since abstractions are the only values
that can have an arrow type. But
[(tabs x T11 t12) t2 ==> [x:=t2]t12] by [ST_AppAbs]. *)
inversion H; subst; try (solve by inversion).
exists (subst x t2 t12)...
SSCase "t2 steps".
(* If [t1] is a value and [t2 ==> t2'], then [t1 t2 ==> t1 t2']
by [ST_App2]. *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
(* Finally, If [t1 ==> t1'], then [t1 t2 ==> t1' t2] by [ST_App1]. *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Nat".
left...
Case "T_Succ".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (S n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsucc t1')...
Case "T_Pred".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (pred n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tpred t1')...
Case "T_Mult".
right.
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
inversion H0; subst; try solve by inversion.
exists (tnat (mult n1 n0))...
SSCase "t2 steps".
inversion H0 as [t2' Hstp].
exists (tmult t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tmult t1' t2)...
Case "T_If0".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
destruct n1 as [|n1'].
SSCase "n1=0".
exists t2...
SSCase "n1<>0".
exists t3...
SCase "t1 steps".
inversion H as [t1' H0].
exists (tif0 t1' t2 t3)...
Case "T_Pair".
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 steps".
right. inversion H0 as [t2' Hstp].
exists (tpair t1 t2')...
SCase "t1 steps".
right. inversion H as [t1' Hstp].
exists (tpair t1' t2)...
Case "T_Fst".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v1...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tfst t1')...
Case "T_Snd".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v2...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsnd t1')...
Case "T_Unit".
left...
(* let *)
(* FILL IN HERE BEGIN *)
Case "T_Let".
right. destruct IHHt1...
SCase "t1 steps".
inversion H; subst.
exists (tlet x x0 t2)...
(* FILL IN HERE END *)
Case "T_Inl".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinl _ t1')... *)
Case "T_Inr".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinr _ t1')... *)
Case "T_Case".
right.
destruct IHHt1...
SCase "t0 is a value".
inversion H; subst; try solve by inversion.
SSCase "t0 is inl".
exists ([x1:=v]t1)...
SSCase "t0 is inr".
exists ([x2:=v]t2)...
SCase "t0 steps".
inversion H as [t0' Hstp].
exists (tcase t0' x1 t1 x2 t2)...
Case "T_Nil".
left...
Case "T_Cons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. inversion H0 as [t2' Hstp].
exists (tcons t1 t2')...
SCase "head steps".
right. inversion H as [t1' Hstp].
exists (tcons t1' t2)...
Case "T_Lcase".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
SSCase "t1=tnil".
exists t2...
SSCase "t1=tcons v1 vl".
exists ([x2:=vl]([x1:=v1]t3))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tlcase t1' t2 x1 x2 t3)...
(* fix *)
(* FILL IN HERE BEGIN *)
Case "T_Fix".
right. destruct IHHt...
SCase "t is a value".
inversion Ht; subst; try solve by inversion.
exists ([x:=tfix (tabs x T1 t12)]t12)...
SCase "t steps".
inversion H; subst. exists (tfix x)...
(* FILL IN HERE END *)
Qed.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* nats *)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* let *)
(* FILL IN HERE BEGIN *)
| afi_let1 : forall x y t1 t2,
appears_free_in x t1 ->
appears_free_in x (tlet y t1 t2)
| afi_let2 : forall x y t1 t2,
x <> y ->
appears_free_in x t2 ->
appears_free_in x (tlet y t1 t2)
(* FILL IN HERE END *)
(* sums *)
| afi_inl : forall x t T,
appears_free_in x t ->
appears_free_in x (tinl T t)
| afi_inr : forall x t T,
appears_free_in x t ->
appears_free_in x (tinr T t)
| afi_case0 : forall x t0 x1 t1 x2 t2,
appears_free_in x t0 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case1 : forall x t0 x1 t1 x2 t2,
x1 <> x ->
appears_free_in x t1 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case2 : forall x t0 x1 t1 x2 t2,
x2 <> x ->
appears_free_in x t2 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
(* lists *)
| afi_cons1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tcons t1 t2)
| afi_cons2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tcons t1 t2)
| afi_lcase1 : forall x t1 t2 y1 y2 t3,
appears_free_in x t1 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase2 : forall x t1 t2 y1 y2 t3,
appears_free_in x t2 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase3 : forall x t1 t2 y1 y2 t3,
y1 <> x ->
y2 <> x ->
appears_free_in x t3 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
(* fix *)
(* FILL IN HERE BEGIN *)
| afi_fix : forall x t,
appears_free_in x t -> appears_free_in x (tfix t)
(* FILL IN HERE END *)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
Case "T_Mult".
apply T_Mult...
Case "T_If0".
apply T_If0...
Case "T_Pair".
apply T_Pair...
(* let *)
(* FILL IN HERE BEGIN *)
Case "T_Let".
apply T_Let with T1...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
(* FILL IN HERE END *)
Case "T_Case".
eapply T_Case...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x2 y)...
Case "T_Cons".
apply T_Cons...
Case "T_Lcase".
eapply T_Lcase... apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
destruct (eq_id_dec x2 y)...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* let *)
(* FILL IN HERE BEGIN *)
Case "T_Let".
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* FILL IN HERE END *)
Case "T_Case".
SCase "left".
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
SCase "right".
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Case "T_Lcase".
clear Htyp1 IHHtyp1 Htyp2 IHHtyp2.
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx... rewrite neq_id in Hctx...
Qed.
(* ###################################################################### *)
(** *** Substitution *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- [x:=v]t : S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 : S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* let *)
(* FILL IN HERE BEGIN *)
Case "tlet".
rename i into y.
eapply T_Let...
destruct (eq_id_dec x y).
SSCase "x = y".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
SSCase "x <> y".
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* FILL IN HERE END *)
Case "tcase".
rename i into x1. rename i0 into x2.
eapply T_Case...
SCase "left arm".
destruct (eq_id_dec x x1).
SSCase "x = x1".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
SSCase "x <> x1".
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
subst. rewrite neq_id...
SCase "right arm".
destruct (eq_id_dec x x2).
SSCase "x = x2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
SSCase "x <> x2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
subst. rewrite neq_id...
Case "tlcase".
rename i into y1. rename i0 into y2.
eapply T_Lcase...
destruct (eq_id_dec x y1).
SCase "x=y1".
simpl.
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
SCase "x<>y1".
destruct (eq_id_dec x y2).
SSCase "x=y2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y2 z)...
SSCase "x<>y2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
subst. rewrite neq_id...
destruct (eq_id_dec y2 z)...
subst. rewrite neq_id...
Qed.
(* ###################################################################### *)
(** *** Preservation *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
(* let *)
(* FILL IN HERE BEGIN *)
Case "T_Let".
eapply substitution_preserves_typing...
(* FILL IN HERE END *)
Case "T_Case".
SCase "ST_CaseInl".
inversion HT1; subst.
eapply substitution_preserves_typing...
SCase "ST_CaseInr".
inversion HT1; subst.
eapply substitution_preserves_typing...
Case "T_Lcase".
SCase "ST_LcaseCons".
inversion HT1; subst.
apply substitution_preserves_typing with (TList T1)...
apply substitution_preserves_typing with T1...
(* fix *)
(* FILL IN HERE BEGIN *)
Case "T_Fix".
inversion HT; subst.
eapply substitution_preserves_typing...
(* FILL IN HERE END *)
Qed.
(** [] *)
End STLCExtended.
(* $Date: 2014-12-01 15:15:02 -0500 (Mon, 01 Dec 2014) $ *)
|
`include "sdio_defines.v"
module sdio_device_phy (
input rst,
input i_posedge_stb,
//Configuration
input i_ddr_en,
input i_spi_phy,
input i_sd1_phy,
input i_sd4_phy,
//Data Link Interface
output o_cmd_phy_idle,
output reg o_cmd_phy,
output reg o_cmd_stb,
output reg o_cmd_crc_good_stb,
output reg [5:0] o_cmd,
output reg [31:0] o_cmd_arg,
input i_rsps_stb,
input [39:0] i_rsps,
input [7:0] i_rsps_len,
input i_rsps_fail,
output reg o_rsps_idle,
//XXX: Need to hook this up
input i_interrupt,
input i_data_activate,
output o_data_finished,
input i_write_flag,
input [12:0] i_data_count,
output o_data_wr_stb,
output [7:0] o_data_wr_data,
input i_data_rd_stb,
input [7:0] i_data_rd_data,
output o_data_hst_rdy,
input i_data_com_rdy,
//FPGA Interface
input i_sdio_clk,
input i_sdio_clk_x2,
output reg o_sdio_cmd_dir,
input i_sdio_cmd_in,
output reg o_sdio_cmd_out,
output o_sdio_data_dir,
input [7:0] i_sdio_data_in,
output [7:0] o_sdio_data_out
);
//Local Parameters
localparam IDLE = 4'h0;
localparam READ_COMMAND = 4'h1;
localparam RESPONSE_DIR_BIT = 4'h2;
localparam WAIT_FOR_RESPONSE = 4'h3;
localparam RESPONSE = 4'h4;
localparam RESPONSE_FIRST_CRC= 4'h5;
localparam RESPONSE_CRC = 4'h6;
localparam RESPONSE_FINISHED = 4'h7;
//Local Registers/Wires
reg [3:0] state;
reg [3:0] phy_mode;
reg [7:0] bit_count;
reg txrx_dir;
reg [6:0] r_crc;
wire [6:0] crc;
wire [6:0] crc_good;
wire busy;
wire crc_bit;
reg crc_en;
reg crc_rst;
reg [39:0] lcl_rsps;
//Submodules
crc7 crc_gen (
.clk (i_sdio_clk ),
.rst (crc_rst ),
.bit (crc_bit ),
.crc (crc ),
.en (crc_en )
);
sdio_data_phy data_phy(
.clk (i_sdio_clk ),
.rst (rst ),
.i_interrupt (i_interrupt ),
.i_posedge_stb (i_posedge_stb ),
.i_ddr_en (i_ddr_en ),
.i_spi_phy (i_spi_phy ),
.i_sd1_phy (i_sd1_phy ),
.i_sd4_phy (i_sd4_phy ),
.i_activate (i_data_activate ),
.o_finished (o_data_finished ),
.i_write_flag (i_write_flag ),
.i_data_count (i_data_count ),
.o_data_wr_stb (o_data_wr_stb ),
.o_data_wr_data (o_data_wr_data ),
.i_data_rd_stb (i_data_rd_stb ),
.i_data_rd_data (i_data_rd_data ),
.o_data_hst_rdy (o_data_hst_rdy ),
.i_data_com_rdy (i_data_com_rdy ),
.o_sdio_data_dir (o_sdio_data_dir ),
.i_sdio_data_in (i_sdio_data_in ),
.o_sdio_data_out (o_sdio_data_out )
);
//Asynchronous Logic
assign busy = ((state != IDLE) || !i_sdio_cmd_in);
assign crc_bit = o_sdio_cmd_dir ? o_sdio_cmd_out: i_sdio_cmd_in;
assign o_cmd_phy_idle = !busy;
//Synchronous Logic
//XXX: this clock should probably be i_sdio_clk
always @ (posedge i_sdio_clk) begin
if (rst) begin
//Start out in SPI mode
bit_count <= 0;
txrx_dir <= 0;
state <= IDLE;
o_rsps_idle <= 0;
o_cmd_stb <= 0;
o_cmd <= 0;
o_cmd_arg <= 0;
r_crc <= 0;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 0;
crc_en <= 0;
crc_rst <= 1;
lcl_rsps <= 0;
end
else begin
//strobes
o_cmd_stb <= 0;
o_cmd_crc_good_stb<= 0;
crc_rst <= 0;
//Incrementing bit count
if (busy) begin
bit_count <= bit_count + 1;
end
else begin
bit_count <= 0;
end
case (state)
IDLE: begin
o_rsps_idle <= 1;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 0;
crc_en <= 0;
crc_rst <= 0;
//Detect beginning of transaction when the command line goes low
if (!i_sdio_cmd_in) begin
o_rsps_idle <= 0;
crc_en <= 1;
//New Command Detected
state <= READ_COMMAND;
end
else begin
crc_rst <= 1;
end
end
READ_COMMAND: begin
if (bit_count == `SDIO_C_BIT_ARG_END) begin
crc_en <= 0;
end
if (bit_count == `SDIO_C_BIT_TXRX_DIR)
txrx_dir <= i_sdio_cmd_in;
else if ((bit_count >= `SDIO_C_BIT_CMD_START) && (bit_count <= `SDIO_C_BIT_CMD_END))
o_cmd <= {o_cmd[4:0], i_sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_ARG_START) && (bit_count <= `SDIO_C_BIT_ARG_END))
o_cmd_arg <= {o_cmd_arg[30:0], i_sdio_cmd_in};
else if ((bit_count >= `SDIO_C_BIT_CRC_START) && (bit_count <= `SDIO_C_BIT_CRC_END))
r_crc <= {r_crc[5:0], i_sdio_cmd_in};
else begin //Last Bit
r_crc <= {r_crc[5:0], i_sdio_cmd_in};
/*
if (r_crc == crc)
o_cmd_crc_good_stb <= 1;
crc_rst <= 1;
o_cmd_stb <= 1;
bit_count <= 0;
o_sdio_cmd_dir <= 1;
o_sdio_cmd_out <= 1;
*/
state <= RESPONSE_DIR_BIT;
end
end
RESPONSE_DIR_BIT: begin
//Test
if (r_crc == crc) begin
o_cmd_crc_good_stb <= 1;
crc_rst <= 1;
end
//$display("CMD:Args %h:%h", o_cmd, o_cmd_arg);
o_cmd_stb <= 1;
o_sdio_cmd_out <= 1;
o_sdio_cmd_dir <= 1;
//End Test
state <= WAIT_FOR_RESPONSE;
end
WAIT_FOR_RESPONSE: begin
if (i_rsps_stb) begin
lcl_rsps <= i_rsps;
state <= RESPONSE;
bit_count <= 0;
o_sdio_cmd_out <= 0; //Direction From Device to Host
end
end
RESPONSE: begin
crc_en <= 1;
o_sdio_cmd_out <= lcl_rsps[39];
lcl_rsps <= {lcl_rsps[38:0], 1'b0};
if (bit_count >= i_rsps_len) begin
crc_en <= 0;
state <= RESPONSE_FIRST_CRC;
bit_count <= 0;
end
end
RESPONSE_FIRST_CRC: begin
o_sdio_cmd_out <= crc[6];
r_crc <= {crc[5:0], 1'b0};
state <= RESPONSE_CRC;
end
RESPONSE_CRC: begin
o_sdio_cmd_out <= r_crc[6];
r_crc <= {r_crc[5:0], 1'b0};
if (bit_count >= 8'h6) begin
state <= RESPONSE_FINISHED;
end
end
RESPONSE_FINISHED: begin
o_sdio_cmd_out <= 1'b1;
state <= IDLE;
end
default: begin
o_sdio_cmd_dir <= 0;
state <= IDLE;
end
endcase
if (i_rsps_fail) begin
//Do not respond when we detect a fail
state <= IDLE;
end
end
end
endmodule
|
module IF_STAGE(
input clk,
input rst,
input instr_fetch_enable,
input [5:0] imm_branch_offset,
input branch_enable,
input jump,
output [7:0] pc,
output [15:0] instr
);
wire[7:0] PCI;
wire[7:0] PCO;
wire[7:0] PCAdd1O;
wire[7:0] PC1AddBr8;
wire[7:0] Br8;
wire[1:0] Mux4Select;
assign Mux4Select = {jump, branch_enable};
SixToEightExtend mySixToEight(
.In(imm_branch_offset),
.Out(Br8)
);
PC myPC(
.clock(clk),
.reset(rst),
.PCEn(instr_fetch_enable),
.in(PCI),
.out(PCO)
);
Add myPCByOne(
.a(PCO),
.b(8'b00000001),
.out(PCAdd1O)
);
Add myPC1ByBz(
.a(Br8),
.b(PCAdd1O),
.out(PC1AddBr8)
);
MUX4#(8) myIfMux4(
.SLCT(Mux4Select),
.IN3(),
.IN2(Br8),
.IN1(PC1AddBr8),
.IN0(PCAdd1O),
.OT(PCI)
);
InstructionMemory#(256) myInstMem(
.reset(rst),
.addr(PCO),
.inst(instr)
);
assign pc = PCO;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_TB_V
`define SKY130_FD_SC_HD__BUFBUF_TB_V
/**
* bufbuf: Double buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__bufbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps/sky130_fd_sc_lp__udp_dff_ps.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_FUNCTIONAL_V
|
/// date:2016/3/9
/// engineer :ZhaiShaoMin
/// module name: communication assist
/// module function: put many components,such as arbiter and download_flit_fsm and
/// upload_flit_fsm,together, then we can get a bigger module which named communication assist.
/// this module is responsible for handling flits from IN fifos and flits to OUT fifos ,as well as
/// providing firendly interfaces to inst cache ,data cache and memory
////////////////////////////////////////////////////////////////////////////////
/// submoddules: arbiter_IN_node, // guiding flits from IN_fifos to the right places with high efficiency
/// arbiter_for_dc, // select source flits from cpu_access,IN_fifos msg and local memory access
/// arbiter_for_mem, // select source flits from local inst cache or local data cache or IN_fifos
/// arbiter_for_OUT_rep,// select src flit from dc_rep_upload and m_rep_upload
/// arbiter_for_OUT_req,// select flit from ic_req_upload or dc_req_upload or m_req_upload
/// ic_download, // receive rep from IN_rep or local mem
/// dc_download, // receive rep from IN_rep or req from IN_req
/// m_download, // receive rep from IN_rep or req from IN_req
/// m_d_areg, // receive rep or req from local mem
/// d_m_areg, // receive req or rep fromlocal data cache
/// i_m_areg, // receive req from local inst cache
/// ic_req_upload, //upload flits from ic(inst cache) to OUT_req
/// dc_rep_upload, //upload flits from dc to OUT_req
/// m_rep_upload, //upload flits from mem to OUT_req
/// dc_req_upload, //upload flits from dc to OUT_rep
/// m_req_upload //upload flits from mem to OUT_req
////////////////////////////////////////////////////////////////////////////////
module commu_assist(//input
clk,
rst,
// I/O between arbiter and IN fifos
// input
req_flit_in, //flit from IN req fifo
req_rdy, // it's ready for arbiter_IN_node to dequeue flit from In req fifo
req_ctrl_in, //control signals from In fifo indicate what kind of flit under transfering
rep_flit_in,
rep_rdy,
rep_ctrl_in,
// output
ack_rep, // arbiter tell IN rep fifo that it's ready to receive flit,
// as well as been used by IN rep fifo as a deq rdy signal
ack_req, //req_rep and req_req are better!
/// I/O about OUT_req/rep fifo
//input
OUT_req_rdy, // arbiter_OUT_req tell OUT req fifo to be ready to receive flit from commu_assist
OUT_rep_rdy, // arbiter_OUT_rep ......
// output
OUT_req_ctrl, // used to tell the frame of msg. 00 means nothing 01 means head flit,
// 10 means body flit,11 means tail flit, exception is invrep which has only one flit.
OUT_req_flit, // flit outputed to OUT req fifo
OUT_req_ack, // same as rdy signal saying now I'm a valid flit, also a enq signal for OUT req fifo
OUT_rep_ctrl, // similar function as above
OUT_rep_flit,
OUT_rep_ack,
/// I/O about inst cache
// input
// v_req_inst, // indicate that's a valid inst request from pc
// pc_addr, // addr of pc used to look up inst cache to find intended inst
// to OUT_req
v_flits_2_ic_req, // saying I'm a valid req flits to OUT req fifo
flits_2_ic_req, // req flits output to OUT req fifo
// to local mem
v_req_i_m_areg, // saying I'm a valid req flits to local home(memory)
req_i_m_areg, // req flits output to local home
// output
v_inst_rep, // saying that is a valid rep data back to pipeline
inst_data, // rep data (inst word) back to inst cache.
/// I/O about data cache
// input
dcache_done_access, // data cache tell arbiter_for_dcache previous access had done via this signal
// output
flits_dcache, // arbiter select a flits to dcache
v_flits_dcache, // means it's a valid flits to dcache
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
v_cpu_access, // means it's a valid access from pipeline
cpu_head, // this part include access ctrl info such as ll or ld ,sc or st ,wr or rd
cpu_addr, //addr of mem ops
cpu_data, // data of store or store-condition
/// I/O about memory
// input
ack_m_donwload, // response to m_download saying i'm now reading flits
ack_d_m_donwload, // similar as above
ack_i_m_donwload, //similar as above
mem_access_done,
mem_ic_download, // flits from mem to ic_download
v_mem_ic_download, // flit above is valid
mem_m_d_areg, // flits from mem to m_d_areg
v_mem_m_d_areg, // it's a valid flits to m_d_areg
mem_m_req, // similar as above
v_mem_m_req,
mem_m_rep,
v_mem_m_rep, //similar as above
en_m_flits_max_rep,
m_flits_max_rep,
en_m_flits_max_req,
m_flits_max_req,
en_inv_ids,
inv_ids_in,
// output
v_m_download, // valic flits from m_download to mem
m_donwload, //flits from m_download to mem
v_d_m_areg, // valid flits from d_m_areg to mem
d_m_areg, // flits from d_m_areg to mem
v_i_m_areg,
i_m_areg,
ic_download_fsm_state, //here are some fsm state indicating whether some state elements is idle or busy
m_d_areg_fsm_state, // which is useful to decide whether or not to output flits from mem to these elements
m_rep_fsm_state,
m_req_fsm_state,
/// I/O about data cache
//input
dcache_d_m_areg, //access via flits from data cache to local mem
v_dcache_d_m_areg, // means it's avalid access
dcache_dc_req, // access via flits to OUT_req_upload corresponding to dcache
v_dcache_dc_req, // means it's avalid access
dcache_dc_rep,
v_dcache_dc_rep,
en_dc_flits_max_rep,
dc_flits_max_rep,
/// output
d_m_areg_fsm_state, // fsm state outputed from commu_assist intended to tell dcache if it's able
// to send flits to these units
dc_req_fsm_state,
dc_rep_fsm_state
);
// I/O between arbiter and IN fifos
// input
input clk;
input rst;
input [15:0] req_flit_in;
input req_rdy;
input [1:0] req_ctrl_in;
input [15:0] rep_flit_in;
input rep_rdy;
input [1:0] rep_ctrl_in;
// output
output ack_rep;
output ack_req;
input OUT_req_rdy;
input OUT_rep_rdy;
// output
output [1:0] OUT_req_ctrl;
output [15:0] OUT_req_flit;
output OUT_req_ack;
output [1:0] OUT_rep_ctrl;
output [15:0] OUT_rep_flit;
output OUT_rep_ack;
// input
// input v_req_inst;
// input [31:0] pc_addr;
input v_flits_2_ic_req;
input [47:0] flits_2_ic_req;
// to local mem
input v_req_i_m_areg;
input [31:0] req_i_m_areg;
// output
output v_inst_rep;
output [127:0] inst_data;
/// I/O about data cache
// input
input dcache_done_access;
// output
output [143:0] flits_dcache;
output v_flits_dcache;
/// I/O about cpu_req_cache about ll/ld/st/sc
// input
input v_cpu_access;
input [3:0] cpu_head;
input [31:0] cpu_addr;
input [31:0] cpu_data;
/// I/O about memory
// input
input ack_m_donwload;
input ack_d_m_donwload;
input ack_i_m_donwload;
input mem_access_done;
input [127:0] mem_ic_download;
input v_mem_ic_download;
input [143:0] mem_m_d_areg;
input v_mem_m_d_areg;
input [47:0] mem_m_req;
input v_mem_m_req;
input [143:0] mem_m_rep;
input v_mem_m_rep;
input en_m_flits_max_rep;
input [3:0] m_flits_max_rep;
input en_m_flits_max_req;
input [1:0] m_flits_max_req;
input en_inv_ids; //from mem
input inv_ids_in;
// output
output v_m_download;
output [175:0] m_donwload;
output v_d_m_areg;
output [175:0] d_m_areg;
output v_i_m_areg;
output [47:0] i_m_areg;
output [1:0] ic_download_fsm_state;
output m_d_areg_fsm_state;
output m_rep_fsm_state;
output [1:0] m_req_fsm_state;
/// I/O about data cache
//input
input [175:0] dcache_d_m_areg;
input v_dcache_d_m_areg;
input [47:0] dcache_dc_req;
input v_dcache_dc_req;
input [175:0] dcache_dc_rep;
input v_dcache_dc_rep;
input en_dc_flits_max_rep;
input [3:0] dc_flits_max_rep;
/// output
output d_m_areg_fsm_state;
output dc_req_fsm_state;
output dc_rep_fsm_state;
///////////////////////////////////////////////
///////////// submodules//////////////////////
//////////////////////////////////////////////
//output of arbiter_IN_node
wire ack_req;
wire ack_rep;
wire v_ic_net;
wire [15:0] flit_ic_net;
wire [1:0] ctrl_ic_net;
wire v_dc_net;
wire [15:0] flit_dc_net;
wire [1:0] ctrl_dc_net;
wire v_mem_net;
wire [15:0] flit_mem_net;
wire [1:0] ctrl_mem_net;
//output of arbiter_for_dcache
wire [143:0] flits_dcache_abter;
wire v_flits_dcache_abter;
wire re_dc_download_flits;
wire re_cpu_access_flits;
wire re_m_d_areg_flits;
wire cpu_done_access;
wire dc_download_done_access;
wire m_d_areg_done_access;
// output of arbiter_for_mem
wire ack_m_download_net;
wire ack_d_m_areg_net;
wire ack_i_m_areg_net;
wire v_m_download_m_net;
wire v_d_m_areg_m_net;
wire v_i_m_areg_m_net;
//output of arbiter_for_OUT_rep
wire OUT_rep_ack;
wire ack_dc_rep_net;
wire ack_mem_rep_net;
wire [1:0] select2_net;
//output of arbiter_for_OUT_req
wire OUT_req_ack;
wire ack_ic_req_net;
wire ack_dc_req_net;
wire ack_mem_req_net;
wire [1:0] select3_net ;
//output of ic_download
wire [1:0] ic_download_state_net;
//wire [127:0] inst_data;
wire v_inst_rep;
//output of dc_download
wire v_flits_dcache;
wire [143:0] flits_dcache;
wire [1:0] dc_download_state_net;
//output of m_download
wire v_m_download;
wire [175:0] m_donwload;
wire [1:0] mem_download_state_net;
//output of m_d_areg
wire [143:0] m_d_areg_flits_net;
wire v_m_d_areg_flits_net;
wire m_d_areg_fsm_state;
//ooutput of d_m_areg
wire [175:0] d_m_areg;
wire v_d_m_areg;
wire d_m_areg_fsm_state;
//output of i_m_areg
wire [47:0] i_m_areg;
wire v_i_m_areg;
//output of m_rep_upload
wire [15:0] m_rep_flit_net;
wire v_m_rep_flit_net;
wire m_rep_fsm_state;
wire [1:0] m_rep_ctrl_net;
//output of dc_rep_upload
wire [15:0] dc_rep_flit_net;
wire v_dc_rep_flit_net;
wire dc_rep_fsm_state;
wire [1:0] dc_rep_ctrl_net;
//output of ic_req_upload
wire [15:0] ic_req_flit_net;
wire v_ic_req_flit_net;
wire [1:0] ic_download_fsm_state;
wire [1:0] ic_req_ctrl_net;
//output of m_req_upload
wire [1:0] m_req_ctrl_net;
wire [15:0] m_req_flit_net;
wire [1:0] m_req_fsm_state;
wire v_m_req_flit_net;
//output of dc_req_upload
wire [15:0] dc_req_flit_net;
wire v_dc_req_flit_net;
wire dc_req_fsm_state;
wire [1:0] dc_req_ctrl_net;
reg [15:0] OUT_req_flit;
reg [1:0] OUT_req_ctrl;
//mux OUT_req_ctrl and OUT_req_flit
always@(*)
begin
case(select3_net)
3'b001:
begin
OUT_req_ctrl=m_req_ctrl_net;
OUT_req_flit=m_req_flit_net;
end
3'b010:
begin
OUT_req_ctrl=dc_req_ctrl_net;
OUT_req_flit=dc_req_flit_net;
end
3'b100:
begin
OUT_req_ctrl=ic_req_ctrl_net;
OUT_req_flit=ic_req_flit_net;
end
default:
begin
OUT_req_ctrl=2'b00;
OUT_req_flit=ic_req_ctrl_net;
end
endcase
end
reg [15:0] OUT_rep_flit;
reg [1:0] OUT_rep_ctrl;
//mux OUT_req_ctrl and OUT_req_flit
always@(*)
begin
case(select2_net)
2'b01:
begin
OUT_rep_ctrl=dc_rep_ctrl_net;
OUT_rep_flit=dc_rep_flit_net;
end
2'b10:
begin
OUT_rep_ctrl=m_rep_ctrl_net;
OUT_rep_flit=m_rep_flit_net;
end
default:
begin
OUT_rep_ctrl=2'b00;
OUT_rep_flit=m_rep_flit_net;
end
endcase
end
arbiter_IN_node arbiter_IN_node_dut(
//input
.clk(clk),
.rst(rst),
.in_req_rdy(req_rdy),
.in_rep_rdy(rep_rdy),
.req_ctrl_in(req_ctrl_in),
.rep_ctrl_in(rep_ctrl_in),
.req_flit_in(req_flit_in),
.rep_flit_in(rep_flit_in),
.ic_download_state_in(ic_download_state_net), // (net)from ic_downlaod
.dc_download_state_in(dc_download_state_net), // from dc_download
.mem_download_state_in(mem_download_state_net), // from mem_downlaod
//output
.ack_req(ack_req), // to IN_req fifo
.ack_rep(ack_rep), // to IN_rep fifo
.v_ic(v_ic_net), // to ic_download
.flit_ic(flit_ic_net),
.ctrl_ic(ctrl_ic_net),
.v_dc(v_dc_net), // to dc_download
.flit_dc(flit_dc_net),
.ctrl_dc(ctrl_dc_net),
.v_mem(v_mem_net), // to mem_download
.flit_mem(flit_mem_net),
.ctrl_mem(ctrl_mem_net)
); // guiding flits from IN_fifos to the right places with high efficiency
arbiter_for_dcache arbiter_for_dcache_dut (
//input
.clk(clk),
.rst(rst),
.dcache_done_access(dcache_done_access), // from data cache
.v_dc_download(v_flits_dcache), // from dc_downlaod
.dc_download_flits(flits_dcache),
.v_cpu(v_cpu_access), // from cpu mem stage
.cpu_access_flits({cpu_head,cpu_addr,cpu_data}),
.v_m_d_areg(v_m_d_areg_flits_net), // from local mem
.m_d_areg_flits(m_d_areg_flits_net),
//output
.flits_dc(flits_dcache_abter), // selected flits to data cache
.v_flits_dc(v_flits_dcache_abter),
.re_dc_download_flits(re_dc_download_flits), // to dc_donwlaod
.re_cpu_access_flits(re_cpu_access_flits), // to cpu mem stage
.re_m_d_areg_flits(re_m_d_areg_flits), // to local mem
.cpu_done_access(cpu_done_access),
.dc_download_done_access(dc_download_done_access),
.m_d_areg_done_access(m_d_areg_done_access)
); // select source flits from cpu_access,IN_fifos msg and local memory access
arbiter_for_mem arbiter_for_mem_dut(
//input
.clk(clk),
.rst(rst),
.v_mem_download(v_m_download), // from mem_downlaod
.v_d_m_areg(v_d_m_areg), // from local data cache
.v_i_m_areg(v_i_m_areg), // from local inst cache
.mem_access_done(mem_access_done), // from local mem
//output
.ack_m_download(ack_m_download_net), // to m_download
.ack_d_m_areg(ack_d_m_areg_net), // to data cache via d_m_areg
.ack_i_m_areg(ack_i_m_areg_net),
.v_m_download_m(v_m_download_m_net), // to mem syaing these flits is valid
.v_d_m_areg_m(v_d_m_areg_m_net),
.v_i_m_areg_m(v_i_m_areg_m_net)
); // select source flits from local inst cache or local data cache or IN_fifos
arbiter_for_OUT_rep arbiter_for_OUT_rep_dut(
//input
.clk(clk),
.rst(rst),
.OUT_rep_rdy(OUT_rep_rdy), // from OUT_rep fifo
.v_dc_rep(v_dc_rep_flit_net), // from dc_upload
.v_mem_rep(v_m_rep_flit_net), // from mem_upload
.dc_rep_flit(dc_rep_flit_net),
.mem_rep_flit(m_rep_flit_net),
.dc_rep_ctrl(dc_rep_ctrl_net),
.mem_rep_ctrl(m_rep_ctrl_net),
//output
.ack_OUT_rep(OUT_rep_ack), // to OUT_rep fifo
.ack_dc_rep(ack_dc_rep_net), // to dc_upload
.ack_mem_rep(ack_mem_rep_net), //to mem_upload
.select(select2_net) // select 1/2
);// select src flit from dc_rep_upload and m_rep_upload
arbiter_for_OUT_req arbiter_for_OUT_req_dut(
//input
.clk(clk),
.rst(rst),
.OUT_req_rdy(OUT_req_rdy), // from OUT_req fifo
.v_ic_req(v_ic_req_flit_net), // from ic_upload_req
.v_dc_req(v_dc_req_flit_net), // from dc_upload_req
.v_mem_req(v_m_req_flit_net), // from mem_upload_req
.ic_req_ctrl(ic_req_ctrl_net),
.dc_req_ctrl(dc_req_ctrl_net),
.mem_req_ctrl(m_req_ctrl_net),
//output
.ack_OUT_req(OUT_req_ack), // to OUT_req
.ack_ic_req(ack_ic_req_net), // to ic_upload_req
.ack_dc_req(ack_dc_req_net), // to dc_
.ack_mem_req(ack_mem_req_net), // to mem_
.select(select3_net)// select one from three
);// select flit from ic_req_upload or dc_req_upload or m_req_upload
ic_download ic_download_dut(
//input
.clk(clk),
.rst(rst),
.rep_flit_ic(flit_ic_net), //from arbiter_for_IN_node
.v_rep_flit_ic(v_ic_net),
.rep_ctrl_ic(ctrl_ic_net),
.mem_flits_ic(mem_ic_download), // from local mem
.v_mem_flits_ic(v_mem_ic_download),
//output
.ic_download_state(ic_download_state_net), // to local mem and arbiter_IN_node
.inst_word_ic(inst_data), // to front of cpu
.v_inst_word(v_inst_rep)
); // receive rep from IN_rep or local mem
dc_download dc_download_dut(
//input
.clk(clk),
.rst(rst),
.IN_flit_dc(flit_dc_net), // from arrbiter_IN_node
.v_IN_flit_dc(v_dc_net),
.In_flit_ctrl_dc(ctrl_dc_net),
.dc_done_access(dcache_done_access), // from data cache
//output
.v_dc_download(v_flits_dcache), // to data cache
.dc_download_flits(flits_dcache),
.dc_download_state(dc_download_state_net) // to arbiter_IN_node
); // receive rep from IN_rep or req from IN_req
m_download m_download_dut(
//input
.clk(clk),
.rst(rst),
.IN_flit_mem(flit_mem_net), // from arrbiter_IN_node
.v_IN_flit_mem(v_mem_net),
.In_flit_ctrl(ctrl_mem_net),
.mem_done_access(mem_access_done), // from mem
//output
.v_m_download(v_m_download), // to arbiter_for_mem
.m_download_flits(m_donwload),
.m_download_state(mem_download_state_net) // to arbiter_IN_node
); // receive rep from IN_rep or req from IN_req
m_d_areg m_d_areg_dut(
//input
.clk(clk),
.rst(rst),
.m_flits_d(mem_m_d_areg), // from local mem
.v_m_flits_d(v_mem_m_d_areg),
.dc_done_access(dcache_done_access), // from data cache
//output
.m_d_areg_flits(m_d_areg_flits_net), // to data cache
.v_m_d_areg_flits(v_m_d_areg_flits_net),
.m_d_areg_state( m_d_areg_fsm_state) // to local mem
); // receive rep or req from local mem
d_m_areg d_m_areg_dut(
//input
.clk(clk), ////////////////////////////note :here local mem or data cache equals mem or data cache
.rst(rst),
.d_flits_m(dcache_d_m_areg), // from data cache
.v_d_flits_m(v_dcache_d_m_areg),
.mem_done_access(mem_access_done), // from local mem
///output
.d_m_areg_flits(d_m_areg), // to local mem
.v_d_m_areg_flits(v_d_m_areg),
.d_m_areg_state(d_m_areg_fsm_state) // to data cache
); // receive req or rep fromlocal data cache
i_m_areg i_m_areg_dut(
//input
.clk(clk),
.rst(rst),
.i_flits_m(req_i_m_areg), // from inst cache
.v_i_flits_m(v_req_i_m_areg),
.mem_done_access(mem_access_done), // from mem
//output
.i_m_areg_flits(i_m_areg), // to mem
.v_i_areg_m_flits(v_i_m_areg)
); // receive req from local inst cache
//note : here we need a ctrl output
m_rep_upload m_rep_upload_dut (
//input
.clk(clk),
.rst(rst),
.m_flits_rep(mem_m_rep), // from mem
.v_m_flits_rep(v_mem_m_rep),
.flits_max(m_flits_max_rep),
.en_flits_max(en_m_flits_max_rep),
.rep_fifo_rdy(ack_mem_rep_net), // from OUT_rep fifo
//output
.m_flit_out(m_rep_flit_net), // to arbiter_OUT_rep
.v_m_flit_out(v_m_rep_flit_net),
.m_ctrl_out(m_rep_ctrl_net),
.m_rep_upload_state(m_rep_fsm_state) // to mem
); //upload flits from mem to OUT_req
//note : here we need a ctrl output
dc_rep_upload dc_rep_upload_dut(
//input
.clk(clk),
.rst(rst),
.dc_flits_rep(dcache_dc_rep), // from dc
.v_dc_flits_rep(v_dcache_dc_rep),
.flits_max(dc_flits_max_rep),
.en_flits_max(en_dc_flits_max_rep),
.rep_fifo_rdy(ack_dc_rep_net), // from OUT_rep fifo
//output
.dc_flit_out(dc_rep_flit_net), // to arbiter_OUT_rep
.v_dc_flit_out(v_dc_rep_flit_net),
.dc_ctrl_out(dc_rep_ctrl_net),
.dc_rep_upload_state(dc_rep_fsm_state) //to dc
); //upload flits from dc to OUT_req
//note : here we need a ctrl output
ic_req_upload ic_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.ic_flits_req(flits_2_ic_req),// from ic
.v_ic_flits_req(v_flits_2_ic_req),
//here need a ctrl .req_fifo_rdy(ack_ic_req_net),
//output
.ic_flit_out(ic_req_flit_net), // to arbiter_OUT_req
.v_ic_flit_out(v_ic_req_flit_net),
.ic_ctrl_out(ic_req_ctrl_net),
.ic_req_upload_state(ic_download_fsm_state) // to inst cache
); //upload flits from ic(inst cache) to OUT_req
//note : here we need a ctrl output
m_req_upload m_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.v_flits_in(v_mem_m_req), // from mem
.out_req_fifo_rdy_in(ack_mem_req_net), //from OUT_req_fifo
.en_inv_ids(en_inv_ids), //from mem
.inv_ids_in(inv_ids_in),
.flits_max_in(m_flits_max_req),
.head_flit(mem_m_req[47:32]),
.addrhi(mem_m_req[31:16]),
.addrlo(mem_m_req[15:0]),
//output
.ctrl_out(m_req_ctrl_net), // to OUT_req_fifo
.flit_out(m_req_flit_net),
.fsm_state(m_req_fsm_state), // to mem
.v_flit_to_req_fifo(v_m_req_flit_net)
); //upload flits from mem to OUT_req
//note : here we need a ctrl output
dc_req_upload dc_req_upload_dut(
//input
.clk(clk),
.rst(rst),
.dc_flits_req(dcache_dc_req), // from dc
.v_dc_flits_req(v_dcache_dc_req),
.req_fifo_rdy(ack_dc_req_net), // from OUT_req_fifo
//output
.dc_flit_out(dc_req_flit_net), // to OUT_req_fifo
.v_dc_flit_out(v_dc_req_flit_net),
.dc_ctrl_out(dc_req_ctrl_net),
.dc_req_upload_state(dc_req_fsm_state) // to dc
); //upload flits from dc to OUT_rep
endmodule
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
mod_type
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [2:0] mod_type;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
assign adc_clk = ck_1356meg;
always @(negedge adc_clk)
begin
if(& adc_d[7:5]) after_hysteresis = 1'b1; // if (adc_d >= 224)
else if(~(| adc_d[7:5])) after_hysteresis = 1'b0; // if (adc_d <= 31)
end
// Divide 13.56 MHz to produce various frequencies for SSP_CLK
// and modulation.
reg [7:0] ssp_clk_divider;
always @(posedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
reg ssp_clk;
always @(negedge adc_clk)
begin
if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
ssp_clk <= ssp_clk_divider[7];
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
// Get next bit at 212kHz
ssp_clk <= ssp_clk_divider[5];
else
// Get next bit at 424Khz
ssp_clk <= ssp_clk_divider[4];
end
// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
// this is arbitrary, because it's just a bitstream.
// One nasty issue, though: I can't make it work with both rx and tx at
// once. The phase wrt ssp_clk must be changed. TODO to find out why
// that is and make a better fix.
reg [2:0] ssp_frame_divider_to_arm;
always @(posedge ssp_clk)
ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
reg [2:0] ssp_frame_divider_from_arm;
always @(negedge ssp_clk)
ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);
reg ssp_frame;
always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION) // not modulating, so listening, to ARM
ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
else
ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
reg modulating_carrier;
always @(*)
if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
modulating_carrier <= 1'b0; // no modulation
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else
modulating_carrier <= 1'b0; // yet unused
// Load modulation. Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_hi = 1'b0; // HF antenna connected to GND
assign pwr_oe3 = 1'b0; // 10k Load
assign pwr_oe1 = modulating_carrier; // 33 Ohms Load
assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
// This is all LF and doesn't matter
assign pwr_lo = 1'b0;
assign pwr_oe2 = 1'b0;
assign dbg = ssp_din;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: idecode.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: This RTL file specifies how instructions are to be decoded
// into their underlying meanings. This is specifically a version
// designed to support a "Next Generation", or "Version 2" instruction
// set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
// in cpudefs.v.
//
// I expect to (eventually) retire the old instruction set, at which point
// this will become the default instruction set decoder.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
`define CPU_SP_REG 4'hd
`define CPU_CC_REG 4'he
`define CPU_PC_REG 4'hf
//
`include "cpudefs.v"
//
//
//
module idecode(i_clk, i_rst, i_ce, i_stalled,
i_instruction, i_gie, i_pc, i_pf_valid,
i_illegal,
o_valid,
o_phase, o_illegal,
o_pc, o_gie,
o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
o_cond, o_wF,
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
o_wR, o_rA, o_rB,
o_early_branch, o_early_branch_stb, o_branch_pc, o_ljmp,
o_pipe,
o_sim, o_sim_immv
);
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
input wire i_clk, i_rst, i_ce, i_stalled;
input wire [31:0] i_instruction;
input wire i_gie;
input wire [(AW-1):0] i_pc;
input wire i_pf_valid, i_illegal;
output wire o_valid, o_phase;
output reg o_illegal;
output reg [AW:0] o_pc;
output reg o_gie;
output reg [6:0] o_dcdR, o_dcdA, o_dcdB;
output wire [31:0] o_I;
output reg o_zI;
output reg [3:0] o_cond;
output reg o_wF;
output reg [3:0] o_op;
output reg o_ALU, o_M, o_DV, o_FP, o_break;
output wire o_lock;
output reg o_wR, o_rA, o_rB;
output wire o_early_branch, o_early_branch_stb;
output wire [(AW-1):0] o_branch_pc;
output wire o_ljmp;
output wire o_pipe;
output reg o_sim /* verilator public_flat */;
output reg [22:0] o_sim_immv /* verilator public_flat */;
`ifdef OPT_PIPELINED
reg r_lock;
`endif
`ifdef OPT_PIPELINED_BUS_ACCESS
reg r_pipe;
`endif
wire [4:0] w_op;
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev,
w_noop, w_lock;
wire [4:0] w_dcdR, w_dcdB, w_dcdA;
wire w_dcdR_pc, w_dcdR_cc;
wire w_dcdA_pc, w_dcdA_cc;
wire w_dcdB_pc, w_dcdB_cc;
wire [3:0] w_cond;
wire w_wF, w_mem, w_sto, w_div, w_fpu;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp, w_ljmp_dly, w_cis_ljmp;
wire [31:0] iword;
`ifdef OPT_CIS
reg [15:0] r_nxt_half;
assign iword = (o_phase)
// set second half as a NOOP ... but really
// shouldn't matter
? { r_nxt_half[15:0], i_instruction[15:0] }
: i_instruction;
`else
assign iword = { 1'b0, i_instruction[30:0] };
`endif
generate
if (EARLY_BRANCHING != 0)
begin
`ifdef OPT_CIS
reg r_pre_ljmp;
always @(posedge i_clk)
if ((i_rst)||(o_early_branch))
r_pre_ljmp <= 1'b0;
else if ((i_ce)&&(i_pf_valid))
r_pre_ljmp <= (!o_phase)&&(i_instruction[31])
&&(i_instruction[14:0] == 15'h7cf8);
else if (i_ce)
r_pre_ljmp <= 1'b0;
assign w_cis_ljmp = r_pre_ljmp;
`else
assign w_cis_ljmp = 1'b0;
`endif
// 0.1111.10010.000.1.1111.000000000...
// 0111.1100.1000.0111.11000....
assign w_ljmp = (iword == 32'h7c87c000);
end else begin
assign w_cis_ljmp = 1'b0;
assign w_ljmp = 1'b0;
end
endgenerate
`ifdef OPT_CIS
`ifdef VERILATOR
wire [4:0] w_cis_op;
always @(iword)
if (!iword[31])
w_cis_op = w_op;
else case(iword[26:24])
3'h0: w_cis_op = 5'h00;
3'h1: w_cis_op = 5'h01;
3'h2: w_cis_op = 5'h02;
3'h3: w_cis_op = 5'h10;
3'h4: w_cis_op = 5'h12;
3'h5: w_cis_op = 5'h13;
3'h6: w_cis_op = 5'h18;
3'h7: w_cis_op = 5'h0d;
endcase
`else
reg [4:0] w_cis_op;
always @(iword,w_op)
if (!iword[31])
w_cis_op <= w_op;
else case(iword[26:24])
3'h0: w_cis_op <= 5'h00;
3'h1: w_cis_op <= 5'h01;
3'h2: w_cis_op <= 5'h02;
3'h3: w_cis_op <= 5'h10;
3'h4: w_cis_op <= 5'h12;
3'h5: w_cis_op <= 5'h13;
3'h6: w_cis_op <= 5'h18;
3'h7: w_cis_op <= 5'h0d;
endcase
`endif
`else
wire [4:0] w_cis_op;
assign w_cis_op = w_op;
`endif
assign w_op= iword[26:22];
assign w_mov = (w_cis_op == 5'h0d);
assign w_ldi = (w_cis_op[4:1] == 4'hc);
assign w_brev = (w_cis_op == 5'h8);
assign w_cmptst = (w_cis_op[4:1] == 4'h8);
assign w_ldilo = (w_cis_op[4:0] == 5'h9);
assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ...
&&(w_cis_op[3:1] != 3'h7); // not the divide
// w_dcdR (4 LUTs)
//
// What register will we be placing results into (if at all)?
//
// Two parts to the result register: the register set, given for
// moves in iword[18] but only for the supervisor, and the other
// four bits encoded in the instruction.
//
assign w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
iword[30:27] };
// 2 LUTs
//
// If the result register is either CC or PC, and this would otherwise
// be a floating point instruction with floating point opcode of 0,
// then this is a NOOP.
assign w_lock = (!iword[31])&&(w_op[4:0]==5'h1d)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
||(IMPLEMENT_FPU==0));
assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7))
||(IMPLEMENT_FPU==0));
// dcdB - What register is used in the opB?
//
assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie;
assign w_dcdB[3:0]= (iword[31])
? (((!iword[23])&&(iword[26:25]==2'b10))
? `CPU_SP_REG : iword[22:19])
: iword[17:14];
// 0 LUTs
assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg
// 2 LUTs, 1 delay each
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
// 0 LUTs
assign w_dcdA_pc = w_dcdR_pc;
assign w_dcdA_cc = w_dcdR_cc;
// 2 LUTs, 1 delays each
assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG);
assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG);
// Under what condition will we execute this
// instruction? Only the load immediate instruction
// is completely unconditional.
//
// 3+4 LUTs
assign w_cond = ((w_ldi)||(iword[31])) ? 4'h8 :
{ (iword[21:19]==3'h0), iword[21:19] };
// 1 LUT
assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00);
assign w_sto = (w_mem)&&( w_cis_op[0]);
// 1 LUT
assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7);
// 2 LUTs
assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11)
&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00);
//
// rA - do we need to read register A?
assign w_rA = // Floating point reads reg A
((w_fpu)&&(w_cis_op[4:1] != 4'hf))
// Divide's read A
||(w_div)
// ALU ops read A,
// except for MOV's and BREV's which don't
||((w_ALU)&&(!w_brev)&&(!w_mov))
// STO's read A
||(w_sto)
// Test/compares
||(w_cmptst);
// rB -- do we read a register for operand B? Specifically, do we
// add the registers value to the immediate to create opB?
assign w_rB = (w_mov)
||((!iword[31])&&(iword[18])&&(!w_ldi))
||(( iword[31])&&(iword[23])&&(!w_ldi))
// If using compressed instruction sets,
// we *always* read on memory operands.
||(( iword[31])&&(w_mem));
// wR -- will we be writing our result back?
// wR_n = !wR
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
assign w_wR_n = (w_sto)
||((!iword[31])&&(w_cis_op[4:3]==2'b11)
&&(w_cis_op[2:1]!=2'b00)
&&(w_dcdR[3:1]==3'h7))
||(w_cmptst);
assign w_wR = ~w_wR_n;
//
// wF -- do we write flags when we are done?
//
assign w_wF = (w_cmptst)
||((w_cond[3])&&((w_fpu)||(w_div)
||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev)
&&(w_dcdR[3:1] != 3'h7))));
// Bottom 13 bits: no LUT's
// w_dcd[12: 0] -- no LUTs
// w_dcd[ 13] -- 2 LUTs
// w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
// w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
reg [22:0] r_I;
wire [22:0] w_I, w_fullI;
wire w_Iz;
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI
// MOVE immediates have one less bit
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] }
// Normal Op-B immediate ... 18 or 14 bits
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
: { {(23-14){iword[13]}}, iword[13:0] }
));
`ifdef OPT_CIS
wire [7:0] w_halfbits;
assign w_halfbits = iword[23:16];
wire [7:0] w_halfI;
assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0]
:(w_halfbits[7])?
{ {(6){w_halfbits[2]}}, w_halfbits[1:0]}
:{ w_halfbits[6], w_halfbits[6:0] };
assign w_I = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI;
`else
assign w_I = w_fullI;
`endif
assign w_Iz = (w_I == 0);
`ifdef OPT_CIS
//
// The o_phase parameter is special. It needs to let the software
// following know that it cannot break/interrupt on an o_phase asserted
// instruction, lest the break take place between the first and second
// half of a CIS instruction. To do this, o_phase must be asserted
// when the first instruction half is valid, but not asserted on either
// a 32-bit instruction or the second half of a 2x16-bit instruction.
reg r_phase;
initial r_phase = 1'b0;
always @(posedge i_clk)
if ((i_rst) // When no instruction is in the pipe, phase is zero
||(o_early_branch)||(w_ljmp_dly))
r_phase <= 1'b0;
else if ((i_ce)&&(i_pf_valid))
r_phase <= (o_phase)? 1'b0
: ((i_instruction[31])&&(i_pf_valid));
else if (i_ce)
r_phase <= 1'b0;
// Phase is '1' on the first instruction of a two-part set
// But, due to the delay in processing, it's '1' when our output is
// valid for that first part, but that'll be the same time we
// are processing the second part ... so it may look to us like a '1'
// on the second half of processing.
assign o_phase = r_phase;
`else
assign o_phase = 1'b0;
`endif
initial o_illegal = 1'b0;
always @(posedge i_clk)
if (i_rst)
o_illegal <= 1'b0;
else if (i_ce)
begin
`ifdef OPT_CIS
o_illegal <= (i_illegal);
`else
o_illegal <= ((i_illegal) || (i_instruction[31]));
`endif
if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c)))
o_illegal <= 1'b1;
if ((IMPLEMENT_DIVIDE==0)&&(w_div))
o_illegal <= 1'b1;
else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7))
o_illegal <= 1'b1;
if ((IMPLEMENT_FPU==0)&&(w_fpu))
o_illegal <= 1'b1;
if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00)
&&(w_dcdR[3:1]==3'h7)
&&(
(w_cis_op[2:0] != 3'h4) // BREAK
`ifdef OPT_PIPELINED
&&(w_cis_op[2:0] != 3'h5) // LOCK
`endif
// SIM instructions are always illegal
&&(w_cis_op[2:0] != 3'h7))) // NOOP
o_illegal <= 1'b1;
end
always @(posedge i_clk)
if (i_ce)
begin
`ifdef OPT_CIS
if (!o_phase)
o_gie<= i_gie;
if (iword[31])
begin
if (o_phase)
o_pc <= o_pc + 1'b1;
else if (i_pf_valid)
o_pc <= { i_pc, 1'b1 };
end else begin
// The normal, non-CIS case
o_pc <= { i_pc + 1'b1, 1'b0 };
end
`else
o_gie<= i_gie;
o_pc <= { i_pc + 1'b1, 1'b0 };
`endif
// Under what condition will we execute this
// instruction? Only the load immediate instruction
// is completely unconditional.
o_cond <= w_cond;
// Don't change the flags on conditional instructions,
// UNLESS: the conditional instruction was a CMP
// or TST instruction.
o_wF <= w_wF;
// Record what operation/op-code (4-bits) we are doing
// Note that LDI magically becomes a MOV
// instruction here. That way it's a pass through
// the ALU. Likewise, the two compare instructions
// CMP and TST becomes SUB and AND here as well.
// We keep only the bottom four bits, since we've
// already done the rest of the decode necessary to
// settle between the other instructions. For example,
// o_FP plus these four bits uniquely defines the FP
// instruction, o_DV plus the bottom of these defines
// the divide, etc.
o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0];
// Default values
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
o_wR <= w_wR;
o_rA <= w_rA;
o_rB <= w_rB;
r_I <= w_I;
o_zI <= w_Iz;
// Turn a NOOP into an ALU operation--subtract in
// particular, although it doesn't really matter as long
// as it doesn't take longer than one clock. Note
// also that this depends upon not setting any registers
// or flags, which should already be true.
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop);
o_M <= w_mem;
o_DV <= w_div;
o_FP <= w_fpu;
o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&(
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7))
||(IMPLEMENT_FPU==0));
`ifdef OPT_PIPELINED
r_lock <= w_lock;
`endif
`ifdef OPT_CIS
r_nxt_half <= { iword[31], iword[14:0] };
`endif
`ifdef VERILATOR
// Support the SIM instruction(s)
o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf)
&&(w_dcdR[3:1] == 3'h7);
`else
o_sim <= 1'b0;
`endif
o_sim_immv <= iword[22:0];
end
`ifdef OPT_PIPELINED
assign o_lock = r_lock;
`else
assign o_lock = 1'b0;
`endif
generate
if (EARLY_BRANCHING!=0)
begin
reg r_early_branch,
r_early_branch_stb,
r_ljmp;
reg [(AW-1):0] r_branch_pc;
initial r_ljmp = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_ljmp <= 1'b0;
`ifdef OPT_CIS
else if ((i_ce)&&(o_phase))
r_ljmp <= w_cis_ljmp;
`endif
else if ((i_ce)&&(i_pf_valid))
r_ljmp <= (w_ljmp);
assign o_ljmp = r_ljmp;
always @(posedge i_clk)
if (i_rst)
begin
r_early_branch <= 1'b0;
r_early_branch_stb <= 1'b0;
end else if ((i_ce)&&(i_pf_valid))
begin
if (r_ljmp)
begin
// LOD (PC),PC
r_early_branch <= 1'b1;
r_early_branch_stb <= 1'b1;
end else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG)
&&(w_cond[3]))
begin
if ((w_op[4:0]==5'h02)&&(!iword[18]))
begin
// Add x,PC
r_early_branch <= 1'b1;
r_early_branch_stb <= 1'b1;
end else begin
r_early_branch <= 1'b0;
r_early_branch_stb <= 1'b0;
end
end else begin
r_early_branch <= 1'b0;
r_early_branch_stb <= 1'b0;
end
end else if (i_ce)
begin
r_early_branch <= 1'b0;
r_early_branch_stb <= 1'b0;
end else
r_early_branch_stb <= 1'b0;
always @(posedge i_clk)
if (i_ce)
begin
if (r_ljmp)
r_branch_pc <= iword[(AW+1):2];
else // Add x,PC
r_branch_pc <= i_pc
+ {{(AW-15){iword[17]}},iword[16:2]}
+ {{(AW-1){1'b0}},1'b1};
end
assign w_ljmp_dly = r_ljmp;
assign o_early_branch = r_early_branch;
assign o_early_branch_stb = r_early_branch_stb;
assign o_branch_pc = r_branch_pc;
end else begin
assign w_ljmp_dly = 1'b0;
assign o_early_branch = 1'b0;
assign o_early_branch_stb = 1'b0;
assign o_branch_pc = {(AW){1'b0}};
assign o_ljmp = 1'b0;
end endgenerate
// To be a pipeable operation there must be ...
// 1. Two valid adjacent instructions
// 2. Both must be memory operations, of the same time (both lods
// or both stos)
// 3. Both must use the same register base address
// 4. Both must be to the same address, or the address incremented
// by one
// Note that we're not using iword here ... there's a lot of logic
// taking place, and it's only valid if the new word is not compressed.
//
reg r_valid;
`ifdef OPT_PIPELINED_BUS_ACCESS
initial r_pipe = 1'b0;
always @(posedge i_clk)
if (i_ce)
r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase))
// Both must be memory operations
&&(w_mem)&&(o_M)
// Both must be writes, or both stores
&&(o_op[0] == w_cis_op[0])
// Both must be register ops
&&(w_rB)
// Both must use the same register for B
&&(w_dcdB[3:0] == o_dcdB[3:0])
// But ... the result can never be B
&&((o_op[0])
||(w_dcdB[3:0] != o_dcdA[3:0]))
// Needs to be to the mode, supervisor or user
&&(i_gie == o_gie)
// Same condition, or no condition before
&&((i_instruction[21:19]==o_cond[2:0])
||(o_cond[2:0] == 3'h0))
// Same immediate
&&((w_I[13:2]==r_I[13:2])
||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1)));
assign o_pipe = r_pipe;
`else
assign o_pipe = 1'b0;
`endif
always @(posedge i_clk)
if (i_rst)
r_valid <= 1'b0;
else if (i_ce)
r_valid <= ((i_pf_valid)||(o_phase)||(i_illegal))
&&(!o_ljmp)&&(!o_early_branch);
else if (!i_stalled)
r_valid <= 1'b0;
assign o_valid = r_valid;
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
// Make Verilator happy across all our various options
// verilator lint_off UNUSED
wire [3:0] possibly_unused;
assign possibly_unused = { w_lock, w_ljmp, w_ljmp_dly, w_cis_ljmp };
// verilator lint_on UNUSED
endmodule
|
(*
Copyright © 2006-2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Import CoRN.algebra.RSetoid.
Require Import CoRN.metric2.Metric.
Require Import CoRN.metric2.UniformContinuity.
Require Export CoRN.reals.fast.CRArith.
Require Import CoRN.reals.fast.CRIR.
Require Import CoRN.reals.Q_in_CReals.
Require Import CoRN.model.totalorder.QMinMax.
Require Import CoRN.reals.fast.CRarctan_small.
Require Import CoRN.transc.MoreArcTan.
Require Import CoRN.tactics.CornTac.
Require Import CoRN.stdlib_omissions.Q.
Set Implicit Arguments.
Local Open Scope Q_scope.
Local Open Scope uc_scope.
Opaque inj_Q CR.
Section Pi.
(**
** Pi (alternate)
(Please import CRpi instead)
This version is slower to compute than CRpi_fast; however it is faster to
compile.
Pi is defined as
68*arctan(1/23) + 32*arctan(1/182) + 40*arctan(1/5118) + 20*arctan(1/6072).
*)
Lemma small_per_23 : (0 <= (1#(23%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_182 : (0 <= (1#(182%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_5118 : (0 <= (1#(5118%positive)) < 1)%Q.
Proof. split; easy. Qed.
Lemma small_per_6072 : (0 <= (1#(6072%positive)) < 1)%Q.
Proof. split; easy. Qed.
Definition r_pi (r:Q) : CR :=
((scale (68%Z*r) (rational_arctan_small_pos small_per_23) +
scale (32%Z*r) (rational_arctan_small_pos small_per_182)) +
(scale (40%Z*r) (rational_arctan_small_pos small_per_5118) +
scale (20%Z*r) (rational_arctan_small_pos small_per_6072)))%CR.
(** To prove that pi is is correct we repeatedly use the arctan sum law.
The problem is that the arctan sum law only works for input between -1
and 1. We use reflect to show that our use of arctan sum law always
satifies this restriction. *)
Let f (a b:Q) : Q :=
let (x,y) := a in
let (z,w) := b in
Qred ((x*w + y*z)%Z/(y*w-x*z)%Z).
Lemma f_char : forall a b, f a b == (a+b)/(1-a*b).
Proof.
intros [x y] [w z].
unfold f.
rewrite -> Qred_correct.
destruct (Z.eq_dec (y*z) (x*w)) as [H|H].
unfold Qmult.
simpl ((Qnum (x # y) * Qnum (w # z) # Qden (x # y) * Qden (w # z))).
repeat rewrite <- H.
replace (y * z - y * z)%Z with 0%Z by ring.
setoid_replace (1-(y * z # y * z)) with 0.
change ((x * z + y * w)%Z * 0 == ((x # y) + (w # z)) * 0).
ring.
rewrite -> (Qmake_Qdiv (y*z)).
change (1 - (y * z)%positive / (y * z)%positive == 0).
field; discriminate.
unfold Zminus.
repeat rewrite -> injz_plus.
change (((x * Zpos z) + (Zpos y * w)) / (Zpos y * Zpos z - x * w) == ((x # y) + (w # z)) / (1 - (x #y)*(w # z))).
repeat rewrite -> Qmake_Qdiv.
field.
repeat split; try discriminate.
cut (~(y * z)%Z == (x * w)%Z).
intros X Y.
apply X.
replace RHS with ((x * w)%Z + 0) by simpl; ring.
rewrite <- Y.
change ((y * z) == (x * w) + (y * z - x * w)).
ring.
intros X; apply H.
unfold Qeq in X.
simpl in X.
rewrite Pmult_1_r in X.
change ((y * z)%Z = (x * w * 1)%Z) in X.
rewrite X.
ring.
Qed.
Lemma ArcTan_plus_ArcTan_Q : forall x y, -(1) <= x <= 1 -> -(1) <= y <= 1 -> ~1-x*y==0 ->
(ArcTan (inj_Q _ x)[+]ArcTan (inj_Q _ y)[=]ArcTan (inj_Q _ (f x y))).
Proof.
intros x y [Hx0 Hx1] [Hy0 Hy1] H.
assert (X:forall z, -(1) <= z -> [--][1][<=]inj_Q IR z).
intros z Hz.
stepl ((inj_Q IR (-(1)))).
apply inj_Q_leEq; assumption.
eapply eq_transitive.
apply (inj_Q_inv IR (1)).
apply un_op_wd_unfolded.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
assert (X0:forall z, z <= 1 -> inj_Q IR z[<=][1]).
intros z Hz.
stepr ((inj_Q IR ((1)))).
apply inj_Q_leEq; assumption.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
assert ([1][-](inj_Q IR x)[*](inj_Q IR y)[#][0]).
stepl (inj_Q IR (1[-]x[*]y)).
(stepr (inj_Q IR [0]); [| now apply (inj_Q_nring IR 0)]).
apply inj_Q_ap; assumption.
eapply eq_transitive.
apply inj_Q_minus.
apply bin_op_wd_unfolded.
rstepr (nring 1:IR); apply (inj_Q_nring IR 1).
apply un_op_wd_unfolded.
apply inj_Q_mult.
apply eq_transitive with (ArcTan (inj_Q IR x[+]inj_Q IR y[/]([1][-]inj_Q IR x[*]inj_Q IR y)[//]X1)).
apply ArcTan_plus_ArcTan; first [apply X; assumption |apply X0; assumption].
apply ArcTan_wd.
stepl (inj_Q IR ((x[+]y)/([1][-]x*y))).
apply inj_Q_wd.
simpl.
symmetry.
apply f_char.
assert (H0:(inj_Q IR ([1][-]x * y))[#][0]).
(stepr (inj_Q IR 0); [| now apply (inj_Q_nring IR 0)]).
apply inj_Q_ap; assumption.
apply eq_transitive with (inj_Q IR (x[+]y)[/]inj_Q IR ([1][-]x * y)[//]H0).
apply (inj_Q_div).
apply div_wd.
apply inj_Q_plus.
eapply eq_transitive.
apply inj_Q_minus.
apply bin_op_wd_unfolded.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
apply un_op_wd_unfolded.
apply inj_Q_mult.
Qed.
Definition ArcTan_multiple : forall x, -(1) <= x <= 1 -> forall n, {True} + {(nring n)[*]ArcTan (inj_Q _ x)[=]ArcTan (inj_Q _ (iter_nat n _ (f x) 0))}.
Proof.
intros x Hx.
induction n.
right.
abstract ( rstepl ([0]:IR); (stepl (ArcTan [0]); [| now apply ArcTan_zero]); apply ArcTan_wd;
apply eq_symmetric; apply (inj_Q_nring IR 0)).
simpl.
destruct (IHn) as [H|H].
left; constructor.
set (y:=(iter_nat n Q (f x) 0)) in *.
destruct (Qlt_le_dec_fast 1 y) as [_|Y0].
left; constructor.
destruct (Qlt_le_dec_fast y (-(1))) as [_|Y1].
left; constructor.
destruct (Qeq_dec (1-x*y) 0) as [_|Y2].
left; constructor.
right.
abstract ( rstepl (ArcTan (inj_Q IR x)[+](nring n[*]ArcTan (inj_Q IR x))); csetoid_rewrite H;
apply ArcTan_plus_ArcTan_Q; try assumption; split; assumption).
Defined.
Lemma reflect_right : forall A B (x:{A}+{B}), (match x with left _ => False | right _ => True end) -> B.
Proof.
intros A B x.
elim x.
contradiction.
trivial.
Qed.
Lemma Pi_Formula :
(((nring 17)[*]ArcTan (inj_Q IR (1 / 23%Z))[+]
(nring 8)[*]ArcTan (inj_Q IR (1 / 182%Z))[+]
(nring 10)[*]ArcTan (inj_Q IR (1 / 5118%Z))[+]
(nring 5)[*]ArcTan (inj_Q IR (1 / 6072%Z)))[=]
Pi[/]FourNZ).
Proof.
assert (H0:-(1) <= (1/(23%Z)) <= 1).
split; discriminate.
assert (H1:-(1) <= (1/(182%Z)) <= 1).
split; discriminate.
assert (H2:-(1) <= (1/(5118%Z)) <= 1).
split; discriminate.
assert (H3:-(1) <= (1/(6072%Z)) <= 1).
split; discriminate.
set (y0:=(iter_nat 17 _ (f (1/23%Z)) 0)).
set (y1:=(iter_nat 8 _ (f (1/182%Z)) 0)).
set (y2:=(iter_nat 10 _ (f (1/5118%Z)) 0)).
set (y3:=(iter_nat 5 _ (f (1/6072%Z)) 0)).
rstepl (nring 17[*]ArcTan (inj_Q IR (1 / 23%Z))[+]
nring 8[*]ArcTan (inj_Q IR (1 / 182%Z))[+]
(nring 10[*]ArcTan (inj_Q IR (1 / 5118%Z))[+]
nring 5[*]ArcTan (inj_Q IR (1 / 6072%Z)))).
csetoid_replace ((nring 17)[*]ArcTan (inj_Q IR (1 / 23%Z))) (ArcTan (inj_Q IR y0));
[|apply (reflect_right (ArcTan_multiple H0 17)); vm_compute; constructor].
csetoid_replace ((nring 8)[*]ArcTan (inj_Q IR (1 / 182%Z))) (ArcTan (inj_Q IR y1));
[|apply (reflect_right (ArcTan_multiple H1 8)); vm_compute; constructor].
csetoid_replace ((nring 10)[*]ArcTan (inj_Q IR (1 / 5118%Z))) (ArcTan (inj_Q IR y2));
[|apply (reflect_right (ArcTan_multiple H2 10)); vm_compute; constructor].
csetoid_replace ((nring 5)[*]ArcTan (inj_Q IR (1 / 6072%Z))) (ArcTan (inj_Q IR y3));
[|apply (reflect_right (ArcTan_multiple H3 5)); vm_compute; constructor].
vm_compute in y0.
vm_compute in y1.
vm_compute in y2.
vm_compute in y3.
csetoid_replace (ArcTan (inj_Q IR y0)[+]ArcTan (inj_Q IR y1)) (ArcTan (inj_Q IR (f y0 y1)));
[|apply ArcTan_plus_ArcTan_Q; try split; vm_compute; discriminate].
csetoid_replace (ArcTan (inj_Q IR y2)[+]ArcTan (inj_Q IR y3)) (ArcTan (inj_Q IR (f y2 y3)));
[|apply ArcTan_plus_ArcTan_Q; try split; vm_compute; discriminate].
set (z0 := (f y0 y1)).
set (z1 := (f y2 y3)).
vm_compute in z0.
vm_compute in z1.
csetoid_replace (ArcTan (inj_Q IR z0)[+]ArcTan (inj_Q IR z1)) (ArcTan (inj_Q IR (f z0 z1)));
[|apply ArcTan_plus_ArcTan_Q; try split; vm_compute; discriminate].
set (z3:= (f z0 z1)).
vm_compute in z3.
eapply eq_transitive;[|apply ArcTan_one].
apply ArcTan_wd.
rstepr (nring 1:IR).
apply (inj_Q_nring IR 1).
Qed.
Lemma r_pi_correct : forall r,
(r_pi r == IRasCR ((inj_Q IR r)[*]Pi))%CR.
Proof.
intros r.
unfold r_pi.
repeat rewrite <- (CRmult_scale).
setoid_replace ((68*r)) with ((4*r*17)) by (simpl; ring).
setoid_replace (32*r) with (4*r*8) by (simpl; ring).
setoid_replace (40*r) with (4*r*10) by (simpl; ring).
setoid_replace (20*r) with (4*r*5) by (simpl; ring).
repeat rewrite <- CRmult_Qmult.
transitivity ('4 * 'r *(' 17 * rational_arctan_small_pos small_per_23 +
' 8 * rational_arctan_small_pos small_per_182 + (' 10 * rational_arctan_small_pos small_per_5118 +
' 5 * rational_arctan_small_pos small_per_6072)))%CR.
ring.
repeat rewrite rational_arctan_small_pos_correct.
repeat rewrite <- IR_inj_Q_as_CR.
repeat (rewrite <- IR_mult_as_CR || rewrite <- IR_plus_as_CR).
apply IRasCR_wd.
rstepr (Four[*]inj_Q IR r[*]Pi[/]FourNZ).
apply mult_wd.
apply mult_wdl.
apply (inj_Q_nring IR 4).
eapply eq_transitive;[|apply Pi_Formula].
rstepr (nring 17[*]ArcTan (inj_Q IR (1 / 23%Z))[+]
nring 8[*]ArcTan (inj_Q IR (1 / 182%Z))[+]
(nring 10[*]ArcTan (inj_Q IR (1 / 5118%Z))[+]
nring 5[*]ArcTan (inj_Q IR (1 / 6072%Z)))).
repeat apply bin_op_wd_unfolded; try apply eq_reflexive.
apply (inj_Q_nring IR 17).
apply (inj_Q_nring IR 8).
apply (inj_Q_nring IR 10).
apply (inj_Q_nring IR 5).
Qed.
Definition CRpi : CR := (r_pi 1).
Lemma CRpi_correct : (IRasCR Pi == CRpi)%CR.
Proof.
unfold CRpi.
rewrite -> r_pi_correct.
apply IRasCR_wd.
rstepl ((nring 1)[*]Pi).
apply mult_wdl.
apply eq_symmetric.
apply (inj_Q_nring IR 1).
Qed.
End Pi.
(* begin hide *)
Hint Rewrite CRpi_correct : IRtoCR.
(* end hide *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06.03.2016 12:07:59
// Design Name:
// Module Name: FSM_C_CORDIC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_C_CORDIC(
//INPUTS
input wire CLK, //system clock
input wire RST_EX, //system reset
input wire ACK_ADD_SUBTX, //RECIBE SI LA SUMA EN FLOTANTE X SE EJECUTO
input wire ACK_ADD_SUBTY, //RECIBE SI LA SUMA EN FLOTANTE Y SE EJECUTO
input wire ACK_ADD_SUBTZ, //RECIBE SI LA SUMA EN FLOTANTE Z SE EJECUTO
input wire ACK_MULT, //RECIBE SI LA MULT EN FLOTANTE X*Y SE EJECUTO
input wire Begin_FSM_EX, //inicia la maquina de estados
input wire [4:0] CONT_ITER,//LLEVA LA CUENTA DE LA ITERACIONES
//OUTPUT SIGNALS
output reg RST, //REALIZA EL RESET DE LOS REGISTROS
output reg MS_1, //SELECCION DEL MUX 1
output reg [1:0] MS_M, //SELECCION DEL MUX_M
output reg EN_REG3, //ENABLE PARA EL REGISTRO 3 CON EL VALOR DEL EXP = COSH + SIN H
output reg EN_REG4, //ENABLE PARA EL REGISTRO 4 CON EL VALOR FINAL DEL RESULTADO CALCULADO
output reg ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
output reg Begin_SUMX, //INICIA ADD/SUM FLOTANTE X
output reg Begin_SUMY, //INICIA ADD/SUM FLOTANTE Y
output reg Begin_SUMZ, //INICIA ADD/SUM FLOTANTE Z
output reg Begin_MULT, //INICIA MULT FLOTANTE X*Y
output reg EN_REG1X, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Y, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg EN_REG1Z, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
output reg [1:0] MS_2, //SELECCION DEL MUX 2
output reg EN_REG2, //ENABLE PARA EL REGISTRO CON LOS VALORES DESPLAZADOS DE LA SEGUNDA ETAPA
output reg CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
output reg EN_REG2XYZ, //ENABLE PARA EL VALOR ANTERIOR DE XYZ DE SEGUNDA ETAPA
output reg ACK_EX, //ACK PARA SABER SI LA OPERACION EX YA SE REALIZO
//registros de selectores
output reg EN_ADDSUBT,
output reg EN_MS_M,
output reg EN_MS1,
output reg EN_MS2
);
parameter [5:0]
//se definen los estados que se utilizaran en la maquina
a = 6'd0,
b = 6'd1,
c = 6'd2,
d = 6'd3,
e = 6'd4,
f = 6'd5,
g = 6'd6,
h = 6'd7,
i = 6'd8,
j = 6'd9,
k = 6'd10,
l = 6'd11,
m = 6'd12,
n = 6'd13,
o = 6'd14,
p = 6'd15,
q = 6'd16,
r = 6'd17,
s = 6'd18,
t = 6'd19;
reg [5:0] state_reg, state_next ; //state registers declaration
////
always @(posedge CLK, posedge RST_EX)
if (RST_EX) begin
state_reg <= a;
end
else begin
state_reg <= state_next;
end
//assign State = state_reg;
///
always @*
begin
state_next = state_reg;
EN_REG2 = 0;
EN_REG3 = 0;
EN_REG4 = 0;
EN_REG1X = 0;
EN_REG1Y = 0;
EN_REG1Z = 0;
EN_REG2XYZ = 0;
Begin_SUMX = 0;
Begin_SUMY = 0;
Begin_SUMZ = 0;
Begin_MULT = 0;
ACK_EX = 0;
CLK_CDIR = 0;
RST = 0;
MS_M = 2'b00;
MS_1 = 0;
MS_2 = 2'b00;
ADD_SUBT = 0;
EN_ADDSUBT = 0;
EN_MS_M = 0;
EN_MS1 = 0;
EN_MS2 = 0;
//nuevos estados
case(state_reg)
a:
begin
if(Begin_FSM_EX)
begin
RST = 1;
state_next = b;
end
else
state_next = a;
end
b:
begin
ADD_SUBT = 0;
EN_ADDSUBT = 1;
MS_M = 2'b00;
EN_MS_M = 1;
MS_1 = 1;
EN_MS1 = 1;
MS_2 = 2'b10;
EN_MS2 = 1;
state_next = c;
end
c:
begin
Begin_SUMZ = 1;
state_next = d;
end
d:
begin
state_next = e;
end
e:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG1X = 1;
EN_REG1Y = 1;
EN_REG1Z = 1;
state_next = f;
end
else
state_next = e;
end
f:
begin
MS_1 = 0;
EN_MS1= 1;
MS_2 = 2'b01;
EN_MS2 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = g;
end
g:
begin
state_next = h;
end
h:
begin
if(CONT_ITER == 5'b00001)
begin
MS_M = 2'b01;
EN_MS_M = 1;
state_next = i;
end
else if (CONT_ITER >= 5'b00010)
begin
MS_M = 2'b10;
EN_MS_M = 1;
state_next = i;
end
else
state_next = i;
end
i:
begin
EN_REG2 = 1;
state_next = j;
end
j:
begin
EN_REG2XYZ = 1;
state_next = k;
end
k:
begin
Begin_SUMX = 1;
Begin_SUMY = 1;
CLK_CDIR = 1;
state_next = l;
end
l:
begin
state_next = m;
end
m:
begin
Begin_SUMZ = 1;
if(ACK_ADD_SUBTX & ACK_ADD_SUBTY)
begin
EN_REG1X = 1;
EN_REG1Y = 1;
//Begin_SUMZ = 1;
state_next = n;
end
else
state_next = m;
end
n:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG1Z = 1;
state_next = o;
end
else
state_next = n;
end
o:
begin
if(CONT_ITER == 5'b01111 )//if(CONT_ITER == 5'b01111 ) //15 iteraciones
begin
MS_2 = 0;
EN_MS2 = 1;
ADD_SUBT = 0;
EN_ADDSUBT = 1;
state_next = p;
end
else
state_next = g;
end
p:
begin
Begin_SUMZ = 1;
state_next = q;
end
q:
begin
if(ACK_ADD_SUBTZ)
begin
EN_REG3 = 1;
state_next = r;
end
else
state_next = q;
end
r:
begin
Begin_MULT = 1;
state_next = s;
end
s:
begin
if(ACK_MULT)
begin
EN_REG4 = 1;
state_next = t;
end
else
state_next = s;
end
t:
begin
ACK_EX = 1;
if(RST_EX)
begin
RST = 1;
state_next = a;
end
end
endcase
end
endmodule
//`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////////
//// Company:
//// Engineer:
////
//// Create Date: 06.03.2016 12:07:59
//// Design Name:
//// Module Name: FSM_C_CORDIC
//// Project Name:
//// Target Devices:
//// Tool Versions:
//// Description:
////
//// Dependencies:
////
//// Revision:
//// Revision 0.01 - File Created
//// Additional Comments:
////
////////////////////////////////////////////////////////////////////////////////////
//module FSM_C_CORDIC(
// //INPUTS
// input wire CLK, //system clock
// input wire RST_EX, //system reset
// input wire ACK_ADD_SUBTX, //RECIBE SI LA SUMA EN FLOTANTE X SE EJECUTO
// input wire ACK_ADD_SUBTY, //RECIBE SI LA SUMA EN FLOTANTE Y SE EJECUTO
// input wire ACK_ADD_SUBTZ, //RECIBE SI LA SUMA EN FLOTANTE Z SE EJECUTO
// input wire Begin_FSM_EX, //inicia la maquina de estados
// input wire [4:0] CONT_ITER,//LLEVA LA CUENTA DE LA ITERACIONES
// //OUTPUT SIGNALS
// output reg RST, //REALIZA EL RESET DE LOS REGISTROS
// output reg MS_1, //SELECCION DEL MUX 1
// output reg [1:0] MS_M, //SELECCION DEL MUX_M
// output reg EN_REG3, //ENABLE PARA EL REGISTRO 3 CON EL VALOR FINAL DEL RESULTADO CALCULADO
// output reg ADD_SUBT, //SELECCION DE OPERACION PARA EL ADD/SUBT FLOTANTE
// output reg Begin_SUMX, //INICIA ADD/SUM FLOTANTE X
// output reg Begin_SUMY, //INICIA ADD/SUM FLOTANTE Y
// output reg Begin_SUMZ, //INICIA ADD/SUM FLOTANTE Z
// output reg EN_REG1X, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
// output reg EN_REG1Y, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
// output reg EN_REG1Z, //ENABLE PARA LOS REGISTROS X,Y,Z DE LA PRIMERA ETAPA
// output reg [1:0] MS_2, //SELECCION DEL MUX 2
// output reg EN_REG2, //ENABLE PARA EL REGISTRO CON LOS VALORES DESPLAZADOS DE LA SEGUNDA ETAPA
// output reg CLK_CDIR, //CLK PARA EL CONTADOR DE ITERACIONES
// output reg EN_REG2XYZ, //ENABLE PARA EL VALOR ANTERIOR DE XYZ DE SEGUNDA ETAPA
// output reg ACK_EX, //ACK PARA SABER SI LA OPERACION EX YA SE REALIZO
// //registros de selectores
// output reg EN_ADDSUBT,
// output reg EN_MS_M,
// output reg EN_MS1,
// output reg EN_MS2
// );
//parameter [5:0]
// //se definen los estados que se utilizaran en la maquina
// a = 6'd0,
// b = 6'd1,
// c = 6'd2,
// d = 6'd3,
// e = 6'd4,
// f = 6'd5,
// g = 6'd6,
// h = 6'd7,
// i = 6'd8,
// j = 6'd9,
// k = 6'd10,
// l = 6'd11,
// m = 6'd12,
// n = 6'd13,
// o = 6'd14,
// p = 6'd15,
// q = 6'd16,
// r = 6'd17;
//reg [5:0] state_reg, state_next ; //state registers declaration
//////
//always @(posedge CLK, posedge RST_EX)
// if (RST_EX) begin
// state_reg <= a;
// end
// else begin
// state_reg <= state_next;
// end
////assign State = state_reg;
/////
//always @*
// begin
// state_next = state_reg;
// EN_REG2 = 0;
// EN_REG3 = 0;
// EN_REG1X = 0;
// EN_REG1Y = 0;
// EN_REG1Z = 0;
// EN_REG2XYZ = 0;
// Begin_SUMX = 0;
// Begin_SUMY = 0;
// Begin_SUMZ = 0;
// ACK_EX = 0;
// CLK_CDIR = 0;
// RST = 0;
// MS_M = 2'b00;
// MS_1 = 0;
// MS_2 = 2'b00;
// ADD_SUBT = 0;
// EN_ADDSUBT = 0;
// EN_MS_M = 0;
// EN_MS1 = 0;
// EN_MS2 = 0;
// //nuevos estados
//case(state_reg)
// a:
// begin
// if(Begin_FSM_EX)
// begin
// RST = 1;
// state_next = b;
// end
// else
// state_next = a;
// end
// b:
// begin
// ADD_SUBT = 0;
// EN_ADDSUBT = 1;
// MS_M = 2'b00;
// EN_MS_M = 1;
// MS_1 = 1;
// EN_MS1 = 1;
// MS_2 = 2'b10;
// EN_MS2 = 1;
// state_next = c;
// end
// c:
// begin
// Begin_SUMZ = 1;
// state_next = d;
// end
// /*d:
// begin
// state_next = e;
// end*/
// d:
// begin
// if(ACK_ADD_SUBTZ)
// begin
// EN_REG1X = 1;
// EN_REG1Y = 1;
// EN_REG1Z = 1;
// state_next = e;
// end
// else
// state_next = d;
// end
// e:
// begin
// MS_1 = 0;
// EN_MS1= 1;
// MS_2 = 2'b01;
// EN_MS2 = 1;
// ADD_SUBT = 0;
// EN_ADDSUBT = 1;
// state_next = f;
// end
// f:
// begin
// state_next = g;
// end
// g:
// begin
// if(CONT_ITER == 5'b00001)
// begin
// MS_M = 2'b01;
// EN_MS_M = 1;
// state_next = h;
// end
// else if (CONT_ITER >= 5'b00010)
// begin
// MS_M = 2'b10;
// EN_MS_M = 1;
// state_next = h;
// end
// else
// state_next = h;
// end
// h:
// begin
// EN_REG2 = 1;
// state_next = i;
// end
// i:
// begin
// EN_REG2XYZ = 1;
// state_next = j;
// end
// j:
// begin
// Begin_SUMX = 1;
// Begin_SUMY = 1;
// CLK_CDIR = 1;
// state_next = k;
// end
// k:
// begin
// state_next = l;
// end
// l:
// begin
// Begin_SUMZ = 1;
// if(ACK_ADD_SUBTX & ACK_ADD_SUBTY)
// begin
// EN_REG1X = 1;
// EN_REG1Y = 1;
// //Begin_SUMZ = 1;
// state_next = m;
// end
// else
// state_next = l;
// end
// m:
// begin
// if(ACK_ADD_SUBTZ)
// begin
// EN_REG1Z = 1;
// state_next = n;
// end
// else
// state_next = m;
// end
// n:
// begin
// if(CONT_ITER == 5'b01111 )//if(CONT_ITER == 5'b01111 ) //15 iteraciones
// begin
// MS_2 = 0;
// EN_MS2 = 1;
// ADD_SUBT = 0;
// EN_ADDSUBT = 1;
// state_next = o;
// end
// else
// state_next = f;
// end
// o:
// begin
// Begin_SUMZ = 1;
// state_next = p;
// end
// p:
// begin
// if(ACK_ADD_SUBTZ)
// begin
// EN_REG3 = 1;
// state_next = q;
// end
// else
// state_next = p;
// end
// q:
// begin
// ACK_EX = 1;
// if(RST_EX)
// begin
// RST = 1;
// state_next = a;
// end
// end
// endcase
//end
//endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/vram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Video RAM module; implements 2KB of on-board VRAM as fpga block RAM.
***************************************************************************************************/
module vram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire vram_bram_we;
wire [7:0] vram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) vram_bram(
.clk(clk_in),
.we(vram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(vram_bram_dout)
);
assign vram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? vram_bram_dout : 8'h00;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "seq_gen/seq_gen.v"
`include "seq_gen/seq_gen_core.v"
`include "seq_rec/seq_rec.v"
`include "seq_rec/seq_rec_core.v"
`include "utils/3_stage_synchronizer.v"
`include "utils/flag_domain_crossing.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/ramb_8_to_n.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
localparam PULSE_BASEADDR = 32'h0000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam SEQ_GEN_BASEADDR = 32'h1000_0000;
localparam SEQ_GEN_HIGHADDR = 32'h2000_0000-1;
localparam SEQ_REC_BASEADDR = 32'h2000_0000;
localparam SEQ_REC_HIGHADDR = 32'h3000_0000 - 1;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
`ifdef BITS
localparam BITS = `BITS;
`else
localparam BITS = 8;
`endif
`ifdef MEM_KB
localparam MEM_KB = `MEM_KB;
`else
localparam MEM_KB = 1;
`endif
wire EX_START_PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
wire [BITS-1:0] SEQ_OUT;
seq_gen #(
.BASEADDR(SEQ_GEN_BASEADDR),
.HIGHADDR(SEQ_GEN_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_KB*1024),
.OUT_BITS(BITS)
) i_seq_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_OUT(SEQ_OUT)
);
seq_rec #(
.BASEADDR(SEQ_REC_BASEADDR),
.HIGHADDR(SEQ_REC_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_KB*1024),
.IN_BITS(BITS)
) i_seq_rec (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SEQ_EXT_START(EX_START_PULSE),
.SEQ_CLK(BUS_CLK),
.SEQ_IN(SEQ_OUT)
);
initial begin
$dumpfile("seq.vcd");
$dumpvars(0);
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:26 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
(bvalid_cnt_inc,
bid_gets_fifo_load_d1_reg,
bid_gets_fifo_load,
axi_wdata_full_cmb114_out,
\axi_bid_int_reg[0] ,
s_axi_aresetn,
s_axi_aclk,
\bvalid_cnt_reg[2] ,
wr_addr_sm_cs,
\bvalid_cnt_reg[2]_0 ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
axi_awaddr_full,
bram_addr_ld_en,
bid_gets_fifo_load_d1,
s_axi_bready,
axi_bvalid_int_reg,
bvalid_cnt,
\bvalid_cnt_reg[1] ,
aw_active,
s_axi_awready,
s_axi_awvalid,
curr_awlen_reg_1_or_2,
axi_awlen_pipe_1_or_2,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
last_data_ack_mod,
axi_awid_pipe,
s_axi_awid,
s_axi_bid,
out,
axi_wr_burst,
s_axi_wvalid,
s_axi_wlast);
output bvalid_cnt_inc;
output bid_gets_fifo_load_d1_reg;
output bid_gets_fifo_load;
output axi_wdata_full_cmb114_out;
output \axi_bid_int_reg[0] ;
input s_axi_aresetn;
input s_axi_aclk;
input \bvalid_cnt_reg[2] ;
input wr_addr_sm_cs;
input \bvalid_cnt_reg[2]_0 ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input axi_awaddr_full;
input bram_addr_ld_en;
input bid_gets_fifo_load_d1;
input s_axi_bready;
input axi_bvalid_int_reg;
input [2:0]bvalid_cnt;
input \bvalid_cnt_reg[1] ;
input aw_active;
input s_axi_awready;
input s_axi_awvalid;
input curr_awlen_reg_1_or_2;
input axi_awlen_pipe_1_or_2;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input last_data_ack_mod;
input axi_awid_pipe;
input [0:0]s_axi_awid;
input [0:0]s_axi_bid;
input [2:0]out;
input axi_wr_burst;
input s_axi_wvalid;
input s_axi_wlast;
wire \Addr_Counters[0].FDRE_I_n_0 ;
wire \Addr_Counters[1].FDRE_I_n_0 ;
wire \Addr_Counters[2].FDRE_I_n_0 ;
wire \Addr_Counters[3].FDRE_I_n_0 ;
wire \Addr_Counters[3].XORCY_I_i_1_n_0 ;
wire CI;
wire D;
wire Data_Exists_DFF_i_2_n_0;
wire Data_Exists_DFF_i_3_n_0;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire S;
wire S0_out;
wire S1_out;
wire addr_cy_1;
wire addr_cy_2;
wire addr_cy_3;
wire aw_active;
wire axi_awaddr_full;
wire axi_awid_pipe;
wire axi_awlen_pipe_1_or_2;
wire \axi_bid_int[0]_i_2_n_0 ;
wire \axi_bid_int_reg[0] ;
wire axi_bvalid_int_i_4_n_0;
wire axi_bvalid_int_i_5_n_0;
wire axi_bvalid_int_i_6_n_0;
wire axi_bvalid_int_reg;
wire axi_wdata_full_cmb114_out;
wire axi_wr_burst;
wire bid_fifo_ld;
wire bid_fifo_not_empty;
wire bid_fifo_rd;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_3_n_0;
wire bid_gets_fifo_load_d1_reg;
wire bram_addr_ld_en;
wire [2:0]bvalid_cnt;
wire bvalid_cnt_inc;
wire \bvalid_cnt_reg[1] ;
wire \bvalid_cnt_reg[2] ;
wire \bvalid_cnt_reg[2]_0 ;
wire curr_awlen_reg_1_or_2;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [0:0]s_axi_awid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_wlast;
wire s_axi_wvalid;
wire sum_A_0;
wire sum_A_1;
wire sum_A_2;
wire sum_A_3;
wire wr_addr_sm_cs;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED ;
wire [3:3]\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[0].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_3),
.Q(\Addr_Counters[0].FDRE_I_n_0 ),
.R(s_axi_aresetn));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* XILINX_TRANSFORM_PINMAP = "LO:O" *)
CARRY4 \Addr_Counters[0].MUXCY_L_I_CARRY4
(.CI(1'b0),
.CO({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED [3],addr_cy_1,addr_cy_2,addr_cy_3}),
.CYINIT(CI),
.DI({\NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED [3],\Addr_Counters[2].FDRE_I_n_0 ,\Addr_Counters[1].FDRE_I_n_0 ,\Addr_Counters[0].FDRE_I_n_0 }),
.O({sum_A_0,sum_A_1,sum_A_2,sum_A_3}),
.S({\Addr_Counters[3].XORCY_I_i_1_n_0 ,S0_out,S1_out,S}));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[0].MUXCY_L_I_i_1
(.I0(\Addr_Counters[1].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[0].FDRE_I_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h8AAAAAAAAAAAAAAA))
\Addr_Counters[0].MUXCY_L_I_i_2
(.I0(bram_addr_ld_en),
.I1(\axi_bid_int[0]_i_2_n_0 ),
.I2(\Addr_Counters[0].FDRE_I_n_0 ),
.I3(\Addr_Counters[1].FDRE_I_n_0 ),
.I4(\Addr_Counters[3].FDRE_I_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(CI));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[1].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_2),
.Q(\Addr_Counters[1].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[1].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[3].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[1].FDRE_I_n_0 ),
.O(S1_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[2].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_1),
.Q(\Addr_Counters[2].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[2].MUXCY_L_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[2].FDRE_I_n_0 ),
.O(S0_out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\Addr_Counters[3].FDRE_I
(.C(s_axi_aclk),
.CE(bid_fifo_not_empty),
.D(sum_A_0),
.Q(\Addr_Counters[3].FDRE_I_n_0 ),
.R(s_axi_aresetn));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\Addr_Counters[3].XORCY_I_i_1
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[2].FDRE_I_n_0 ),
.I3(bram_addr_ld_en),
.I4(\axi_bid_int[0]_i_2_n_0 ),
.I5(\Addr_Counters[3].FDRE_I_n_0 ),
.O(\Addr_Counters[3].XORCY_I_i_1_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
Data_Exists_DFF
(.C(s_axi_aclk),
.CE(1'b1),
.D(D),
.Q(bid_fifo_not_empty),
.R(s_axi_aresetn));
LUT4 #(
.INIT(16'hFE0A))
Data_Exists_DFF_i_1
(.I0(bram_addr_ld_en),
.I1(Data_Exists_DFF_i_2_n_0),
.I2(Data_Exists_DFF_i_3_n_0),
.I3(bid_fifo_not_empty),
.O(D));
LUT6 #(
.INIT(64'h000000000000FFFD))
Data_Exists_DFF_i_2
(.I0(bvalid_cnt_inc),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.I3(bvalid_cnt[1]),
.I4(bid_gets_fifo_load_d1_reg),
.I5(bid_gets_fifo_load_d1),
.O(Data_Exists_DFF_i_2_n_0));
LUT4 #(
.INIT(16'hFFFE))
Data_Exists_DFF_i_3
(.I0(\Addr_Counters[0].FDRE_I_n_0 ),
.I1(\Addr_Counters[1].FDRE_I_n_0 ),
.I2(\Addr_Counters[3].FDRE_I_n_0 ),
.I3(\Addr_Counters[2].FDRE_I_n_0 ),
.O(Data_Exists_DFF_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM " *)
(* srl_name = "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\FIFO_RAM[0].SRL16E_I
(.A0(\Addr_Counters[0].FDRE_I_n_0 ),
.A1(\Addr_Counters[1].FDRE_I_n_0 ),
.A2(\Addr_Counters[2].FDRE_I_n_0 ),
.A3(\Addr_Counters[3].FDRE_I_n_0 ),
.CE(CI),
.CLK(s_axi_aclk),
.D(bid_fifo_ld),
.Q(bid_fifo_rd));
LUT3 #(
.INIT(8'hB8))
\FIFO_RAM[0].SRL16E_I_i_1
(.I0(axi_awid_pipe),
.I1(axi_awaddr_full),
.I2(s_axi_awid),
.O(bid_fifo_ld));
LUT5 #(
.INIT(32'hACAFACA0))
\axi_bid_int[0]_i_1
(.I0(bid_fifo_ld),
.I1(bid_fifo_rd),
.I2(bid_gets_fifo_load),
.I3(\axi_bid_int[0]_i_2_n_0 ),
.I4(s_axi_bid),
.O(\axi_bid_int_reg[0] ));
LUT6 #(
.INIT(64'hA888AAAAA8888888))
\axi_bid_int[0]_i_2
(.I0(bid_fifo_not_empty),
.I1(bid_gets_fifo_load_d1),
.I2(s_axi_bready),
.I3(axi_bvalid_int_reg),
.I4(bid_gets_fifo_load_d1_i_3_n_0),
.I5(bvalid_cnt_inc),
.O(\axi_bid_int[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h000055FD00000000))
axi_bvalid_int_i_2
(.I0(out[2]),
.I1(axi_wdata_full_cmb114_out),
.I2(axi_bvalid_int_i_4_n_0),
.I3(axi_wr_burst),
.I4(out[1]),
.I5(axi_bvalid_int_i_5_n_0),
.O(bvalid_cnt_inc));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hFE000000))
axi_bvalid_int_i_3
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(axi_bvalid_int_reg),
.I4(s_axi_bready),
.O(bid_gets_fifo_load_d1_reg));
LUT6 #(
.INIT(64'h1F11000000000000))
axi_bvalid_int_i_4
(.I0(axi_bvalid_int_i_6_n_0),
.I1(\bvalid_cnt_reg[2] ),
.I2(wr_addr_sm_cs),
.I3(\bvalid_cnt_reg[2]_0 ),
.I4(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I5(axi_awaddr_full),
.O(axi_bvalid_int_i_4_n_0));
LUT5 #(
.INIT(32'h74446444))
axi_bvalid_int_i_5
(.I0(out[0]),
.I1(out[2]),
.I2(s_axi_wvalid),
.I3(s_axi_wlast),
.I4(axi_wdata_full_cmb114_out),
.O(axi_bvalid_int_i_5_n_0));
LUT5 #(
.INIT(32'hFEFFFFFF))
axi_bvalid_int_i_6
(.I0(curr_awlen_reg_1_or_2),
.I1(axi_awlen_pipe_1_or_2),
.I2(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I3(axi_awaddr_full),
.I4(last_data_ack_mod),
.O(axi_bvalid_int_i_6_n_0));
LUT6 #(
.INIT(64'h7F7F7F007F007F00))
axi_wready_int_mod_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[2]),
.I3(aw_active),
.I4(s_axi_awready),
.I5(s_axi_awvalid),
.O(axi_wdata_full_cmb114_out));
LUT6 #(
.INIT(64'h00000800AA00AA00))
bid_gets_fifo_load_d1_i_1
(.I0(bram_addr_ld_en),
.I1(bid_gets_fifo_load_d1_reg),
.I2(bid_fifo_not_empty),
.I3(bvalid_cnt_inc),
.I4(\bvalid_cnt_reg[1] ),
.I5(bid_gets_fifo_load_d1_i_3_n_0),
.O(bid_gets_fifo_load));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hFE))
bid_gets_fifo_load_d1_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(bid_gets_fifo_load_d1_i_3_n_0));
endmodule
(* C_BRAM_ADDR_WIDTH = "14" *) (* C_BRAM_INST_MODE = "EXTERNAL" *) (* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *) (* C_ECC_TYPE = "0" *) (* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *) (* C_MEMORY_DEPTH = "16384" *) (* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *) (* C_S_AXI_ADDR_WIDTH = "16" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_DATA_WIDTH = "32" *) (* C_S_AXI_ID_WIDTH = "1" *)
(* C_S_AXI_PROTOCOL = "AXI4" *) (* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
(s_axi_aclk,
s_axi_aresetn,
ecc_interrupt,
ecc_ue,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_ctrl_awvalid,
s_axi_ctrl_awready,
s_axi_ctrl_awaddr,
s_axi_ctrl_wdata,
s_axi_ctrl_wvalid,
s_axi_ctrl_wready,
s_axi_ctrl_bresp,
s_axi_ctrl_bvalid,
s_axi_ctrl_bready,
s_axi_ctrl_araddr,
s_axi_ctrl_arvalid,
s_axi_ctrl_arready,
s_axi_ctrl_rdata,
s_axi_ctrl_rresp,
s_axi_ctrl_rvalid,
s_axi_ctrl_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
input s_axi_aclk;
input s_axi_aresetn;
output ecc_interrupt;
output ecc_ue;
input [0:0]s_axi_awid;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_ctrl_awvalid;
output s_axi_ctrl_awready;
input [31:0]s_axi_ctrl_awaddr;
input [31:0]s_axi_ctrl_wdata;
input s_axi_ctrl_wvalid;
output s_axi_ctrl_wready;
output [1:0]s_axi_ctrl_bresp;
output s_axi_ctrl_bvalid;
input s_axi_ctrl_bready;
input [31:0]s_axi_ctrl_araddr;
input s_axi_ctrl_arvalid;
output s_axi_ctrl_arready;
output [31:0]s_axi_ctrl_rdata;
output [1:0]s_axi_ctrl_rresp;
output s_axi_ctrl_rvalid;
input s_axi_ctrl_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
wire \<const0> ;
wire [15:2]\^bram_addr_a ;
wire [15:2]\^bram_addr_b ;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign bram_addr_a[15:2] = \^bram_addr_a [15:2];
assign bram_addr_a[1] = \<const0> ;
assign bram_addr_a[0] = \<const0> ;
assign bram_addr_b[15:2] = \^bram_addr_b [15:2];
assign bram_addr_b[1] = \<const0> ;
assign bram_addr_b[0] = \<const0> ;
assign bram_clk_a = s_axi_aclk;
assign bram_clk_b = s_axi_aclk;
assign bram_rst_b = bram_rst_a;
assign bram_we_b[3] = \<const0> ;
assign bram_we_b[2] = \<const0> ;
assign bram_we_b[1] = \<const0> ;
assign bram_we_b[0] = \<const0> ;
assign bram_wrdata_b[31] = \<const0> ;
assign bram_wrdata_b[30] = \<const0> ;
assign bram_wrdata_b[29] = \<const0> ;
assign bram_wrdata_b[28] = \<const0> ;
assign bram_wrdata_b[27] = \<const0> ;
assign bram_wrdata_b[26] = \<const0> ;
assign bram_wrdata_b[25] = \<const0> ;
assign bram_wrdata_b[24] = \<const0> ;
assign bram_wrdata_b[23] = \<const0> ;
assign bram_wrdata_b[22] = \<const0> ;
assign bram_wrdata_b[21] = \<const0> ;
assign bram_wrdata_b[20] = \<const0> ;
assign bram_wrdata_b[19] = \<const0> ;
assign bram_wrdata_b[18] = \<const0> ;
assign bram_wrdata_b[17] = \<const0> ;
assign bram_wrdata_b[16] = \<const0> ;
assign bram_wrdata_b[15] = \<const0> ;
assign bram_wrdata_b[14] = \<const0> ;
assign bram_wrdata_b[13] = \<const0> ;
assign bram_wrdata_b[12] = \<const0> ;
assign bram_wrdata_b[11] = \<const0> ;
assign bram_wrdata_b[10] = \<const0> ;
assign bram_wrdata_b[9] = \<const0> ;
assign bram_wrdata_b[8] = \<const0> ;
assign bram_wrdata_b[7] = \<const0> ;
assign bram_wrdata_b[6] = \<const0> ;
assign bram_wrdata_b[5] = \<const0> ;
assign bram_wrdata_b[4] = \<const0> ;
assign bram_wrdata_b[3] = \<const0> ;
assign bram_wrdata_b[2] = \<const0> ;
assign bram_wrdata_b[1] = \<const0> ;
assign bram_wrdata_b[0] = \<const0> ;
assign ecc_interrupt = \<const0> ;
assign ecc_ue = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_ctrl_arready = \<const0> ;
assign s_axi_ctrl_awready = \<const0> ;
assign s_axi_ctrl_bresp[1] = \<const0> ;
assign s_axi_ctrl_bresp[0] = \<const0> ;
assign s_axi_ctrl_bvalid = \<const0> ;
assign s_axi_ctrl_rdata[31] = \<const0> ;
assign s_axi_ctrl_rdata[30] = \<const0> ;
assign s_axi_ctrl_rdata[29] = \<const0> ;
assign s_axi_ctrl_rdata[28] = \<const0> ;
assign s_axi_ctrl_rdata[27] = \<const0> ;
assign s_axi_ctrl_rdata[26] = \<const0> ;
assign s_axi_ctrl_rdata[25] = \<const0> ;
assign s_axi_ctrl_rdata[24] = \<const0> ;
assign s_axi_ctrl_rdata[23] = \<const0> ;
assign s_axi_ctrl_rdata[22] = \<const0> ;
assign s_axi_ctrl_rdata[21] = \<const0> ;
assign s_axi_ctrl_rdata[20] = \<const0> ;
assign s_axi_ctrl_rdata[19] = \<const0> ;
assign s_axi_ctrl_rdata[18] = \<const0> ;
assign s_axi_ctrl_rdata[17] = \<const0> ;
assign s_axi_ctrl_rdata[16] = \<const0> ;
assign s_axi_ctrl_rdata[15] = \<const0> ;
assign s_axi_ctrl_rdata[14] = \<const0> ;
assign s_axi_ctrl_rdata[13] = \<const0> ;
assign s_axi_ctrl_rdata[12] = \<const0> ;
assign s_axi_ctrl_rdata[11] = \<const0> ;
assign s_axi_ctrl_rdata[10] = \<const0> ;
assign s_axi_ctrl_rdata[9] = \<const0> ;
assign s_axi_ctrl_rdata[8] = \<const0> ;
assign s_axi_ctrl_rdata[7] = \<const0> ;
assign s_axi_ctrl_rdata[6] = \<const0> ;
assign s_axi_ctrl_rdata[5] = \<const0> ;
assign s_axi_ctrl_rdata[4] = \<const0> ;
assign s_axi_ctrl_rdata[3] = \<const0> ;
assign s_axi_ctrl_rdata[2] = \<const0> ;
assign s_axi_ctrl_rdata[1] = \<const0> ;
assign s_axi_ctrl_rdata[0] = \<const0> ;
assign s_axi_ctrl_rresp[1] = \<const0> ;
assign s_axi_ctrl_rresp[0] = \<const0> ;
assign s_axi_ctrl_rvalid = \<const0> ;
assign s_axi_ctrl_wready = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top \gext_inst.abcv4_0_ext_inst
(.bram_addr_a(\^bram_addr_a ),
.bram_addr_b(\^bram_addr_b ),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[15:2]),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[15:2]),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
s_axi_bid,
s_axi_rid,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output [0:0]s_axi_bid;
output [0:0]s_axi_rid;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [0:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [0:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi \GEN_AXI4.I_FULL_AXI
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
(s_axi_rvalid,
s_axi_rlast,
s_axi_bvalid,
s_axi_awready,
bram_rst_a,
bram_addr_a,
bram_en_a,
bram_we_a,
bram_wrdata_a,
bram_addr_b,
s_axi_rdata,
s_axi_wready,
s_axi_arready,
s_axi_bid,
s_axi_rid,
bram_en_b,
s_axi_aresetn,
s_axi_wvalid,
s_axi_wlast,
s_axi_rready,
s_axi_bready,
s_axi_awburst,
s_axi_aclk,
s_axi_awlen,
s_axi_awaddr,
s_axi_awid,
s_axi_wstrb,
s_axi_wdata,
s_axi_arlen,
s_axi_araddr,
s_axi_arid,
bram_rddata_b,
s_axi_arburst,
s_axi_awvalid,
s_axi_arvalid);
output s_axi_rvalid;
output s_axi_rlast;
output s_axi_bvalid;
output s_axi_awready;
output bram_rst_a;
output [13:0]bram_addr_a;
output bram_en_a;
output [3:0]bram_we_a;
output [31:0]bram_wrdata_a;
output [13:0]bram_addr_b;
output [31:0]s_axi_rdata;
output s_axi_wready;
output s_axi_arready;
output [0:0]s_axi_bid;
output [0:0]s_axi_rid;
output bram_en_b;
input s_axi_aresetn;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_rready;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_aclk;
input [7:0]s_axi_awlen;
input [13:0]s_axi_awaddr;
input [0:0]s_axi_awid;
input [3:0]s_axi_wstrb;
input [31:0]s_axi_wdata;
input [7:0]s_axi_arlen;
input [13:0]s_axi_araddr;
input [0:0]s_axi_arid;
input [31:0]bram_rddata_b;
input [1:0]s_axi_arburst;
input s_axi_awvalid;
input s_axi_arvalid;
wire I_WR_CHNL_n_36;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire [13:0]bram_addr_a;
wire [13:0]bram_addr_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl I_RD_CHNL
(.\GEN_AWREADY.axi_aresetn_d2_reg (I_WR_CHNL_n_36),
.Q(bram_addr_b),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_en_b(bram_en_b),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl I_WR_CHNL
(.\GEN_AW_DUAL.aw_active_reg_0 (I_WR_CHNL_n_36),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_aresetn_re_reg(axi_aresetn_re_reg),
.bram_addr_a(bram_addr_a),
.bram_en_a(bram_en_a),
.bram_we_a(bram_we_a),
.bram_wrdata_a(bram_wrdata_a),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(bram_rst_a),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
(bram_rst_a,
s_axi_rdata,
s_axi_rlast,
s_axi_rvalid,
s_axi_rid,
bram_en_b,
Q,
s_axi_arready,
s_axi_araddr,
s_axi_aclk,
s_axi_arid,
\GEN_AWREADY.axi_aresetn_d2_reg ,
s_axi_aresetn,
s_axi_rready,
s_axi_arlen,
axi_aresetn_d2,
s_axi_arvalid,
axi_aresetn_re_reg,
s_axi_arburst,
bram_rddata_b);
output bram_rst_a;
output [31:0]s_axi_rdata;
output s_axi_rlast;
output s_axi_rvalid;
output [0:0]s_axi_rid;
output bram_en_b;
output [13:0]Q;
output s_axi_arready;
input [13:0]s_axi_araddr;
input s_axi_aclk;
input [0:0]s_axi_arid;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input s_axi_aresetn;
input s_axi_rready;
input [7:0]s_axi_arlen;
input axi_aresetn_d2;
input s_axi_arvalid;
input axi_aresetn_re_reg;
input [1:0]s_axi_arburst;
input [31:0]bram_rddata_b;
wire \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ;
wire \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ;
wire \/i__n_0 ;
wire \FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ;
wire \GEN_ARREADY.axi_arready_int_i_1_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_2_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_3_n_0 ;
wire \GEN_ARREADY.axi_early_arready_int_i_4_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_1_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_2_n_0 ;
wire \GEN_AR_DUAL.ar_active_i_3_n_0 ;
wire \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ;
wire \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ;
wire \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_int[0]_i_2_n_0 ;
wire \GEN_RID.axi_rid_temp2[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_full_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp2_reg_n_0_[0] ;
wire \GEN_RID.axi_rid_temp[0]_i_1_n_0 ;
wire \GEN_RID.axi_rid_temp[0]_i_3_n_0 ;
wire \GEN_RID.axi_rid_temp_full_i_1_n_0 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_18;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_26;
wire I_WRAP_BRST_n_27;
wire I_WRAP_BRST_n_3;
wire I_WRAP_BRST_n_4;
wire I_WRAP_BRST_n_5;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire [13:0]Q;
wire act_rd_burst;
wire act_rd_burst_i_1_n_0;
wire act_rd_burst_i_3_n_0;
wire act_rd_burst_i_4_n_0;
wire act_rd_burst_i_5_n_0;
wire act_rd_burst_set;
wire act_rd_burst_two;
wire act_rd_burst_two_i_1_n_0;
wire ar_active;
wire araddr_pipe_ld43_out;
wire axi_araddr_full;
wire [1:0]axi_arburst_pipe;
wire axi_aresetn_d2;
wire axi_aresetn_re_reg;
wire axi_arid_pipe;
wire [7:0]axi_arlen_pipe;
wire axi_arlen_pipe_1_or_2;
wire axi_arready_int;
wire [1:1]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_arsize_pipe_max_i_1_n_0;
wire axi_b2b_brst;
wire axi_b2b_brst_i_1_n_0;
wire axi_b2b_brst_i_2_n_0;
wire axi_early_arready_int;
wire axi_rd_burst;
wire axi_rd_burst_i_1_n_0;
wire axi_rd_burst_i_2_n_0;
wire axi_rd_burst_i_3_n_0;
wire axi_rd_burst_two;
wire axi_rd_burst_two_i_1_n_0;
wire axi_rd_burst_two_reg_n_0;
wire axi_rid_temp;
wire axi_rid_temp2;
wire axi_rid_temp2_full;
wire axi_rid_temp_full;
wire axi_rid_temp_full_d1;
wire axi_rlast_int_i_1_n_0;
wire axi_rlast_set;
wire axi_rvalid_clr_ok;
wire axi_rvalid_clr_ok_i_1_n_0;
wire axi_rvalid_clr_ok_i_2_n_0;
wire axi_rvalid_clr_ok_i_3_n_0;
wire axi_rvalid_int_i_1_n_0;
wire axi_rvalid_set;
wire axi_rvalid_set_cmb;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_en_b;
wire bram_en_int_i_10_n_0;
wire bram_en_int_i_11_n_0;
wire bram_en_int_i_12_n_0;
wire bram_en_int_i_13_n_0;
wire bram_en_int_i_1_n_0;
wire bram_en_int_i_2_n_0;
wire bram_en_int_i_3_n_0;
wire bram_en_int_i_4_n_0;
wire bram_en_int_i_5_n_0;
wire bram_en_int_i_6_n_0;
wire bram_en_int_i_7_n_0;
wire bram_en_int_i_9_n_0;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire [7:0]brst_cnt;
wire \brst_cnt[0]_i_1_n_0 ;
wire \brst_cnt[1]_i_1_n_0 ;
wire \brst_cnt[2]_i_1_n_0 ;
wire \brst_cnt[3]_i_1_n_0 ;
wire \brst_cnt[4]_i_1_n_0 ;
wire \brst_cnt[4]_i_2_n_0 ;
wire \brst_cnt[5]_i_1_n_0 ;
wire \brst_cnt[6]_i_1_n_0 ;
wire \brst_cnt[6]_i_2_n_0 ;
wire \brst_cnt[7]_i_1_n_0 ;
wire \brst_cnt[7]_i_2_n_0 ;
wire \brst_cnt[7]_i_3_n_0 ;
wire \brst_cnt[7]_i_4_n_0 ;
wire brst_cnt_max;
wire brst_cnt_max_d1;
wire brst_one;
wire brst_one_i_1_n_0;
wire brst_one_i_2_n_0;
wire brst_zero;
wire brst_zero_i_1_n_0;
wire brst_zero_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire disable_b2b_brst_cmb;
wire disable_b2b_brst_i_2_n_0;
wire disable_b2b_brst_i_3_n_0;
wire disable_b2b_brst_i_4_n_0;
wire end_brst_rd;
wire end_brst_rd_clr;
wire end_brst_rd_clr_i_1_n_0;
wire end_brst_rd_i_1_n_0;
wire last_bram_addr;
wire last_bram_addr0;
wire last_bram_addr_i_2_n_0;
wire last_bram_addr_i_3_n_0;
wire last_bram_addr_i_4_n_0;
wire last_bram_addr_i_5_n_0;
wire last_bram_addr_i_6_n_0;
wire last_bram_addr_i_7_n_0;
wire last_bram_addr_i_8_n_0;
wire last_bram_addr_i_9_n_0;
wire no_ar_ack;
wire no_ar_ack_i_1_n_0;
wire p_0_in13_in;
wire p_13_out;
wire p_48_out;
wire p_4_out;
wire p_9_out;
wire pend_rd_op;
wire pend_rd_op_i_1_n_0;
wire pend_rd_op_i_2_n_0;
wire pend_rd_op_i_3_n_0;
wire pend_rd_op_i_4_n_0;
wire pend_rd_op_i_5_n_0;
wire pend_rd_op_i_6_n_0;
wire pend_rd_op_i_7_n_0;
wire pend_rd_op_i_8_n_0;
wire rd_addr_sm_cs;
wire rd_adv_buf67_out;
wire [3:0]rd_data_sm_cs;
wire \rd_data_sm_cs[0]_i_1_n_0 ;
wire \rd_data_sm_cs[0]_i_2_n_0 ;
wire \rd_data_sm_cs[0]_i_3_n_0 ;
wire \rd_data_sm_cs[0]_i_4_n_0 ;
wire \rd_data_sm_cs[1]_i_1_n_0 ;
wire \rd_data_sm_cs[1]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_1_n_0 ;
wire \rd_data_sm_cs[2]_i_2_n_0 ;
wire \rd_data_sm_cs[2]_i_3_n_0 ;
wire \rd_data_sm_cs[2]_i_4_n_0 ;
wire \rd_data_sm_cs[2]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_2_n_0 ;
wire \rd_data_sm_cs[3]_i_3_n_0 ;
wire \rd_data_sm_cs[3]_i_4_n_0 ;
wire \rd_data_sm_cs[3]_i_5_n_0 ;
wire \rd_data_sm_cs[3]_i_6_n_0 ;
wire \rd_data_sm_cs[3]_i_7_n_0 ;
wire rd_data_sm_ns;
wire [31:0]rd_skid_buf;
wire rd_skid_buf_ld;
wire rd_skid_buf_ld_cmb;
wire rd_skid_buf_ld_reg;
wire rddata_mux_sel;
wire rddata_mux_sel_cmb;
wire rddata_mux_sel_i_1_n_0;
wire rddata_mux_sel_i_3_n_0;
(* RTL_KEEP = "yes" *) wire [2:0]rlast_sm_cs;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire s_axi_arready;
wire s_axi_arvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire s_axi_rvalid;
LUT6 #(
.INIT(64'h0011001300130013))
\/FSM_sequential_rlast_sm_cs[0]_i_2
(.I0(axi_rd_burst),
.I1(rlast_sm_cs[1]),
.I2(act_rd_burst_two),
.I3(axi_rd_burst_two_reg_n_0),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h003F007F003F0055))
\/FSM_sequential_rlast_sm_cs[1]_i_2
(.I0(axi_rd_burst),
.I1(s_axi_rready),
.I2(s_axi_rvalid),
.I3(rlast_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_two),
.O(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF000F111F000E000))
\/i_
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[1]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rlast_sm_cs[0]),
.I5(last_bram_addr),
.O(\/i__n_0 ));
LUT6 #(
.INIT(64'h00008080000F8080))
\/i___0
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[1]),
.I4(rlast_sm_cs[2]),
.I5(s_axi_rlast),
.O(axi_rlast_set));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[0]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[0]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[0]),
.O(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h01FF0100))
\FSM_sequential_rlast_sm_cs[1]_i_1
(.I0(rlast_sm_cs[2]),
.I1(rlast_sm_cs[0]),
.I2(\/FSM_sequential_rlast_sm_cs[1]_i_2_n_0 ),
.I3(\/i__n_0 ),
.I4(rlast_sm_cs[1]),
.O(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00A4FFFF00A40000))
\FSM_sequential_rlast_sm_cs[2]_i_1
(.I0(rlast_sm_cs[1]),
.I1(p_0_in13_in),
.I2(rlast_sm_cs[0]),
.I3(rlast_sm_cs[2]),
.I4(\/i__n_0 ),
.I5(rlast_sm_cs[2]),
.O(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h1))
\FSM_sequential_rlast_sm_cs[2]_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst),
.O(p_0_in13_in));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[0]_i_1_n_0 ),
.Q(rlast_sm_cs[0]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[1]_i_1_n_0 ),
.Q(rlast_sm_cs[1]),
.R(bram_rst_a));
(* KEEP = "yes" *)
FDRE \FSM_sequential_rlast_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_rlast_sm_cs[2]_i_1_n_0 ),
.Q(rlast_sm_cs[2]),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hAAAAAEEE))
\GEN_ARREADY.axi_arready_int_i_1
(.I0(p_9_out),
.I1(axi_arready_int),
.I2(s_axi_arvalid),
.I3(axi_araddr_full),
.I4(araddr_pipe_ld43_out),
.O(\GEN_ARREADY.axi_arready_int_i_1_n_0 ));
LUT4 #(
.INIT(16'hBAAA))
\GEN_ARREADY.axi_arready_int_i_2
(.I0(axi_aresetn_re_reg),
.I1(axi_early_arready_int),
.I2(axi_araddr_full),
.I3(bram_addr_ld_en),
.O(p_9_out));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_ARREADY.axi_arready_int_i_1_n_0 ),
.Q(axi_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h0000000000000200))
\GEN_ARREADY.axi_early_arready_int_i_1
(.I0(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ),
.I1(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ),
.I2(rd_data_sm_cs[3]),
.I3(brst_one),
.I4(axi_arready_int),
.I5(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.O(p_48_out));
LUT6 #(
.INIT(64'h03C4000400C40004))
\GEN_ARREADY.axi_early_arready_int_i_2
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(rd_adv_buf67_out),
.I5(bram_en_int_i_9_n_0),
.O(\GEN_ARREADY.axi_early_arready_int_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h7))
\GEN_ARREADY.axi_early_arready_int_i_3
(.I0(axi_araddr_full),
.I1(s_axi_arvalid),
.O(\GEN_ARREADY.axi_early_arready_int_i_3_n_0 ));
LUT6 #(
.INIT(64'hAAEAAAEAFFFFAAEA))
\GEN_ARREADY.axi_early_arready_int_i_4
(.I0(I_WRAP_BRST_n_27),
.I1(\rd_data_sm_cs[3]_i_6_n_0 ),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(brst_zero),
.I5(rd_adv_buf67_out),
.O(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_ARREADY.axi_early_arready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_48_out),
.Q(axi_early_arready_int),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0FBFBFBF0F0F0F0))
\GEN_AR_DUAL.ar_active_i_1
(.I0(\GEN_AR_DUAL.ar_active_i_2_n_0 ),
.I1(\rd_data_sm_cs[2]_i_3_n_0 ),
.I2(bram_addr_ld_en),
.I3(\rd_data_sm_cs[2]_i_5_n_0 ),
.I4(rd_adv_buf67_out),
.I5(ar_active),
.O(\GEN_AR_DUAL.ar_active_i_1_n_0 ));
LUT6 #(
.INIT(64'hB0FFBFFFB0FFBF0F))
\GEN_AR_DUAL.ar_active_i_2
(.I0(\GEN_AR_DUAL.ar_active_i_3_n_0 ),
.I1(I_WRAP_BRST_n_27),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[1]),
.I4(axi_rd_burst_two_reg_n_0),
.I5(axi_rd_burst),
.O(\GEN_AR_DUAL.ar_active_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h0DFFFFFF))
\GEN_AR_DUAL.ar_active_i_3
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(\GEN_AR_DUAL.ar_active_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_DUAL.ar_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.ar_active_i_1_n_0 ),
.Q(ar_active),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
LUT6 #(
.INIT(64'h10001000F0F01000))
\GEN_AR_DUAL.rd_addr_sm_cs_i_1
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I4(last_bram_addr),
.I5(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.O(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ));
FDRE \GEN_AR_DUAL.rd_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0 ),
.Q(rd_addr_sm_cs),
.R(\GEN_AWREADY.axi_aresetn_d2_reg ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[8]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[9]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[10]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[11]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[12]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[13]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[0]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[1]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[2]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[3]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[4]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[5]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[6]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_araddr[7]),
.Q(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.R(1'b0));
LUT6 #(
.INIT(64'h00C08888CCCC8888))
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1
(.I0(araddr_pipe_ld43_out),
.I1(s_axi_aresetn),
.I2(s_axi_arvalid),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I4(axi_araddr_full),
.I5(bram_addr_ld_en),
.O(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0 ),
.Q(axi_araddr_full),
.R(1'b0));
LUT4 #(
.INIT(16'h03AA))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.I1(s_axi_arburst[0]),
.I2(s_axi_arburst[1]),
.I3(araddr_pipe_ld43_out),
.O(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[0]),
.Q(axi_arburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arburst[1]),
.Q(axi_arburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arid),
.Q(axi_arid_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h220022002A002200))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1
(.I0(axi_aresetn_d2),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ),
.I2(rd_addr_sm_cs),
.I3(s_axi_arvalid),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ),
.I5(axi_araddr_full),
.O(araddr_pipe_ld43_out));
LUT6 #(
.INIT(64'hFFFFFF70FFFFFFFF))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(brst_zero),
.I3(I_WRAP_BRST_n_26),
.I4(I_WRAP_BRST_n_27),
.I5(last_bram_addr),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3
(.I0(no_ar_ack),
.I1(pend_rd_op),
.I2(ar_active),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1
(.I0(s_axi_arlen[1]),
.I1(s_axi_arlen[7]),
.I2(s_axi_arlen[4]),
.I3(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ),
.O(p_13_out));
LUT4 #(
.INIT(16'hFFFE))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2
(.I0(s_axi_arlen[6]),
.I1(s_axi_arlen[2]),
.I2(s_axi_arlen[5]),
.I3(s_axi_arlen[3]),
.O(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(p_13_out),
.Q(axi_arlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[0]),
.Q(axi_arlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[1]),
.Q(axi_arlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[2]),
.Q(axi_arlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[3]),
.Q(axi_arlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[4]),
.Q(axi_arlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[5]),
.Q(axi_arlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[6]),
.Q(axi_arlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(s_axi_arlen[7]),
.Q(axi_arlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(araddr_pipe_ld43_out),
.D(1'b1),
.Q(axi_arsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000BAAA0000))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1
(.I0(brst_cnt_max),
.I1(pend_rd_op),
.I2(ar_active),
.I3(brst_zero),
.I4(s_axi_aresetn),
.I5(bram_addr_ld_en),
.O(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0 ),
.Q(brst_cnt_max),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2
(.I0(Q[4]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[3]),
.I5(Q[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4
(.I0(Q[6]),
.I1(Q[4]),
.I2(I_WRAP_BRST_n_24),
.I3(Q[5]),
.I4(Q[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_14),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_13),
.Q(Q[9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_12),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_11),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_10),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(I_WRAP_BRST_n_9),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_22),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_21),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_20),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_19),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_18),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_17),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_16),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_7),
.D(I_WRAP_BRST_n_15),
.Q(Q[7]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1
(.I0(rd_skid_buf[0]),
.I1(bram_rddata_b[0]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0 ),
.Q(s_axi_rdata[0]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1
(.I0(rd_skid_buf[10]),
.I1(bram_rddata_b[10]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0 ),
.Q(s_axi_rdata[10]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1
(.I0(rd_skid_buf[11]),
.I1(bram_rddata_b[11]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0 ),
.Q(s_axi_rdata[11]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1
(.I0(rd_skid_buf[12]),
.I1(bram_rddata_b[12]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0 ),
.Q(s_axi_rdata[12]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1
(.I0(rd_skid_buf[13]),
.I1(bram_rddata_b[13]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0 ),
.Q(s_axi_rdata[13]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1
(.I0(rd_skid_buf[14]),
.I1(bram_rddata_b[14]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0 ),
.Q(s_axi_rdata[14]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1
(.I0(rd_skid_buf[15]),
.I1(bram_rddata_b[15]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0 ),
.Q(s_axi_rdata[15]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1
(.I0(rd_skid_buf[16]),
.I1(bram_rddata_b[16]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0 ),
.Q(s_axi_rdata[16]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1
(.I0(rd_skid_buf[17]),
.I1(bram_rddata_b[17]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0 ),
.Q(s_axi_rdata[17]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1
(.I0(rd_skid_buf[18]),
.I1(bram_rddata_b[18]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0 ),
.Q(s_axi_rdata[18]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1
(.I0(rd_skid_buf[19]),
.I1(bram_rddata_b[19]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0 ),
.Q(s_axi_rdata[19]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1
(.I0(rd_skid_buf[1]),
.I1(bram_rddata_b[1]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0 ),
.Q(s_axi_rdata[1]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1
(.I0(rd_skid_buf[20]),
.I1(bram_rddata_b[20]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0 ),
.Q(s_axi_rdata[20]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1
(.I0(rd_skid_buf[21]),
.I1(bram_rddata_b[21]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0 ),
.Q(s_axi_rdata[21]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1
(.I0(rd_skid_buf[22]),
.I1(bram_rddata_b[22]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0 ),
.Q(s_axi_rdata[22]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1
(.I0(rd_skid_buf[23]),
.I1(bram_rddata_b[23]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0 ),
.Q(s_axi_rdata[23]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1
(.I0(rd_skid_buf[24]),
.I1(bram_rddata_b[24]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0 ),
.Q(s_axi_rdata[24]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1
(.I0(rd_skid_buf[25]),
.I1(bram_rddata_b[25]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0 ),
.Q(s_axi_rdata[25]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1
(.I0(rd_skid_buf[26]),
.I1(bram_rddata_b[26]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0 ),
.Q(s_axi_rdata[26]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1
(.I0(rd_skid_buf[27]),
.I1(bram_rddata_b[27]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0 ),
.Q(s_axi_rdata[27]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1
(.I0(rd_skid_buf[28]),
.I1(bram_rddata_b[28]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0 ),
.Q(s_axi_rdata[28]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1
(.I0(rd_skid_buf[29]),
.I1(bram_rddata_b[29]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0 ),
.Q(s_axi_rdata[29]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1
(.I0(rd_skid_buf[2]),
.I1(bram_rddata_b[2]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0 ),
.Q(s_axi_rdata[2]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1
(.I0(rd_skid_buf[30]),
.I1(bram_rddata_b[30]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0 ),
.Q(s_axi_rdata[30]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT4 #(
.INIT(16'h08FF))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.I2(axi_b2b_brst),
.I3(s_axi_aresetn),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1414545410000404))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3
(.I0(rd_skid_buf[31]),
.I1(bram_rddata_b[31]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ));
LUT2 #(
.INIT(4'h1))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.O(rd_adv_buf67_out));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0 ),
.Q(s_axi_rdata[31]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1
(.I0(rd_skid_buf[3]),
.I1(bram_rddata_b[3]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0 ),
.Q(s_axi_rdata[3]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1
(.I0(rd_skid_buf[4]),
.I1(bram_rddata_b[4]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0 ),
.Q(s_axi_rdata[4]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1
(.I0(rd_skid_buf[5]),
.I1(bram_rddata_b[5]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0 ),
.Q(s_axi_rdata[5]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1
(.I0(rd_skid_buf[6]),
.I1(bram_rddata_b[6]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0 ),
.Q(s_axi_rdata[6]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1
(.I0(rd_skid_buf[7]),
.I1(bram_rddata_b[7]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0 ),
.Q(s_axi_rdata[7]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1
(.I0(rd_skid_buf[8]),
.I1(bram_rddata_b[8]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0 ),
.Q(s_axi_rdata[8]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1
(.I0(rd_skid_buf[9]),
.I1(bram_rddata_b[9]),
.I2(rddata_mux_sel),
.O(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0 ),
.D(\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0 ),
.Q(s_axi_rdata[9]),
.R(\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAAABAAAAAA))
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1
(.I0(rd_skid_buf_ld_reg),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[3]),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[2]),
.I5(rd_data_sm_cs[0]),
.O(rd_skid_buf_ld));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[0]),
.Q(rd_skid_buf[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[10]),
.Q(rd_skid_buf[10]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[11]),
.Q(rd_skid_buf[11]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[12]),
.Q(rd_skid_buf[12]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[13]),
.Q(rd_skid_buf[13]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[14]),
.Q(rd_skid_buf[14]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[15]),
.Q(rd_skid_buf[15]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[16]),
.Q(rd_skid_buf[16]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[17]),
.Q(rd_skid_buf[17]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[18]),
.Q(rd_skid_buf[18]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[19]),
.Q(rd_skid_buf[19]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[1]),
.Q(rd_skid_buf[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[20]),
.Q(rd_skid_buf[20]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[21]),
.Q(rd_skid_buf[21]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[22]),
.Q(rd_skid_buf[22]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[23]),
.Q(rd_skid_buf[23]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[24]),
.Q(rd_skid_buf[24]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[25]),
.Q(rd_skid_buf[25]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[26]),
.Q(rd_skid_buf[26]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[27]),
.Q(rd_skid_buf[27]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[28]),
.Q(rd_skid_buf[28]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[29]),
.Q(rd_skid_buf[29]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[2]),
.Q(rd_skid_buf[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[30]),
.Q(rd_skid_buf[30]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[31]),
.Q(rd_skid_buf[31]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[3]),
.Q(rd_skid_buf[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[4]),
.Q(rd_skid_buf[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[5]),
.Q(rd_skid_buf[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[6]),
.Q(rd_skid_buf[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[7]),
.Q(rd_skid_buf[7]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[8]),
.Q(rd_skid_buf[8]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]
(.C(s_axi_aclk),
.CE(rd_skid_buf_ld),
.D(bram_rddata_b[9]),
.Q(rd_skid_buf[9]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hE200E200F0000000))
\GEN_RID.axi_rid_int[0]_i_1
(.I0(s_axi_rid),
.I1(axi_rvalid_set),
.I2(axi_rid_temp),
.I3(s_axi_aresetn),
.I4(axi_b2b_brst),
.I5(\GEN_RID.axi_rid_int[0]_i_2_n_0 ),
.O(\GEN_RID.axi_rid_int[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h7))
\GEN_RID.axi_rid_int[0]_i_2
(.I0(s_axi_rready),
.I1(s_axi_rlast),
.O(\GEN_RID.axi_rid_int[0]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_int[0]_i_1_n_0 ),
.Q(s_axi_rid),
.R(1'b0));
LUT6 #(
.INIT(64'hB8FFFFFFB8000000))
\GEN_RID.axi_rid_temp2[0]_i_1
(.I0(axi_arid_pipe),
.I1(axi_araddr_full),
.I2(s_axi_arid),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.I5(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.O(\GEN_RID.axi_rid_temp2[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h08080000C8C800C0))
\GEN_RID.axi_rid_temp2_full_i_1
(.I0(bram_addr_ld_en),
.I1(s_axi_aresetn),
.I2(axi_rid_temp2_full),
.I3(axi_rid_temp_full_d1),
.I4(axi_rid_temp_full),
.I5(p_4_out),
.O(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2_full_i_1_n_0 ),
.Q(axi_rid_temp2_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp2_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp2[0]_i_1_n_0 ),
.Q(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hCFAACFCFC0AAC0C0))
\GEN_RID.axi_rid_temp[0]_i_1
(.I0(axi_rid_temp2),
.I1(\GEN_RID.axi_rid_temp2_reg_n_0_[0] ),
.I2(\GEN_RID.axi_rid_temp[0]_i_3_n_0 ),
.I3(axi_rid_temp_full),
.I4(bram_addr_ld_en),
.I5(axi_rid_temp),
.O(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\GEN_RID.axi_rid_temp[0]_i_2
(.I0(axi_arid_pipe),
.I1(axi_araddr_full),
.I2(s_axi_arid),
.O(axi_rid_temp2));
LUT6 #(
.INIT(64'hAA08AAAAAA08AA08))
\GEN_RID.axi_rid_temp[0]_i_3
(.I0(axi_rid_temp2_full),
.I1(axi_rid_temp_full_d1),
.I2(axi_rid_temp_full),
.I3(axi_rvalid_set),
.I4(\GEN_RID.axi_rid_int[0]_i_2_n_0 ),
.I5(axi_b2b_brst),
.O(\GEN_RID.axi_rid_temp[0]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rid_temp_full),
.Q(axi_rid_temp_full_d1),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF0F0F0E000F0A0A0))
\GEN_RID.axi_rid_temp_full_i_1
(.I0(bram_addr_ld_en),
.I1(axi_rid_temp_full_d1),
.I2(s_axi_aresetn),
.I3(p_4_out),
.I4(axi_rid_temp_full),
.I5(axi_rid_temp2_full),
.O(\GEN_RID.axi_rid_temp_full_i_1_n_0 ));
LUT4 #(
.INIT(16'hEAAA))
\GEN_RID.axi_rid_temp_full_i_2
(.I0(axi_rvalid_set),
.I1(s_axi_rready),
.I2(s_axi_rlast),
.I3(axi_b2b_brst),
.O(p_4_out));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp_full_i_1_n_0 ),
.Q(axi_rid_temp_full),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_RID.axi_rid_temp_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_RID.axi_rid_temp[0]_i_1_n_0 ),
.Q(axi_rid_temp),
.R(bram_rst_a));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 I_WRAP_BRST
(.D({I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16,I_WRAP_BRST_n_17,I_WRAP_BRST_n_18,I_WRAP_BRST_n_19,I_WRAP_BRST_n_20,I_WRAP_BRST_n_21,I_WRAP_BRST_n_22}),
.E({bram_addr_ld_en_mod,I_WRAP_BRST_n_7}),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg (\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg (\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0 ),
.\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] (axi_arlen_pipe[3:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] (I_WRAP_BRST_n_0),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 (I_WRAP_BRST_n_8),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 (Q[9:0]),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (I_WRAP_BRST_n_24),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0 ),
.Q(rd_data_sm_cs),
.SR(bram_rst_a),
.ar_active(ar_active),
.axi_araddr_full(axi_araddr_full),
.axi_aresetn_d2(axi_aresetn_d2),
.axi_arlen_pipe_1_or_2(axi_arlen_pipe_1_or_2),
.axi_arsize_pipe(axi_arsize_pipe),
.axi_arsize_pipe_max(axi_arsize_pipe_max),
.axi_b2b_brst(axi_b2b_brst),
.axi_rd_burst(axi_rd_burst),
.axi_rd_burst_two_reg(axi_rd_burst_two_reg_n_0),
.axi_rvalid_int_reg(s_axi_rvalid),
.bram_addr_ld_en(bram_addr_ld_en),
.brst_zero(brst_zero),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.disable_b2b_brst(disable_b2b_brst),
.end_brst_rd(end_brst_rd),
.last_bram_addr(last_bram_addr),
.no_ar_ack(no_ar_ack),
.pend_rd_op(pend_rd_op),
.rd_addr_sm_cs(rd_addr_sm_cs),
.\rd_data_sm_cs_reg[1] (I_WRAP_BRST_n_25),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arlen(s_axi_arlen[3:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rready(s_axi_rready),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_26),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_27),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_2),
.\wrap_burst_total_reg[0]_1 (I_WRAP_BRST_n_3),
.\wrap_burst_total_reg[0]_2 (I_WRAP_BRST_n_4),
.\wrap_burst_total_reg[0]_3 (I_WRAP_BRST_n_5));
LUT6 #(
.INIT(64'h000000002EEE22E2))
act_rd_burst_i_1
(.I0(act_rd_burst),
.I1(act_rd_burst_set),
.I2(bram_addr_ld_en),
.I3(axi_rd_burst_two),
.I4(axi_rd_burst),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'hA8A888A888888888))
act_rd_burst_i_2
(.I0(\rd_data_sm_cs[2]_i_3_n_0 ),
.I1(act_rd_burst_i_4_n_0),
.I2(act_rd_burst_i_5_n_0),
.I3(axi_rd_burst_i_2_n_0),
.I4(I_WRAP_BRST_n_4),
.I5(bram_addr_ld_en),
.O(act_rd_burst_set));
LUT6 #(
.INIT(64'h20000040FFFFFFFF))
act_rd_burst_i_3
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(\rd_data_sm_cs[3]_i_7_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(s_axi_aresetn),
.O(act_rd_burst_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h5500FC00))
act_rd_burst_i_4
(.I0(bram_en_int_i_12_n_0),
.I1(axi_rd_burst_two_reg_n_0),
.I2(axi_rd_burst),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[1]),
.O(act_rd_burst_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h1))
act_rd_burst_i_5
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(act_rd_burst_i_5_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_i_1_n_0),
.Q(act_rd_burst),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000E2EEE222))
act_rd_burst_two_i_1
(.I0(act_rd_burst_two),
.I1(act_rd_burst_set),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(axi_rd_burst_two_reg_n_0),
.I5(act_rd_burst_i_3_n_0),
.O(act_rd_burst_two_i_1_n_0));
FDRE #(
.INIT(1'b0))
act_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(act_rd_burst_two_i_1_n_0),
.Q(act_rd_burst_two),
.R(1'b0));
LUT2 #(
.INIT(4'hE))
axi_arsize_pipe_max_i_1
(.I0(araddr_pipe_ld43_out),
.I1(axi_arsize_pipe_max),
.O(axi_arsize_pipe_max_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_arsize_pipe_max_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_arsize_pipe_max_i_1_n_0),
.Q(axi_arsize_pipe_max),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hF000F074F0F0F074))
axi_b2b_brst_i_1
(.I0(I_WRAP_BRST_n_27),
.I1(axi_b2b_brst_i_2_n_0),
.I2(axi_b2b_brst),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(disable_b2b_brst_i_2_n_0),
.O(axi_b2b_brst_i_1_n_0));
LUT6 #(
.INIT(64'h00000000AA080000))
axi_b2b_brst_i_2
(.I0(\rd_data_sm_cs[0]_i_3_n_0 ),
.I1(end_brst_rd),
.I2(axi_b2b_brst),
.I3(brst_zero),
.I4(rd_adv_buf67_out),
.I5(I_WRAP_BRST_n_27),
.O(axi_b2b_brst_i_2_n_0));
FDRE #(
.INIT(1'b0))
axi_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_b2b_brst_i_1_n_0),
.Q(axi_b2b_brst),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h303000A0))
axi_rd_burst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_i_1_n_0));
LUT6 #(
.INIT(64'h0000000001000111))
axi_rd_burst_i_2
(.I0(I_WRAP_BRST_n_2),
.I1(I_WRAP_BRST_n_5),
.I2(axi_arlen_pipe[1]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[1]),
.I5(axi_rd_burst_i_3_n_0),
.O(axi_rd_burst_i_2_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFBBFCB8))
axi_rd_burst_i_3
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(axi_arlen_pipe[4]),
.I4(s_axi_arlen[4]),
.I5(last_bram_addr_i_9_n_0),
.O(axi_rd_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rd_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_i_1_n_0),
.Q(axi_rd_burst),
.R(1'b0));
LUT5 #(
.INIT(32'hC0C000A0))
axi_rd_burst_two_i_1
(.I0(axi_rd_burst_two_reg_n_0),
.I1(axi_rd_burst_two),
.I2(s_axi_aresetn),
.I3(brst_zero),
.I4(bram_addr_ld_en),
.O(axi_rd_burst_two_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hA808))
axi_rd_burst_two_i_2
(.I0(axi_rd_burst_i_2_n_0),
.I1(s_axi_arlen[0]),
.I2(axi_araddr_full),
.I3(axi_arlen_pipe[0]),
.O(axi_rd_burst_two));
FDRE #(
.INIT(1'b0))
axi_rd_burst_two_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rd_burst_two_i_1_n_0),
.Q(axi_rd_burst_two_reg_n_0),
.R(1'b0));
LUT4 #(
.INIT(16'h88A8))
axi_rlast_int_i_1
(.I0(s_axi_aresetn),
.I1(axi_rlast_set),
.I2(s_axi_rlast),
.I3(s_axi_rready),
.O(axi_rlast_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rlast_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rlast_int_i_1_n_0),
.Q(s_axi_rlast),
.R(1'b0));
LUT6 #(
.INIT(64'h00000000FFFFEEEA))
axi_rvalid_clr_ok_i_1
(.I0(axi_rvalid_clr_ok),
.I1(last_bram_addr),
.I2(disable_b2b_brst),
.I3(disable_b2b_brst_cmb),
.I4(axi_rvalid_clr_ok_i_2_n_0),
.I5(axi_rvalid_clr_ok_i_3_n_0),
.O(axi_rvalid_clr_ok_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hAAAAAEAA))
axi_rvalid_clr_ok_i_2
(.I0(bram_addr_ld_en),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.O(axi_rvalid_clr_ok_i_2_n_0));
LUT3 #(
.INIT(8'h4F))
axi_rvalid_clr_ok_i_3
(.I0(\GEN_ARREADY.axi_early_arready_int_i_4_n_0 ),
.I1(bram_addr_ld_en),
.I2(s_axi_aresetn),
.O(axi_rvalid_clr_ok_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_clr_ok_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_clr_ok_i_1_n_0),
.Q(axi_rvalid_clr_ok),
.R(1'b0));
LUT6 #(
.INIT(64'h00E0E0E0E0E0E0E0))
axi_rvalid_int_i_1
(.I0(s_axi_rvalid),
.I1(axi_rvalid_set),
.I2(s_axi_aresetn),
.I3(axi_rvalid_clr_ok),
.I4(s_axi_rlast),
.I5(s_axi_rready),
.O(axi_rvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_rvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_int_i_1_n_0),
.Q(s_axi_rvalid),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0100))
axi_rvalid_set_i_1
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.O(axi_rvalid_set_cmb));
FDRE #(
.INIT(1'b0))
axi_rvalid_set_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_rvalid_set_cmb),
.Q(axi_rvalid_set),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFEEFFFA0022000A))
bram_en_int_i_1
(.I0(bram_en_int_i_2_n_0),
.I1(bram_en_int_i_3_n_0),
.I2(bram_en_int_i_4_n_0),
.I3(rd_data_sm_cs[3]),
.I4(rd_data_sm_cs[2]),
.I5(bram_en_b),
.O(bram_en_int_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hE0000000))
bram_en_int_i_10
(.I0(act_rd_burst),
.I1(act_rd_burst_two),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(bram_addr_ld_en),
.O(bram_en_int_i_10_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0111))
bram_en_int_i_11
(.I0(end_brst_rd),
.I1(brst_zero),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(bram_en_int_i_11_n_0));
LUT6 #(
.INIT(64'hBFFFBFBFBFFFBFFF))
bram_en_int_i_12
(.I0(I_WRAP_BRST_n_27),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(brst_zero),
.I4(axi_b2b_brst),
.I5(end_brst_rd),
.O(bram_en_int_i_12_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h45))
bram_en_int_i_13
(.I0(brst_zero),
.I1(axi_b2b_brst),
.I2(end_brst_rd),
.O(bram_en_int_i_13_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF4044))
bram_en_int_i_2
(.I0(bram_en_int_i_5_n_0),
.I1(rd_data_sm_cs[1]),
.I2(bram_en_int_i_6_n_0),
.I3(rd_data_sm_cs[2]),
.I4(bram_en_int_i_7_n_0),
.I5(I_WRAP_BRST_n_0),
.O(bram_en_int_i_2_n_0));
LUT6 #(
.INIT(64'h707370707C7F7C7C))
bram_en_int_i_3
(.I0(bram_en_int_i_6_n_0),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(rd_adv_buf67_out),
.I4(bram_en_int_i_9_n_0),
.I5(bram_en_int_i_10_n_0),
.O(bram_en_int_i_3_n_0));
LUT6 #(
.INIT(64'hA0001111AAAA1111))
bram_en_int_i_4
(.I0(rd_data_sm_cs[0]),
.I1(bram_addr_ld_en),
.I2(bram_en_int_i_11_n_0),
.I3(brst_one),
.I4(rd_data_sm_cs[1]),
.I5(bram_en_int_i_12_n_0),
.O(bram_en_int_i_4_n_0));
LUT6 #(
.INIT(64'h0044054455440544))
bram_en_int_i_5
(.I0(rd_data_sm_cs[2]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(bram_en_int_i_9_n_0),
.I3(rd_data_sm_cs[0]),
.I4(rd_adv_buf67_out),
.I5(bram_en_int_i_13_n_0),
.O(bram_en_int_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hECCC))
bram_en_int_i_6
(.I0(pend_rd_op),
.I1(bram_addr_ld_en),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.O(bram_en_int_i_6_n_0));
LUT6 #(
.INIT(64'h5554005500540000))
bram_en_int_i_7
(.I0(rd_data_sm_cs[1]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(axi_rd_burst),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[0]),
.I5(bram_addr_ld_en),
.O(bram_en_int_i_7_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
bram_en_int_i_9
(.I0(brst_zero),
.I1(end_brst_rd),
.O(bram_en_int_i_9_n_0));
FDRE #(
.INIT(1'b0))
bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_int_i_1_n_0),
.Q(bram_en_b),
.R(bram_rst_a));
LUT5 #(
.INIT(32'hD1DDD111))
\brst_cnt[0]_i_1
(.I0(brst_cnt[0]),
.I1(bram_addr_ld_en),
.I2(axi_arlen_pipe[0]),
.I3(axi_araddr_full),
.I4(s_axi_arlen[0]),
.O(\brst_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[1]_i_1
(.I0(axi_arlen_pipe[1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8B8B88B))
\brst_cnt[2]_i_1
(.I0(I_WRAP_BRST_n_2),
.I1(bram_addr_ld_en),
.I2(brst_cnt[2]),
.I3(brst_cnt[1]),
.I4(brst_cnt[0]),
.O(\brst_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B8B88B))
\brst_cnt[3]_i_1
(.I0(I_WRAP_BRST_n_5),
.I1(bram_addr_ld_en),
.I2(brst_cnt[3]),
.I3(brst_cnt[2]),
.I4(brst_cnt[0]),
.I5(brst_cnt[1]),
.O(\brst_cnt[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB800B800B8FF))
\brst_cnt[4]_i_1
(.I0(axi_arlen_pipe[4]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[4]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[4]),
.I5(\brst_cnt[4]_i_2_n_0 ),
.O(\brst_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFFFE))
\brst_cnt[4]_i_2
(.I0(brst_cnt[3]),
.I1(brst_cnt[2]),
.I2(brst_cnt[0]),
.I3(brst_cnt[1]),
.O(\brst_cnt[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hB800B8FFB8FFB800))
\brst_cnt[5]_i_1
(.I0(axi_arlen_pipe[5]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[5]),
.I3(bram_addr_ld_en),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hB88BB8B8))
\brst_cnt[6]_i_1
(.I0(\brst_cnt[6]_i_2_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[6]),
.I3(brst_cnt[5]),
.I4(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[6]_i_2
(.I0(axi_arlen_pipe[6]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[6]),
.O(\brst_cnt[6]_i_2_n_0 ));
LUT2 #(
.INIT(4'hE))
\brst_cnt[7]_i_1
(.I0(bram_addr_ld_en),
.I1(I_WRAP_BRST_n_8),
.O(\brst_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B88BB8B8B8B8))
\brst_cnt[7]_i_2
(.I0(\brst_cnt[7]_i_3_n_0 ),
.I1(bram_addr_ld_en),
.I2(brst_cnt[7]),
.I3(brst_cnt[6]),
.I4(brst_cnt[5]),
.I5(\brst_cnt[7]_i_4_n_0 ),
.O(\brst_cnt[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\brst_cnt[7]_i_3
(.I0(axi_arlen_pipe[7]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[7]),
.O(\brst_cnt[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h00000001))
\brst_cnt[7]_i_4
(.I0(brst_cnt[4]),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.I3(brst_cnt[2]),
.I4(brst_cnt[3]),
.O(\brst_cnt[7]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
brst_cnt_max_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_cnt_max),
.Q(brst_cnt_max_d1),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[0]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[0]_i_1_n_0 ),
.Q(brst_cnt[0]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[1]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[1]_i_1_n_0 ),
.Q(brst_cnt[1]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[2]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[2]_i_1_n_0 ),
.Q(brst_cnt[2]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[3]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[3]_i_1_n_0 ),
.Q(brst_cnt[3]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[4]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[4]_i_1_n_0 ),
.Q(brst_cnt[4]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[5]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[5]_i_1_n_0 ),
.Q(brst_cnt[5]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[6]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[6]_i_1_n_0 ),
.Q(brst_cnt[6]),
.R(bram_rst_a));
FDRE #(
.INIT(1'b0))
\brst_cnt_reg[7]
(.C(s_axi_aclk),
.CE(\brst_cnt[7]_i_1_n_0 ),
.D(\brst_cnt[7]_i_2_n_0 ),
.Q(brst_cnt[7]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h00000000F0EE0000))
brst_one_i_1
(.I0(brst_one),
.I1(brst_one_i_2_n_0),
.I2(axi_rd_burst_two),
.I3(bram_addr_ld_en),
.I4(s_axi_aresetn),
.I5(last_bram_addr_i_2_n_0),
.O(brst_one_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h08))
brst_one_i_2
(.I0(last_bram_addr_i_5_n_0),
.I1(brst_cnt[1]),
.I2(brst_cnt[0]),
.O(brst_one_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_one_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_one_i_1_n_0),
.Q(brst_one),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h00E0))
brst_zero_i_1
(.I0(brst_zero),
.I1(last_bram_addr_i_2_n_0),
.I2(s_axi_aresetn),
.I3(brst_zero_i_2_n_0),
.O(brst_zero_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h8A80AAAA))
brst_zero_i_2
(.I0(bram_addr_ld_en),
.I1(axi_arlen_pipe[0]),
.I2(axi_araddr_full),
.I3(s_axi_arlen[0]),
.I4(axi_rd_burst_i_2_n_0),
.O(brst_zero_i_2_n_0));
FDRE #(
.INIT(1'b0))
brst_zero_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(brst_zero_i_1_n_0),
.Q(brst_zero),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_1
(.I0(s_axi_arburst[0]),
.I1(axi_arburst_pipe[0]),
.I2(s_axi_arburst[1]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[1]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_fixed_burst),
.Q(curr_fixed_burst_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_1
(.I0(s_axi_arburst[1]),
.I1(axi_arburst_pipe[1]),
.I2(s_axi_arburst[0]),
.I3(axi_araddr_full),
.I4(axi_arburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_wrap_burst),
.Q(curr_wrap_burst_reg),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF000D0000))
disable_b2b_brst_i_1
(.I0(axi_rd_burst),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[3]),
.I4(disable_b2b_brst_i_2_n_0),
.I5(disable_b2b_brst_i_3_n_0),
.O(disable_b2b_brst_cmb));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT2 #(
.INIT(4'h2))
disable_b2b_brst_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.O(disable_b2b_brst_i_2_n_0));
LUT6 #(
.INIT(64'hEEEEEEE00EE0EEEE))
disable_b2b_brst_i_3
(.I0(disable_b2b_brst_i_4_n_0),
.I1(disable_b2b_brst),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[3]),
.O(disable_b2b_brst_i_3_n_0));
LUT6 #(
.INIT(64'h0000FE0000000000))
disable_b2b_brst_i_4
(.I0(brst_zero),
.I1(end_brst_rd),
.I2(brst_one),
.I3(rd_data_sm_cs[0]),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[2]_i_3_n_0 ),
.O(disable_b2b_brst_i_4_n_0));
FDRE #(
.INIT(1'b0))
disable_b2b_brst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(disable_b2b_brst_cmb),
.Q(disable_b2b_brst),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFCD00002200))
end_brst_rd_clr_i_1
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(end_brst_rd_clr),
.O(end_brst_rd_clr_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_clr_i_1_n_0),
.Q(end_brst_rd_clr),
.R(bram_rst_a));
LUT5 #(
.INIT(32'h0020F020))
end_brst_rd_i_1
(.I0(brst_cnt_max),
.I1(brst_cnt_max_d1),
.I2(s_axi_aresetn),
.I3(end_brst_rd),
.I4(end_brst_rd_clr),
.O(end_brst_rd_i_1_n_0));
FDRE #(
.INIT(1'b0))
end_brst_rd_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(end_brst_rd_i_1_n_0),
.Q(end_brst_rd),
.R(1'b0));
LUT6 #(
.INIT(64'hFAAAAAAAAAAAAFAB))
last_bram_addr_i_1
(.I0(last_bram_addr_i_2_n_0),
.I1(last_bram_addr_i_3_n_0),
.I2(rd_data_sm_cs[2]),
.I3(last_bram_addr_i_4_n_0),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(last_bram_addr0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'h08))
last_bram_addr_i_2
(.I0(last_bram_addr_i_5_n_0),
.I1(brst_cnt[0]),
.I2(brst_cnt[1]),
.O(last_bram_addr_i_2_n_0));
LUT6 #(
.INIT(64'h7F7F707F7F7F7F7F))
last_bram_addr_i_3
(.I0(p_0_in13_in),
.I1(rd_adv_buf67_out),
.I2(rd_data_sm_cs[3]),
.I3(bram_addr_ld_en),
.I4(I_WRAP_BRST_n_4),
.I5(axi_rd_burst_i_2_n_0),
.O(last_bram_addr_i_3_n_0));
LUT6 #(
.INIT(64'hA888200000000000))
last_bram_addr_i_4
(.I0(rd_adv_buf67_out),
.I1(bram_addr_ld_en),
.I2(pend_rd_op),
.I3(p_0_in13_in),
.I4(last_bram_addr_i_6_n_0),
.I5(\rd_data_sm_cs[3]_i_6_n_0 ),
.O(last_bram_addr_i_4_n_0));
LUT6 #(
.INIT(64'h0000000000000002))
last_bram_addr_i_5
(.I0(I_WRAP_BRST_n_8),
.I1(brst_cnt[7]),
.I2(brst_cnt[3]),
.I3(brst_cnt[4]),
.I4(brst_cnt[2]),
.I5(last_bram_addr_i_7_n_0),
.O(last_bram_addr_i_5_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
last_bram_addr_i_6
(.I0(last_bram_addr_i_8_n_0),
.I1(last_bram_addr_i_9_n_0),
.I2(I_WRAP_BRST_n_3),
.I3(I_WRAP_BRST_n_5),
.I4(I_WRAP_BRST_n_2),
.I5(I_WRAP_BRST_n_4),
.O(last_bram_addr_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'hE))
last_bram_addr_i_7
(.I0(brst_cnt[6]),
.I1(brst_cnt[5]),
.O(last_bram_addr_i_7_n_0));
LUT5 #(
.INIT(32'hFFFACCFA))
last_bram_addr_i_8
(.I0(s_axi_arlen[4]),
.I1(axi_arlen_pipe[4]),
.I2(s_axi_arlen[5]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[5]),
.O(last_bram_addr_i_8_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFFFACCFA))
last_bram_addr_i_9
(.I0(s_axi_arlen[6]),
.I1(axi_arlen_pipe[6]),
.I2(s_axi_arlen[7]),
.I3(axi_araddr_full),
.I4(axi_arlen_pipe[7]),
.O(last_bram_addr_i_9_n_0));
FDRE #(
.INIT(1'b0))
last_bram_addr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(last_bram_addr0),
.Q(last_bram_addr),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h88C8AAAAAAAAAAAA))
no_ar_ack_i_1
(.I0(no_ar_ack),
.I1(rd_data_sm_cs[1]),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[3]_i_6_n_0 ),
.I5(rd_data_sm_cs[0]),
.O(no_ar_ack_i_1_n_0));
FDRE #(
.INIT(1'b0))
no_ar_ack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(no_ar_ack_i_1_n_0),
.Q(no_ar_ack),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hAAAAFFFEAAAA0002))
pend_rd_op_i_1
(.I0(pend_rd_op_i_2_n_0),
.I1(pend_rd_op_i_3_n_0),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(pend_rd_op_i_4_n_0),
.I5(pend_rd_op),
.O(pend_rd_op_i_1_n_0));
LUT6 #(
.INIT(64'h0FFCC8C80CCCC8C8))
pend_rd_op_i_2
(.I0(p_0_in13_in),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(rd_data_sm_cs[2]),
.I5(pend_rd_op_i_5_n_0),
.O(pend_rd_op_i_2_n_0));
LUT6 #(
.INIT(64'h0303070733F3FFFF))
pend_rd_op_i_3
(.I0(p_0_in13_in),
.I1(rd_data_sm_cs[0]),
.I2(rd_data_sm_cs[1]),
.I3(s_axi_rlast),
.I4(pend_rd_op),
.I5(bram_addr_ld_en),
.O(pend_rd_op_i_3_n_0));
LUT6 #(
.INIT(64'h0000000080FFD5FF))
pend_rd_op_i_4
(.I0(rd_data_sm_cs[0]),
.I1(rd_adv_buf67_out),
.I2(pend_rd_op),
.I3(rd_data_sm_cs[1]),
.I4(pend_rd_op_i_6_n_0),
.I5(pend_rd_op_i_7_n_0),
.O(pend_rd_op_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
pend_rd_op_i_5
(.I0(ar_active),
.I1(end_brst_rd),
.O(pend_rd_op_i_5_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h15))
pend_rd_op_i_6
(.I0(bram_addr_ld_en),
.I1(end_brst_rd),
.I2(ar_active),
.O(pend_rd_op_i_6_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'hF1FF))
pend_rd_op_i_7
(.I0(pend_rd_op_i_8_n_0),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.O(pend_rd_op_i_7_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFF0008888))
pend_rd_op_i_8
(.I0(pend_rd_op),
.I1(s_axi_rlast),
.I2(ar_active),
.I3(end_brst_rd),
.I4(rd_data_sm_cs[0]),
.I5(rd_data_sm_cs[1]),
.O(pend_rd_op_i_8_n_0));
FDRE #(
.INIT(1'b0))
pend_rd_op_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(pend_rd_op_i_1_n_0),
.Q(pend_rd_op),
.R(bram_rst_a));
LUT6 #(
.INIT(64'hFFFFFFFF54005555))
\rd_data_sm_cs[0]_i_1
(.I0(\rd_data_sm_cs[0]_i_2_n_0 ),
.I1(pend_rd_op),
.I2(bram_addr_ld_en),
.I3(rd_adv_buf67_out),
.I4(\rd_data_sm_cs[0]_i_3_n_0 ),
.I5(\rd_data_sm_cs[0]_i_4_n_0 ),
.O(\rd_data_sm_cs[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hE000E0E0FFFFFFFF))
\rd_data_sm_cs[0]_i_2
(.I0(act_rd_burst_two),
.I1(act_rd_burst),
.I2(disable_b2b_brst_i_2_n_0),
.I3(bram_addr_ld_en),
.I4(rd_adv_buf67_out),
.I5(\rd_data_sm_cs[3]_i_6_n_0 ),
.O(\rd_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\rd_data_sm_cs[0]_i_3
(.I0(rd_data_sm_cs[1]),
.I1(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h001100F7001100D5))
\rd_data_sm_cs[0]_i_4
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[3]),
.I5(p_0_in13_in),
.O(\rd_data_sm_cs[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAEAAAEFFFFAAAE))
\rd_data_sm_cs[1]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(\rd_data_sm_cs[1]_i_2_n_0 ),
.I2(end_brst_rd),
.I3(brst_zero),
.I4(I_WRAP_BRST_n_25),
.I5(\rd_data_sm_cs[2]_i_4_n_0 ),
.O(\rd_data_sm_cs[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h04))
\rd_data_sm_cs[1]_i_2
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFEEEAEAEA))
\rd_data_sm_cs[2]_i_1
(.I0(\rd_data_sm_cs[2]_i_2_n_0 ),
.I1(\rd_data_sm_cs[2]_i_3_n_0 ),
.I2(\rd_data_sm_cs[2]_i_4_n_0 ),
.I3(p_0_in13_in),
.I4(disable_b2b_brst_i_2_n_0),
.I5(\rd_data_sm_cs[2]_i_5_n_0 ),
.O(\rd_data_sm_cs[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000007000F000000))
\rd_data_sm_cs[2]_i_2
(.I0(\rd_data_sm_cs[3]_i_7_n_0 ),
.I1(bram_addr_ld_en),
.I2(rd_data_sm_cs[3]),
.I3(rd_data_sm_cs[2]),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h1))
\rd_data_sm_cs[2]_i_3
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.O(\rd_data_sm_cs[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC8C8C8C808C8C8C8))
\rd_data_sm_cs[2]_i_4
(.I0(axi_rd_burst_two_reg_n_0),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[0]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.I5(I_WRAP_BRST_n_27),
.O(\rd_data_sm_cs[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0004000400040000))
\rd_data_sm_cs[2]_i_5
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(rd_data_sm_cs[1]),
.I3(rd_data_sm_cs[0]),
.I4(brst_zero),
.I5(end_brst_rd),
.O(\rd_data_sm_cs[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'h7444777730007444))
\rd_data_sm_cs[3]_i_1
(.I0(\rd_data_sm_cs[3]_i_3_n_0 ),
.I1(\rd_data_sm_cs[3]_i_4_n_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(\rd_data_sm_cs[3]_i_5_n_0 ),
.I5(bram_addr_ld_en),
.O(rd_data_sm_ns));
LUT6 #(
.INIT(64'h00800000AA800000))
\rd_data_sm_cs[3]_i_2
(.I0(\rd_data_sm_cs[3]_i_6_n_0 ),
.I1(bram_addr_ld_en),
.I2(\rd_data_sm_cs[3]_i_7_n_0 ),
.I3(rd_data_sm_cs[1]),
.I4(rd_data_sm_cs[0]),
.I5(rd_adv_buf67_out),
.O(\rd_data_sm_cs[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00000D0000000000))
\rd_data_sm_cs[3]_i_3
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(rd_adv_buf67_out),
.I4(rd_data_sm_cs[3]),
.I5(\rd_data_sm_cs[0]_i_3_n_0 ),
.O(\rd_data_sm_cs[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hBFAD))
\rd_data_sm_cs[3]_i_4
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h0053))
\rd_data_sm_cs[3]_i_5
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[1]),
.I2(rd_data_sm_cs[2]),
.I3(rd_data_sm_cs[0]),
.O(\rd_data_sm_cs[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h2))
\rd_data_sm_cs[3]_i_6
(.I0(rd_data_sm_cs[2]),
.I1(rd_data_sm_cs[3]),
.O(\rd_data_sm_cs[3]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h8880))
\rd_data_sm_cs[3]_i_7
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(act_rd_burst_two),
.I3(act_rd_burst),
.O(\rd_data_sm_cs[3]_i_7_n_0 ));
FDRE \rd_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[0]_i_1_n_0 ),
.Q(rd_data_sm_cs[0]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[1]_i_1_n_0 ),
.Q(rd_data_sm_cs[1]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[2]_i_1_n_0 ),
.Q(rd_data_sm_cs[2]),
.R(bram_rst_a));
FDRE \rd_data_sm_cs_reg[3]
(.C(s_axi_aclk),
.CE(rd_data_sm_ns),
.D(\rd_data_sm_cs[3]_i_2_n_0 ),
.Q(rd_data_sm_cs[3]),
.R(bram_rst_a));
LUT6 #(
.INIT(64'h1000111111110000))
rd_skid_buf_ld_reg_i_1
(.I0(rd_data_sm_cs[3]),
.I1(rd_data_sm_cs[2]),
.I2(s_axi_rvalid),
.I3(s_axi_rready),
.I4(rd_data_sm_cs[1]),
.I5(rd_data_sm_cs[0]),
.O(rd_skid_buf_ld_cmb));
FDRE #(
.INIT(1'b0))
rd_skid_buf_ld_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rd_skid_buf_ld_cmb),
.Q(rd_skid_buf_ld_reg),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hFE02))
rddata_mux_sel_i_1
(.I0(rddata_mux_sel_cmb),
.I1(rd_data_sm_cs[3]),
.I2(rddata_mux_sel_i_3_n_0),
.I3(rddata_mux_sel),
.O(rddata_mux_sel_i_1_n_0));
LUT6 #(
.INIT(64'hD208D208D208F208))
rddata_mux_sel_i_2
(.I0(rd_data_sm_cs[0]),
.I1(rd_data_sm_cs[1]),
.I2(rd_adv_buf67_out),
.I3(rd_data_sm_cs[2]),
.I4(act_rd_burst),
.I5(act_rd_burst_two),
.O(rddata_mux_sel_cmb));
LUT6 #(
.INIT(64'hA007AF07AF07AF07))
rddata_mux_sel_i_3
(.I0(rd_data_sm_cs[1]),
.I1(axi_rd_burst_two_reg_n_0),
.I2(rd_data_sm_cs[0]),
.I3(rd_data_sm_cs[2]),
.I4(s_axi_rvalid),
.I5(s_axi_rready),
.O(rddata_mux_sel_i_3_n_0));
FDRE #(
.INIT(1'b0))
rddata_mux_sel_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(rddata_mux_sel_i_1_n_0),
.Q(rddata_mux_sel),
.R(bram_rst_a));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'hEAAA))
s_axi_arready_INST_0
(.I0(axi_arready_int),
.I1(s_axi_rvalid),
.I2(s_axi_rready),
.I3(axi_early_arready_int),
.O(s_axi_arready));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
(axi_aresetn_d2,
axi_aresetn_re_reg,
bram_en_a,
bram_wrdata_a,
s_axi_bvalid,
\GEN_AW_DUAL.aw_active_reg_0 ,
s_axi_wready,
s_axi_awready,
s_axi_bid,
bram_addr_a,
bram_we_a,
s_axi_aresetn_0,
s_axi_aclk,
s_axi_awaddr,
s_axi_aresetn,
s_axi_awid,
s_axi_wdata,
s_axi_wvalid,
s_axi_wlast,
s_axi_bready,
s_axi_awburst,
s_axi_awvalid,
s_axi_awlen,
s_axi_wstrb);
output axi_aresetn_d2;
output axi_aresetn_re_reg;
output bram_en_a;
output [31:0]bram_wrdata_a;
output s_axi_bvalid;
output \GEN_AW_DUAL.aw_active_reg_0 ;
output s_axi_wready;
output s_axi_awready;
output [0:0]s_axi_bid;
output [13:0]bram_addr_a;
output [3:0]bram_we_a;
input s_axi_aresetn_0;
input s_axi_aclk;
input [13:0]s_axi_awaddr;
input s_axi_aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_wdata;
input s_axi_wvalid;
input s_axi_wlast;
input s_axi_bready;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
input [7:0]s_axi_awlen;
input [3:0]s_axi_wstrb;
wire BID_FIFO_n_1;
wire BID_FIFO_n_4;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ;
wire \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_1_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_2_n_0 ;
wire \GEN_AWREADY.axi_awready_int_i_3_n_0 ;
wire \GEN_AW_DUAL.aw_active_i_2_n_0 ;
wire \GEN_AW_DUAL.aw_active_reg_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ;
wire \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ;
wire \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ;
wire \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ;
wire \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ;
wire \I_RD_CHNL/axi_aresetn_d1 ;
wire I_WRAP_BRST_n_0;
wire I_WRAP_BRST_n_10;
wire I_WRAP_BRST_n_11;
wire I_WRAP_BRST_n_12;
wire I_WRAP_BRST_n_13;
wire I_WRAP_BRST_n_14;
wire I_WRAP_BRST_n_15;
wire I_WRAP_BRST_n_16;
wire I_WRAP_BRST_n_17;
wire I_WRAP_BRST_n_19;
wire I_WRAP_BRST_n_2;
wire I_WRAP_BRST_n_20;
wire I_WRAP_BRST_n_21;
wire I_WRAP_BRST_n_22;
wire I_WRAP_BRST_n_23;
wire I_WRAP_BRST_n_24;
wire I_WRAP_BRST_n_25;
wire I_WRAP_BRST_n_7;
wire I_WRAP_BRST_n_8;
wire I_WRAP_BRST_n_9;
wire aw_active;
wire axi_aresetn_d2;
wire axi_aresetn_re;
wire axi_aresetn_re_reg;
wire axi_awaddr_full;
wire [1:0]axi_awburst_pipe;
wire axi_awid_pipe;
wire [7:0]axi_awlen_pipe;
wire axi_awlen_pipe_1_or_2;
wire [1:1]axi_awsize_pipe;
wire axi_bvalid_int_i_1_n_0;
wire axi_wdata_full_cmb;
wire axi_wdata_full_cmb114_out;
wire axi_wdata_full_reg;
wire axi_wr_burst;
wire axi_wr_burst_cmb;
wire axi_wr_burst_cmb0;
wire axi_wr_burst_i_1_n_0;
wire axi_wr_burst_i_3_n_0;
wire axi_wready_int_mod_i_1_n_0;
wire axi_wready_int_mod_i_3_n_0;
wire bid_gets_fifo_load;
wire bid_gets_fifo_load_d1;
wire bid_gets_fifo_load_d1_i_2_n_0;
wire [13:0]bram_addr_a;
wire bram_addr_inc;
wire [13:10]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire bram_en_a;
wire bram_en_cmb;
wire [3:0]bram_we_a;
wire [31:0]bram_wrdata_a;
wire [2:0]bvalid_cnt;
wire \bvalid_cnt[0]_i_1_n_0 ;
wire \bvalid_cnt[1]_i_1_n_0 ;
wire \bvalid_cnt[2]_i_1_n_0 ;
wire bvalid_cnt_inc;
wire bvalid_cnt_inc11_out;
wire clr_bram_we;
wire clr_bram_we_cmb;
wire curr_awlen_reg_1_or_2;
wire curr_awlen_reg_1_or_20;
wire curr_awlen_reg_1_or_2_i_2_n_0;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire delay_aw_active_clr;
wire last_data_ack_mod;
wire p_18_out;
wire p_9_out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire wr_addr_sm_cs;
(* RTL_KEEP = "yes" *) wire [2:0]wr_data_sm_cs;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO BID_FIFO
(.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awid_pipe(axi_awid_pipe),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.\axi_bid_int_reg[0] (BID_FIFO_n_4),
.axi_bvalid_int_reg(s_axi_bvalid),
.axi_wdata_full_cmb114_out(axi_wdata_full_cmb114_out),
.axi_wr_burst(axi_wr_burst),
.bid_gets_fifo_load(bid_gets_fifo_load),
.bid_gets_fifo_load_d1(bid_gets_fifo_load_d1),
.bid_gets_fifo_load_d1_reg(BID_FIFO_n_1),
.bram_addr_ld_en(bram_addr_ld_en),
.bvalid_cnt(bvalid_cnt),
.bvalid_cnt_inc(bvalid_cnt_inc),
.\bvalid_cnt_reg[1] (bid_gets_fifo_load_d1_i_2_n_0),
.\bvalid_cnt_reg[2] (I_WRAP_BRST_n_20),
.\bvalid_cnt_reg[2]_0 (I_WRAP_BRST_n_19),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn_0),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.wr_addr_sm_cs(wr_addr_sm_cs));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[0]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h05051F1A))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(axi_wr_burst_cmb0),
.I2(wr_data_sm_cs[0]),
.I3(axi_wdata_full_cmb114_out),
.I4(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h5515))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3
(.I0(I_WRAP_BRST_n_21),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.O(axi_wr_burst_cmb0));
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[1]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000554000555540))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2
(.I0(wr_data_sm_cs[1]),
.I1(s_axi_wlast),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[2]),
.I5(axi_wr_burst),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1
(.I0(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ),
.I1(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ),
.I2(wr_data_sm_cs[2]),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h44010001))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2
(.I0(wr_data_sm_cs[2]),
.I1(wr_data_sm_cs[1]),
.I2(axi_wdata_full_cmb114_out),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h7774777774744444))
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[0]),
.I5(s_axi_wvalid),
.O(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0 ));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0 ),
.Q(wr_data_sm_cs[0]),
.R(s_axi_aresetn_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0 ),
.Q(wr_data_sm_cs[1]),
.R(s_axi_aresetn_0));
(* KEEP = "yes" *)
FDRE \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0 ),
.Q(wr_data_sm_cs[2]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_aresetn),
.Q(\I_RD_CHNL/axi_aresetn_d1 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\I_RD_CHNL/axi_aresetn_d1 ),
.Q(axi_aresetn_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\GEN_AWREADY.axi_aresetn_re_reg_i_1
(.I0(s_axi_aresetn),
.I1(\I_RD_CHNL/axi_aresetn_d1 ),
.O(axi_aresetn_re));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_aresetn_re_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_aresetn_re),
.Q(axi_aresetn_re_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFBFBFFFFFAA00))
\GEN_AWREADY.axi_awready_int_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(bram_addr_ld_en),
.I4(axi_aresetn_re_reg),
.I5(s_axi_awready),
.O(\GEN_AWREADY.axi_awready_int_i_1_n_0 ));
LUT6 #(
.INIT(64'h5444444400000000))
\GEN_AWREADY.axi_awready_int_i_2
(.I0(\GEN_AWREADY.axi_awready_int_i_3_n_0 ),
.I1(aw_active),
.I2(bvalid_cnt[1]),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(s_axi_awvalid),
.O(\GEN_AWREADY.axi_awready_int_i_2_n_0 ));
LUT6 #(
.INIT(64'hAABABABABABABABA))
\GEN_AWREADY.axi_awready_int_i_3
(.I0(wr_addr_sm_cs),
.I1(I_WRAP_BRST_n_21),
.I2(last_data_ack_mod),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\GEN_AWREADY.axi_awready_int_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AWREADY.axi_awready_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AWREADY.axi_awready_int_i_1_n_0 ),
.Q(s_axi_awready),
.R(s_axi_aresetn_0));
LUT1 #(
.INIT(2'h1))
\GEN_AW_DUAL.aw_active_i_1
(.I0(axi_aresetn_d2),
.O(\GEN_AW_DUAL.aw_active_reg_0 ));
LUT6 #(
.INIT(64'hFFFFF7FFFFFF0000))
\GEN_AW_DUAL.aw_active_i_2
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(wr_data_sm_cs[2]),
.I3(delay_aw_active_clr),
.I4(bram_addr_ld_en),
.I5(aw_active),
.O(\GEN_AW_DUAL.aw_active_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.aw_active_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.aw_active_i_2_n_0 ),
.Q(aw_active),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h80))
\GEN_AW_DUAL.last_data_ack_mod_i_1
(.I0(s_axi_wready),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(p_18_out));
FDRE #(
.INIT(1'b0))
\GEN_AW_DUAL.last_data_ack_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_18_out),
.Q(last_data_ack_mod),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0010001000100000))
\GEN_AW_DUAL.wr_addr_sm_cs_i_1
(.I0(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ),
.I1(wr_addr_sm_cs),
.I2(s_axi_awvalid),
.I3(axi_awaddr_full),
.I4(I_WRAP_BRST_n_20),
.I5(aw_active),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000040))
\GEN_AW_DUAL.wr_addr_sm_cs_i_2
(.I0(I_WRAP_BRST_n_20),
.I1(last_data_ack_mod),
.I2(axi_awaddr_full),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(axi_awlen_pipe_1_or_2),
.I5(curr_awlen_reg_1_or_2),
.O(\GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0 ));
FDRE \GEN_AW_DUAL.wr_addr_sm_cs_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0 ),
.Q(wr_addr_sm_cs),
.R(\GEN_AW_DUAL.aw_active_reg_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[8]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[9]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[10]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[11]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[12]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[13]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[0]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[1]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[2]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[3]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[4]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[5]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[6]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awaddr[7]),
.Q(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.R(1'b0));
LUT5 #(
.INIT(32'h4000EA00))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(s_axi_aresetn),
.I4(bram_addr_ld_en),
.O(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0 ),
.Q(axi_awaddr_full),
.R(1'b0));
LUT6 #(
.INIT(64'hBF00BF00BF00FF40))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.I3(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.I4(s_axi_awburst[0]),
.I5(s_axi_awburst[1]),
.O(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0 ),
.Q(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[0]),
.Q(axi_awburst_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awburst[1]),
.Q(axi_awburst_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awid),
.Q(axi_awid_pipe),
.R(1'b0));
LUT3 #(
.INIT(8'h40))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1
(.I0(axi_awaddr_full),
.I1(\GEN_AWREADY.axi_awready_int_i_2_n_0 ),
.I2(axi_aresetn_d2),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h0002))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(s_axi_awlen[3]),
.I2(s_axi_awlen[2]),
.I3(s_axi_awlen[1]),
.O(p_9_out));
LUT4 #(
.INIT(16'h0001))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2
(.I0(s_axi_awlen[4]),
.I1(s_axi_awlen[6]),
.I2(s_axi_awlen[7]),
.I3(s_axi_awlen[5]),
.O(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(p_9_out),
.Q(axi_awlen_pipe_1_or_2),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[0]),
.Q(axi_awlen_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[1]),
.Q(axi_awlen_pipe[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[2]),
.Q(axi_awlen_pipe[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[3]),
.Q(axi_awlen_pipe[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[4]),
.Q(axi_awlen_pipe[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[5]),
.Q(axi_awlen_pipe[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[6]),
.Q(axi_awlen_pipe[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(s_axi_awlen[7]),
.Q(axi_awlen_pipe[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0 ),
.D(1'b1),
.Q(axi_awsize_pipe),
.R(1'b0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0
(.I0(bram_addr_a[4]),
.I1(bram_addr_a[1]),
.I2(bram_addr_a[0]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[3]),
.I5(bram_addr_a[5]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hF7FFFFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0
(.I0(bram_addr_a[6]),
.I1(bram_addr_a[4]),
.I2(I_WRAP_BRST_n_17),
.I3(bram_addr_a[5]),
.I4(bram_addr_a[7]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(s_axi_wvalid),
.O(bram_addr_inc));
LUT4 #(
.INIT(16'h1000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[0]),
.I3(wr_data_sm_cs[1]),
.O(bram_addr_rst_cmb));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_8),
.Q(bram_addr_a[8]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_7),
.Q(bram_addr_a[9]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[10]),
.Q(bram_addr_a[10]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[11]),
.Q(bram_addr_a[11]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[12]),
.Q(bram_addr_a[12]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en_mod),
.D(bram_addr_ld[13]),
.Q(bram_addr_a[13]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_16),
.Q(bram_addr_a[0]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_15),
.Q(bram_addr_a[1]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_14),
.Q(bram_addr_a[2]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_13),
.Q(bram_addr_a[3]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_12),
.Q(bram_addr_a[4]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_11),
.Q(bram_addr_a[5]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_10),
.Q(bram_addr_a[6]),
.R(I_WRAP_BRST_n_0));
FDRE #(
.INIT(1'b0))
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]
(.C(s_axi_aclk),
.CE(I_WRAP_BRST_n_2),
.D(I_WRAP_BRST_n_9),
.Q(bram_addr_a[7]),
.R(I_WRAP_BRST_n_0));
LUT5 #(
.INIT(32'h15FF1500))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.O(axi_wdata_full_cmb));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wdata_full_cmb),
.Q(axi_wdata_full_reg),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h4777477444444444))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I1(wr_data_sm_cs[2]),
.I2(wr_data_sm_cs[1]),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(s_axi_wvalid),
.O(bram_en_cmb));
LUT3 #(
.INIT(8'h15))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bram_en_cmb),
.Q(bram_en_a),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0010001000101110))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1
(.I0(wr_data_sm_cs[0]),
.I1(wr_data_sm_cs[1]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I5(axi_wr_burst),
.O(clr_bram_we_cmb));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h80))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2
(.I0(axi_wdata_full_cmb114_out),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(clr_bram_we_cmb),
.Q(clr_bram_we),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hFEAAFEFF02AA0200))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1
(.I0(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ),
.I1(axi_wr_burst),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[2]),
.I4(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ),
.I5(delay_aw_active_clr),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ));
LUT5 #(
.INIT(32'h0000222E))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2
(.I0(s_axi_wlast),
.I1(wr_data_sm_cs[2]),
.I2(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0 ),
.I3(wr_data_sm_cs[0]),
.I4(wr_data_sm_cs[1]),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0 ));
LUT6 #(
.INIT(64'h8B338B0088008800))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3
(.I0(delay_aw_active_clr),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(axi_wdata_full_cmb114_out),
.I5(bvalid_cnt_inc11_out),
.O(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0 ));
LUT2 #(
.INIT(4'h8))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4
(.I0(s_axi_wvalid),
.I1(s_axi_wlast),
.O(bvalid_cnt_inc11_out));
FDRE #(
.INIT(1'b0))
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0 ),
.Q(delay_aw_active_clr),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[0].bram_wrdata_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[0]),
.Q(bram_wrdata_a[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[10].bram_wrdata_int_reg[10]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[10]),
.Q(bram_wrdata_a[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[11].bram_wrdata_int_reg[11]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[11]),
.Q(bram_wrdata_a[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[12].bram_wrdata_int_reg[12]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[12]),
.Q(bram_wrdata_a[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[13].bram_wrdata_int_reg[13]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[13]),
.Q(bram_wrdata_a[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[14].bram_wrdata_int_reg[14]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[14]),
.Q(bram_wrdata_a[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[15].bram_wrdata_int_reg[15]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[15]),
.Q(bram_wrdata_a[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[16].bram_wrdata_int_reg[16]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[16]),
.Q(bram_wrdata_a[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[17].bram_wrdata_int_reg[17]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[17]),
.Q(bram_wrdata_a[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[18].bram_wrdata_int_reg[18]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[18]),
.Q(bram_wrdata_a[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[19].bram_wrdata_int_reg[19]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[19]),
.Q(bram_wrdata_a[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[1].bram_wrdata_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[1]),
.Q(bram_wrdata_a[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[20].bram_wrdata_int_reg[20]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[20]),
.Q(bram_wrdata_a[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[21].bram_wrdata_int_reg[21]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[21]),
.Q(bram_wrdata_a[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[22].bram_wrdata_int_reg[22]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[22]),
.Q(bram_wrdata_a[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[23].bram_wrdata_int_reg[23]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[23]),
.Q(bram_wrdata_a[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[24].bram_wrdata_int_reg[24]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[24]),
.Q(bram_wrdata_a[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[25].bram_wrdata_int_reg[25]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[25]),
.Q(bram_wrdata_a[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[26].bram_wrdata_int_reg[26]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[26]),
.Q(bram_wrdata_a[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[27].bram_wrdata_int_reg[27]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[27]),
.Q(bram_wrdata_a[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[28].bram_wrdata_int_reg[28]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[28]),
.Q(bram_wrdata_a[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[29].bram_wrdata_int_reg[29]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[29]),
.Q(bram_wrdata_a[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[2].bram_wrdata_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[2]),
.Q(bram_wrdata_a[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[30].bram_wrdata_int_reg[30]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[30]),
.Q(bram_wrdata_a[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[31].bram_wrdata_int_reg[31]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[31]),
.Q(bram_wrdata_a[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[3].bram_wrdata_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[3]),
.Q(bram_wrdata_a[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[4].bram_wrdata_int_reg[4]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[4]),
.Q(bram_wrdata_a[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[5].bram_wrdata_int_reg[5]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[5]),
.Q(bram_wrdata_a[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[6].bram_wrdata_int_reg[6]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[6]),
.Q(bram_wrdata_a[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[7].bram_wrdata_int_reg[7]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[7]),
.Q(bram_wrdata_a[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[8].bram_wrdata_int_reg[8]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[8]),
.Q(bram_wrdata_a[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\GEN_WRDATA[9].bram_wrdata_int_reg[9]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wdata[9]),
.Q(bram_wrdata_a[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hD0FF))
\GEN_WR_NO_ECC.bram_we_int[3]_i_1
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.I2(clr_bram_we),
.I3(s_axi_aresetn),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
LUT2 #(
.INIT(4'h2))
\GEN_WR_NO_ECC.bram_we_int[3]_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[2]),
.O(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[0]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[0]),
.Q(bram_we_a[0]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[1]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[1]),
.Q(bram_we_a[1]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[2]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[2]),
.Q(bram_we_a[2]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\GEN_WR_NO_ECC.bram_we_int_reg[3]
(.C(s_axi_aclk),
.CE(\GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0 ),
.D(s_axi_wstrb[3]),
.Q(bram_we_a[3]),
.R(\GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst I_WRAP_BRST
(.D({bram_addr_ld,I_WRAP_BRST_n_7,I_WRAP_BRST_n_8,I_WRAP_BRST_n_9,I_WRAP_BRST_n_10,I_WRAP_BRST_n_11,I_WRAP_BRST_n_12,I_WRAP_BRST_n_13,I_WRAP_BRST_n_14,I_WRAP_BRST_n_15,I_WRAP_BRST_n_16}),
.E(I_WRAP_BRST_n_2),
.\GEN_AWREADY.axi_aresetn_d2_reg (axi_aresetn_d2),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg (\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg (\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] (\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0 ),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] (I_WRAP_BRST_n_17),
.\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 (\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0 ),
.Q(axi_awlen_pipe[3:0]),
.SR(I_WRAP_BRST_n_0),
.aw_active(aw_active),
.axi_awaddr_full(axi_awaddr_full),
.axi_awlen_pipe_1_or_2(axi_awlen_pipe_1_or_2),
.axi_awsize_pipe(axi_awsize_pipe),
.bram_addr_a(bram_addr_a[9:0]),
.bram_addr_inc(bram_addr_inc),
.bram_addr_ld_en(bram_addr_ld_en),
.bram_addr_ld_en_mod(bram_addr_ld_en_mod),
.bram_addr_rst_cmb(bram_addr_rst_cmb),
.bvalid_cnt(bvalid_cnt),
.curr_awlen_reg_1_or_2(curr_awlen_reg_1_or_2),
.curr_fixed_burst(curr_fixed_burst),
.curr_fixed_burst_reg(curr_fixed_burst_reg),
.curr_fixed_burst_reg_reg(I_WRAP_BRST_n_24),
.curr_wrap_burst(curr_wrap_burst),
.curr_wrap_burst_reg(curr_wrap_burst_reg),
.curr_wrap_burst_reg_reg(I_WRAP_BRST_n_25),
.last_data_ack_mod(last_data_ack_mod),
.out(wr_data_sm_cs),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(s_axi_aresetn_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen[3:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wvalid(s_axi_wvalid),
.\save_init_bram_addr_ld_reg[15]_0 (I_WRAP_BRST_n_19),
.\save_init_bram_addr_ld_reg[15]_1 (I_WRAP_BRST_n_20),
.\save_init_bram_addr_ld_reg[15]_2 (I_WRAP_BRST_n_21),
.wr_addr_sm_cs(wr_addr_sm_cs),
.\wrap_burst_total_reg[0]_0 (I_WRAP_BRST_n_22),
.\wrap_burst_total_reg[2]_0 (I_WRAP_BRST_n_23));
FDRE #(
.INIT(1'b0))
\axi_bid_int_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(BID_FIFO_n_4),
.Q(s_axi_bid),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hAAAAAAAAAAAA8A88))
axi_bvalid_int_i_1
(.I0(s_axi_aresetn),
.I1(bvalid_cnt_inc),
.I2(BID_FIFO_n_1),
.I3(bvalid_cnt[0]),
.I4(bvalid_cnt[2]),
.I5(bvalid_cnt[1]),
.O(axi_bvalid_int_i_1_n_0));
FDRE #(
.INIT(1'b0))
axi_bvalid_int_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_bvalid_int_i_1_n_0),
.Q(s_axi_bvalid),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
axi_wr_burst_i_1
(.I0(axi_wr_burst_cmb),
.I1(axi_wr_burst_i_3_n_0),
.I2(axi_wr_burst),
.O(axi_wr_burst_i_1_n_0));
LUT5 #(
.INIT(32'h3088FCBB))
axi_wr_burst_i_2
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[1]),
.I2(axi_wr_burst_cmb0),
.I3(wr_data_sm_cs[0]),
.I4(s_axi_wlast),
.O(axi_wr_burst_cmb));
LUT6 #(
.INIT(64'h00000000AAAAA222))
axi_wr_burst_i_3
(.I0(s_axi_wvalid),
.I1(wr_data_sm_cs[0]),
.I2(axi_wr_burst_cmb0),
.I3(s_axi_wlast),
.I4(wr_data_sm_cs[1]),
.I5(wr_data_sm_cs[2]),
.O(axi_wr_burst_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wr_burst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wr_burst_i_1_n_0),
.Q(axi_wr_burst),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hEA00EAFF00000000))
axi_wready_int_mod_i_1
(.I0(axi_wdata_full_cmb114_out),
.I1(axi_awaddr_full),
.I2(bram_addr_ld_en),
.I3(wr_data_sm_cs[2]),
.I4(axi_wready_int_mod_i_3_n_0),
.I5(s_axi_aresetn),
.O(axi_wready_int_mod_i_1_n_0));
LUT5 #(
.INIT(32'hF8F9F0F0))
axi_wready_int_mod_i_3
(.I0(wr_data_sm_cs[1]),
.I1(wr_data_sm_cs[0]),
.I2(axi_wdata_full_reg),
.I3(axi_wdata_full_cmb114_out),
.I4(s_axi_wvalid),
.O(axi_wready_int_mod_i_3_n_0));
FDRE #(
.INIT(1'b0))
axi_wready_int_mod_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(axi_wready_int_mod_i_1_n_0),
.Q(s_axi_wready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hEF))
bid_gets_fifo_load_d1_i_2
(.I0(bvalid_cnt[1]),
.I1(bvalid_cnt[2]),
.I2(bvalid_cnt[0]),
.O(bid_gets_fifo_load_d1_i_2_n_0));
FDRE #(
.INIT(1'b0))
bid_gets_fifo_load_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bid_gets_fifo_load),
.Q(bid_gets_fifo_load_d1),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h95956A6A95956AAA))
\bvalid_cnt[0]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD5D5BFBF2A2A4000))
\bvalid_cnt[1]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hD52AFF00FF00BF00))
\bvalid_cnt[2]_i_1
(.I0(bvalid_cnt_inc),
.I1(s_axi_bready),
.I2(s_axi_bvalid),
.I3(bvalid_cnt[2]),
.I4(bvalid_cnt[0]),
.I5(bvalid_cnt[1]),
.O(\bvalid_cnt[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[0]_i_1_n_0 ),
.Q(bvalid_cnt[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[1]_i_1_n_0 ),
.Q(bvalid_cnt[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\bvalid_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\bvalid_cnt[2]_i_1_n_0 ),
.Q(bvalid_cnt[2]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'h0000000000000151))
curr_awlen_reg_1_or_2_i_1
(.I0(I_WRAP_BRST_n_23),
.I1(s_axi_awlen[2]),
.I2(axi_awaddr_full),
.I3(axi_awlen_pipe[2]),
.I4(I_WRAP_BRST_n_22),
.I5(curr_awlen_reg_1_or_2_i_2_n_0),
.O(curr_awlen_reg_1_or_20));
LUT6 #(
.INIT(64'hF5F5F5F5F5F5F5C5))
curr_awlen_reg_1_or_2_i_2
(.I0(\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0 ),
.I1(axi_awlen_pipe[5]),
.I2(axi_awaddr_full),
.I3(axi_awlen_pipe[6]),
.I4(axi_awlen_pipe[7]),
.I5(axi_awlen_pipe[4]),
.O(curr_awlen_reg_1_or_2_i_2_n_0));
FDRE #(
.INIT(1'b0))
curr_awlen_reg_1_or_2_reg
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(curr_awlen_reg_1_or_20),
.Q(curr_awlen_reg_1_or_2),
.R(s_axi_aresetn_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h00053305))
curr_fixed_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_fixed_burst));
FDRE #(
.INIT(1'b0))
curr_fixed_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_24),
.Q(curr_fixed_burst_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h000ACC0A))
curr_wrap_burst_reg_i_2
(.I0(s_axi_awburst[1]),
.I1(axi_awburst_pipe[1]),
.I2(s_axi_awburst[0]),
.I3(axi_awaddr_full),
.I4(axi_awburst_pipe[0]),
.O(curr_wrap_burst));
FDRE #(
.INIT(1'b0))
curr_wrap_burst_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_WRAP_BRST_n_25),
.Q(curr_wrap_burst_reg),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
(SR,
bram_addr_ld_en_mod,
E,
D,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
bram_addr_ld_en,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
\save_init_bram_addr_ld_reg[15]_2 ,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[2]_0 ,
curr_fixed_burst_reg_reg,
curr_wrap_burst_reg_reg,
curr_fixed_burst_reg,
bram_addr_inc,
bram_addr_rst_cmb,
s_axi_aresetn,
out,
s_axi_wvalid,
bram_addr_a,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ,
axi_awaddr_full,
s_axi_awaddr,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ,
\GEN_AWREADY.axi_aresetn_d2_reg ,
wr_addr_sm_cs,
last_data_ack_mod,
bvalid_cnt,
aw_active,
s_axi_awvalid,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ,
axi_awlen_pipe_1_or_2,
curr_awlen_reg_1_or_2,
curr_wrap_burst_reg,
Q,
s_axi_awlen,
axi_awsize_pipe,
curr_fixed_burst,
curr_wrap_burst,
s_axi_aresetn_0,
s_axi_aclk);
output [0:0]SR;
output bram_addr_ld_en_mod;
output [0:0]E;
output [13:0]D;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
output bram_addr_ld_en;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
output \save_init_bram_addr_ld_reg[15]_2 ;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[2]_0 ;
output curr_fixed_burst_reg_reg;
output curr_wrap_burst_reg_reg;
input curr_fixed_burst_reg;
input bram_addr_inc;
input bram_addr_rst_cmb;
input s_axi_aresetn;
input [2:0]out;
input s_axi_wvalid;
input [9:0]bram_addr_a;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
input axi_awaddr_full;
input [13:0]s_axi_awaddr;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
input \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
input \GEN_AWREADY.axi_aresetn_d2_reg ;
input wr_addr_sm_cs;
input last_data_ack_mod;
input [2:0]bvalid_cnt;
input aw_active;
input s_axi_awvalid;
input \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
input axi_awlen_pipe_1_or_2;
input curr_awlen_reg_1_or_2;
input curr_wrap_burst_reg;
input [3:0]Q;
input [3:0]s_axi_awlen;
input [0:0]axi_awsize_pipe;
input curr_fixed_burst;
input curr_wrap_burst;
input s_axi_aresetn_0;
input s_axi_aclk;
wire [13:0]D;
wire [0:0]E;
wire \GEN_AWREADY.axi_aresetn_d2_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ;
wire \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ;
wire [3:0]Q;
wire [0:0]SR;
wire aw_active;
wire axi_awaddr_full;
wire axi_awlen_pipe_1_or_2;
wire [0:0]axi_awsize_pipe;
wire [9:0]bram_addr_a;
wire bram_addr_inc;
wire [9:1]bram_addr_ld;
wire bram_addr_ld_en;
wire bram_addr_ld_en_mod;
wire bram_addr_rst_cmb;
wire [2:0]bvalid_cnt;
wire curr_awlen_reg_1_or_2;
wire curr_fixed_burst;
wire curr_fixed_burst_reg;
wire curr_fixed_burst_reg_reg;
wire curr_wrap_burst;
wire curr_wrap_burst_reg;
wire curr_wrap_burst_reg_reg;
wire last_data_ack_mod;
wire [2:0]out;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [13:0]s_axi_awaddr;
wire [3:0]s_axi_awlen;
wire s_axi_awvalid;
wire s_axi_wvalid;
wire [15:3]save_init_bram_addr_ld;
wire \save_init_bram_addr_ld[3]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg[15]_2 ;
wire wr_addr_sm_cs;
wire [2:0]wrap_burst_total;
wire \wrap_burst_total[0]_i_1__0_n_0 ;
wire \wrap_burst_total[0]_i_2__0_n_0 ;
wire \wrap_burst_total[0]_i_4__0_n_0 ;
wire \wrap_burst_total[0]_i_5_n_0 ;
wire \wrap_burst_total[1]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_1__0_n_0 ;
wire \wrap_burst_total[2]_i_2__0_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[2]_0 ;
LUT6 #(
.INIT(64'hBB8BBBBB88B88888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1
(.I0(bram_addr_ld[8]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[7]),
.I5(bram_addr_a[8]),
.O(D[8]));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(E));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2
(.I0(bram_addr_ld[9]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[9]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0 ),
.I4(bram_addr_a[8]),
.O(D[9]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1
(.I0(save_init_bram_addr_ld[12]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1
(.I0(save_init_bram_addr_ld[13]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1
(.I0(save_init_bram_addr_ld[14]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[12]),
.O(D[12]));
LUT5 #(
.INIT(32'h4500FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0
(.I0(bram_addr_ld_en_mod),
.I1(curr_fixed_burst_reg),
.I2(bram_addr_inc),
.I3(bram_addr_rst_cmb),
.I4(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'hAAABAAAAAAAAAAAA))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.I2(out[1]),
.I3(out[2]),
.I4(out[0]),
.I5(s_axi_wvalid),
.O(bram_addr_ld_en_mod));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3
(.I0(save_init_bram_addr_ld[15]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[13]),
.O(D[13]));
LUT6 #(
.INIT(64'h55555555FFFFFFDF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6
(.I0(curr_wrap_burst_reg),
.I1(wrap_burst_total[1]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[0]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ));
LUT6 #(
.INIT(64'h000000008F00C000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8
(.I0(bram_addr_a[2]),
.I1(bram_addr_a[1]),
.I2(wrap_burst_total[1]),
.I3(bram_addr_a[0]),
.I4(wrap_burst_total[0]),
.I5(wrap_burst_total[2]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hB800B800B800FFFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1
(.I0(\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg ),
.I1(axi_awaddr_full),
.I2(s_axi_awaddr[0]),
.I3(bram_addr_ld_en),
.I4(bram_addr_ld_en_mod),
.I5(bram_addr_a[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h8BB8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1
(.I0(bram_addr_ld[1]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[1]),
.I3(bram_addr_a[0]),
.O(D[1]));
LUT5 #(
.INIT(32'h8BB8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1
(.I0(bram_addr_ld[2]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[0]),
.I4(bram_addr_a[1]),
.O(D[2]));
LUT6 #(
.INIT(64'h8BB8B8B8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1
(.I0(bram_addr_ld[3]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[3]),
.I3(bram_addr_a[2]),
.I4(bram_addr_a[0]),
.I5(bram_addr_a[1]),
.O(D[3]));
LUT4 #(
.INIT(16'hB88B))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1
(.I0(bram_addr_ld[4]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.O(D[4]));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1
(.I0(bram_addr_ld[5]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[5]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I4(bram_addr_a[4]),
.O(D[5]));
LUT6 #(
.INIT(64'hB8B88BB8B8B8B8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1
(.I0(bram_addr_ld[6]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[6]),
.I3(bram_addr_a[4]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I5(bram_addr_a[5]),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0
(.I0(bram_addr_a[1]),
.I1(bram_addr_a[0]),
.I2(bram_addr_a[2]),
.I3(bram_addr_a[3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ));
LUT5 #(
.INIT(32'hB88BB8B8))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1
(.I0(bram_addr_ld[7]),
.I1(bram_addr_ld_en_mod),
.I2(bram_addr_a[7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(bram_addr_a[6]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'h00E2))
curr_fixed_burst_reg_i_1__0
(.I0(curr_fixed_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_fixed_burst),
.I3(SR),
.O(curr_fixed_burst_reg_reg));
LUT4 #(
.INIT(16'h00E2))
curr_wrap_burst_reg_i_1__0
(.I0(curr_wrap_burst_reg),
.I1(bram_addr_ld_en),
.I2(curr_wrap_burst),
.I3(SR),
.O(curr_wrap_burst_reg_reg));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1
(.I0(save_init_bram_addr_ld[10]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[8]),
.O(bram_addr_ld[8]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1
(.I0(save_init_bram_addr_ld[11]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[9]),
.O(bram_addr_ld[9]));
LUT6 #(
.INIT(64'h0808080808AA0808))
\save_init_bram_addr_ld[15]_i_1
(.I0(\GEN_AWREADY.axi_aresetn_d2_reg ),
.I1(\save_init_bram_addr_ld_reg[15]_0 ),
.I2(wr_addr_sm_cs),
.I3(\save_init_bram_addr_ld_reg[15]_1 ),
.I4(last_data_ack_mod),
.I5(\save_init_bram_addr_ld_reg[15]_2 ),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h007F007F007F0000))
\save_init_bram_addr_ld[15]_i_2
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.I3(aw_active),
.I4(axi_awaddr_full),
.I5(s_axi_awvalid),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT3 #(
.INIT(8'h80))
\save_init_bram_addr_ld[15]_i_3
(.I0(bvalid_cnt[2]),
.I1(bvalid_cnt[0]),
.I2(bvalid_cnt[1]),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
LUT4 #(
.INIT(16'hFFFD))
\save_init_bram_addr_ld[15]_i_4
(.I0(axi_awaddr_full),
.I1(\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg ),
.I2(axi_awlen_pipe_1_or_2),
.I3(curr_awlen_reg_1_or_2),
.O(\save_init_bram_addr_ld_reg[15]_2 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1
(.I0(\save_init_bram_addr_ld[3]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[1]),
.O(bram_addr_ld[1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hC80C))
\save_init_bram_addr_ld[3]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(save_init_bram_addr_ld[3]),
.I2(wrap_burst_total[1]),
.I3(wrap_burst_total[2]),
.O(\save_init_bram_addr_ld[3]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1
(.I0(\save_init_bram_addr_ld[4]_i_2__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[2]),
.O(bram_addr_ld[2]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2__0
(.I0(save_init_bram_addr_ld[4]),
.I1(wrap_burst_total[0]),
.I2(wrap_burst_total[2]),
.I3(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[4]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\save_init_bram_addr_ld[5]_i_1
(.I0(save_init_bram_addr_ld[5]),
.I1(\save_init_bram_addr_ld[5]_i_2__0_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I3(\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg ),
.I4(axi_awaddr_full),
.I5(s_axi_awaddr[3]),
.O(bram_addr_ld[3]));
LUT3 #(
.INIT(8'hFB))
\save_init_bram_addr_ld[5]_i_2__0
(.I0(wrap_burst_total[0]),
.I1(wrap_burst_total[2]),
.I2(wrap_burst_total[1]),
.O(\save_init_bram_addr_ld[5]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1
(.I0(save_init_bram_addr_ld[6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[4]),
.O(bram_addr_ld[4]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1
(.I0(save_init_bram_addr_ld[7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[5]),
.O(bram_addr_ld[5]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1
(.I0(save_init_bram_addr_ld[8]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[6]),
.O(bram_addr_ld[6]));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1
(.I0(save_init_bram_addr_ld[9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0 ),
.I2(\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg ),
.I3(axi_awaddr_full),
.I4(s_axi_awaddr[7]),
.O(bram_addr_ld[7]));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[8]),
.Q(save_init_bram_addr_ld[10]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[9]),
.Q(save_init_bram_addr_ld[11]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(save_init_bram_addr_ld[12]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(save_init_bram_addr_ld[13]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(save_init_bram_addr_ld[14]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(save_init_bram_addr_ld[15]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[1]),
.Q(save_init_bram_addr_ld[3]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[2]),
.Q(save_init_bram_addr_ld[4]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[3]),
.Q(save_init_bram_addr_ld[5]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[4]),
.Q(save_init_bram_addr_ld[6]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[5]),
.Q(save_init_bram_addr_ld[7]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[6]),
.Q(save_init_bram_addr_ld[8]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(bram_addr_ld[7]),
.Q(save_init_bram_addr_ld[9]),
.R(s_axi_aresetn_0));
LUT6 #(
.INIT(64'hF909090900000000))
\wrap_burst_total[0]_i_1__0
(.I0(\wrap_burst_total[0]_i_2__0_n_0 ),
.I1(\wrap_burst_total_reg[0]_0 ),
.I2(\wrap_burst_total[0]_i_4__0_n_0 ),
.I3(Q[1]),
.I4(Q[2]),
.I5(\wrap_burst_total[0]_i_5_n_0 ),
.O(\wrap_burst_total[0]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2__0
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[2]),
.O(\wrap_burst_total[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_3__0
(.I0(Q[1]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[1]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_4__0
(.I0(axi_awaddr_full),
.I1(axi_awsize_pipe),
.O(\wrap_burst_total[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'h000ACC0A))
\wrap_burst_total[0]_i_5
(.I0(s_axi_awlen[0]),
.I1(Q[0]),
.I2(s_axi_awlen[3]),
.I3(axi_awaddr_full),
.I4(Q[3]),
.O(\wrap_burst_total[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h000008F3))
\wrap_burst_total[1]_i_1__0
(.I0(Q[2]),
.I1(axi_awaddr_full),
.I2(axi_awsize_pipe),
.I3(\wrap_burst_total_reg[2]_0 ),
.I4(\wrap_burst_total[2]_i_2__0_n_0 ),
.O(\wrap_burst_total[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h5000000044004400))
\wrap_burst_total[2]_i_1__0
(.I0(\wrap_burst_total[2]_i_2__0_n_0 ),
.I1(s_axi_awlen[2]),
.I2(Q[2]),
.I3(\wrap_burst_total_reg[2]_0 ),
.I4(axi_awsize_pipe),
.I5(axi_awaddr_full),
.O(\wrap_burst_total[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h335FFF5F))
\wrap_burst_total[2]_i_2__0
(.I0(s_axi_awlen[1]),
.I1(Q[1]),
.I2(s_axi_awlen[0]),
.I3(axi_awaddr_full),
.I4(Q[0]),
.O(\wrap_burst_total[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3__0
(.I0(Q[3]),
.I1(axi_awaddr_full),
.I2(s_axi_awlen[3]),
.O(\wrap_burst_total_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1__0_n_0 ),
.Q(wrap_burst_total[0]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1__0_n_0 ),
.Q(wrap_burst_total[1]),
.R(s_axi_aresetn_0));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1__0_n_0 ),
.Q(wrap_burst_total[2]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "wrap_brst" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ,
SR,
\wrap_burst_total_reg[0]_0 ,
\wrap_burst_total_reg[0]_1 ,
\wrap_burst_total_reg[0]_2 ,
\wrap_burst_total_reg[0]_3 ,
E,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ,
D,
bram_addr_ld_en,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ,
\rd_data_sm_cs_reg[1] ,
\save_init_bram_addr_ld_reg[15]_0 ,
\save_init_bram_addr_ld_reg[15]_1 ,
Q,
axi_rvalid_int_reg,
s_axi_rready,
end_brst_rd,
brst_zero,
s_axi_aresetn,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ,
axi_arsize_pipe,
s_axi_arlen,
axi_araddr_full,
curr_fixed_burst_reg,
s_axi_araddr,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ,
curr_wrap_burst_reg,
axi_rd_burst_two_reg,
axi_rd_burst,
axi_aresetn_d2,
last_bram_addr,
rd_addr_sm_cs,
s_axi_arvalid,
no_ar_ack,
pend_rd_op,
ar_active,
axi_b2b_brst,
axi_arsize_pipe_max,
disable_b2b_brst,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ,
axi_arlen_pipe_1_or_2,
s_axi_aclk);
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
output [0:0]SR;
output \wrap_burst_total_reg[0]_0 ;
output \wrap_burst_total_reg[0]_1 ;
output \wrap_burst_total_reg[0]_2 ;
output \wrap_burst_total_reg[0]_3 ;
output [1:0]E;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
output [13:0]D;
output bram_addr_ld_en;
output \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
output \rd_data_sm_cs_reg[1] ;
output \save_init_bram_addr_ld_reg[15]_0 ;
output \save_init_bram_addr_ld_reg[15]_1 ;
input [3:0]Q;
input axi_rvalid_int_reg;
input s_axi_rready;
input end_brst_rd;
input brst_zero;
input s_axi_aresetn;
input [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
input [0:0]axi_arsize_pipe;
input [3:0]s_axi_arlen;
input axi_araddr_full;
input curr_fixed_burst_reg;
input [13:0]s_axi_araddr;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
input [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
input \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
input \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
input curr_wrap_burst_reg;
input axi_rd_burst_two_reg;
input axi_rd_burst;
input axi_aresetn_d2;
input last_bram_addr;
input rd_addr_sm_cs;
input s_axi_arvalid;
input no_ar_ack;
input pend_rd_op;
input ar_active;
input axi_b2b_brst;
input axi_arsize_pipe_max;
input disable_b2b_brst;
input \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
input axi_arlen_pipe_1_or_2;
input s_axi_aclk;
wire [13:0]D;
wire [1:0]E;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ;
wire \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ;
wire [3:0]\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ;
wire [9:0]\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ;
wire \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ;
wire [3:0]Q;
wire [0:0]SR;
wire ar_active;
wire axi_araddr_full;
wire axi_aresetn_d2;
wire axi_arlen_pipe_1_or_2;
wire [0:0]axi_arsize_pipe;
wire axi_arsize_pipe_max;
wire axi_b2b_brst;
wire axi_rd_burst;
wire axi_rd_burst_two_reg;
wire axi_rvalid_int_reg;
wire bram_addr_ld_en;
wire brst_zero;
wire curr_fixed_burst_reg;
wire curr_wrap_burst_reg;
wire disable_b2b_brst;
wire end_brst_rd;
wire last_bram_addr;
wire no_ar_ack;
wire pend_rd_op;
wire rd_addr_sm_cs;
wire \rd_data_sm_cs_reg[1] ;
wire s_axi_aclk;
wire [13:0]s_axi_araddr;
wire s_axi_aresetn;
wire [3:0]s_axi_arlen;
wire s_axi_arvalid;
wire s_axi_rready;
wire \save_init_bram_addr_ld[10]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[11]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_2__0_n_0 ;
wire \save_init_bram_addr_ld[15]_i_3__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[3]_i_2_n_0 ;
wire \save_init_bram_addr_ld[4]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[4]_i_2_n_0 ;
wire \save_init_bram_addr_ld[5]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[5]_i_2_n_0 ;
wire \save_init_bram_addr_ld[6]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[7]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[8]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld[9]_i_1__0_n_0 ;
wire \save_init_bram_addr_ld_reg[15]_0 ;
wire \save_init_bram_addr_ld_reg[15]_1 ;
wire \save_init_bram_addr_ld_reg_n_0_[10] ;
wire \save_init_bram_addr_ld_reg_n_0_[11] ;
wire \save_init_bram_addr_ld_reg_n_0_[12] ;
wire \save_init_bram_addr_ld_reg_n_0_[13] ;
wire \save_init_bram_addr_ld_reg_n_0_[14] ;
wire \save_init_bram_addr_ld_reg_n_0_[15] ;
wire \save_init_bram_addr_ld_reg_n_0_[3] ;
wire \save_init_bram_addr_ld_reg_n_0_[4] ;
wire \save_init_bram_addr_ld_reg_n_0_[5] ;
wire \save_init_bram_addr_ld_reg_n_0_[6] ;
wire \save_init_bram_addr_ld_reg_n_0_[7] ;
wire \save_init_bram_addr_ld_reg_n_0_[8] ;
wire \save_init_bram_addr_ld_reg_n_0_[9] ;
wire \wrap_burst_total[0]_i_1_n_0 ;
wire \wrap_burst_total[0]_i_5__0_n_0 ;
wire \wrap_burst_total[1]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_1_n_0 ;
wire \wrap_burst_total[2]_i_2_n_0 ;
wire \wrap_burst_total_reg[0]_0 ;
wire \wrap_burst_total_reg[0]_1 ;
wire \wrap_burst_total_reg[0]_2 ;
wire \wrap_burst_total_reg[0]_3 ;
wire \wrap_burst_total_reg_n_0_[0] ;
wire \wrap_burst_total_reg_n_0_[1] ;
wire \wrap_burst_total_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hDF20FFFFDF200000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.O(D[8]));
LUT3 #(
.INIT(8'h5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I2(curr_fixed_burst_reg),
.O(E[0]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [9]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [8]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hE0F0E0FFE0F0E0F0))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ),
.I2(\rd_data_sm_cs_reg[1] ),
.I3(Q[1]),
.I4(Q[3]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5
(.I0(axi_rd_burst_two_reg),
.I1(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h0D00000000000000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6
(.I0(end_brst_rd),
.I1(axi_b2b_brst),
.I2(brst_zero),
.I3(axi_rvalid_int_reg),
.I4(s_axi_rready),
.I5(Q[0]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[12] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[10]),
.O(D[10]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[13] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[11]),
.O(D[11]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[14] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT1 #(
.INIT(2'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.O(E[1]));
LUT5 #(
.INIT(32'hB8BBB888))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[15] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h1))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0
(.I0(bram_addr_ld_en),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ));
LUT5 #(
.INIT(32'h88A80000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ),
.I2(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I4(curr_wrap_burst_reg),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h000000008F00A000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I4(\wrap_burst_total_reg_n_0_[0] ),
.I5(\wrap_burst_total_reg_n_0_[2] ),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h00000000A808FD5D))
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0
(.I0(bram_addr_ld_en),
.I1(s_axi_araddr[0]),
.I2(axi_araddr_full),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg ),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I5(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.O(D[0]));
LUT4 #(
.INIT(16'h6F60))
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AFF6A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h6AAAFFFF6AAA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.O(D[3]));
LUT4 #(
.INIT(16'h9F90))
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.O(D[4]));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hA6AAFFFFA6AA0000))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [4]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [5]),
.I4(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I5(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.O(D[6]));
LUT4 #(
.INIT(16'h7FFF))
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [1]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [0]),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [2]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [3]),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6] ));
LUT5 #(
.INIT(32'h9AFF9A00))
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0
(.I0(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [7]),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1 [6]),
.I3(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0 ),
.I4(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'h0000000000004000))
bram_en_int_i_8
(.I0(Q[0]),
.I1(Q[2]),
.I2(axi_rvalid_int_reg),
.I3(s_axi_rready),
.I4(end_brst_rd),
.I5(brst_zero),
.O(\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11] ));
LUT1 #(
.INIT(2'h1))
bram_rst_b_INST_0
(.I0(s_axi_aresetn),
.O(SR));
LUT6 #(
.INIT(64'h0302030203020300))
\rd_data_sm_cs[1]_i_3
(.I0(Q[0]),
.I1(Q[3]),
.I2(Q[2]),
.I3(Q[1]),
.I4(axi_rd_burst_two_reg),
.I5(axi_rd_burst),
.O(\rd_data_sm_cs_reg[1] ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[10]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[10] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[8]),
.O(\save_init_bram_addr_ld[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[11]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[11] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[9]),
.O(\save_init_bram_addr_ld[11]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h8888888A88888888))
\save_init_bram_addr_ld[15]_i_1__0
(.I0(axi_aresetn_d2),
.I1(\save_init_bram_addr_ld[15]_i_2__0_n_0 ),
.I2(\save_init_bram_addr_ld[15]_i_3__0_n_0 ),
.I3(\save_init_bram_addr_ld_reg[15]_0 ),
.I4(\save_init_bram_addr_ld_reg[15]_1 ),
.I5(last_bram_addr),
.O(bram_addr_ld_en));
LUT6 #(
.INIT(64'h0000000000000054))
\save_init_bram_addr_ld[15]_i_2__0
(.I0(rd_addr_sm_cs),
.I1(axi_araddr_full),
.I2(s_axi_arvalid),
.I3(no_ar_ack),
.I4(pend_rd_op),
.I5(ar_active),
.O(\save_init_bram_addr_ld[15]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\save_init_bram_addr_ld[15]_i_3__0
(.I0(brst_zero),
.I1(s_axi_rready),
.I2(axi_rvalid_int_reg),
.O(\save_init_bram_addr_ld[15]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0040))
\save_init_bram_addr_ld[15]_i_4__0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.O(\save_init_bram_addr_ld_reg[15]_0 ));
LUT5 #(
.INIT(32'hFFFDFFFF))
\save_init_bram_addr_ld[15]_i_5
(.I0(axi_arsize_pipe_max),
.I1(disable_b2b_brst),
.I2(\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg ),
.I3(axi_arlen_pipe_1_or_2),
.I4(axi_araddr_full),
.O(\save_init_bram_addr_ld_reg[15]_1 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[3]_i_1__0
(.I0(\save_init_bram_addr_ld[3]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[1]),
.O(\save_init_bram_addr_ld[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hA282))
\save_init_bram_addr_ld[3]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[3] ),
.I1(\wrap_burst_total_reg_n_0_[1] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[0] ),
.O(\save_init_bram_addr_ld[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[4]_i_1__0
(.I0(\save_init_bram_addr_ld[4]_i_2_n_0 ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[2]),
.O(\save_init_bram_addr_ld[4]_i_1__0_n_0 ));
LUT4 #(
.INIT(16'hA28A))
\save_init_bram_addr_ld[4]_i_2
(.I0(\save_init_bram_addr_ld_reg_n_0_[4] ),
.I1(\wrap_burst_total_reg_n_0_[0] ),
.I2(\wrap_burst_total_reg_n_0_[2] ),
.I3(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\save_init_bram_addr_ld[5]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[5] ),
.I1(\save_init_bram_addr_ld[5]_i_2_n_0 ),
.I2(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I3(\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg ),
.I4(axi_araddr_full),
.I5(s_axi_araddr[3]),
.O(\save_init_bram_addr_ld[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h04))
\save_init_bram_addr_ld[5]_i_2
(.I0(\wrap_burst_total_reg_n_0_[0] ),
.I1(\wrap_burst_total_reg_n_0_[2] ),
.I2(\wrap_burst_total_reg_n_0_[1] ),
.O(\save_init_bram_addr_ld[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[6]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[6] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[4]),
.O(\save_init_bram_addr_ld[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[7]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[7] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[5]),
.O(\save_init_bram_addr_ld[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[8]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[8] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[6]),
.O(\save_init_bram_addr_ld[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\save_init_bram_addr_ld[9]_i_1__0
(.I0(\save_init_bram_addr_ld_reg_n_0_[9] ),
.I1(\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0 ),
.I2(\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg ),
.I3(axi_araddr_full),
.I4(s_axi_araddr[7]),
.O(\save_init_bram_addr_ld[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[10]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[10]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[10] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[11]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[11]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[11] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[12]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[10]),
.Q(\save_init_bram_addr_ld_reg_n_0_[12] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[13]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[11]),
.Q(\save_init_bram_addr_ld_reg_n_0_[13] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[14]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[12]),
.Q(\save_init_bram_addr_ld_reg_n_0_[14] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[15]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(D[13]),
.Q(\save_init_bram_addr_ld_reg_n_0_[15] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[3]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[3]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[4]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[4]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[5]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[5]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[6]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[6]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[7]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[7]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[7] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[8]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[8]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[8] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\save_init_bram_addr_ld_reg[9]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\save_init_bram_addr_ld[9]_i_1__0_n_0 ),
.Q(\save_init_bram_addr_ld_reg_n_0_[9] ),
.R(SR));
LUT6 #(
.INIT(64'h00000000A000C300))
\wrap_burst_total[0]_i_1
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(\wrap_burst_total_reg[0]_0 ),
.I2(\wrap_burst_total_reg[0]_1 ),
.I3(\wrap_burst_total_reg[0]_2 ),
.I4(\wrap_burst_total[0]_i_5__0_n_0 ),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_2
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[2]),
.O(\wrap_burst_total_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[1]),
.O(\wrap_burst_total_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[0]_i_4
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[0]),
.O(\wrap_burst_total_reg[0]_2 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
\wrap_burst_total[0]_i_5__0
(.I0(axi_araddr_full),
.I1(axi_arsize_pipe),
.O(\wrap_burst_total[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h220A880A000A880A))
\wrap_burst_total[1]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(axi_arsize_pipe),
.I2(s_axi_arlen[3]),
.I3(axi_araddr_full),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I5(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.O(\wrap_burst_total[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hA000888800000000))
\wrap_burst_total[2]_i_1
(.I0(\wrap_burst_total[2]_i_2_n_0 ),
.I1(s_axi_arlen[2]),
.I2(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [2]),
.I3(axi_arsize_pipe),
.I4(axi_araddr_full),
.I5(\wrap_burst_total_reg[0]_3 ),
.O(\wrap_burst_total[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hCCA000A0))
\wrap_burst_total[2]_i_2
(.I0(s_axi_arlen[1]),
.I1(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [1]),
.I2(s_axi_arlen[0]),
.I3(axi_araddr_full),
.I4(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [0]),
.O(\wrap_burst_total[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hB8))
\wrap_burst_total[2]_i_3
(.I0(\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3] [3]),
.I1(axi_araddr_full),
.I2(s_axi_arlen[3]),
.O(\wrap_burst_total_reg[0]_3 ));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[0]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[0]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[1]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[1]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\wrap_burst_total_reg[2]
(.C(s_axi_aclk),
.CE(bram_addr_ld_en),
.D(\wrap_burst_total[2]_i_1_n_0 ),
.Q(\wrap_burst_total_reg_n_0_[2] ),
.R(SR));
endmodule
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
bram_rst_a,
bram_clk_a,
bram_en_a,
bram_we_a,
bram_addr_a,
bram_wrdata_a,
bram_rddata_a,
bram_rst_b,
bram_clk_b,
bram_en_b,
bram_we_b,
bram_addr_b,
bram_wrdata_b,
bram_rddata_b);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [15:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input s_axi_awlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [15:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input s_axi_arlock;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *) output bram_rst_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) output bram_clk_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) output bram_en_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) output [3:0]bram_we_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) output [15:0]bram_addr_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) output [31:0]bram_wrdata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) input [31:0]bram_rddata_a;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *) output bram_rst_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) output bram_clk_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *) output bram_en_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *) output [3:0]bram_we_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) output [15:0]bram_addr_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *) output [31:0]bram_wrdata_b;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) input [31:0]bram_rddata_b;
wire [15:0]bram_addr_a;
wire [15:0]bram_addr_b;
wire bram_clk_a;
wire bram_clk_b;
wire bram_en_a;
wire bram_en_b;
wire [31:0]bram_rddata_a;
wire [31:0]bram_rddata_b;
wire bram_rst_a;
wire bram_rst_b;
wire [3:0]bram_we_a;
wire [3:0]bram_we_b;
wire [31:0]bram_wrdata_a;
wire [31:0]bram_wrdata_b;
wire s_axi_aclk;
wire [15:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [7:0]s_axi_arlen;
wire s_axi_arlock;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [15:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [7:0]s_axi_awlen;
wire s_axi_awlock;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_U0_ecc_interrupt_UNCONNECTED;
wire NLW_U0_ecc_ue_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_arready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_awready_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_ctrl_wready_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_bresp_UNCONNECTED;
wire [31:0]NLW_U0_s_axi_ctrl_rdata_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_ctrl_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
(* C_BRAM_ADDR_WIDTH = "14" *)
(* C_BRAM_INST_MODE = "EXTERNAL" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "0" *)
(* C_ECC_TYPE = "0" *)
(* C_FAMILY = "zynq" *)
(* C_FAULT_INJECT = "0" *)
(* C_MEMORY_DEPTH = "16384" *)
(* C_SELECT_XPM = "0" *)
(* C_SINGLE_PORT_BRAM = "0" *)
(* C_S_AXI_ADDR_WIDTH = "16" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_S_AXI_ID_WIDTH = "1" *)
(* C_S_AXI_PROTOCOL = "AXI4" *)
(* C_S_AXI_SUPPORTS_NARROW_BURST = "0" *)
(* downgradeipidentifiedwarnings = "yes" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl U0
(.bram_addr_a(bram_addr_a),
.bram_addr_b(bram_addr_b),
.bram_clk_a(bram_clk_a),
.bram_clk_b(bram_clk_b),
.bram_en_a(bram_en_a),
.bram_en_b(bram_en_b),
.bram_rddata_a(bram_rddata_a),
.bram_rddata_b(bram_rddata_b),
.bram_rst_a(bram_rst_a),
.bram_rst_b(bram_rst_b),
.bram_we_a(bram_we_a),
.bram_we_b(bram_we_b),
.bram_wrdata_a(bram_wrdata_a),
.bram_wrdata_b(bram_wrdata_b),
.ecc_interrupt(NLW_U0_ecc_interrupt_UNCONNECTED),
.ecc_ue(NLW_U0_ecc_ue_UNCONNECTED),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(1'b0),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(1'b0),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_ctrl_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_arready(NLW_U0_s_axi_ctrl_arready_UNCONNECTED),
.s_axi_ctrl_arvalid(1'b0),
.s_axi_ctrl_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_awready(NLW_U0_s_axi_ctrl_awready_UNCONNECTED),
.s_axi_ctrl_awvalid(1'b0),
.s_axi_ctrl_bready(1'b0),
.s_axi_ctrl_bresp(NLW_U0_s_axi_ctrl_bresp_UNCONNECTED[1:0]),
.s_axi_ctrl_bvalid(NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED),
.s_axi_ctrl_rdata(NLW_U0_s_axi_ctrl_rdata_UNCONNECTED[31:0]),
.s_axi_ctrl_rready(1'b0),
.s_axi_ctrl_rresp(NLW_U0_s_axi_ctrl_rresp_UNCONNECTED[1:0]),
.s_axi_ctrl_rvalid(NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED),
.s_axi_ctrl_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_ctrl_wready(NLW_U0_s_axi_ctrl_wready_UNCONNECTED),
.s_axi_ctrl_wvalid(1'b0),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module shifter(
clk, // input
reset_n, // input
enable, // input, used to enable the shifter. if low, no start or restart possible
start, // input, asserted by executor when new triplet available
halt, // input, goes high on test fail. causes the shifter to halt while keeping all its registers unchanged
restart, // input, used to restart shifter on restarting a test
step_mode_tck, // input // high when step mode "tck" active
go_step_tck, // input // high-pulse causes the scan clock timer to resume (if halted in step mode)
data_req, // output
sxr_done, // output
busy, // output
pause_request, // input
drive, // input
mask, // input
expect, // input
sxr_type, // input
sxr_length, // input
bits_processed, // output
//fail, // output
sp_tms, // output
sp_tck, // output
sp_tdo, // output
//sp_tdi, // input
sp_exp, // output
sp_msk, // output
scan_clock_frequency, // input
tap_state_feedback, // input // holds tap state read from tap state monitor (in executor module)
// IMPORTANT: THIS IS THE REALTIME TAP STATE OF THE TARGET !
tap_state_send, // output // sends tap state to tap state monitor (in executor module)
shifter_state, // output, read by rf
scan_clock_timer_state // output
);
`include "parameters_global.v"
input clk;
input reset_n;
input enable;
input start;
input halt;
input restart;
input step_mode_tck;
input go_step_tck;
output reg data_req;
output reg sxr_done;
output reg busy;
input pause_request;
input [`byte_width-1:0] drive;
input [`byte_width-1:0] mask;
input [`byte_width-1:0] expect;
input [`byte_width-1:0] sxr_type;
`include "include_sxr_type.v" // wire to bit assignments
input [`chain_length_width-1:0] sxr_length;
output reg [`chain_length_width-1:0] bits_processed;
input [`byte_width-1:0] scan_clock_frequency; // driven by lcp
output reg sp_tms;
output reg sp_tck;
output reg sp_tdo;
output reg sp_exp;
output reg sp_msk;
//input sp_tdi;
input [`nibble_width-1:0] tap_state_feedback;
output reg [`nibble_width-1:0] tap_state_send;
output reg [`byte_width-1:0] shifter_state;
output [`timer_scan_state_width-1:0] scan_clock_timer_state;
reg ignore_sxr_type;
reg sct_start;
scan_clock_timer sct ( // CS: restart input ?
.clk(clk), // input
.reset_n(reset_n), // input
.delay(scan_clock_frequency), // input
.start(sct_start), // input
.done(sct_done), // output
.step_mode_tck(step_mode_tck), // input
.go_step_tck(go_step_tck), // input, ignored when step_mode_tck is cleared
.timer_scan_state(scan_clock_timer_state) // output
);
always @(posedge clk or negedge reset_n) begin
if (~reset_n)
begin
data_req <= #`DEL 1'b0;
sxr_done <= #`DEL 1'b0;
busy <= #`DEL 1'b0;
sct_start <= #`DEL 1'b0;
sp_tms <= #`DEL init_state_tms;
sp_tck <= #`DEL init_state_tck;
sp_tdo <= #`DEL init_state_tdo;
sp_exp <= #`DEL init_state_exp;
sp_msk <= #`DEL init_state_mask;
bits_processed <= #`DEL `chain_length_width'b0;
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
tap_state_send <= #`DEL TAP_TEST_LOGIG_RESET;
ignore_sxr_type <= #`DEL 0;
end
else
begin
//if (enable && restart)
if (restart)
begin
data_req <= #`DEL 1'b0;
sxr_done <= #`DEL 1'b0;
busy <= #`DEL 1'b0;
sct_start <= #`DEL 1'b0;
sp_tms <= #`DEL init_state_tms;
sp_tck <= #`DEL init_state_tck;
sp_tdo <= #`DEL init_state_tdo;
sp_exp <= #`DEL init_state_exp;
sp_msk <= #`DEL init_state_mask;
bits_processed <= #`DEL `chain_length_width'b0;
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
tap_state_send <= #`DEL TAP_TEST_LOGIG_RESET;
ignore_sxr_type <= #`DEL 0;
end
else
begin
if (halt)
begin
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
end
else
begin
case (shifter_state) // synthesis parallel_case
SHIFTER_STATE_IDLE: //0h
begin
data_req <= #`DEL 1'b0;
sxr_done <= #`DEL 1'b0; // clear sxr done (has been set one state before)
if (enable && start) // starting is allowed if enabled
begin
shifter_state <= #`DEL SHIFTER_STATE_EVAL_TAP_STATE;
end
end
SHIFTER_STATE_EVAL_TAP_STATE: // 01h
begin
case (tap_state_feedback) // synthesis parallel_case
TAP_TEST_LOGIG_RESET:
begin
if (bits_processed == 0)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_1; // 02h // next rti
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_0;
end
end
TAP_RUN_TEST_IDLE:
begin
if (bits_processed == 0)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_3; // 04h // next sel-dr
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_1;
end
end
// DR SCAN BRANCH
TAP_SHIFT_DR:
begin // in this case a triplet has been provided by executor
if (bits_processed < sxr_length)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_1; // 0Ah // next shift-dr
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_2;
end
end
TAP_PAUSE_DR:
begin // A start signal here is accepted if no bits have been processed yet.
// In other words: If a new sxr starts.
if (bits_processed == 0)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2DR_1; // 12h
if (~sxr_type_sir && ~sxr_type_end_state_rti) // sdr AND end state pause-dr requested
begin
ignore_sxr_type <= #`DEL 0;
end
else
begin
ignore_sxr_type <= #`DEL 1;
end
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_3; // F3h
end
end
// IR SCAN BRANCH
TAP_SHIFT_IR:
begin // in this case a triplet has been provided by executor
if (bits_processed < sxr_length)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_1; // 1Dh // next shift-ir
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_7; // F7
end
end
TAP_PAUSE_IR:
begin // A start signal here is accepted if no bits have been processed yet.
// In other words: If a new sxr starts.
if (bits_processed == 0)
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2IR_1; // 25h
if (sxr_type_sir && ~sxr_type_end_state_rti) // sir AND end state pause-ir requested
begin
ignore_sxr_type <= #`DEL 0;
end
else
begin
ignore_sxr_type <= #`DEL 1;
end
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_6; // F6h
end
end
default: // a start command received in other states is invalid:
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_8; // F8h
end
endcase
end
////////////////////////////////////////////////////////////////////////////////////////
// SXR SCAN INITIAL PHASE
SHIFTER_STATE_TLR_TO_SELDR_1: // 02h
begin // clear tms to prepare transition to rti
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tms <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_2;
end
end
SHIFTER_STATE_TLR_TO_SELDR_2: // 03h
begin // set tck to latch tms -> target assumes tap state rti
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_RUN_TEST_IDLE;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_3; // 04h
end
end
SHIFTER_STATE_TLR_TO_SELDR_3: // 04h
begin // clear tck, set tms to prepare transition to select-dr-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 1;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_4;
end
end
SHIFTER_STATE_TLR_TO_SELDR_4: // 05h
begin // set tck to latch tms -> target assumes tap state select-dr-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SELECT_DR_SCAN;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EVAL_SXR_TYPE;
end
end
SHIFTER_STATE_EVAL_SXR_TYPE: // 06h
begin // clear tck, clear/set tms according to sxr type to prepare transition to capture-dr or select-ir-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
if (~sxr_type_sir)
// if any kind of dr-scan, clear tms to prepare transition to capture-dr
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_SELDR_TO_SHIFTDR_1; // 07h
end
else
// if any kind of ir-scan, set tms to prepare transition to select-ir-scan
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_SELDR_TO_SELIR; // 18h
end
sct_start <= #`DEL 1; // start scan clock timer
end
end
///////////////////////////////////////////////////////////////////////////////////////////////
// DR SCAN BRANCH OF TAP CONTROLLER
SHIFTER_STATE_SELDR_TO_SHIFTDR_1: // 07h
begin // set tck to latch tms -> target assumes tap state capture-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_CAPTURE_DR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SELDR_TO_SHIFTDR_2;
end
end
SHIFTER_STATE_SELDR_TO_SHIFTDR_2: // 08h
begin // clear tck, clear tms to prepare transition to shift-dr-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SELDR_TO_SHIFTDR_3;
end
end
SHIFTER_STATE_SELDR_TO_SHIFTDR_3: // 09h
begin // set tck to latch tms -> target assumes tap state shift-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SHIFT_DR;
busy <= #`DEL 1'b1; // notify other shifters to wait in pause-dr
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_1;
end
end
SHIFTER_STATE_SHIFTDR_1: // 0Ah
begin // clear tck -> target outputs (first) scan data bit (selected by bits 2:0 of bits_processed).
// if bits_processed < sxr_length-1 -> clear tms to prepare transition to shift-dr (means stay in shift-dr)
// otherwise set tms to prepare transition to exit-1-dr (means leave shift-dr)
// in shift-xr state these rules apply:
// 1) tck falling edge -> tdo updates to bit 0,1,2,...
// 2) tck rising edge -> tdi samples bit 0,1,2,...
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tdo <= #`DEL drive[bits_processed[2:0]];
sp_exp <= #`DEL expect[bits_processed[2:0]];
sp_msk <= #`DEL mask[bits_processed[2:0]];
sct_start <= #`DEL 1; // start scan clock timer
// for all bits_processed except second-to-last and last:
if (bits_processed < sxr_length - 1)
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_2; // 0Bh // sample bit, stay in shift-dr
end
else
if (bits_processed == sxr_length - 1) // if second-to-last bit beeing processed
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_4; // sample last bit, prepare transition to exit-1-dr
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_11; // FBh
end
end
end
SHIFTER_STATE_SHIFTDR_2: // 0Bh
begin // set tck to latch tms -> target remains in tap state shift-dr / target samples tdi / bit processed
// on rising tck edge, increment bits_processed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SHIFT_DR;
sct_start <= #`DEL 1; // start scan clock timer
bits_processed <= #`DEL bits_processed + 1;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_3; // evaluate bits_processed
end
end
SHIFTER_STATE_SHIFTDR_3: // 0Ch
begin // if 8 bits have been processed, go to idle state and wait for next start signal
// target remains in shift-dr while next triplet is being provided
// otherwise proceed with next bit
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (bits_processed[2:0] == 0) // || bits_processed[3:0] == 0)
// the lowest nibble of bits_processed is 8 after 8 processed bits
// they overflow to zero after another 8 bits
begin
//tap_state_send <= #`DEL TAP_SHIFT_DR;
data_req <= #`DEL 1'b1; // notify executor that triplet has been processed
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_SHIFTDR_1; // 0Ah
end
end
SHIFTER_STATE_SHIFTDR_4: // 0Dh
begin // set tck to latch tms -> target assumes tap state exit-1-dr / target samples tdi one last time / last bit processed
// on rising tck edge, increment bits_processed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_EXIT1_DR;
sct_start <= #`DEL 1; // start scan clock timer
bits_processed <= #`DEL bits_processed + 1;
shifter_state <= #`DEL SHIFTER_STATE_EXIT1DR_1; // 0Eh
end
end
SHIFTER_STATE_EXIT1DR_1: // 0Eh
begin // clear tck, clear tms to prepare transition to pause-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_PAUSEDR_1;
end
end
SHIFTER_STATE_PAUSEDR_1: // 0Fh
begin // set tck to latch tms -> target assumes tap state pause-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_PAUSE_DR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_PAUSEDR_2;
end
end
// NOTE: in pause-dr: tck halts (no toggeling)
// tck continues once all shifters have cleared their busy output
// (all busy signals are ORed in executor to signal pause_request)
// this ensures a synchronized proceeding of all shifters
SHIFTER_STATE_PAUSEDR_2: // 10h
begin // clear busy signal so that other waiting shfiters can proceed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
busy <= #`DEL 1'b0; // notify other shifters that shifting is complete
shifter_state <= #`DEL SHIFTER_STATE_PAUSEDR_3; // 11h
end
end
SHIFTER_STATE_PAUSEDR_3: // 11h
begin // if no more pause requests, proceed to exit2-dr (if endstate rti) or idle (if endstate pause-dr)
if (pause_request == 0)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 1;
if (sxr_type_end_state_rti)
// if endstate is rti, proceed to exit2-dr
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2DR_1; // 12h
end
else
// if endstate is pause-dr, proceed to idle and wait for start signal
begin
sxr_done <= #`DEL 1'b1; // notify executor, that sxr is done
bits_processed <= #`DEL 0; // clear bit counter
shifter_state <= #`DEL SHIFTER_STATE_IDLE; // 00h
end
end
end
SHIFTER_STATE_EXIT2DR_1: // 12h
begin // set tck to latch tms -> target assumes tap state exit2-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_EXIT2_DR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2DR_2;
end
end
SHIFTER_STATE_EXIT2DR_2: // 13h
begin // clear tck.
// set tms to prepare transition to update-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_UPDATEDR_1;
end
end
SHIFTER_STATE_UPDATEDR_1: // 14h
begin // set tck to latch tms -> target assumes tap state update-dr
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_UPDATE_DR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_UPDATEDR_2; // 15h
end
end
SHIFTER_STATE_UPDATEDR_2: // 15h
begin // clear tck.
// according to required end state, clear/set tms to prepare transition to rti or select-dr-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
if (ignore_sxr_type)
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_4; // 05h // next: select-dr-scan
end
else
begin
if (sxr_type_end_state_rti)
// if end state (of ending sxr) is run-test/idle, clear tms to prepare transition to run-test/idle
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_RTI_1; // 16h // next: rti
end
else
// if end state (of begining sxr) is pause-dr, set tms to prepare transition to select-dr-scan
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_4; // 05h // next: select-dr-scan
end
end
ignore_sxr_type <= #`DEL 0;
end
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RETURN FROM UPDATE-XR TO RTI OR SELECT-DR-SCAN
SHIFTER_STATE_RTI_1: // 16h
begin // set tck to latch tms -> target assumes tap state rti (coming from update-dr)
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_RUN_TEST_IDLE;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_RTI_2; // 17h
end
end
SHIFTER_STATE_RTI_2: // 17h
begin // clear tck.
// whatever endstate is required, go to SHIFTER_STATE_IDLE and wait for start signal
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 1;
bits_processed <= #`DEL 0; // clear bit counter
sxr_done <= #`DEL 1'b1; // notify executor, that sxr is done
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// IR SCAN BRANCH OF TAP CONTROLLER
SHIFTER_STATE_SELDR_TO_SELIR: // 18h
begin // set tck to latch tms -> target assumes tap state select-ir-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SELECT_IR_SCAN;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SELIR_TO_SHIFTIR_1; // 19h
end
end
SHIFTER_STATE_SELIR_TO_SHIFTIR_1: // 19h
begin // clear tck, clear/set tms according to sxr type to prepare transition to capture-ir (or test-logic-reset ?)
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
if (sxr_type_sir)
// if any kind of ir-scan, set tms to prepare transition to capture-ir
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_SELIR_TO_SHIFTIR_2; // 1Ah
end
else
// other sxr types drive the executor in error state // CS: move to tlr instead ?
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_4; // F4h
end
sct_start <= #`DEL 1; // start scan clock timer
end
end
SHIFTER_STATE_SELIR_TO_SHIFTIR_2: // 1Ah
begin // set tck to latch tms -> target assumes tap state capture-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_CAPTURE_IR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SELIR_TO_SHIFTIR_3; // 1Bh
end
end
SHIFTER_STATE_SELIR_TO_SHIFTIR_3: // 1Bh
begin // clear tck, clear tms to prepare transition to shift-ir-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SELIR_TO_SHIFTIR_4; // 1Ch
end
end
SHIFTER_STATE_SELIR_TO_SHIFTIR_4: // 1Ch
begin // set tck to latch tms -> target assumes tap state shift-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SHIFT_IR;
busy <= #`DEL 1'b1; // notify other shifters to wait in pause-ir
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_1; // 1Dh
end
end
SHIFTER_STATE_SHIFTIR_1: // 1Dh
begin // clear tck -> target outputs (first) scan data bit (selected by bits 2:0 of bits_processed).
// if bits_processed < sxr_length-1 -> clear tms to prepare transition to shift-ir (means stay in shift-ir)
// otherwise set tms to prepare transition to exit-1-ir (means leave shift-ir)
// in shift-xr state these rules apply:
// 1) tck falling edge -> tdo updates to bit 0,1,2,...
// 2) tck rising edge -> tdi samples bit 0,1,2,...
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tdo <= #`DEL drive[bits_processed[2:0]];
sp_exp <= #`DEL expect[bits_processed[2:0]];
sp_msk <= #`DEL mask[bits_processed[2:0]];
sct_start <= #`DEL 1; // start scan clock timer
// for all bits_processed except second-to-last and last:
if (bits_processed < sxr_length - 1)
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_2; // 1Eh // sample bit, stay in shift-ir
end
else
if (bits_processed == sxr_length - 1) // if second-to-last bit beeing processed
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_4; // 20h // sample last bit, prepare transition to exit-1-ir
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_ERROR_5; // F5h
end
end
end
SHIFTER_STATE_SHIFTIR_2: // 1Eh
begin // set tck to latch tms -> target remains in tap state shift-ir / target samples tdi / bit processed
// on rising tck edge, increment bits_processed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_SHIFT_IR;
sct_start <= #`DEL 1; // start scan clock timer
bits_processed <= #`DEL bits_processed + 1;
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_3; // 1Fh // evaluate bits_processed
end
end
SHIFTER_STATE_SHIFTIR_3: // 1Fh
begin // if 8 bits have been processed, go to idle state and wait for next start signal
// target remains in shift-ir while next triplet is being provided
// otherwise proceed with next bit
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (bits_processed[2:0] == 0) // || bits_processed[3:0] == 0)
// the lowest nibble of bits_processed is 8 after 8 processed bits
// they overflow to zero after another 8 bits
begin
data_req <= #`DEL 1'b1; // notify executor that triplet has been processed
shifter_state <= #`DEL SHIFTER_STATE_IDLE;
end
else
begin
shifter_state <= #`DEL SHIFTER_STATE_SHIFTIR_1; // 1Dh
end
end
SHIFTER_STATE_SHIFTIR_4: // 20h
begin // set tck to latch tms -> target assumes tap state exit-1-ir / target samples tdi one last time / last bit processed
// on rising tck edge, increment bits_processed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_EXIT1_IR;
sct_start <= #`DEL 1; // start scan clock timer
bits_processed <= #`DEL bits_processed + 1;
shifter_state <= #`DEL SHIFTER_STATE_EXIT1IR_1; // 21h
end
end
SHIFTER_STATE_EXIT1IR_1: // 21h
begin // clear tck, clear tms to prepare transition to pause-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_PAUSEIR_1; // 22h
end
end
SHIFTER_STATE_PAUSEIR_1: // 22h
begin // set tck to latch tms -> target assumes tap state pause-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_PAUSE_IR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_PAUSEIR_2; // 23h
end
end
// NOTE: in pause-dr: tck halts (no toggeling)
// tck continues once all shifters have cleared their busy output
// (all busy signals are ORed in executor to signal pause_request)
// this ensures a synchronized proceeding of all shifters
SHIFTER_STATE_PAUSEIR_2: // 23h
begin // clear busy signal so that other waiting shfiters can proceed
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
busy <= #`DEL 1'b0; // notify other shifters that shifting is complete
shifter_state <= #`DEL SHIFTER_STATE_PAUSEIR_3; // 24h
end
end
SHIFTER_STATE_PAUSEIR_3: // 24h
begin // if no more pause requests, proceed to exit2-ir (if endstate rti) or idle (if endstate pause-ir)
if (pause_request == 0)
begin
sp_tck <= #`DEL 0;
sp_tms <= #`DEL 1;
if (sxr_type_end_state_rti)
// if endstate is rti, proceed to exit2-ir
begin
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2IR_1; // 25h
end
else
// if endstate is pause-ir, proceed to idle and wait for start signal
begin
sxr_done <= #`DEL 1'b1; // notify executor, that sxr is done
bits_processed <= #`DEL 0; // clear bit counter
shifter_state <= #`DEL SHIFTER_STATE_IDLE; // 00h
end
end
end
SHIFTER_STATE_EXIT2IR_1: // 25h
begin // set tck to latch tms -> target assumes tap state exit2-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_EXIT2_IR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_EXIT2IR_2; // 26h
end
end
SHIFTER_STATE_EXIT2IR_2: // 26h
begin // clear tck.
// set tms to prepare transition to update-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_UPDATEIR_1; // 27h
end
end
SHIFTER_STATE_UPDATEIR_1: // 27h
begin // set tck to latch tms -> target assumes tap state update-ir
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 1;
tap_state_send <= #`DEL TAP_UPDATE_IR;
sct_start <= #`DEL 1; // start scan clock timer
shifter_state <= #`DEL SHIFTER_STATE_UPDATEIR_2; // 28h
end
end
SHIFTER_STATE_UPDATEIR_2: // 28h
begin // clear tck.
// according to required end state, clear/set tms to prepare transition to rti or select-dr-scan
sct_start <= #`DEL 0; // clear scan clock timer start signal
if (sct_done)
begin
sp_tck <= #`DEL 0;
sct_start <= #`DEL 1; // start scan clock timer
if (ignore_sxr_type)
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_4; // 05h // next: select-dr-scan
end
else
begin
if (sxr_type_end_state_rti)
// if end state run-test/idle required, clear tms to prepare transition to run-test/idle
begin
sp_tms <= #`DEL 0;
shifter_state <= #`DEL SHIFTER_STATE_RTI_1; // 16h // next: rti
end
else
// if end state pause-ir required, set tms to prepare transition to select-dr-scan
begin
sp_tms <= #`DEL 1;
shifter_state <= #`DEL SHIFTER_STATE_TLR_TO_SELDR_4; // 05h // next: select-dr-scan
end
end
ignore_sxr_type <= #`DEL 0;
end
end
endcase
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_4_V
`define SKY130_FD_SC_HS__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND3B_BEHAVIORAL_PP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND3B_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:47:35 03/24/2015
// Design Name:
// Module Name: clk_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: DIV min is 2, don't do 1 or 0
//
//////////////////////////////////////////////////////////////////////////////////
module clk_divider #(
parameter DIV = 2
)(
input rst,
input clk,
output div_clk
);
parameter CTR_SIZE = $clog2(DIV);
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg div_clk_d, div_clk_q;
assign div_clk = div_clk_q;
always @(*) begin
div_clk_d = div_clk_q;
ctr_d = ctr_q + 1;
//Div clk goes high at 0, and lasts period of clk
if (ctr_q == 0) begin
div_clk_d = 1;
end else begin
div_clk_d = 0;
end
//Restart when reach DIV cnts
if(ctr_q == DIV-1) begin
ctr_d = 0;
end
end
always @(posedge clk) begin
if (rst) begin
div_clk_q <= 0;
ctr_q <= 0;
end else begin
div_clk_q <= div_clk_d;
ctr_q <= ctr_d;
end
end
endmodule
|
// hps_design_SMP_HPS.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_SMP_HPS #(
parameter F2S_Width = 0,
parameter S2F_Width = 0
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_lw_axi_clk, // h2f_lw_axi_clock.clk
output wire [11:0] h2f_lw_AWID, // h2f_lw_axi_master.awid
output wire [20:0] h2f_lw_AWADDR, // .awaddr
output wire [3:0] h2f_lw_AWLEN, // .awlen
output wire [2:0] h2f_lw_AWSIZE, // .awsize
output wire [1:0] h2f_lw_AWBURST, // .awburst
output wire [1:0] h2f_lw_AWLOCK, // .awlock
output wire [3:0] h2f_lw_AWCACHE, // .awcache
output wire [2:0] h2f_lw_AWPROT, // .awprot
output wire h2f_lw_AWVALID, // .awvalid
input wire h2f_lw_AWREADY, // .awready
output wire [11:0] h2f_lw_WID, // .wid
output wire [31:0] h2f_lw_WDATA, // .wdata
output wire [3:0] h2f_lw_WSTRB, // .wstrb
output wire h2f_lw_WLAST, // .wlast
output wire h2f_lw_WVALID, // .wvalid
input wire h2f_lw_WREADY, // .wready
input wire [11:0] h2f_lw_BID, // .bid
input wire [1:0] h2f_lw_BRESP, // .bresp
input wire h2f_lw_BVALID, // .bvalid
output wire h2f_lw_BREADY, // .bready
output wire [11:0] h2f_lw_ARID, // .arid
output wire [20:0] h2f_lw_ARADDR, // .araddr
output wire [3:0] h2f_lw_ARLEN, // .arlen
output wire [2:0] h2f_lw_ARSIZE, // .arsize
output wire [1:0] h2f_lw_ARBURST, // .arburst
output wire [1:0] h2f_lw_ARLOCK, // .arlock
output wire [3:0] h2f_lw_ARCACHE, // .arcache
output wire [2:0] h2f_lw_ARPROT, // .arprot
output wire h2f_lw_ARVALID, // .arvalid
input wire h2f_lw_ARREADY, // .arready
input wire [11:0] h2f_lw_RID, // .rid
input wire [31:0] h2f_lw_RDATA, // .rdata
input wire [1:0] h2f_lw_RRESP, // .rresp
input wire h2f_lw_RLAST, // .rlast
input wire h2f_lw_RVALID, // .rvalid
output wire h2f_lw_RREADY, // .rready
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [1:0] mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
hps_design_SMP_HPS_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_lw_axi_clk (h2f_lw_axi_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (h2f_lw_AWID), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (h2f_lw_AWADDR), // .awaddr
.h2f_lw_AWLEN (h2f_lw_AWLEN), // .awlen
.h2f_lw_AWSIZE (h2f_lw_AWSIZE), // .awsize
.h2f_lw_AWBURST (h2f_lw_AWBURST), // .awburst
.h2f_lw_AWLOCK (h2f_lw_AWLOCK), // .awlock
.h2f_lw_AWCACHE (h2f_lw_AWCACHE), // .awcache
.h2f_lw_AWPROT (h2f_lw_AWPROT), // .awprot
.h2f_lw_AWVALID (h2f_lw_AWVALID), // .awvalid
.h2f_lw_AWREADY (h2f_lw_AWREADY), // .awready
.h2f_lw_WID (h2f_lw_WID), // .wid
.h2f_lw_WDATA (h2f_lw_WDATA), // .wdata
.h2f_lw_WSTRB (h2f_lw_WSTRB), // .wstrb
.h2f_lw_WLAST (h2f_lw_WLAST), // .wlast
.h2f_lw_WVALID (h2f_lw_WVALID), // .wvalid
.h2f_lw_WREADY (h2f_lw_WREADY), // .wready
.h2f_lw_BID (h2f_lw_BID), // .bid
.h2f_lw_BRESP (h2f_lw_BRESP), // .bresp
.h2f_lw_BVALID (h2f_lw_BVALID), // .bvalid
.h2f_lw_BREADY (h2f_lw_BREADY), // .bready
.h2f_lw_ARID (h2f_lw_ARID), // .arid
.h2f_lw_ARADDR (h2f_lw_ARADDR), // .araddr
.h2f_lw_ARLEN (h2f_lw_ARLEN), // .arlen
.h2f_lw_ARSIZE (h2f_lw_ARSIZE), // .arsize
.h2f_lw_ARBURST (h2f_lw_ARBURST), // .arburst
.h2f_lw_ARLOCK (h2f_lw_ARLOCK), // .arlock
.h2f_lw_ARCACHE (h2f_lw_ARCACHE), // .arcache
.h2f_lw_ARPROT (h2f_lw_ARPROT), // .arprot
.h2f_lw_ARVALID (h2f_lw_ARVALID), // .arvalid
.h2f_lw_ARREADY (h2f_lw_ARREADY), // .arready
.h2f_lw_RID (h2f_lw_RID), // .rid
.h2f_lw_RDATA (h2f_lw_RDATA), // .rdata
.h2f_lw_RRESP (h2f_lw_RRESP), // .rresp
.h2f_lw_RLAST (h2f_lw_RLAST), // .rlast
.h2f_lw_RVALID (h2f_lw_RVALID), // .rvalid
.h2f_lw_RREADY (h2f_lw_RREADY) // .rready
);
hps_design_SMP_HPS_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
`timescale 1ns / 100ps
module sasc_brg(/*AUTOARG*/
// Outputs
sio_ce, sio_ce_x4,
// Inputs
clk, arst_n
);
output sio_ce; // baud rate
output sio_ce_x4; // baud rate x 4
input clk;
input arst_n;
reg sio_ce;
reg sio_ce_x4;
parameter br_38400_16MHz = 103; // 16e6 / (38400*4) = 104 = 103 + 1
`define BRX4pre &{brx4_cntr[6:5],brx4_cntr[2:0]}
reg [6:0] brx4_cntr;
reg [1:0] br_cntr;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
brx4_cntr <= 0;
else if (`BRX4pre)
brx4_cntr <= 0;
else
brx4_cntr <= brx4_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
br_cntr <= 0;
else if (`BRX4pre)
br_cntr <= br_cntr + 1'b1;
always @ (posedge clk or negedge arst_n)
if (~arst_n)
begin
sio_ce_x4 <= 1'b0;
sio_ce <= 1'b0;
end
else
begin
sio_ce_x4 <= `BRX4pre;
sio_ce <= (&br_cntr) & (`BRX4pre);
end
endmodule // sasc_brg
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Implements store buffer. ////
//// ////
//// To Do: ////
//// - byte combining ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sb.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.2 2002/08/22 02:18:55 lampret
// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
//
// Revision 1.1 2002/08/18 19:53:08 lampret
// Added store buffer.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sb(
// RISC clock, reset
clk, rst,
// Internal RISC bus (DC<->SB)
dcsb_dat_i, dcsb_adr_i, dcsb_cyc_i, dcsb_stb_i, dcsb_we_i, dcsb_sel_i, dcsb_cab_i,
dcsb_dat_o, dcsb_ack_o, dcsb_err_o,
// BIU bus
sbbiu_dat_o, sbbiu_adr_o, sbbiu_cyc_o, sbbiu_stb_o, sbbiu_we_o, sbbiu_sel_o, sbbiu_cab_o,
sbbiu_dat_i, sbbiu_ack_i, sbbiu_err_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// RISC clock, reset
//
input clk; // RISC clock
input rst; // RISC reset
//
// Internal RISC bus (DC<->SB)
//
input [dw-1:0] dcsb_dat_i; // input data bus
input [aw-1:0] dcsb_adr_i; // address bus
input dcsb_cyc_i; // WB cycle
input dcsb_stb_i; // WB strobe
input dcsb_we_i; // WB write enable
input dcsb_cab_i; // CAB input
input [3:0] dcsb_sel_i; // byte selects
output [dw-1:0] dcsb_dat_o; // output data bus
output dcsb_ack_o; // ack output
output dcsb_err_o; // err output
//
// BIU bus
//
output [dw-1:0] sbbiu_dat_o; // output data bus
output [aw-1:0] sbbiu_adr_o; // address bus
output sbbiu_cyc_o; // WB cycle
output sbbiu_stb_o; // WB strobe
output sbbiu_we_o; // WB write enable
output sbbiu_cab_o; // CAB input
output [3:0] sbbiu_sel_o; // byte selects
input [dw-1:0] sbbiu_dat_i; // input data bus
input sbbiu_ack_i; // ack output
input sbbiu_err_i; // err output
`ifdef OR1200_SB_IMPLEMENTED
//
// Internal wires and regs
//
wire [4+dw+aw-1:0] fifo_dat_i; // FIFO data in
wire [4+dw+aw-1:0] fifo_dat_o; // FIFO data out
wire fifo_wr;
wire fifo_rd;
wire fifo_full;
wire fifo_empty;
wire sel_sb;
reg outstanding_store;
reg fifo_wr_ack;
//
// FIFO data in/out
//
assign fifo_dat_i = {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
assign {sbbiu_sel_o, sbbiu_dat_o, sbbiu_adr_o} = sel_sb ? fifo_dat_o : {dcsb_sel_i, dcsb_dat_i, dcsb_adr_i};
//
// Control
//
assign fifo_wr = dcsb_cyc_i & dcsb_stb_i & dcsb_we_i & ~fifo_full & ~fifo_wr_ack;
assign fifo_rd = ~outstanding_store;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sel_sb ? fifo_wr_ack : sbbiu_ack_i;
assign dcsb_err_o = sel_sb ? 1'b0 : sbbiu_err_i; // SB never returns error
assign sbbiu_cyc_o = sel_sb ? outstanding_store : dcsb_cyc_i;
assign sbbiu_stb_o = sel_sb ? outstanding_store : dcsb_stb_i;
assign sbbiu_we_o = sel_sb ? 1'b1 : dcsb_we_i;
assign sbbiu_cab_o = sel_sb ? 1'b0 : dcsb_cab_i;
assign sel_sb = ~fifo_empty | (fifo_empty & outstanding_store); // | fifo_wr;
//
// Store buffer FIFO instantiation
//
or1200_sb_fifo or1200_sb_fifo (
.clk_i(clk),
.rst_i(rst),
.dat_i(fifo_dat_i),
.wr_i(fifo_wr),
.rd_i(fifo_rd),
.dat_o(fifo_dat_o),
.full_o(fifo_full),
.empty_o(fifo_empty)
);
//
// fifo_rd
//
always @(posedge clk or posedge rst)
if (rst)
outstanding_store <= #1 1'b0;
else if (sbbiu_ack_i)
outstanding_store <= #1 1'b0;
else if (sel_sb | fifo_wr)
outstanding_store <= #1 1'b1;
//
// fifo_wr_ack
//
always @(posedge clk or posedge rst)
if (rst)
fifo_wr_ack <= #1 1'b0;
else if (fifo_wr)
fifo_wr_ack <= #1 1'b1;
else
fifo_wr_ack <= #1 1'b0;
`else // !OR1200_SB_IMPLEMENTED
assign sbbiu_dat_o = dcsb_dat_i;
assign sbbiu_adr_o = dcsb_adr_i;
assign sbbiu_cyc_o = dcsb_cyc_i;
assign sbbiu_stb_o = dcsb_stb_i;
assign sbbiu_we_o = dcsb_we_i;
assign sbbiu_cab_o = dcsb_cab_i;
assign sbbiu_sel_o = dcsb_sel_i;
assign dcsb_dat_o = sbbiu_dat_i;
assign dcsb_ack_o = sbbiu_ack_i;
assign dcsb_err_o = sbbiu_err_i;
`endif
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : fetch_ctrl.v
// Author : Yufeng Bai
// Email : [email protected]
// Created On : 2015-04-30
//
//-------------------------------------------------------------------
//
// Modified : 2014-08-18 by HLL
// Description : db supported
// Modified : 2015-09-02 by HLL
// Description : db rearranged to next pipeline
// Modified : 2015-09-05 by HLL
// Description : intra supported
// Modified : 2015-09-16 by HLL
// Description : cur_chroma provided in the order of uvuvuv...
// Modified : 2015-09-17 by HLL
// Description : ref_chroma provided in the order of uvuvuv...
// Modified : 2015-09-19 by HLL
// Description : load_db_chroma & store_db_chroma provided in the order of uvuvuv...
// more modes connected out
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module fetch_ctrl (
clk ,
rstn ,
sysif_start_i ,
sysif_type_i ,
sysif_done_o ,
sysif_total_x_i ,
sysif_total_y_i ,
sysif_fime_y_o ,
sysif_fme_y_o ,
sysif_mc_y_o ,
cimv_pre_i ,
cimv_fme_i ,
cur_luma_done_o ,
cur_luma_data_o ,
cur_luma_valid_o ,
cur_luma_addr_o ,
cur_chroma_done_o ,
cur_chroma_data_o ,
cur_chroma_valid_o ,
cur_chroma_addr_o ,
ref_luma_done_o ,
ref_luma_data_o ,
ref_luma_valid_o ,
ref_luma_addr_o ,
ref_chroma_done_o ,
ref_chroma_data_o ,
ref_chroma_valid_o ,
ref_chroma_addr_o ,
db_store_addr_o ,
db_store_en_o ,
db_store_data_i ,
db_store_done_o ,
db_ref_addr_o ,
db_ref_en_o ,
db_ref_data_o ,
extif_start_o ,
extif_done_i ,
extif_mode_o ,
extif_x_o ,
extif_y_o ,
extif_width_o ,
extif_height_o ,
extif_wren_i ,
extif_rden_i ,
extif_data_i ,
extif_data_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] sysif_start_i ; // "system interface
output [1-1:0] sysif_done_o ; // "system interface
input sysif_type_i ;
input [`PIC_X_WIDTH-1:0] sysif_total_x_i ; // "system interface
input [`PIC_Y_WIDTH-1:0] sysif_total_y_i ; // "system interface
output [8-1:0] sysif_fime_y_o ; // cur fime y num
output [8-1:0] sysif_fme_y_o ; // cur fme y num
output [8-1:0] sysif_mc_y_o ; // cur fme y num
input [20-1:0] cimv_pre_i ; // cime mv
input [20-1:0] cimv_fme_i ; // fme mv
output [1-1:0] cur_luma_done_o ; // write current lcu done
output [32*`PIXEL_WIDTH-1:0] cur_luma_data_o ; // write current lcu data
output [1-1:0] cur_luma_valid_o ; // write current lcu data valid
output [7-1:0] cur_luma_addr_o ; // write current lcu data address
output [1-1:0] cur_chroma_done_o ; // write current lcu done
output [32*`PIXEL_WIDTH-1:0] cur_chroma_data_o ; // write current lcu data
output [1-1:0] cur_chroma_valid_o ; // write current lcu data valid
output [6-1:0] cur_chroma_addr_o ; // write current lcu data address
output [1-1:0] ref_luma_done_o ; // write ref lcu done
output [96*`PIXEL_WIDTH-1:0] ref_luma_data_o ; // write ref lcu data
output [1-1:0] ref_luma_valid_o ; // write ref data valid
output [7-1:0] ref_luma_addr_o ; // write ref luma addr
output [1-1:0] ref_chroma_done_o ; // write ref lcu done
output [96*`PIXEL_WIDTH-1:0] ref_chroma_data_o ; // write ref lcu data
output ref_chroma_valid_o ; // write ref data valid
output [6-1:0] ref_chroma_addr_o ; // write ref chroma addr
output reg [8-1:0] db_store_addr_o ; // read db_pixel ram address
output [1-1:0] db_store_en_o ; // read db_pixel ram enable
input [32*`PIXEL_WIDTH-1:0] db_store_data_i ; // read db_pixel ram data
output db_store_done_o ;
output [5-1:0] db_ref_addr_o ; // write db_ref ram address
output [1-1:0] db_ref_en_o ; // write db_ref ram enable
output [16*`PIXEL_WIDTH-1:0] db_ref_data_o ; // write db_ref ram data
output [1-1:0] extif_start_o ; // ext mem load start
input [1-1:0] extif_done_i ; // ext mem load done
output [5-1:0] extif_mode_o ; // "ext mode: {load/store} {luma
output [6+`PIC_X_WIDTH-1:0] extif_x_o ; // x in ref frame
output [6+`PIC_Y_WIDTH-1:0] extif_y_o ; // y in ref frame
output [8-1:0] extif_width_o ; // ref window width
output [8-1:0] extif_height_o ; // ref window height
input extif_wren_i ; // write sram enable
input extif_rden_i ; // read sram enable
input [16*`PIXEL_WIDTH-1:0] extif_data_i ; // ext data input
output [16*`PIXEL_WIDTH-1:0] extif_data_o ; // ext data output
// ********************************************
//
// PARAMETER DECLARATION
//
// ********************************************
parameter INTRA = 0 ,
INTER = 1 ;
parameter AXI_WIDTH = 'd128;
localparam AXI_WIDTH_PIXEL = AXI_WIDTH / `PIXEL_WIDTH ;
parameter IDLE = 'd00; // //
parameter P1 = 'd01; // CIME // PRELOA
parameter P2 = 'd02; // CIME,PRELOA // PRELOA,PRE_I
parameter P3 = 'd03; // CIME,PRELOA,FIME // PRELOA,PRE_I,INTRA
parameter P4 = 'd04; // CIME,PRELOA,FIME,FME // PRELOA,PRE_I,INTRA,DB
parameter P5 = 'd05; // CIME,PRELOA,FIME,FME,MC // PRE_I,INTRA,DB
parameter P6 = 'd06; // CIME,PRELOA,FIME,FME,MC,DB // INTRA,DB
parameter P7 = 'd07; // PRELOA,FIME,FME,MC,DB // DB
parameter P8 = 'd08; // FIME,FME,MC,DB // CABAC
parameter P9 = 'd09; // FME,MC,DB //
parameter P10 = 'd10; // MC,DB //
parameter P11 = 'd11; // DB //
parameter P12 = 'd12; // CABCA //
parameter LOAD_CUR_SUB = 01 ,
LOAD_REF_SUB = 02 ,
LOAD_CUR_LUMA = 03 ,
LOAD_REF_LUMA = 04 ,
LOAD_CUR_CHROMA = 05 ,
LOAD_REF_CHROMA = 06 ,
LOAD_DB_LUMA = 07 ,
LOAD_DB_CHROMA = 08 ,
STORE_DB_LUMA = 09 ,
STORE_DB_CHROMA = 10 ;
parameter DB_STORE_IDLE = 0 ,
DB_STORE_LUMA_PRE = 1 ,
DB_STORE_LUMA_CUR = 2 ,
DB_STORE_CHRO_PRE = 3 ,
DB_STORE_CHRO_CUR = 4 ;
// ********************************************
//
// WIRE / REG DECLARATION
//
// ********************************************
reg sysif_start_r;
reg cime, preload, fime, fme, mc, db;
reg pre_i, intra;
reg [3:0] current_state, next_state;
reg [4:0] current_fetch, next_fetch;
reg [7:0] first_x,first_y ;
reg [7:0] pre_x ,pre_y ;
reg [7:0] fime_x,fime_y ;
reg [7:0] fme_x ,fme_y ;
reg [7:0] mc_x ,mc_y ;
reg [7:0] db_0_x ,db_0_y ;
reg [7:0] db_1_x ,db_1_y ;
reg [7:0] db_2_x ,db_2_y ;
reg [7:0] pre_i_x ,pre_i_y ;
reg [7:0] intra_x ,intra_y ;
reg store_db_done ;
wire store_db ;
reg [11:0] luma_ref_x_s,luma_ref_y_s,
luma_ref_x_s_r1,luma_ref_x_s_r2,
luma_ref_y_s_r1,luma_ref_y_s_r2;
reg [7:0] luma_ref_height,luma_ref_height_r1,luma_ref_height_r2;
wire signed [10-1:0] cimv_pre_i_x,cimv_pre_i_y;
reg [AXI_WIDTH-1:0] extif_data_0;
reg [AXI_WIDTH-1:0] extif_data_1;
reg [AXI_WIDTH-1:0] extif_data_2;
reg [AXI_WIDTH-1:0] extif_data_3;
reg [AXI_WIDTH-1:0] extif_data_4;
reg [1:0] cur_luma_cnt;
reg [2:0] ref_luma_cnt;
reg [1:0] cur_chroma_cnt;
reg [2:0] ref_chroma_cnt;
reg [6 : 0] cur_luma_addr ;
reg [5 : 0] cur_chroma_addr ;
reg [6 : 0] ref_luma_addr_o ;
reg [5 : 0] ref_chroma_addr ;
reg [8 : 0] db_store_addr_r ;
reg [8 : 0] db_store_addr_w ;
reg [4 : 0] db_ref_addr_o ;
reg [5-1:0] extif_mode_o ; // "ext mode: {load/store} {luma
reg [6+`PIC_X_WIDTH-1:0] extif_x_o; // x in ref frame
reg [6+`PIC_Y_WIDTH-1:0] extif_y_o; // y in ref frame
reg [8-1:0] extif_width_o ; // ref window width
reg [8-1:0] extif_height_o ; // ref window height
reg [96*`PIXEL_WIDTH-1:0] ref_luma_data_o; // write ref lcu data
wire [96*`PIXEL_WIDTH-1:0] ref_luma_data;
wire [128*`PIXEL_WIDTH-1:0] ref_luma_lshift;
wire [128*`PIXEL_WIDTH-1:0] ref_luma_rshift;
reg [1-1:0] extif_start_o;
reg [1-1:0] sysif_done_o;
reg [1-1:0] cur_luma_valid_o;
reg [1-1:0] cur_chroma_valid_o;
reg chroma_ref_lshift_r1,chroma_ref_lshift_r2;
reg chroma_ref_rshift_r1,chroma_ref_rshift_r2;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_u_lshift ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_u_rshift ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_v_lshift ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_v_rshift ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_u_data ;
wire [48*`PIXEL_WIDTH-1 : 0] ref_chroma_v_data ;
wire [96*`PIXEL_WIDTH-1 : 0] ref_chroma_data ;
reg [96*`PIXEL_WIDTH-1 : 0] ref_chroma_data_o ;
reg db_store_done_w ;
reg [2 : 0] cur_state_db_store ;
reg [2 : 0] cur_state_db_store_d ;
reg [2 : 0] nxt_state_db_store ;
// ********************************************
//
// Sequential Logi
//
// ********************************************
//
// main ctrl
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
current_state <= IDLE;
sysif_start_r <= 1'b0;
end
else begin
current_state <= next_state;
sysif_start_r <= sysif_start_i;
end
end
always @ (*) begin
next_state = IDLE ;
if( sysif_type_i==INTER ) begin
case (current_state)
IDLE: if (sysif_start_i) next_state = P1 ; else next_state = IDLE ;
P1 : if (sysif_start_i) next_state = P2 ; else next_state = P1 ;
P2 : if (sysif_start_i) next_state = P3 ; else next_state = P2 ;
P3 : if (sysif_start_i) next_state = P4 ; else next_state = P3 ;
P4 : if (sysif_start_i) next_state = P5 ; else next_state = P4 ;
P5 : if (sysif_start_i) next_state = P6 ; else next_state = P5 ;
P6 : if (sysif_start_i && pre_x == sysif_total_x_i && pre_y == sysif_total_y_i)
next_state = P7 ; else next_state = P6 ;
P7 : if (sysif_start_i) next_state = P8 ; else next_state = P7 ;
P8 : if (sysif_start_i) next_state = P9 ; else next_state = P8 ;
P9 : if (sysif_start_i) next_state = P10 ; else next_state = P9 ;
P10 : if (sysif_start_i) next_state = P11 ; else next_state = P10 ;
P11 : if (sysif_start_i) next_state = P12 ; else next_state = P11 ;
P12 : if (sysif_start_i) next_state = IDLE ; else next_state = P12 ;
endcase
end
else begin
case (current_state)
IDLE: if (sysif_start_i) next_state = P1 ; else next_state = IDLE ;
P1 : if (sysif_start_i) next_state = P2 ; else next_state = P1 ;
P2 : if (sysif_start_i) next_state = P3 ; else next_state = P2 ;
P3 : if (sysif_start_i) next_state = P4 ; else next_state = P3 ;
P4 : if (sysif_start_i && pre_i_x == sysif_total_x_i && pre_i_y == sysif_total_y_i)
next_state = P5 ; else next_state = P4 ;
P5 : if (sysif_start_i) next_state = P6 ; else next_state = P5 ;
P6 : if (sysif_start_i) next_state = P7 ; else next_state = P6 ;
P7 : if (sysif_start_i) next_state = P8 ; else next_state = P7 ;
P8 : if (sysif_start_i) next_state = IDLE ; else next_state = P8 ;
endcase
end
end
always @ (posedge clk or negedge rstn) begin
if( !rstn ) begin
first_x <= 0 ;
first_y <= 0 ;
end
else if( (current_state == IDLE) ) begin
first_x <= 0 ;
first_y <= 0 ;
end
else if( sysif_start_i ) begin
if( first_x == sysif_total_x_i ) begin
first_x <= 0 ;
first_y <= first_y + 1 ;
end
else begin
first_x <= first_x + 1 ;
end
end
end
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
pre_x <= 0 ; pre_y <= 0 ;
fime_x <= 0 ; fime_y <= 0 ;
fme_x <= 0 ; fme_y <= 0 ;
mc_x <= 0 ; mc_y <= 0 ;
db_0_x <= 0 ; db_0_y <= 0 ;
db_1_x <= 0 ; db_1_y <= 0 ;
pre_i_x <= 0 ; pre_i_y <= 0 ;
intra_x <= 0 ; intra_y <= 0 ;
end
else if( sysif_start_i ) begin
if( sysif_type_i==INTER ) begin
pre_x <= first_x ; pre_y <= first_y ;
fime_x <= pre_x ; fime_y <= pre_y ;
fme_x <= fime_x ; fme_y <= fime_y ;
mc_x <= fme_x ; mc_y <= fme_y ;
db_0_x <= mc_x ; db_0_y <= mc_y ;
db_1_x <= db_0_x ; db_1_y <= db_0_y ;
db_2_x <= db_1_x ; db_2_y <= db_1_y ;
end
else begin
pre_i_x <= first_x ; pre_i_y <= first_y ;
intra_x <= pre_i_x ; intra_y <= pre_i_y ;
db_0_x <= intra_x ; db_0_y <= intra_y ;
db_1_x <= db_0_x ; db_1_y <= db_0_y ;
db_2_x <= db_1_x ; db_2_y <= db_1_y ;
end
end
end
always @ (*) begin
{cime, preload, fime, fme, mc, db} = 6'b000000 ;
{preload, pre_i, intra ,db} = 4'b0000 ;
if( sysif_type_i==INTER ) begin
case (current_state)
IDLE: {cime, preload, fime, fme, mc, db} = 6'b000000 ;
P1 : {cime, preload, fime, fme, mc, db} = 6'b100000 ;
P2 : {cime, preload, fime, fme, mc, db} = 6'b110000 ;
P3 : {cime, preload, fime, fme, mc, db} = 6'b111000 ;
P4 : {cime, preload, fime, fme, mc, db} = 6'b111100 ;
P5 : {cime, preload, fime, fme, mc, db} = 6'b111110 ;
P6 : {cime, preload, fime, fme, mc, db} = 6'b111111 ;
P7 : {cime, preload, fime, fme, mc, db} = 6'b011111 ;
P8 : {cime, preload, fime, fme, mc, db} = 6'b001111 ;
P9 : {cime, preload, fime, fme, mc, db} = 6'b000111 ;
P10 : {cime, preload, fime, fme, mc, db} = 6'b000011 ;
P11 : {cime, preload, fime, fme, mc, db} = 6'b000001 ;
P12 : {cime, preload, fime, fme, mc, db} = 6'b000000 ;
endcase
end
else begin
case (current_state)
IDLE: {preload, pre_i, intra ,db} = 4'b0000 ;
P1 : {preload, pre_i, intra ,db} = 4'b1000 ;
P2 : {preload, pre_i, intra ,db} = 4'b1100 ;
P3 : {preload, pre_i, intra ,db} = 4'b1110 ;
P4 : {preload, pre_i, intra ,db} = 4'b1111 ;
P5 : {preload, pre_i, intra ,db} = 4'b0111 ;
P6 : {preload, pre_i, intra ,db} = 4'b0011 ;
P7 : {preload, pre_i, intra ,db} = 4'b0001 ;
P8 : {preload, pre_i, intra ,db} = 4'b0000 ;
endcase
end
end
// arbiter
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
current_fetch <= IDLE;
end
else begin
current_fetch <= next_fetch;
end
end
//preload : LOAD cur_sub_luma, LOAD ref_sub_luma, LOAD cur_luma, LOAD ref_luma
// fme : LOAD cur_chroma, LOAD ref_chroma
// mc : LOAD ref_db
// db : STORE db
//fetch priority : cur_sub_luma > ref_sub_luma > cur_luma > ref_luma > cur_chroma > ref_chroma > ref_db > db
always @ (*) begin
next_fetch = IDLE;
case (current_fetch)
IDLE : begin if( sysif_start_r )
next_fetch = LOAD_CUR_SUB;
else begin
next_fetch = IDLE;
end
end
LOAD_CUR_SUB : begin if((cime & extif_done_i) | (~cime))
next_fetch = LOAD_REF_SUB;
else begin
next_fetch = LOAD_CUR_SUB;
end
end
LOAD_REF_SUB : begin if((cime & extif_done_i) | (~cime))
next_fetch = LOAD_CUR_LUMA;
else begin
next_fetch = LOAD_REF_SUB;
end
end
LOAD_CUR_LUMA : begin if((preload & extif_done_i) | (~preload))
next_fetch = LOAD_REF_LUMA;
else begin
next_fetch = LOAD_CUR_LUMA;
end
end
LOAD_REF_LUMA : begin if((preload & extif_done_i) | (~preload) | (sysif_type_i==INTRA))
next_fetch = LOAD_CUR_CHROMA;
else begin
next_fetch = LOAD_REF_LUMA;
end
end
LOAD_CUR_CHROMA : begin if( sysif_type_i==INTRA ) begin
if((pre_i & extif_done_i) | (~pre_i))
next_fetch = LOAD_REF_CHROMA;
else begin
next_fetch = LOAD_CUR_CHROMA;
end
end
else begin
if((fme & extif_done_i) | (~fme))
next_fetch = LOAD_REF_CHROMA;
else begin
next_fetch = LOAD_CUR_CHROMA;
end
end
end
LOAD_REF_CHROMA : begin if((fme & extif_done_i) | (~fme))
next_fetch = LOAD_DB_LUMA;
else begin
next_fetch = LOAD_REF_CHROMA;
end
end
LOAD_DB_LUMA : begin if( sysif_type_i==INTRA) begin
if((intra & extif_done_i) | (~intra) | (intra_y == 0))
next_fetch = LOAD_DB_CHROMA;
else begin
next_fetch = LOAD_DB_LUMA;
end
end
else begin
if((mc & extif_done_i) | (~mc) | (mc_y == 0))
next_fetch = LOAD_DB_CHROMA;
else begin
next_fetch = LOAD_DB_LUMA;
end
end
end
LOAD_DB_CHROMA : begin if( sysif_type_i==INTRA) begin
if((intra & extif_done_i) | (~intra) | (intra_y == 0))
next_fetch = STORE_DB_LUMA;
else begin
next_fetch = LOAD_DB_CHROMA;
end
end
else begin
if((mc & extif_done_i) | (~mc) | (mc_y == 0))
next_fetch = STORE_DB_LUMA;
else begin
next_fetch = LOAD_DB_CHROMA;
end
end
end
STORE_DB_LUMA : begin if( ~store_db )
next_fetch = STORE_DB_CHROMA ;
else if( extif_done_i )
next_fetch = STORE_DB_CHROMA ;
else begin
next_fetch = STORE_DB_LUMA ;
end
end
STORE_DB_CHROMA : begin if( ~store_db )
next_fetch = IDLE ;
else if( extif_done_i ) begin
if( store_db_done )
next_fetch = IDLE ;
else begin
next_fetch = STORE_DB_LUMA ;
end
end
else begin
next_fetch = STORE_DB_CHROMA ;
end
end
endcase
end
// take care of store_db twice, when x == total_x
assign store_db = db & (db_1_x != 'd0);
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
store_db_done <= 'd0;
end
else if( current_fetch == LOAD_DB_CHROMA ) begin
if (db_1_x == sysif_total_x_i)
store_db_done <= 'd0;
else
store_db_done <= 'd1;
end
else if( (current_fetch==STORE_DB_CHROMA) & extif_done_i ) begin
store_db_done <= 'd1;
end
end
// address gen
always @ (*) begin
case (current_fetch)
LOAD_CUR_SUB : begin extif_x_o = first_x;
extif_y_o = first_y;
extif_width_o = 'd16;
extif_height_o = 'd16;
extif_mode_o = LOAD_CUR_SUB;
end
LOAD_REF_SUB : begin extif_x_o = first_x;
extif_y_o = first_y;
extif_width_o = 'd16;
extif_height_o = 'd16;
extif_mode_o = LOAD_REF_SUB;
end
LOAD_CUR_LUMA : begin extif_x_o = ( sysif_type_i==INTRA ) ? first_x : pre_x ;
extif_y_o = ( sysif_type_i==INTRA ) ? first_y : pre_y ;
extif_width_o = 'd64;
extif_height_o = 'd64;
extif_mode_o = LOAD_CUR_LUMA;
end
LOAD_REF_LUMA : begin extif_x_o = luma_ref_x_s;
extif_y_o = luma_ref_y_s;
extif_width_o = 'd96;
extif_height_o = luma_ref_height;
extif_mode_o = LOAD_REF_LUMA;
end
LOAD_CUR_CHROMA : begin extif_x_o = ( sysif_type_i==INTRA ) ? pre_i_x : fme_x ;
extif_y_o = ( sysif_type_i==INTRA ) ? pre_i_y : fme_y ;
extif_width_o = 'd64;
extif_height_o = 'd64;
extif_mode_o = LOAD_CUR_CHROMA;
end
LOAD_REF_CHROMA : begin extif_x_o = luma_ref_x_s_r2;
extif_y_o = luma_ref_y_s_r2;
extif_width_o = 'd96;
extif_height_o = luma_ref_height_r2;
extif_mode_o = LOAD_REF_CHROMA;
end
LOAD_DB_LUMA : begin extif_x_o =(( sysif_type_i==INTRA ) ? intra_x : mc_x ) * 64;
extif_y_o =(( sysif_type_i==INTRA ) ? intra_y : mc_y ) * 64 - 4;
extif_width_o = 'd64;
extif_height_o = 'd4;
extif_mode_o = LOAD_DB_LUMA;
end
LOAD_DB_CHROMA : begin extif_x_o =(( sysif_type_i==INTRA ) ? intra_x : mc_x ) * 64;
extif_y_o =(( sysif_type_i==INTRA ) ? intra_y : mc_y ) * 64 - 8;
extif_width_o = 'd64;
extif_height_o = 'd8;
extif_mode_o = LOAD_DB_CHROMA;
end
STORE_DB_LUMA : begin extif_x_o = ( store_db_done & (db_1_x==sysif_total_x_i) ) ? (db_1_x * 64) : (db_2_x * 64 ) ;
extif_y_o = ( db_1_y==0 ) ? (db_1_y * 64) : (db_1_y * 64 - 4) ;
extif_width_o = 64 ;
extif_height_o = ( db_1_y==0 ) ? 64 : 68 ;
extif_mode_o = STORE_DB_LUMA ;
end
STORE_DB_CHROMA : begin extif_x_o = ( store_db_done & (db_1_x==sysif_total_x_i) ) ? (db_1_x * 64) : (db_2_x * 64 ) ;
extif_y_o = ( db_1_y==0 ) ? (db_1_y * 64) : (db_1_y * 64 - 8) ;
extif_width_o = 64 ;
extif_height_o = ( db_1_y==0 ) ? 64 : 72 ;
extif_mode_o = STORE_DB_CHROMA ;
end
default : begin extif_x_o = 'd0;
extif_y_o = 'd0;
extif_width_o = 'd0;
extif_height_o = 'd0;
extif_mode_o = IDLE;
end
endcase
end
// extif_start_o
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
extif_start_o <= 1'b0;
end
else if( sysif_type_i==INTER ) begin
if ( (current_fetch == IDLE && next_fetch == LOAD_CUR_SUB && cime ) || // cur_sub
(current_fetch == LOAD_CUR_SUB && next_fetch == LOAD_REF_SUB && cime ) || // ref_sub
(current_fetch == LOAD_REF_SUB && next_fetch == LOAD_CUR_LUMA && preload ) || // cur_luma
(current_fetch == LOAD_CUR_LUMA && next_fetch == LOAD_REF_LUMA && preload ) || // ref_luma
(current_fetch == LOAD_REF_LUMA && next_fetch == LOAD_CUR_CHROMA && fme ) || // cur_chroma
(current_fetch == LOAD_CUR_CHROMA && next_fetch == LOAD_REF_CHROMA && fme ) || // ref_chroma
(current_fetch == LOAD_REF_CHROMA && next_fetch == LOAD_DB_LUMA && mc && (mc_y !=0) ) || // load db_luma
(current_fetch == LOAD_DB_LUMA && next_fetch == LOAD_DB_CHROMA && mc && (mc_y !=0) ) || // load db_chroma
(current_fetch == LOAD_DB_CHROMA && next_fetch == STORE_DB_LUMA && store_db ) || // store db luma
(current_fetch == STORE_DB_LUMA && next_fetch == STORE_DB_CHROMA && store_db ) || // store db chroma
(current_fetch == STORE_DB_CHROMA && store_db_done == 1'b0 && extif_done_i ) ) // store db luma & chroma again at x=total
extif_start_o <= 1'b1;
else begin
extif_start_o <= 1'b0;
end
end
else begin
if( (current_fetch == LOAD_REF_SUB && next_fetch == LOAD_CUR_LUMA && preload ) || // cur_luma
(current_fetch == LOAD_REF_LUMA && next_fetch == LOAD_CUR_CHROMA && pre_i ) || // cur_chroma
(current_fetch == LOAD_REF_CHROMA && next_fetch == LOAD_DB_LUMA && intra && (intra_y !=0) ) || // load db luma
(current_fetch == LOAD_DB_LUMA && next_fetch == LOAD_DB_CHROMA && intra && (intra_y !=0) ) || // load db_chroma
(current_fetch == LOAD_DB_CHROMA && next_fetch == STORE_DB_LUMA && store_db ) || // store db luma
(current_fetch == STORE_DB_LUMA && next_fetch == STORE_DB_CHROMA && store_db ) || // store db chroma
(current_fetch == STORE_DB_CHROMA && store_db_done == 1'b0 && extif_done_i ) ) // store db luma & chroma again at x=total
extif_start_o <= 1'b1 ;
else begin
extif_start_o <= 1'b0 ;
end
end
end
// ref address calc
assign cimv_pre_i_x = cimv_pre_i[19:10];
assign cimv_pre_i_y = cimv_pre_i[9:0];
// ref x & y coordinate
wire signed [13:0] pre_x_minus16 = pre_x * 64 - 'd16;
wire signed [13:0] pre_x_plus80 = pre_x * 64 + cimv_pre_i_x + 'd80;
wire signed [13:0] pre_y_minus16 = pre_y * 64 - 'd16;
always @ (*) begin
if ( pre_x_minus16 < 0 )
luma_ref_x_s = 'd0;
// else if ( pre_x_plus80 > (sysif_total_x_i+1)*64)
// luma_ref_x_s = (sysif_total_x_i+1)*64 - 'd96;
else
luma_ref_x_s = pre_x * 64 + cimv_pre_i_x - 'd16;
end
always @ (*) begin
if ( pre_y_minus16 < 0 )
luma_ref_y_s = 'd0;
else
luma_ref_y_s = pre_y* 64 + cimv_pre_i_y - 'd16;
end
// ref width & height
always @ (*) begin
if ( pre_y_minus16 < 0 )
luma_ref_height = 96 + (pre_y * 64 + cimv_pre_i_y - 'd16) ;
else if ( (pre_y * 64 + cimv_pre_i_y + 'd80) > (sysif_total_y_i+1)*64)
luma_ref_height = (sysif_total_y_i+1)*64 - 2 * ( pre_y * 64 + cimv_pre_i_y);
else
luma_ref_height = 'd96;
end
// chroma
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
luma_ref_height_r1 <= 0 ;
luma_ref_height_r2 <= 0 ;
luma_ref_x_s_r1 <= 0 ;
luma_ref_x_s_r2 <= 0 ;
luma_ref_y_s_r1 <= 0 ;
luma_ref_y_s_r2 <= 0 ;
chroma_ref_lshift_r1 <= 0 ;
chroma_ref_lshift_r2 <= 0 ;
chroma_ref_rshift_r1 <= 0 ;
chroma_ref_rshift_r2 <= 0 ;
end
else if (sysif_done_o) begin
luma_ref_height_r1 <= luma_ref_height ;
luma_ref_height_r2 <= luma_ref_height_r1 ;
luma_ref_x_s_r1 <= luma_ref_x_s ;
luma_ref_x_s_r2 <= luma_ref_x_s_r1 ;
luma_ref_y_s_r1 <= luma_ref_y_s ;
luma_ref_y_s_r2 <= luma_ref_y_s_r1 ;
chroma_ref_lshift_r1 <= (pre_x_minus16 < 0) ;
chroma_ref_lshift_r2 <= chroma_ref_lshift_r1 ;
chroma_ref_rshift_r1 <= (pre_x_plus80 > (sysif_total_x_i+1)*64) ;
chroma_ref_rshift_r2 <= chroma_ref_rshift_r1 ;
end
end
// ***********************************************
// Assignment
// ***********************************************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
sysif_done_o <= 1'b0;
end
else begin
sysif_done_o <= (current_fetch == STORE_DB_CHROMA ) & ( (extif_done_i & store_db_done) | (~store_db) ) ;
end
end
assign cur_luma_done_o = (current_fetch == LOAD_CUR_LUMA) && (preload & extif_done_i);
assign cur_chroma_done_o = (current_fetch == LOAD_CUR_CHROMA) && (fme & extif_done_i);
assign ref_luma_done_o = (current_fetch == LOAD_REF_LUMA) && (preload & extif_done_i);
assign ref_chroma_done_o = (current_fetch == LOAD_REF_CHROMA) && (fme & extif_done_i);
assign db_store_done_o = (current_fetch == STORE_DB_CHROMA) && (db & extif_done_i);
assign db_store_en_o = 1 ;
assign extif_data_o = ((cur_state_db_store_d==DB_STORE_CHRO_PRE)|(cur_state_db_store_d==DB_STORE_CHRO_CUR))
? ( db_store_addr_r[0] ? { db_store_data_i[127:120],db_store_data_i[095:088],db_store_data_i[119:112],db_store_data_i[087:080],db_store_data_i[111:104],db_store_data_i[079:072],db_store_data_i[103:096],db_store_data_i[071:064]
,db_store_data_i[063:056],db_store_data_i[031:024],db_store_data_i[055:048],db_store_data_i[023:016],db_store_data_i[047:040],db_store_data_i[015:008],db_store_data_i[039:032],db_store_data_i[007:000]
}
: { db_store_data_i[255:248],db_store_data_i[223:216],db_store_data_i[247:240],db_store_data_i[215:208],db_store_data_i[239:232],db_store_data_i[207:200],db_store_data_i[231:224],db_store_data_i[199:192]
,db_store_data_i[191:184],db_store_data_i[159:152],db_store_data_i[183:176],db_store_data_i[151:144],db_store_data_i[175:168],db_store_data_i[143:136],db_store_data_i[167:160],db_store_data_i[135:128]
}
)
: ( db_store_addr_r[0] ? db_store_data_i[16*`PIXEL_WIDTH-1:0] : db_store_data_i[32*`PIXEL_WIDTH-1:16*`PIXEL_WIDTH] );
assign db_ref_en_o = ( (current_fetch==LOAD_DB_LUMA)|(current_fetch==LOAD_DB_CHROMA) ) && extif_wren_i ;
assign db_ref_data_o = ( db_ref_addr_o<16 ) ? extif_data_i :
{ extif_data_i[127:120],extif_data_i[111:104],extif_data_i[095:088],extif_data_i[079:072],extif_data_i[063:056],extif_data_i[047:040],extif_data_i[031:024],extif_data_i[015:008]
,extif_data_i[119:112],extif_data_i[103:096],extif_data_i[087:080],extif_data_i[071:064],extif_data_i[055:048],extif_data_i[039:032],extif_data_i[023:016],extif_data_i[007:000]
} ;
// ***********************
// Data Alias (modify this part if AXI_WIDTH is changed)
// ***********************
always @ (posedge clk or negedge rstn) begin
if (~rstn) begin
extif_data_0 <= 'd0;
extif_data_1 <= 'd0;
extif_data_2 <= 'd0;
extif_data_3 <= 'd0;
extif_data_4 <= 'd0;
end
else if (extif_wren_i) begin
extif_data_0 <= extif_data_i;
extif_data_1 <= extif_data_0;
extif_data_2 <= extif_data_1;
extif_data_3 <= extif_data_2;
extif_data_4 <= extif_data_3;
end
end
// cur luma
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cur_luma_addr <= 'd0;
end
else if (cur_luma_valid_o) begin
cur_luma_addr <= cur_luma_addr + 'd1;
end
end
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
cur_luma_cnt <= 0 ;
cur_luma_valid_o <= 0 ;
end
else if( current_fetch!=next_fetch ) begin
cur_luma_cnt <= 0 ;
cur_luma_valid_o <= 0 ;
end
else if( (current_fetch==LOAD_CUR_LUMA) && extif_wren_i ) begin
if( cur_luma_cnt==(32/AXI_WIDTH_PIXEL-1) ) begin
cur_luma_cnt <= 0 ;
cur_luma_valid_o <= 1 ;
end
else begin
cur_luma_cnt <= cur_luma_cnt + 1 ;
cur_luma_valid_o <= 0 ;
end
end
else begin
cur_luma_valid_o <= 0 ;
end
end
assign cur_luma_data_o = { extif_data_1 ,extif_data_0 };
assign cur_luma_addr_o = { cur_luma_addr[6],
cur_luma_addr[0],
cur_luma_addr[5:1]
};
// ref_luma
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
ref_luma_addr_o <= 0 ;
ref_luma_cnt <= 0 ;
end
else if( current_fetch!=next_fetch ) begin
ref_luma_addr_o <= 0 ;
ref_luma_cnt <= 0 ;
end
else if( (current_fetch==LOAD_REF_LUMA) && extif_wren_i ) begin
if( ref_luma_cnt==(96/AXI_WIDTH_PIXEL-1) ) begin
ref_luma_addr_o <= ref_luma_addr_o+1 ;
ref_luma_cnt <= 0 ;
end
else begin
ref_luma_addr_o <= ref_luma_addr_o ;
ref_luma_cnt <= ref_luma_cnt+1 ;
end
end
end
assign ref_luma_data = {extif_data_4,extif_data_3, extif_data_2,
extif_data_1,extif_data_0, extif_data_i};
assign ref_luma_valid_o= (current_fetch==LOAD_REF_LUMA) && extif_wren_i && (ref_luma_cnt==(96/AXI_WIDTH_PIXEL-1)) ;
assign ref_luma_lshift = {{32{extif_data_4[16*`PIXEL_WIDTH-1:15*`PIXEL_WIDTH]}},ref_luma_data} >> ('d16 * `PIXEL_WIDTH);
assign ref_luma_rshift = {extif_data_4,extif_data_3,extif_data_2,
extif_data_1,extif_data_0,{32{extif_data_0[`PIXEL_WIDTH-1:0]}}};
always @ (*) begin
if ( pre_x_minus16< 0)
ref_luma_data_o = ref_luma_lshift[96*`PIXEL_WIDTH-1:0];
else if (pre_x_plus80 > (sysif_total_x_i+1)*64)
ref_luma_data_o = {extif_data_4,extif_data_3,extif_data_2,extif_data_1,extif_data_0,{16{extif_data_0[`PIXEL_WIDTH-1:0]}}};
else
ref_luma_data_o = ref_luma_data;
end
// cur_chroma
always @ (posedge clk or negedge rstn) begin
if(~rstn) begin
cur_chroma_addr <= 'd0;
end
else if (cur_chroma_valid_o) begin
cur_chroma_addr <= cur_chroma_addr + 'd1;
end
end
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
cur_chroma_cnt <= 0 ;
cur_chroma_valid_o <= 0 ;
end
else if( current_fetch!=next_fetch ) begin
cur_chroma_cnt <= 0 ;
cur_chroma_valid_o <= 0 ;
end
else if( (current_fetch==LOAD_CUR_CHROMA) && extif_wren_i ) begin
if( cur_chroma_cnt==(32/AXI_WIDTH_PIXEL-1) ) begin
cur_chroma_cnt <= 0 ;
cur_chroma_valid_o <= 1 ;
end
else begin
cur_chroma_cnt <= cur_chroma_cnt + 1 ;
cur_chroma_valid_o <= 0;
end
end
else begin
cur_chroma_valid_o <= 0 ;
end
end
assign cur_chroma_data_o = { extif_data_1[127:120],extif_data_1[111:104],extif_data_1[095:088],extif_data_1[079:072],extif_data_1[063:056],extif_data_1[047:040],extif_data_1[031:024],extif_data_1[015:008]
,extif_data_0[127:120],extif_data_0[111:104],extif_data_0[095:088],extif_data_0[079:072],extif_data_0[063:056],extif_data_0[047:040],extif_data_0[031:024],extif_data_0[015:008]
,extif_data_1[119:112],extif_data_1[103:096],extif_data_1[087:080],extif_data_1[071:064],extif_data_1[055:048],extif_data_1[039:032],extif_data_1[023:016],extif_data_1[007:000]
,extif_data_0[119:112],extif_data_0[103:096],extif_data_0[087:080],extif_data_0[071:064],extif_data_0[055:048],extif_data_0[039:032],extif_data_0[023:016],extif_data_0[007:000]
};
assign cur_chroma_addr_o = { cur_chroma_addr[5],
cur_chroma_addr[0],
cur_chroma_addr[4:1]
};
// ref_chroma ***
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
ref_chroma_addr <= 0 ;
ref_chroma_cnt <= 0 ;
end
else if( current_fetch!=next_fetch ) begin
ref_chroma_addr <= 0 ;
ref_chroma_cnt <= 0 ;
end
else if( (current_fetch==LOAD_REF_CHROMA) && extif_wren_i ) begin
if( ref_chroma_cnt==(48/AXI_WIDTH_PIXEL*2-1) ) begin
ref_chroma_cnt <= 0 ;
ref_chroma_addr <= ref_chroma_addr+1 ;
end
else begin
ref_chroma_addr <= ref_chroma_addr ;
ref_chroma_cnt <= ref_chroma_cnt+1 ;
end
end
end
assign ref_chroma_valid_o = (current_fetch==LOAD_REF_CHROMA) && extif_wren_i && ref_chroma_cnt==(48/AXI_WIDTH_PIXEL*2-1) ;
assign ref_chroma_addr_o = ref_chroma_addr ;
assign ref_chroma_u_data = { extif_data_4[127:120],extif_data_4[111:104],extif_data_4[095:088],extif_data_4[079:072],extif_data_4[063:056],extif_data_4[047:040],extif_data_4[031:024],extif_data_4[015:008]
,extif_data_3[127:120],extif_data_3[111:104],extif_data_3[095:088],extif_data_3[079:072],extif_data_3[063:056],extif_data_3[047:040],extif_data_3[031:024],extif_data_3[015:008]
,extif_data_2[127:120],extif_data_2[111:104],extif_data_2[095:088],extif_data_2[079:072],extif_data_2[063:056],extif_data_2[047:040],extif_data_2[031:024],extif_data_2[015:008]
,extif_data_1[127:120],extif_data_1[111:104],extif_data_1[095:088],extif_data_1[079:072],extif_data_1[063:056],extif_data_1[047:040],extif_data_1[031:024],extif_data_1[015:008]
,extif_data_0[127:120],extif_data_0[111:104],extif_data_0[095:088],extif_data_0[079:072],extif_data_0[063:056],extif_data_0[047:040],extif_data_0[031:024],extif_data_0[015:008]
,extif_data_i[127:120],extif_data_i[111:104],extif_data_i[095:088],extif_data_i[079:072],extif_data_i[063:056],extif_data_i[047:040],extif_data_i[031:024],extif_data_i[015:008]
};
assign ref_chroma_v_data = { extif_data_4[119:112],extif_data_4[103:096],extif_data_4[087:080],extif_data_4[071:064],extif_data_4[055:048],extif_data_4[039:032],extif_data_4[023:016],extif_data_4[007:000]
,extif_data_3[119:112],extif_data_3[103:096],extif_data_3[087:080],extif_data_3[071:064],extif_data_3[055:048],extif_data_3[039:032],extif_data_3[023:016],extif_data_3[007:000]
,extif_data_2[119:112],extif_data_2[103:096],extif_data_2[087:080],extif_data_2[071:064],extif_data_2[055:048],extif_data_2[039:032],extif_data_2[023:016],extif_data_2[007:000]
,extif_data_1[119:112],extif_data_1[103:096],extif_data_1[087:080],extif_data_1[071:064],extif_data_1[055:048],extif_data_1[039:032],extif_data_1[023:016],extif_data_1[007:000]
,extif_data_0[119:112],extif_data_0[103:096],extif_data_0[087:080],extif_data_0[071:064],extif_data_0[055:048],extif_data_0[039:032],extif_data_0[023:016],extif_data_0[007:000]
,extif_data_i[119:112],extif_data_i[103:096],extif_data_i[087:080],extif_data_i[071:064],extif_data_i[055:048],extif_data_i[039:032],extif_data_i[023:016],extif_data_i[007:000]
};
assign ref_chroma_u_lshift = {{8{ref_chroma_u_data[48*`PIXEL_WIDTH-1:47*`PIXEL_WIDTH]}},ref_chroma_u_data}>>(8*`PIXEL_WIDTH) ;
assign ref_chroma_v_lshift = {{8{ref_chroma_v_data[48*`PIXEL_WIDTH-1:47*`PIXEL_WIDTH]}},ref_chroma_v_data}>>(8*`PIXEL_WIDTH) ;
assign ref_chroma_u_rshift = {ref_chroma_u_data>>(8*`PIXEL_WIDTH),{8{ref_chroma_u_data[09*`PIXEL_WIDTH-1:08*`PIXEL_WIDTH]}}} ;
assign ref_chroma_v_rshift = {ref_chroma_v_data>>(8*`PIXEL_WIDTH),{8{ref_chroma_v_data[09*`PIXEL_WIDTH-1:08*`PIXEL_WIDTH]}}} ;
always @ (*) begin
if ( chroma_ref_lshift_r2 )
ref_chroma_data_o = { ref_chroma_u_lshift ,ref_chroma_v_lshift };
else if ( chroma_ref_rshift_r2 )
ref_chroma_data_o = { ref_chroma_u_rshift ,ref_chroma_v_rshift };
else begin
ref_chroma_data_o = { ref_chroma_u_data ,ref_chroma_v_data };
end
end
// db_ref_addr_o
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
db_ref_addr_o <= 0 ;
end
else if( (current_fetch==LOAD_DB_LUMA) & extif_start_o ) begin
db_ref_addr_o <= 0 ;
end
else if( ((current_fetch==LOAD_DB_LUMA)|(current_fetch==LOAD_DB_CHROMA)) & extif_wren_i ) begin
db_ref_addr_o <= db_ref_addr_o + 1;
end
end
// cur_state_db_store
always @(posedge clk or negedge rstn ) begin
if( !rstn )
cur_state_db_store <= DB_STORE_IDLE ;
else begin
cur_state_db_store <= nxt_state_db_store ;
end
end
// nxt_state_db_store
always @(*) begin
nxt_state_db_store = DB_STORE_IDLE ;
case( cur_state_db_store )
DB_STORE_IDLE : if( (current_fetch==STORE_DB_LUMA)&(extif_start_o) )
if( db_1_y==0 ) nxt_state_db_store = DB_STORE_LUMA_CUR ;
else nxt_state_db_store = DB_STORE_LUMA_PRE ;
else nxt_state_db_store = DB_STORE_IDLE ;
DB_STORE_LUMA_PRE : if( db_store_done_w ) nxt_state_db_store = DB_STORE_LUMA_CUR ;
else nxt_state_db_store = DB_STORE_LUMA_PRE ;
DB_STORE_LUMA_CUR : if( db_store_done_w )
if( db_1_y==0 ) nxt_state_db_store = DB_STORE_CHRO_CUR ;
else nxt_state_db_store = DB_STORE_CHRO_PRE ;
else nxt_state_db_store = DB_STORE_LUMA_CUR ;
DB_STORE_CHRO_PRE : if( db_store_done_w ) nxt_state_db_store = DB_STORE_CHRO_CUR ;
else nxt_state_db_store = DB_STORE_CHRO_PRE ;
DB_STORE_CHRO_CUR : if( db_store_done_w ) nxt_state_db_store = DB_STORE_IDLE ;
else nxt_state_db_store = DB_STORE_CHRO_CUR ;
endcase
end
// db_store_done_w
always @(*) begin
db_store_done_w = ( db_store_addr_r == ( 1-1) ) & extif_rden_i ;
case( cur_state_db_store )
DB_STORE_IDLE : db_store_done_w = ( db_store_addr_r == ( 1-1) ) & extif_rden_i ;
DB_STORE_LUMA_PRE : db_store_done_w = ( db_store_addr_r == ( 16-1) ) & extif_rden_i ;
DB_STORE_LUMA_CUR : db_store_done_w = ( db_store_addr_r == (256-1) ) & extif_rden_i ;
DB_STORE_CHRO_PRE : db_store_done_w = ( db_store_addr_r == ( 16-1) ) & extif_rden_i ;
DB_STORE_CHRO_CUR : db_store_done_w = ( db_store_addr_r == (128-1) ) & extif_rden_i ;
endcase
end
// db_store_addr_r
always @(posedge clk or negedge rstn ) begin
if( !rstn ) begin
db_store_addr_r <= 0 ;
end
else if( (current_fetch==STORE_DB_LUMA) & extif_start_o ) begin
db_store_addr_r <= 0 ;
end
else if( ((current_fetch==STORE_DB_LUMA)|(current_fetch==STORE_DB_CHROMA)) & extif_rden_i ) begin
if( db_store_done_w )
db_store_addr_r <= 0 ;
else begin
db_store_addr_r <= db_store_addr_r + 1 ;
end
end
end
// db_store_addr_w
always @(*) begin
db_store_addr_w = db_store_addr_r ;
if( (current_fetch==STORE_DB_LUMA) & extif_start_o )
db_store_addr_w = 0 ;
else if( (current_fetch==STORE_DB_LUMA)|(current_fetch==STORE_DB_CHROMA) ) begin
if( extif_rden_i ) begin
if( db_store_done_w )
db_store_addr_w = 0 ;
else begin
db_store_addr_w = db_store_addr_r + 1 ;
end
end
else begin
db_store_addr_w = db_store_addr_r ;
end
end
end
// cur_state_db_store_d
always @(posedge clk or negedge rstn ) begin
if( !rstn )
cur_state_db_store_d <= 0 ;
else if( (current_fetch==STORE_DB_LUMA) | (current_fetch==STORE_DB_CHROMA) & extif_rden_i )begin
cur_state_db_store_d <= nxt_state_db_store ;
end
end
// db_store_addr_o
always @(*) begin
db_store_addr_o = 0 ;
case( nxt_state_db_store )
DB_STORE_IDLE : db_store_addr_o = 0 ;
DB_STORE_LUMA_PRE : db_store_addr_o = 192 + { db_store_addr_w[8:4] ,db_store_addr_w[1] ,db_store_addr_w[3:2] };
DB_STORE_LUMA_CUR : db_store_addr_o = 0 + { db_store_addr_w[8:7] ,db_store_addr_w[1] ,db_store_addr_w[6:2] };
DB_STORE_CHRO_PRE : db_store_addr_o = 200 + { db_store_addr_w[8:4] ,db_store_addr_w[1] ,db_store_addr_w[3:2] };
DB_STORE_CHRO_CUR : db_store_addr_o = 128 + { db_store_addr_w[8:4] ,db_store_addr_w[1] ,db_store_addr_w[3:2] };
endcase
end
//output
assign sysif_fime_y_o = fime_y ;
assign sysif_fme_y_o = fme_y ;
assign sysif_mc_y_o = mc_y ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_2_V
`define SKY130_FD_SC_HS__DLRBN_2_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrbn_2 (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrbn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrbn_2 (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrbn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_2_V
`define SKY130_FD_SC_LP__NAND2_2_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:06 08/03/2009
// Design Name:
// Module Name: ctrl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MCtrl(input clk,
input reset,
input [31:0] Inst_in,
input zero,
input overflow,
input MIO_ready,
output reg MemRead,
output reg MemWrite,
output [2:0]ALU_operation,
output [4:0]state_out,
output reg CPU_MIO,
output reg IorD,
output reg IRWrite,
output reg [1:0]RegDst,
output reg RegWrite,
output reg [1:0]MemtoReg,
output reg ALUSrcA,
output reg [1:0]ALUSrcB,
output reg [1:0]PCSource,
output reg PCWrite,
output reg PCWriteCond,
output reg Branch
);
reg [3:0] state, Q;
reg [1:0] ALUop;
wire[3:0] D;
parameter IF = 4'b0000, ID = 4'b0001, Mem_Ex = 4'b0010, Mem_RD = 4'b0011, LW_WB = 4'b0100,
Mem_W = 4'b0101, R_Exc = 4'b0110, R_WB = 4'b0111, Beq_Exc= 4'b1000, J = 4'b1001,
Error = 4'b1111;
`define Datapath_signals {PCWrite, PCWriteCond,IorD, MemRead, MemWrite,IRWrite, MemtoReg, PCSource, ALUSrcA, ALUSrcB, RegWrite, RegDst, Branch, ALUop, CPU_MIO}
parameter value0 = 20'b10010100000010000000, value1 = 20'b00000000000110000000,
value2 = 20'b00000000001100000000, value3 = 20'b00110000000000000001,
value4 = 20'b00000001000001000000, value5 = 20'b00101000000000000001,
value6 = 20'b00000000001000000100, value7 = 20'b00000000000001010000,
value8 = 20'b01000000011000001010, value9 = 20'b10000000100000000000;
parameter AND=3'b000, OR=3'b001, ADD=3'b010, SUB=3'b110, NOR=3'b100, SLT=3'b111, XOR=3'b011, SRL=3'b101;
assign state_out={1'b0,Q};
wire [5:0] OP = Inst_in[31:26];
//
wire s0 = ~|Q; //if Q=0000 then s0 = 1
wire s1 = ~Q[3] && ~Q[2] && ~Q[1] && Q[0] ; //if Q=0001 then s1 = 1
wire s2 = ~Q[3] && ~Q[2] && Q[1] && ~Q[0] ; //if Q=0010 then s2 = 1
wire s3 = ~Q[3] && ~Q[2] && Q[1] && Q[0] ; //if Q=0011 then s3 = 1
wire s4 = ~Q[3] && Q[2] && ~Q[1] && ~Q[0] ; //if Q=0100 then s4 = 1
wire s5 = ~Q[3] && Q[2] && ~Q[1] && Q[0] ; //if Q=0101 then s5 = 1
wire s6 = ~Q[3] && Q[2] && Q[1] && ~Q[0] ; //if Q=0110 then s6 = 1
wire s7 = ~Q[3] && Q[2] && Q[1] && Q[0] ; //if Q=0111 then s7 = 1
wire s8 = Q[3] && ~Q[2] && ~Q[1] && ~Q[0] ; //if Q=1000 then s8 = 1
wire s9 = Q[3] && ~Q[2] && ~Q[1] && Q[0] ; //if Q=1001 then s9 = 1
wire Rtype = ~|OP;
wire LS = (OP == 6'b10x011) ? 1 : 0;
wire IBeq = (OP == 6'b000100) ? 1 : 0;
wire Jump = (OP == 6'b000010) ? 1 : 0;
wire Load = (OP == 6'b100011) ? 1 : 0;
wire Store = (OP == 6'b101011) ? 1 : 0;
assign D[3] = s1 && (IBeq || Jump);
assign D[2] = s1 && Rtype || s2 && Store || s3 && Load || s6 && Rtype;
assign D[1] = s1 && (LS || Rtype) || s2 && Load || s6 && Rtype;
assign D[0] = s0 || s1 && Jump || s2 && Load || s2 && Store || s6 && Rtype;
always @ (posedge clk or posedge reset)
if (reset==1) Q <= IF;
else Q <= D;
always @ * begin
case(Q) //state
IF: `Datapath_signals = value0;
ID: `Datapath_signals = value1;
Mem_Ex: `Datapath_signals = value2;
Mem_RD: `Datapath_signals = value3;
LW_WB: `Datapath_signals = value4;
Mem_W: `Datapath_signals = value5;
R_Exc: `Datapath_signals = value6;
R_WB: `Datapath_signals = value7;
Beq_Exc: `Datapath_signals = value8;
J: `Datapath_signals = value9;
default: `Datapath_signals = value0;
endcase
end
//ALU Decoder
ALU_Decoder ALU_D(.ALUop(ALUop),
.Fun(Inst_in[5:0]),
.ALU_Control(ALU_operation)
);
/* always @ * begin
case(ALUop)
2'b00: ALU_operation = 3'b010; //add¼ÆËãµØÖ·
2'b01: ALU_operation = 3'b110; //sub±È½ÏÌõ¼þ
2'b10:
case (Inst_in[5:0])
6'b100000: ALU_operation = ADD;
6'b100010: ALU_operation = SUB;
6'b100100: ALU_operation = AND;
6'b100101: ALU_operation = OR;
6'b100111: ALU_operation = NOR;
6'b101010: ALU_operation = SLT;
6'b000010: ALU_operation = SRL; //shfit 1bit right
6'b000000: ALU_operation = XOR;
default: ALU_operation = ADD;
endcase
2'b11: ALU_operation = 3'b111; //slti
endcase
end
*/
/* always @ (posedge clk or posedge reset)
if (reset==1) begin
state <= IF;
end
else
case (state)
IF: begin
if(MIO_ready)begin state <= ID; end
else begin state <= IF;end
end
ID: begin
case (Inst_in[31:26])
6'b000000:begin state <= R_Exc; end //R-type OP
6'b100011:begin state <= Mem_Ex; end //Lw
6'b101011:begin state <= Mem_Ex; end //Sw
6'b000010:begin state <= J; end //Jump
6'b000100:begin state <= Beq_Exc; end //Beq
default: begin state <= Error; end
endcase
end //end ID
Mem_Ex:begin
if(Inst_in[31:26]==6'b100011)begin
state <= Mem_RD; end
else if(Inst_in[31:26]==6'b101011)begin
state <= Mem_W; end
end
Mem_RD:begin
if(MIO_ready)begin
state <= LW_WB; end
else begin
state <=Mem_RD; end
end
Mem_W:begin
if(MIO_ready)begin
state <= IF; end
else begin
state <= Mem_W; end
end
LW_WB:begin
state <=IF; end
R_Exc:begin
state <= R_WB; end
R_WB:begin
state <= IF; end
Beq_Exc:begin
state <= IF; end
J:begin
state <= IF; end
Error: state <= Error;
default: begin
state <= Error; end
endcase
*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/13/2017 04:41:05 PM
// Design Name:
// Module Name: top_sr_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_sr_tb #(parameter WIDTH=170,
parameter CNT_WIDTH=8,
parameter DIV_WIDTH=6,
parameter SHIFT_DIRECTION=1,
parameter READ_TRIG_SRC=0,
parameter READ_DELAY=0)();
reg clk_in;
reg rst;
reg start;
reg [WIDTH-1:0] din;
reg data_in_p;
reg data_in_n;
reg [DIV_WIDTH-1:0] div;
wire clk_sr_p, clk_sr_n;
wire data_out_p, data_out_n;
wire load_sr_p,load_sr_n;
wire [WIDTH-1:0] dout;
wire clk;
wire valid;
top_new #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .DIV_WIDTH(DIV_WIDTH),.SHIFT_DIRECTION(SHIFT_DIRECTION),.READ_TRIG_SRC(READ_TRIG_SRC),.READ_DELAY(READ_DELAY))
DUT4(
.clk_in(clk_in),
.rst(rst),
.pulse_in(start),
.din(din),
.div(div),
.data_in_p(data_in_p),
.data_in_n(data_in_n),
.clk_sr_p(clk_sr_p),
.clk_sr_n(clk_sr_n),
.data_out_p(data_out_p),
.data_out_n(data_out_n),
.load_sr_p(load_sr_p),
.load_sr_n(load_sr_n),
.dout(dout),
.clk(clk),
.valid(valid)
);
initial begin
$dumpfile("top_sr.dump");
$dumpvars(0, Top_SR);
end
initial begin
clk_in=0;
forever #25 clk_in=~clk_in;
end
initial begin
rst=0;
#100 rst=1;
#100 rst=0;
end
initial begin
din={1'b1,169'b1011};
div=6'b1;
start=0;
#675 start=1;
#50 start=0;
#19500 start=1;
#50 start=0;
end
initial begin
data_in_p=0;
data_in_n=1;
#1125
data_in_p=1;
data_in_n=0;
#200
data_in_p=0;
data_in_n=1;
#200
data_in_p=1;
data_in_n=0;
end
endmodule
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx control unit
inputs from execute stage
generate pipeline controls
manage SPRs
issue addresses for exceptions to fetch stage
control branches going to fetch stage
contains tick timer
contains PIC logic
Copyright (C) 2012 Julius Baxter <[email protected]>
Copyright (C) 2012-2013 Stefan Kristiansson <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_ctrl_cappuccino
#(
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
`OR1K_RESET_VECTOR,8'd0},
parameter FEATURE_SYSCALL = "ENABLED",
parameter FEATURE_TRAP = "ENABLED",
parameter FEATURE_RANGE = "ENABLED",
parameter FEATURE_DATACACHE = "NONE",
parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
parameter OPTION_DCACHE_SET_WIDTH = 9,
parameter OPTION_DCACHE_WAYS = 2,
parameter FEATURE_DMMU = "NONE",
parameter OPTION_DMMU_SET_WIDTH = 6,
parameter OPTION_DMMU_WAYS = 1,
parameter FEATURE_INSTRUCTIONCACHE = "NONE",
parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
parameter OPTION_ICACHE_SET_WIDTH = 9,
parameter OPTION_ICACHE_WAYS = 2,
parameter FEATURE_IMMU = "NONE",
parameter OPTION_IMMU_SET_WIDTH = 6,
parameter OPTION_IMMU_WAYS = 1,
parameter FEATURE_TIMER = "ENABLED",
parameter FEATURE_DEBUGUNIT = "NONE",
parameter FEATURE_PERFCOUNTERS = "NONE",
parameter FEATURE_PMU = "NONE",
parameter FEATURE_MAC = "NONE",
parameter FEATURE_FPU = "NONE",
parameter FEATURE_MULTICORE = "NONE",
parameter FEATURE_PIC = "ENABLED",
parameter OPTION_PIC_TRIGGER = "LEVEL",
parameter OPTION_PIC_NMI_WIDTH = 0,
parameter FEATURE_DSX ="NONE",
parameter FEATURE_FASTCONTEXTS = "NONE",
parameter OPTION_RF_NUM_SHADOW_GPR = 0,
parameter FEATURE_OVERFLOW = "NONE",
parameter FEATURE_CARRY_FLAG = "ENABLED",
parameter SPR_SR_WIDTH = 16,
parameter SPR_SR_RESET_VALUE = 16'h8001
)
(
input clk,
input rst,
// ALU result - either jump target, SPR address
input [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_i,
// LSU address, needed for effective address
input [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_i,
// Operand B from RF might be jump address, might be value for SPR
input [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_i,
input ctrl_flag_set_i,
input ctrl_flag_clear_i,
input atomic_flag_set_i,
input atomic_flag_clear_i,
input [OPTION_OPERAND_WIDTH-1:0] pc_ctrl_i,
input ctrl_op_mfspr_i,
input ctrl_op_mtspr_i,
input ctrl_op_rfe_i,
// Indicate if branch will be taken based on instruction currently in
// decode stage.
input decode_branch_i,
input [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_i,
input branch_mispredict_i,
input [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_i,
// PC of execute stage (NPC)
input [OPTION_OPERAND_WIDTH-1:0] pc_execute_i,
input execute_op_branch_i,
// Exception inputs, registered on output of execute stage
input except_ibus_err_i,
input except_itlb_miss_i,
input except_ipagefault_i,
input except_ibus_align_i,
input except_illegal_i,
input except_syscall_i,
input except_dbus_i,
input except_dtlb_miss_i,
input except_dpagefault_i,
input except_trap_i,
input except_align_i,
// Inputs from two units that can stall proceedings
input fetch_valid_i,
input decode_valid_i,
input execute_valid_i,
input ctrl_valid_i,
input fetch_exception_taken_i,
input decode_bubble_i,
input execute_bubble_i,
// External IRQ lines in
input [31:0] irq_i,
// Exception PC output, used in the lsu to properly signal dbus errors that
// has went through the store buffer
output [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_o,
// Exception PC input coming from the store buffer
input [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_i,
input store_buffer_err_i,
// SPR data out
output [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o,
// WE to RF for l.mfspr
output ctrl_mfspr_ack_o,
output ctrl_mtspr_ack_o,
// Flag out to branch control, combinatorial
output ctrl_flag_o,
// Arithmetic flags to and from ALU
output ctrl_carry_o,
input ctrl_carry_set_i,
input ctrl_carry_clear_i,
input ctrl_overflow_set_i,
input ctrl_overflow_clear_i,
// FPU Status flags to and from ALU
output [`OR1K_FPCSR_RM_SIZE-1:0] ctrl_fpu_round_mode_o,
input [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_i,
input ctrl_fpcsr_set_i,
// Branch indicator from control unit (l.rfe/exception)
output ctrl_branch_exception_o,
// PC out to fetch stage for l.rfe, exceptions
output [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_o,
// Clear instructions from decode and fetch stage
output pipeline_flush_o,
// Indicate that a rfe is going on
output doing_rfe_o,
output padv_fetch_o,
output padv_decode_o,
output padv_execute_o,
output padv_ctrl_o,
// Debug bus
input [15:0] du_addr_i,
input du_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] du_dat_i,
input du_we_i,
output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
output du_ack_o,
// Stall control from debug interface
input du_stall_i,
output du_stall_o,
output [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o,
output du_restart_o,
// SPR accesses to external units (cache, mmu, etc.)
output [15:0] spr_bus_addr_o,
output spr_bus_we_o,
output spr_bus_stb_o,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i,
input spr_bus_ack_dc_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i,
input spr_bus_ack_ic_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i,
input spr_bus_ack_dmmu_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i,
input spr_bus_ack_immu_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i,
input spr_bus_ack_mac_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i,
input spr_bus_ack_pmu_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i,
input spr_bus_ack_pcu_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i,
input spr_bus_ack_fpu_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_i,
input spr_gpr_ack_i,
output [15:0] spr_sr_o,
output reg ctrl_bubble_o,
input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i,
input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i
);
// Internal signals
reg [SPR_SR_WIDTH-1:0] spr_sr;
reg [SPR_SR_WIDTH-1:0] spr_esr;
reg [OPTION_OPERAND_WIDTH-1:0] spr_epcr;
reg [OPTION_OPERAND_WIDTH-1:0] spr_eear;
reg [OPTION_OPERAND_WIDTH-1:0] spr_evbar;
// Programmable Interrupt Control SPRs
wire [31:0] spr_picmr;
wire [31:0] spr_picsr;
// Tick Timer SPRs
wire [31:0] spr_ttmr;
wire [31:0] spr_ttcr;
// FPU Control & Status Register
// and related exeption signals
reg [`OR1K_FPCSR_WIDTH-1:0] spr_fpcsr;
wire except_fpu;
reg [OPTION_OPERAND_WIDTH-1:0] spr_ppc;
reg [OPTION_OPERAND_WIDTH-1:0] spr_npc;
reg execute_delay_slot;
reg ctrl_delay_slot;
wire execute_waiting;
reg execute_waiting_r;
reg decode_execute_halt;
reg exception_taken;
reg [OPTION_OPERAND_WIDTH-1:0] last_branch_insn_pc;
reg [OPTION_OPERAND_WIDTH-1:0] last_branch_target_pc;
reg padv_ctrl;
reg exception_r;
reg [OPTION_OPERAND_WIDTH-1:0] exception_pc_addr;
reg waiting_for_fetch;
reg doing_rfe_r;
wire doing_rfe;
wire deassert_doing_rfe;
wire exception, exception_pending;
reg ctrl_stage_exceptions;
wire exception_re;
wire except_ticktimer;
wire except_pic;
wire except_range;
wire [15:0] spr_addr;
wire [OPTION_OPERAND_WIDTH-1:0] b;
wire deassert_decode_execute_halt;
/* Debug SPRs */
reg [31:0] spr_dmr1;
reg [31:0] spr_dmr2;
reg [31:0] spr_dsr;
reg [31:0] spr_drr;
/* DU internal control signals */
wire du_access;
reg cpu_stall;
wire du_restart_from_stall;
reg [5:0] pstep;
wire stepping;
wire stepped_into_delay_slot;
reg stepped_into_exception;
reg stepped_into_rfe;
wire du_npc_write;
reg du_npc_written;
wire stall_on_trap;
/* Wires for SPR management */
wire spr_access_valid;
wire spr_we;
wire spr_read;
wire spr_ack;
wire [OPTION_OPERAND_WIDTH-1:0] spr_write_dat;
reg [11:0] spr_access;
wire [11:0] spr_access_ack;
wire [31:0] spr_internal_read_dat [0:11];
wire spr_read_access;
wire spr_write_access;
wire spr_bus_access;
reg [OPTION_OPERAND_WIDTH-1:0] spr_sys_group_read;
/* Wires from mor1kx_cfgrs module */
wire [31:0] spr_vr;
wire [31:0] spr_vr2;
wire [31:0] spr_avr;
wire [31:0] spr_upr;
wire [31:0] spr_cpucfgr;
wire [31:0] spr_dmmucfgr;
wire [31:0] spr_immucfgr;
wire [31:0] spr_dccfgr;
wire [31:0] spr_iccfgr;
wire [31:0] spr_dcfgr;
wire [31:0] spr_pccfgr;
wire [31:0] spr_isr [0:7];
assign b = ctrl_rfb_i;
assign ctrl_branch_exception_o = (exception_r | ctrl_op_rfe_i | doing_rfe) &
!exception_taken;
assign exception_pending = (except_ibus_err_i | except_ibus_align_i |
except_illegal_i | except_syscall_i |
except_dbus_i | except_align_i |
except_ticktimer | except_range | except_fpu |
except_pic | except_trap_i |
except_itlb_miss_i | except_ipagefault_i |
except_dtlb_miss_i | except_dpagefault_i);
assign exception = exception_pending &
(padv_ctrl & !ctrl_bubble_o | ctrl_stage_exceptions);
assign exception_re = exception & !exception_r & !exception_taken;
assign except_range = (FEATURE_RANGE!="NONE") ? spr_sr[`OR1K_SPR_SR_OVE] &&
(spr_sr[`OR1K_SPR_SR_OV] | ctrl_overflow_set_i) &
!doing_rfe : 0;
assign deassert_decode_execute_halt = fetch_exception_taken_i &
decode_execute_halt;
assign ctrl_branch_except_pc_o = (ctrl_op_rfe_i | doing_rfe) ? spr_epcr :
exception_pc_addr;
assign ctrl_epcr_o = ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i;
always @(posedge clk)
ctrl_stage_exceptions <= except_align_i | except_dbus_i | except_range |
except_fpu |
except_dtlb_miss_i | except_dpagefault_i;
always @(posedge clk)
if (exception & !exception_r)
casez(
{
except_itlb_miss_i,
except_ipagefault_i,
except_ibus_err_i,
except_illegal_i,
except_align_i,
except_ibus_align_i,
except_syscall_i,
except_dtlb_miss_i,
except_dpagefault_i,
except_trap_i,
except_dbus_i,
except_range,
except_fpu,
except_pic,
except_ticktimer
}
)
15'b1??????????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_ITLB_VECTOR,8'd0};
15'b01?????????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_IPF_VECTOR,8'd0};
15'b001????????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_BERR_VECTOR,8'd0};
15'b0001???????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_ILLEGAL_VECTOR,8'd0};
15'b00001??????????,
15'b000001?????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_ALIGN_VECTOR,8'd0};
15'b0000001????????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_SYSCALL_VECTOR,8'd0};
15'b00000001???????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_DTLB_VECTOR,8'd0};
15'b000000001??????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_DPF_VECTOR,8'd0};
15'b0000000001????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_TRAP_VECTOR,8'd0};
15'b00000000001????:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_BERR_VECTOR,8'd0};
15'b000000000001???:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_RANGE_VECTOR,8'd0};
15'b0000000000001??:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_FP_VECTOR,8'd0};
15'b00000000000001?:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_INT_VECTOR,8'd0};
//15'b00000000000001:
default:
exception_pc_addr <= spr_evbar |
{19'd0,`OR1K_TT_VECTOR,8'd0};
endcase // casex (...
assign execute_waiting = !execute_valid_i;
assign padv_fetch_o = !execute_waiting & !cpu_stall & !decode_bubble_i
& (!stepping | (stepping & pstep[0] & !fetch_valid_i));
assign padv_decode_o = fetch_valid_i & !execute_waiting &
!decode_execute_halt & !cpu_stall
& (!stepping | (stepping & pstep[1]));
assign padv_execute_o = ((decode_valid_i & !execute_waiting &
/* Stop fetch before exception branch continuing */
!(exception_r & fetch_exception_taken_i)) |
(!execute_waiting & execute_waiting_r &
fetch_valid_i) |
// Case where execute became ready before fetch
// after delay in execute stage
(waiting_for_fetch & fetch_valid_i)) &
// Not exceptions occurring
!decode_execute_halt & !exception_re & !ctrl_op_rfe_i
& !cpu_stall & (!stepping | (stepping & pstep[2]));
assign padv_ctrl_o = padv_ctrl;
assign spr_addr = du_access ? du_addr_i : ctrl_alu_result_i[15:0];
assign ctrl_mfspr_ack_o = spr_ack;
assign ctrl_mtspr_ack_o = spr_ack;
// Pipeline flush
assign pipeline_flush_o = (padv_ctrl & ctrl_op_rfe_i) |
(exception_re) |
cpu_stall;
// Flag output
wire ctrl_flag_clear = ctrl_flag_clear_i | atomic_flag_clear_i;
wire ctrl_flag_set = ctrl_flag_set_i | atomic_flag_set_i;
assign ctrl_flag_o = (!ctrl_flag_clear & spr_sr[`OR1K_SPR_SR_F]) |
ctrl_flag_set;
// Carry output
assign ctrl_carry_o = FEATURE_CARRY_FLAG!="NONE" &
(!ctrl_carry_clear_i & spr_sr[`OR1K_SPR_SR_CY] |
ctrl_carry_set_i);
// Ctrl stage pipeline advance signal is one cycle behind execute stage's
always @(posedge clk `OR_ASYNC_RST)
if (rst)
padv_ctrl <= 0;
else
padv_ctrl <= padv_execute_o;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
execute_waiting_r <= 0;
else if (!execute_waiting)
execute_waiting_r <= 0;
else if (decode_valid_i & execute_waiting)
execute_waiting_r <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
decode_execute_halt <= 0;
else if (du_restart_from_stall)
decode_execute_halt <= 0;
else if (decode_execute_halt & deassert_decode_execute_halt)
decode_execute_halt <= 0;
else if ((ctrl_op_rfe_i | exception) & !decode_execute_halt &
!exception_taken)
decode_execute_halt <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
exception_r <= 0;
else if (exception_taken | du_restart_from_stall)
exception_r <= 0;
else if (exception & !exception_r)
exception_r <= 1;
// Signal to indicate that the incoming exception or l.rfe has been taken
// and we're waiting for it to propagate through the pipeline.
always @(posedge clk `OR_ASYNC_RST)
if (rst)
exception_taken <= 0;
else if (exception_taken)
exception_taken <= 0;
else if (exception_r & fetch_exception_taken_i)
exception_taken <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
last_branch_insn_pc <= 0;
else if (padv_execute_o & execute_op_branch_i)
last_branch_insn_pc <= pc_execute_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
last_branch_target_pc <= 0;
else if (padv_execute_o & branch_mispredict_i)
last_branch_target_pc <= execute_mispredict_target_i;
else if (padv_decode_o & decode_branch_i)
last_branch_target_pc <= decode_branch_target_i;
// Used to gate execute stage's advance signal in the case where a LSU op has
// finished before the next instruction has been fetched. Typically this
// occurs when not using icache and doing lots of memory accesses.
always @(posedge clk `OR_ASYNC_RST)
if (rst)
waiting_for_fetch <= 0;
else if (fetch_valid_i)
waiting_for_fetch <= 0;
else if (!execute_waiting & execute_waiting_r & !fetch_valid_i)
waiting_for_fetch <= 1;
assign doing_rfe = ((padv_ctrl & ctrl_op_rfe_i) | doing_rfe_r) &
!deassert_doing_rfe;
assign doing_rfe_o = doing_rfe;
assign deassert_doing_rfe = fetch_exception_taken_i & doing_rfe_r;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
doing_rfe_r <= 0;
else if (deassert_doing_rfe)
doing_rfe_r <= 0;
else if (padv_ctrl)
doing_rfe_r <= ctrl_op_rfe_i;
assign spr_sr_o = spr_sr;
// FPU related: FPCSR and exception
generate
`ifdef OR1K_FPCSR_MASK_FLAGS
reg [`OR1K_FPCSR_ALLF_SIZE-1:0] spr_fpcsr_mf; // mask for FPU flags
`endif
/* verilator lint_off WIDTH */
if (FEATURE_FPU != "NONE") begin : fpu_csr_ena
/* verilator lint_on WIDTH */
assign ctrl_fpu_round_mode_o = spr_fpcsr[`OR1K_FPCSR_RM];
// select all flags
`ifdef OR1K_FPCSR_MASK_FLAGS
wire [`OR1K_FPCSR_ALLF_SIZE-1:0] masked_fpres_flags =
ctrl_fpcsr_i[`OR1K_FPCSR_ALLF] & spr_fpcsr_mf;
wire [`OR1K_FPCSR_ALLF_SIZE-1:0] masked_fpcsr_flags =
spr_fpcsr[`OR1K_FPCSR_ALLF] & spr_fpcsr_mf;
wire [`OR1K_FPCSR_ALLF_SIZE-1:0] fpu_allf =
ctrl_fpcsr_set_i ? masked_fpres_flags :
masked_fpcsr_flags;
`else
wire [`OR1K_FPCSR_ALLF_SIZE-1:0] fpu_allf =
ctrl_fpcsr_set_i ? ctrl_fpcsr_i[`OR1K_FPCSR_ALLF] :
spr_fpcsr[`OR1K_FPCSR_ALLF];
`endif
assign except_fpu = (~doing_rfe) &
spr_fpcsr[`OR1K_FPCSR_FPEE] &
(|fpu_allf);
// FPU Control & status register
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
spr_fpcsr <= `OR1K_FPCSR_RESET_VALUE;
`ifdef OR1K_FPCSR_MASK_FLAGS
spr_fpcsr_mf <= `OR1K_FPCSR_MASK_RESET_VALUE;
`endif
end
else if (exception_re) begin
spr_fpcsr[`OR1K_FPCSR_ALLF] <= fpu_allf;
spr_fpcsr[`OR1K_FPCSR_RM] <= spr_fpcsr[`OR1K_FPCSR_RM];
spr_fpcsr[`OR1K_FPCSR_FPEE] <= 1'b0;
end
else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] &
(spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) &&
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR)) begin
spr_fpcsr <= spr_write_dat[`OR1K_FPCSR_WIDTH-1:0]; // update all fields
`ifdef OR1K_FPCSR_MASK_FLAGS
spr_fpcsr_mf <= spr_write_dat[`OR1K_FPCSR_MASK_ALL];
`endif
end
else if (padv_ctrl & ctrl_fpcsr_set_i) begin
spr_fpcsr[`OR1K_FPCSR_ALLF] <= fpu_allf;
spr_fpcsr[`OR1K_FPCSR_RM] <= spr_fpcsr[`OR1K_FPCSR_RM];
spr_fpcsr[`OR1K_FPCSR_FPEE] <= spr_fpcsr[`OR1K_FPCSR_FPEE];
end
end // FPCSR reg's always(@posedge clk)
end
else begin : fpu_csr_none
assign ctrl_fpu_round_mode_o = {`OR1K_FPCSR_RM_SIZE{1'b0}};
assign except_fpu = 0;
// FPU Control & status register
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
spr_fpcsr <= {`OR1K_FPCSR_WIDTH{1'b0}};
`ifdef OR1K_FPCSR_MASK_FLAGS
spr_fpcsr_mf <= {`OR1K_FPCSR_ALLF_SIZE{1'b0}};
`endif
end
end // FPCSR reg's always(@posedge clk)
end
endgenerate // FPU related: FPCSR and exception
// Supervision register
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_sr <= SPR_SR_RESET_VALUE;
else if (exception_re)
begin
// Go into supervisor mode, disable interrupts, MMUs
spr_sr[`OR1K_SPR_SR_SM ] <= 1'b1;
if (FEATURE_TIMER!="NONE")
spr_sr[`OR1K_SPR_SR_TEE ] <= 1'b0;
if (FEATURE_PIC!="NONE")
spr_sr[`OR1K_SPR_SR_IEE ] <= 1'b0;
if (FEATURE_DMMU!="NONE")
spr_sr[`OR1K_SPR_SR_DME ] <= 1'b0;
if (FEATURE_IMMU!="NONE")
spr_sr[`OR1K_SPR_SR_IME ] <= 1'b0;
if (FEATURE_DSX!="NONE")
spr_sr[`OR1K_SPR_SR_DSX ] <= ctrl_delay_slot;
if (FEATURE_OVERFLOW!="NONE")
spr_sr[`OR1K_SPR_SR_OVE ] <= 1'b0;
end
else if ((spr_we & spr_access[`OR1K_SPR_SYS_BASE] &
(spr_sr[`OR1K_SPR_SR_SM] & padv_ctrl | du_access)) &&
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_SR_ADDR))
begin
spr_sr[`OR1K_SPR_SR_SM ] <= spr_write_dat[`OR1K_SPR_SR_SM ];
spr_sr[`OR1K_SPR_SR_F ] <= spr_write_dat[`OR1K_SPR_SR_F ];
if (FEATURE_TIMER!="NONE")
spr_sr[`OR1K_SPR_SR_TEE ] <= spr_write_dat[`OR1K_SPR_SR_TEE ];
if (FEATURE_PIC!="NONE")
spr_sr[`OR1K_SPR_SR_IEE ] <= spr_write_dat[`OR1K_SPR_SR_IEE ];
if (FEATURE_DATACACHE!="NONE")
spr_sr[`OR1K_SPR_SR_DCE ] <= spr_write_dat[`OR1K_SPR_SR_DCE ];
if (FEATURE_INSTRUCTIONCACHE!="NONE")
spr_sr[`OR1K_SPR_SR_ICE ] <= spr_write_dat[`OR1K_SPR_SR_ICE ];
if (FEATURE_DMMU!="NONE")
spr_sr[`OR1K_SPR_SR_DME ] <= spr_write_dat[`OR1K_SPR_SR_DME ];
if (FEATURE_IMMU!="NONE")
spr_sr[`OR1K_SPR_SR_IME ] <= spr_write_dat[`OR1K_SPR_SR_IME ];
if (FEATURE_FASTCONTEXTS!="NONE")
spr_sr[`OR1K_SPR_SR_CE ] <= spr_write_dat[`OR1K_SPR_SR_CE ];
if (FEATURE_CARRY_FLAG!="NONE")
spr_sr[`OR1K_SPR_SR_CY] <= spr_write_dat[`OR1K_SPR_SR_CY];
if (FEATURE_OVERFLOW!="NONE") begin
spr_sr[`OR1K_SPR_SR_OV ] <= spr_write_dat[`OR1K_SPR_SR_OV ];
spr_sr[`OR1K_SPR_SR_OVE ] <= spr_write_dat[`OR1K_SPR_SR_OVE ];
end
if (FEATURE_DSX!="NONE")
spr_sr[`OR1K_SPR_SR_DSX ] <= spr_write_dat[`OR1K_SPR_SR_DSX ];
spr_sr[`OR1K_SPR_SR_EPH ] <= spr_write_dat[`OR1K_SPR_SR_EPH ];
end
else if (padv_ctrl)
begin
spr_sr[`OR1K_SPR_SR_F ] <= ctrl_flag_set ? 1 :
ctrl_flag_clear ? 0 :
spr_sr[`OR1K_SPR_SR_F ];
if (FEATURE_CARRY_FLAG!="NONE")
spr_sr[`OR1K_SPR_SR_CY] <= ctrl_carry_set_i ? 1 :
ctrl_carry_clear_i ? 0 :
spr_sr[`OR1K_SPR_SR_CY];
if (FEATURE_OVERFLOW!="NONE")
spr_sr[`OR1K_SPR_SR_OV ] <= ctrl_overflow_set_i ? 1 :
ctrl_overflow_clear_i ? 0 :
spr_sr[`OR1K_SPR_SR_OV ];
// Skip FO. TODO: make this even more selective.
if (ctrl_op_rfe_i)
spr_sr[14:0] <= spr_esr[14:0];
end
// Exception SR
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_esr <= SPR_SR_RESET_VALUE;
else if (exception_re)
begin
spr_esr <= spr_sr;
if (FEATURE_OVERFLOW!="NONE")
begin
if (ctrl_overflow_set_i)
spr_esr[`OR1K_SPR_SR_OV] <= 1'b1;
else if (ctrl_overflow_clear_i)
spr_esr[`OR1K_SPR_SR_OV] <= 1'b0;
end
if (FEATURE_CARRY_FLAG!="NONE") begin
if (ctrl_carry_set_i)
spr_esr[`OR1K_SPR_SR_CY] <= 1'b1;
else if (ctrl_carry_clear_i)
spr_esr[`OR1K_SPR_SR_CY] <= 1'b0;
end
end
else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_ESR0_ADDR))
spr_esr <= spr_write_dat[SPR_SR_WIDTH-1:0];
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_bubble_o <= 0;
else if (padv_execute_o)
ctrl_bubble_o <= execute_bubble_i;
// Exception PC
always @(posedge clk)
if (exception_re) begin
if (except_ibus_err_i)
spr_epcr <= last_branch_insn_pc;
// Syscall is a special case, we return back to the instruction _after_
// the syscall instruction, unless the syscall was in a delay slot
else if (except_syscall_i)
spr_epcr <= ctrl_delay_slot ? ctrl_epcr_o : pc_ctrl_i + 4;
else if (store_buffer_err_i)
spr_epcr <= store_buffer_epcr_i;
// Don't update EPCR on software breakpoint
else if (!(stall_on_trap & except_trap_i))
spr_epcr <= ctrl_epcr_o;
end else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR)) begin
spr_epcr <= spr_write_dat;
end
// Exception Effective Address
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_eear <= {OPTION_OPERAND_WIDTH{1'b0}};
else if (/*padv_ctrl & exception*/ exception_re)
begin
if (except_ibus_err_i | except_itlb_miss_i | except_ipagefault_i)
spr_eear <= pc_ctrl_i;
else
spr_eear <= ctrl_lsu_adr_i;
end
// Track the PC
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_ppc <= OPTION_RESET_PC;
else if (padv_ctrl)
spr_ppc <= pc_ctrl_i;
// Generate the NPC for SPR accesses
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_npc <= OPTION_RESET_PC;
else if (du_npc_write)
spr_npc <= du_dat_i;
else if (du_npc_written)
spr_npc <= spr_npc;
else if (stepping) begin
if (stepped_into_rfe)
spr_npc <= spr_epcr;
else if (stepped_into_delay_slot)
spr_npc <= last_branch_target_pc;
else if (stepped_into_exception)
spr_npc <= exception_pc_addr;
else
spr_npc <= pc_ctrl_i + 4;
end else if (stall_on_trap & padv_ctrl & except_trap_i)
spr_npc <= pc_ctrl_i;
else if (cpu_stall & padv_ctrl)
spr_npc <= ctrl_delay_slot ? pc_ctrl_i - 4 : pc_ctrl_i;
else if (!cpu_stall)
spr_npc <= pc_execute_i;
// Exception Vector Address
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_evbar <= {OPTION_OPERAND_WIDTH{1'b0}};
else if (spr_we && spr_access[`OR1K_SPR_SYS_BASE] &&
`SPR_OFFSET(spr_addr)==`SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR))
spr_evbar <= {spr_write_dat[OPTION_OPERAND_WIDTH-1:13], 13'd0};
// Remember when we're in a delay slot in execute stage.
always @(posedge clk `OR_ASYNC_RST)
if (rst)
execute_delay_slot <= 0;
else if (padv_execute_o)
execute_delay_slot <= execute_op_branch_i;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
ctrl_delay_slot <= 0;
else if (padv_execute_o)
ctrl_delay_slot <= execute_delay_slot;
mor1kx_cfgrs
#(.FEATURE_PIC (FEATURE_PIC),
.FEATURE_TIMER (FEATURE_TIMER),
.OPTION_PIC_TRIGGER (OPTION_PIC_TRIGGER),
.FEATURE_DSX (FEATURE_DSX),
.FEATURE_FASTCONTEXTS (FEATURE_FASTCONTEXTS),
.OPTION_RF_NUM_SHADOW_GPR (OPTION_RF_NUM_SHADOW_GPR),
.FEATURE_OVERFLOW (FEATURE_OVERFLOW),
.FEATURE_DATACACHE (FEATURE_DATACACHE),
.OPTION_DCACHE_BLOCK_WIDTH (OPTION_DCACHE_BLOCK_WIDTH),
.OPTION_DCACHE_SET_WIDTH (OPTION_DCACHE_SET_WIDTH),
.OPTION_DCACHE_WAYS (OPTION_DCACHE_WAYS),
.FEATURE_DMMU (FEATURE_DMMU),
.OPTION_DMMU_SET_WIDTH (OPTION_DMMU_SET_WIDTH),
.OPTION_DMMU_WAYS (OPTION_DMMU_WAYS),
.FEATURE_INSTRUCTIONCACHE (FEATURE_INSTRUCTIONCACHE),
.OPTION_ICACHE_BLOCK_WIDTH (OPTION_ICACHE_BLOCK_WIDTH),
.OPTION_ICACHE_SET_WIDTH (OPTION_ICACHE_SET_WIDTH),
.OPTION_ICACHE_WAYS (OPTION_ICACHE_WAYS),
.FEATURE_IMMU (FEATURE_IMMU),
.OPTION_IMMU_SET_WIDTH (OPTION_IMMU_SET_WIDTH),
.OPTION_IMMU_WAYS (OPTION_IMMU_WAYS),
.FEATURE_DEBUGUNIT (FEATURE_DEBUGUNIT),
.FEATURE_PERFCOUNTERS (FEATURE_PERFCOUNTERS),
.FEATURE_MAC (FEATURE_MAC),
.FEATURE_FPU (FEATURE_FPU), // mor1kx_cfgrs instance
.FEATURE_SYSCALL (FEATURE_SYSCALL),
.FEATURE_TRAP (FEATURE_TRAP),
.FEATURE_RANGE (FEATURE_RANGE),
.FEATURE_DELAYSLOT ("ENABLED"),
.FEATURE_EVBAR ("ENABLED")
)
mor1kx_cfgrs
(/*AUTOINST*/
// Outputs
.spr_vr (spr_vr[31:0]),
.spr_vr2 (spr_vr2[31:0]),
.spr_upr (spr_upr[31:0]),
.spr_cpucfgr (spr_cpucfgr[31:0]),
.spr_dmmucfgr (spr_dmmucfgr[31:0]),
.spr_immucfgr (spr_immucfgr[31:0]),
.spr_dccfgr (spr_dccfgr[31:0]),
.spr_iccfgr (spr_iccfgr[31:0]),
.spr_dcfgr (spr_dcfgr[31:0]),
.spr_pccfgr (spr_pccfgr[31:0]),
.spr_avr (spr_avr[31:0]));
/* Implementation-specific registers */
assign spr_isr[0] = 0;
assign spr_isr[1] = 0;
assign spr_isr[2] = 0;
assign spr_isr[3] = 0;
assign spr_isr[4] = 0;
assign spr_isr[5] = 0;
assign spr_isr[6] = 0;
assign spr_isr[7] = 0;
// System group (0) SPR data out
always @* begin
spr_sys_group_read = 0;
if (spr_access[`OR1K_SPR_SYS_BASE])
case(`SPR_OFFSET(spr_addr))
`SPR_OFFSET(`OR1K_SPR_VR_ADDR):
spr_sys_group_read = spr_vr;
`SPR_OFFSET(`OR1K_SPR_VR2_ADDR):
spr_sys_group_read = {spr_vr2[31:8], `MOR1KX_PIPEID_CAPPUCCINO};
`SPR_OFFSET(`OR1K_SPR_AVR_ADDR):
spr_sys_group_read = spr_avr;
`SPR_OFFSET(`OR1K_SPR_UPR_ADDR):
spr_sys_group_read = spr_upr;
`SPR_OFFSET(`OR1K_SPR_CPUCFGR_ADDR):
spr_sys_group_read = spr_cpucfgr;
`SPR_OFFSET(`OR1K_SPR_DMMUCFGR_ADDR):
spr_sys_group_read = spr_dmmucfgr;
`SPR_OFFSET(`OR1K_SPR_IMMUCFGR_ADDR):
spr_sys_group_read = spr_immucfgr;
`SPR_OFFSET(`OR1K_SPR_DCCFGR_ADDR):
spr_sys_group_read = spr_dccfgr;
`SPR_OFFSET(`OR1K_SPR_ICCFGR_ADDR):
spr_sys_group_read = spr_iccfgr;
`SPR_OFFSET(`OR1K_SPR_DCFGR_ADDR):
spr_sys_group_read = spr_dcfgr;
`SPR_OFFSET(`OR1K_SPR_PCCFGR_ADDR):
spr_sys_group_read = spr_pccfgr;
`SPR_OFFSET(`OR1K_SPR_NPC_ADDR):
spr_sys_group_read = spr_npc;
`SPR_OFFSET(`OR1K_SPR_SR_ADDR):
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
spr_sr};
`SPR_OFFSET(`OR1K_SPR_PPC_ADDR):
spr_sys_group_read = spr_ppc;
`ifdef OR1K_FPCSR_MASK_FLAGS
`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR):
spr_sys_group_read =
{{(OPTION_OPERAND_WIDTH-`OR1K_FPCSR_WIDTH-`OR1K_FPCSR_ALLF_SIZE){1'b0}},
spr_fpcsr_mf,spr_fpcsr};
`else
`SPR_OFFSET(`OR1K_SPR_FPCSR_ADDR):
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-`OR1K_FPCSR_WIDTH){1'b0}},
spr_fpcsr};
`endif
`SPR_OFFSET(`OR1K_SPR_EPCR0_ADDR):
spr_sys_group_read = spr_epcr;
`SPR_OFFSET(`OR1K_SPR_EEAR0_ADDR):
spr_sys_group_read = spr_eear;
`SPR_OFFSET(`OR1K_SPR_ESR0_ADDR):
spr_sys_group_read = {{(OPTION_OPERAND_WIDTH-SPR_SR_WIDTH){1'b0}},
spr_esr};
`SPR_OFFSET(`OR1K_SPR_EVBAR_ADDR):
spr_sys_group_read = spr_evbar;
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR):
spr_sys_group_read = spr_isr[0];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +1:
spr_sys_group_read = spr_isr[1];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +2:
spr_sys_group_read = spr_isr[2];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +3:
spr_sys_group_read = spr_isr[3];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +4:
spr_sys_group_read = spr_isr[4];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +5:
spr_sys_group_read = spr_isr[5];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +6:
spr_sys_group_read = spr_isr[6];
`SPR_OFFSET(`OR1K_SPR_ISR0_ADDR) +7:
spr_sys_group_read = spr_isr[7];
`SPR_OFFSET(`OR1K_SPR_COREID_ADDR):
// If the multicore feature is activated this address returns the
// core identifier, 0 otherwise
spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ?
multicore_coreid_i : 0;
`SPR_OFFSET(`OR1K_SPR_NUMCORES_ADDR):
// If the multicore feature is activated this address returns the
// core identifier, 0 otherwise
spr_sys_group_read = (FEATURE_MULTICORE!="NONE") ?
multicore_numcores_i : 0;
default:
// GPR read
if (spr_addr[10:9] == 2'h2)
spr_sys_group_read = spr_gpr_dat_i; // Register file
endcase
end
/* System group read data MUX in */
assign spr_internal_read_dat[`OR1K_SPR_SYS_BASE] = spr_sys_group_read;
/* System group ack generation */
assign spr_access_ack[`OR1K_SPR_SYS_BASE] = spr_access[`OR1K_SPR_SYS_BASE] &
((spr_addr[10:9] == 2'h2) ?
spr_gpr_ack_i : 1);
//
// Generate data to the register file for mfspr operations
// Read datas are simply ORed since set to 0 when not
// concerned by spr access.
//
assign mfspr_dat_o = spr_internal_read_dat[`OR1K_SPR_SYS_BASE] |
spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] |
spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] |
spr_internal_read_dat[`OR1K_SPR_DC_BASE] |
spr_internal_read_dat[`OR1K_SPR_IC_BASE] |
spr_internal_read_dat[`OR1K_SPR_MAC_BASE] |
spr_internal_read_dat[`OR1K_SPR_DU_BASE] |
spr_internal_read_dat[`OR1K_SPR_PC_BASE] |
spr_internal_read_dat[`OR1K_SPR_PM_BASE] |
spr_internal_read_dat[`OR1K_SPR_PIC_BASE] |
spr_internal_read_dat[`OR1K_SPR_TT_BASE] |
spr_internal_read_dat[`OR1K_SPR_FPU_BASE];
// PIC SPR control
generate
if (FEATURE_PIC !="NONE") begin : pic
/* mor1kx_pic AUTO_TEMPLATE (
.spr_picsr_o (spr_picsr),
.spr_picmr_o (spr_picmr),
.spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]),
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]),
// Inputs
.spr_we_i (spr_we),
.spr_access_i (spr_access[`OR1K_SPR_PIC_BASE])
.spr_addr_i (spr_addr),
.spr_dat_i (spr_write_dat),
);*/
mor1kx_pic
#(
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH)
)
mor1kx_pic
(/*AUTOINST*/
// Outputs
.spr_picmr_o (spr_picmr), // Templated
.spr_picsr_o (spr_picsr), // Templated
.spr_bus_ack (spr_access_ack[`OR1K_SPR_PIC_BASE]), // Templated
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_PIC_BASE]), // Templated
// Inputs
.clk (clk),
.rst (rst),
.irq_i (irq_i[31:0]),
.spr_access_i (spr_access[`OR1K_SPR_PIC_BASE]), // Templated
.spr_we_i (spr_we), // Templated
.spr_addr_i (spr_addr), // Templated
.spr_dat_i (spr_write_dat)); // Templated
assign except_pic = (|spr_picsr) & spr_sr[`OR1K_SPR_SR_IEE] &
!ctrl_op_mtspr_i & !doing_rfe;
end
else begin
assign except_pic = 0;
assign spr_picsr = 0;
assign spr_picmr = 0;
assign spr_access_ack[`OR1K_SPR_PIC_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_PIC_BASE] = 0;
end // else: !if(FEATURE_PIC !="NONE")
endgenerate
generate
if (FEATURE_TIMER!="NONE") begin : tt
/* mor1kx_ticktimer AUTO_TEMPLATE (
.spr_ttmr_o (spr_ttmr),
.spr_ttcr_o (spr_ttcr),
.spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]),
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]),
// Inputs
.spr_access_i (spr_access[`OR1K_SPR_TT_BASE]),
.spr_we_i (spr_we),
.spr_addr_i (spr_addr),
.spr_dat_i (spr_write_dat),
);*/
mor1kx_ticktimer mor1kx_ticktimer
(/*AUTOINST*/
// Outputs
.spr_ttmr_o (spr_ttmr), // Templated
.spr_ttcr_o (spr_ttcr), // Templated
.spr_bus_ack (spr_access_ack[`OR1K_SPR_TT_BASE]), // Templated
.spr_dat_o (spr_internal_read_dat[`OR1K_SPR_TT_BASE]), // Templated
// Inputs
.clk (clk),
.rst (rst),
.spr_access_i (spr_access[`OR1K_SPR_TT_BASE]), // Templated
.spr_we_i (spr_we), // Templated
.spr_addr_i (spr_addr), // Templated
.spr_dat_i (spr_write_dat)); // Templated
assign except_ticktimer = spr_ttmr[28] & spr_sr[`OR1K_SPR_SR_TEE] &
!ctrl_op_mtspr_i & !doing_rfe;
end // if (FEATURE_TIMER!="NONE")
else begin
assign except_ticktimer = 0;
assign spr_ttmr = 0;
assign spr_ttcr = 0;
assign spr_access_ack[`OR1K_SPR_TT_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_TT_BASE] = 0;
end // else: !if(FEATURE_TIMER!="NONE")
endgenerate
/* SPR access control - allow accesses from either the instructions or from
the debug interface */
assign spr_read_access = (ctrl_op_mfspr_i | (du_access & !du_we_i));
assign spr_write_access = (ctrl_op_mtspr_i | (du_access & du_we_i));
assign spr_write_dat = du_access ? du_dat_i : b;
assign spr_we = spr_write_access & spr_access_valid;
assign spr_read = spr_read_access & spr_access_valid;
/* A bus out to other units that live outside of the control unit */
assign spr_bus_addr_o = spr_addr;
assign spr_bus_we_o = spr_write_access & spr_access_valid & spr_bus_access;
assign spr_bus_stb_o = (spr_read_access | spr_write_access) &
spr_access_valid & spr_bus_access;
assign spr_bus_dat_o = spr_write_dat;
/* Select spr */
always @(*) begin
spr_access <= 0;
case(`SPR_BASE(spr_addr))
// System group
`OR1K_SPR_SYS_BASE:
spr_access[`OR1K_SPR_SYS_BASE] <= 1'b1;
// DMMU
`OR1K_SPR_DMMU_BASE:
spr_access[`OR1K_SPR_DMMU_BASE] <= (FEATURE_DMMU!="NONE");
// IMMU
`OR1K_SPR_IMMU_BASE:
spr_access[`OR1K_SPR_IMMU_BASE] <= (FEATURE_IMMU!="NONE");
// Data cache
`OR1K_SPR_DC_BASE:
spr_access[`OR1K_SPR_DC_BASE] <= (FEATURE_DATACACHE!="NONE");
// Instruction cache
`OR1K_SPR_IC_BASE:
spr_access[`OR1K_SPR_IC_BASE] <= (FEATURE_INSTRUCTIONCACHE!= "NONE");
// MAC unit
`OR1K_SPR_MAC_BASE:
spr_access[`OR1K_SPR_MAC_BASE] <= (FEATURE_MAC!="NONE");
// Debug unit
`OR1K_SPR_DU_BASE:
spr_access[`OR1K_SPR_DU_BASE] <= (FEATURE_DEBUGUNIT!="NONE");
// Performance counters
`OR1K_SPR_PC_BASE:
spr_access[`OR1K_SPR_PC_BASE] <= (FEATURE_PERFCOUNTERS!="NONE");
// Power Management
`OR1K_SPR_PM_BASE:
spr_access[`OR1K_SPR_PM_BASE] <= (FEATURE_PMU!="NONE");
// PIC
`OR1K_SPR_PIC_BASE:
spr_access[`OR1K_SPR_PIC_BASE] <= (FEATURE_PIC!="NONE");
// Tick timer
`OR1K_SPR_TT_BASE:
spr_access[`OR1K_SPR_TT_BASE] <= (FEATURE_TIMER!="NONE");
// FPU
`OR1K_SPR_FPU_BASE:
spr_access[`OR1K_SPR_FPU_BASE] <= (FEATURE_FPU!="NONE");
/* generate invalid if the group is not present in the design */
default:
spr_access <= 0;
endcase
end
// Is the SPR in the design?
assign spr_access_valid = |spr_access;
assign spr_ack = (|spr_access_ack) | !spr_access_valid;
/* Is a SPR bus access needed, or is the requested SPR in this file? */
assign spr_bus_access = /* Any of the units we don't have in this file */
/* System group */
!(spr_access[`OR1K_SPR_SYS_BASE] ||
/* Debug Group */
spr_access[`OR1K_SPR_DU_BASE] ||
/* PIC Group */
spr_access[`OR1K_SPR_PIC_BASE] ||
/* Tick Group */
spr_access[`OR1K_SPR_TT_BASE]) ||
// GPR
(spr_access[`OR1K_SPR_SYS_BASE] &&
spr_addr[10:9]==2'h2);
generate
if (FEATURE_DEBUGUNIT!="NONE") begin : du
reg [OPTION_OPERAND_WIDTH-1:0] du_read_dat;
reg du_ack;
reg du_stall_r;
reg [1:0] branch_step;
assign du_access = du_stb_i;
// Generate ack back to the debug interface bus
always @(posedge clk `OR_ASYNC_RST)
if (rst)
du_ack <= 0;
else if (du_ack)
du_ack <= 0;
else if (du_stb_i) begin
du_ack <= spr_ack;
end
assign du_ack_o = du_ack;
/* Data back to the debug bus */
always @(posedge clk)
du_read_dat <= mfspr_dat_o;
assign du_dat_o = du_read_dat;
always @(posedge clk)
if (rst)
cpu_stall <= 0;
else if (!du_stall_i)
cpu_stall <= 0;
else if (padv_execute_o & !execute_bubble_i & du_stall_i |
du_stall_o)
cpu_stall <= 1;
/* goes out to the debug interface and comes back 1 cycle later
via du_stall_i */
assign du_stall_o = stepping & pstep[4] |
(stall_on_trap & padv_ctrl & except_trap_i);
/* Pulse to indicate we're restarting after a stall */
assign du_restart_from_stall = du_stall_r & !du_stall_i;
/* NPC debug control logic */
assign du_npc_write = (du_we_i && du_addr_i==`OR1K_SPR_NPC_ADDR &&
du_ack_o);
/* Pick the traps-cause-stall bit out of the DSR */
assign stall_on_trap = spr_dsr[`OR1K_SPR_DSR_TE];
/* record if NPC was written while we were stalled.
If so, we will use this value for restarting */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
du_npc_written <= 0;
else if (du_restart_from_stall)
du_npc_written <= 0;
else if (du_npc_write)
du_npc_written <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
stepped_into_exception <= 0;
else if (du_restart_from_stall)
stepped_into_exception <= 0;
else if (exception & stepping & (padv_ctrl | ctrl_stage_exceptions))
stepped_into_exception <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
stepped_into_rfe <= 0;
else if (du_restart_from_stall)
stepped_into_rfe <= 0;
else if (stepping & padv_ctrl)
stepped_into_rfe <= ctrl_op_rfe_i;
assign du_restart_pc_o = spr_npc;
assign du_restart_o = du_restart_from_stall;
/* Indicate when we're stepping */
assign stepping = spr_dmr1[`OR1K_SPR_DMR1_ST] &
spr_dsr[`OR1K_SPR_DSR_TE];
always @(posedge clk `OR_ASYNC_RST)
if (rst)
pstep <= 0;
else if (du_restart_from_stall & stepping)
pstep <= 6'h1;
else if ((pstep[0] & fetch_valid_i) |
/* decode is always single cycle */
(pstep[1] & padv_decode_o) |
/* execute stage */
(pstep[2] & (execute_valid_i | ctrl_stage_exceptions)) |
/* ctrl stage */
(pstep[3] & (ctrl_valid_i | ctrl_stage_exceptions)) |
pstep[4])
pstep <= {pstep[4:0],1'b0};
always @(posedge clk `OR_ASYNC_RST)
if (rst)
branch_step <= 0;
else if (du_npc_written)
branch_step <= 0;
else if (stepping & pstep[2])
branch_step <= {branch_step[0], decode_branch_i};
else if (!stepping & padv_ctrl)
branch_step <= {branch_step[0], ctrl_delay_slot};
assign stepped_into_delay_slot = branch_step[1] & stepping;
/* Signals for waveform debuging */
wire [31:0] spr_read_data_group_0;
assign spr_read_data_group_0 = spr_internal_read_dat[0];
wire [31:0] spr_read_data_group_1;
assign spr_read_data_group_1 = spr_internal_read_dat[1];
wire [31:0] spr_read_data_group_2;
assign spr_read_data_group_2 = spr_internal_read_dat[2];
wire [31:0] spr_read_data_group_3;
assign spr_read_data_group_3 = spr_internal_read_dat[3];
wire [31:0] spr_read_data_group_4;
assign spr_read_data_group_4 = spr_internal_read_dat[4];
wire [31:0] spr_read_data_group_5;
assign spr_read_data_group_5 = spr_internal_read_dat[5];
wire [31:0] spr_read_data_group_6;
assign spr_read_data_group_6 = spr_internal_read_dat[6];
wire [31:0] spr_read_data_group_7;
assign spr_read_data_group_7 = spr_internal_read_dat[7];
wire [31:0] spr_read_data_group_8;
assign spr_read_data_group_8 = spr_internal_read_dat[8];
wire [31:0] spr_read_data_group_9;
assign spr_read_data_group_9 = spr_internal_read_dat[9];
/* always single cycle access */
assign spr_access_ack[`OR1K_SPR_DU_BASE] = spr_access[`OR1K_SPR_DU_BASE];
assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] =
(spr_addr==`OR1K_SPR_DMR1_ADDR) ?
spr_dmr1 :
(spr_addr==`OR1K_SPR_DMR2_ADDR) ?
spr_dmr2 :
(spr_addr==`OR1K_SPR_DSR_ADDR) ?
spr_dsr :
(spr_addr==`OR1K_SPR_DRR_ADDR) ?
spr_drr : 0;
/* Put the incoming stall signal through a register to detect FE */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
du_stall_r <= 0;
else
du_stall_r <= du_stall_i;
/* DMR1 */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_dmr1 <= 0;
else if (spr_we && spr_addr==`OR1K_SPR_DMR1_ADDR)
spr_dmr1[23:0] <= spr_write_dat[23:0];
/* DMR2 */
always @(posedge clk)
spr_dmr2 <= 0;
/* DSR */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_dsr <= 0;
else if (spr_we && spr_addr==`OR1K_SPR_DSR_ADDR)
spr_dsr[13:0] <= spr_write_dat[13:0];
/* DRR */
always @(posedge clk `OR_ASYNC_RST)
if (rst)
spr_drr <= 0;
else if (spr_we && spr_addr==`OR1K_SPR_DRR_ADDR)
spr_drr[13:0] <= spr_write_dat[13:0];
else if (stall_on_trap & padv_ctrl & except_trap_i)
spr_drr[`OR1K_SPR_DRR_TE] <= 1;
end // block: du
else
begin : no_du
assign du_access = 0;
assign du_stall_o = 0;
assign du_ack_o = 0;
assign du_restart_o = 0;
assign du_restart_pc_o = 0;
assign stepping = 0;
assign du_npc_write = 0;
assign stepped_into_delay_slot = 0;
assign du_dat_o = 0;
assign du_restart_from_stall = 0;
assign spr_access_ack[`OR1K_SPR_DU_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_DU_BASE] = 0;
always @(posedge clk)
begin
spr_dmr1 <= 0;
spr_dmr2 <= 0;
spr_dsr <= 0;
spr_drr <= 0;
du_npc_written <= 0;
cpu_stall <= 0;
end
end
endgenerate
// Controls to generate ACKs from units that are external to this module
generate
if (FEATURE_DMMU!="NONE") begin : dmmu_ctrl
assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = spr_bus_ack_dmmu_i &
spr_access[`OR1K_SPR_DMMU_BASE];
assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] =
spr_bus_dat_dmmu_i &
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DMMU_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_DMMU_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_DMMU_BASE] = 0;
end
endgenerate
generate
if (FEATURE_IMMU!="NONE") begin : immu_ctrl
assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = spr_bus_ack_immu_i &
spr_access[`OR1K_SPR_IMMU_BASE];
assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] =
spr_bus_dat_immu_i &
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IMMU_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_IMMU_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_IMMU_BASE] = 0;
end
endgenerate
generate
if (FEATURE_DATACACHE!="NONE") begin : datacache_ctrl
assign spr_access_ack[`OR1K_SPR_DC_BASE] = spr_bus_ack_dc_i &
spr_access[`OR1K_SPR_DC_BASE];
assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] =
spr_bus_dat_dc_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_DC_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_DC_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_DC_BASE] = 0;
end
endgenerate
generate
if (FEATURE_INSTRUCTIONCACHE!="NONE") begin : instructioncache_ctrl
assign spr_access_ack[`OR1K_SPR_IC_BASE] = spr_bus_ack_ic_i &
spr_access[`OR1K_SPR_IC_BASE];
assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] =
spr_bus_dat_ic_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_IC_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_IC_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_IC_BASE] = 0;
end
endgenerate
generate
if (FEATURE_MAC!="NONE") begin : mac_ctrl
assign spr_access_ack[`OR1K_SPR_MAC_BASE] = spr_bus_ack_mac_i &
spr_access[`OR1K_SPR_MAC_BASE];
assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] =
spr_bus_dat_mac_i &
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_MAC_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_MAC_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_MAC_BASE] = 0;
end
endgenerate
generate
if (FEATURE_PERFCOUNTERS!="NONE") begin : perfcounters_ctrl
assign spr_access_ack[`OR1K_SPR_PC_BASE] = spr_bus_ack_pcu_i &
spr_access[`OR1K_SPR_PC_BASE];
assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] =
spr_bus_dat_pcu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PC_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_PC_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_PC_BASE] = 0;
end
endgenerate
generate
if (FEATURE_PMU!="NONE") begin : pmu_ctrl
assign spr_access_ack[`OR1K_SPR_PM_BASE] = spr_bus_ack_pmu_i &
spr_access[`OR1K_SPR_PM_BASE];
assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] =
spr_bus_dat_pmu_i & {OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_PM_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_PM_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_PM_BASE] = 0;
end
endgenerate
generate
if (FEATURE_FPU!="NONE") begin : fpu_ctrl
assign spr_access_ack[`OR1K_SPR_FPU_BASE] = spr_bus_ack_fpu_i;
assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] =
spr_bus_dat_fpu_i &
{OPTION_OPERAND_WIDTH{spr_access[`OR1K_SPR_FPU_BASE]}};
end else begin
assign spr_access_ack[`OR1K_SPR_FPU_BASE] = 0;
assign spr_internal_read_dat[`OR1K_SPR_FPU_BASE] = 0;
end
endgenerate
endmodule // mor1kx_ctrl_cappuccino
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX4_LP_V
`define SKY130_FD_SC_LP__MUX4_LP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_lp (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux4_lp (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX4_LP_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Nov 8 02:18:17 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff3_sign_out, sel_mux_2_reg_0_, data_output2_63_,
cordic_FSM_state_reg_3_, n569, n570, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n706, n707,
n708, n709, n710, n711, n712, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n976, n977, n978,
n979, n980, n981, n982, n983, n984, n985, n986, n987, n988, n989,
n990, n991, n992, n993, n994, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043,
n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053,
n1054, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1266,
n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276,
n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286,
n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296,
n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306,
n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316,
n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326,
n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336,
n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1475,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1543, n1544, n1546, n1547, n1549, n1550, n1551, n1552,
n1553, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1588,
n1591, n1592, n1593, n1594, n1595, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1662, n1663, n1665, n1666,
n1667, n1668, n1669, n1670, n1671, n1672, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1946, n1947, n1948, n1949, n1951, n1953, n1954, n1955, n1956,
n1957, n1958, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1987, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3026,
n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036,
n3037, n3038, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047,
n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057,
n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067,
n3068, n3069, n3070, n3071, n3072, n3073, n3075, n3076, n3077, n3078,
n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088,
n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098,
n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108,
n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118,
n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128,
n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178,
n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188,
n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198,
n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208,
n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218,
n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228,
n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238,
n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248,
n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258,
n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268,
n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278,
n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288,
n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298,
n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308,
n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318,
n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328,
n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338,
n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348,
n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358,
n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368,
n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378,
n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388,
n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398,
n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408,
n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418,
n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428,
n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438,
n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448,
n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458,
n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468,
n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478,
n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488,
n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498,
n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508,
n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518,
n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528,
n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538,
n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548,
n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558,
n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568,
n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578,
n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588,
n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598,
n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608,
n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618,
n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628,
n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638,
n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648,
n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658,
n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668,
n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678,
n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688,
n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698,
n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708,
n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718,
n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728,
n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738,
n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748,
n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758,
n3759, n3763, n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776,
n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786,
n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796,
n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806,
n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816,
n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826,
n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836,
n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846,
n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856,
n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866,
n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876,
n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886,
n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896,
n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906,
n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916,
n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926,
n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936,
n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946,
n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956,
n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966,
n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976,
n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986,
n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996,
n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006,
n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016,
n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026,
n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036,
n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046,
n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056,
n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117,
n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268,
n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278,
n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288,
n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298,
n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308,
n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318,
n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328,
n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338,
n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348,
n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358,
n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368,
n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378,
n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388,
n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398,
n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408,
n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418,
n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428,
n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438,
n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448,
n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458,
n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468,
n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478,
n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488,
n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498,
n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508,
n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518,
n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528,
n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538,
n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548,
n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558,
n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568,
n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578,
n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588,
n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598,
n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608,
n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618,
n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628,
n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638,
n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648,
n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658,
n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668,
n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678,
n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688,
n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698,
n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708,
n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718,
n4719, n4720, n4722;
wire [1:0] cont_var_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:48] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [62:0] sign_inv_out;
DFFRX4TS cont_var_count_reg_1_ ( .D(n1342), .CK(clk), .RN(n1820), .Q(
cont_var_out[1]), .QN(n3893) );
DFFRX4TS cont_var_count_reg_0_ ( .D(n1337), .CK(clk), .RN(n1821), .Q(
cont_var_out[0]), .QN(n3910) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n1284), .CK(clk), .RN(n1772), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n1276), .CK(clk), .RN(n1771), .Q(d_ff1_Z[57]),
.QN(n2439) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n1271), .CK(clk), .RN(n1770), .Q(d_ff1_Z[62]),
.QN(n2441) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n1071), .CK(clk), .RN(n4502), .Q(
sign_inv_out[1]), .QN(n3838) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n1069), .CK(clk), .RN(n1806), .Q(
sign_inv_out[2]), .QN(n3839) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n1053), .CK(clk), .RN(n1627), .Q(
sign_inv_out[10]), .QN(n3846) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n1051), .CK(clk), .RN(n1818), .Q(
sign_inv_out[11]), .QN(n3847) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n1049), .CK(clk), .RN(n4069), .Q(
sign_inv_out[12]), .QN(n3848) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n1047), .CK(clk), .RN(n4489), .Q(
sign_inv_out[13]), .QN(n3849) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n1045), .CK(clk), .RN(n4071), .Q(
sign_inv_out[14]), .QN(n3850) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n1043), .CK(clk), .RN(n4498), .Q(
sign_inv_out[15]), .QN(n3851) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n1039), .CK(clk), .RN(n1776), .Q(
sign_inv_out[17]), .QN(n3853) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n1037), .CK(clk), .RN(n1631), .Q(
sign_inv_out[18]), .QN(n3854) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n1033), .CK(clk), .RN(n1623), .Q(
sign_inv_out[20]), .QN(n3855) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n1031), .CK(clk), .RN(n4482), .Q(
sign_inv_out[21]), .QN(n3856) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n1029), .CK(clk), .RN(n1628), .Q(
sign_inv_out[22]), .QN(n3857) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n1027), .CK(clk), .RN(n4488), .Q(
sign_inv_out[23]), .QN(n3858) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n1025), .CK(clk), .RN(n1632), .Q(
sign_inv_out[24]), .QN(n3859) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n1023), .CK(clk), .RN(n1623), .Q(
sign_inv_out[25]), .QN(n3860) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n1021), .CK(clk), .RN(n1631), .Q(
sign_inv_out[26]), .QN(n3861) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n1019), .CK(clk), .RN(n1771), .Q(
sign_inv_out[27]), .QN(n3862) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n1017), .CK(clk), .RN(n1770), .Q(
sign_inv_out[28]), .QN(n3863) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n1013), .CK(clk), .RN(n1768), .Q(
sign_inv_out[30]), .QN(n3864) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n1011), .CK(clk), .RN(n4086), .Q(
sign_inv_out[31]), .QN(n3865) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n1009), .CK(clk), .RN(n1784), .Q(
sign_inv_out[32]), .QN(n3866) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n1007), .CK(clk), .RN(n4075), .Q(
sign_inv_out[33]), .QN(n3867) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n1005), .CK(clk), .RN(n1626), .Q(
sign_inv_out[34]), .QN(n3868) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n1003), .CK(clk), .RN(n1788), .Q(
sign_inv_out[35]), .QN(n3869) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n1001), .CK(clk), .RN(n1786), .Q(
sign_inv_out[36]), .QN(n3870) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n999), .CK(clk), .RN(n2406), .Q(
sign_inv_out[37]), .QN(n3871) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n997), .CK(clk), .RN(n1798), .Q(
sign_inv_out[38]), .QN(n3872) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n991), .CK(clk), .RN(n1783), .Q(
sign_inv_out[41]), .QN(n3874) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n989), .CK(clk), .RN(n4478), .Q(
sign_inv_out[42]), .QN(n3875) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n987), .CK(clk), .RN(n4486), .Q(
sign_inv_out[43]), .QN(n3876) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n985), .CK(clk), .RN(n4487), .Q(
sign_inv_out[44]), .QN(n3877) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n981), .CK(clk), .RN(n1634), .Q(
sign_inv_out[46]), .QN(n3879) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n979), .CK(clk), .RN(n1801), .Q(
sign_inv_out[47]), .QN(n3880) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n977), .CK(clk), .RN(n4483), .Q(
sign_inv_out[48]), .QN(n3881) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n973), .CK(clk), .RN(n1779), .Q(
sign_inv_out[50]), .QN(n3882) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n971), .CK(clk), .RN(n1813), .Q(
sign_inv_out[51]), .QN(n3883) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n969), .CK(clk), .RN(n1804), .Q(
sign_inv_out[52]), .QN(n3884) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n967), .CK(clk), .RN(n1624), .Q(
sign_inv_out[53]), .QN(n3885) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n965), .CK(clk), .RN(n1789), .Q(
sign_inv_out[54]), .QN(n3886) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n963), .CK(clk), .RN(n4087), .Q(
sign_inv_out[55]), .QN(n3887) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n961), .CK(clk), .RN(n4504), .Q(
sign_inv_out[56]), .QN(n3888) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n959), .CK(clk), .RN(n1807), .Q(
sign_inv_out[57]), .QN(n3889) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n957), .CK(clk), .RN(n1811), .Q(
sign_inv_out[58]), .QN(n3890) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n953), .CK(clk), .RN(n4080), .Q(
sign_inv_out[60]), .QN(n3795) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n951), .CK(clk), .RN(n4499), .Q(
sign_inv_out[61]), .QN(n3796) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n949), .CK(clk), .RN(n4481), .Q(
sign_inv_out[62]), .QN(n3797) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n945), .CK(clk), .RN(n4482), .Q(
d_ff3_LUT_out[0]), .QN(n2162) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n943), .CK(clk), .RN(n1790), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n942), .CK(clk), .RN(n1806), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n940), .CK(clk), .RN(n1805), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n939), .CK(clk), .RN(n1625), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n938), .CK(clk), .RN(n2393), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n936), .CK(clk), .RN(n4072), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n935), .CK(clk), .RN(n1801), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_12_ ( .D(n933), .CK(clk), .RN(n4084), .Q(
d_ff3_LUT_out[12]) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n932), .CK(clk), .RN(n1782), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_LUT_Q_reg_14_ ( .D(n931), .CK(clk), .RN(n1798), .Q(
d_ff3_LUT_out[14]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n930), .CK(clk), .RN(n4083), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS reg_LUT_Q_reg_16_ ( .D(n929), .CK(clk), .RN(n4073), .Q(
d_ff3_LUT_out[16]) );
DFFRX1TS reg_LUT_Q_reg_17_ ( .D(n928), .CK(clk), .RN(n4075), .Q(
d_ff3_LUT_out[17]), .QN(n3924) );
DFFRX1TS reg_LUT_Q_reg_18_ ( .D(n927), .CK(clk), .RN(n1797), .Q(
d_ff3_LUT_out[18]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n926), .CK(clk), .RN(n4079), .Q(
d_ff3_LUT_out[19]), .QN(n2164) );
DFFRX1TS reg_LUT_Q_reg_20_ ( .D(n925), .CK(clk), .RN(n4076), .Q(
d_ff3_LUT_out[20]) );
DFFRX1TS reg_LUT_Q_reg_21_ ( .D(n924), .CK(clk), .RN(n2395), .Q(
d_ff3_LUT_out[21]) );
DFFRX1TS reg_LUT_Q_reg_22_ ( .D(n923), .CK(clk), .RN(n4486), .Q(
d_ff3_LUT_out[22]) );
DFFRX1TS reg_LUT_Q_reg_24_ ( .D(n921), .CK(clk), .RN(n1804), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n919), .CK(clk), .RN(n4497), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n918), .CK(clk), .RN(n1788), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_LUT_Q_reg_28_ ( .D(n917), .CK(clk), .RN(n4500), .Q(
d_ff3_LUT_out[28]) );
DFFRX1TS reg_LUT_Q_reg_29_ ( .D(n916), .CK(clk), .RN(n4082), .Q(
d_ff3_LUT_out[29]), .QN(n2160) );
DFFRX1TS reg_LUT_Q_reg_31_ ( .D(n914), .CK(clk), .RN(n4081), .Q(
d_ff3_LUT_out[31]) );
DFFRX1TS reg_LUT_Q_reg_33_ ( .D(n912), .CK(clk), .RN(n1811), .Q(
d_ff3_LUT_out[33]) );
DFFRX1TS reg_LUT_Q_reg_39_ ( .D(n906), .CK(clk), .RN(n1807), .Q(
d_ff3_LUT_out[39]) );
DFFRX1TS reg_LUT_Q_reg_40_ ( .D(n905), .CK(clk), .RN(n4070), .Q(
d_ff3_LUT_out[40]) );
DFFRX1TS reg_LUT_Q_reg_41_ ( .D(n904), .CK(clk), .RN(n1623), .Q(
d_ff3_LUT_out[41]) );
DFFRX1TS reg_LUT_Q_reg_42_ ( .D(n903), .CK(clk), .RN(n4082), .Q(
d_ff3_LUT_out[42]) );
DFFRX1TS reg_LUT_Q_reg_44_ ( .D(n901), .CK(clk), .RN(n1631), .Q(
d_ff3_LUT_out[44]) );
DFFRX1TS reg_LUT_Q_reg_45_ ( .D(n900), .CK(clk), .RN(n1813), .Q(
d_ff3_LUT_out[45]) );
DFFRX1TS reg_LUT_Q_reg_46_ ( .D(n899), .CK(clk), .RN(n1632), .Q(
d_ff3_LUT_out[46]) );
DFFRX1TS reg_LUT_Q_reg_47_ ( .D(n898), .CK(clk), .RN(n4494), .Q(
d_ff3_LUT_out[47]) );
DFFRX1TS reg_LUT_Q_reg_49_ ( .D(n896), .CK(clk), .RN(n1630), .Q(
d_ff3_LUT_out[49]) );
DFFRX1TS reg_LUT_Q_reg_50_ ( .D(n895), .CK(clk), .RN(n1797), .Q(
d_ff3_LUT_out[50]) );
DFFRX1TS reg_LUT_Q_reg_52_ ( .D(n894), .CK(clk), .RN(n4074), .Q(
d_ff3_LUT_out[52]), .QN(n3956) );
DFFRX1TS reg_LUT_Q_reg_53_ ( .D(n893), .CK(clk), .RN(n1801), .Q(
d_ff3_LUT_out[53]), .QN(n3792) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n890), .CK(clk), .RN(n1630), .Q(
d_ff3_LUT_out[56]), .QN(n3937) );
DFFRX1TS reg_shift_y_Q_reg_52_ ( .D(n709), .CK(clk), .RN(n4083), .Q(
d_ff3_sh_y_out[52]), .QN(n3991) );
DFFRX1TS reg_shift_y_Q_reg_53_ ( .D(n708), .CK(clk), .RN(n1791), .Q(
d_ff3_sh_y_out[53]), .QN(n3793) );
DFFRX1TS reg_shift_y_Q_reg_54_ ( .D(n707), .CK(clk), .RN(n1793), .Q(
d_ff3_sh_y_out[54]), .QN(n3923) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n4084), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n4073), .Q(
d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n1779), .Q(
d_ff2_Z[2]), .QN(n2161) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n1777), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n4505), .Q(
d_ff2_Z[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n4495), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n1778), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n4487), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n1634), .Q(
d_ff2_Z[8]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n1633), .Q(
d_ff2_Z[9]), .QN(n2168) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n836), .CK(clk), .RN(n2389), .Q(
d_ff2_Z[53]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n831), .CK(clk), .RN(n4504), .Q(
d_ff2_Z[58]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n828), .CK(clk), .RN(n4078), .Q(
d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n827), .CK(clk), .RN(n1791), .Q(
d_ff2_Z[62]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n826), .CK(clk), .RN(n4491), .Q(
d_ff2_Z[63]), .QN(n3777) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n824), .CK(clk), .RN(n1792), .Q(
d_ff2_Y[0]), .QN(n3780) );
DFFRX1TS reg_shift_y_Q_reg_0_ ( .D(n823), .CK(clk), .RN(n4496), .Q(
d_ff3_sh_y_out[0]), .QN(n3925) );
DFFRX1TS reg_shift_y_Q_reg_1_ ( .D(n821), .CK(clk), .RN(n1789), .Q(
d_ff3_sh_y_out[1]), .QN(n3926) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n820), .CK(clk), .RN(n1794), .Q(
d_ff2_Y[2]), .QN(n3781) );
DFFRX1TS reg_shift_y_Q_reg_2_ ( .D(n819), .CK(clk), .RN(n1626), .Q(
d_ff3_sh_y_out[2]), .QN(n3927) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n818), .CK(clk), .RN(n1793), .Q(
d_ff2_Y[3]), .QN(n3782) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n816), .CK(clk), .RN(n1787), .Q(
d_ff2_Y[4]), .QN(n3783) );
DFFRX1TS reg_shift_y_Q_reg_4_ ( .D(n815), .CK(clk), .RN(n4488), .Q(
d_ff3_sh_y_out[4]), .QN(n3929) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n814), .CK(clk), .RN(n1618), .Q(
d_ff2_Y[5]), .QN(n3804) );
DFFRX1TS reg_shift_y_Q_reg_5_ ( .D(n813), .CK(clk), .RN(n4485), .Q(
d_ff3_sh_y_out[5]), .QN(n3957) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n812), .CK(clk), .RN(n1785), .Q(
d_ff2_Y[6]), .QN(n3805) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n810), .CK(clk), .RN(n1782), .Q(
d_ff2_Y[7]), .QN(n3806) );
DFFRX1TS reg_shift_y_Q_reg_7_ ( .D(n809), .CK(clk), .RN(n4085), .Q(
d_ff3_sh_y_out[7]), .QN(n3959) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n808), .CK(clk), .RN(n4079), .Q(
d_ff2_Y[8]), .QN(n3807) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n806), .CK(clk), .RN(n1816), .Q(
d_ff2_Y[9]), .QN(n3808) );
DFFRX1TS reg_shift_y_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n1818), .Q(
d_ff3_sh_y_out[9]), .QN(n3961) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n4490), .Q(
d_ff2_Y[10]), .QN(n3809) );
DFFRX1TS reg_shift_y_Q_reg_10_ ( .D(n803), .CK(clk), .RN(n4069), .Q(
d_ff3_sh_y_out[10]), .QN(n3962) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n802), .CK(clk), .RN(n1815), .Q(
d_ff2_Y[11]), .QN(n3810) );
DFFRX1TS reg_shift_y_Q_reg_11_ ( .D(n801), .CK(clk), .RN(n4489), .Q(
d_ff3_sh_y_out[11]), .QN(n3963) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n800), .CK(clk), .RN(n1817), .Q(
d_ff2_Y[12]), .QN(n3811) );
DFFRX1TS reg_shift_y_Q_reg_12_ ( .D(n799), .CK(clk), .RN(n4479), .Q(
d_ff3_sh_y_out[12]), .QN(n3964) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n798), .CK(clk), .RN(n1814), .Q(
d_ff2_Y[13]), .QN(n3812) );
DFFRX1TS reg_shift_y_Q_reg_13_ ( .D(n797), .CK(clk), .RN(n2390), .Q(
d_ff3_sh_y_out[13]), .QN(n3965) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n796), .CK(clk), .RN(n2387), .Q(
d_ff2_Y[14]), .QN(n3813) );
DFFRX1TS reg_shift_y_Q_reg_14_ ( .D(n795), .CK(clk), .RN(n1803), .Q(
d_ff3_sh_y_out[14]), .QN(n3966) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n794), .CK(clk), .RN(n1624), .Q(
d_ff2_Y[15]), .QN(n3784) );
DFFRX1TS reg_shift_y_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n1614), .Q(
d_ff3_sh_y_out[15]), .QN(n3930) );
DFFRX1TS reg_shift_y_Q_reg_16_ ( .D(n791), .CK(clk), .RN(n1611), .Q(
d_ff3_sh_y_out[16]), .QN(n3931) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n790), .CK(clk), .RN(n1617), .Q(
d_ff2_Y[17]), .QN(n3814) );
DFFRX1TS reg_shift_y_Q_reg_17_ ( .D(n789), .CK(clk), .RN(n1802), .Q(
d_ff3_sh_y_out[17]), .QN(n3967) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n788), .CK(clk), .RN(n4488), .Q(
d_ff2_Y[18]), .QN(n3816) );
DFFRX1TS reg_shift_y_Q_reg_18_ ( .D(n787), .CK(clk), .RN(n1786), .Q(
d_ff3_sh_y_out[18]), .QN(n3968) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n784), .CK(clk), .RN(n1803), .Q(
d_ff2_Y[20]), .QN(n3786) );
DFFRX1TS reg_shift_y_Q_reg_20_ ( .D(n783), .CK(clk), .RN(n1614), .Q(
d_ff3_sh_y_out[20]), .QN(n3932) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n782), .CK(clk), .RN(n1617), .Q(
d_ff2_Y[21]), .QN(n3771) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n780), .CK(clk), .RN(n1802), .Q(
d_ff2_Y[22]), .QN(n3819) );
DFFRX1TS reg_shift_y_Q_reg_22_ ( .D(n779), .CK(clk), .RN(n1611), .Q(
d_ff3_sh_y_out[22]), .QN(n3969) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n778), .CK(clk), .RN(n2400), .Q(
d_ff2_Y[23]), .QN(n3787) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n774), .CK(clk), .RN(n4486), .Q(
d_ff2_Y[25]), .QN(n3788) );
DFFRX1TS reg_shift_y_Q_reg_25_ ( .D(n773), .CK(clk), .RN(n1787), .Q(
d_ff3_sh_y_out[25]), .QN(n3933) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n772), .CK(clk), .RN(n1785), .Q(
d_ff2_Y[26]), .QN(n3789) );
DFFRX1TS reg_shift_y_Q_reg_26_ ( .D(n771), .CK(clk), .RN(n1618), .Q(
d_ff3_sh_y_out[26]), .QN(n3934) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n770), .CK(clk), .RN(n4077), .Q(
d_ff2_Y[27]), .QN(n3790) );
DFFRX1TS reg_shift_y_Q_reg_27_ ( .D(n769), .CK(clk), .RN(n4491), .Q(
d_ff3_sh_y_out[27]), .QN(n3935) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n766), .CK(clk), .RN(n2400), .Q(
d_ff2_Y[29]), .QN(n3820) );
DFFRX1TS reg_shift_y_Q_reg_29_ ( .D(n765), .CK(clk), .RN(n4501), .Q(
d_ff3_sh_y_out[29]), .QN(n3970) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n764), .CK(clk), .RN(n2396), .Q(
d_ff2_Y[30]), .QN(n3821) );
DFFRX1TS reg_shift_y_Q_reg_30_ ( .D(n763), .CK(clk), .RN(n4496), .Q(
d_ff3_sh_y_out[30]), .QN(n3971) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n762), .CK(clk), .RN(n4085), .Q(
d_ff2_Y[31]), .QN(n3822) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n760), .CK(clk), .RN(n1808), .Q(
d_ff2_Y[32]), .QN(n3823) );
DFFRX1TS reg_shift_y_Q_reg_32_ ( .D(n759), .CK(clk), .RN(n4075), .Q(
d_ff3_sh_y_out[32]), .QN(n3973) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n758), .CK(clk), .RN(n1784), .Q(
d_ff2_Y[33]), .QN(n3824) );
DFFRX1TS reg_shift_y_Q_reg_33_ ( .D(n757), .CK(clk), .RN(n1627), .Q(
d_ff3_sh_y_out[33]), .QN(n3974) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n756), .CK(clk), .RN(n4483), .Q(
d_ff2_Y[34]), .QN(n3825) );
DFFRX1TS reg_shift_y_Q_reg_34_ ( .D(n755), .CK(clk), .RN(n4087), .Q(
d_ff3_sh_y_out[34]), .QN(n3975) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n754), .CK(clk), .RN(n1783), .Q(
d_ff2_Y[35]), .QN(n3826) );
DFFRX1TS reg_shift_y_Q_reg_35_ ( .D(n753), .CK(clk), .RN(n1780), .Q(
d_ff3_sh_y_out[35]), .QN(n3976) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n752), .CK(clk), .RN(n1628), .Q(
d_ff2_Y[36]), .QN(n3827) );
DFFRX1TS reg_shift_y_Q_reg_36_ ( .D(n751), .CK(clk), .RN(n4502), .Q(
d_ff3_sh_y_out[36]), .QN(n3977) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n750), .CK(clk), .RN(n4086), .Q(
d_ff2_Y[37]), .QN(n3828) );
DFFRX1TS reg_shift_y_Q_reg_37_ ( .D(n749), .CK(clk), .RN(n1771), .Q(
d_ff3_sh_y_out[37]), .QN(n3978) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n748), .CK(clk), .RN(n1775), .Q(
d_ff2_Y[38]), .QN(n3829) );
DFFRX1TS reg_shift_y_Q_reg_38_ ( .D(n747), .CK(clk), .RN(n1774), .Q(
d_ff3_sh_y_out[38]), .QN(n3979) );
DFFRX1TS reg_shift_y_Q_reg_39_ ( .D(n745), .CK(clk), .RN(n1773), .Q(
d_ff3_sh_y_out[39]), .QN(n3980) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n744), .CK(clk), .RN(n1772), .Q(
d_ff2_Y[40]), .QN(n3830) );
DFFRX1TS reg_shift_y_Q_reg_40_ ( .D(n743), .CK(clk), .RN(n4478), .Q(
d_ff3_sh_y_out[40]), .QN(n3981) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n742), .CK(clk), .RN(n1768), .Q(
d_ff2_Y[41]), .QN(n3801) );
DFFRX1TS reg_shift_y_Q_reg_41_ ( .D(n741), .CK(clk), .RN(n4480), .Q(
d_ff3_sh_y_out[41]), .QN(n3982) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n740), .CK(clk), .RN(n2403), .Q(
d_ff2_Y[42]), .QN(n3802) );
DFFRX1TS reg_shift_y_Q_reg_42_ ( .D(n739), .CK(clk), .RN(n1768), .Q(
d_ff3_sh_y_out[42]), .QN(n3983) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n738), .CK(clk), .RN(n1641), .Q(
d_ff2_Y[43]), .QN(n3803) );
DFFRX1TS reg_shift_y_Q_reg_43_ ( .D(n737), .CK(clk), .RN(n4071), .Q(
d_ff3_sh_y_out[43]), .QN(n3984) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n736), .CK(clk), .RN(n1612), .Q(
d_ff2_Y[44]), .QN(n3831) );
DFFRX1TS reg_shift_y_Q_reg_44_ ( .D(n735), .CK(clk), .RN(n1823), .Q(
d_ff3_sh_y_out[44]), .QN(n3985) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n734), .CK(clk), .RN(n1639), .Q(
d_ff2_Y[45]), .QN(n3832) );
DFFRX1TS reg_shift_y_Q_reg_45_ ( .D(n733), .CK(clk), .RN(n1822), .Q(
d_ff3_sh_y_out[45]), .QN(n3986) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n732), .CK(clk), .RN(n1769), .Q(
d_ff2_Y[46]), .QN(n3833) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n730), .CK(clk), .RN(n1770), .Q(
d_ff2_Y[47]), .QN(n3834) );
DFFRX1TS reg_shift_y_Q_reg_47_ ( .D(n729), .CK(clk), .RN(n2392), .Q(
d_ff3_sh_y_out[47]), .QN(n3988) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n728), .CK(clk), .RN(n1795), .Q(
d_ff2_Y[48]), .QN(n3951) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n727), .CK(clk), .RN(n1781), .Q(
d_ff3_sh_y_out[48]), .QN(n3798) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n726), .CK(clk), .RN(n4484), .Q(
d_ff2_Y[49]), .QN(n3835) );
DFFRX1TS reg_shift_y_Q_reg_49_ ( .D(n725), .CK(clk), .RN(n2393), .Q(
d_ff3_sh_y_out[49]), .QN(n3989) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n724), .CK(clk), .RN(n1799), .Q(
d_ff2_Y[50]), .QN(n3836) );
DFFRX1TS reg_shift_y_Q_reg_50_ ( .D(n723), .CK(clk), .RN(n4482), .Q(
d_ff3_sh_y_out[50]), .QN(n3990) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n722), .CK(clk), .RN(n1796), .Q(
d_ff2_Y[51]), .QN(n3953) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n721), .CK(clk), .RN(n4502), .Q(
d_ff3_sh_y_out[51]), .QN(n3799) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n698), .CK(clk), .RN(n4503), .Q(
d_ff2_Y[63]), .QN(n3791) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n697), .CK(clk), .RN(n1617), .Q(
d_ff3_sh_y_out[63]), .QN(n3770) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n696), .CK(clk), .RN(n4493), .Q(
d_ff2_X[0]), .QN(n3900) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n694), .CK(clk), .RN(n4492), .Q(
d_ff2_X[1]), .QN(n3916) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n693), .CK(clk), .RN(n1611), .Q(n2443),
.QN(n4510) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n692), .CK(clk), .RN(n2394), .Q(
d_ff2_X[2]), .QN(n3917) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n691), .CK(clk), .RN(n1803), .Q(n2445),
.QN(n4512) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n690), .CK(clk), .RN(n1812), .Q(
d_ff2_X[3]), .QN(n3773) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n689), .CK(clk), .RN(n1614), .Q(n2447),
.QN(n4513) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n1806), .Q(
d_ff2_X[4]), .QN(n3940) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n2393), .Q(n2424),
.QN(n4515) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n686), .CK(clk), .RN(n1805), .Q(
d_ff2_X[5]), .QN(n3941) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n685), .CK(clk), .RN(n2392), .Q(n2449),
.QN(n4517) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n682), .CK(clk), .RN(n1625), .Q(
d_ff2_X[7]), .QN(n3895) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n681), .CK(clk), .RN(n4484), .Q(n2451),
.QN(n4520) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n680), .CK(clk), .RN(n4072), .Q(
d_ff2_X[8]), .QN(n3896) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n679), .CK(clk), .RN(n1795), .Q(n2426),
.QN(n4521) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n678), .CK(clk), .RN(n4501), .Q(
d_ff2_X[9]), .QN(n3897) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n677), .CK(clk), .RN(n1781), .Q(n2453),
.QN(n4522) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n676), .CK(clk), .RN(n1807), .Q(
d_ff2_X[10]), .QN(n3942) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n675), .CK(clk), .RN(n1630), .Q(n2455),
.QN(n4523) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n673), .CK(clk), .RN(n1779), .Q(n2457),
.QN(n4527) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n672), .CK(clk), .RN(n1804), .Q(
d_ff2_X[12]), .QN(n3943) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n671), .CK(clk), .RN(n4505), .Q(n2459),
.QN(n4529) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n670), .CK(clk), .RN(n1613), .Q(
d_ff2_X[13]), .QN(n3898) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n669), .CK(clk), .RN(n4495), .Q(n2461),
.QN(n4530) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n667), .CK(clk), .RN(n4487), .Q(n2474),
.QN(n4531) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n666), .CK(clk), .RN(n2390), .Q(
d_ff2_X[15]), .QN(n3918) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n664), .CK(clk), .RN(n2396), .Q(
d_ff2_X[16]), .QN(n3919) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n662), .CK(clk), .RN(n2487), .Q(
d_ff2_X[17]), .QN(n3815) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n661), .CK(clk), .RN(n1633), .Q(n2463),
.QN(n4535) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n660), .CK(clk), .RN(n4074), .Q(
d_ff2_X[18]), .QN(n3817) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n659), .CK(clk), .RN(n1634), .Q(n2465),
.QN(n4536) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n658), .CK(clk), .RN(n2406), .Q(
d_ff2_X[19]), .QN(n3899) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n656), .CK(clk), .RN(n1794), .Q(
d_ff2_X[20]), .QN(n3818) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n652), .CK(clk), .RN(n1790), .Q(
d_ff2_X[22]), .QN(n3920) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n650), .CK(clk), .RN(n1798), .Q(
d_ff2_X[23]), .QN(n3944) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n648), .CK(clk), .RN(n4499), .Q(
d_ff2_X[24]), .QN(n3901) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n647), .CK(clk), .RN(n2398), .Q(n2467),
.QN(n4546) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n1820), .Q(
d_ff2_X[25]), .QN(n3921) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n4072), .Q(n2469),
.QN(n4548) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n644), .CK(clk), .RN(n1819), .Q(
d_ff2_X[26]), .QN(n3902) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n643), .CK(clk), .RN(n1625), .Q(n2476),
.QN(n4550) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n642), .CK(clk), .RN(n4481), .Q(
d_ff2_X[27]), .QN(n3945) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n641), .CK(clk), .RN(n2387), .Q(n2478),
.QN(n4552) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n639), .CK(clk), .RN(n4081), .Q(n2480),
.QN(n4554) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n636), .CK(clk), .RN(n1613), .Q(
d_ff2_X[30]), .QN(n3946) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n635), .CK(clk), .RN(n4070), .Q(n2482),
.QN(n4560) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n633), .CK(clk), .RN(n2394), .Q(n2484),
.QN(n4561) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n630), .CK(clk), .RN(n1796), .Q(
d_ff2_X[33]), .QN(n3947) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n629), .CK(clk), .RN(n1774), .Q(n2428),
.QN(n4564) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n627), .CK(clk), .RN(n1775), .Q(n2430),
.QN(n4566) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n623), .CK(clk), .RN(n1821), .Q(n2432),
.QN(n4568) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n622), .CK(clk), .RN(n4498), .Q(
d_ff2_X[37]), .QN(n3948) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n621), .CK(clk), .RN(n4497), .Q(n2412),
.QN(n4569) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n620), .CK(clk), .RN(n1799), .Q(
d_ff2_X[38]), .QN(n3938) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n619), .CK(clk), .RN(n4078), .Q(n2414),
.QN(n4570) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n617), .CK(clk), .RN(n4493), .Q(n2416),
.QN(n4572) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n616), .CK(clk), .RN(n1776), .Q(
d_ff2_X[40]), .QN(n3939) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n615), .CK(clk), .RN(n1796), .Q(n2418),
.QN(n4573) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n613), .CK(clk), .RN(n1794), .Q(n2420),
.QN(n4575) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n608), .CK(clk), .RN(n1810), .Q(
d_ff2_X[44]), .QN(n3949) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n607), .CK(clk), .RN(n1802), .Q(n2471),
.QN(n4581) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n605), .CK(clk), .RN(n2400), .Q(n2434),
.QN(n4582) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n603), .CK(clk), .RN(n2390), .Q(n2436),
.QN(n4584) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n602), .CK(clk), .RN(n4080), .Q(
d_ff2_X[47]), .QN(n3950) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n601), .CK(clk), .RN(n2396), .Q(n2422),
.QN(n4586) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_48_ ( .D(n600), .CK(clk), .RN(n2487), .Q(
d_ff2_X[48]), .QN(n4588) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2187), .CK(clk), .RN(n4074), .Q(
d_ff3_sh_x_out[48]), .QN(n3936) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n596), .CK(clk), .RN(n2487), .Q(
d_ff2_X[50]), .QN(n3952) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n594), .CK(clk), .RN(n4485), .Q(
d_ff2_X[51]), .QN(n3954) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n593), .CK(clk), .RN(n4077), .Q(
d_ff3_sh_x_out[51]), .QN(n3794) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n570), .CK(clk), .RN(n1792), .Q(
d_ff2_X[63]), .QN(n3922) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n569), .CK(clk), .RN(n1800), .Q(
d_ff3_sh_x_out[63]), .QN(n3778) );
DFFSX1TS R_13 ( .D(n4614), .CK(clk), .SN(n1796), .Q(n4456) );
DFFSX1TS R_33 ( .D(n4518), .CK(clk), .SN(n2396), .Q(n4442) );
DFFSX1TS R_34 ( .D(n4509), .CK(clk), .SN(n2390), .Q(n4441) );
DFFSX1TS R_35 ( .D(n4508), .CK(clk), .SN(n1802), .Q(n4440) );
DFFSX2TS R_81 ( .D(n2301), .CK(clk), .SN(n1822), .Q(n4412) );
DFFSX1TS R_82 ( .D(n4596), .CK(clk), .SN(n2395), .Q(n4411) );
DFFSX1TS R_83 ( .D(n4595), .CK(clk), .SN(n1799), .Q(n4410) );
DFFSX2TS R_114 ( .D(n4526), .CK(clk), .SN(n4491), .Q(n4388) );
DFFSX2TS R_238 ( .D(n4609), .CK(clk), .SN(n4486), .Q(n4320) );
DFFSX2TS R_529 ( .D(n4603), .CK(clk), .SN(n4498), .Q(n4164) );
DFFSX2TS R_530 ( .D(n4602), .CK(clk), .SN(n1822), .Q(n4163) );
DFFRX1TS R_543 ( .D(n4599), .CK(clk), .RN(n1786), .Q(n4159) );
DFFSX1TS R_586 ( .D(n4606), .CK(clk), .SN(n1798), .Q(n4129) );
DFFSX1TS R_587 ( .D(n4605), .CK(clk), .SN(n4083), .Q(n4128) );
DFFSX1TS R_588 ( .D(n4604), .CK(clk), .SN(n1800), .Q(n4127) );
DFFSX1TS R_628 ( .D(n4600), .CK(clk), .SN(n2406), .Q(n4098) );
DFFSX2TS R_629 ( .D(n4601), .CK(clk), .SN(n1823), .Q(n4097) );
DFFSX1TS R_630 ( .D(n2157), .CK(clk), .SN(n2487), .Q(n4096) );
DFFSX1TS R_631 ( .D(n4612), .CK(clk), .SN(n1801), .Q(n4095) );
DFFSX1TS R_632 ( .D(n4611), .CK(clk), .SN(n1797), .Q(n4094) );
DFFSX1TS R_633 ( .D(n4610), .CK(clk), .SN(n1616), .Q(n4093) );
DFFSX2TS R_552 ( .D(n4616), .CK(clk), .SN(n1612), .QN(n3904) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n1072), .CK(clk), .RN(n1772), .Q(
data_output[0]), .QN(n4007) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n1070), .CK(clk), .RN(n1817), .Q(
data_output[1]), .QN(n4008) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n4076), .Q(
data_output[2]), .QN(n4009) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n1066), .CK(clk), .RN(n2403), .Q(
data_output[3]), .QN(n4010) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n1064), .CK(clk), .RN(n1772), .Q(
data_output[4]), .QN(n4011) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n1062), .CK(clk), .RN(n4480), .Q(
data_output[5]), .QN(n4012) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n1060), .CK(clk), .RN(n4478), .Q(
data_output[6]), .QN(n4013) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n1058), .CK(clk), .RN(n1628), .Q(
data_output[7]), .QN(n4014) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n1056), .CK(clk), .RN(n4086), .Q(
data_output[8]), .QN(n4015) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n1054), .CK(clk), .RN(n1783), .Q(
data_output[9]), .QN(n4016) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n1052), .CK(clk), .RN(n1815), .Q(
data_output[10]), .QN(n4017) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n1050), .CK(clk), .RN(n4490), .Q(
data_output[11]), .QN(n4018) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n1048), .CK(clk), .RN(n1816), .Q(
data_output[12]), .QN(n4019) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n1046), .CK(clk), .RN(n4479), .Q(
data_output[13]), .QN(n4020) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n1044), .CK(clk), .RN(n1612), .Q(
data_output[14]), .QN(n4021) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n1042), .CK(clk), .RN(n1822), .Q(
data_output[15]), .QN(n4022) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n1040), .CK(clk), .RN(n1823), .Q(
data_output[16]), .QN(n4023) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n1038), .CK(clk), .RN(n1777), .Q(
data_output[17]), .QN(n4024) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n1036), .CK(clk), .RN(n4500), .Q(
data_output[18]), .QN(n4025) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n1034), .CK(clk), .RN(n1632), .Q(
data_output[19]), .QN(n4026) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n1032), .CK(clk), .RN(n1790), .Q(
data_output[20]), .QN(n4027) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n1030), .CK(clk), .RN(n4495), .Q(
data_output[21]), .QN(n4028) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n1028), .CK(clk), .RN(n1780), .Q(
data_output[22]), .QN(n4029) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n1026), .CK(clk), .RN(n4480), .Q(
data_output[23]), .QN(n4030) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n1024), .CK(clk), .RN(n1768), .Q(
data_output[24]), .QN(n4031) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n1022), .CK(clk), .RN(n1775), .Q(
data_output[25]), .QN(n4032) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n1020), .CK(clk), .RN(n1776), .Q(
data_output[26]), .QN(n4033) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n1018), .CK(clk), .RN(n1641), .Q(
data_output[27]), .QN(n4034) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n1016), .CK(clk), .RN(n1769), .Q(
data_output[28]), .QN(n4035) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n1014), .CK(clk), .RN(n1639), .Q(
data_output[29]), .QN(n4036) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n1012), .CK(clk), .RN(n1616), .Q(
data_output[30]), .QN(n4037) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n1010), .CK(clk), .RN(n1773), .Q(
data_output[31]), .QN(n4038) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n1008), .CK(clk), .RN(n4505), .Q(
data_output[32]), .QN(n4039) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n1006), .CK(clk), .RN(n1785), .Q(
data_output[33]), .QN(n4040) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n1004), .CK(clk), .RN(n1792), .Q(
data_output[34]), .QN(n4041) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n1002), .CK(clk), .RN(n4491), .Q(
data_output[35]), .QN(n4042) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n1000), .CK(clk), .RN(n4496), .Q(
data_output[36]), .QN(n4043) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n998), .CK(clk), .RN(n4083), .Q(
data_output[37]), .QN(n4044) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n996), .CK(clk), .RN(n4084), .Q(
data_output[38]), .QN(n4045) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n994), .CK(clk), .RN(n4073), .Q(
data_output[39]), .QN(n4046) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n992), .CK(clk), .RN(n1774), .Q(
data_output[40]), .QN(n4047) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n990), .CK(clk), .RN(n1618), .Q(
data_output[41]), .QN(n4048) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n988), .CK(clk), .RN(n1627), .Q(
data_output[42]), .QN(n4049) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n986), .CK(clk), .RN(n1787), .Q(
data_output[43]), .QN(n4050) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n984), .CK(clk), .RN(n4500), .Q(
data_output[44]), .QN(n4051) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n982), .CK(clk), .RN(n1777), .Q(
data_output[45]), .QN(n4052) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n980), .CK(clk), .RN(n1633), .Q(
data_output[46]), .QN(n4053) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n978), .CK(clk), .RN(n1782), .Q(
data_output[47]), .QN(n4054) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n976), .CK(clk), .RN(n4085), .Q(
data_output[48]), .QN(n4055) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n974), .CK(clk), .RN(n4079), .Q(
data_output[49]), .QN(n4056) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n972), .CK(clk), .RN(n2395), .Q(
data_output[50]), .QN(n4057) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n970), .CK(clk), .RN(n1793), .Q(
data_output[51]), .QN(n4058) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n968), .CK(clk), .RN(n4494), .Q(
data_output[52]), .QN(n4059) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n966), .CK(clk), .RN(n1773), .Q(
data_output[53]), .QN(n4060) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n964), .CK(clk), .RN(n1613), .Q(
data_output[54]), .QN(n4061) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n962), .CK(clk), .RN(n1778), .Q(
data_output[55]), .QN(n4062) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n960), .CK(clk), .RN(n4485), .Q(
data_output[56]), .QN(n4063) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n958), .CK(clk), .RN(n2403), .Q(
data_output[57]), .QN(n4064) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n956), .CK(clk), .RN(n1799), .Q(
data_output[58]), .QN(n4065) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n954), .CK(clk), .RN(n1791), .Q(
data_output[59]), .QN(n4066) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n952), .CK(clk), .RN(n2389), .Q(
data_output[60]), .QN(n4004) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n950), .CK(clk), .RN(n1819), .Q(
data_output[61]), .QN(n4005) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n948), .CK(clk), .RN(n1820), .Q(
data_output[62]), .QN(n4006) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(n825), .CK(clk), .RN(n4068), .Q(
d_ff3_sign_out), .QN(n4003) );
DFFSX2TS R_170 ( .D(n3727), .CK(clk), .SN(n1814), .Q(n4358) );
DFFSX2TS R_171 ( .D(n4559), .CK(clk), .SN(n4482), .Q(n4357) );
DFFSX2TS R_210 ( .D(n4559), .CK(clk), .SN(n1795), .Q(n4332) );
DFFSX2TS R_4 ( .D(n2076), .CK(clk), .SN(n1639), .Q(n4463) );
DFFSX2TS R_25 ( .D(n4583), .CK(clk), .SN(n4502), .Q(n4448) );
DFFSX2TS R_28 ( .D(n4576), .CK(clk), .SN(n4086), .Q(n4446) );
DFFSX2TS R_31 ( .D(n2174), .CK(clk), .SN(n1618), .Q(n4444) );
DFFSX2TS R_37 ( .D(n1544), .CK(clk), .SN(n1796), .Q(n4439) );
DFFSX2TS R_43 ( .D(n2159), .CK(clk), .SN(n4488), .Q(n4435) );
DFFSX2TS R_46 ( .D(n4571), .CK(clk), .SN(n4492), .Q(n4433) );
DFFSX2TS R_52 ( .D(n2112), .CK(clk), .SN(n1802), .Q(n4429) );
DFFSX2TS R_58 ( .D(n2014), .CK(clk), .SN(n4501), .Q(n4424) );
DFFSX2TS R_61 ( .D(n4677), .CK(clk), .SN(n1812), .Q(n4422) );
DFFSX2TS R_64 ( .D(n4658), .CK(clk), .SN(n2393), .Q(n4420) );
DFFSX2TS R_67 ( .D(n4643), .CK(clk), .SN(n4484), .Q(n4419) );
DFFSX2TS R_70 ( .D(n2001), .CK(clk), .SN(n1613), .QN(n2003) );
DFFSX2TS R_73 ( .D(n2075), .CK(clk), .SN(n4078), .Q(n4418) );
DFFSX2TS R_76 ( .D(n1603), .CK(clk), .SN(n1813), .Q(n4416), .QN(n1940) );
DFFSX2TS R_79 ( .D(n4692), .CK(clk), .SN(n4068), .Q(n4414) );
DFFSX2TS R_85 ( .D(n2028), .CK(clk), .SN(n4085), .Q(n4408) );
DFFSX2TS R_91 ( .D(n2127), .CK(clk), .SN(n1804), .Q(n4404) );
DFFSX2TS R_94 ( .D(n2097), .CK(clk), .SN(n1613), .Q(n4402) );
DFFSX2TS R_112 ( .D(n2307), .CK(clk), .SN(n1783), .Q(n4390) );
DFFSX2TS R_119 ( .D(n2031), .CK(clk), .SN(n1782), .Q(n4383) );
DFFSX2TS R_122 ( .D(n2135), .CK(clk), .SN(n1623), .Q(n4381), .QN(n1978) );
DFFSX2TS R_128 ( .D(n2352), .CK(clk), .SN(n1623), .Q(n4378) );
DFFSX2TS R_131 ( .D(n4675), .CK(clk), .SN(n4493), .Q(n4376) );
DFFSX2TS R_134 ( .D(n4656), .CK(clk), .SN(n4482), .Q(n4375) );
DFFSX2TS R_137 ( .D(n4641), .CK(clk), .SN(n2392), .Q(n4374) );
DFFSX2TS R_140 ( .D(n1824), .CK(clk), .SN(n2393), .QN(n1826) );
DFFSX2TS R_143 ( .D(n4574), .CK(clk), .SN(n1628), .Q(n4372) );
DFFSX2TS R_149 ( .D(n2345), .CK(clk), .SN(n1768), .Q(n4368) );
DFFSX2TS R_152 ( .D(n2251), .CK(clk), .SN(n4478), .Q(n4366), .QN(n2037) );
DFFSX2TS R_155 ( .D(n1610), .CK(clk), .SN(n1811), .Q(n4365), .QN(n1834) );
DFFSX2TS R_158 ( .D(n4690), .CK(clk), .SN(n1821), .Q(n4363) );
DFFSX2TS R_161 ( .D(n2302), .CK(clk), .SN(n4087), .QN(n1973) );
DFFSX2TS R_164 ( .D(n1949), .CK(clk), .SN(n4480), .Q(n1565) );
DFFSX2TS R_167 ( .D(n4714), .CK(clk), .SN(n4079), .Q(n4361) );
DFFSX2TS R_179 ( .D(n2067), .CK(clk), .SN(n1799), .Q(n4353) );
DFFSX2TS R_182 ( .D(n2070), .CK(clk), .SN(n1790), .Q(n4351) );
DFFSX2TS R_188 ( .D(n1951), .CK(clk), .SN(n4071), .Q(n4345) );
DFFSX2TS R_191 ( .D(n2040), .CK(clk), .SN(n1626), .Q(n4343) );
DFFSX2TS R_194 ( .D(n2022), .CK(clk), .SN(n1807), .Q(n4341) );
DFFSX2TS R_197 ( .D(n2313), .CK(clk), .SN(n1780), .QN(n1957) );
DFFSX2TS R_206 ( .D(n1970), .CK(clk), .SN(n4501), .Q(n4335) );
DFFSX2TS R_212 ( .D(n1993), .CK(clk), .SN(n2394), .Q(n4331), .QN(n1927) );
DFFSX2TS R_215 ( .D(n4654), .CK(clk), .SN(n1790), .QN(n1842) );
DFFSX2TS R_218 ( .D(n2015), .CK(clk), .SN(n2393), .Q(n4330) );
DFFSX2TS R_221 ( .D(n2172), .CK(clk), .SN(n1806), .QN(n2051) );
DFFSX2TS R_224 ( .D(n1962), .CK(clk), .SN(n1794), .Q(n4328) );
DFFSX2TS R_227 ( .D(n2096), .CK(clk), .SN(n1793), .Q(n4327) );
DFFSX2TS R_230 ( .D(n2303), .CK(clk), .SN(n1626), .QN(n2304) );
DFFSX2TS R_233 ( .D(n2253), .CK(clk), .SN(n1772), .Q(n4324) );
DFFSX2TS R_236 ( .D(n2343), .CK(clk), .SN(n1790), .Q(n4322) );
DFFSX2TS R_242 ( .D(n4553), .CK(clk), .SN(n1800), .Q(n4317) );
DFFSX2TS R_245 ( .D(n4549), .CK(clk), .SN(n4079), .Q(n4315) );
DFFSX2TS R_248 ( .D(n2074), .CK(clk), .SN(n1627), .Q(n4313) );
DFFSX2TS R_251 ( .D(n2245), .CK(clk), .SN(n1802), .Q(n4311) );
DFFSX2TS R_257 ( .D(n2008), .CK(clk), .SN(n4492), .Q(n4306) );
DFFSX2TS R_260 ( .D(n2004), .CK(clk), .SN(n1820), .Q(n4304) );
DFFSX2TS R_263 ( .D(n2243), .CK(clk), .SN(n1823), .Q(n4302) );
DFFSX2TS R_296 ( .D(n2120), .CK(clk), .SN(n1788), .Q(n4296) );
DFFSX2TS R_299 ( .D(n2033), .CK(clk), .SN(n1786), .Q(n4293) );
DFFSX2TS R_302 ( .D(n2346), .CK(clk), .SN(n1627), .Q(n4290) );
DFFSX2TS R_305 ( .D(n1968), .CK(clk), .SN(n1627), .QN(n1969) );
DFFSX2TS R_308 ( .D(n1965), .CK(clk), .SN(n1791), .Q(n4288), .QN(n1828) );
DFFSX2TS R_311 ( .D(n1948), .CK(clk), .SN(n4087), .Q(n4286) );
DFFSX2TS R_314 ( .D(n2042), .CK(clk), .SN(n1794), .Q(n4284) );
DFFSX2TS R_317 ( .D(n2126), .CK(clk), .SN(n1632), .Q(n4283), .QN(n1955) );
DFFSX2TS R_320 ( .D(n2034), .CK(clk), .SN(n4486), .Q(n4282) );
DFFSX2TS R_323 ( .D(n2038), .CK(clk), .SN(n1793), .QN(n2039) );
DFFSX2TS R_326 ( .D(n2114), .CK(clk), .SN(n4495), .Q(n4279) );
DFFSX2TS R_329 ( .D(n1979), .CK(clk), .SN(n1789), .Q(n4278) );
DFFSX2TS R_335 ( .D(n1947), .CK(clk), .SN(n1778), .Q(n4274) );
DFFSX2TS R_338 ( .D(n2344), .CK(clk), .SN(n1780), .Q(n4272) );
DFFSX2TS R_341 ( .D(n1971), .CK(clk), .SN(n1631), .QN(n1972) );
DFFSX2TS R_344 ( .D(n2134), .CK(clk), .SN(n4505), .Q(n4271) );
DFFSX2TS R_347 ( .D(n2367), .CK(clk), .SN(n4075), .Q(n4269), .QN(n2017) );
DFFSX2TS R_353 ( .D(n2193), .CK(clk), .SN(n4078), .Q(n4264) );
DFFSX2TS R_362 ( .D(n1983), .CK(clk), .SN(n1784), .Q(n4259) );
DFFSX2TS R_368 ( .D(n2244), .CK(clk), .SN(n1817), .Q(n4253) );
DFFSX2TS R_383 ( .D(n2024), .CK(clk), .SN(n1818), .Q(n4247) );
DFFSX2TS R_410 ( .D(n2242), .CK(clk), .SN(n1792), .Q(n4229) );
DFFSX2TS R_413 ( .D(n4711), .CK(clk), .SN(n1802), .Q(n4227) );
DFFSX2TS R_416 ( .D(n4672), .CK(clk), .SN(n1613), .Q(n4226) );
DFFSX2TS R_419 ( .D(n2009), .CK(clk), .SN(n1805), .Q(n4225) );
DFFSX2TS R_422 ( .D(n2000), .CK(clk), .SN(n4489), .Q(n4224) );
DFFSX2TS R_425 ( .D(n2171), .CK(clk), .SN(n2403), .Q(n4223) );
DFFSX2TS R_428 ( .D(n2052), .CK(clk), .SN(n2398), .QN(n2054) );
DFFSX2TS R_431 ( .D(n1990), .CK(clk), .SN(n1797), .Q(n4220) );
DFFSX2TS R_434 ( .D(n4670), .CK(clk), .SN(n1807), .Q(n4218) );
DFFSX2TS R_437 ( .D(n4651), .CK(clk), .SN(n4082), .Q(n4217) );
DFFSX2TS R_440 ( .D(n1609), .CK(clk), .SN(n1788), .Q(n4215) );
DFFSX2TS R_443 ( .D(n2170), .CK(clk), .SN(n1794), .Q(n4214) );
DFFSX2TS R_446 ( .D(n1923), .CK(clk), .SN(n1625), .Q(n4211) );
DFFSX2TS R_449 ( .D(n4686), .CK(clk), .SN(n4073), .Q(n4208) );
DFFSX2TS R_461 ( .D(n4626), .CK(clk), .SN(n1793), .Q(n4204) );
DFFSX2TS R_464 ( .D(n1992), .CK(clk), .SN(n2400), .Q(n4202) );
DFFSX2TS R_467 ( .D(n1985), .CK(clk), .SN(n4072), .Q(n4199) );
DFFSX2TS R_473 ( .D(n4666), .CK(clk), .SN(n1804), .Q(n4195) );
DFFSX2TS R_476 ( .D(n2057), .CK(clk), .SN(n1809), .Q(n4194) );
DFFSX2TS R_479 ( .D(n1991), .CK(clk), .SN(n4073), .Q(n4193) );
DFFSX2TS R_482 ( .D(n1608), .CK(clk), .SN(n1792), .Q(n4191) );
DFFSX2TS R_485 ( .D(n4700), .CK(clk), .SN(n1806), .Q(n4189) );
DFFSX2TS R_488 ( .D(n4683), .CK(clk), .SN(n4084), .Q(n4187) );
DFFSX2TS R_491 ( .D(n4664), .CK(clk), .SN(n1624), .Q(n4186) );
DFFSX2TS R_494 ( .D(n1994), .CK(clk), .SN(n1818), .Q(n4185) );
DFFSX2TS R_497 ( .D(n2058), .CK(clk), .SN(n1821), .Q(n4184) );
DFFSX2TS R_500 ( .D(n2342), .CK(clk), .SN(n4496), .QN(n2010) );
DFFSX2TS R_503 ( .D(n4698), .CK(clk), .SN(n4503), .Q(n4182) );
DFFSX2TS R_506 ( .D(n4681), .CK(clk), .SN(n1623), .Q(n4179) );
DFFSX2TS R_509 ( .D(n4708), .CK(clk), .SN(n2390), .Q(n4176) );
DFFSX2TS R_512 ( .D(n4662), .CK(clk), .SN(n2387), .Q(n4174) );
DFFSX2TS R_515 ( .D(n1995), .CK(clk), .SN(n4069), .Q(n4171) );
DFFSX2TS R_518 ( .D(n4633), .CK(clk), .SN(n1820), .Q(n4170) );
DFFSX2TS R_521 ( .D(n1845), .CK(clk), .SN(n1789), .QN(n1847) );
DFFSX2TS R_524 ( .D(n4696), .CK(clk), .SN(n1812), .Q(n4167) );
DFFSX2TS R_527 ( .D(n1607), .CK(clk), .SN(n1631), .Q(n4165) );
DFFSX2TS R_532 ( .D(n4660), .CK(clk), .SN(n4081), .Q(n4162) );
DFFSX2TS R_535 ( .D(n4645), .CK(clk), .SN(n4489), .Q(n4161) );
DFFSX2TS R_538 ( .D(n2046), .CK(clk), .SN(n4481), .Q(n4160) );
DFFSX2TS R_541 ( .D(n2055), .CK(clk), .SN(n1626), .QN(n2056) );
DFFSX2TS R_547 ( .D(n4694), .CK(clk), .SN(n4493), .Q(n4157) );
DFFSX2TS R_550 ( .D(n1999), .CK(clk), .SN(n1776), .Q(n4154) );
DFFSX2TS R_554 ( .D(n4589), .CK(clk), .SN(n1787), .Q(n4153) );
DFFSX2TS R_557 ( .D(n4578), .CK(clk), .SN(n4479), .Q(n4151) );
DFFSX2TS R_560 ( .D(n2110), .CK(clk), .SN(n4483), .Q(n4149) );
DFFSX2TS R_566 ( .D(n2309), .CK(clk), .SN(n1771), .Q(n4145) );
DFFSX2TS R_569 ( .D(n2062), .CK(clk), .SN(n1617), .Q(n4143) );
DFFSX2TS R_572 ( .D(n2061), .CK(clk), .SN(n4077), .Q(n4140) );
DFFSX2TS R_578 ( .D(n4587), .CK(clk), .SN(n1807), .Q(n4135) );
DFFSX2TS R_596 ( .D(n2116), .CK(clk), .SN(n1776), .Q(n4121) );
DFFSX2TS R_599 ( .D(n2173), .CK(clk), .SN(n1611), .Q(n4119) );
DFFSX2TS R_605 ( .D(n2132), .CK(clk), .SN(n2400), .Q(n4115) );
DFFSX2TS R_608 ( .D(n2072), .CK(clk), .SN(n1777), .Q(n4113) );
DFFSX2TS R_611 ( .D(n4555), .CK(clk), .SN(n4079), .Q(n4111) );
DFFSX2TS R_614 ( .D(n2069), .CK(clk), .SN(n4486), .Q(n4109) );
DFFSX2TS R_617 ( .D(n1989), .CK(clk), .SN(n1787), .Q(n4107) );
DFFSX2TS R_620 ( .D(n2071), .CK(clk), .SN(n2390), .Q(n4105) );
DFFSX2TS R_623 ( .D(n2064), .CK(clk), .SN(n4502), .Q(n4103) );
DFFSX2TS R_638 ( .D(n1528), .CK(clk), .SN(n1770), .Q(n4089) );
DFFSX2TS R_57 ( .D(n4621), .CK(clk), .SN(n1804), .Q(n4425) );
DFFSX2TS R_69 ( .D(n4713), .CK(clk), .SN(n1611), .QN(n2002) );
DFFSX2TS R_78 ( .D(n4693), .CK(clk), .SN(n4481), .Q(n4415) );
DFFSX2TS R_84 ( .D(n4638), .CK(clk), .SN(n4075), .Q(n4409) );
DFFSX2TS R_118 ( .D(n4632), .CK(clk), .SN(n1784), .Q(n4384) );
DFFSX2TS R_148 ( .D(n4657), .CK(clk), .SN(n1822), .Q(n4369) );
DFFSX2TS R_151 ( .D(n4648), .CK(clk), .SN(n1771), .Q(n4367), .QN(n2036) );
DFFSX2TS R_157 ( .D(n4691), .CK(clk), .SN(n4499), .Q(n4364) );
DFFSX2TS R_166 ( .D(n4631), .CK(clk), .SN(n4483), .Q(n4362) );
DFFSX2TS R_187 ( .D(n4663), .CK(clk), .SN(n1612), .Q(n4346) );
DFFSX2TS R_190 ( .D(n4628), .CK(clk), .SN(n1787), .Q(n4344) );
DFFSX2TS R_193 ( .D(n4627), .CK(clk), .SN(n1803), .Q(n4342), .QN(n1475) );
DFFSX2TS R_205 ( .D(n4697), .CK(clk), .SN(n1634), .Q(n4336) );
DFFSX2TS R_232 ( .D(n4650), .CK(clk), .SN(n1770), .Q(n4325) );
DFFSX2TS R_256 ( .D(n4705), .CK(clk), .SN(n4503), .Q(n4307) );
DFFSX2TS R_259 ( .D(n4689), .CK(clk), .SN(n1819), .Q(n4305) );
DFFSX2TS R_262 ( .D(n4667), .CK(clk), .SN(n4498), .Q(n4303) );
DFFSX2TS R_295 ( .D(n4635), .CK(clk), .SN(n1618), .Q(n4297) );
DFFSX2TS R_298 ( .D(n4637), .CK(clk), .SN(n1785), .Q(n4294) );
DFFSX2TS R_301 ( .D(n4659), .CK(clk), .SN(n4502), .Q(n4291) );
DFFSX2TS R_307 ( .D(n4649), .CK(clk), .SN(n1792), .Q(n4289), .QN(n1829) );
DFFSX2TS R_310 ( .D(n4665), .CK(clk), .SN(n1781), .Q(n4287) );
DFFSX2TS R_313 ( .D(n4646), .CK(clk), .SN(n4491), .Q(n4285) );
DFFSX2TS R_325 ( .D(n4634), .CK(clk), .SN(n4487), .Q(n4280) );
DFFSX2TS R_334 ( .D(n4629), .CK(clk), .SN(n1634), .Q(n4275) );
DFFSX2TS R_337 ( .D(n4655), .CK(clk), .SN(n1630), .Q(n4273) );
DFFSX2TS R_352 ( .D(n4669), .CK(clk), .SN(n4069), .Q(n4265) );
DFFSX2TS R_367 ( .D(n4671), .CK(clk), .SN(n4489), .Q(n4254) );
DFFSX2TS R_382 ( .D(n4661), .CK(clk), .SN(n4479), .Q(n4248) );
DFFSX2TS R_409 ( .D(n4624), .CK(clk), .SN(n2396), .Q(n4230) );
DFFSX2TS R_412 ( .D(n4712), .CK(clk), .SN(n2487), .Q(n4228) );
DFFSX2TS R_427 ( .D(n4704), .CK(clk), .SN(n1805), .QN(n2053) );
DFFSX2TS R_430 ( .D(n4688), .CK(clk), .SN(n4083), .Q(n4221) );
DFFSX2TS R_445 ( .D(n4703), .CK(clk), .SN(n4082), .Q(n4212) );
DFFSX2TS R_448 ( .D(n4687), .CK(clk), .SN(n2406), .Q(n4209) );
DFFSX2TS R_463 ( .D(n4710), .CK(clk), .SN(n4074), .Q(n4203) );
DFFSX2TS R_466 ( .D(n4702), .CK(clk), .SN(n1809), .Q(n4200) );
DFFSX2TS R_484 ( .D(n4701), .CK(clk), .SN(n2394), .Q(n4190) );
DFFSX2TS R_487 ( .D(n4684), .CK(clk), .SN(n1775), .Q(n4188) );
DFFSX2TS R_502 ( .D(n4699), .CK(clk), .SN(n1810), .Q(n4183) );
DFFSX2TS R_505 ( .D(n4682), .CK(clk), .SN(n2486), .Q(n4180) );
DFFSX2TS R_508 ( .D(n4709), .CK(clk), .SN(n1616), .Q(n4177) );
DFFSX2TS R_514 ( .D(n4647), .CK(clk), .SN(n4479), .Q(n4172) );
DFFSX2TS R_523 ( .D(n4697), .CK(clk), .SN(n4080), .Q(n4168) );
DFFSX2TS R_526 ( .D(n4680), .CK(clk), .SN(n2403), .Q(n4166) );
DFFSX2TS R_546 ( .D(n4695), .CK(clk), .SN(n1624), .Q(n4158) );
DFFSX2TS R_549 ( .D(n4679), .CK(clk), .SN(n1774), .Q(n4155) );
DFFSX2TS R_571 ( .D(n4630), .CK(clk), .SN(n1781), .Q(n4141) );
DFFSX2TS R_637 ( .D(n4705), .CK(clk), .SN(n4076), .Q(n4090) );
DFFSX2TS R_5 ( .D(n4467), .CK(clk), .SN(n1769), .Q(n4462) );
DFFSX2TS R_26 ( .D(n4469), .CK(clk), .SN(n4085), .Q(n4447) );
DFFSX2TS R_29 ( .D(n4470), .CK(clk), .SN(n4499), .Q(n4445) );
DFFSX2TS R_32 ( .D(n4470), .CK(clk), .SN(n1809), .Q(n4443) );
DFFSX2TS R_38 ( .D(n4466), .CK(clk), .SN(n4497), .Q(n4438) );
DFFSX2TS R_44 ( .D(n4468), .CK(clk), .SN(n4485), .Q(n4434) );
DFFSX2TS R_47 ( .D(n4467), .CK(clk), .SN(n2394), .Q(n4432) );
DFFSX2TS R_59 ( .D(n4474), .CK(clk), .SN(n1614), .Q(n4423) );
DFFSX2TS R_62 ( .D(n1636), .CK(clk), .SN(n4080), .Q(n4421) );
DFFSX2TS R_74 ( .D(n4467), .CK(clk), .SN(n1787), .Q(n4417) );
DFFSX2TS R_80 ( .D(n3254), .CK(clk), .SN(n2389), .Q(n4413) );
DFFSX2TS R_86 ( .D(n2402), .CK(clk), .SN(n1783), .Q(n4407) );
DFFSX2TS R_92 ( .D(n4470), .CK(clk), .SN(n4074), .Q(n4403) );
DFFSX2TS R_95 ( .D(n4469), .CK(clk), .SN(n2396), .Q(n4401) );
DFFSX2TS R_120 ( .D(n2402), .CK(clk), .SN(n4086), .Q(n4382) );
DFFSX2TS R_141 ( .D(n3254), .CK(clk), .SN(n1774), .Q(n4373) );
DFFSX2TS R_168 ( .D(n4472), .CK(clk), .SN(n1628), .Q(n4360) );
DFFSX2TS R_180 ( .D(n4466), .CK(clk), .SN(n2392), .Q(n4352) );
DFFSX2TS R_183 ( .D(n2388), .CK(clk), .SN(n1811), .Q(n4350) );
DFFSX2TS R_219 ( .D(n4474), .CK(clk), .SN(n4482), .Q(n4329) );
DFFSX2TS R_228 ( .D(n2402), .CK(clk), .SN(n4496), .Q(n4326) );
DFFSX2TS R_234 ( .D(n4472), .CK(clk), .SN(n1639), .Q(n4323) );
DFFSX2TS R_237 ( .D(n2402), .CK(clk), .SN(n1769), .Q(n4321) );
DFFSX2TS R_246 ( .D(n4470), .CK(clk), .SN(n4075), .Q(n4314) );
DFFSX2TS R_249 ( .D(n4470), .CK(clk), .SN(n4494), .Q(n4312) );
DFFSX2TS R_252 ( .D(n4470), .CK(clk), .SN(n2396), .Q(n4310) );
DFFSX2TS R_297 ( .D(n4472), .CK(clk), .SN(n4488), .Q(n4295) );
DFFSX2TS R_300 ( .D(n4472), .CK(clk), .SN(n4485), .Q(n4292) );
DFFSX2TS R_321 ( .D(n4472), .CK(clk), .SN(n4077), .Q(n4281) );
DFFSX2TS R_426 ( .D(n4474), .CK(clk), .SN(n4482), .Q(n4222) );
DFFSX2TS R_432 ( .D(n1636), .CK(clk), .SN(n4504), .Q(n4219) );
DFFSX2TS R_438 ( .D(n3254), .CK(clk), .SN(n4501), .Q(n4216) );
DFFSX2TS R_444 ( .D(n3254), .CK(clk), .SN(n4491), .Q(n4213) );
DFFSX2TS R_447 ( .D(n3254), .CK(clk), .SN(n1808), .Q(n4210) );
DFFSX2TS R_480 ( .D(n1636), .CK(clk), .SN(n1795), .Q(n4192) );
DFFSX2TS R_504 ( .D(n4474), .CK(clk), .SN(n4081), .Q(n4181) );
DFFSX2TS R_507 ( .D(n3254), .CK(clk), .SN(n1773), .Q(n4178) );
DFFSX2TS R_510 ( .D(n4474), .CK(clk), .SN(n1800), .Q(n4175) );
DFFSX2TS R_513 ( .D(n4474), .CK(clk), .SN(n1625), .Q(n4173) );
DFFSX2TS R_522 ( .D(n3254), .CK(clk), .SN(n1788), .Q(n4169) );
DFFSX2TS R_548 ( .D(n4474), .CK(clk), .SN(n2387), .Q(n4156) );
DFFSX2TS R_555 ( .D(n2388), .CK(clk), .SN(n4504), .Q(n4152) );
DFFSX2TS R_558 ( .D(n4466), .CK(clk), .SN(n1627), .Q(n4150) );
DFFSX2TS R_561 ( .D(n2388), .CK(clk), .SN(n4478), .Q(n4148) );
DFFSX2TS R_567 ( .D(n4470), .CK(clk), .SN(n1784), .Q(n4144) );
DFFSX2TS R_579 ( .D(n4466), .CK(clk), .SN(n1816), .Q(n4134) );
DFFSX2TS R_597 ( .D(n2388), .CK(clk), .SN(n4485), .Q(n4120) );
DFFSX2TS R_600 ( .D(n4466), .CK(clk), .SN(n1632), .Q(n4118) );
DFFSX2TS R_606 ( .D(n4467), .CK(clk), .SN(n4487), .Q(n4114) );
DFFSX2TS R_609 ( .D(n4468), .CK(clk), .SN(n1618), .Q(n4112) );
DFFSX2TS R_612 ( .D(n4468), .CK(clk), .SN(n1784), .Q(n4110) );
DFFSX2TS R_615 ( .D(n2388), .CK(clk), .SN(n1618), .Q(n4108) );
DFFSX2TS R_618 ( .D(n2140), .CK(clk), .SN(n2393), .Q(n4106) );
DFFSX2TS R_621 ( .D(n2388), .CK(clk), .SN(n1616), .Q(n4104) );
DFFSX2TS R_624 ( .D(n4466), .CK(clk), .SN(n1779), .Q(n4102) );
DFFSX2TS R_200 ( .D(n4619), .CK(clk), .SN(n1626), .Q(n4339) );
DFFSX2TS R_201 ( .D(n4618), .CK(clk), .SN(n1797), .Q(n4338) );
DFFSX2TS R_199 ( .D(n4620), .CK(clk), .SN(n1798), .Q(n4340) );
DFFSX2TS R_332 ( .D(n3992), .CK(clk), .SN(n4491), .Q(n4277) );
DFFSX2TS R_350 ( .D(n3996), .CK(clk), .SN(n1779), .Q(n4267) );
DFFSX2TS R_371 ( .D(n4001), .CK(clk), .SN(n1628), .Q(n4252) );
DFFSX2TS R_386 ( .D(n3995), .CK(clk), .SN(n4490), .Q(n4245) );
DFFSX2TS R_389 ( .D(n4000), .CK(clk), .SN(n4485), .Q(n4244) );
DFFSX2TS R_392 ( .D(n3993), .CK(clk), .SN(n1633), .Q(n4242) );
DFFSX2TS R_395 ( .D(n3994), .CK(clk), .SN(n1815), .Q(n4240) );
DFFSX2TS R_398 ( .D(n2030), .CK(clk), .SN(n1814), .Q(n4238) );
DFFSX2TS R_401 ( .D(n3998), .CK(clk), .SN(n4495), .Q(n4236) );
DFFSX2TS R_404 ( .D(n3997), .CK(clk), .SN(n1778), .Q(n4234) );
DFFSX2TS R_407 ( .D(n3999), .CK(clk), .SN(n4488), .Q(n4232) );
DFFSX2TS R_349 ( .D(n4653), .CK(clk), .SN(n1816), .Q(n4268) );
DFFSX2TS R_385 ( .D(n4652), .CK(clk), .SN(n4070), .Q(n4246) );
DFFSX2TS R_391 ( .D(n4636), .CK(clk), .SN(n1777), .Q(n4243) );
DFFSX2TS R_397 ( .D(n4639), .CK(clk), .SN(n4494), .Q(n4239) );
DFFSX2TS R_351 ( .D(n4472), .CK(clk), .SN(n4505), .Q(n4266) );
DFFSX2TS R_393 ( .D(n2402), .CK(clk), .SN(n4500), .Q(n4241) );
DFFSX2TS R_399 ( .D(n2402), .CK(clk), .SN(n1813), .Q(n4237) );
DFFSX2TS R_1 ( .D(n2306), .CK(clk), .SN(n1771), .Q(n4465), .QN(n2105) );
DFFSX2TS R_7 ( .D(n4585), .CK(clk), .SN(n1630), .Q(n4461) );
DFFSX2TS R_10 ( .D(n2322), .CK(clk), .SN(n1785), .Q(n4459) );
DFFSX2TS R_16 ( .D(n4516), .CK(clk), .SN(n4081), .Q(n4454) );
DFFSX2TS R_19 ( .D(n4617), .CK(clk), .SN(n1770), .Q(n4452) );
DFFSX2TS R_40 ( .D(n4551), .CK(clk), .SN(n1772), .Q(n4437) );
DFFSX2TS R_49 ( .D(n2297), .CK(clk), .SN(n1812), .Q(n4431) );
DFFSX2TS R_55 ( .D(n4540), .CK(clk), .SN(n1633), .Q(n4427) );
DFFSX2TS R_88 ( .D(n4580), .CK(clk), .SN(n1781), .Q(n4406) );
DFFSX2TS R_97 ( .D(n4558), .CK(clk), .SN(n1801), .Q(n4400) );
DFFSX2TS R_100 ( .D(n4542), .CK(clk), .SN(n4070), .Q(n4398) );
DFFSX2TS R_103 ( .D(n4538), .CK(clk), .SN(n2387), .Q(n4396) );
DFFSX2TS R_106 ( .D(n1541), .CK(clk), .SN(n1773), .Q(n4394) );
DFFSX2TS R_109 ( .D(n4514), .CK(clk), .SN(n4484), .Q(n4392) );
DFFSX2TS R_125 ( .D(n2278), .CK(clk), .SN(n1788), .Q(n4380) );
DFFSX2TS R_146 ( .D(n2279), .CK(clk), .SN(n4505), .Q(n4370) );
DFFSX2TS R_176 ( .D(n4533), .CK(clk), .SN(n1774), .Q(n4355) );
DFFSX2TS R_185 ( .D(n2066), .CK(clk), .SN(n2403), .Q(n4348) );
DFFSX2TS R_203 ( .D(n2117), .CK(clk), .SN(n4495), .Q(n4337) );
DFFSX2TS R_254 ( .D(n4511), .CK(clk), .SN(n1776), .Q(n4309) );
DFFSX2TS R_284 ( .D(n1977), .CK(clk), .SN(n1776), .Q(n4300) );
DFFSX2TS R_289 ( .D(n2321), .CK(clk), .SN(n1808), .Q(n4299) );
DFFSX2TS R_356 ( .D(n2032), .CK(clk), .SN(n4483), .Q(n4262) );
DFFSX2TS R_359 ( .D(n1958), .CK(clk), .SN(n1778), .QN(n1943) );
DFFSX2TS R_452 ( .D(n4668), .CK(clk), .SN(n1611), .Q(n4207) );
DFFSX2TS R_455 ( .D(n2045), .CK(clk), .SN(n1808), .Q(n4206) );
DFFSX2TS R_458 ( .D(n2007), .CK(clk), .SN(n4481), .Q(n4205) );
DFFSX2TS R_470 ( .D(n2013), .CK(clk), .SN(n2395), .Q(n4197) );
DFFSX2TS R_563 ( .D(n4547), .CK(clk), .SN(n4480), .Q(n4147) );
DFFSX2TS R_575 ( .D(n4507), .CK(clk), .SN(n1774), .Q(n4137) );
DFFSX2TS R_581 ( .D(n2296), .CK(clk), .SN(n4503), .Q(n4133), .QN(n2108) );
DFFSX2TS R_584 ( .D(n4528), .CK(clk), .SN(n2400), .Q(n4131) );
DFFSX2TS R_590 ( .D(n4544), .CK(clk), .SN(n4072), .Q(n4126) );
DFFSX2TS R_593 ( .D(n2065), .CK(clk), .SN(n2487), .Q(n4123) );
DFFSX2TS R_626 ( .D(n1905), .CK(clk), .SN(n1820), .Q(n4100) );
DFFSX2TS R_175 ( .D(n4640), .CK(clk), .SN(n2486), .Q(n4356) );
DFFSX2TS R_184 ( .D(n4642), .CK(clk), .SN(n1775), .Q(n4349) );
DFFSX2TS R_469 ( .D(n4685), .CK(clk), .SN(n1799), .Q(n4198) );
DFFSX2TS R_574 ( .D(n4623), .CK(clk), .SN(n1773), .Q(n4138) );
DFFSX2TS R_592 ( .D(n4644), .CK(clk), .SN(n1815), .Q(n4124) );
DFFSX2TS R_625 ( .D(n4697), .CK(clk), .SN(n4490), .Q(n4101) );
DFFSX2TS R_8 ( .D(n4468), .CK(clk), .SN(n1779), .Q(n4460) );
DFFSX2TS R_17 ( .D(n2388), .CK(clk), .SN(n4071), .Q(n4453) );
DFFSX2TS R_20 ( .D(n4470), .CK(clk), .SN(n1768), .Q(n4451) );
DFFSX2TS R_41 ( .D(n4467), .CK(clk), .SN(n1639), .Q(n4436) );
DFFSX2TS R_50 ( .D(n4468), .CK(clk), .SN(n4478), .Q(n4430) );
DFFSX2TS R_56 ( .D(n4467), .CK(clk), .SN(n4082), .Q(n4426) );
DFFSX2TS R_89 ( .D(n4469), .CK(clk), .SN(n1782), .Q(n4405) );
DFFSX2TS R_98 ( .D(n4470), .CK(clk), .SN(n1797), .Q(n4399) );
DFFSX2TS R_104 ( .D(n4468), .CK(clk), .SN(n4078), .Q(n4395) );
DFFSX2TS R_107 ( .D(n4467), .CK(clk), .SN(n1628), .Q(n4393) );
DFFSX2TS R_110 ( .D(n4468), .CK(clk), .SN(n4488), .Q(n4391) );
DFFSX2TS R_177 ( .D(n4468), .CK(clk), .SN(n4086), .Q(n4354) );
DFFSX2TS R_186 ( .D(n4466), .CK(clk), .SN(n4480), .Q(n4347) );
DFFSX2TS R_255 ( .D(n4469), .CK(clk), .SN(n1771), .Q(n4308) );
DFFSX2TS R_471 ( .D(n4474), .CK(clk), .SN(n1796), .Q(n4196) );
DFFSX2TS R_576 ( .D(n4470), .CK(clk), .SN(n2390), .Q(n4136) );
DFFSX2TS R_582 ( .D(n2388), .CK(clk), .SN(n1810), .Q(n4132), .QN(n2109) );
DFFSX2TS R_585 ( .D(n4466), .CK(clk), .SN(n2487), .Q(n4130) );
DFFSX2TS R_591 ( .D(n2388), .CK(clk), .SN(n4500), .Q(n4125) );
DFFSX2TS R_594 ( .D(n4466), .CK(clk), .SN(n4068), .Q(n4122) );
DFFSX2TS R_627 ( .D(n2388), .CK(clk), .SN(n1819), .Q(n4099) );
DFFSX1TS R_363 ( .D(n2618), .CK(clk), .SN(n4084), .Q(n4258) );
DFFSX1TS R_375 ( .D(n4471), .CK(clk), .SN(n4074), .Q(n4250) );
DFFSX1TS R_357 ( .D(n4471), .CK(clk), .SN(n4073), .Q(n4261) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_52_ ( .D(n592), .CK(clk), .RN(n4086), .Q(
d_ff2_X[52]) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n715), .CK(clk), .RN(n1807), .Q(
d_ff2_Y[57]), .QN(n3903) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n591), .CK(clk), .RN(n4485), .Q(
d_ff2_X[53]), .QN(n3892) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n589), .CK(clk), .RN(n1784), .Q(
d_ff2_X[55]), .QN(n3772) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n714), .CK(clk), .RN(n1804), .Q(
d_ff2_Y[58]), .QN(n3913) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n711), .CK(clk), .RN(n1613), .Q(
d_ff2_Y[61]), .QN(n3911) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n717), .CK(clk), .RN(n1803), .Q(
d_ff2_Y[55]), .QN(n3915) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n716), .CK(clk), .RN(n1611), .Q(
d_ff2_Y[56]), .QN(n4473) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n1785), .Q(
d_ff2_Z[23]) );
DFFSX1TS R_209 ( .D(n2624), .CK(clk), .SN(n2400), .Q(n4333) );
DFFRHQX1TS reg_LUT_Q_reg_23_ ( .D(n922), .CK(clk), .RN(n2387), .Q(
d_ff3_LUT_out[23]) );
DFFRHQX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n684), .CK(clk), .RN(n2398),
.Q(d_ff2_X[6]) );
DFFRHQX1TS reg_shift_y_Q_reg_23_ ( .D(n777), .CK(clk), .RN(n1624), .Q(
d_ff3_sh_y_out[23]) );
DFFRHQX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n654), .CK(clk), .RN(n1625),
.Q(d_ff2_X[21]) );
DFFRHQX1TS reg_LUT_Q_reg_43_ ( .D(n902), .CK(clk), .RN(n4081), .Q(
d_ff3_LUT_out[43]) );
DFFRHQX8TS cordic_FSM_state_reg_reg_3_ ( .D(n1345), .CK(clk), .RN(n4722),
.Q(cordic_FSM_state_reg_3_) );
DFFSHQX8TS cordic_FSM_state_reg_reg_1_ ( .D(n3759), .CK(clk), .SN(n4722),
.Q(n3894) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n908), .CK(clk), .RN(n1810), .Q(
d_ff3_LUT_out[37]), .QN(n3955) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n807), .CK(clk), .RN(n4501), .Q(
d_ff3_sh_y_out[8]), .QN(n3960) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n761), .CK(clk), .RN(n4087), .Q(
d_ff3_sh_y_out[31]), .QN(n3972) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n731), .CK(clk), .RN(n4503), .Q(
d_ff3_sh_y_out[46]), .QN(n3987) );
DFFSRHQX4TS reg_LUT_Q_reg_36_ ( .D(n909), .CK(clk), .SN(1'b1), .RN(n1817),
.Q(d_ff3_LUT_out[36]) );
DFFSRHQX4TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n879), .CK(clk), .SN(1'b1),
.RN(n4504), .Q(d_ff2_Z[10]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n638), .CK(clk), .RN(n1814), .Q(
d_ff2_X[29]), .QN(n4556) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n634), .CK(clk), .RN(n4494), .Q(
d_ff2_X[31]), .QN(n3907) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n640), .CK(clk), .RN(n1815), .Q(
d_ff2_X[28]), .QN(n3906) );
DFFRX2TS reg_Z0_Q_reg_6_ ( .D(n1327), .CK(clk), .RN(n4489), .Q(d_ff1_Z[6])
);
DFFRX2TS reg_Z0_Q_reg_4_ ( .D(n1329), .CK(clk), .RN(n4479), .Q(d_ff1_Z[4])
);
DFFRX2TS reg_Z0_Q_reg_8_ ( .D(n1325), .CK(clk), .RN(n4081), .Q(d_ff1_Z[8])
);
DFFRX2TS reg_Z0_Q_reg_5_ ( .D(n1328), .CK(clk), .RN(n1816), .Q(d_ff1_Z[5])
);
DFFRX2TS reg_Z0_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n2398), .Q(d_ff1_Z[7])
);
DFFSX4TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n3763), .CK(clk), .SN(n1614),
.Q(n2355), .QN(d_ff2_Y[59]) );
DFFSX2TS R_275 ( .D(n2024), .CK(clk), .SN(n1782), .QN(n2333) );
DFFSX2TS R_278 ( .D(n2042), .CK(clk), .SN(n1792), .Q(n4301) );
DFFSX2TS R_281 ( .D(n2031), .CK(clk), .SN(n2389), .QN(n2327) );
DFFSX4TS R_239 ( .D(n4608), .CK(clk), .SN(n1804), .Q(n4319) );
DFFRX1TS reg_shift_x_Q_reg_15_ ( .D(n665), .CK(clk), .RN(n1616), .QN(n4532)
);
DFFRX1TS reg_shift_x_Q_reg_21_ ( .D(n653), .CK(clk), .RN(n1616), .QN(n4541)
);
DFFRX1TS reg_shift_x_Q_reg_16_ ( .D(n663), .CK(clk), .RN(n1800), .QN(n4534)
);
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n587), .CK(clk), .RN(n1768),
.Q(d_ff2_X[57]) );
DFFSRHQX4TS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n843), .CK(clk), .SN(1'b1),
.RN(n4078), .Q(d_ff2_Z[46]) );
DFFRX2TS reg_Z0_Q_reg_32_ ( .D(n1301), .CK(clk), .RN(n4493), .Q(d_ff1_Z[32])
);
DFFRX2TS reg_Z0_Q_reg_30_ ( .D(n1303), .CK(clk), .RN(n2394), .Q(d_ff1_Z[30])
);
DFFRX2TS reg_Z0_Q_reg_28_ ( .D(n1305), .CK(clk), .RN(n4080), .Q(d_ff1_Z[28])
);
DFFRX2TS reg_Z0_Q_reg_27_ ( .D(n1306), .CK(clk), .RN(n1624), .Q(d_ff1_Z[27])
);
DFFRX2TS reg_Z0_Q_reg_29_ ( .D(n1304), .CK(clk), .RN(n2387), .Q(d_ff1_Z[29])
);
DFFSRHQX4TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n877), .CK(clk), .SN(1'b1),
.RN(n1819), .Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n848), .CK(clk), .RN(n1789), .Q(
d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n849), .CK(clk), .RN(n1626), .Q(
d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n847), .CK(clk), .RN(n1800), .Q(
d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n850), .CK(clk), .RN(n1788), .Q(
d_ff2_Z[39]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n1778), .Q(
d_ff2_Z[14]) );
DFFRX1TS reg_Z0_Q_reg_41_ ( .D(n1292), .CK(clk), .RN(n4068), .Q(d_ff1_Z[41])
);
DFFRX1TS reg_Z0_Q_reg_39_ ( .D(n1294), .CK(clk), .RN(n1821), .Q(d_ff1_Z[39])
);
DFFRX4TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n4077), .Q(
d_ff2_Z[22]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1777), .Q(
d_ff2_Z[21]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n4087), .Q(
d_ff2_Z[20]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n4505), .Q(
d_ff2_Z[19]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n4502), .Q(
d_ff2_Z[17]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n4487), .Q(
d_ff2_Z[16]) );
DFFSX2TS R_240 ( .D(n4607), .CK(clk), .SN(n1801), .Q(n4318) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n792), .CK(clk), .RN(n4075), .Q(
d_ff2_Y[16]), .QN(n3785) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n822), .CK(clk), .RN(n2390), .Q(
d_ff2_Y[1]), .QN(n3779) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n674), .CK(clk), .RN(n1809), .Q(
d_ff2_X[11]), .QN(n3905) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n614), .CK(clk), .RN(n1614), .Q(
d_ff2_X[41]), .QN(n2631) );
DFFSRHQX4TS R_286 ( .D(n1267), .CK(clk), .SN(1'b1), .RN(n4499), .Q(
sel_mux_2_reg_0_) );
DFFSX2TS R_402 ( .D(n4471), .CK(clk), .SN(n4487), .Q(n4235) );
DFFSX2TS R_117 ( .D(n4563), .CK(clk), .SN(n1631), .Q(n4385) );
DFFSX2TS R_115 ( .D(n4525), .CK(clk), .SN(n1773), .Q(n4387) );
DFFSX2TS R_116 ( .D(n4524), .CK(clk), .SN(n1778), .Q(n4386) );
DFFSX4TS R_354 ( .D(n2402), .CK(clk), .SN(n4072), .Q(n4263) );
DFFSX4TS R_333 ( .D(n2402), .CK(clk), .SN(n1611), .Q(n4276) );
DFFRHQX8TS cordic_FSM_state_reg_reg_0_ ( .D(n1343), .CK(clk), .RN(n4722),
.Q(n2382) );
DFFRHQX8TS cordic_FSM_state_reg_reg_2_ ( .D(n1344), .CK(clk), .RN(n4722),
.Q(n2380) );
DFFRHQX8TS cont_iter_count_reg_1_ ( .D(n1340), .CK(clk), .RN(n2398), .Q(
n2378) );
DFFRHQX2TS reg_Z0_Q_reg_40_ ( .D(n1293), .CK(clk), .RN(n1812), .Q(n2377) );
DFFRHQX2TS reg_Z0_Q_reg_42_ ( .D(n1291), .CK(clk), .RN(n1817), .Q(n2376) );
DFFRHQX2TS reg_Z0_Q_reg_38_ ( .D(n1295), .CK(clk), .RN(n4068), .Q(n2375) );
DFFRHQX4TS reg_Z0_Q_reg_37_ ( .D(n1296), .CK(clk), .RN(n4082), .Q(n2374) );
DFFRHQX8TS reg_ch_mux_1_Q_reg_0_ ( .D(n1268), .CK(clk), .RN(n2403), .Q(n2362) );
DFFRHQX8TS cont_iter_count_reg_0_ ( .D(n1341), .CK(clk), .RN(n1625), .Q(
n2360) );
DFFRHQX8TS cont_iter_count_reg_2_ ( .D(n1339), .CK(clk), .RN(n4072), .Q(
n2357) );
DFFRHQX2TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n720), .CK(clk), .RN(n4494),
.Q(n2354) );
DFFRHQX2TS R_287_IP ( .D(n1267), .CK(clk), .RN(n4080), .Q(n2348) );
DFFSX2TS R_267 ( .D(n4720), .CK(clk), .SN(n4484), .QN(n2341) );
DFFSX2TS R_265 ( .D(n1514), .CK(clk), .SN(n1795), .QN(n2340) );
DFFSX2TS R_270 ( .D(n4719), .CK(clk), .SN(n1783), .QN(n2338) );
DFFSX2TS R_273 ( .D(n4718), .CK(clk), .SN(n4493), .QN(n2336) );
DFFSX2TS R_276 ( .D(n4717), .CK(clk), .SN(n1798), .QN(n2334) );
DFFSX2TS R_274 ( .D(n2955), .CK(clk), .SN(n4075), .QN(n2332) );
DFFSX2TS R_279 ( .D(n4716), .CK(clk), .SN(n4496), .QN(n2330) );
DFFSX2TS R_282 ( .D(n4715), .CK(clk), .SN(n1817), .QN(n2328) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n585), .CK(clk), .RN(n4078),
.Q(n2324) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n586), .CK(clk), .RN(n1810),
.Q(n2317) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n846), .CK(clk), .RN(n4489),
.Q(n2300) );
DFFRHQX8TS reg_region_flag_Q_reg_1_ ( .D(n1334), .CK(clk), .RN(n2387), .Q(
n2298) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n857), .CK(clk), .RN(n2394),
.Q(n2285) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n1819),
.Q(n2284) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n4499),
.Q(n2283) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n4481),
.Q(n2282) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n1820),
.Q(n2281) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n1821),
.Q(n2280) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n588), .CK(clk), .RN(n1818),
.Q(n2276) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n844), .CK(clk), .RN(n1813),
.Q(n2275) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n845), .CK(clk), .RN(n4492),
.Q(n2274) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n4479),
.Q(n2270) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n4503),
.Q(n2269) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n4504),
.Q(n2267) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n837), .CK(clk), .RN(n4498),
.Q(n2265) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n838), .CK(clk), .RN(n4490),
.Q(n2264) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n839), .CK(clk), .RN(n4070),
.Q(n2263) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n840), .CK(clk), .RN(n1814),
.Q(n2262) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n841), .CK(clk), .RN(n1816),
.Q(n2261) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n842), .CK(clk), .RN(n1811),
.Q(n2260) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n2389),
.Q(n2259) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n4071),
.Q(n2258) );
DFFRHQX8TS reg_ch_mux_3_Q_reg_0_ ( .D(n1269), .CK(clk), .RN(n4081), .Q(n2257) );
DFFRHQX2TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n710), .CK(clk), .RN(n1769),
.Q(n2254) );
DFFRHQX2TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n830), .CK(clk), .RN(n4497),
.Q(n2252) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n583), .CK(clk), .RN(n4069),
.Q(n2248) );
DFFRHQX2TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n718), .CK(clk), .RN(n1641),
.Q(n2246) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n628), .CK(clk), .RN(n1801), .Q(
d_ff2_X[34]), .QN(n4565) );
DFFSRHQX4TS reg_val_muxY_2stage_Q_reg_60_ ( .D(n712), .CK(clk), .SN(1'b1),
.RN(n1818), .Q(d_ff2_Y[60]) );
DFFRHQX2TS reg_LUT_Q_reg_48_ ( .D(n2158), .CK(clk), .RN(n1770), .Q(
d_ff3_LUT_out[48]) );
DFFRX4TS reg_shift_y_Q_reg_55_ ( .D(n706), .CK(clk), .RN(n1634), .Q(
d_ff3_sh_y_out[55]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n851), .CK(clk), .RN(n1775), .Q(
d_ff2_Z[38]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n852), .CK(clk), .RN(n1641), .Q(
d_ff2_Z[37]) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n855), .CK(clk), .RN(n1773), .Q(
d_ff2_Z[34]) );
DFFRX2TS reg_Z0_Q_reg_48_ ( .D(n1285), .CK(clk), .RN(n1811), .Q(d_ff1_Z[48])
);
DFFRX2TS reg_Z0_Q_reg_47_ ( .D(n1286), .CK(clk), .RN(n4070), .Q(d_ff1_Z[47])
);
DFFRX1TS reg_Z0_Q_reg_54_ ( .D(n1279), .CK(clk), .RN(n1809), .Q(d_ff1_Z[54])
);
DFFRX2TS reg_Z0_Q_reg_51_ ( .D(n1282), .CK(clk), .RN(n4490), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n834), .CK(clk), .RN(n1809), .Q(
d_ff2_Z[55]), .QN(n2169) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n833), .CK(clk), .RN(n1805), .Q(
d_ff2_Z[56]), .QN(n2167) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n829), .CK(clk), .RN(n1808), .Q(
d_ff2_Z[60]), .QN(n2166) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n832), .CK(clk), .RN(n4082), .Q(
d_ff2_Z[57]), .QN(n2165) );
DFFRX1TS reg_shift_x_Q_reg_29_ ( .D(n637), .CK(clk), .RN(n2398), .QN(n4557)
);
DFFRX2TS reg_Z0_Q_reg_59_ ( .D(n1274), .CK(clk), .RN(n1639), .Q(d_ff1_Z[59])
);
DFFRX2TS reg_Z0_Q_reg_58_ ( .D(n1275), .CK(clk), .RN(n4492), .Q(d_ff1_Z[58])
);
DFFRX2TS reg_Z0_Q_reg_63_ ( .D(n1270), .CK(clk), .RN(n4503), .Q(d_ff1_Z[63])
);
DFFRX2TS reg_Z0_Q_reg_61_ ( .D(n1272), .CK(clk), .RN(n4478), .Q(d_ff1_Z[61])
);
DFFRX2TS reg_Z0_Q_reg_60_ ( .D(n1273), .CK(clk), .RN(n1812), .Q(d_ff1_Z[60])
);
DFFRX4TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n624), .CK(clk), .RN(n1797), .Q(
d_ff2_X[36]), .QN(n3909) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n781), .CK(clk), .RN(n1778), .Q(
d_ff3_sh_y_out[21]), .QN(n3891) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n786), .CK(clk), .RN(n4480), .Q(
d_ff2_Y[19]) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n626), .CK(clk), .RN(n1612),
.Q(n2145) );
DFFRX1TS d_ff5_Q_reg_3_ ( .D(n1067), .CK(clk), .RN(n1784), .Q(
sign_inv_out[3]), .QN(n3840) );
DFFRX1TS d_ff5_Q_reg_4_ ( .D(n1065), .CK(clk), .RN(n2392), .Q(
sign_inv_out[4]), .QN(n3841) );
DFFRX1TS d_ff5_Q_reg_8_ ( .D(n1057), .CK(clk), .RN(n1808), .Q(
sign_inv_out[8]), .QN(n3845) );
DFFRX1TS d_ff5_Q_reg_7_ ( .D(n1059), .CK(clk), .RN(n1809), .Q(
sign_inv_out[7]), .QN(n3844) );
DFFRX1TS d_ff5_Q_reg_5_ ( .D(n1063), .CK(clk), .RN(n4484), .Q(
sign_inv_out[5]), .QN(n3842) );
DFFRX1TS d_ff5_Q_reg_6_ ( .D(n1061), .CK(clk), .RN(n1795), .Q(
sign_inv_out[6]), .QN(n3843) );
DFFRX4TS d_ff5_Q_reg_16_ ( .D(n1041), .CK(clk), .RN(n1802), .QN(n3852) );
DFFRX4TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n776), .CK(clk), .RN(n1771), .Q(
d_ff2_Y[24]) );
DFFRHQX2TS reg_shift_x_Q_reg_55_ ( .D(n578), .CK(clk), .RN(n1815), .Q(n2131)
);
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n584), .CK(clk), .RN(n4493),
.Q(n2123) );
DFFRX4TS R_12 ( .D(n4615), .CK(clk), .RN(n1630), .Q(n4457) );
DFFSX2TS R_14 ( .D(n4613), .CK(clk), .SN(n1786), .Q(n4455) );
DFFSX2TS R_405 ( .D(n1621), .CK(clk), .SN(n1634), .Q(n4233) );
DFFSX2TS R_545 ( .D(n4597), .CK(clk), .SN(n4497), .QN(n2103) );
DFFSX2TS R_544 ( .D(n4598), .CK(clk), .SN(n1612), .QN(n2102) );
DFFRX4TS d_ff5_Q_reg_45_ ( .D(n983), .CK(clk), .RN(n1623), .QN(n3878) );
DFFRX4TS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n835), .CK(clk), .RN(n4496), .Q(
d_ff2_Z[54]), .QN(n2095) );
DFFSRHQX4TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n590), .CK(clk), .SN(1'b1),
.RN(n2389), .Q(d_ff2_X[54]) );
DFFRHQX4TS reg_shift_x_Q_reg_53_ ( .D(n580), .CK(clk), .RN(n1806), .Q(n3769)
);
DFFRHQX2TS reg_shift_x_Q_reg_0_ ( .D(n695), .CK(clk), .RN(n4076), .Q(n2089)
);
DFFRHQX4TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1805),
.Q(n2268) );
DFFSX2TS R_644 ( .D(n2599), .CK(clk), .SN(n4084), .Q(n2087) );
DFFSX2TS R_645 ( .D(n2596), .CK(clk), .SN(n4083), .Q(n2086) );
DFFSX2TS R_646 ( .D(n2598), .CK(clk), .SN(n2406), .Q(n2085) );
DFFSX2TS R_647 ( .D(n3399), .CK(clk), .SN(n2395), .Q(n2084) );
DFFSX2TS R_648 ( .D(n3398), .CK(clk), .SN(n1799), .Q(n2083) );
DFFSX2TS R_649 ( .D(n3397), .CK(clk), .SN(n1796), .Q(n2082) );
DFFSX2TS R_650 ( .D(n2556), .CK(clk), .SN(n1795), .Q(n2081) );
DFFSX2TS R_651 ( .D(n2576), .CK(clk), .SN(n4484), .Q(n2080) );
DFFSX2TS R_652 ( .D(n2577), .CK(clk), .SN(n2392), .Q(n2079) );
DFFSX2TS R_653 ( .D(n2623), .CK(clk), .SN(n4070), .Q(n2078) );
DFFSX2TS R_654 ( .D(n2622), .CK(clk), .SN(n4494), .Q(n2077) );
DFFSX2TS R_113 ( .D(n4467), .CK(clk), .SN(n1631), .Q(n4389) );
DFFSX2TS R_636 ( .D(n4468), .CK(clk), .SN(n1630), .Q(n4091) );
DFFSX2TS R_23 ( .D(n4469), .CK(clk), .SN(n4076), .Q(n4449) );
DFFSX2TS R_129 ( .D(n4471), .CK(clk), .SN(n1775), .Q(n4377) );
DFFSX2TS R_126 ( .D(n4471), .CK(clk), .SN(n1786), .Q(n4379) );
DFFSX2TS R_231 ( .D(n4471), .CK(clk), .SN(n4502), .QN(n2305) );
DFFSX2TS R_672 ( .D(n3254), .CK(clk), .SN(n1617), .Q(n2006) );
DFFSX2TS R_603 ( .D(n2140), .CK(clk), .SN(n1818), .Q(n4116) );
DFFSX2TS R_366 ( .D(n1621), .CK(clk), .SN(n1634), .Q(n4255) );
DFFSX2TS R_345 ( .D(n2402), .CK(clk), .SN(n1633), .Q(n4270) );
DFFSX4TS R_686 ( .D(n4625), .CK(clk), .SN(n1617), .Q(n1939) );
DFFSX2TS R_690 ( .D(n4676), .CK(clk), .SN(n1614), .Q(n1934), .QN(n1933) );
DFFSX2TS R_691 ( .D(n4706), .CK(clk), .SN(n4084), .Q(n1932), .QN(n1835) );
DFFSX2TS R_696 ( .D(n4644), .CK(clk), .SN(n1811), .Q(n1922), .QN(n1921) );
DFFSX2TS R_698 ( .D(n4634), .CK(clk), .SN(n4069), .Q(n1919) );
DFFSX2TS R_699 ( .D(n4623), .CK(clk), .SN(n1786), .Q(n1918), .QN(n1846) );
DFFSX2TS R_702 ( .D(n4636), .CK(clk), .SN(n1616), .Q(n1915) );
DFFSX2TS R_703 ( .D(n4702), .CK(clk), .SN(n4086), .Q(n1914) );
DFFSX2TS R_704 ( .D(n4685), .CK(clk), .SN(n1625), .Q(n1913), .QN(n1912) );
DFFSX2TS R_705 ( .D(n4701), .CK(clk), .SN(n1785), .Q(n1911), .QN(n1910) );
DFFSX2TS R_706 ( .D(n4680), .CK(clk), .SN(n1624), .Q(n1909), .QN(n1908) );
DFFSX2TS R_711 ( .D(n4631), .CK(clk), .SN(n1785), .Q(n1902), .QN(n1825) );
DFFSX2TS R_712 ( .D(n4661), .CK(clk), .SN(n4083), .Q(n1901) );
DFFSX2TS R_713 ( .D(n4629), .CK(clk), .SN(n1817), .Q(n1900) );
DFFSX2TS R_715 ( .D(n4630), .CK(clk), .SN(n1632), .Q(n1898), .QN(n1897) );
DFFSX2TS R_716 ( .D(n4652), .CK(clk), .SN(n1641), .Q(n1896) );
DFFSX2TS R_718 ( .D(n4695), .CK(clk), .SN(n2389), .Q(n1894), .QN(n1893) );
DFFSX2TS R_719 ( .D(n4679), .CK(clk), .SN(n1630), .Q(n1892), .QN(n1832) );
DFFSX2TS R_720 ( .D(n4632), .CK(clk), .SN(n1819), .Q(n1891) );
DFFSX2TS R_721 ( .D(n4646), .CK(clk), .SN(n4490), .Q(n1890) );
DFFSX2TS R_722 ( .D(n4647), .CK(clk), .SN(n2392), .Q(n1889) );
DFFSX2TS R_723 ( .D(n4703), .CK(clk), .SN(n4085), .Q(n1888) );
DFFSX2TS R_724 ( .D(n4663), .CK(clk), .SN(n2406), .Q(n1887) );
DFFSX2TS R_725 ( .D(n4689), .CK(clk), .SN(n1782), .Q(n1886), .QN(n1760) );
DFFSX2TS R_728 ( .D(n4640), .CK(clk), .SN(n4492), .Q(n1883) );
DFFSX2TS R_729 ( .D(n4624), .CK(clk), .SN(n1775), .Q(n1882), .QN(n1881) );
DFFSX2TS R_732 ( .D(n4648), .CK(clk), .SN(n1617), .Q(n1878) );
DFFSX2TS R_735 ( .D(n4688), .CK(clk), .SN(n4079), .Q(n1875) );
DFFSX2TS R_736 ( .D(n4649), .CK(clk), .SN(n4077), .Q(n1874) );
DFFSX2TS R_737 ( .D(n4667), .CK(clk), .SN(n1806), .Q(n1873) );
DFFSX2TS R_740 ( .D(n4687), .CK(clk), .SN(n4505), .Q(n1870), .QN(n1869) );
DFFSX2TS R_742 ( .D(n4671), .CK(clk), .SN(n1614), .Q(n1867) );
DFFSX2TS R_743 ( .D(n4712), .CK(clk), .SN(n1780), .Q(n1866) );
DFFSX2TS R_744 ( .D(n4691), .CK(clk), .SN(n4495), .Q(n1865), .QN(n1864) );
DFFSX2TS R_745 ( .D(n4655), .CK(clk), .SN(n1768), .Q(n1863), .QN(n1843) );
DFFSX2TS R_746 ( .D(n4659), .CK(clk), .SN(n2395), .Q(n1862) );
DFFSX2TS R_751 ( .D(n2016), .CK(clk), .SN(n1814), .QN(n1856) );
DFFSX2TS R_752 ( .D(n2155), .CK(clk), .SN(n4077), .Q(n1855), .QN(n1854) );
DFFSX2TS R_753 ( .D(n4476), .CK(clk), .SN(n1780), .QN(n1853) );
DFFSX2TS R_754 ( .D(n1636), .CK(clk), .SN(n1798), .Q(n1852) );
DFFSX2TS R_755 ( .D(n2133), .CK(clk), .SN(n1779), .Q(n1851), .QN(n1850) );
DFFSX2TS R_756 ( .D(n2088), .CK(clk), .SN(n1793), .Q(n1849), .QN(n1848) );
DFFRHQX8TS reg_ch_mux_2_Q_reg_1_ ( .D(n1266), .CK(clk), .RN(n4480), .Q(n1762) );
DFFSX4TS R_674 ( .D(n4474), .CK(clk), .SN(n1816), .Q(n1998), .QN(n1941) );
DFFSX4TS R_679 ( .D(n1621), .CK(clk), .SN(n4087), .Q(n1981) );
DFFSX4TS R_465 ( .D(n1636), .CK(clk), .SN(n1801), .Q(n4201) );
DFFSX4TS R_748 ( .D(n4713), .CK(clk), .SN(n4500), .Q(n1859) );
DFFSX4TS R_726 ( .D(n4682), .CK(clk), .SN(n4500), .Q(n1885) );
DFFRHQX4TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n719), .CK(clk), .RN(n1639),
.Q(n2368) );
DFFSX4TS R_662 ( .D(n1636), .CK(clk), .SN(n1791), .Q(n2050), .QN(n1836) );
DFFRX1TS d_ff5_Q_reg_40_ ( .D(n993), .CK(clk), .RN(n1797), .Q(
sign_inv_out[40]), .QN(n3873) );
DFFSX4TS R_664 ( .D(n1621), .CK(clk), .SN(n4496), .Q(n2044) );
DFFSX4TS R_669 ( .D(n1621), .CK(clk), .SN(n4487), .Q(n2019), .QN(n1833) );
DFFSX4TS R_2 ( .D(n4467), .CK(clk), .SN(n1641), .Q(n4464), .QN(n2106) );
DFFSX4TS R_688 ( .D(n4678), .CK(clk), .SN(n4080), .Q(n1936) );
DFFSX4TS R_243 ( .D(n4469), .CK(clk), .SN(n4073), .Q(n4316) );
DFFSX4TS R_681 ( .D(n4471), .CK(clk), .SN(n1789), .Q(n1967), .QN(n1830) );
DFFSX4TS R_661 ( .D(n1636), .CK(clk), .SN(n4499), .Q(n2060), .QN(n1581) );
DFFSX4TS R_687 ( .D(n4622), .CK(clk), .SN(n1789), .Q(n1938), .QN(n1937) );
DFFSX4TS R_708 ( .D(n4704), .CK(clk), .SN(n1638), .Q(n1906) );
DFFSX4TS R_663 ( .D(n1636), .CK(clk), .SN(n1810), .Q(n2048), .QN(n1844) );
DFFSX4TS R_739 ( .D(n4627), .CK(clk), .SN(n1813), .Q(n1871) );
DFFSX4TS R_689 ( .D(n4673), .CK(clk), .SN(n1777), .Q(n1935), .QN(n1839) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n817), .CK(clk), .RN(n4077), .Q(
d_ff3_sh_y_out[3]), .QN(n3928) );
DFFSRHQX4TS d_ff5_data_out_Q_reg_63_ ( .D(n946), .CK(clk), .SN(1'b1), .RN(
n4481), .Q(data_output[63]) );
DFFRX1TS reg_Z0_Q_reg_31_ ( .D(n1302), .CK(clk), .RN(n1810), .Q(d_ff1_Z[31])
);
DFFSX2TS R_635 ( .D(n4593), .CK(clk), .SN(n1809), .Q(n4092) );
DFFSX2TS R_381 ( .D(n2402), .CK(clk), .SN(n1805), .Q(n4249) );
DFFRHQX2TS reg_shift_x_Q_reg_56_ ( .D(n577), .CK(clk), .RN(n1779), .Q(n1579)
);
DFFRX4TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n582), .CK(clk), .RN(n1813), .Q(
d_ff2_X[62]), .QN(n3912) );
DFFRHQX2TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n612), .CK(clk), .RN(n1814),
.Q(n1569) );
DFFSX4TS R_747 ( .D(n4642), .CK(clk), .SN(n1641), .Q(n1861) );
DFFSX4TS R_727 ( .D(n4699), .CK(clk), .SN(n4068), .Q(n1884) );
DFFRX4TS d_ff5_Q_reg_63_ ( .D(n947), .CK(clk), .RN(n1781), .Q(
data_output2_63_), .QN(n1552) );
DFFSX4TS R_750 ( .D(n4709), .CK(clk), .SN(n1794), .Q(n1857) );
DFFSX4TS R_730 ( .D(n4639), .CK(clk), .SN(n1772), .Q(n1880) );
DFFRX4TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n668), .CK(clk), .RN(n4069), .Q(
d_ff2_X[14]), .QN(n3914) );
DFFRX4TS reg_shift_x_Q_reg_52_ ( .D(n581), .CK(clk), .RN(n1780), .Q(n2473),
.QN(n4594) );
DFFRHQX2TS reg_Z0_Q_reg_46_ ( .D(n1287), .CK(clk), .RN(n1812), .Q(n1517) );
DFFRHQX8TS cont_iter_count_reg_3_ ( .D(n1338), .CK(clk), .RN(n1638), .Q(
n2370) );
DFFRX4TS d_ff5_Q_reg_0_ ( .D(n1073), .CK(clk), .RN(n2406), .Q(
sign_inv_out[0]), .QN(n3837) );
DFFSX4TS R_738 ( .D(n4710), .CK(clk), .SN(n1777), .Q(n1872) );
DFFSX4TS R_710 ( .D(n4621), .CK(clk), .SN(n1823), .Q(n1904), .QN(n1903) );
DFFSX4TS R_731 ( .D(n4635), .CK(clk), .SN(n4504), .Q(n1879) );
DFFSX4TS R_684 ( .D(n1621), .CK(clk), .SN(n4076), .Q(n1953), .QN(n1566) );
DFFSX4TS R_685 ( .D(n4707), .CK(clk), .SN(n1633), .Q(n1946), .QN(n1562) );
DFFRHQX4TS reg_region_flag_Q_reg_0_ ( .D(n1335), .CK(clk), .RN(n1823), .Q(
n2323) );
DFFSX4TS R_717 ( .D(n4638), .CK(clk), .SN(n1783), .Q(n1895) );
DFFSX4TS R_701 ( .D(n4653), .CK(clk), .SN(n1769), .Q(n1916) );
DFFSX4TS R_697 ( .D(n4650), .CK(clk), .SN(n1800), .Q(n1920) );
DFFSX4TS R_694 ( .D(n1636), .CK(clk), .SN(n1791), .Q(n1924) );
DFFSX4TS R_680 ( .D(n4472), .CK(clk), .SN(n1781), .Q(n1975), .QN(n1925) );
DFFSX4TS R_741 ( .D(n4628), .CK(clk), .SN(n1821), .Q(n1868) );
DFFSX4TS R_714 ( .D(n4693), .CK(clk), .SN(n1815), .Q(n1899), .QN(n1575) );
DFFSX4TS R_707 ( .D(n4637), .CK(clk), .SN(n1791), .Q(n1907) );
DFFRX1TS R_208 ( .D(n941), .CK(clk), .RN(n4483), .Q(n4334) );
DFFSX4TS R_749 ( .D(n4657), .CK(clk), .SN(n4071), .Q(n1858) );
DFFRHQX4TS reg_operation_Q_reg_0_ ( .D(n1336), .CK(clk), .RN(n1822), .Q(
n2319) );
DFFSX2TS R_144 ( .D(n2140), .CK(clk), .SN(n4087), .Q(n4371) );
DFFSX4TS R_671 ( .D(n4474), .CK(clk), .SN(n2398), .Q(n2012), .QN(n1563) );
DFFSX4TS R_693 ( .D(n4674), .CK(clk), .SN(n1623), .Q(n1930), .QN(n1929) );
DFFSX4TS R_683 ( .D(n1621), .CK(clk), .SN(n4486), .Q(n1960), .QN(n1944) );
DFFSX1TS R_374 ( .D(n4002), .CK(clk), .SN(n1806), .Q(n4251) );
DFFRX2TS reg_Z0_Q_reg_13_ ( .D(n1320), .CK(clk), .RN(n4071), .Q(d_ff1_Z[13])
);
DFFSX2TS R_639 ( .D(n2140), .CK(clk), .SN(n4498), .Q(n4088) );
DFFSX2TS R_101 ( .D(n4469), .CK(clk), .SN(n1803), .Q(n4397) );
DFFRX2TS R_169 ( .D(n915), .CK(clk), .RN(n1793), .Q(n4359) );
DFFSX4TS R_677 ( .D(n1636), .CK(clk), .SN(n1790), .Q(n1987) );
DFFSX4TS R_733 ( .D(n4665), .CK(clk), .SN(n4072), .Q(n1877) );
DFFRX1TS reg_Z0_Q_reg_44_ ( .D(n1289), .CK(clk), .RN(n1798), .Q(d_ff1_Z[44])
);
DFFRX1TS reg_Z0_Q_reg_18_ ( .D(n1315), .CK(clk), .RN(n1796), .Q(d_ff1_Z[18])
);
DFFRX2TS reg_Z0_Q_reg_17_ ( .D(n1316), .CK(clk), .RN(n1799), .Q(d_ff1_Z[17])
);
DFFRX2TS reg_Z0_Q_reg_53_ ( .D(n1280), .CK(clk), .RN(n4079), .Q(d_ff1_Z[53])
);
DFFRX2TS reg_Z0_Q_reg_55_ ( .D(n1278), .CK(clk), .RN(n4478), .Q(d_ff1_Z[55])
);
DFFSX2TS R_364 ( .D(n4705), .CK(clk), .SN(n1613), .Q(n4257) );
DFFRX2TS reg_Z0_Q_reg_36_ ( .D(n1297), .CK(clk), .RN(n1639), .Q(d_ff1_Z[36])
);
DFFRX2TS reg_Z0_Q_reg_35_ ( .D(n1298), .CK(clk), .RN(n1769), .Q(d_ff1_Z[35])
);
DFFRX1TS reg_Z0_Q_reg_24_ ( .D(n1309), .CK(clk), .RN(n2392), .Q(d_ff1_Z[24])
);
DFFSX2TS R_602 ( .D(n1988), .CK(clk), .SN(n1808), .Q(n4117) );
DFFSX2TS R_365 ( .D(n1931), .CK(clk), .SN(n4082), .Q(n4256) );
DFFRX2TS reg_Z0_Q_reg_34_ ( .D(n1299), .CK(clk), .RN(n1641), .Q(d_ff1_Z[34])
);
DFFRX1TS reg_Z0_Q_reg_22_ ( .D(n1311), .CK(clk), .RN(n2393), .Q(d_ff1_Z[22])
);
DFFRX1TS reg_Z0_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(n4498), .Q(d_ff1_Z[11])
);
DFFRX1TS reg_Z0_Q_reg_26_ ( .D(n1307), .CK(clk), .RN(n1795), .Q(d_ff1_Z[26])
);
DFFSX2TS R_290 ( .D(n2140), .CK(clk), .SN(n2398), .Q(n4298) );
DFFRX1TS reg_Z0_Q_reg_20_ ( .D(n1313), .CK(clk), .RN(n1790), .Q(d_ff1_Z[20])
);
DFFRX1TS reg_Z0_Q_reg_19_ ( .D(n1314), .CK(clk), .RN(n1791), .Q(d_ff1_Z[19])
);
DFFRX1TS reg_Z0_Q_reg_16_ ( .D(n1317), .CK(clk), .RN(n1822), .Q(d_ff1_Z[16])
);
DFFRX1TS reg_Z0_Q_reg_21_ ( .D(n1312), .CK(clk), .RN(n4482), .Q(d_ff1_Z[21])
);
DFFRX1TS reg_Z0_Q_reg_15_ ( .D(n1318), .CK(clk), .RN(n1612), .Q(d_ff1_Z[15])
);
DFFRX1TS reg_Z0_Q_reg_25_ ( .D(n1308), .CK(clk), .RN(n4484), .Q(d_ff1_Z[25])
);
DFFSX2TS R_408 ( .D(n2618), .CK(clk), .SN(n4501), .Q(n4231) );
DFFRX2TS reg_Z0_Q_reg_33_ ( .D(n1300), .CK(clk), .RN(n1768), .Q(d_ff1_Z[33])
);
DFFSX2TS R_11 ( .D(n4467), .CK(clk), .SN(n1805), .Q(n4458) );
DFFSX1TS R_570 ( .D(n4469), .CK(clk), .SN(n4074), .Q(n4142) );
DFFSX1TS R_573 ( .D(n4469), .CK(clk), .SN(n4085), .Q(n4139) );
DFFSX2TS R_22 ( .D(n1553), .CK(clk), .SN(n1807), .Q(n4450) );
DFFSX2TS R_564 ( .D(n4469), .CK(clk), .SN(n4483), .Q(n4146) );
DFFSX2TS R_53 ( .D(n4468), .CK(clk), .SN(n1803), .Q(n4428) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n920), .CK(clk), .RN(n1631), .Q(
d_ff3_LUT_out[25]), .QN(n1605) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n853), .CK(clk), .RN(n2403), .Q(
d_ff2_Z[36]) );
DFFRX1TS reg_shift_y_Q_reg_19_ ( .D(n785), .CK(clk), .RN(n4501), .Q(
d_ff3_sh_y_out[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n856), .CK(clk), .RN(n1776), .Q(
d_ff2_Z[33]) );
DFFRX1TS reg_LUT_Q_reg_55_ ( .D(n891), .CK(clk), .RN(n1627), .Q(
d_ff3_LUT_out[55]) );
DFFRX1TS reg_LUT_Q_reg_32_ ( .D(n913), .CK(clk), .RN(n1782), .Q(
d_ff3_LUT_out[32]) );
DFFRX1TS reg_shift_y_Q_reg_28_ ( .D(n767), .CK(clk), .RN(n1628), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n892), .CK(clk), .RN(n2395), .Q(
d_ff3_LUT_out[54]), .QN(n1561) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n937), .CK(clk), .RN(n2400), .Q(
d_ff3_LUT_out[8]), .QN(n2366) );
DFFRX1TS reg_LUT_Q_reg_38_ ( .D(n907), .CK(clk), .RN(n1626), .Q(
d_ff3_LUT_out[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n746), .CK(clk), .RN(n4492), .Q(
d_ff2_Y[39]), .QN(n3800) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n854), .CK(clk), .RN(n1774), .Q(
d_ff2_Z[35]) );
DFFRX1TS reg_shift_y_Q_reg_24_ ( .D(n2188), .CK(clk), .RN(n1772), .Q(
d_ff3_sh_y_out[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n632), .CK(clk), .RN(n1787), .Q(
d_ff2_X[32]), .QN(n3908) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n618), .CK(clk), .RN(n1617), .Q(
d_ff2_X[39]), .QN(n2630) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n604), .CK(clk), .RN(n1786), .Q(
d_ff2_X[46]), .QN(n3776) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n1633), .Q(
d_ff2_Z[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n606), .CK(clk), .RN(n1788), .Q(
d_ff2_X[45]), .QN(n3775) );
DFFRX2TS reg_shift_y_Q_reg_6_ ( .D(n811), .CK(clk), .RN(n2487), .QN(n3958)
);
DFFRX2TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n768), .CK(clk), .RN(n4483), .Q(
d_ff2_Y[28]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n598), .CK(clk), .RN(n1783), .Q(
d_ff2_X[49]), .QN(n4590) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n610), .CK(clk), .RN(n1792), .Q(
d_ff2_X[43]), .QN(n3774) );
DFFRX1TS reg_LUT_Q_reg_34_ ( .D(n911), .CK(clk), .RN(n4491), .QN(n2163) );
DFFSX4TS R_734 ( .D(n4684), .CK(clk), .SN(n1632), .Q(n1876) );
DFFRX1TS reg_Z0_Q_reg_12_ ( .D(n1321), .CK(clk), .RN(n4076), .Q(d_ff1_Z[12])
);
DFFRX1TS reg_Z0_Q_reg_45_ ( .D(n1288), .CK(clk), .RN(n1800), .Q(d_ff1_Z[45])
);
DFFRX1TS reg_Z0_Q_reg_43_ ( .D(n1290), .CK(clk), .RN(n1808), .Q(d_ff1_Z[43])
);
DFFRX1TS reg_Z0_Q_reg_52_ ( .D(n1281), .CK(clk), .RN(n1616), .Q(d_ff1_Z[52])
);
DFFRX1TS reg_Z0_Q_reg_9_ ( .D(n1324), .CK(clk), .RN(n1823), .Q(d_ff1_Z[9])
);
DFFRX1TS reg_Z0_Q_reg_23_ ( .D(n1310), .CK(clk), .RN(n1794), .Q(d_ff1_Z[23])
);
DFFRX1TS reg_Z0_Q_reg_50_ ( .D(n1283), .CK(clk), .RN(n4074), .Q(d_ff1_Z[50])
);
DFFRX1TS reg_Z0_Q_reg_56_ ( .D(n1277), .CK(clk), .RN(n4486), .Q(d_ff1_Z[56])
);
DFFRX1TS reg_Z0_Q_reg_1_ ( .D(n1332), .CK(clk), .RN(n4084), .Q(d_ff1_Z[1])
);
DFFRX1TS reg_Z0_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n2395), .Q(d_ff1_Z[3])
);
DFFRX1TS reg_Z0_Q_reg_0_ ( .D(n1333), .CK(clk), .RN(n2406), .Q(d_ff1_Z[0])
);
DFFRX1TS reg_Z0_Q_reg_2_ ( .D(n1331), .CK(clk), .RN(n4083), .Q(d_ff1_Z[2]),
.QN(n2136) );
DFFRX1TS reg_Z0_Q_reg_10_ ( .D(n1323), .CK(clk), .RN(n4068), .Q(d_ff1_Z[10])
);
DFFRX2TS reg_Z0_Q_reg_14_ ( .D(n1319), .CK(clk), .RN(n4497), .Q(d_ff1_Z[14])
);
DFFRX1TS reg_shift_x_Q_reg_19_ ( .D(n657), .CK(clk), .RN(n1781), .QN(n4537)
);
DFFRX1TS reg_shift_x_Q_reg_6_ ( .D(n683), .CK(clk), .RN(n4488), .QN(n4519)
);
DFFRX1TS reg_shift_x_Q_reg_35_ ( .D(n625), .CK(clk), .RN(n1618), .QN(n4567)
);
DFFRX1TS reg_shift_x_Q_reg_43_ ( .D(n609), .CK(clk), .RN(n1789), .QN(n4579)
);
DFFRX1TS reg_shift_x_Q_reg_42_ ( .D(n611), .CK(clk), .RN(n4073), .QN(n4577)
);
DFFRX1TS reg_shift_x_Q_reg_32_ ( .D(n631), .CK(clk), .RN(n4085), .QN(n4562)
);
DFFRX2TS reg_shift_x_Q_reg_54_ ( .D(n579), .CK(clk), .RN(n2396), .Q(n2411),
.QN(n1604) );
DFFRX2TS reg_shift_x_Q_reg_50_ ( .D(n595), .CK(clk), .RN(n1770), .Q(n2091),
.QN(n4592) );
DFFRX1TS reg_shift_x_Q_reg_22_ ( .D(n651), .CK(clk), .RN(n4500), .QN(n4543)
);
DFFRX1TS reg_shift_x_Q_reg_20_ ( .D(n655), .CK(clk), .RN(n4495), .QN(n4539)
);
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(clk), .RN(n1780), .QN(n4545)
);
DFFRX1TS reg_shift_x_Q_reg_49_ ( .D(n597), .CK(clk), .RN(n1632), .QN(n4591)
);
DFFSX4TS R_668 ( .D(n1621), .CK(clk), .SN(n4497), .Q(n2027) );
DFFSX4TS R_700 ( .D(n4669), .CK(clk), .SN(n1803), .Q(n1917) );
OAI2BB1X2TS U1472 ( .A0N(d_ff3_LUT_out[28]), .A1N(n2624), .B0(n3718), .Y(
n917) );
MXI2X2TS U1473 ( .A(n3714), .B(n3937), .S0(n3747), .Y(n890) );
OAI2BB1X2TS U1474 ( .A0N(d_ff2_Y[32]), .A1N(n1508), .B0(n3292), .Y(n760) );
NOR2X2TS U1475 ( .A(n2594), .B(n910), .Y(n2622) );
NAND2X2TS U1476 ( .A(n2176), .B(n2218), .Y(n4612) );
NOR2X2TS U1477 ( .A(n2230), .B(n3334), .Y(n4509) );
NAND3X4TS U1478 ( .A(n2980), .B(n2981), .C(n4563), .Y(n912) );
AOI22X2TS U1479 ( .A0(n1584), .A1(n1657), .B0(n2546), .B1(n2071), .Y(n589)
);
NAND3X4TS U1480 ( .A(n2934), .B(n2927), .C(n1601), .Y(n926) );
NAND2X2TS U1481 ( .A(n2594), .B(d_ff2_Y[56]), .Y(n4596) );
INVX3TS U1482 ( .A(n1564), .Y(n1949) );
NAND3X6TS U1483 ( .A(n1495), .B(n2927), .C(n3216), .Y(n920) );
AOI22X2TS U1484 ( .A0(n2307), .A1(n2544), .B0(n3743), .B1(n3900), .Y(n696)
);
MX2X2TS U1485 ( .A(n1560), .B(n1561), .S0(n3551), .Y(n3646) );
NAND2X1TS U1486 ( .A(n3549), .B(d_ff2_Y[58]), .Y(n3550) );
NAND2X2TS U1487 ( .A(n1704), .B(n2563), .Y(n2832) );
NAND2X2TS U1488 ( .A(n3751), .B(n2283), .Y(n2734) );
INVX12TS U1489 ( .A(n2570), .Y(n1584) );
NAND2X2TS U1490 ( .A(n3252), .B(n3491), .Y(n3492) );
INVX2TS U1491 ( .A(n1569), .Y(n1570) );
NAND2BX2TS U1492 ( .AN(n4565), .B(n2230), .Y(n2227) );
NAND2X2TS U1493 ( .A(n3717), .B(n2121), .Y(n3188) );
INVX1TS U1494 ( .A(n3732), .Y(n1538) );
NAND2X2TS U1495 ( .A(n1592), .B(n3562), .Y(n2833) );
NAND2X2TS U1496 ( .A(n2202), .B(n1738), .Y(n3005) );
BUFX16TS U1497 ( .A(n3684), .Y(n1494) );
NAND3X1TS U1498 ( .A(n3001), .B(d_ff1_Z[50]), .C(n2885), .Y(n2711) );
NAND2X6TS U1499 ( .A(n2764), .B(n1537), .Y(n4563) );
CLKMX2X2TS U1500 ( .A(n1885), .B(n4278), .S0(n1980), .Y(n1979) );
NAND3X4TS U1501 ( .A(n2301), .B(n3711), .C(n3546), .Y(n4601) );
CLKMX2X2TS U1502 ( .A(n1872), .B(n4337), .S0(n2018), .Y(n2117) );
INVX12TS U1503 ( .A(n3296), .Y(n1507) );
NAND2X6TS U1504 ( .A(n1671), .B(n3024), .Y(n1488) );
NAND2X2TS U1505 ( .A(n1508), .B(d_ff2_Y[29]), .Y(n1705) );
OR2X4TS U1506 ( .A(n1640), .B(n575), .Y(n2571) );
NAND2XLTS U1507 ( .A(n3735), .B(n1579), .Y(n2610) );
CLKMX2X2TS U1508 ( .A(n1576), .B(n4378), .S0(n4377), .Y(n2352) );
NAND2X2TS U1509 ( .A(n3210), .B(n1669), .Y(n3211) );
AND2X4TS U1510 ( .A(n3489), .B(n3541), .Y(n3723) );
NAND2X4TS U1511 ( .A(n3212), .B(n2619), .Y(n2788) );
CLKMX2X2TS U1512 ( .A(n3910), .B(n3265), .S0(n3714), .Y(n2942) );
NOR2X4TS U1513 ( .A(n1656), .B(n1655), .Y(n1654) );
OR2X1TS U1514 ( .A(n3683), .B(n3913), .Y(n2181) );
NOR2BX2TS U1515 ( .AN(n3498), .B(n1547), .Y(n1493) );
AO21X2TS U1516 ( .A0(n2317), .A1(n3552), .B0(n3735), .Y(n2177) );
NAND2X4TS U1517 ( .A(n1713), .B(n2582), .Y(n2814) );
NAND2X2TS U1518 ( .A(n3725), .B(n2431), .Y(n2228) );
NOR2X6TS U1519 ( .A(n3276), .B(n3649), .Y(n3742) );
NAND2X2TS U1520 ( .A(n3321), .B(n2199), .Y(n3322) );
AND2X4TS U1521 ( .A(n3644), .B(n3247), .Y(n1722) );
NAND2X4TS U1522 ( .A(n1749), .B(n2954), .Y(n1748) );
MXI2X2TS U1523 ( .A(n1908), .B(n1957), .S0(n1960), .Y(n2313) );
NAND3X1TS U1524 ( .A(n2849), .B(d_ff1_Z[27]), .C(n2363), .Y(n2826) );
BUFX6TS U1525 ( .A(n3727), .Y(n1709) );
NAND2X2TS U1526 ( .A(n2739), .B(n3614), .Y(n2652) );
NAND3X1TS U1527 ( .A(n2845), .B(d_ff1_Z[51]), .C(n2885), .Y(n2705) );
OR2X4TS U1528 ( .A(n2410), .B(n2163), .Y(n2179) );
MXI2X2TS U1529 ( .A(n1903), .B(n1978), .S0(n1980), .Y(n2135) );
NAND2X2TS U1530 ( .A(n1644), .B(d_ff2_X[62]), .Y(n3331) );
NAND2X4TS U1531 ( .A(n2544), .B(n3641), .Y(n3029) );
NAND2BX2TS U1532 ( .AN(n2524), .B(n3586), .Y(n2779) );
NAND2X2TS U1533 ( .A(n2539), .B(n3007), .Y(n3008) );
NAND2X2TS U1534 ( .A(n2383), .B(n3571), .Y(n2841) );
NAND2X2TS U1535 ( .A(n2539), .B(n3579), .Y(n2871) );
BUFX6TS U1536 ( .A(n3549), .Y(n2594) );
INVX3TS U1537 ( .A(n1711), .Y(n2787) );
NAND2X2TS U1538 ( .A(n3606), .B(n2201), .Y(n2100) );
NAND2X2TS U1539 ( .A(n2878), .B(d_ff2_Z[58]), .Y(n2870) );
NAND2X2TS U1540 ( .A(n1713), .B(n2565), .Y(n2840) );
NAND2X2TS U1541 ( .A(n1704), .B(n2586), .Y(n2817) );
NAND3X1TS U1542 ( .A(n2845), .B(d_ff1_Z[52]), .C(n2885), .Y(n2708) );
INVX4TS U1543 ( .A(n2068), .Y(n2144) );
NAND2X4TS U1544 ( .A(n2932), .B(n1496), .Y(n1495) );
NAND2X2TS U1545 ( .A(n3747), .B(d_ff3_sh_y_out[55]), .Y(n1685) );
NAND2X2TS U1546 ( .A(n3659), .B(n2566), .Y(n2644) );
NAND2X2TS U1547 ( .A(n2107), .B(n3240), .Y(n2771) );
NAND2X2TS U1548 ( .A(n3047), .B(n3557), .Y(n2742) );
OR2X4TS U1549 ( .A(n2410), .B(n2164), .Y(n1601) );
NAND2X2TS U1550 ( .A(n2839), .B(n2516), .Y(n2727) );
NAND2X2TS U1551 ( .A(n3047), .B(n3594), .Y(n2966) );
NAND2X2TS U1552 ( .A(n2202), .B(n3286), .Y(n3019) );
NAND2X2TS U1553 ( .A(n2107), .B(n3222), .Y(n2770) );
NAND2X4TS U1554 ( .A(n2619), .B(n1668), .Y(n1489) );
NAND2X2TS U1555 ( .A(n2202), .B(n3625), .Y(n3034) );
OR2X4TS U1556 ( .A(n2410), .B(n2160), .Y(n1600) );
NAND2X2TS U1557 ( .A(n1586), .B(n2269), .Y(n2850) );
INVX2TS U1558 ( .A(n3678), .Y(n2067) );
NOR2X2TS U1559 ( .A(n3490), .B(n3912), .Y(n3493) );
NAND2X2TS U1560 ( .A(n1580), .B(d_ff2_Y[25]), .Y(n1731) );
NAND2X2TS U1561 ( .A(n3751), .B(n2267), .Y(n2848) );
NOR2X2TS U1562 ( .A(n2629), .B(n2626), .Y(n2625) );
NAND2X2TS U1563 ( .A(n2878), .B(d_ff2_Z[46]), .Y(n2662) );
NAND2X2TS U1564 ( .A(n2878), .B(n2252), .Y(n2679) );
NAND2X2TS U1565 ( .A(n2878), .B(n2261), .Y(n2673) );
NAND2X2TS U1566 ( .A(n2878), .B(n2265), .Y(n2709) );
NAND2X2TS U1567 ( .A(n2878), .B(n2260), .Y(n2669) );
NAND2X2TS U1568 ( .A(n2878), .B(d_ff2_Z[53]), .Y(n2778) );
OAI21X1TS U1569 ( .A0(n3055), .A1(n3054), .B0(n1504), .Y(n3056) );
NAND2X2TS U1570 ( .A(n2495), .B(d_ff2_Z[63]), .Y(n2867) );
NAND2X2TS U1571 ( .A(n1585), .B(d_ff2_Z[12]), .Y(n2824) );
NAND3X2TS U1572 ( .A(n2535), .B(d_ff1_Z[32]), .C(n2835), .Y(n2736) );
NAND2X2TS U1573 ( .A(n2878), .B(d_ff2_Z[61]), .Y(n2880) );
NAND2X2TS U1574 ( .A(n3751), .B(n2280), .Y(n2831) );
NAND2X2TS U1575 ( .A(n3751), .B(n2258), .Y(n2818) );
NAND2X2TS U1576 ( .A(n2624), .B(d_ff3_LUT_out[32]), .Y(n2220) );
NAND2X4TS U1577 ( .A(n1742), .B(n2954), .Y(n1741) );
NAND2X4TS U1578 ( .A(n2199), .B(n3640), .Y(n3271) );
NAND2X2TS U1579 ( .A(n2843), .B(d_ff2_Z[33]), .Y(n2741) );
MXI2X2TS U1580 ( .A(n4248), .B(n4247), .S0(n2026), .Y(n3619) );
NAND2X2TS U1581 ( .A(n2839), .B(n2513), .Y(n2715) );
XNOR2X2TS U1582 ( .A(n2128), .B(n2237), .Y(n2786) );
NAND2X4TS U1583 ( .A(n2543), .B(n2029), .Y(n2547) );
NAND2X1TS U1584 ( .A(n3751), .B(n2270), .Y(n2856) );
NAND2X4TS U1585 ( .A(n3293), .B(n2199), .Y(n3294) );
NAND2X4TS U1586 ( .A(n2495), .B(d_ff2_Z[62]), .Y(n2784) );
NAND2X4TS U1587 ( .A(n3033), .B(d_ff2_Y[14]), .Y(n1487) );
BUFX8TS U1588 ( .A(n3530), .Y(n3384) );
NAND2X1TS U1589 ( .A(n1645), .B(d_ff2_Y[63]), .Y(n3482) );
NAND2X1TS U1590 ( .A(n3500), .B(n3400), .Y(n3402) );
NAND2X1TS U1591 ( .A(n3174), .B(d_ff2_Z[19]), .Y(n3086) );
NAND2X1TS U1592 ( .A(n3174), .B(d_ff2_Z[20]), .Y(n3083) );
NAND2X1TS U1593 ( .A(n3159), .B(d_ff2_Z[21]), .Y(n3080) );
NAND2X1TS U1594 ( .A(n3159), .B(d_ff2_Z[14]), .Y(n3101) );
AOI22X1TS U1595 ( .A0(d_ff3_LUT_out[23]), .A1(n3528), .B0(n3175), .B1(
d_ff3_sh_y_out[23]), .Y(n3525) );
BUFX8TS U1596 ( .A(n3518), .Y(n3379) );
NAND2X1TS U1597 ( .A(n3174), .B(d_ff2_Z[15]), .Y(n3098) );
AOI22X1TS U1598 ( .A0(d_ff2_Z[55]), .A1(n3496), .B0(n3339), .B1(n1714), .Y(
n3391) );
NAND2X1TS U1599 ( .A(n3516), .B(d_ff3_LUT_out[55]), .Y(n3387) );
NAND2X2TS U1600 ( .A(n3381), .B(n3409), .Y(n3410) );
CLKINVX12TS U1601 ( .A(n2524), .Y(n2385) );
INVX3TS U1602 ( .A(n2235), .Y(n2139) );
NAND2X6TS U1603 ( .A(n2608), .B(n2930), .Y(n1692) );
CLKAND2X2TS U1604 ( .A(d_ff1_Z[53]), .B(n2885), .Y(n2512) );
INVX12TS U1605 ( .A(n2570), .Y(n1595) );
OR3X2TS U1606 ( .A(n1555), .B(n3714), .C(n3205), .Y(n1506) );
AND2X2TS U1607 ( .A(n2374), .B(n2835), .Y(n2513) );
BUFX12TS U1608 ( .A(n2912), .Y(n3700) );
NOR2X2TS U1609 ( .A(n3050), .B(beg_fsm_cordic), .Y(n3051) );
INVX2TS U1610 ( .A(n1954), .Y(n3299) );
CLKMX2X2TS U1611 ( .A(n1908), .B(n1957), .S0(n1960), .Y(n3297) );
BUFX4TS U1612 ( .A(n2111), .Y(n3725) );
CLKBUFX2TS U1613 ( .A(sel_mux_2_reg_0_), .Y(n2939) );
MX2X2TS U1614 ( .A(n2105), .B(n1903), .S0(n2106), .Y(n3624) );
INVX8TS U1615 ( .A(n2592), .Y(n1768) );
BUFX6TS U1616 ( .A(n3722), .Y(n1669) );
INVX6TS U1617 ( .A(n4578), .Y(n1648) );
OR2X4TS U1618 ( .A(n3549), .B(n3547), .Y(n2156) );
NAND3X1TS U1619 ( .A(n3205), .B(n3732), .C(n1667), .Y(n1737) );
BUFX16TS U1620 ( .A(n2714), .Y(n3659) );
INVX12TS U1621 ( .A(n3737), .Y(n3720) );
BUFX16TS U1622 ( .A(n2225), .Y(n2230) );
NAND2X6TS U1623 ( .A(n2608), .B(n2930), .Y(n1531) );
INVX12TS U1624 ( .A(n2235), .Y(n3744) );
AND2X2TS U1625 ( .A(d_ff1_Z[39]), .B(n2671), .Y(n2566) );
AND2X2TS U1626 ( .A(d_ff1_Z[17]), .B(n2970), .Y(n2580) );
INVX2TS U1627 ( .A(n1575), .Y(n1576) );
BUFX16TS U1628 ( .A(n2974), .Y(n2511) );
CLKINVX6TS U1629 ( .A(n3647), .Y(n2561) );
CLKINVX6TS U1630 ( .A(n2524), .Y(n2107) );
CLKINVX6TS U1631 ( .A(n4002), .Y(n2865) );
INVX6TS U1632 ( .A(n2173), .Y(n2068) );
NAND2X2TS U1633 ( .A(d_ff2_Y[60]), .B(n3485), .Y(n3486) );
NAND2X1TS U1634 ( .A(n3714), .B(n2153), .Y(n3244) );
MX2X4TS U1635 ( .A(n1943), .B(n1562), .S0(n1944), .Y(n3672) );
NAND2BX2TS U1636 ( .AN(n1678), .B(n3558), .Y(n2503) );
CLKMX2X4TS U1637 ( .A(n1940), .B(n1942), .S0(n1941), .Y(n3579) );
MXI2X2TS U1638 ( .A(n1862), .B(n4420), .S0(n2049), .Y(n3573) );
INVX2TS U1639 ( .A(n3563), .Y(n4692) );
INVX2TS U1640 ( .A(n3236), .Y(n3237) );
INVX4TS U1641 ( .A(n1753), .Y(n1742) );
INVX2TS U1642 ( .A(n2055), .Y(n3607) );
BUFX16TS U1643 ( .A(n3689), .Y(n1588) );
INVX12TS U1644 ( .A(n2854), .Y(n1585) );
INVX2TS U1645 ( .A(n1845), .Y(n3604) );
INVX6TS U1646 ( .A(n2110), .Y(n3728) );
CLKINVX6TS U1647 ( .A(n2226), .Y(n1680) );
CLKINVX1TS U1648 ( .A(n1573), .Y(n2277) );
INVX2TS U1649 ( .A(n2253), .Y(n1652) );
INVX12TS U1650 ( .A(n3296), .Y(n1508) );
INVX2TS U1651 ( .A(n2052), .Y(n3574) );
INVX2TS U1652 ( .A(n3998), .Y(n2998) );
BUFX16TS U1653 ( .A(n2845), .Y(n1704) );
CLKINVX6TS U1654 ( .A(n1707), .Y(n2531) );
INVX2TS U1655 ( .A(n1668), .Y(n3256) );
INVX4TS U1656 ( .A(n2303), .Y(n3290) );
CLKXOR2X2TS U1657 ( .A(d_ff2_X[53]), .B(n3227), .Y(n2128) );
CLKAND2X2TS U1658 ( .A(d_ff1_Z[55]), .B(n2885), .Y(n2542) );
AND2X2TS U1659 ( .A(d_ff1_Z[35]), .B(n2835), .Y(n2516) );
BUFX16TS U1660 ( .A(n2199), .Y(n1700) );
INVX4TS U1661 ( .A(n2297), .Y(n2073) );
NAND2X6TS U1662 ( .A(n3722), .B(n3543), .Y(n2984) );
NAND2X4TS U1663 ( .A(n2502), .B(n1713), .Y(n2501) );
INVX3TS U1664 ( .A(n2193), .Y(n3293) );
AND2X2TS U1665 ( .A(n2975), .B(d_ff1_Z[8]), .Y(n2184) );
BUFX8TS U1666 ( .A(n2801), .Y(n2535) );
CLKAND2X2TS U1667 ( .A(d_ff1_Z[33]), .B(n2835), .Y(n2518) );
CLKAND2X2TS U1668 ( .A(d_ff1_Z[36]), .B(n2835), .Y(n2514) );
CLKINVX6TS U1669 ( .A(n1571), .Y(n1522) );
INVX3TS U1670 ( .A(n2097), .Y(n2063) );
CLKAND2X2TS U1671 ( .A(n2975), .B(d_ff1_Z[7]), .Y(n2182) );
CLKAND2X2TS U1672 ( .A(n2975), .B(d_ff1_Z[6]), .Y(n2186) );
CLKAND2X2TS U1673 ( .A(n2975), .B(d_ff1_Z[4]), .Y(n2185) );
AND2X2TS U1674 ( .A(d_ff1_Z[28]), .B(n2363), .Y(n2498) );
INVX8TS U1675 ( .A(n2159), .Y(n1650) );
CLKAND2X2TS U1676 ( .A(d_ff1_Z[34]), .B(n2835), .Y(n2517) );
MXI2X2TS U1677 ( .A(n4346), .B(n4345), .S0(n1953), .Y(n3281) );
INVX2TS U1678 ( .A(n3695), .Y(n4555) );
NAND2X6TS U1679 ( .A(n3716), .B(n2361), .Y(n3189) );
CLKAND2X2TS U1680 ( .A(n3197), .B(n3215), .Y(n1520) );
NAND2X6TS U1681 ( .A(n1519), .B(n2774), .Y(n1540) );
NOR2BX2TS U1682 ( .AN(d_ff1_Z[16]), .B(n2564), .Y(n2582) );
XOR2X1TS U1683 ( .A(n3227), .B(n2368), .Y(n2772) );
XOR2X2TS U1684 ( .A(n2093), .B(n3324), .Y(n3325) );
NOR2BX2TS U1685 ( .AN(d_ff1_Z[25]), .B(n2564), .Y(n2565) );
INVX2TS U1686 ( .A(n2038), .Y(n3063) );
NOR2X2TS U1687 ( .A(n3731), .B(n3072), .Y(n3206) );
CLKINVX6TS U1688 ( .A(n1640), .Y(n1535) );
MXI2X2TS U1689 ( .A(n4367), .B(n4366), .S0(n2043), .Y(n3009) );
AND2X2TS U1690 ( .A(n2207), .B(n3050), .Y(n2206) );
INVX2TS U1691 ( .A(n2120), .Y(n3060) );
INVX12TS U1692 ( .A(n2570), .Y(n1583) );
INVX2TS U1693 ( .A(n3996), .Y(n1646) );
NAND2X4TS U1694 ( .A(n3735), .B(n1605), .Y(n1496) );
INVX6TS U1695 ( .A(n1751), .Y(n1749) );
MXI2X2TS U1696 ( .A(n4305), .B(n4304), .S0(n2005), .Y(n3564) );
MXI2X2TS U1697 ( .A(n1930), .B(n4331), .S0(n1997), .Y(n3568) );
INVX6TS U1698 ( .A(n2619), .Y(n1491) );
INVX2TS U1699 ( .A(n1971), .Y(n3729) );
INVX4TS U1700 ( .A(n2242), .Y(n3288) );
INVX4TS U1701 ( .A(n2245), .Y(n3674) );
INVX3TS U1702 ( .A(n1549), .Y(n3284) );
INVX1TS U1703 ( .A(n3645), .Y(n1560) );
NOR3X2TS U1704 ( .A(d_ff2_Y[56]), .B(d_ff2_Y[57]), .C(d_ff2_Y[58]), .Y(n3546) );
MXI2X2TS U1705 ( .A(n1859), .B(n4370), .S0(n1980), .Y(n3260) );
CLKBUFX2TS U1706 ( .A(n3208), .Y(n1486) );
MXI2X2TS U1707 ( .A(n1885), .B(n4278), .S0(n1980), .Y(n3222) );
MXI2X2TS U1708 ( .A(n1895), .B(n4215), .S0(n2059), .Y(n3592) );
MXI2X2TS U1709 ( .A(n1872), .B(n4337), .S0(n2018), .Y(n3652) );
MXI2X2TS U1710 ( .A(n1891), .B(n4160), .S0(n1695), .Y(n3611) );
MXI2X2TS U1711 ( .A(n1874), .B(n4194), .S0(n2059), .Y(n3589) );
BUFX3TS U1712 ( .A(n3273), .Y(n1735) );
INVX1TS U1713 ( .A(n1552), .Y(n1546) );
INVX12TS U1714 ( .A(n1571), .Y(n1530) );
BUFX20TS U1715 ( .A(n2912), .Y(n3698) );
INVX8TS U1716 ( .A(n3429), .Y(n3439) );
BUFX6TS U1717 ( .A(n2632), .Y(n3530) );
INVX8TS U1718 ( .A(n3429), .Y(n3415) );
BUFX8TS U1719 ( .A(n3422), .Y(n3456) );
BUFX8TS U1720 ( .A(n3359), .Y(n3521) );
BUFX8TS U1721 ( .A(n3359), .Y(n3389) );
BUFX8TS U1722 ( .A(n3359), .Y(n3416) );
BUFX3TS U1723 ( .A(n2354), .Y(n2141) );
BUFX6TS U1724 ( .A(n2632), .Y(n3518) );
BUFX12TS U1725 ( .A(n3361), .Y(n3183) );
NAND3X2TS U1726 ( .A(n2087), .B(n2086), .C(n2085), .Y(n576) );
NAND3X2TS U1727 ( .A(n2081), .B(n2080), .C(n2079), .Y(n575) );
BUFX3TS U1728 ( .A(d_ff2_X[52]), .Y(n1719) );
INVX3TS U1729 ( .A(n2101), .Y(n3412) );
NAND4X2TS U1730 ( .A(n4388), .B(n4387), .C(n4386), .D(n4385), .Y(n3693) );
NAND2X4TS U1731 ( .A(n3190), .B(n1759), .Y(n2608) );
BUFX6TS U1732 ( .A(n2811), .Y(n2671) );
BUFX3TS U1733 ( .A(n3475), .Y(n2129) );
INVX12TS U1734 ( .A(n3273), .Y(n2361) );
BUFX3TS U1735 ( .A(n3190), .Y(n1521) );
BUFX6TS U1736 ( .A(n2811), .Y(n2885) );
BUFX16TS U1737 ( .A(n3272), .Y(n2619) );
INVX4TS U1738 ( .A(n2811), .Y(n2579) );
CLKMX2X4TS U1739 ( .A(n1938), .B(n4277), .S0(n4276), .Y(n3992) );
BUFX16TS U1740 ( .A(n2801), .Y(n2854) );
CLKMX2X4TS U1741 ( .A(n1888), .B(n4252), .S0(n2018), .Y(n4001) );
INVX2TS U1742 ( .A(n3328), .Y(n3329) );
NOR2X1TS U1743 ( .A(n2153), .B(ack_cordic), .Y(n3052) );
BUFX16TS U1744 ( .A(n2739), .Y(n1676) );
INVX6TS U1745 ( .A(n1518), .Y(n3473) );
BUFX16TS U1746 ( .A(n2839), .Y(n1713) );
NAND2X4TS U1747 ( .A(n3228), .B(n3191), .Y(n3223) );
BUFX3TS U1748 ( .A(n2353), .Y(n1485) );
NAND2X6TS U1749 ( .A(n2560), .B(n3190), .Y(n3716) );
CLKBUFX2TS U1750 ( .A(n1524), .Y(n1696) );
INVX12TS U1751 ( .A(n1996), .Y(n1997) );
NOR2X1TS U1752 ( .A(n2320), .B(n2299), .Y(n2684) );
BUFX16TS U1753 ( .A(n2224), .Y(n1519) );
CLKINVX6TS U1754 ( .A(n1505), .Y(n3049) );
CLKINVX2TS U1755 ( .A(n1909), .Y(n1841) );
NAND2X6TS U1756 ( .A(n3313), .B(n3215), .Y(n3217) );
BUFX12TS U1757 ( .A(n2519), .Y(n2202) );
NAND2X4TS U1758 ( .A(n3475), .B(n3474), .Y(n2219) );
BUFX3TS U1759 ( .A(d_ff2_X[54]), .Y(n2093) );
NAND2X4TS U1760 ( .A(n3265), .B(n3714), .Y(n2615) );
CLKAND2X2TS U1761 ( .A(d_ff1_Z[13]), .B(n2970), .Y(n2502) );
INVX4TS U1762 ( .A(n1946), .Y(n1942) );
BUFX6TS U1763 ( .A(n2936), .Y(n1498) );
INVX4TS U1764 ( .A(n3654), .Y(n4574) );
BUFX8TS U1765 ( .A(n2537), .Y(n3296) );
BUFX3TS U1766 ( .A(n2323), .Y(n2154) );
BUFX12TS U1767 ( .A(n2224), .Y(n3684) );
NAND2X4TS U1768 ( .A(n3710), .B(n3072), .Y(n3692) );
NAND2X2TS U1769 ( .A(n3710), .B(n3190), .Y(n2929) );
INVX4TS U1770 ( .A(n3732), .Y(n2602) );
NAND2X4TS U1771 ( .A(n3326), .B(n2947), .Y(n1753) );
AND2X2TS U1772 ( .A(n3911), .B(n2628), .Y(n2308) );
BUFX12TS U1773 ( .A(n2138), .Y(n1684) );
BUFX4TS U1774 ( .A(n2247), .Y(n2143) );
INVX4TS U1775 ( .A(n1930), .Y(n1926) );
BUFX6TS U1776 ( .A(n3338), .Y(n3421) );
BUFX8TS U1777 ( .A(n2632), .Y(n3130) );
NOR3X4TS U1778 ( .A(n4159), .B(n2102), .C(n2103), .Y(n2101) );
OR2X4TS U1779 ( .A(n3245), .B(n2350), .Y(n2212) );
BUFX8TS U1780 ( .A(n2050), .Y(n2049) );
INVX2TS U1781 ( .A(n2298), .Y(n2299) );
BUFX12TS U1782 ( .A(n2714), .Y(n2839) );
INVX6TS U1783 ( .A(n2347), .Y(n3326) );
BUFX3TS U1784 ( .A(n3243), .Y(n3054) );
INVX2TS U1785 ( .A(n2254), .Y(n2255) );
OR2X4TS U1786 ( .A(n2351), .B(n3245), .Y(n3050) );
INVX6TS U1787 ( .A(n2951), .Y(n3072) );
INVX8TS U1788 ( .A(n2226), .Y(n2954) );
BUFX6TS U1789 ( .A(n1975), .Y(n1974) );
NOR2X6TS U1790 ( .A(n2587), .B(n2499), .Y(n2693) );
BUFX12TS U1791 ( .A(n2060), .Y(n2059) );
NAND2X6TS U1792 ( .A(n2703), .B(n2372), .Y(n3474) );
BUFX8TS U1793 ( .A(n2019), .Y(n2018) );
BUFX4TS U1794 ( .A(n2811), .Y(n2970) );
NOR3X6TS U1795 ( .A(n1754), .B(n3324), .C(n3191), .Y(n1757) );
INVX1TS U1796 ( .A(beg_fsm_cordic), .Y(n2191) );
NOR2X6TS U1797 ( .A(n1764), .B(n1759), .Y(n1758) );
INVX4TS U1798 ( .A(d_ff2_Y[60]), .Y(n2628) );
INVX6TS U1799 ( .A(n3214), .Y(n3215) );
NOR2X4TS U1800 ( .A(n1754), .B(n3324), .Y(n2689) );
INVX6TS U1801 ( .A(n1523), .Y(n1524) );
BUFX8TS U1802 ( .A(n3746), .Y(n2587) );
BUFX6TS U1803 ( .A(d_ff2_Y[55]), .Y(n1702) );
CLKINVX6TS U1804 ( .A(n3319), .Y(n2223) );
INVX6TS U1805 ( .A(n3227), .Y(n1759) );
NAND2X6TS U1806 ( .A(n2694), .B(n3191), .Y(n2763) );
INVX2TS U1807 ( .A(n2372), .Y(n2222) );
NOR2X4TS U1808 ( .A(n2789), .B(n3746), .Y(n2640) );
NAND2X6TS U1809 ( .A(n2761), .B(n2760), .Y(n3071) );
BUFX12TS U1810 ( .A(n3648), .Y(n2572) );
INVX4TS U1811 ( .A(n2319), .Y(n2320) );
INVX2TS U1812 ( .A(n1525), .Y(n2946) );
BUFX6TS U1813 ( .A(n1653), .Y(n1667) );
INVX12TS U1814 ( .A(n2358), .Y(n3324) );
OR2X6TS U1815 ( .A(n1693), .B(n3746), .Y(n1755) );
INVX2TS U1816 ( .A(n2357), .Y(n2358) );
INVX6TS U1817 ( .A(n2104), .Y(n1649) );
BUFX6TS U1818 ( .A(n2276), .Y(n1573) );
NOR2X6TS U1819 ( .A(n2951), .B(n1693), .Y(n2694) );
BUFX8TS U1820 ( .A(n2147), .Y(n1504) );
CLKINVX2TS U1821 ( .A(n2370), .Y(n1509) );
BUFX12TS U1822 ( .A(n2789), .Y(n2692) );
INVX6TS U1823 ( .A(n2246), .Y(n2247) );
BUFX6TS U1824 ( .A(n2360), .Y(n1703) );
NAND2X6TS U1825 ( .A(n2951), .B(n2949), .Y(n2948) );
INVX12TS U1826 ( .A(n2633), .Y(n2350) );
INVX6TS U1827 ( .A(n2368), .Y(n2369) );
INVX3TS U1828 ( .A(n2231), .Y(n3187) );
INVX12TS U1829 ( .A(n1693), .Y(n2379) );
INVX12TS U1830 ( .A(n2951), .Y(n1526) );
INVX12TS U1831 ( .A(n2949), .Y(n1527) );
INVX8TS U1832 ( .A(d_ff2_X[54]), .Y(n2949) );
NAND3X4TS U1833 ( .A(n2604), .B(n3711), .C(n3223), .Y(n3196) );
NAND3X8TS U1834 ( .A(n2410), .B(n2604), .C(n2361), .Y(n3212) );
NAND2X8TS U1835 ( .A(n3708), .B(n1707), .Y(n2762) );
BUFX20TS U1836 ( .A(n3549), .Y(n1644) );
INVX16TS U1837 ( .A(n3272), .Y(n1571) );
OAI21X4TS U1838 ( .A0(n1513), .A1(n2345), .B0(n2892), .Y(n1019) );
AND2X8TS U1839 ( .A(n2370), .B(n2357), .Y(n2099) );
OAI2BB1X4TS U1840 ( .A0N(d_ff2_Y[4]), .A1N(n3044), .B0(n3005), .Y(n816) );
MX2X6TS U1841 ( .A(n1875), .B(n4435), .S0(n4434), .Y(n2159) );
NAND2X4TS U1842 ( .A(n2546), .B(n2021), .Y(n3021) );
OAI22X2TS U1843 ( .A0(n2982), .A1(n2984), .B0(n1644), .B1(d_ff3_LUT_out[39]),
.Y(n2695) );
MXI2X4TS U1844 ( .A(n3923), .B(n3320), .S0(n1644), .Y(n707) );
AND3X6TS U1845 ( .A(n1713), .B(d_ff1_Z[10]), .C(n2970), .Y(n1767) );
NAND2X2TS U1846 ( .A(n3659), .B(n2567), .Y(n2647) );
OAI21X2TS U1847 ( .A0(n1514), .A1(n3999), .B0(n2509), .Y(n983) );
AND2X8TS U1848 ( .A(n2122), .B(n2619), .Y(n1710) );
OAI2BB1X4TS U1849 ( .A0N(d_ff2_Y[6]), .A1N(n3044), .B0(n3019), .Y(n812) );
AOI22X2TS U1850 ( .A0(n1516), .A1(n2113), .B0(n3754), .B1(n1588), .Y(n4717)
);
NAND3X4TS U1851 ( .A(n2724), .B(n2725), .C(n2726), .Y(n851) );
NAND2X2TS U1852 ( .A(n2849), .B(n2515), .Y(n2724) );
OAI21X2TS U1853 ( .A0(n3992), .A1(n1513), .B0(n1483), .Y(n1073) );
XNOR2X4TS U1854 ( .A(n3319), .B(n2137), .Y(n3320) );
MXI2X4TS U1855 ( .A(n2485), .B(n3907), .S0(n1519), .Y(n633) );
NAND3X4TS U1856 ( .A(n2847), .B(n2848), .C(n2846), .Y(n861) );
NAND2X4TS U1857 ( .A(n1700), .B(n3573), .Y(n2847) );
NAND2X4TS U1858 ( .A(n3175), .B(n3412), .Y(n3413) );
MXI2X4TS U1859 ( .A(n4183), .B(n4182), .S0(n4181), .Y(n3601) );
MXI2X4TS U1860 ( .A(n4177), .B(n4176), .S0(n4175), .Y(n3610) );
OAI2BB1X4TS U1861 ( .A0N(d_ff2_Y[33]), .A1N(n1507), .B0(n3294), .Y(n758) );
MXI2X2TS U1862 ( .A(n3807), .B(n3960), .S0(n3727), .Y(n807) );
INVX8TS U1863 ( .A(n2789), .Y(n1734) );
NAND2BX4TS U1864 ( .AN(n2935), .B(n2206), .Y(n2205) );
AOI22X2TS U1865 ( .A0(n3334), .A1(n3521), .B0(n3183), .B1(d_ff3_sh_y_out[1]),
.Y(n3335) );
OAI21X4TS U1866 ( .A0(n4442), .A1(n4441), .B0(n4440), .Y(n3334) );
NAND2X4TS U1867 ( .A(n1964), .B(n2199), .Y(n3292) );
AOI22X4TS U1868 ( .A0(n1515), .A1(n3690), .B0(n3758), .B1(n2496), .Y(n4720)
);
INVX4TS U1869 ( .A(n2339), .Y(n3758) );
INVX4TS U1870 ( .A(n2326), .Y(n3752) );
AND2X8TS U1871 ( .A(n3187), .B(n3242), .Y(n2592) );
OAI2BB1X4TS U1872 ( .A0N(d_ff2_Y[34]), .A1N(n1508), .B0(n3295), .Y(n756) );
CLKINVX6TS U1873 ( .A(n4587), .Y(n2551) );
OAI21X2TS U1874 ( .A0(n1644), .A1(n3488), .B0(n3487), .Y(n4604) );
NOR2X4TS U1875 ( .A(d_ff2_X[7]), .B(n2536), .Y(n2200) );
NOR2X2TS U1876 ( .A(n1531), .B(n2373), .Y(n3069) );
NAND3X4TS U1877 ( .A(n2822), .B(n2821), .C(n2820), .Y(n866) );
OAI2BB1X4TS U1878 ( .A0N(n4334), .A1N(n4333), .B0(n4332), .Y(n941) );
NOR2X4TS U1879 ( .A(n1640), .B(n1750), .Y(n1745) );
OAI2BB1X4TS U1880 ( .A0N(n3303), .A1N(d_ff2_Y[39]), .B0(n2771), .Y(n746) );
BUFX16TS U1881 ( .A(n3747), .Y(n1658) );
OAI21X2TS U1882 ( .A0(n1704), .A1(n2143), .B0(n3268), .Y(n718) );
OAI21X4TS U1883 ( .A0(n1704), .A1(n3915), .B0(n3213), .Y(n717) );
MX2X4TS U1884 ( .A(n2314), .B(n2315), .S0(n1696), .Y(n2634) );
OAI2BB1X4TS U1885 ( .A0N(d_ff2_X[63]), .A1N(n1585), .B0(n2797), .Y(n570) );
MXI2X4TS U1886 ( .A(n2481), .B(n3906), .S0(n2594), .Y(n639) );
NAND2X4TS U1887 ( .A(n3033), .B(d_ff2_Y[12]), .Y(n2548) );
NAND2X6TS U1888 ( .A(n2361), .B(n1707), .Y(n2983) );
NAND2X4TS U1889 ( .A(n1643), .B(n3672), .Y(n3673) );
NAND3X4TS U1890 ( .A(n2802), .B(n2803), .C(n2100), .Y(n870) );
NOR2X8TS U1891 ( .A(n3542), .B(n3723), .Y(n933) );
NOR2X4TS U1892 ( .A(n2613), .B(d_ff3_LUT_out[12]), .Y(n3542) );
OAI2BB1X4TS U1893 ( .A0N(d_ff2_Y[28]), .A1N(n1507), .B0(n3013), .Y(n768) );
NOR2X4TS U1894 ( .A(n2603), .B(n3215), .Y(n3210) );
NAND3X4TS U1895 ( .A(n2860), .B(n2862), .C(n2861), .Y(n889) );
NAND2X4TS U1896 ( .A(n2488), .B(n3394), .Y(n2599) );
NAND2X4TS U1897 ( .A(n2488), .B(n2620), .Y(n2556) );
NAND3X4TS U1898 ( .A(n2717), .B(n2716), .C(n2715), .Y(n852) );
MXI2X4TS U1899 ( .A(n2472), .B(n3949), .S0(n2215), .Y(n607) );
OR3X6TS U1900 ( .A(n1765), .B(n1766), .C(n1767), .Y(n879) );
NAND2X2TS U1901 ( .A(n2218), .B(n2627), .Y(n4606) );
NAND2X6TS U1902 ( .A(n3611), .B(n1676), .Y(n2973) );
AOI22X2TS U1903 ( .A0(n2533), .A1(n2116), .B0(n3726), .B1(n3744), .Y(n684)
);
NAND2X6TS U1904 ( .A(n2546), .B(n3561), .Y(n2785) );
MXI2X4TS U1905 ( .A(n3897), .B(n2454), .S0(n1547), .Y(n677) );
NOR2X2TS U1906 ( .A(n3645), .B(n3191), .Y(n2925) );
NAND2X4TS U1907 ( .A(n2311), .B(n2625), .Y(n4614) );
AOI22X2TS U1908 ( .A0(n1989), .A1(n2385), .B0(n2318), .B1(n2495), .Y(n586)
);
NAND2X4TS U1909 ( .A(n2385), .B(n2073), .Y(n2798) );
NAND2X4TS U1910 ( .A(n2385), .B(n3638), .Y(n3075) );
NAND2X4TS U1911 ( .A(n2385), .B(n2041), .Y(n3295) );
NAND2X4TS U1912 ( .A(n2385), .B(n3607), .Y(n2862) );
NAND2X2TS U1913 ( .A(n3659), .B(n2568), .Y(n2650) );
MXI2X4TS U1914 ( .A(n2335), .B(n4046), .S0(n2292), .Y(n994) );
INVX16TS U1915 ( .A(n2287), .Y(n2292) );
NAND2X2TS U1916 ( .A(n3549), .B(n3395), .Y(n3396) );
OAI21X4TS U1917 ( .A0(n1514), .A1(n1968), .B0(n2506), .Y(n987) );
AOI22X2TS U1918 ( .A0(n3696), .A1(n3728), .B0(n2496), .B1(sign_inv_out[14]),
.Y(n2890) );
NAND2X2TS U1919 ( .A(n1736), .B(n3692), .Y(n3194) );
NAND3X4TS U1920 ( .A(n2535), .B(d_ff1_Z[0]), .C(n2975), .Y(n2860) );
MXI2X4TS U1921 ( .A(n3788), .B(n3933), .S0(n3705), .Y(n773) );
MXI2X4TS U1922 ( .A(n3952), .B(n4592), .S0(n3705), .Y(n595) );
MXI2X4TS U1923 ( .A(n2146), .B(n4567), .S0(n3705), .Y(n625) );
MXI2X4TS U1924 ( .A(n3909), .B(n2433), .S0(n3705), .Y(n623) );
MXI2X4TS U1925 ( .A(n3777), .B(n4003), .S0(n3705), .Y(n825) );
OAI21X2TS U1926 ( .A0(n3915), .A1(n3518), .B0(n3391), .Y(add_subt_dataA[55])
);
INVX16TS U1927 ( .A(n2739), .Y(n1678) );
OAI2BB1X4TS U1928 ( .A0N(d_ff2_X[30]), .A1N(n1508), .B0(n3035), .Y(n636) );
NOR2X2TS U1929 ( .A(n3659), .B(n2355), .Y(n2574) );
BUFX4TS U1930 ( .A(n2844), .Y(n1591) );
OAI2BB1X4TS U1931 ( .A0N(d_ff2_X[33]), .A1N(n1507), .B0(n2944), .Y(n630) );
NAND2X4TS U1932 ( .A(n2119), .B(n2199), .Y(n2944) );
OAI2BB1X4TS U1933 ( .A0N(d_ff2_X[5]), .A1N(n3044), .B0(n3041), .Y(n686) );
BUFX20TS U1934 ( .A(n2618), .Y(n4472) );
NAND2X4TS U1935 ( .A(n2202), .B(n3305), .Y(n3306) );
MX2X4TS U1936 ( .A(d_ff1_Z[54]), .B(data_in[54]), .S0(n1511), .Y(n1279) );
NAND2X4TS U1937 ( .A(n3724), .B(n3560), .Y(n2822) );
NAND2X4TS U1938 ( .A(n3046), .B(d_ff2_Y[17]), .Y(n2550) );
OAI2BB1X4TS U1939 ( .A0N(d_ff2_X[20]), .A1N(n3046), .B0(n3040), .Y(n656) );
MXI2X2TS U1940 ( .A(n3900), .B(n2090), .S0(n1709), .Y(n695) );
OAI21X4TS U1941 ( .A0(n2379), .A1(n3072), .B0(n3191), .Y(n3073) );
OAI2BB1X4TS U1942 ( .A0N(d_ff2_Y[30]), .A1N(n1508), .B0(n3003), .Y(n764) );
MXI2X4TS U1943 ( .A(n3848), .B(n4019), .S0(n2293), .Y(n1048) );
MXI2X4TS U1944 ( .A(n3880), .B(n4054), .S0(n2293), .Y(n978) );
MXI2X4TS U1945 ( .A(n3859), .B(n4031), .S0(n2293), .Y(n1024) );
MXI2X4TS U1946 ( .A(n3882), .B(n4057), .S0(n2293), .Y(n972) );
MXI2X4TS U1947 ( .A(n3860), .B(n4032), .S0(n2293), .Y(n1022) );
MXI2X4TS U1948 ( .A(n3885), .B(n4060), .S0(n2293), .Y(n966) );
MXI2X4TS U1949 ( .A(n3839), .B(n4009), .S0(n2290), .Y(n1068) );
MXI2X4TS U1950 ( .A(n3853), .B(n4024), .S0(n2290), .Y(n1038) );
MXI2X4TS U1951 ( .A(n3867), .B(n4040), .S0(n2290), .Y(n1006) );
MXI2X4TS U1952 ( .A(n3846), .B(n4017), .S0(n2290), .Y(n1052) );
MXI2X4TS U1953 ( .A(n3866), .B(n4039), .S0(n2290), .Y(n1008) );
MXI2X4TS U1954 ( .A(n3887), .B(n4062), .S0(n2290), .Y(n962) );
NAND2X4TS U1955 ( .A(n3742), .B(n1484), .Y(n907) );
MX2X4TS U1956 ( .A(n2375), .B(data_in[38]), .S0(n3740), .Y(n1295) );
CLKMX2X4TS U1957 ( .A(d_ff1_Z[31]), .B(data_in[31]), .S0(n3740), .Y(n1302)
);
MX2X4TS U1958 ( .A(d_ff1_Z[6]), .B(data_in[6]), .S0(n3740), .Y(n1327) );
MX2X4TS U1959 ( .A(d_ff1_Z[32]), .B(data_in[32]), .S0(n3740), .Y(n1301) );
NAND2X4TS U1960 ( .A(n2385), .B(n3604), .Y(n2859) );
OAI2BB1X4TS U1961 ( .A0N(d_ff2_Y[2]), .A1N(n3044), .B0(n3002), .Y(n820) );
NAND2X4TS U1962 ( .A(n2546), .B(n3288), .Y(n3002) );
NAND2X8TS U1963 ( .A(n1772), .B(n2939), .Y(n2941) );
OR2X6TS U1964 ( .A(n2410), .B(n2621), .Y(n2180) );
NAND2BX4TS U1965 ( .AN(n2410), .B(d_ff3_LUT_out[5]), .Y(n2765) );
NAND2X4TS U1966 ( .A(n3267), .B(n2383), .Y(n3268) );
NAND2X4TS U1967 ( .A(n3299), .B(n2383), .Y(n3300) );
NAND2X4TS U1968 ( .A(n2383), .B(n3680), .Y(n3681) );
NAND2X4TS U1969 ( .A(n3652), .B(n2383), .Y(n3653) );
NAND2X2TS U1970 ( .A(n2234), .B(d_ff2_Z[0]), .Y(n2861) );
NAND2X2TS U1971 ( .A(n2234), .B(d_ff2_Z[8]), .Y(n2965) );
NAND2X2TS U1972 ( .A(n2234), .B(d_ff2_Z[3]), .Y(n2793) );
NAND2X2TS U1973 ( .A(n2234), .B(d_ff2_Z[1]), .Y(n2858) );
NAND2X2TS U1974 ( .A(n2234), .B(d_ff2_Z[4]), .Y(n2968) );
NAND2X2TS U1975 ( .A(n2234), .B(d_ff2_Z[5]), .Y(n2962) );
NAND2X2TS U1976 ( .A(n2234), .B(d_ff2_Z[7]), .Y(n2959) );
NAND2X2TS U1977 ( .A(n2234), .B(d_ff2_Z[6]), .Y(n2977) );
NAND2X4TS U1978 ( .A(n1591), .B(n3605), .Y(n2735) );
MXI2X4TS U1979 ( .A(n1887), .B(n4174), .S0(n4173), .Y(n3605) );
OAI21X4TS U1980 ( .A0(n4412), .A1(n4411), .B0(n4410), .Y(n3479) );
NOR2X6TS U1981 ( .A(n2104), .B(d_ff2_Y[55]), .Y(n2142) );
CLKINVX3TS U1982 ( .A(d_ff2_Y[55]), .Y(n1679) );
NAND3X6TS U1983 ( .A(n2973), .B(n2971), .C(n2972), .Y(n880) );
OR2X4TS U1984 ( .A(n2538), .B(n2168), .Y(n2972) );
NAND2X4TS U1985 ( .A(n2695), .B(n4525), .Y(n906) );
NAND2X8TS U1986 ( .A(n3473), .B(n2219), .Y(n2301) );
MXI2X4TS U1987 ( .A(n3840), .B(n4010), .S0(n2291), .Y(n1066) );
MXI2X4TS U1988 ( .A(n3854), .B(n4025), .S0(n2291), .Y(n1036) );
MXI2X4TS U1989 ( .A(n3847), .B(n4018), .S0(n2291), .Y(n1050) );
MXI2X4TS U1990 ( .A(n3844), .B(n4014), .S0(n2291), .Y(n1058) );
MXI2X4TS U1991 ( .A(n3857), .B(n4029), .S0(n2291), .Y(n1028) );
MXI2X4TS U1992 ( .A(n3856), .B(n4028), .S0(n2291), .Y(n1030) );
MXI2X4TS U1993 ( .A(n3868), .B(n4041), .S0(n2291), .Y(n1004) );
NAND2X4TS U1994 ( .A(n1580), .B(d_ff2_Z[19]), .Y(n2803) );
OAI2BB1X4TS U1995 ( .A0N(d_ff2_Y[22]), .A1N(n1580), .B0(n3008), .Y(n780) );
OAI2BB1X4TS U1996 ( .A0N(d_ff2_Y[27]), .A1N(n1580), .B0(n3021), .Y(n770) );
OAI2BB1X4TS U1997 ( .A0N(d_ff2_X[27]), .A1N(n1580), .B0(n3038), .Y(n642) );
MXI2X4TS U1998 ( .A(n3886), .B(n4061), .S0(n2293), .Y(n964) );
INVX16TS U1999 ( .A(n2287), .Y(n2293) );
MXI2X4TS U2000 ( .A(n3889), .B(n4064), .S0(n2290), .Y(n958) );
INVX16TS U2001 ( .A(n2286), .Y(n2290) );
NAND3X4TS U2002 ( .A(n2728), .B(n2729), .C(n2727), .Y(n854) );
NAND2X4TS U2003 ( .A(n1689), .B(n2954), .Y(n1686) );
MXI2X4TS U2004 ( .A(n3873), .B(n4047), .S0(n2294), .Y(n992) );
MXI2X4TS U2005 ( .A(n3861), .B(n4033), .S0(n2294), .Y(n1020) );
MXI2X4TS U2006 ( .A(n3875), .B(n4049), .S0(n2294), .Y(n988) );
MXI2X4TS U2007 ( .A(n3871), .B(n4044), .S0(n2294), .Y(n998) );
MXI2X4TS U2008 ( .A(n3850), .B(n4021), .S0(n2294), .Y(n1044) );
MXI2X4TS U2009 ( .A(n3890), .B(n4065), .S0(n2294), .Y(n956) );
NAND2X4TS U2010 ( .A(n3724), .B(n3613), .Y(n2812) );
NOR2X4TS U2011 ( .A(n1532), .B(d_ff3_LUT_out[6]), .Y(n3201) );
MXI2X4TS U2012 ( .A(n3888), .B(n4063), .S0(n2291), .Y(n960) );
INVX16TS U2013 ( .A(n2286), .Y(n2291) );
MXI2X4TS U2014 ( .A(n3877), .B(n4051), .S0(n2288), .Y(n984) );
MXI2X4TS U2015 ( .A(n3864), .B(n4037), .S0(n2288), .Y(n1012) );
MXI2X4TS U2016 ( .A(n3837), .B(n4007), .S0(n2288), .Y(n1072) );
MXI2X4TS U2017 ( .A(n3842), .B(n4012), .S0(n2288), .Y(n1062) );
MXI2X4TS U2018 ( .A(n3855), .B(n4027), .S0(n2288), .Y(n1032) );
MXI2X4TS U2019 ( .A(n3851), .B(n4022), .S0(n2288), .Y(n1042) );
MXI2X4TS U2020 ( .A(n3869), .B(n4042), .S0(n2288), .Y(n1002) );
MXI2X4TS U2021 ( .A(n3796), .B(n4005), .S0(n2288), .Y(n950) );
NAND3X4TS U2022 ( .A(n2809), .B(n2808), .C(n2810), .Y(n874) );
MXI2X4TS U2023 ( .A(n3862), .B(n4034), .S0(n2295), .Y(n1018) );
MXI2X4TS U2024 ( .A(n3876), .B(n4050), .S0(n2295), .Y(n986) );
MXI2X4TS U2025 ( .A(n3872), .B(n4045), .S0(n2295), .Y(n996) );
MXI2X4TS U2026 ( .A(n3841), .B(n4011), .S0(n2295), .Y(n1064) );
MXI2X4TS U2027 ( .A(n3874), .B(n4048), .S0(n2295), .Y(n990) );
MXI2X4TS U2028 ( .A(n3849), .B(n4020), .S0(n2295), .Y(n1046) );
MXI2X4TS U2029 ( .A(n3795), .B(n4004), .S0(n2295), .Y(n952) );
MXI2X4TS U2030 ( .A(n3188), .B(n3717), .S0(n2587), .Y(n1341) );
CLKINVX3TS U2031 ( .A(n2990), .Y(n2989) );
INVX4TS U2032 ( .A(n3636), .Y(n4528) );
NAND2X4TS U2033 ( .A(n2543), .B(n3636), .Y(n3032) );
NAND2X2TS U2034 ( .A(n3282), .B(n2201), .Y(n3012) );
NAND3X6TS U2035 ( .A(n1751), .B(n1599), .C(n1753), .Y(n1743) );
OAI2BB1X4TS U2036 ( .A0N(n3278), .A1N(n2924), .B0(n2921), .Y(n963) );
BUFX20TS U2037 ( .A(n3720), .Y(n1511) );
OAI2BB1X4TS U2038 ( .A0N(d_ff2_X[50]), .A1N(n3751), .B0(n3316), .Y(n596) );
NAND2X2TS U2039 ( .A(n2739), .B(n3620), .Y(n3316) );
NAND3X6TS U2040 ( .A(n1490), .B(n3713), .C(n1489), .Y(n929) );
OAI2BB1X4TS U2041 ( .A0N(d_ff3_LUT_out[20]), .A1N(n2629), .B0(n3713), .Y(
n925) );
NAND2X2TS U2042 ( .A(n2107), .B(n3241), .Y(n2636) );
MXI2X4TS U2043 ( .A(n3878), .B(n4052), .S0(n2289), .Y(n982) );
MXI2X4TS U2044 ( .A(n3865), .B(n4038), .S0(n2289), .Y(n1010) );
MXI2X4TS U2045 ( .A(n3838), .B(n4008), .S0(n2289), .Y(n1070) );
MXI2X4TS U2046 ( .A(n3843), .B(n4013), .S0(n2289), .Y(n1060) );
MXI2X4TS U2047 ( .A(n3852), .B(n4023), .S0(n2289), .Y(n1040) );
MXI2X4TS U2048 ( .A(n3863), .B(n4035), .S0(n2289), .Y(n1016) );
MXI2X4TS U2049 ( .A(n3883), .B(n4058), .S0(n2289), .Y(n970) );
MX2X4TS U2050 ( .A(d_ff1_Z[57]), .B(data_in[57]), .S0(n1512), .Y(n1276) );
BUFX20TS U2051 ( .A(n3720), .Y(n1512) );
MX2X4TS U2052 ( .A(d_ff1_Z[8]), .B(data_in[8]), .S0(n1510), .Y(n1325) );
MX2X4TS U2053 ( .A(d_ff1_Z[7]), .B(data_in[7]), .S0(n1510), .Y(n1326) );
MX2X4TS U2054 ( .A(d_ff1_Z[48]), .B(data_in[48]), .S0(n1510), .Y(n1285) );
MX2X4TS U2055 ( .A(d_ff1_Z[56]), .B(data_in[56]), .S0(n3739), .Y(n1277) );
MX2X4TS U2056 ( .A(d_ff1_Z[52]), .B(data_in[52]), .S0(n3739), .Y(n1281) );
MX2X4TS U2057 ( .A(d_ff1_Z[50]), .B(data_in[50]), .S0(n3739), .Y(n1283) );
MX2X4TS U2058 ( .A(d_ff1_Z[0]), .B(data_in[0]), .S0(n3739), .Y(n1333) );
MX2X4TS U2059 ( .A(d_ff1_Z[2]), .B(data_in[2]), .S0(n3739), .Y(n1331) );
MX2X4TS U2060 ( .A(d_ff1_Z[44]), .B(data_in[44]), .S0(n3739), .Y(n1289) );
MX2X4TS U2061 ( .A(d_ff1_Z[45]), .B(data_in[45]), .S0(n3739), .Y(n1288) );
MX2X4TS U2062 ( .A(d_ff1_Z[1]), .B(data_in[1]), .S0(n3739), .Y(n1332) );
MX2X4TS U2063 ( .A(d_ff1_Z[43]), .B(data_in[43]), .S0(n3739), .Y(n1290) );
MX2X4TS U2064 ( .A(d_ff1_Z[3]), .B(data_in[3]), .S0(n3739), .Y(n1330) );
AOI22X2TS U2065 ( .A0(n3700), .A1(n2118), .B0(sign_inv_out[34]), .B1(n3689),
.Y(n2902) );
AOI22X2TS U2066 ( .A0(n3700), .A1(n2115), .B0(sign_inv_out[35]), .B1(n1642),
.Y(n2700) );
AOI22X2TS U2067 ( .A0(n3700), .A1(n3676), .B0(sign_inv_out[31]), .B1(n1642),
.Y(n2905) );
AOI22X2TS U2068 ( .A0(n3700), .A1(n3668), .B0(sign_inv_out[55]), .B1(n1642),
.Y(n2921) );
AOI22X2TS U2069 ( .A0(n3700), .A1(n3660), .B0(sign_inv_out[53]), .B1(n1642),
.Y(n2922) );
AOI22X2TS U2070 ( .A0(n3700), .A1(n2119), .B0(sign_inv_out[33]), .B1(n1642),
.Y(n2903) );
AOI22X2TS U2071 ( .A0(n3700), .A1(n3679), .B0(sign_inv_out[58]), .B1(n1642),
.Y(n2919) );
OAI2BB1X4TS U2072 ( .A0N(n2205), .A1N(n2310), .B0(n2938), .Y(n1344) );
INVX12TS U2073 ( .A(n2241), .Y(n1725) );
NAND2X8TS U2074 ( .A(n2696), .B(n3243), .Y(n2241) );
INVX12TS U2075 ( .A(n2286), .Y(n2289) );
INVX6TS U2076 ( .A(n2098), .Y(n1574) );
OAI2BB1X4TS U2077 ( .A0N(n3283), .A1N(n2924), .B0(n2908), .Y(n1057) );
OAI2BB1X4TS U2078 ( .A0N(d_ff2_Y[18]), .A1N(n3046), .B0(n3015), .Y(n788) );
INVX8TS U2079 ( .A(n4476), .Y(n2588) );
NAND2X4TS U2080 ( .A(n2220), .B(n3742), .Y(n913) );
INVX16TS U2081 ( .A(n3757), .Y(n2286) );
NAND2X8TS U2082 ( .A(n2686), .B(n3242), .Y(n3757) );
BUFX20TS U2083 ( .A(n2951), .Y(n2499) );
AND2X8TS U2084 ( .A(n3541), .B(n3071), .Y(n1659) );
NAND3X6TS U2085 ( .A(n2794), .B(n2792), .C(n2793), .Y(n886) );
AOI22X4TS U2086 ( .A0(n2557), .A1(sign_inv_out[41]), .B0(n2092), .B1(n3691),
.Y(n2508) );
CLKINVX12TS U2087 ( .A(n1733), .Y(n2240) );
INVX16TS U2088 ( .A(n1637), .Y(n1671) );
AOI22X4TS U2089 ( .A0(n1516), .A1(n3665), .B0(n2496), .B1(sign_inv_out[0]),
.Y(n1483) );
NAND2X6TS U2090 ( .A(n1488), .B(n1487), .Y(n796) );
NOR2X8TS U2091 ( .A(n2233), .B(n2231), .Y(n2232) );
NAND2X4TS U2092 ( .A(n2229), .B(d_ff3_LUT_out[38]), .Y(n1484) );
NAND2X8TS U2093 ( .A(n1671), .B(n3283), .Y(n3014) );
BUFX20TS U2094 ( .A(n2519), .Y(n2201) );
NAND2X2TS U2095 ( .A(n3047), .B(n3009), .Y(n3010) );
OAI2BB1X4TS U2096 ( .A0N(d_ff2_Y[21]), .A1N(n3046), .B0(n3010), .Y(n782) );
NAND2X8TS U2097 ( .A(n3489), .B(n3073), .Y(n3713) );
AOI22X4TS U2098 ( .A0(n2496), .A1(sign_inv_out[61]), .B0(n3655), .B1(n1515),
.Y(n2493) );
NAND2X8TS U2099 ( .A(n1491), .B(d_ff3_LUT_out[16]), .Y(n1490) );
NOR2X8TS U2100 ( .A(n2510), .B(n1492), .Y(n2595) );
NOR2X8TS U2101 ( .A(d_ff2_X[53]), .B(n2379), .Y(n1492) );
NAND2X4TS U2102 ( .A(n2312), .B(n1493), .Y(n4619) );
AND2X8TS U2103 ( .A(n3330), .B(n3329), .Y(n2312) );
NOR2X8TS U2104 ( .A(n2111), .B(n3071), .Y(n2150) );
NOR2X8TS U2105 ( .A(d_ff2_X[52]), .B(n3746), .Y(n2510) );
NAND2X2TS U2106 ( .A(n2739), .B(n3566), .Y(n2868) );
OAI21X4TS U2107 ( .A0(n2155), .A1(n2117), .B0(n1497), .Y(n953) );
AOI22X2TS U2108 ( .A0(n1588), .A1(sign_inv_out[60]), .B0(n3691), .B1(n3678),
.Y(n1497) );
NAND3X6TS U2109 ( .A(n3332), .B(n3711), .C(n2248), .Y(n4613) );
NAND2X2TS U2110 ( .A(n2974), .B(n3595), .Y(n2649) );
OAI2BB1X4TS U2111 ( .A0N(n2588), .A1N(n3060), .B0(n3061), .Y(n1051) );
INVX16TS U2112 ( .A(n1736), .Y(n3273) );
NOR2X8TS U2113 ( .A(n3893), .B(cont_var_out[0]), .Y(n3205) );
OAI2BB1X4TS U2114 ( .A0N(d_ff2_Y[31]), .A1N(n1507), .B0(n3023), .Y(n762) );
OAI2BB1X4TS U2115 ( .A0N(d_ff2_Y[15]), .A1N(n3033), .B0(n2994), .Y(n794) );
OAI2BB1X4TS U2116 ( .A0N(d_ff2_Y[43]), .A1N(n2407), .B0(n2769), .Y(n738) );
NAND2X4TS U2117 ( .A(n1594), .B(n3617), .Y(n3026) );
AOI22X4TS U2118 ( .A0(n2496), .A1(sign_inv_out[56]), .B0(n3703), .B1(n3664),
.Y(n2923) );
NAND2X4TS U2119 ( .A(n2385), .B(n3624), .Y(n2797) );
INVX8TS U2120 ( .A(n2801), .Y(n2843) );
NAND3BX4TS U2121 ( .AN(n1666), .B(n2653), .C(n2654), .Y(n848) );
INVX8TS U2122 ( .A(n3545), .Y(n2140) );
AOI22X2TS U2123 ( .A0(n3662), .A1(n3691), .B0(n2557), .B1(sign_inv_out[24]),
.Y(n2888) );
BUFX20TS U2124 ( .A(n2912), .Y(n1516) );
CLKINVX12TS U2125 ( .A(n3737), .Y(n3738) );
BUFX12TS U2126 ( .A(n2256), .Y(n2214) );
INVX12TS U2127 ( .A(n2643), .Y(n2655) );
AOI22X2TS U2128 ( .A0(n2496), .A1(sign_inv_out[26]), .B0(n3661), .B1(n3698),
.Y(n2893) );
INVX16TS U2129 ( .A(n2682), .Y(n4469) );
BUFX12TS U2130 ( .A(n2256), .Y(n2147) );
BUFX16TS U2131 ( .A(n2912), .Y(n3691) );
AOI22X2TS U2132 ( .A0(n1515), .A1(n2068), .B0(sign_inv_out[36]), .B1(n1724),
.Y(n2900) );
AOI22X2TS U2133 ( .A0(n2504), .A1(sign_inv_out[28]), .B0(n3675), .B1(n3698),
.Y(n2891) );
INVX3TS U2134 ( .A(n1732), .Y(n1523) );
NAND2X8TS U2135 ( .A(n3205), .B(n2936), .Y(n1505) );
INVX16TS U2136 ( .A(n2795), .Y(n2936) );
MXI2X4TS U2137 ( .A(n2130), .B(n2681), .S0(n2936), .Y(n2359) );
OAI2BB1X4TS U2138 ( .A0N(n1506), .A1N(n3263), .B0(n1696), .Y(n2938) );
INVX4TS U2139 ( .A(n3054), .Y(n3263) );
OAI22X2TS U2140 ( .A0(n3717), .A1(n3716), .B0(n3731), .B1(n3191), .Y(n1338)
);
BUFX16TS U2141 ( .A(n3720), .Y(n1510) );
INVX8TS U2142 ( .A(n2955), .Y(n4477) );
INVX8TS U2143 ( .A(n4477), .Y(n1513) );
INVX16TS U2144 ( .A(n4477), .Y(n1514) );
BUFX16TS U2145 ( .A(n2912), .Y(n1515) );
NAND2X4TS U2146 ( .A(d_ff2_Y[55]), .B(n1509), .Y(n1698) );
NOR2X8TS U2147 ( .A(n1702), .B(n3191), .Y(n1518) );
NAND2X2TS U2148 ( .A(n2591), .B(n3553), .Y(n2577) );
OAI21X2TS U2149 ( .A0(n2611), .A1(n2229), .B0(n2610), .Y(n577) );
CLKAND2X2TS U2150 ( .A(n2147), .B(n2198), .Y(n1536) );
INVX12TS U2151 ( .A(n1655), .Y(n1550) );
INVX12TS U2152 ( .A(n3489), .Y(n3252) );
INVX12TS U2153 ( .A(n2682), .Y(n2388) );
INVX12TS U2154 ( .A(n2682), .Y(n4466) );
NAND2X8TS U2155 ( .A(n1526), .B(n1527), .Y(n1525) );
MXI2X4TS U2156 ( .A(n3748), .B(n3991), .S0(n3747), .Y(n709) );
MXI2X4TS U2157 ( .A(n3833), .B(n3987), .S0(n3747), .Y(n731) );
MXI2X4TS U2158 ( .A(n3831), .B(n3985), .S0(n3747), .Y(n735) );
CLKINVX12TS U2159 ( .A(n3737), .Y(n3740) );
CLKINVX12TS U2160 ( .A(n3737), .Y(n3741) );
MX2X6TS U2161 ( .A(n4090), .B(n4089), .S0(n4088), .Y(n1528) );
INVX8TS U2162 ( .A(n1528), .Y(n3664) );
MX2X4TS U2163 ( .A(n1529), .B(n2473), .S0(n3735), .Y(n581) );
AO21X4TS U2164 ( .A0(n1719), .A1(n2587), .B0(n2237), .Y(n1529) );
INVX8TS U2165 ( .A(n1547), .Y(n1532) );
NAND2X6TS U2166 ( .A(n2979), .B(n2587), .Y(n4526) );
NAND3X4TS U2167 ( .A(n3200), .B(n1600), .C(n2993), .Y(n916) );
INVX16TS U2168 ( .A(n2589), .Y(n1640) );
INVX8TS U2169 ( .A(n3651), .Y(n1537) );
BUFX12TS U2170 ( .A(n2111), .Y(n3651) );
INVX12TS U2171 ( .A(n2098), .Y(n1543) );
INVX16TS U2172 ( .A(n1551), .Y(n2682) );
BUFX20TS U2173 ( .A(n2760), .Y(n3732) );
NAND2X8TS U2174 ( .A(n3192), .B(n3711), .Y(n3706) );
NAND2X8TS U2175 ( .A(n3475), .B(n3474), .Y(n1539) );
INVX16TS U2176 ( .A(n1697), .Y(n3475) );
NAND3X4TS U2177 ( .A(n1702), .B(n2372), .C(n3319), .Y(n1681) );
OR2X4TS U2178 ( .A(n1678), .B(n4692), .Y(n2674) );
MXI2X4TS U2179 ( .A(n4415), .B(n4414), .S0(n4413), .Y(n3563) );
MX2X4TS U2180 ( .A(n1880), .B(n4394), .S0(n4393), .Y(n1541) );
CLKINVX12TS U2181 ( .A(n1723), .Y(n2098) );
INVX12TS U2182 ( .A(n2240), .Y(n3689) );
MX2X4TS U2183 ( .A(n1857), .B(n4439), .S0(n4438), .Y(n1544) );
MXI2X2TS U2184 ( .A(n2688), .B(n2687), .S0(n2292), .Y(n946) );
CLKINVX12TS U2185 ( .A(n1551), .Y(n3545) );
NAND2X2TS U2186 ( .A(n3047), .B(n3572), .Y(n2884) );
AOI22X2TS U2187 ( .A0(n3703), .A1(n3202), .B0(sign_inv_out[54]), .B1(n2504),
.Y(n3203) );
AOI22X2TS U2188 ( .A0(n1515), .A1(n3259), .B0(sign_inv_out[7]), .B1(n2409),
.Y(n2910) );
AOI22X2TS U2189 ( .A0(n3698), .A1(n3657), .B0(n2504), .B1(sign_inv_out[62]),
.Y(n2956) );
AOI22X4TS U2190 ( .A0(n3624), .A1(n3691), .B0(n1588), .B1(n1546), .Y(n2494)
);
BUFX20TS U2191 ( .A(n2111), .Y(n1547) );
MXI2X2TS U2192 ( .A(n2277), .B(n1573), .S0(n3554), .Y(n2611) );
MXI2X4TS U2193 ( .A(n3884), .B(n4059), .S0(n2292), .Y(n968) );
MXI2X4TS U2194 ( .A(n3881), .B(n4055), .S0(n2292), .Y(n976) );
MXI2X4TS U2195 ( .A(n3858), .B(n4030), .S0(n2292), .Y(n1026) );
MXI2X4TS U2196 ( .A(n3879), .B(n4053), .S0(n2292), .Y(n980) );
MXI2X4TS U2197 ( .A(n3870), .B(n4043), .S0(n2292), .Y(n1000) );
MXI2X4TS U2198 ( .A(n3845), .B(n4015), .S0(n2292), .Y(n1056) );
MX2X6TS U2199 ( .A(n1918), .B(n4327), .S0(n4326), .Y(n1549) );
CLKINVX12TS U2200 ( .A(n2530), .Y(n1655) );
NAND3X4TS U2201 ( .A(n4098), .B(n4097), .C(n4096), .Y(n3409) );
MXI2X2TS U2202 ( .A(n3924), .B(n3708), .S0(n2230), .Y(n928) );
NAND3X4TS U2203 ( .A(n3708), .B(n3692), .C(n1756), .Y(n2641) );
BUFX16TS U2204 ( .A(n2912), .Y(n3703) );
OR2X8TS U2205 ( .A(n2359), .B(n2612), .Y(n1551) );
MX2X4TS U2206 ( .A(n1884), .B(n4450), .S0(n4449), .Y(n1553) );
BUFX4TS U2207 ( .A(n3554), .Y(n2591) );
OR2X8TS U2208 ( .A(n2198), .B(n2310), .Y(n1555) );
CLKINVX12TS U2209 ( .A(n1555), .Y(n2937) );
NAND2BX4TS U2210 ( .AN(n1678), .B(n3221), .Y(n2768) );
NAND2BX2TS U2211 ( .AN(n2554), .B(n3578), .Y(n2830) );
NAND2X4TS U2212 ( .A(n1643), .B(n3618), .Y(n3027) );
CLKINVX12TS U2213 ( .A(n1723), .Y(n2408) );
INVX2TS U2214 ( .A(n2216), .Y(n1556) );
INVX4TS U2215 ( .A(n1556), .Y(n1557) );
BUFX20TS U2216 ( .A(n2714), .Y(n2570) );
NAND3BX4TS U2217 ( .AN(n1558), .B(n2806), .C(n2807), .Y(n872) );
AND2X4TS U2218 ( .A(n2570), .B(n2580), .Y(n1558) );
NAND2X2TS U2219 ( .A(n2539), .B(n3565), .Y(n2726) );
NAND2X4TS U2220 ( .A(n1676), .B(n3615), .Y(n1677) );
NAND2X4TS U2221 ( .A(n3637), .B(n1676), .Y(n3048) );
NAND2X2TS U2222 ( .A(n1676), .B(n3590), .Y(n2825) );
NAND2X4TS U2223 ( .A(n2573), .B(n1646), .Y(n1727) );
NAND3BX4TS U2224 ( .AN(n1559), .B(n2122), .C(n3235), .Y(n2529) );
OR2X4TS U2225 ( .A(n3485), .B(n3727), .Y(n1559) );
BUFX20TS U2226 ( .A(n3489), .Y(n2215) );
MXI2X4TS U2227 ( .A(n2010), .B(n1881), .S0(n1563), .Y(n2342) );
INVX8TS U2228 ( .A(n2312), .Y(n3332) );
BUFX12TS U2229 ( .A(n2241), .Y(n1723) );
MXI2X4TS U2230 ( .A(n1565), .B(n1861), .S0(n1566), .Y(n1564) );
INVX16TS U2231 ( .A(n2924), .Y(n2155) );
NAND2BX4TS U2232 ( .AN(n1678), .B(n3591), .Y(n2794) );
OR2X6TS U2233 ( .A(n2122), .B(n3236), .Y(n3239) );
OAI2BB1X4TS U2234 ( .A0N(d_ff2_Y[61]), .A1N(n1507), .B0(n3322), .Y(n711) );
AOI2BB2X4TS U2235 ( .B0(n2491), .B1(n2489), .A0N(n3330), .A1N(n1572), .Y(
n4607) );
OR2X4TS U2236 ( .A(n3735), .B(n2124), .Y(n1572) );
INVX16TS U2237 ( .A(n3554), .Y(n3330) );
NAND2X2TS U2238 ( .A(n2539), .B(n3609), .Y(n2646) );
INVX16TS U2239 ( .A(n2190), .Y(n3543) );
MXI2X4TS U2240 ( .A(n4200), .B(n4199), .S0(n1987), .Y(n3586) );
NAND2X4TS U2241 ( .A(n3657), .B(n2533), .Y(n3658) );
BUFX20TS U2242 ( .A(n2224), .Y(n3711) );
AOI2BB2X4TS U2243 ( .B0(n4553), .B1(n1643), .A0N(d_ff2_X[28]), .A1N(n2854),
.Y(n640) );
AOI21X4TS U2244 ( .A0(n3227), .A1(n3191), .B0(n1521), .Y(n3192) );
NAND2X4TS U2245 ( .A(n3190), .B(n3228), .Y(n2774) );
INVX16TS U2246 ( .A(n1764), .Y(n3190) );
INVX16TS U2247 ( .A(n2801), .Y(n1580) );
NAND2X4TS U2248 ( .A(n2843), .B(d_ff2_Z[35]), .Y(n2728) );
NAND2X4TS U2249 ( .A(n1580), .B(d_ff2_Z[15]), .Y(n2809) );
AOI22X2TS U2250 ( .A0(n3696), .A1(n3636), .B0(sign_inv_out[12]), .B1(n2409),
.Y(n2889) );
AOI22X2TS U2251 ( .A0(n3696), .A1(n3630), .B0(sign_inv_out[15]), .B1(n1574),
.Y(n3066) );
AOI22X2TS U2252 ( .A0(n3623), .A1(n3703), .B0(sign_inv_out[17]), .B1(n1588),
.Y(n3062) );
INVX8TS U2253 ( .A(n1581), .Y(n1582) );
INVX16TS U2254 ( .A(n2854), .Y(n1586) );
NAND2X4TS U2255 ( .A(n1586), .B(n2285), .Y(n2737) );
NAND2X4TS U2256 ( .A(n1586), .B(n2268), .Y(n2842) );
OAI2BB1X4TS U2257 ( .A0N(d_ff2_Y[63]), .A1N(n1585), .B0(n2767), .Y(n698) );
OAI2BB1X4TS U2258 ( .A0N(d_ff2_Y[0]), .A1N(n1586), .B0(n2997), .Y(n824) );
AOI22X4TS U2259 ( .A0(n2557), .A1(sign_inv_out[43]), .B0(n1648), .B1(n3703),
.Y(n2506) );
AOI22X2TS U2260 ( .A0(sign_inv_out[44]), .A1(n2496), .B0(n3627), .B1(n1516),
.Y(n2497) );
BUFX20TS U2261 ( .A(n3689), .Y(n2504) );
MX2X4TS U2262 ( .A(n4369), .B(n4368), .S0(n2026), .Y(n2345) );
MX2X4TS U2263 ( .A(n4273), .B(n4272), .S0(n2026), .Y(n2344) );
MX2X4TS U2264 ( .A(n4291), .B(n4290), .S0(n2026), .Y(n2346) );
NAND2X4TS U2265 ( .A(n2843), .B(d_ff2_Z[17]), .Y(n2806) );
NAND2X4TS U2266 ( .A(n2843), .B(d_ff2_Z[37]), .Y(n2716) );
NAND2X4TS U2267 ( .A(n1580), .B(d_ff2_Z[14]), .Y(n2852) );
NAND2X4TS U2268 ( .A(n1580), .B(d_ff2_Z[16]), .Y(n2815) );
NAND2X4TS U2269 ( .A(n1580), .B(d_ff2_Z[34]), .Y(n2731) );
BUFX20TS U2270 ( .A(n2844), .Y(n1592) );
BUFX20TS U2271 ( .A(n2844), .Y(n1593) );
BUFX20TS U2272 ( .A(n2844), .Y(n1594) );
AOI22X2TS U2273 ( .A0(n1593), .A1(n2127), .B0(n1584), .B1(n4565), .Y(n628)
);
NAND2X4TS U2274 ( .A(n1594), .B(n3628), .Y(n2203) );
NAND2X4TS U2275 ( .A(n1593), .B(n3642), .Y(n3037) );
NAND2X4TS U2276 ( .A(n1594), .B(n3623), .Y(n3042) );
NAND2X2TS U2277 ( .A(n1595), .B(n2262), .Y(n2676) );
NAND2X2TS U2278 ( .A(n1595), .B(n2264), .Y(n2706) );
NAND2X4TS U2279 ( .A(n3744), .B(d_ff2_Z[38]), .Y(n2725) );
NAND2X2TS U2280 ( .A(n3744), .B(d_ff2_Z[40]), .Y(n2651) );
NOR2X4TS U2281 ( .A(n2153), .B(n3245), .Y(n2637) );
NOR2X4TS U2282 ( .A(n2026), .B(n1475), .Y(n1739) );
CLKMX2X2TS U2283 ( .A(n1864), .B(n2017), .S0(n2018), .Y(n3307) );
MXI2X2TS U2284 ( .A(n1939), .B(n4191), .S0(n2048), .Y(n3591) );
NAND3X2TS U2285 ( .A(n2930), .B(n1498), .C(n2929), .Y(n2931) );
NAND3X1TS U2286 ( .A(n2538), .B(n2438), .C(n2885), .Y(n2675) );
NAND2X2TS U2287 ( .A(n1680), .B(n1668), .Y(n2933) );
NAND2X1TS U2288 ( .A(n3531), .B(d_ff2_Y[1]), .Y(n3468) );
BUFX6TS U2289 ( .A(n3130), .Y(n3374) );
NAND4X4TS U2290 ( .A(n1748), .B(n1744), .C(n1743), .D(n1741), .Y(n578) );
INVX12TS U2291 ( .A(n2592), .Y(n2486) );
INVX2TS U2292 ( .A(result_add_subt[56]), .Y(n4705) );
MX2X4TS U2293 ( .A(n1889), .B(n4322), .S0(n4321), .Y(n2343) );
AND2X8TS U2294 ( .A(n2953), .B(n1684), .Y(n1599) );
AND2X8TS U2295 ( .A(n3272), .B(n2763), .Y(n1602) );
CLKMX2X4TS U2296 ( .A(n1946), .B(n4416), .S0(n1997), .Y(n1603) );
AND2X8TS U2297 ( .A(n3543), .B(n1667), .Y(n1606) );
MX2X4TS U2298 ( .A(n4166), .B(n4165), .S0(n1987), .Y(n1607) );
MX2X4TS U2299 ( .A(n1939), .B(n4191), .S0(n1695), .Y(n1608) );
MX2X4TS U2300 ( .A(n1895), .B(n4215), .S0(n1582), .Y(n1609) );
CLKMX2X4TS U2301 ( .A(n1932), .B(n4365), .S0(n2049), .Y(n1610) );
CLKBUFX3TS U2302 ( .A(n3538), .Y(n1612) );
CLKBUFX3TS U2303 ( .A(n1615), .Y(n4489) );
CLKBUFX3TS U2304 ( .A(n1615), .Y(n2389) );
CLKBUFX3TS U2305 ( .A(n1615), .Y(n4504) );
CLKBUFX3TS U2306 ( .A(n1615), .Y(n4490) );
CLKBUFX3TS U2307 ( .A(n1615), .Y(n4481) );
CLKBUFX3TS U2308 ( .A(n1629), .Y(n1624) );
CLKBUFX3TS U2309 ( .A(n1615), .Y(n1625) );
CLKBUFX3TS U2310 ( .A(n1615), .Y(n4070) );
CLKINVX3TS U2311 ( .A(n2397), .Y(n1614) );
INVX2TS U2312 ( .A(n2386), .Y(n1615) );
CLKINVX3TS U2313 ( .A(n2384), .Y(n1616) );
CLKINVX3TS U2314 ( .A(n2386), .Y(n2398) );
CLKBUFX3TS U2315 ( .A(n3536), .Y(n1617) );
CLKINVX3TS U2316 ( .A(n2391), .Y(n2406) );
CLKINVX3TS U2317 ( .A(n2399), .Y(n1611) );
BUFX3TS U2318 ( .A(n1620), .Y(n4484) );
CLKBUFX3TS U2319 ( .A(n1619), .Y(n1634) );
CLKBUFX3TS U2320 ( .A(n3535), .Y(n1618) );
CLKBUFX3TS U2321 ( .A(n1620), .Y(n1631) );
BUFX3TS U2322 ( .A(n1620), .Y(n4483) );
CLKBUFX3TS U2323 ( .A(n4086), .Y(n4482) );
CLKBUFX3TS U2324 ( .A(n3540), .Y(n4488) );
CLKBUFX3TS U2325 ( .A(n1620), .Y(n1632) );
CLKBUFX3TS U2326 ( .A(n1619), .Y(n1630) );
CLKBUFX3TS U2327 ( .A(n3539), .Y(n1623) );
CLKBUFX3TS U2328 ( .A(n4506), .Y(n4086) );
NAND3X4TS U2329 ( .A(n3315), .B(n1550), .C(n2179), .Y(n911) );
INVX6TS U2330 ( .A(n2954), .Y(n1747) );
NAND2X4TS U2331 ( .A(n2149), .B(d_ff2_X[1]), .Y(n2204) );
INVX3TS U2332 ( .A(n2558), .Y(n2491) );
CLKBUFX3TS U2333 ( .A(n1638), .Y(n3540) );
OAI2BB1X2TS U2334 ( .A0N(d_ff2_X[51]), .A1N(n2495), .B0(n3271), .Y(n594) );
CLKINVX3TS U2335 ( .A(n2151), .Y(n2403) );
INVX4TS U2336 ( .A(n1531), .Y(n2704) );
CLKINVX3TS U2337 ( .A(n2151), .Y(n1639) );
NAND2X2TS U2338 ( .A(n2974), .B(n3632), .Y(n3040) );
NAND2X4TS U2339 ( .A(n1643), .B(n3633), .Y(n3035) );
NAND3X1TS U2340 ( .A(n3096), .B(n3095), .C(n3094), .Y(add_subt_dataA[16]) );
INVX4TS U2341 ( .A(n3513), .Y(n2094) );
NAND2X2TS U2342 ( .A(n3182), .B(d_ff2_Z[17]), .Y(n3092) );
NAND2X2TS U2343 ( .A(n3182), .B(d_ff2_Z[22]), .Y(n3077) );
INVX8TS U2344 ( .A(n3197), .Y(n1754) );
BUFX12TS U2345 ( .A(n3361), .Y(n3381) );
INVX8TS U2346 ( .A(n4583), .Y(n1647) );
BUFX8TS U2347 ( .A(n2632), .Y(n3515) );
INVX4TS U2348 ( .A(n4553), .Y(n3675) );
BUFX12TS U2349 ( .A(n3422), .Y(n3532) );
INVX4TS U2350 ( .A(n3262), .Y(n2062) );
INVX3TS U2351 ( .A(n2132), .Y(n3663) );
INVX2TS U2352 ( .A(n2337), .Y(n3756) );
INVX2TS U2353 ( .A(n3469), .Y(n3233) );
INVX4TS U2354 ( .A(n3258), .Y(n2069) );
MX2X2TS U2355 ( .A(n1831), .B(n1832), .S0(n1833), .Y(n3240) );
INVX4TS U2356 ( .A(n1729), .Y(n1728) );
INVX4TS U2357 ( .A(n3702), .Y(n2074) );
INVX4TS U2358 ( .A(n3701), .Y(n2075) );
CLKBUFX3TS U2359 ( .A(n2406), .Y(n4069) );
CLKBUFX3TS U2360 ( .A(n3537), .Y(n4078) );
CLKBUFX3TS U2361 ( .A(n3537), .Y(n4499) );
CLKBUFX3TS U2362 ( .A(n1629), .Y(n4501) );
CLKBUFX3TS U2363 ( .A(n1611), .Y(n1613) );
CLKBUFX3TS U2364 ( .A(n3537), .Y(n4494) );
CLKBUFX3TS U2365 ( .A(n4482), .Y(n1627) );
CLKBUFX3TS U2366 ( .A(n4505), .Y(n3537) );
CLKBUFX3TS U2367 ( .A(n4484), .Y(n1628) );
CLKBUFX3TS U2368 ( .A(n1620), .Y(n1626) );
CLKBUFX3TS U2369 ( .A(n3540), .Y(n4496) );
CLKBUFX3TS U2370 ( .A(n4086), .Y(n1633) );
CLKBUFX3TS U2371 ( .A(n3540), .Y(n4486) );
NAND2X4TS U2372 ( .A(n2548), .B(n2547), .Y(n800) );
NAND2X4TS U2373 ( .A(n2204), .B(n2203), .Y(n694) );
INVX6TS U2374 ( .A(n1677), .Y(n1765) );
BUFX16TS U2375 ( .A(n2618), .Y(n4471) );
NAND2X4TS U2376 ( .A(n1731), .B(n1727), .Y(n774) );
CLKBUFX3TS U2377 ( .A(n3540), .Y(n4495) );
NAND2X4TS U2378 ( .A(n2503), .B(n2501), .Y(n2525) );
CLKBUFX3TS U2379 ( .A(n3540), .Y(n4505) );
OAI21X2TS U2380 ( .A0(n2744), .A1(n2940), .B0(n2192), .Y(n1266) );
NAND2X4TS U2381 ( .A(n2571), .B(n2177), .Y(n2576) );
CLKBUFX2TS U2382 ( .A(n3540), .Y(n1619) );
CLKBUFX3TS U2383 ( .A(n4506), .Y(n1620) );
CLKBUFX3TS U2384 ( .A(n1638), .Y(n4480) );
BUFX20TS U2385 ( .A(n2618), .Y(n1621) );
CLKINVX6TS U2386 ( .A(n4475), .Y(n1622) );
NAND3X4TS U2387 ( .A(n1641), .B(n2940), .C(n1762), .Y(n2192) );
CLKBUFX3TS U2388 ( .A(n2403), .Y(n4500) );
CLKBUFX3TS U2389 ( .A(n1638), .Y(n4478) );
NAND2X6TS U2390 ( .A(n3217), .B(n3216), .Y(n1656) );
NAND2X6TS U2391 ( .A(n2561), .B(n1759), .Y(n2993) );
INVX3TS U2392 ( .A(n3718), .Y(n3226) );
INVX8TS U2393 ( .A(n2592), .Y(n1641) );
INVX2TS U2394 ( .A(n1737), .Y(n2189) );
NAND2X2TS U2395 ( .A(n3159), .B(d_ff2_Z[16]), .Y(n3095) );
INVX2TS U2396 ( .A(n3532), .Y(n1827) );
NOR2X1TS U2397 ( .A(n2351), .B(ack_cordic), .Y(n2935) );
INVX2TS U2398 ( .A(n3745), .Y(n1674) );
INVX3TS U2399 ( .A(n4555), .Y(n2113) );
CLKMX2X2TS U2400 ( .A(n4172), .B(n4171), .S0(n1997), .Y(n1995) );
NAND2X6TS U2401 ( .A(n1730), .B(n1728), .Y(n3996) );
BUFX20TS U2402 ( .A(n3338), .Y(n3359) );
INVX2TS U2403 ( .A(n3606), .Y(n4645) );
INVX4TS U2404 ( .A(n2035), .Y(n3994) );
MXI2X2TS U2405 ( .A(n1926), .B(n1927), .S0(n1997), .Y(n1993) );
INVX6TS U2406 ( .A(n3669), .Y(n4583) );
INVX3TS U2407 ( .A(n1824), .Y(n3594) );
NOR2X8TS U2408 ( .A(n1763), .B(sel_mux_2_reg_0_), .Y(n3338) );
INVX2TS U2409 ( .A(n3400), .Y(n2490) );
INVX4TS U2410 ( .A(n2116), .Y(n3666) );
INVX2TS U2411 ( .A(n2335), .Y(n3755) );
INVX4TS U2412 ( .A(n2309), .Y(n3662) );
CLKMX2X4TS U2413 ( .A(n1859), .B(n4370), .S0(n1980), .Y(n1976) );
CLKMX2X2TS U2414 ( .A(n1892), .B(n1851), .S0(n2018), .Y(n2133) );
CLKMX2X2TS U2415 ( .A(n1859), .B(n4370), .S0(n1980), .Y(n2279) );
CLKMX2X2TS U2416 ( .A(n4303), .B(n4302), .S0(n1966), .Y(n2243) );
CLKMX2X2TS U2417 ( .A(n1939), .B(n4328), .S0(n1966), .Y(n1962) );
CLKMX2X2TS U2418 ( .A(n1906), .B(n4300), .S0(n1980), .Y(n1977) );
CLKMX2X2TS U2419 ( .A(n1874), .B(n4194), .S0(n1582), .Y(n2057) );
INVX4TS U2420 ( .A(n3661), .Y(n4549) );
CLKMX2X2TS U2421 ( .A(n1909), .B(n4133), .S0(n4132), .Y(n2296) );
CLKMX2X2TS U2422 ( .A(n1904), .B(n4465), .S0(n4464), .Y(n2306) );
MX2X4TS U2423 ( .A(n4325), .B(n4324), .S0(n4323), .Y(n2253) );
INVX2TS U2424 ( .A(n4556), .Y(n1670) );
INVX4TS U2425 ( .A(n2348), .Y(n2349) );
NAND3X2TS U2426 ( .A(n4340), .B(n4339), .C(n4338), .Y(n3499) );
INVX4TS U2427 ( .A(n2317), .Y(n2318) );
INVX4TS U2428 ( .A(n1839), .Y(n1840) );
CLKBUFX3TS U2429 ( .A(n3538), .Y(n4498) );
CLKBUFX3TS U2430 ( .A(n3538), .Y(n4497) );
CLKBUFX3TS U2431 ( .A(n3538), .Y(n4076) );
CLKBUFX3TS U2432 ( .A(n3538), .Y(n4071) );
CLKBUFX3TS U2433 ( .A(n4481), .Y(n4068) );
CLKBUFX3TS U2434 ( .A(n1615), .Y(n4479) );
CLKBUFX3TS U2435 ( .A(n3537), .Y(n4493) );
CLKBUFX3TS U2436 ( .A(n3537), .Y(n4492) );
CLKBUFX3TS U2437 ( .A(n3537), .Y(n4503) );
NAND2X6TS U2438 ( .A(n1710), .B(n3686), .Y(n4611) );
CLKBUFX3TS U2439 ( .A(n4482), .Y(n4491) );
CLKBUFX3TS U2440 ( .A(n3536), .Y(n4081) );
NAND3X6TS U2441 ( .A(n1687), .B(n1686), .C(n1685), .Y(n706) );
CLKBUFX3TS U2442 ( .A(n3536), .Y(n4080) );
CLKBUFX3TS U2443 ( .A(n3536), .Y(n4072) );
CLKBUFX3TS U2444 ( .A(n3536), .Y(n4082) );
NAND2X6TS U2445 ( .A(n2216), .B(n3647), .Y(n3544) );
CLKBUFX3TS U2446 ( .A(n4506), .Y(n4485) );
CLKBUFX3TS U2447 ( .A(n3535), .Y(n4074) );
CLKBUFX3TS U2448 ( .A(n1620), .Y(n4085) );
CLKBUFX3TS U2449 ( .A(n1620), .Y(n4087) );
INVX2TS U2450 ( .A(n2391), .Y(n1629) );
CLKBUFX3TS U2451 ( .A(n3535), .Y(n4073) );
CLKBUFX3TS U2452 ( .A(n3535), .Y(n4083) );
CLKBUFX3TS U2453 ( .A(n3535), .Y(n4084) );
NAND4X4TS U2454 ( .A(n2934), .B(n3216), .C(n2933), .D(n2178), .Y(n945) );
CLKBUFX3TS U2455 ( .A(n3539), .Y(n4502) );
CLKBUFX3TS U2456 ( .A(n3540), .Y(n4487) );
CLKBUFX3TS U2457 ( .A(n3539), .Y(n4075) );
INVX6TS U2458 ( .A(n1689), .Y(n1688) );
NAND3X4TS U2459 ( .A(n2129), .B(n3474), .C(n4473), .Y(n3476) );
NAND3X2TS U2460 ( .A(n2666), .B(n2665), .C(n2664), .Y(n846) );
CLKBUFX3TS U2461 ( .A(n3539), .Y(n4079) );
NAND2X4TS U2462 ( .A(n2550), .B(n2549), .Y(n790) );
CLKBUFX3TS U2463 ( .A(n3539), .Y(n4077) );
CLKINVX6TS U2464 ( .A(n4475), .Y(n1635) );
BUFX20TS U2465 ( .A(n3254), .Y(n1636) );
CLKMX2X3TS U2466 ( .A(d_ff1_Z[27]), .B(data_in[27]), .S0(n3741), .Y(n1306)
);
NAND2X4TS U2467 ( .A(n2544), .B(n3281), .Y(n3003) );
BUFX20TS U2468 ( .A(n2524), .Y(n1637) );
INVX2TS U2469 ( .A(n2151), .Y(n1638) );
OAI21X1TS U2470 ( .A0(n4561), .A1(n3130), .B0(n3507), .Y(add_subt_dataB[31])
);
OAI21X1TS U2471 ( .A0(n4554), .A1(n3530), .B0(n3511), .Y(add_subt_dataB[28])
);
OAI21X1TS U2472 ( .A0(n4560), .A1(n3130), .B0(n3508), .Y(add_subt_dataB[30])
);
OAI21X1TS U2473 ( .A0(n4557), .A1(n3530), .B0(n3510), .Y(add_subt_dataB[29])
);
INVX16TS U2474 ( .A(n3543), .Y(n2365) );
INVX16TS U2475 ( .A(n2240), .Y(n1642) );
INVX2TS U2476 ( .A(n3587), .Y(n4666) );
BUFX20TS U2477 ( .A(n2520), .Y(n1643) );
XOR2X2TS U2478 ( .A(n2685), .B(data_output2_63_), .Y(n2688) );
INVX2TS U2479 ( .A(n3557), .Y(n4668) );
INVX2TS U2480 ( .A(n3569), .Y(n4672) );
MX2X2TS U2481 ( .A(n1891), .B(n4160), .S0(n1695), .Y(n2046) );
INVX2TS U2482 ( .A(n3580), .Y(n4690) );
INVX2TS U2483 ( .A(n3603), .Y(n4660) );
INVX12TS U2484 ( .A(n1755), .Y(n3710) );
INVX12TS U2485 ( .A(n1708), .Y(n2701) );
BUFX16TS U2486 ( .A(n2632), .Y(n3429) );
INVX6TS U2487 ( .A(n2948), .Y(n2606) );
INVX6TS U2488 ( .A(n4574), .Y(n2092) );
INVX2TS U2489 ( .A(n3573), .Y(n4658) );
INVX2TS U2490 ( .A(n3567), .Y(n4675) );
INVX2TS U2491 ( .A(n2251), .Y(n1716) );
INVX2TS U2492 ( .A(n3597), .Y(n4664) );
INVX8TS U2493 ( .A(n3130), .Y(n1645) );
INVX4TS U2494 ( .A(n2016), .Y(n3311) );
INVX6TS U2495 ( .A(n2001), .Y(n3561) );
INVX2TS U2496 ( .A(n3583), .Y(n4626) );
INVX2TS U2497 ( .A(n1965), .Y(n1715) );
INVX2TS U2498 ( .A(n3576), .Y(n4670) );
BUFX12TS U2499 ( .A(n2048), .Y(n1695) );
INVX2TS U2500 ( .A(n3593), .Y(n4700) );
NAND2X6TS U2501 ( .A(n2239), .B(n2238), .Y(n4553) );
INVX2TS U2502 ( .A(n3620), .Y(n1905) );
INVX2TS U2503 ( .A(n3279), .Y(n2032) );
INVX4TS U2504 ( .A(n3993), .Y(n2029) );
INVX2TS U2505 ( .A(n3565), .Y(n4677) );
MX2X2TS U2506 ( .A(n1870), .B(n4283), .S0(n1960), .Y(n2126) );
MX2X2TS U2507 ( .A(n4344), .B(n4343), .S0(n2043), .Y(n2040) );
MX2X2TS U2508 ( .A(n4254), .B(n4253), .S0(n2043), .Y(n2244) );
BUFX16TS U2509 ( .A(n1981), .Y(n1980) );
INVX2TS U2510 ( .A(n2089), .Y(n2090) );
INVX2TS U2511 ( .A(n1851), .Y(n1831) );
MX2X2TS U2512 ( .A(n1828), .B(n1829), .S0(n1830), .Y(n3007) );
NAND3BX2TS U2513 ( .AN(n4457), .B(n4456), .C(n4455), .Y(n3469) );
BUFX3TS U2514 ( .A(d_ff1_Z[49]), .Y(n2438) );
NOR2X4TS U2515 ( .A(cont_var_out[1]), .B(cont_var_out[0]), .Y(n2681) );
INVX2TS U2516 ( .A(n2145), .Y(n2146) );
INVX2TS U2517 ( .A(n1760), .Y(n1761) );
INVX6TS U2518 ( .A(n1762), .Y(n1763) );
BUFX16TS U2519 ( .A(n2044), .Y(n2043) );
INVX4TS U2520 ( .A(n2343), .Y(n1651) );
MX2X4TS U2521 ( .A(n1930), .B(n4119), .S0(n4118), .Y(n2173) );
NAND2X4TS U2522 ( .A(n4266), .B(n4267), .Y(n1730) );
CLKBUFX2TS U2523 ( .A(n2430), .Y(n2431) );
MX2X2TS U2524 ( .A(n1834), .B(n1835), .S0(n1836), .Y(n3570) );
INVX4TS U2525 ( .A(n2354), .Y(n1675) );
MX2X2TS U2526 ( .A(n1934), .B(n4459), .S0(n4458), .Y(n2322) );
INVX16TS U2527 ( .A(n3746), .Y(n1653) );
INVX4TS U2528 ( .A(result_add_subt[50]), .Y(n4697) );
NAND2X2TS U2529 ( .A(n2570), .B(n2578), .Y(n2802) );
OAI21X4TS U2530 ( .A0(n3219), .A1(n3218), .B0(n1654), .Y(n918) );
NAND3X6TS U2531 ( .A(n4525), .B(n3195), .C(n1550), .Y(n930) );
NAND2X8TS U2532 ( .A(n2691), .B(n1640), .Y(n4525) );
AND2X8TS U2533 ( .A(n2638), .B(n2692), .Y(n1691) );
NAND2X8TS U2534 ( .A(n2937), .B(n2638), .Y(n3208) );
NAND2X4TS U2535 ( .A(n1595), .B(d_ff2_Z[41]), .Y(n2653) );
BUFX20TS U2536 ( .A(n2520), .Y(n2544) );
BUFX20TS U2537 ( .A(n2486), .Y(n1772) );
NAND2X2TS U2538 ( .A(n1595), .B(n2275), .Y(n2657) );
NOR2X6TS U2539 ( .A(n2198), .B(n1721), .Y(n2686) );
CLKBUFX2TS U2540 ( .A(n3772), .Y(n1657) );
NAND2X8TS U2541 ( .A(n2696), .B(n3243), .Y(n1733) );
NAND3X4TS U2542 ( .A(n2535), .B(d_ff1_Z[3]), .C(n2975), .Y(n2792) );
OAI2BB1X2TS U2543 ( .A0N(n3279), .A1N(n1717), .B0(n2922), .Y(n967) );
NAND3X4TS U2544 ( .A(n3239), .B(n3238), .C(n2529), .Y(n4616) );
AOI22X2TS U2545 ( .A0(n2063), .A1(n3703), .B0(n1724), .B1(sign_inv_out[32]),
.Y(n2904) );
AOI22X2TS U2546 ( .A0(n1588), .A1(sign_inv_out[51]), .B0(n1516), .B1(n3640),
.Y(n2918) );
NOR2X8TS U2547 ( .A(n1659), .B(n3551), .Y(n3276) );
AOI22X2TS U2548 ( .A0(n3696), .A1(n3635), .B0(n2504), .B1(sign_inv_out[5]),
.Y(n2907) );
NAND3X4TS U2549 ( .A(n2927), .B(n2766), .C(n2765), .Y(n940) );
AND2X8TS U2550 ( .A(n3070), .B(n1755), .Y(n3541) );
NOR2X8TS U2551 ( .A(n2499), .B(n2692), .Y(n3070) );
MX2X4TS U2552 ( .A(n1875), .B(n4232), .S0(n4231), .Y(n3999) );
NAND2X4TS U2553 ( .A(n1676), .B(n3634), .Y(n3031) );
AO22X4TS U2554 ( .A0(n1984), .A1(n2543), .B0(n1586), .B1(d_ff2_Y[45]), .Y(
n734) );
MXI2X4TS U2555 ( .A(n2423), .B(n3950), .S0(n1644), .Y(n601) );
CLKINVX12TS U2556 ( .A(n1662), .Y(n2266) );
NAND2X8TS U2557 ( .A(n1663), .B(n1525), .Y(n1662) );
NAND2X4TS U2558 ( .A(n3548), .B(n4601), .Y(n4603) );
INVX12TS U2559 ( .A(n2287), .Y(n2294) );
OAI2BB1X4TS U2560 ( .A0N(n2901), .A1N(n3281), .B0(n2906), .Y(n1013) );
OAI21X4TS U2561 ( .A0(n1530), .A1(n3479), .B0(n3478), .Y(n4595) );
AOI22X2TS U2562 ( .A0(n1515), .A1(n3258), .B0(n1724), .B1(sign_inv_out[8]),
.Y(n2908) );
OAI2BB1X4TS U2563 ( .A0N(d_ff2_Y[26]), .A1N(n1580), .B0(n3006), .Y(n772) );
NAND2X4TS U2564 ( .A(n2511), .B(n3574), .Y(n2540) );
AOI22X2TS U2565 ( .A0(n2504), .A1(sign_inv_out[52]), .B0(n3691), .B1(n3749),
.Y(n2917) );
AOI22X2TS U2566 ( .A0(n1588), .A1(sign_inv_out[50]), .B0(n3696), .B1(n3620),
.Y(n2920) );
AOI22X4TS U2567 ( .A0(n2606), .A1(n1663), .B0(n3772), .B1(n2692), .Y(n2605)
);
NAND2X8TS U2568 ( .A(d_ff2_X[55]), .B(n1734), .Y(n1663) );
BUFX16TS U2569 ( .A(n2522), .Y(n3047) );
BUFX12TS U2570 ( .A(n3551), .Y(n1665) );
NAND3X4TS U2571 ( .A(n3199), .B(n4563), .C(n3198), .Y(n942) );
NAND2X2TS U2572 ( .A(n2511), .B(n3616), .Y(n2713) );
NOR2BX4TS U2573 ( .AN(n2569), .B(n2139), .Y(n1666) );
NAND2X4TS U2574 ( .A(n2383), .B(n3290), .Y(n3291) );
NAND2X8TS U2575 ( .A(n3197), .B(n3190), .Y(n1736) );
NAND3X8TS U2576 ( .A(n2930), .B(n2361), .C(n2763), .Y(n2764) );
BUFX6TS U2577 ( .A(n3710), .Y(n1668) );
NAND2X1TS U2578 ( .A(n3639), .B(n2520), .Y(n3043) );
OAI22X4TS U2579 ( .A0(n2535), .A1(n2161), .B0(n2342), .B1(n2524), .Y(n2523)
);
BUFX20TS U2580 ( .A(n2974), .Y(n2573) );
AND2X8TS U2581 ( .A(n2224), .B(n3710), .Y(n3313) );
OAI2BB1X4TS U2582 ( .A0N(d_ff2_X[23]), .A1N(n1580), .B0(n3028), .Y(n650) );
OAI2BB1X4TS U2583 ( .A0N(d_ff2_X[25]), .A1N(n1580), .B0(n3036), .Y(n646) );
NAND2X4TS U2584 ( .A(n2544), .B(n3284), .Y(n3000) );
CLKINVX12TS U2585 ( .A(n1694), .Y(n2175) );
NAND2X2TS U2586 ( .A(n2974), .B(n3598), .Y(n2881) );
NAND2BX4TS U2587 ( .AN(n1637), .B(n3627), .Y(n3318) );
NAND2BX4TS U2588 ( .AN(n1637), .B(n2957), .Y(n2767) );
NAND2BX4TS U2589 ( .AN(n1637), .B(n3280), .Y(n3023) );
AOI2BB2X4TS U2590 ( .B0(n1671), .B1(n4555), .A0N(n1670), .A1N(n1704), .Y(
n638) );
AOI22X4TS U2591 ( .A0(n4549), .A1(n1671), .B0(n3902), .B1(n1584), .Y(n644)
);
OAI21X4TS U2592 ( .A0(n1878), .A1(n4426), .B0(n1672), .Y(n3637) );
NAND2BX4TS U2593 ( .AN(n4427), .B(n4426), .Y(n1672) );
AOI21X1TS U2594 ( .A0(n2141), .A1(n2587), .B0(n1674), .Y(n3748) );
NAND2X8TS U2595 ( .A(n1675), .B(n1653), .Y(n3745) );
NAND2BX4TS U2596 ( .AN(n1678), .B(n3564), .Y(n2663) );
NAND2X8TS U2597 ( .A(n2225), .B(n3191), .Y(n2226) );
NAND3X8TS U2598 ( .A(n1683), .B(n1681), .C(n1682), .Y(n1689) );
AOI2BB2X4TS U2599 ( .B0(n2222), .B1(n2142), .A0N(n1649), .A1N(n1679), .Y(
n1682) );
NAND2X6TS U2600 ( .A(n2223), .B(n2142), .Y(n1683) );
NAND2X8TS U2601 ( .A(n1688), .B(n1684), .Y(n1687) );
INVX16TS U2602 ( .A(n1690), .Y(n2138) );
NAND2X8TS U2603 ( .A(n2637), .B(n1691), .Y(n1690) );
NOR2X4TS U2604 ( .A(n3718), .B(n1692), .Y(n2791) );
NAND2X8TS U2605 ( .A(n3711), .B(n1692), .Y(n2927) );
NOR2X4TS U2606 ( .A(n2531), .B(n1692), .Y(n2607) );
NOR2X4TS U2607 ( .A(n3224), .B(n1531), .Y(n3225) );
BUFX20TS U2608 ( .A(n2378), .Y(n1693) );
AOI21X4TS U2609 ( .A0(n3229), .A1(n3255), .B0(n3731), .Y(n1340) );
NOR2X6TS U2610 ( .A(n3892), .B(n3227), .Y(n1694) );
INVX16TS U2611 ( .A(n3894), .Y(n2633) );
BUFX20TS U2612 ( .A(n3689), .Y(n2496) );
OAI2BB1X4TS U2613 ( .A0N(n1635), .A1N(n1963), .B0(n2888), .Y(n1025) );
INVX16TS U2614 ( .A(n2789), .Y(n3191) );
NOR2X8TS U2615 ( .A(n2763), .B(n1667), .Y(n2373) );
NAND3X8TS U2616 ( .A(n1698), .B(n1649), .C(n1699), .Y(n1697) );
NAND2X8TS U2617 ( .A(n2364), .B(n2372), .Y(n1699) );
INVX16TS U2618 ( .A(n2225), .Y(n3705) );
INVX16TS U2619 ( .A(n2350), .Y(n2351) );
NAND2X4TS U2620 ( .A(n1961), .B(n3724), .Y(n2997) );
NAND2X4TS U2621 ( .A(n1593), .B(n3588), .Y(n2816) );
MX2X4TS U2622 ( .A(d_ff1_Z[5]), .B(data_in[5]), .S0(n3738), .Y(n1328) );
MX2X4TS U2623 ( .A(d_ff1_Z[23]), .B(data_in[23]), .S0(n3738), .Y(n1310) );
AOI21X4TS U2624 ( .A0(n2248), .A1(n2123), .B0(n2629), .Y(n3232) );
INVX16TS U2625 ( .A(n2225), .Y(n2229) );
NAND2X8TS U2626 ( .A(n1703), .B(n1693), .Y(n3648) );
NOR3X8TS U2627 ( .A(n3714), .B(n3208), .C(n3910), .Y(n3250) );
NAND2X2TS U2628 ( .A(n2201), .B(n3287), .Y(n3016) );
OAI2BB1X4TS U2629 ( .A0N(d_ff2_Y[3]), .A1N(n3044), .B0(n3016), .Y(n818) );
NAND2X4TS U2630 ( .A(n3724), .B(n3589), .Y(n2804) );
OAI2BB1X4TS U2631 ( .A0N(n1718), .A1N(n2125), .B0(n3066), .Y(n1043) );
INVX16TS U2632 ( .A(n4476), .Y(n2924) );
INVX16TS U2633 ( .A(n3543), .Y(n3551) );
NAND2X8TS U2634 ( .A(n2616), .B(n2617), .Y(n2612) );
NAND3X4TS U2635 ( .A(n2853), .B(n2851), .C(n2852), .Y(n875) );
NAND2X4TS U2636 ( .A(n2546), .B(n3063), .Y(n3015) );
INVX16TS U2637 ( .A(n2526), .Y(n3046) );
INVX12TS U2638 ( .A(n2286), .Y(n2288) );
NAND3X2TS U2639 ( .A(n2742), .B(n2740), .C(n2741), .Y(n856) );
NAND2X2TS U2640 ( .A(n2573), .B(n3582), .Y(n2660) );
NAND2X8TS U2641 ( .A(n2951), .B(n2247), .Y(n2372) );
OAI2BB1X4TS U2642 ( .A0N(n2544), .A1N(n3619), .B0(n1705), .Y(n766) );
NAND2X6TS U2643 ( .A(n3272), .B(n2930), .Y(n3274) );
OAI2BB1X4TS U2644 ( .A0N(d_ff2_X[22]), .A1N(n1580), .B0(n3031), .Y(n652) );
OAI2BB1X4TS U2645 ( .A0N(d_ff2_Y[51]), .A1N(n2495), .B0(n3270), .Y(n722) );
OAI21X4TS U2646 ( .A0(n4518), .A1(n3201), .B0(n3200), .Y(n939) );
NOR2X6TS U2647 ( .A(n2987), .B(n3274), .Y(n4518) );
NAND2X4TS U2648 ( .A(n2225), .B(n2255), .Y(n3236) );
BUFX6TS U2649 ( .A(n1953), .Y(n1706) );
BUFX6TS U2650 ( .A(n3071), .Y(n1707) );
NOR2X8TS U2651 ( .A(n3227), .B(n2369), .Y(n1708) );
INVX16TS U2652 ( .A(n3549), .Y(n3707) );
NAND2X8TS U2653 ( .A(n2702), .B(n2701), .Y(n3319) );
NAND2X8TS U2654 ( .A(n3745), .B(n2639), .Y(n2702) );
NAND2X2TS U2655 ( .A(n3047), .B(n3608), .Y(n2654) );
OAI2BB1X4TS U2656 ( .A0N(d_ff2_Y[38]), .A1N(n3303), .B0(n2999), .Y(n748) );
OAI21X4TS U2657 ( .A0(n1514), .A1(n2346), .B0(n2891), .Y(n1017) );
INVX12TS U2658 ( .A(n2572), .Y(n2560) );
AOI22X4TS U2659 ( .A0(n3698), .A1(n3638), .B0(n2409), .B1(sign_inv_out[40]),
.Y(n3204) );
OAI21X4TS U2660 ( .A0(n1514), .A1(n2313), .B0(n3204), .Y(n993) );
AOI2BB2X4TS U2661 ( .B0(n2555), .B1(n2704), .A0N(n2613), .A1N(
d_ff3_LUT_out[13]), .Y(n932) );
NAND3X2TS U2662 ( .A(n2841), .B(n2840), .C(n2842), .Y(n864) );
MXI2X4TS U2663 ( .A(n3934), .B(n3789), .S0(n2613), .Y(n771) );
MXI2X4TS U2664 ( .A(n3973), .B(n3823), .S0(n2613), .Y(n759) );
NOR2X8TS U2665 ( .A(n2697), .B(n2257), .Y(n2698) );
NAND2X8TS U2666 ( .A(n1732), .B(cordic_FSM_state_reg_3_), .Y(n2697) );
NOR2X4TS U2667 ( .A(n3209), .B(n1519), .Y(n1342) );
OAI2BB1X4TS U2668 ( .A0N(d_ff2_Y[44]), .A1N(n3744), .B0(n3300), .Y(n736) );
INVX4TS U2669 ( .A(n2979), .Y(n2980) );
OAI2BB1X4TS U2670 ( .A0N(n3288), .A1N(n1717), .B0(n2915), .Y(n1069) );
OAI2BB1X4TS U2671 ( .A0N(d_ff2_Y[24]), .A1N(n1580), .B0(n2996), .Y(n776) );
AND2X8TS U2672 ( .A(n2229), .B(d_ff3_LUT_out[7]), .Y(n1711) );
AOI22X2TS U2673 ( .A0(n3691), .A1(n3629), .B0(sign_inv_out[37]), .B1(n1543),
.Y(n2899) );
OAI2BB1X4TS U2674 ( .A0N(n3290), .A1N(n1718), .B0(n2899), .Y(n999) );
NAND2BX4TS U2675 ( .AN(n1712), .B(n2660), .Y(n845) );
OAI2BB1X2TS U2676 ( .A0N(n2274), .A1N(n3744), .B0(n2659), .Y(n1712) );
BUFX16TS U2677 ( .A(n2714), .Y(n2849) );
OAI21X4TS U2678 ( .A0(n2215), .A1(d_ff3_LUT_out[3]), .B0(n3196), .Y(n3199)
);
NOR2X8TS U2679 ( .A(n1759), .B(n1667), .Y(n3228) );
INVX16TS U2680 ( .A(n2380), .Y(n2381) );
AOI22X4TS U2681 ( .A0(n3696), .A1(n2073), .B0(sign_inv_out[38]), .B1(n2557),
.Y(n3057) );
OAI21X4TS U2682 ( .A0(n1514), .A1(n3998), .B0(n3057), .Y(n997) );
NAND3X4TS U2683 ( .A(n2816), .B(n2814), .C(n2815), .Y(n873) );
NAND3X8TS U2684 ( .A(n2528), .B(n2175), .C(n2266), .Y(n2527) );
OAI2BB1X4TS U2685 ( .A0N(n3680), .A1N(n2924), .B0(n2923), .Y(n961) );
BUFX20TS U2686 ( .A(n2539), .Y(n2533) );
OAI21X4TS U2687 ( .A0(n4473), .A1(n2849), .B0(n3681), .Y(n716) );
AOI22X4TS U2688 ( .A0(n2309), .A1(n3724), .B0(n3901), .B1(n1595), .Y(n648)
);
INVX16TS U2689 ( .A(n2235), .Y(n2878) );
CLKBUFX2TS U2690 ( .A(d_ff2_X[55]), .Y(n1714) );
MXI2X4TS U2691 ( .A(n3899), .B(n4537), .S0(n3252), .Y(n657) );
OAI2BB1X4TS U2692 ( .A0N(d_ff2_Y[5]), .A1N(n3044), .B0(n3012), .Y(n814) );
OAI2BB1X4TS U2693 ( .A0N(n3284), .A1N(n2901), .B0(n2909), .Y(n1071) );
AOI22X2TS U2694 ( .A0(n3621), .A1(n3698), .B0(n1543), .B1(sign_inv_out[47]),
.Y(n3220) );
OAI21X4TS U2695 ( .A0(n1514), .A1(n1979), .B0(n2508), .Y(n991) );
MXI2X4TS U2696 ( .A(n1919), .B(n4170), .S0(n2049), .Y(n3615) );
MXI2X4TS U2697 ( .A(n3771), .B(n3891), .S0(n3252), .Y(n781) );
BUFX20TS U2698 ( .A(n2955), .Y(n4475) );
OAI2BB1X4TS U2699 ( .A0N(n1622), .A1N(n1715), .B0(n2895), .Y(n1029) );
OAI2BB1X4TS U2700 ( .A0N(n1622), .A1N(n1651), .B0(n2897), .Y(n1033) );
INVX16TS U2701 ( .A(n4475), .Y(n1717) );
OAI2BB1X4TS U2702 ( .A0N(n1717), .A1N(n1716), .B0(n2896), .Y(n1031) );
INVX16TS U2703 ( .A(n4475), .Y(n1718) );
OAI2BB1X4TS U2704 ( .A0N(n1718), .A1N(n1652), .B0(n2894), .Y(n1027) );
CLKINVX12TS U2705 ( .A(n2381), .Y(n1720) );
OAI2BB1X4TS U2706 ( .A0N(n3024), .A1N(n1718), .B0(n2890), .Y(n1045) );
OAI2BB1X4TS U2707 ( .A0N(n3058), .A1N(n1718), .B0(n3059), .Y(n1047) );
OAI2BB1X4TS U2708 ( .A0N(n2588), .A1N(n3063), .B0(n3064), .Y(n1037) );
NOR2X4TS U2709 ( .A(n2410), .B(d_ff3_LUT_out[27]), .Y(n3218) );
NAND2X2TS U2710 ( .A(n2539), .B(n3585), .Y(n2877) );
MXI2X4TS U2711 ( .A(n2405), .B(n3936), .S0(n3736), .Y(n2187) );
NAND2X8TS U2712 ( .A(n3684), .B(n2774), .Y(n2932) );
MXI2X4TS U2713 ( .A(n3327), .B(n1604), .S0(n3747), .Y(n579) );
BUFX20TS U2714 ( .A(n2316), .Y(n2224) );
AOI2BB2X4TS U2715 ( .B0(n1516), .B1(n3622), .A0N(n3852), .A1N(n2408), .Y(
n3065) );
OAI21X4TS U2716 ( .A0(n3994), .A1(n1514), .B0(n3065), .Y(n1041) );
NAND3BX4TS U2717 ( .AN(n2634), .B(n1486), .C(n1535), .Y(n2635) );
INVX16TS U2718 ( .A(n1720), .Y(n1721) );
NOR2X8TS U2719 ( .A(n2381), .B(cordic_FSM_state_reg_3_), .Y(n2236) );
OAI2BB1X4TS U2720 ( .A0N(n3245), .A1N(n3246), .B0(n1722), .Y(n1345) );
BUFX20TS U2721 ( .A(n1642), .Y(n1724) );
NAND2X8TS U2722 ( .A(n1725), .B(n2257), .Y(n2955) );
OAI2BB1X4TS U2723 ( .A0N(n1717), .A1N(n1564), .B0(n3062), .Y(n1039) );
OAI21X4TS U2724 ( .A0(n1874), .A1(n4397), .B0(n1726), .Y(n3634) );
NAND2BX4TS U2725 ( .AN(n4398), .B(n4397), .Y(n1726) );
NOR2BX4TS U2726 ( .AN(n4268), .B(n4266), .Y(n1729) );
NAND3X8TS U2727 ( .A(n2213), .B(n1732), .C(n2310), .Y(n2217) );
NOR2X1TS U2728 ( .A(n1524), .B(n2381), .Y(n2743) );
INVX16TS U2729 ( .A(n2256), .Y(n1732) );
OAI2BB1X4TS U2730 ( .A0N(n1635), .A1N(n1646), .B0(n2887), .Y(n1023) );
MXI2X4TS U2731 ( .A(n4141), .B(n4140), .S0(n4139), .Y(n3259) );
OAI2BB1X4TS U2732 ( .A0N(n3285), .A1N(n2911), .B0(n2910), .Y(n1059) );
BUFX20TS U2733 ( .A(n2537), .Y(n2536) );
BUFX16TS U2734 ( .A(n2217), .Y(n2190) );
OAI2BB1X4TS U2735 ( .A0N(n2588), .A1N(n2029), .B0(n2889), .Y(n1049) );
MXI2X4TS U2736 ( .A(n4180), .B(n4179), .S0(n4178), .Y(n3608) );
MXI2X4TS U2737 ( .A(n4425), .B(n4424), .S0(n4423), .Y(n3566) );
INVX4TS U2738 ( .A(n3259), .Y(n2061) );
NAND2X2TS U2739 ( .A(n2520), .B(n3584), .Y(n2810) );
NAND2X4TS U2740 ( .A(n3278), .B(n2202), .Y(n3213) );
NAND2X2TS U2741 ( .A(n3047), .B(n3568), .Y(n2720) );
NAND2X8TS U2742 ( .A(n1734), .B(n2951), .Y(n1764) );
NAND2BX4TS U2743 ( .AN(n3273), .B(n2986), .Y(n2987) );
NOR2X4TS U2744 ( .A(n1653), .B(n2789), .Y(n2761) );
NOR2X8TS U2745 ( .A(n3227), .B(n1653), .Y(n3197) );
OAI2BB1X4TS U2746 ( .A0N(n1738), .A1N(n2911), .B0(n2916), .Y(n1065) );
AOI21X4TS U2747 ( .A0(n2026), .A1(n4341), .B0(n1739), .Y(n1738) );
NOR2X8TS U2748 ( .A(n1746), .B(n1745), .Y(n1744) );
NOR2X8TS U2749 ( .A(n2953), .B(n1747), .Y(n1746) );
INVX2TS U2750 ( .A(n2131), .Y(n1750) );
OR2X8TS U2751 ( .A(n3326), .B(n1752), .Y(n1751) );
NAND2X4TS U2752 ( .A(n2948), .B(n1714), .Y(n1752) );
NAND2X2TS U2753 ( .A(n3710), .B(n3191), .Y(n1756) );
NOR2X8TS U2754 ( .A(n1758), .B(n1757), .Y(n3708) );
MXI2X4TS U2755 ( .A(n1901), .B(n4162), .S0(n2059), .Y(n3603) );
AND2X4TS U2756 ( .A(n2495), .B(d_ff2_Z[10]), .Y(n1766) );
NAND2X2TS U2757 ( .A(n3047), .B(n3583), .Y(n2969) );
NAND2X8TS U2758 ( .A(n1721), .B(n2198), .Y(n2231) );
CLKBUFX3TS U2759 ( .A(n1638), .Y(n1769) );
CLKBUFX3TS U2760 ( .A(n1641), .Y(n1770) );
CLKBUFX3TS U2761 ( .A(n1638), .Y(n1771) );
CLKBUFX3TS U2762 ( .A(n1638), .Y(n1773) );
CLKBUFX3TS U2763 ( .A(n1639), .Y(n1774) );
CLKBUFX3TS U2764 ( .A(n4506), .Y(n1775) );
CLKBUFX3TS U2765 ( .A(n3540), .Y(n1776) );
CLKBUFX3TS U2766 ( .A(n4506), .Y(n1777) );
CLKBUFX3TS U2767 ( .A(n3540), .Y(n1778) );
CLKBUFX3TS U2768 ( .A(n3540), .Y(n1779) );
CLKBUFX3TS U2769 ( .A(n1623), .Y(n1780) );
CLKBUFX3TS U2770 ( .A(n1631), .Y(n1781) );
CLKBUFX3TS U2771 ( .A(n1623), .Y(n1782) );
CLKBUFX3TS U2772 ( .A(n1632), .Y(n1783) );
CLKBUFX3TS U2773 ( .A(n4500), .Y(n1784) );
CLKBUFX3TS U2774 ( .A(n1634), .Y(n1785) );
CLKBUFX3TS U2775 ( .A(n1633), .Y(n1786) );
CLKBUFX3TS U2776 ( .A(n4495), .Y(n1787) );
CLKBUFX3TS U2777 ( .A(n4505), .Y(n1788) );
CLKBUFX3TS U2778 ( .A(n1630), .Y(n1789) );
CLKBUFX3TS U2779 ( .A(n4483), .Y(n1790) );
CLKBUFX3TS U2780 ( .A(n1627), .Y(n1791) );
CLKBUFX3TS U2781 ( .A(n3536), .Y(n1792) );
CLKBUFX3TS U2782 ( .A(n1629), .Y(n1793) );
CLKBUFX3TS U2783 ( .A(n1629), .Y(n1794) );
CLKBUFX3TS U2784 ( .A(n1628), .Y(n1795) );
CLKBUFX3TS U2785 ( .A(n1626), .Y(n1796) );
CLKBUFX3TS U2786 ( .A(n1618), .Y(n1797) );
CLKBUFX3TS U2787 ( .A(n1618), .Y(n1798) );
CLKBUFX3TS U2788 ( .A(n1614), .Y(n1799) );
CLKBUFX3TS U2789 ( .A(n3537), .Y(n1800) );
CLKBUFX3TS U2790 ( .A(n1616), .Y(n1801) );
CLKBUFX3TS U2791 ( .A(n1616), .Y(n1802) );
CLKBUFX3TS U2792 ( .A(n1614), .Y(n1803) );
CLKBUFX3TS U2793 ( .A(n1611), .Y(n1804) );
CLKBUFX3TS U2794 ( .A(n1617), .Y(n1805) );
CLKBUFX3TS U2795 ( .A(n1617), .Y(n1806) );
CLKBUFX3TS U2796 ( .A(n1615), .Y(n1807) );
CLKBUFX3TS U2797 ( .A(n1629), .Y(n1808) );
CLKBUFX3TS U2798 ( .A(n2406), .Y(n1809) );
CLKBUFX3TS U2799 ( .A(n3537), .Y(n1810) );
CLKBUFX3TS U2800 ( .A(n1615), .Y(n1811) );
CLKBUFX3TS U2801 ( .A(n3537), .Y(n1812) );
CLKBUFX3TS U2802 ( .A(n2487), .Y(n1813) );
CLKBUFX3TS U2803 ( .A(n2390), .Y(n1814) );
CLKBUFX3TS U2804 ( .A(n1625), .Y(n1815) );
CLKBUFX3TS U2805 ( .A(n2398), .Y(n1816) );
CLKBUFX3TS U2806 ( .A(n1613), .Y(n1817) );
CLKBUFX3TS U2807 ( .A(n1624), .Y(n1818) );
CLKBUFX3TS U2808 ( .A(n4494), .Y(n1819) );
CLKBUFX3TS U2809 ( .A(n3538), .Y(n1820) );
CLKBUFX3TS U2810 ( .A(n4481), .Y(n1821) );
CLKBUFX3TS U2811 ( .A(n1612), .Y(n1822) );
CLKBUFX3TS U2812 ( .A(n1612), .Y(n1823) );
CLKBUFX2TS U2813 ( .A(n2403), .Y(n3539) );
CLKBUFX2TS U2814 ( .A(n3539), .Y(n3535) );
INVX2TS U2815 ( .A(n2391), .Y(n2392) );
INVX2TS U2816 ( .A(n2391), .Y(n2395) );
INVX2TS U2817 ( .A(n2384), .Y(n2396) );
INVX2TS U2818 ( .A(n2386), .Y(n2387) );
INVX2TS U2819 ( .A(n2386), .Y(n2394) );
CLKBUFX2TS U2820 ( .A(n4490), .Y(n3538) );
OAI21X2TS U2821 ( .A0(n2628), .A1(n3530), .B0(n3343), .Y(add_subt_dataA[60])
);
INVX12TS U2822 ( .A(n2609), .Y(n3554) );
NAND2X4TS U2823 ( .A(n2619), .B(n2311), .Y(n3399) );
NAND2X6TS U2824 ( .A(n3330), .B(n2619), .Y(n4609) );
NAND3X2TS U2825 ( .A(n2591), .B(n2324), .C(n1494), .Y(n3398) );
MXI2X4TS U2826 ( .A(n1825), .B(n1826), .S0(n4373), .Y(n1824) );
AOI2BB2X2TS U2827 ( .B0(d_ff3_LUT_out[6]), .B1(n3182), .A0N(n1827), .A1N(
n3958), .Y(n3366) );
MX2X4TS U2828 ( .A(n1842), .B(n1843), .S0(n1844), .Y(n3562) );
MXI2X4TS U2829 ( .A(n1846), .B(n1847), .S0(n4169), .Y(n1845) );
MXI2X4TS U2830 ( .A(n4188), .B(n4187), .S0(n1852), .Y(n3595) );
MXI2X2TS U2831 ( .A(n1857), .B(n4439), .S0(n4438), .Y(n3690) );
MXI2X4TS U2832 ( .A(n1866), .B(n4380), .S0(n4379), .Y(n3321) );
MXI2X4TS U2833 ( .A(n1866), .B(n4463), .S0(n4462), .Y(n3655) );
CLKMX2X4TS U2834 ( .A(n1868), .B(n4214), .S0(n4213), .Y(n2170) );
MXI2X4TS U2835 ( .A(n1872), .B(n4353), .S0(n4352), .Y(n3678) );
MXI2X2TS U2836 ( .A(n1877), .B(n4429), .S0(n4428), .Y(n3676) );
MXI2X4TS U2837 ( .A(n1883), .B(n4330), .S0(n4329), .Y(n3588) );
MX2X4TS U2838 ( .A(n1886), .B(n4244), .S0(n1960), .Y(n4000) );
MXI2X4TS U2839 ( .A(n1888), .B(n4103), .S0(n4102), .Y(n3202) );
MXI2X4TS U2840 ( .A(n1890), .B(n4313), .S0(n4312), .Y(n3702) );
MXI2X4TS U2841 ( .A(n1891), .B(n4418), .S0(n4417), .Y(n3701) );
CLKMX2X4TS U2842 ( .A(n1900), .B(n4223), .S0(n4222), .Y(n2171) );
MXI2X4TS U2843 ( .A(n1902), .B(n4109), .S0(n4108), .Y(n3258) );
MX2X4TS U2844 ( .A(n4336), .B(n4335), .S0(n1974), .Y(n1970) );
MXI2X4TS U2845 ( .A(n1906), .B(n4105), .S0(n4104), .Y(n3668) );
MXI2X2TS U2846 ( .A(n1907), .B(n4205), .S0(n2012), .Y(n3558) );
MXI2X4TS U2847 ( .A(n1907), .B(n4143), .S0(n4142), .Y(n3262) );
MXI2X4TS U2848 ( .A(n1914), .B(n4351), .S0(n4350), .Y(n3660) );
MXI2X2TS U2849 ( .A(n1915), .B(n4193), .S0(n4192), .Y(n3590) );
MXI2X2TS U2850 ( .A(n1916), .B(n4225), .S0(n2012), .Y(n3571) );
CLKMX2X4TS U2851 ( .A(n1917), .B(n4299), .S0(n4298), .Y(n2321) );
MXI2X2TS U2852 ( .A(n4212), .B(n4211), .S0(n4210), .Y(n3581) );
INVX2TS U2853 ( .A(n3581), .Y(n1923) );
MX2X4TS U2854 ( .A(n1973), .B(n1926), .S0(n1925), .Y(n3301) );
MXI2X4TS U2855 ( .A(n4307), .B(n4306), .S0(n2012), .Y(n3572) );
MX2X4TS U2856 ( .A(n4307), .B(n4306), .S0(n2012), .Y(n2008) );
INVX2TS U2857 ( .A(n3680), .Y(n1931) );
MXI2X4TS U2858 ( .A(n4257), .B(n4256), .S0(n4255), .Y(n3680) );
MXI2X4TS U2859 ( .A(n1932), .B(n4113), .S0(n4112), .Y(n3677) );
MX2X4TS U2860 ( .A(n1936), .B(n4431), .S0(n4430), .Y(n2297) );
MX2X4TS U2861 ( .A(n1936), .B(n4236), .S0(n4235), .Y(n3998) );
MXI2X4TS U2862 ( .A(n1942), .B(n1943), .S0(n1960), .Y(n1958) );
MXI2X4TS U2863 ( .A(n1946), .B(n4107), .S0(n4106), .Y(n3679) );
MX2X4TS U2864 ( .A(n4275), .B(n4274), .S0(n1706), .Y(n1947) );
MX2X4TS U2865 ( .A(n4287), .B(n4286), .S0(n1706), .Y(n1948) );
MX2X4TS U2866 ( .A(n4346), .B(n4345), .S0(n1706), .Y(n1951) );
MXI2X4TS U2867 ( .A(n1869), .B(n1955), .S0(n1960), .Y(n1954) );
MXI2X4TS U2868 ( .A(n1761), .B(n4244), .S0(n1960), .Y(n1956) );
MX2X4TS U2869 ( .A(n1918), .B(n4327), .S0(n4326), .Y(n2096) );
MXI2X2TS U2870 ( .A(n1876), .B(n4271), .S0(n4270), .Y(n3221) );
MX2X4TS U2871 ( .A(n1876), .B(n4271), .S0(n4270), .Y(n2134) );
MXI2X2TS U2872 ( .A(n1857), .B(n1849), .S0(n4249), .Y(n3241) );
MX2X4TS U2873 ( .A(n1857), .B(n1849), .S0(n4249), .Y(n2088) );
INVX2TS U2874 ( .A(n3992), .Y(n1961) );
MXI2X4TS U2875 ( .A(n4246), .B(n4245), .S0(n1966), .Y(n1963) );
MXI2X4TS U2876 ( .A(n4303), .B(n4302), .S0(n1966), .Y(n1964) );
MX2X4TS U2877 ( .A(n4289), .B(n4288), .S0(n1966), .Y(n1965) );
BUFX16TS U2878 ( .A(n1967), .Y(n1966) );
MXI2X4TS U2879 ( .A(n1912), .B(n1969), .S0(n1974), .Y(n1968) );
MXI2X4TS U2880 ( .A(n1910), .B(n1972), .S0(n1974), .Y(n1971) );
NAND2X4TS U2881 ( .A(n3724), .B(n3301), .Y(n3302) );
OAI2BB1X4TS U2882 ( .A0N(n3301), .A1N(n2901), .B0(n2900), .Y(n1001) );
MXI2X4TS U2883 ( .A(n1929), .B(n1973), .S0(n1974), .Y(n2302) );
INVX2TS U2884 ( .A(n3997), .Y(n1982) );
INVX2TS U2885 ( .A(n3277), .Y(n1983) );
INVX2TS U2886 ( .A(n3999), .Y(n1984) );
MXI2X4TS U2887 ( .A(n4166), .B(n4165), .S0(n1987), .Y(n3614) );
MX2X4TS U2888 ( .A(n4200), .B(n4199), .S0(n1987), .Y(n1985) );
NAND2X2TS U2889 ( .A(n2573), .B(n3580), .Y(n2670) );
MXI2X4TS U2890 ( .A(n4364), .B(n4363), .S0(n1987), .Y(n3580) );
INVX3TS U2891 ( .A(n3602), .Y(n4641) );
NAND2X2TS U2892 ( .A(n2539), .B(n3602), .Y(n2807) );
MXI2X4TS U2893 ( .A(n1861), .B(n4374), .S0(n1987), .Y(n3602) );
MXI2X4TS U2894 ( .A(n1917), .B(n4299), .S0(n4298), .Y(n2119) );
MXI2X4TS U2895 ( .A(n1885), .B(n4372), .S0(n4371), .Y(n3654) );
INVX2TS U2896 ( .A(n3641), .Y(n1988) );
MXI2X4TS U2897 ( .A(n1919), .B(n4117), .S0(n4116), .Y(n3641) );
INVX2TS U2898 ( .A(n3679), .Y(n1989) );
MXI2X2TS U2899 ( .A(n4203), .B(n4202), .S0(n4201), .Y(n3585) );
INVX2TS U2900 ( .A(n3575), .Y(n1990) );
MXI2X2TS U2901 ( .A(n4221), .B(n4220), .S0(n4219), .Y(n3575) );
INVX2TS U2902 ( .A(n3590), .Y(n1991) );
INVX2TS U2903 ( .A(n3585), .Y(n1992) );
MX2X4TS U2904 ( .A(n1878), .B(n4185), .S0(n1997), .Y(n1994) );
CLKINVX12TS U2905 ( .A(n1998), .Y(n1996) );
MXI2X4TS U2906 ( .A(n1917), .B(n4207), .S0(n1997), .Y(n3557) );
INVX2TS U2907 ( .A(n3605), .Y(n4662) );
MXI2X2TS U2908 ( .A(n1896), .B(n4217), .S0(n4216), .Y(n3578) );
INVX2TS U2909 ( .A(n3578), .Y(n4651) );
MXI2X4TS U2910 ( .A(n1936), .B(n4422), .S0(n4421), .Y(n3565) );
MX2X4TS U2911 ( .A(n4155), .B(n4154), .S0(n2005), .Y(n1999) );
MX2X4TS U2912 ( .A(n1880), .B(n4224), .S0(n2005), .Y(n2000) );
MXI2X4TS U2913 ( .A(n2002), .B(n2003), .S0(n2005), .Y(n2001) );
MX2X4TS U2914 ( .A(n4305), .B(n4304), .S0(n2005), .Y(n2004) );
NAND2X2TS U2915 ( .A(n2533), .B(n3593), .Y(n2710) );
MXI2X4TS U2916 ( .A(n4190), .B(n4189), .S0(n2005), .Y(n3593) );
BUFX16TS U2917 ( .A(n2006), .Y(n2005) );
MXI2X4TS U2918 ( .A(n1880), .B(n4224), .S0(n2005), .Y(n3584) );
MXI2X4TS U2919 ( .A(n4155), .B(n4154), .S0(n2005), .Y(n3609) );
MX2X4TS U2920 ( .A(n1907), .B(n4205), .S0(n2012), .Y(n2007) );
MX2X4TS U2921 ( .A(n1916), .B(n4225), .S0(n2012), .Y(n2009) );
NAND2X2TS U2922 ( .A(n1594), .B(n3597), .Y(n2723) );
MXI2X4TS U2923 ( .A(n1877), .B(n4186), .S0(n2012), .Y(n3597) );
NAND2X1TS U2924 ( .A(n3047), .B(n3610), .Y(n2680) );
INVX2TS U2925 ( .A(n3610), .Y(n4708) );
INVX2TS U2926 ( .A(n3559), .Y(n2013) );
MXI2X2TS U2927 ( .A(n4198), .B(n4197), .S0(n4196), .Y(n3559) );
MXI2X2TS U2928 ( .A(n4158), .B(n4157), .S0(n4156), .Y(n3612) );
INVX2TS U2929 ( .A(n3566), .Y(n2014) );
INVX2TS U2930 ( .A(n3588), .Y(n2015) );
MXI2X4TS U2931 ( .A(n1893), .B(n1856), .S0(n2018), .Y(n2016) );
MX2X4TS U2932 ( .A(n4230), .B(n4229), .S0(n2018), .Y(n2242) );
MX2X4TS U2933 ( .A(n1865), .B(n4269), .S0(n2018), .Y(n2367) );
MXI2X4TS U2934 ( .A(n4280), .B(n4279), .S0(n2026), .Y(n2020) );
MXI2X4TS U2935 ( .A(n4369), .B(n4368), .S0(n2026), .Y(n2021) );
MX2X4TS U2936 ( .A(n4342), .B(n4341), .S0(n2027), .Y(n2022) );
BUFX20TS U2937 ( .A(n2027), .Y(n2026) );
MXI2X4TS U2938 ( .A(n4273), .B(n4272), .S0(n2026), .Y(n2023) );
MX2X4TS U2939 ( .A(n4248), .B(n4247), .S0(n2027), .Y(n2024) );
MXI2X4TS U2940 ( .A(n4291), .B(n4290), .S0(n2026), .Y(n2025) );
MX2X4TS U2941 ( .A(n4280), .B(n4279), .S0(n2027), .Y(n2114) );
INVX2TS U2942 ( .A(n3024), .Y(n2028) );
INVX2TS U2943 ( .A(n2125), .Y(n2030) );
INVX2TS U2944 ( .A(n3618), .Y(n2031) );
NOR2BX4TS U2945 ( .AN(n4263), .B(n4264), .Y(n2194) );
NOR2X4TS U2946 ( .A(n4263), .B(n4265), .Y(n2195) );
MX2X4TS U2947 ( .A(n1866), .B(n4380), .S0(n4379), .Y(n2278) );
MX2X4TS U2948 ( .A(n1932), .B(n4251), .S0(n4250), .Y(n4002) );
MXI2X2TS U2949 ( .A(n1899), .B(n4378), .S0(n4377), .Y(n3309) );
INVX2TS U2950 ( .A(n3058), .Y(n2033) );
INVX2TS U2951 ( .A(n3285), .Y(n2034) );
MXI2X4TS U2952 ( .A(n1898), .B(n4282), .S0(n4281), .Y(n3285) );
MXI2X4TS U2953 ( .A(n4362), .B(n4361), .S0(n4360), .Y(n3283) );
MX2X4TS U2954 ( .A(n4297), .B(n4296), .S0(n4295), .Y(n2120) );
MXI2X4TS U2955 ( .A(n1883), .B(n4240), .S0(n2043), .Y(n2035) );
MXI2X4TS U2956 ( .A(n2036), .B(n2037), .S0(n2043), .Y(n2251) );
MXI2X4TS U2957 ( .A(n1921), .B(n2039), .S0(n2043), .Y(n2038) );
MXI2X4TS U2958 ( .A(n4254), .B(n4253), .S0(n2043), .Y(n2041) );
MX2X4TS U2959 ( .A(n4285), .B(n4284), .S0(n2043), .Y(n2042) );
NAND2X2TS U2960 ( .A(n1593), .B(n3587), .Y(n2738) );
MXI2X4TS U2961 ( .A(n1873), .B(n4195), .S0(n1695), .Y(n3587) );
MX2X4TS U2962 ( .A(n1920), .B(n4206), .S0(n1695), .Y(n2045) );
NAND2X2TS U2963 ( .A(n2974), .B(n3569), .Y(n2729) );
MXI2X4TS U2964 ( .A(n1840), .B(n4226), .S0(n2048), .Y(n3569) );
NAND2X2TS U2965 ( .A(n2739), .B(n3576), .Y(n2732) );
MXI2X4TS U2966 ( .A(n1867), .B(n4218), .S0(n2049), .Y(n3576) );
MXI2X2TS U2967 ( .A(n1858), .B(n4375), .S0(n2049), .Y(n3596) );
MXI2X4TS U2968 ( .A(n1890), .B(n4161), .S0(n2049), .Y(n3606) );
MXI2X4TS U2969 ( .A(n1871), .B(n4204), .S0(n2049), .Y(n3583) );
MXI2X4TS U2970 ( .A(n1897), .B(n2051), .S0(n2059), .Y(n2172) );
MXI2X4TS U2971 ( .A(n2053), .B(n2054), .S0(n2059), .Y(n2052) );
MXI2X4TS U2972 ( .A(n1937), .B(n2056), .S0(n2059), .Y(n2055) );
NAND2X2TS U2973 ( .A(n1592), .B(n3603), .Y(n2837) );
NAND2X2TS U2974 ( .A(n2739), .B(n3567), .Y(n2717) );
MXI2X4TS U2975 ( .A(n1934), .B(n4376), .S0(n2059), .Y(n3567) );
MX2X4TS U2976 ( .A(n1879), .B(n4184), .S0(n1582), .Y(n2058) );
NAND2X4TS U2977 ( .A(n4316), .B(n4317), .Y(n2239) );
MXI2X4TS U2978 ( .A(n1886), .B(n4448), .S0(n4447), .Y(n3669) );
MXI2X4TS U2979 ( .A(n1870), .B(n4406), .S0(n4405), .Y(n3627) );
NAND2BX4TS U2980 ( .AN(n4316), .B(n1862), .Y(n2238) );
MXI2X4TS U2981 ( .A(n1916), .B(n4147), .S0(n4146), .Y(n3643) );
MXI2X4TS U2982 ( .A(n1884), .B(n4450), .S0(n4449), .Y(n3640) );
MXI2X4TS U2983 ( .A(n1913), .B(n4151), .S0(n4150), .Y(n3670) );
MXI2X4TS U2984 ( .A(n1899), .B(n4135), .S0(n4134), .Y(n3656) );
NAND2BX4TS U2985 ( .AN(n4131), .B(n4130), .Y(n2545) );
OAI21X4TS U2986 ( .A0(n1915), .A1(n4130), .B0(n2545), .Y(n3636) );
INVX2TS U2987 ( .A(n3202), .Y(n2064) );
INVX2TS U2988 ( .A(n3642), .Y(n2065) );
INVX2TS U2989 ( .A(n3623), .Y(n2066) );
INVX2TS U2990 ( .A(n3660), .Y(n2070) );
INVX2TS U2991 ( .A(n3668), .Y(n2071) );
MXI2X4TS U2992 ( .A(n4101), .B(n4100), .S0(n4099), .Y(n3620) );
MX2X6TS U2993 ( .A(n1900), .B(n4121), .S0(n4120), .Y(n2116) );
MXI2X4TS U2994 ( .A(n1920), .B(n4126), .S0(n4125), .Y(n3631) );
MX2X6TS U2995 ( .A(n1895), .B(n4149), .S0(n4148), .Y(n2110) );
MXI2X4TS U2996 ( .A(n1894), .B(n4153), .S0(n4152), .Y(n3697) );
MXI2X4TS U2997 ( .A(n1868), .B(n4454), .S0(n4453), .Y(n3635) );
MXI2X4TS U2998 ( .A(n1865), .B(n4461), .S0(n4460), .Y(n3621) );
MXI2X4TS U2999 ( .A(n1889), .B(n4396), .S0(n4395), .Y(n3632) );
MXI2X4TS U3000 ( .A(n1871), .B(n4392), .S0(n4391), .Y(n3639) );
MXI2X4TS U3001 ( .A(n4356), .B(n4355), .S0(n4354), .Y(n3622) );
MXI2X4TS U3002 ( .A(n1901), .B(n4111), .S0(n4110), .Y(n3695) );
MXI2X4TS U3003 ( .A(n1911), .B(n4092), .S0(n4091), .Y(n3749) );
MX2X4TS U3004 ( .A(n1877), .B(n4429), .S0(n4428), .Y(n2112) );
INVX2TS U3005 ( .A(n3677), .Y(n2072) );
MXI2X4TS U3006 ( .A(n1876), .B(n4446), .S0(n4445), .Y(n3671) );
MXI2X4TS U3007 ( .A(n1935), .B(n4444), .S0(n4443), .Y(n2115) );
MXI2X4TS U3008 ( .A(n1867), .B(n4404), .S0(n4403), .Y(n2118) );
MXI2X4TS U3009 ( .A(n1887), .B(n4400), .S0(n4399), .Y(n3633) );
MXI2X4TS U3010 ( .A(n1863), .B(n4315), .S0(n4314), .Y(n3661) );
MX2X6TS U3011 ( .A(n1879), .B(n4311), .S0(n4310), .Y(n2245) );
MX2X6TS U3012 ( .A(n1896), .B(n4145), .S0(n4144), .Y(n2309) );
MXI2X4TS U3013 ( .A(n4138), .B(n4137), .S0(n4136), .Y(n3628) );
MXI2X4TS U3014 ( .A(n1859), .B(n4452), .S0(n4451), .Y(n3657) );
INVX12TS U3015 ( .A(n3545), .Y(n4467) );
MXI2X2TS U3016 ( .A(n1938), .B(n4390), .S0(n4389), .Y(n3665) );
INVX2TS U3017 ( .A(n3655), .Y(n2076) );
MXI2X4TS U3018 ( .A(n1934), .B(n4459), .S0(n4458), .Y(n3629) );
MXI2X4TS U3019 ( .A(n1858), .B(n4437), .S0(n4436), .Y(n3626) );
MXI2X4TS U3020 ( .A(n1892), .B(n4433), .S0(n4432), .Y(n3699) );
MXI2X4TS U3021 ( .A(n1880), .B(n4394), .S0(n4393), .Y(n3630) );
MX2X6TS U3022 ( .A(n1939), .B(n4115), .S0(n4114), .Y(n2132) );
MX2X4TS U3023 ( .A(n1938), .B(n4390), .S0(n4389), .Y(n2307) );
NOR2X4TS U3024 ( .A(n2078), .B(n2077), .Y(n910) );
INVX12TS U3025 ( .A(n2099), .Y(n3214) );
INVX2TS U3026 ( .A(n2616), .Y(n2532) );
NOR2BX2TS U3027 ( .AN(d_ff1_Z[11]), .B(n2564), .Y(n2586) );
NOR2BX2TS U3028 ( .AN(d_ff1_Z[24]), .B(n2564), .Y(n2562) );
NOR2BX2TS U3029 ( .AN(d_ff1_Z[26]), .B(n2564), .Y(n2563) );
AND2X4TS U3030 ( .A(n3328), .B(n2123), .Y(n2559) );
CLKINVX6TS U3031 ( .A(n2355), .Y(n2356) );
INVX8TS U3032 ( .A(n2301), .Y(n2218) );
INVX2TS U3033 ( .A(n2537), .Y(n2407) );
NOR2X2TS U3034 ( .A(n3714), .B(cont_var_out[1]), .Y(n3249) );
NAND2X2TS U3035 ( .A(n3439), .B(d_ff2_Y[16]), .Y(n3096) );
INVX8TS U3036 ( .A(n3208), .Y(ack_add_subt) );
NAND3X2TS U3037 ( .A(n2218), .B(n3711), .C(d_ff2_Y[57]), .Y(n4598) );
NAND2X2TS U3038 ( .A(n1643), .B(n3749), .Y(n3750) );
CLKAND2X2TS U3039 ( .A(n2375), .B(n2835), .Y(n2515) );
NAND2X4TS U3040 ( .A(n2211), .B(n3688), .Y(n3644) );
INVX2TS U3041 ( .A(n2212), .Y(n2211) );
INVX2TS U3042 ( .A(n3555), .Y(n2620) );
NOR2X4TS U3043 ( .A(n3705), .B(n3734), .Y(n2943) );
AND2X2TS U3044 ( .A(n1573), .B(d_ff2_X[57]), .Y(n2597) );
INVX2TS U3045 ( .A(n2930), .Y(n2603) );
NOR2X4TS U3046 ( .A(n3709), .B(n2150), .Y(n3200) );
INVX2TS U3047 ( .A(n4488), .Y(n2399) );
NAND3X2TS U3048 ( .A(n3472), .B(n3402), .C(n3401), .Y(add_subt_dataB[60]) );
INVX2TS U3049 ( .A(n3769), .Y(n3519) );
AOI22X2TS U3050 ( .A0(n2511), .A1(n2064), .B0(n2949), .B1(n1595), .Y(n590)
);
NAND3X2TS U3051 ( .A(n2782), .B(n2780), .C(n2781), .Y(n835) );
NAND2X4TS U3052 ( .A(n2843), .B(d_ff2_Z[54]), .Y(n2781) );
AOI21X2TS U3053 ( .A0(n3233), .A1(n1665), .B0(n3232), .Y(n4615) );
NAND2X4TS U3054 ( .A(n2543), .B(n2025), .Y(n3013) );
AOI22X1TS U3055 ( .A0(n3743), .A1(n2124), .B0(n2067), .B1(n3724), .Y(n584)
);
OR2X4TS U3056 ( .A(n2538), .B(n2165), .Y(n2873) );
OR2X4TS U3057 ( .A(n2538), .B(n2166), .Y(n2876) );
OR2X4TS U3058 ( .A(n2538), .B(n2167), .Y(n2883) );
NAND2X4TS U3059 ( .A(n2541), .B(n2540), .Y(n834) );
MXI2X2TS U3060 ( .A(n3908), .B(n4562), .S0(n2629), .Y(n631) );
MXI2X2TS U3061 ( .A(n4590), .B(n4591), .S0(n3551), .Y(n597) );
MXI2X2TS U3062 ( .A(n1570), .B(n4577), .S0(n3736), .Y(n611) );
AOI22X2TS U3063 ( .A0(n1643), .A1(n2076), .B0(n2249), .B1(n3743), .Y(n583)
);
INVX2TS U3064 ( .A(n2248), .Y(n2249) );
NAND2X2TS U3065 ( .A(n1768), .B(n2257), .Y(n3266) );
NOR2X4TS U3066 ( .A(n2532), .B(n3263), .Y(n3264) );
NAND2X2TS U3067 ( .A(n2533), .B(n3600), .Y(n2819) );
NAND2X2TS U3068 ( .A(n1585), .B(n2259), .Y(n2828) );
NAND2X1TS U3069 ( .A(n2539), .B(n3575), .Y(n2658) );
NAND2X2TS U3070 ( .A(n2234), .B(n2281), .Y(n2834) );
NAND2X2TS U3071 ( .A(n2495), .B(n2282), .Y(n2838) );
NAND2X1TS U3072 ( .A(n2495), .B(n2284), .Y(n2722) );
NAND2X2TS U3073 ( .A(n2234), .B(n2300), .Y(n2665) );
NAND2X2TS U3074 ( .A(n2573), .B(n3559), .Y(n2666) );
INVX2TS U3075 ( .A(n2324), .Y(n2325) );
INVX2TS U3076 ( .A(n2329), .Y(n3753) );
INVX2TS U3077 ( .A(n2331), .Y(n3754) );
NAND3X2TS U3078 ( .A(n1772), .B(n2990), .C(n2362), .Y(n2991) );
OAI21X2TS U3079 ( .A0(n1713), .A1(n2369), .B0(n3269), .Y(n719) );
NAND2X2TS U3080 ( .A(n3279), .B(n2511), .Y(n3269) );
NAND2X2TS U3081 ( .A(n2035), .B(n1643), .Y(n2995) );
NAND2X2TS U3082 ( .A(n3252), .B(n2490), .Y(n2489) );
AOI22X2TS U3083 ( .A0(n2546), .A1(n2110), .B0(n3914), .B1(n1584), .Y(n668)
);
AOI22X2TS U3084 ( .A0(n2149), .A1(n3734), .B0(n2543), .B1(n2072), .Y(n587)
);
NOR2X4TS U3085 ( .A(n3050), .B(n2191), .Y(n2315) );
INVX2TS U3086 ( .A(d_ff3_LUT_out[43]), .Y(n2621) );
INVX2TS U3087 ( .A(data_output[63]), .Y(n2687) );
NAND2X4TS U3088 ( .A(n2865), .B(n2383), .Y(n3667) );
INVX2TS U3089 ( .A(n3627), .Y(n4580) );
INVX2TS U3090 ( .A(n3657), .Y(n4617) );
INVX2TS U3091 ( .A(n3621), .Y(n4585) );
INVX4TS U3092 ( .A(n4576), .Y(n2552) );
INVX2TS U3093 ( .A(n3283), .Y(n4714) );
INVX4TS U3094 ( .A(n2118), .Y(n2127) );
INVX4TS U3095 ( .A(n2115), .Y(n2174) );
NOR2X4TS U3096 ( .A(n3649), .B(n3650), .Y(n4559) );
OAI21X2TS U3097 ( .A0(n3682), .A1(n3911), .B0(n2613), .Y(n3483) );
NOR2X2TS U3098 ( .A(n2629), .B(n2628), .Y(n2627) );
CLKBUFX2TS U3099 ( .A(n1638), .Y(n4506) );
INVX2TS U3100 ( .A(n3490), .Y(n2626) );
NAND2X4TS U3101 ( .A(n2543), .B(n3626), .Y(n3038) );
INVX2TS U3102 ( .A(n2469), .Y(n2470) );
INVX2TS U3103 ( .A(n2465), .Y(n2466) );
NAND2X4TS U3104 ( .A(n1594), .B(n3622), .Y(n3045) );
NAND2X4TS U3105 ( .A(n1592), .B(n3630), .Y(n3030) );
NAND2X2TS U3106 ( .A(n2199), .B(n3635), .Y(n3041) );
NAND2X4TS U3107 ( .A(n3277), .B(n2199), .Y(n3270) );
NAND2X4TS U3108 ( .A(n2543), .B(n3311), .Y(n3312) );
NAND2X4TS U3109 ( .A(n2546), .B(n3307), .Y(n3308) );
NAND2X4TS U3110 ( .A(n1592), .B(n1651), .Y(n3004) );
NAND2X1TS U3111 ( .A(n2520), .B(n3058), .Y(n3020) );
NAND2X2TS U3112 ( .A(n2385), .B(n3285), .Y(n3017) );
OAI21X2TS U3113 ( .A0(n1513), .A1(n2352), .B0(n2505), .Y(n977) );
OAI21X2TS U3114 ( .A0(n1513), .A1(n2134), .B0(n2507), .Y(n989) );
NOR2X4TS U3115 ( .A(n2553), .B(n3251), .Y(n1337) );
NAND2X4TS U3116 ( .A(n1547), .B(n2575), .Y(n2553) );
INVX4TS U3117 ( .A(n3250), .Y(n2575) );
MXI2X4TS U3118 ( .A(n4228), .B(n4227), .S0(n1852), .Y(n3598) );
AOI2BB2X2TS U3119 ( .B0(n3219), .B1(n3716), .A0N(n2215), .A1N(
d_ff3_LUT_out[23]), .Y(n922) );
NOR2X4TS U3120 ( .A(n3211), .B(n3212), .Y(n2623) );
AOI2BB2X4TS U3121 ( .B0(n3509), .B1(d_ff3_sh_y_out[34]), .A0N(n2163), .A1N(
n2094), .Y(n3353) );
NOR2X8TS U3122 ( .A(sel_mux_2_reg_0_), .B(n1762), .Y(n3339) );
OAI2BB1X2TS U3123 ( .A0N(n2091), .A1N(n1645), .B0(n3497), .Y(
add_subt_dataB[50]) );
OAI2BB1X2TS U3124 ( .A0N(n3769), .A1N(n1645), .B0(n3517), .Y(
add_subt_dataB[53]) );
OAI2BB1X2TS U3125 ( .A0N(n2411), .A1N(n1645), .B0(n3385), .Y(
add_subt_dataB[54]) );
BUFX20TS U3126 ( .A(n2316), .Y(n3272) );
INVX16TS U3127 ( .A(n2217), .Y(n2316) );
AOI2BB2X4TS U3128 ( .B0(n3175), .B1(n2093), .A0N(n2095), .A1N(n2094), .Y(
n3393) );
NAND2X8TS U3129 ( .A(n1539), .B(n3473), .Y(n2122) );
MX2X6TS U3130 ( .A(n1873), .B(n4402), .S0(n4401), .Y(n2097) );
AOI22X2TS U3131 ( .A0(n3696), .A1(n3633), .B0(sign_inv_out[30]), .B1(n1724),
.Y(n2906) );
AOI2BB2X4TS U3132 ( .B0(n1650), .B1(n1515), .A0N(n2098), .A1N(n3878), .Y(
n2509) );
BUFX20TS U3133 ( .A(n2521), .Y(n2519) );
INVX16TS U3134 ( .A(n2287), .Y(n2295) );
NOR2X8TS U3135 ( .A(n2247), .B(n2951), .Y(n2104) );
INVX12TS U3136 ( .A(n2697), .Y(n2696) );
MX2X4TS U3137 ( .A(n2108), .B(n1841), .S0(n2109), .Y(n3638) );
NAND2BX4TS U3138 ( .AN(n3477), .B(n3476), .Y(n3478) );
BUFX20TS U3139 ( .A(n2190), .Y(n2111) );
MX2X4TS U3140 ( .A(n1935), .B(n4234), .S0(n4233), .Y(n3997) );
OR2X8TS U3141 ( .A(n2311), .B(n3331), .Y(n4620) );
INVX16TS U3142 ( .A(n3737), .Y(n3739) );
NOR2X6TS U3143 ( .A(n2931), .B(n1540), .Y(n3219) );
XNOR2X4TS U3144 ( .A(n3072), .B(n2143), .Y(n2137) );
BUFX20TS U3145 ( .A(n2519), .Y(n2199) );
BUFX20TS U3146 ( .A(n2519), .Y(n2844) );
BUFX20TS U3147 ( .A(n2520), .Y(n3724) );
OR2X8TS U3148 ( .A(n2231), .B(n2233), .Y(n2121) );
XOR2X4TS U3149 ( .A(n2347), .B(n3325), .Y(n3327) );
NAND2X4TS U3150 ( .A(n2528), .B(n2175), .Y(n2347) );
MX2X4TS U3151 ( .A(d_ff3_sh_y_out[28]), .B(d_ff2_Y[28]), .S0(n3684), .Y(n767) );
BUFX12TS U3152 ( .A(n3359), .Y(n3159) );
BUFX12TS U3153 ( .A(n3359), .Y(n3174) );
BUFX8TS U3154 ( .A(n3359), .Y(n3182) );
NAND2X8TS U3155 ( .A(n2698), .B(n3243), .Y(n2699) );
OAI2BB1X2TS U3156 ( .A0N(n3672), .A1N(n2901), .B0(n2919), .Y(n957) );
INVX4TS U3157 ( .A(n2123), .Y(n2124) );
MXI2X4TS U3158 ( .A(n4239), .B(n4238), .S0(n4237), .Y(n2125) );
AND2X8TS U3159 ( .A(n2381), .B(n2633), .Y(n3243) );
BUFX20TS U3160 ( .A(n2378), .Y(n3227) );
XOR2X4TS U3161 ( .A(n2593), .B(n2320), .Y(n2130) );
NAND2X4TS U3162 ( .A(n2495), .B(d_ff2_Z[23]), .Y(n2821) );
AOI21X4TS U3163 ( .A0(ack_add_subt), .A1(n3249), .B0(cont_var_out[0]), .Y(
n3251) );
OR3X6TS U3164 ( .A(n2139), .B(n2136), .C(n2579), .Y(n2863) );
BUFX20TS U3165 ( .A(n2801), .Y(n3001) );
NOR2X8TS U3166 ( .A(n2196), .B(n2197), .Y(n2521) );
NAND3X2TS U3167 ( .A(n2122), .B(n2619), .C(n3682), .Y(n4605) );
MX2X4TS U3168 ( .A(d_ff3_sh_y_out[24]), .B(d_ff2_Y[24]), .S0(n2230), .Y(
n2188) );
BUFX20TS U3169 ( .A(n3727), .Y(n2589) );
CLKINVX6TS U3170 ( .A(n1721), .Y(n2152) );
INVX16TS U3171 ( .A(n2224), .Y(n3735) );
NAND2X8TS U3172 ( .A(n2308), .B(n3556), .Y(n3685) );
CLKINVX12TS U3173 ( .A(n3485), .Y(n3556) );
BUFX20TS U3174 ( .A(n2655), .Y(n2235) );
OR2X8TS U3175 ( .A(n2301), .B(n3550), .Y(n4600) );
INVX8TS U3176 ( .A(n2701), .Y(n2364) );
CLKINVX12TS U3177 ( .A(n4476), .Y(n2911) );
NAND2X4TS U3178 ( .A(n2369), .B(n3227), .Y(n2639) );
BUFX20TS U3179 ( .A(n2655), .Y(n2537) );
INVX12TS U3180 ( .A(n3545), .Y(n4468) );
NAND2X2TS U3181 ( .A(n2381), .B(ready_add_subt), .Y(n3053) );
NAND2BX1TS U3182 ( .AN(n2310), .B(n3051), .Y(n2208) );
NAND3X4TS U3183 ( .A(n3247), .B(n3717), .C(n2210), .Y(n2209) );
BUFX6TS U3184 ( .A(cordic_FSM_state_reg_3_), .Y(n3245) );
NAND3X8TS U3185 ( .A(n2310), .B(n2350), .C(n2362), .Y(n2196) );
AOI22X2TS U3186 ( .A0(n2383), .A1(n2174), .B0(n2146), .B1(n1584), .Y(n626)
);
NAND2BX1TS U3187 ( .AN(n1485), .B(n2310), .Y(n2210) );
INVX12TS U3188 ( .A(n2353), .Y(n3242) );
OR2X6TS U3189 ( .A(n2382), .B(n2633), .Y(n2353) );
NOR2X4TS U3190 ( .A(n1536), .B(n3242), .Y(n2207) );
CLKAND2X2TS U3191 ( .A(n3187), .B(n3242), .Y(n2151) );
INVX16TS U3192 ( .A(n2201), .Y(n2554) );
NOR2X8TS U3193 ( .A(n2197), .B(n2196), .Y(n2148) );
MXI2X4TS U3194 ( .A(n3797), .B(n4006), .S0(n2292), .Y(n948) );
INVX6TS U3195 ( .A(n2526), .Y(n2149) );
BUFX20TS U3196 ( .A(n2235), .Y(n2526) );
INVX12TS U3197 ( .A(n2150), .Y(n2530) );
BUFX20TS U3198 ( .A(n2316), .Y(n3549) );
NOR2BX2TS U3199 ( .AN(d_ff2_X[55]), .B(n2949), .Y(n2952) );
INVX12TS U3200 ( .A(n2152), .Y(n2153) );
OR2X4TS U3201 ( .A(n1968), .B(n2524), .Y(n2769) );
INVX16TS U3202 ( .A(n2522), .Y(n2524) );
MX2X4TS U3203 ( .A(d_ff3_sh_y_out[19]), .B(d_ff2_Y[19]), .S0(n3711), .Y(n785) );
BUFX20TS U3204 ( .A(n2380), .Y(n2310) );
AOI22X2TS U3205 ( .A0(n1643), .A1(n2144), .B0(n3744), .B1(n3909), .Y(n624)
);
INVX12TS U3206 ( .A(n2643), .Y(n2714) );
BUFX16TS U3207 ( .A(n3489), .Y(n2613) );
AO22X4TS U3208 ( .A0(n3231), .A1(n2624), .B0(n2613), .B1(n2181), .Y(n2157)
);
OR2X2TS U3209 ( .A(n2230), .B(d_ff3_LUT_out[48]), .Y(n2158) );
CLKBUFX2TS U3210 ( .A(n3535), .Y(n3536) );
INVX2TS U3211 ( .A(n4483), .Y(n2397) );
INVX2TS U3212 ( .A(n4484), .Y(n2384) );
INVX12TS U3213 ( .A(n3489), .Y(n2624) );
AND2X2TS U3214 ( .A(n3543), .B(d_ff2_Y[61]), .Y(n2176) );
INVX12TS U3215 ( .A(n2225), .Y(n3736) );
OR2X2TS U3216 ( .A(n3489), .B(n2162), .Y(n2178) );
INVX2TS U3217 ( .A(n3394), .Y(n3552) );
CLKINVX6TS U3218 ( .A(n2612), .Y(n2796) );
AND2X2TS U3219 ( .A(n2975), .B(d_ff1_Z[5]), .Y(n2183) );
INVX2TS U3220 ( .A(n3699), .Y(n4571) );
INVX2TS U3221 ( .A(n3697), .Y(n4589) );
INVX4TS U3222 ( .A(n3656), .Y(n4587) );
INVX4TS U3223 ( .A(n3671), .Y(n4576) );
NOR2X4TS U3224 ( .A(n2195), .B(n2194), .Y(n2193) );
INVX6TS U3225 ( .A(n2363), .Y(n2564) );
INVX12TS U3226 ( .A(n2362), .Y(n2811) );
INVX2TS U3227 ( .A(n1619), .Y(n2391) );
INVX2TS U3228 ( .A(n2391), .Y(n2393) );
INVX2TS U3229 ( .A(n2399), .Y(n2400) );
INVX2TS U3230 ( .A(n2397), .Y(n2487) );
INVX2TS U3231 ( .A(n1620), .Y(n2386) );
INVX2TS U3232 ( .A(n2384), .Y(n2390) );
OAI21X2TS U3233 ( .A0(n4577), .A1(n3518), .B0(n3350), .Y(add_subt_dataB[42])
);
INVX12TS U3234 ( .A(n3272), .Y(n2629) );
AOI2BB2X4TS U3235 ( .B0(n3225), .B1(n3226), .A0N(n2619), .A1N(
d_ff3_LUT_out[21]), .Y(n924) );
NAND2X8TS U3236 ( .A(n3713), .B(n2530), .Y(n3650) );
NAND2X8TS U3237 ( .A(n2198), .B(n2214), .Y(n2197) );
INVX12TS U3238 ( .A(cordic_FSM_state_reg_3_), .Y(n2198) );
NAND2BX4TS U3239 ( .AN(n1637), .B(n2998), .Y(n2999) );
AOI21X4TS U3240 ( .A0(n2061), .A1(n1700), .B0(n2200), .Y(n682) );
INVX16TS U3241 ( .A(n2382), .Y(n2256) );
NAND3BX4TS U3242 ( .AN(n2209), .B(n3056), .C(n2208), .Y(n1343) );
INVX12TS U3243 ( .A(n2801), .Y(n2495) );
NAND2BX4TS U3244 ( .AN(n2212), .B(n2743), .Y(n2940) );
NAND2BX4TS U3245 ( .AN(n3054), .B(n2212), .Y(n2314) );
NOR2X8TS U3246 ( .A(n2633), .B(cordic_FSM_state_reg_3_), .Y(n2213) );
AOI2BB2X4TS U3247 ( .B0(n3723), .B1(n1669), .A0N(n2215), .A1N(
d_ff3_LUT_out[45]), .Y(n900) );
AOI2BB2X4TS U3248 ( .B0(n3723), .B1(n1538), .A0N(n2215), .A1N(
d_ff3_LUT_out[50]), .Y(n895) );
AOI2BB2X4TS U3249 ( .B0(n3068), .B1(n2607), .A0N(n2215), .A1N(
d_ff3_LUT_out[31]), .Y(n914) );
AOI2BB2X4TS U3250 ( .B0(n3237), .B1(n3685), .A0N(n2215), .A1N(n3904), .Y(
n3238) );
AOI2BB2X4TS U3251 ( .B0(n2985), .B1(n2371), .A0N(n2215), .A1N(
d_ff3_LUT_out[18]), .Y(n927) );
AOI2BB2X4TS U3252 ( .B0(n2791), .B1(n2790), .A0N(n2215), .A1N(
d_ff3_LUT_out[55]), .Y(n891) );
NAND2X4TS U3253 ( .A(n3733), .B(n1557), .Y(n943) );
NOR2X8TS U3254 ( .A(n1606), .B(n2138), .Y(n2216) );
BUFX20TS U3255 ( .A(n2316), .Y(n2225) );
NAND2X4TS U3256 ( .A(n2228), .B(n2227), .Y(n627) );
INVX16TS U3257 ( .A(n2232), .Y(n3737) );
NAND2X8TS U3258 ( .A(n2351), .B(n2147), .Y(n2233) );
OAI2BB1X4TS U3259 ( .A0N(d_ff2_Y[1]), .A1N(n1584), .B0(n3000), .Y(n822) );
INVX12TS U3260 ( .A(n2235), .Y(n2234) );
NAND3X8TS U3261 ( .A(n2236), .B(n2214), .C(n2350), .Y(n2643) );
CLKBUFX3TS U3262 ( .A(n2510), .Y(n2237) );
NAND2X4TS U3263 ( .A(n2383), .B(n3629), .Y(n2945) );
CLKMX2X4TS U3264 ( .A(d_ff1_Z[28]), .B(data_in[28]), .S0(n3738), .Y(n1305)
);
AND2X8TS U3265 ( .A(n1504), .B(n3245), .Y(n2616) );
NOR2X8TS U3266 ( .A(n2351), .B(n2147), .Y(n2638) );
CLKINVX12TS U3267 ( .A(n2595), .Y(n2528) );
AOI22X2TS U3268 ( .A0(n3698), .A1(n3697), .B0(n2557), .B1(n3756), .Y(n4719)
);
NAND2X8TS U3269 ( .A(n2138), .B(n2689), .Y(n2690) );
AND2X8TS U3270 ( .A(n3732), .B(n2138), .Y(n2979) );
NAND2X4TS U3271 ( .A(n1684), .B(n3072), .Y(n2766) );
AOI22X2TS U3272 ( .A0(n3698), .A1(n3699), .B0(n3755), .B1(n2496), .Y(n4718)
);
BUFX16TS U3273 ( .A(n2714), .Y(n2845) );
NAND2X4TS U3274 ( .A(n2544), .B(n2023), .Y(n3006) );
NAND2X4TS U3275 ( .A(n2544), .B(n3309), .Y(n3310) );
AOI22X2TS U3276 ( .A0(n2544), .A1(n1528), .B0(n2277), .B1(n3743), .Y(n588)
);
NAND2X4TS U3277 ( .A(n1956), .B(n2544), .Y(n3304) );
OAI2BB1X4TS U3278 ( .A0N(n2141), .A1N(n1585), .B0(n3730), .Y(n720) );
OAI21X2TS U3279 ( .A0(n1704), .A1(n2628), .B0(n3653), .Y(n712) );
BUFX20TS U3280 ( .A(n2520), .Y(n2546) );
INVX8TS U3281 ( .A(n3670), .Y(n4578) );
NAND3BX4TS U3282 ( .AN(n2271), .B(n2805), .C(n2804), .Y(n867) );
AND2X4TS U3283 ( .A(n2570), .B(n2584), .Y(n2271) );
NAND3BX4TS U3284 ( .AN(n2272), .B(n2812), .C(n2813), .Y(n869) );
AND2X4TS U3285 ( .A(n2570), .B(n2585), .Y(n2272) );
NAND3BX4TS U3286 ( .AN(n2273), .B(n2800), .C(n2799), .Y(n868) );
AND2X4TS U3287 ( .A(n2570), .B(n2583), .Y(n2273) );
OR2X4TS U3288 ( .A(n2172), .B(n2524), .Y(n2960) );
OR2X4TS U3289 ( .A(n2170), .B(n2524), .Y(n2963) );
OR2X4TS U3290 ( .A(n2171), .B(n2524), .Y(n2978) );
NAND2X2TS U3291 ( .A(n1700), .B(n3596), .Y(n2827) );
OAI2BB1X2TS U3292 ( .A0N(n4473), .A1N(n1518), .B0(n3549), .Y(n3477) );
INVX16TS U3293 ( .A(n3757), .Y(n2287) );
AND2X8TS U3294 ( .A(n3330), .B(n3329), .Y(n2311) );
CLKINVX12TS U3295 ( .A(n4609), .Y(n2488) );
MXI2X4TS U3296 ( .A(n2304), .B(n1933), .S0(n2305), .Y(n2303) );
AND2X8TS U3297 ( .A(n3556), .B(n2628), .Y(n3682) );
MXI2X2TS U3298 ( .A(n2684), .B(n2683), .S0(n2154), .Y(n2685) );
MX2X4TS U3299 ( .A(n2154), .B(shift_region_flag[0]), .S0(n1511), .Y(n1335)
);
AOI21X4TS U3300 ( .A0(n1854), .A1(n2327), .B0(n2328), .Y(n2326) );
AOI2BB1X4TS U3301 ( .A0N(n1855), .A1N(n4301), .B0(n2330), .Y(n2329) );
AOI21X4TS U3302 ( .A0(n2332), .A1(n2333), .B0(n2334), .Y(n2331) );
AOI21X4TS U3303 ( .A0(n1853), .A1(n1850), .B0(n2336), .Y(n2335) );
AOI21X4TS U3304 ( .A0(n1853), .A1(n1856), .B0(n2338), .Y(n2337) );
AOI21X4TS U3305 ( .A0(n2340), .A1(n1848), .B0(n2341), .Y(n2339) );
INVX4TS U3306 ( .A(n2635), .Y(n3759) );
OAI2BB1X4TS U3307 ( .A0N(n1719), .A1N(n2495), .B0(n3750), .Y(n592) );
NAND3X2TS U3308 ( .A(n3472), .B(n3404), .C(n3403), .Y(add_subt_dataB[51]) );
NAND3X2TS U3309 ( .A(n3472), .B(n3406), .C(n3405), .Y(add_subt_dataB[48]) );
NAND3X2TS U3310 ( .A(n3472), .B(n3408), .C(n3407), .Y(add_subt_dataB[59]) );
NAND3X2TS U3311 ( .A(n3472), .B(n3411), .C(n3410), .Y(add_subt_dataB[58]) );
NAND3X2TS U3312 ( .A(n3472), .B(n3414), .C(n3413), .Y(add_subt_dataB[57]) );
NAND2X6TS U3313 ( .A(n3516), .B(d_ff3_LUT_out[48]), .Y(n3472) );
NOR2X8TS U3314 ( .A(d_ff2_Y[56]), .B(d_ff2_Y[57]), .Y(n3683) );
INVX16TS U3315 ( .A(n2360), .Y(n3746) );
INVX6TS U3316 ( .A(n2702), .Y(n2703) );
INVX8TS U3317 ( .A(n2362), .Y(n2363) );
NOR2BX4TS U3318 ( .AN(n3772), .B(n2946), .Y(n2947) );
OAI2BB2X4TS U3319 ( .B0(n3274), .B1(n1735), .A0N(n2365), .A1N(n2366), .Y(
n3275) );
OA21X4TS U3320 ( .A0(n2602), .A1(n2601), .B0(n2600), .Y(n2371) );
NOR2X4TS U3321 ( .A(n2692), .B(n2640), .Y(n2601) );
INVX12TS U3322 ( .A(n2373), .Y(n3722) );
NOR2X4TS U3323 ( .A(n3053), .B(n2351), .Y(n2617) );
AND2X4TS U3324 ( .A(n3772), .B(n2949), .Y(n2950) );
MXI2X4TS U3325 ( .A(n3774), .B(n4579), .S0(n3735), .Y(n609) );
MXI2X4TS U3326 ( .A(n3776), .B(n2437), .S0(n1665), .Y(n603) );
MXI2X4TS U3327 ( .A(n2630), .B(n2417), .S0(n3252), .Y(n617) );
BUFX20TS U3328 ( .A(n2520), .Y(n2383) );
NAND2X2TS U3329 ( .A(n2539), .B(n3599), .Y(n2799) );
BUFX8TS U3330 ( .A(n3339), .Y(n3422) );
MXI2X4TS U3331 ( .A(n3948), .B(n2413), .S0(n1547), .Y(n621) );
MXI2X4TS U3332 ( .A(n3938), .B(n2415), .S0(n2629), .Y(n619) );
MXI2X4TS U3333 ( .A(n3939), .B(n2419), .S0(n1665), .Y(n615) );
NAND2X8TS U3334 ( .A(n2762), .B(n1522), .Y(n2934) );
AOI22X2TS U3335 ( .A0(n3691), .A1(n3628), .B0(n2409), .B1(sign_inv_out[1]),
.Y(n2909) );
AOI22X2TS U3336 ( .A0(n3696), .A1(n3262), .B0(n1724), .B1(sign_inv_out[13]),
.Y(n3059) );
AOI22X2TS U3337 ( .A0(n1515), .A1(n3642), .B0(n1574), .B1(sign_inv_out[18]),
.Y(n3064) );
AOI22X2TS U3338 ( .A0(n1516), .A1(n3625), .B0(n1724), .B1(sign_inv_out[2]),
.Y(n2915) );
AOI22X2TS U3339 ( .A0(n3703), .A1(n3674), .B0(n1724), .B1(sign_inv_out[11]),
.Y(n3061) );
BUFX16TS U3340 ( .A(n3361), .Y(n2401) );
BUFX12TS U3341 ( .A(n3361), .Y(n3160) );
BUFX12TS U3342 ( .A(n3361), .Y(n3175) );
BUFX12TS U3343 ( .A(n3361), .Y(n3520) );
BUFX20TS U3344 ( .A(n2618), .Y(n2402) );
MXI2X4TS U3345 ( .A(n3775), .B(n2435), .S0(n1547), .Y(n605) );
INVX2TS U3346 ( .A(n4588), .Y(n2404) );
CLKINVX6TS U3347 ( .A(n2404), .Y(n2405) );
AOI22X2TS U3348 ( .A0(n2543), .A1(n4574), .B0(n2631), .B1(n3743), .Y(n614)
);
MXI2X4TS U3349 ( .A(n2631), .B(n2421), .S0(n2229), .Y(n613) );
AOI22X2TS U3350 ( .A0(n3743), .A1(n3905), .B0(n2544), .B1(n2245), .Y(n674)
);
MXI2X4TS U3351 ( .A(n3905), .B(n2458), .S0(n1547), .Y(n673) );
OAI2BB1X4TS U3352 ( .A0N(d_ff2_Y[46]), .A1N(n2407), .B0(n3304), .Y(n732) );
INVX16TS U3353 ( .A(n2408), .Y(n2409) );
AOI22X2TS U3354 ( .A0(n1516), .A1(n3631), .B0(n2409), .B1(sign_inv_out[23]),
.Y(n2894) );
AOI22X2TS U3355 ( .A0(n3691), .A1(n3634), .B0(n2409), .B1(sign_inv_out[22]),
.Y(n2895) );
AOI22X2TS U3356 ( .A0(n1515), .A1(n3637), .B0(n2409), .B1(sign_inv_out[21]),
.Y(n2896) );
AOI22X2TS U3357 ( .A0(n1516), .A1(n3632), .B0(n2409), .B1(sign_inv_out[20]),
.Y(n2897) );
AOI22X2TS U3358 ( .A0(n3698), .A1(n1647), .B0(n1543), .B1(sign_inv_out[46]),
.Y(n2886) );
AOI22X2TS U3359 ( .A0(n1544), .A1(n2533), .B0(n2325), .B1(n2407), .Y(n585)
);
INVX16TS U3360 ( .A(n3253), .Y(n3254) );
BUFX20TS U3361 ( .A(n3272), .Y(n2410) );
NAND2X6TS U3362 ( .A(n3272), .B(n3324), .Y(n3647) );
MX2X4TS U3363 ( .A(d_ff1_Z[10]), .B(data_in[10]), .S0(n3715), .Y(n1323) );
MX2X4TS U3364 ( .A(d_ff1_Z[12]), .B(data_in[12]), .S0(n3715), .Y(n1321) );
MX2X4TS U3365 ( .A(d_ff1_Z[14]), .B(data_in[14]), .S0(n3715), .Y(n1319) );
INVX2TS U3366 ( .A(n2412), .Y(n2413) );
INVX2TS U3367 ( .A(n2414), .Y(n2415) );
INVX2TS U3368 ( .A(n2416), .Y(n2417) );
INVX2TS U3369 ( .A(n2418), .Y(n2419) );
INVX2TS U3370 ( .A(n2420), .Y(n2421) );
INVX2TS U3371 ( .A(n2422), .Y(n2423) );
OAI21X4TS U3372 ( .A0(n4320), .A1(n4319), .B0(n4318), .Y(n3400) );
MX2X4TS U3373 ( .A(d_ff1_Z[11]), .B(data_in[11]), .S0(n3715), .Y(n1322) );
MX2X4TS U3374 ( .A(d_ff1_Z[15]), .B(data_in[15]), .S0(n3715), .Y(n1318) );
MX2X4TS U3375 ( .A(d_ff1_Z[16]), .B(data_in[16]), .S0(n3715), .Y(n1317) );
MX2X4TS U3376 ( .A(d_ff1_Z[19]), .B(data_in[19]), .S0(n1511), .Y(n1314) );
MX2X4TS U3377 ( .A(d_ff1_Z[20]), .B(data_in[20]), .S0(n3740), .Y(n1313) );
MX2X4TS U3378 ( .A(d_ff1_Z[21]), .B(data_in[21]), .S0(n1512), .Y(n1312) );
MX2X4TS U3379 ( .A(d_ff1_Z[22]), .B(data_in[22]), .S0(n3741), .Y(n1311) );
MX2X4TS U3380 ( .A(d_ff1_Z[24]), .B(data_in[24]), .S0(n3741), .Y(n1309) );
MX2X4TS U3381 ( .A(d_ff1_Z[25]), .B(data_in[25]), .S0(n3740), .Y(n1308) );
MX2X4TS U3382 ( .A(d_ff1_Z[26]), .B(data_in[26]), .S0(n3740), .Y(n1307) );
NAND2X4TS U3383 ( .A(n3744), .B(d_ff2_Z[20]), .Y(n2813) );
NAND2X4TS U3384 ( .A(n1580), .B(d_ff2_Z[21]), .Y(n2800) );
NAND2X4TS U3385 ( .A(n1580), .B(d_ff2_Z[22]), .Y(n2805) );
NAND2X1TS U3386 ( .A(n1583), .B(n2263), .Y(n2712) );
INVX2TS U3387 ( .A(n2424), .Y(n2425) );
INVX2TS U3388 ( .A(n2426), .Y(n2427) );
INVX2TS U3389 ( .A(n2428), .Y(n2429) );
INVX2TS U3390 ( .A(n2432), .Y(n2433) );
INVX2TS U3391 ( .A(n2434), .Y(n2435) );
INVX2TS U3392 ( .A(n2436), .Y(n2437) );
MXI2X4TS U3393 ( .A(n4294), .B(n4293), .S0(n4292), .Y(n3058) );
MXI2X4TS U3394 ( .A(n4409), .B(n4408), .S0(n4407), .Y(n3024) );
NAND2X4TS U3395 ( .A(n1593), .B(n1564), .Y(n2549) );
MXI2X4TS U3396 ( .A(n4287), .B(n4286), .S0(n1953), .Y(n3280) );
MX2X4TS U3397 ( .A(d_ff1_Z[9]), .B(data_in[9]), .S0(n3715), .Y(n1324) );
MX2X4TS U3398 ( .A(d_ff1_Z[18]), .B(data_in[18]), .S0(n3715), .Y(n1315) );
INVX2TS U3399 ( .A(n2439), .Y(n2440) );
INVX2TS U3400 ( .A(n2441), .Y(n2442) );
INVX2TS U3401 ( .A(n2443), .Y(n2444) );
INVX2TS U3402 ( .A(n2445), .Y(n2446) );
INVX2TS U3403 ( .A(n2447), .Y(n2448) );
INVX2TS U3404 ( .A(n2449), .Y(n2450) );
MXI2X4TS U3405 ( .A(n3726), .B(n4519), .S0(n1547), .Y(n683) );
INVX2TS U3406 ( .A(n2451), .Y(n2452) );
INVX2TS U3407 ( .A(n2453), .Y(n2454) );
INVX2TS U3408 ( .A(n2455), .Y(n2456) );
INVX2TS U3409 ( .A(n2457), .Y(n2458) );
INVX2TS U3410 ( .A(n2459), .Y(n2460) );
INVX2TS U3411 ( .A(n2461), .Y(n2462) );
INVX2TS U3412 ( .A(n2463), .Y(n2464) );
INVX2TS U3413 ( .A(n2467), .Y(n2468) );
INVX2TS U3414 ( .A(n2471), .Y(n2472) );
MXI2X4TS U3415 ( .A(n4336), .B(n4335), .S0(n1974), .Y(n3305) );
MXI2X4TS U3416 ( .A(n1884), .B(n4259), .S0(n4258), .Y(n3277) );
NAND2X2TS U3417 ( .A(n2533), .B(n3729), .Y(n3730) );
MXI2X4TS U3418 ( .A(n1914), .B(n4262), .S0(n4261), .Y(n3279) );
MXI2X4TS U3419 ( .A(n1906), .B(n4300), .S0(n1980), .Y(n3278) );
MX2X4TS U3420 ( .A(d_ff1_Z[13]), .B(data_in[13]), .S0(n3715), .Y(n1320) );
MX2X4TS U3421 ( .A(d_ff1_Z[17]), .B(data_in[17]), .S0(n3715), .Y(n1316) );
MX2X4TS U3422 ( .A(d_ff1_Z[33]), .B(data_in[33]), .S0(n3738), .Y(n1300) );
MX2X4TS U3423 ( .A(d_ff1_Z[34]), .B(data_in[34]), .S0(n3741), .Y(n1299) );
MX2X4TS U3424 ( .A(d_ff1_Z[35]), .B(data_in[35]), .S0(n1511), .Y(n1298) );
MX2X4TS U3425 ( .A(d_ff1_Z[36]), .B(data_in[36]), .S0(n3740), .Y(n1297) );
CLKMX2X4TS U3426 ( .A(d_ff1_Z[39]), .B(data_in[39]), .S0(n3741), .Y(n1294)
);
AND2X2TS U3427 ( .A(n2377), .B(n2671), .Y(n2568) );
CLKMX2X4TS U3428 ( .A(d_ff1_Z[41]), .B(data_in[41]), .S0(n3738), .Y(n1292)
);
AND2X4TS U3429 ( .A(d_ff1_Z[41]), .B(n2671), .Y(n2569) );
AND2X2TS U3430 ( .A(n2376), .B(n2671), .Y(n2567) );
MX2X4TS U3431 ( .A(d_ff1_Z[53]), .B(data_in[53]), .S0(n3738), .Y(n1280) );
MX2X4TS U3432 ( .A(d_ff1_Z[55]), .B(data_in[55]), .S0(n1512), .Y(n1278) );
NAND2X4TS U3433 ( .A(n2546), .B(n3621), .Y(n3317) );
NAND3X2TS U3434 ( .A(n2538), .B(d_ff1_Z[54]), .C(n2885), .Y(n2780) );
INVX2TS U3435 ( .A(n2474), .Y(n2475) );
INVX2TS U3436 ( .A(n2476), .Y(n2477) );
MXI2X2TS U3437 ( .A(n3902), .B(n2477), .S0(n3725), .Y(n643) );
INVX2TS U3438 ( .A(n2478), .Y(n2479) );
INVX2TS U3439 ( .A(n2480), .Y(n2481) );
MXI2X2TS U3440 ( .A(n4557), .B(n4556), .S0(n3684), .Y(n637) );
INVX2TS U3441 ( .A(n2482), .Y(n2483) );
MXI2X2TS U3442 ( .A(n2483), .B(n3946), .S0(n3684), .Y(n635) );
INVX2TS U3443 ( .A(n2484), .Y(n2485) );
OAI2BB1X4TS U3444 ( .A0N(d_ff2_X[15]), .A1N(n3033), .B0(n3030), .Y(n666) );
OAI2BB1X4TS U3445 ( .A0N(d_ff2_X[18]), .A1N(n3046), .B0(n3037), .Y(n660) );
OAI2BB1X4TS U3446 ( .A0N(d_ff2_X[17]), .A1N(n3046), .B0(n3042), .Y(n662) );
OAI2BB1X4TS U3447 ( .A0N(d_ff2_X[16]), .A1N(n3046), .B0(n3045), .Y(n664) );
NOR2X4TS U3448 ( .A(n3705), .B(n2318), .Y(n3553) );
OAI21X4TS U3449 ( .A0(n2155), .A1(n2278), .B0(n2493), .Y(n951) );
OAI21X4TS U3450 ( .A0(n2155), .A1(n2135), .B0(n2494), .Y(n947) );
NAND3X2TS U3451 ( .A(n2658), .B(n2657), .C(n2656), .Y(n844) );
AOI22X4TS U3452 ( .A0(n1595), .A1(n3907), .B0(n2511), .B1(n2112), .Y(n634)
);
BUFX20TS U3453 ( .A(n2522), .Y(n2539) );
OAI21X4TS U3454 ( .A0(n2155), .A1(n1976), .B0(n2956), .Y(n949) );
OAI21X4TS U3455 ( .A0(n1514), .A1(n1954), .B0(n2497), .Y(n985) );
NAND2X2TS U3456 ( .A(n1583), .B(d_ff2_Z[36]), .Y(n2719) );
AOI22X2TS U3457 ( .A0(n1516), .A1(n3639), .B0(n1724), .B1(sign_inv_out[4]),
.Y(n2916) );
AOI22X2TS U3458 ( .A0(n1515), .A1(n3663), .B0(n1543), .B1(sign_inv_out[3]),
.Y(n2914) );
AOI22X2TS U3459 ( .A0(n1515), .A1(n3666), .B0(sign_inv_out[6]), .B1(n1724),
.Y(n2913) );
BUFX20TS U3460 ( .A(n2955), .Y(n4476) );
NAND2X2TS U3461 ( .A(n2849), .B(n2512), .Y(n2777) );
OAI21X4TS U3462 ( .A0(n3903), .A1(n2536), .B0(n3667), .Y(n715) );
NAND2X1TS U3463 ( .A(n3659), .B(n2498), .Y(n2846) );
NAND2X4TS U3464 ( .A(n1520), .B(n1530), .Y(n3198) );
NOR2X2TS U3465 ( .A(n1759), .B(n3214), .Y(n2926) );
OAI2BB1X4TS U3466 ( .A0N(d_ff2_Y[40]), .A1N(n3303), .B0(n3298), .Y(n744) );
AOI22X2TS U3467 ( .A0(n1516), .A1(n3641), .B0(sign_inv_out[10]), .B1(n1543),
.Y(n3067) );
OAI2BB1X4TS U3468 ( .A0N(n2020), .A1N(n1717), .B0(n3067), .Y(n1053) );
BUFX20TS U3469 ( .A(n2522), .Y(n2974) );
CLKBUFX2TS U3470 ( .A(n2130), .Y(n2500) );
NAND2X2TS U3471 ( .A(n3659), .B(n2581), .Y(n2808) );
OAI2BB1X4TS U3472 ( .A0N(d_ff2_X[21]), .A1N(n3751), .B0(n3048), .Y(n654) );
AOI22X2TS U3473 ( .A0(n3691), .A1(n3677), .B0(n2504), .B1(sign_inv_out[57]),
.Y(n2864) );
AOI22X2TS U3474 ( .A0(n2557), .A1(sign_inv_out[48]), .B0(n3656), .B1(n3703),
.Y(n2505) );
AOI22X2TS U3475 ( .A0(n2557), .A1(sign_inv_out[42]), .B0(n3671), .B1(n3696),
.Y(n2507) );
INVX12TS U3476 ( .A(n2682), .Y(n4470) );
OAI2BB1X4TS U3477 ( .A0N(d_ff2_Y[20]), .A1N(n3046), .B0(n3004), .Y(n784) );
OAI2BB1X4TS U3478 ( .A0N(d_ff2_Y[19]), .A1N(n3046), .B0(n3026), .Y(n786) );
AOI22X2TS U3479 ( .A0(n1588), .A1(sign_inv_out[27]), .B0(n3626), .B1(n3698),
.Y(n2892) );
NAND2X2TS U3480 ( .A(n3724), .B(n3581), .Y(n2782) );
BUFX20TS U3481 ( .A(n2522), .Y(n2739) );
BUFX20TS U3482 ( .A(n1642), .Y(n2557) );
INVX12TS U3483 ( .A(n2801), .Y(n3751) );
OAI21X4TS U3484 ( .A0(n2849), .A1(n3912), .B0(n3658), .Y(n582) );
MXI2X4TS U3485 ( .A(n4344), .B(n4343), .S0(n2043), .Y(n3282) );
MXI2X4TS U3486 ( .A(n1939), .B(n4328), .S0(n1966), .Y(n3287) );
MXI2X4TS U3487 ( .A(n4275), .B(n4274), .S0(n1953), .Y(n3286) );
MXI2X4TS U3488 ( .A(n1882), .B(n4309), .S0(n4308), .Y(n3625) );
NAND3X4TS U3489 ( .A(n2785), .B(n2784), .C(n2783), .Y(n827) );
NAND2X1TS U3490 ( .A(n2845), .B(n2514), .Y(n2718) );
NAND2X1TS U3491 ( .A(n2849), .B(n2517), .Y(n2730) );
NAND2X1TS U3492 ( .A(n2845), .B(n2518), .Y(n2740) );
INVX8TS U3493 ( .A(n2235), .Y(n3743) );
OAI2BB1X4TS U3494 ( .A0N(d_ff2_Y[35]), .A1N(n1507), .B0(n3289), .Y(n754) );
AOI2BB2X4TS U3495 ( .B0(n2069), .B1(n1592), .A0N(n2536), .A1N(d_ff2_X[8]),
.Y(n680) );
AOI2BB2X4TS U3496 ( .B0(n2075), .B1(n2573), .A0N(n3659), .A1N(d_ff2_X[9]),
.Y(n678) );
AOI2BB2X4TS U3497 ( .B0(n2074), .B1(n1643), .A0N(n2536), .A1N(d_ff2_X[19]),
.Y(n658) );
AOI2BB2X4TS U3498 ( .B0(n2546), .B1(n2062), .A0N(n3001), .A1N(d_ff2_X[13]),
.Y(n670) );
BUFX20TS U3499 ( .A(n2521), .Y(n2520) );
BUFX20TS U3500 ( .A(n2148), .Y(n2522) );
NAND2BX4TS U3501 ( .AN(n2523), .B(n2863), .Y(n887) );
NAND3X2TS U3502 ( .A(n2526), .B(d_ff1_Z[18]), .C(n2970), .Y(n2855) );
NAND2BX4TS U3503 ( .AN(n2525), .B(n2850), .Y(n876) );
NAND2X2TS U3504 ( .A(n2739), .B(n3592), .Y(n2853) );
NAND2X8TS U3505 ( .A(n2527), .B(n2605), .Y(n2609) );
AO21X4TS U3506 ( .A0(d_ff3_LUT_out[41]), .A1(n2590), .B0(n3650), .Y(n904) );
NOR2X8TS U3507 ( .A(n3707), .B(n3722), .Y(n3649) );
OAI2BB1X4TS U3508 ( .A0N(n3282), .A1N(n2911), .B0(n2907), .Y(n1063) );
OAI2BB1X4TS U3509 ( .A0N(n3286), .A1N(n2911), .B0(n2913), .Y(n1061) );
INVX16TS U3510 ( .A(n2121), .Y(n3731) );
NAND2X2TS U3511 ( .A(n2878), .B(d_ff2_Z[39]), .Y(n2645) );
NAND2X2TS U3512 ( .A(n1583), .B(d_ff2_Z[42]), .Y(n2648) );
AND3X8TS U3513 ( .A(n1602), .B(n3708), .C(n3692), .Y(n2555) );
NAND2BX4TS U3514 ( .AN(n2534), .B(n2856), .Y(n871) );
OAI2BB1X4TS U3515 ( .A0N(n3577), .A1N(n2573), .B0(n2855), .Y(n2534) );
OAI2BB1X4TS U3516 ( .A0N(d_ff2_Y[47]), .A1N(n3751), .B0(n3308), .Y(n730) );
OAI2BB1X4TS U3517 ( .A0N(d_ff2_Y[48]), .A1N(n1595), .B0(n3310), .Y(n728) );
OAI2BB1X4TS U3518 ( .A0N(d_ff2_Y[49]), .A1N(n1585), .B0(n3312), .Y(n726) );
OAI2BB1X4TS U3519 ( .A0N(d_ff2_Y[50]), .A1N(n3751), .B0(n3306), .Y(n724) );
OAI2BB1X4TS U3520 ( .A0N(d_ff2_Y[8]), .A1N(n3044), .B0(n3014), .Y(n808) );
NAND2BX4TS U3521 ( .AN(n1637), .B(n2125), .Y(n2994) );
BUFX20TS U3522 ( .A(n2537), .Y(n2538) );
AOI2BB2X4TS U3523 ( .B0(n2542), .B1(n2536), .A0N(n2536), .A1N(n2169), .Y(
n2541) );
BUFX20TS U3524 ( .A(n2520), .Y(n2543) );
AOI22X4TS U3525 ( .A0(n2149), .A1(n3908), .B0(n2543), .B1(n2097), .Y(n632)
);
AOI2BB2X4TS U3526 ( .B0(n3743), .B1(n2630), .A0N(n2554), .A1N(n3699), .Y(
n618) );
AOI2BB2X4TS U3527 ( .B0(n4590), .B1(n3751), .A0N(n2554), .A1N(n3697), .Y(
n598) );
AOI2BB2X4TS U3528 ( .B0(n2405), .B1(n1595), .A0N(n2554), .A1N(n2551), .Y(
n600) );
AOI2BB2X4TS U3529 ( .B0(n3775), .B1(n2878), .A0N(n2554), .A1N(n1650), .Y(
n606) );
AOI2BB2X4TS U3530 ( .B0(n3743), .B1(n3776), .A0N(n2554), .A1N(n1647), .Y(
n604) );
AOI2BB2X4TS U3531 ( .B0(n3743), .B1(n3774), .A0N(n2554), .A1N(n1648), .Y(
n610) );
AOI2BB2X4TS U3532 ( .B0(n3743), .B1(n1570), .A0N(n2554), .A1N(n2552), .Y(
n612) );
NAND3X2TS U3533 ( .A(n2538), .B(d_ff1_Z[60]), .C(n2363), .Y(n2875) );
NAND3X2TS U3534 ( .A(n2538), .B(d_ff1_Z[61]), .C(n2363), .Y(n2879) );
NAND3X2TS U3535 ( .A(n2538), .B(d_ff1_Z[63]), .C(n2975), .Y(n2866) );
NAND3X2TS U3536 ( .A(n3659), .B(d_ff1_Z[58]), .C(n2885), .Y(n2869) );
NAND3X2TS U3537 ( .A(n2538), .B(n2440), .C(n2885), .Y(n2872) );
NAND3X2TS U3538 ( .A(n2526), .B(d_ff1_Z[56]), .C(n2885), .Y(n2882) );
NOR2X8TS U3539 ( .A(n2560), .B(n3324), .Y(n3645) );
INVX16TS U3540 ( .A(n2121), .Y(n3715) );
CLKINVX12TS U3541 ( .A(n4476), .Y(n2901) );
OAI2BB1X4TS U3542 ( .A0N(n3744), .A1N(d_ff2_X[44]), .B0(n3318), .Y(n608) );
OAI2BB1X4TS U3543 ( .A0N(n3744), .A1N(d_ff2_X[47]), .B0(n3317), .Y(n602) );
NAND3X4TS U3544 ( .A(n2084), .B(n2083), .C(n2082), .Y(n574) );
NAND2X8TS U3545 ( .A(n3049), .B(ack_add_subt), .Y(n3717) );
OAI2BB1X2TS U3546 ( .A0N(n1982), .A1N(n1717), .B0(n2700), .Y(n1003) );
OAI2BB1X2TS U3547 ( .A0N(n3293), .A1N(n1718), .B0(n2903), .Y(n1007) );
OAI2BB1X2TS U3548 ( .A0N(n2041), .A1N(n2901), .B0(n2902), .Y(n1005) );
OAI2BB1X2TS U3549 ( .A0N(n1964), .A1N(n1717), .B0(n2904), .Y(n1009) );
NOR2X4TS U3550 ( .A(n3747), .B(n2559), .Y(n2558) );
OAI2BB1X4TS U3551 ( .A0N(n2561), .A1N(n2560), .B0(n3646), .Y(n892) );
OAI2BB1X4TS U3552 ( .A0N(d_ff2_Y[16]), .A1N(n3046), .B0(n2995), .Y(n792) );
NAND2X1TS U3553 ( .A(n2849), .B(n2182), .Y(n2958) );
NAND2X1TS U3554 ( .A(n3659), .B(n2183), .Y(n2961) );
OAI2BB1X2TS U3555 ( .A0N(n3280), .A1N(n1718), .B0(n2905), .Y(n1011) );
NAND2X1TS U3556 ( .A(n2849), .B(n2562), .Y(n2829) );
NAND2X1TS U3557 ( .A(n2845), .B(n2184), .Y(n2964) );
NAND2X1TS U3558 ( .A(n2839), .B(n2185), .Y(n2967) );
NAND2X1TS U3559 ( .A(n2849), .B(n2186), .Y(n2976) );
NAND3X2TS U3560 ( .A(n2536), .B(d_ff1_Z[59]), .C(n2363), .Y(n2678) );
OAI2BB1X4TS U3561 ( .A0N(n2865), .A1N(n2588), .B0(n2864), .Y(n959) );
OAI2BB1X4TS U3562 ( .A0N(n3305), .A1N(n2924), .B0(n2920), .Y(n973) );
OAI2BB1X4TS U3563 ( .A0N(n3729), .A1N(n2901), .B0(n2917), .Y(n969) );
OAI2BB1X4TS U3564 ( .A0N(n3277), .A1N(n2911), .B0(n2918), .Y(n971) );
NAND2X4TS U3565 ( .A(n3193), .B(n3706), .Y(n919) );
OAI2BB1X4TS U3566 ( .A0N(n3287), .A1N(n2911), .B0(n2914), .Y(n1067) );
NAND2X4TS U3567 ( .A(n3256), .B(n3255), .Y(n3257) );
MXI2X4TS U3568 ( .A(n2326), .B(n4016), .S0(n2294), .Y(n1054) );
MXI2X4TS U3569 ( .A(n2329), .B(n4026), .S0(n2295), .Y(n1034) );
MXI2X4TS U3570 ( .A(n2331), .B(n4036), .S0(n2289), .Y(n1014) );
MXI2X4TS U3571 ( .A(n2337), .B(n4056), .S0(n2295), .Y(n974) );
MXI2X4TS U3572 ( .A(n2339), .B(n4066), .S0(n2292), .Y(n954) );
NAND2X2TS U3573 ( .A(n2138), .B(n3227), .Y(n2775) );
MXI2X4TS U3574 ( .A(n3194), .B(d_ff3_LUT_out[15]), .S0(n3707), .Y(n3195) );
AOI21X2TS U3575 ( .A0(n2101), .A1(n2624), .B0(n3323), .Y(n4599) );
MXI2X4TS U3576 ( .A(n3914), .B(n2475), .S0(n2229), .Y(n667) );
AOI21X4TS U3577 ( .A0(d_ff3_LUT_out[33]), .A1(n2624), .B0(n3709), .Y(n2981)
);
NAND3X2TS U3578 ( .A(n2536), .B(d_ff1_Z[47]), .C(n2671), .Y(n2668) );
NAND3X2TS U3579 ( .A(n2536), .B(d_ff1_Z[48]), .C(n2671), .Y(n2672) );
NAND3X2TS U3580 ( .A(n2570), .B(d_ff1_Z[1]), .C(n2975), .Y(n2857) );
NAND2X8TS U3581 ( .A(n3683), .B(n3234), .Y(n3485) );
NOR2BX4TS U3582 ( .AN(n2636), .B(n2574), .Y(n3763) );
MXI2X4TS U3583 ( .A(n1668), .B(n3227), .S0(n3717), .Y(n3229) );
NAND2X4TS U3584 ( .A(n3275), .B(n3706), .Y(n937) );
MXI2X4TS U3585 ( .A(n3778), .B(n3922), .S0(n2619), .Y(n569) );
NOR2BX4TS U3586 ( .AN(d_ff1_Z[19]), .B(n2579), .Y(n2578) );
MXI2X4TS U3587 ( .A(n4534), .B(n3919), .S0(n1494), .Y(n663) );
MXI2X4TS U3588 ( .A(n4541), .B(n3248), .S0(n1519), .Y(n653) );
NOR2BX4TS U3589 ( .AN(d_ff1_Z[15]), .B(n2564), .Y(n2581) );
NOR2BX4TS U3590 ( .AN(d_ff1_Z[21]), .B(n2579), .Y(n2583) );
NOR2BX4TS U3591 ( .AN(d_ff1_Z[22]), .B(n2579), .Y(n2584) );
NOR2BX4TS U3592 ( .AN(d_ff1_Z[20]), .B(n2579), .Y(n2585) );
MXI2X4TS U3593 ( .A(n3932), .B(n3786), .S0(n2230), .Y(n783) );
MXI2X4TS U3594 ( .A(n3930), .B(n3784), .S0(n2230), .Y(n793) );
NAND3X2TS U3595 ( .A(n2845), .B(d_ff1_Z[23]), .C(n2363), .Y(n2820) );
NAND3X2TS U3596 ( .A(n2839), .B(n2442), .C(n2363), .Y(n2783) );
NAND3X2TS U3597 ( .A(n2845), .B(d_ff1_Z[9]), .C(n2970), .Y(n2971) );
OAI22X4TS U3598 ( .A0(n2641), .A1(n3274), .B0(n2613), .B1(d_ff3_LUT_out[9]),
.Y(n2642) );
MXI2X4TS U3599 ( .A(n3931), .B(n3785), .S0(n2619), .Y(n791) );
MXI2X4TS U3600 ( .A(n4532), .B(n3918), .S0(n1644), .Y(n665) );
NAND2X6TS U3601 ( .A(n3489), .B(n2926), .Y(n3216) );
BUFX12TS U3602 ( .A(n3727), .Y(n2590) );
MXI2X2TS U3603 ( .A(n3783), .B(n3929), .S0(n2365), .Y(n815) );
XOR2X4TS U3604 ( .A(n2593), .B(n2320), .Y(n3265) );
XOR2X4TS U3605 ( .A(n2323), .B(n2298), .Y(n2593) );
MXI2X4TS U3606 ( .A(n2479), .B(n3945), .S0(n2594), .Y(n641) );
OAI22X4TS U3607 ( .A0(n1494), .A1(n576), .B0(n1658), .B1(n2597), .Y(n2596)
);
NAND2BX4TS U3608 ( .AN(n3330), .B(n2943), .Y(n2598) );
OAI21X4TS U3609 ( .A0(n2602), .A1(n2601), .B0(n2600), .Y(n2982) );
AOI21X4TS U3610 ( .A0(n2693), .A1(n2692), .B0(n3215), .Y(n2600) );
OAI21X4TS U3611 ( .A0(n3732), .A1(n2693), .B0(n2692), .Y(n2604) );
NAND2X8TS U3612 ( .A(n2640), .B(n2760), .Y(n2930) );
NOR2X8TS U3613 ( .A(n2379), .B(n2951), .Y(n2760) );
INVX16TS U3614 ( .A(n2614), .Y(n2618) );
AND4X8TS U3615 ( .A(n2616), .B(n2615), .C(n2667), .D(n2617), .Y(n2614) );
OAI2BB1X4TS U3616 ( .A0N(d_ff3_LUT_out[22]), .A1N(n2590), .B0(n3706), .Y(
n923) );
NOR2BX4TS U3617 ( .AN(n3272), .B(n2925), .Y(n3068) );
AOI22X1TS U3618 ( .A0(n3694), .A1(n2138), .B0(n3693), .B1(n2624), .Y(n4524)
);
MXI2X4TS U3619 ( .A(n2587), .B(n3956), .S0(n1658), .Y(n894) );
MXI2X2TS U3620 ( .A(n3773), .B(n2448), .S0(n2365), .Y(n689) );
MXI2X4TS U3621 ( .A(n3810), .B(n3963), .S0(n1571), .Y(n801) );
OAI21X2TS U3622 ( .A0(n1513), .A1(n2367), .B0(n3220), .Y(n979) );
NAND3X4TS U3623 ( .A(n2993), .B(n2776), .C(n2775), .Y(n931) );
MXI2X4TS U3624 ( .A(n3780), .B(n3925), .S0(n2229), .Y(n823) );
NOR2X8TS U3625 ( .A(n3735), .B(n3214), .Y(n3709) );
NAND2X4TS U3626 ( .A(n2573), .B(n1963), .Y(n2996) );
NAND2X4TS U3627 ( .A(n2573), .B(n3631), .Y(n3028) );
OAI2BB1X4TS U3628 ( .A0N(d_ff2_Y[7]), .A1N(n3044), .B0(n3017), .Y(n810) );
INVX16TS U3629 ( .A(n3001), .Y(n3044) );
MXI2X2TS U3630 ( .A(n3943), .B(n2460), .S0(n2229), .Y(n671) );
MXI2X2TS U3631 ( .A(n3942), .B(n2456), .S0(n2365), .Y(n675) );
MXI2X2TS U3632 ( .A(n3818), .B(n4539), .S0(n2365), .Y(n655) );
MXI2X2TS U3633 ( .A(n3898), .B(n2462), .S0(n3651), .Y(n669) );
MXI2X2TS U3634 ( .A(n3815), .B(n2464), .S0(n2365), .Y(n661) );
MXI2X4TS U3635 ( .A(n3814), .B(n3967), .S0(n2229), .Y(n789) );
MXI2X4TS U3636 ( .A(n3811), .B(n3964), .S0(n1571), .Y(n799) );
MXI2X4TS U3637 ( .A(n3805), .B(n3958), .S0(n2589), .Y(n811) );
MXI2X4TS U3638 ( .A(n3787), .B(n3704), .S0(n1571), .Y(n777) );
MXI2X2TS U3639 ( .A(n3920), .B(n4543), .S0(n3252), .Y(n651) );
MXI2X2TS U3640 ( .A(n3817), .B(n2466), .S0(n2365), .Y(n659) );
MXI2X4TS U3641 ( .A(n3819), .B(n3969), .S0(n2589), .Y(n779) );
OAI21X2TS U3642 ( .A0(n1713), .A1(n2255), .B0(n3261), .Y(n710) );
AOI22X2TS U3643 ( .A0(n2533), .A1(n2070), .B0(n3744), .B1(n3892), .Y(n591)
);
NAND2X4TS U3644 ( .A(n2533), .B(n3297), .Y(n3298) );
NAND2X2TS U3645 ( .A(n1519), .B(n3486), .Y(n3487) );
OAI2BB1X4TS U3646 ( .A0N(d_ff3_LUT_out[40]), .A1N(n2624), .B0(n3718), .Y(
n905) );
AOI22X2TS U3647 ( .A0(n2543), .A1(n2132), .B0(n1584), .B1(n3773), .Y(n690)
);
AOI22X2TS U3648 ( .A0(n3712), .A1(n1644), .B0(n1668), .B1(n3709), .Y(n4508)
);
OAI2BB1X4TS U3649 ( .A0N(d_ff2_Y[9]), .A1N(n3033), .B0(n3027), .Y(n806) );
OAI2BB1X4TS U3650 ( .A0N(d_ff2_Y[10]), .A1N(n3033), .B0(n3011), .Y(n804) );
OAI2BB1X4TS U3651 ( .A0N(d_ff2_Y[11]), .A1N(n3033), .B0(n3018), .Y(n802) );
OAI2BB1X4TS U3652 ( .A0N(d_ff2_Y[13]), .A1N(n3033), .B0(n3020), .Y(n798) );
MXI2X4TS U3653 ( .A(n3779), .B(n3926), .S0(n2365), .Y(n821) );
NAND3X2TS U3654 ( .A(n3315), .B(n1550), .C(n2180), .Y(n902) );
OAI21X2TS U3655 ( .A0(n2536), .A1(n3913), .B0(n3673), .Y(n714) );
NAND2X4TS U3656 ( .A(n3260), .B(n1700), .Y(n3261) );
AOI22X2TS U3657 ( .A0(n3691), .A1(n3643), .B0(sign_inv_out[25]), .B1(n2557),
.Y(n2887) );
NAND2X4TS U3658 ( .A(n1982), .B(n2383), .Y(n3289) );
OAI2BB1X4TS U3659 ( .A0N(d_ff2_X[10]), .A1N(n3033), .B0(n3029), .Y(n676) );
OAI2BB1X4TS U3660 ( .A0N(d_ff2_X[12]), .A1N(n3033), .B0(n3032), .Y(n672) );
INVX16TS U3661 ( .A(n3001), .Y(n3033) );
BUFX20TS U3662 ( .A(n2655), .Y(n2801) );
NAND2X4TS U3663 ( .A(n2573), .B(n3643), .Y(n3036) );
OAI2BB1X4TS U3664 ( .A0N(d_ff2_Y[23]), .A1N(n1580), .B0(n3022), .Y(n778) );
NAND2X4TS U3665 ( .A(n2573), .B(n1652), .Y(n3022) );
OAI2BB1X2TS U3666 ( .A0N(d_ff2_Y[36]), .A1N(n3303), .B0(n3302), .Y(n752) );
OAI2BB1X2TS U3667 ( .A0N(d_ff2_Y[37]), .A1N(n3303), .B0(n3291), .Y(n750) );
BUFX20TS U3668 ( .A(n3254), .Y(n4474) );
OAI2BB1X4TS U3669 ( .A0N(d_ff3_LUT_out[36]), .A1N(n2365), .B0(n3718), .Y(
n909) );
MXI2X4TS U3670 ( .A(n3257), .B(n3792), .S0(n2589), .Y(n893) );
MXI2X4TS U3671 ( .A(n2773), .B(n3793), .S0(n3747), .Y(n708) );
MXI2X4TS U3672 ( .A(n3791), .B(n3770), .S0(n3705), .Y(n697) );
MXI2X2TS U3673 ( .A(n3944), .B(n4545), .S0(n2229), .Y(n649) );
MXI2X4TS U3674 ( .A(n3816), .B(n3968), .S0(n1547), .Y(n787) );
MXI2X2TS U3675 ( .A(n3941), .B(n2450), .S0(n2365), .Y(n685) );
MXI2X2TS U3676 ( .A(n3895), .B(n2452), .S0(n3651), .Y(n681) );
MXI2X4TS U3677 ( .A(n3809), .B(n3962), .S0(n1571), .Y(n803) );
MXI2X4TS U3678 ( .A(n3812), .B(n3965), .S0(n1571), .Y(n797) );
BUFX20TS U3679 ( .A(n2912), .Y(n3696) );
MXI2X4TS U3680 ( .A(n3782), .B(n3928), .S0(n2589), .Y(n817) );
MXI2X4TS U3681 ( .A(n3804), .B(n3957), .S0(n2589), .Y(n813) );
MXI2X4TS U3682 ( .A(n3806), .B(n3959), .S0(n2590), .Y(n809) );
INVX16TS U3683 ( .A(n2699), .Y(n2912) );
AND2X8TS U3684 ( .A(n2796), .B(n3049), .Y(n3253) );
NAND2X4TS U3685 ( .A(n3060), .B(n2546), .Y(n3018) );
NAND2X4TS U3686 ( .A(n2020), .B(n2511), .Y(n3011) );
MXI2X4TS U3687 ( .A(n3790), .B(n3935), .S0(n3252), .Y(n769) );
MXI2X2TS U3688 ( .A(n3901), .B(n2468), .S0(n3736), .Y(n647) );
MXI2X4TS U3689 ( .A(n3824), .B(n3974), .S0(n2629), .Y(n757) );
MXI2X4TS U3690 ( .A(n3825), .B(n3975), .S0(n2624), .Y(n755) );
MXI2X4TS U3691 ( .A(n3826), .B(n3976), .S0(n1709), .Y(n753) );
MXI2X4TS U3692 ( .A(n3827), .B(n3977), .S0(n1709), .Y(n751) );
MXI2X4TS U3693 ( .A(n3803), .B(n3984), .S0(n3736), .Y(n737) );
MXI2X4TS U3694 ( .A(n3832), .B(n3986), .S0(n3736), .Y(n733) );
MXI2X4TS U3695 ( .A(n3813), .B(n3966), .S0(n2590), .Y(n795) );
MXI2X4TS U3696 ( .A(n3808), .B(n3961), .S0(n2589), .Y(n805) );
MXI2X4TS U3697 ( .A(n3781), .B(n3927), .S0(n1547), .Y(n819) );
OAI21X2TS U3698 ( .A0(n2629), .A1(n3493), .B0(n3492), .Y(n4618) );
AOI21X2TS U3699 ( .A0(d_ff2_Y[57]), .A1(d_ff2_Y[56]), .B0(n3551), .Y(n3323)
);
BUFX20TS U3700 ( .A(n2316), .Y(n3489) );
MXI2X4TS U3701 ( .A(n1521), .B(n3955), .S0(n1571), .Y(n908) );
AO21X4TS U3702 ( .A0(d_ff3_LUT_out[42]), .A1(n3707), .B0(n3544), .Y(n903) );
AO21X4TS U3703 ( .A0(d_ff3_LUT_out[47]), .A1(n3707), .B0(n3544), .Y(n898) );
MXI2X4TS U3704 ( .A(n3829), .B(n3979), .S0(n1709), .Y(n747) );
MXI2X4TS U3705 ( .A(n3800), .B(n3980), .S0(n3707), .Y(n745) );
MXI2X4TS U3706 ( .A(n3830), .B(n3981), .S0(n3252), .Y(n743) );
MXI2X4TS U3707 ( .A(n3801), .B(n3982), .S0(n2590), .Y(n741) );
MXI2X4TS U3708 ( .A(n3953), .B(n3799), .S0(n3736), .Y(n721) );
MXI2X4TS U3709 ( .A(n3951), .B(n3798), .S0(n3736), .Y(n727) );
MXI2X4TS U3710 ( .A(n3834), .B(n3988), .S0(n3736), .Y(n729) );
MXI2X4TS U3711 ( .A(n3835), .B(n3989), .S0(n3736), .Y(n725) );
MXI2X4TS U3712 ( .A(n3836), .B(n3990), .S0(n3736), .Y(n723) );
MXI2X4TS U3713 ( .A(n3266), .B(n2500), .S0(n3264), .Y(n1269) );
AO21X4TS U3714 ( .A0(d_ff3_LUT_out[46]), .A1(n3707), .B0(n1602), .Y(n899) );
AO21X4TS U3715 ( .A0(d_ff3_LUT_out[44]), .A1(n3747), .B0(n1602), .Y(n901) );
AO21X4TS U3716 ( .A0(d_ff3_LUT_out[49]), .A1(n3707), .B0(n1602), .Y(n896) );
MXI2X4TS U3717 ( .A(n3828), .B(n3978), .S0(n3707), .Y(n749) );
NAND2X8TS U3718 ( .A(n2986), .B(n3489), .Y(n3718) );
INVX16TS U3719 ( .A(n3549), .Y(n3747) );
OR2X8TS U3720 ( .A(n2349), .B(n1762), .Y(n2632) );
NAND2X1TS U3721 ( .A(n3521), .B(d_ff2_Z[23]), .Y(n3419) );
OAI21X1TS U3722 ( .A0(n2090), .A1(n3384), .B0(n3336), .Y(add_subt_dataB[0])
);
BUFX20TS U3731 ( .A(n2370), .Y(n2789) );
BUFX20TS U3732 ( .A(n2357), .Y(n2951) );
NAND2X4TS U3733 ( .A(n2642), .B(n4526), .Y(n936) );
NAND3X2TS U3734 ( .A(n2646), .B(n2644), .C(n2645), .Y(n850) );
NAND3X2TS U3735 ( .A(n2649), .B(n2647), .C(n2648), .Y(n847) );
NAND3X2TS U3736 ( .A(n2651), .B(n2650), .C(n2652), .Y(n849) );
NAND3X1TS U3737 ( .A(n2537), .B(d_ff1_Z[45]), .C(n2671), .Y(n2656) );
MXI2X2TS U3738 ( .A(n4209), .B(n4208), .S0(n1924), .Y(n3582) );
NAND3X1TS U3739 ( .A(n2537), .B(d_ff1_Z[44]), .C(n2671), .Y(n2659) );
NAND3X1TS U3740 ( .A(n1517), .B(n2537), .C(n2671), .Y(n2661) );
NAND3X2TS U3741 ( .A(n2663), .B(n2662), .C(n2661), .Y(n843) );
NAND3X1TS U3742 ( .A(d_ff1_Z[43]), .B(n2537), .C(n2671), .Y(n2664) );
NOR2X8TS U3743 ( .A(n3214), .B(n3648), .Y(n2795) );
NAND2X2TS U3744 ( .A(n2936), .B(n3910), .Y(n2667) );
NAND3X2TS U3745 ( .A(n2670), .B(n2669), .C(n2668), .Y(n842) );
NAND3X2TS U3746 ( .A(n2674), .B(n2673), .C(n2672), .Y(n841) );
NAND2X1TS U3747 ( .A(n2539), .B(n3612), .Y(n2677) );
NAND3X2TS U3748 ( .A(n2676), .B(n2677), .C(n2675), .Y(n840) );
NAND3X2TS U3749 ( .A(n2679), .B(n2680), .C(n2678), .Y(n830) );
NOR2X1TS U3750 ( .A(n2319), .B(n2298), .Y(n2683) );
NAND2X6TS U3751 ( .A(n2690), .B(n3716), .Y(n2691) );
NAND2X1TS U3752 ( .A(n3047), .B(n3601), .Y(n2707) );
NAND3X2TS U3753 ( .A(n2706), .B(n2707), .C(n2705), .Y(n838) );
NAND3X2TS U3754 ( .A(n2710), .B(n2709), .C(n2708), .Y(n837) );
MXI2X2TS U3755 ( .A(n4168), .B(n4167), .S0(n1924), .Y(n3616) );
NAND3X2TS U3756 ( .A(n2713), .B(n2712), .C(n2711), .Y(n839) );
CLKMX2X4TS U3757 ( .A(n4243), .B(n4242), .S0(n4241), .Y(n3993) );
BUFX8TS U3758 ( .A(n2811), .Y(n2835) );
NAND3X2TS U3759 ( .A(n2719), .B(n2718), .C(n2720), .Y(n853) );
NAND3X1TS U3760 ( .A(n2526), .B(d_ff1_Z[31]), .C(n2835), .Y(n2721) );
NAND3X2TS U3761 ( .A(n2721), .B(n2723), .C(n2722), .Y(n858) );
NAND3X2TS U3762 ( .A(n2730), .B(n2731), .C(n2732), .Y(n855) );
NAND3X1TS U3763 ( .A(n2714), .B(d_ff1_Z[30]), .C(n2835), .Y(n2733) );
NAND3X2TS U3764 ( .A(n2733), .B(n2735), .C(n2734), .Y(n859) );
NAND3X2TS U3765 ( .A(n2736), .B(n2738), .C(n2737), .Y(n857) );
NAND2X1TS U3766 ( .A(n1498), .B(cont_var_out[1]), .Y(n2744) );
NAND2X1TS U3767 ( .A(n3415), .B(d_ff2_Y[28]), .Y(n2747) );
NAND2X1TS U3768 ( .A(n3416), .B(n2267), .Y(n2746) );
BUFX20TS U3769 ( .A(n3339), .Y(n3361) );
NAND2X1TS U3770 ( .A(n3392), .B(d_ff2_X[28]), .Y(n2745) );
NAND3X2TS U3771 ( .A(n2747), .B(n2746), .C(n2745), .Y(add_subt_dataA[28]) );
NAND2X1TS U3772 ( .A(n3415), .B(d_ff2_Y[27]), .Y(n2750) );
NAND2X1TS U3773 ( .A(n3496), .B(n2259), .Y(n2749) );
NAND2X1TS U3774 ( .A(n2401), .B(d_ff2_X[27]), .Y(n2748) );
NAND3X2TS U3775 ( .A(n2750), .B(n2749), .C(n2748), .Y(add_subt_dataA[27]) );
NAND2X1TS U3776 ( .A(n3415), .B(d_ff2_Y[26]), .Y(n2753) );
NAND2X1TS U3777 ( .A(n3521), .B(n2281), .Y(n2752) );
NAND2X1TS U3778 ( .A(n3509), .B(d_ff2_X[26]), .Y(n2751) );
NAND3X2TS U3779 ( .A(n2753), .B(n2752), .C(n2751), .Y(add_subt_dataA[26]) );
NAND2X1TS U3780 ( .A(n3415), .B(d_ff2_Y[25]), .Y(n2756) );
NAND2X1TS U3781 ( .A(n3513), .B(n2268), .Y(n2755) );
NAND2X1TS U3782 ( .A(n3532), .B(d_ff2_X[25]), .Y(n2754) );
NAND3X2TS U3783 ( .A(n2756), .B(n2755), .C(n2754), .Y(add_subt_dataA[25]) );
NAND2X1TS U3784 ( .A(n3415), .B(d_ff2_Y[24]), .Y(n2759) );
NAND2X1TS U3785 ( .A(n3382), .B(n2280), .Y(n2758) );
NAND2X1TS U3786 ( .A(n3527), .B(d_ff2_X[24]), .Y(n2757) );
NAND3X2TS U3787 ( .A(n2759), .B(n2758), .C(n2757), .Y(add_subt_dataA[24]) );
MXI2X2TS U3788 ( .A(n1904), .B(n4381), .S0(n1980), .Y(n2957) );
INVX8TS U3789 ( .A(n2570), .Y(n3303) );
OAI2BB1X2TS U3790 ( .A0N(d_ff2_Y[42]), .A1N(n3303), .B0(n2768), .Y(n740) );
OAI2BB1X2TS U3791 ( .A0N(d_ff2_Y[41]), .A1N(n3303), .B0(n2770), .Y(n742) );
XOR2X1TS U3792 ( .A(n2772), .B(n3745), .Y(n2773) );
OAI21X4TS U3793 ( .A0(n2613), .A1(d_ff3_LUT_out[14]), .B0(n2932), .Y(n2776)
);
NAND3X2TS U3794 ( .A(n2778), .B(n2777), .C(n2779), .Y(n836) );
MXI2X4TS U3795 ( .A(n2786), .B(n3519), .S0(n1535), .Y(n580) );
NAND3X4TS U3796 ( .A(n2788), .B(n2934), .C(n2787), .Y(n938) );
NAND2X4TS U3797 ( .A(n3710), .B(n3070), .Y(n2986) );
AND3X4TS U3798 ( .A(n3722), .B(n1498), .C(n3223), .Y(n2790) );
BUFX8TS U3799 ( .A(n2811), .Y(n2975) );
OAI2BB1X2TS U3800 ( .A0N(d_ff2_X[38]), .A1N(n3303), .B0(n2798), .Y(n620) );
MXI2X2TS U3801 ( .A(n1878), .B(n4185), .S0(n1997), .Y(n3599) );
MXI2X2TS U3802 ( .A(n4172), .B(n4171), .S0(n1997), .Y(n3613) );
MXI2X2TS U3803 ( .A(n1879), .B(n4184), .S0(n2059), .Y(n3600) );
NAND3X2TS U3804 ( .A(n2817), .B(n2818), .C(n2819), .Y(n878) );
MXI2X2TS U3805 ( .A(n1920), .B(n4206), .S0(n2048), .Y(n3560) );
NAND3X1TS U3806 ( .A(n2849), .B(d_ff1_Z[12]), .C(n2970), .Y(n2823) );
NAND3X2TS U3807 ( .A(n2825), .B(n2824), .C(n2823), .Y(n877) );
NAND3X2TS U3808 ( .A(n2827), .B(n2828), .C(n2826), .Y(n862) );
NAND3X2TS U3809 ( .A(n2830), .B(n2829), .C(n2831), .Y(n865) );
NAND3X2TS U3810 ( .A(n2833), .B(n2832), .C(n2834), .Y(n863) );
NAND3X1TS U3811 ( .A(n3659), .B(d_ff1_Z[29]), .C(n2835), .Y(n2836) );
NAND3X2TS U3812 ( .A(n2836), .B(n2837), .C(n2838), .Y(n860) );
NAND3X1TS U3813 ( .A(n2714), .B(d_ff1_Z[14]), .C(n2970), .Y(n2851) );
MXI2X2TS U3814 ( .A(n1922), .B(n4419), .S0(n1924), .Y(n3577) );
NAND3X2TS U3815 ( .A(n2859), .B(n2858), .C(n2857), .Y(n888) );
NAND3X2TS U3816 ( .A(n2868), .B(n2866), .C(n2867), .Y(n826) );
NAND3X2TS U3817 ( .A(n2870), .B(n2871), .C(n2869), .Y(n831) );
NAND2X1TS U3818 ( .A(n2974), .B(n3570), .Y(n2874) );
NAND3X2TS U3819 ( .A(n2874), .B(n2872), .C(n2873), .Y(n832) );
NAND3X2TS U3820 ( .A(n2877), .B(n2875), .C(n2876), .Y(n829) );
NAND3X2TS U3821 ( .A(n2880), .B(n2879), .C(n2881), .Y(n828) );
NAND3X2TS U3822 ( .A(n2884), .B(n2882), .C(n2883), .Y(n833) );
OAI21X2TS U3823 ( .A0(n1513), .A1(n4000), .B0(n2886), .Y(n981) );
CLKMX2X4TS U3824 ( .A(n4246), .B(n4245), .S0(n1966), .Y(n3995) );
OAI21X2TS U3825 ( .A0(n2344), .A1(n4475), .B0(n2893), .Y(n1021) );
INVX16TS U3826 ( .A(n2936), .Y(n3714) );
MXI2X4TS U3827 ( .A(n2942), .B(n2941), .S0(n2940), .Y(n1267) );
NOR2X8TS U3828 ( .A(n1573), .B(d_ff2_X[57]), .Y(n3394) );
INVX2TS U3829 ( .A(d_ff2_X[57]), .Y(n3734) );
OAI2BB1X2TS U3830 ( .A0N(d_ff2_X[37]), .A1N(n3303), .B0(n2945), .Y(n622) );
OAI22X4TS U3831 ( .A0(n2952), .A1(n2499), .B0(n2950), .B1(n3072), .Y(n2953)
);
NAND3X2TS U3832 ( .A(n2958), .B(n2960), .C(n2959), .Y(n882) );
NAND3X2TS U3833 ( .A(n2961), .B(n2963), .C(n2962), .Y(n884) );
NAND3X2TS U3834 ( .A(n2964), .B(n2966), .C(n2965), .Y(n881) );
NAND3X2TS U3835 ( .A(n2967), .B(n2969), .C(n2968), .Y(n885) );
NAND3X2TS U3836 ( .A(n2976), .B(n2978), .C(n2977), .Y(n883) );
NOR2X4TS U3837 ( .A(n2984), .B(n2983), .Y(n2985) );
NOR2X1TS U3838 ( .A(n3245), .B(n1504), .Y(n2988) );
NAND2X2TS U3839 ( .A(n3054), .B(n2988), .Y(n2990) );
NAND2X4TS U3840 ( .A(n1669), .B(n2989), .Y(n2992) );
NAND2X4TS U3841 ( .A(n2992), .B(n2991), .Y(n1268) );
MXI2X2TS U3842 ( .A(n4285), .B(n4284), .S0(n2043), .Y(n3617) );
MXI2X2TS U3843 ( .A(n4384), .B(n4383), .S0(n4382), .Y(n3618) );
OAI2BB1X2TS U3844 ( .A0N(d_ff2_X[2]), .A1N(n3044), .B0(n3034), .Y(n692) );
MXI2X4TS U3845 ( .A(n4124), .B(n4123), .S0(n4122), .Y(n3642) );
MXI2X4TS U3846 ( .A(n4349), .B(n4348), .S0(n4347), .Y(n3623) );
OAI2BB1X2TS U3847 ( .A0N(d_ff2_X[4]), .A1N(n3044), .B0(n3043), .Y(n688) );
NOR2X2TS U3848 ( .A(n2351), .B(n2198), .Y(n3687) );
NAND2X2TS U3849 ( .A(n3687), .B(n3052), .Y(n3247) );
NAND2X1TS U3850 ( .A(n3053), .B(n3245), .Y(n3055) );
AOI2BB2X4TS U3851 ( .B0(n3069), .B1(n3068), .A0N(n1640), .A1N(
d_ff3_LUT_out[10]), .Y(n935) );
AO21X4TS U3852 ( .A0(d_ff3_LUT_out[24]), .A1(n3707), .B0(n3276), .Y(n921) );
OAI2BB1X2TS U3853 ( .A0N(d_ff2_X[40]), .A1N(n3303), .B0(n3075), .Y(n616) );
NAND2X1TS U3854 ( .A(n3415), .B(d_ff2_Y[22]), .Y(n3078) );
BUFX12TS U3855 ( .A(n3422), .Y(n3417) );
NAND2X1TS U3856 ( .A(n3417), .B(d_ff2_X[22]), .Y(n3076) );
NAND3X2TS U3857 ( .A(n3078), .B(n3077), .C(n3076), .Y(add_subt_dataA[22]) );
NAND2X1TS U3858 ( .A(n3415), .B(d_ff2_Y[21]), .Y(n3081) );
NAND2X1TS U3859 ( .A(n3417), .B(d_ff2_X[21]), .Y(n3079) );
NAND3X2TS U3860 ( .A(n3081), .B(n3080), .C(n3079), .Y(add_subt_dataA[21]) );
NAND2X1TS U3861 ( .A(n3415), .B(d_ff2_Y[20]), .Y(n3084) );
NAND2X1TS U3862 ( .A(n3417), .B(d_ff2_X[20]), .Y(n3082) );
NAND3X2TS U3863 ( .A(n3084), .B(n3083), .C(n3082), .Y(add_subt_dataA[20]) );
NAND2X1TS U3864 ( .A(n3415), .B(d_ff2_Y[19]), .Y(n3087) );
NAND2X1TS U3865 ( .A(n3417), .B(d_ff2_X[19]), .Y(n3085) );
NAND3X2TS U3866 ( .A(n3087), .B(n3086), .C(n3085), .Y(add_subt_dataA[19]) );
NAND2X1TS U3867 ( .A(n3439), .B(d_ff2_Y[18]), .Y(n3090) );
NAND2X1TS U3868 ( .A(n3182), .B(n2270), .Y(n3089) );
NAND2X1TS U3869 ( .A(n3417), .B(d_ff2_X[18]), .Y(n3088) );
NAND3X2TS U3870 ( .A(n3090), .B(n3089), .C(n3088), .Y(add_subt_dataA[18]) );
NAND2X1TS U3871 ( .A(n3439), .B(d_ff2_Y[17]), .Y(n3093) );
NAND2X1TS U3872 ( .A(n3417), .B(d_ff2_X[17]), .Y(n3091) );
NAND3X2TS U3873 ( .A(n3093), .B(n3092), .C(n3091), .Y(add_subt_dataA[17]) );
NAND2X1TS U3874 ( .A(n3417), .B(d_ff2_X[16]), .Y(n3094) );
NAND2X1TS U3875 ( .A(n3439), .B(d_ff2_Y[15]), .Y(n3099) );
NAND2X1TS U3876 ( .A(n3417), .B(d_ff2_X[15]), .Y(n3097) );
NAND3X2TS U3877 ( .A(n3099), .B(n3098), .C(n3097), .Y(add_subt_dataA[15]) );
NAND2X1TS U3878 ( .A(n3439), .B(d_ff2_Y[14]), .Y(n3102) );
NAND2X1TS U3879 ( .A(n3417), .B(d_ff2_X[14]), .Y(n3100) );
NAND3X2TS U3880 ( .A(n3102), .B(n3101), .C(n3100), .Y(add_subt_dataA[14]) );
NAND2X1TS U3881 ( .A(n1645), .B(d_ff2_Y[49]), .Y(n3105) );
NAND2X1TS U3882 ( .A(n3382), .B(n2262), .Y(n3104) );
NAND2X1TS U3883 ( .A(n3532), .B(d_ff2_X[49]), .Y(n3103) );
NAND3X2TS U3884 ( .A(n3105), .B(n3104), .C(n3103), .Y(add_subt_dataA[49]) );
NAND2X1TS U3885 ( .A(n1645), .B(d_ff2_Y[50]), .Y(n3108) );
NAND2X1TS U3886 ( .A(n3389), .B(n2263), .Y(n3107) );
NAND2X1TS U3887 ( .A(n3532), .B(d_ff2_X[50]), .Y(n3106) );
NAND3X2TS U3888 ( .A(n3108), .B(n3107), .C(n3106), .Y(add_subt_dataA[50]) );
NAND2X1TS U3889 ( .A(n1645), .B(d_ff2_Y[51]), .Y(n3111) );
NAND2X1TS U3890 ( .A(n3496), .B(n2264), .Y(n3110) );
NAND2X1TS U3891 ( .A(n3509), .B(d_ff2_X[51]), .Y(n3109) );
NAND3X2TS U3892 ( .A(n3111), .B(n3110), .C(n3109), .Y(add_subt_dataA[51]) );
INVX8TS U3893 ( .A(n3429), .Y(n3158) );
NAND2X1TS U3894 ( .A(n3158), .B(d_ff2_Y[34]), .Y(n3114) );
NAND2X1TS U3895 ( .A(n3389), .B(d_ff2_Z[34]), .Y(n3113) );
NAND2X1TS U3896 ( .A(n3527), .B(d_ff2_X[34]), .Y(n3112) );
NAND3X2TS U3897 ( .A(n3114), .B(n3113), .C(n3112), .Y(add_subt_dataA[34]) );
NAND2X1TS U3898 ( .A(n3158), .B(d_ff2_Y[35]), .Y(n3117) );
NAND2X1TS U3899 ( .A(n3416), .B(d_ff2_Z[35]), .Y(n3116) );
NAND2X1TS U3900 ( .A(n3381), .B(n2145), .Y(n3115) );
NAND3X2TS U3901 ( .A(n3117), .B(n3116), .C(n3115), .Y(add_subt_dataA[35]) );
NAND2X1TS U3902 ( .A(n3158), .B(d_ff2_Y[36]), .Y(n3120) );
NAND2X1TS U3903 ( .A(n3496), .B(d_ff2_Z[36]), .Y(n3119) );
NAND2X1TS U3904 ( .A(n3532), .B(d_ff2_X[36]), .Y(n3118) );
NAND3X2TS U3905 ( .A(n3120), .B(n3119), .C(n3118), .Y(add_subt_dataA[36]) );
NAND2X1TS U3906 ( .A(n3158), .B(d_ff2_Y[37]), .Y(n3123) );
NAND2X1TS U3907 ( .A(n3521), .B(d_ff2_Z[37]), .Y(n3122) );
NAND2X1TS U3908 ( .A(n3527), .B(d_ff2_X[37]), .Y(n3121) );
NAND3X2TS U3909 ( .A(n3123), .B(n3122), .C(n3121), .Y(add_subt_dataA[37]) );
NAND2X1TS U3910 ( .A(n3158), .B(d_ff2_Y[38]), .Y(n3126) );
NAND2X1TS U3911 ( .A(n3513), .B(d_ff2_Z[38]), .Y(n3125) );
NAND2X1TS U3912 ( .A(n3381), .B(d_ff2_X[38]), .Y(n3124) );
NAND3X2TS U3913 ( .A(n3126), .B(n3125), .C(n3124), .Y(add_subt_dataA[38]) );
NAND2X1TS U3914 ( .A(n3158), .B(d_ff2_Y[29]), .Y(n3129) );
NAND2X1TS U3915 ( .A(n3416), .B(n2282), .Y(n3128) );
NAND2X1TS U3916 ( .A(n3160), .B(d_ff2_X[29]), .Y(n3127) );
NAND3X2TS U3917 ( .A(n3129), .B(n3128), .C(n3127), .Y(add_subt_dataA[29]) );
INVX8TS U3918 ( .A(n3429), .Y(n3173) );
NAND2X1TS U3919 ( .A(n3173), .B(d_ff2_Y[44]), .Y(n3133) );
NAND2X1TS U3920 ( .A(n3521), .B(n2274), .Y(n3132) );
NAND2X1TS U3921 ( .A(n3512), .B(d_ff2_X[44]), .Y(n3131) );
NAND3X2TS U3922 ( .A(n3133), .B(n3132), .C(n3131), .Y(add_subt_dataA[44]) );
NAND2X1TS U3923 ( .A(n3173), .B(d_ff2_Y[45]), .Y(n3136) );
NAND2X1TS U3924 ( .A(n3513), .B(n2275), .Y(n3135) );
NAND2X1TS U3925 ( .A(n3520), .B(d_ff2_X[45]), .Y(n3134) );
NAND3X2TS U3926 ( .A(n3136), .B(n3135), .C(n3134), .Y(add_subt_dataA[45]) );
NAND2X1TS U3927 ( .A(n3173), .B(d_ff2_Y[46]), .Y(n3139) );
NAND2X1TS U3928 ( .A(n3382), .B(d_ff2_Z[46]), .Y(n3138) );
NAND2X1TS U3929 ( .A(n3175), .B(d_ff2_X[46]), .Y(n3137) );
NAND3X2TS U3930 ( .A(n3139), .B(n3138), .C(n3137), .Y(add_subt_dataA[46]) );
NAND2X1TS U3931 ( .A(n3173), .B(d_ff2_Y[47]), .Y(n3142) );
NAND2X1TS U3932 ( .A(n3182), .B(n2260), .Y(n3141) );
NAND2X1TS U3933 ( .A(n3509), .B(d_ff2_X[47]), .Y(n3140) );
NAND3X2TS U3934 ( .A(n3142), .B(n3141), .C(n3140), .Y(add_subt_dataA[47]) );
NAND2X1TS U3935 ( .A(n3173), .B(d_ff2_Y[48]), .Y(n3145) );
NAND2X1TS U3936 ( .A(n3174), .B(n2261), .Y(n3144) );
NAND2X1TS U3937 ( .A(n2401), .B(d_ff2_X[48]), .Y(n3143) );
NAND3X2TS U3938 ( .A(n3145), .B(n3144), .C(n3143), .Y(add_subt_dataA[48]) );
NAND2X1TS U3939 ( .A(n3158), .B(d_ff2_Y[30]), .Y(n3148) );
NAND2X1TS U3940 ( .A(n3389), .B(n2283), .Y(n3147) );
NAND2X1TS U3941 ( .A(n3512), .B(d_ff2_X[30]), .Y(n3146) );
NAND3X2TS U3942 ( .A(n3148), .B(n3147), .C(n3146), .Y(add_subt_dataA[30]) );
NAND2X1TS U3943 ( .A(n3173), .B(d_ff2_Y[40]), .Y(n3151) );
NAND2X1TS U3944 ( .A(n3382), .B(d_ff2_Z[40]), .Y(n3150) );
NAND2X1TS U3945 ( .A(n3392), .B(d_ff2_X[40]), .Y(n3149) );
NAND3X2TS U3946 ( .A(n3151), .B(n3150), .C(n3149), .Y(add_subt_dataA[40]) );
NAND2X1TS U3947 ( .A(n3158), .B(d_ff2_Y[31]), .Y(n3154) );
NAND2X1TS U3948 ( .A(n3496), .B(n2284), .Y(n3153) );
NAND2X1TS U3949 ( .A(n3183), .B(d_ff2_X[31]), .Y(n3152) );
NAND3X2TS U3950 ( .A(n3154), .B(n3153), .C(n3152), .Y(add_subt_dataA[31]) );
NAND2X1TS U3951 ( .A(n3158), .B(d_ff2_Y[33]), .Y(n3157) );
NAND2X1TS U3952 ( .A(n3521), .B(d_ff2_Z[33]), .Y(n3156) );
NAND2X1TS U3953 ( .A(n2401), .B(d_ff2_X[33]), .Y(n3155) );
NAND3X2TS U3954 ( .A(n3157), .B(n3156), .C(n3155), .Y(add_subt_dataA[33]) );
NAND2X1TS U3955 ( .A(n3158), .B(d_ff2_Y[32]), .Y(n3163) );
NAND2X1TS U3956 ( .A(n3513), .B(n2285), .Y(n3162) );
NAND2X1TS U3957 ( .A(n3512), .B(d_ff2_X[32]), .Y(n3161) );
NAND3X2TS U3958 ( .A(n3163), .B(n3162), .C(n3161), .Y(add_subt_dataA[32]) );
NAND2X1TS U3959 ( .A(n3173), .B(d_ff2_Y[39]), .Y(n3166) );
NAND2X1TS U3960 ( .A(n3182), .B(d_ff2_Z[39]), .Y(n3165) );
NAND2X1TS U3961 ( .A(n3392), .B(d_ff2_X[39]), .Y(n3164) );
NAND3X2TS U3962 ( .A(n3166), .B(n3165), .C(n3164), .Y(add_subt_dataA[39]) );
NAND2X1TS U3963 ( .A(n3173), .B(d_ff2_Y[41]), .Y(n3169) );
NAND2X1TS U3964 ( .A(n3174), .B(d_ff2_Z[41]), .Y(n3168) );
NAND2X1TS U3965 ( .A(n3381), .B(d_ff2_X[41]), .Y(n3167) );
NAND3X2TS U3966 ( .A(n3169), .B(n3168), .C(n3167), .Y(add_subt_dataA[41]) );
NAND2X1TS U3967 ( .A(n3173), .B(d_ff2_Y[42]), .Y(n3172) );
NAND2X1TS U3968 ( .A(n3159), .B(d_ff2_Z[42]), .Y(n3171) );
NAND2X1TS U3969 ( .A(n3160), .B(n1569), .Y(n3170) );
NAND3X2TS U3970 ( .A(n3172), .B(n3171), .C(n3170), .Y(add_subt_dataA[42]) );
NAND2X1TS U3971 ( .A(n3173), .B(d_ff2_Y[43]), .Y(n3178) );
NAND2X1TS U3972 ( .A(n3389), .B(n2300), .Y(n3177) );
NAND2X1TS U3973 ( .A(n3183), .B(d_ff2_X[43]), .Y(n3176) );
NAND3X2TS U3974 ( .A(n3178), .B(n3177), .C(n3176), .Y(add_subt_dataA[43]) );
NAND2X1TS U3975 ( .A(n1645), .B(n2141), .Y(n3181) );
NAND2X1TS U3976 ( .A(n3159), .B(n2265), .Y(n3180) );
NAND2X1TS U3977 ( .A(n3512), .B(n1719), .Y(n3179) );
NAND3X2TS U3978 ( .A(n3181), .B(n3180), .C(n3179), .Y(add_subt_dataA[52]) );
NAND2X1TS U3979 ( .A(n1645), .B(d_ff2_Y[59]), .Y(n3186) );
NAND2X1TS U3980 ( .A(n3389), .B(n2252), .Y(n3185) );
NAND2X1TS U3981 ( .A(n3532), .B(n2324), .Y(n3184) );
NAND3X2TS U3982 ( .A(n3186), .B(n3185), .C(n3184), .Y(add_subt_dataA[59]) );
MXI2X4TS U3983 ( .A(n3189), .B(d_ff3_LUT_out[26]), .S0(n2629), .Y(n3193) );
OAI21X2TS U3984 ( .A0(n4001), .A1(n4475), .B0(n3203), .Y(n965) );
OAI21X4TS U3985 ( .A0(n3717), .A1(n2572), .B0(n3206), .Y(n3207) );
OAI2BB1X4TS U3986 ( .A0N(ack_add_subt), .A1N(n2189), .B0(n3207), .Y(n1339)
);
XNOR2X4TS U3987 ( .A(n3250), .B(cont_var_out[1]), .Y(n3209) );
NAND2X4TS U3988 ( .A(n3716), .B(n3223), .Y(n3224) );
INVX2TS U3989 ( .A(n3228), .Y(n3255) );
NOR2X4TS U3990 ( .A(n2317), .B(n2324), .Y(n3230) );
NAND2X4TS U3991 ( .A(n3394), .B(n3230), .Y(n3328) );
INVX2TS U3992 ( .A(n3409), .Y(n3231) );
NOR2X4TS U3993 ( .A(n2356), .B(d_ff2_Y[58]), .Y(n3234) );
NOR3X1TS U3994 ( .A(d_ff2_Y[60]), .B(d_ff2_Y[61]), .C(n2255), .Y(n3235) );
NAND3X2TS U3995 ( .A(n1485), .B(n3244), .C(n3263), .Y(n3246) );
NOR2X2TS U3996 ( .A(n2153), .B(n1504), .Y(n3688) );
INVX2TS U3997 ( .A(d_ff2_X[21]), .Y(n3248) );
INVX2TS U3998 ( .A(n4001), .Y(n3267) );
MXI2X1TS U3999 ( .A(n3947), .B(n2429), .S0(n3551), .Y(n629) );
BUFX20TS U4000 ( .A(n2190), .Y(n3727) );
MXI2X1TS U4001 ( .A(n3940), .B(n2425), .S0(n3727), .Y(n687) );
MXI2X1TS U4002 ( .A(n3896), .B(n2427), .S0(n3727), .Y(n679) );
MXI2X1TS U4003 ( .A(n3822), .B(n3972), .S0(n3551), .Y(n761) );
MXI2X1TS U4004 ( .A(n3821), .B(n3971), .S0(n3551), .Y(n763) );
MXI2X1TS U4005 ( .A(n3820), .B(n3970), .S0(n3551), .Y(n765) );
INVX4TS U4006 ( .A(n3313), .Y(n3314) );
AND2X8TS U4007 ( .A(n3314), .B(n3713), .Y(n3315) );
NAND2X1TS U4008 ( .A(n3329), .B(n2124), .Y(n4608) );
AOI22X2TS U4009 ( .A0(d_ff2_Z[62]), .A1(n3182), .B0(n3160), .B1(d_ff2_X[62]),
.Y(n3333) );
OAI21X2TS U4010 ( .A0(n2255), .A1(n3530), .B0(n3333), .Y(add_subt_dataA[62])
);
OAI21X2TS U4011 ( .A0(n4510), .A1(n3379), .B0(n3335), .Y(add_subt_dataB[1])
);
AOI22X1TS U4012 ( .A0(d_ff3_LUT_out[0]), .A1(n3416), .B0(n3512), .B1(
d_ff3_sh_y_out[0]), .Y(n3336) );
AOI22X1TS U4013 ( .A0(d_ff2_Z[56]), .A1(n3521), .B0(n3509), .B1(n1573), .Y(
n3337) );
OAI21X1TS U4014 ( .A0(n4473), .A1(n3518), .B0(n3337), .Y(add_subt_dataA[56])
);
INVX8TS U4015 ( .A(n3429), .Y(n3500) );
NAND2X1TS U4016 ( .A(n3500), .B(n1579), .Y(n3342) );
BUFX12TS U4017 ( .A(n3421), .Y(n3516) );
NAND2X1TS U4018 ( .A(n3516), .B(d_ff3_LUT_out[56]), .Y(n3341) );
NAND2X1TS U4019 ( .A(n3160), .B(n3479), .Y(n3340) );
NAND3X1TS U4020 ( .A(n3342), .B(n3341), .C(n3340), .Y(add_subt_dataB[56]) );
AOI22X1TS U4021 ( .A0(d_ff2_Z[60]), .A1(n3513), .B0(n3381), .B1(n2123), .Y(
n3343) );
BUFX12TS U4022 ( .A(n3359), .Y(n3496) );
BUFX16TS U4023 ( .A(n3361), .Y(n3512) );
AOI22X1TS U4024 ( .A0(d_ff3_LUT_out[46]), .A1(n3416), .B0(n3512), .B1(
d_ff3_sh_y_out[46]), .Y(n3344) );
OAI21X2TS U4025 ( .A0(n4584), .A1(n3379), .B0(n3344), .Y(add_subt_dataB[46])
);
AOI22X2TS U4026 ( .A0(d_ff3_LUT_out[47]), .A1(n3174), .B0(n3512), .B1(
d_ff3_sh_y_out[47]), .Y(n3345) );
OAI21X1TS U4027 ( .A0(n4586), .A1(n3530), .B0(n3345), .Y(add_subt_dataB[47])
);
AOI22X2TS U4028 ( .A0(d_ff3_LUT_out[49]), .A1(n3174), .B0(n3392), .B1(
d_ff3_sh_y_out[49]), .Y(n3346) );
OAI21X2TS U4029 ( .A0(n4591), .A1(n3515), .B0(n3346), .Y(add_subt_dataB[49])
);
AOI22X1TS U4030 ( .A0(d_ff3_LUT_out[45]), .A1(n3389), .B0(n3520), .B1(
d_ff3_sh_y_out[45]), .Y(n3347) );
OAI21X2TS U4031 ( .A0(n4582), .A1(n3379), .B0(n3347), .Y(add_subt_dataB[45])
);
AOI22X1TS U4032 ( .A0(d_ff3_LUT_out[44]), .A1(n3416), .B0(n3175), .B1(
d_ff3_sh_y_out[44]), .Y(n3348) );
OAI21X2TS U4033 ( .A0(n4581), .A1(n3379), .B0(n3348), .Y(add_subt_dataB[44])
);
AOI22X2TS U4034 ( .A0(d_ff3_LUT_out[43]), .A1(n3182), .B0(n3520), .B1(
d_ff3_sh_y_out[43]), .Y(n3349) );
OAI21X2TS U4035 ( .A0(n4579), .A1(n3515), .B0(n3349), .Y(add_subt_dataB[43])
);
AOI22X2TS U4036 ( .A0(d_ff3_LUT_out[42]), .A1(n3159), .B0(n3509), .B1(
d_ff3_sh_y_out[42]), .Y(n3350) );
AOI22X2TS U4037 ( .A0(d_ff3_LUT_out[41]), .A1(n3159), .B0(n3527), .B1(
d_ff3_sh_y_out[41]), .Y(n3351) );
OAI21X1TS U4038 ( .A0(n4575), .A1(n3518), .B0(n3351), .Y(add_subt_dataB[41])
);
BUFX12TS U4039 ( .A(n3359), .Y(n3513) );
AOI22X2TS U4040 ( .A0(d_ff3_LUT_out[40]), .A1(n3513), .B0(n3183), .B1(
d_ff3_sh_y_out[40]), .Y(n3352) );
OAI21X1TS U4041 ( .A0(n4573), .A1(n3515), .B0(n3352), .Y(add_subt_dataB[40])
);
BUFX16TS U4042 ( .A(n3361), .Y(n3509) );
OAI21X2TS U4043 ( .A0(n4566), .A1(n3384), .B0(n3353), .Y(add_subt_dataB[34])
);
AOI22X1TS U4044 ( .A0(d_ff3_LUT_out[32]), .A1(n3174), .B0(n3527), .B1(
d_ff3_sh_y_out[32]), .Y(n3354) );
OAI21X2TS U4045 ( .A0(n4562), .A1(n3384), .B0(n3354), .Y(add_subt_dataB[32])
);
OAI2BB1X2TS U4046 ( .A0N(n4359), .A1N(n4358), .B0(n4357), .Y(n915) );
BUFX12TS U4047 ( .A(n3421), .Y(n3528) );
BUFX16TS U4048 ( .A(n3361), .Y(n3527) );
AOI22X1TS U4049 ( .A0(d_ff3_LUT_out[27]), .A1(n3528), .B0(n2401), .B1(
d_ff3_sh_y_out[27]), .Y(n3355) );
OAI21X2TS U4050 ( .A0(n4552), .A1(n3374), .B0(n3355), .Y(add_subt_dataB[27])
);
AOI22X1TS U4051 ( .A0(d_ff3_LUT_out[21]), .A1(n3528), .B0(n3532), .B1(
d_ff3_sh_y_out[21]), .Y(n3356) );
OAI21X2TS U4052 ( .A0(n4541), .A1(n3374), .B0(n3356), .Y(add_subt_dataB[21])
);
BUFX12TS U4053 ( .A(n3359), .Y(n3382) );
AOI22X1TS U4054 ( .A0(d_ff3_LUT_out[20]), .A1(n3513), .B0(n3512), .B1(
d_ff3_sh_y_out[20]), .Y(n3357) );
OAI21X2TS U4055 ( .A0(n4539), .A1(n3374), .B0(n3357), .Y(add_subt_dataB[20])
);
AOI22X1TS U4056 ( .A0(d_ff3_LUT_out[19]), .A1(n3382), .B0(n3509), .B1(
d_ff3_sh_y_out[19]), .Y(n3358) );
OAI21X2TS U4057 ( .A0(n4537), .A1(n3374), .B0(n3358), .Y(add_subt_dataB[19])
);
AOI22X1TS U4058 ( .A0(d_ff3_LUT_out[10]), .A1(n3382), .B0(n3381), .B1(
d_ff3_sh_y_out[10]), .Y(n3360) );
OAI21X2TS U4059 ( .A0(n4523), .A1(n3384), .B0(n3360), .Y(add_subt_dataB[10])
);
BUFX12TS U4060 ( .A(n3361), .Y(n3392) );
AOI22X1TS U4061 ( .A0(d_ff3_LUT_out[5]), .A1(n3389), .B0(n2401), .B1(
d_ff3_sh_y_out[5]), .Y(n3362) );
OAI21X2TS U4062 ( .A0(n4517), .A1(n3379), .B0(n3362), .Y(add_subt_dataB[5])
);
AOI22X1TS U4063 ( .A0(d_ff3_LUT_out[18]), .A1(n3382), .B0(n3392), .B1(
d_ff3_sh_y_out[18]), .Y(n3363) );
OAI21X2TS U4064 ( .A0(n4536), .A1(n3374), .B0(n3363), .Y(add_subt_dataB[18])
);
AOI22X1TS U4065 ( .A0(d_ff3_LUT_out[17]), .A1(n3389), .B0(n3160), .B1(
d_ff3_sh_y_out[17]), .Y(n3364) );
OAI21X2TS U4066 ( .A0(n4535), .A1(n3374), .B0(n3364), .Y(add_subt_dataB[17])
);
AOI22X1TS U4067 ( .A0(d_ff3_LUT_out[7]), .A1(n3416), .B0(n2401), .B1(
d_ff3_sh_y_out[7]), .Y(n3365) );
OAI21X2TS U4068 ( .A0(n4520), .A1(n3379), .B0(n3365), .Y(add_subt_dataB[7])
);
OAI21X2TS U4069 ( .A0(n4519), .A1(n3379), .B0(n3366), .Y(add_subt_dataB[6])
);
AOI22X1TS U4070 ( .A0(d_ff3_LUT_out[13]), .A1(n3416), .B0(n3183), .B1(
d_ff3_sh_y_out[13]), .Y(n3367) );
OAI21X2TS U4071 ( .A0(n4530), .A1(n3384), .B0(n3367), .Y(add_subt_dataB[13])
);
AOI22X1TS U4072 ( .A0(n941), .A1(n3174), .B0(n3392), .B1(d_ff3_sh_y_out[4]),
.Y(n3368) );
OAI21X2TS U4073 ( .A0(n4515), .A1(n3379), .B0(n3368), .Y(add_subt_dataB[4])
);
AOI22X1TS U4074 ( .A0(d_ff3_LUT_out[12]), .A1(n3496), .B0(n2401), .B1(
d_ff3_sh_y_out[12]), .Y(n3369) );
OAI21X2TS U4075 ( .A0(n4529), .A1(n3384), .B0(n3369), .Y(add_subt_dataB[12])
);
AOI22X1TS U4076 ( .A0(d_ff3_LUT_out[8]), .A1(n3513), .B0(n3175), .B1(
d_ff3_sh_y_out[8]), .Y(n3370) );
OAI21X2TS U4077 ( .A0(n4521), .A1(n3379), .B0(n3370), .Y(add_subt_dataB[8])
);
AOI22X1TS U4078 ( .A0(d_ff3_LUT_out[33]), .A1(n3159), .B0(n3381), .B1(
d_ff3_sh_y_out[33]), .Y(n3371) );
OAI21X2TS U4079 ( .A0(n4564), .A1(n3384), .B0(n3371), .Y(add_subt_dataB[33])
);
AOI22X1TS U4080 ( .A0(d_ff3_LUT_out[3]), .A1(n3159), .B0(n3160), .B1(
d_ff3_sh_y_out[3]), .Y(n3372) );
OAI21X2TS U4081 ( .A0(n4513), .A1(n3374), .B0(n3372), .Y(add_subt_dataB[3])
);
AOI22X1TS U4082 ( .A0(d_ff3_LUT_out[16]), .A1(n3521), .B0(n3532), .B1(
d_ff3_sh_y_out[16]), .Y(n3373) );
OAI21X2TS U4083 ( .A0(n4534), .A1(n3374), .B0(n3373), .Y(add_subt_dataB[16])
);
AOI22X1TS U4084 ( .A0(d_ff3_LUT_out[15]), .A1(n3513), .B0(n3175), .B1(
d_ff3_sh_y_out[15]), .Y(n3375) );
OAI21X2TS U4085 ( .A0(n4532), .A1(n3384), .B0(n3375), .Y(add_subt_dataB[15])
);
AOI22X1TS U4086 ( .A0(d_ff3_LUT_out[2]), .A1(n3496), .B0(n3183), .B1(
d_ff3_sh_y_out[2]), .Y(n3376) );
OAI21X2TS U4087 ( .A0(n4512), .A1(n3530), .B0(n3376), .Y(add_subt_dataB[2])
);
AOI22X1TS U4088 ( .A0(d_ff3_LUT_out[14]), .A1(n3416), .B0(n3520), .B1(
d_ff3_sh_y_out[14]), .Y(n3377) );
OAI21X2TS U4089 ( .A0(n4531), .A1(n3384), .B0(n3377), .Y(add_subt_dataB[14])
);
AOI22X1TS U4090 ( .A0(d_ff3_LUT_out[9]), .A1(n3521), .B0(n3512), .B1(
d_ff3_sh_y_out[9]), .Y(n3378) );
OAI21X2TS U4091 ( .A0(n4522), .A1(n3379), .B0(n3378), .Y(add_subt_dataB[9])
);
AOI22X1TS U4092 ( .A0(d_ff2_Z[61]), .A1(n3382), .B0(n2401), .B1(n2248), .Y(
n3380) );
OAI21X1TS U4093 ( .A0(n3911), .A1(n3518), .B0(n3380), .Y(add_subt_dataA[61])
);
AOI22X1TS U4094 ( .A0(n3693), .A1(n3496), .B0(n3527), .B1(d_ff3_sh_y_out[11]), .Y(n3383) );
OAI21X2TS U4095 ( .A0(n4527), .A1(n3384), .B0(n3383), .Y(add_subt_dataB[11])
);
AOI22X1TS U4096 ( .A0(d_ff3_LUT_out[54]), .A1(n3516), .B0(n3160), .B1(
d_ff3_sh_y_out[54]), .Y(n3385) );
NAND2X1TS U4097 ( .A(n3500), .B(n2131), .Y(n3388) );
NAND2X1TS U4098 ( .A(n3527), .B(d_ff3_sh_y_out[55]), .Y(n3386) );
NAND3X1TS U4099 ( .A(n3388), .B(n3387), .C(n3386), .Y(add_subt_dataB[55]) );
AOI22X1TS U4100 ( .A0(d_ff2_Z[53]), .A1(n3382), .B0(n3520), .B1(d_ff2_X[53]),
.Y(n3390) );
OAI21X1TS U4101 ( .A0(n2369), .A1(n3374), .B0(n3390), .Y(add_subt_dataA[53])
);
OAI21X1TS U4102 ( .A0(n2143), .A1(n3515), .B0(n3393), .Y(add_subt_dataA[54])
);
NAND2X6TS U4103 ( .A(n3394), .B(n2318), .Y(n3555) );
NAND2X2TS U4104 ( .A(n3555), .B(n2324), .Y(n3395) );
OAI21X4TS U4105 ( .A0(n1530), .A1(n574), .B0(n3396), .Y(n3397) );
NAND3X2TS U4106 ( .A(n4129), .B(n4128), .C(n4127), .Y(n3488) );
NAND2X1TS U4107 ( .A(n3512), .B(n3488), .Y(n3401) );
NAND2X1TS U4108 ( .A(n3500), .B(d_ff3_sh_x_out[51]), .Y(n3404) );
NAND2X1TS U4109 ( .A(n3532), .B(d_ff3_sh_y_out[51]), .Y(n3403) );
NAND2X1TS U4110 ( .A(n3500), .B(d_ff3_sh_x_out[48]), .Y(n3406) );
NAND2X1TS U4111 ( .A(n3175), .B(d_ff3_sh_y_out[48]), .Y(n3405) );
NAND2X1TS U4112 ( .A(n3500), .B(n574), .Y(n3408) );
NAND2X2TS U4113 ( .A(n4164), .B(n4163), .Y(n3547) );
NAND2X1TS U4114 ( .A(n3381), .B(n3547), .Y(n3407) );
NAND2X1TS U4115 ( .A(n3500), .B(n575), .Y(n3411) );
NAND2X1TS U4116 ( .A(n3500), .B(n576), .Y(n3414) );
NAND2X1TS U4117 ( .A(n3415), .B(d_ff2_Y[23]), .Y(n3420) );
NAND2X1TS U4118 ( .A(n3417), .B(d_ff2_X[23]), .Y(n3418) );
NAND3X1TS U4119 ( .A(n3420), .B(n3419), .C(n3418), .Y(add_subt_dataA[23]) );
NAND2X1TS U4120 ( .A(n3439), .B(d_ff2_Y[12]), .Y(n3425) );
BUFX8TS U4121 ( .A(n3421), .Y(n3455) );
NAND2X1TS U4122 ( .A(n3455), .B(d_ff2_Z[12]), .Y(n3424) );
NAND2X1TS U4123 ( .A(n3456), .B(d_ff2_X[12]), .Y(n3423) );
NAND3X1TS U4124 ( .A(n3425), .B(n3424), .C(n3423), .Y(add_subt_dataA[12]) );
NAND2X1TS U4125 ( .A(n3439), .B(d_ff2_Y[13]), .Y(n3428) );
NAND2X1TS U4126 ( .A(n3455), .B(n2269), .Y(n3427) );
NAND2X1TS U4127 ( .A(n3456), .B(d_ff2_X[13]), .Y(n3426) );
NAND3X1TS U4128 ( .A(n3428), .B(n3427), .C(n3426), .Y(add_subt_dataA[13]) );
INVX8TS U4129 ( .A(n3429), .Y(n3531) );
NAND2X1TS U4130 ( .A(n3531), .B(d_ff2_Y[2]), .Y(n3432) );
NAND2X1TS U4131 ( .A(n3516), .B(d_ff2_Z[2]), .Y(n3431) );
NAND2X1TS U4132 ( .A(n3183), .B(d_ff2_X[2]), .Y(n3430) );
NAND3X1TS U4133 ( .A(n3432), .B(n3431), .C(n3430), .Y(add_subt_dataA[2]) );
NAND2X1TS U4134 ( .A(n3439), .B(d_ff2_Y[11]), .Y(n3435) );
NAND2X1TS U4135 ( .A(n3455), .B(n2258), .Y(n3434) );
NAND2X1TS U4136 ( .A(n3456), .B(d_ff2_X[11]), .Y(n3433) );
NAND3X1TS U4137 ( .A(n3435), .B(n3434), .C(n3433), .Y(add_subt_dataA[11]) );
NAND2X1TS U4138 ( .A(n3439), .B(d_ff2_Y[10]), .Y(n3438) );
NAND2X1TS U4139 ( .A(n3455), .B(d_ff2_Z[10]), .Y(n3437) );
NAND2X1TS U4140 ( .A(n3456), .B(d_ff2_X[10]), .Y(n3436) );
NAND3X1TS U4141 ( .A(n3438), .B(n3437), .C(n3436), .Y(add_subt_dataA[10]) );
NAND2X1TS U4142 ( .A(n3439), .B(d_ff2_Y[9]), .Y(n3442) );
NAND2X1TS U4143 ( .A(n3455), .B(d_ff2_Z[9]), .Y(n3441) );
NAND2X1TS U4144 ( .A(n3456), .B(d_ff2_X[9]), .Y(n3440) );
NAND3X1TS U4145 ( .A(n3442), .B(n3441), .C(n3440), .Y(add_subt_dataA[9]) );
NAND2X1TS U4146 ( .A(n3531), .B(d_ff2_Y[8]), .Y(n3445) );
NAND2X1TS U4147 ( .A(n3455), .B(d_ff2_Z[8]), .Y(n3444) );
NAND2X1TS U4148 ( .A(n3456), .B(d_ff2_X[8]), .Y(n3443) );
NAND3X1TS U4149 ( .A(n3445), .B(n3444), .C(n3443), .Y(add_subt_dataA[8]) );
NAND2X1TS U4150 ( .A(n3531), .B(d_ff2_Y[7]), .Y(n3448) );
NAND2X1TS U4151 ( .A(n3455), .B(d_ff2_Z[7]), .Y(n3447) );
NAND2X1TS U4152 ( .A(n3456), .B(d_ff2_X[7]), .Y(n3446) );
NAND3X1TS U4153 ( .A(n3448), .B(n3447), .C(n3446), .Y(add_subt_dataA[7]) );
NAND2X1TS U4154 ( .A(n3531), .B(d_ff2_Y[6]), .Y(n3451) );
NAND2X1TS U4155 ( .A(n3455), .B(d_ff2_Z[6]), .Y(n3450) );
NAND2X1TS U4156 ( .A(n3456), .B(d_ff2_X[6]), .Y(n3449) );
NAND3X1TS U4157 ( .A(n3451), .B(n3450), .C(n3449), .Y(add_subt_dataA[6]) );
NAND2X1TS U4158 ( .A(n3531), .B(d_ff2_Y[5]), .Y(n3454) );
NAND2X1TS U4159 ( .A(n3455), .B(d_ff2_Z[5]), .Y(n3453) );
NAND2X1TS U4160 ( .A(n3456), .B(d_ff2_X[5]), .Y(n3452) );
NAND3X1TS U4161 ( .A(n3454), .B(n3453), .C(n3452), .Y(add_subt_dataA[5]) );
NAND2X1TS U4162 ( .A(n3531), .B(d_ff2_Y[4]), .Y(n3459) );
NAND2X1TS U4163 ( .A(n3455), .B(d_ff2_Z[4]), .Y(n3458) );
NAND2X1TS U4164 ( .A(n3456), .B(d_ff2_X[4]), .Y(n3457) );
NAND3X1TS U4165 ( .A(n3459), .B(n3458), .C(n3457), .Y(add_subt_dataA[4]) );
NAND2X1TS U4166 ( .A(n3531), .B(d_ff2_Y[3]), .Y(n3462) );
NAND2X1TS U4167 ( .A(n3516), .B(d_ff2_Z[3]), .Y(n3461) );
NAND2X1TS U4168 ( .A(n3509), .B(d_ff2_X[3]), .Y(n3460) );
NAND3X1TS U4169 ( .A(n3462), .B(n3461), .C(n3460), .Y(add_subt_dataA[3]) );
NAND2X1TS U4170 ( .A(n3531), .B(d_ff2_Y[0]), .Y(n3465) );
NAND2X1TS U4171 ( .A(n3516), .B(d_ff2_Z[0]), .Y(n3464) );
NAND2X1TS U4172 ( .A(n3527), .B(d_ff2_X[0]), .Y(n3463) );
NAND3X1TS U4173 ( .A(n3465), .B(n3464), .C(n3463), .Y(add_subt_dataA[0]) );
NAND2X1TS U4174 ( .A(n3516), .B(d_ff2_Z[1]), .Y(n3467) );
NAND2X1TS U4175 ( .A(n3392), .B(d_ff2_X[1]), .Y(n3466) );
NAND3X1TS U4176 ( .A(n3468), .B(n3467), .C(n3466), .Y(add_subt_dataA[1]) );
NAND3X2TS U4177 ( .A(n4095), .B(n4094), .C(n4093), .Y(n3484) );
NAND2X1TS U4178 ( .A(n3520), .B(n3484), .Y(n3471) );
NAND2X1TS U4179 ( .A(n3500), .B(n3469), .Y(n3470) );
NAND3X1TS U4180 ( .A(n3470), .B(n3471), .C(n3472), .Y(add_subt_dataB[61]) );
NOR2X4TS U4181 ( .A(n2248), .B(n2123), .Y(n3490) );
NAND2X1TS U4182 ( .A(n3516), .B(d_ff2_Z[63]), .Y(n3481) );
NAND2X1TS U4183 ( .A(n3509), .B(d_ff2_X[63]), .Y(n3480) );
NAND3X1TS U4184 ( .A(n3482), .B(n3481), .C(n3480), .Y(add_subt_dataA[63]) );
OAI21X2TS U4185 ( .A0(n1530), .A1(n3484), .B0(n3483), .Y(n4610) );
INVX2TS U4186 ( .A(n3499), .Y(n3491) );
AOI22X1TS U4187 ( .A0(d_ff2_Z[58]), .A1(n3496), .B0(n2401), .B1(n2317), .Y(
n3494) );
OAI21X1TS U4188 ( .A0(n3913), .A1(n3518), .B0(n3494), .Y(add_subt_dataA[58])
);
AOI22X1TS U4189 ( .A0(d_ff3_LUT_out[52]), .A1(n3416), .B0(n3532), .B1(
d_ff3_sh_y_out[52]), .Y(n3495) );
OAI21X1TS U4190 ( .A0(n4594), .A1(n3130), .B0(n3495), .Y(add_subt_dataB[52])
);
AOI22X1TS U4191 ( .A0(d_ff3_LUT_out[50]), .A1(n3389), .B0(n3160), .B1(
d_ff3_sh_y_out[50]), .Y(n3497) );
NOR3X2TS U4192 ( .A(n2248), .B(n2123), .C(d_ff2_X[62]), .Y(n3498) );
NAND2X1TS U4193 ( .A(n3500), .B(n3499), .Y(n3502) );
NAND2X1TS U4194 ( .A(n3520), .B(n3904), .Y(n3501) );
NAND2X2TS U4195 ( .A(n3502), .B(n3501), .Y(add_subt_dataB[62]) );
AOI22X2TS U4196 ( .A0(d_ff3_LUT_out[38]), .A1(n3382), .B0(n3381), .B1(
d_ff3_sh_y_out[38]), .Y(n3503) );
OAI21X1TS U4197 ( .A0(n4570), .A1(n3515), .B0(n3503), .Y(add_subt_dataB[38])
);
AOI22X2TS U4198 ( .A0(d_ff3_LUT_out[37]), .A1(n3389), .B0(n3392), .B1(
d_ff3_sh_y_out[37]), .Y(n3504) );
OAI21X1TS U4199 ( .A0(n4569), .A1(n3515), .B0(n3504), .Y(add_subt_dataB[37])
);
AOI22X2TS U4200 ( .A0(d_ff3_LUT_out[36]), .A1(n3174), .B0(n3160), .B1(
d_ff3_sh_y_out[36]), .Y(n3505) );
OAI21X2TS U4201 ( .A0(n4568), .A1(n3518), .B0(n3505), .Y(add_subt_dataB[36])
);
AOI22X2TS U4202 ( .A0(n910), .A1(n3159), .B0(n3183), .B1(d_ff3_sh_y_out[35]),
.Y(n3506) );
OAI21X2TS U4203 ( .A0(n4567), .A1(n3515), .B0(n3506), .Y(add_subt_dataB[35])
);
AOI22X2TS U4204 ( .A0(d_ff3_LUT_out[31]), .A1(n3496), .B0(n3527), .B1(
d_ff3_sh_y_out[31]), .Y(n3507) );
AOI22X2TS U4205 ( .A0(n915), .A1(n3528), .B0(n3381), .B1(d_ff3_sh_y_out[30]),
.Y(n3508) );
AOI22X2TS U4206 ( .A0(d_ff3_LUT_out[29]), .A1(n3528), .B0(n3509), .B1(
d_ff3_sh_y_out[29]), .Y(n3510) );
AOI22X2TS U4207 ( .A0(d_ff3_LUT_out[28]), .A1(n3528), .B0(n2401), .B1(
d_ff3_sh_y_out[28]), .Y(n3511) );
AOI22X2TS U4208 ( .A0(d_ff3_LUT_out[39]), .A1(n3182), .B0(n3175), .B1(
d_ff3_sh_y_out[39]), .Y(n3514) );
OAI21X1TS U4209 ( .A0(n4572), .A1(n3518), .B0(n3514), .Y(add_subt_dataB[39])
);
AOI22X1TS U4210 ( .A0(d_ff3_LUT_out[53]), .A1(n3516), .B0(n3183), .B1(
d_ff3_sh_y_out[53]), .Y(n3517) );
AOI22X1TS U4211 ( .A0(d_ff2_Z[57]), .A1(n3521), .B0(n3527), .B1(d_ff2_X[57]),
.Y(n3522) );
OAI21X1TS U4212 ( .A0(n3903), .A1(n3530), .B0(n3522), .Y(add_subt_dataA[57])
);
AOI22X2TS U4213 ( .A0(d_ff3_LUT_out[25]), .A1(n3528), .B0(n3392), .B1(
d_ff3_sh_y_out[25]), .Y(n3523) );
OAI21X2TS U4214 ( .A0(n4548), .A1(n3130), .B0(n3523), .Y(add_subt_dataB[25])
);
AOI22X2TS U4215 ( .A0(d_ff3_LUT_out[24]), .A1(n3528), .B0(n3183), .B1(
d_ff3_sh_y_out[24]), .Y(n3524) );
OAI21X2TS U4216 ( .A0(n4546), .A1(n3515), .B0(n3524), .Y(add_subt_dataB[24])
);
OAI21X2TS U4217 ( .A0(n4545), .A1(n3518), .B0(n3525), .Y(add_subt_dataB[23])
);
AOI22X2TS U4218 ( .A0(d_ff3_LUT_out[22]), .A1(n3528), .B0(n3175), .B1(
d_ff3_sh_y_out[22]), .Y(n3526) );
OAI21X2TS U4219 ( .A0(n4543), .A1(n3515), .B0(n3526), .Y(add_subt_dataB[22])
);
AOI22X2TS U4220 ( .A0(d_ff3_LUT_out[26]), .A1(n3528), .B0(n3160), .B1(
d_ff3_sh_y_out[26]), .Y(n3529) );
OAI21X2TS U4221 ( .A0(n4550), .A1(n3530), .B0(n3529), .Y(add_subt_dataB[26])
);
NAND2X1TS U4222 ( .A(n3531), .B(d_ff3_sh_x_out[63]), .Y(n3534) );
NAND2X1TS U4223 ( .A(n3520), .B(d_ff3_sh_y_out[63]), .Y(n3533) );
NAND2X2TS U4224 ( .A(n3534), .B(n3533), .Y(add_subt_dataB[63]) );
INVX2TS U4225 ( .A(rst), .Y(n4722) );
INVX2TS U4226 ( .A(result_add_subt[36]), .Y(n4674) );
OA21X4TS U4227 ( .A0(n2624), .A1(d_ff2_Y[59]), .B0(n2156), .Y(n3548) );
NAND3X2TS U4228 ( .A(n2122), .B(n3556), .C(n2156), .Y(n4602) );
INVX2TS U4229 ( .A(n3562), .Y(n4654) );
INVX2TS U4230 ( .A(n3577), .Y(n4643) );
INVX2TS U4231 ( .A(n3582), .Y(n4686) );
INVX2TS U4232 ( .A(n3595), .Y(n4683) );
INVX2TS U4233 ( .A(n3596), .Y(n4656) );
INVX2TS U4234 ( .A(n3598), .Y(n4711) );
INVX2TS U4235 ( .A(n3601), .Y(n4698) );
INVX2TS U4236 ( .A(n3608), .Y(n4681) );
INVX2TS U4237 ( .A(n3612), .Y(n4694) );
INVX2TS U4238 ( .A(n3615), .Y(n4633) );
INVX2TS U4239 ( .A(n3616), .Y(n4696) );
INVX2TS U4240 ( .A(n3622), .Y(n4533) );
INVX2TS U4241 ( .A(n3625), .Y(n4511) );
INVX2TS U4242 ( .A(n3626), .Y(n4551) );
INVX2TS U4243 ( .A(n3628), .Y(n4507) );
INVX2TS U4244 ( .A(n3631), .Y(n4544) );
INVX2TS U4245 ( .A(n3632), .Y(n4538) );
INVX2TS U4246 ( .A(n3633), .Y(n4558) );
INVX2TS U4247 ( .A(n3634), .Y(n4542) );
INVX2TS U4248 ( .A(n3749), .Y(n4593) );
INVX2TS U4249 ( .A(n3635), .Y(n4516) );
INVX2TS U4250 ( .A(n3637), .Y(n4540) );
INVX2TS U4251 ( .A(n3639), .Y(n4514) );
INVX2TS U4252 ( .A(n3643), .Y(n4547) );
INVX2TS U4253 ( .A(n3644), .Y(beg_add_subt) );
MXI2X2TS U4254 ( .A(n3921), .B(n2470), .S0(n2629), .Y(n645) );
MXI2X2TS U4255 ( .A(n3916), .B(n2444), .S0(n2229), .Y(n693) );
MXI2X2TS U4256 ( .A(n3917), .B(n2446), .S0(n3651), .Y(n691) );
NAND3X2TS U4257 ( .A(n2122), .B(n1519), .C(n3683), .Y(n4597) );
INVX2TS U4258 ( .A(n3685), .Y(n3686) );
XNOR2X1TS U4259 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(op_add_subt)
);
INVX2TS U4260 ( .A(result_add_subt[59]), .Y(n4709) );
INVX2TS U4261 ( .A(result_add_subt[57]), .Y(n4706) );
INVX2TS U4262 ( .A(result_add_subt[27]), .Y(n4657) );
INVX2TS U4263 ( .A(result_add_subt[37]), .Y(n4676) );
INVX2TS U4264 ( .A(result_add_subt[62]), .Y(n4713) );
INVX2TS U4265 ( .A(result_add_subt[17]), .Y(n4642) );
INVX2TS U4266 ( .A(result_add_subt[28]), .Y(n4659) );
INVX2TS U4267 ( .A(result_add_subt[26]), .Y(n4655) );
INVX2TS U4268 ( .A(result_add_subt[47]), .Y(n4691) );
INVX2TS U4269 ( .A(result_add_subt[61]), .Y(n4712) );
INVX2TS U4270 ( .A(result_add_subt[34]), .Y(n4671) );
INVX2TS U4271 ( .A(result_add_subt[5]), .Y(n4628) );
INVX2TS U4272 ( .A(result_add_subt[44]), .Y(n4687) );
INVX2TS U4273 ( .A(result_add_subt[4]), .Y(n4627) );
INVX2TS U4274 ( .A(result_add_subt[60]), .Y(n4710) );
INVX2TS U4275 ( .A(result_add_subt[32]), .Y(n4667) );
INVX2TS U4276 ( .A(result_add_subt[22]), .Y(n4649) );
INVX2TS U4277 ( .A(result_add_subt[45]), .Y(n4688) );
INVX2TS U4278 ( .A(result_add_subt[42]), .Y(n4684) );
INVX2TS U4279 ( .A(result_add_subt[35]), .Y(n4673) );
INVX2TS U4280 ( .A(result_add_subt[31]), .Y(n4665) );
INVX2TS U4281 ( .A(result_add_subt[21]), .Y(n4648) );
INVX2TS U4282 ( .A(result_add_subt[38]), .Y(n4678) );
INVX2TS U4283 ( .A(result_add_subt[11]), .Y(n4635) );
INVX2TS U4284 ( .A(result_add_subt[15]), .Y(n4639) );
INVX2TS U4285 ( .A(result_add_subt[2]), .Y(n4624) );
INVX2TS U4286 ( .A(result_add_subt[16]), .Y(n4640) );
INVX2TS U4287 ( .A(result_add_subt[51]), .Y(n4699) );
INVX2TS U4288 ( .A(result_add_subt[41]), .Y(n4682) );
INVX2TS U4289 ( .A(result_add_subt[46]), .Y(n4689) );
INVX2TS U4290 ( .A(result_add_subt[30]), .Y(n4663) );
INVX2TS U4291 ( .A(result_add_subt[54]), .Y(n4703) );
INVX2TS U4292 ( .A(result_add_subt[20]), .Y(n4647) );
INVX2TS U4293 ( .A(result_add_subt[19]), .Y(n4646) );
INVX2TS U4294 ( .A(result_add_subt[9]), .Y(n4632) );
INVX2TS U4295 ( .A(result_add_subt[0]), .Y(n4622) );
INVX2TS U4296 ( .A(result_add_subt[39]), .Y(n4679) );
INVX2TS U4297 ( .A(result_add_subt[49]), .Y(n4695) );
INVX2TS U4298 ( .A(result_add_subt[14]), .Y(n4638) );
INVX2TS U4299 ( .A(result_add_subt[24]), .Y(n4652) );
INVX2TS U4300 ( .A(result_add_subt[7]), .Y(n4630) );
INVX2TS U4301 ( .A(result_add_subt[48]), .Y(n4693) );
INVX2TS U4302 ( .A(result_add_subt[6]), .Y(n4629) );
INVX2TS U4303 ( .A(result_add_subt[3]), .Y(n4625) );
INVX2TS U4304 ( .A(result_add_subt[29]), .Y(n4661) );
INVX2TS U4305 ( .A(result_add_subt[8]), .Y(n4631) );
INVX2TS U4306 ( .A(result_add_subt[63]), .Y(n4621) );
INVX2TS U4307 ( .A(result_add_subt[55]), .Y(n4704) );
INVX2TS U4308 ( .A(result_add_subt[13]), .Y(n4637) );
INVX2TS U4309 ( .A(result_add_subt[58]), .Y(n4707) );
INVX2TS U4310 ( .A(result_add_subt[40]), .Y(n4680) );
INVX2TS U4311 ( .A(result_add_subt[52]), .Y(n4701) );
INVX2TS U4312 ( .A(result_add_subt[43]), .Y(n4685) );
INVX2TS U4313 ( .A(result_add_subt[53]), .Y(n4702) );
INVX2TS U4314 ( .A(result_add_subt[12]), .Y(n4636) );
INVX2TS U4315 ( .A(result_add_subt[25]), .Y(n4653) );
INVX2TS U4316 ( .A(result_add_subt[33]), .Y(n4669) );
INVX2TS U4317 ( .A(result_add_subt[1]), .Y(n4623) );
INVX2TS U4318 ( .A(result_add_subt[10]), .Y(n4634) );
INVX2TS U4319 ( .A(result_add_subt[23]), .Y(n4650) );
INVX2TS U4320 ( .A(result_add_subt[18]), .Y(n4644) );
AND2X2TS U4321 ( .A(n3688), .B(n3687), .Y(ready_cordic) );
INVX2TS U4322 ( .A(n3692), .Y(n3694) );
AOI22X1TS U4323 ( .A0(n3696), .A1(n3701), .B0(n3752), .B1(n2504), .Y(n4715)
);
AOI22X1TS U4324 ( .A0(n3698), .A1(n3702), .B0(n3753), .B1(n2557), .Y(n4716)
);
INVX2TS U4325 ( .A(d_ff3_sh_y_out[23]), .Y(n3704) );
INVX2TS U4326 ( .A(n3708), .Y(n3712) );
CLKMX2X2TS U4327 ( .A(d_ff1_Z[4]), .B(data_in[4]), .S0(n3738), .Y(n1329) );
INVX2TS U4328 ( .A(shift_region_flag[1]), .Y(n3719) );
MXI2X1TS U4329 ( .A(n2299), .B(n3719), .S0(n3731), .Y(n1334) );
INVX2TS U4330 ( .A(operation), .Y(n3721) );
MXI2X1TS U4331 ( .A(n2320), .B(n3721), .S0(n3731), .Y(n1336) );
INVX2TS U4332 ( .A(d_ff2_X[6]), .Y(n3726) );
CLKMX2X2TS U4333 ( .A(d_ff1_Z[60]), .B(data_in[60]), .S0(n3731), .Y(n1273)
);
CLKMX2X2TS U4334 ( .A(d_ff1_Z[58]), .B(data_in[58]), .S0(n3731), .Y(n1275)
);
CLKMX2X2TS U4335 ( .A(d_ff1_Z[61]), .B(data_in[61]), .S0(n3731), .Y(n1272)
);
CLKMX2X2TS U4336 ( .A(d_ff1_Z[59]), .B(data_in[59]), .S0(n3731), .Y(n1274)
);
CLKMX2X2TS U4337 ( .A(d_ff1_Z[63]), .B(data_in[63]), .S0(n3731), .Y(n1270)
);
MXI2X1TS U4338 ( .A(n3954), .B(n3794), .S0(n3551), .Y(n593) );
MXI2X4TS U4339 ( .A(n3732), .B(d_ff3_LUT_out[2]), .S0(n3651), .Y(n3733) );
MXI2X1TS U4340 ( .A(n3802), .B(n3983), .S0(n2111), .Y(n739) );
CLKMX2X2TS U4341 ( .A(d_ff1_Z[51]), .B(data_in[51]), .S0(n3741), .Y(n1282)
);
CLKMX2X2TS U4342 ( .A(n2377), .B(data_in[40]), .S0(n1512), .Y(n1293) );
CLKMX2X2TS U4343 ( .A(d_ff1_Z[47]), .B(data_in[47]), .S0(n3738), .Y(n1286)
);
CLKMX2X2TS U4344 ( .A(n1517), .B(data_in[46]), .S0(n3741), .Y(n1287) );
CLKMX2X2TS U4345 ( .A(n2376), .B(data_in[42]), .S0(n3738), .Y(n1291) );
CLKMX2X2TS U4346 ( .A(d_ff1_Z[62]), .B(data_in[62]), .S0(n3738), .Y(n1271)
);
CLKMX2X2TS U4347 ( .A(d_ff1_Z[29]), .B(data_in[29]), .S0(n3741), .Y(n1304)
);
CLKMX2X2TS U4348 ( .A(d_ff1_Z[30]), .B(data_in[30]), .S0(n3741), .Y(n1303)
);
CLKMX2X2TS U4349 ( .A(n2438), .B(data_in[49]), .S0(n3740), .Y(n1284) );
CLKMX2X2TS U4350 ( .A(n2374), .B(data_in[37]), .S0(n3741), .Y(n1296) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk1.tcl_syn.sdf");
endmodule
|
`include "command_defines.v"
//Receives a key, value pair from FIFO arbiter.
//Composes a UDP packet and pushes it through the output queues
module packet_composer
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter NUM_QUEUES = 8,
parameter NUM_QUEUES_WIDTH = log2(NUM_QUEUES),
parameter STAGE_NUM = 4,
parameter IOQ_STAGE_NUM = 8'hff,
//parameter MAX_NUM_PROCS=2,
parameter WORKER_ADDR_WIDTH=2,
parameter TOTAL_DATA=8,
parameter MAX_NUM_WORKERS=4 //KARMA, DEEPAK-OPTIPLEX, RCG-STUDIO AND MAYA
)
(
// --- interface to next module
output reg out_wr,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl, // new checksum assuming decremented TTL
input out_rdy,
input [31:0] iteration_accum_value,
input iteration_terminate_check,
//read interface from DDR (used by flush data function)
input [63:0] dram_fifo_readdata,
output reg dram_fifo_read,
input dram_fifo_empty,
input [31:0] num_keys,
input start_update,
//i/f b/w TX EXT FIFO and packet composer
input [63:0] tx_ext_update_q,
output reg tx_ext_update_rdreq,
input tx_ext_update_empty,
input tx_ext_update_almost_full,
input [31:0] interpkt_gap_cycles,
input [31:0] shard_id,
input [31:0] log_2_num_workers_in,
// misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
localparam MAX_NUM_PROCS=2**WORKER_ADDR_WIDTH;
localparam MAC_ADDR_WIDTH=48;
localparam IP_ADDR_WIDTH=32;
reg dram_fifo_read_next;
//------------------- Internal parameters -----------------------
//Hardcode IP headers (simplfies our hardware logic)
localparam NUM_STATES = 13;
localparam WAIT_DATA = 0;
localparam READ_WAIT_FIFO = 1;
localparam WAIT_CYCLE = 2;
localparam NETFPGA_HDR = 3;
localparam WORD_0 = 4;
localparam WORD_1 = 5;
localparam WORD_2 = 6;
localparam WORD_3 = 7;
localparam WORD_4 = 8;
localparam WORD_5 = 9;
localparam WORD_6 = 10;
localparam WORD_7 = 11;
localparam INTERPKT_GAP = 12;
localparam PUT =1;
localparam FLUSH =2;
localparam TCHECK =3;
//---------------------- Wires and regs -------------------------
reg [log2(NUM_STATES)-1:0] state;
reg [log2(NUM_STATES)-1:0] state_next;
reg [DATA_WIDTH-1:0] out_data_next;
reg [CTRL_WIDTH-1:0] out_ctrl_next;
reg out_wr_next;
reg [31:0] interpkt_gap_counter, interpkt_gap_counter_next;
reg accum_value_fifo_rdreq, accum_value_fifo_rdreq_next;
wire [31:0] accum_value_fifo_dataout;
wire accum_value_fifo_empty;
wire accum_value_fifo_full;
reg [31:0] packet_sent /*synthesis noprune*/;
reg [31:0] key, key_next, val, val_next;
//wire [31:0] key_little; //key in little endian format;
//wire [31:0] val_little; //val in little endian format;
//assign key = tx_ext_update_q[63:32];
//assign val = tx_ext_update_q[31:0];
//assign key_little = {key[7:0],key[15:8],key[23:16],key[31:24]};
//assign val_little = {val[7:0],val[15:8],val[23:16],val[31:24]};
wire [31:0] mask;
assign mask = ~({32{1'b1}}<<log_2_num_workers_in);
wire [31:0] target_shard_id;
assign target_shard_id = key&mask;
//-------------------------- Logic ------------------------------
localparam INTERPKT_CLK_CYCLES = 8000; //try doubling the cycles from 4000 to 8000- as software is still overwhelmed with packet floods
reg tx_ext_update_rdreq_next;// tx_ext_update_rdreq_next;
//`include "headers.v"
//A small fifo to store the iteration accumulate value
txfifo #(
.DATA_WIDTH(32),
.LOCAL_FIFO_DEPTH(4)
) accum_value_fifo (
//.aclr (reset),
.aclr (reset),
.data (iteration_accum_value),
.clock (clk),
.rdreq (accum_value_fifo_rdreq),
.wrreq (iteration_terminate_check),
.q (accum_value_fifo_dataout),
.empty (accum_value_fifo_empty),
.full (accum_value_fifo_full),
.usedw ()
);
reg [1:0] select, select_next;
wire [DATA_WIDTH-1:0] netfpga_header;
wire [IP_ADDR_WIDTH-1:0] fpga_ip[MAX_NUM_WORKERS-1:0];
wire [IP_ADDR_WIDTH-1:0] asst_ip[MAX_NUM_WORKERS-1:0];
wire [MAC_ADDR_WIDTH-1:0] asst_mac[MAX_NUM_WORKERS-1:0];
wire [MAC_ADDR_WIDTH-1:0] nf2_mac[3:0]; //MACS OF NetFPGA ports
wire [MAC_ADDR_WIDTH-1:0] router_mac[3:0]; //MACS OF Router ports
assign fpga_ip[0]=32'h0a010101; //10.1.1.1
assign fpga_ip[1]=32'h14010101; //20.1.1.1
assign fpga_ip[2]=32'h1E010101; //30.1.1.1
assign fpga_ip[3]=32'h28010101; //40.1.1.1
assign asst_ip[0]=32'h0a010102; //10.1.1.2
assign asst_ip[1]=32'h14010102; //20.1.1.2
assign asst_ip[2]=32'h1E010102; //30.1.1.2
assign asst_ip[3]=32'h28010102; //40.1.1.2
assign asst_mac[0]=48'h0014d1176bee; //karma eth1 mac
assign asst_mac[1]=48'h0014d1176be2; //deepak-OptiPlex-780 eth1 mac
assign asst_mac[2]=48'h0014d1265344; //rcg-studio eth1 mac
assign asst_mac[3]=48'h0014d125d09f; //maya eth1 mac
assign nf2_mac[0]=48'h004e46324300;
assign nf2_mac[1]=48'h004e46324301;
assign nf2_mac[2]=48'h004e46324302;
assign nf2_mac[3]=48'h004e46324303;
assign router_mac[0]=48'h004e46324300; //karma ->nf2c0 of NetFPGA
assign router_mac[1]=48'h004e46324301; //optiPlex -> nf2c1 of NetFPGA
assign router_mac[2]=48'h004e46324302; //rcg-studio -> nf2c2 of NetFPGA
assign router_mac[3]=48'h004e46324303; //maya -> nf2c3 of NetFPGA
wire [IP_ADDR_WIDTH-1:0] src_ip;
wire [IP_ADDR_WIDTH-1:0] dst_ip;
wire [MAC_ADDR_WIDTH-1:0] src_mac;
wire [MAC_ADDR_WIDTH-1:0] dst_mac;
wire [15:0] checksum;
reg [31:0] pkt_count, pkt_count_next;
// assign netfpga_header = 64'h0001000800010040;
// all PUT requests exit through port nf2c1 (port code msb 16 bits of header = 00004)
// PUT packet will carry 150 KV pairs = 7 header words + 150 KV words
// total 157 (0x9d) words or 157*8 bytes=1256 (0x4e8) bytes
//assign netfpga_header = (select==PUT)?64'h0004000800010040:64'h0001000800010040;
assign netfpga_header = (select==PUT)?64'h0004000800010040:64'h0001000800010040;
assign src_ip = fpga_ip[shard_id];
assign dst_ip = (select==PUT)?fpga_ip[target_shard_id]:asst_ip[shard_id];
assign src_mac = (select==PUT)?nf2_mac[1]:48'h004e46324300; //Use eth0 port of netfpga always
//assign dst_mac = (select==PUT)?nf2_mac[2]:asst_mac[shard_id];
assign dst_mac = (select==PUT)?router_mac[shard_id]:asst_mac[shard_id];
wire [15:0] ether_type_16;
wire [3:0] ip_version_4;
wire [3:0] ip_hdr_length_4;
wire [7:0] ip_tos_8;
wire [15:0] ip_total_length_16;
wire [15:0] ip_id_16;
wire [2:0] ip_flags_3;
wire [12:0] ip_flag_offset_13;
wire [7:0] ip_ttl_8;
wire [7:0] ip_prot_8;
wire [15:0] udp_src_16;
wire [15:0] udp_dst_16;
wire [15:0] udp_length_16;
//08004510
assign ether_type_16=16'h0800 ;
assign ip_version_4=4'h4;
assign ip_hdr_length_4=4'h5;
assign ip_tos_8=8'h10;
//assign ip_total_length_16=(select==PUT)?16'h04da:16'h0032;
assign ip_total_length_16=(select==PUT)?16'h0032:16'h0032;
assign ip_id_16=16'hd431;
assign ip_flags_3=3'h0;
assign ip_flag_offset_13=13'h0;
assign ip_ttl_8=8'h14;
assign ip_prot_8=8'h11;
assign udp_src_16=16'h001e; //use UDP port 30
assign udp_dst_16=16'h001e; //use UDP port 30
assign udp_length_16=16'h001e; //ignore UDP length
binary_adder_tree binary_adder_tree ( .A({ip_version_4,ip_hdr_length_4,ip_tos_8}),
.B({ip_total_length_16}),
.C({ip_id_16}),
.D({ip_flags_3,ip_flag_offset_13}),
.E({ip_ttl_8,ip_prot_8}),
.F({src_ip[31:16]}),
.G({src_ip[15:0]}),
.H({dst_ip[31:16]}),
.I({dst_ip[15:0]}),
.checksum_reg(checksum),
.clk(clk)
);
reg [63:0] command_word;
always@(*) begin
case(select)
PUT: command_word = 64'h0000090000000000;
FLUSH: command_word = 64'h00000a0000000000;
TCHECK: command_word = 64'h00000b0000000000;
default: command_word = 64'h0000000000000000;
endcase
end
reg [31:0] timeout;
reg start_timeout, start_timeout_next;
wire timeout_expired;
assign timeout_expired = (timeout==0)&(start_timeout==0);
always@(posedge clk)
begin
if(reset) begin
timeout <= 0;
end
else begin
if(start_timeout) begin
timeout <= interpkt_gap_cycles;
end
else if(timeout_expired) begin
timeout <= 0;
end
else begin
timeout <= timeout-1;
end
end
end
/* Modify the packet's hdrs and add the module hdr */
always @(*) begin
state_next = state;
dram_fifo_read_next = 1'b0;
accum_value_fifo_rdreq_next = 1'b0;
// interpkt_gap_counter_next = interpkt_gap_counter;
start_timeout_next = 0;
tx_ext_update_rdreq_next = 1'b0;
select_next = select;
out_data_next = out_data;
out_ctrl_next = out_ctrl;
out_wr_next = 0;
key_next = key;
val_next = val;
pkt_count_next = pkt_count;
case(state)
WAIT_DATA: begin
pkt_count_next = 0;
//Priority decoder
if(!accum_value_fifo_empty) begin //send a packet with the currently accumulated value
accum_value_fifo_rdreq_next = 1;
state_next = READ_WAIT_FIFO;
select_next = TCHECK;
end
else if(!dram_fifo_empty) begin
dram_fifo_read_next = 1;
state_next = READ_WAIT_FIFO;
select_next = FLUSH;
end
else if((!tx_ext_update_empty)&start_update)begin //send PUT packets only when start_update signal is high- send must stop after START_UPDATE is pulled low
tx_ext_update_rdreq_next = 1;
state_next = READ_WAIT_FIFO;
select_next = PUT;
end
end
READ_WAIT_FIFO:begin
if(out_rdy) begin
state_next = WAIT_CYCLE;
end
end
WAIT_CYCLE:begin
case(select)
PUT: key_next = tx_ext_update_q[63:32];
FLUSH: key_next = dram_fifo_readdata[63:32];
TCHECK: key_next = 0;
default: key_next = 0;
endcase
case(select)
PUT: val_next = tx_ext_update_q[31:0];
FLUSH: val_next = dram_fifo_readdata[31:0];
TCHECK: val_next = accum_value_fifo_dataout[31:0];
default: val_next = 0;
endcase
/*
if(select==PUT) begin
if(pkt_count==150) begin
state_next = INTERPKT_GAP; //last kv pair
start_timeout_next = 1;
//interpkt_gap_counter_next = interpkt_gap_cycles;
end
else if(pkt_count==0) begin //first kv pair
state_next = NETFPGA_HDR;
end
else begin //any other kv pair
state_next = WORD_7;
end
end
else begin
*/
state_next = NETFPGA_HDR;
//end
end
//see http://www.stanford.edu/~hyzeng/paper/airfpga.pdf to understand
//NetFPGA packet headers
NETFPGA_HDR:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = netfpga_header; //{16'h0001,16'h0009f,16'h0001,16'h004F8}; //{port_dst(16),word_len(16), port_src(16), byte_len(16)} //
out_ctrl_next = 8'hFF;
state_next = WORD_0;
end
end
WORD_0:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {dst_mac,src_mac[47:32]};
out_ctrl_next = 8'h00;
state_next = WORD_1;
end
end
WORD_1:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {src_mac[31:0],ether_type_16,ip_version_4,ip_hdr_length_4,ip_tos_8};
out_ctrl_next = 8'h00;
state_next = WORD_2;
end
end
WORD_2:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {ip_total_length_16,ip_id_16,ip_flags_3,ip_flag_offset_13,ip_ttl_8,ip_prot_8};
out_ctrl_next = 8'h00;
state_next = WORD_3;
end
end
WORD_3:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {checksum,src_ip,dst_ip[31:16]};
out_ctrl_next = 8'h00;
state_next = WORD_4;
end
end
WORD_4:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {dst_ip[15:0],udp_src_16,udp_dst_16,udp_length_16};
out_ctrl_next = 8'h00;
state_next = WORD_5;
end
end
WORD_5:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {command_word};
out_ctrl_next = 8'h00;
state_next = WORD_6;
end
end
WORD_6:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {64'h0};
out_ctrl_next = 8'h00;
state_next = WORD_7;
end
end
WORD_7:begin
if(out_rdy) begin
out_wr_next = 1;
out_data_next = {key,val};
/*
if(select==PUT) begin
tx_ext_update_rdreq_next = (pkt_count==149)?0:1;
out_ctrl_next = (pkt_count==149)?8'h80:8'h00;
state_next = READ_WAIT_FIFO;
pkt_count_next = pkt_count+1;
end
else begin
*/
start_timeout_next = 1;
out_ctrl_next = 8'h80;
state_next = INTERPKT_GAP;
//end
end
end
INTERPKT_GAP:begin
if(timeout_expired) begin
state_next = WAIT_DATA;
end
end
endcase
end
always @(posedge clk) begin
if(reset) begin
state <= WAIT_DATA;
out_data <= 0;
out_ctrl <= 1;
out_wr <= 0;
// interpkt_gap_counter <= 0;
start_timeout <= 0;
tx_ext_update_rdreq <= 0;
dram_fifo_read <= 0;
accum_value_fifo_rdreq <= 0;
select <= 0;
out_data <= 0;
out_ctrl <= 0;
key <= 0;
val <= 0;
pkt_count <= 0;
end
else begin
//pipelined data and write signals
//to sync the last data and wr_done signals
state <= state_next;
out_data <= out_data_next;
out_ctrl <= out_ctrl_next;
out_wr <= out_wr_next;
//interpkt_gap_counter <= interpkt_gap_counter_next;
start_timeout <= start_timeout_next;
tx_ext_update_rdreq <= tx_ext_update_rdreq_next;
dram_fifo_read <= dram_fifo_read_next;
accum_value_fifo_rdreq <= accum_value_fifo_rdreq_next;
select <= select_next;
out_data <= out_data_next;
out_ctrl <= out_ctrl_next;
key <= key_next;
val <= val_next;
pkt_count <= pkt_count_next;
end // else: !if(reset)
end // always @ (posedge clk)
/*statistics collection*/
always@(posedge clk)
begin
if(reset) begin
packet_sent <= 0;
end
else begin
packet_sent <= ((state==WAIT_CYCLE)&&(select==FLUSH))?(packet_sent+1):(packet_sent);
end
end
endmodule // op_lut_process_sm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputisolatch.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hd__lpflow_inputisolatch dut (.D(D), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_TB_V
|
/*
* Copyright (c) 2015 Instrumentation Technologies
* All Rights Reserved.
*
* $Id: $
*/
// synopsys translate_off
`timescale 1ns / 1ps
// synopsys translate_on
module axi_wr_fifo #(
parameter DW = 64 , // data width (8,16,...,1024)
parameter AW = 32 , // address width
parameter FW = 5 , // address width of FIFO pointers
parameter SW = DW >> 3 // strobe width - 1 bit for every data byte
)
(
// global signals
input axi_clk_i , // global clock
input axi_rstn_i , // global reset
// Connection to AXI master
output reg [ AW-1: 0] axi_waddr_o , // write address
output reg [ DW-1: 0] axi_wdata_o , // write data
output reg [ SW-1: 0] axi_wsel_o , // write byte select
output reg axi_wvalid_o , // write data valid
output reg [ 4-1: 0] axi_wlen_o , // write burst length
output reg axi_wfixed_o , // write burst type (fixed / incremental)
input axi_werr_i , // write error
input axi_wrdy_i , // write ready
// data and configuration
input [ DW-1: 0] wr_data_i , // write data
input wr_val_i , // write data valid
input [ AW-1: 0] ctrl_start_addr_i , // range start address
input [ AW-1: 0] ctrl_stop_addr_i , // range stop address
input [ 4-1: 0] ctrl_trig_size_i , // trigger level
input ctrl_wrap_i , // start from begining when reached stop
input ctrl_clr_i , // clear / flush
output reg stat_overflow_o , // overflow indicator
output [ AW-1: 0] stat_cur_addr_o , // current address
output reg stat_write_data_o // write data indicator
);
//---------------------------------------------------------------------------------
//
// Write address channel
reg [ FW-1: 0] wr_pt ;
reg [ FW-1: 0] rd_pt ;
reg [ FW : 0] fill_lvl ;
reg [ DW-1: 0] fifo[(1<<FW)-1:0] ;
reg data_in_reg ;
reg clear ;
reg [ 4-1: 0] dat_cnt ;
reg [ AW : 0] next_address ;
reg fifo_flush ;
reg [ AW-1: 0] sys_start_addr_r ;
reg [ AW-1: 0] sys_stop_addr_r ;
reg [ 4-1: 0] sys_trig_size_r ;
wire push = wr_val_i && !fill_lvl[FW] ;
wire pop ;
wire new_burst ;
// overflow detection & indication
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_overflow_o <= 'h0 ;
end
else begin
stat_overflow_o <= fill_lvl[FW] && wr_val_i;
end
end
reg clear_do ;
always @ (posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
clear <= 1'h1 ;
clear_do <= 1'b0 ;
end
else begin
if (ctrl_clr_i)
clear_do <= 1'b1 ;
else if (clear)
clear_do <= 1'b0 ;
clear <= clear_do && !axi_wvalid_o && !new_burst;
end
end
always @ (posedge axi_clk_i)
begin
if (clear) begin
wr_pt <= 4'h0 ;
rd_pt <= 4'h0 ;
end
else begin
if (push) begin
fifo[wr_pt] <= wr_data_i ;
wr_pt <= wr_pt + {{FW-1{1'b0}},1'b1} ;
end
if (pop) begin
axi_wdata_o <= fifo[rd_pt] ;
rd_pt <= rd_pt + {{FW-1{1'b0}},1'b1} ;
end
end
end
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
data_in_reg <= 'h0 ;
end
else begin
if (pop)
data_in_reg <= 1'b1 ;
else if ((axi_wrdy_i && axi_wvalid_o) || clear)
data_in_reg <= 1'b0 ;
end
end
wire fifo_flush_cond = |fill_lvl && !wr_val_i && !dat_cnt[3:1];
always @(posedge axi_clk_i)
begin
if (clear) begin
fill_lvl <= {FW+1{1'h0}} ;
fifo_flush <= 1'h0 ;
end
else begin
if (push && !pop)
fill_lvl <= fill_lvl + {{FW{1'b0}}, 1'h1} ;
else if(!push && pop)
fill_lvl <= fill_lvl - {{FW{1'b0}}, 1'h1} ;
if (fifo_flush_cond)
fifo_flush <= 1'b1 ;
else if (axi_wrdy_i)
fifo_flush <= 1'b0 ;
end
end
wire [8 :0] next_end_address = next_address[10:3] + {3'h0,fill_lvl} ; // to where we have data
wire [AW :0] next_stop_address = {1'b0,sys_stop_addr_r[AW-1:3]} - next_address[AW:3] - {{AW-FW+1{1'h0}},fill_lvl} ;
// select which boundary condition is more restricting - 0x0 - 4k boundary is more restricting; 0x1 end address is more restricting
wire [AW+1:0] boundary_condition = {1'b0,next_address[AW:3]} + {{AW-FW+1{1'h0}},fill_lvl} - {1'b0,sys_stop_addr_r[AW-1:3]} ;
// select which boundary condition is more restricting, next transmission would cross the 4k address boundary (64-bit access) or stop address
wire [2 :0] boundary_cross = {boundary_condition[AW+1], next_end_address[8],next_stop_address[AW]} ;
// prevents data to be trapped in output register
reg single_burst ;
reg single_burst_r ;
wire single_burst_posedge = !single_burst_r && single_burst;
always @(posedge axi_clk_i)
begin
if (clear) begin
single_burst <= 'h0 ;
single_burst_r <= 'h0 ;
end
else begin
single_burst <= (!fill_lvl && !fifo_flush && !dat_cnt && data_in_reg) ;
single_burst_r <= single_burst ;
end
end
assign new_burst = (((fifo_flush && axi_wrdy_i) || (fill_lvl >= {{FW-4{1'b0}},sys_trig_size_r})) && !dat_cnt && |fill_lvl
|| single_burst_posedge)
&& !clear_do;
always @(posedge axi_clk_i)
begin
if (clear) begin
dat_cnt <= 4'h0 ;
axi_wsel_o <= {SW{1'b1}} ;
axi_wfixed_o <= 1'b0 ;
axi_wlen_o <= 4'h0 ;
end
else begin
if (new_burst && (next_address <= {1'b0,sys_stop_addr_r})) begin
if (boundary_cross[1:0] || fill_lvl[FW:4]) begin
if (fill_lvl[FW:4] && !boundary_cross[1:0]) begin //enough space to stop address --!boundary_cross[1:0]
dat_cnt <= 4'hF ;
axi_wlen_o <= 4'hF ;
end
else begin
// select which boundary condition is more restricting
// 0x0 - 4k boundary is more restricting
// 0x1 - end address is more restricting
if (boundary_cross[2]) begin
dat_cnt <= 4'hF - next_address[6:3];
axi_wlen_o <= 4'hF - next_address[6:3];
end
else begin
dat_cnt <= sys_stop_addr_r[6:3] - next_address[6:3];
axi_wlen_o <= sys_stop_addr_r[6:3] - next_address[6:3];
end
end
end
else begin
if (fifo_flush || fifo_flush_cond) begin
dat_cnt <= fill_lvl[3:0] - 4'h1 ;
axi_wlen_o <= fill_lvl[3:0] - 4'h1 ;
end
else begin
dat_cnt <= fill_lvl[3:0] ;
axi_wlen_o <= fill_lvl[3:0] ;
end
end
end
else if (axi_wrdy_i && axi_wvalid_o && dat_cnt) begin
dat_cnt <= dat_cnt - 4'h1;
axi_wlen_o <= axi_wlen_o - 4'h1;
end
end
end
wire [4-1: 0] aaaa = 4'hF - next_address[6:3];
wire [4-1: 0] bbbb = sys_stop_addr_r[6:3] - next_address[6:3];
wire [4-1: 0] cccc = fill_lvl[3:0] - 4'h1;
wire [4-1: 0] dddd = fill_lvl[3:0];
assign pop = (!data_in_reg && fill_lvl) || ((|dat_cnt || (new_burst && axi_wvalid_o))
&& axi_wrdy_i && axi_wvalid_o && fill_lvl) ;
always @(posedge axi_clk_i)
begin
if (clear) begin
axi_wvalid_o <= 1'h0 ;
axi_waddr_o <= ctrl_start_addr_i ;
next_address <= {1'b0,ctrl_start_addr_i} ;
sys_start_addr_r <= ctrl_start_addr_i ;
sys_stop_addr_r <= ctrl_stop_addr_i ;
sys_trig_size_r <= ctrl_trig_size_i ;
end
else begin
if ((next_address <= {1'b0,sys_stop_addr_r}) && // still in address rage
( (new_burst && axi_wrdy_i) || (|dat_cnt && axi_wrdy_i && fill_lvl) ) ) begin //new burst || still data in package
axi_wvalid_o <= 1'h1 ;
next_address <= next_address + DW/8 ; // in bytes
axi_waddr_o <= next_address[AW-1:0] ;
end
else if (ctrl_wrap_i && new_burst && (axi_waddr_o==sys_stop_addr_r)) begin //wrap around
axi_wvalid_o <= 1'h1 ;
next_address <= {1'b0,sys_start_addr_r} + DW/8 ; // in bytes
axi_waddr_o <= sys_start_addr_r ;
end
else if (axi_wrdy_i) begin
axi_wvalid_o <= 1'h0 ;
end
end
end
// write data indication
always @(posedge axi_clk_i)
begin
if (!axi_rstn_i) begin
stat_write_data_o <= 'h0 ;
end
else begin
stat_write_data_o <= (next_address <= {1'b0,sys_stop_addr_r}) ; // address in range
end
end
assign stat_cur_addr_o = next_address ; // current address
endmodule // axi_wr_fifo
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : LBIT BLT State Machine
// File : dex_smblt.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smlblt
(
input de_clk,
input de_rstn,
input goblt,
input stpl_pk_1,
input apat_1,
input sor,
input eof,
input sos,
input eos,
input local_eol,
input mcrdy,
input signx,
input signy,
input yeqz,
input xeqz,
input read_2,
input ps32_1,
input ps16_1,
input ps32_2,
input ps16_2,
input eol_2,
input local_sol,
input eor,
input ps8_2,
input apat32_2,
input soc,
input cache_rdy,
input sfd_2,
input wr_gt_8_16,
input wrk5_eqz,
input mw_fip,
input rmw,
output reg [21:0] lb_op,
output reg [4:0] lb_ksel,
output reg lb_set_busy,
output reg lb_clr_busy,
output reg lb_ld_wcnt,
output reg lb_mem_req,
output reg lb_mem_rd,
output reg lb_dchgy,
output reg lb_rstn_wad,
output reg lb_ld_rad,
output reg lb_ld_rad_e,
output reg lb_set_sol,
output reg lb_set_eol,
output reg lb_ld_msk,
output reg lb_set_soc,
output reg lb_clr_soc,
output reg lb_set_local_eol,
output reg lb_clr_local_eol,
output reg lb_set_sos,
output reg lb_clr_sos,
output reg lb_set_eos,
output reg lb_clr_eos,
output reg lb_set_sor,
output reg lb_clr_sor,
output reg lb_set_eof,
output reg lb_clr_eof,
output reg lb_clr_sol,
output reg tx_clr_seol,
output reg lb_mul,
output reg lb_rst_cr
);
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
parameter
LB_WAIT = 5'h0,
LBS1 = 5'h1,
LBS2 = 5'h2,
LBS3 = 5'h3,
LBS4 = 5'h4,
LBS5 = 5'h5,
LBS6 = 5'h6,
LBS7 = 5'h7,
LBS8 = 5'h8,
LBR1 = 5'h9,
LBR2 = 5'ha,
LBR3 = 5'hb,
LBW1 = 5'hc,
LBW2 = 5'hd,
LBW3 = 5'he,
LBW4 = 5'hf,
LBW5 = 5'h10,
LBW6 = 5'h11,
LBW7 = 5'h12,
LBW8 = 5'h13,
LBW9 = 5'h14,
LBW10 = 5'h15,
LBW11 = 5'h16,
LBNL1 = 5'h17,
LBNL2 = 5'h18,
LBNL3 = 5'h19,
LBNL4 = 5'h1a,
LBNL5 = 5'h1b,
LBNL6 = 5'h1c,
LBTX0 = 5'h1e,
LBTX1 = 5'h1f,
noop = 5'h0,
src = 5'h0,
dst = 5'h1,
size = 5'h2,
sorgl = 5'he,
pline = 5'h10,
dorgl = 5'hf,
dst_sav = 5'h9,
wr_wrds_sav = 5'hc,
sav_rad = 5'h3,
hst_pg_cnt = 5'h7,
wr_wrds = 5'h6,
pg_ff = 5'h5,
wr_seg = 5'hd,
pages = 5'h7,
sav_wr_wrds = 5'h8,
pages_X16 = 5'h7,
sav_src_dst = 5'h3,
apcn = 5'h6,
mov_k = 5'he,
movx = 5'hf,
mov = 5'hd,
add = 5'h1,
pad_x = 5'h9,
pix_ln = 5'h5,
c_m_bnib = 5'h10,
X4 = 5'h15,
X8 = 5'h18,
pix_ff = 5'h4,
addnib = 5'h2,
div16 = 5'ha,
sub = 5'h12,
sublin = 5'h1c,
subx = 5'h13,
div4l = 5'h1d,
div8l = 5'h1e,
div16l = 5'h1f,
amcn = 5'h4,
X16 = 5'h19,
addlin = 5'h1b,
wrlo = 2'b10,
wrhi = 2'b01,
wrno = 2'b11,
wrhl = 2'b00,
one = 5'h1,
four = 5'h4,
seven = 5'h5,
eight = 5'h6,
D64 = 5'h11,
D112 = 5'h14,
D128 = 5'h15,
D896 = 5'h16;
/****************************************************************/
/* define internal wires and make assignments */
reg [4:0] lb_cs;
reg [4:0] lb_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)lb_cs <= 5'b0;
else lb_cs <= lb_ns;
end
always @*
begin
lb_op = 22'b00000_00000_00000_00000_11;
lb_ksel = one;
lb_set_busy = 1'b0;
lb_clr_busy = 1'b0;
lb_ld_wcnt = 1'b0;
lb_mem_req = 1'b0;
lb_mem_rd = 1'b0;
lb_dchgy = 1'b0;
lb_rstn_wad = 1'b0;
lb_ld_rad = 1'b0;
lb_ld_rad_e = 1'b0;
lb_set_sol = 1'b0;
lb_set_eol = 1'b0;
lb_mem_rd = 1'b0;
lb_ld_msk = 1'b0;
lb_set_soc = 1'b0;
lb_clr_soc = 1'b0;
lb_set_local_eol = 1'b0;
lb_clr_local_eol = 1'b0;
lb_set_sos = 1'b0;
lb_clr_sos = 1'b0;
lb_set_eos = 1'b0;
lb_clr_eos = 1'b0;
lb_set_sor = 1'b0;
lb_clr_sor = 1'b0;
lb_set_eof = 1'b0;
lb_clr_eof = 1'b0;
lb_clr_sol = 1'b0;
tx_clr_seol = 1'b0;
lb_mul = 1'b0;
lb_rst_cr = 1'b0;
case(lb_cs) /* synopsys full_case parallel_case */
/* Calculate the number of bits per line including 32bit or 8bit padding. */
/* ELSE wait. */
LB_WAIT: if(goblt && stpl_pk_1 && !apat_1)
begin
if(read_2)lb_ns=LBS1;
else begin
lb_ns=LBS4;
lb_mul = 1'b1;
end
lb_op={size,noop,pad_x,pix_ln,wrlo};
lb_set_busy = 1'b1;
lb_mul = 1'b1;
end
else lb_ns= LB_WAIT;
/* add org low nibble to source point */
LBS1: begin
lb_op={sorgl,src,add,src,wrhi};
if(read_2)lb_ns=LBS2;
else lb_ns=LBS4;
end
/* The first step to calculate the number of pixels in the fifo, is 128 bytes */
/* minus the source offset. */
LBS2: begin
lb_op={noop,pline,c_m_bnib,noop,wrno};
lb_ns=LBS3;
lb_ksel=D128;
end
/* The second step to calculate the number of pixels in the fifo, is multiply by 8 */
LBS3: begin
lb_op={pline,noop,X8,pix_ff,wrhi};
lb_ns=LBS4;
end
/* Add org destination point and */
/* save the original destination X, to use on the next scan line. */
LBS4: begin
lb_op={dorgl,dst,addnib,dst_sav,wrhl};
lb_ns=LBS5;
lb_set_sol=1'b1; // set start of line.
lb_set_sor=1'b1; // set start of reads.
lb_set_soc=1'b1; // set start of command.
end
/* calculate the write words per line adjusted X size. */
/* load the word count register for sfd mode. */
LBS5: begin
lb_ns=LBS6;
lb_op={pline,size,div16,wr_wrds_sav,wrhi};
end
/* generate the start and end mask to be loaded in LBS10. */
LBS6: begin
lb_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
lb_ns=LBS7;
lb_op={dst,size,add,noop,wrno};
lb_rstn_wad = 1'b1;
end
LBS7: begin
lb_ns=LBS8;
if(ps32_2 && !read_2)lb_op={src,src,add,noop,wrno};
else if(ps16_2 && !read_2)lb_op={src,noop,X4,noop,wrno};
else lb_op={src,noop,X8,noop,wrno};
lb_ld_msk=1'b1; /* load the mask generated in LBS6. */
end
/* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */
/* this will set the first read 8 flag if source nibble is less than destination nibble.*/
LBS8: begin
if(read_2 && mcrdy)begin
lb_ns=LBR1;
if(wrk5_eqz | wr_gt_8_16)lb_ld_rad = 1'b1;
lb_op={pline,dst,sublin,sav_rad,wrhi};
end
else if(sfd_2 && !wr_gt_8_16 && mcrdy)
begin
lb_ns=LBTX0;
lb_set_eol=1'b1;
lb_op={pline,dst,sublin,sav_rad,wrhi};
end
else if (mcrdy)
begin
lb_ns=LBW3;
lb_ld_rad = 1'b1;
lb_op={pline,dst,sublin,sav_rad,wrhi};
end
else
begin
lb_ns=LBS8;
lb_op={noop,pline,mov,noop,wrno};
end
end
/* set the number of pages per read. */
LBR1: begin
lb_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
lb_ns=LBR2;
if(!wrk5_eqz && soc)lb_op={noop,hst_pg_cnt,movx,noop,wrno};
else lb_op={noop,noop,mov_k,noop,wrno};
if(sor) lb_ksel=eight;
else lb_ksel=seven;
end
LBR2: begin
lb_ns=LBR3;
if(!sor)lb_op={pix_ff,noop,apcn,pix_ff,wrhi};
lb_ksel=D896;
end
/* request the page read. */
LBR3: begin
if(mcrdy && !mw_fip)
begin
lb_mem_req=1'b1;
lb_mem_rd=1'b1;
lb_ns=LBW1;
lb_op={noop,wr_wrds,mov,noop,wrno};
lb_ld_wcnt=1'b1;
end
else lb_ns=LBR3;
end
/* subtract pixel per line from pixels in the fifo. */
/* to find out which is larger. */
LBW1: begin
if(!wrk5_eqz && !wr_gt_8_16 && soc)
begin
lb_ns=LBTX0;
lb_set_eol=1'b1;
lb_op={noop,sav_rad,mov,noop,wrno};
end
else begin
lb_ns=LBW2;
lb_op={pix_ff,pix_ln,subx,noop,wrno};
end
end
/* calculate the pages in the fifo. */
LBW2: begin
lb_ns=LBW3;
if(ps8_2)lb_op={dst,pix_ff,div16l,pg_ff,wrhi};
else if(ps16_2)lb_op={dst,pix_ff,div8l,pg_ff,wrhi};
else lb_op={dst,pix_ff,div4l,pg_ff,wrhi};
end
/* calculate the segment count. */
/* if no read segment equals words per line count. */
LBW3: begin
lb_ns=LBW4;
if(signx && read_2)
begin /* write the whole fifo to memory. */
lb_op={pline,noop,amcn,wr_seg,wrhi};
lb_set_eof=1'b1;
lb_set_sos=1'b1;
end
else if(xeqz && read_2)
begin /* write the whole fifo to memory. */
lb_op={noop,wr_wrds,mov,wr_seg,wrhi};
lb_set_eof=1'b1;
lb_set_local_eol=1'b1;
end
else begin /* write the whole line to memory. */
lb_op={noop,wr_wrds,mov,wr_seg,wrhi};
lb_set_local_eol=1'b1;
end
end
/* write segment minus max page count of seven */
/* or eight if no read. */
LBW4: begin
if(mcrdy && cache_rdy)
begin
lb_ns=LBW5;
lb_op={pline,noop,amcn,noop,wrno};
// lb_ksel=eight;
if(!rmw)lb_ksel=eight;
else lb_ksel=four;
end
else begin
lb_ns=LBW4;
lb_op={noop,pline,mov,noop,wrno};
end
end
/* Wait for the pipline. */
LBW5: begin
if(xeqz)lb_ns=LBNL3;
else if(soc)
begin
lb_ns=LBW6;
lb_clr_soc=1'b1;
end
else lb_ns=LBW6;
if(sos)begin
lb_clr_sos=1'b1;
lb_op={wr_seg,noop,movx,wr_wrds,wrlo};
end
end
/* calculate the pages to request. */
LBW6: begin
lb_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
lb_ns=LBW7;
// lb_ksel=eight;
if(!rmw)lb_ksel=eight;
else lb_ksel=four;
if((xeqz || signx) && (local_eol || !read_2))
begin /* end of segment and end of line. */
/* must setup for next line. */
lb_op={noop,wr_seg,mov,pages,wrhi};
lb_set_eol=1'b1;
lb_set_eos=1'b1;
end
else if(xeqz || signx)
begin /* end of this segment and not end of line. */
/* need more read data. */
lb_op={noop,wr_seg,mov,pages,wrhi};
lb_set_eos=1'b1;
end
else lb_op={noop,noop,mov_k,pages,wrhi};
end
/* update the segment page count. */
LBW7: begin
lb_op={pline,dst,X16,pages,wrhi};
lb_ns=LBW8;
end
/* update the segment page count. */
LBW8: begin
lb_mem_req=1'b1;
if(read_2)lb_ns=LBW9;
else lb_ns=LBW10;
if(eof && eos && !local_eol)lb_op={sav_wr_wrds,wr_wrds,subx,wr_wrds,wrhi};
else if(eof && eos)lb_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
else lb_op={wr_seg,pages,sub,wr_seg,wrhi};
end
/* update the pixels in the fifo count. */
LBW9: begin
if(local_eol && eos)lb_op={pix_ff,pix_ln,subx,pix_ff,wrhi};
lb_ns=LBW10;
lb_clr_sol = 1'b1;
end
/* update the destination X. */
LBW10: begin
if(read_2)lb_op={dst,pages_X16,add,dst,wrhi};
else lb_op={dst,noop,apcn,dst,wrhi};
if(local_eol && eos)lb_ns = LBNL1;
else if(eof && eos)lb_ns = LBNL3;
else lb_ns=LBW11;
// lb_ksel=D128;
if(!rmw)lb_ksel=D128;
else lb_ksel=D64;
end
/* update the destination X. */
LBW11: begin
lb_op={noop,wr_seg,mov,noop,wrno};
lb_ns=LBW4;
end
/* restore the write words per line. */
LBNL1: begin
lb_ns=LBNL2;
if(read_2)lb_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
else lb_op={noop,sav_wr_wrds,mov,wr_seg,wrhi};
lb_dchgy = 1'b1;
end
LBNL2: begin
if(mcrdy)
begin
lb_op={sav_rad,pix_ln,addlin,sav_rad,wrhi};
lb_ld_rad = 1'b1;
if(read_2)lb_ns=LBNL3;
else lb_ns=LBNL4;
end
else lb_ns=LBNL2;
end
/* Increment the source Y registers. */
LBNL3: begin
lb_ns=LBNL4;
if(eof)lb_op={src,noop,apcn,src,wrhi};
if(sor && eof)begin
lb_ksel=D128;
lb_clr_sor=1'b1;
end
else lb_ksel=D112;
end
LBNL4: begin
if((local_eol && eos) || !read_2)begin
lb_op={size,noop,amcn,size,wrlo};
lb_set_sol=1'b1;
end
else lb_op={noop,size,mov,noop,wrno};
lb_clr_eos=1'b1;
lb_ns=LBNL5;
end
/* Wait for pipeline delay. */
LBNL5: lb_ns=LBNL6;
/* If Y size register goes to zero the bit blt is all done. */
/* else go back and read more data. */
/* Restore the original X destination registers. */
LBNL6: begin
if(yeqz)begin
lb_clr_busy = 1'b1;
lb_ns=LB_WAIT;
lb_rst_cr = 1'b1;
end
else if(eof & read_2)begin
lb_ns=LBR1;
lb_clr_eof = 1'b1;
if(local_eol)lb_op={noop,sav_src_dst,movx,dst,wrhi};
end
else if(!read_2)
begin
lb_ns=LBW3;
lb_op={noop,sav_src_dst,movx,dst,wrhi};
end
else begin
lb_ns=LBW1;
lb_op={noop,sav_src_dst,movx,dst,wrhi};
end
lb_clr_local_eol=1'b1;
end
LBTX0: begin
if(!soc && yeqz)
begin
lb_clr_busy = 1'b1;
lb_ns=LB_WAIT;
lb_rst_cr = 1'b1;
tx_clr_seol = 1'b1;
end
else if(mcrdy && cache_rdy)
begin
lb_op={size,noop,amcn,size,wrlo};
// lb_dchgy = 1'b1;
lb_ns=LBTX1;
lb_clr_soc=1'b1;
lb_ld_rad_e = 1'b1;
// NEW
lb_set_sol=1'b1;
lb_set_eol=1'b1;
//
end
else begin
lb_ns=LBTX0;
lb_set_soc = 1'b1;
lb_op={noop,pline,mov,noop,wrno};
end
end
LBTX1: begin
lb_ns=LBTX0;
lb_op={sav_rad,pix_ln,addlin,sav_rad,wrhi};
lb_mem_req=1'b1;
lb_dchgy = 1'b1;
// OLD
// lb_set_sol=1'b1;
// lb_set_eol=1'b1;
end
endcase
end
endmodule
|
//-----------------------------------------------------------------
// RISC-V Core
// V1.0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// [email protected]
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014-2019, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
module riscv_issue
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter SUPPORT_MULDIV = 1
,parameter SUPPORT_DUAL_ISSUE = 1
,parameter SUPPORT_LOAD_BYPASS = 1
,parameter SUPPORT_MUL_BYPASS = 1
,parameter SUPPORT_REGFILE_XILINX = 0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input fetch_valid_i
,input [ 31:0] fetch_instr_i
,input [ 31:0] fetch_pc_i
,input fetch_fault_fetch_i
,input fetch_fault_page_i
,input fetch_instr_exec_i
,input fetch_instr_lsu_i
,input fetch_instr_branch_i
,input fetch_instr_mul_i
,input fetch_instr_div_i
,input fetch_instr_csr_i
,input fetch_instr_rd_valid_i
,input fetch_instr_invalid_i
,input branch_exec_request_i
,input branch_exec_is_taken_i
,input branch_exec_is_not_taken_i
,input [ 31:0] branch_exec_source_i
,input branch_exec_is_call_i
,input branch_exec_is_ret_i
,input branch_exec_is_jmp_i
,input [ 31:0] branch_exec_pc_i
,input branch_d_exec_request_i
,input [ 31:0] branch_d_exec_pc_i
,input [ 1:0] branch_d_exec_priv_i
,input branch_csr_request_i
,input [ 31:0] branch_csr_pc_i
,input [ 1:0] branch_csr_priv_i
,input [ 31:0] writeback_exec_value_i
,input writeback_mem_valid_i
,input [ 31:0] writeback_mem_value_i
,input [ 5:0] writeback_mem_exception_i
,input [ 31:0] writeback_mul_value_i
,input writeback_div_valid_i
,input [ 31:0] writeback_div_value_i
,input [ 31:0] csr_result_e1_value_i
,input csr_result_e1_write_i
,input [ 31:0] csr_result_e1_wdata_i
,input [ 5:0] csr_result_e1_exception_i
,input lsu_stall_i
,input take_interrupt_i
// Outputs
,output fetch_accept_o
,output branch_request_o
,output [ 31:0] branch_pc_o
,output [ 1:0] branch_priv_o
,output exec_opcode_valid_o
,output lsu_opcode_valid_o
,output csr_opcode_valid_o
,output mul_opcode_valid_o
,output div_opcode_valid_o
,output [ 31:0] opcode_opcode_o
,output [ 31:0] opcode_pc_o
,output opcode_invalid_o
,output [ 4:0] opcode_rd_idx_o
,output [ 4:0] opcode_ra_idx_o
,output [ 4:0] opcode_rb_idx_o
,output [ 31:0] opcode_ra_operand_o
,output [ 31:0] opcode_rb_operand_o
,output [ 31:0] lsu_opcode_opcode_o
,output [ 31:0] lsu_opcode_pc_o
,output lsu_opcode_invalid_o
,output [ 4:0] lsu_opcode_rd_idx_o
,output [ 4:0] lsu_opcode_ra_idx_o
,output [ 4:0] lsu_opcode_rb_idx_o
,output [ 31:0] lsu_opcode_ra_operand_o
,output [ 31:0] lsu_opcode_rb_operand_o
,output [ 31:0] mul_opcode_opcode_o
,output [ 31:0] mul_opcode_pc_o
,output mul_opcode_invalid_o
,output [ 4:0] mul_opcode_rd_idx_o
,output [ 4:0] mul_opcode_ra_idx_o
,output [ 4:0] mul_opcode_rb_idx_o
,output [ 31:0] mul_opcode_ra_operand_o
,output [ 31:0] mul_opcode_rb_operand_o
,output [ 31:0] csr_opcode_opcode_o
,output [ 31:0] csr_opcode_pc_o
,output csr_opcode_invalid_o
,output [ 4:0] csr_opcode_rd_idx_o
,output [ 4:0] csr_opcode_ra_idx_o
,output [ 4:0] csr_opcode_rb_idx_o
,output [ 31:0] csr_opcode_ra_operand_o
,output [ 31:0] csr_opcode_rb_operand_o
,output csr_writeback_write_o
,output [ 11:0] csr_writeback_waddr_o
,output [ 31:0] csr_writeback_wdata_o
,output [ 5:0] csr_writeback_exception_o
,output [ 31:0] csr_writeback_exception_pc_o
,output [ 31:0] csr_writeback_exception_addr_o
,output exec_hold_o
,output mul_hold_o
,output interrupt_inhibit_o
);
`include "riscv_defs.v"
wire enable_muldiv_w = SUPPORT_MULDIV;
wire enable_mul_bypass_w = SUPPORT_MUL_BYPASS;
wire stall_w;
wire squash_w;
//-------------------------------------------------------------
// Priv level
//-------------------------------------------------------------
reg [1:0] priv_x_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
priv_x_q <= `PRIV_MACHINE;
else if (branch_csr_request_i)
priv_x_q <= branch_csr_priv_i;
//-------------------------------------------------------------
// Issue Select
//-------------------------------------------------------------
wire opcode_valid_w = fetch_valid_i & ~squash_w & ~branch_csr_request_i;
// Branch request (CSR branch - ecall, xret, or branch instruction)
assign branch_request_o = branch_csr_request_i | branch_d_exec_request_i;
assign branch_pc_o = branch_csr_request_i ? branch_csr_pc_i : branch_d_exec_pc_i;
assign branch_priv_o = branch_csr_request_i ? branch_csr_priv_i : priv_x_q;
//-------------------------------------------------------------
// Instruction Decoder
//-------------------------------------------------------------
wire [4:0] issue_ra_idx_w = fetch_instr_i[19:15];
wire [4:0] issue_rb_idx_w = fetch_instr_i[24:20];
wire [4:0] issue_rd_idx_w = fetch_instr_i[11:7];
wire issue_sb_alloc_w = fetch_instr_rd_valid_i;
wire issue_exec_w = fetch_instr_exec_i;
wire issue_lsu_w = fetch_instr_lsu_i;
wire issue_branch_w = fetch_instr_branch_i;
wire issue_mul_w = fetch_instr_mul_i;
wire issue_div_w = fetch_instr_div_i;
wire issue_csr_w = fetch_instr_csr_i;
wire issue_invalid_w = fetch_instr_invalid_i;
//-------------------------------------------------------------
// Pipeline status tracking
//-------------------------------------------------------------
wire pipe_squash_e1_e2_w;
reg opcode_issue_r;
reg opcode_accept_r;
wire pipe_stall_raw_w;
wire pipe_load_e1_w;
wire pipe_store_e1_w;
wire pipe_mul_e1_w;
wire pipe_branch_e1_w;
wire [4:0] pipe_rd_e1_w;
wire [31:0] pipe_pc_e1_w;
wire [31:0] pipe_opcode_e1_w;
wire [31:0] pipe_operand_ra_e1_w;
wire [31:0] pipe_operand_rb_e1_w;
wire pipe_load_e2_w;
wire pipe_mul_e2_w;
wire [4:0] pipe_rd_e2_w;
wire [31:0] pipe_result_e2_w;
wire pipe_valid_wb_w;
wire pipe_csr_wb_w;
wire [4:0] pipe_rd_wb_w;
wire [31:0] pipe_result_wb_w;
wire [31:0] pipe_pc_wb_w;
wire [31:0] pipe_opc_wb_w;
wire [31:0] pipe_ra_val_wb_w;
wire [31:0] pipe_rb_val_wb_w;
wire [`EXCEPTION_W-1:0] pipe_exception_wb_w;
wire [`EXCEPTION_W-1:0] issue_fault_w = fetch_fault_fetch_i ? `EXCEPTION_FAULT_FETCH:
fetch_fault_page_i ? `EXCEPTION_PAGE_FAULT_INST: `EXCEPTION_W'b0;
riscv_pipe_ctrl
#(
.SUPPORT_LOAD_BYPASS(SUPPORT_LOAD_BYPASS)
,.SUPPORT_MUL_BYPASS(SUPPORT_MUL_BYPASS)
)
u_pipe_ctrl
(
.clk_i(clk_i)
,.rst_i(rst_i)
// Issue
,.issue_valid_i(opcode_issue_r)
,.issue_accept_i(opcode_accept_r)
,.issue_stall_i(stall_w)
,.issue_lsu_i(issue_lsu_w)
,.issue_csr_i(issue_csr_w)
,.issue_div_i(issue_div_w)
,.issue_mul_i(issue_mul_w)
,.issue_branch_i(issue_branch_w)
,.issue_rd_valid_i(issue_sb_alloc_w)
,.issue_rd_i(issue_rd_idx_w)
,.issue_exception_i(issue_fault_w)
,.issue_pc_i(opcode_pc_o)
,.issue_opcode_i(opcode_opcode_o)
,.issue_operand_ra_i(opcode_ra_operand_o)
,.issue_operand_rb_i(opcode_rb_operand_o)
,.issue_branch_taken_i(branch_d_exec_request_i)
,.issue_branch_target_i(branch_d_exec_pc_i)
,.take_interrupt_i(take_interrupt_i)
// Execution stage 1: ALU result
,.alu_result_e1_i(writeback_exec_value_i)
,.csr_result_value_e1_i(csr_result_e1_value_i)
,.csr_result_write_e1_i(csr_result_e1_write_i)
,.csr_result_wdata_e1_i(csr_result_e1_wdata_i)
,.csr_result_exception_e1_i(csr_result_e1_exception_i)
// Execution stage 1
,.load_e1_o(pipe_load_e1_w)
,.store_e1_o(pipe_store_e1_w)
,.mul_e1_o(pipe_mul_e1_w)
,.branch_e1_o(pipe_branch_e1_w)
,.rd_e1_o(pipe_rd_e1_w)
,.pc_e1_o(pipe_pc_e1_w)
,.opcode_e1_o(pipe_opcode_e1_w)
,.operand_ra_e1_o(pipe_operand_ra_e1_w)
,.operand_rb_e1_o(pipe_operand_rb_e1_w)
// Execution stage 2: Other results
,.mem_complete_i(writeback_mem_valid_i)
,.mem_result_e2_i(writeback_mem_value_i)
,.mem_exception_e2_i(writeback_mem_exception_i)
,.mul_result_e2_i(writeback_mul_value_i)
// Execution stage 2
,.load_e2_o(pipe_load_e2_w)
,.mul_e2_o(pipe_mul_e2_w)
,.rd_e2_o(pipe_rd_e2_w)
,.result_e2_o(pipe_result_e2_w)
,.stall_o(pipe_stall_raw_w)
,.squash_e1_e2_o(pipe_squash_e1_e2_w)
,.squash_e1_e2_i(1'b0)
,.squash_wb_i(1'b0)
// Out of pipe: Divide Result
,.div_complete_i(writeback_div_valid_i)
,.div_result_i(writeback_div_value_i)
// Commit
,.valid_wb_o(pipe_valid_wb_w)
,.csr_wb_o(pipe_csr_wb_w)
,.rd_wb_o(pipe_rd_wb_w)
,.result_wb_o(pipe_result_wb_w)
,.pc_wb_o(pipe_pc_wb_w)
,.opcode_wb_o(pipe_opc_wb_w)
,.operand_ra_wb_o(pipe_ra_val_wb_w)
,.operand_rb_wb_o(pipe_rb_val_wb_w)
,.exception_wb_o(pipe_exception_wb_w)
,.csr_write_wb_o(csr_writeback_write_o)
,.csr_waddr_wb_o(csr_writeback_waddr_o)
,.csr_wdata_wb_o(csr_writeback_wdata_o)
);
assign exec_hold_o = stall_w;
assign mul_hold_o = stall_w;
//-------------------------------------------------------------
// Pipe1 - Status tracking
//-------------------------------------------------------------
assign csr_writeback_exception_o = pipe_exception_wb_w;
assign csr_writeback_exception_pc_o = pipe_pc_wb_w;
assign csr_writeback_exception_addr_o = pipe_result_wb_w;
//-------------------------------------------------------------
// Blocking events (division, CSR unit access)
//-------------------------------------------------------------
reg div_pending_q;
reg csr_pending_q;
// Division operations take 2 - 34 cycles and stall
// the pipeline (complete out-of-pipe) until completed.
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
div_pending_q <= 1'b0;
else if (pipe_squash_e1_e2_w)
div_pending_q <= 1'b0;
else if (div_opcode_valid_o && issue_div_w)
div_pending_q <= 1'b1;
else if (writeback_div_valid_i)
div_pending_q <= 1'b0;
// CSR operations are infrequent - avoid any complications of pipelining them.
// These only take a 2-3 cycles anyway and may result in a pipe flush (e.g. ecall, ebreak..).
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
csr_pending_q <= 1'b0;
else if (pipe_squash_e1_e2_w)
csr_pending_q <= 1'b0;
else if (csr_opcode_valid_o && issue_csr_w)
csr_pending_q <= 1'b1;
else if (pipe_csr_wb_w)
csr_pending_q <= 1'b0;
assign squash_w = pipe_squash_e1_e2_w;
//-------------------------------------------------------------
// Issue / scheduling logic
//-------------------------------------------------------------
reg [31:0] scoreboard_r;
always @ *
begin
opcode_issue_r = 1'b0;
opcode_accept_r = 1'b0;
scoreboard_r = 32'b0;
// Execution units with >= 2 cycle latency
if (SUPPORT_LOAD_BYPASS == 0)
begin
if (pipe_load_e2_w)
scoreboard_r[pipe_rd_e2_w] = 1'b1;
end
if (SUPPORT_MUL_BYPASS == 0)
begin
if (pipe_mul_e2_w)
scoreboard_r[pipe_rd_e2_w] = 1'b1;
end
// Execution units with >= 1 cycle latency (loads / multiply)
if (pipe_load_e1_w || pipe_mul_e1_w)
scoreboard_r[pipe_rd_e1_w] = 1'b1;
// Do not start multiply, division or CSR operation in the cycle after a load (leaving only ALU operations and branches)
if ((pipe_load_e1_w || pipe_store_e1_w) && (issue_mul_w || issue_div_w || issue_csr_w))
scoreboard_r = 32'hFFFFFFFF;
// Stall - no issues...
if (lsu_stall_i || stall_w || div_pending_q || csr_pending_q)
;
// Primary slot (lsu, branch, alu, mul, div, csr)
else if (opcode_valid_w &&
!(scoreboard_r[issue_ra_idx_w] ||
scoreboard_r[issue_rb_idx_w] ||
scoreboard_r[issue_rd_idx_w]))
begin
opcode_issue_r = 1'b1;
opcode_accept_r = 1'b1;
if (opcode_accept_r && issue_sb_alloc_w && (|issue_rd_idx_w))
scoreboard_r[issue_rd_idx_w] = 1'b1;
end
end
assign lsu_opcode_valid_o = opcode_issue_r & ~take_interrupt_i;
assign exec_opcode_valid_o = opcode_issue_r;
assign mul_opcode_valid_o = enable_muldiv_w & opcode_issue_r;
assign div_opcode_valid_o = enable_muldiv_w & opcode_issue_r;
assign interrupt_inhibit_o = csr_pending_q || issue_csr_w;
assign fetch_accept_o = opcode_valid_w ? (opcode_accept_r & ~take_interrupt_i) : 1'b1;
assign stall_w = pipe_stall_raw_w;
//-------------------------------------------------------------
// Register File
//-------------------------------------------------------------
wire [31:0] issue_ra_value_w;
wire [31:0] issue_rb_value_w;
wire [31:0] issue_b_ra_value_w;
wire [31:0] issue_b_rb_value_w;
// Register file: 1W2R
riscv_regfile
#(
.SUPPORT_REGFILE_XILINX(SUPPORT_REGFILE_XILINX)
)
u_regfile
(
.clk_i(clk_i),
.rst_i(rst_i),
// Write ports
.rd0_i(pipe_rd_wb_w),
.rd0_value_i(pipe_result_wb_w),
// Read ports
.ra0_i(issue_ra_idx_w),
.rb0_i(issue_rb_idx_w),
.ra0_value_o(issue_ra_value_w),
.rb0_value_o(issue_rb_value_w)
);
//-------------------------------------------------------------
// Issue Slot 0
//-------------------------------------------------------------
assign opcode_opcode_o = fetch_instr_i;
assign opcode_pc_o = fetch_pc_i;
assign opcode_rd_idx_o = issue_rd_idx_w;
assign opcode_ra_idx_o = issue_ra_idx_w;
assign opcode_rb_idx_o = issue_rb_idx_w;
assign opcode_invalid_o= 1'b0;
reg [31:0] issue_ra_value_r;
reg [31:0] issue_rb_value_r;
always @ *
begin
// NOTE: Newest version of operand takes priority
issue_ra_value_r = issue_ra_value_w;
issue_rb_value_r = issue_rb_value_w;
// Bypass - WB
if (pipe_rd_wb_w == issue_ra_idx_w)
issue_ra_value_r = pipe_result_wb_w;
if (pipe_rd_wb_w == issue_rb_idx_w)
issue_rb_value_r = pipe_result_wb_w;
// Bypass - E2
if (pipe_rd_e2_w == issue_ra_idx_w)
issue_ra_value_r = pipe_result_e2_w;
if (pipe_rd_e2_w == issue_rb_idx_w)
issue_rb_value_r = pipe_result_e2_w;
// Bypass - E1
if (pipe_rd_e1_w == issue_ra_idx_w)
issue_ra_value_r = writeback_exec_value_i;
if (pipe_rd_e1_w == issue_rb_idx_w)
issue_rb_value_r = writeback_exec_value_i;
// Reg 0 source
if (issue_ra_idx_w == 5'b0)
issue_ra_value_r = 32'b0;
if (issue_rb_idx_w == 5'b0)
issue_rb_value_r = 32'b0;
end
assign opcode_ra_operand_o = issue_ra_value_r;
assign opcode_rb_operand_o = issue_rb_value_r;
//-------------------------------------------------------------
// Load store unit
//-------------------------------------------------------------
assign lsu_opcode_opcode_o = opcode_opcode_o;
assign lsu_opcode_pc_o = opcode_pc_o;
assign lsu_opcode_rd_idx_o = opcode_rd_idx_o;
assign lsu_opcode_ra_idx_o = opcode_ra_idx_o;
assign lsu_opcode_rb_idx_o = opcode_rb_idx_o;
assign lsu_opcode_ra_operand_o = opcode_ra_operand_o;
assign lsu_opcode_rb_operand_o = opcode_rb_operand_o;
assign lsu_opcode_invalid_o = 1'b0;
//-------------------------------------------------------------
// Multiply
//-------------------------------------------------------------
assign mul_opcode_opcode_o = opcode_opcode_o;
assign mul_opcode_pc_o = opcode_pc_o;
assign mul_opcode_rd_idx_o = opcode_rd_idx_o;
assign mul_opcode_ra_idx_o = opcode_ra_idx_o;
assign mul_opcode_rb_idx_o = opcode_rb_idx_o;
assign mul_opcode_ra_operand_o = opcode_ra_operand_o;
assign mul_opcode_rb_operand_o = opcode_rb_operand_o;
assign mul_opcode_invalid_o = 1'b0;
//-------------------------------------------------------------
// CSR unit
//-------------------------------------------------------------
assign csr_opcode_valid_o = opcode_issue_r & ~take_interrupt_i;
assign csr_opcode_opcode_o = opcode_opcode_o;
assign csr_opcode_pc_o = opcode_pc_o;
assign csr_opcode_rd_idx_o = opcode_rd_idx_o;
assign csr_opcode_ra_idx_o = opcode_ra_idx_o;
assign csr_opcode_rb_idx_o = opcode_rb_idx_o;
assign csr_opcode_ra_operand_o = opcode_ra_operand_o;
assign csr_opcode_rb_operand_o = opcode_rb_operand_o;
assign csr_opcode_invalid_o = opcode_issue_r && issue_invalid_w;
//-------------------------------------------------------------
// Checker Interface
//-------------------------------------------------------------
`ifdef verilator
riscv_trace_sim
u_pipe_dec0_verif
(
.valid_i(pipe_valid_wb_w)
,.pc_i(pipe_pc_wb_w)
,.opcode_i(pipe_opc_wb_w)
);
wire [4:0] v_pipe_rs1_w = pipe_opc_wb_w[19:15];
wire [4:0] v_pipe_rs2_w = pipe_opc_wb_w[24:20];
function [0:0] complete_valid0; /*verilator public*/
begin
complete_valid0 = pipe_valid_wb_w;
end
endfunction
function [31:0] complete_pc0; /*verilator public*/
begin
complete_pc0 = pipe_pc_wb_w;
end
endfunction
function [31:0] complete_opcode0; /*verilator public*/
begin
complete_opcode0 = pipe_opc_wb_w;
end
endfunction
function [4:0] complete_ra0; /*verilator public*/
begin
complete_ra0 = v_pipe_rs1_w;
end
endfunction
function [4:0] complete_rb0; /*verilator public*/
begin
complete_rb0 = v_pipe_rs2_w;
end
endfunction
function [4:0] complete_rd0; /*verilator public*/
begin
complete_rd0 = pipe_rd_wb_w;
end
endfunction
function [31:0] complete_ra_val0; /*verilator public*/
begin
complete_ra_val0 = pipe_ra_val_wb_w;
end
endfunction
function [31:0] complete_rb_val0; /*verilator public*/
begin
complete_rb_val0 = pipe_rb_val_wb_w;
end
endfunction
function [31:0] complete_rd_val0; /*verilator public*/
begin
if (|pipe_rd_wb_w)
complete_rd_val0 = pipe_result_wb_w;
else
complete_rd_val0 = 32'b0;
end
endfunction
function [5:0] complete_exception; /*verilator public*/
begin
complete_exception = pipe_exception_wb_w;
end
endfunction
`endif
endmodule
|
//-------------------------------------------------------------------------------------------------
// I2S CODEC slave module: The I2S bus is over-sampled using the FPGA clock to allow the logic run
// in the FPGA clock domain. Note FPGA clock must be at least 2x the I2S. Clock to synchronize
// the signals using the FPGA clock and shift registers.
//
// I2S Interface structure: 16 bit interface, Bits are sent in most to least significant order
// command, then address and finally data bits as follows:
//
//
// +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+
// TK| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// + +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +--+ +
//
// + +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +
// TF| | | |
// +--+ +--+
//
// |<------------------ Left Channel ------------->|<--------------- Right Channel --------------->|
// 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
// TD| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
// +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
//
//-------------------------------------------------------------------------------------------------
module I2S_slave16 (
input clk, // Main Clock
input FRM, // I2S Framing Input
input BCK, // I2S Sample bit clock input
input DIN, // I2S Serial audio data input
output [15:0] out_L, // Left output
output [15:0] out_R, // Right output
output ready_L, // Signal that data is ready to be sent out
output ready_R // Signal that data is ready to be sent out
);
//-----------------------------------------------------------------------------
// Assign output
//-----------------------------------------------------------------------------
assign out_L = data_L[15:0]; // Left Channel Data bits
assign out_R = data_R[15:0]; // Right Channel Data bits
assign ready_L = FRM_Rise; // Data is ready pulse
assign ready_R = FRM_Fall; // Data is ready pulse
//-----------------------------------------------------------------------------
// Sync BCK to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] FRM_1;
always @(posedge BCK) FRM_1 <= {FRM_1[1:0], FRM};
wire FRM_delayed = FRM_1[1];
//-----------------------------------------------------------------------------
// Sync FRM to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] FRMr;
always @(posedge clk) FRMr <= {FRMr[1:0], FRM_delayed};
wire FRM_Rise = (FRMr[2:1] == 2'b01); // Message starts at rising edge
wire FRM_Fall = (FRMr[2:1] == 2'b10); // Message stops at falling edge
//-----------------------------------------------------------------------------
// I2S receiver:
// This is a 32 bit I2S format, 16 bits data for each channel.
// FPGA is only one slave on the bus so we don't bother with a tri-state buffer
// for MISO otherwise we would need to tri-state MISO when SSEL is inactive
//-----------------------------------------------------------------------------
reg [16:0] data_R; // Shift register of output data
reg [16:0] data_L; // Shift register of output data
always @(posedge BCK) begin
if(FRM_delayed) begin // If Frame not active
data_R <= {data_R[15:0], DIN}; // Input shift-left register
end
else begin
data_L <= {data_L[15:0], DIN}; // Input shift-left register
end
end
//-----------------------------------------------------------------------------
endmodule
//-----------------------------------------------------------------------------
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:05:34 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_47 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire enable_Pipeline_input, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5,
OP_FLAG_INIT, SIGN_FLAG_INIT, ZERO_FLAG_INIT, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, ADD_OVRFLW_NRM, n_7_net_, left_right_SHT2,
bit_shift_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2,
ADD_OVRFLW_NRM2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, n_21_net_, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
N59, N60, ADD_OVRFLW_SGF, inst_ShiftRegister_net3656620,
SFT2FRMT_STAGE_VARS_net3656530, FRMT_STAGE_DATAOUT_net3656458,
SGF_STAGE_DMP_net3656512, NRM_STAGE_Raw_mant_net3656494,
INPUT_STAGE_OPERANDY_net3656458, EXP_STAGE_DMP_net3656512,
SHT1_STAGE_DMP_net3656512, SHT2_STAGE_DMP_net3656512,
SHT2_SHIFT_DATA_net3656494, array_comparators_GTComparator_N0,
array_comparators_LTComparator_N0, n388, n389, n390,
DP_OP_15J180_122_6956_n18, DP_OP_15J180_122_6956_n17,
DP_OP_15J180_122_6956_n16, DP_OP_15J180_122_6956_n15,
DP_OP_15J180_122_6956_n14, DP_OP_15J180_122_6956_n8,
DP_OP_15J180_122_6956_n7, DP_OP_15J180_122_6956_n6,
DP_OP_15J180_122_6956_n5, DP_OP_15J180_122_6956_n4,
DP_OP_15J180_122_6956_n3, DP_OP_15J180_122_6956_n2,
DP_OP_15J180_122_6956_n1, intadd_428_CI, intadd_428_SUM_2_,
intadd_428_SUM_1_, intadd_428_SUM_0_, intadd_428_n3, intadd_428_n2,
intadd_428_n1, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412,
n413, n414, n415, n416, n417, n418, n419, n420, n422, n423, n424,
n425, n426, n427, n428, n429, n430, n431, n432, n433, n434, n435,
n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457,
n458, n459, n460, n461, n462, n463, n464, n465, n466, n467, n468,
n469, n470, n471, n472, n473, n474, n475, n476, n477, n478, n479,
n480, n481, n482, n483, n484, n485, n486, n487, n488, n489, n490,
n491, n492, n493, n494, n495, n496, n497, n498, n499, n500, n501,
n502, n503, n504, n505, n506, n507, n508, n509, n510, n511, n512,
n513, n514, n515, n516, n517, n518, n519, n520, n521, n522, n523,
n524, n525, n526, n527, n528, n529, n530, n531, n532, n533, n534,
n535, n536, n537, n538, n539, n540, n541, n542, n543, n544, n545,
n546, n547, n548, n549, n550, n551, n552, n553, n554, n555, n556,
n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578,
n579, n580, n581, n582, n583, n584, n585, n586, n587, n588, n589,
n590, n591, n592, n593, n594, n595, n596, n597, n598, n599, n600,
n601, n602, n603, n604, n605, n606, n607, n608, n609, n610, n611,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094;
wire [3:1] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [30:0] intDY_EWSW;
wire [30:0] DMP_INIT_EWSW;
wire [27:0] DmP_INIT_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [4:0] Shift_amount_EXP_EW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [4:0] LZD_raw_out_EWR;
wire [4:2] shft_value_mux_o_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [51:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [25:0] sftr_odat_SHT2_SWR;
wire [4:0] LZD_output_NRM2_EW;
wire [7:0] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [24:2] DmP_mant_SFG_SWR;
wire [25:1] Raw_mant_SGF;
wire [31:0] formatted_number_W;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7_48 inst_ShiftRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n390), .ENCLK(inst_ShiftRegister_net3656620), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13_47 SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[1]), .ENCLK(
SFT2FRMT_STAGE_VARS_net3656530), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_6 FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(clk), .EN(n412), .ENCLK(FRMT_STAGE_DATAOUT_net3656458), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_5 SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(n_21_net_), .ENCLK(SGF_STAGE_DMP_net3656512), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_1 NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7[2]), .ENCLK(
NRM_STAGE_Raw_mant_net3656494), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_7 INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(clk), .EN(enable_Pipeline_input), .ENCLK(
INPUT_STAGE_OPERANDY_net3656458), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_9 EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_6), .ENCLK(EXP_STAGE_DMP_net3656512),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_8 SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(Shift_reg_FLAGS_7_5), .ENCLK(SHT1_STAGE_DMP_net3656512),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_7 SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(clk), .EN(busy), .ENCLK(SHT2_STAGE_DMP_net3656512), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_4 SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(clk), .EN(n_7_net_), .ENCLK(SHT2_SHIFT_DATA_net3656494), .TE(1'b0) );
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1094), .CK(
inst_ShiftRegister_net3656620), .RN(n1058), .Q(Shift_reg_FLAGS_7_6) );
DFFRXLTS inst_ShiftRegister_Q_reg_5_ ( .D(Shift_reg_FLAGS_7_6), .CK(
inst_ShiftRegister_net3656620), .RN(n1059), .Q(Shift_reg_FLAGS_7_5) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(
inst_ShiftRegister_net3656620), .RN(n1059), .Q(Shift_reg_FLAGS_7[3])
);
DFFRXLTS inst_ShiftRegister_Q_reg_2_ ( .D(Shift_reg_FLAGS_7[3]), .CK(
inst_ShiftRegister_net3656620), .RN(n1060), .Q(Shift_reg_FLAGS_7[2])
);
DFFRXLTS inst_ShiftRegister_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[1]), .CK(
inst_ShiftRegister_net3656620), .RN(n1060), .QN(n402) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(Shift_amount_EXP_EW[0]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1061), .Q(Shift_amount_SHT1_EWR[0])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(Shift_amount_EXP_EW[1]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1060), .Q(Shift_amount_SHT1_EWR[1])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(Shift_amount_EXP_EW[2]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1061), .Q(Shift_amount_SHT1_EWR[2])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(Shift_amount_EXP_EW[3]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1063), .Q(Shift_amount_SHT1_EWR[3])
);
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(Shift_amount_EXP_EW[4]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1062), .Q(Shift_amount_SHT1_EWR[4])
);
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(Data_X[28]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[28]), .QN(
n427) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(DmP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1060), .Q(DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(DmP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_mant_SHT1_SW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(DmP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1061), .Q(DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(DmP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1064), .Q(DmP_mant_SHT1_SW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(DmP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1059), .Q(DmP_EXP_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(DmP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1058), .Q(DmP_mant_SHT1_SW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(DmP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_EXP_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(DmP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1059), .Q(DmP_mant_SHT1_SW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(DmP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1058), .Q(DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(DmP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_mant_SHT1_SW[4]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(DmP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1058), .Q(DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(DmP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1061), .Q(DmP_mant_SHT1_SW[5]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(DmP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1060), .Q(DmP_EXP_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(DmP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1062), .Q(DmP_mant_SHT1_SW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(DmP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1064), .Q(DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(DmP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1061), .Q(DmP_mant_SHT1_SW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(DmP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1062), .Q(DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(DmP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1064), .Q(DmP_mant_SHT1_SW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(DmP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1064), .Q(DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(DmP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_mant_SHT1_SW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(DmP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1059), .Q(DmP_EXP_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(DmP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_mant_SHT1_SW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(DmP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1061), .Q(DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(DmP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1078), .Q(DmP_mant_SHT1_SW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(DmP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1063), .Q(DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(DmP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1065), .Q(DmP_mant_SHT1_SW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(DmP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1077), .Q(DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(DmP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1070), .Q(DmP_mant_SHT1_SW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(DmP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1079), .Q(DmP_EXP_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(DmP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1075), .Q(DmP_mant_SHT1_SW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(DmP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1078), .Q(DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(DmP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1070), .Q(DmP_mant_SHT1_SW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(DmP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n462), .Q(DmP_EXP_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(DmP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1071), .Q(DmP_mant_SHT1_SW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(DmP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n460), .Q(DmP_EXP_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(DmP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n464), .Q(DmP_mant_SHT1_SW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(DmP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n463), .Q(DmP_EXP_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(DmP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1073), .Q(DmP_mant_SHT1_SW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(DmP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(DmP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1088), .Q(DmP_mant_SHT1_SW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(DmP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1067), .Q(DmP_EXP_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(DmP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1087), .Q(DmP_mant_SHT1_SW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(DmP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1085), .Q(DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(DmP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n425), .Q(DmP_mant_SHT1_SW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(DmP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1086), .Q(DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(DmP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1088), .Q(DmP_mant_SHT1_SW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(DmP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1067), .Q(DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(DmP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1080), .Q(DmP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(DmP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1082), .Q(DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(DmP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1077), .Q(DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(DmP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1068), .Q(DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(DMP_INIT_EWSW[0]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(DMP_INIT_EWSW[1]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(DMP_INIT_EWSW[2]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(DMP_INIT_EWSW[3]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(DMP_INIT_EWSW[4]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(DMP_INIT_EWSW[5]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n460), .Q(DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(DMP_INIT_EWSW[6]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n464), .Q(DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(DMP_INIT_EWSW[7]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n463), .Q(DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(DMP_INIT_EWSW[8]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n462), .Q(DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(DMP_INIT_EWSW[9]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1071), .Q(DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(DMP_INIT_EWSW[10]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1073), .Q(DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(DMP_INIT_EWSW[11]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(DMP_INIT_EWSW[12]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n460), .Q(DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(DMP_INIT_EWSW[13]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n464), .Q(DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(DMP_INIT_EWSW[14]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n463), .Q(DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(DMP_INIT_EWSW[15]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1073), .Q(DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(DMP_INIT_EWSW[16]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(DMP_INIT_EWSW[17]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(DMP_INIT_EWSW[18]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(DMP_INIT_EWSW[19]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(DMP_INIT_EWSW[20]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n462), .Q(DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(DMP_INIT_EWSW[21]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1071), .Q(DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(DMP_INIT_EWSW[22]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1073), .Q(DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(DMP_INIT_EWSW[23]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_EXP_EWSW[23]), .QN(n430)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(DMP_INIT_EWSW[27]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(DMP_INIT_EWSW[28]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(DMP_INIT_EWSW[29]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n464), .Q(DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(DMP_INIT_EWSW[30]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n463), .Q(DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3656512), .RN(n460), .Q(ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1073), .Q(OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_INIT), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1066), .Q(SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(DMP_EXP_EWSW[0]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(DMP_EXP_EWSW[1]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(DMP_EXP_EWSW[2]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(DMP_EXP_EWSW[3]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(DMP_EXP_EWSW[4]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(DMP_EXP_EWSW[5]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n460), .Q(DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(DMP_EXP_EWSW[6]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n464), .Q(DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(DMP_EXP_EWSW[7]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n463), .Q(DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(DMP_EXP_EWSW[8]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n462), .Q(DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(DMP_EXP_EWSW[9]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1071), .Q(DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(DMP_EXP_EWSW[10]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1073), .Q(DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(DMP_EXP_EWSW[11]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(DMP_EXP_EWSW[12]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(DMP_EXP_EWSW[13]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(DMP_EXP_EWSW[14]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(DMP_EXP_EWSW[15]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(DMP_EXP_EWSW[16]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(DMP_EXP_EWSW[17]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n462), .Q(DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(DMP_EXP_EWSW[18]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1071), .Q(DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(DMP_EXP_EWSW[19]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1073), .Q(DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(DMP_EXP_EWSW[20]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1066), .Q(DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(DMP_EXP_EWSW[21]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1072), .Q(DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(DMP_EXP_EWSW[22]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1069), .Q(DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(DMP_EXP_EWSW[23]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(DMP_EXP_EWSW[24]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n464), .Q(DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(DMP_EXP_EWSW[25]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n463), .Q(DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(DMP_EXP_EWSW[26]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(DMP_EXP_EWSW[27]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(DMP_EXP_EWSW[28]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(DMP_EXP_EWSW[29]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(DMP_EXP_EWSW[30]), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(ZERO_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(OP_FLAG_SHT1) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_EXP), .CK(
SHT1_STAGE_DMP_net3656512), .RN(n1074), .Q(SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT1_EWSW[0]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT1_EWSW[1]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT1_EWSW[2]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT1_EWSW[3]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1076), .Q(DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT1_EWSW[4]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT1_EWSW[5]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT1_EWSW[6]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT1_EWSW[7]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT1_EWSW[8]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n411), .Q(DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT1_EWSW[9]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT1_EWSW[10]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1075), .Q(DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT1_EWSW[11]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT1_EWSW[12]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT1_EWSW[13]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT1_EWSW[14]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1062), .Q(DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT1_EWSW[15]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT1_EWSW[16]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1075), .Q(DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT1_EWSW[17]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1060), .Q(DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT1_EWSW[18]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT1_EWSW[19]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n425), .Q(DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT1_EWSW[20]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1089), .Q(DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT1_EWSW[21]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT1_EWSW[22]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT1_EWSW[23]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(DMP_SHT2_EWSW[23]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(DMP_SFG[23]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1087), .Q(DMP_exp_NRM_EW[0]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(DMP_exp_NRM_EW[0]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1088), .Q(DMP_exp_NRM2_EW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT1_EWSW[24]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1058), .Q(DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(DMP_SHT2_EWSW[24]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(DMP_SFG[24]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1071), .Q(DMP_exp_NRM_EW[1]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(DMP_exp_NRM_EW[1]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1086), .Q(DMP_exp_NRM2_EW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT1_EWSW[25]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1081), .Q(DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(DMP_SHT2_EWSW[25]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(DMP_SFG[25]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1067), .Q(DMP_exp_NRM_EW[2]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(DMP_exp_NRM_EW[2]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1088), .Q(DMP_exp_NRM2_EW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT1_EWSW[26]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n411), .Q(DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(DMP_SHT2_EWSW[26]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(DMP_SFG[26]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1086), .Q(DMP_exp_NRM_EW[3]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(DMP_exp_NRM_EW[3]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1087), .Q(DMP_exp_NRM2_EW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT1_EWSW[27]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n425), .Q(DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(DMP_SHT2_EWSW[27]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(DMP_SFG[27]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1067), .Q(DMP_exp_NRM_EW[4]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(DMP_exp_NRM_EW[4]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1076), .Q(DMP_exp_NRM2_EW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT1_EWSW[28]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1076), .Q(DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(DMP_SHT2_EWSW[28]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(DMP_SFG[28]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1087), .Q(DMP_exp_NRM_EW[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(DMP_exp_NRM_EW[5]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1088), .Q(DMP_exp_NRM2_EW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT1_EWSW[29]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(DMP_SHT2_EWSW[29]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1084), .Q(DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(DMP_SFG[29]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1085), .Q(DMP_exp_NRM_EW[6]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(DMP_exp_NRM_EW[6]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1089), .Q(DMP_exp_NRM2_EW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT1_EWSW[30]), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(DMP_SHT2_EWSW[30]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1075), .Q(DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(DMP_SFG[30]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1068), .Q(DMP_exp_NRM_EW[7]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(DMP_exp_NRM_EW[7]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1086), .Q(DMP_exp_NRM2_EW[7]) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1059), .Q(ZERO_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1079), .Q(OP_FLAG_SHT2) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT1), .CK(
SHT2_STAGE_DMP_net3656512), .RN(n1078), .Q(SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1061), .Q(ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(Raw_mant_SGF[2]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1065), .QN(n396) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(Raw_mant_SGF[4]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1075), .QN(n395) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(LZD_raw_out_EWR[3]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1078), .Q(LZD_output_NRM2_EW[3])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(LZD_raw_out_EWR[0]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1067), .Q(LZD_output_NRM2_EW[0])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(LZD_raw_out_EWR[2]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1086), .Q(LZD_output_NRM2_EW[2])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(LZD_raw_out_EWR[1]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1087), .Q(LZD_output_NRM2_EW[1])
);
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(LZD_raw_out_EWR[4]), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1088), .Q(LZD_output_NRM2_EW[4])
);
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(SIGN_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1068), .Q(SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1081), .Q(ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1084), .Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_SFG), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1081), .Q(SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(SIGN_FLAG_NRM), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .RN(n1080), .Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(Data_array_SWR[3]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1080), .Q(Data_array_SWR[29]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(Data_array_SWR[2]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1089), .Q(Data_array_SWR[28]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(Data_array_SWR[1]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1084), .Q(Data_array_SWR[27]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(Data_array_SWR[0]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1089), .Q(Data_array_SWR[26]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(sftr_odat_SHT2_SWR[1]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1082), .Q(N60) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(sftr_odat_SHT2_SWR[25]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1088), .QN(n429) );
CMPR32X2TS DP_OP_15J180_122_6956_U9 ( .A(DMP_exp_NRM2_EW[0]), .B(n946), .C(
DP_OP_15J180_122_6956_n18), .CO(DP_OP_15J180_122_6956_n8), .S(
exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_15J180_122_6956_U8 ( .A(DP_OP_15J180_122_6956_n17), .B(
DMP_exp_NRM2_EW[1]), .C(DP_OP_15J180_122_6956_n8), .CO(
DP_OP_15J180_122_6956_n7), .S(exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_15J180_122_6956_U7 ( .A(DP_OP_15J180_122_6956_n16), .B(
DMP_exp_NRM2_EW[2]), .C(DP_OP_15J180_122_6956_n7), .CO(
DP_OP_15J180_122_6956_n6), .S(exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_15J180_122_6956_U6 ( .A(DP_OP_15J180_122_6956_n15), .B(
DMP_exp_NRM2_EW[3]), .C(DP_OP_15J180_122_6956_n6), .CO(
DP_OP_15J180_122_6956_n5), .S(exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS intadd_428_U4 ( .A(DmP_EXP_EWSW[24]), .B(n1041), .C(intadd_428_CI), .CO(intadd_428_n3), .S(intadd_428_SUM_0_) );
CMPR32X2TS intadd_428_U3 ( .A(DmP_EXP_EWSW[25]), .B(n1040), .C(intadd_428_n3), .CO(intadd_428_n2), .S(intadd_428_SUM_1_) );
CMPR32X2TS intadd_428_U2 ( .A(DmP_EXP_EWSW[26]), .B(n1053), .C(intadd_428_n2), .CO(intadd_428_n1), .S(intadd_428_SUM_2_) );
DFFSX2TS R_0 ( .D(n1054), .CK(INPUT_STAGE_OPERANDY_net3656458), .SN(n1064),
.Q(n1092) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(N59), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1075), .Q(Raw_mant_NRM_SWR[0]),
.QN(n1052) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(Data_Y[0]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDY_EWSW[0]), .QN(
n1051) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(Data_Y[26]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1080), .Q(intDY_EWSW[26]), .QN(
n1050) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(Data_Y[15]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1078), .Q(intDY_EWSW[15]), .QN(
n1049) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(Data_Y[3]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDY_EWSW[3]), .QN(
n1048) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(Data_Y[1]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDY_EWSW[1]), .QN(
n1047) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(Data_Y[11]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDY_EWSW[11]), .QN(
n1046) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(Data_Y[25]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n425), .Q(intDY_EWSW[25]), .QN(
n1045) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(Data_Y[18]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1071), .Q(intDY_EWSW[18]), .QN(
n1044) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(Data_Y[17]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n462), .Q(intDY_EWSW[17]), .QN(
n1043) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(Data_Y[8]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1058), .Q(intDY_EWSW[8]), .QN(
n1042) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(Data_Y[12]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1076), .Q(intDY_EWSW[12]), .QN(
n1039) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(Data_Y[27]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1084), .Q(intDY_EWSW[27]), .QN(
n1038) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(Data_Y[9]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDY_EWSW[9]), .QN(
n1037) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(Data_Y[22]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1078), .Q(intDY_EWSW[22]), .QN(
n1036) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(Data_Y[20]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1088), .Q(intDY_EWSW[20]), .QN(
n1035) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(Data_Y[2]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDY_EWSW[2]), .QN(
n1034) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(Data_Y[21]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1067), .Q(intDY_EWSW[21]), .QN(
n1033) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(Data_Y[13]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1065), .Q(intDY_EWSW[13]), .QN(
n1032) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(Data_Y[24]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1078), .Q(intDY_EWSW[24]), .QN(
n1031) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(Data_Y[10]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDY_EWSW[10]), .QN(
n1030) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(Data_Y[4]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1058), .Q(intDY_EWSW[4]), .QN(
n1029) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(Data_Y[16]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n460), .Q(intDY_EWSW[16]), .QN(
n1028) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(Data_Y[6]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1064), .Q(intDY_EWSW[6]), .QN(
n1027) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(Data_Y[5]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDY_EWSW[5]), .QN(
n1026) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(Data_Y[7]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDY_EWSW[7]), .QN(
n1025) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n389), .CK(clk), .RN(
n1063), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1024) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(DMP_SHT2_EWSW[22]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1076), .Q(DMP_SFG[22]), .QN(n1023) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(Raw_mant_SGF[5]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1065), .Q(Raw_mant_NRM_SWR[5]),
.QN(n1021) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(Data_array_SWR[25]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1082), .Q(Data_array_SWR[51]), .QN(
n1019) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(Data_X[16]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[16]), .QN(
n1018) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(Data_array_SWR[23]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1068), .Q(Data_array_SWR[49]), .QN(
n1017) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(Data_X[30]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[30]), .QN(
n1015) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(Data_X[29]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[29]), .QN(
n1014) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(DMP_SHT2_EWSW[20]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SFG[20]), .QN(n1012) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(Data_X[23]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDX_EWSW[23]), .QN(
n1011) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(Data_X[26]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDX_EWSW[26]), .QN(
n1010) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(Data_X[19]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[19]), .QN(
n1009) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(Data_X[14]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[14]), .QN(
n1008) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(Data_X[12]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1058), .Q(intDX_EWSW[12]), .QN(
n1007) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(Data_X[11]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1062), .Q(intDX_EWSW[11]), .QN(
n1006) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(Data_X[6]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[6]), .QN(
n1005) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(Data_X[25]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1062), .Q(intDX_EWSW[25]), .QN(
n1004) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(Data_X[17]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1064), .Q(intDX_EWSW[17]), .QN(
n1003) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(Data_X[10]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[10]), .QN(
n1002) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(Data_X[8]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDX_EWSW[8]), .QN(
n1001) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(Data_X[1]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[1]), .QN(
n1000) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(DMP_SHT2_EWSW[18]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1078), .Q(DMP_SFG[18]), .QN(n998) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(DMP_SHT2_EWSW[17]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SFG[17]), .QN(n997) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(Data_X[13]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[13]), .QN(
n996) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(Data_Y[30]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1068), .Q(intDY_EWSW[30]), .QN(
n995) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(DMP_SHT2_EWSW[16]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n461), .Q(DMP_SFG[16]), .QN(n993) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(Raw_mant_SGF[12]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1075), .Q(Raw_mant_NRM_SWR[12]),
.QN(n992) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(DMP_SHT2_EWSW[14]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SFG[14]), .QN(n991) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(DMP_SHT2_EWSW[15]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SFG[15]), .QN(n990) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(Raw_mant_SGF[20]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1084), .Q(Raw_mant_NRM_SWR[20]),
.QN(n989) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(Raw_mant_SGF[25]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1082), .Q(Raw_mant_NRM_SWR[25]),
.QN(n988) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(Raw_mant_SGF[18]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1075), .Q(Raw_mant_NRM_SWR[18]),
.QN(n987) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(Raw_mant_SGF[14]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1068), .Q(Raw_mant_NRM_SWR[14]),
.QN(n986) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(DMP_SHT2_EWSW[12]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SFG[12]), .QN(n984) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(Raw_mant_SGF[17]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1080), .Q(Raw_mant_NRM_SWR[17]),
.QN(n983) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(Raw_mant_SGF[1]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1065), .Q(Raw_mant_NRM_SWR[1]),
.QN(n982) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(Raw_mant_SGF[3]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1077), .Q(Raw_mant_NRM_SWR[3]),
.QN(n980) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_10_ ( .D(DMP_SHT2_EWSW[10]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n425), .Q(DMP_SFG[10]), .QN(n979) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(Raw_mant_SGF[6]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1076), .Q(Raw_mant_NRM_SWR[6]),
.QN(n978) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(DMP_SHT2_EWSW[8]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1062), .Q(DMP_SFG[8]), .QN(n976) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(DMP_SHT2_EWSW[6]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SFG[6]), .QN(n974) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(DMP_SHT2_EWSW[5]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SFG[5]), .QN(n973) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(DMP_SHT2_EWSW[4]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1065), .Q(DMP_SFG[4]), .QN(n972) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(DMP_SHT2_EWSW[2]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1081), .Q(DMP_SFG[2]), .QN(n970) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(DMP_SHT2_EWSW[0]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SFG[0]), .QN(n969) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(Data_Y[14]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1077), .Q(intDY_EWSW[14]), .QN(
n967) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(Data_Y[19]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1073), .Q(intDY_EWSW[19]), .QN(
n966) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n388), .CK(clk), .RN(
n1064), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n965) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(Data_array_SWR[24]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n425), .Q(Data_array_SWR[50]), .QN(
n964) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(Data_Y[23]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1075), .Q(intDY_EWSW[23]), .QN(
n963) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(DMP_SHT2_EWSW[21]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1075), .Q(DMP_SFG[21]), .QN(n962) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(DMP_SHT2_EWSW[19]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1081), .Q(DMP_SFG[19]), .QN(n960) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(Data_X[24]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1059), .Q(intDX_EWSW[24]), .QN(
n959) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(Data_X[27]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDX_EWSW[27]), .QN(
n958) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(Data_X[22]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDX_EWSW[22]), .QN(
n957) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(Data_X[20]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1062), .Q(intDX_EWSW[20]), .QN(
n956) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(Data_X[18]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1064), .Q(intDX_EWSW[18]), .QN(
n955) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(Data_X[9]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[9]), .QN(
n954) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(Data_X[21]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1060), .Q(intDX_EWSW[21]), .QN(
n953) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(Data_X[15]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1058), .Q(intDX_EWSW[15]), .QN(
n952) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(Data_X[3]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1062), .Q(intDX_EWSW[3]), .QN(
n951) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(Data_Y[29]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n425), .Q(intDY_EWSW[29]), .QN(
n950) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(DMP_SHT2_EWSW[13]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1077), .Q(DMP_SFG[13]), .QN(n948) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(DMP_SHT2_EWSW[11]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1076), .Q(DMP_SFG[11]), .QN(n947) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(DMP_SHT2_EWSW[9]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SFG[9]), .QN(n945) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(DMP_SHT2_EWSW[7]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DMP_SFG[7]), .QN(n944) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(DMP_SHT2_EWSW[3]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1076), .Q(DMP_SFG[3]), .QN(n942) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(DMP_SHT2_EWSW[1]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1074), .Q(DMP_SFG[1]), .QN(n941) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n1094), .CK(clk), .RN(
n1058), .Q(inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n940) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n412), .CK(clk), .RN(n1059), .Q(ready) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(formatted_number_W[23]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1067), .Q(final_result_ieee[23])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(formatted_number_W[24]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1087), .Q(final_result_ieee[24])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(formatted_number_W[25]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1089), .Q(final_result_ieee[25])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(formatted_number_W[26]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1085), .Q(final_result_ieee[26])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(formatted_number_W[27]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1086), .Q(final_result_ieee[27])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(formatted_number_W[28]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1076), .Q(final_result_ieee[28])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(formatted_number_W[29]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1067), .Q(final_result_ieee[29])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(formatted_number_W[30]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1088), .Q(final_result_ieee[30])
);
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(array_comparators_LTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3656458), .RN(n1075), .Q(underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(array_comparators_GTComparator_N0),
.CK(FRMT_STAGE_DATAOUT_net3656458), .RN(n1086), .Q(overflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(ZERO_FLAG_SHT1SHT2), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1082), .Q(zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(formatted_number_W[31]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1084), .Q(final_result_ieee[31])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(formatted_number_W[8]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1082), .Q(final_result_ieee[8])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(formatted_number_W[9]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1065), .Q(final_result_ieee[9])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(formatted_number_W[10]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1068), .Q(final_result_ieee[10])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(formatted_number_W[11]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1074), .Q(final_result_ieee[11])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(formatted_number_W[12]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1075), .Q(final_result_ieee[12])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(formatted_number_W[13]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1084), .Q(final_result_ieee[13])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(formatted_number_W[0]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1075), .Q(final_result_ieee[0])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(formatted_number_W[1]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(formatted_number_W[2]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(formatted_number_W[3]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(formatted_number_W[4]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(formatted_number_W[5]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(formatted_number_W[6]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n411), .Q(final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(formatted_number_W[7]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1067), .Q(final_result_ieee[7])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(formatted_number_W[14]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1087), .Q(final_result_ieee[14])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(formatted_number_W[15]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1081), .Q(final_result_ieee[15])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(formatted_number_W[16]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1085), .Q(final_result_ieee[16])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(formatted_number_W[17]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1086), .Q(final_result_ieee[17])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(formatted_number_W[18]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1082), .Q(final_result_ieee[18])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(formatted_number_W[19]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1087), .Q(final_result_ieee[19])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(formatted_number_W[20]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1085), .Q(final_result_ieee[20])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(formatted_number_W[21]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1075), .Q(final_result_ieee[21])
);
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(formatted_number_W[22]), .CK(
FRMT_STAGE_DATAOUT_net3656458), .RN(n1087), .Q(final_result_ieee[22])
);
DFFRX1TS inst_ShiftRegister_Q_reg_4_ ( .D(Shift_reg_FLAGS_7_5), .CK(
inst_ShiftRegister_net3656620), .RN(n1062), .Q(busy) );
CMPR32X2TS DP_OP_15J180_122_6956_U5 ( .A(DP_OP_15J180_122_6956_n14), .B(
DMP_exp_NRM2_EW[4]), .C(DP_OP_15J180_122_6956_n5), .CO(
DP_OP_15J180_122_6956_n4), .S(exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_15J180_122_6956_U4 ( .A(n946), .B(DMP_exp_NRM2_EW[5]), .C(
DP_OP_15J180_122_6956_n4), .CO(DP_OP_15J180_122_6956_n3), .S(
exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_15J180_122_6956_U3 ( .A(n946), .B(DMP_exp_NRM2_EW[6]), .C(
DP_OP_15J180_122_6956_n3), .CO(DP_OP_15J180_122_6956_n2), .S(
exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_15J180_122_6956_U2 ( .A(n946), .B(DMP_exp_NRM2_EW[7]), .C(
DP_OP_15J180_122_6956_n2), .CO(DP_OP_15J180_122_6956_n1), .S(
exp_rslt_NRM2_EW1[7]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(sftr_odat_SHT2_SWR[2]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1082), .Q(DmP_mant_SFG_SWR[2]) );
DFFSX2TS SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n428), .CK(
SFT2FRMT_STAGE_VARS_net3656530), .SN(n1086), .Q(n946), .QN(
ADD_OVRFLW_NRM2) );
DFFRX2TS inst_ShiftRegister_Q_reg_1_ ( .D(Shift_reg_FLAGS_7[2]), .CK(
inst_ShiftRegister_net3656620), .RN(n1060), .Q(Shift_reg_FLAGS_7[1]),
.QN(n1093) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(Data_X[7]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1064), .QN(n1057) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(Data_X[5]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .QN(n1055) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(Data_X[4]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1062), .Q(intDX_EWSW[4]), .QN(
n1056) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(DMP_INIT_EWSW[26]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1070), .Q(DMP_EXP_EWSW[26]), .QN(n1053) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(Raw_mant_SGF[22]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1076), .Q(Raw_mant_NRM_SWR[22]),
.QN(n949) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(Raw_mant_SGF[11]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[11])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(Raw_mant_SGF[13]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[13])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(Raw_mant_SGF[23]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[23])
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(sftr_odat_SHT2_SWR[24]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1077), .Q(DmP_mant_SFG_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(Raw_mant_SGF[24]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[24])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(Raw_mant_SGF[10]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[10])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(Raw_mant_SGF[16]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[16])
);
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(Raw_mant_SGF[21]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1083), .Q(Raw_mant_NRM_SWR[21])
);
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(Data_Y[28]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1068), .Q(intDY_EWSW[28]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(sftr_odat_SHT2_SWR[20]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1086), .Q(DmP_mant_SFG_SWR[20]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(sftr_odat_SHT2_SWR[18]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1087), .Q(DmP_mant_SFG_SWR[18]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(sftr_odat_SHT2_SWR[16]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1085), .Q(DmP_mant_SFG_SWR[16]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(sftr_odat_SHT2_SWR[8]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[8]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(sftr_odat_SHT2_SWR[6]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[6]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(sftr_odat_SHT2_SWR[4]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[4]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(sftr_odat_SHT2_SWR[14]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n425), .Q(DmP_mant_SFG_SWR[14]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(sftr_odat_SHT2_SWR[12]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1083), .Q(DmP_mant_SFG_SWR[12]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(sftr_odat_SHT2_SWR[10]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1083), .Q(DmP_mant_SFG_SWR[10]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(sftr_odat_SHT2_SWR[22]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1086), .Q(DmP_mant_SFG_SWR[22]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(shft_value_mux_o_EWR[3]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1083), .Q(shift_value_SHT2_EWR[3])
);
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(Raw_mant_SGF[7]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1078), .Q(Raw_mant_NRM_SWR[7]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(Data_array_SWR[16]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1058), .Q(Data_array_SWR[42]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(Data_array_SWR[17]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1080), .Q(Data_array_SWR[43]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(Raw_mant_SGF[19]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1084), .Q(Raw_mant_NRM_SWR[19])
);
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(Data_array_SWR[18]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1081), .Q(Data_array_SWR[44]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(Data_array_SWR[19]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1068), .Q(Data_array_SWR[45]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(Raw_mant_SGF[8]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1089), .Q(Raw_mant_NRM_SWR[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(Data_array_SWR[9]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1070), .Q(Data_array_SWR[35]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(Data_array_SWR[8]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1068), .Q(Data_array_SWR[34]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(Data_array_SWR[10]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1081), .Q(Data_array_SWR[36]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(Data_array_SWR[11]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1082), .Q(Data_array_SWR[37]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(Data_X[2]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDX_EWSW[2]), .QN(
n400) );
DFFRX1TS SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n410), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1081), .Q(bit_shift_SHT2) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(sftr_odat_SHT2_SWR[19]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1064), .Q(DmP_mant_SFG_SWR[19]), .QN(
n398) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(sftr_odat_SHT2_SWR[17]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1087), .Q(DmP_mant_SFG_SWR[17]), .QN(
n397) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(Data_array_SWR[21]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n425), .Q(Data_array_SWR[47]), .QN(
n961) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(Data_array_SWR[22]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1080), .Q(Data_array_SWR[48]), .QN(
n1016) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(Data_array_SWR[20]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1084), .Q(Data_array_SWR[46]), .QN(
n1022) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(Data_array_SWR[15]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n411), .Q(Data_array_SWR[41]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(Data_X[0]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1063), .Q(intDX_EWSW[0]), .QN(
n401) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(Data_X[31]), .CK(
INPUT_STAGE_OPERANDY_net3656458), .RN(n1061), .Q(intDX_EWSW[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(Data_array_SWR[13]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1080), .Q(Data_array_SWR[39]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(Data_array_SWR[12]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1082), .Q(Data_array_SWR[38]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(Data_array_SWR[14]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1081), .Q(Data_array_SWR[40]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(Raw_mant_SGF[9]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1075), .Q(Raw_mant_NRM_SWR[9]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(Raw_mant_SGF[15]), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1080), .Q(Raw_mant_NRM_SWR[15])
);
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(shft_value_mux_o_EWR[4]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1081), .Q(shift_value_SHT2_EWR[4]),
.QN(n994) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(sftr_odat_SHT2_SWR[0]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1084), .Q(N59) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_2_ ( .D(ADD_OVRFLW_SGF), .CK(
NRM_STAGE_Raw_mant_net3656494), .RN(n1088), .Q(ADD_OVRFLW_NRM), .QN(
n428) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(Data_array_SWR[6]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n425), .Q(Data_array_SWR[32]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(Data_array_SWR[7]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1074), .Q(Data_array_SWR[33]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(Data_array_SWR[5]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1068), .Q(Data_array_SWR[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(Data_array_SWR[4]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n425), .Q(Data_array_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(sftr_odat_SHT2_SWR[9]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[9]), .QN(
n975) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(sftr_odat_SHT2_SWR[23]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1088), .Q(DmP_mant_SFG_SWR[23]), .QN(
n1020) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(sftr_odat_SHT2_SWR[21]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1067), .Q(DmP_mant_SFG_SWR[21]), .QN(
n1013) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(sftr_odat_SHT2_SWR[7]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[7]), .QN(
n943) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(sftr_odat_SHT2_SWR[5]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n411), .Q(DmP_mant_SFG_SWR[5]), .QN(
n971) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(sftr_odat_SHT2_SWR[3]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(DmP_mant_SFG_SWR[3]), .QN(
n968) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(sftr_odat_SHT2_SWR[15]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1084), .Q(DmP_mant_SFG_SWR[15]), .QN(
n985) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(sftr_odat_SHT2_SWR[11]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1082), .Q(DmP_mant_SFG_SWR[11]), .QN(
n977) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(sftr_odat_SHT2_SWR[13]), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1080), .Q(DmP_mant_SFG_SWR[13]), .QN(
n981) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(DMP_INIT_EWSW[25]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n462), .Q(DMP_EXP_EWSW[25]), .QN(n1040)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(DMP_INIT_EWSW[24]), .CK(
EXP_STAGE_DMP_net3656512), .RN(n1071), .Q(DMP_EXP_EWSW[24]), .QN(n1041) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(shft_value_mux_o_EWR[2]), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1083), .Q(shift_value_SHT2_EWR[2]),
.QN(n999) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1090), .CK(
SHT2_SHIFT_DATA_net3656494), .RN(n1080), .Q(left_right_SHT2), .QN(n394) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(OP_FLAG_SHT2), .CK(
SGF_STAGE_DMP_net3656512), .RN(n1079), .Q(n393), .QN(n1091) );
NAND2X4TS U582 ( .A(n665), .B(n660), .Y(n653) );
AOI211X2TS U583 ( .A0(Data_array_SWR[42]), .A1(n465), .B0(n499), .C0(n498),
.Y(n552) );
AOI211X2TS U584 ( .A0(Data_array_SWR[43]), .A1(n465), .B0(n499), .C0(n476),
.Y(n524) );
AOI222X4TS U585 ( .A0(DMP_SFG[16]), .A1(DmP_mant_SFG_SWR[18]), .B0(
DMP_SFG[16]), .B1(n648), .C0(DmP_mant_SFG_SWR[18]), .C1(n648), .Y(n773) );
AOI222X4TS U586 ( .A0(DMP_SFG[12]), .A1(DmP_mant_SFG_SWR[14]), .B0(
DMP_SFG[12]), .B1(n636), .C0(DmP_mant_SFG_SWR[14]), .C1(n636), .Y(n891) );
AOI222X4TS U587 ( .A0(DMP_SFG[10]), .A1(DmP_mant_SFG_SWR[12]), .B0(
DMP_SFG[10]), .B1(n625), .C0(DmP_mant_SFG_SWR[12]), .C1(n625), .Y(n630) );
NAND2X1TS U588 ( .A(n763), .B(n436), .Y(n765) );
NOR2X1TS U589 ( .A(Raw_mant_NRM_SWR[14]), .B(n441), .Y(n436) );
NOR2XLTS U590 ( .A(n405), .B(n511), .Y(n512) );
OAI21XLTS U591 ( .A0(n639), .A1(n641), .B0(n638), .Y(n637) );
OAI21XLTS U592 ( .A0(n659), .A1(n902), .B0(n658), .Y(n657) );
OAI21XLTS U593 ( .A0(n633), .A1(n635), .B0(n632), .Y(n631) );
OAI21XLTS U594 ( .A0(n729), .A1(n653), .B0(n728), .Y(Data_array_SWR[4]) );
OAI21XLTS U595 ( .A0(n741), .A1(n653), .B0(n740), .Y(Data_array_SWR[20]) );
OAI21XLTS U596 ( .A0(n718), .A1(n653), .B0(n688), .Y(Data_array_SWR[17]) );
OAI21XLTS U597 ( .A0(n932), .A1(n414), .B0(n679), .Y(Data_array_SWR[25]) );
OAI22X1TS U598 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n991), .B0(n641), .B1(n640),
.Y(n743) );
OAI22X1TS U599 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n972), .B0(n546), .B1(n545),
.Y(n560) );
XOR2X1TS U600 ( .A(n917), .B(n429), .Y(Raw_mant_SGF[25]) );
XOR2X1TS U601 ( .A(n910), .B(n909), .Y(Raw_mant_SGF[24]) );
XOR2X1TS U602 ( .A(n905), .B(n904), .Y(Raw_mant_SGF[23]) );
OAI21X1TS U603 ( .A0(n736), .A1(n653), .B0(n686), .Y(Data_array_SWR[21]) );
OAI21X1TS U604 ( .A0(n697), .A1(n653), .B0(n696), .Y(Data_array_SWR[3]) );
OAI21X1TS U605 ( .A0(n725), .A1(n408), .B0(n681), .Y(Data_array_SWR[6]) );
OAI21X1TS U606 ( .A0(n712), .A1(n414), .B0(n694), .Y(Data_array_SWR[9]) );
OAI21X1TS U607 ( .A0(n713), .A1(n408), .B0(n677), .Y(Data_array_SWR[10]) );
OAI21X1TS U608 ( .A0(n932), .A1(n404), .B0(n668), .Y(Data_array_SWR[22]) );
OAI21X1TS U609 ( .A0(n731), .A1(n653), .B0(n701), .Y(Data_array_SWR[15]) );
OAI21X1TS U610 ( .A0(n731), .A1(n408), .B0(n671), .Y(Data_array_SWR[14]) );
OAI21X1TS U611 ( .A0(n707), .A1(n653), .B0(n684), .Y(Data_array_SWR[2]) );
AOI222X4TS U612 ( .A0(DMP_SFG[22]), .A1(DmP_mant_SFG_SWR[24]), .B0(
DMP_SFG[22]), .B1(n908), .C0(DmP_mant_SFG_SWR[24]), .C1(n908), .Y(n913) );
OAI21X1TS U613 ( .A0(n725), .A1(n653), .B0(n706), .Y(Data_array_SWR[7]) );
OAI21X1TS U614 ( .A0(n724), .A1(n653), .B0(n690), .Y(Data_array_SWR[5]) );
OAI21X1TS U615 ( .A0(n719), .A1(n653), .B0(n699), .Y(Data_array_SWR[19]) );
OAI21X1TS U616 ( .A0(n711), .A1(n653), .B0(n710), .Y(Data_array_SWR[1]) );
OAI21X1TS U617 ( .A0(n730), .A1(n414), .B0(n692), .Y(Data_array_SWR[13]) );
OAI21X1TS U618 ( .A0(n735), .A1(n414), .B0(n734), .Y(Data_array_SWR[12]) );
OAI21X1TS U619 ( .A0(n719), .A1(n408), .B0(n674), .Y(Data_array_SWR[18]) );
OAI21X1TS U620 ( .A0(n717), .A1(n414), .B0(n716), .Y(Data_array_SWR[8]) );
OAI21X1TS U621 ( .A0(n723), .A1(n653), .B0(n722), .Y(Data_array_SWR[16]) );
OAI21X1TS U622 ( .A0(n713), .A1(n414), .B0(n703), .Y(Data_array_SWR[11]) );
XOR2X1TS U623 ( .A(n900), .B(n899), .Y(Raw_mant_SGF[21]) );
OAI21X1TS U624 ( .A0(n652), .A1(n655), .B0(n651), .Y(n650) );
AOI222X4TS U625 ( .A0(DMP_SFG[20]), .A1(DmP_mant_SFG_SWR[22]), .B0(
DMP_SFG[20]), .B1(n817), .C0(DmP_mant_SFG_SWR[22]), .C1(n817), .Y(n903) );
XOR2X1TS U626 ( .A(n777), .B(n776), .Y(Raw_mant_SGF[19]) );
OAI211X1TS U627 ( .A0(n707), .A1(n424), .B0(n711), .C0(n661), .Y(
Data_array_SWR[0]) );
OAI21X1TS U628 ( .A0(n645), .A1(n647), .B0(n644), .Y(n643) );
AOI222X4TS U629 ( .A0(DMP_SFG[18]), .A1(DmP_mant_SFG_SWR[20]), .B0(
DMP_SFG[18]), .B1(n656), .C0(DmP_mant_SFG_SWR[20]), .C1(n656), .Y(n896) );
AND2X2TS U630 ( .A(n665), .B(n664), .Y(n666) );
AOI222X4TS U631 ( .A0(DMP_SFG[14]), .A1(DmP_mant_SFG_SWR[16]), .B0(
DMP_SFG[14]), .B1(n642), .C0(DmP_mant_SFG_SWR[16]), .C1(n642), .Y(n742) );
AOI22X1TS U632 ( .A0(DMP_SFG[13]), .A1(n985), .B0(n893), .B1(n892), .Y(n640)
);
NOR2X6TS U633 ( .A(array_comparators_LTComparator_N0), .B(
array_comparators_GTComparator_N0), .Y(n475) );
AND3X2TS U634 ( .A(n435), .B(exp_rslt_NRM2_EW1[7]), .C(n434), .Y(
array_comparators_GTComparator_N0) );
NAND2BX1TS U635 ( .AN(n755), .B(n422), .Y(n764) );
AOI31X1TS U636 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n456), .A2(n992), .B0(n455),
.Y(n457) );
AOI222X4TS U637 ( .A0(DMP_SFG[8]), .A1(DmP_mant_SFG_SWR[10]), .B0(DMP_SFG[8]), .B1(n579), .C0(DmP_mant_SFG_SWR[10]), .C1(n579), .Y(n619) );
NAND2BX1TS U638 ( .AN(n765), .B(Raw_mant_NRM_SWR[10]), .Y(n760) );
NAND3BX1TS U639 ( .AN(n864), .B(n862), .C(n861), .Y(n882) );
AOI222X4TS U640 ( .A0(DMP_SFG[6]), .A1(DmP_mant_SFG_SWR[8]), .B0(DMP_SFG[6]),
.B1(n568), .C0(DmP_mant_SFG_SWR[8]), .C1(n568), .Y(n573) );
AOI22X2TS U641 ( .A0(DMP_SFG[5]), .A1(n943), .B0(n561), .B1(n560), .Y(n566)
);
NOR2X1TS U642 ( .A(Raw_mant_NRM_SWR[10]), .B(n765), .Y(n437) );
AOI31X1TS U643 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n454), .A2(n983), .B0(n757),
.Y(n446) );
AOI31X1TS U644 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n454), .A2(n453), .B0(n757),
.Y(n458) );
AOI222X4TS U645 ( .A0(DMP_SFG[4]), .A1(DmP_mant_SFG_SWR[6]), .B0(DMP_SFG[4]),
.B1(n547), .C0(DmP_mant_SFG_SWR[6]), .C1(n547), .Y(n562) );
OAI22X1TS U646 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n970), .B0(n534), .B1(n533),
.Y(n539) );
OAI211X1TS U647 ( .A0(n822), .A1(n879), .B0(n821), .C0(n820), .Y(n828) );
NAND2X4TS U648 ( .A(n406), .B(n994), .Y(n510) );
CLKBUFX3TS U649 ( .A(n469), .Y(n418) );
NOR2X4TS U650 ( .A(n406), .B(n511), .Y(n473) );
INVX1TS U651 ( .A(n440), .Y(n454) );
OAI211XLTS U652 ( .A0(intDX_EWSW[8]), .A1(n1042), .B0(n845), .C0(n848), .Y(
n859) );
AOI222X4TS U653 ( .A0(DMP_SFG[2]), .A1(DmP_mant_SFG_SWR[4]), .B0(DMP_SFG[2]),
.B1(n535), .C0(DmP_mant_SFG_SWR[4]), .C1(n535), .Y(n541) );
OAI211XLTS U654 ( .A0(n1048), .A1(intDX_EWSW[3]), .B0(n833), .C0(n832), .Y(
n836) );
NAND2X4TS U655 ( .A(n405), .B(n994), .Y(n466) );
INVX1TS U656 ( .A(n747), .Y(n749) );
INVX1TS U657 ( .A(n756), .Y(n758) );
NOR2X4TS U658 ( .A(shift_value_SHT2_EWR[4]), .B(n588), .Y(n469) );
CLKINVX3TS U659 ( .A(n494), .Y(n468) );
NAND3X1TS U660 ( .A(n1050), .B(n819), .C(intDX_EWSW[26]), .Y(n821) );
OAI211X2TS U661 ( .A0(intDX_EWSW[12]), .A1(n1039), .B0(n855), .C0(n841), .Y(
n857) );
OAI21X1TS U662 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n443), .B0(n988), .Y(n444)
);
INVX3TS U663 ( .A(n916), .Y(n912) );
OAI211X2TS U664 ( .A0(intDX_EWSW[20]), .A1(n1035), .B0(n875), .C0(n860), .Y(
n869) );
NOR2X6TS U665 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n465) );
NAND2BX1TS U666 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n876) );
NAND2BX1TS U667 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n866) );
NAND2BX1TS U668 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n860) );
NOR3X1TS U669 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[16]), .C(
Raw_mant_NRM_SWR[17]), .Y(n756) );
NOR3X1TS U670 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
Raw_mant_NRM_SWR[21]), .Y(n750) );
NAND2BX1TS U671 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n820) );
NAND2BX1TS U672 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n819) );
NOR3X1TS U673 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .Y(n763) );
OAI32X2TS U674 ( .A0(n916), .A1(n915), .A2(n914), .B0(n913), .B1(n912), .Y(
n917) );
NAND2BXLTS U675 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n832) );
AOI2BB2XLTS U676 ( .B0(intDX_EWSW[3]), .B1(n1048), .A0N(intDY_EWSW[2]),
.A1N(n834), .Y(n835) );
NAND2BXLTS U677 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n847) );
NAND3XLTS U678 ( .A(n1042), .B(n845), .C(intDX_EWSW[8]), .Y(n846) );
NOR2XLTS U679 ( .A(n843), .B(intDY_EWSW[10]), .Y(n844) );
OAI21XLTS U680 ( .A0(intDX_EWSW[13]), .A1(n1032), .B0(intDX_EWSW[12]), .Y(
n842) );
NOR2XLTS U681 ( .A(n878), .B(intDY_EWSW[24]), .Y(n818) );
NAND2BXLTS U682 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n845) );
NAND2BXLTS U683 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n841) );
OAI21XLTS U684 ( .A0(intDX_EWSW[23]), .A1(n963), .B0(intDX_EWSW[22]), .Y(
n871) );
BUFX4TS U685 ( .A(n1093), .Y(n682) );
NAND2X1TS U686 ( .A(n750), .B(n747), .Y(n440) );
OAI22X1TS U687 ( .A0(DmP_mant_SFG_SWR[14]), .A1(n984), .B0(n635), .B1(n634),
.Y(n892) );
OAI22X1TS U688 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n974), .B0(n567), .B1(n566),
.Y(n571) );
CLKAND2X2TS U689 ( .A(DmP_mant_SFG_SWR[8]), .B(n974), .Y(n567) );
OAI22X1TS U690 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n993), .B0(n647), .B1(n646),
.Y(n774) );
OAI22X1TS U691 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n998), .B0(n655), .B1(n654),
.Y(n897) );
CLKAND2X2TS U692 ( .A(DmP_mant_SFG_SWR[16]), .B(n991), .Y(n641) );
AOI22X1TS U693 ( .A0(DMP_SFG[7]), .A1(n975), .B0(n572), .B1(n571), .Y(n577)
);
CLKAND2X2TS U694 ( .A(DmP_mant_SFG_SWR[10]), .B(n976), .Y(n578) );
OAI22X1TS U695 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n979), .B0(n624), .B1(n623),
.Y(n628) );
OAI22X1TS U696 ( .A0(DmP_mant_SFG_SWR[10]), .A1(n976), .B0(n578), .B1(n577),
.Y(n617) );
AOI22X1TS U697 ( .A0(DMP_SFG[19]), .A1(n1013), .B0(n898), .B1(n897), .Y(n901) );
OAI21XLTS U698 ( .A0(n494), .A1(n1019), .B0(n491), .Y(n492) );
OAI21XLTS U699 ( .A0(n494), .A1(n964), .B0(n493), .Y(n495) );
AOI211X1TS U700 ( .A0(n420), .A1(Data_array_SWR[45]), .B0(n496), .C0(n490),
.Y(n507) );
OAI21XLTS U701 ( .A0(n494), .A1(n1017), .B0(n489), .Y(n490) );
AO22XLTS U702 ( .A0(Data_array_SWR[44]), .A1(n469), .B0(n416), .B1(
Data_array_SWR[40]), .Y(n487) );
AOI211X1TS U703 ( .A0(Data_array_SWR[44]), .A1(n420), .B0(n496), .C0(n482),
.Y(n509) );
OAI21XLTS U704 ( .A0(n1016), .A1(n494), .B0(n481), .Y(n482) );
AO22XLTS U705 ( .A0(n469), .A1(Data_array_SWR[45]), .B0(n416), .B1(
Data_array_SWR[41]), .Y(n480) );
AOI22X1TS U706 ( .A0(DMP_SFG[3]), .A1(n971), .B0(n540), .B1(n539), .Y(n545)
);
CLKAND2X2TS U707 ( .A(DmP_mant_SFG_SWR[6]), .B(n972), .Y(n546) );
AOI22X1TS U708 ( .A0(DMP_SFG[11]), .A1(n981), .B0(n629), .B1(n628), .Y(n634)
);
CLKAND2X2TS U709 ( .A(DmP_mant_SFG_SWR[14]), .B(n984), .Y(n635) );
CLKAND2X2TS U710 ( .A(DmP_mant_SFG_SWR[18]), .B(n993), .Y(n647) );
AOI22X1TS U711 ( .A0(DMP_SFG[15]), .A1(n397), .B0(n744), .B1(n743), .Y(n646)
);
AOI22X1TS U712 ( .A0(DMP_SFG[17]), .A1(n398), .B0(n775), .B1(n774), .Y(n654)
);
CLKAND2X2TS U713 ( .A(DmP_mant_SFG_SWR[20]), .B(n998), .Y(n655) );
AOI22X1TS U714 ( .A0(DMP_SFG[9]), .A1(n977), .B0(n618), .B1(n617), .Y(n623)
);
CLKAND2X2TS U715 ( .A(DmP_mant_SFG_SWR[12]), .B(n979), .Y(n624) );
NAND2BXLTS U716 ( .AN(Raw_mant_NRM_SWR[23]), .B(n949), .Y(n450) );
INVX2TS U717 ( .A(n447), .Y(n448) );
AOI22X1TS U718 ( .A0(DMP_SFG[1]), .A1(n968), .B0(n529), .B1(n528), .Y(n533)
);
CLKAND2X2TS U719 ( .A(DmP_mant_SFG_SWR[4]), .B(n970), .Y(n534) );
NAND2X1TS U720 ( .A(DMP_SFG[0]), .B(DmP_mant_SFG_SWR[2]), .Y(n887) );
AO22XLTS U721 ( .A0(n935), .A1(LZD_raw_out_EWR[4]), .B0(
Shift_amount_SHT1_EWR[4]), .B1(n934), .Y(shft_value_mux_o_EWR[4]) );
XOR2XLTS U722 ( .A(n895), .B(n894), .Y(Raw_mant_SGF[15]) );
OAI21XLTS U723 ( .A0(DmP_mant_SFG_SWR[15]), .A1(n948), .B0(n893), .Y(n894)
);
XOR2XLTS U724 ( .A(n570), .B(n569), .Y(Raw_mant_SGF[9]) );
OAI21XLTS U725 ( .A0(n565), .A1(n567), .B0(n564), .Y(n563) );
XOR2XLTS U726 ( .A(n549), .B(n548), .Y(Raw_mant_SGF[7]) );
AO22XLTS U727 ( .A0(n1090), .A1(LZD_raw_out_EWR[3]), .B0(
Shift_amount_SHT1_EWR[3]), .B1(n934), .Y(shft_value_mux_o_EWR[3]) );
XOR2XLTS U728 ( .A(n627), .B(n626), .Y(Raw_mant_SGF[13]) );
XOR2XLTS U729 ( .A(n581), .B(n580), .Y(Raw_mant_SGF[11]) );
AO22XLTS U730 ( .A0(n935), .A1(LZD_raw_out_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n1093), .Y(shft_value_mux_o_EWR[2]) );
CLKAND2X2TS U731 ( .A(n475), .B(sftr_odat_SHT2_SWR[24]), .Y(
formatted_number_W[22]) );
CLKAND2X2TS U732 ( .A(n475), .B(sftr_odat_SHT2_SWR[23]), .Y(
formatted_number_W[21]) );
CLKAND2X2TS U733 ( .A(n475), .B(sftr_odat_SHT2_SWR[22]), .Y(
formatted_number_W[20]) );
CLKAND2X2TS U734 ( .A(n426), .B(sftr_odat_SHT2_SWR[21]), .Y(
formatted_number_W[19]) );
CLKAND2X2TS U735 ( .A(n426), .B(sftr_odat_SHT2_SWR[20]), .Y(
formatted_number_W[18]) );
CLKAND2X2TS U736 ( .A(n426), .B(sftr_odat_SHT2_SWR[19]), .Y(
formatted_number_W[17]) );
CLKAND2X2TS U737 ( .A(n426), .B(sftr_odat_SHT2_SWR[18]), .Y(
formatted_number_W[16]) );
CLKAND2X2TS U738 ( .A(n426), .B(sftr_odat_SHT2_SWR[17]), .Y(
formatted_number_W[15]) );
CLKAND2X2TS U739 ( .A(n475), .B(sftr_odat_SHT2_SWR[16]), .Y(
formatted_number_W[14]) );
CLKAND2X2TS U740 ( .A(n475), .B(sftr_odat_SHT2_SWR[9]), .Y(
formatted_number_W[7]) );
CLKAND2X2TS U741 ( .A(n475), .B(sftr_odat_SHT2_SWR[8]), .Y(
formatted_number_W[6]) );
CLKAND2X2TS U742 ( .A(n426), .B(sftr_odat_SHT2_SWR[7]), .Y(
formatted_number_W[5]) );
CLKAND2X2TS U743 ( .A(n426), .B(sftr_odat_SHT2_SWR[6]), .Y(
formatted_number_W[4]) );
CLKAND2X2TS U744 ( .A(n426), .B(sftr_odat_SHT2_SWR[5]), .Y(
formatted_number_W[3]) );
CLKAND2X2TS U745 ( .A(n426), .B(sftr_odat_SHT2_SWR[4]), .Y(
formatted_number_W[2]) );
CLKAND2X2TS U746 ( .A(n475), .B(sftr_odat_SHT2_SWR[3]), .Y(
formatted_number_W[1]) );
CLKAND2X2TS U747 ( .A(n475), .B(sftr_odat_SHT2_SWR[2]), .Y(
formatted_number_W[0]) );
CLKAND2X2TS U748 ( .A(n475), .B(sftr_odat_SHT2_SWR[15]), .Y(
formatted_number_W[13]) );
CLKAND2X2TS U749 ( .A(n475), .B(sftr_odat_SHT2_SWR[14]), .Y(
formatted_number_W[12]) );
CLKAND2X2TS U750 ( .A(n475), .B(sftr_odat_SHT2_SWR[13]), .Y(
formatted_number_W[11]) );
CLKAND2X2TS U751 ( .A(n475), .B(sftr_odat_SHT2_SWR[12]), .Y(
formatted_number_W[10]) );
CLKAND2X2TS U752 ( .A(n475), .B(sftr_odat_SHT2_SWR[11]), .Y(
formatted_number_W[9]) );
CLKAND2X2TS U753 ( .A(n475), .B(sftr_odat_SHT2_SWR[10]), .Y(
formatted_number_W[8]) );
AOI2BB1XLTS U754 ( .A0N(array_comparators_LTComparator_N0), .A1N(
SIGN_FLAG_SHT1SHT2), .B0(array_comparators_GTComparator_N0), .Y(
formatted_number_W[31]) );
OR2X1TS U755 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[6]), .Y(formatted_number_W[29]) );
OR2X1TS U756 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[5]), .Y(formatted_number_W[28]) );
OR2X1TS U757 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[4]), .Y(formatted_number_W[27]) );
OR2X1TS U758 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[3]), .Y(formatted_number_W[26]) );
OR2X1TS U759 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[1]), .Y(formatted_number_W[24]) );
OR2X1TS U760 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[0]), .Y(formatted_number_W[23]) );
OAI21XLTS U761 ( .A0(n544), .A1(n546), .B0(n543), .Y(n542) );
XOR2XLTS U762 ( .A(n746), .B(n745), .Y(Raw_mant_SGF[17]) );
OAI21XLTS U763 ( .A0(n622), .A1(n624), .B0(n621), .Y(n620) );
OAI21XLTS U764 ( .A0(n510), .A1(n556), .B0(n555), .Y(sftr_odat_SHT2_SWR[1])
);
AOI211X1TS U765 ( .A0(n759), .A1(n758), .B0(n757), .C0(n768), .Y(n761) );
INVX2TS U766 ( .A(n406), .Y(n608) );
OR2X1TS U767 ( .A(shift_value_SHT2_EWR[4]), .B(n497), .Y(n399) );
INVX2TS U768 ( .A(n705), .Y(n403) );
INVX2TS U769 ( .A(n705), .Y(n404) );
INVX2TS U770 ( .A(left_right_SHT2), .Y(n405) );
INVX2TS U771 ( .A(n405), .Y(n406) );
INVX2TS U772 ( .A(n666), .Y(n407) );
INVX4TS U773 ( .A(n666), .Y(n408) );
INVX4TS U774 ( .A(n924), .Y(n927) );
INVX4TS U775 ( .A(n921), .Y(n923) );
INVX4TS U776 ( .A(n919), .Y(n928) );
CLKINVX3TS U777 ( .A(n679), .Y(n409) );
CLKINVX3TS U778 ( .A(n679), .Y(n410) );
OAI221X1TS U779 ( .A0(n1002), .A1(intDY_EWSW[10]), .B0(n400), .B1(
intDY_EWSW[2]), .C0(n783), .Y(n786) );
OAI221X1TS U780 ( .A0(n951), .A1(intDY_EWSW[3]), .B0(n1010), .B1(
intDY_EWSW[26]), .C0(n791), .Y(n794) );
OAI221X1TS U781 ( .A0(n956), .A1(intDY_EWSW[20]), .B0(n1015), .B1(
intDY_EWSW[30]), .C0(n805), .Y(n812) );
AOI221X1TS U782 ( .A0(intDX_EWSW[30]), .A1(n995), .B0(intDX_EWSW[29]), .B1(
n950), .C0(n825), .Y(n827) );
NOR2X2TS U783 ( .A(n587), .B(n999), .Y(n499) );
CLKINVX3TS U784 ( .A(rst), .Y(n461) );
BUFX4TS U785 ( .A(n1076), .Y(n1074) );
OAI21XLTS U786 ( .A0(n559), .A1(n466), .B0(n553), .Y(sftr_odat_SHT2_SWR[25])
);
OAI211X1TS U787 ( .A0(n994), .A1(n559), .B0(n502), .C0(n501), .Y(n520) );
AOI21X2TS U788 ( .A0(n465), .A1(Data_array_SWR[51]), .B0(n500), .Y(n559) );
BUFX4TS U789 ( .A(n1071), .Y(n1065) );
BUFX4TS U790 ( .A(n1069), .Y(n1079) );
BUFX4TS U791 ( .A(n462), .Y(n1075) );
BUFX4TS U792 ( .A(n1071), .Y(n1078) );
OAI211X1TS U793 ( .A0(n994), .A1(n584), .B0(n583), .C0(n582), .Y(n596) );
AOI21X2TS U794 ( .A0(Data_array_SWR[48]), .A1(n465), .B0(n500), .Y(n584) );
OAI211X1TS U795 ( .A0(n994), .A1(n601), .B0(n600), .C0(n599), .Y(n611) );
AOI21X2TS U796 ( .A0(n465), .A1(Data_array_SWR[49]), .B0(n500), .Y(n601) );
INVX4TS U797 ( .A(rst), .Y(n411) );
CLKBUFX2TS U798 ( .A(n1073), .Y(n1085) );
BUFX4TS U799 ( .A(n1071), .Y(n1059) );
BUFX4TS U800 ( .A(n1073), .Y(n1060) );
BUFX4TS U801 ( .A(n1066), .Y(n1063) );
BUFX4TS U802 ( .A(n1072), .Y(n1061) );
AOI21X2TS U803 ( .A0(n465), .A1(Data_array_SWR[50]), .B0(n500), .Y(n556) );
AOI21X2TS U804 ( .A0(n465), .A1(Data_array_SWR[46]), .B0(n589), .Y(n605) );
AOI21X2TS U805 ( .A0(n465), .A1(Data_array_SWR[47]), .B0(n586), .Y(n610) );
AOI222X4TS U806 ( .A0(DmP_mant_SFG_SWR[2]), .A1(n969), .B0(
DmP_mant_SFG_SWR[2]), .B1(n888), .C0(n969), .C1(n888), .Y(n529) );
OR2X1TS U807 ( .A(N60), .B(N59), .Y(n888) );
INVX2TS U808 ( .A(n402), .Y(n412) );
OAI21XLTS U809 ( .A0(n510), .A1(n559), .B0(n558), .Y(sftr_odat_SHT2_SWR[0])
);
BUFX4TS U810 ( .A(n682), .Y(n934) );
INVX2TS U811 ( .A(n653), .Y(n413) );
INVX2TS U812 ( .A(n413), .Y(n414) );
OAI21X2TS U813 ( .A0(n663), .A1(n980), .B0(n662), .Y(n738) );
BUFX4TS U814 ( .A(n918), .Y(n926) );
AOI222X4TS U815 ( .A0(n682), .A1(DmP_mant_SHT1_SW[1]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[22]), .C0(Raw_mant_NRM_SWR[3]), .C1(n409), .Y(n697)
);
INVX2TS U816 ( .A(n470), .Y(n415) );
INVX2TS U817 ( .A(n415), .Y(n416) );
INVX2TS U818 ( .A(n415), .Y(n417) );
INVX2TS U819 ( .A(n399), .Y(n419) );
INVX2TS U820 ( .A(n399), .Y(n420) );
OAI2BB1X1TS U821 ( .A0N(n935), .A1N(Raw_mant_NRM_SWR[15]), .B0(n675), .Y(
n715) );
NOR2X1TS U822 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[8]), .Y(n766)
);
NOR4X1TS U823 ( .A(Raw_mant_NRM_SWR[9]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[11]), .D(n762), .Y(n442) );
INVX2TS U824 ( .A(n395), .Y(n422) );
INVX2TS U825 ( .A(n396), .Y(n423) );
INVX2TS U826 ( .A(n739), .Y(n424) );
NOR2X4TS U827 ( .A(n665), .B(n664), .Y(n739) );
BUFX3TS U828 ( .A(n424), .Y(n933) );
OAI221X1TS U829 ( .A0(n958), .A1(intDY_EWSW[27]), .B0(n1009), .B1(
intDY_EWSW[19]), .C0(n799), .Y(n802) );
OAI221X1TS U830 ( .A0(n1003), .A1(intDY_EWSW[17]), .B0(n1018), .B1(
intDY_EWSW[16]), .C0(n807), .Y(n810) );
OAI221X1TS U831 ( .A0(n1057), .A1(intDY_EWSW[7]), .B0(n1008), .B1(
intDY_EWSW[14]), .C0(n789), .Y(n796) );
BUFX3TS U832 ( .A(n462), .Y(n425) );
BUFX3TS U833 ( .A(n461), .Y(n462) );
NOR2X2TS U834 ( .A(n986), .B(n441), .Y(n757) );
NOR3X6TS U835 ( .A(n435), .B(exp_rslt_NRM2_EW1[7]), .C(n432), .Y(
array_comparators_LTComparator_N0) );
XNOR2X2TS U836 ( .A(DP_OP_15J180_122_6956_n1), .B(ADD_OVRFLW_NRM2), .Y(n435)
);
OAI21X2TS U837 ( .A0(n978), .A1(n679), .B0(n678), .Y(n727) );
OAI21X2TS U838 ( .A0(n987), .A1(n679), .B0(n672), .Y(n721) );
OAI21X2TS U839 ( .A0(n986), .A1(n679), .B0(n669), .Y(n733) );
NAND2X2TS U840 ( .A(Shift_reg_FLAGS_7[1]), .B(ADD_OVRFLW_NRM), .Y(n679) );
AOI222X4TS U841 ( .A0(n682), .A1(DmP_mant_SHT1_SW[0]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[23]), .C0(n423), .C1(n410), .Y(n707) );
OAI21XLTS U842 ( .A0(intDX_EWSW[3]), .A1(n1048), .B0(intDX_EWSW[2]), .Y(n834) );
NOR2X4TS U843 ( .A(n660), .B(n665), .Y(n705) );
INVX4TS U844 ( .A(n924), .Y(n925) );
BUFX4TS U845 ( .A(n918), .Y(n924) );
BUFX3TS U846 ( .A(n475), .Y(n426) );
AOI21X2TS U847 ( .A0(n465), .A1(Data_array_SWR[45]), .B0(n467), .Y(n598) );
AOI21X2TS U848 ( .A0(n465), .A1(Data_array_SWR[44]), .B0(n483), .Y(n614) );
NAND2X2TS U849 ( .A(bit_shift_SHT2), .B(shift_value_SHT2_EWR[3]), .Y(n587)
);
NAND3X2TS U850 ( .A(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.C(n994), .Y(n494) );
OAI221X4TS U851 ( .A0(n427), .A1(intDY_EWSW[28]), .B0(n1005), .B1(
intDY_EWSW[6]), .C0(n797), .Y(n804) );
OAI32X1TS U852 ( .A0(Raw_mant_NRM_SWR[23]), .A1(Raw_mant_NRM_SWR[21]), .A2(
n989), .B0(n949), .B1(Raw_mant_NRM_SWR[23]), .Y(n443) );
NOR2XLTS U853 ( .A(Raw_mant_NRM_SWR[20]), .B(Raw_mant_NRM_SWR[21]), .Y(n452)
);
NOR2XLTS U854 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[17]), .Y(n453)
);
NOR4X2TS U855 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .C(
Raw_mant_NRM_SWR[22]), .D(Raw_mant_NRM_SWR[23]), .Y(n747) );
NOR2XLTS U856 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[11]), .Y(n748)
);
INVX2TS U857 ( .A(intDX_EWSW[28]), .Y(n824) );
OAI21XLTS U858 ( .A0(intDX_EWSW[1]), .A1(n1047), .B0(intDX_EWSW[0]), .Y(n831) );
OAI21XLTS U859 ( .A0(intDX_EWSW[15]), .A1(n1049), .B0(intDX_EWSW[14]), .Y(
n851) );
NOR2XLTS U860 ( .A(n864), .B(intDY_EWSW[16]), .Y(n865) );
OAI21XLTS U861 ( .A0(intDX_EWSW[21]), .A1(n1033), .B0(intDX_EWSW[20]), .Y(
n863) );
OR2X1TS U862 ( .A(ADD_OVRFLW_NRM2), .B(LZD_output_NRM2_EW[0]), .Y(n780) );
OR2X1TS U863 ( .A(n499), .B(n496), .Y(n488) );
NAND2X1TS U864 ( .A(n769), .B(n978), .Y(n755) );
OAI21XLTS U865 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n960), .B0(n898), .Y(n899)
);
OAI21XLTS U866 ( .A0(n576), .A1(n578), .B0(n575), .Y(n574) );
OR2X1TS U867 ( .A(array_comparators_LTComparator_N0), .B(
exp_rslt_NRM2_EW1[2]), .Y(formatted_number_W[25]) );
OAI21XLTS U868 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(n937), .B0(
n936), .Y(n388) );
OR2X2TS U869 ( .A(ADD_OVRFLW_NRM), .B(n934), .Y(n663) );
INVX4TS U870 ( .A(n663), .Y(n1090) );
OR4X2TS U871 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n431) );
OR4X2TS U872 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n431), .Y(n432) );
AND4X1TS U873 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
exp_rslt_NRM2_EW1[1]), .D(exp_rslt_NRM2_EW1[0]), .Y(n433) );
AND4X1TS U874 ( .A(exp_rslt_NRM2_EW1[6]), .B(exp_rslt_NRM2_EW1[5]), .C(
exp_rslt_NRM2_EW1[4]), .D(n433), .Y(n434) );
NOR2X1TS U875 ( .A(Raw_mant_NRM_SWR[18]), .B(n440), .Y(n759) );
NAND2X1TS U876 ( .A(n759), .B(n756), .Y(n441) );
INVX2TS U877 ( .A(n436), .Y(n762) );
NOR2X1TS U878 ( .A(Raw_mant_NRM_SWR[13]), .B(n762), .Y(n456) );
OAI21X1TS U879 ( .A0(n440), .A1(n987), .B0(n760), .Y(n455) );
NAND2X1TS U880 ( .A(n766), .B(n437), .Y(n447) );
NOR2X2TS U881 ( .A(Raw_mant_NRM_SWR[7]), .B(n447), .Y(n769) );
AOI21X1TS U882 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n982), .B0(n423), .Y(n438) );
NOR3X2TS U883 ( .A(Raw_mant_NRM_SWR[5]), .B(n422), .C(n755), .Y(n752) );
NAND2X1TS U884 ( .A(n752), .B(n980), .Y(n772) );
OAI22X1TS U885 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n764), .B0(n438), .B1(n772),
.Y(n439) );
AOI211X1TS U886 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n456), .B0(n455), .C0(n439),
.Y(n754) );
AOI22X1TS U887 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n442), .B0(
Raw_mant_NRM_SWR[6]), .B1(n769), .Y(n445) );
NAND4X1TS U888 ( .A(n754), .B(n446), .C(n445), .D(n444), .Y(
LZD_raw_out_EWR[0]) );
OA21XLTS U889 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n423), .B0(n752), .Y(n449) );
OAI31X1TS U890 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n449), .A2(
Raw_mant_NRM_SWR[6]), .B0(n448), .Y(n771) );
NOR2X1TS U891 ( .A(Raw_mant_NRM_SWR[24]), .B(Raw_mant_NRM_SWR[25]), .Y(n451)
);
AOI32X1TS U892 ( .A0(n452), .A1(n451), .A2(Raw_mant_NRM_SWR[19]), .B0(n450),
.B1(n451), .Y(n459) );
NAND4X1TS U893 ( .A(n771), .B(n459), .C(n458), .D(n457), .Y(
LZD_raw_out_EWR[1]) );
AOI33XLTS U894 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n965), .B1(n940), .B2(n1024),
.Y(n390) );
BUFX3TS U895 ( .A(n461), .Y(n1071) );
BUFX3TS U896 ( .A(n461), .Y(n1070) );
BUFX3TS U897 ( .A(n461), .Y(n1069) );
CLKBUFX2TS U898 ( .A(n461), .Y(n460) );
CLKBUFX2TS U899 ( .A(n461), .Y(n463) );
BUFX3TS U900 ( .A(n461), .Y(n1072) );
CLKBUFX2TS U901 ( .A(n462), .Y(n1089) );
BUFX3TS U902 ( .A(n1069), .Y(n1088) );
BUFX3TS U903 ( .A(n1069), .Y(n1084) );
BUFX3TS U904 ( .A(n1072), .Y(n1086) );
BUFX3TS U905 ( .A(n1066), .Y(n1087) );
CLKBUFX2TS U906 ( .A(n461), .Y(n464) );
BUFX3TS U907 ( .A(n1069), .Y(n1062) );
BUFX3TS U908 ( .A(n1073), .Y(n1067) );
BUFX3TS U909 ( .A(n461), .Y(n1066) );
BUFX3TS U910 ( .A(n461), .Y(n1073) );
BUFX3TS U911 ( .A(n1072), .Y(n1082) );
BUFX3TS U912 ( .A(n1066), .Y(n1068) );
BUFX3TS U913 ( .A(n1073), .Y(n1083) );
BUFX3TS U914 ( .A(n462), .Y(n1077) );
BUFX3TS U915 ( .A(n462), .Y(n1081) );
BUFX3TS U916 ( .A(n1071), .Y(n1080) );
BUFX3TS U917 ( .A(n1072), .Y(n1058) );
BUFX3TS U918 ( .A(n1070), .Y(n1076) );
BUFX3TS U919 ( .A(n1066), .Y(n1064) );
NOR2BX2TS U920 ( .AN(bit_shift_SHT2), .B(n465), .Y(n500) );
NAND2BX2TS U921 ( .AN(shift_value_SHT2_EWR[3]), .B(shift_value_SHT2_EWR[2]),
.Y(n588) );
OAI21X1TS U922 ( .A0(n588), .A1(n1017), .B0(n587), .Y(n467) );
NAND2X1TS U923 ( .A(shift_value_SHT2_EWR[3]), .B(n999), .Y(n497) );
AOI22X1TS U924 ( .A0(n468), .A1(Data_array_SWR[41]), .B0(n419), .B1(
Data_array_SWR[37]), .Y(n472) );
NOR2BX1TS U925 ( .AN(n465), .B(shift_value_SHT2_EWR[4]), .Y(n470) );
AOI22X1TS U926 ( .A0(n469), .A1(Data_array_SWR[33]), .B0(n416), .B1(
Data_array_SWR[29]), .Y(n471) );
OAI211X1TS U927 ( .A0(n598), .A1(n994), .B0(n472), .C0(n471), .Y(n515) );
NAND2X1TS U928 ( .A(shift_value_SHT2_EWR[4]), .B(bit_shift_SHT2), .Y(n511)
);
AOI21X1TS U929 ( .A0(left_right_SHT2), .A1(n515), .B0(n473), .Y(n474) );
OAI21X1TS U930 ( .A0(n584), .A1(n466), .B0(n474), .Y(sftr_odat_SHT2_SWR[22])
);
OAI22X1TS U931 ( .A0(n588), .A1(n961), .B0(n497), .B1(n1019), .Y(n476) );
AOI22X1TS U932 ( .A0(n418), .A1(Data_array_SWR[31]), .B0(n417), .B1(
Data_array_SWR[27]), .Y(n478) );
AOI22X1TS U933 ( .A0(n468), .A1(Data_array_SWR[39]), .B0(n419), .B1(
Data_array_SWR[35]), .Y(n477) );
OAI211X1TS U934 ( .A0(n524), .A1(n994), .B0(n478), .C0(n477), .Y(n554) );
AOI21X1TS U935 ( .A0(left_right_SHT2), .A1(n554), .B0(n473), .Y(n479) );
OAI21X1TS U936 ( .A0(n556), .A1(n466), .B0(n479), .Y(sftr_odat_SHT2_SWR[24])
);
INVX2TS U937 ( .A(n511), .Y(n496) );
AOI211X1TS U938 ( .A0(n420), .A1(Data_array_SWR[49]), .B0(n488), .C0(n480),
.Y(n508) );
AOI22X1TS U939 ( .A0(n418), .A1(Data_array_SWR[40]), .B0(n417), .B1(
Data_array_SWR[36]), .Y(n481) );
AOI22X1TS U940 ( .A0(n406), .A1(n508), .B0(n509), .B1(n608), .Y(
sftr_odat_SHT2_SWR[10]) );
OAI21X1TS U941 ( .A0(n588), .A1(n1016), .B0(n587), .Y(n483) );
AOI22X1TS U942 ( .A0(n468), .A1(Data_array_SWR[40]), .B0(n419), .B1(
Data_array_SWR[36]), .Y(n485) );
AOI22X1TS U943 ( .A0(n469), .A1(Data_array_SWR[32]), .B0(n417), .B1(
Data_array_SWR[28]), .Y(n484) );
OAI211X1TS U944 ( .A0(n614), .A1(n994), .B0(n485), .C0(n484), .Y(n513) );
AOI21X1TS U945 ( .A0(left_right_SHT2), .A1(n513), .B0(n473), .Y(n486) );
OAI21X1TS U946 ( .A0(n601), .A1(n466), .B0(n486), .Y(sftr_odat_SHT2_SWR[23])
);
AOI211X1TS U947 ( .A0(Data_array_SWR[48]), .A1(n420), .B0(n488), .C0(n487),
.Y(n506) );
AOI22X1TS U948 ( .A0(n418), .A1(Data_array_SWR[41]), .B0(n417), .B1(
Data_array_SWR[37]), .Y(n489) );
AOI22X1TS U949 ( .A0(left_right_SHT2), .A1(n506), .B0(n507), .B1(n608), .Y(
sftr_odat_SHT2_SWR[11]) );
AOI22X1TS U950 ( .A0(n469), .A1(Data_array_SWR[43]), .B0(n416), .B1(
Data_array_SWR[39]), .Y(n491) );
AOI211X1TS U951 ( .A0(n420), .A1(Data_array_SWR[47]), .B0(n496), .C0(n492),
.Y(n504) );
AOI22X1TS U952 ( .A0(n469), .A1(Data_array_SWR[42]), .B0(n416), .B1(
Data_array_SWR[38]), .Y(n493) );
AOI211X1TS U953 ( .A0(n420), .A1(Data_array_SWR[46]), .B0(n496), .C0(n495),
.Y(n505) );
AOI22X1TS U954 ( .A0(n406), .A1(n504), .B0(n505), .B1(n608), .Y(
sftr_odat_SHT2_SWR[12]) );
OAI22X1TS U955 ( .A0(n588), .A1(n1022), .B0(n497), .B1(n964), .Y(n498) );
AOI22X1TS U956 ( .A0(n418), .A1(Data_array_SWR[39]), .B0(n419), .B1(
Data_array_SWR[43]), .Y(n502) );
AOI22X1TS U957 ( .A0(n417), .A1(Data_array_SWR[35]), .B0(n468), .B1(
Data_array_SWR[47]), .Y(n501) );
AOI21X1TS U958 ( .A0(n406), .A1(n520), .B0(n473), .Y(n503) );
OAI21X1TS U959 ( .A0(n552), .A1(n466), .B0(n503), .Y(sftr_odat_SHT2_SWR[16])
);
AOI22X1TS U960 ( .A0(left_right_SHT2), .A1(n505), .B0(n504), .B1(n405), .Y(
sftr_odat_SHT2_SWR[13]) );
AOI22X1TS U961 ( .A0(n406), .A1(n507), .B0(n506), .B1(n405), .Y(
sftr_odat_SHT2_SWR[14]) );
AOI22X1TS U962 ( .A0(left_right_SHT2), .A1(n509), .B0(n508), .B1(n405), .Y(
sftr_odat_SHT2_SWR[15]) );
BUFX3TS U963 ( .A(n512), .Y(n606) );
AOI21X1TS U964 ( .A0(n608), .A1(n513), .B0(n606), .Y(n514) );
OAI21X1TS U965 ( .A0(n601), .A1(n510), .B0(n514), .Y(sftr_odat_SHT2_SWR[2])
);
AOI21X1TS U966 ( .A0(n608), .A1(n515), .B0(n606), .Y(n516) );
OAI21X1TS U967 ( .A0(n510), .A1(n584), .B0(n516), .Y(sftr_odat_SHT2_SWR[3])
);
AOI22X1TS U968 ( .A0(n468), .A1(Data_array_SWR[46]), .B0(n419), .B1(
Data_array_SWR[42]), .Y(n518) );
AOI22X1TS U969 ( .A0(n469), .A1(Data_array_SWR[38]), .B0(n416), .B1(
Data_array_SWR[34]), .Y(n517) );
OAI211X1TS U970 ( .A0(n994), .A1(n556), .B0(n518), .C0(n517), .Y(n522) );
AOI21X1TS U971 ( .A0(n608), .A1(n522), .B0(n606), .Y(n519) );
OAI21X1TS U972 ( .A0(n524), .A1(n510), .B0(n519), .Y(sftr_odat_SHT2_SWR[8])
);
AOI21X1TS U973 ( .A0(n608), .A1(n520), .B0(n606), .Y(n521) );
OAI21X1TS U974 ( .A0(n552), .A1(n510), .B0(n521), .Y(sftr_odat_SHT2_SWR[9])
);
AOI21X1TS U975 ( .A0(left_right_SHT2), .A1(n522), .B0(n473), .Y(n523) );
OAI21X1TS U976 ( .A0(n524), .A1(n466), .B0(n523), .Y(sftr_odat_SHT2_SWR[17])
);
NAND2X1TS U977 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n940), .Y(n937)
);
NAND2X1TS U978 ( .A(n965), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n936)
);
NAND2X1TS U979 ( .A(DmP_EXP_EWSW[23]), .B(n430), .Y(n527) );
OAI21XLTS U980 ( .A0(DmP_EXP_EWSW[23]), .A1(n430), .B0(n527), .Y(
Shift_amount_EXP_EW[0]) );
INVX2TS U981 ( .A(intadd_428_SUM_0_), .Y(Shift_amount_EXP_EW[1]) );
INVX2TS U982 ( .A(intadd_428_SUM_1_), .Y(Shift_amount_EXP_EW[2]) );
CLKBUFX2TS U983 ( .A(n1091), .Y(n916) );
AOI22X1TS U984 ( .A0(n912), .A1(n529), .B0(n887), .B1(n916), .Y(n526) );
NAND2X1TS U985 ( .A(DmP_mant_SFG_SWR[3]), .B(n941), .Y(n528) );
OAI21XLTS U986 ( .A0(DmP_mant_SFG_SWR[3]), .A1(n941), .B0(n528), .Y(n525) );
XOR2XLTS U987 ( .A(n526), .B(n525), .Y(Raw_mant_SGF[3]) );
INVX2TS U988 ( .A(intadd_428_SUM_2_), .Y(Shift_amount_EXP_EW[3]) );
INVX2TS U989 ( .A(n527), .Y(intadd_428_CI) );
NOR2X1TS U990 ( .A(DmP_mant_SFG_SWR[4]), .B(n970), .Y(n532) );
AOI222X4TS U991 ( .A0(n941), .A1(n887), .B0(n941), .B1(n968), .C0(n887),
.C1(n968), .Y(n535) );
BUFX3TS U992 ( .A(n1091), .Y(n649) );
AOI22X1TS U993 ( .A0(n912), .A1(n533), .B0(n535), .B1(n649), .Y(n531) );
OAI21XLTS U994 ( .A0(n532), .A1(n534), .B0(n531), .Y(n530) );
OAI31X1TS U995 ( .A0(n532), .A1(n531), .A2(n534), .B0(n530), .Y(
Raw_mant_SGF[4]) );
AOI22X1TS U996 ( .A0(n912), .A1(n539), .B0(n541), .B1(n649), .Y(n537) );
NAND2X1TS U997 ( .A(DmP_mant_SFG_SWR[5]), .B(n942), .Y(n540) );
OAI21XLTS U998 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n942), .B0(n540), .Y(n536) );
XOR2XLTS U999 ( .A(n537), .B(n536), .Y(Raw_mant_SGF[5]) );
OAI211X1TS U1000 ( .A0(n940), .A1(n936), .B0(n937), .C0(beg_OP), .Y(n538) );
INVX2TS U1001 ( .A(n538), .Y(enable_Pipeline_input) );
NOR2X1TS U1002 ( .A(DmP_mant_SFG_SWR[6]), .B(n972), .Y(n544) );
AOI222X4TS U1003 ( .A0(n541), .A1(n942), .B0(n541), .B1(n971), .C0(n942),
.C1(n971), .Y(n547) );
AOI22X1TS U1004 ( .A0(n912), .A1(n545), .B0(n547), .B1(n649), .Y(n543) );
OAI31X1TS U1005 ( .A0(n544), .A1(n543), .A2(n546), .B0(n542), .Y(
Raw_mant_SGF[6]) );
AOI22X1TS U1006 ( .A0(n912), .A1(n560), .B0(n562), .B1(n649), .Y(n549) );
NAND2X1TS U1007 ( .A(DmP_mant_SFG_SWR[7]), .B(n973), .Y(n561) );
OAI21XLTS U1008 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n973), .B0(n561), .Y(n548)
);
AOI22X1TS U1009 ( .A0(n418), .A1(Data_array_SWR[30]), .B0(n420), .B1(
Data_array_SWR[34]), .Y(n551) );
AOI22X1TS U1010 ( .A0(n417), .A1(Data_array_SWR[26]), .B0(n468), .B1(
Data_array_SWR[38]), .Y(n550) );
OAI211X1TS U1011 ( .A0(n552), .A1(n994), .B0(n551), .C0(n550), .Y(n557) );
AOI21X1TS U1012 ( .A0(left_right_SHT2), .A1(n557), .B0(n473), .Y(n553) );
AOI21X1TS U1013 ( .A0(n405), .A1(n554), .B0(n606), .Y(n555) );
AOI21X1TS U1014 ( .A0(n405), .A1(n557), .B0(n606), .Y(n558) );
NOR2X1TS U1015 ( .A(DmP_mant_SFG_SWR[8]), .B(n974), .Y(n565) );
AOI222X4TS U1016 ( .A0(n562), .A1(n973), .B0(n562), .B1(n943), .C0(n973),
.C1(n943), .Y(n568) );
AOI22X1TS U1017 ( .A0(n912), .A1(n566), .B0(n568), .B1(n649), .Y(n564) );
OAI31X1TS U1018 ( .A0(n565), .A1(n564), .A2(n567), .B0(n563), .Y(
Raw_mant_SGF[8]) );
AOI22X1TS U1019 ( .A0(n912), .A1(n571), .B0(n573), .B1(n649), .Y(n570) );
NAND2X1TS U1020 ( .A(DmP_mant_SFG_SWR[9]), .B(n944), .Y(n572) );
OAI21XLTS U1021 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n944), .B0(n572), .Y(n569)
);
NOR2X1TS U1022 ( .A(DmP_mant_SFG_SWR[10]), .B(n976), .Y(n576) );
AOI222X4TS U1023 ( .A0(n573), .A1(n944), .B0(n573), .B1(n975), .C0(n944),
.C1(n975), .Y(n579) );
AOI22X1TS U1024 ( .A0(n912), .A1(n577), .B0(n579), .B1(n649), .Y(n575) );
OAI31X1TS U1025 ( .A0(n576), .A1(n575), .A2(n578), .B0(n574), .Y(
Raw_mant_SGF[10]) );
AOI22X1TS U1026 ( .A0(n912), .A1(n617), .B0(n619), .B1(n649), .Y(n581) );
NAND2X1TS U1027 ( .A(DmP_mant_SFG_SWR[11]), .B(n945), .Y(n618) );
OAI21XLTS U1028 ( .A0(DmP_mant_SFG_SWR[11]), .A1(n945), .B0(n618), .Y(n580)
);
AOI22X1TS U1029 ( .A0(Data_array_SWR[44]), .A1(n468), .B0(Data_array_SWR[40]), .B1(n420), .Y(n583) );
AOI22X1TS U1030 ( .A0(n418), .A1(Data_array_SWR[36]), .B0(Data_array_SWR[32]), .B1(n417), .Y(n582) );
AOI21X1TS U1031 ( .A0(left_right_SHT2), .A1(n596), .B0(n473), .Y(n585) );
OAI21X1TS U1032 ( .A0(n598), .A1(n466), .B0(n585), .Y(sftr_odat_SHT2_SWR[19]) );
OAI21X1TS U1033 ( .A0(n588), .A1(n1019), .B0(n587), .Y(n586) );
OAI21X1TS U1034 ( .A0(n588), .A1(n964), .B0(n587), .Y(n589) );
AOI22X1TS U1035 ( .A0(n468), .A1(Data_array_SWR[42]), .B0(n419), .B1(
Data_array_SWR[38]), .Y(n591) );
AOI22X1TS U1036 ( .A0(n418), .A1(Data_array_SWR[34]), .B0(n416), .B1(
Data_array_SWR[30]), .Y(n590) );
OAI211X1TS U1037 ( .A0(n605), .A1(n994), .B0(n591), .C0(n590), .Y(n607) );
AOI21X1TS U1038 ( .A0(left_right_SHT2), .A1(n607), .B0(n473), .Y(n592) );
OAI21X1TS U1039 ( .A0(n610), .A1(n466), .B0(n592), .Y(sftr_odat_SHT2_SWR[21]) );
AOI22X1TS U1040 ( .A0(n468), .A1(Data_array_SWR[43]), .B0(n419), .B1(
Data_array_SWR[39]), .Y(n594) );
AOI22X1TS U1041 ( .A0(n418), .A1(Data_array_SWR[35]), .B0(n416), .B1(
Data_array_SWR[31]), .Y(n593) );
OAI211X1TS U1042 ( .A0(n610), .A1(n994), .B0(n594), .C0(n593), .Y(n603) );
AOI21X1TS U1043 ( .A0(n608), .A1(n603), .B0(n606), .Y(n595) );
OAI21X1TS U1044 ( .A0(n605), .A1(n510), .B0(n595), .Y(sftr_odat_SHT2_SWR[5])
);
AOI21X1TS U1045 ( .A0(n405), .A1(n596), .B0(n606), .Y(n597) );
OAI21X1TS U1046 ( .A0(n598), .A1(n510), .B0(n597), .Y(sftr_odat_SHT2_SWR[6])
);
AOI22X1TS U1047 ( .A0(n468), .A1(Data_array_SWR[45]), .B0(n420), .B1(
Data_array_SWR[41]), .Y(n600) );
AOI22X1TS U1048 ( .A0(n418), .A1(Data_array_SWR[37]), .B0(n417), .B1(
Data_array_SWR[33]), .Y(n599) );
AOI21X1TS U1049 ( .A0(n394), .A1(n611), .B0(n606), .Y(n602) );
OAI21X1TS U1050 ( .A0(n614), .A1(n510), .B0(n602), .Y(sftr_odat_SHT2_SWR[7])
);
AOI21X1TS U1051 ( .A0(n406), .A1(n603), .B0(n473), .Y(n604) );
OAI21X1TS U1052 ( .A0(n605), .A1(n466), .B0(n604), .Y(sftr_odat_SHT2_SWR[20]) );
AOI21X1TS U1053 ( .A0(n394), .A1(n607), .B0(n606), .Y(n609) );
OAI21X1TS U1054 ( .A0(n610), .A1(n510), .B0(n609), .Y(sftr_odat_SHT2_SWR[4])
);
AOI21X1TS U1055 ( .A0(left_right_SHT2), .A1(n611), .B0(n473), .Y(n613) );
OAI21X1TS U1056 ( .A0(n614), .A1(n466), .B0(n613), .Y(sftr_odat_SHT2_SWR[18]) );
NOR2BX1TS U1057 ( .AN(LZD_output_NRM2_EW[3]), .B(ADD_OVRFLW_NRM2), .Y(n615)
);
XOR2X1TS U1058 ( .A(n946), .B(n615), .Y(DP_OP_15J180_122_6956_n15) );
NOR2BX1TS U1059 ( .AN(LZD_output_NRM2_EW[4]), .B(ADD_OVRFLW_NRM2), .Y(n616)
);
XOR2X1TS U1060 ( .A(n946), .B(n616), .Y(DP_OP_15J180_122_6956_n14) );
NOR2X1TS U1061 ( .A(DmP_mant_SFG_SWR[12]), .B(n979), .Y(n622) );
AOI222X4TS U1062 ( .A0(n619), .A1(n945), .B0(n619), .B1(n977), .C0(n945),
.C1(n977), .Y(n625) );
AOI22X1TS U1063 ( .A0(n393), .A1(n623), .B0(n625), .B1(n649), .Y(n621) );
OAI31X1TS U1064 ( .A0(n622), .A1(n621), .A2(n624), .B0(n620), .Y(
Raw_mant_SGF[12]) );
AOI22X1TS U1065 ( .A0(n393), .A1(n628), .B0(n630), .B1(n649), .Y(n627) );
NAND2X1TS U1066 ( .A(DmP_mant_SFG_SWR[13]), .B(n947), .Y(n629) );
OAI21XLTS U1067 ( .A0(DmP_mant_SFG_SWR[13]), .A1(n947), .B0(n629), .Y(n626)
);
NOR2X1TS U1068 ( .A(DmP_mant_SFG_SWR[14]), .B(n984), .Y(n633) );
AOI222X4TS U1069 ( .A0(n630), .A1(n947), .B0(n630), .B1(n981), .C0(n947),
.C1(n981), .Y(n636) );
AOI22X1TS U1070 ( .A0(n393), .A1(n634), .B0(n636), .B1(n649), .Y(n632) );
OAI31X1TS U1071 ( .A0(n633), .A1(n632), .A2(n635), .B0(n631), .Y(
Raw_mant_SGF[14]) );
NOR2X1TS U1072 ( .A(DmP_mant_SFG_SWR[16]), .B(n991), .Y(n639) );
NAND2X1TS U1073 ( .A(DmP_mant_SFG_SWR[15]), .B(n948), .Y(n893) );
AOI222X4TS U1074 ( .A0(n891), .A1(n948), .B0(n891), .B1(n985), .C0(n948),
.C1(n985), .Y(n642) );
AOI22X1TS U1075 ( .A0(n393), .A1(n640), .B0(n642), .B1(n649), .Y(n638) );
OAI31X1TS U1076 ( .A0(n639), .A1(n638), .A2(n641), .B0(n637), .Y(
Raw_mant_SGF[16]) );
NOR2X1TS U1077 ( .A(DmP_mant_SFG_SWR[18]), .B(n993), .Y(n645) );
NAND2X1TS U1078 ( .A(DmP_mant_SFG_SWR[17]), .B(n990), .Y(n744) );
AOI222X4TS U1079 ( .A0(n742), .A1(n990), .B0(n742), .B1(n397), .C0(n990),
.C1(n397), .Y(n648) );
AOI22X1TS U1080 ( .A0(n393), .A1(n646), .B0(n648), .B1(n1091), .Y(n644) );
OAI31X1TS U1081 ( .A0(n645), .A1(n644), .A2(n647), .B0(n643), .Y(
Raw_mant_SGF[18]) );
NOR2X1TS U1082 ( .A(DmP_mant_SFG_SWR[20]), .B(n998), .Y(n652) );
NAND2X1TS U1083 ( .A(DmP_mant_SFG_SWR[19]), .B(n997), .Y(n775) );
AOI222X4TS U1084 ( .A0(n773), .A1(n997), .B0(n773), .B1(n398), .C0(n997),
.C1(n398), .Y(n656) );
AOI22X1TS U1085 ( .A0(n393), .A1(n654), .B0(n656), .B1(n649), .Y(n651) );
OAI31X1TS U1086 ( .A0(n652), .A1(n651), .A2(n655), .B0(n650), .Y(
Raw_mant_SGF[20]) );
AOI221X4TS U1087 ( .A0(Raw_mant_NRM_SWR[0]), .A1(n1090), .B0(
Raw_mant_NRM_SWR[25]), .B1(n663), .C0(n682), .Y(n932) );
AOI22X2TS U1088 ( .A0(n1090), .A1(LZD_raw_out_EWR[1]), .B0(
Shift_amount_SHT1_EWR[1]), .B1(n682), .Y(n665) );
OAI22X2TS U1089 ( .A0(Shift_reg_FLAGS_7[1]), .A1(Shift_amount_SHT1_EWR[0]),
.B0(LZD_raw_out_EWR[0]), .B1(n663), .Y(n660) );
NOR2X1TS U1090 ( .A(DmP_mant_SFG_SWR[22]), .B(n1012), .Y(n659) );
NAND2X1TS U1091 ( .A(DmP_mant_SFG_SWR[21]), .B(n960), .Y(n898) );
AOI222X4TS U1092 ( .A0(n896), .A1(n960), .B0(n896), .B1(n1013), .C0(n960),
.C1(n1013), .Y(n817) );
AOI22X1TS U1093 ( .A0(n393), .A1(n901), .B0(n817), .B1(n916), .Y(n658) );
CLKAND2X2TS U1094 ( .A(DmP_mant_SFG_SWR[22]), .B(n1012), .Y(n902) );
OAI31X1TS U1095 ( .A0(n659), .A1(n658), .A2(n902), .B0(n657), .Y(
Raw_mant_SGF[22]) );
INVX2TS U1096 ( .A(n660), .Y(n664) );
AOI22X1TS U1097 ( .A0(n1090), .A1(Raw_mant_NRM_SWR[24]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n410), .Y(n711) );
INVX2TS U1098 ( .A(n697), .Y(n709) );
AOI22X1TS U1099 ( .A0(n1090), .A1(Raw_mant_NRM_SWR[25]), .B0(n705), .B1(n709), .Y(n661) );
AOI22X1TS U1100 ( .A0(n409), .A1(Raw_mant_NRM_SWR[22]), .B0(
DmP_mant_SHT1_SW[20]), .B1(n682), .Y(n662) );
INVX4TS U1101 ( .A(n663), .Y(n935) );
AOI222X4TS U1102 ( .A0(n934), .A1(DmP_mant_SHT1_SW[22]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n410), .C0(Raw_mant_NRM_SWR[1]), .C1(n935),
.Y(n929) );
AOI222X4TS U1103 ( .A0(n934), .A1(DmP_mant_SHT1_SW[21]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n410), .C0(n423), .C1(n935), .Y(n930) );
OAI22X1TS U1104 ( .A0(n929), .A1(n933), .B0(n930), .B1(n408), .Y(n667) );
AOI21X1TS U1105 ( .A0(n413), .A1(n738), .B0(n667), .Y(n668) );
AOI222X4TS U1106 ( .A0(n934), .A1(DmP_mant_SHT1_SW[13]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[10]), .C0(Raw_mant_NRM_SWR[15]), .C1(n409), .Y(n731)
);
AOI22X1TS U1107 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1090), .B0(
DmP_mant_SHT1_SW[12]), .B1(n682), .Y(n669) );
AOI222X4TS U1108 ( .A0(n934), .A1(DmP_mant_SHT1_SW[15]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[8]), .C0(Raw_mant_NRM_SWR[17]), .C1(n409), .Y(n718)
);
AOI222X4TS U1109 ( .A0(n934), .A1(DmP_mant_SHT1_SW[14]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[9]), .C0(Raw_mant_NRM_SWR[16]), .C1(n409), .Y(n723)
);
OAI22X1TS U1110 ( .A0(n718), .A1(n403), .B0(n723), .B1(n933), .Y(n670) );
AOI21X1TS U1111 ( .A0(n413), .A1(n733), .B0(n670), .Y(n671) );
AOI222X4TS U1112 ( .A0(n934), .A1(DmP_mant_SHT1_SW[17]), .B0(
Raw_mant_NRM_SWR[19]), .B1(n410), .C0(Raw_mant_NRM_SWR[6]), .C1(n935),
.Y(n719) );
AOI22X1TS U1113 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1090), .B0(
DmP_mant_SHT1_SW[16]), .B1(n682), .Y(n672) );
AOI222X4TS U1114 ( .A0(n934), .A1(DmP_mant_SHT1_SW[19]), .B0(
Raw_mant_NRM_SWR[21]), .B1(n410), .C0(n422), .C1(n935), .Y(n736) );
AOI222X4TS U1115 ( .A0(n934), .A1(DmP_mant_SHT1_SW[18]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n410), .C0(Raw_mant_NRM_SWR[5]), .C1(n935),
.Y(n741) );
OAI22X1TS U1116 ( .A0(n736), .A1(n404), .B0(n741), .B1(n933), .Y(n673) );
AOI21X1TS U1117 ( .A0(n413), .A1(n721), .B0(n673), .Y(n674) );
AOI222X4TS U1118 ( .A0(n934), .A1(DmP_mant_SHT1_SW[9]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n410), .C0(Raw_mant_NRM_SWR[14]), .C1(n935),
.Y(n713) );
AOI22X1TS U1119 ( .A0(n409), .A1(Raw_mant_NRM_SWR[10]), .B0(
DmP_mant_SHT1_SW[8]), .B1(n682), .Y(n675) );
AOI222X4TS U1120 ( .A0(n934), .A1(DmP_mant_SHT1_SW[11]), .B0(n935), .B1(
Raw_mant_NRM_SWR[12]), .C0(Raw_mant_NRM_SWR[13]), .C1(n409), .Y(n730)
);
AOI222X4TS U1121 ( .A0(n934), .A1(DmP_mant_SHT1_SW[10]), .B0(
Raw_mant_NRM_SWR[12]), .B1(n409), .C0(Raw_mant_NRM_SWR[13]), .C1(n935),
.Y(n735) );
OAI22X1TS U1122 ( .A0(n730), .A1(n404), .B0(n735), .B1(n933), .Y(n676) );
AOI21X1TS U1123 ( .A0(n413), .A1(n715), .B0(n676), .Y(n677) );
AOI222X4TS U1124 ( .A0(n682), .A1(DmP_mant_SHT1_SW[5]), .B0(n1090), .B1(
Raw_mant_NRM_SWR[18]), .C0(Raw_mant_NRM_SWR[7]), .C1(n409), .Y(n725)
);
AOI22X1TS U1125 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1090), .B0(
DmP_mant_SHT1_SW[4]), .B1(n682), .Y(n678) );
AOI222X4TS U1126 ( .A0(n682), .A1(DmP_mant_SHT1_SW[7]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n410), .C0(Raw_mant_NRM_SWR[16]), .C1(n935),
.Y(n712) );
AOI222X4TS U1127 ( .A0(n934), .A1(DmP_mant_SHT1_SW[6]), .B0(
Raw_mant_NRM_SWR[8]), .B1(n410), .C0(Raw_mant_NRM_SWR[17]), .C1(n935),
.Y(n717) );
OAI22X1TS U1128 ( .A0(n712), .A1(n403), .B0(n717), .B1(n933), .Y(n680) );
AOI21X1TS U1129 ( .A0(n413), .A1(n727), .B0(n680), .Y(n681) );
AOI222X4TS U1130 ( .A0(n682), .A1(DmP_mant_SHT1_SW[3]), .B0(n935), .B1(
Raw_mant_NRM_SWR[20]), .C0(Raw_mant_NRM_SWR[5]), .C1(n409), .Y(n724)
);
AOI222X4TS U1131 ( .A0(n682), .A1(DmP_mant_SHT1_SW[2]), .B0(n935), .B1(
Raw_mant_NRM_SWR[21]), .C0(n422), .C1(n409), .Y(n729) );
OAI22X1TS U1132 ( .A0(n724), .A1(n404), .B0(n729), .B1(n933), .Y(n683) );
AOI21X1TS U1133 ( .A0(n666), .A1(n709), .B0(n683), .Y(n684) );
OAI22X1TS U1134 ( .A0(n929), .A1(n404), .B0(n930), .B1(n933), .Y(n685) );
AOI21X1TS U1135 ( .A0(n666), .A1(n738), .B0(n685), .Y(n686) );
OAI22X1TS U1136 ( .A0(n741), .A1(n404), .B0(n719), .B1(n933), .Y(n687) );
AOI21X1TS U1137 ( .A0(n666), .A1(n721), .B0(n687), .Y(n688) );
OAI22X1TS U1138 ( .A0(n717), .A1(n403), .B0(n725), .B1(n933), .Y(n689) );
AOI21X1TS U1139 ( .A0(n666), .A1(n727), .B0(n689), .Y(n690) );
OAI22X1TS U1140 ( .A0(n723), .A1(n403), .B0(n731), .B1(n933), .Y(n691) );
AOI21X1TS U1141 ( .A0(n666), .A1(n733), .B0(n691), .Y(n692) );
OAI22X1TS U1142 ( .A0(n735), .A1(n403), .B0(n713), .B1(n933), .Y(n693) );
AOI21X1TS U1143 ( .A0(n666), .A1(n715), .B0(n693), .Y(n694) );
OAI22X1TS U1144 ( .A0(n724), .A1(n424), .B0(n729), .B1(n408), .Y(n695) );
AOI21X1TS U1145 ( .A0(n705), .A1(n727), .B0(n695), .Y(n696) );
OAI22X1TS U1146 ( .A0(n736), .A1(n933), .B0(n741), .B1(n407), .Y(n698) );
AOI21X1TS U1147 ( .A0(n705), .A1(n738), .B0(n698), .Y(n699) );
OAI22X1TS U1148 ( .A0(n718), .A1(n424), .B0(n723), .B1(n408), .Y(n700) );
AOI21X1TS U1149 ( .A0(n705), .A1(n721), .B0(n700), .Y(n701) );
OAI22X1TS U1150 ( .A0(n730), .A1(n424), .B0(n735), .B1(n407), .Y(n702) );
AOI21X1TS U1151 ( .A0(n705), .A1(n733), .B0(n702), .Y(n703) );
OAI22X1TS U1152 ( .A0(n712), .A1(n424), .B0(n717), .B1(n407), .Y(n704) );
AOI21X1TS U1153 ( .A0(n705), .A1(n715), .B0(n704), .Y(n706) );
OAI22X1TS U1154 ( .A0(n729), .A1(n404), .B0(n707), .B1(n408), .Y(n708) );
AOI21X1TS U1155 ( .A0(n739), .A1(n709), .B0(n708), .Y(n710) );
OAI22X1TS U1156 ( .A0(n713), .A1(n403), .B0(n712), .B1(n407), .Y(n714) );
AOI21X1TS U1157 ( .A0(n739), .A1(n715), .B0(n714), .Y(n716) );
OAI22X1TS U1158 ( .A0(n719), .A1(n404), .B0(n718), .B1(n408), .Y(n720) );
AOI21X1TS U1159 ( .A0(n739), .A1(n721), .B0(n720), .Y(n722) );
OAI22X1TS U1160 ( .A0(n725), .A1(n403), .B0(n724), .B1(n407), .Y(n726) );
AOI21X1TS U1161 ( .A0(n739), .A1(n727), .B0(n726), .Y(n728) );
OAI22X1TS U1162 ( .A0(n731), .A1(n403), .B0(n730), .B1(n407), .Y(n732) );
AOI21X1TS U1163 ( .A0(n739), .A1(n733), .B0(n732), .Y(n734) );
OAI22X1TS U1164 ( .A0(n930), .A1(n404), .B0(n736), .B1(n408), .Y(n737) );
AOI21X1TS U1165 ( .A0(n739), .A1(n738), .B0(n737), .Y(n740) );
AOI22X1TS U1166 ( .A0(n393), .A1(n743), .B0(n742), .B1(n1091), .Y(n746) );
OAI21XLTS U1167 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n990), .B0(n744), .Y(n745)
);
OAI22X1TS U1168 ( .A0(n750), .A1(n749), .B0(n748), .B1(n762), .Y(n751) );
AOI21X1TS U1169 ( .A0(n752), .A1(Raw_mant_NRM_SWR[3]), .B0(n751), .Y(n753)
);
OAI211X1TS U1170 ( .A0(n755), .A1(n1021), .B0(n754), .C0(n753), .Y(
LZD_raw_out_EWR[2]) );
NOR3X1TS U1171 ( .A(n423), .B(n772), .C(n982), .Y(n768) );
OAI211X1TS U1172 ( .A0(n763), .A1(n762), .B0(n761), .C0(n760), .Y(
LZD_raw_out_EWR[3]) );
OAI31X1TS U1173 ( .A0(n766), .A1(Raw_mant_NRM_SWR[10]), .A2(n765), .B0(n764),
.Y(n767) );
AOI211X1TS U1174 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n769), .B0(n768), .C0(n767),
.Y(n770) );
OAI211X1TS U1175 ( .A0(n1052), .A1(n772), .B0(n771), .C0(n770), .Y(
LZD_raw_out_EWR[4]) );
AOI22X1TS U1176 ( .A0(n393), .A1(n774), .B0(n773), .B1(n916), .Y(n777) );
OAI21XLTS U1177 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n997), .B0(n775), .Y(n776)
);
NOR2BX1TS U1178 ( .AN(LZD_output_NRM2_EW[2]), .B(ADD_OVRFLW_NRM2), .Y(n778)
);
XOR2X1TS U1179 ( .A(n946), .B(n778), .Y(DP_OP_15J180_122_6956_n16) );
NOR2BX1TS U1180 ( .AN(LZD_output_NRM2_EW[1]), .B(ADD_OVRFLW_NRM2), .Y(n779)
);
XOR2X1TS U1181 ( .A(n946), .B(n779), .Y(DP_OP_15J180_122_6956_n17) );
XOR2X1TS U1182 ( .A(n946), .B(n780), .Y(DP_OP_15J180_122_6956_n18) );
NOR2BX1TS U1183 ( .AN(exp_rslt_NRM2_EW1[7]), .B(
array_comparators_GTComparator_N0), .Y(formatted_number_W[30]) );
XOR2XLTS U1184 ( .A(DMP_EXP_EWSW[27]), .B(DmP_EXP_EWSW[27]), .Y(n781) );
XOR2XLTS U1185 ( .A(intadd_428_n1), .B(n781), .Y(Shift_amount_EXP_EW[4]) );
AOI22X1TS U1186 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n936), .B1(n940), .Y(n1094)
);
XNOR2X1TS U1187 ( .A(add_subt), .B(Data_Y[31]), .Y(n1054) );
XNOR2X1TS U1188 ( .A(intDX_EWSW[31]), .B(n1092), .Y(OP_FLAG_INIT) );
AOI22X1TS U1189 ( .A0(intDX_EWSW[23]), .A1(intDY_EWSW[23]), .B0(n963), .B1(
n1011), .Y(n788) );
AOI22X1TS U1190 ( .A0(n952), .A1(intDY_EWSW[15]), .B0(n996), .B1(
intDY_EWSW[13]), .Y(n782) );
OAI221XLTS U1191 ( .A0(n952), .A1(intDY_EWSW[15]), .B0(n996), .B1(
intDY_EWSW[13]), .C0(n782), .Y(n787) );
AOI22X1TS U1192 ( .A0(n1002), .A1(intDY_EWSW[10]), .B0(n400), .B1(
intDY_EWSW[2]), .Y(n783) );
AOI22X1TS U1193 ( .A0(n954), .A1(intDY_EWSW[9]), .B0(n1006), .B1(
intDY_EWSW[11]), .Y(n784) );
OAI221XLTS U1194 ( .A0(n954), .A1(intDY_EWSW[9]), .B0(n1006), .B1(
intDY_EWSW[11]), .C0(n784), .Y(n785) );
NOR4X1TS U1195 ( .A(n788), .B(n787), .C(n786), .D(n785), .Y(n816) );
AOI22X1TS U1196 ( .A0(n1057), .A1(intDY_EWSW[7]), .B0(n1008), .B1(
intDY_EWSW[14]), .Y(n789) );
AOI22X1TS U1197 ( .A0(n1055), .A1(intDY_EWSW[5]), .B0(n1056), .B1(
intDY_EWSW[4]), .Y(n790) );
OAI221XLTS U1198 ( .A0(n1055), .A1(intDY_EWSW[5]), .B0(n1056), .B1(
intDY_EWSW[4]), .C0(n790), .Y(n795) );
AOI22X1TS U1199 ( .A0(n951), .A1(intDY_EWSW[3]), .B0(n1010), .B1(
intDY_EWSW[26]), .Y(n791) );
AOI22X1TS U1200 ( .A0(n1000), .A1(intDY_EWSW[1]), .B0(n401), .B1(
intDY_EWSW[0]), .Y(n792) );
OAI221XLTS U1201 ( .A0(n1000), .A1(intDY_EWSW[1]), .B0(n401), .B1(
intDY_EWSW[0]), .C0(n792), .Y(n793) );
NOR4X1TS U1202 ( .A(n796), .B(n795), .C(n794), .D(n793), .Y(n815) );
AOI22X1TS U1203 ( .A0(n427), .A1(intDY_EWSW[28]), .B0(n1005), .B1(
intDY_EWSW[6]), .Y(n797) );
AOI22X1TS U1204 ( .A0(n955), .A1(intDY_EWSW[18]), .B0(n1014), .B1(
intDY_EWSW[29]), .Y(n798) );
OAI221XLTS U1205 ( .A0(n955), .A1(intDY_EWSW[18]), .B0(n1014), .B1(
intDY_EWSW[29]), .C0(n798), .Y(n803) );
AOI22X1TS U1206 ( .A0(n958), .A1(intDY_EWSW[27]), .B0(n1009), .B1(
intDY_EWSW[19]), .Y(n799) );
AOI22X1TS U1207 ( .A0(n1004), .A1(intDY_EWSW[25]), .B0(n959), .B1(
intDY_EWSW[24]), .Y(n800) );
OAI221XLTS U1208 ( .A0(n1004), .A1(intDY_EWSW[25]), .B0(n959), .B1(
intDY_EWSW[24]), .C0(n800), .Y(n801) );
NOR4X1TS U1209 ( .A(n804), .B(n803), .C(n802), .D(n801), .Y(n814) );
AOI22X1TS U1210 ( .A0(n956), .A1(intDY_EWSW[20]), .B0(n1015), .B1(
intDY_EWSW[30]), .Y(n805) );
AOI22X1TS U1211 ( .A0(n1001), .A1(intDY_EWSW[8]), .B0(n953), .B1(
intDY_EWSW[21]), .Y(n806) );
OAI221XLTS U1212 ( .A0(n1001), .A1(intDY_EWSW[8]), .B0(n953), .B1(
intDY_EWSW[21]), .C0(n806), .Y(n811) );
AOI22X1TS U1213 ( .A0(n1003), .A1(intDY_EWSW[17]), .B0(n1018), .B1(
intDY_EWSW[16]), .Y(n807) );
AOI22X1TS U1214 ( .A0(n957), .A1(intDY_EWSW[22]), .B0(n1007), .B1(
intDY_EWSW[12]), .Y(n808) );
OAI221XLTS U1215 ( .A0(n957), .A1(intDY_EWSW[22]), .B0(n1007), .B1(
intDY_EWSW[12]), .C0(n808), .Y(n809) );
NOR4X1TS U1216 ( .A(n812), .B(n811), .C(n810), .D(n809), .Y(n813) );
NAND4XLTS U1217 ( .A(n816), .B(n815), .C(n814), .D(n813), .Y(n884) );
NOR2BX1TS U1218 ( .AN(OP_FLAG_INIT), .B(n884), .Y(ZERO_FLAG_INIT) );
NOR2BX1TS U1219 ( .AN(Shift_reg_FLAGS_7[3]), .B(n412), .Y(n_21_net_) );
AOI222X4TS U1220 ( .A0(n903), .A1(n962), .B0(n903), .B1(n1020), .C0(n962),
.C1(n1020), .Y(n908) );
AOI21X1TS U1221 ( .A0(n913), .A1(n429), .B0(n912), .Y(ADD_OVRFLW_SGF) );
NOR2X1TS U1222 ( .A(n1045), .B(intDX_EWSW[25]), .Y(n878) );
AOI22X1TS U1223 ( .A0(intDX_EWSW[25]), .A1(n1045), .B0(intDX_EWSW[24]), .B1(
n818), .Y(n822) );
OAI21X1TS U1224 ( .A0(intDX_EWSW[26]), .A1(n1050), .B0(n819), .Y(n879) );
NOR2X1TS U1225 ( .A(n995), .B(intDX_EWSW[30]), .Y(n826) );
NOR2X1TS U1226 ( .A(n950), .B(intDX_EWSW[29]), .Y(n823) );
AOI211X1TS U1227 ( .A0(intDY_EWSW[28]), .A1(n824), .B0(n826), .C0(n823), .Y(
n877) );
NOR3X1TS U1228 ( .A(n824), .B(n823), .C(intDY_EWSW[28]), .Y(n825) );
AOI2BB2X1TS U1229 ( .B0(n828), .B1(n877), .A0N(n827), .A1N(n826), .Y(n883)
);
NOR2X1TS U1230 ( .A(n1043), .B(intDX_EWSW[17]), .Y(n864) );
NOR2X1TS U1231 ( .A(n1046), .B(intDX_EWSW[11]), .Y(n843) );
AOI21X1TS U1232 ( .A0(intDY_EWSW[10]), .A1(n1002), .B0(n843), .Y(n848) );
OAI2BB1X1TS U1233 ( .A0N(n1055), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n829) );
OAI22X1TS U1234 ( .A0(intDY_EWSW[4]), .A1(n829), .B0(n1055), .B1(
intDY_EWSW[5]), .Y(n840) );
OAI2BB1X1TS U1235 ( .A0N(n1057), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n830) );
OAI22X1TS U1236 ( .A0(intDY_EWSW[6]), .A1(n830), .B0(n1057), .B1(
intDY_EWSW[7]), .Y(n839) );
OAI2BB2XLTS U1237 ( .B0(intDY_EWSW[0]), .B1(n831), .A0N(intDX_EWSW[1]),
.A1N(n1047), .Y(n833) );
AOI222X1TS U1238 ( .A0(intDY_EWSW[4]), .A1(n1056), .B0(n836), .B1(n835),
.C0(intDY_EWSW[5]), .C1(n1055), .Y(n838) );
AOI22X1TS U1239 ( .A0(intDY_EWSW[7]), .A1(n1057), .B0(intDY_EWSW[6]), .B1(
n1005), .Y(n837) );
OAI32X1TS U1240 ( .A0(n840), .A1(n839), .A2(n838), .B0(n837), .B1(n839), .Y(
n858) );
OA22X1TS U1241 ( .A0(n967), .A1(intDX_EWSW[14]), .B0(n1049), .B1(
intDX_EWSW[15]), .Y(n855) );
OAI2BB2XLTS U1242 ( .B0(intDY_EWSW[12]), .B1(n842), .A0N(intDX_EWSW[13]),
.A1N(n1032), .Y(n854) );
AOI22X1TS U1243 ( .A0(intDX_EWSW[11]), .A1(n1046), .B0(intDX_EWSW[10]), .B1(
n844), .Y(n850) );
AOI21X1TS U1244 ( .A0(n847), .A1(n846), .B0(n857), .Y(n849) );
OAI2BB2XLTS U1245 ( .B0(n850), .B1(n857), .A0N(n849), .A1N(n848), .Y(n853)
);
OAI2BB2XLTS U1246 ( .B0(intDY_EWSW[14]), .B1(n851), .A0N(intDX_EWSW[15]),
.A1N(n1049), .Y(n852) );
AOI211X1TS U1247 ( .A0(n855), .A1(n854), .B0(n853), .C0(n852), .Y(n856) );
OAI31X1TS U1248 ( .A0(n859), .A1(n858), .A2(n857), .B0(n856), .Y(n862) );
OA22X1TS U1249 ( .A0(n1036), .A1(intDX_EWSW[22]), .B0(n963), .B1(
intDX_EWSW[23]), .Y(n875) );
OAI21X1TS U1250 ( .A0(intDX_EWSW[18]), .A1(n1044), .B0(n866), .Y(n870) );
AOI211X1TS U1251 ( .A0(intDY_EWSW[16]), .A1(n1018), .B0(n869), .C0(n870),
.Y(n861) );
OAI2BB2XLTS U1252 ( .B0(intDY_EWSW[20]), .B1(n863), .A0N(intDX_EWSW[21]),
.A1N(n1033), .Y(n874) );
AOI22X1TS U1253 ( .A0(intDX_EWSW[17]), .A1(n1043), .B0(intDX_EWSW[16]), .B1(
n865), .Y(n868) );
AOI32X1TS U1254 ( .A0(n1044), .A1(n866), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n966), .Y(n867) );
OAI32X1TS U1255 ( .A0(n870), .A1(n869), .A2(n868), .B0(n867), .B1(n869), .Y(
n873) );
OAI2BB2XLTS U1256 ( .B0(intDY_EWSW[22]), .B1(n871), .A0N(intDX_EWSW[23]),
.A1N(n963), .Y(n872) );
AOI211X1TS U1257 ( .A0(n875), .A1(n874), .B0(n873), .C0(n872), .Y(n881) );
NAND4BBX1TS U1258 ( .AN(n879), .BN(n878), .C(n877), .D(n876), .Y(n880) );
AOI32X1TS U1259 ( .A0(n883), .A1(n882), .A2(n881), .B0(n880), .B1(n883), .Y(
n918) );
AOI21X1TS U1260 ( .A0(n884), .A1(n927), .B0(intDX_EWSW[31]), .Y(n885) );
AOI21X1TS U1261 ( .A0(n1092), .A1(n928), .B0(n885), .Y(SIGN_FLAG_INIT) );
NAND2X1TS U1262 ( .A(N59), .B(n912), .Y(n886) );
XNOR2X1TS U1263 ( .A(n886), .B(N60), .Y(Raw_mant_SGF[1]) );
OAI21XLTS U1264 ( .A0(DMP_SFG[0]), .A1(DmP_mant_SFG_SWR[2]), .B0(n887), .Y(
n890) );
NAND2X1TS U1265 ( .A(n888), .B(n912), .Y(n889) );
XOR2XLTS U1266 ( .A(n890), .B(n889), .Y(Raw_mant_SGF[2]) );
AOI22X1TS U1267 ( .A0(n393), .A1(n892), .B0(n891), .B1(n1091), .Y(n895) );
AOI22X1TS U1268 ( .A0(n393), .A1(n897), .B0(n896), .B1(n1091), .Y(n900) );
OAI22X1TS U1269 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1012), .B0(n902), .B1(n901), .Y(n906) );
AOI22X1TS U1270 ( .A0(n393), .A1(n906), .B0(n903), .B1(n1091), .Y(n905) );
NAND2X1TS U1271 ( .A(DmP_mant_SFG_SWR[23]), .B(n962), .Y(n907) );
OAI21XLTS U1272 ( .A0(DmP_mant_SFG_SWR[23]), .A1(n962), .B0(n907), .Y(n904)
);
NOR2X1TS U1273 ( .A(DmP_mant_SFG_SWR[24]), .B(n1023), .Y(n915) );
AOI21X1TS U1274 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1023), .B0(n915), .Y(n910)
);
AOI22X1TS U1275 ( .A0(DMP_SFG[21]), .A1(n1020), .B0(n907), .B1(n906), .Y(
n911) );
AOI22X1TS U1276 ( .A0(n393), .A1(n911), .B0(n908), .B1(n916), .Y(n909) );
AOI21X1TS U1277 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n1023), .B0(n911), .Y(n914)
);
BUFX3TS U1278 ( .A(n924), .Y(n920) );
BUFX3TS U1279 ( .A(n920), .Y(n919) );
AOI22X1TS U1280 ( .A0(n919), .A1(n1051), .B0(n401), .B1(n923), .Y(
DmP_INIT_EWSW[0]) );
AOI22X1TS U1281 ( .A0(n919), .A1(n1047), .B0(n1000), .B1(n928), .Y(
DmP_INIT_EWSW[1]) );
AOI22X1TS U1282 ( .A0(n919), .A1(n1034), .B0(n400), .B1(n923), .Y(
DmP_INIT_EWSW[2]) );
AOI22X1TS U1283 ( .A0(n919), .A1(n1048), .B0(n951), .B1(n928), .Y(
DmP_INIT_EWSW[3]) );
AOI22X1TS U1284 ( .A0(n919), .A1(n1029), .B0(n1056), .B1(n928), .Y(
DmP_INIT_EWSW[4]) );
AOI22X1TS U1285 ( .A0(n919), .A1(n1026), .B0(n1055), .B1(n927), .Y(
DmP_INIT_EWSW[5]) );
AOI22X1TS U1286 ( .A0(n919), .A1(n1027), .B0(n1005), .B1(n923), .Y(
DmP_INIT_EWSW[6]) );
AOI22X1TS U1287 ( .A0(n919), .A1(n1025), .B0(n1057), .B1(n923), .Y(
DmP_INIT_EWSW[7]) );
AOI22X1TS U1288 ( .A0(n919), .A1(n1042), .B0(n1001), .B1(n928), .Y(
DmP_INIT_EWSW[8]) );
AOI22X1TS U1289 ( .A0(n919), .A1(n1037), .B0(n954), .B1(n928), .Y(
DmP_INIT_EWSW[9]) );
AOI22X1TS U1290 ( .A0(n920), .A1(n1030), .B0(n1002), .B1(n923), .Y(
DmP_INIT_EWSW[10]) );
AOI22X1TS U1291 ( .A0(n920), .A1(n1046), .B0(n1006), .B1(n923), .Y(
DmP_INIT_EWSW[11]) );
AOI22X1TS U1292 ( .A0(n920), .A1(n1039), .B0(n1007), .B1(n928), .Y(
DmP_INIT_EWSW[12]) );
AOI22X1TS U1293 ( .A0(n920), .A1(n1032), .B0(n996), .B1(n928), .Y(
DmP_INIT_EWSW[13]) );
AOI22X1TS U1294 ( .A0(n920), .A1(n967), .B0(n1008), .B1(n923), .Y(
DmP_INIT_EWSW[14]) );
AOI22X1TS U1295 ( .A0(n920), .A1(n1049), .B0(n952), .B1(n923), .Y(
DmP_INIT_EWSW[15]) );
AOI22X1TS U1296 ( .A0(n920), .A1(n1028), .B0(n1018), .B1(n928), .Y(
DmP_INIT_EWSW[16]) );
AOI22X1TS U1297 ( .A0(n920), .A1(n1043), .B0(n1003), .B1(n923), .Y(
DmP_INIT_EWSW[17]) );
AOI22X1TS U1298 ( .A0(n920), .A1(n1044), .B0(n955), .B1(n928), .Y(
DmP_INIT_EWSW[18]) );
AOI22X1TS U1299 ( .A0(n920), .A1(n966), .B0(n1009), .B1(n928), .Y(
DmP_INIT_EWSW[19]) );
AOI22X1TS U1300 ( .A0(n924), .A1(n1035), .B0(n956), .B1(n923), .Y(
DmP_INIT_EWSW[20]) );
AOI22X1TS U1301 ( .A0(n924), .A1(n1033), .B0(n953), .B1(n923), .Y(
DmP_INIT_EWSW[21]) );
AOI22X1TS U1302 ( .A0(n924), .A1(n1036), .B0(n957), .B1(n927), .Y(
DmP_INIT_EWSW[22]) );
AOI22X1TS U1303 ( .A0(n924), .A1(n963), .B0(n1011), .B1(n927), .Y(
DmP_INIT_EWSW[23]) );
AOI22X1TS U1304 ( .A0(n924), .A1(n1031), .B0(n959), .B1(n928), .Y(
DmP_INIT_EWSW[24]) );
AOI22X1TS U1305 ( .A0(n924), .A1(n1045), .B0(n1004), .B1(n927), .Y(
DmP_INIT_EWSW[25]) );
AOI22X1TS U1306 ( .A0(n924), .A1(n1050), .B0(n1010), .B1(n927), .Y(
DmP_INIT_EWSW[26]) );
AOI22X1TS U1307 ( .A0(n924), .A1(n1038), .B0(n958), .B1(n923), .Y(
DmP_INIT_EWSW[27]) );
AOI22X1TS U1308 ( .A0(n924), .A1(n401), .B0(n1051), .B1(n927), .Y(
DMP_INIT_EWSW[0]) );
AOI22X1TS U1309 ( .A0(n924), .A1(n1000), .B0(n1047), .B1(n927), .Y(
DMP_INIT_EWSW[1]) );
BUFX3TS U1310 ( .A(n920), .Y(n921) );
AOI22X1TS U1311 ( .A0(n921), .A1(n400), .B0(n1034), .B1(n928), .Y(
DMP_INIT_EWSW[2]) );
INVX2TS U1312 ( .A(n924), .Y(n922) );
AOI22X1TS U1313 ( .A0(n921), .A1(n951), .B0(n1048), .B1(n922), .Y(
DMP_INIT_EWSW[3]) );
AOI22X1TS U1314 ( .A0(n921), .A1(n1056), .B0(n1029), .B1(n922), .Y(
DMP_INIT_EWSW[4]) );
AOI22X1TS U1315 ( .A0(n921), .A1(n1055), .B0(n1026), .B1(n922), .Y(
DMP_INIT_EWSW[5]) );
AOI22X1TS U1316 ( .A0(n921), .A1(n1005), .B0(n1027), .B1(n922), .Y(
DMP_INIT_EWSW[6]) );
AOI22X1TS U1317 ( .A0(n921), .A1(n1057), .B0(n1025), .B1(n922), .Y(
DMP_INIT_EWSW[7]) );
AOI22X1TS U1318 ( .A0(n921), .A1(n1001), .B0(n1042), .B1(n922), .Y(
DMP_INIT_EWSW[8]) );
AOI22X1TS U1319 ( .A0(n921), .A1(n954), .B0(n1037), .B1(n925), .Y(
DMP_INIT_EWSW[9]) );
AOI22X1TS U1320 ( .A0(n921), .A1(n1002), .B0(n1030), .B1(n925), .Y(
DMP_INIT_EWSW[10]) );
AOI22X1TS U1321 ( .A0(n921), .A1(n1006), .B0(n1046), .B1(n925), .Y(
DMP_INIT_EWSW[11]) );
AOI22X1TS U1322 ( .A0(n926), .A1(n1007), .B0(n1039), .B1(n922), .Y(
DMP_INIT_EWSW[12]) );
AOI22X1TS U1323 ( .A0(n926), .A1(n996), .B0(n1032), .B1(n922), .Y(
DMP_INIT_EWSW[13]) );
AOI22X1TS U1324 ( .A0(n926), .A1(n1008), .B0(n967), .B1(n922), .Y(
DMP_INIT_EWSW[14]) );
AOI22X1TS U1325 ( .A0(n926), .A1(n952), .B0(n1049), .B1(n925), .Y(
DMP_INIT_EWSW[15]) );
AOI22X1TS U1326 ( .A0(n926), .A1(n1018), .B0(n1028), .B1(n925), .Y(
DMP_INIT_EWSW[16]) );
AOI22X1TS U1327 ( .A0(n926), .A1(n1003), .B0(n1043), .B1(n927), .Y(
DMP_INIT_EWSW[17]) );
AOI22X1TS U1328 ( .A0(n926), .A1(n955), .B0(n1044), .B1(n925), .Y(
DMP_INIT_EWSW[18]) );
AOI22X1TS U1329 ( .A0(n926), .A1(n1009), .B0(n966), .B1(n925), .Y(
DMP_INIT_EWSW[19]) );
AOI22X1TS U1330 ( .A0(n926), .A1(n956), .B0(n1035), .B1(n925), .Y(
DMP_INIT_EWSW[20]) );
AOI22X1TS U1331 ( .A0(n926), .A1(n953), .B0(n1033), .B1(n925), .Y(
DMP_INIT_EWSW[21]) );
AOI22X1TS U1332 ( .A0(n926), .A1(n957), .B0(n1036), .B1(n925), .Y(
DMP_INIT_EWSW[22]) );
AOI22X1TS U1333 ( .A0(n924), .A1(n1011), .B0(n963), .B1(n925), .Y(
DMP_INIT_EWSW[23]) );
AOI22X1TS U1334 ( .A0(n926), .A1(n959), .B0(n1031), .B1(n925), .Y(
DMP_INIT_EWSW[24]) );
AOI22X1TS U1335 ( .A0(n926), .A1(n1004), .B0(n1045), .B1(n925), .Y(
DMP_INIT_EWSW[25]) );
AOI22X1TS U1336 ( .A0(n926), .A1(n1010), .B0(n1050), .B1(n925), .Y(
DMP_INIT_EWSW[26]) );
AOI22X1TS U1337 ( .A0(n926), .A1(n958), .B0(n1038), .B1(n925), .Y(
DMP_INIT_EWSW[27]) );
OAI2BB2XLTS U1338 ( .B0(n927), .B1(n824), .A0N(n927), .A1N(intDY_EWSW[28]),
.Y(DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U1339 ( .B0(n927), .B1(n1014), .A0N(n927), .A1N(intDY_EWSW[29]),
.Y(DMP_INIT_EWSW[29]) );
OAI2BB2XLTS U1340 ( .B0(n927), .B1(n1015), .A0N(n927), .A1N(intDY_EWSW[30]),
.Y(DMP_INIT_EWSW[30]) );
OAI22X1TS U1341 ( .A0(n929), .A1(n653), .B0(n932), .B1(n408), .Y(
Data_array_SWR[24]) );
OAI222X1TS U1342 ( .A0(n424), .A1(n932), .B0(n653), .B1(n930), .C0(n408),
.C1(n929), .Y(Data_array_SWR[23]) );
INVX2TS U1344 ( .A(n936), .Y(n939) );
AOI22X1TS U1345 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n965), .B0(
beg_OP), .B1(n940), .Y(n938) );
OAI22X1TS U1346 ( .A0(n939), .A1(n938), .B0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B1(n937), .Y(n389) );
NAND2BXLTS U1347 ( .AN(busy), .B(n1093), .Y(n_7_net_) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpu_syn_constraints_clk20.tcl_GATED_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
module SHDScheduler #(parameter DNA_DATA_WIDTH = 128, NUM_CLUSTERS = 8) (
input clk,
input rst,
//Receiver Interface
output dna_rd_en,
input[DNA_DATA_WIDTH - 1:0] dna_data_in,
input dna_valid_in,
//Cluster Interface
input shd_clk,
input[NUM_CLUSTERS - 1:0] shd_rd_en_in,
output[NUM_CLUSTERS - 1:0] shd_valid_out,
output[NUM_CLUSTERS*DNA_DATA_WIDTH - 1:0] shd_dna_data_out
);
reg[DNA_DATA_WIDTH - 1:0] dna_data_r;
reg dna_valid_r = 0;
wire accept_dna_data;
reg dna_issued;
//Register incoming dna data
always@(posedge clk) begin
if(rst) begin
dna_data_r <= 0;
dna_valid_r <= 0;
end
else begin
if(accept_dna_data) begin
dna_data_r <= dna_data_in;
dna_valid_r <= dna_valid_in;
end
end
end
assign accept_dna_data = !dna_valid_r || dna_issued;
assign dna_rd_en = accept_dna_data;
//SHD FIFOs
wire[NUM_CLUSTERS - 1:0] shd_fifo_full, shd_fifo_empty;
reg[NUM_CLUSTERS - 1:0] shd_fifo_wr_en;
genvar i;
generate
for (i=0; i < NUM_CLUSTERS; i=i+1) begin
shd_fifo i_shd_fifo (
.rst(rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(shd_clk), // input wire rd_clk
.din(dna_data_r), // input wire [255 : 0] din
.wr_en(shd_fifo_wr_en[i]), // input wire wr_en
.rd_en(shd_rd_en_in[i]), // input wire rd_en
.dout(shd_dna_data_out[i*DNA_DATA_WIDTH +: DNA_DATA_WIDTH]), // output wire [255 : 0] dout
.full(shd_fifo_full[i]), // output wire full
.empty(shd_fifo_empty[i]) // output wire empty
);
end
endgenerate
assign shd_valid_out = ~shd_fifo_empty;
// --- ARBITRATION LOGIC ---
//SHD PE iterator
parameter CLUSTER_BITS = $clog2(NUM_CLUSTERS);
reg[CLUSTER_BITS - 1:0] cluster_iterator = 0;
wire advance_cluster_it;
always@(posedge clk) begin
if(rst) begin
cluster_iterator <= 0;
end
else begin
if(advance_cluster_it) begin
cluster_iterator <= cluster_iterator + 1'b1;
end
end
end
assign advance_cluster_it = dna_issued; //We want to preserve the order. Looking for non-full FIFOs may break it
//Issue to current FIFO if not full
always@* begin
shd_fifo_wr_en = {NUM_CLUSTERS{1'b0}};
dna_issued = 1'b0;
if(dna_valid_r && ~shd_fifo_full[cluster_iterator]) begin
shd_fifo_wr_en[cluster_iterator] = 1'b1;
dna_issued = 1'b1;
end
end
// --- END - ARBITRATION LOGIC ---
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3_SYMBOL_V
`define SKY130_FD_SC_HD__NOR3_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_2_V
`define SKY130_FD_SC_MS__A211O_2_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a211o_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A211O_PP_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_PP_SYMBOL_V
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the DATA : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module clock_reduce(
input clk,
input reset_n,
input [2:0] clock_sel,
output clk_reduced,
output clk_100_reduced
);
reg [10:0] counter;
reg [10:0] counter_100;
assign clk_reduced = clk_reduced_p | clk_reduced_n;
assign clk_100_reduced = clk_100_reduced_p | clk_100_reduced_n;
reg clk_reduced_i;
reg clk_100_reduced_i;
reg clk_reduced_p;
reg clk_100_reduced_p;
reg clk_reduced_n;
reg clk_100_reduced_n;
always@(*)
begin
clk_reduced_p = 1'b0;
if(clk_reduced_i)
begin
clk_reduced_p = 1'b1;
end
end
always@(*)
begin
clk_reduced_n = 1'b1;
if(!clk_reduced_i)
begin
clk_reduced_n = 1'b0;
end
end
always@(*)
begin
clk_100_reduced_p = 1'b0;
if(clk_100_reduced_i)
begin
clk_100_reduced_p = 1'b1;
end
end
always@(*)
begin
clk_100_reduced_n = 1'b1;
if(!clk_100_reduced_i)
begin
clk_100_reduced_n = 1'b0;
end
end
always@(posedge clk)
begin
if(!reset_n)
begin
counter <= 11'd0;
counter_100 <= 11'd0;
clk_reduced_i <= 1'b0;
clk_100_reduced_i <= 1'b0;
end
else
begin
case(clock_sel)
3'd0://2mhz - 500 ns
begin
if(counter >=11'd0 && counter <=11'd99 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd100 && counter <=11'd199 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd1://5mhz
begin
if(counter >=11'd0 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd40 && counter <=11'd79 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd2://10mhz
begin
if(counter >=11'd0 && counter <=11'd19 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd20 && counter <=11'd39 )
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd3://50mhz
begin
if(counter >=11'd0 && counter <=11'd3 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd4 && counter <=11'd7)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd4://100mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd4)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd5://150mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter >=11'd2 && counter <=11'd3)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd6://200mhz
begin
if(counter >=11'd0 && counter <=11'd1 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter == 11'd2)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
3'd7://300mhz
begin
if(counter ==11'd0 )
begin
clk_reduced_i <= 1'b1;
counter <= counter + 11'd1;
end
else if(counter ==11'd1)
begin
clk_reduced_i <= 1'b0;
counter <= counter + 11'd1;
end
else
begin
clk_reduced_i <= 1'b1;
counter <= 11'd0;
end
end
endcase
if(counter_100 >=11'd0 && counter_100 <=11'd1 )
begin
clk_100_reduced_i <= 1'b1;
counter_100 <= counter_100 + 11'd1;
end
else if(counter_100 >=11'd2 && counter_100 <=11'd4)
begin
clk_100_reduced_i <= 1'b0;
counter_100 <= counter_100 + 11'd1;
end
else
begin
clk_100_reduced_i <= 1'b1;
counter_100 <= 11'd0;
end
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module tri_intersect_data_array_ram (addr0, ce0, d0, we0, q0, addr1, ce1, d1, we1, q1, clk);
parameter DWIDTH = 576;
parameter AWIDTH = 1;
parameter MEM_SIZE = 2;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
input[DWIDTH-1:0] d1;
input we1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
if (we1)
begin
ram[addr1] <= d1;
q1 <= d1;
end
else
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module tri_intersect_data_array(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1);
parameter DataWidth = 32'd576;
parameter AddressRange = 32'd2;
parameter AddressWidth = 32'd1;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
input we1;
input[DataWidth - 1:0] d1;
output[DataWidth - 1:0] q1;
tri_intersect_data_array_ram tri_intersect_data_array_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.d1( d1 ),
.we1( we1 ),
.q1( q1 ));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's mem2reg alignment ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Two versions of Memory to register data alignment. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_mem2reg.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/03/28 19:14:10 lampret
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:46 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_mem2reg(addr, lsu_op, memdata, regdata);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [1:0] addr;
input [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
input [width-1:0] memdata;
output [width-1:0] regdata;
//
// In the past faster implementation of mem2reg (today probably slower)
//
`ifdef OR1200_IMPL_MEM2REG2
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO 4'b0000
reg [7:0] regdata_hh;
reg [7:0] regdata_hl;
reg [7:0] regdata_lh;
reg [7:0] regdata_ll;
reg [width-1:0] aligned;
reg [3:0] sel_byte0, sel_byte1,
sel_byte2, sel_byte3;
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
//
// Byte select 0
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b01x, 2'b00}: // lbz/lbs 0
sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
{3'b01x, 2'b01}, // lbz/lbs 1
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
{3'b01x, 2'b10}: // lbz/lbs 2
sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
default: // all other cases
sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
endcase
end
//
// Byte select 1
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}: // lbz
sel_byte1 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}: // lbs 0
sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}: // lbs 2
sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
default: // all other cases
sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
endcase
end
//
// Byte select 2
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte2 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
endcase
end
//
// Byte select 3
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte3 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
endcase
end
//
// Byte 0
//
always @(sel_byte0 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte0) // synopsys parallel_case infer_mux
`else
case(sel_byte0) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte0) // synopsys parallel_case
`else
case(sel_byte0) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_BYTE0: begin
regdata_ll = memdata[7:0];
end
`OR1200_M2R_BYTE1: begin
regdata_ll = memdata[15:8];
end
`OR1200_M2R_BYTE2: begin
regdata_ll = memdata[23:16];
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_BYTE3: begin
`endif
regdata_ll = memdata[31:24];
end
endcase
end
//
// Byte 1
//
always @(sel_byte1 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte1) // synopsys parallel_case infer_mux
`else
case(sel_byte1) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte1) // synopsys parallel_case
`else
case(sel_byte1) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_lh = 8'h00;
end
`OR1200_M2R_BYTE1: begin
regdata_lh = memdata[15:8];
end
`OR1200_M2R_BYTE3: begin
regdata_lh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_lh = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_lh = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_lh = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_lh = {8{memdata[31]}};
end
endcase
end
//
// Byte 2
//
always @(sel_byte2 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte2) // synopsys parallel_case infer_mux
`else
case(sel_byte2) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte2) // synopsys parallel_case
`else
case(sel_byte2) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_hl = 8'h00;
end
`OR1200_M2R_BYTE2: begin
regdata_hl = memdata[23:16];
end
`OR1200_M2R_EXTB0: begin
regdata_hl = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_hl = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_hl = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_hl = {8{memdata[31]}};
end
endcase
end
//
// Byte 3
//
always @(sel_byte3 or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
`ifdef OR1200_CASE_DEFAULT
case(sel_byte3) // synopsys parallel_case infer_mux
`else
case(sel_byte3) // synopsys full_case parallel_case infer_mux
`endif
`else
`ifdef OR1200_CASE_DEFAULT
case(sel_byte3) // synopsys parallel_case
`else
case(sel_byte3) // synopsys full_case parallel_case
`endif
`endif
`OR1200_M2R_ZERO: begin
regdata_hh = 8'h00;
end
`OR1200_M2R_BYTE3: begin
regdata_hh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_hh = {8{memdata[7]}};
end
`OR1200_M2R_EXTB1: begin
regdata_hh = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_hh = {8{memdata[23]}};
end
`ifdef OR1200_CASE_DEFAULT
`OR1200_M2R_EXTB3: begin
`else
`OR1200_M2R_EXTB3: begin
`endif
regdata_hh = {8{memdata[31]}};
end
endcase
end
`else
//
// Straightforward implementation of mem2reg
//
reg [width-1:0] regdata;
reg [width-1:0] aligned;
//
// Alignment
//
always @(addr or memdata) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(addr) // synopsys parallel_case infer_mux
`else
case(addr) // synopsys parallel_case
`endif
2'b00:
aligned = memdata;
2'b01:
aligned = {memdata[23:0], 8'b0};
2'b10:
aligned = {memdata[15:0], 16'b0};
2'b11:
aligned = {memdata[7:0], 24'b0};
endcase
end
//
// Bytes
//
always @(lsu_op or aligned) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(lsu_op) // synopsys parallel_case infer_mux
`else
case(lsu_op) // synopsys parallel_case
`endif
`OR1200_LSUOP_LBZ: begin
regdata[7:0] = aligned[31:24];
regdata[31:8] = 24'b0;
end
`OR1200_LSUOP_LBS: begin
regdata[7:0] = aligned[31:24];
regdata[31:8] = {24{aligned[31]}};
end
`OR1200_LSUOP_LHZ: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = 16'b0;
end
`OR1200_LSUOP_LHS: begin
regdata[15:0] = aligned[31:16];
regdata[31:16] = {16{aligned[31]}};
end
default:
regdata = aligned;
endcase
end
`endif
endmodule
|
// Copyright (c) 2013-2015, Intel Corporation
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of Intel Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
module spl_pt_mem #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8
) (
input wire clk,
// port 0, read/write
input wire we0,
input wire re0,
input wire [ADDR_WIDTH-1:0] addr0,
input wire [DATA_WIDTH-1:0] din0,
output reg [DATA_WIDTH-1:0] dout0,
// port 1, read only
input wire re1,
input wire [ADDR_WIDTH-1:0] addr1,
output reg [DATA_WIDTH-1:0] dout1
);
`ifdef VENDOR_XILINX
(* ram_extract = "yes", ram_style = "block" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`else
(* ramstyle = "AUTO, no_rw_check" *)
reg [DATA_WIDTH-1:0] mem[0:2**ADDR_WIDTH-1];
`endif
always @(posedge clk) begin
if (we0)
mem[addr0] <= din0;
if (re0)
dout0 <= mem[addr0];
if (re1)
dout1 <= mem[addr1];
end
endmodule
|
`timescale 1ns / 1ps
module mpemu_t;
`define DATALEN 32
reg [31:0] testdata_a [`DATALEN-1:0];
reg [31:0] testdata_b [`DATALEN-1:0];
reg [31:0] testdata_p [`DATALEN-1:0];
// ins
reg clk;
reg [23:0] mpcand_i;
reg [23:0] mplier_i;
// outs
wire [27:0] mprod_o;
mpemu uut(
.clk(clk),
.mpcand_i(mpcand_i), .mplier_i(mplier_i),
.mprod_o(mprod_o));
parameter TCLK = 41.0; // ~40.69ns (24.576Mhz)
integer i;
initial begin
$dumpfile("mpemu_t.lxt");
$dumpvars(0, mpemu_t);
$readmemh("testdata/gen/mp_a.hex", testdata_a);
$readmemh("testdata/gen/mp_b.hex", testdata_b);
$readmemh("testdata/gen/mp_p.hex", testdata_p);
clk = 1'b0;
#TCLK;
mpcand_i = 24'h100000;
mplier_i = 24'h123456;
#TCLK;
mpcand_i = 24'h123456;
mplier_i = 24'h100000;
#TCLK;
mpcand_i = 24'hffffff; // -1
mplier_i = 24'h080000;
#TCLK;
for (i = 0; i < `DATALEN; i = i + 1) begin
mpcand_i = testdata_a[i];
mplier_i = testdata_b[i];
#TCLK;
end
#(TCLK*8);
$finish(2);
end
always #(TCLK/2) clk = ~clk;
integer i2;
always begin
#(TCLK*6);
$display("%h should be %h", mprod_o, 28'h02468ac);
#TCLK;
$display("%h should be %h", mprod_o, 28'h02468ac);
#TCLK;
$display("%h should be %h", mprod_o, 28'hfffffff);
#TCLK;
for (i2 = 0; i2 < `DATALEN; i2 = i2 + 1) begin
$display("%h should be %h", mprod_o, testdata_p[i2][27:0]);
#TCLK;
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: tlu_mmu_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
/*
// Description: MMU Control - I & D.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module tlu_mmu_ctl ( /*AUTOARG*/
// Outputs
dmmu_any_sfsr_wr, dmmu_sfsr_wr_en_l, dmmu_sfar_wr_en_l,
immu_any_sfsr_wr, immu_sfsr_wr_en_l, immu_tsb_rd_en, tlu_tte_tag_g,
tlu_dtlb_rw_index_vld_g, tlu_dtlb_rw_index_g,
tlu_dtlb_data_rd_g, tlu_dtlb_tag_rd_g, tlu_itlb_rw_index_vld_g,
tlu_itlb_wr_vld_g, itlb_wr_vld_g, tlu_itlb_rw_index_g,
tlu_itlb_data_rd_g, tlu_itlb_tag_rd_g, tlu_idtsb_8k_ptr,
tlu_dtlb_invalidate_all_g, tlu_itlb_invalidate_all_g, tlu_slxa_thrd_sel,
tlu_lsu_ldxa_tid_w2, tlu_itlb_dmp_vld_g,
tlu_itlb_dmp_all_g, tlu_itlb_dmp_pctxt_g, tlu_itlb_dmp_actxt_g,
tlu_itlb_dmp_nctxt_g, tlu_dtlb_dmp_vld_g, tlu_dtlb_dmp_all_g,
tlu_dtlb_dmp_pctxt_g, tlu_dtlb_dmp_sctxt_g, tlu_dtlb_dmp_nctxt_g,
tlu_dtlb_dmp_actxt_g, tlu_idtlb_dmp_thrid_g, tlu_dmp_key_vld_g,
tlu_int_asi_load, tlu_int_asi_store, tlu_int_asi_thrid,
tlu_int_asi_vld, tlb_access_rst_l,
tlu_lsu_stxa_ack, tlu_lsu_stxa_ack_tid, mra_wr_ptr, mra_rd_ptr,
mra_wr_vld, mra_rd_vld, tag_access_wdata_sel,
tlu_admp_key_sel, mra_byte_wen,
tlu_tte_wr_pid_g, tlu_lsu_ldxa_async_data_vld, tlu_tte_real_g,
tlu_ldxa_l1mx1_sel, tlu_ldxa_l1mx2_sel, tlu_ldxa_l2mx1_sel,
lsu_ifu_inj_ack, tlu_tlb_tag_invrt_parity, tlu_tlb_data_invrt_parity,
tlu_sun4r_tte_g, so, lsu_exu_ldxa_m, tlu_lng_ltncy_en_l,
tlu_tag_access_ctxt_sel_m, tlu_tsb_rd_ps0_sel, tlu_tlb_access_en_l_d1,
// Inputs
ifu_lsu_ld_inst_e, ifu_lsu_st_inst_e, spu_tlu_rsrv_illgl_m,
lsu_tlu_dmmu_miss_g,
tlu_dtsb_split_w2, tlu_dtsb_size_w2, tlu_dtag_access_w2, tlu_itsb_split_w2,
tlu_itsb_size_w2, tlu_ctxt_cfg_w2, lsu_tlu_st_rs3_data_g,
lsu_tlu_st_rs3_data_b48_g, lsu_tlu_st_rs3_data_b12t0_g,
ifu_tlu_immu_miss_m, ifu_lsu_thrid_s,
ifu_lsu_alt_space_e, lsu_tlu_dtlb_done,
ifu_tlu_itlb_done, lsu_tlu_tlb_asi_state_m, lsu_tlu_tlb_ldst_va_m,
lsu_tlu_tlb_ld_inst_m, lsu_tlu_tlb_st_inst_m,
lsu_tlu_tlb_access_tid_m, dmmu_sfsr_trp_wr,
immu_sfsr_trp_wr, lsu_tlu_daccess_excptn_g,
lsu_tlu_daccess_prot_g,
lsu_pid_state0, lsu_pid_state1, lsu_pid_state2, lsu_pid_state3,
lsu_tlu_nucleus_ctxt_m, lsu_tlu_tte_pg_sz_g, ifu_lsu_error_inj,
ifu_tlu_alt_space_d, ifu_lsu_imm_asi_d,
ifu_lsu_memref_d, lsu_asi_reg0, lsu_asi_reg1, lsu_asi_reg2,
lsu_asi_reg3, exu_mmu_early_va_e, rclk, arst_l, grst_l,
si,se,ifu_tlu_flush_m,tlu_mmu_early_flush_pipe_w,lsu_mmu_early_flush_w,
tlu_tag_access_ctxt_g, tlu_lsu_tl_zero,
exu_tlu_va_oor_jl_ret_m, exu_tlu_va_oor_m, tlu_lsu_pstate_am, tlu_tsb_base_w2_d1,
lsu_mmu_flush_pipe_w, ifu_tlu_inst_vld_m, ifu_mmu_trap_m, ffu_tlu_ill_inst_m,
exu_lsu_priority_trap_m, sehold, rst_tri_en, tlu_itag_acc_sel_g, lsu_mmu_defr_trp_taken_g,
ifu_tlu_priv_violtn_m
) ;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
input ifu_lsu_ld_inst_e; // inst_is_load (src-decode)
input ifu_lsu_st_inst_e; // inst is store (src-decode)
input lsu_tlu_dmmu_miss_g ; // ld/st misses in dtlb.
input spu_tlu_rsrv_illgl_m ;
input tlu_itag_acc_sel_g ;
input lsu_mmu_defr_trp_taken_g ;
// The timing on these signals can be changed to any earlier stage.
// For both SPARC_HPV_EN and non-SPARC_HPV_EN - tsb,tag-access
// dtsb maps to ps0. itsb maps to ps1.
input [47:13] tlu_tsb_base_w2_d1 ;
//input [47:13] tlu_dtsb_base_w2 ;
input tlu_dtsb_split_w2 ;
input [3:0] tlu_dtsb_size_w2 ;
input [47:13] tlu_dtag_access_w2 ; // used to represent both i/d.
//input [47:13] tlu_itsb_base_w2 ;
input tlu_itsb_split_w2 ;
input [3:0] tlu_itsb_size_w2 ;
// For SPARC_HPV_EN - BEGIN
input [5:0] tlu_ctxt_cfg_w2 ; // i/d context zero/non-zero config.
//input tlu_tag_access_nctxt_g ;// tag-access contains nucleus context.
// For SPARC_HPV_EN - END
input [62:61] lsu_tlu_st_rs3_data_g ; // Page Size (1,0) bits of TTE
input lsu_tlu_st_rs3_data_b48_g ; // Page Size (2) bits of TTE
//input [2:0] lsu_tlu_st_rs3_data_b10t8_g ; // ps1 of ctxt-cfg
input [12:0] lsu_tlu_st_rs3_data_b12t0_g ;
//input [2:0] lsu_tlu_st_rs3_data_b2t0_g ; // sun4v tte size
input ifu_tlu_immu_miss_m ;
input [1:0] ifu_lsu_thrid_s ; // Thread id.
input ifu_lsu_alt_space_e ; // alt-space access
input lsu_tlu_dtlb_done ; // dtlb rd/wr/dmp complete
input ifu_tlu_itlb_done ; // itlb rd/wr/dmp complete
//input int_tlu_asi_data_vld ; // asi return vld for int blk
//input int_tlu_ldxa_illgl_va ; // int asi has illgl va
input [7:0] lsu_tlu_tlb_asi_state_m ;
input [10:0] lsu_tlu_tlb_ldst_va_m ;
input lsu_tlu_tlb_ld_inst_m ;
input lsu_tlu_tlb_st_inst_m ;
input [1:0] lsu_tlu_tlb_access_tid_m ;
input ifu_tlu_flush_m ;
input tlu_mmu_early_flush_pipe_w ;
input lsu_mmu_early_flush_w ;
input [3:0] dmmu_sfsr_trp_wr ;
input [3:0] immu_sfsr_trp_wr ;
//input tlu_inst_vld_m ; // qualified inst vld
input lsu_tlu_daccess_excptn_g ; // data access exception
input lsu_tlu_daccess_prot_g ;// data access protection
// obsolete with SPARC_HPV_EN !!!
//input lsu_tlu_asi_rd_unc ; // uncorrectable error for tlb rd
input [2:0] lsu_pid_state0 ; // pid thread0 ; global use
input [2:0] lsu_pid_state1 ; // pid thread1 ; global use
input [2:0] lsu_pid_state2 ; // pid thread2 ; global use
input [2:0] lsu_pid_state3 ; // pid thread3 ; global use
input lsu_tlu_nucleus_ctxt_m ;// access is nucleus context
input [2:0] lsu_tlu_tte_pg_sz_g ; // page-size of tte
input [3:0] ifu_lsu_error_inj ; // inject parity error into tlb
// BEGIN - MMU_ASI_RD_CHANGE
// !! early va required.
input ifu_tlu_alt_space_d ; // alt space access - new;_e exists
//input ifu_lsu_imm_asi_vld_d ; // imm asi is vld - current
input [8:0] ifu_lsu_imm_asi_d ; // imm asi - current
input ifu_lsu_memref_d; // ld/st - prefer ld_inst_e;
input [7:0] lsu_asi_reg0 ; // asi state - thread0
input [7:0] lsu_asi_reg1 ; // asi state - thread1
input [7:0] lsu_asi_reg2 ; // asi state - thread2
input [7:0] lsu_asi_reg3 ; // asi state - thread3
//input [1:0] ifu_tlu_thrid_d ; // thread id
input [7:0] exu_mmu_early_va_e; // early va from exu
// END - MMU_ASI_RD_CHANGE
input [12:0] tlu_tag_access_ctxt_g ;
input [3:0] tlu_lsu_tl_zero; // trap level is zero.
//input exu_tlu_ttype_vld_m; // exu src ttype vld
input exu_tlu_va_oor_jl_ret_m;
input exu_tlu_va_oor_m;
input [3:0] tlu_lsu_pstate_am;
input lsu_mmu_flush_pipe_w ;
input ifu_tlu_inst_vld_m ;
input ifu_mmu_trap_m ;
input ffu_tlu_ill_inst_m ;
input exu_lsu_priority_trap_m ; // fill/ue
input ifu_tlu_priv_violtn_m ;
input rclk ;
input arst_l, grst_l;
input si,se;
input sehold ;
input rst_tri_en ;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
output dmmu_any_sfsr_wr ;
output [3:0] dmmu_sfsr_wr_en_l ;
output [3:0] dmmu_sfar_wr_en_l ;
//output [3:0] dmmu_tsb_wr_en ;
//output [3:0] dmmu_tsb_rd_en ;
//output [3:0] dmmu_tag_access_wr_en ;
//output [3:0] dmmu_tag_access_rd_en ;
//output dmmu_tag_read_en ;
output immu_any_sfsr_wr ;
output [3:0] immu_sfsr_wr_en_l ;
//output [3:0] immu_tsb_wr_en ;
output [3:0] immu_tsb_rd_en ;
//output [3:0] immu_tag_access_wr_en ;
//output [3:0] immu_tag_access_rd_en ;
//output immu_tag_read_en ;
// tlb/itlb related control can potentially be
// made g-stage.
output [2:0] tlu_tte_tag_g ;
output tlu_dtlb_rw_index_vld_g ;
output [5:0] tlu_dtlb_rw_index_g ;
output tlu_dtlb_data_rd_g ;
output tlu_dtlb_tag_rd_g ;
output tlu_itlb_rw_index_vld_g ;
output tlu_itlb_wr_vld_g ;
output itlb_wr_vld_g ;
output [5:0] tlu_itlb_rw_index_g ;
output tlu_itlb_data_rd_g ;
output tlu_itlb_tag_rd_g ;
output [47:0] tlu_idtsb_8k_ptr ; // maps to ps0/ps1 ptr. require only 1.
output tlu_dtlb_invalidate_all_g ;
output tlu_itlb_invalidate_all_g ;
output [3:0] tlu_slxa_thrd_sel ;
output [1:0] tlu_lsu_ldxa_tid_w2 ;
output tlu_itlb_dmp_vld_g ;
output tlu_itlb_dmp_all_g ;
output tlu_itlb_dmp_pctxt_g ;
output tlu_itlb_dmp_actxt_g ;
output tlu_itlb_dmp_nctxt_g ;
output tlu_dtlb_dmp_vld_g ;
output tlu_dtlb_dmp_all_g ;
output tlu_dtlb_dmp_pctxt_g ;
output tlu_dtlb_dmp_sctxt_g ;
output tlu_dtlb_dmp_nctxt_g ;
output tlu_dtlb_dmp_actxt_g ;
output [1:0] tlu_idtlb_dmp_thrid_g ;
output [4:0] tlu_dmp_key_vld_g ;
output tlu_int_asi_load;
output tlu_int_asi_store;
output [1:0] tlu_int_asi_thrid;
output tlu_int_asi_vld;
//output tlb_access_en_l ;
output tlb_access_rst_l ;
output tlu_lsu_stxa_ack ; // write to tlb is complete.
output [1:0] tlu_lsu_stxa_ack_tid ;
output [3:0] mra_wr_ptr ; // wr ptr for mra
output [3:0] mra_rd_ptr ; // thrd id for rd.
output mra_wr_vld ; // write pointer vld
output mra_rd_vld ; // read vld
output [19:0] mra_byte_wen ;
output [2:0] tag_access_wdata_sel ;
output tlu_admp_key_sel ;
//output tlu_mmu_sync_data_excp_g ; // sync asi related data excp
//output tlu_lsu_dtlb_rd_unc ; // unc error for tlb rd
//output [3:0] tlu_dldxa_mx2_sel ; // obsolete for SPARC_HPV_EN
//output [2:0] tlu_dldxa_mx3_sel ; // obsolete for SPARC_HPV_EN
//output [2:0] tlu_dldxa_fmx_sel ; // obsolete for SPARC_HPV_EN
//output [3:0] tlu_ildxa_mx1_sel ; // obsolete for SPARC_HPV_EN
//output [2:0] tlu_ildxa_fmx_sel ; // obsolete for SPARC_HPV_EN
output [2:0] tlu_tte_wr_pid_g ; // thread selected pid
output tlu_lsu_ldxa_async_data_vld ; // tlu_lsu_ldxa_data_vld is for async op.
output tlu_tte_real_g ; // tte is real
output [3:0] tlu_ldxa_l1mx1_sel ; // mmu ldxa level1 mx1 sel
output [3:0] tlu_ldxa_l1mx2_sel ; // mmu ldxa level1 mx2 sel
output [2:0] tlu_ldxa_l2mx1_sel ; // mmu ldxa level2 mx1 sel
output [3:0] lsu_ifu_inj_ack ; // ack for tlb error injection.
output tlu_tlb_tag_invrt_parity ; // invert parity on write tag.
output tlu_tlb_data_invrt_parity ; // invert parity on write data.
output tlu_sun4r_tte_g ; // sun4r vs. sun4v tte.
output lsu_exu_ldxa_m ;
output tlu_lng_ltncy_en_l ;
output [2:0] tlu_tag_access_ctxt_sel_m ;
output tlu_tsb_rd_ps0_sel ;
output tlu_tlb_access_en_l_d1 ;
output so ;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
reg dmmu_invalidate_all_en_m ;
reg immu_invalidate_all_en_m ;
reg dmmu_decode_asi58_e ;
reg immu_decode_asi50_e ;
reg dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e ;
reg immu_8k_ptr_e,immu_64k_ptr_e;
reg dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e ;
reg dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e ;
reg dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e ;
reg immu_zctxt_ps0_tsb_e, immu_zctxt_ps1_tsb_e ;
reg immu_nzctxt_ps0_tsb_e, immu_nzctxt_ps1_tsb_e ;
reg immu_zctxt_cfg_e, immu_nzctxt_cfg_e ;
reg dmmu_data_in_en_m,dmmu_data_access_en_m;
reg dmmu_tag_read_en_m,dmmu_demap_en_m;
wire sehold_d1 ;
wire tlb_access_en_l ;
wire dmmu_sync_illgl_va_g ;
wire dmmu_async_supported_asi,dmmu_async_illgl_va_g ;
wire immu_sync_illgl_va_g ;
wire immu_async_supported_asi,immu_async_illgl_va_g ;
wire ld_inst_m,st_inst_m ;
wire ld_inst_g,st_inst_g ;
wire [3:0] tsb_size ;
wire tsb_split ;
//wire [47:13] tsb_base ;
wire [47:13] tag_access ;
/*wire tsb_sz_8k_b0_mx1_out,tsb_sz_8k_b1_mx1_out,tsb_sz_8k_b2_mx1_out,tsb_sz_8k_b3_mx1_out;
wire tsb_sz_8k_b4_mx1_out,tsb_sz_8k_b5_mx1_out,tsb_sz_8k_b6_mx1_out,tsb_sz_8k_b7_mx1_out;
wire tsb_sz_8k_b0_mx2_out,tsb_sz_8k_b1_mx2_out,tsb_sz_8k_b2_mx2_out,tsb_sz_8k_b3_mx2_out;
wire tsb_sz_8k_b4_mx2_out,tsb_sz_8k_b5_mx2_out,tsb_sz_8k_b6_mx2_out,tsb_sz_8k_b7_mx2_out;
wire tsb_sz_8k_b0_mx3_out,tsb_sz_8k_b1_mx3_out,tsb_sz_8k_b2_mx3_out,tsb_sz_8k_b3_mx3_out;
wire tsb_sz_8k_b4_mx3_out,tsb_sz_8k_b5_mx3_out,tsb_sz_8k_b6_mx3_out,tsb_sz_8k_b7_mx3_out;
wire tsb_sz_64k_b0_mx1_out,tsb_sz_64k_b1_mx1_out,tsb_sz_64k_b2_mx1_out,tsb_sz_64k_b3_mx1_out;
wire tsb_sz_64k_b4_mx1_out,tsb_sz_64k_b5_mx1_out,tsb_sz_64k_b6_mx1_out,tsb_sz_64k_b7_mx1_out;
wire tsb_sz_64k_b0_mx2_out,tsb_sz_64k_b1_mx2_out,tsb_sz_64k_b2_mx2_out,tsb_sz_64k_b3_mx2_out;
wire tsb_sz_64k_b4_mx2_out,tsb_sz_64k_b5_mx2_out,tsb_sz_64k_b6_mx2_out ;
wire tsb_sz_64k_b0_mx3_out,tsb_sz_64k_b1_mx3_out,tsb_sz_64k_b2_mx3_out,tsb_sz_64k_b3_mx3_out;
wire tsb_sz_64k_b4_mx3_out ;*/
wire dtlb_rw_index_vld_g,dtlb_wr_vld_g ;
wire dmmu_data_in_wr_en, dmmu_data_access_wr_en ;
wire dmmu_tag_read_rd_en, dmmu_data_access_rd_en ;
wire immu_data_in_wr_en, immu_data_access_wr_en ;
wire immu_data_access_rd_en, immu_tag_read_rd_en ;
wire itlb_rw_index_vld_g,itlb_wr_vld_g;
wire tlu_ldxa_data_vld ;
wire tlu_dldxa_data_vld ;
wire [1:0] thrid_d,thrid_e,thrid_m,thrid_g ;
wire thread0_sel_g, thread1_sel_g ;
wire thread2_sel_g, thread3_sel_g ;
wire alt_space_m, alt_space_g ;
wire immu_miss_g;
wire ddemap_by_page,ddemap_by_ctxt,ddemap_all;
wire idemap_by_page,idemap_by_ctxt,idemap_all;
wire demap_pctxt,demap_sctxt,demap_nctxt ;
//wire lsu_tlu_page_ebit_g ;
wire ddemap_vld, idemap_vld ;
wire [2:0] tlu_tte_tag_g ;
wire demap_resrv ;
wire itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend ;
wire dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend ;
wire tlb_access_en ;
wire tlb_access_rst ;
wire dmra_wr_g, imra_wr_g ;
wire dmmu_data_in_en, dmmu_data_access_en, dmmu_tag_read_en, dmmu_demap_en ;
wire immu_data_in_en, immu_data_access_en, immu_tag_read_en, immu_demap_en ;
wire immu_invalidate_all_en,dmmu_invalidate_all_en ;
wire tlb_wr_vld_g ;
wire tlb_admp_en, tlb_admp_rst, tlb_wr_rst ;
wire tlb_admp_mode,tlb_write_mode ;
wire tlb_ldst_inst_m ;
wire tlb_admp_mode_d1 ;
wire itlb_wr_vld_unmsked,dtlb_wr_vld_unmsked;
wire idemap_pend, ddemap_pend ;
wire itlb_tag_rd_en, dtlb_tag_rd_en ;
wire [3:0] dsfsr_asi_wr_en ;
wire [3:0] isfsr_asi_wr_en ;
wire [10:3] tlb_ldst_va_g ;
wire tlb_ld_inst_g,tlb_st_inst_g ;
wire tlb_ld_inst_unflushed,tlb_st_inst_unflushed ;
wire [1:0] tlb_access_tid_g ;
wire inst_vld_g ;
wire st_inst_unflushed, ld_inst_unflushed ;
wire imra_lng_lat_rd,dmra_lng_lat_rd ;
wire iside_mra_access_rd, iside_mra_access_wr ;
wire [1:0] mra_raccess_tid ;
//wire dmmu_sync_rd_only_asi_g ;
//wire immu_sync_rd_only_asi_g ;
wire dptr0_pg64k_en,dptr1_pg64k_en,dptr2_pg64k_en,dptr3_pg64k_en;
wire dptr0_pg64k_vld,dptr1_pg64k_vld,dptr2_pg64k_vld,dptr3_pg64k_vld;
//wire dmmu_direct_ptr_rd_en ;
wire tlu_dtlb_rd_done ;
wire dmmu_ctxt_cfg_en, immu_ctxt_cfg_en ;
//wire dmmu_ctxt_cfg_rd_en ;
wire dacc_prot_ps1_match ;
wire tacc_nctxt, itacc_nctxt, dtacc_nctxt ; // for in-pipe access
wire tacc_anctxt, itacc_anctxt, dtacc_anctxt ;// for async access
wire thread0_async_g,thread1_async_g,thread2_async_g ;
wire sun4r_tte_g ;
wire dmmu_decode_asi58_m, immu_decode_asi50_m ;
wire dmmu_zctxt_ps0_tsb_m, dmmu_zctxt_ps1_tsb_m,
dmmu_nzctxt_ps0_tsb_m, dmmu_nzctxt_ps1_tsb_m,
dmmu_zctxt_cfg_m, dmmu_nzctxt_cfg_m,
immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,
immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,
immu_zctxt_cfg_m, immu_nzctxt_cfg_m ;
wire dmmu_sync_fsr_en, dmmu_sync_far_en,
dmmu_zctxt_ps0_tsb_en, dmmu_zctxt_ps1_tsb_en,
dmmu_nzctxt_ps0_tsb_en, dmmu_nzctxt_ps1_tsb_en,
dmmu_zctxt_cfg_en, dmmu_nzctxt_cfg_en,
immu_sync_fsr_en,
immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,
immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,
immu_zctxt_cfg_en, immu_nzctxt_cfg_en ;
wire dmmu_tag_target_en_m,dmmu_tag_access_en_m;
wire immu_tag_target_en_m,immu_tag_access_en_m;
wire dmmu_tag_access_en;
wire immu_tag_access_en;
wire dmmu_8k_ptr_en_m,dmmu_64k_ptr_en_m,dmmu_direct_ptr_en_m ;
wire immu_8k_ptr_en_m,immu_64k_ptr_en_m ;
wire dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,
dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,
dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,
dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,
immu_sync_fsr_en_m,
immu_zctxt_ps0_tsb_en_m, immu_zctxt_ps1_tsb_en_m,
immu_nzctxt_ps0_tsb_en_m, immu_nzctxt_ps1_tsb_en_m,
immu_zctxt_cfg_en_m, immu_nzctxt_cfg_en_m ;
wire thread0_d,thread1_d,thread2_d,thread3_d;
wire thread0_e, thread1_e, thread2_e, thread3_e ;
wire [7:0] asi_state_d, asi_state_e ;
wire memref_e,memref_m ;
wire [7:0] early_va_m ;
wire idmra_rd_d ;
wire idmra_nzctxt_rd_d ;
wire idmra_fault_rd_d ;
wire dmmu_tsb_en_m, dmmu_ctxt_cfg_en_m ;
wire immu_tsb_en_m, immu_ctxt_cfg_en_m ;
wire tlu_ildxa_data_vld ;
wire dmmu_direct_8kptr_sel_g ; // direct ptr should select 8k ptr
wire dmmu_tsb_en ;
wire immu_tsb_en ;
wire mra_field1_en, mra_field2_en ;
wire mra_field3_en, mra_field4_en ;
//=========================================================================================
// RESET/CLK
//=========================================================================================
wire clk;
assign clk = rclk;
wire rst_l;
dffrl_async rstff(.din (grst_l),
.q (rst_l),
.clk (clk), .se(se), .si(), .so(),
.rst_l (arst_l));
//=========================================================================================
// Early Flush Generation
//=========================================================================================
wire ifu_tlu_flush_w ;
dff_s #(1) stg_w (
.din (ifu_tlu_flush_m),
.q (ifu_tlu_flush_w),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
wire local_flush_w ;
assign local_flush_w =
ifu_tlu_flush_w | // ifu flush
lsu_mmu_defr_trp_taken_g | // defr trp
tlu_mmu_early_flush_pipe_w | // tlu flush
lsu_mmu_early_flush_w ; // lsu early flush
wire flush_w_inst_vld_m ;
assign flush_w_inst_vld_m =
ifu_tlu_inst_vld_m &
~(lsu_mmu_flush_pipe_w & (thrid_m[1:0] == thrid_g[1:0])) ; // really lsu_flush_pipe_w
dff_s stgw_ivld (
.din (flush_w_inst_vld_m),
.q (inst_vld_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Bug 4183
wire priority_squash_m, priority_squash_g ;
assign priority_squash_m =
ifu_mmu_trap_m | ffu_tlu_ill_inst_m | exu_lsu_priority_trap_m | spu_tlu_rsrv_illgl_m ;
wire trp_vld_m,trp_vld_g ;
assign trp_vld_m = flush_w_inst_vld_m & ~priority_squash_m ;
dff_s #(2) sqshstgw (
.din ({priority_squash_m,trp_vld_m}),
.q ({priority_squash_g,trp_vld_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
//=========================================================================================
// Staging
//=========================================================================================
dff_s #(2) stg_d (
.din (ifu_lsu_thrid_s[1:0]),
.q (thrid_d[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(2) stg_e (
.din (thrid_d[1:0]),
.q (thrid_e[1:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(5) stg_m (
.din ({ifu_lsu_ld_inst_e,ifu_lsu_st_inst_e,
thrid_e[1:0],ifu_lsu_alt_space_e}),
.q ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(6) stg_g (
.din ({ld_inst_m,st_inst_m,thrid_m[1:0],alt_space_m,ifu_tlu_immu_miss_m}),
.q ({ld_inst_unflushed,st_inst_unflushed,thrid_g[1:0],alt_space_g,immu_miss_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// reads are terminated for illegal va case.
assign ld_inst_g = ld_inst_unflushed & inst_vld_g & ~local_flush_w ;
//assign ld_inst_g = ld_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) & ;
// writes are terminated for illegal va case.
assign st_inst_g = st_inst_unflushed & inst_vld_g & ~local_flush_w &
~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g) ;
//assign st_inst_g = st_inst_unflushed & inst_vld_g & ~(dmmu_sync_illgl_va_g | immu_sync_illgl_va_g);
assign thread0_sel_g = ~thrid_g[1] & ~thrid_g[0] ;
assign thread1_sel_g = ~thrid_g[1] & thrid_g[0] ;
assign thread2_sel_g = thrid_g[1] & ~thrid_g[0] ;
assign thread3_sel_g = thrid_g[1] & thrid_g[0] ;
assign tlu_slxa_thrd_sel[0] = ~thrid_m[1] & ~thrid_m[0] ;
assign tlu_slxa_thrd_sel[1] = ~thrid_m[1] & thrid_m[0] ;
assign tlu_slxa_thrd_sel[2] = thrid_m[1] & ~thrid_m[0] ;
assign tlu_slxa_thrd_sel[3] = thrid_m[1] & thrid_m[0] ;
/*dff stgivld_g (
.din (tlu_inst_vld_m),
.q (inst_vld_g),
.clk (clk),
.se (1'b0), .si (), .so ()
); */
//=========================================================================================
// ASI RD DP MUX SELECT
//=========================================================================================
// qualification with vld not required as this dp is used by synchronous ops only
// Need to be made non zero-hot in functional mode
// Decode of bits va[5:4] to distinguish reads.
wire va_54_eq_0,va_54_eq_1,va_54_eq_2,va_54_eq_3 ;
wire [2:0] ldxa_l1mx1_sel_d1 ;
assign va_54_eq_0 = (~early_va_m[5] & ~early_va_m[4]) ;
assign va_54_eq_1 = (~early_va_m[5] & early_va_m[4]) ;
assign va_54_eq_2 = ( early_va_m[5] & ~early_va_m[4]) ;
assign va_54_eq_3 = ( early_va_m[5] & early_va_m[4]) ;
// i/d tag-target
// Extend for MacroTest Control.
assign tlu_ldxa_l1mx1_sel[0] =
((((dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_0) & ~sehold_d1) | rst_tri_en) |
(ldxa_l1mx1_sel_d1[0] & sehold_d1) ;
assign tlu_ldxa_l1mx1_sel[1] =
((dmmu_zctxt_ps0_tsb_e | dmmu_nzctxt_ps0_tsb_e |
immu_zctxt_ps0_tsb_e | immu_nzctxt_ps0_tsb_e) & ~sehold_d1 & ~rst_tri_en) |
(ldxa_l1mx1_sel_d1[1] & sehold_d1) ;
assign tlu_ldxa_l1mx1_sel[2] =
((dmmu_zctxt_ps1_tsb_e | dmmu_nzctxt_ps1_tsb_e |
immu_zctxt_ps1_tsb_e | immu_nzctxt_ps1_tsb_e) & ~sehold_d1 & ~rst_tri_en) |
(ldxa_l1mx1_sel_d1[2] & sehold_d1) ;
// Extend flops to hold selects for MacroTest of MRA.
wire [2:0] ldxa_l1mx1_sel_out ;
dff_s #(3) l1mx1s_stgd1(
.din (tlu_ldxa_l1mx1_sel[2:0]),
.q (ldxa_l1mx1_sel_out[2:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// scan protection.
assign ldxa_l1mx1_sel_d1[0] = ldxa_l1mx1_sel_out[0] ;
assign ldxa_l1mx1_sel_d1[1] = ldxa_l1mx1_sel_out[1] & ~rst_tri_en ;
assign ldxa_l1mx1_sel_d1[2] = ldxa_l1mx1_sel_out[2] & ~rst_tri_en ;
wire sehold_out ;
dff_s #(1) seh_d1 (
.din (sehold),
.q (sehold_out),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign sehold_d1 = sehold_out & ~rst_tri_en ;
// i/d tag-access
assign tlu_ldxa_l1mx1_sel[3] = ~|tlu_ldxa_l1mx1_sel[2:1];
wire ldxa_l1mx1_sel3;
// * read timing change.
assign ldxa_l1mx1_sel3 =
(dmmu_decode_asi58_m | immu_decode_asi50_m) & va_54_eq_3 & ~rst_tri_en ;
// d sync-fsr
// * read timing change.
wire dmmu_sync_fsr_m_sel,dmmu_sync_far_m_sel,immu_sync_fsr_m_sel;
assign dmmu_sync_fsr_m_sel = (dmmu_decode_asi58_m & va_54_eq_1) | rst_tri_en ;
assign dmmu_sync_far_m_sel = (dmmu_decode_asi58_m & va_54_eq_2) & ~rst_tri_en ;
assign immu_sync_fsr_m_sel = (immu_decode_asi50_m & va_54_eq_1) & ~rst_tri_en ;
assign tlu_ldxa_l1mx2_sel[0] = dmmu_sync_fsr_m_sel ;
// d sync-far
// * read timing change.
assign tlu_ldxa_l1mx2_sel[1] = dmmu_sync_far_m_sel ;
// i sync-fsr
assign tlu_ldxa_l1mx2_sel[2] = immu_sync_fsr_m_sel ;
assign tlu_ldxa_l1mx2_sel[3] = ~|tlu_ldxa_l1mx2_sel[2:0];
wire ldxa_l1mx2_sel3;
assign ldxa_l1mx2_sel3 = (dmmu_zctxt_cfg_m | dmmu_nzctxt_cfg_m |
immu_zctxt_cfg_m | immu_nzctxt_cfg_m) & ~rst_tri_en ;
assign tlu_ldxa_l2mx1_sel[0] =
|{ldxa_l1mx1_sel3,ldxa_l1mx1_sel_d1[2:1],(tlu_ldxa_l1mx1_sel[0] & ~rst_tri_en)} ;
assign tlu_ldxa_l2mx1_sel[1] = |{ldxa_l1mx2_sel3,tlu_ldxa_l1mx2_sel[2:0]} ;
assign tlu_ldxa_l2mx1_sel[2] = ~|tlu_ldxa_l2mx1_sel[1:0];
//=========================================================================================
// MRA RD/WRITE
//=========================================================================================
wire [3:0] isfsr_trp_wr ;
wire flush_mmuasi_wr ;
assign flush_mmuasi_wr = ifu_tlu_flush_w | lsu_mmu_defr_trp_taken_g ; // Bug 5196
assign isfsr_trp_wr[0] = immu_sfsr_trp_wr[0] & ~flush_mmuasi_wr ;
assign isfsr_trp_wr[1] = immu_sfsr_trp_wr[1] & ~flush_mmuasi_wr ;
assign isfsr_trp_wr[2] = immu_sfsr_trp_wr[2] & ~flush_mmuasi_wr ;
assign isfsr_trp_wr[3] = immu_sfsr_trp_wr[3] & ~flush_mmuasi_wr ;
wire tag_access_nctxt_g ;
wire immu_miss_vld_g ;
assign immu_miss_vld_g = immu_miss_g & inst_vld_g ;
// fast-asi read takes precedence over long-latency rd. Can long-latency read get
// starved out ?? Assume memref_d is never x.
assign dmra_lng_lat_rd = ((dmmu_data_in_en | dmmu_data_access_en) & tlb_st_inst_g & ~ifu_lsu_memref_d) ;
assign imra_lng_lat_rd = ((immu_data_in_en | immu_data_access_en) & tlb_st_inst_g & ~ifu_lsu_memref_d) ;
//assign dmra_lng_lat_rd = ((dmmu_data_in_en | dmmu_data_access_en) & tlb_st_inst_g) ;
//assign imra_lng_lat_rd = ((immu_data_in_en | immu_data_access_en) & tlb_st_inst_g) ;
wire dmra_ldst,imra_ldst ;
assign dmra_ldst = dmmu_tag_access_en | dmmu_tsb_en | dmmu_ctxt_cfg_en ;
assign imra_ldst = immu_tag_access_en | immu_tsb_en | immu_ctxt_cfg_en ;
// sync_far_en no longer written/read
assign dmra_wr_g =
(dmra_ldst & st_inst_g) |
(lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g)
& trp_vld_g & ~flush_mmuasi_wr ;
//(lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g) & inst_vld_g ;
// Bug 4183
wire isfsr_trap ;
assign isfsr_trap = |isfsr_trp_wr[3:0] ;
assign imra_wr_g =
(imra_ldst & st_inst_g) |
//((immu_tag_access_en | immu_tsb_en | immu_ctxt_cfg_en) & st_inst_g) |
(immu_miss_vld_g & ~flush_mmuasi_wr) | isfsr_trap ;
wire dmra_rw_d ;
assign iside_mra_access_rd = ((~dmra_rw_d) & ~(imra_lng_lat_rd | dmra_lng_lat_rd)) | imra_lng_lat_rd ;
assign iside_mra_access_wr = imra_wr_g ;
assign mra_raccess_tid[1:0] = (dmra_lng_lat_rd | imra_lng_lat_rd) ? tlb_access_tid_g[1:0] : thrid_d[1:0] ;
wire idside_nzctxt_accwr_early_m,idside_nzctxt_accwr_early_g ;
assign idside_nzctxt_accwr_early_m =
((dmmu_nzctxt_cfg_en_m | immu_nzctxt_cfg_en_m |
dmmu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps0_tsb_en_m |
dmmu_nzctxt_ps1_tsb_en_m | immu_nzctxt_ps1_tsb_en_m) & st_inst_m) ; // tsb/cfg asi wr
dff_s ctacc_stgg (
.din (idside_nzctxt_accwr_early_m),
.q (idside_nzctxt_accwr_early_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//wire idside_nzctxt_access ;
wire idside_nzctxt_access_rd,idside_nzctxt_access_wr ;
wire st_wr_g ;
assign idside_nzctxt_access_wr =
((dmmu_tag_access_en | immu_tag_access_en) // tag-access asi write
& st_inst_unflushed & ~tag_access_nctxt_g) |
((lsu_tlu_daccess_excptn_g | lsu_tlu_daccess_prot_g | lsu_tlu_dmmu_miss_g |
immu_miss_g | (isfsr_trap)) // tag-access exception write
& inst_vld_g & ~tag_access_nctxt_g) |
(idside_nzctxt_accwr_early_g & st_wr_g) ; // Bug 4828
//((dmmu_nzctxt_cfg_en | immu_nzctxt_cfg_en |
//dmmu_nzctxt_ps0_tsb_en | immu_nzctxt_ps0_tsb_en |
//dmmu_nzctxt_ps1_tsb_en | immu_nzctxt_ps1_tsb_en) & st_inst_unflushed) ; // tsb/cfg asi wr
assign idside_nzctxt_access_rd =
(idmra_nzctxt_rd_d) | // => nzctxt rd with decode
(idmra_fault_rd_d & ~tacc_nctxt) | // => fault-based rd
((dmra_lng_lat_rd | imra_lng_lat_rd) & ~tacc_anctxt) ;
// access non zero context levels
assign mra_wr_ptr[3:0] = {thrid_g[1:0],idside_nzctxt_access_wr,iside_mra_access_wr};
assign mra_rd_ptr[3:0] = {mra_raccess_tid[1:0],idside_nzctxt_access_rd,iside_mra_access_rd};
assign mra_wr_vld = dmra_wr_g | imra_wr_g ;
assign mra_rd_vld = idmra_rd_d | dmra_lng_lat_rd | imra_lng_lat_rd ;
assign dmmu_ctxt_cfg_en = dmmu_zctxt_cfg_en | dmmu_nzctxt_cfg_en ;
assign immu_ctxt_cfg_en = immu_zctxt_cfg_en | immu_nzctxt_cfg_en ;
//assign dmmu_ctxt_cfg_rd_en = (dmmu_zctxt_cfg_en | dmmu_nzctxt_cfg_en) & ld_inst_g ;
//assign immu_ctxt_cfg_rd_en = (immu_zctxt_cfg_en | immu_nzctxt_cfg_en) & ld_inst_g ;
// Change - with 8 tsbs per thread, tsb can be in any of the 3 fields
// of a line in the mra.
wire mra_itag_acc_en,mra_dtag_acc_en ;
// Be careful about loading on trap conditions.
assign st_wr_g = st_inst_unflushed & ~local_flush_w ;
assign mra_itag_acc_en =
(immu_tag_access_en & st_wr_g) | immu_miss_g | (isfsr_trap) ;
assign mra_dtag_acc_en =
(dmmu_tag_access_en & st_wr_g) | lsu_tlu_dmmu_miss_g | lsu_tlu_daccess_excptn_g |
lsu_tlu_daccess_prot_g ;
assign mra_field1_en = (dmmu_zctxt_ps0_tsb_en | immu_zctxt_ps0_tsb_en |
dmmu_nzctxt_ps0_tsb_en | immu_nzctxt_ps0_tsb_en) & st_wr_g ;
// dmmu_nzctxt_ps0_tsb_en | immu_nzctxt_ps0_tsb_en) & st_inst_unflushed ; Bug 3378
assign mra_field2_en = (dmmu_zctxt_ps1_tsb_en | immu_zctxt_ps1_tsb_en |
dmmu_nzctxt_ps1_tsb_en | immu_nzctxt_ps1_tsb_en) & st_wr_g ;
assign mra_field3_en = mra_itag_acc_en | mra_dtag_acc_en ;
assign mra_field4_en = (dmmu_ctxt_cfg_en | immu_ctxt_cfg_en) & st_wr_g ;
// for use of rf16x160
assign mra_byte_wen[19:14] = {6{mra_field1_en}} ;
assign mra_byte_wen[13:8] = {6{mra_field2_en}} ;
assign mra_byte_wen[7:2] = {6{mra_field3_en}} ;
assign mra_byte_wen[1:0] = {2{mra_field4_en}} ;
// active-low selects
// Need to add inst_access_excp to the sel !!!
// Prioritized between the two sels.
assign tag_access_wdata_sel[0] =
~(tag_access_wdata_sel[1] | tag_access_wdata_sel[2]) | rst_tri_en ;
//assign tag_access_wdata_sel[1] = (immu_miss_g | isfsr_trap) & ~rst_tri_en ; // Timing
assign tag_access_wdata_sel[1] = tlu_itag_acc_sel_g & ~rst_tri_en ;
assign tag_access_wdata_sel[2] = (dmra_ldst | imra_ldst) & st_wr_g & ~rst_tri_en ;
// Bug 4728
wire [12:0] tag_access_wdata_ctxt ;
assign tag_access_wdata_ctxt[12:0] =
tag_access_wdata_sel[2] ? lsu_tlu_st_rs3_data_b12t0_g[12:0] : tlu_tag_access_ctxt_g[12:0] ;
assign tag_access_nctxt_g = (tag_access_wdata_ctxt[12:0] == 13'd0) ;
//=========================================================================================
// Tag-Access Context Per thread
//=========================================================================================
// Mark ctxt field in tag-access register as being nucleus or non-nucleus.
// State will not be ~rst_l as use is expected to be preceeded by write.
wire [3:0] itacc_ctxt_en, dtacc_ctxt_en ;
wire itacc_nctxt0,itacc_nctxt1,itacc_nctxt2,itacc_nctxt3;
wire dtacc_nctxt0,dtacc_nctxt1,dtacc_nctxt2,dtacc_nctxt3;
assign itacc_ctxt_en[0] = thread0_sel_g & mra_itag_acc_en & mra_wr_vld ;
assign itacc_ctxt_en[1] = thread1_sel_g & mra_itag_acc_en & mra_wr_vld ;
assign itacc_ctxt_en[2] = thread2_sel_g & mra_itag_acc_en & mra_wr_vld ;
assign itacc_ctxt_en[3] = thread3_sel_g & mra_itag_acc_en & mra_wr_vld ;
assign dtacc_ctxt_en[0] = thread0_sel_g & mra_dtag_acc_en & mra_wr_vld ;
assign dtacc_ctxt_en[1] = thread1_sel_g & mra_dtag_acc_en & mra_wr_vld ;
assign dtacc_ctxt_en[2] = thread2_sel_g & mra_dtag_acc_en & mra_wr_vld ;
assign dtacc_ctxt_en[3] = thread3_sel_g & mra_dtag_acc_en & mra_wr_vld ;
// Thread0
dffe_s itacc_ctxt0 (
.din (tag_access_nctxt_g), .q (itacc_nctxt0),
.en (itacc_ctxt_en[0]), .clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s dtacc_ctxt0 (
.din (tag_access_nctxt_g), .q (dtacc_nctxt0),
.en (dtacc_ctxt_en[0]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread1
dffe_s itacc_ctxt1 (
.din (tag_access_nctxt_g), .q (itacc_nctxt1),
.en (itacc_ctxt_en[1]), .clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s dtacc_ctxt1 (
.din (tag_access_nctxt_g), .q (dtacc_nctxt1),
.en (dtacc_ctxt_en[1]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread2
dffe_s itacc_ctxt2 (
.din (tag_access_nctxt_g), .q (itacc_nctxt2),
.en (itacc_ctxt_en[2]), .clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s dtacc_ctxt2 (
.din (tag_access_nctxt_g), .q (dtacc_nctxt2),
.en (dtacc_ctxt_en[2]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread3
dffe_s itacc_ctxt3 (
.din (tag_access_nctxt_g), .q (itacc_nctxt3),
.en (itacc_ctxt_en[3]), .clk (clk),
.se (1'b0), .si (), .so ()
);
dffe_s dtacc_ctxt3 (
.din (tag_access_nctxt_g), .q (dtacc_nctxt3),
.en (dtacc_ctxt_en[3]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// In-pipe Access
assign itacc_nctxt =
thread0_d ? itacc_nctxt0 :
thread1_d ? itacc_nctxt1 :
thread2_d ? itacc_nctxt2 : itacc_nctxt3 ;
assign dtacc_nctxt =
thread0_d ? dtacc_nctxt0 :
thread1_d ? dtacc_nctxt1 :
thread2_d ? dtacc_nctxt2 : dtacc_nctxt3 ;
assign tacc_nctxt =
iside_mra_access_rd ? itacc_nctxt : dtacc_nctxt ;
// Asynchronous Access
assign itacc_anctxt =
thread0_async_g ? itacc_nctxt0 :
thread1_async_g ? itacc_nctxt1 :
thread2_async_g ? itacc_nctxt2 : itacc_nctxt3 ;
assign dtacc_anctxt =
thread0_async_g ? dtacc_nctxt0 :
thread1_async_g ? dtacc_nctxt1 :
thread2_async_g ? dtacc_nctxt2 : dtacc_nctxt3 ;
assign tacc_anctxt =
imra_lng_lat_rd ? itacc_anctxt : dtacc_anctxt ;
//=========================================================================================
// Interrupt Control
//=========================================================================================
assign tlu_int_asi_load = ld_inst_g & alt_space_g ;
assign tlu_int_asi_store = st_inst_g & alt_space_g ;
assign tlu_int_asi_thrid[1:0] = thrid_g[1:0] ;
assign tlu_int_asi_vld = alt_space_g ;
//=========================================================================================
// ASI Error Condition
//=========================================================================================
// Supported asi but illegal_va. ldxa must signal this occurrence when returning data
// to LSU.
// The decode can be shared with the statement below (grape)
// SPARC_HPV_EN - Needs to change once asi assignments are available !!!
// Bug 2201 : pid and va_wtchpt decoded in lsu (asi 58)
/*wire lsu_asi58_g ;
assign lsu_asi58_g =
((tlu_ldst_va_g[8:0] == 9'h080) | // pid
(tlu_ldst_va_g[8:0] == 9'h038)) ; // va-wtchpt
assign dmmu_sync_supported_asi =
(((lsu_asi_state[7:0] == 8'h58) & ~lsu_asi58_g) |
(lsu_asi_state[7:0] == 8'h59) |
(lsu_asi_state[7:0] == 8'h5A) |
(lsu_asi_state[7:0] == 8'h5B)) & alt_space_g ;*/
wire dmmu_inv_all_asi ;
assign dmmu_inv_all_asi =
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h08}) ;
wire dmmu_async_supported_asi_m ;
assign dmmu_async_supported_asi_m =
((lsu_tlu_tlb_asi_state_m[7:0] == 8'h5C) |
//dmmu_inv_all_asi |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h5D) |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h5E) |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h5F)) & tlb_ldst_inst_m ;
dff_s stgg_dasi (
.din (dmmu_async_supported_asi_m),
.q (dmmu_async_supported_asi),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign dmmu_async_illgl_va_g =
dmmu_async_supported_asi &
~(dmmu_data_in_en |
dmmu_invalidate_all_en | immu_invalidate_all_en | // Bug 4901
dmmu_data_access_en |
dmmu_tag_read_en | dmmu_demap_en) ;
/*assign immu_sync_supported_asi =
((lsu_asi_state[7:0] == 8'h50) |
(lsu_asi_state[7:0] == 8'h51) |
(lsu_asi_state[7:0] == 8'h52)) & alt_space_g ;
assign immu_sync_illgl_va_g =
immu_sync_supported_asi & ~(immu_tag_target_en | immu_sync_fsr_en | immu_tsb_en |
immu_tag_access_en | immu_8k_ptr_en | immu_64k_ptr_en | immu_ctxt_cfg_en) ;*/
wire immu_inv_all_asi ;
assign immu_inv_all_asi =
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h00}) ;
wire immu_async_supported_asi_m ;
assign immu_async_supported_asi_m =
((lsu_tlu_tlb_asi_state_m[7:0] == 8'h54) |
//immu_inv_all_asi |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h60) | // Bug 4901
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h55) |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h56) |
(lsu_tlu_tlb_asi_state_m[7:0] == 8'h57)) & tlb_ldst_inst_m ;
dff_s stgg_iasi (
.din (immu_async_supported_asi_m),
.q (immu_async_supported_asi),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign immu_async_illgl_va_g =
immu_async_supported_asi &
~(immu_data_in_en |
immu_data_access_en | immu_tag_read_en | immu_demap_en |
immu_invalidate_all_en | dmmu_invalidate_all_en) ; // Bug 4901
//=========================================================================================
// IN-PIPE ASI RD SUPPORT
//=========================================================================================
assign thread0_d = ~thrid_d[1] & ~thrid_d[0] ;
assign thread1_d = ~thrid_d[1] & thrid_d[0] ;
assign thread2_d = thrid_d[1] & ~thrid_d[0] ;
assign thread3_d = thrid_d[1] & thrid_d[0] ;
wire [7:0] asi_reg0_d1 ;
dff_s #(8) stgd1_asi0 (
.din (lsu_asi_reg0[7:0]),
.q (asi_reg0_d1[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [7:0] asi_reg1_d1 ;
dff_s #(8) stgd1_asi1 (
.din (lsu_asi_reg1[7:0]),
.q (asi_reg1_d1[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [7:0] asi_reg2_d1 ;
dff_s #(8) stgd1_asi2 (
.din (lsu_asi_reg2[7:0]),
.q (asi_reg2_d1[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [7:0] asi_reg3_d1 ;
dff_s #(8) stgd1_asi3 (
.din (lsu_asi_reg3[7:0]),
.q (asi_reg3_d1[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [7:0] asi_reg_state ;
assign asi_reg_state[7:0] =
(thread0_d ? asi_reg0_d1[7:0] :
(thread1_d ? asi_reg1_d1[7:0] :
(thread2_d ? asi_reg2_d1[7:0] :
asi_reg3_d1[7:0]))) ;
wire imm_asi_vld_d ;
assign imm_asi_vld_d = ~ifu_lsu_imm_asi_d[8] ;
// Use of asi delayed by a cycle.
assign asi_state_d[7:0] = imm_asi_vld_d ?
ifu_lsu_imm_asi_d[7:0] : asi_reg_state[7:0] ;
dff_s #(8) stgd1_asi (
.din (asi_state_d[7:0]),
.q (asi_state_e[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// bit8 is unused.
dff_s #(8) stgd1_eva (
.din (exu_mmu_early_va_e[7:0]),
.q (early_va_m[7:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(6) stgd1_mref (
.din ({ifu_lsu_memref_d,thread0_d,thread1_d,thread2_d,thread3_d,ifu_tlu_alt_space_d}),
.q ({memref_e,thread0_e, thread1_e, thread2_e, thread3_e,alt_space_e}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dff_s #(1) stgm_mref (
.din (memref_e),
.q (memref_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// qualification with memref_d to cut down on number of speculative reads
// decode can be shared with corresponding enables
// gates can be shared.
// Establish that mra *could* be read by sync events. full decode would
// cause critical path.
assign idmra_rd_d =
//((asi_state_d[6:4] == 3'h6) | // specifically tag-access.
((asi_state_d[6:4] == 3'h5) |
(asi_state_d[6:4] == 3'h3)) & ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
// need to decode 58,59,5a,5B,31,32,39,3A,33,3B
// use lower hex. need to distinguish 1 & 2 between both accesses.
assign dmra_rw_d =
(asi_state_d[3:0] == 4'b1000) | // 8
(((asi_state_d[3:0] == 4'b0001) | // 1
(asi_state_d[3:0] == 4'b0010)) & asi_state_d[5]) | // 2 ;1 & 2 need distinction between I&D
(asi_state_d[3:0] == 4'b1001) | // 9
(asi_state_d[3:0] == 4'b1010) | // A
(asi_state_d[2:0] == 3'b011) ; // partial B
// Read requires that ctxt of access be chosen.
// ctxt_cfg,ps0_tsb,ps1_tsb require decode for ctxt.
// tag_access,ps0-ptr,ps1-ptr,direct-ptr,tag-target require lookup of logged ctxt.
// ** Solution here is to exclude zctxt asi rds from equation.
assign idmra_nzctxt_rd_d =
(asi_state_d[7:4] == 4'h3) & // common
((asi_state_d[3:0] == 4'h9) | // dmmu_nzctxt_ps0_tsb
(asi_state_d[3:0] == 4'hA) | // dmmu_nzctxt_ps1_tsb
(asi_state_d[3:0] == 4'hB) | // dmmu_nzctxt_cfg
(asi_state_d[3:0] == 4'hD) | // immu_nzctxt_ps0_tsb
(asi_state_d[3:0] == 4'hE) | // immu_nzctxt_ps1_tsb
(asi_state_d[3:0] == 4'hF)) & // immu_nzctxt_cfg
ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
// Fault based reads
assign idmra_fault_rd_d =
(asi_state_d[7:4] == 4'h5) & // common
((asi_state_d[3:0] == 4'h8) | // dmmu_tag_access/target; va ignored
(asi_state_d[3:0] == 4'h9) | // dmmu_ps0_ptr
(asi_state_d[3:0] == 4'hA) | // dmmu_ps1_ptr
(asi_state_d[3:0] == 4'hB) | // direct_ptr
(asi_state_d[3:0] == 4'h0) | // immu_tag_access/target ; va ignored
(asi_state_d[3:0] == 4'h1) | // immu_ps0_ptr
(asi_state_d[3:0] == 4'h2)) & // immu_ps1_ptr
ifu_tlu_alt_space_d & ifu_lsu_memref_d ;
// Note - tag_access needs to be included.
always @ (/*AUTOSENSE*/alt_space_e or asi_state_e or memref_e)
begin
// DMMU
dmmu_decode_asi58_e =
({asi_state_e[7:0]} == {8'h58}) & alt_space_e & memref_e ;
dmmu_8k_ptr_e =
({asi_state_e[7:0]} == {8'h59}) & alt_space_e & memref_e ;
dmmu_64k_ptr_e =
({asi_state_e[7:0]} == {8'h5A}) & alt_space_e & memref_e ;
dmmu_direct_ptr_e =
({asi_state_e[7:0]} == {8'h5B}) & alt_space_e & memref_e ;
dmmu_zctxt_ps0_tsb_e =
({asi_state_e[7:0]} == {8'h31}) & alt_space_e & memref_e ;
dmmu_zctxt_ps1_tsb_e =
({asi_state_e[7:0]} == {8'h32}) & alt_space_e & memref_e ;
dmmu_nzctxt_ps0_tsb_e =
({asi_state_e[7:0]} == {8'h39}) & alt_space_e & memref_e ;
dmmu_nzctxt_ps1_tsb_e =
({asi_state_e[7:0]} == {8'h3A}) & alt_space_e & memref_e ;
dmmu_zctxt_cfg_e =
({asi_state_e[7:0]} == {8'h33}) & alt_space_e & memref_e ;
dmmu_nzctxt_cfg_e =
({asi_state_e[7:0]} == {8'h3B}) & alt_space_e & memref_e ;
// IMMU
immu_decode_asi50_e =
({asi_state_e[7:0]} == {8'h50}) & alt_space_e & memref_e ;
immu_8k_ptr_e =
({asi_state_e[7:0]} == {8'h51}) & alt_space_e & memref_e ;
immu_64k_ptr_e =
({asi_state_e[7:0]} == {8'h52}) & alt_space_e & memref_e ;
immu_zctxt_ps0_tsb_e =
({asi_state_e[7:0]} == {8'h35}) & alt_space_e & memref_e ;
immu_zctxt_ps1_tsb_e =
({asi_state_e[7:0]} == {8'h36}) & alt_space_e & memref_e ;
immu_nzctxt_ps0_tsb_e =
({asi_state_e[7:0]} == {8'h3D}) & alt_space_e & memref_e ;
immu_nzctxt_ps1_tsb_e =
({asi_state_e[7:0]} == {8'h3E}) & alt_space_e & memref_e ;
immu_zctxt_cfg_e =
({asi_state_e[7:0]} == {8'h37}) & alt_space_e & memref_e ;
immu_nzctxt_cfg_e =
({asi_state_e[7:0]} == {8'h3F}) & alt_space_e & memref_e ;
end
wire immu_64k_ptr_m,immu_8k_ptr_m,dmmu_direct_ptr_m,dmmu_64k_ptr_m,
dmmu_8k_ptr_m ;
dff_s #(19) fastasi_m (
.din ({dmmu_8k_ptr_e,dmmu_64k_ptr_e,dmmu_direct_ptr_e,
dmmu_decode_asi58_e, immu_decode_asi50_e,
dmmu_zctxt_ps0_tsb_e, dmmu_zctxt_ps1_tsb_e,
dmmu_nzctxt_ps0_tsb_e, dmmu_nzctxt_ps1_tsb_e,
dmmu_zctxt_cfg_e, dmmu_nzctxt_cfg_e,
immu_zctxt_ps0_tsb_e, immu_zctxt_ps1_tsb_e,
immu_nzctxt_ps0_tsb_e, immu_nzctxt_ps1_tsb_e,
immu_zctxt_cfg_e, immu_nzctxt_cfg_e,
immu_8k_ptr_e,immu_64k_ptr_e}),
.q ({dmmu_8k_ptr_m,dmmu_64k_ptr_m,dmmu_direct_ptr_m,
dmmu_decode_asi58_m, immu_decode_asi50_m,
dmmu_zctxt_ps0_tsb_m, dmmu_zctxt_ps1_tsb_m,
dmmu_nzctxt_ps0_tsb_m, dmmu_nzctxt_ps1_tsb_m,
dmmu_zctxt_cfg_m, dmmu_nzctxt_cfg_m,
immu_zctxt_ps0_tsb_m, immu_zctxt_ps1_tsb_m,
immu_nzctxt_ps0_tsb_m, immu_nzctxt_ps1_tsb_m,
immu_zctxt_cfg_m, immu_nzctxt_cfg_m,
immu_8k_ptr_m,immu_64k_ptr_m}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign dmmu_tag_target_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_tag_access_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h30) ;
assign dmmu_sync_fsr_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h18) ;
assign dmmu_sync_far_en_m = dmmu_decode_asi58_m & (early_va_m[7:0] == 8'h20) ;
assign dmmu_zctxt_ps0_tsb_en_m = dmmu_zctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_zctxt_ps1_tsb_en_m = dmmu_zctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_nzctxt_ps0_tsb_en_m = dmmu_nzctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_nzctxt_ps1_tsb_en_m = dmmu_nzctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_zctxt_cfg_en_m = dmmu_zctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_nzctxt_cfg_en_m = dmmu_nzctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_8k_ptr_en_m = dmmu_8k_ptr_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_64k_ptr_en_m = dmmu_64k_ptr_m & (early_va_m[7:0] == 8'h00) ;
assign dmmu_direct_ptr_en_m = dmmu_direct_ptr_m & (early_va_m[7:0] == 8'h00) ;
// Calculation of dmmu illgl-va
wire dmmu_sync_supported_asi_e ;
wire dmmu_sync_supported_asi_m ;
assign dmmu_sync_supported_asi_e =
(dmmu_decode_asi58_e | dmmu_zctxt_ps0_tsb_e | dmmu_zctxt_ps1_tsb_e |
dmmu_nzctxt_ps0_tsb_e | dmmu_nzctxt_ps1_tsb_e | dmmu_zctxt_cfg_e |
dmmu_nzctxt_cfg_e | dmmu_8k_ptr_e | dmmu_64k_ptr_e | dmmu_direct_ptr_e);
dff_s stgm_dsynca (
.din (dmmu_sync_supported_asi_e),
.q (dmmu_sync_supported_asi_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire dmmu_sync_illgl_va_m ;
assign dmmu_sync_illgl_va_m = dmmu_sync_supported_asi_m & ~(dmmu_tag_target_en_m |
dmmu_tag_access_en_m | dmmu_sync_fsr_en_m | dmmu_sync_far_en_m | dmmu_tsb_en_m |
dmmu_ctxt_cfg_en_m | dmmu_8k_ptr_en_m | dmmu_64k_ptr_en_m | dmmu_direct_ptr_en_m);
assign dmmu_tsb_en_m =
dmmu_zctxt_ps0_tsb_en_m | dmmu_zctxt_ps1_tsb_en_m |
dmmu_nzctxt_ps0_tsb_en_m | dmmu_nzctxt_ps1_tsb_en_m ;
assign dmmu_ctxt_cfg_en_m = dmmu_zctxt_cfg_en_m | dmmu_nzctxt_cfg_en_m ;
assign immu_tag_target_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h00) ;
assign immu_tag_access_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h30) ;
assign immu_sync_fsr_en_m = immu_decode_asi50_m & (early_va_m[7:0] == 8'h18) ;
assign immu_zctxt_ps0_tsb_en_m = immu_zctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign immu_zctxt_ps1_tsb_en_m = immu_zctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign immu_nzctxt_ps0_tsb_en_m = immu_nzctxt_ps0_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign immu_nzctxt_ps1_tsb_en_m = immu_nzctxt_ps1_tsb_m & (early_va_m[7:0] == 8'h00) ;
assign immu_zctxt_cfg_en_m = immu_zctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
assign immu_nzctxt_cfg_en_m = immu_nzctxt_cfg_m & (early_va_m[7:0] == 8'h00) ;
assign immu_8k_ptr_en_m = immu_8k_ptr_m & (early_va_m[7:0] == 8'h00) ;
assign immu_64k_ptr_en_m = immu_64k_ptr_m & (early_va_m[7:0] == 8'h00) ;
assign immu_tsb_en_m =
immu_zctxt_ps0_tsb_en_m | immu_zctxt_ps1_tsb_en_m |
immu_nzctxt_ps0_tsb_en_m | immu_nzctxt_ps1_tsb_en_m ;
assign immu_ctxt_cfg_en_m = immu_zctxt_cfg_en_m | immu_nzctxt_cfg_en_m ;
// Calculation of immu illgl-va
wire immu_sync_supported_asi_e ;
wire immu_sync_supported_asi_m ;
assign immu_sync_supported_asi_e =
(immu_decode_asi50_e | immu_zctxt_ps0_tsb_e | immu_zctxt_ps1_tsb_e |
immu_nzctxt_ps0_tsb_e | immu_nzctxt_ps1_tsb_e | immu_zctxt_cfg_e |
immu_nzctxt_cfg_e | immu_8k_ptr_e | immu_64k_ptr_e);
dff_s stgm_isynca (
.din (immu_sync_supported_asi_e),
.q (immu_sync_supported_asi_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire immu_sync_illgl_va_m ;
assign immu_sync_illgl_va_m = immu_sync_supported_asi_m & ~(immu_tag_target_en_m |
immu_tag_access_en_m | immu_sync_fsr_en_m | immu_tsb_en_m | immu_ctxt_cfg_en_m |
immu_8k_ptr_en_m | immu_64k_ptr_en_m);
dff_s #(2) stgg_illgl (
.din ({immu_sync_illgl_va_m,dmmu_sync_illgl_va_m}),
.q ({immu_sync_illgl_va_g,dmmu_sync_illgl_va_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Staged to g for writes
dff_s #(17) fastasi_g (
.din ({dmmu_tag_access_en_m,
dmmu_sync_fsr_en_m, dmmu_sync_far_en_m,
dmmu_zctxt_ps0_tsb_en_m, dmmu_zctxt_ps1_tsb_en_m,
dmmu_nzctxt_ps0_tsb_en_m, dmmu_nzctxt_ps1_tsb_en_m,
dmmu_zctxt_cfg_en_m, dmmu_nzctxt_cfg_en_m,
immu_tag_access_en_m,
immu_sync_fsr_en_m,
immu_zctxt_ps0_tsb_en_m, immu_zctxt_ps1_tsb_en_m,
immu_nzctxt_ps0_tsb_en_m, immu_nzctxt_ps1_tsb_en_m,
immu_zctxt_cfg_en_m, immu_nzctxt_cfg_en_m}),
.q ({dmmu_tag_access_en,
dmmu_sync_fsr_en, dmmu_sync_far_en,
dmmu_zctxt_ps0_tsb_en, dmmu_zctxt_ps1_tsb_en,
dmmu_nzctxt_ps0_tsb_en, dmmu_nzctxt_ps1_tsb_en,
dmmu_zctxt_cfg_en, dmmu_nzctxt_cfg_en,
immu_tag_access_en,
immu_sync_fsr_en,
immu_zctxt_ps0_tsb_en, immu_zctxt_ps1_tsb_en,
immu_nzctxt_ps0_tsb_en, immu_nzctxt_ps1_tsb_en,
immu_zctxt_cfg_en, immu_nzctxt_cfg_en}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
// MMU ASI Decode - D-Side
//=========================================================================================
// Assumption is that only 9 bits of VA are required.
// Comparison for asi-state and va is to be done uniformly in w2.
// This will have to change because of tsb mapping to mra.
assign dmmu_tsb_en =
dmmu_zctxt_ps0_tsb_en | dmmu_zctxt_ps1_tsb_en |
dmmu_nzctxt_ps0_tsb_en | dmmu_nzctxt_ps1_tsb_en ;
assign tlb_ldst_inst_m = lsu_tlu_tlb_ld_inst_m | lsu_tlu_tlb_st_inst_m ;
// M-stage decoding for long-latency tlb accesses
always @ (/*AUTOSENSE*/dmmu_inv_all_asi or lsu_tlu_tlb_asi_state_m
or lsu_tlu_tlb_ldst_va_m[7:0] or tlb_ldst_inst_m)
begin
dmmu_data_in_en_m =
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h5C,8'h00}) & tlb_ldst_inst_m ;
dmmu_invalidate_all_en_m =
dmmu_inv_all_asi & tlb_ldst_inst_m ;
//({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h08}) & tlb_ldst_inst_m ;
// Address specifies tlb entry.
dmmu_data_access_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5D}) & tlb_ldst_inst_m ;
// Address specifies tlb entry.
dmmu_tag_read_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5E}) & tlb_ldst_inst_m ;
dmmu_demap_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h5F}) & tlb_ldst_inst_m ;
end
// Stage to g.
// Make dff->dffre. This required to avoid conflict between fast-asi and lng-latency
// rds of mra. Specifically, data-in/data_access need to be staged, along with
// support information.
wire lng_ltncy_en_d1 ;
assign tlu_lng_ltncy_en_l = ~lng_ltncy_en_d1 | sehold ;
wire lng_ltncy_en ;
dff_s stgd1_lltncyen (
.din (lng_ltncy_en),
.q (lng_ltncy_en_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign lng_ltncy_en = (lsu_tlu_tlb_st_inst_m | lsu_tlu_tlb_ld_inst_m) ;
wire lng_ltncy_rst ;
assign lng_ltncy_rst =
tlb_ld_inst_unflushed | // all reads processed immediately
(tlb_st_inst_unflushed & // all writes not requiring mra processed immediately
~(dmmu_data_in_en | dmmu_data_access_en | immu_data_in_en | immu_data_access_en)) |
dmra_lng_lat_rd | imra_lng_lat_rd | // lng-ltncy rds - delay until bubble available.
((tlb_ld_inst_unflushed | tlb_st_inst_unflushed) & // rst w/o use if illgl-va
(dmmu_async_illgl_va_g | immu_async_illgl_va_g)) |
~rst_l ;
dffe_s #(10) dtlbacc_stgg (
.din ({lsu_tlu_tlb_ldst_va_m[10:3], lsu_tlu_tlb_access_tid_m[1:0]}),
.q ({tlb_ldst_va_g[10:3],tlb_access_tid_g[1:0]}),
.clk (clk),
.en (lng_ltncy_en),
.se (1'b0), .si (), .so ()
);
dffre_s #(7) dtlbaccr_stgg (
.din ({dmmu_data_in_en_m,dmmu_data_access_en_m,dmmu_tag_read_en_m,
dmmu_demap_en_m,dmmu_invalidate_all_en_m,
lsu_tlu_tlb_ld_inst_m,lsu_tlu_tlb_st_inst_m}),
.q ({dmmu_data_in_en,dmmu_data_access_en,dmmu_tag_read_en,
dmmu_demap_en,dmmu_invalidate_all_en,
tlb_ld_inst_unflushed,tlb_st_inst_unflushed}),
.clk (clk),
.rst (lng_ltncy_rst), .en (lng_ltncy_en),
.se (1'b0), .si (), .so ()
);
assign tlb_st_inst_g = tlb_st_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;
assign tlb_ld_inst_g = tlb_ld_inst_unflushed & ~(dmmu_async_illgl_va_g | immu_async_illgl_va_g) ;
assign dsfsr_asi_wr_en[0] = dmmu_sync_fsr_en & st_inst_g & thread0_sel_g ;
assign dsfsr_asi_wr_en[1] = dmmu_sync_fsr_en & st_inst_g & thread1_sel_g ;
assign dsfsr_asi_wr_en[2] = dmmu_sync_fsr_en & st_inst_g & thread2_sel_g ;
assign dsfsr_asi_wr_en[3] = dmmu_sync_fsr_en & st_inst_g & thread3_sel_g ;
assign dmmu_any_sfsr_wr = dmmu_sync_fsr_en & st_inst_g ; //|(dsfsr_asi_wr_en[3:0]);
assign dmmu_sfsr_wr_en_l[3:0] =
~(dsfsr_asi_wr_en[3:0] | (dmmu_sfsr_trp_wr[3:0] & {4{~priority_squash_g}})) ; // Bug 4183
assign dmmu_sfar_wr_en_l[0] =
~((dmmu_sync_far_en & st_inst_g & thread0_sel_g) |
(dmmu_sfsr_trp_wr[0] & ~priority_squash_g)) ; // Bug 4183
assign dmmu_sfar_wr_en_l[1] =
~((dmmu_sync_far_en & st_inst_g & thread1_sel_g) |
(dmmu_sfsr_trp_wr[1] & ~priority_squash_g)) ;
assign dmmu_sfar_wr_en_l[2] =
~((dmmu_sync_far_en & st_inst_g & thread2_sel_g) |
(dmmu_sfsr_trp_wr[2] & ~priority_squash_g)) ;
assign dmmu_sfar_wr_en_l[3] =
~((dmmu_sync_far_en & st_inst_g & thread3_sel_g) |
(dmmu_sfsr_trp_wr[3] & ~priority_squash_g)) ;
assign dmmu_data_in_wr_en = dmmu_data_in_en & tlb_st_inst_g ; // Write-Only.
assign dmmu_data_access_wr_en = dmmu_data_access_en & tlb_st_inst_g ;
// non-threaded as shared resource
assign dmmu_data_access_rd_en = dmmu_data_access_en & tlb_ld_inst_g ;
// take exception for write case.
assign dmmu_tag_read_rd_en = dmmu_tag_read_en & tlb_ld_inst_g ;
assign dtlb_rw_index_vld_g = dmmu_data_access_rd_en | dmmu_data_access_wr_en | dmmu_tag_read_rd_en ;
// terminate write if tlb full and signal exception.
assign dtlb_wr_vld_g = (dmmu_data_in_wr_en | dmmu_data_access_wr_en) & ~ifu_lsu_memref_d ;
wire dtlb_rw_index_vld_pend ;
wire [5:0] dtlb_rw_index_pend ;
dffre_s #(1) stgw2_dtlbctl (
.din (dtlb_rw_index_vld_g),
.q (dtlb_rw_index_vld_pend),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(6) stgw2_dtlbidx (
.din (tlb_ldst_va_g[8:3]),
.q (dtlb_rw_index_pend[5:0]),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire tlb_rd_mode, tlb_rd_mode_d1 ;
assign tlb_rd_mode =
tlu_itlb_tag_rd_g | tlu_itlb_data_rd_g | // i-side read
tlu_dtlb_tag_rd_g | tlu_dtlb_data_rd_g ; // d-side read
dff_s stgd1_rmode (
.din (tlb_rd_mode),
.q (tlb_rd_mode_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire dtlb_done_d1 ;
dff_s stgd1_ddone (
.din (lsu_tlu_dtlb_done),
.q (dtlb_done_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire itlb_done_d1 ;
dff_s stgd1_idone (
.din (ifu_tlu_itlb_done),
.q (itlb_done_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Advanced by a cycle.
assign tlu_dtlb_rw_index_vld_g = dtlb_rw_index_vld_g | dtlb_rw_index_vld_pend ;
//assign tlu_dtlb_rw_index_vld_g = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~dtlb_done_d1) ; //Bug3974
//assign tlu_dtlb_rw_index_vld_g = dtlb_rw_index_vld_g | (dtlb_rw_index_vld_pend & ~lsu_tlu_dtlb_done) ;
assign tlu_dtlb_rw_index_g[5:0] = (tlb_ldst_va_g[8:3] & {6{~(tlb_admp_mode | tlb_write_mode | tlb_rd_mode_d1)}}) |
dtlb_rw_index_pend[5:0] ;
// Exception on reserved field.
assign demap_pctxt = ~tlb_ldst_va_g[5] & ~tlb_ldst_va_g[4] ;
assign demap_sctxt = ~tlb_ldst_va_g[5] & tlb_ldst_va_g[4] ;
assign demap_nctxt = tlb_ldst_va_g[5] & ~tlb_ldst_va_g[4] ;
// reserved ctxt causes demap to be ignored.
// reserved dmp type causes demap to be ignored.
assign demap_resrv = (tlb_ldst_va_g[5] & tlb_ldst_va_g[4]) // ctxt
| (tlb_ldst_va_g[7] & tlb_ldst_va_g[6]) ; // type
assign ddemap_by_page = dmmu_demap_en & ~tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
assign ddemap_by_ctxt = dmmu_demap_en & ~tlb_ldst_va_g[7] & tlb_ldst_va_g[6] ;
assign ddemap_all = dmmu_demap_en & tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
// assumption is that demap_all is unaffected by presence of reserved ctxt as it
// does not use ctxt.
assign ddemap_vld = ((ddemap_by_page | ddemap_by_ctxt) & ~demap_resrv) |
ddemap_all ;
//wire dtlb_dmp_by_ctxt_pend ;
wire dtlb_dmp_all_pend ;
wire dtlb_dmp_pctxt_pend ;
wire dtlb_dmp_sctxt_pend ;
wire dtlb_dmp_nctxt_pend ;
wire [1:0] idtlb_dmp_thrid_pend ;
wire [1:0] ldst_asi_tid ;
wire dmmu_inv_all_g, dmmu_inv_all_pend ;
assign dmmu_inv_all_g = dmmu_invalidate_all_en & tlb_st_inst_g ;
// Demap/Invalidate
dffre_s #(5) stgw2_dtlbdmp (
.din ({ddemap_all,demap_pctxt,demap_sctxt,demap_nctxt,dmmu_inv_all_g}),
.q ({dtlb_dmp_all_pend,dtlb_dmp_pctxt_pend,dtlb_dmp_sctxt_pend,
dtlb_dmp_nctxt_pend,dmmu_inv_all_pend }),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Bug 3905 - rm from above flop.
assign idtlb_dmp_thrid_pend[1:0] = tlb_access_tid_g[1:0] ;
assign ldst_asi_tid[1:0] =
(lsu_tlu_dtlb_done | dmmu_async_illgl_va_g | immu_async_illgl_va_g) ?
idtlb_dmp_thrid_pend[1:0] : thrid_g[1:0] ;
// Thread for tlb
dff_s #(4) stg_w2 (
.din ({ldst_asi_tid[1:0],idtlb_dmp_thrid_pend[1:0]}),
.q ({tlu_lsu_ldxa_tid_w2[1:0],tlu_lsu_stxa_ack_tid[1:0]}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~dtlb_done_d1) ;
//assign tlu_dtlb_invalidate_all_g = dmmu_inv_all_g | (dmmu_inv_all_pend & ~lsu_tlu_dtlb_done) ;
// Timing Change : Delay by a cycle to match vlds.
wire pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt ;
wire pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt ;
//assign pre_dtlb_dmp_by_ctxt = (ddemap_by_ctxt | dtlb_dmp_by_ctxt_pend) & ~tlu_admp_key_sel ;
assign pre_dtlb_dmp_all = (ddemap_all | dtlb_dmp_all_pend) & ~tlu_admp_key_sel ;
assign pre_dtlb_dmp_pctxt = (dtlb_dmp_pctxt_pend) & ~tlu_admp_key_sel ;
assign pre_dtlb_dmp_sctxt = (dtlb_dmp_sctxt_pend) & ~tlu_admp_key_sel ;
assign pre_dtlb_dmp_nctxt = (dtlb_dmp_nctxt_pend) & ~tlu_admp_key_sel ;
assign pre_dtlb_dmp_actxt = tlu_admp_key_sel ;
dff_s #(5) dmp_stgd1 (
.din ({pre_dtlb_dmp_all, pre_dtlb_dmp_pctxt,
pre_dtlb_dmp_sctxt, pre_dtlb_dmp_nctxt, pre_dtlb_dmp_actxt}),
.q ({tlu_dtlb_dmp_all_g,tlu_dtlb_dmp_pctxt_g,
tlu_dtlb_dmp_sctxt_g,tlu_dtlb_dmp_nctxt_g,tlu_dtlb_dmp_actxt_g}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_idtlb_dmp_thrid_g = tlb_access_tid_g[1:0] | idtlb_dmp_thrid_pend[1:0] ;
//=========================================================================================
// MMU ASI Decode - I-Side
//=========================================================================================
// Assumption is that only 9 bits of VA are required.
// Comparison for asi-state and va is to be done uniformly in w2.
assign immu_tsb_en =
immu_zctxt_ps0_tsb_en | immu_zctxt_ps1_tsb_en |
immu_nzctxt_ps0_tsb_en | immu_nzctxt_ps1_tsb_en ;
reg immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m;
// M-stage decoding for long-latency tlb accesses
always @ (/*AUTOSENSE*/immu_inv_all_asi or lsu_tlu_tlb_asi_state_m
or lsu_tlu_tlb_ldst_va_m[7:0] or tlb_ldst_inst_m)
begin
immu_data_in_en_m =
({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h54,8'h00}) & tlb_ldst_inst_m ;
// Address specifies tlb entry.
immu_invalidate_all_en_m =
immu_inv_all_asi & tlb_ldst_inst_m ;
//({lsu_tlu_tlb_asi_state_m[7:0],lsu_tlu_tlb_ldst_va_m[7:0]} == {8'h60,8'h00}) & tlb_ldst_inst_m ;
immu_data_access_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h55}) & tlb_ldst_inst_m ;
// Address specifies tlb entry.
immu_tag_read_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h56}) & tlb_ldst_inst_m ;
immu_demap_en_m =
({lsu_tlu_tlb_asi_state_m[7:0]} == {8'h57}) & tlb_ldst_inst_m ;
end
// Stage to g.
// Convert to dffre to resolve conflict between fast-asi and lng-ltncy reads.
dffre_s #(5) itlbacc_stgg (
.din ({immu_data_in_en_m,immu_data_access_en_m,immu_tag_read_en_m,immu_demap_en_m,immu_invalidate_all_en_m}),
.q ({immu_data_in_en,immu_data_access_en,immu_tag_read_en,immu_demap_en,immu_invalidate_all_en}),
.clk (clk),
.rst (lng_ltncy_rst), .en (lng_ltncy_en),
.se (1'b0), .si (), .so ()
);
assign isfsr_asi_wr_en[0] = immu_sync_fsr_en & st_inst_g & thread0_sel_g ;
assign isfsr_asi_wr_en[1] = immu_sync_fsr_en & st_inst_g & thread1_sel_g ;
assign isfsr_asi_wr_en[2] = immu_sync_fsr_en & st_inst_g & thread2_sel_g ;
assign isfsr_asi_wr_en[3] = immu_sync_fsr_en & st_inst_g & thread3_sel_g ;
assign immu_any_sfsr_wr = immu_sync_fsr_en & st_inst_g ; //|(isfsr_asi_wr_en[3:0]);
assign immu_sfsr_wr_en_l[3:0] = ~(isfsr_trp_wr[3:0] | isfsr_asi_wr_en[3:0]) ;
assign immu_tsb_rd_en[0] = immu_tsb_en & ld_inst_g & thread0_sel_g ;
assign immu_tsb_rd_en[1] = immu_tsb_en & ld_inst_g & thread1_sel_g ;
assign immu_tsb_rd_en[2] = immu_tsb_en & ld_inst_g & thread2_sel_g ;
assign immu_tsb_rd_en[3] = immu_tsb_en & ld_inst_g & thread3_sel_g ;
assign immu_data_in_wr_en = immu_data_in_en & tlb_st_inst_g ; // Write-Only.
assign immu_data_access_wr_en = immu_data_access_en & tlb_st_inst_g ;
assign immu_data_access_rd_en = immu_data_access_en & tlb_ld_inst_g ;
assign immu_tag_read_rd_en = immu_tag_read_en & tlb_ld_inst_g ;
assign itlb_rw_index_vld_g = immu_data_access_rd_en | immu_data_access_wr_en | immu_tag_read_rd_en ;
// terminate write if tlb full and signal exception.
assign itlb_wr_vld_g = (immu_data_in_wr_en | immu_data_access_wr_en) & ~ifu_lsu_memref_d ;
wire itlb_rw_index_vld_pend ;
dffre_s #(1) stgw2_itlbctl (
.din (itlb_rw_index_vld_g),
.q (itlb_rw_index_vld_pend),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_itlb_rw_index_vld_g = itlb_rw_index_vld_g | (itlb_rw_index_vld_pend & ~itlb_done_d1) ;
assign tlu_itlb_rw_index_g[5:0] = tlu_dtlb_rw_index_g[5:0] ;
assign idemap_by_page = immu_demap_en & ~tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
assign idemap_by_ctxt = immu_demap_en & ~tlb_ldst_va_g[7] & tlb_ldst_va_g[6] ;
assign idemap_all = immu_demap_en & tlb_ldst_va_g[7] & ~tlb_ldst_va_g[6] ;
// assumption is that demap_all is unaffected by presence of reserved ctxt as it
// does not use ctxt.
assign idemap_vld = ((idemap_by_page | idemap_by_ctxt) & ~(demap_resrv | demap_sctxt)) |
idemap_all ;
wire itlb_dmp_by_ctxt_pend ;
wire itlb_dmp_all_pend ;
wire immu_inv_all_g, immu_inv_all_pend ;
assign immu_inv_all_g = immu_invalidate_all_en & tlb_st_inst_g ;
// Demap
dffre_s #(3) stgw2_itlbdmp (
.din ({idemap_by_ctxt,idemap_all,immu_inv_all_g}),
.q ({itlb_dmp_by_ctxt_pend, itlb_dmp_all_pend,immu_inv_all_pend}),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire tlu_itlb_dmp_all_g = (idemap_all | itlb_dmp_all_pend) & ~tlu_admp_key_sel ;
assign tlu_itlb_invalidate_all_g = immu_inv_all_g | (immu_inv_all_pend & ~itlb_done_d1) ;
assign tlu_itlb_dmp_pctxt_g = tlu_dtlb_dmp_pctxt_g ;
// Timing Change - delay by 1-cycle to match vld.
wire pre_itlb_dmp_actxt ;
assign pre_itlb_dmp_actxt = tlu_admp_key_sel ;
dff_s #(1) preidmp_d1 (
.din (pre_itlb_dmp_actxt),
.q (tlu_itlb_dmp_actxt_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_itlb_dmp_nctxt_g = tlu_dtlb_dmp_nctxt_g ;
// Adapt key vlds to autodemap.
// Note that sense of global bit has changed. Otherwise vlds remain same.
assign tlu_dmp_key_vld_g[4:0] =
(ddemap_by_ctxt | idemap_by_ctxt) ? 5'b00000 : // demap-ctxt - include only ctxt
(ddemap_all | idemap_all) ? 5'b00001 : // demap-all - do not include va or ctxt
// Bug 3129 5'b11110 ; // else include both va and ctxt
tlb_ldst_va_g[9] ? 5'b11111 : // include va and NO ctxt;dmp-pg-real
5'b11110 ; // include both va and ctxt; dmp-pg
// real tte for demap and write. both are indicated in bit 9 of va.
// demap_by_ctxt will not effect real translations.
assign tlu_tte_real_g = tlb_ldst_va_g[9] & ~(ddemap_by_ctxt | idemap_by_ctxt) ;
//=========================================================================================
// EXCEPTIONS
//=========================================================================================
// Now generated in LSU.
// These are all related to asi use.
/*assign tlu_mmu_sync_data_excp_g =
(immu_sync_rd_only_asi_g | dmmu_sync_rd_only_asi_g) & st_inst_unflushed & inst_vld_g ;*/
//=========================================================================================
// TAG/DATA RD/WR/DMP HANDSHAKE
//=========================================================================================
// RD/WR HANDSHAKE
// Need to add autodemap capability.
// Assume mutually exclusive by construction.
assign tlb_access_en = itlb_wr_vld_g | immu_data_access_rd_en | immu_tag_read_rd_en |
dtlb_wr_vld_g | dmmu_data_access_rd_en | dmmu_tag_read_rd_en |
idemap_vld | ddemap_vld | immu_inv_all_g | dmmu_inv_all_g ;
assign tlb_access_en_l = ~tlb_access_en ;
assign tlb_access_rst = ~rst_l | ((lsu_tlu_dtlb_done | ifu_tlu_itlb_done) & ~(tlb_admp_mode | tlb_admp_mode_d1)) ;
assign tlb_access_rst_l = ~tlb_access_rst ;
wire tlb_access_en_l_d1 ;
dff_s #(1) stgd1_tlbacc (
.din (tlb_access_en_l),
.q (tlb_access_en_l_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_tlb_access_en_l_d1 = tlb_access_en_l_d1 | sehold ;
assign itlb_tag_rd_en = immu_tag_read_rd_en | immu_data_access_rd_en ;
assign dtlb_tag_rd_en = dmmu_tag_read_rd_en | dmmu_data_access_rd_en ;
dffre_s #(8) tlb_access (
.din ({itlb_wr_vld_g,immu_data_access_rd_en,itlb_tag_rd_en,
dtlb_wr_vld_g,dmmu_data_access_rd_en,dtlb_tag_rd_en,
idemap_vld, ddemap_vld}),
.q ({itlb_wr_pend,itlb_data_rd_pend,itlb_tag_rd_pend,
dtlb_wr_pend,dtlb_data_rd_pend,dtlb_tag_rd_pend,
idemap_pend, ddemap_pend}),
.rst (tlb_access_rst), .en (tlb_access_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_dtlb_rd_done = lsu_tlu_dtlb_done & (dtlb_data_rd_pend | dtlb_tag_rd_pend) ;
//assign itlb_rd_done = ifu_tlu_itlb_done & (itlb_data_rd_pend | itlb_tag_rd_pend) ;
// w2 should be renamed to g at some time !!!
// Write may take one extra cycle to get initiated !!!
assign itlb_wr_vld_unmsked = (itlb_wr_vld_g | (itlb_wr_pend & ~itlb_done_d1)) ;
wire pre_itlb_wr_vld_g ;
assign pre_itlb_wr_vld_g = (itlb_wr_pend & ~itlb_done_d1) & tlb_write_mode ;
//assign pre_itlb_wr_vld_g = itlb_wr_vld_unmsked & tlb_write_mode ;
// name kept as _g for now to avoid interface change.
assign tlu_itlb_wr_vld_g = pre_itlb_wr_vld_g ;
/*dff #(1) iwvld_d1 (
.din (pre_itlb_wr_vld_g),
.q (tlu_itlb_wr_vld_g),
.clk (clk),
.se (1'b0), .si (), .so ()
); */
assign tlu_itlb_data_rd_g = immu_data_access_rd_en | (itlb_data_rd_pend & ~itlb_done_d1) ;
assign tlu_itlb_tag_rd_g = (immu_tag_read_rd_en | immu_data_access_rd_en) | (itlb_tag_rd_pend & ~itlb_done_d1) ;
assign dtlb_wr_vld_unmsked = (dtlb_wr_vld_g | (dtlb_wr_pend & ~dtlb_done_d1)) ;
wire pre_dtlb_wr_vld_g ;
assign pre_dtlb_wr_vld_g = (dtlb_wr_pend & ~dtlb_done_d1) & tlb_write_mode ;
// name kept as _g for now to avoid interface change.
//assign tlu_dtlb_wr_vld_g = pre_dtlb_wr_vld_g ;
assign tlu_dtlb_data_rd_g = dmmu_data_access_rd_en | (dtlb_data_rd_pend & ~dtlb_done_d1) ;
assign tlu_dtlb_tag_rd_g = (dmmu_tag_read_rd_en | dmmu_data_access_rd_en) | (dtlb_tag_rd_pend & ~dtlb_done_d1) ;
// Delay by a cycle - rd for long-latency matches fast-asi.
// Both occur on a posedge.
wire dtlb_dmp_vld_g,itlb_dmp_vld_g;
assign dtlb_dmp_vld_g =
// qual with dtlb-done may not be needed. Taken into account in ddemap_pend.
(ddemap_pend & ~dtlb_done_d1) |
(dtlb_wr_vld_unmsked & tlb_admp_mode) ;
assign itlb_dmp_vld_g =
(idemap_pend & ~itlb_done_d1) |
(itlb_wr_vld_unmsked & tlb_admp_mode) ;
// dmp_vld should be w2. kept as _g for now to avoid
// interface change.
wire dtlb_dmp_vld_d1,itlb_dmp_vld_d1 ;
dff_s #(2) dmpvld_d1 (
.din ({dtlb_dmp_vld_g,itlb_dmp_vld_g}),
.q ({dtlb_dmp_vld_d1,itlb_dmp_vld_d1}),
.clk (clk),
.se (1'b0), .si (), .so ()
);
assign tlu_dtlb_dmp_vld_g = dtlb_dmp_vld_d1 & ~dtlb_done_d1 ;
assign tlu_itlb_dmp_vld_g = itlb_dmp_vld_d1 & ~itlb_done_d1 ;
wire stxa_ack ;
// Assume mutually exclusive.
// Third term is meant to complete demap with reserved ctxt.
assign stxa_ack =
(((itlb_wr_pend | dtlb_wr_pend) & ~(tlb_admp_mode | tlb_admp_mode_d1)) |
idemap_pend | ddemap_pend | immu_inv_all_pend | dmmu_inv_all_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done) |
(demap_resrv & tlb_st_inst_g &
((immu_demap_en & ~idemap_all) | (dmmu_demap_en & ~ddemap_all))) | //5053
(demap_sctxt & tlb_st_inst_g & (immu_demap_en & ~idemap_all)) | // Bug5053
// iside should not use sctxt
// lng-latency store needs to signal cmplt to lsu even with illegal va
(tlb_st_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;
dff_s #(1) stack_d1 (
.din (stxa_ack),
.q (tlu_lsu_stxa_ack),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
// AUTODEMAP
//=========================================================================================
assign tlb_wr_vld_g = itlb_wr_vld_unmsked | dtlb_wr_vld_unmsked ;
assign tlb_admp_en = tlb_wr_vld_g & ~tlb_admp_mode & ~tlb_write_mode ;
assign tlb_admp_rst = ~rst_l |
(((itlb_wr_pend | dtlb_wr_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done)) & tlb_admp_mode) ;
assign tlb_wr_rst = ~rst_l |
(((itlb_wr_pend | dtlb_wr_pend) & (lsu_tlu_dtlb_done | ifu_tlu_itlb_done))
& tlb_write_mode & ~tlb_admp_mode_d1) ;
assign tlu_admp_key_sel = (dtlb_wr_vld_g | itlb_wr_vld_g) | tlb_admp_mode ;
// 1st Phase - Autodemap
dffre_s #(1) dmp1_ff (
.din (tlb_wr_vld_g),
.q (tlb_admp_mode),
.rst (tlb_admp_rst), .en (tlb_admp_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// this is temporary - IFU is spuriously sourcing extra done signal.
dff_s #(1) admp_d1 (
.din (tlb_admp_mode),
.q (tlb_admp_mode_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// 2nd Phase - Follow-up with Write
dffre_s #(1) dmp2_ff (
.din (tlb_admp_rst),
.q (tlb_write_mode),
.rst (tlb_wr_rst), .en (tlb_admp_rst),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
wire tlu_ldxa_async_data_vld ;
assign tlu_ldxa_async_data_vld =
tlu_dtlb_rd_done |
(tlb_ld_inst_unflushed & (dmmu_async_illgl_va_g | immu_async_illgl_va_g)) ;
assign tlu_dldxa_data_vld =
// ** need to qualify with inst_vld in LSU
((dmmu_tag_target_en_m |
dmmu_8k_ptr_en_m |
dmmu_64k_ptr_en_m |
dmmu_direct_ptr_en_m |
dmmu_tsb_en_m |
dmmu_tag_access_en_m |
dmmu_sync_fsr_en_m |
dmmu_sync_far_en_m |
dmmu_ctxt_cfg_en_m) & ld_inst_m) ;
//tlu_dtlb_rd_done | // complete thru lsu
// for sync/async lng-latency ldxa with illegal va
// MMU_ASI
//(ld_inst_g & dmmu_sync_illgl_va_g) |
//(tlb_ld_inst_unflushed & dmmu_async_illgl_va_g) ;
assign tlu_ildxa_data_vld =
// ** need to qualify with inst_vld in LSU
((immu_tag_target_en_m |
immu_8k_ptr_en_m |
immu_64k_ptr_en_m |
immu_tsb_en_m |
immu_tag_access_en_m |
immu_sync_fsr_en_m |
immu_ctxt_cfg_en_m) & ld_inst_m) ;
// for sync/async lng-latency ldxa with illegal va
// MMU_ASI
//(ld_inst_g & immu_sync_illgl_va_g) |
//(tlb_ld_inst_unflushed & immu_async_illgl_va_g) ;
assign tlu_ldxa_data_vld = tlu_ildxa_data_vld | tlu_dldxa_data_vld ;
// Flush needs to be removed.
assign lsu_exu_ldxa_m = tlu_ldxa_data_vld & ~(dmmu_sync_illgl_va_m | immu_sync_illgl_va_m);
dff_s #(1) stg_asyncdvld (
.din (tlu_ldxa_async_data_vld),
.q (tlu_lsu_ldxa_async_data_vld),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
// SFSR/SFAR Control
//=========================================================================================
// In tcl
//=========================================================================================
// PS0 and PS1 Ptr Registers (NEW !!!!)
//=========================================================================================
// If N=TSB_Size, P=Page_Size, then
// Ptr = TSB_Base<63:13+N> | VA<21+N+3xP:13+3xP> | 0000 if TSB not split
// Ptr = TSB_Base<63:14+N> | 0 | VA<21+N+3xP:13+3xP> | 0000 if TSB split
// Assume P=0(8K),1(64K),3(4M),5(256M).
// Note that Nmax=11 even though N=0..15, for 256M page. This is because VA cannot exceed 47 for ms bit.
// Otherwise entire range of N can be covered by all 3 remaining page-size.
// Timing :
//
// | D-stage | E-stage | M-stage | W-stage |
// | Read setup | Read + | Logic + | Latched in |
// | to mra | Logic | xmit | LSU. Select|
// | | | | for wr-back|
//
// TSB Size Logic - Form 8 bits for 8k and 64k Ptr regs respectively.
// Macrotest support for logic in shadow of mra scan collar.
// Scan only. Scan value valid in 2nd cycle of macrotest.
wire mtest_rdps0_sel ;
dff_s #(1) rps0d_d1 (
.din (1'b0),
.q (mtest_rdps0_sel),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
wire tsb_rd_ps0_sel ;
assign tlu_tsb_rd_ps0_sel = tsb_rd_ps0_sel ;
assign tsb_rd_ps0_sel =
((dmmu_8k_ptr_e | immu_8k_ptr_e |
// really _m stage.
dmmu_direct_8kptr_sel_g) & ~sehold_d1) | // direct-ptr selects ps0
(mtest_rdps0_sel & sehold_d1) ;
// Choose between zero and non-zero context
assign tsb_size[3:0] =
tsb_rd_ps0_sel ? tlu_dtsb_size_w2[3:0] : tlu_itsb_size_w2[3:0] ;
assign tsb_split =
tsb_rd_ps0_sel ? tlu_dtsb_split_w2 : tlu_itsb_split_w2 ;
// Mux'ed and staged in mmu_dp.
assign tag_access[47:13] = tlu_dtag_access_w2[47:13] ;
wire [2:0] page_size,tsb_page_size_g ;
assign page_size[2:0] = tsb_page_size_g[2:0] ;
// Currently, all the logic is done in one stage. This will have to
// be rearranged once the read of the mra is advanced.
wire pg8k,pg64k,pg4M;
assign pg8k = ~page_size[2] & ~page_size[1] & ~page_size[0] ; // 000
assign pg64k = ~page_size[2] & ~page_size[1] & page_size[0] ; // 001
assign pg4M = ~page_size[2] & page_size[1] & page_size[0] ; // 011
//assign pg256M = page_size[2] & ~page_size[1] & page_size[0] ; // 101
// Mux tag-access <36:13>,<39:13>,<45:22>,<51:28> based on page-size.
// Notebook contains greater detail of mapping of base,tag-access to ptr.
wire [23:0] va ;
assign va[23:0] = pg8k ? tag_access[36:13] :
pg64k ? tag_access[39:16] :
pg4M ? tag_access[45:22] :
{{5{tag_access[47]}},tag_access[46:28]} ;// 256M
//{4'b0000,tag_access[47:28]} ; // 256M // Bug3727
// The ptr address is broken up into 3 regions :
// ptr<3:0>=4'b0000, : constant
// ptr<12:4>=va<8:0> : va from tag-access only
// ptr<27:13>=va<23:9>/base<27:13>/0/1 : va from tag-access OR tsb base address OR '0/1' (split).
// ptr<28>=base<28>/0/1 : tsb base address OR '0' (split).
// ptr<47:29>=base<47:29> : tsb base address.
// Assuming N=0..15. Could be reduced to N=11.
// Need to take exception for unused page size and value of N not compatible with selected page-size.
wire [28:13] ptr ;
wire ps1;
assign ps1 = ~tsb_rd_ps0_sel ;
// This is an obvious flop boundary break.
wire [3:0] tsb_size_d1 ;
wire tsb_split_d1 ;
wire [47:13] tsb_base_d1 ;
wire ps1_d1 ;
wire [23:0] va_d1 ;
dff_s #(4) tsbsize_stgd1 (
.din (tsb_size[3:0]),
.q (tsb_size_d1[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
dff_s #(1) tsbsplit_stgd1 (
.din (tsb_split),
.q (tsb_split_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
assign tsb_base_d1[47:13] = tlu_tsb_base_w2_d1[47:13] ;
dff_s #(1) ps1_stgd1 (
.din (ps1),
.q (ps1_d1),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
dff_s #(24) va_stgd1 (
.din (va[23:0]),
.q (va_d1[23:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
) ;
// These equations have to be optimized.
assign ptr[28] = ((tsb_size_d1==4'd15) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[28] ;
assign ptr[27] = (tsb_size_d1==4'd15) ? va_d1[23] : ((tsb_size_d1==4'd14) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[27] ;
assign ptr[26] = (tsb_size_d1>=4'd14) ? va_d1[22] : ((tsb_size_d1==4'd13) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[26] ;
assign ptr[25] = (tsb_size_d1>=4'd13) ? va_d1[21] : ((tsb_size_d1==4'd12) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[25] ;
assign ptr[24] = (tsb_size_d1>=4'd12) ? va_d1[20] : ((tsb_size_d1==4'd11) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[24] ;
assign ptr[23] = (tsb_size_d1>=4'd11) ? va_d1[19] : ((tsb_size_d1==4'd10) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[23] ;
assign ptr[22] = (tsb_size_d1>=4'd10) ? va_d1[18] : ((tsb_size_d1==4'd9) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[22] ;
assign ptr[21] = (tsb_size_d1>=4'd9) ? va_d1[17] : ((tsb_size_d1==4'd8) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[21] ;
assign ptr[20] = (tsb_size_d1>=4'd8) ? va_d1[16] : ((tsb_size_d1==4'd7) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[20] ;
assign ptr[19] = (tsb_size_d1>=4'd7) ? va_d1[15] : ((tsb_size_d1==4'd6) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[19] ;
assign ptr[18] = (tsb_size_d1>=4'd6) ? va_d1[14] : ((tsb_size_d1==4'd5) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[18] ;
assign ptr[17] = (tsb_size_d1>=4'd5) ? va_d1[13] : ((tsb_size_d1==4'd4) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[17] ;
assign ptr[16] = (tsb_size_d1>=4'd4) ? va_d1[12] : ((tsb_size_d1==4'd3) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[16] ;
assign ptr[15] = (tsb_size_d1>=4'd3) ? va_d1[11] : ((tsb_size_d1==4'd2) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[15] ;
assign ptr[14] = (tsb_size_d1>=4'd2) ? va_d1[10] : ((tsb_size_d1==4'd1) & tsb_split_d1) ? ps1_d1 : tsb_base_d1[14] ;
assign ptr[13] = (tsb_size_d1>=4'd1) ? va_d1[9] : tsb_split_d1 ? ps1_d1 : tsb_base_d1[13] ;
// TSB 8K Ptr. This maps to tsb ps0 ptr !!!
// This is mapped to either PS0 or PS1 ptr. Do not need to send
// 8k and 64K ptrs to mmu_dp.
// Direct ptr needs to be accounted for.
assign tlu_idtsb_8k_ptr[47:0] =
{tsb_base_d1[47:29],
ptr[28:13],
va_d1[8:0],
4'b0000};
//=========================================================================================
// Establishing Context for Ptr Read
//=========================================================================================
// Context of Ptr Read determined by context within d/i tag-access register.
// Markers per thread will be maintained to determine whether any subsequent
// ptr access is made in nucleus or non-nucleus context.
// Note i and d tag-access can be merged within tlu_mmu_dp.v
// write of tag-access ctxt needs to be setup in M for subsequent read of MRA in M.
assign tsb_page_size_g[2:0] = tsb_rd_ps0_sel ? tlu_ctxt_cfg_w2[2:0] : tlu_ctxt_cfg_w2[5:3] ;
// Listening Flops for Macrotest of mra.
dff_s #(6) ctxtcfg_listen (
.din (tlu_ctxt_cfg_w2[5:0]),
.q (),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
// Direct Ptr State
//=========================================================================================
// For new ptr support, if page-size of tte matches that of ps1 then
// direct-ptr maps to ps1-ptr else ps0-ptr.
wire daccess_prot_qual ;
assign daccess_prot_qual =
lsu_tlu_daccess_prot_g & ~lsu_tlu_daccess_excptn_g &
inst_vld_g & ~(priority_squash_g | flush_mmuasi_wr) ;
// For SPARC_HPV_EN, 64k represents ps1 ptr.
assign dptr0_pg64k_en = daccess_prot_qual & thread0_sel_g ;
assign dptr1_pg64k_en = daccess_prot_qual & thread1_sel_g ;
assign dptr2_pg64k_en = daccess_prot_qual & thread2_sel_g ;
assign dptr3_pg64k_en = daccess_prot_qual & thread3_sel_g ;
// For SPARC_HPV_EN this means ps0 sel. This should be an internal
// wire with SPARC_HPV_EN
assign dmmu_direct_8kptr_sel_g =
dmmu_direct_ptr_e & ((thread0_e & ~dptr0_pg64k_vld) |
(thread1_e & ~dptr1_pg64k_vld) |
(thread2_e & ~dptr2_pg64k_vld) |
(thread3_e & ~dptr3_pg64k_vld));
wire dptr_state_din ;
assign dptr_state_din = dacc_prot_ps1_match ;
dffre_s #(1) dptrstate_0 (
.din (dptr_state_din),
.q (dptr0_pg64k_vld),
.rst (~rst_l), .en (dptr0_pg64k_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(1) dptrstate_1 (
.din (dptr_state_din),
.q (dptr1_pg64k_vld),
.rst (~rst_l), .en (dptr1_pg64k_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(1) dptrstate_2 (
.din (dptr_state_din),
.q (dptr2_pg64k_vld),
.rst (~rst_l), .en (dptr2_pg64k_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
dffre_s #(1) dptrstate_3 (
.din (dptr_state_din),
.q (dptr3_pg64k_vld),
.rst (~rst_l), .en (dptr3_pg64k_en),
.clk (clk),
.se (1'b0), .si (), .so ()
);
//=========================================================================================
// PS1 PAGE SIZE FOR DMMU
//=========================================================================================
// Maintain ps1 page-size for dmmu zero/non-zero ctxt. This is required to compare
// against the page-size of the tte on a data-access-protection to set-up the
// direct-pointer. Note that the real copy is in the mra.
wire [2:0] zctxt_cfg0_ps1,zctxt_cfg1_ps1,zctxt_cfg2_ps1,zctxt_cfg3_ps1;
wire [2:0] nzctxt_cfg0_ps1,nzctxt_cfg1_ps1,nzctxt_cfg2_ps1,nzctxt_cfg3_ps1;
wire [3:0] dzctxt_cfg_wr_en ;
wire [3:0] dnzctxt_cfg_wr_en ;
assign dzctxt_cfg_wr_en[3] = dmmu_zctxt_cfg_en & st_inst_g & thread3_sel_g ;
assign dzctxt_cfg_wr_en[2] = dmmu_zctxt_cfg_en & st_inst_g & thread2_sel_g ;
assign dzctxt_cfg_wr_en[1] = dmmu_zctxt_cfg_en & st_inst_g & thread1_sel_g ;
assign dzctxt_cfg_wr_en[0] = dmmu_zctxt_cfg_en & st_inst_g & thread0_sel_g ;
assign dnzctxt_cfg_wr_en[3] = dmmu_nzctxt_cfg_en & st_inst_g & thread3_sel_g ;
assign dnzctxt_cfg_wr_en[2] = dmmu_nzctxt_cfg_en & st_inst_g & thread2_sel_g ;
assign dnzctxt_cfg_wr_en[1] = dmmu_nzctxt_cfg_en & st_inst_g & thread1_sel_g ;
assign dnzctxt_cfg_wr_en[0] = dmmu_nzctxt_cfg_en & st_inst_g & thread0_sel_g ;
// Thread0
// Zero-Ctxt Cfg PS1
dffe_s #(3) zctxtps1_0 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (zctxt_cfg0_ps1[2:0]),
.en (dzctxt_cfg_wr_en[0]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Non-Zero-Ctxt Cfg PS1
dffe_s #(3) nzctxtps1_0 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (nzctxt_cfg0_ps1[2:0]),
.en (dnzctxt_cfg_wr_en[0]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread1
// Zero-Ctxt Cfg PS1
dffe_s #(3) zctxtps1_1 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (zctxt_cfg1_ps1[2:0]),
.en (dzctxt_cfg_wr_en[1]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Non-Zero-Ctxt Cfg PS1
dffe_s #(3) nzctxtps1_1 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (nzctxt_cfg1_ps1[2:0]),
.en (dnzctxt_cfg_wr_en[1]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread2
// Zero-Ctxt Cfg PS1
dffe_s #(3) zctxtps1_2 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (zctxt_cfg2_ps1[2:0]),
.en (dzctxt_cfg_wr_en[2]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Non-Zero-Ctxt Cfg PS1
dffe_s #(3) nzctxtps1_2 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (nzctxt_cfg2_ps1[2:0]),
.en (dnzctxt_cfg_wr_en[2]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Thread3
// Zero-Ctxt Cfg PS1
dffe_s #(3) zctxtps1_3 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (zctxt_cfg3_ps1[2:0]),
.en (dzctxt_cfg_wr_en[3]), .clk (clk),
.se (1'b0), .si (), .so ()
);
// Non-Zero-Ctxt Cfg PS1
dffe_s #(3) nzctxtps1_3 (
.din (lsu_tlu_st_rs3_data_b12t0_g[10:8]),
.q (nzctxt_cfg3_ps1[2:0]),
.en (dnzctxt_cfg_wr_en[3]), .clk (clk),
.se (1'b0), .si (), .so ()
);
wire [2:0] zctxt_cfg_ps1,nzctxt_cfg_ps1 ;
assign zctxt_cfg_ps1[2:0] =
thread0_sel_g ? zctxt_cfg0_ps1[2:0] :
thread1_sel_g ? zctxt_cfg1_ps1[2:0] :
thread2_sel_g ? zctxt_cfg2_ps1[2:0] :
zctxt_cfg3_ps1[2:0] ;
assign nzctxt_cfg_ps1[2:0] =
thread0_sel_g ? nzctxt_cfg0_ps1[2:0] :
thread1_sel_g ? nzctxt_cfg1_ps1[2:0] :
thread2_sel_g ? nzctxt_cfg2_ps1[2:0] :
nzctxt_cfg3_ps1[2:0] ;
wire nucleus_ctxt_g ;
dff_s nctxt_stgg(
.din (lsu_tlu_nucleus_ctxt_m),
.q (nucleus_ctxt_g),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire [2:0] ctxt_cfg_ps1 ;
assign ctxt_cfg_ps1[2:0] =
nucleus_ctxt_g ? zctxt_cfg_ps1[2:0] : nzctxt_cfg_ps1[2:0] ;
assign dacc_prot_ps1_match
= (lsu_tlu_tte_pg_sz_g[2:0] == ctxt_cfg_ps1[2:0]) ;
//=========================================================================================
// CTXT SEL
//=========================================================================================
wire thread_tl_zero_e,thread_tl_zero_m ;
assign thread_tl_zero_e =
thread0_e ? tlu_lsu_tl_zero[0] :
thread1_e ? tlu_lsu_tl_zero[1] :
thread2_e ? tlu_lsu_tl_zero[2] : tlu_lsu_tl_zero[3];
dff_s tlz_stgm(
.din (thread_tl_zero_e),
.q (thread_tl_zero_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
// Generate selects for ctxt to be written to tag_access
// iside trap meant to cover immu_miss and inst_access_excp
// modified for hypervisor support
// assign iside_trap = exu_tlu_ttype_vld_m | immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m;
wire pstate_am_e,pstate_am_m;
assign pstate_am_e =
(thread0_e & tlu_lsu_pstate_am[0]) |
(thread1_e & tlu_lsu_pstate_am[1]) |
(thread2_e & tlu_lsu_pstate_am[2]) |
(thread3_e & tlu_lsu_pstate_am[3]);
dff_s pam_stgm(
.din (pstate_am_e),
.q (pstate_am_m),
.clk (clk),
.se (1'b0), .si (), .so ()
);
wire immu_va_oor_brnchetc_m ;
assign immu_va_oor_brnchetc_m
= exu_tlu_va_oor_m & ~pstate_am_m & ~memref_m;
wire iside_trap ;
assign iside_trap =
ifu_tlu_immu_miss_m | // exu_tlu_ttype_vld_m : Rm along with Bug 5346
immu_va_oor_brnchetc_m | exu_tlu_va_oor_jl_ret_m |
ifu_tlu_priv_violtn_m ; // Bug 5346.
assign tlu_tag_access_ctxt_sel_m[0] = iside_trap & thread_tl_zero_m;
assign tlu_tag_access_ctxt_sel_m[1] = iside_trap & ~thread_tl_zero_m;
assign tlu_tag_access_ctxt_sel_m[2] = ~iside_trap;
//=========================================================================================
// TLB Write Data
//=========================================================================================
wire [2:0] pg_size ;
wire page_8k, page_64k, page_4m ;
wire va_15_13_vld, va_21_16_vld, va_27_22_vld ;
assign sun4r_tte_g = ~tlb_ldst_va_g[10] ;
assign tlu_sun4r_tte_g = sun4r_tte_g ;
assign pg_size[2:0] =
sun4r_tte_g ? {lsu_tlu_st_rs3_data_b48_g,lsu_tlu_st_rs3_data_g[62:61]} :
{lsu_tlu_st_rs3_data_b12t0_g[2:0]} ;
assign page_8k = ~pg_size[2] & ~pg_size[1] & ~pg_size[0] ;
assign page_64k = ~pg_size[2] & ~pg_size[1] & pg_size[0] ;
assign page_4m = ~pg_size[2] & pg_size[1] & pg_size[0] ;
//assign page_256m = pg_size[2] & ~pg_size[1] & pg_size[0] ;
assign va_15_13_vld = page_8k ;
assign va_21_16_vld = page_8k | page_64k ;
assign va_27_22_vld = page_8k | page_64k | page_4m ;
assign tlu_tte_tag_g[2:0] = {va_27_22_vld,va_21_16_vld,va_15_13_vld} ;
assign thread0_async_g = ~tlb_access_tid_g[1] & ~tlb_access_tid_g[0] ;
assign thread1_async_g = ~tlb_access_tid_g[1] & tlb_access_tid_g[0] ;
assign thread2_async_g = tlb_access_tid_g[1] & ~tlb_access_tid_g[0] ;
//assign thread3_async_g = tlb_access_tid_g[1] & tlb_access_tid_g[0] ; // to be used in instanced mux
assign tlu_tte_wr_pid_g[2:0] =
thread0_async_g ? lsu_pid_state0[2:0] :
thread1_async_g ? lsu_pid_state1[2:0] :
thread2_async_g ? lsu_pid_state2[2:0] : lsu_pid_state3[2:0] ;
// Error Injection :
// Error injection is one-shot. It will occur for either dmmu or immu. The ifu
// is informed once the error injection is accomplished.
wire i_tag_invrt_par,d_tag_invrt_par ;
wire i_data_invrt_par,d_data_invrt_par ;
assign tlu_tlb_tag_invrt_parity = i_tag_invrt_par | d_tag_invrt_par ;
assign i_tag_invrt_par = (ifu_lsu_error_inj[2] & (immu_data_in_en | immu_data_access_en)) ;
assign d_tag_invrt_par = (ifu_lsu_error_inj[0] & (dmmu_data_in_en | dmmu_data_access_en)) ;
assign tlu_tlb_data_invrt_parity = i_data_invrt_par | d_data_invrt_par ;
assign i_data_invrt_par = (ifu_lsu_error_inj[3] & (immu_data_in_en | immu_data_access_en)) ;
assign d_data_invrt_par = (ifu_lsu_error_inj[1] & (dmmu_data_in_en | dmmu_data_access_en)) ;
wire tlb_wr_vld ;
assign tlb_wr_vld = dtlb_wr_vld_g | itlb_wr_vld_g ;
wire [3:0] err_inj_ack ;
assign err_inj_ack[0] = tlb_wr_vld & d_tag_invrt_par ;
assign err_inj_ack[1] = tlb_wr_vld & d_data_invrt_par ;
assign err_inj_ack[2] = tlb_wr_vld & i_tag_invrt_par ;
assign err_inj_ack[3] = tlb_wr_vld & i_data_invrt_par ;
dff_s #(4) err_inj (
.din (err_inj_ack[3:0]),
.q (lsu_ifu_inj_ack[3:0]),
.clk (clk),
.se (1'b0), .si (), .so ()
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_rptr_b.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_rptr_b(out21 ,out20 ,out19 ,out18 ,out17 ,out16 ,out15
,out14 ,out13 ,out12 ,out10 ,out9 ,out8 ,out6 ,out5 ,out4 ,out3 ,
out2 ,in21 ,in20 ,in19 ,in18 ,in17 ,in16 ,in15 ,in14 ,in13 ,in12 ,
out1 ,out0 ,in10 ,in22 ,out22 ,in24 ,out24 ,out25 ,vdd18 ,in25 ,in2
,in5 ,in1 ,in4 ,in9 ,out11 ,in3 ,in11 ,in0 ,in6 ,in8 );
output [8:1] out14 ;
output [8:1] out13 ;
output [1:0] out10 ;
output [1:0] out9 ;
output [1:0] out4 ;
output [4:0] out1 ;
output [7:0] out25 ;
input [8:1] in14 ;
input [8:1] in13 ;
input [1:0] in10 ;
input [7:0] in25 ;
input [4:0] in1 ;
input [1:0] in4 ;
input [1:0] in9 ;
output out21 ;
output out20 ;
output out19 ;
output out18 ;
output out17 ;
output out16 ;
output out15 ;
output out12 ;
output out8 ;
output out6 ;
output out5 ;
output out3 ;
output out2 ;
output out0 ;
output out22 ;
output out24 ;
output out11 ;
input in21 ;
input in20 ;
input in19 ;
input in18 ;
input in17 ;
input in16 ;
input in15 ;
input in12 ;
input in22 ;
input in24 ;
input vdd18 ;
input in2 ;
input in5 ;
input in3 ;
input in11 ;
input in0 ;
input in6 ;
input in8 ;
bw_u1_buf_30x I10_1_ (
.z (out9[1] ),
.a (in9[1] ) );
bw_u1_buf_30x I0 (
.z (out2 ),
.a (in2 ) );
bw_u1_buf_30x I1 (
.z (out3 ),
.a (in3 ) );
bw_u1_buf_30x I65_2_ (
.z (out1[2] ),
.a (in1[2] ) );
bw_u1_buf_30x I4 (
.z (out6 ),
.a (in6 ) );
bw_u1_buf_30x I5 (
.z (out5 ),
.a (in5 ) );
bw_u1_buf_30x I34_1_ (
.z (out13[1] ),
.a (in13[1] ) );
bw_u1_buf_30x I6 (
.z (out11 ),
.a (in11 ) );
bw_u1_buf_30x I35_7_ (
.z (out14[7] ),
.a (in14[7] ) );
bw_u1_buf_30x I7 (
.z (out12 ),
.a (in12 ) );
bw_u1_buf_30x I66 (
.z (out0 ),
.a (in0 ) );
bw_u1_buf_30x I65_3_ (
.z (out1[3] ),
.a (in1[3] ) );
bw_u1_buf_30x I34_2_ (
.z (out13[2] ),
.a (in13[2] ) );
bw_u1_buf_30x I35_8_ (
.z (out14[8] ),
.a (in14[8] ) );
bw_u1_buf_30x I65_4_ (
.z (out1[4] ),
.a (in1[4] ) );
bw_u1_buf_30x I34_3_ (
.z (out13[3] ),
.a (in13[3] ) );
bw_u1_buf_30x I35_1_ (
.z (out14[1] ),
.a (in14[1] ) );
bw_u1_buf_30x I9_0_ (
.z (out10[0] ),
.a (in10[0] ) );
bw_u1_buf_30x I11 (
.z (out8 ),
.a (in8 ) );
bw_u1_buf_30x I34_4_ (
.z (out13[4] ),
.a (in13[4] ) );
bw_u1_buf_30x I35_2_ (
.z (out14[2] ),
.a (in14[2] ) );
bw_u1_buf_30x I9_1_ (
.z (out10[1] ),
.a (in10[1] ) );
bw_u1_buf_30x I34_5_ (
.z (out13[5] ),
.a (in13[5] ) );
bw_u1_buf_30x I35_3_ (
.z (out14[3] ),
.a (in14[3] ) );
bw_u1_buf_30x I2_0_ (
.z (out4[0] ),
.a (in4[0] ) );
bw_u1_buf_30x I102 (
.z (out22 ),
.a (in22 ) );
bw_u1_buf_30x I34_6_ (
.z (out13[6] ),
.a (in13[6] ) );
bw_u1_buf_30x I35_4_ (
.z (out14[4] ),
.a (in14[4] ) );
bw_u1_buf_30x I36 (
.z (out15 ),
.a (in15 ) );
bw_u1_buf_30x I37 (
.z (out16 ),
.a (in16 ) );
bw_u1_buf_30x I38 (
.z (out17 ),
.a (in17 ) );
bw_u1_buf_30x I39 (
.z (out19 ),
.a (in19 ) );
bw_u1_buf_30x I110 (
.z (out24 ),
.a (in24 ) );
bw_u1_buf_30x I65_0_ (
.z (out1[0] ),
.a (in1[0] ) );
bw_u1_buf_30x I2_1_ (
.z (out4[1] ),
.a (in4[1] ) );
bw_u1_buf_30x I40 (
.z (out18 ),
.a (in18 ) );
bw_u1_buf_30x I41 (
.z (out20 ),
.a (in20 ) );
bw_u1_buf_30x I42 (
.z (out21 ),
.a (in21 ) );
bw_io_ddr_vref_rptr I115 (
.out ({out25 } ),
.in ({in25 } ),
.vdd18 (vdd18 ) );
bw_u1_buf_30x I34_7_ (
.z (out13[7] ),
.a (in13[7] ) );
bw_u1_buf_30x I35_5_ (
.z (out14[5] ),
.a (in14[5] ) );
bw_u1_buf_30x I10_0_ (
.z (out9[0] ),
.a (in9[0] ) );
bw_u1_buf_30x I65_1_ (
.z (out1[1] ),
.a (in1[1] ) );
bw_u1_buf_30x I34_8_ (
.z (out13[8] ),
.a (in13[8] ) );
bw_u1_buf_30x I35_6_ (
.z (out14[6] ),
.a (in14[6] ) );
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:29:20 10/26/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(
input clk,
input reset,
input rx,
input fsm,
output [2:0] Led,
output tx
);
`define TXreg 3'b001
`define controltx 3'b011
`define RXreg 3'b101
`define controlrx 3'b111
`define NOTREADY 3'b000
`define WAITRX 3'b001
`define TRANS 3'b010
`define PASSTX 3'b011
`define CHECKTX 3'b100
`define PASSTX1 3'b101
`define STOP 3'b111
`define RXREADY dout[1]
reg wr_tx, rd_tx, wr_rx, rd_rx, rx_sel, tx_sel, finished, dadd, clr;
reg [7:0] data;
wire [7:0] ready, dout_tx;
wire [8:0] dout_rx;
reg [2:0] addr_rx, addr_tx;
reg [2:0] nstate, pstate, dout;
reg [1:0] trans;
assign ready = 8'b00000001;
uart_tx #(.PERIOD(8'h1A)) out(
.clk (clk),
.reset (reset),
.wren (wr_tx),
.rden (rd_tx),
.din (data),
.dout (dout_tx),
.txout (tx),
.addr (addr_tx));
uart_rx #(.PERIOD(8'h1A)) in(
.clk (clk),
.reset (reset),
.wren (wr_rx),
.rden (rd_rx),
.din (ready),
.dout (dout_rx),
.rxin (rx),
.addr (addr_rx));
// adder
always @(posedge clk or posedge reset) begin
if(reset)
data <= 8'b11111111;
else begin
if(rx_sel)
data <= dout_rx + 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if(reset)
dout = dout_rx[2:0];
else begin
if(dadd)
dout = dout_tx[2:0];
else
dout = dout_rx[2:0];
end
end
assign Led[0] = dout[0];
assign Led[1] = dout[1];
assign Led[2] = data[2];
always @* begin
addr_rx = `controlrx;
case(rx_sel)
1'b1:
addr_rx = `RXreg;
endcase
end
always @* begin
if(tx_sel)
addr_tx = `TXreg;
else
addr_tx = `controltx;
end
//trans clock
always @(posedge clk or posedge reset) begin
if(reset)
trans <= 2'b00;
else begin
trans <= trans + 1;
if(clr)
trans <= 2'b00;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `NOTREADY;
else
pstate <= nstate;
end
// fsm
always @* begin
wr_tx = 0; wr_rx = 0;
rd_tx = 0; rd_tx = 0;
rx_sel = 0; tx_sel = 0;
finished = 0; clr = 0;
nstate = pstate;
case (pstate)
`NOTREADY: begin
wr_rx = 1;
nstate = `WAITRX;
end
`WAITRX: begin
rd_rx = 1;
if(`RXREADY) begin
nstate = `TRANS;
clr = 1;
end
end
`TRANS: begin
if(trans == 2'b11) begin
rd_rx = 1;
rx_sel = 1;
nstate = `PASSTX;
end
end
`PASSTX: begin
rd_rx = 1;
rx_sel = 1;
nstate = `PASSTX1;
end
`PASSTX1: begin
wr_tx = 1;
tx_sel = 1;
nstate = `STOP;
end
`STOP: begin
nstate = `STOP;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/14/2016 06:25:09 AM
// Design Name:
// Module Name: Exp_operation_m
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation_m
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//underflow
input wire load_b_i,//overflow
input wire load_c_i,//result
input wire [EW:0] Data_A_i,
input wire [EW:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
///////////////////////////////////////////////
wire [EW:0] Data_S;
wire Overflow_A;
wire Overflow_flag_A;
wire underflow_exp_reg;
wire [EW:0] U_Limit;
/////////////////////////////Exponent calculation///
add_sub_carry_out #(.W(EW+1)) exp_add_subt_m(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S ({Overflow_A,Data_S})
);
RegisterMult #(.W(EW+1)) exp_result_m(
.clk (clk),
.rst (rst),
.load (load_c_i),
.D (Data_S),
.Q (Data_Result_o)
);
//Overflow/////////////////////////////////
RegisterMult#(.W(1)) Oflow_A_m (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Overflow_A),
.Q(Overflow_flag_A)
);
assign Overflow_flag_o = Overflow_flag_A | Data_Result_o[EW];
//Underflow//////////////////////////////
Comparator_Less #(.W(EW+1)) Exp_unflow_Comparator_m (
.Data_A(Data_S),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) Underflow_m (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(underflow_exp_reg),
.Q(Underflow_flag_o)
);
//Este valor de upper_limit es definido por la precision del formato
// 127 para simple
//1023 para doble
localparam integer Upper_limit = (2**(EW-1)-1);
assign U_Limit = Upper_limit[EW:0];
//generate
// if (EW == 8)
// assign U_Limit = 9'd127;
// else
// assign U_Limit = 12'd1023;
//endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
`define SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
/**
* probec_p: Virtual current probe point.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probec_p (
X,
A
);
output X;
input A;
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_FUNCTIONAL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: SILAB , Physics Institute of Bonn University
// Engineer: Viacheslav Filimonov
//
// Create Date: 10:40:28 12/16/2013
// Design Name:
// Module Name: KX7_IF_Test_Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module KX7_IF_Test_Top(
// FX 3 interface
input wire fx3_pclk_100MHz,
(* IOB = "FORCE" *) input wire fx3_wr, // force IOB register
(* IOB = "FORCE" *) input wire fx3_cs, // async. signal
(* IOB = "FORCE" *) input wire fx3_oe, // async. signal
input wire fx3_rst, // async. signal from FX3, active high
(* IOB = "FORCE" *) output wire fx3_ack, // force IOB register
(* IOB = "FORCE" *) output wire fx3_rdy, // force IOB register
// output wire reset_fx3,
inout wire [31:0] fx3_bus, // 32 bit databus
// 200 MHz oscillator
input wire sys_clk_p,
input wire sys_clk_n,
// 100 Mhz oscillator
input wire Clk100,
// GPIO
output wire [8:1] led,
(* IOB = "FORCE" *) output wire fx3_rd_finish,
input wire Reset_button,// async. signal
input wire FLAG1, // was DMA Flag; currently connected to TEST signal from FX3
(* IOB = "FORCE" *) input wire FLAG2, // DMA watermark flag for thread 2 of FX3
// Power supply regulators EN signals
output wire EN_VD1,
output wire EN_VD2,
output wire EN_VA1,
output wire EN_VA2,
// Command sequencer signals
output wire CMD_CLK_OUT,
(* IOB = "FORCE" *) output wire CMD_DATA,
// FE-I4_rx signals
(* IOB = "FORCE" *) input wire [3:0] DOBOUT,
// Over Current Protection (BIC only)
input wire [3:0] OC
);
//assign reset_fx3 = 1; // not to reset fx3 while loading fpga
assign EN_VD1 = 1;
assign EN_VD2 = 1;
assign EN_VA1 = 1;
assign EN_VA2 = 1;
wire [31:0] BUS_ADD;
wire [31:0] BUS_DATA;
wire BUS_RD, BUS_WR, BUS_RST, BUS_CLK;
//assign BUS_RST = (BUS_RST | (!LOCKED));
wire BUS_BYTE_ACCESS;
assign BUS_BYTE_ACCESS = (BUS_ADD < 32'h8000_0000) ? 1'b1 : 1'b0;
wire RST;
assign RST = ((fx3_rst)|(!LOCKED)|(!Reset_button)); // Button is acticve low
FX3_IF FX3_IF_inst (
.fx3_bus(fx3_bus),
.fx3_wr(fx3_wr),
.fx3_oe(fx3_oe),
.fx3_cs(fx3_cs),
.fx3_clk(fx3_pclk_100MHz),
.fx3_rdy(fx3_rdy),
.fx3_ack(fx3_ack),
.fx3_rd_finish(fx3_rd_finish),
.fx3_rst(RST), // PLL is reset first
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_BYTE_ACCESS(BUS_BYTE_ACCESS),
.FLAG1(FLAG1),
.FLAG2(FLAG2)
);
wire clk40mhz_pll, clk320mhz_pll, clk160mhz_pll, clk16mhz_pll;
wire pll_feedback, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(64), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(32), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT3_DIVIDE(80), // Divide amount for CLKOUT0 (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.DIVCLK_DIVIDE(5), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
// Generated 40 MHz clock
.CLKOUT0(clk40mhz_pll),
.CLKOUT1(clk320mhz_pll),
.CLKOUT2(clk160mhz_pll),
.CLKOUT3(clk16mhz_pll),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(pll_feedback),
.LOCKED(LOCKED), // 1-bit output: LOCK
// Input 100 MHz clock
.CLKIN1(BUS_CLK),
// Control Ports
.PWRDWN(0),
.RST(fx3_rst), // Reset from FX3
// Feedback
.CLKFBIN(pll_feedback)
);
wire clk40mhz, clk320mhz, clk160mhz, clk16mhz;
BUFG BUFG_inst_40 (
.O(clk40mhz), // Clock buffer output
.I(clk40mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_320 (
.O(clk320mhz), // Clock buffer output
.I(clk320mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_160 (
.O(clk160mhz), // Clock buffer output
.I(clk160mhz_pll) // Clock buffer input
);
BUFG BUFG_inst_16 (
.O(clk16mhz), // Clock buffer output
.I(clk16mhz_pll) // Clock buffer input
);
// ------- MODULE ADDRESSES ------- //
localparam CMD_BASEADDR = 32'h0000;
localparam CMD_HIGHADDR = 32'h8000-1;
localparam FIFO_BASEADDR = 32'h8100;
localparam FIFO_HIGHADDR = 32'h8200-1;
localparam RX4_BASEADDR = 32'h8300;
localparam RX4_HIGHADDR = 32'h8400-1;
localparam RX3_BASEADDR = 32'h8400;
localparam RX3_HIGHADDR = 32'h8500-1;
localparam RX2_BASEADDR = 32'h8500;
localparam RX2_HIGHADDR = 32'h8600-1;
localparam RX1_BASEADDR = 32'h8600;
localparam RX1_HIGHADDR = 32'h8700-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
// Command sequencer
wire CMD_EXT_START_FLAG;
assign CMD_EXT_START_FLAG = 0;
cmd_seq
#(
.BASEADDR(CMD_BASEADDR),
.HIGHADDR(CMD_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) icmd (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CMD_CLK_OUT(CMD_CLK_OUT),
.CMD_CLK_IN(clk40mhz),
.CMD_EXT_START_FLAG(CMD_EXT_START_FLAG),
.CMD_EXT_START_ENABLE(),
.CMD_DATA(CMD_DATA),
.CMD_READY(),
.CMD_START_FLAG()
);
// FE-I4 RXs
parameter DSIZE = 10;
wire [3:0] FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA [3:0];
//assign FIFO_READ = 0;
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: rx_gen
fei4_rx
#(
.BASEADDR(RX1_BASEADDR-32'h0100*i),
.HIGHADDR(RX1_HIGHADDR-32'h0100*i),
.DSIZE(DSIZE),
.DATA_IDENTIFIER(i+1),
.ABUSWIDTH(ABUSWIDTH)
) i_fei4_rx (
.RX_CLK(clk160mhz),
.RX_CLK2X(clk320mhz),
.DATA_CLK(clk16mhz),
.RX_DATA(DOBOUT[i]),
.RX_READY(led[i+1]),
.RX_8B10B_DECODER_ERR(),
.RX_FIFO_OVERFLOW_ERR(),
.FIFO_CLK(1'b0),
.FIFO_READ(FIFO_READ[i]),
.FIFO_EMPTY(FIFO_EMPTY[i]),
.FIFO_DATA(FIFO_DATA[i]),
.RX_FIFO_FULL(),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
end
endgenerate
// Arbiter
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire [3:0] READ_GRANT;
rrp_arbiter
#(
.WIDTH(4)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ(~FIFO_EMPTY),
.HOLD_REQ({4'b0}),
.DATA_IN({FIFO_DATA[3],FIFO_DATA[2],FIFO_DATA[1], FIFO_DATA[0]}),
.READ_GRANT(READ_GRANT),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
assign FIFO_READ = READ_GRANT[3:0];
// BRAM
wire FIFO_NOT_EMPTY, FIFO_FULL, FIFO_NEAR_FULL, FIFO_READ_ERROR;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(FIFO_NOT_EMPTY),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(FIFO_NEAR_FULL),
.FIFO_READ_ERROR(FIFO_READ_ERROR)
);
assign led[5] = FIFO_NOT_EMPTY;
assign led[6] = FIFO_FULL;
assign led[7] = FIFO_NEAR_FULL;
assign led[8] = FIFO_READ_ERROR;
/*
always @ (posedge BUS_CLK)
begin
if (BUS_RST)
begin
led[5] <= 0;
led[6] <= 0;
led[7] <= 0;
led[8] <= 0;
end
else
begin
if (FIFO_NOT_EMPTY)
led[5] <= 1;
else if (FIFO_FULL)
led[6] <= 1;
else if (FIFO_NEAR_FULL)
led[7] <= 1;
else if (FIFO_READ_ERROR)
led[8] <= 1;
end
end
*/
/*
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(led[8:1])
);
*/
/*
Register #(
.REG_SIZE(32),
.ADDRESS(1))
Reg1_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg1),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
Register #(
.REG_SIZE(32),
.ADDRESS(2))
Reg2_inst (
.D(DataIn),
.WR(WR),
.RD(RD),
.Addr(Addr),
.CLK(CLK_100MHz),
.Q(Reg2),
.RB(DataOut),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
.RST(RST)
);
BRAM_Test #(
.ADDRESS( 32'h10_00_00_00),
.MEM_SIZE(32'h00_00_40_00))
BRAM_Test_inst (
.DataIn(DataIn),
.WR(WR),
.RD(RD),
.CLK(CLK_100MHz),
.DataOut(DataOut),
.Addr(Addr[31:0]),
.RDYB(RDYB),
.RD_VALID_N(ACKB),
// .DMA_RDY(DMA_RDY),
.RST(RST)
);
DDR3_256_8 #(
.ADDRESS( 32'h20_00_00_00),
.MEM_SIZE(32'h10_00_00_00))
DDR3_256_8_inst (
.DataIn(DataIn[31:0]),
.WR(WR),
.RD(RD),
.Addr(Addr[31:0]),
.DataOut(DataOut[31:0]),
.RDY_N(RDYB),
.RD_VALID_N(ACKB),
.CLK_OUT(CLK_100MHz),
.RST(RST),
.Reset_button2(Reset_button2),
.INIT_COMPLETE(INIT_COMPLETE),
.ddr3_dq(ddr3_dq),
.ddr3_addr(ddr3_addr),
// .ddr3_dm(ddr3_dm),
.ddr3_dqs_p(ddr3_dqs_p),
.ddr3_dqs_n(ddr3_dqs_n),
.ddr3_ba(ddr3_ba),
.ddr3_ck_p(ddr3_ck_p),
.ddr3_ck_n(ddr3_ck_n),
.ddr3_ras_n(ddr3_ras_n),
.ddr3_cas_n(ddr3_cas_n),
.ddr3_we_n(ddr3_we_n),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_cke(ddr3_cke),
.ddr3_odt(ddr3_odt),
// .ddr3_cs_n(ddr3_cs_n),
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.Clk100(Clk100),
.full_fifo(full_fifo),
// .DMA_RDY(DMA_RDY),
.CS_FX3(CS_FX3),
.FLAG2_reg(FLAG2_reg)
);
*/
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:28 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_stub.v
// Design : ip_design_led_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "led_controller_v1_0,Vivado 2017.3" *)
module ip_design_led_controller_0_0(LEDs_out, s00_axi_awaddr, s00_axi_awprot,
s00_axi_awvalid, s00_axi_awready, s00_axi_wdata, s00_axi_wstrb, s00_axi_wvalid,
s00_axi_wready, s00_axi_bresp, s00_axi_bvalid, s00_axi_bready, s00_axi_araddr,
s00_axi_arprot, s00_axi_arvalid, s00_axi_arready, s00_axi_rdata, s00_axi_rresp,
s00_axi_rvalid, s00_axi_rready, s00_axi_aclk, s00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn" */;
output [7:0]LEDs_out;
input [3:0]s00_axi_awaddr;
input [2:0]s00_axi_awprot;
input s00_axi_awvalid;
output s00_axi_awready;
input [31:0]s00_axi_wdata;
input [3:0]s00_axi_wstrb;
input s00_axi_wvalid;
output s00_axi_wready;
output [1:0]s00_axi_bresp;
output s00_axi_bvalid;
input s00_axi_bready;
input [3:0]s00_axi_araddr;
input [2:0]s00_axi_arprot;
input s00_axi_arvalid;
output s00_axi_arready;
output [31:0]s00_axi_rdata;
output [1:0]s00_axi_rresp;
output s00_axi_rvalid;
input s00_axi_rready;
input s00_axi_aclk;
input s00_axi_aresetn;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altera_primitive_sync_fifo_34in_34out_8depth.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 216 11/23/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_primitive_sync_fifo_34in_34out_8depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
almost_empty,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [33:0] data;
input rdreq;
input sclr;
input wrreq;
output almost_empty;
output almost_full;
output empty;
output full;
output [33:0] q;
output [2:0] usedw;
wire [2:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [33:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [2:0] usedw = sub_wire0[2:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [33:0] q = sub_wire3[33:0];
wire almost_empty = sub_wire4;
wire almost_full = sub_wire5;
scfifo scfifo_component (
.clock (clock),
.sclr (sclr),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (sub_wire4),
.almost_full (sub_wire5));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_empty_value = 2,
scfifo_component.almost_full_value = 6,
scfifo_component.intended_device_family = "Cyclone IV GX",
scfifo_component.lpm_numwords = 8,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 34,
scfifo_component.lpm_widthu = 3,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "2"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "6"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "8"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "34"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "34"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "2"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "6"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "34"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL "almost_empty"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 34 0 INPUT NODEFVAL "data[33..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 34 0 OUTPUT NODEFVAL "q[33..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 3 0 OUTPUT NODEFVAL "usedw[2..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 34 0 data 0 0 34 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 34 0 @q 0 0 34 0
// Retrieval info: CONNECT: usedw 0 0 3 0 @usedw 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_34in_34out_8depth_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
(** We need a result similar to [f_equal], but for setoid equalities. *)
Lemma f_equiv : forall f g x y,
(N.eq==>Aeq)%signature f g -> N.eq x y -> Aeq (f x) (g y).
Proof.
auto.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0.
repeat red; intros.
apply f_equiv; auto.
apply recursion_wd; try red; auto.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt.
apply strong_rec0_wd; auto.
now rewrite Enn'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
apply f_equiv; auto with *.
rewrite recursion_succ; try (repeat red; auto with *; fail).
apply f_wd.
apply recursion_wd; try red; auto with *.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ.
apply f_wd; auto with *.
red; intros; rewrite strong_rec0_0; auto with *.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
apply f_wd; auto with *.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Implicit Arguments strong_rec [A].
End NStrongRecProp.
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_data;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (ram_data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
wire reset_sync;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire unxcomplemented_resetxx0;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (clk),
.din (reset),
.dout (reset_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
resetrequest <= 1'b0;
break_on_reset <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
break_on_reset <= jdo[19] ? 1
: jdo[18] ? 0
: break_on_reset;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset_sync)
begin
jtag_break <= break_on_reset;
resetlatch <= 1;
end
else if (debugreq & ~debugack & break_on_reset)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 24: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 26: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 26: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
itm,
trc_ctrl,
trc_on
)
;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire advanced_exc_occured;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] eic_addr;
wire [ 31: 0] exc_addr;
wire instr_retired;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_external_interrupt;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_exc_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exc_record_handler /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
wire sync_timer_reached_zero;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign advanced_exc_occured = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_external_interrupt = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign exc_addr = 32'b0;
assign eic_addr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_timer_reached_zero = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exc <= 0;
pending_exc_addr <= 0;
pending_exc_handler <= 0;
pending_exc_record_handler <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | advanced_exc_occured)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_exc <= 1;
pending_exc_addr <= exc_addr;
pending_exc_record_handler <= 0;
if (is_external_interrupt)
pending_exc_handler <= eic_addr;
else if (is_fast_tlb_miss_exception)
pending_exc_handler <= 32'h0;
else
pending_exc_handler <= 32'h80020;
pending_frametype <= 4'b0000;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~advanced_exc_occured)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
end
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else if (record_itrace & pending_exc)
begin
if (pending_exc_record_handler)
begin
itm <= {4'b0010, pending_exc_handler[31 : 1], 1'b1};
pending_exc <= 1'b0;
pending_exc_record_handler <= 1'b0;
end
else
begin
itm <= {4'b0010, pending_exc_addr[31 : 1], 1'b0};
pending_exc_record_handler <= 1'b1;
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 1'b0;
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 26: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//wasca_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
wasca_nios2_gen2_0_cpu_nios2_oci_td_mode wasca_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else
begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
)
;
output [ 1: 0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_input_tm_cnt;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
)
;
output [ 3: 0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 3: 0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt)
begin
if (ge3_free & (input_tm_cnt == 3))
fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1)
fifo_wrptr_inc = 1;
else
fifo_wrptr_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
)
;
output [ 4: 0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [ 1: 0] input_tm_cnt;
reg [ 4: 0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt)
begin
if (empty)
fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3))
fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2))
fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1)
fifo_cnt_inc = 0;
else
fifo_cnt_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dtm,
itm,
jrst_n,
reset_n,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_input_tm_cnt;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifo_cnt_inc;
wire [ 35: 0] fifo_head;
reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] fifo_read_mux;
reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifo_wrptr_inc;
wire [ 3: 0] fifo_wrptr_plus1;
wire [ 3: 0] fifo_wrptr_plus2;
wire ge2_free;
wire ge3_free;
wire input_ge1;
wire input_ge2;
wire input_ge3;
wire [ 1: 0] input_tm_cnt;
wire itm_valid;
reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] overflow_pending_atm;
wire [ 35: 0] overflow_pending_dtm;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign ge2_free = ~fifo_cnt[4];
assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
assign empty = ~|fifo_cnt;
assign fifo_wrptr_plus1 = fifo_wrptr + 1;
assign fifo_wrptr_plus2 = fifo_wrptr + 2;
wasca_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt the_wasca_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt
(
.atm_valid (atm_valid),
.compute_input_tm_cnt (compute_input_tm_cnt),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign input_tm_cnt = compute_input_tm_cnt;
wasca_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc the_wasca_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc
(
.fifo_wrptr_inc (fifo_wrptr_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
wasca_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc the_wasca_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc
(
.empty (empty),
.fifo_cnt_inc (fifo_cnt_inc),
.ge2_free (ge2_free),
.ge3_free (ge3_free),
.input_tm_cnt (input_tm_cnt)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fifo_rdptr <= 0;
fifo_wrptr <= 0;
fifo_cnt <= 0;
overflow_pending <= 1;
end
else
begin
fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
fifo_cnt <= fifo_cnt + fifo_cnt_inc;
if (~empty)
fifo_rdptr <= fifo_rdptr + 1;
if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
overflow_pending <= 1;
else if (atm_valid | dtm_valid)
overflow_pending <= 0;
end
end
assign fifo_head = fifo_read_mux;
assign tw = itm;
assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
(((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
(((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
(((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
(((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
(((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
(((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
(((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
(((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
(((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
(((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
(((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
(((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
(((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
(((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
(((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
(((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
(((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
(((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
overflow_pending_dtm;
assign input_ge1 = |input_tm_cnt;
assign input_ge2 = input_tm_cnt[1];
assign input_ge3 = &input_tm_cnt;
assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
(fifo_rdptr == 4'd1)? fifo_1 :
(fifo_rdptr == 4'd2)? fifo_2 :
(fifo_rdptr == 4'd3)? fifo_3 :
(fifo_rdptr == 4'd4)? fifo_4 :
(fifo_rdptr == 4'd5)? fifo_5 :
(fifo_rdptr == 4'd6)? fifo_6 :
(fifo_rdptr == 4'd7)? fifo_7 :
(fifo_rdptr == 4'd8)? fifo_8 :
(fifo_rdptr == 4'd9)? fifo_9 :
(fifo_rdptr == 4'd10)? fifo_10 :
(fifo_rdptr == 4'd11)? fifo_11 :
(fifo_rdptr == 4'd12)? fifo_12 :
(fifo_rdptr == 4'd13)? fifo_13 :
(fifo_rdptr == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
)
;
output [ 35: 0] tr_data;
wire [ 35: 0] tr_data;
assign tr_data = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000001;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000001);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input clock;
input [ 31: 0] data;
input reset_req;
input wren;
wire clocken;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clock),
.clocken0 (clocken),
.data_a (data),
.q_a (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_ocimem (
// inputs:
address,
byteenable,
clk,
debugaccess,
jdo,
jrst_n,
read,
reset_req,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
ociram_readdata,
waitrequest
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] ociram_readdata;
output waitrequest;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input read;
input reset_req;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 8: 0] MonARegAddrInc;
wire MonARegAddrIncAccessingRAM;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon_ram_wr;
wire [ 31: 0] cfgrom_readdata;
reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 7: 0] ociram_addr;
wire [ 3: 0] ociram_byteenable;
wire [ 31: 0] ociram_readdata;
wire [ 31: 0] ociram_wr_data;
wire ociram_wr_en;
reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
jtag_rd <= 1'b0;
jtag_rd_d1 <= 1'b0;
jtag_ram_wr <= 1'b0;
jtag_ram_rd <= 1'b0;
jtag_ram_rd_d1 <= 1'b0;
jtag_ram_access <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
jtag_rd <= 1'b1;
jtag_ram_rd <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
jtag_rd <= 1'b1;
jtag_ram_rd <= ~jdo[17];
jtag_ram_access <= ~jdo[17];
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonARegAddrInc;
MonDReg <= jdo[34 : 3];
jtag_ram_wr <= MonARegAddrIncAccessingRAM;
jtag_ram_access <= MonARegAddrIncAccessingRAM;
end
else
begin
jtag_rd <= 0;
jtag_ram_wr <= 0;
jtag_ram_rd <= 0;
jtag_ram_access <= 0;
if (jtag_rd_d1)
MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
end
jtag_rd_d1 <= jtag_rd;
jtag_ram_rd_d1 <= jtag_ram_rd;
if (~waitrequest)
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
else if (write)
waitrequest <= ~address[8] & jtag_ram_access;
else if (read)
begin
avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
waitrequest <= ~avalon_ociram_readdata_ready;
end
else
begin
waitrequest <= 1'b1;
avalon_ociram_readdata_ready <= 1'b0;
end
end
end
assign MonARegAddrInc = MonAReg[10 : 2]+1;
assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
assign avalon_ram_wr = write & ~address[8] & debugaccess;
assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
//wasca_nios2_gen2_0_cpu_ociram_sp_ram, which is an nios_sp_ram
wasca_nios2_gen2_0_cpu_ociram_sp_ram_module wasca_nios2_gen2_0_cpu_ociram_sp_ram
(
.address (ociram_addr),
.byteenable (ociram_byteenable),
.clock (clk),
.data (ociram_wr_data),
.q (ociram_readdata),
.reset_req (reset_req),
.wren (ociram_wr_en)
);
//synthesis translate_off
`ifdef NO_PLI
defparam wasca_nios2_gen2_0_cpu_ociram_sp_ram.lpm_file = "wasca_nios2_gen2_0_cpu_ociram_default_contents.dat";
`else
defparam wasca_nios2_gen2_0_cpu_ociram_sp_ram.lpm_file = "wasca_nios2_gen2_0_cpu_ociram_default_contents.hex";
`endif
//synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00080020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001b1b :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00080000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address_nxt,
av_ld_data_aligned_filtered,
byteenable_nxt,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess_nxt,
hbreak_enabled,
read_nxt,
reset,
reset_n,
reset_req,
write_nxt,
writedata_nxt,
// outputs:
debug_mem_slave_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest,
waitrequest
)
;
output debug_mem_slave_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
output waitrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 24: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 26: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess_nxt;
input hbreak_enabled;
input read_nxt;
input reset;
input reset_n;
input reset_req;
input write_nxt;
input [ 31: 0] writedata_nxt;
wire [ 31: 0] MonDReg;
reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire [ 26: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire debug_mem_slave_debugaccess_to_roms;
reg debugaccess;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire [ 31: 0] ociram_readdata;
wire ocireg_ers;
wire ocireg_mrs;
reg read;
reg [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire [ 35: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire waitrequest;
reg write;
reg [ 31: 0] writedata;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
wasca_nios2_gen2_0_cpu_nios2_oci_debug the_wasca_nios2_gen2_0_cpu_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
wasca_nios2_gen2_0_cpu_nios2_oci_break the_wasca_nios2_gen2_0_cpu_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
wasca_nios2_gen2_0_cpu_nios2_oci_xbrk the_wasca_nios2_gen2_0_cpu_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
wasca_nios2_gen2_0_cpu_nios2_oci_dbrk the_wasca_nios2_gen2_0_cpu_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
wasca_nios2_gen2_0_cpu_nios2_oci_itrace the_wasca_nios2_gen2_0_cpu_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
wasca_nios2_gen2_0_cpu_nios2_oci_dtrace the_wasca_nios2_gen2_0_cpu_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
wasca_nios2_gen2_0_cpu_nios2_oci_fifo the_wasca_nios2_gen2_0_cpu_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.trc_on (trc_on),
.tw (tw)
);
wasca_nios2_gen2_0_cpu_nios2_oci_pib the_wasca_nios2_gen2_0_cpu_nios2_oci_pib
(
.tr_data (tr_data)
);
wasca_nios2_gen2_0_cpu_nios2_oci_im the_wasca_nios2_gen2_0_cpu_nios2_oci_im
(
.clk (clk),
.jrst_n (jrst_n),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
wasca_nios2_gen2_0_cpu_nios2_avalon_reg the_wasca_nios2_gen2_0_cpu_nios2_avalon_reg
(
.address (address),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
wasca_nios2_gen2_0_cpu_nios2_ocimem the_wasca_nios2_gen2_0_cpu_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.byteenable (byteenable),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.ociram_readdata (ociram_readdata),
.read (read),
.reset_req (reset_req),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign debug_mem_slave_debugaccess_to_roms = debugack;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
address <= 0;
else
address <= address_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
byteenable <= 0;
else
byteenable <= byteenable_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
writedata <= 0;
else
writedata <= writedata_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
debugaccess <= 0;
else
debugaccess <= debugaccess_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
read <= 0;
else
read <= read ? waitrequest : read_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
write <= 0;
else
write <= write ? waitrequest : write_nxt;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
readdata <= 0;
else
readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
end
wasca_nios2_gen2_0_cpu_debug_slave_wrapper the_wasca_nios2_gen2_0_cpu_debug_slave_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_data |
trigout |
debugack;
assign debugreq = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu (
// inputs:
clk,
d_readdata,
d_waitrequest,
debug_mem_slave_address,
debug_mem_slave_byteenable,
debug_mem_slave_debugaccess,
debug_mem_slave_read,
debug_mem_slave_write,
debug_mem_slave_writedata,
i_readdata,
i_waitrequest,
irq,
reset_n,
reset_req,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
debug_mem_slave_debugaccess_to_roms,
debug_mem_slave_readdata,
debug_mem_slave_waitrequest,
debug_reset_request,
dummy_ci_port,
i_address,
i_read
)
;
output [ 26: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output debug_mem_slave_debugaccess_to_roms;
output [ 31: 0] debug_mem_slave_readdata;
output debug_mem_slave_waitrequest;
output debug_reset_request;
output dummy_ci_port;
output [ 26: 0] i_address;
output i_read;
input clk;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 8: 0] debug_mem_slave_address;
input [ 3: 0] debug_mem_slave_byteenable;
input debug_mem_slave_debugaccess;
input debug_mem_slave_read;
input debug_mem_slave_write;
input [ 31: 0] debug_mem_slave_writedata;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 31: 0] irq;
input reset_n;
input reset_req;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_and;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_intr_inst;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_ex;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_ld_st_ex;
wire D_ctrl_logic;
wire D_ctrl_mem16;
wire D_ctrl_mem32;
wire D_ctrl_mem8;
wire D_ctrl_rd_ctl_reg;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_set_src2_rem_imm;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_signed_imm12;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_src_imm5_shift_rot;
wire D_ctrl_st;
wire D_ctrl_st_ex;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
wire D_is_opx_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 4: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 24: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 71: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 26: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
wire E_rf_ecc_recoverable_valid;
wire E_rf_ecc_unrecoverable_valid;
wire E_rf_ecc_valid_any;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire [ 4: 0] E_shift_rot_shfcnt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
wire E_valid;
reg E_valid_from_R;
wire [ 71: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 4: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire F_is_opx_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 4: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_op_rsv02;
wire F_op_op_rsv09;
wire F_op_op_rsv10;
wire F_op_op_rsv17;
wire F_op_op_rsv18;
wire F_op_op_rsv25;
wire F_op_op_rsv26;
wire F_op_op_rsv33;
wire F_op_op_rsv34;
wire F_op_op_rsv41;
wire F_op_op_rsv42;
wire F_op_op_rsv49;
wire F_op_op_rsv57;
wire F_op_op_rsv61;
wire F_op_op_rsv62;
wire F_op_op_rsv63;
wire F_op_opx_rsv00;
wire F_op_opx_rsv10;
wire F_op_opx_rsv15;
wire F_op_opx_rsv17;
wire F_op_opx_rsv21;
wire F_op_opx_rsv25;
wire F_op_opx_rsv33;
wire F_op_opx_rsv34;
wire F_op_opx_rsv35;
wire F_op_opx_rsv42;
wire F_op_opx_rsv43;
wire F_op_opx_rsv44;
wire F_op_opx_rsv47;
wire F_op_opx_rsv50;
wire F_op_opx_rsv51;
wire F_op_opx_rsv55;
wire F_op_opx_rsv56;
wire F_op_opx_rsv60;
wire F_op_opx_rsv63;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 24: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 24: 0] F_pc_no_crst_nxt;
wire [ 24: 0] F_pc_nxt;
wire [ 24: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 26: 0] F_pcb;
wire [ 26: 0] F_pcb_nxt;
wire [ 26: 0] F_pcb_plus_four;
wire F_valid;
wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_and;
wire R_ctrl_alu_force_and_nxt;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_intr_inst;
wire R_ctrl_intr_inst_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_ex;
wire R_ctrl_ld_ex_nxt;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_ld_st_ex;
wire R_ctrl_ld_st_ex_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_mem16;
wire R_ctrl_mem16_nxt;
reg R_ctrl_mem32;
wire R_ctrl_mem32_nxt;
reg R_ctrl_mem8;
wire R_ctrl_mem8_nxt;
reg R_ctrl_rd_ctl_reg;
wire R_ctrl_rd_ctl_reg_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_set_src2_rem_imm;
wire R_ctrl_set_src2_rem_imm_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_signed_imm12;
wire R_ctrl_signed_imm12_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_src_imm5_shift_rot;
wire R_ctrl_src_imm5_shift_rot_nxt;
reg R_ctrl_st;
reg R_ctrl_st_ex;
wire R_ctrl_st_ex_nxt;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_a_q;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_rf_b_q;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
wire [ 31: 0] R_stw_data;
reg R_valid;
wire [ 71: 0] R_vinst;
reg R_wr_dst_reg;
reg W1_rf_ecc_recoverable_valid;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg [ 31: 0] W_cdsr_reg;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
wire [ 31: 0] W_cpuid_reg;
wire [ 4: 0] W_dst_regnum;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 26: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_up_ex_mon_state;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 71: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 26: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
reg d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
wire debug_mem_slave_clk;
wire debug_mem_slave_debugaccess_to_roms;
wire [ 31: 0] debug_mem_slave_readdata;
wire debug_mem_slave_reset;
wire debug_mem_slave_waitrequest;
wire debug_reset_request;
wire dummy_ci_port;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 26: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_wasca_nios2_gen2_0_cpu_test_bench, which is an e_instance
wasca_nios2_gen2_0_cpu_test_bench the_wasca_nios2_gen2_0_cpu_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[10 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[10 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[10 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_op_rsv02 = F_iw_op == 2;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_op_rsv09 = F_iw_op == 9;
assign F_op_op_rsv10 = F_iw_op == 10;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_op_rsv17 = F_iw_op == 17;
assign F_op_op_rsv18 = F_iw_op == 18;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_op_rsv25 = F_iw_op == 25;
assign F_op_op_rsv26 = F_iw_op == 26;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_op_rsv33 = F_iw_op == 33;
assign F_op_op_rsv34 = F_iw_op == 34;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_op_rsv41 = F_iw_op == 41;
assign F_op_op_rsv42 = F_iw_op == 42;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_op_rsv49 = F_iw_op == 49;
assign F_op_custom = F_iw_op == 50;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_op_rsv57 = F_iw_op == 57;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_op_rsv61 = F_iw_op == 61;
assign F_op_op_rsv62 = F_iw_op == 62;
assign F_op_op_rsv63 = F_iw_op == 63;
assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
assign F_is_opx_inst = F_iw_op == 58;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign dummy_ci_port = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = irq[31 : 0] & 32'b00000000000000000000000000000001;
assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 131080 :
(F_pc_sel_nxt == 2'b01)? 66568 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[26 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid | W_rf_ecc_unrecoverable_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 131072;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | W_rf_ecc_unrecoverable_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid | W1_rf_ecc_recoverable_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 :
D_ctrl_alu_force_and ? 2'b01 :
D_logic_op_raw;
assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign E_rf_ecc_valid_any = E_rf_ecc_recoverable_valid|E_rf_ecc_unrecoverable_valid;
assign W_rf_ecc_valid_any = W_rf_ecc_recoverable_valid|W_rf_ecc_unrecoverable_valid;
assign E_rf_ecc_recoverable_valid = 1'b0;
assign E_rf_ecc_unrecoverable_valid = 1'b0;
assign W_dst_regnum = R_dst_regnum;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_recoverable_valid <= 0;
else
W_rf_ecc_recoverable_valid <= E_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W1_rf_ecc_recoverable_valid <= 0;
else
W1_rf_ecc_recoverable_valid <= W_rf_ecc_recoverable_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_rf_ecc_unrecoverable_valid <= 0;
else
W_rf_ecc_unrecoverable_valid <= E_rf_ecc_unrecoverable_valid & ~E_rf_ecc_recoverable_valid;
end
assign R_rf_a = R_rf_a_q;
assign R_rf_b = R_rf_b_q;
assign W_rf_wren = (R_wr_dst_reg & W_valid) | W_rf_ecc_valid_any | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//wasca_nios2_gen2_0_cpu_register_bank_a, which is an nios_sdp_ram
wasca_nios2_gen2_0_cpu_register_bank_a_module wasca_nios2_gen2_0_cpu_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a_q),
.rdaddress (D_iw_a),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam wasca_nios2_gen2_0_cpu_register_bank_a.lpm_file = "wasca_nios2_gen2_0_cpu_rf_ram_a.dat";
`else
defparam wasca_nios2_gen2_0_cpu_register_bank_a.lpm_file = "wasca_nios2_gen2_0_cpu_rf_ram_a.hex";
`endif
//synthesis translate_on
//wasca_nios2_gen2_0_cpu_register_bank_b, which is an nios_sdp_ram
wasca_nios2_gen2_0_cpu_register_bank_b_module wasca_nios2_gen2_0_cpu_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b_q),
.rdaddress (D_iw_b),
.wraddress (W_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam wasca_nios2_gen2_0_cpu_register_bank_b.lpm_file = "wasca_nios2_gen2_0_cpu_rf_ram_b.dat";
`else
defparam wasca_nios2_gen2_0_cpu_register_bank_b.lpm_file = "wasca_nios2_gen2_0_cpu_rf_ram_b.hex";
`endif
//synthesis translate_on
assign R_src1 = (((R_ctrl_br & E_valid_from_R) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid_from_R))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_src_imm5_shift_rot)? {{11 {1'b0}},D_iw_imm5} :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid_from_R <= 0;
else
E_valid_from_R <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_valid = E_valid_from_R & ~E_rf_ecc_valid_any;
assign E_stall = (E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall) & ~(E_rf_ecc_valid_any|W_rf_ecc_valid_any|W1_rf_ecc_recoverable_valid);
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[26 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_shfcnt = E_src2[4 : 0];
assign E_shift_rot_cnt_nxt = E_new_inst ? E_shift_rot_shfcnt : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 5'd0)? W_status_reg :
(D_iw_control_regnum == 5'd1)? W_estatus_reg :
(D_iw_control_regnum == 5'd2)? W_bstatus_reg :
(D_iw_control_regnum == 5'd3)? W_ienable_reg :
(D_iw_control_regnum == 5'd4)? W_ipending_reg :
(D_iw_control_regnum == 5'd5)? W_cpuid_reg :
W_cdsr_reg;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rd_ctl_reg))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_sth_data = R_rf_b[15 : 0];
assign R_stw_data = R_rf_b[31 : 0];
assign R_stb_data = R_rf_b[7 : 0];
assign E_st_data = (D_ctrl_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_ctrl_mem16)? {R_sth_data, R_sth_data} :
R_stw_data;
assign E_mem_byte_en = ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst & ~E_rf_ecc_valid_any) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = ((R_ctrl_st & (~R_ctrl_st_ex | W_up_ex_mon_state)) & E_new_inst & ~E_rf_ecc_valid_any) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_ctrl_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_ctrl_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_ctrl_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_ctrl_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_ctrl_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_up_ex_mon_state <= 0;
else if (R_en)
W_up_ex_mon_state <= (R_ctrl_ld_ex & W_valid) ? 1'b1 :
((D_op_eret & W_valid) | (R_ctrl_st_ex & W_valid)) ? 1'b0 :
W_up_ex_mon_state;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= D_ctrl_intr_inst ? W_status_reg : E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cdsr_reg <= 0;
else
W_cdsr_reg <= 0;
end
assign W_cpuid_reg = 0;
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rd_ctl_reg ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[26 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst | W_rf_ecc_unrecoverable_valid) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception|W_rf_ecc_unrecoverable_valid) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000001;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000001;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_write <= 0;
else
d_write <= d_write_nxt;
end
wasca_nios2_gen2_0_cpu_nios2_oci the_wasca_nios2_gen2_0_cpu_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address_nxt (debug_mem_slave_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.byteenable_nxt (debug_mem_slave_byteenable),
.clk (debug_mem_slave_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
.debugaccess_nxt (debug_mem_slave_debugaccess),
.hbreak_enabled (hbreak_enabled),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.read_nxt (debug_mem_slave_read),
.readdata (debug_mem_slave_readdata),
.reset (debug_mem_slave_reset),
.reset_n (reset_n),
.reset_req (reset_req),
.resetrequest (debug_reset_request),
.waitrequest (debug_mem_slave_waitrequest),
.write_nxt (debug_mem_slave_write),
.writedata_nxt (debug_mem_slave_writedata)
);
//debug_mem_slave, which is an e_avalon_slave
assign debug_mem_slave_clk = clk;
assign debug_mem_slave_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv44|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv02|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = 1'b0;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_rd_ctl_reg = D_op_rdctl;
assign R_ctrl_rd_ctl_reg_nxt = D_ctrl_rd_ctl_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rd_ctl_reg <= 0;
else if (R_en)
R_ctrl_rd_ctl_reg <= R_ctrl_rd_ctl_reg_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|D_op_jmpi|D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_ror;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|D_op_srl|D_op_srai|D_op_sra|D_op_ror;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_sll|
D_op_roli|
D_op_rol|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_ror;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_set_src2_rem_imm = 1'b0;
assign R_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_set_src2_rem_imm <= 0;
else if (R_en)
R_ctrl_set_src2_rem_imm <= R_ctrl_set_src2_rem_imm_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_signed_imm12 = 1'b0;
assign R_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_signed_imm12 <= 0;
else if (R_en)
R_ctrl_signed_imm12 <= R_ctrl_signed_imm12_nxt;
end
assign D_ctrl_src_imm5_shift_rot = D_op_roli|D_op_slli|D_op_srli|D_op_srai;
assign R_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src_imm5_shift_rot <= 0;
else if (R_en)
R_ctrl_src_imm5_shift_rot <= R_ctrl_src_imm5_shift_rot_nxt;
end
assign D_ctrl_br_uncond = D_op_br;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|D_op_bge|D_op_blt|D_op_bne|D_op_beq|D_op_bgeu|D_op_bltu;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_bgeu;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_ex = 1'b0;
assign R_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_ex <= 0;
else if (R_en)
R_ctrl_ld_ex <= R_ctrl_ld_ex_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st_ex = 1'b0;
assign R_ctrl_st_ex_nxt = D_ctrl_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st_ex <= 0;
else if (R_en)
R_ctrl_st_ex <= R_ctrl_st_ex_nxt;
end
assign D_ctrl_st = D_op_stb|D_op_sth|D_op_stw|D_op_stbio|D_op_sthio|D_op_stwio;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_st_ex = 1'b0;
assign R_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_st_ex <= 0;
else if (R_en)
R_ctrl_ld_st_ex <= R_ctrl_ld_st_ex_nxt;
end
assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
assign R_ctrl_mem8_nxt = D_ctrl_mem8;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem8 <= 0;
else if (R_en)
R_ctrl_mem8 <= R_ctrl_mem8_nxt;
end
assign D_ctrl_mem16 = D_op_ldhu|D_op_ldh|D_op_ldhio|D_op_ldhuio|D_op_sth|D_op_sthio;
assign R_ctrl_mem16_nxt = D_ctrl_mem16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem16 <= 0;
else if (R_en)
R_ctrl_mem16 <= R_ctrl_mem16_nxt;
end
assign D_ctrl_mem32 = D_op_ldw|D_op_ldwio|D_op_stw|D_op_stwio;
assign R_ctrl_mem32_nxt = D_ctrl_mem32;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_mem32 <= 0;
else if (R_en)
R_ctrl_mem32 <= R_ctrl_mem32_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_jmpi;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_ldb|
D_op_ldh|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_roli|
D_op_slli|
D_op_srli|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_intr_inst = 1'b0;
assign R_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_intr_inst <= 0;
else if (R_en)
R_ctrl_intr_inst <= R_ctrl_intr_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_opx_rsv44|
D_op_crst|
D_op_ldl|
D_op_op_rsv09|
D_op_op_rsv10|
D_op_op_rsv17|
D_op_op_rsv18|
D_op_op_rsv25|
D_op_op_rsv26|
D_op_op_rsv33|
D_op_op_rsv34|
D_op_op_rsv41|
D_op_op_rsv42|
D_op_op_rsv49|
D_op_op_rsv57|
D_op_op_rsv61|
D_op_op_rsv62|
D_op_op_rsv63|
D_op_opx_rsv00|
D_op_opx_rsv10|
D_op_opx_rsv15|
D_op_opx_rsv17|
D_op_opx_rsv21|
D_op_opx_rsv25|
D_op_opx_rsv33|
D_op_opx_rsv34|
D_op_opx_rsv35|
D_op_opx_rsv42|
D_op_opx_rsv43|
D_op_opx_rsv47|
D_op_opx_rsv50|
D_op_opx_rsv51|
D_op_opx_rsv55|
D_op_opx_rsv56|
D_op_opx_rsv60|
D_op_opx_rsv63|
D_op_rdprs|
D_op_stc|
D_op_wrprs|
D_op_intr|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_ret|
D_op_jmp|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_bgeu|
D_op_beq|
D_op_bne|
D_op_br;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
assign D_ctrl_alu_force_and = 1'b0;
assign R_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_and <= 0;
else if (R_en)
R_ctrl_alu_force_and <= R_ctrl_alu_force_and_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_custom)? 56'h20637573746f6d :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_custom)? 56'h20637573746f6d :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
assign R_vinst = R_valid ? D_inst : {9{8'h2d}};
assign E_vinst = E_valid ? D_inst : {9{8'h2d}};
assign W_vinst = W_valid ? D_inst : {9{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
/*
*******************************************************************************
* File Name : ada_exu_div.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 1st, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : The multicycle Divider unit.
* op_div and op_divu MUST BE disasserted after the setup
* cycle for normal operation, or the operation will be
* restarted
*******************************************************************************
*/
module ada_exu_div(
input clk, // clock
input rst, // reset
input op_divs, // 1 for signed operation
input op_divu, // 1 for unsigned operation
input [31:0] dividend, //
input [31:0] divisor, //
output [31:0] quotient, //
output [31:0] remainder, //
output stall // 1 while calculating
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result will be negative
reg [4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; //
//--------------------------------------------------------------------------
// assigments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = residual;
assign stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate the current digit
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calcule the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
active <= 1'b0;
neg_result <= 1'b0;
cycle <= 5'b0;
result <= 32'b0;
denominator <= 32'b0;
residual <= 32'b0;
end
else begin
if(op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
active <= 1'b1;
end
else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
active <= 1'b1;
end
else if (active) begin
// run a iteration
if(partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 15:19:41 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_stub.v
// Design : led_controller_design_rst_ps7_0_100M_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
module debounceSM(
//Inputs
signal_in, rst_n, clk,
//Outputs
signal_out
);
//Inputs
input wire signal_in, rst_n, clk;
//Outputs
output reg signal_out;
localparam target_count = 4'h4;
localparam state_low = 2'b00;
localparam state_posedge = 2'b01;
localparam state_negedge = 2'b10;
localparam state_high = 2'b11;
reg [1:0] current_state, next_state;
reg [3:0] count;
wire [3:0] next_count;
reg reset_count;
always@(posedge clk, negedge rst_n)begin
if(~rst_n)begin
current_state <= 2'b00;
count <= 4'b0000;
end
else begin
current_state <= next_state;
count <= next_count;
end
end
assign next_count = (reset_count) ? 4'b0000 : count + 4'b0001;
always@(current_state, signal_in, count)begin
next_state = state_low;
signal_out = 1'b0;
reset_count = 1'b1;
case(current_state)
state_low : begin
signal_out = 1'b0;
if(signal_in)begin
reset_count = 1'b0;
next_state = state_posedge;
end
else begin
reset_count = 1'b1;
next_state = state_low;
end
end
state_posedge : begin
signal_out = 1'b0;
if(signal_in)begin
reset_count = 1'b0;
end
else begin
reset_count = 1'b1;
end
if(count == target_count && signal_in)begin
next_state = state_high;
end
else if(signal_in)begin
next_state = state_posedge;
end
else begin
next_state = state_low;
end
end
state_high : begin
signal_out = 1'b1;
if(~signal_in)begin
reset_count = 1'b0;
next_state = state_negedge;
end
else begin
reset_count = 1'b1;
next_state = state_high;
end
end
state_negedge : begin
signal_out = 1'b1;
if(~signal_in)begin
reset_count = 1'b0;
end
else begin
reset_count = 1'b1;
end
if(count == target_count && ~signal_in)begin
next_state = state_low;
end
else if(~signal_in)begin
next_state = state_negedge;
end
else begin
next_state = state_high;
end
end
default : begin
next_state = state_low;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311AI_TB_V
`define SKY130_FD_SC_LS__O311AI_TB_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o311ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_SYMBOL_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_64x256.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_64x256 (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [7:0] byteena_a;
input clock;
input [63:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (clock),
.byteena_a (byteena_a),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({64{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 64,
altsyncram_component.width_b = 64,
altsyncram_component.width_byteena_a = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "8"
// Retrieval info: USED_PORT: byteena_a 0 0 8 0 INPUT VCC byteena_a[7..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL rdaddress[7..0]
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL wraddress[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @byteena_a 0 0 8 0 byteena_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Weak Keeper
// /___/ /\ Filename : KEEPER.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module KEEPER (O);
inout O;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
reg in;
always @(O)
if (O)
in <= 1;
else
in <= 0;
buf (pull1, pull0) B1 (O, in);
endmodule
`endcelldefine
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 10:10:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
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